1421 files changed, 24292 insertions, 104496 deletions

diff --git a/.travis.yml b/.travis.yml
index 8333fae..591915d 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -40,7 +40,7 @@ install:
  - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
  # prepare buildman environment
  - echo -e "[toolchain]\nroot = /usr" > ~/.buildman
- - echo -e "\n[toolchain-alias]\nblackfin = bfin\nsh = sh4\nopenrisc = or32" >> ~/.buildman
+ - echo -e "\n[toolchain-alias]\nsh = sh4\nopenrisc = or32" >> ~/.buildman
  - cat ~/.buildman
  - virtualenv /tmp/venv
  - . /tmp/venv/bin/activate
@@ -60,7 +60,6 @@ env:
 before_script:
   # install toolchains based on TOOLCHAIN} variable
   - if [[ "${TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman --fetch-arch avr32 ; fi
-  - if [[ "${TOOLCHAIN}" == *bfin* ]]; then ./tools/buildman/buildman --fetch-arch bfin ; fi
   - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi
   - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
   - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi
@@ -135,10 +134,13 @@ matrix:
           BUILDMAN="freescale -x powerpc,m68k,aarch64"
     - env:
         - JOB="Freescale AArch64"
-          BUILDMAN="freescale -x powerpc,m68k,armv7,arm9,arm11"
+          BUILDMAN="freescale&aarch64"
     - env:
-        - JOB="i.MX (non-Freescale)"
-          BUILDMAN="mx -x freescale"
+        - JOB="i.MX6 (non-Freescale)"
+          BUILDMAN="mx6 -x freescale"
+    - env:
+        - JOB="i.MX (non-Freescale, non-i.MX6)"
+          BUILDMAN="mx -x freescale,mx6"
     - env:
         - BUILDMAN="samsung"
     - env:
@@ -150,7 +152,7 @@ matrix:
     - env:
         - BUILDMAN="sun7i"
     - env:
-        - BUILDMAN="sun8i"
+        - BUILDMAN="sun8i -x orangepi_pc2"
     - env:
         - BUILDMAN="sun9i"
     - env:
diff --git a/Kconfig b/Kconfig
index e0744d1..1cf990d 100644
--- a/Kconfig
+++ b/Kconfig
@@ -284,9 +284,9 @@ config SYS_EXTRA_OPTIONS
 	  new boards should not use this option.
 
 config SYS_TEXT_BASE
-	depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
+	depends on ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
 		(M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS || \
-		ARCH_ZYNQ
+		ARCH_ZYNQ || ARCH_KEYSTONE
 	depends on !EFI_APP
 	hex "Text Base"
 	help
diff --git a/MAINTAINERS b/MAINTAINERS
index c60cd2a..eadb21f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -173,9 +173,12 @@ F:	arch/arm/include/asm/arch-sti*/
 ARM SUNXI
 M:	Jagan Teki <jagan@openedev.com>
 M:	Maxime Ripard <maxime.ripard@free-electrons.com>
+S:	Maintained
 T:	git git://git.denx.de/u-boot-sunxi.git
 F:	arch/arm/cpu/armv7/sunxi/
 F:	arch/arm/include/asm/arch-sunxi/
+F:	arch/arm/mach-sunxi/
+F:	board/sunxi/
 
 ARM TEGRA
 M:	Tom Warren <twarren@nvidia.com>
@@ -221,12 +224,6 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-avr32.git
 F:	arch/avr32/
 
-BLACKFIN
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-T:	git git://git.denx.de/u-boot-blackfin.git
-F:	arch/blackfin/
-
 BUILDMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
@@ -313,11 +310,6 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-mmc.git
 F:	drivers/mmc/
 
-OPENRISC
-M:	Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
-S:	Maintained
-F:	arch/openrisc/
-
 PATMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
@@ -419,12 +411,6 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-sh.git
 F:	arch/sh/
 
-SPARC
-#M:	Francois Retief <fgretief@spaceteq.co.za>
-S:	Orphaned (Since 2016-02)
-T:	git git://git.denx.de/u-boot-sparc.git
-F:	arch/sparc/
-
 SPI
 M:	Jagan Teki <jagan@openedev.com>
 S:	Maintained
diff --git a/Makefile b/Makefile
index 1001bc5..09b597d 100644
--- a/Makefile
+++ b/Makefile
@@ -3,9 +3,9 @@
 #
 
 VERSION = 2017
-PATCHLEVEL = 03
+PATCHLEVEL = 05
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 NAME =
 
 # *DOCUMENTATION*
@@ -805,6 +805,10 @@ ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
 endif
 
 LDFLAGS_u-boot += $(LDFLAGS_FINAL)
+
+# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
+LDFLAGS_u-boot += $(call ld-option, --no-dynamic-linker)
+
 ifneq ($(CONFIG_SYS_TEXT_BASE),)
 LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
 endif
@@ -1345,13 +1349,17 @@ spl/u-boot-spl: tools prepare \
 spl/sunxi-spl.bin: spl/u-boot-spl
 	@:
 
+spl/sunxi-spl-with-ecc.bin: spl/sunxi-spl.bin
+	@:
+
 spl/u-boot-spl.sfp: spl/u-boot-spl
 	@:
 
 spl/boot.bin: spl/u-boot-spl
 	@:
 
-tpl/u-boot-tpl.bin: tools prepare
+tpl/u-boot-tpl.bin: tools prepare \
+		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb)
 	$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all
 
 TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include)
diff --git a/README b/README
index aa907ce..f7ab78a 100644
--- a/README
+++ b/README
@@ -137,7 +137,6 @@ Directory Hierarchy:
   /arc			Files generic to ARC architecture
   /arm			Files generic to ARM architecture
   /avr32		Files generic to AVR32 architecture
-  /blackfin		Files generic to Analog Devices Blackfin architecture
   /m68k			Files generic to m68k architecture
   /microblaze		Files generic to microblaze architecture
   /mips			Files generic to MIPS architecture
@@ -147,7 +146,6 @@ Directory Hierarchy:
   /powerpc		Files generic to PowerPC architecture
   /sandbox		Files generic to HW-independent "sandbox"
   /sh			Files generic to SH architecture
-  /sparc		Files generic to SPARC architecture
   /x86			Files generic to x86 architecture
 /api			Machine/arch independent API for external apps
 /board			Board dependent files
@@ -2869,8 +2867,6 @@ The following options need to be configured:
 
 		CONFIG_AT91SAM9XE
 		enable special bootcounter support on at91sam9xe based boards.
-		CONFIG_BLACKFIN
-		enable special bootcounter support on blackfin based boards.
 		CONFIG_SOC_DA8XX
 		enable special bootcounter support on da850 based boards.
 		CONFIG_BOOTCOUNT_RAM
@@ -5911,11 +5907,6 @@ For PowerPC, the following registers have specific use:
     average for all boards 752 bytes for the whole U-Boot image,
     624 text + 127 data).
 
-On Blackfin, the normal C ABI (except for P3) is followed as documented here:
-	http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
-
-    ==> U-Boot will use P3 to hold a pointer to the global data
-
 On ARM, the following registers are used:
 
 	R0:	function argument word/integer result
diff --git a/api/api_storage.c b/api/api_storage.c
index e80818d..a5357bc 100644
--- a/api/api_storage.c
+++ b/api/api_storage.c
@@ -331,10 +331,14 @@ lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start
 	if (!dev_stor_is_valid(type, dd))
 		return 0;
 
+#ifdef CONFIG_BLK
+	return blk_dread(dd, start, len, buf);
+#else
 	if ((dd->block_read) == NULL) {
 		debugf("no block_read() for device 0x%08x\n", cookie);
 		return 0;
 	}
 
 	return dd->block_read(dd, start, len, buf);
+#endif	/* defined(CONFIG_BLK) */
 }
diff --git a/arch/Kconfig b/arch/Kconfig
index 76c690f..160accd 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -13,6 +13,9 @@ config ARC
 	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
 	select ARCH_EARLY_INIT_R
+	select CLK
+	select TIMER
+	select ARC_TIMER
 
 config ARM
 	bool "ARM architecture"
@@ -24,10 +27,6 @@ config AVR32
 	bool "AVR32 architecture"
 	select CREATE_ARCH_SYMLINK
 
-config BLACKFIN
-	bool "Blackfin architecture"
-	select ARCH_MISC_INIT
-
 config M68K
 	bool "M68000 architecture"
 	select HAVE_PRIVATE_LIBGCC
@@ -52,9 +51,6 @@ config NIOS2
 	select DM
 	select CPU
 
-config OPENRISC
-	bool "OpenRISC architecture"
-
 config PPC
 	bool "PowerPC architecture"
 	select HAVE_PRIVATE_LIBGCC
@@ -77,10 +73,6 @@ config SH
 	bool "SuperH architecture"
 	select HAVE_PRIVATE_LIBGCC
 
-config SPARC
-	bool "SPARC architecture"
-	select CREATE_ARCH_SYMLINK
-
 config X86
 	bool "x86 architecture"
 	select CREATE_ARCH_SYMLINK
@@ -159,16 +151,13 @@ config SYS_CONFIG_NAME
 source "arch/arc/Kconfig"
 source "arch/arm/Kconfig"
 source "arch/avr32/Kconfig"
-source "arch/blackfin/Kconfig"
 source "arch/m68k/Kconfig"
 source "arch/microblaze/Kconfig"
 source "arch/mips/Kconfig"
 source "arch/nds32/Kconfig"
 source "arch/nios2/Kconfig"
-source "arch/openrisc/Kconfig"
 source "arch/powerpc/Kconfig"
 source "arch/sandbox/Kconfig"
 source "arch/sh/Kconfig"
-source "arch/sparc/Kconfig"
 source "arch/x86/Kconfig"
 source "arch/xtensa/Kconfig"
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 4c5696b..6e4b1d0 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -118,7 +118,7 @@ config SYS_DCACHE_OFF
 
 choice
 	prompt "Target select"
-	default TARGET_AXS10X
+	default TARGET_AXS103
 
 config TARGET_TB100
 	bool "Support tb100"
@@ -126,8 +126,11 @@ config TARGET_TB100
 config TARGET_NSIM
 	bool "Support standalone nSIM & Free nSIM"
 
-config TARGET_AXS10X
-	bool "Support Synopsys Designware SDP board (AXS101 & AXS103)"
+config TARGET_AXS101
+	bool "Support Synopsys Designware SDP board AXS101"
+
+config TARGET_AXS103
+	bool "Support Synopsys Designware SDP board AXS103"
 
 endchoice
 
diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile
index 1d94c08..218a647 100644
--- a/arch/arc/dts/Makefile
+++ b/arch/arc/dts/Makefile
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-dtb-$(CONFIG_TARGET_AXS10X) +=  axs10x.dtb
+dtb-$(CONFIG_TARGET_AXS101) +=  axs101.dtb
+dtb-$(CONFIG_TARGET_AXS103) +=  axs103.dtb
 dtb-$(CONFIG_TARGET_NSIM) +=  nsim.dtb
 dtb-$(CONFIG_TARGET_TB100) +=  abilis_tb100.dtb
 
diff --git a/arch/arc/dts/abilis_tb100.dts b/arch/arc/dts/abilis_tb100.dts
index cf395c4..23329ec 100644
--- a/arch/arc/dts/abilis_tb100.dts
+++ b/arch/arc/dts/abilis_tb100.dts
@@ -8,13 +8,19 @@
 #include "skeleton.dtsi"
 
 / {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
 	aliases {
 		console = &uart0;
 	};
 
+	cpu_card {
+		core_clk: core_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <500000000>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
 	uart0: serial@ff100000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0xff100000 0x1000>;
diff --git a/arch/arc/dts/axc001.dtsi b/arch/arc/dts/axc001.dtsi
new file mode 100644
index 0000000..1cf630d
--- /dev/null
+++ b/arch/arc/dts/axc001.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	cpu_card {
+		core_clk: core_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <750000000>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
+
diff --git a/arch/arc/dts/axc003.dtsi b/arch/arc/dts/axc003.dtsi
new file mode 100644
index 0000000..5e9270a
--- /dev/null
+++ b/arch/arc/dts/axc003.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	cpu_card {
+		core_clk: core_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
+
diff --git a/arch/arc/dts/axs101.dts b/arch/arc/dts/axs101.dts
new file mode 100644
index 0000000..ec7b8b7
--- /dev/null
+++ b/arch/arc/dts/axs101.dts
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+
+/include/ "axc001.dtsi"
+/include/ "axs10x_mb.dtsi"
+
+
+/ {
+	chosen {
+		stdout-path = &uart0;
+	};
+};
+
diff --git a/arch/arc/dts/axs103.dts b/arch/arc/dts/axs103.dts
new file mode 100644
index 0000000..8f7a76f
--- /dev/null
+++ b/arch/arc/dts/axs103.dts
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+
+/include/ "axc003.dtsi"
+/include/ "axs10x_mb.dtsi"
+
+
+/ {
+	chosen {
+		stdout-path = &uart0;
+	};
+};
+
diff --git a/arch/arc/dts/axs10x.dts b/arch/arc/dts/axs10x.dts
deleted file mode 100644
index 391d067..0000000
--- a/arch/arc/dts/axs10x.dts
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (C) 2015 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/dts-v1/;
-
-#include "skeleton.dtsi"
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	aliases {
-		console = &uart0;
-	};
-
-	clocks {
-		apbclk: apbclk {
-			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
-			#clock-cells = <0>;
-		};
-	};
-
-	uart0: serial0@e0022000 {
-		compatible = "snps,dw-apb-uart";
-		reg = <0xe0022000 0x1000>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-	};
-
-	ethernet@e0018000 {
-		#interrupt-cells = <1>;
-		compatible = "altr,socfpga-stmmac";
-		reg = < 0xe0018000 0x2000 >;
-		interrupts = < 25 >;
-		interrupt-names = "macirq";
-		phy-mode = "gmii";
-		snps,pbl = < 32 >;
-		clocks = <&apbclk>;
-		clock-names = "stmmaceth";
-		max-speed = <100>;
-	};
-
-	ehci@0xe0040000 {
-		compatible = "generic-ehci";
-		reg = < 0xe0040000 0x100 >;
-		interrupts = < 8 >;
-	};
-
-	ohci@0xe0060000 {
-		compatible = "generic-ohci";
-		reg = < 0xe0060000 0x100 >;
-		interrupts = < 8 >;
-	};
-};
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
new file mode 100644
index 0000000..b74d3c8
--- /dev/null
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/ {
+	axs10x_mb@e0000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00000000 0xe0000000 0x10000000>;
+		u-boot,dm-pre-reloc;
+
+		clocks {
+			compatible = "simple-bus";
+			u-boot,dm-pre-reloc;
+
+			apbclk: apbclk {
+				compatible = "fixed-clock";
+				clock-frequency = <50000000>;
+				#clock-cells = <0>;
+			};
+
+			uartclk: uartclk {
+				compatible = "fixed-clock";
+				clock-frequency = <33333333>;
+				#clock-cells = <0>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		ethernet@18000 {
+			#interrupt-cells = <1>;
+			compatible = "altr,socfpga-stmmac";
+			reg = < 0x18000 0x2000 >;
+			interrupts = < 25 >;
+			interrupt-names = "macirq";
+			phy-mode = "gmii";
+			snps,pbl = < 32 >;
+			clocks = <&apbclk>;
+			clock-names = "stmmaceth";
+			max-speed = <100>;
+		};
+
+		ehci@0x40000 {
+			compatible = "generic-ehci";
+			reg = < 0x40000 0x100 >;
+			interrupts = < 8 >;
+		};
+
+		ohci@0x60000 {
+			compatible = "generic-ohci";
+			reg = < 0x60000 0x100 >;
+			interrupts = < 8 >;
+		};
+
+		uart0: serial0@22000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x22000 0x100>;
+			clocks = <&uartclk>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+		};
+	};
+};
diff --git a/arch/arc/dts/nsim.dts b/arch/arc/dts/nsim.dts
index 69e16c2..491c46d 100644
--- a/arch/arc/dts/nsim.dts
+++ b/arch/arc/dts/nsim.dts
@@ -8,17 +8,23 @@
 #include "skeleton.dtsi"
 
 / {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
 	aliases {
 		console = &arcuart0;
 	};
 
+	cpu_card {
+		core_clk: core_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <70000000>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
 	arcuart0: serial@0xc0fc1000 {
 		compatible = "snps,arc-uart";
 		reg = <0xc0fc1000 0x100>;
-		clock-frequency = <80000000>;
+		clock-frequency = <70000000>;
 	};
 
 };
diff --git a/arch/arc/dts/skeleton.dtsi b/arch/arc/dts/skeleton.dtsi
index b41d241..279fc6c 100644
--- a/arch/arc/dts/skeleton.dtsi
+++ b/arch/arc/dts/skeleton.dtsi
@@ -9,5 +9,22 @@
 	#size-cells = <1>;
 	chosen { };
 	aliases { };
-	memory { device_type = "memory"; reg = <0 0>; };
+
+	cpu_card {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		timer@0 {
+			compatible = "snps,arc-timer";
+			clocks = <&core_clk>;
+			reg = <0 1>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256M */
+	};
 };
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index cf999b0..54a9b00 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -33,6 +33,10 @@
 #define ARC_AUX_TIMER0_CTRL	0x22	/* Timer 0 control */
 #define ARC_AUX_TIMER0_LIMIT	0x23	/* Timer 0 limit */
 
+#define ARC_AUX_TIMER1_CNT	0x100	/* Timer 1 count */
+#define ARC_AUX_TIMER1_CTRL	0x101	/* Timer 1 control */
+#define ARC_AUX_TIMER1_LIMIT	0x102	/* Timer 1 limit */
+
 #define ARC_AUX_INTR_VEC_BASE	0x25
 
 /* Data cache related auxiliary registers */
diff --git a/arch/arc/include/asm/init_helpers.h b/arch/arc/include/asm/init_helpers.h
deleted file mode 100644
index 7607e19..0000000
--- a/arch/arc/include/asm/init_helpers.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARC_INIT_HELPERS_H
-#define _ASM_ARC_INIT_HELPERS_H
-
-int init_cache_f_r(void);
-
-#endif	/* _ASM_ARC_INIT_HELPERS_H */
diff --git a/arch/arc/include/asm/relocate.h b/arch/arc/include/asm/relocate.h
deleted file mode 100644
index 4c5f923..0000000
--- a/arch/arc/include/asm/relocate.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARC_RELOCATE_H
-#define _ASM_ARC_RELOCATE_H
-
-#include <common.h>
-
-int copy_uboot_to_ram(void);
-int clear_bss(void);
-int do_elf_reloc_fixups(void);
-
-#endif	/* _ASM_ARC_RELOCATE_H */
diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile
index eb62b3c..12097bf 100644
--- a/arch/arc/lib/Makefile
+++ b/arch/arc/lib/Makefile
@@ -18,7 +18,6 @@ obj-y += memcmp.o
 obj-y += memcpy-700.o
 obj-y += memset.o
 obj-y += reset.o
-obj-y += timer.o
 obj-y += ints_low.o
 obj-y += init_helpers.o
 
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index b6ec831..f1436bf 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -59,10 +59,16 @@ static unsigned int __before_slc_op(const int op)
 
 static void __after_slc_op(const int op, unsigned int reg)
 {
-	if (op & OP_FLUSH)	/* flush / flush-n-inv both wait */
+	if (op & OP_FLUSH) {	/* flush / flush-n-inv both wait */
+		/*
+		 * Make sure "busy" bit reports correct status,
+		 * see STAR 9001165532
+		 */
+		read_aux_reg(ARC_AUX_SLC_CTRL);
 		while (read_aux_reg(ARC_AUX_SLC_CTRL) &
 		       DC_CTRL_FLUSH_STATUS)
 			;
+	}
 
 	/* Switch back to default Invalidate mode */
 	if (op == OP_INV)
diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c
index d1f10ab..cb80893 100644
--- a/arch/arc/lib/cpu.c
+++ b/arch/arc/lib/cpu.c
@@ -28,3 +28,9 @@ int arch_early_init_r(void)
 	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
 	return 0;
 }
+
+/* This is a dummy function on arc */
+int dram_init(void)
+{
+	return 0;
+}
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 90ee7e0..b2ba768 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -10,6 +10,22 @@
 #include <asm/arcregs.h>
 
 ENTRY(_start)
+	; Non-masters will be halted immediately, they might be kicked later
+	; by platform code right before passing control to the Linux kernel
+	; in bootm.c:boot_jump_linux().
+	lr 	r5, [identity]
+	lsr	r5, r5, 8
+	bmsk	r5, r5, 7
+	cmp	r5, 0
+	mov.nz	r0, r5
+	bz	.Lmaster_proceed
+	flag	1
+	nop
+	nop
+	nop
+
+.Lmaster_proceed:
+
 	/* Setup interrupt vector base that matches "__text_start" */
 	sr	__ivt_start, [ARC_AUX_INTR_VEC_BASE]
 
diff --git a/arch/arc/lib/timer.c b/arch/arc/lib/timer.c
deleted file mode 100644
index a0acbbc..0000000
--- a/arch/arc/lib/timer.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/arcregs.h>
-
-#define NH_MODE	(1 << 1)	/* Disable timer if CPU is halted */
-
-int timer_init(void)
-{
-	write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
-	/* Set max value for counter/timer */
-	write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
-	/* Set initial count value and restart counter/timer */
-	write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
-	return 0;
-}
-
-unsigned long timer_read_counter(void)
-{
-	return read_aux_reg(ARC_AUX_TIMER0_CNT);
-}
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2781ff0..42f93b4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -214,6 +214,10 @@ config ENABLE_ARM_SOC_BOOT0_HOOK
 	  ARM_SOC_BOOT0_HOOK which contains the required assembler
 	  preprocessor code.
 
+config ARM_CORTEX_CPU_IS_UP
+	bool
+	default n
+
 config USE_ARCH_MEMCPY
 	bool "Use an assembly optimized implementation of memcpy"
 	default y
@@ -559,6 +563,14 @@ config TARGET_BCMNSP
 	bool "Support bcmnsp"
 	select CPU_V7
 
+config TARGET_BCMNS2
+	bool "Support Broadcom Northstar2"
+	select ARM64
+	help
+	  Support for Broadcom Northstar 2 SoCs.  NS2 is a quad-core 64-bit
+	  ARMv8 Cortex-A57 processors targeting a broad range of networking
+	  applications
+
 config ARCH_EXYNOS
 	bool "Samsung EXYNOS"
 	select DM
@@ -722,6 +734,12 @@ config OMAP54XX
 config AM43XX
 	bool "AM43XX SoC"
 	select ARCH_OMAP2
+	imply SPL_DM
+	imply SPL_DM_SEQ_ALIAS
+	imply SPL_OF_CONTROL
+	imply SPL_OF_TRANSLATE
+	imply SPL_SEPARATE_BSS
+	imply SPL_SYS_MALLOC_SIMPLE
 	imply SYS_THUMB_BUILD
 	help
 	  Support for AM43xx SOC from Texas Instruments.
@@ -1118,6 +1136,7 @@ config ARCH_STI
 	select DM_SERIAL
 	select BLK
 	select DM_MMC
+	select DM_RESET
 	help
 	  Support for STMicroelectronics STiH407/10 SoC family.
 	  This SoC is used on Linaro 96Board STiH410-B2260
@@ -1239,6 +1258,7 @@ source "board/broadcom/bcm23550_w1d/Kconfig"
 source "board/broadcom/bcm28155_ap/Kconfig"
 source "board/broadcom/bcmcygnus/Kconfig"
 source "board/broadcom/bcmnsp/Kconfig"
+source "board/broadcom/bcmns2/Kconfig"
 source "board/cavium/thunderx/Kconfig"
 source "board/cirrus/edb93xx/Kconfig"
 source "board/compulab/cm_t335/Kconfig"
@@ -1269,6 +1289,7 @@ source "board/freescale/mx53evk/Kconfig"
 source "board/freescale/mx53loco/Kconfig"
 source "board/freescale/mx53smd/Kconfig"
 source "board/freescale/s32v234evb/Kconfig"
+source "board/gdsys/a38x/Kconfig"
 source "board/grinn/chiliboard/Kconfig"
 source "board/gumstix/pepper/Kconfig"
 source "board/h2200/Kconfig"
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 08d7d1b..907c693 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -120,7 +120,7 @@ endif
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
-		-j .u_boot_list -j .rela.dyn
+		-j .u_boot_list -j .rela.dyn -j .got -j .got.plt
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
 		-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c
index e8ba1ae..1edb1a4 100644
--- a/arch/arm/cpu/arm720t/interrupts.c
+++ b/arch/arm/cpu/arm720t/interrupts.c
@@ -12,12 +12,6 @@
 
 #include <common.h>
 
-#ifdef CONFIG_USE_IRQ
-void do_irq (struct pt_regs *pt_regs)
-{
-}
-#endif
-
 #if defined(CONFIG_TEGRA)
 static ulong timestamp;
 static ulong lastdec;
diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile
index 7aa432a..8faf34b 100644
--- a/arch/arm/cpu/arm920t/Makefile
+++ b/arch/arm/cpu/arm920t/Makefile
@@ -8,7 +8,6 @@
 extra-y	= start.o
 
 obj-y	+= cpu.o
-obj-$(CONFIG_USE_IRQ)	+= interrupts.o
 
 obj-$(CONFIG_EP93XX) += ep93xx/
 obj-$(CONFIG_IMX) += imx/
diff --git a/arch/arm/cpu/arm920t/interrupts.c b/arch/arm/cpu/arm920t/interrupts.c
deleted file mode 100644
index 0e04d36..0000000
--- a/arch/arm/cpu/arm920t/interrupts.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/proc-armv/ptrace.h>
-
-#if defined (CONFIG_ARCH_INTEGRATOR)
-void do_irq (struct pt_regs *pt_regs)
-{
-	/* ASSUMED to be a timer interrupt  */
-	/* Just clear it - count handled in */
-	/* integratorap.c                   */
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x0C) = 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm920t/s3c24x0/Makefile b/arch/arm/cpu/arm920t/s3c24x0/Makefile
index e44c549..e78f8a0 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/Makefile
+++ b/arch/arm/cpu/arm920t/s3c24x0/Makefile
@@ -5,7 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_USE_IRQ) += interrupts.o
 obj-$(CONFIG_DISPLAY_CPUINFO)	+= cpu_info.o
 obj-y	+= speed.o
 obj-y	+= timer.o
diff --git a/arch/arm/cpu/arm920t/s3c24x0/interrupts.c b/arch/arm/cpu/arm920t/s3c24x0/interrupts.c
deleted file mode 100644
index 036e3b9..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/interrupts.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#include <asm/arch/s3c24x0_cpu.h>
-#include <asm/proc-armv/ptrace.h>
-
-void do_irq (struct pt_regs *pt_regs)
-{
-	struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt();
-	u_int32_t intpnd = readl(&irq->INTPND);
-
-}
diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c
index f3b9a66..6a9000e 100644
--- a/arch/arm/cpu/arm926ejs/armada100/dram.c
+++ b/arch/arm/cpu/arm926ejs/armada100/dram.c
@@ -108,7 +108,9 @@ int dram_init(void)
  * If this function is not defined here,
  * board.c alters dram bank zero configuration defined above.
  */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	dram_init();
+
+	return 0;
 }
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index 3d41d37..e1dc5f3 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -37,7 +37,7 @@
 
 	.align	5
 
-#define	ONE_MS		(GENERIC_TIMER_CLK / 1000)
+#define	ONE_MS		(COUNTER_FREQUENCY / 1000)
 #define	RESET_WAIT	(30 * ONE_MS)
 
 .globl	psci_version
diff --git a/arch/arm/cpu/armv7/ls102xa/timer.c b/arch/arm/cpu/armv7/ls102xa/timer.c
index e6a32ca..d5237d2 100644
--- a/arch/arm/cpu/armv7/ls102xa/timer.c
+++ b/arch/arm/cpu/armv7/ls102xa/timer.c
@@ -62,7 +62,7 @@ int timer_init(void)
 	/* Enable System Counter */
 	writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);
 
-	freq = GENERIC_TIMER_CLK;
+	freq = COUNTER_FREQUENCY;
 	asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
 
 	/* Set PL1 Physical Timer Ctrl */
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 95ce938..e39aba7 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -188,11 +188,11 @@ ENTRY(_nonsec_init)
  * we do this here instead.
  * But first check if we have the generic timer.
  */
-#ifdef CONFIG_TIMER_CLK_FREQ
+#ifdef COUNTER_FREQUENCY
 	mrc	p15, 0, r0, c0, c1, 1		@ read ID_PFR1
 	and	r0, r0, #CPUID_ARM_GENTIMER_MASK	@ mask arch timer bits
 	cmp	r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
-	ldreq	r1, =CONFIG_TIMER_CLK_FREQ
+	ldreq	r1, =COUNTER_FREQUENCY
 	mcreq	p15, 0, r1, c14, c0, 0		@ write CNTFRQ
 #endif
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index 766b8c7..104dc90 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -46,7 +46,7 @@ static u32 __secure cp15_read_cntp_ctl(void)
 	return val;
 }
 
-#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000)
+#define ONE_MS (COUNTER_FREQUENCY / 1000)
 
 static void __secure __mdelay(u32 ms)
 {
diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
index e1a6c40..93c9085 100644
--- a/arch/arm/cpu/armv7m/Makefile
+++ b/arch/arm/cpu/armv7m/Makefile
@@ -6,6 +6,5 @@
 #
 
 extra-y := start.o
-obj-y += cpu.o
-
+obj-y += cpu.o cache.o
 obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o
diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
new file mode 100644
index 0000000..162cfe3
--- /dev/null
+++ b/arch/arm/cpu/armv7m/cache.c
@@ -0,0 +1,336 @@
+/*
+ * (C) Copyright 2017
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/armv7m.h>
+#include <asm/io.h>
+
+/* Cache maintenance operation registers */
+
+#define V7M_CACHE_REG_ICIALLU		((u32 *)(V7M_CACHE_MAINT_BASE + 0x00))
+#define INVAL_ICACHE_POU		0
+#define V7M_CACHE_REG_ICIMVALU		((u32 *)(V7M_CACHE_MAINT_BASE + 0x08))
+#define V7M_CACHE_REG_DCIMVAC		((u32 *)(V7M_CACHE_MAINT_BASE + 0x0C))
+#define V7M_CACHE_REG_DCISW		((u32 *)(V7M_CACHE_MAINT_BASE + 0x10))
+#define V7M_CACHE_REG_DCCMVAU		((u32 *)(V7M_CACHE_MAINT_BASE + 0x14))
+#define V7M_CACHE_REG_DCCMVAC		((u32 *)(V7M_CACHE_MAINT_BASE + 0x18))
+#define V7M_CACHE_REG_DCCSW		((u32 *)(V7M_CACHE_MAINT_BASE + 0x1C))
+#define V7M_CACHE_REG_DCCIMVAC		((u32 *)(V7M_CACHE_MAINT_BASE + 0x20))
+#define V7M_CACHE_REG_DCCISW		((u32 *)(V7M_CACHE_MAINT_BASE + 0x24))
+#define WAYS_SHIFT			30
+#define SETS_SHIFT			5
+
+/* armv7m processor feature registers */
+
+#define V7M_PROC_REG_CLIDR		((u32 *)(V7M_PROC_FTR_BASE + 0x00))
+#define V7M_PROC_REG_CTR		((u32 *)(V7M_PROC_FTR_BASE + 0x04))
+#define V7M_PROC_REG_CCSIDR		((u32 *)(V7M_PROC_FTR_BASE + 0x08))
+#define MASK_NUM_WAYS			GENMASK(12, 3)
+#define MASK_NUM_SETS			GENMASK(27, 13)
+#define CLINE_SIZE_MASK			GENMASK(2, 0)
+#define NUM_WAYS_SHIFT			3
+#define NUM_SETS_SHIFT			13
+#define V7M_PROC_REG_CSSELR		((u32 *)(V7M_PROC_FTR_BASE + 0x0C))
+#define SEL_I_OR_D			BIT(0)
+
+enum cache_type {
+	DCACHE,
+	ICACHE,
+};
+
+/* PoU : Point of Unification, Poc: Point of Coherency */
+enum cache_action {
+	INVALIDATE_POU,		/* i-cache invalidate by address */
+	INVALIDATE_POC,		/* d-cache invalidate by address */
+	INVALIDATE_SET_WAY,	/* d-cache invalidate by sets/ways */
+	FLUSH_POU,		/* d-cache clean by address to the PoU */
+	FLUSH_POC,		/* d-cache clean by address to the PoC */
+	FLUSH_SET_WAY,		/* d-cache clean by sets/ways */
+	FLUSH_INVAL_POC,	/* d-cache clean & invalidate by addr to PoC */
+	FLUSH_INVAL_SET_WAY,	/* d-cache clean & invalidate by set/ways */
+};
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+struct dcache_config {
+	u32 ways;
+	u32 sets;
+};
+
+static void get_cache_ways_sets(struct dcache_config *cache)
+{
+	u32 cache_size_id = readl(V7M_PROC_REG_CCSIDR);
+
+	cache->ways = (cache_size_id & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+	cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT;
+}
+
+/*
+ * Return the io register to perform required cache action like clean or clean
+ * & invalidate by sets/ways.
+ */
+static u32 *get_action_reg_set_ways(enum cache_action action)
+{
+	switch (action) {
+	case INVALIDATE_SET_WAY:
+		return V7M_CACHE_REG_DCISW;
+	case FLUSH_SET_WAY:
+		return V7M_CACHE_REG_DCCSW;
+	case FLUSH_INVAL_SET_WAY:
+		return V7M_CACHE_REG_DCCISW;
+	default:
+		break;
+	};
+
+	return NULL;
+}
+
+/*
+ * Return the io register to perform required cache action like clean or clean
+ * & invalidate by adddress or range.
+ */
+static u32 *get_action_reg_range(enum cache_action action)
+{
+	switch (action) {
+	case INVALIDATE_POU:
+		return V7M_CACHE_REG_ICIMVALU;
+	case INVALIDATE_POC:
+		return V7M_CACHE_REG_DCIMVAC;
+	case FLUSH_POU:
+		return V7M_CACHE_REG_DCCMVAU;
+	case FLUSH_POC:
+		return V7M_CACHE_REG_DCCMVAC;
+	case FLUSH_INVAL_POC:
+		return V7M_CACHE_REG_DCCIMVAC;
+	default:
+		break;
+	}
+
+	return NULL;
+}
+
+static u32 get_cline_size(enum cache_type type)
+{
+	u32 size;
+
+	if (type == DCACHE)
+		clrbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
+	else if (type == ICACHE)
+		setbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
+	/* Make sure cache selection is effective for next memory access */
+	dsb();
+
+	size = readl(V7M_PROC_REG_CCSIDR) & CLINE_SIZE_MASK;
+	/* Size enocoded as 2 less than log(no_of_words_in_cache_line) base 2 */
+	size = 1 << (size + 2);
+	debug("cache line size is %d\n", size);
+
+	return size;
+}
+
+/* Perform the action like invalidate/clean on a range of cache addresses */
+static int action_cache_range(enum cache_action action, u32 start_addr,
+			      int64_t size)
+{
+	u32 cline_size;
+	u32 *action_reg;
+	enum cache_type type;
+
+	action_reg = get_action_reg_range(action);
+	if (!action_reg)
+		return -EINVAL;
+	if (action == INVALIDATE_POU)
+		type = ICACHE;
+	else
+		type = DCACHE;
+
+	/* Cache line size is minium size for the cache action */
+	cline_size = get_cline_size(type);
+	/* Align start address to cache line boundary */
+	start_addr &= ~(cline_size - 1);
+	debug("total size for cache action = %llx\n", size);
+	do {
+		writel(start_addr, action_reg);
+		size -= cline_size;
+		start_addr += cline_size;
+	} while (size > cline_size);
+
+	/* Make sure cache action is effective for next memory access */
+	dsb();
+	isb();	/* Make sure instruction stream sees it */
+	debug("cache action on range done\n");
+
+	return 0;
+}
+
+/* Perform the action like invalidate/clean on all cached addresses */
+static int action_dcache_all(enum cache_action action)
+{
+	struct dcache_config cache;
+	u32 *action_reg;
+	int i, j;
+
+	action_reg = get_action_reg_set_ways(action);
+	if (!action_reg)
+		return -EINVAL;
+
+	clrbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
+	/* Make sure cache selection is effective for next memory access */
+	dsb();
+
+	get_cache_ways_sets(&cache);	/* Get number of ways & sets */
+	debug("cache: ways= %d, sets= %d\n", cache.ways + 1, cache.sets + 1);
+	for (i = cache.sets; i >= 0; i--) {
+		for (j = cache.ways; j >= 0; j--) {
+			writel((j << WAYS_SHIFT) | (i << SETS_SHIFT),
+			       action_reg);
+		}
+	}
+
+	/* Make sure cache action is effective for next memory access */
+	dsb();
+	isb();	/* Make sure instruction stream sees it */
+
+	return 0;
+}
+
+void dcache_enable(void)
+{
+	if (dcache_status())	/* return if cache already enabled */
+		return;
+
+	if (action_dcache_all(INVALIDATE_SET_WAY)) {
+		printf("ERR: D-cache not enabled\n");
+		return;
+	}
+
+	setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE));
+
+	/* Make sure cache action is effective for next memory access */
+	dsb();
+	isb();	/* Make sure instruction stream sees it */
+}
+
+void dcache_disable(void)
+{
+	if (!dcache_status())
+		return;
+
+	/* if dcache is enabled-> dcache disable & then flush */
+	if (action_dcache_all(FLUSH_SET_WAY)) {
+		printf("ERR: D-cache not flushed\n");
+		return;
+	}
+
+	clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE));
+
+	/* Make sure cache action is effective for next memory access */
+	dsb();
+	isb();	/* Make sure instruction stream sees it */
+}
+
+int dcache_status(void)
+{
+	return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_DCACHE)) != 0;
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	if (action_cache_range(INVALIDATE_POC, start, stop - start)) {
+		printf("ERR: D-cache not invalidated\n");
+		return;
+	}
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	if (action_cache_range(FLUSH_POC, start, stop - start)) {
+		printf("ERR: D-cache not flushed\n");
+		return;
+	}
+}
+#else
+void dcache_enable(void)
+{
+	return;
+}
+
+void dcache_disable(void)
+{
+	return;
+}
+
+int dcache_status(void)
+{
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+
+void invalidate_icache_all(void)
+{
+	writel(INVAL_ICACHE_POU, V7M_CACHE_REG_ICIALLU);
+
+	/* Make sure cache action is effective for next memory access */
+	dsb();
+	isb();	/* Make sure instruction stream sees it */
+}
+
+void icache_enable(void)
+{
+	if (icache_status())
+		return;
+
+	invalidate_icache_all();
+	setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE));
+
+	/* Make sure cache action is effective for next memory access */
+	dsb();
+	isb();	/* Make sure instruction stream sees it */
+}
+
+int icache_status(void)
+{
+	return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_ICACHE)) != 0;
+}
+
+void icache_disable(void)
+{
+	if (!icache_status())
+		return;
+
+	isb();	/* flush pipeline */
+	clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE));
+	isb();	/* subsequent instructions fetch see cache disable effect */
+}
+#else
+void icache_enable(void)
+{
+	return;
+}
+
+void icache_disable(void)
+{
+	return;
+}
+
+int icache_status(void)
+{
+	return 0;
+}
+#endif
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a99b1c6..b24462b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -73,6 +73,7 @@ config ARCH_LS2080A
 	select SYS_FSL_ERRATUM_A009803
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A010165
+	select SYS_FSL_ERRATUM_A009203
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 
@@ -134,6 +135,8 @@ config FSL_LS_PPA
 choice
 	prompt "FSL Layerscape PPA firmware loading-media select"
 	depends on FSL_LS_PPA
+	default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
+	default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
 	default SYS_LS_PPA_FW_IN_XIP
 
 config SYS_LS_PPA_FW_IN_XIP
@@ -142,13 +145,27 @@ config SYS_LS_PPA_FW_IN_XIP
 	  Say Y here if the PPA firmware locate at XIP flash, such
 	  as NOR or QSPI flash.
 
+config SYS_LS_PPA_FW_IN_MMC
+	bool "eMMC or SD Card"
+	help
+	  Say Y here if the PPA firmware locate at eMMC/SD card.
+
+config SYS_LS_PPA_FW_IN_NAND
+	bool "NAND"
+	help
+	  Say Y here if the PPA firmware locate at NAND flash.
+
 endchoice
 
 config SYS_LS_PPA_FW_ADDR
 	hex "Address of PPA firmware loading from"
 	depends on FSL_LS_PPA
 	default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+	default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
 	default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x500000 if SYS_LS_PPA_FW_IN_MMC
+	default 0x500000 if SYS_LS_PPA_FW_IN_NAND
+
 	help
 	  If the PPA firmware locate at XIP flash, such as NOR or
 	  QSPI flash, this address is a directly memory-mapped.
@@ -307,6 +324,9 @@ config SYS_FSL_ERRATUM_A008585
 config SYS_FSL_ERRATUM_A008850
 	bool
 
+config SYS_FSL_ERRATUM_A009203
+	bool
+
 config SYS_FSL_ERRATUM_A009635
 	bool
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 7e66ee0..d446527 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <asm/system.h>
@@ -89,6 +90,49 @@ static inline void early_mmu_setup(void)
 	set_sctlr(get_sctlr() | CR_M);
 }
 
+static void fix_pcie_mmu_map(void)
+{
+#ifdef CONFIG_LS2080A
+	unsigned int i;
+	u32 svr, ver;
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	svr = gur_in32(&gur->svr);
+	ver = SVR_SOC_VER(svr);
+
+	/* Fix PCIE base and size for LS2088A */
+	if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
+	    (ver == SVR_LS2048A) || (ver == SVR_LS2044A)) {
+		for (i = 0; i < ARRAY_SIZE(final_map); i++) {
+			switch (final_map[i].phys) {
+			case CONFIG_SYS_PCIE1_PHYS_ADDR:
+				final_map[i].phys = 0x2000000000ULL;
+				final_map[i].virt = 0x2000000000ULL;
+				final_map[i].size = 0x800000000ULL;
+				break;
+			case CONFIG_SYS_PCIE2_PHYS_ADDR:
+				final_map[i].phys = 0x2800000000ULL;
+				final_map[i].virt = 0x2800000000ULL;
+				final_map[i].size = 0x800000000ULL;
+				break;
+			case CONFIG_SYS_PCIE3_PHYS_ADDR:
+				final_map[i].phys = 0x3000000000ULL;
+				final_map[i].virt = 0x3000000000ULL;
+				final_map[i].size = 0x800000000ULL;
+				break;
+			case CONFIG_SYS_PCIE4_PHYS_ADDR:
+				final_map[i].phys = 0x3800000000ULL;
+				final_map[i].virt = 0x3800000000ULL;
+				final_map[i].size = 0x800000000ULL;
+				break;
+			default:
+				break;
+			}
+		}
+	}
+#endif
+}
+
 /*
  * The final tables look similar to early tables, but different in detail.
  * These tables are in DRAM. Sub tables are added to enable cache for
@@ -103,6 +147,9 @@ static inline void final_mmu_setup(void)
 	unsigned int el = current_el();
 	int index;
 
+	/* fix the final_map before filling in the block entries */
+	fix_pcie_mmu_map();
+
 	mem_map = final_map;
 
 	/* Update mapping for DDR to actual size */
@@ -436,7 +483,14 @@ int arch_early_init_r(void)
 #endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
-	erratum_a009635();
+	u32 svr_dev_id;
+	/*
+	 * erratum A009635 is valid only for LS2080A SoC and
+	 * its personalitiesi
+	 */
+	svr_dev_id = get_svr() >> 16;
+	if (svr_dev_id == SVR_DEV_LS2080A)
+		erratum_a009635();
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
 	erratum_a009942_check_cpo();
@@ -610,7 +664,7 @@ phys_size_t get_effective_memsize(void)
 	return ea_size;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 	phys_size_t dp_ddr_size;
@@ -719,6 +773,8 @@ void dram_init_banksize(void)
 		}
 	}
 #endif
+
+	return 0;
 }
 
 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
@@ -821,7 +877,7 @@ void update_early_mmu_table(void)
 
 __weak int dram_init(void)
 {
-	gd->ram_size = initdram(0);
+	fsl_initdram();
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 	/* This will break-before-make MMU for DDR */
 	update_early_mmu_table();
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 26d4a30..762a95b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -387,8 +387,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_firmware(blob);
 #endif
+#ifndef CONFIG_LS1012A
 	fsl_fdt_disable_usb(blob);
-
+#endif
 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
 	fdt_fixup_gic(blob);
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index 7faa86c..955e0b7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -23,6 +23,11 @@ int xfi_dpmac[XFI8 + 1];
 int sgmii_dpmac[SGMII16 + 1];
 #endif
 
+__weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
+{
+	return;
+}
+
 int is_serdes_configured(enum srds_prtcl device)
 {
 	int ret = 0;
@@ -46,20 +51,22 @@ int is_serdes_configured(enum srds_prtcl device)
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-	u32 cfg = gur_in32(&gur->rcwsr[28]);
+	u32 cfg = 0;
 	int i;
 
 	switch (sd) {
 #ifdef CONFIG_SYS_FSL_SRDS_1
 	case FSL_SRDS_1:
-		cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
-		cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+		cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
+		cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+		cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
 		break;
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	case FSL_SRDS_2:
-		cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
-		cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+		cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
+		cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
+		cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
 		break;
 #endif
 	default:
@@ -78,8 +85,8 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 	return -ENODEV;
 }
 
-void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
-		u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
+void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
+		 u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 cfg;
@@ -90,7 +97,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 
 	memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
 
-	cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
+	cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
 	cfg >>= sd_prctl_shift;
 	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 
@@ -106,28 +113,10 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 #ifdef CONFIG_FSL_MC_ENET
 			switch (lane_prtcl) {
 			case QSGMII_A:
-				wriop_init_dpmac(sd, 5, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 6, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 7, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 8, (int)lane_prtcl);
-				break;
 			case QSGMII_B:
-				wriop_init_dpmac(sd, 1, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 2, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 3, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 4, (int)lane_prtcl);
-				break;
 			case QSGMII_C:
-				wriop_init_dpmac(sd, 13, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 14, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 15, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 16, (int)lane_prtcl);
-				break;
 			case QSGMII_D:
-				wriop_init_dpmac(sd, 9, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 10, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 11, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 12, (int)lane_prtcl);
+				wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
 				break;
 			default:
 				if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
@@ -165,15 +154,17 @@ void fsl_serdes_init(void)
 #ifdef CONFIG_SYS_FSL_SRDS_1
 	serdes_init(FSL_SRDS_1,
 		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
-		    FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK,
-		    FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT,
+		    FSL_CHASSIS3_SRDS1_REGSR,
+		    FSL_CHASSIS3_SRDS1_PRTCL_MASK,
+		    FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
 		    serdes1_prtcl_map);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	serdes_init(FSL_SRDS_2,
 		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
-		    FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK,
-		    FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT,
+		    FSL_CHASSIS3_SRDS2_REGSR,
+		    FSL_CHASSIS3_SRDS2_PRTCL_MASK,
+		    FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
 		    serdes2_prtcl_map);
 #endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
index b68e87d..b35ad5f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <malloc.h>
 #include <config.h>
 #include <errno.h>
 #include <asm/system.h>
@@ -21,9 +22,17 @@
 #include <fsl_validate.h>
 #endif
 
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_NAND
+#include <nand.h>
+#elif defined(CONFIG_SYS_LS_PPA_FW_IN_MMC)
+#include <mmc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
 int ppa_init(void)
 {
-	const void *ppa_fit_addr;
+	void *ppa_fit_addr;
 	u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
 	int ret;
 
@@ -34,10 +43,137 @@ int ppa_init(void)
 
 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
 	ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
+	debug("%s: PPA image load from XIP\n", __func__);
+#else /* !CONFIG_SYS_LS_PPA_FW_IN_XIP */
+	size_t fw_length, fdt_header_len = sizeof(struct fdt_header);
+
+	/* Copy PPA image from MMC/SD/NAND to allocated memory */
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_MMC
+	struct mmc *mmc;
+	int dev = CONFIG_SYS_MMC_ENV_DEV;
+	struct fdt_header *fitp;
+	u32 cnt;
+	u32 blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512;
+
+	debug("%s: PPA image load from eMMC/SD\n", __func__);
+
+	ret = mmc_initialize(gd->bd);
+	if (ret) {
+		printf("%s: mmc_initialize() failed\n", __func__);
+		return ret;
+	}
+	mmc = find_mmc_device(dev);
+	if (!mmc) {
+		printf("PPA: MMC cannot find device for PPA firmware\n");
+		return -ENODEV;
+	}
+
+	ret = mmc_init(mmc);
+	if (ret) {
+		printf("%s: mmc_init() failed\n", __func__);
+		return ret;
+	}
+
+	fitp = malloc(roundup(fdt_header_len, 512));
+	if (!fitp) {
+		printf("PPA: malloc failed for FIT header(size 0x%zx)\n",
+		       roundup(fdt_header_len, 512));
+		return -ENOMEM;
+	}
+
+	cnt = DIV_ROUND_UP(fdt_header_len, 512);
+	debug("%s: MMC read PPA FIT header: dev # %u, block # %u, count %u\n",
+	      __func__, dev, blk, cnt);
+	ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, fitp);
+	if (ret != cnt) {
+		free(fitp);
+		printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
+		       CONFIG_SYS_LS_PPA_FW_ADDR);
+		return -EIO;
+	}
+
+	/* flush cache after read */
+	flush_cache((ulong)fitp, cnt * 512);
+
+	ret = fdt_check_header(fitp);
+	if (ret) {
+		free(fitp);
+		printf("%s: fdt_check_header() failed\n", __func__);
+		return ret;
+	}
+
+	fw_length = fdt_totalsize(fitp);
+	free(fitp);
+
+	fw_length = roundup(fw_length, 512);
+	ppa_fit_addr = malloc(fw_length);
+	if (!ppa_fit_addr) {
+		printf("PPA: malloc failed for PPA image(size 0x%zx)\n",
+		       fw_length);
+		return -ENOMEM;
+	}
+
+	cnt = DIV_ROUND_UP(fw_length, 512);
+	debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n",
+	      __func__, dev, blk, cnt);
+	ret = mmc->block_dev.block_read(&mmc->block_dev,
+					blk, cnt, ppa_fit_addr);
+	if (ret != cnt) {
+		free(ppa_fit_addr);
+		printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
+		       CONFIG_SYS_LS_PPA_FW_ADDR);
+		return -EIO;
+	}
+
+	/* flush cache after read */
+	flush_cache((ulong)ppa_fit_addr, cnt * 512);
+
+#elif defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
+	struct fdt_header fit;
+
+	debug("%s: PPA image load from NAND\n", __func__);
+
+	nand_init();
+	ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
+		       &fdt_header_len, (u_char *)&fit);
+	if (ret == -EUCLEAN) {
+		printf("NAND read of PPA FIT header at offset 0x%x failed\n",
+		       CONFIG_SYS_LS_PPA_FW_ADDR);
+		return -EIO;
+	}
+
+	ret = fdt_check_header(&fit);
+	if (ret) {
+		printf("%s: fdt_check_header() failed\n", __func__);
+		return ret;
+	}
+
+	fw_length = fdt_totalsize(&fit);
+
+	ppa_fit_addr = malloc(fw_length);
+	if (!ppa_fit_addr) {
+		printf("PPA: malloc failed for PPA image(size 0x%zx)\n",
+		       fw_length);
+		return -ENOMEM;
+	}
+
+	ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
+		       &fw_length, (u_char *)ppa_fit_addr);
+	if (ret == -EUCLEAN) {
+		free(ppa_fit_addr);
+		printf("NAND read of PPA firmware at offset 0x%x failed\n",
+		       CONFIG_SYS_LS_PPA_FW_ADDR);
+		return -EIO;
+	}
+
+	/* flush cache after read */
+	flush_cache((ulong)ppa_fit_addr, fw_length);
 #else
 #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
 #endif
 
+#endif
+
 #ifdef CONFIG_CHAIN_OF_TRUST
 	ppa_img_addr = (uintptr_t)ppa_fit_addr;
 	if (fsl_check_boot_mode_secure() != 0) {
@@ -65,5 +201,10 @@ int ppa_init(void)
 	      boot_loc_ptr_l, boot_loc_ptr_h);
 	ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h);
 
+#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
+	defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
+	free(ppa_fit_addr);
+#endif
+
 	return ret;
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index b54a937..9e3cdd7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -152,6 +152,7 @@ static void erratum_rcw_src(void)
  * This erratum requires setting glitch_en bit to enable
  * digital glitch filter to improve clock stability.
  */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
 static void erratum_a009203(void)
 {
 	u8 __iomem *ptr;
@@ -178,6 +179,7 @@ static void erratum_a009203(void)
 #endif
 #endif
 }
+#endif
 
 void bypass_smmu(void)
 {
@@ -191,7 +193,9 @@ void fsl_lsch3_early_init_f(void)
 {
 	erratum_rcw_src();
 	init_early_memctl_regs();	/* tighten IFC timing */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
 	erratum_a009203();
+#endif
 	erratum_a008514();
 	erratum_a008336();
 #ifdef CONFIG_CHAIN_OF_TRUST
diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 499e1dd..5ac48eb 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -13,7 +13,7 @@ config SPL_LIBGENERIC_SUPPORT
 	default y
 
 config SPL_MMC_SUPPORT
-	default y
+	default y if MMC_SDHCI_ZYNQ
 
 config SPL_SERIAL_SUPPORT
 	default y
diff --git a/arch/arm/cpu/sa1100/cpu.c b/arch/arm/cpu/sa1100/cpu.c
index 4c9752a..59585af 100644
--- a/arch/arm/cpu/sa1100/cpu.c
+++ b/arch/arm/cpu/sa1100/cpu.c
@@ -19,10 +19,6 @@
 #include <asm/system.h>
 #include <asm/io.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
 int cleanup_before_linux (void)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8187f65..aeb6674 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -29,17 +29,20 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3036-sdk.dtb \
+	rk3288-evb.dtb \
+	rk3288-fennec.dtb \
 	rk3288-firefly.dtb \
+	rk3288-miqi.dtb \
+	rk3288-popmetal.dtb \
+	rk3188-radxarock.dtb \
+	rk3288-rock2-square.dtb \
+	rk3288-tinker.dtb \
 	rk3288-veyron-jerry.dtb \
 	rk3288-veyron-mickey.dtb \
 	rk3288-veyron-minnie.dtb \
-	rk3288-rock2-square.dtb \
-	rk3288-evb.dtb \
-	rk3288-fennec.dtb \
-	rk3288-tinker.dtb \
-	rk3288-popmetal.dtb \
 	rk3328-evb.dtb \
-	rk3399-evb.dtb
+	rk3399-evb.dtb \
+	rk3399-puma.dtb
 dtb-$(CONFIG_ARCH_MESON) += \
 	meson-gxbb-odroidc2.dtb
 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
@@ -58,6 +61,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra30-colibri.dtb \
 	tegra30-tec-ng.dtb \
 	tegra114-dalmore.dtb \
+	tegra124-apalis.dtb \
 	tegra124-jetson-tk1.dtb \
 	tegra124-nyan-big.dtb \
 	tegra124-cei-tk1-som.dtb \
@@ -71,16 +75,19 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 
 dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-3720-db.dtb			\
+	armada-3720-espressobin.dtb		\
 	armada-375-db.dtb			\
 	armada-388-clearfog.dtb			\
 	armada-388-gp.dtb			\
 	armada-385-amc.dtb			\
 	armada-7040-db.dtb			\
 	armada-8040-db.dtb			\
+	armada-8040-mcbin.dtb			\
 	armada-xp-gp.dtb			\
 	armada-xp-maxbcm.dtb			\
 	armada-xp-synology-ds414.dtb		\
-	armada-xp-theadorable.dtb
+	armada-xp-theadorable.dtb		\
+	armada-38x-controlcenterdc.dtb
 
 dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
 	uniphier-ld11-ref.dtb
@@ -221,6 +228,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \
 	sun5i-a13-olinuxino-micro.dtb \
 	sun5i-a13-q8-tablet.dtb \
 	sun5i-a13-utoo-p66.dtb \
+	sun5i-gr8-chip-pro.dtb \
 	sun5i-r8-chip.dtb
 dtb-$(CONFIG_MACH_SUN6I) += \
 	sun6i-a31-app4-evb1.dtb \
@@ -294,13 +302,17 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h3-orangepi-pc-plus.dtb \
 	sun8i-h3-orangepi-plus.dtb \
 	sun8i-h3-orangepi-plus2e.dtb \
-	sun8i-h3-nanopi-neo.dtb
+	sun8i-h3-nanopi-neo.dtb \
+	sun8i-h3-nanopi-neo-air.dtb
+dtb-$(CONFIG_MACH_SUN50I_H5) += \
+	sun50i-h5-orangepi-pc2.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
 	sun50i-a64-pine64-plus.dtb \
 	sun50i-a64-pine64.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
-	sun9i-a80-cubieboard4.dtb
+	sun9i-a80-cubieboard4.dtb \
+	sun9i-a80-cx-a99.dtb
 
 dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 	vf610-colibri.dtb \
diff --git a/arch/arm/dts/am437x-gp-evm-u-boot.dtsi b/arch/arm/dts/am437x-gp-evm-u-boot.dtsi
new file mode 100644
index 0000000..885a9a9
--- /dev/null
+++ b/arch/arm/dts/am437x-gp-evm-u-boot.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "dra7.dtsi"
+ */
+
+/{
+	ocp {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
+
+&mmc1 {
+	u-boot,dm-pre-reloc;
+};
+
+&mac {
+	u-boot,dm-pre-reloc;
+};
+
+&davinci_mdio {
+	u-boot,dm-pre-reloc;
+};
+
+&cpsw_emac0 {
+	u-boot,dm-pre-reloc;
+};
+
+&phy_sel {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts
new file mode 100644
index 0000000..aa6587a
--- /dev/null
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -0,0 +1,135 @@
+/*
+ * Device Tree file for Marvell Armada 3720 community board
+ * (ESPRESSOBin)
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Konstantin Porotchkin <kostap@marvell.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "armada-372x.dtsi"
+
+/ {
+	model = "Marvell Armada 3720 Community Board ESPRESSOBin";
+	compatible = "marvell,armada-3720-espressobin", "marvell,armada3720", "marvell,armada3710";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		ethernet0 = &eth0;
+		i2c0 = &i2c0;
+		spi0 = &spi0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
+	};
+};
+
+&comphy {
+	max-lanes = <3>;
+	phy0 {
+		phy-type = <PHY_TYPE_PEX0>;
+		phy-speed = <PHY_SPEED_2_5G>;
+	};
+
+	phy1 {
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+
+	phy2 {
+		phy-type = <PHY_TYPE_SATA0>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	phy-mode = "rgmii";
+	phy_addr = <0x1>;
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+/* CON3 */
+&sata {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p128", "spi-flash";
+		reg = <0>; /* Chip select 0 */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+	};
+};
+
+/* Exported on the micro USB connector CON32 through an FTDI */
+&uart0 {
+	status = "okay";
+};
+
+/* CON29 */
+&usb2 {
+	status = "okay";
+};
+
+/* CON31 */
+&usb3 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index 062f2a6..5bea63b 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -193,6 +193,20 @@
 				status = "disabled";
 			};
 
+			pinctl0: pinctl@13830 { /* north bridge */
+				compatible = "marvell,armada-3700-pinctl";
+				bank-name = "armada-3700-nb";
+				reg = <0x13830 0x4>;
+				pin-count = <36>;
+			};
+
+			pinctl1: pinctl@18830 { /* south bridge */
+				compatible = "marvell,armada-3700-pinctl";
+				bank-name = "armada-3700-sb";
+				reg = <0x18830 0x4>;
+				pin-count = <30>;
+			};
+
 			comphy: comphy@18300 {
 				compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
 				reg = <0x18300 0x28>,
diff --git a/arch/arm/dts/armada-38x-controlcenterdc.dts b/arch/arm/dts/armada-38x-controlcenterdc.dts
new file mode 100644
index 0000000..d183fd7
--- /dev/null
+++ b/arch/arm/dts/armada-38x-controlcenterdc.dts
@@ -0,0 +1,589 @@
+/*
+ * Device Tree file for the Guntermann & Drunck ControlCenter-Compact board
+ *
+ * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
+ *
+ * based on the Device Tree file for Marvell Armada 388 evaluation board
+ * (DB-88F6820), which is
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "armada-388.dtsi"
+
+&gpio0 {
+	u-boot,dm-pre-reloc;
+};
+
+&gpio1 {
+	u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+};
+
+/ {
+	model = "Controlcenter Digital Compact";
+	compatible = "marvell,a385-db", "marvell,armada388",
+		"marvell,armada385", "marvell,armada380";
+
+	chosen {
+		bootargs = "console=ttyS1,115200 earlyprintk";
+		stdout-path = "/soc/internal-regs/serial@12100";
+	};
+
+	aliases {
+		ethernet0 = &eth0;
+		ethernet2 = &eth2;
+		mdio-gpio0 = &MDIO0;
+		mdio-gpio1 = &MDIO1;
+		mdio-gpio2 = &MDIO2;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		i2c0 = &I2C0;
+		i2c1 = &I2C1;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>; /* 256 MB */
+	};
+
+	clocks {
+		sc16isclk: sc16isclk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <11059200>;
+		};
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+		internal-regs {
+			spi0: spi@10600 {
+				status = "okay";
+				sc16is741: sc16is741@0 {
+					compatible = "nxp,sc16is741";
+					reg = <0>;
+					clocks = <&sc16isclk>;
+					spi-max-frequency = <4000000>;
+					interrupt-parent = <&gpio0>;
+					interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+					gpio-controller;
+					#gpio-cells = <2>;
+				};
+			};
+
+			spi1: spi@10680 {
+				status = "okay";
+				u-boot,dm-pre-reloc;
+				spi-flash@0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "n25q016a";
+					reg = <0>; /* Chip select 0 */
+					spi-max-frequency = <108000000>;
+				};
+				spi-flash@1 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "n25q128a11";
+					reg = <1>; /* Chip select 1 */
+					spi-max-frequency = <108000000>;
+					u-boot,dm-pre-reloc;
+				};
+			};
+
+			I2C0: i2c@11000 {
+				status = "okay";
+				clock-frequency = <1000000>;
+				u-boot,dm-pre-reloc;
+				PCA21: pca9698@21 {
+					compatible = "nxp,pca9698";
+					reg = <0x21>;
+					#gpio-cells = <2>;
+					gpio-controller;
+				};
+				PCA22: pca9698@22 {
+					compatible = "nxp,pca9698";
+					u-boot,dm-pre-reloc;
+					reg = <0x22>;
+					#gpio-cells = <2>;
+					gpio-controller;
+				};
+				PCA23: pca9698@23 {
+					compatible = "nxp,pca9698";
+					reg = <0x23>;
+					#gpio-cells = <2>;
+					gpio-controller;
+				};
+				PCA24: pca9698@24 {
+					compatible = "nxp,pca9698";
+					reg = <0x24>;
+					#gpio-cells = <2>;
+					gpio-controller;
+				};
+				PCA25: pca9698@25 {
+					compatible = "nxp,pca9698";
+					reg = <0x25>;
+					#gpio-cells = <2>;
+					gpio-controller;
+				};
+				PCA26: pca9698@26 {
+					compatible = "nxp,pca9698";
+					reg = <0x26>;
+					#gpio-cells = <2>;
+					gpio-controller;
+				};
+			};
+
+			I2C1: i2c@11100 {
+				status = "okay";
+				clock-frequency = <400000>;
+				at97sc3205t@29 {
+					compatible = "atmel,at97sc3204t";
+					reg = <0x29>;
+					u-boot,i2c-offset-len = <0>;
+				};
+				emc2305@2d {
+					compatible = "smsc,emc2305";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x2d>;
+					fan@0 {
+						reg = <0>;
+					};
+					fan@1 {
+						reg = <1>;
+					};
+					fan@2 {
+						reg = <2>;
+					};
+					fan@3 {
+						reg = <3>;
+					};
+					fan@4 {
+						reg = <4>;
+					};
+				};
+				lm77@48 {
+					compatible = "national,lm77";
+					reg = <0x48>;
+				};
+				ads1015@49 {
+					compatible = "ti,ads1015";
+					reg = <0x49>;
+				};
+				lm77@4a {
+					compatible = "national,lm77";
+					reg = <0x4a>;
+				};
+				ads1015@4b {
+					compatible = "ti,ads1015";
+					reg = <0x4b>;
+				};
+				emc2305@4c {
+					compatible = "smsc,emc2305";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x4c>;
+					fan@0 {
+						reg = <0>;
+					};
+					fan@1 {
+						reg = <1>;
+					};
+					fan@2 {
+						reg = <2>;
+					};
+					fan@3 {
+						reg = <3>;
+					};
+					fan@4 {
+						reg = <4>;
+					};
+				};
+				at24c512@54 {
+					compatible = "atmel,24c512";
+					reg = <0x54>;
+					u-boot,i2c-offset-len = <2>;
+				};
+				ds1339@68 {
+					compatible = "dallas,ds1339";
+					reg = <0x68>;
+				};
+			};
+
+			serial@12000 {
+				status = "okay";
+			};
+
+			serial@12100 {
+				status = "okay";
+			};
+
+			ethernet@34000 {
+				status = "okay";
+				phy = <&phy1>;
+				phy-mode = "sgmii";
+			};
+
+			usb@58000 {
+				status = "ok";
+			};
+
+			ethernet@70000 {
+				status = "okay";
+				phy = <&phy0>;
+				phy-mode = "sgmii";
+			};
+
+			mdio@72004 {
+				phy0: ethernet-phy@0 {
+					reg = <1>;
+				};
+
+				phy1: ethernet-phy@1 {
+					reg = <0>;
+				};
+			};
+
+			sata@a8000 {
+				status = "okay";
+			};
+
+			sdhci@d8000 {
+				broken-cd;
+				wp-inverted;
+				bus-width = <4>;
+				status = "okay";
+				no-1-8-v;
+			};
+
+			usb3@f0000 {
+				status = "okay";
+			};
+		};
+
+		pcie-controller {
+			status = "okay";
+			/*
+			 * The two PCIe units are accessible through
+			 * standard PCIe slots on the board.
+			 */
+			pcie@3,0 {
+				/* Port 0, Lane 0 */
+				status = "okay";
+			};
+		};
+
+		MDIO0: mdio0 {
+			compatible = "virtual,mdio-gpio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpios = < /*MDC*/ &gpio0 13 0
+				  /*MDIO*/ &gpio0 14 0>;
+			mv88e1240@0 {
+				reg = <0x0>;
+			};
+			mv88e1240@1 {
+				reg = <0x1>;
+			};
+			mv88e1240@2 {
+				reg = <0x2>;
+			};
+			mv88e1240@3 {
+				reg = <0x3>;
+			};
+			mv88e1240@4 {
+				reg = <0x4>;
+			};
+			mv88e1240@5 {
+				reg = <0x5>;
+			};
+			mv88e1240@6 {
+				reg = <0x6>;
+			};
+			mv88e1240@7 {
+				reg = <0x7>;
+			};
+			mv88e1240@8 {
+				reg = <0x8>;
+			};
+			mv88e1240@9 {
+				reg = <0x9>;
+			};
+			mv88e1240@a {
+				reg = <0xa>;
+			};
+			mv88e1240@b {
+				reg = <0xb>;
+			};
+			mv88e1240@c {
+				reg = <0xc>;
+			};
+			mv88e1240@d {
+				reg = <0xd>;
+			};
+			mv88e1240@e {
+				reg = <0xe>;
+			};
+			mv88e1240@f {
+				reg = <0xf>;
+			};
+			mv88e1240@10 {
+				reg = <0x10>;
+			};
+			mv88e1240@11 {
+				reg = <0x11>;
+			};
+			mv88e1240@12 {
+				reg = <0x12>;
+			};
+			mv88e1240@13 {
+				reg = <0x13>;
+			};
+			mv88e1240@14 {
+				reg = <0x14>;
+			};
+			mv88e1240@15 {
+				reg = <0x15>;
+			};
+			mv88e1240@16 {
+				reg = <0x16>;
+			};
+			mv88e1240@17 {
+				reg = <0x17>;
+			};
+			mv88e1240@18 {
+				reg = <0x18>;
+			};
+			mv88e1240@19 {
+				reg = <0x19>;
+			};
+			mv88e1240@1a {
+				reg = <0x1a>;
+			};
+			mv88e1240@1b {
+				reg = <0x1b>;
+			};
+			mv88e1240@1c {
+				reg = <0x1c>;
+			};
+			mv88e1240@1d {
+				reg = <0x1d>;
+			};
+			mv88e1240@1e {
+				reg = <0x1e>;
+			};
+			mv88e1240@1f {
+				reg = <0x1f>;
+			};
+		};
+
+		MDIO1: mdio1 {
+			compatible = "virtual,mdio-gpio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpios = < /*MDC*/ &gpio0 25 0
+				  /*MDIO*/ &gpio1 13 0>;
+			mv88e1240@0 {
+				reg = <0x0>;
+			};
+			mv88e1240@1 {
+				reg = <0x1>;
+			};
+			mv88e1240@2 {
+				reg = <0x2>;
+			};
+			mv88e1240@3 {
+				reg = <0x3>;
+			};
+			mv88e1240@4 {
+				reg = <0x4>;
+			};
+			mv88e1240@5 {
+				reg = <0x5>;
+			};
+			mv88e1240@6 {
+				reg = <0x6>;
+			};
+			mv88e1240@7 {
+				reg = <0x7>;
+			};
+			mv88e1240@8 {
+				reg = <0x8>;
+			};
+			mv88e1240@9 {
+				reg = <0x9>;
+			};
+			mv88e1240@a {
+				reg = <0xa>;
+			};
+			mv88e1240@b {
+				reg = <0xb>;
+			};
+			mv88e1240@c {
+				reg = <0xc>;
+			};
+			mv88e1240@d {
+				reg = <0xd>;
+			};
+			mv88e1240@e {
+				reg = <0xe>;
+			};
+			mv88e1240@f {
+				reg = <0xf>;
+			};
+			mv88e1240@10 {
+				reg = <0x10>;
+			};
+			mv88e1240@11 {
+				reg = <0x11>;
+			};
+			mv88e1240@12 {
+				reg = <0x12>;
+			};
+			mv88e1240@13 {
+				reg = <0x13>;
+			};
+			mv88e1240@14 {
+				reg = <0x14>;
+			};
+			mv88e1240@15 {
+				reg = <0x15>;
+			};
+			mv88e1240@16 {
+				reg = <0x16>;
+			};
+			mv88e1240@17 {
+				reg = <0x17>;
+			};
+			mv88e1240@18 {
+				reg = <0x18>;
+			};
+			mv88e1240@19 {
+				reg = <0x19>;
+			};
+			mv88e1240@1a {
+				reg = <0x1a>;
+			};
+			mv88e1240@1b {
+				reg = <0x1b>;
+			};
+			mv88e1240@1c {
+				reg = <0x1c>;
+			};
+			mv88e1240@1d {
+				reg = <0x1d>;
+			};
+			mv88e1240@1e {
+				reg = <0x1e>;
+			};
+			mv88e1240@1f {
+				reg = <0x1f>;
+			};
+		};
+
+		MDIO2: mdio2 {
+			compatible = "virtual,mdio-gpio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpios = < /*MDC*/ &gpio1 14 0
+				  /*MDIO*/ &gpio0 24 0>;
+			mv88e1240@0 {
+				reg = <0x0>;
+			};
+			mv88e1240@1 {
+				reg = <0x1>;
+			};
+			mv88e1240@2 {
+				reg = <0x2>;
+			};
+			mv88e1240@3 {
+				reg = <0x3>;
+			};
+			mv88e1240@4 {
+				reg = <0x4>;
+			};
+			mv88e1240@5 {
+				reg = <0x5>;
+			};
+			mv88e1240@6 {
+				reg = <0x6>;
+			};
+			mv88e1240@7 {
+				reg = <0x7>;
+			};
+			mv88e1240@8 {
+				reg = <0x8>;
+			};
+			mv88e1240@9 {
+				reg = <0x9>;
+			};
+			mv88e1240@a {
+				reg = <0xa>;
+			};
+			mv88e1240@b {
+				reg = <0xb>;
+			};
+			mv88e1240@c {
+				reg = <0xc>;
+			};
+			mv88e1240@d {
+				reg = <0xd>;
+			};
+			mv88e1240@e {
+				reg = <0xe>;
+			};
+			mv88e1240@f {
+				reg = <0xf>;
+			};
+			mv88e1240@10 {
+				reg = <0x10>;
+			};
+			mv88e1240@11 {
+				reg = <0x11>;
+			};
+			mv88e1240@12 {
+				reg = <0x12>;
+			};
+			mv88e1240@13 {
+				reg = <0x13>;
+			};
+			mv88e1240@14 {
+				reg = <0x14>;
+			};
+			mv88e1240@15 {
+				reg = <0x15>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		finder_led {
+			label = "finder-led";
+			gpios = <&PCA22 25 0>;
+		};
+
+		status_led {
+			label = "status-led";
+			gpios = <&gpio0 29 0>;
+		};
+	};
+};
diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index 63442df..84e0dbd 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -159,7 +159,7 @@
 &cpm_comphy {
 	phy0 {
 		phy-type = <PHY_TYPE_SGMII2>;
-		phy-speed = <PHY_SPEED_3_125G>;
+		phy-speed = <PHY_SPEED_1_25G>;
 	};
 
 	phy1 {
@@ -209,3 +209,28 @@
 	no-1-8-v;
 	non-removable;
 };
+
+&cpm_mdio {
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&cpm_ethernet {
+	status = "okay";
+};
+
+&cpm_eth1 {
+	status = "okay";
+	phy = <&phy0>;
+	phy-mode = "sgmii";
+};
+
+&cpm_eth2 {
+	status = "okay";
+	phy = <&phy1>;
+	phy-mode = "rgmii-id";
+};
diff --git a/arch/arm/dts/armada-7040.dtsi b/arch/arm/dts/armada-7040.dtsi
index 78d995d..b5be0c4 100644
--- a/arch/arm/dts/armada-7040.dtsi
+++ b/arch/arm/dts/armada-7040.dtsi
@@ -45,6 +45,7 @@
  * one CP110.
  */
 
+#include <dt-bindings/gpio/gpio.h>
 #include "armada-ap806-quad.dtsi"
 #include "armada-cp110-master.dtsi"
 
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index 40def9d..f1f196f 100644
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -283,3 +283,19 @@
 &cps_utmi0 {
 	status = "okay";
 };
+
+&cpm_mdio {
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&cpm_ethernet {
+	status = "okay";
+};
+
+&cpm_eth2 {
+	status = "okay";
+	phy = <&phy1>;
+	phy-mode = "rgmii-id";
+};
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
new file mode 100644
index 0000000..e42b092
--- /dev/null
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -0,0 +1,293 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#include "armada-8040.dtsi" /* include SoC device tree */
+
+/ {
+	model = "MACCHIATOBin-8040";
+	compatible = "marvell,armada8040-mcbin",
+		     "marvell,armada8040";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		i2c0 = &cpm_i2c0;
+		i2c1 = &cpm_i2c1;
+		spi0 = &cps_spi1;
+		gpio0 = &ap_gpio0;
+		gpio1 = &cpm_gpio0;
+		gpio2 = &cpm_gpio1;
+	};
+
+	memory@00000000 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	simple-bus {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb3h0_vbus: usb3-vbus0 {
+			compatible = "regulator-fixed";
+			pinctrl-names = "default";
+			pinctrl-0 = <&cpm_xhci_vbus_pins>;
+			regulator-name = "reg-usb3h0-vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			startup-delay-us = <500000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
+		};
+	};
+};
+
+/* Accessible over the mini-USB CON9 connector on the main board */
+&uart0 {
+	status = "okay";
+};
+
+&ap_pinctl {
+	/*
+	 * MPP Bus:
+	 * eMMC [0-10]
+	 * UART0 [11,19]
+	 */
+		  /* 0 1 2 3 4 5 6 7 8 9 */
+	pin-func = < 1 1 1 1 1 1 1 1 1 1
+		     1 3 0 0 0 0 0 0 0 3 >;
+};
+
+/* on-board eMMC */
+&ap_sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ap_emmc_pins>;
+	bus-width= <8>;
+	status = "okay";
+};
+
+&cpm_pinctl {
+	/*
+	 * MPP Bus:
+	 * [0-31] = 0xff: Keep default CP0_shared_pins:
+	 * [11] CLKOUT_MPP_11 (out)
+	 * [23] LINK_RD_IN_CP2CP (in)
+	 * [25] CLKOUT_MPP_25 (out)
+	 * [29] AVS_FB_IN_CP2CP (in)
+	 * [32,34] SMI
+	 * [33]    MSS power down
+	 * [35-38] CP0 I2C1 and I2C0
+	 * [39] MSS CKE Enable
+	 * [40,41] CP0 UART1 TX/RX
+	 * [42,43] XSMI (controls two 10G phys)
+	 * [47] USB VBUS EN
+	 * [48] FAN PWM
+	 * [49] 10G port 1 interrupt
+	 * [50] 10G port 0 interrupt
+	 * [51] 2.5G SFP TX fault
+	 * [52] PCIe reset out
+	 * [53] 2.5G SFP mode
+	 * [54] 2.5G SFP LOS
+	 * [55] Micro SD card detect
+	 * [56-61] Micro SD
+	 * [62] CP1 KR SFP FAULT
+	 */
+		/*   0    1    2    3    4    5    6    7    8    9 */
+	pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0    7    0xa  7    2    2    2    2    0xa
+		     7    7    8    8    0    0    0    0    0    0
+		     0    0    0    0    0    0    0xe  0xe  0xe  0xe
+		     0xe  0xe  0 >;
+
+	cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
+		marvell,pins = < 47 >;
+		marvell,function = <0>;
+	};
+
+	cpm_pcie_reset_pins: cpm-pcie-reset-pins {
+		marvell,pins = < 52 >;
+		marvell,function = <0>;
+	};
+};
+
+/* uSD slot */
+&cpm_sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_sdhci_pins>;
+	bus-width= <4>;
+	status = "okay";
+};
+
+/* PCIe x4 */
+&cpm_pcie0 {
+	num-lanes = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_pcie_reset_pins>;
+	marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */
+	status = "okay";
+};
+
+&cpm_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_i2c0_pins>;
+	status = "okay";
+	clock-frequency = <100000>;
+};
+
+&cpm_i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_i2c1_pins>;
+	status = "okay";
+	clock-frequency = <100000>;
+};
+
+&cpm_sata0 {
+	status = "okay";
+};
+
+&cpm_comphy {
+	/*
+	 * CP0 Serdes Configuration:
+	 * Lane 0: PCIe0 (x4)
+	 * Lane 1: PCIe0 (x4)
+	 * Lane 2: PCIe0 (x4)
+	 * Lane 3: PCIe0 (x4)
+	 * Lane 4: KR (10G)
+	 * Lane 5: SATA1
+	 */
+	phy0 {
+		phy-type = <PHY_TYPE_PEX0>;
+	};
+	phy1 {
+		phy-type = <PHY_TYPE_PEX0>;
+	};
+	phy2 {
+		phy-type = <PHY_TYPE_PEX0>;
+	};
+	phy3 {
+		phy-type = <PHY_TYPE_PEX0>;
+	};
+	phy4 {
+		phy-type = <PHY_TYPE_KR>;
+	};
+	phy5 {
+		phy-type = <PHY_TYPE_SATA1>;
+	};
+};
+
+&cps_sata0 {
+	status = "okay";
+};
+
+&cps_usb3_0 {
+	vbus-supply = <&reg_usb3h0_vbus>;
+	status = "okay";
+};
+
+&cps_utmi0 {
+	status = "okay";
+};
+
+&cps_pinctl {
+	/*
+	 * MPP Bus:
+	 * [0-5] TDM
+	 * [6,7] CP1_UART 0
+	 * [8]   CP1 10G SFP LOS
+	 * [9]   CP1 10G PHY RESET
+	 * [10]  CP1 10G SFP TX Disable
+	 * [11]  CP1 10G SFP Mode
+	 * [12]  SPI1 CS1n
+	 * [13]  SPI1 MISO (TDM and SPI ROM shared)
+	 * [14]  SPI1 CS0n
+	 * [15]  SPI1 MOSI (TDM and SPI ROM shared)
+	 * [16]  SPI1 CLK (TDM and SPI ROM shared)
+	 * [24]  CP1 2.5G SFP TX Disable
+	 * [26]  CP0 10G SFP TX Fault
+	 * [27]  CP0 10G SFP Mode
+	 * [28]  CP0 10G SFP LOS
+	 * [29]  CP0 10G SFP TX Disable
+	 * [30]  USB Over current indication
+	 * [31]  10G Port 0 phy reset
+	 * [32-62] = 0xff: Keep default CP1_shared_pins:
+	 */
+		/*   0    1    2    3    4    5    6    7    8    9 */
+	pin-func = < 0x4  0x4  0x4  0x4  0x4  0x4  0x8  0x8  0x0  0x0
+		     0x0  0x0  0x3  0x3  0x3  0x3  0x3  0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0x0  0xff 0x0  0x0  0x0 0x0
+		     0x0  0x0  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff>;
+};
+
+&cps_spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cps_spi1_pins>;
+	status = "okay";
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "U-Boot";
+				reg = <0 0x200000>;
+			};
+			partition@400000 {
+				label = "Filesystem";
+				reg = <0x200000 0xce0000>;
+			};
+		};
+	};
+};
+
+&cps_comphy {
+	/*
+	 * CP1 Serdes Configuration:
+	 * Lane 0: SGMII2
+	 * Lane 1: SATA 0
+	 * Lane 2: USB HOST 0
+	 * Lane 3: SATA1
+	 * Lane 4: KR (10G)
+	 * Lane 5: SGMII3
+	 */
+	phy0 {
+		phy-type = <PHY_TYPE_SGMII2>;
+		phy-speed = <PHY_SPEED_1_25G>;
+	};
+	phy1 {
+		phy-type = <PHY_TYPE_SATA0>;
+	};
+	phy2 {
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+	};
+	phy3 {
+		phy-type = <PHY_TYPE_SATA1>;
+	};
+	phy4 {
+		phy-type = <PHY_TYPE_KR>;
+	};
+	phy5 {
+		phy-type = <PHY_TYPE_SGMII3>;
+	};
+};
diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi
index 9c1b28c..96cc112 100644
--- a/arch/arm/dts/armada-8040.dtsi
+++ b/arch/arm/dts/armada-8040.dtsi
@@ -45,6 +45,7 @@
  * two CP110.
  */
 
+#include <dt-bindings/gpio/gpio.h>
 #include "armada-ap806-quad.dtsi"
 #include "armada-cp110-master.dtsi"
 #include "armada-cp110-slave.dtsi"
diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi
index 3042cb1..e0d3016 100644
--- a/arch/arm/dts/armada-ap806.dtsi
+++ b/arch/arm/dts/armada-ap806.dtsi
@@ -158,6 +158,14 @@
 				};
 			};
 
+			ap_gpio0: gpio@6F5040 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x6F5040 0x40>;
+				ngpios = <20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
 			xor@400000 {
 				compatible = "marvell,mv-xor-v2";
 				reg = <0x400000 0x1000>,
diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi
index 661a696..229046f 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -61,6 +61,43 @@
 			interrupt-parent = <&gic>;
 			ranges = <0x0 0x0 0xf2000000 0x2000000>;
 
+			cpm_ethernet: ethernet@0 {
+				compatible = "marvell,armada-7k-pp22";
+				reg = <0x0 0x100000>, <0x129000 0xb000>;
+				clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
+				clock-names = "pp_clk", "gop_clk", "mg_clk";
+				status = "disabled";
+				dma-coherent;
+
+				cpm_eth0: eth0 {
+					interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+					port-id = <0>;
+					gop-port-id = <0>;
+					status = "disabled";
+				};
+
+				cpm_eth1: eth1 {
+					interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+					port-id = <1>;
+					gop-port-id = <2>;
+					status = "disabled";
+				};
+
+				cpm_eth2: eth2 {
+					interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+					port-id = <2>;
+					gop-port-id = <3>;
+					status = "disabled";
+				};
+			};
+
+			cpm_mdio: mdio@12a200 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "marvell,orion-mdio";
+				reg = <0x12a200 0x10>;
+			};
+
 			cpm_syscon0: system-controller@440000 {
 				compatible = "marvell,cp110-system-controller0",
 					     "syscon";
@@ -94,6 +131,10 @@
 					marvell,pins = < 37 38 >;
 					marvell,function = <2>;
 				};
+				cpm_i2c1_pins: cpm-i2c-pins-1 {
+					marvell,pins = < 35 36 >;
+					marvell,function = <2>;
+				};
 				cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 {
 					marvell,pins = < 44 45 46 47 48 49 50 51
 							 52 53 54 55 >;
@@ -113,6 +154,24 @@
 				};
 			};
 
+			cpm_gpio0: gpio@440100 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x440100 0x40>;
+				ngpios = <32>;
+				gpiobase = <20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			cpm_gpio1: gpio@440140 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x440140 0x40>;
+				ngpios = <31>;
+				gpiobase = <52>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
 			cpm_sata0: sata@540000 {
 				compatible = "marvell,armada-8k-ahci";
 				reg = <0x540000 0x30000>;
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi
index 92ef55c..5876391 100644
--- a/arch/arm/dts/armada-cp110-slave.dtsi
+++ b/arch/arm/dts/armada-cp110-slave.dtsi
@@ -61,6 +61,43 @@
 			interrupt-parent = <&gic>;
 			ranges = <0x0 0x0 0xf4000000 0x2000000>;
 
+			cps_ethernet: ethernet@0 {
+				compatible = "marvell,armada-7k-pp22";
+				reg = <0x0 0x100000>, <0x129000 0xb000>;
+				clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
+				clock-names = "pp_clk", "gop_clk", "mg_clk";
+				status = "disabled";
+				dma-coherent;
+
+				cps_eth0: eth0 {
+					interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+					port-id = <0>;
+					gop-port-id = <0>;
+					status = "disabled";
+				};
+
+				cps_eth1: eth1 {
+					interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+					port-id = <1>;
+					gop-port-id = <2>;
+					status = "disabled";
+				};
+
+				cps_eth2: eth2 {
+					interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+					port-id = <2>;
+					gop-port-id = <3>;
+					status = "disabled";
+				};
+			};
+
+			cps_mdio: mdio@12a200 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "marvell,orion-mdio";
+				reg = <0x12a200 0x10>;
+			};
+
 			cps_syscon0: system-controller@440000 {
 				compatible = "marvell,cp110-system-controller0",
 					     "syscon";
@@ -100,6 +137,24 @@
 				};
 			};
 
+			cps_gpio0: gpio@440100 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x440100 0x40>;
+				ngpios = <32>;
+				gpiobase = <20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			cps_gpio1: gpio@440140 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x440140 0x40>;
+				ngpios = <31>;
+				gpiobase = <52>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
 			cps_sata0: sata@540000 {
 				compatible = "marvell,armada-8k-ahci";
 				reg = <0x540000 0x30000>;
diff --git a/arch/arm/dts/axp209.dtsi b/arch/arm/dts/axp209.dtsi
index afbe89c..675bb0f 100644
--- a/arch/arm/dts/axp209.dtsi
+++ b/arch/arm/dts/axp209.dtsi
@@ -53,6 +53,12 @@
 	interrupt-controller;
 	#interrupt-cells = <1>;
 
+	axp_gpio: gpio {
+		compatible = "x-powers,axp209-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	regulators {
 		/* Default work frequency for buck regulators */
 		x-powers,dcdc-freq = <1500>;
diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts
index 69c0605..ac422e4 100644
--- a/arch/arm/dts/exynos4210-trats.dts
+++ b/arch/arm/dts/exynos4210-trats.dts
@@ -23,6 +23,7 @@
 		console = "/serial@13820000";
 		mmc0 = "/sdhci@12510000";
 		mmc2 = "/sdhci@12530000";
+		i2c8 = &i2c_fg;
 	};
 
 	fimd@11c00000 {
@@ -113,6 +114,14 @@
 	dwmmc@12550000 {
 		status = "disabled";
 	};
+
+	i2c_fg: fuel-gauge {
+		compatible = "i2c-gpio";
+		gpios = <&gpy4 1 0>,	/* sda */
+			<&gpy4 0 0>;	/* scl */
+		i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+		status = "okay";
+	};
 };
 
 &i2c_5 {
diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts
index 188cb93..8710747 100644
--- a/arch/arm/dts/exynos4412-odroid.dts
+++ b/arch/arm/dts/exynos4412-odroid.dts
@@ -213,7 +213,7 @@
 
 				buck8_reg: BUCK8 {
 					regulator-name = "VCC_P3V3_2.85V";
-					regulator-min-microvolt = <2850000>;
+					regulator-min-microvolt = <750000>;
 					regulator-max-microvolt = <3300000>;
 				};
 			};
diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts
index 1fbcf89..fd9e48c 100644
--- a/arch/arm/dts/exynos4412-trats2.dts
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -27,6 +27,8 @@
 		i2c5 = "/i2c@138b0000";
 		i2c6 = "/i2c@138c0000";
 		i2c7 = "/i2c@138d0000";
+		i2c8 = &i2c_fg;
+		i2c9 = &i2c_max77693;
 		serial0 = "/serial@13800000";
 		console = "/serial@13820000";
 		mmc0 = "/sdhci@12510000";
@@ -34,6 +36,22 @@
 		mshc0 = "/dwmmc@12550000";
 	};
 
+	i2c_fg: fuel-gauge {
+		compatible = "i2c-gpio";
+		gpios = <&gpf1 5 0>,	/* sda */
+			<&gpf1 4 0>;	/* scl */
+		i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+		status = "okay";
+	};
+
+	i2c_max77693: max77693 {
+		compatible = "i2c-gpio";
+		gpio = <&gpm2 0 0>,	/* sda */
+		       <&gpm2 1 0>;	/* scl */
+		i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+		status = "okay";
+	};
+
 	i2c@138d0000 {
 		samsung,i2c-sda-delay = <100>;
 		samsung,i2c-slave-addr = <0x10>;
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index ed5ea54..23b3cec 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -114,7 +114,7 @@
 			reg = <0x0 0x1550000 0x0 0x10000>,
 				<0x0 0x40000000 0x0 0x4000000>;
 			reg-names = "QuadSPI", "QuadSPI-memory";
-			num-cs = <2>;
+			num-cs = <1>;
 			big-endian;
 			status = "disabled";
 		};
diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi
new file mode 100644
index 0000000..6305f57
--- /dev/null
+++ b/arch/arm/dts/omap5-u-boot.dtsi
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "dra7.dtsi"
+ */
+
+/{
+	ocp {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+};
+
+&uart3 {
+	u-boot,dm-pre-reloc;
+};
+
+&mmc1 {
+	u-boot,dm-pre-reloc;
+};
+
+&mmc2 {
+	u-boot,dm-pre-reloc;
+};
+
+&l4_cfg {
+	u-boot,dm-pre-reloc;
+};
+
+&scm {
+	u-boot,dm-pre-reloc;
+};
+
+&scm_conf {
+	u-boot,dm-pre-reloc;
+};
+
+&qspi {
+	u-boot,dm-pre-reloc;
+
+	m25p80@0 {
+		u-boot,dm-pre-reloc;
+	};
+};
diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts
new file mode 100644
index 0000000..5f5b5e9
--- /dev/null
+++ b/arch/arm/dts/rk3188-radxarock.dts
@@ -0,0 +1,382 @@
+/*
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "rk3188.dtsi"
+
+/ {
+	model = "Radxa Rock";
+	compatible = "radxa,rock", "rockchip,rk3188";
+
+	chosen {
+/*		stdout-path = &uart2; */
+		stdout-path = "serial2:115200n8";
+	};
+
+	config {
+		u-boot,dm-pre-reloc;
+		u-boot,boot-led = "rock:red:power";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x60000000 0x80000000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+
+		power {
+			gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			label = "GPIO Key Power";
+			linux,input-type = <1>;
+			wakeup-source;
+			debounce-interval = <100>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		green {
+			label = "rock:green:user1";
+			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		blue {
+			label = "rock:blue:user2";
+			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		sleep {
+			label = "rock:red:power";
+			gpios = <&gpio0 15 0>;
+			default-state = "off";
+		};
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "SPDIF";
+
+		simple-audio-card,dai-link@1 {  /* S/PDIF - S/PDIF */
+			cpu { sound-dai = <&spdif>; };
+			codec { sound-dai = <&spdif_out>; };
+		};
+	};
+
+	spdif_out: spdif-out {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+	ir_recv: gpio-ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio0 10 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ir_recv_pin>;
+	};
+
+	vcc_otg: usb-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&otg_vbus_drv>;
+		regulator-name = "otg-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_sd0: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "sdmmc-supply";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio3 1 GPIO_ACTIVE_LOW>;
+		startup-delay-us = <100000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_host: usb-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&host_vbus_drv>;
+		regulator-name = "host-pwr";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vsys: vsys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vsys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+	};
+};
+
+&dmc {
+	rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6
+		0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4
+		0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0
+		0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0
+		0x4 0x0>;
+	rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00
+		0x220 0x40 0x0 0x0>;
+	rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>;
+};
+
+&emac {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+
+	phy = <&phy0>;
+	phy-supply = <&vcc_rmii>;
+
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&cpu0 {
+	cpu0-supply = <&vdd_arm>;
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtc_int>;
+		#clock-cells = <0>;
+		clock-output-names = "xin32k";
+	};
+
+	act8846: act8846@5a {
+		compatible = "active-semi,act8846";
+		reg = <0x5a>;
+		status = "okay";
+		system-power-controller;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&act8846_dvs0_ctl>;
+
+		vp1-supply = <&vsys>;
+		vp2-supply = <&vsys>;
+		vp3-supply = <&vsys>;
+		vp4-supply = <&vsys>;
+		inl1-supply = <&vcc_io>;
+		inl2-supply = <&vsys>;
+		inl3-supply = <&vsys>;
+
+		regulators {
+			vcc_ddr: REG1 {
+				regulator-name = "VCC_DDR";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+			};
+
+			vdd_log: REG2 {
+				regulator-name = "VDD_LOG";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			vdd_arm: REG3 {
+				regulator-name = "VDD_ARM";
+				regulator-min-microvolt = <875000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-always-on;
+			};
+
+			vcc_io: REG4 {
+				regulator-name = "VCC_IO";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vdd_10: REG5 {
+				regulator-name = "VDD_10";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			vdd_hdmi: REG6 {
+				regulator-name = "VDD_HDMI";
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-always-on;
+			};
+
+			vcc18: REG7 {
+				regulator-name = "VCC_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			vcca_33: REG8 {
+				regulator-name = "VCCA_33";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vcc_rmii: REG9 {
+				regulator-name = "VCC_RMII";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vccio_wl: REG10 {
+				regulator-name = "VCCIO_WL";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vcc_18: REG11 {
+				regulator-name = "VCC18_IO";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			vcc28: REG12 {
+				regulator-name = "VCC_28";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&mmc0 {
+	num-slots = <1>;
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
+	vmmc-supply = <&vcc_sd0>;
+
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&pwm3 {
+	status = "okay";
+};
+
+&pinctrl {
+	pcfg_output_low: pcfg-output-low {
+		output-low;
+	};
+
+	act8846 {
+		act8846_dvs0_ctl: act8846-dvs0-ctl {
+			rockchip,pins = <RK_GPIO3 27 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+	};
+
+	hym8563 {
+		rtc_int: rtc-int {
+			rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	lan8720a  {
+		phy_int: phy-int {
+			rockchip,pins = <RK_GPIO3 26 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	ir-receiver {
+		ir_recv_pin: ir-recv-pin {
+			rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		host_vbus_drv: host-vbus-drv {
+			rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		otg_vbus_drv: otg-vbus-drv {
+			rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&spdif {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+	u-boot,dm-spl;
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};
+
+&usb_host {
+	status = "okay";
+};
+
+&usb_otg {
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts
index 97568a3..59ff8bc 100644
--- a/arch/arm/dts/rk3288-firefly.dts
+++ b/arch/arm/dts/rk3288-firefly.dts
@@ -50,6 +50,11 @@
 			rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
 	};
+	usb_host {
+		host_vbus_drv: host-vbus-drv {
+			rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
 };
 
 &pwm1 {
@@ -61,6 +66,11 @@
 	reg-shift = <2>;
 };
 
+&usb_host1 {
+	vbus-supply = <&vcc_host_5v>;
+	status = "okay";
+};
+
 &sdmmc {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/rk3288-miqi.dts b/arch/arm/dts/rk3288-miqi.dts
new file mode 100644
index 0000000..7b92caf
--- /dev/null
+++ b/arch/arm/dts/rk3288-miqi.dts
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3288-miqi.dtsi"
+
+/ {
+	model = "mqmaker MiQi";
+	compatible = "mqmaker,miqi", "rockchip,rk3288";
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+};
+
+&dmc {
+	rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+		0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+		0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+		0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+		0x5 0x0>;
+	rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+		0xa60 0x40 0x10 0x0>;
+	rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+};
+
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+	u-boot,dm-pre-reloc;
+	reg-shift = <2>;
+};
+
+&sdmmc {
+	u-boot,dm-pre-reloc;
+};
+
+&emmc {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi
new file mode 100644
index 0000000..47dc0f9
--- /dev/null
+++ b/arch/arm/dts/rk3288-miqi.dtsi
@@ -0,0 +1,423 @@
+/*
+ * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ X11
+ */
+
+#include "rk3288.dtsi"
+
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0 0x80000000>;
+	};
+
+	ext_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+		clock-output-names = "ext_gmac";
+	};
+
+	io_domains: io-domains {
+		compatible = "rockchip,rk3288-io-voltage-domain";
+		rockchip,grf = <&grf>;
+
+		audio-supply = <&vcca_33>;
+		flash0-supply = <&vcc_flash>;
+		flash1-supply = <&vcc_lan>;
+		gpio30-supply = <&vcc_io>;
+		gpio1830-supply = <&vcc_io>;
+		lcdc-supply = <&vcc_io>;
+		sdcard-supply = <&vccio_sd>;
+		wifi-supply = <&vcc_18>;
+	};
+
+
+	leds {
+		u-boot,dm-pre-reloc;
+		compatible = "gpio-leds";
+
+		work {
+			u-boot,dm-pre-reloc;
+			gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
+			label = "miqi:green:user";
+			linux,default-trigger = "default-on";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_ctl>;
+		};
+	};
+
+	vcc_flash: flash-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_flash";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_host: usb-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&host_vbus_drv>;
+		regulator-name = "vcc_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_sd: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_pwr>;
+		regulator-name = "vcc_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <100000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_sys: vsys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&cpu0 {
+	cpu0-supply = <&vdd_cpu>;
+};
+
+&emmc {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	disable-wp;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
+	vmmc-supply = <&vcc_io>;
+	vqmmc-supply = <&vcc_flash>;
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_MAC>;
+	assigned-clock-parents = <&ext_gmac>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rgmii";
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 1000000>;
+	snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c5>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	vdd_cpu: syr827@40 {
+		compatible = "silergy,syr827";
+		fcs,suspend-voltage-selector = <1>;
+		reg = <0x40>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <1350000>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-enable-ramp-delay = <300>;
+		regulator-ramp-delay = <8000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vdd_gpu: syr828@41 {
+		compatible = "silergy,syr828";
+		fcs,suspend-voltage-selector = <1>;
+		reg = <0x41>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <1350000>;
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	hym8563: hym8563@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+	};
+
+	act8846: act8846@5a {
+		compatible = "active-semi,act8846";
+		reg = <0x5a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_vsel>;
+		system-power-controller;
+
+		vp1-supply = <&vcc_sys>;
+		vp2-supply = <&vcc_sys>;
+		vp3-supply = <&vcc_sys>;
+		vp4-supply = <&vcc_sys>;
+		inl1-supply = <&vcc_sys>;
+		inl2-supply = <&vcc_sys>;
+		inl3-supply = <&vcc_20>;
+
+		regulators {
+			vcc_ddr: REG1 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+			};
+
+			vcc_io: REG2 {
+				regulator-name = "vcc_io";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vdd_log: REG3 {
+				regulator-name = "vdd_log";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+			};
+
+			vcc_20: REG4 {
+				regulator-name = "vcc_20";
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-always-on;
+			};
+
+			vccio_sd: REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vdd10_lcd: REG6 {
+				regulator-name = "vdd10_lcd";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			vcca_18: REG7 {
+				regulator-name = "vcca_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			vcca_33: REG8 {
+				regulator-name = "vcca_33";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vcc_lan: REG9 {
+				regulator-name = "vcc_lan";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vdd_10: REG10 {
+				regulator-name = "vdd_10";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			vcc_18: REG11 {
+				regulator-name = "vcc_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			vcc18_lcd: REG12 {
+				regulator-name = "vcc18_lcd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&pinctrl {
+	pcfg_output_high: pcfg-output-high {
+		output-high;
+	};
+
+	pcfg_output_low: pcfg-output-low {
+		output-low;
+	};
+
+	pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
+		bias-pull-up;
+		drive-strength = <12>;
+	};
+
+	act8846 {
+		pmic_int: pmic-int {
+			rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		pmic_sleep: pmic-sleep {
+			rockchip,pins = <0 0 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+
+		pmic_vsel: pmic-vsel {
+			rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+	};
+
+	gmac {
+		phy_int: phy-int {
+			rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_pmeb: phy-pmeb {
+			rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_rst: phy-rst {
+			rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+	};
+
+	leds {
+		led_ctl: led-ctl {
+			rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdmmc {
+		/*
+		 * Default drive strength isn't enough to achieve even
+		 * high-speed mode on firefly board so bump up to 12ma.
+		 */
+		sdmmc_bus4: sdmmc-bus4 {
+			rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
+					<6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
+					<6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
+					<6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+		};
+
+		sdmmc_clk: sdmmc-clk {
+			rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>;
+		};
+
+		sdmmc_cmd: sdmmc-cmd {
+			rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+		};
+
+		sdmmc_pwr: sdmmc-pwr {
+			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb_host {
+		host_vbus_drv: host-vbus-drv {
+			rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&saradc {
+	vref-supply = <&vcc_18>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	disable-wp;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <0>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};
+
+&usb_host1 {
+	vbus-supply = <&vcc_host>;
+	status = "okay";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index a959989..c3a7ca2 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -95,6 +95,7 @@
 };
 
 &dwc3_typec0 {
+	rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
@@ -107,6 +108,7 @@
 };
 
 &dwc3_typec1 {
+	rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/rk3399-puma.dts b/arch/arm/dts/rk3399-puma.dts
new file mode 100644
index 0000000..917df1e
--- /dev/null
+++ b/arch/arm/dts/rk3399-puma.dts
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+#include "rk3399-sdram-ddr3-1333.dtsi"
+
+/ {
+	model = "Theobroma Systems RK3399-Q7 SoM";
+	compatible = "tsd,puma", "rockchip,rk3399";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		u-boot,spl-boot-order = &spiflash, &sdhci, &sdmmc;
+	};
+
+	aliases {
+		spi0 = &spi1;
+		spi1 = &spi5;
+	};
+
+	vdd_center: vdd-center {
+		compatible = "pwm-regulator";
+		pwms = <&pwm3 0 25000 0>;
+		regulator-name = "vdd_center";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-init-microvolt = <950000>;
+		regulator-always-on;
+		regulator-boot-on;
+		status = "okay";
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc5v0_host: vcc5v0-host-en {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&pwm3 {
+	status = "okay";
+};
+
+&sdmmc {
+        u-boot,dm-pre-reloc;
+	bus-width = <4>;
+	fifo-mode; /* until we fix DMA in SPL */
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&dwc3_typec0 {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&dwc3_typec1 {
+	status = "okay";
+};
+
+&pinctrl {
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins =
+				<1 21 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		pmic_dvs2: pmic-dvs2 {
+			rockchip,pins =
+				<1 18 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+};
+
+&gmac {
+        phy-supply = <&vcc_phy>;
+	phy-mode = "rgmii";
+	clock_in_out = "input";
+	snps,reset-gpio = <&gpio3 16 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	tx_delay = <0x10>;
+	rx_delay = <0x10>;
+	status = "okay";
+};
+
+&spi1 {
+	u-boot,dm-pre-reloc;
+
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	spiflash: w25q32dw@0 {
+		u-boot,dm-pre-reloc;
+
+		compatible = "spi-flash";
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		spi-cpol;
+		spi-cpha;
+	};
+};
+
+&spi5 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi
new file mode 100644
index 0000000..bed236d
--- /dev/null
+++ b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi
@@ -0,0 +1,1537 @@
+/*
+ * (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+&dmc {
+        rockchip,sdram-params = <
+		0x1
+		0xa
+		0x3
+		0x2
+		0x1
+		0x0
+		0xf
+		0xf
+		1
+		0x80120e12
+		0x11030802
+		0x00000002
+		0x00006246
+		0x0000004c
+		0x00000000
+		0x1
+		0xa
+		0x3
+		0x2
+		0x1
+		0x0
+		0xf
+		0xf
+		1
+		0x80120e12
+		0x11030802
+		0x00000002
+		0x00006246
+		0x0000004c
+		0x00000000
+		666
+		3
+		2
+/*		13 */ 9
+		1
+		0x00000600
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+/*		0xaae60 */ 7
+		0x00000000
+		0x00000000
+		0x00000000
+/* 		0xaae60 */ 7
+		0x00000000
+		0x00000000
+		0x00000000
+/*		0xaae60 */ 7
+		0x00000000
+		0x00000000
+		0x01000000
+		0x00000000
+		0x00000101
+		0x00020100
+		0x000208d6
+		0x00051616
+		0x02000200
+		0x07140200
+		0x00071400
+		0x04000714
+		0x20040004
+		0x18090517
+		0x17200400
+		0x00180905
+		0x05172004
+		0x05001809
+		0x00000c04
+		0x0400b6d0
+		0x0c040505
+		0x0400b6d0
+		0x0c040505
+		0x0400b6d0
+		0x02030005
+		0x090a0900
+		0x000a090a
+		0x14000a0a
+		0x00000a0a
+		0x00010000
+		0x03131313
+		0x00090909
+		0x00000000
+		0x03010000
+		0x144800ea
+		0x144800ea
+		0x144800ea
+		0x00000000
+		0x00040004
+		0x00100004
+		0x00100010
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x02000000
+		0x020000f0
+		0x020000f0
+		0x000000f0
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000301
+		0x00000001
+		0x00000000
+		0x00000000
+		0x01000000
+		0x80104002
+		0x00040003
+		0x00040005
+		0x00030000
+		0x00050004
+		0x00000004
+		0x00040003
+		0x00040005
+		0x51200000
+		0x00002890
+		0x28905120
+		0x51200000
+		0x00002890
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x07070700
+		0x00070707
+		0x00030200
+		0x00040700
+		0x00000302
+		0x02000407
+		0x00000003
+		0x00030f04
+		0x00070004
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00010000
+		0x00010000
+		0x20040020
+		0x00200400
+		0x01000400
+		0x00000b80
+		0x00000000
+		0x00000001
+		0x00000002
+		0x0000000e
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00860000
+		0x00a70043
+		0x00a70000
+		0x00430086
+		0x000000a7
+		0x008600a7
+		0x00a70043
+		0x00a70000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00420a60
+		0x0a600010
+		0x00100042
+		0x00420a60
+		0x00000010
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00420a60
+		0x0a600010
+		0x00100042
+		0x00420a60
+		0x00000010
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x01000000
+		0x00000000
+		0x00000000
+		0x18151100
+		0x0000000c
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00020003
+		0x00400100
+		0x00000000
+		0x01000200
+		0x00000040
+		0x00020000
+		0x00400100
+		0x00000000
+		0x00000000
+		0x00000000
+		0x01010100
+		0x00000202
+		0x0a000001
+		0x01000f0f
+		0x00000000
+		0x00000000
+		0x00010003
+		0x00000c03
+		0x00000000
+		0x00000000
+		0x01000000
+		0x00010000
+		0x00000001
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00010000
+		0x06060602
+		0x01000606
+		0x00000001
+		0x03030300
+		0x03080808
+		0x03050303
+		0x03050303
+		0x00050303
+		0x00020202
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x0d000001
+		0x00010028
+		0x00010000
+		0x00000003
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00010100
+		0x01000000
+		0x00000001
+		0x00000303
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x000556aa
+		0x000aaaaa
+		0x000aa955
+		0x00055555
+		0x000b3133
+		0x0004cd33
+		0x0004cecc
+		0x000b32cc
+		0x00010300
+		0x03000100
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00ffff00
+		0x13130000
+		0x08000013
+		0x00002890
+		0x00000200
+		0x00000200
+		0x00000200
+		0x00000200
+		0x00002890
+		0x000195a0
+		0x28900609
+		0x00000200
+		0x00000200
+		0x00000200
+		0x00000200
+		0x00002890
+		0x000195a0
+		0x28900609
+		0x00000200
+		0x00000200
+		0x00000200
+		0x00000200
+		0x00002890
+		0x000195a0
+		0x02020609
+		0x03030202
+		0x00000014
+		0x00000000
+		0x00000000
+		0x00001403
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00030000
+		0x00060018
+		0x00060018
+		0x00060018
+		0x00000000
+		0x00000000
+		0x01000000
+		0x01050105
+		0x00050105
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x01000100
+		0x01010101
+		0x01000101
+		0x01000100
+		0x00010001
+		0x00010002
+		0x00020100
+		0x00000002
+		0x00000600
+		0x00000000
+		0x00005120
+		0x00002890
+		0x00005120
+		0x00002890
+		0x00005120
+		0x28902890
+		0x00000200
+		0x00000200
+		0x00000200
+		0x00000200
+		0x00002890
+		0x00000200
+		0x00000200
+		0x00000200
+		0x00000200
+		0x00002890
+		0x00000200
+		0x00000200
+		0x00000200
+		0x00000200
+		0x00010000
+		0x00000007
+		0x110f0001
+		0x3c020000
+		0x3fffffff
+		0x3c030000
+		0x1dc0ffff
+		0x3c010000
+		0x1dc0ffff
+		0x3c000000
+		0x1dc0ffff
+		0x3c300400
+		0x1dc7ffff
+		0x3c000000
+		0x00000000
+		0x3c000000
+		0x00000000
+		0x3c000000
+		0x00000000
+		0x03000101
+		0x00222222
+		0x07140007
+		0x00071400
+		0x00000014
+		0x144800ea
+		0x144800ea
+		0x144800ea
+		0x00000500
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x04040000
+		0x0d000004
+		0x00000128
+		0x00000000
+		0x00030003
+		0x00000014
+		0x00000000
+		0x00000000
+		0x06060002
+		0x06010601
+		0x08060601
+		0x02020401
+		0x00080104
+		0x00000000
+		0x00000000
+		0x03030300
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00030300
+		0x00000014
+		0x00000000
+		0x01010300
+		0x00000000
+		0x00000000
+		0x01000000
+		0x00000101
+		0x55555a5a
+		0x55555a5a
+		0x55555a5a
+		0x55555a5a
+		0x09090001
+		0x06060009
+		0x01010006
+		0x00000101
+		0x00030000
+		0x17030000
+		0x00060018
+		0x00060018
+		0x00060018
+		0x00000000
+		0x00000000
+		0x00000000
+		0x140a0000
+		0x000a000a
+		0x00000a00
+		0x010a000a
+		0x00000100
+		0x01000000
+		0x00000000
+		0x00000100
+		0x1e1a0000
+		0x10010204
+		0x07070705
+		0x20000202
+		0x00201000
+		0x00201000
+		0x04041000
+		0x0f0f0100
+		0x0001010f
+		0x004b004a
+		0x1a030000
+		0x0102041e
+		0x34000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00004200
+		0x00000010
+		0x004d4d00
+		0x00100042
+		0x4d000000
+		0x0000424d
+		0x00000010
+		0x004d4d00
+		0x00100042
+		0x4d000000
+		0x0000424d
+		0x00000010
+		0x004d4d00
+		0x00100042
+		0x4d000000
+		0x0042004d
+		0x00000010
+		0x004d4d00
+		0x00100042
+		0x4d000000
+		0x0000424d
+		0x00000010
+		0x004d4d00
+		0x00100042
+		0x4d000000
+		0x0000424d
+		0x00000010
+		0x004d4d00
+		0x00100042
+		0x4d000000
+		0x0000004d
+		0x00a700a7
+		0x050400a7
+		0x0a050909
+		0x1700b4fc
+		0x07042000
+		0x0909050c
+		0x00000a05
+		0x1700b4fc
+		0x07042000
+		0x0909050c
+		0x00000a05
+		0x1700b4fc
+		0x07042000
+		0x0200020c
+		0x02000200
+		0x02000200
+		0x02000200
+		0x02000200
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x01000300
+		0x00289000
+		0x000195a0
+		0x00002890
+		0x000195a0
+		0x00002890
+		0x000195a0
+		0x08000000
+		0x00000100
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000001
+		0x76543210
+		0x0004c008
+		0x00000055
+		0x00000000
+		0x00000000
+		0x00010000
+		0x0111ff11
+		0x0011ff11
+		0x00010300
+		0x05000100
+		0x00000001
+		0x001700c0
+		0x00cc0001
+		0x00000066
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x04080000
+		0x04080400
+		0x08000000
+		0x0c00c007
+		0x00000100
+		0x00000100
+		0x55555555
+		0xaaaaaaaa
+		0x55555555
+		0xaaaaaaaa
+		0x00005555
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00200000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x02800280
+		0x02800280
+		0x02800280
+		0x02800280
+		0x00000280
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00800000
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00550080
+		0x00000001
+		0x00000000
+		0x00000000
+		0x00000200
+		0x00000000
+		0x51313152
+		0x80013130
+		0x01000080
+		0x00100000
+		0x07054208
+		0x000f0c0f
+		0x01000140
+		0x00000c20
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x76543210
+		0x0004c008
+		0x00000055
+		0x00000000
+		0x00000000
+		0x00010000
+		0x0111ff11
+		0x0011ff11
+		0x00010300
+		0x05000100
+		0x00000001
+		0x001700c0
+		0x00cc0001
+		0x00000066
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x04080000
+		0x04080400
+		0x08000000
+		0x0c00c007
+		0x00000100
+		0x00000100
+		0x55555555
+		0xaaaaaaaa
+		0x55555555
+		0xaaaaaaaa
+		0x00005555
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00200000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x02800280
+		0x02800280
+		0x02800280
+		0x02800280
+		0x00000280
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00800000
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00550080
+		0x00000001
+		0x00000000
+		0x00000000
+		0x00000200
+		0x00000000
+		0x51313152
+		0x80013130
+		0x01000080
+		0x00100000
+		0x07054208
+		0x000f0c0f
+		0x01000140
+		0x00000c20
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x76543210
+		0x0004c008
+		0x00000055
+		0x00000000
+		0x00000000
+		0x00010000
+		0x0111ff11
+		0x0011ff11
+		0x00010300
+		0x05000100
+		0x00000001
+		0x001700c0
+		0x00cc0001
+		0x00000066
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x04080000
+		0x04080400
+		0x08000000
+		0x0c00c007
+		0x00000100
+		0x00000100
+		0x55555555
+		0xaaaaaaaa
+		0x55555555
+		0xaaaaaaaa
+		0x00005555
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00200000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x02800280
+		0x02800280
+		0x02800280
+		0x02800280
+		0x00000280
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00800000
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00550080
+		0x00000001
+		0x00000000
+		0x00000000
+		0x00000200
+		0x00000000
+		0x51313152
+		0x80013130
+		0x01000080
+		0x00100000
+		0x07054208
+		0x000f0c0f
+		0x01000140
+		0x00000c20
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x76543210
+		0x0004c008
+		0x00000055
+		0x00000000
+		0x00000000
+		0x00010000
+		0x0111ff11
+		0x0011ff11
+		0x00010300
+		0x05000100
+		0x00000001
+		0x001700c0
+		0x00cc0001
+		0x00000066
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x04080000
+		0x04080400
+		0x08000000
+		0x0c00c007
+		0x00000100
+		0x00000100
+		0x55555555
+		0xaaaaaaaa
+		0x55555555
+		0xaaaaaaaa
+		0x00005555
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00200000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x02800280
+		0x02800280
+		0x02800280
+		0x02800280
+		0x00000280
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00800000
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00800080
+		0x00550080
+		0x00000001
+		0x00000000
+		0x00000000
+		0x00000200
+		0x00000000
+		0x51313152
+		0x80013130
+		0x01000080
+		0x00100000
+		0x07054208
+		0x000f0c0f
+		0x01000140
+		0x00000c20
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00800000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00400320
+		0x00000040
+		0x00dcba98
+		0x00000000
+		0x00dcba98
+		0x01000000
+		0x00020003
+		0x00000000
+		0x00000000
+		0x00000000
+		0x0000002a
+		0x00000015
+		0x00000015
+		0x0000002a
+		0x00000033
+		0x0000000c
+		0x0000000c
+		0x00000033
+		0x0a418820
+		0x103f0000
+		0x0000003f
+		0x00030055
+		0x03000300
+		0x03000300
+		0x00000300
+		0x42080010
+		0x00000003
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00800000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00400320
+		0x00000040
+		0x00000000
+		0x00000000
+		0x00000000
+		0x01000000
+		0x00020003
+		0x00000000
+		0x00000000
+		0x00000000
+		0x0000002a
+		0x00000015
+		0x00000015
+		0x0000002a
+		0x00000033
+		0x0000000c
+		0x0000000c
+		0x00000033
+		0x16a4a0e6
+		0x103f0000
+		0x0000003f
+		0x00030055
+		0x03000300
+		0x03000300
+		0x00000300
+		0x42080010
+		0x00000003
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00800000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00400320
+		0x00000040
+		0x00000000
+		0x00000000
+		0x00000000
+		0x01000000
+		0x00020003
+		0x00000000
+		0x00000000
+		0x00000000
+		0x0000002a
+		0x00000015
+		0x00000015
+		0x0000002a
+		0x00000033
+		0x0000000c
+		0x0000000c
+		0x00000033
+		0x1ee6b16a
+		0x103f0000
+		0x0000003f
+		0x00030055
+		0x03000300
+		0x03000300
+		0x00000300
+		0x42080010
+		0x00000003
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000001
+		0x00000000
+		0x01000005
+		0x04000f00
+		0x00020040
+		0x00020055
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00010100
+		0x00000601
+		0x00000000
+		0x00006400
+		0x01221102
+		0x00000000
+		0x00031f00
+		0x031f031f
+		0x031f031f
+		0x00030003
+		0x03000300
+		0x00000300
+		0x01221102
+		0x00000000
+		0x00000000
+		0x03020000
+		0x00000001
+		0x00008011
+		0x00000011
+		0x00000440
+		0x00000040
+		0x00004011
+		0x00004011
+		0x00004410
+		0x00004410
+		0x00004410
+		0x00004410
+		0x00004410
+		0x00004011
+		0x00004410
+		0x00004011
+		0x00004410
+		0x00004011
+		0x00004410
+		0x00000000
+		0x00000000
+		0x00000000
+		0x04000000
+		0x00000000
+		0x00000000
+		0x00000508
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0x00000000
+		0xe4000000
+		0x00000000
+		0x00000000
+		0x01010000
+		0x00000000
+	>;
+};
+
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 456fdb6..dbe55f2 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -239,7 +239,6 @@
 		compatible = "rockchip,rk3399-xhci";
 		reg = <0x0 0xfe800000 0x0 0x100000>;
 		status = "disabled";
-		rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
 		snps,dis-enblslpm-quirk;
 		snps,phyif-utmi-bits = <16>;
 		snps,dis-u2-freeclk-exists-quirk;
@@ -261,7 +260,6 @@
 		compatible = "rockchip,rk3399-xhci";
 		reg = <0x0 0xfe900000 0x0 0x100000>;
 		status = "disabled";
-		rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 		snps,dis-enblslpm-quirk;
 		snps,phyif-utmi-bits = <16>;
 		snps,dis-u2-freeclk-exists-quirk;
@@ -600,6 +598,25 @@
 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+        gmac: eth@fe300000 {
+                compatible = "rockchip,rk3399-gmac";
+                reg = <0x0 0xfe300000 0x0 0x10000>;
+                rockchip,grf = <&grf>;
+                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
+                interrupt-names = "macirq";
+                clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
+                         <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
+                         <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
+                         <&cru PCLK_GMAC>;
+                clock-names = "stmmaceth", "mac_clk_rx",
+                              "mac_clk_tx", "clk_mac_ref",
+                              "clk_mac_refout", "aclk_mac",
+                              "pclk_mac";
+                resets = <&cru SRST_A_GMAC>;
+                reset-names = "stmmaceth";
+                status = "disabled";
+        };
+
 	spdif: spdif@ff870000 {
 		compatible = "rockchip,rk3399-spdif";
 		reg = <0x0 0xff870000 0x0 0x1000>;
@@ -865,6 +882,42 @@
 			};
 		};
 
+		gmac {
+			rgmii_pins: rgmii-pins {
+				rockchip,pins =
+					/* mac_txclk */
+					<3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
+					/* mac_rxclk */
+					<3 14 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_mdio */
+					<3 13 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_txen */
+					<3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
+					/* mac_clk */
+					<3 11 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_rxdv */
+					<3 9 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_mdc */
+					<3 8 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_rxd1 */
+					<3 7 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_rxd0 */
+					<3 6 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_txd1 */
+					<3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
+					/* mac_txd0 */
+					<3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
+					/* mac_rxd3 */
+					<3 3 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_rxd2 */
+					<3 2 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_txd3 */
+					<3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
+					/* mac_txd2 */
+					<3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
+			};
+		};
+
 		sdmmc {
 			sdmmc_bus1: sdmmc-bus1 {
 				rockchip,pins =
diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
new file mode 100644
index 0000000..de60f78
--- /dev/null
+++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun8i-h3.dtsi"
+
+/ {
+	model = "OrangePi PC 2";
+	compatible = "xunlong,orangepi-pc-2", "allwinner,sun50i-h5";
+
+	cpus {
+		cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			enable-method = "psci";
+		};
+		cpu@1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			enable-method = "psci";
+		};
+		cpu@2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			enable-method = "psci";
+		};
+		cpu@3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			enable-method = "psci";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0x40000000 0x40000000>;
+	};
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &emac;
+	};
+
+	soc {
+		reg_vcc3v3: vcc3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "vcc3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+	};
+};
+
+&gic {
+	compatible = "arm,gic-400";
+};
+
+&mmc0 {
+	compatible = "allwinner,sun50i-h5-mmc",
+		     "allwinner,sun50i-a64-mmc",
+		     "allwinner,sun5i-a13-mmc";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 5 6 0>;
+	cd-inverted;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emac_rgmii_pins>;
+	phy-mode = "rgmii";
+	phy = <&phy1>;
+	status = "okay";
+
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
diff --git a/arch/arm/dts/sun5i-gr8-chip-pro.dts b/arch/arm/dts/sun5i-gr8-chip-pro.dts
new file mode 100644
index 0000000..92a2dc6
--- /dev/null
+++ b/arch/arm/dts/sun5i-gr8-chip-pro.dts
@@ -0,0 +1,266 @@
+/*
+ * Copyright 2016 Free Electrons
+ * Copyright 2016 NextThing Co
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-gr8.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "NextThing C.H.I.P. Pro";
+	compatible = "nextthing,chip-pro", "nextthing,gr8";
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		status {
+			label = "chip-pro:white:status";
+			gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	mmc0_pwrseq: mmc0_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_reg_on_pin_chip_pro>;
+		reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */
+	};
+};
+
+&codec {
+	status = "okay";
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_a>;
+	status = "okay";
+
+	axp209: pmic@34 {
+		reg = <0x34>;
+
+		/*
+		* The interrupt is routed through the "External Fast
+		* Interrupt Request" pin (ball G13 of the module)
+		* directly to the main interrupt controller, without
+		* any other controller interfering.
+		*/
+		interrupts = <0>;
+	};
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins_a>;
+	status = "disabled";
+};
+
+&i2s0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0_mclk_pins_a>, <&i2s0_data_pins_a>;
+	status = "disabled";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>;
+	vmmc-supply = <&reg_vcc3v3>;
+	mmc-pwrseq = <&mmc0_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+&nfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
+	status = "okay";
+
+	nand@0 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0>;
+		allwinner,rb = <0>;
+		nand-ecc-mode = "hw";
+	};
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&otg_sram {
+	status = "okay";
+};
+
+&pio {
+	usb0_id_pin_chip_pro: usb0-id-pin@0 {
+		allwinner,pins = "PG2";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	wifi_reg_on_pin_chip_pro: wifi-reg-on-pin@0 {
+		allwinner,pins = "PB10";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins>;
+	status = "disabled";
+};
+
+&reg_dcdc2 {
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+	regulator-always-on;
+};
+
+&reg_dcdc3 {
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "vdd-sys";
+	regulator-always-on;
+};
+
+&reg_ldo1 {
+	regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "avcc";
+	regulator-always-on;
+};
+
+/*
+ * Both LDO3 and LDO4 are used in parallel to power up the
+ * WiFi/BT chip.
+ */
+&reg_ldo3 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi-1";
+	regulator-always-on;
+};
+
+&reg_ldo4 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi-2";
+	regulator-always-on;
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins_a>, <&uart2_cts_rts_pins_a>;
+	status = "disabled";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins_a>, <&uart3_cts_rts_pins_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	/*
+	 * The CHIP Pro doesn't have a controllable VBUS, nor does it
+	 * have any 5v rail on the board itself.
+	 *
+	 * If one wants to use it as a true OTG port, it should be
+	 * done in the baseboard, and its DT / overlay will add it.
+	 */
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb_power_supply {
+	status = "okay";
+};
+
+&usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_pin_chip_pro>;
+	usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+	usb0_vbus_power-supply = <&usb_power_supply>;
+	usb1_vbus-supply = <&reg_vcc5v0>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/sun5i-gr8.dtsi b/arch/arm/dts/sun5i-gr8.dtsi
new file mode 100644
index 0000000..ea86d4d
--- /dev/null
+++ b/arch/arm/dts/sun5i-gr8.dtsi
@@ -0,0 +1,1132 @@
+/*
+ * Copyright 2016 Mylène Josserand
+ *
+ * Mylène Josserand <mylene.josserand@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/clock/sun4i-a10-pll2.h>
+#include <dt-bindings/dma/sun4i-a10.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	interrupt-parent = <&intc>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a8";
+			reg = <0x0>;
+			clocks = <&cpu>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/*
+		 * This is a dummy clock, to be used as placeholder on
+		 * other mux clocks when a specific parent clock is not
+		 * yet implemented. It should be dropped when the driver
+		 * is complete.
+		 */
+		dummy: dummy {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <0>;
+		};
+
+		osc24M: clk@01c20050 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-osc-clk";
+			reg = <0x01c20050 0x4>;
+			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
+		};
+
+		osc3M: osc3M-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <8>;
+			clock-mult = <1>;
+			clocks = <&osc24M>;
+			clock-output-names = "osc3M";
+		};
+
+		osc32k: clk@0 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			clock-output-names = "osc32k";
+		};
+
+		pll1: clk@01c20000 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-pll1-clk";
+			reg = <0x01c20000 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll1";
+		};
+
+		pll2: clk@01c20008 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun5i-a13-pll2-clk";
+			reg = <0x01c20008 0x8>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll2-1x", "pll2-2x",
+					     "pll2-4x", "pll2-8x";
+		};
+
+		pll3: clk@01c20010 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-pll3-clk";
+			reg = <0x01c20010 0x4>;
+			clocks = <&osc3M>;
+			clock-output-names = "pll3";
+		};
+
+		pll3x2: pll3x2-clk {
+			compatible = "allwinner,sun4i-a10-pll3-2x-clk";
+			#clock-cells = <0>;
+			clock-div = <1>;
+			clock-mult = <2>;
+			clocks = <&pll3>;
+			clock-output-names = "pll3-2x";
+		};
+
+		pll4: clk@01c20018 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-pll1-clk";
+			reg = <0x01c20018 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll4";
+		};
+
+		pll5: clk@01c20020 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-pll5-clk";
+			reg = <0x01c20020 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll5_ddr", "pll5_other";
+		};
+
+		pll6: clk@01c20028 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-pll6-clk";
+			reg = <0x01c20028 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll6_sata", "pll6_other", "pll6";
+		};
+
+		pll7: clk@01c20030 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-pll3-clk";
+			reg = <0x01c20030 0x4>;
+			clocks = <&osc3M>;
+			clock-output-names = "pll7";
+		};
+
+		pll7x2: pll7x2-clk {
+			compatible = "allwinner,sun4i-a10-pll3-2x-clk";
+			#clock-cells = <0>;
+			clock-div = <1>;
+			clock-mult = <2>;
+			clocks = <&pll7>;
+			clock-output-names = "pll7-2x";
+		};
+
+		/* dummy is 200M */
+		cpu: cpu@01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-cpu-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+			clock-output-names = "cpu";
+		};
+
+		axi: axi@01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-axi-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&cpu>;
+			clock-output-names = "axi";
+		};
+
+		ahb: ahb@01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun5i-a13-ahb-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&axi>, <&cpu>, <&pll6 1>;
+			clock-output-names = "ahb";
+			/*
+			 * Use PLL6 as parent, instead of CPU/AXI
+			 * which has rate changes due to cpufreq
+			 */
+			assigned-clocks = <&ahb>;
+			assigned-clock-parents = <&pll6 1>;
+		};
+
+		apb0: apb0@01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-apb0-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&ahb>;
+			clock-output-names = "apb0";
+		};
+
+		apb1: clk@01c20058 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-apb1-clk";
+			reg = <0x01c20058 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+			clock-output-names = "apb1";
+		};
+
+		axi_gates: clk@01c2005c {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-gates-clk";
+			reg = <0x01c2005c 0x4>;
+			clocks = <&axi>;
+			clock-indices = <0>;
+			clock-output-names = "axi_dram";
+		};
+
+		ahb_gates: clk@01c20060 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun5i-a13-ahb-gates-clk";
+			reg = <0x01c20060 0x8>;
+			clocks = <&ahb>;
+			clock-indices = <0>, <1>,
+					<2>, <5>, <6>,
+					<7>, <8>, <9>,
+					<10>, <13>,
+					<14>, <17>, <20>,
+					<21>, <22>,
+					<28>, <32>, <34>,
+					<36>, <40>, <44>,
+					<46>, <51>,
+					<52>;
+			clock-output-names = "ahb_usbotg", "ahb_ehci",
+					     "ahb_ohci", "ahb_ss", "ahb_dma",
+					     "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+					     "ahb_mmc2", "ahb_nand",
+					     "ahb_sdram", "ahb_emac", "ahb_spi0",
+					     "ahb_spi1", "ahb_spi2",
+					     "ahb_hstimer", "ahb_ve", "ahb_tve",
+					     "ahb_lcd", "ahb_csi", "ahb_de_be",
+					     "ahb_de_fe", "ahb_iep",
+					     "ahb_mali400";
+		};
+
+		apb0_gates: clk@01c20068 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-gates-clk";
+			reg = <0x01c20068 0x4>;
+			clocks = <&apb0>;
+			clock-indices = <0>, <3>,
+					<5>, <6>;
+			clock-output-names = "apb0_codec", "apb0_i2s0",
+					     "apb0_pio", "apb0_ir";
+		};
+
+		apb1_gates: clk@01c2006c {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-gates-clk";
+			reg = <0x01c2006c 0x4>;
+			clocks = <&apb1>;
+			clock-indices = <0>, <1>,
+					<2>, <17>,
+					<18>, <19>;
+			clock-output-names = "apb1_i2c0", "apb1_i2c1",
+					     "apb1_i2c2", "apb1_uart1",
+					     "apb1_uart2", "apb1_uart3";
+		};
+
+		nand_clk: clk@01c20080 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20080 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "nand";
+		};
+
+		ms_clk: clk@01c20084 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20084 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "ms";
+		};
+
+		mmc0_clk: clk@01c20088 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-mmc-clk";
+			reg = <0x01c20088 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "mmc0",
+					     "mmc0_output",
+					     "mmc0_sample";
+		};
+
+		mmc1_clk: clk@01c2008c {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-mmc-clk";
+			reg = <0x01c2008c 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "mmc1",
+					     "mmc1_output",
+					     "mmc1_sample";
+		};
+
+		mmc2_clk: clk@01c20090 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-mmc-clk";
+			reg = <0x01c20090 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "mmc2",
+					     "mmc2_output",
+					     "mmc2_sample";
+		};
+
+		ts_clk: clk@01c20098 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20098 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "ts";
+		};
+
+		ss_clk: clk@01c2009c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c2009c 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "ss";
+		};
+
+		spi0_clk: clk@01c200a0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200a0 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "spi0";
+		};
+
+		spi1_clk: clk@01c200a4 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200a4 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "spi1";
+		};
+
+		spi2_clk: clk@01c200a8 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200a8 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "spi2";
+		};
+
+		ir0_clk: clk@01c200b0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200b0 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "ir0";
+		};
+
+		i2s0_clk: clk@01c200b8 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod1-clk";
+			reg = <0x01c200b8 0x4>;
+			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+				 <&pll2 SUN4I_A10_PLL2_4X>,
+				 <&pll2 SUN4I_A10_PLL2_2X>,
+				 <&pll2 SUN4I_A10_PLL2_1X>;
+			clock-output-names = "i2s0";
+		};
+
+		spdif_clk: clk@01c200c0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod1-clk";
+			reg = <0x01c200c0 0x4>;
+			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+				 <&pll2 SUN4I_A10_PLL2_4X>,
+				 <&pll2 SUN4I_A10_PLL2_2X>,
+				 <&pll2 SUN4I_A10_PLL2_1X>;
+			clock-output-names = "spdif";
+		};
+
+		usb_clk: clk@01c200cc {
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			compatible = "allwinner,sun5i-a13-usb-clk";
+			reg = <0x01c200cc 0x4>;
+			clocks = <&pll6 1>;
+			clock-output-names = "usb_ohci0", "usb_phy";
+		};
+
+		dram_gates: clk@01c20100 {
+			#clock-cells = <1>;
+			compatible = "nextthing,gr8-dram-gates-clk",
+				     "allwinner,sun4i-a10-gates-clk";
+			reg = <0x01c20100 0x4>;
+			clocks = <&pll5 0>;
+			clock-indices = <0>,
+					<1>,
+					<25>,
+					<26>,
+					<29>,
+					<31>;
+			clock-output-names = "dram_ve",
+					     "dram_csi",
+					     "dram_de_fe",
+					     "dram_de_be",
+					     "dram_ace",
+					     "dram_iep";
+		};
+
+		de_be_clk: clk@01c20104 {
+			#clock-cells = <0>;
+			#reset-cells = <0>;
+			compatible = "allwinner,sun4i-a10-display-clk";
+			reg = <0x01c20104 0x4>;
+			clocks = <&pll3>, <&pll7>, <&pll5 1>;
+			clock-output-names = "de-be";
+		};
+
+		de_fe_clk: clk@01c2010c {
+			#clock-cells = <0>;
+			#reset-cells = <0>;
+			compatible = "allwinner,sun4i-a10-display-clk";
+			reg = <0x01c2010c 0x4>;
+			clocks = <&pll3>, <&pll7>, <&pll5 1>;
+			clock-output-names = "de-fe";
+		};
+
+		tcon_ch0_clk: clk@01c20118 {
+			#clock-cells = <0>;
+			#reset-cells = <1>;
+			compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+			reg = <0x01c20118 0x4>;
+			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+			clock-output-names = "tcon-ch0-sclk";
+		};
+
+		tcon_ch1_clk: clk@01c2012c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+			reg = <0x01c2012c 0x4>;
+			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+			clock-output-names = "tcon-ch1-sclk";
+		};
+
+		codec_clk: clk@01c20140 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-codec-clk";
+			reg = <0x01c20140 0x4>;
+			clocks = <&pll2 SUN4I_A10_PLL2_1X>;
+			clock-output-names = "codec";
+		};
+
+		mbus_clk: clk@01c2015c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun5i-a13-mbus-clk";
+			reg = <0x01c2015c 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "mbus";
+		};
+	};
+
+	display-engine {
+		compatible = "allwinner,sun5i-a13-display-engine";
+		allwinner,pipelines = <&fe0>;
+	};
+
+	soc@01c00000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		sram-controller@01c00000 {
+			compatible = "allwinner,sun4i-a10-sram-controller";
+			reg = <0x01c00000 0x30>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			sram_a: sram@00000000 {
+				compatible = "mmio-sram";
+				reg = <0x00000000 0xc000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00000000 0xc000>;
+			};
+
+			sram_d: sram@00010000 {
+				compatible = "mmio-sram";
+				reg = <0x00010000 0x1000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00010000 0x1000>;
+
+				otg_sram: sram-section@0000 {
+					compatible = "allwinner,sun4i-a10-sram-d";
+					reg = <0x0000 0x1000>;
+					status = "disabled";
+				};
+			};
+		};
+
+		dma: dma-controller@01c02000 {
+			compatible = "allwinner,sun4i-a10-dma";
+			reg = <0x01c02000 0x1000>;
+			interrupts = <27>;
+			clocks = <&ahb_gates 6>;
+			#dma-cells = <2>;
+		};
+
+		nfc: nand@01c03000 {
+			compatible = "allwinner,sun4i-a10-nand";
+			reg = <0x01c03000 0x1000>;
+			interrupts = <37>;
+			clocks = <&ahb_gates 13>, <&nand_clk>;
+			clock-names = "ahb", "mod";
+			dmas = <&dma SUN4I_DMA_DEDICATED 3>;
+			dma-names = "rxtx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi0: spi@01c05000 {
+			compatible = "allwinner,sun4i-a10-spi";
+			reg = <0x01c05000 0x1000>;
+			interrupts = <10>;
+			clocks = <&ahb_gates 20>, <&spi0_clk>;
+			clock-names = "ahb", "mod";
+			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
+			       <&dma SUN4I_DMA_DEDICATED 26>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@01c06000 {
+			compatible = "allwinner,sun4i-a10-spi";
+			reg = <0x01c06000 0x1000>;
+			interrupts = <11>;
+			clocks = <&ahb_gates 21>, <&spi1_clk>;
+			clock-names = "ahb", "mod";
+			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
+			       <&dma SUN4I_DMA_DEDICATED 8>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		tve0: tv-encoder@01c0a000 {
+			compatible = "allwinner,sun4i-a10-tv-encoder";
+			reg = <0x01c0a000 0x1000>;
+			clocks = <&ahb_gates 34>;
+			resets = <&tcon_ch0_clk 0>;
+			status = "disabled";
+
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tve0_in_tcon0: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&tcon0_out_tve0>;
+				};
+			};
+		};
+
+		tcon0: lcd-controller@01c0c000 {
+			compatible = "allwinner,sun5i-a13-tcon";
+			reg = <0x01c0c000 0x1000>;
+			interrupts = <44>;
+			resets = <&tcon_ch0_clk 1>;
+			reset-names = "lcd";
+			clocks = <&ahb_gates 36>,
+				 <&tcon_ch0_clk>,
+				 <&tcon_ch1_clk>;
+			clock-names = "ahb",
+				      "tcon-ch0",
+				      "tcon-ch1";
+			clock-output-names = "tcon-pixel-clock";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tcon0_in: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					tcon0_in_be0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&be0_out_tcon0>;
+					};
+				};
+
+				tcon0_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					tcon0_out_tve0: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&tve0_in_tcon0>;
+					};
+				};
+			};
+		};
+
+		mmc0: mmc@01c0f000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c0f000 0x1000>;
+			clocks = <&ahb_gates 8>,
+				 <&mmc0_clk 0>,
+				 <&mmc0_clk 1>,
+				 <&mmc0_clk 2>;
+			clock-names = "ahb",
+				      "mmc",
+				      "output",
+				      "sample";
+			interrupts = <32>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc1: mmc@01c10000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c10000 0x1000>;
+			clocks = <&ahb_gates 9>,
+				 <&mmc1_clk 0>,
+				 <&mmc1_clk 1>,
+				 <&mmc1_clk 2>;
+			clock-names = "ahb",
+				      "mmc",
+				      "output",
+				      "sample";
+			interrupts = <33>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc2: mmc@01c11000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c11000 0x1000>;
+			clocks = <&ahb_gates 10>,
+				 <&mmc2_clk 0>,
+				 <&mmc2_clk 1>,
+				 <&mmc2_clk 2>;
+			clock-names = "ahb",
+				      "mmc",
+				      "output",
+				      "sample";
+			interrupts = <34>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		usb_otg: usb@01c13000 {
+			compatible = "allwinner,sun4i-a10-musb";
+			reg = <0x01c13000 0x0400>;
+			clocks = <&ahb_gates 0>;
+			interrupts = <38>;
+			interrupt-names = "mc";
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			extcon = <&usbphy 0>;
+			allwinner,sram = <&otg_sram 1>;
+			status = "disabled";
+
+			dr_mode = "otg";
+		};
+
+		usbphy: phy@01c13400 {
+			#phy-cells = <1>;
+			compatible = "allwinner,sun5i-a13-usb-phy";
+			reg = <0x01c13400 0x10 0x01c14800 0x4>;
+			reg-names = "phy_ctrl", "pmu1";
+			clocks = <&usb_clk 8>;
+			clock-names = "usb_phy";
+			resets = <&usb_clk 0>, <&usb_clk 1>;
+			reset-names = "usb0_reset", "usb1_reset";
+			status = "disabled";
+		};
+
+		ehci0: usb@01c14000 {
+			compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
+			reg = <0x01c14000 0x100>;
+			interrupts = <39>;
+			clocks = <&ahb_gates 1>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci0: usb@01c14400 {
+			compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
+			reg = <0x01c14400 0x100>;
+			interrupts = <40>;
+			clocks = <&usb_clk 6>, <&ahb_gates 2>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		spi2: spi@01c17000 {
+			compatible = "allwinner,sun4i-a10-spi";
+			reg = <0x01c17000 0x1000>;
+			interrupts = <12>;
+			clocks = <&ahb_gates 22>, <&spi2_clk>;
+			clock-names = "ahb", "mod";
+			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
+			       <&dma SUN4I_DMA_DEDICATED 28>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		intc: interrupt-controller@01c20400 {
+			compatible = "allwinner,sun4i-a10-ic";
+			reg = <0x01c20400 0x400>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		pio: pinctrl@01c20800 {
+			compatible = "nextthing,gr8-pinctrl";
+			reg = <0x01c20800 0x400>;
+			interrupts = <28>;
+			clocks = <&apb0_gates 5>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#gpio-cells = <3>;
+
+			i2c0_pins_a: i2c0@0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			i2c1_pins_a: i2c1@0 {
+				allwinner,pins = "PB15", "PB16";
+				allwinner,function = "i2c1";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			i2c2_pins_a: i2c2@0 {
+				allwinner,pins = "PB17", "PB18";
+				allwinner,function = "i2c2";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			i2s0_data_pins_a: i2s0-data@0 {
+				allwinner,pins = "PB6", "PB7", "PB8", "PB9";
+				allwinner,function = "i2s0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			i2s0_mclk_pins_a: i2s0-mclk@0 {
+				allwinner,pins = "PB5";
+				allwinner,function = "i2s0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			ir0_rx_pins_a: ir0@0 {
+				allwinner,pins = "PB4";
+				allwinner,function = "ir0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			lcd_rgb666_pins: lcd-rgb666@0 {
+				allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
+						 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
+						 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
+						 "PD24", "PD25", "PD26", "PD27";
+				allwinner,function = "lcd0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			mmc0_pins_a: mmc0@0 {
+				allwinner,pins = "PF0", "PF1", "PF2", "PF3",
+						 "PF4", "PF5";
+				allwinner,function = "mmc0";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_pins_a: nand-base0@0 {
+				allwinner,pins = "PC0", "PC1", "PC2",
+						"PC5", "PC8", "PC9", "PC10",
+						"PC11", "PC12", "PC13", "PC14",
+						"PC15";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs0_pins_a: nand-cs@0 {
+				allwinner,pins = "PC4";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_rb0_pins_a: nand-rb@0 {
+				allwinner,pins = "PC6";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			pwm0_pins_a: pwm0@0 {
+				allwinner,pins = "PB2";
+				allwinner,function = "pwm0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			pwm1_pins: pwm1 {
+				allwinner,pins = "PG13";
+				allwinner,function = "pwm1";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			spdif_tx_pins_a: spdif@0 {
+				allwinner,pins = "PB10";
+				allwinner,function = "spdif";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+			};
+
+			uart1_pins_a: uart1@1 {
+				allwinner,pins = "PG3", "PG4";
+				allwinner,function = "uart1";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart1_cts_rts_pins_a: uart1-cts-rts@0 {
+				allwinner,pins = "PG5", "PG6";
+				allwinner,function = "uart1";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart2_pins_a: uart2@1 {
+				allwinner,pins = "PD2", "PD3";
+				allwinner,function = "uart2";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart2_cts_rts_pins_a: uart2-cts-rts@0 {
+				allwinner,pins = "PD4", "PD5";
+				allwinner,function = "uart2";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart3_pins_a: uart3@1 {
+				allwinner,pins = "PG9", "PG10";
+				allwinner,function = "uart3";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart3_cts_rts_pins_a: uart3-cts-rts@0 {
+				allwinner,pins = "PG11", "PG12";
+				allwinner,function = "uart3";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+		};
+
+		pwm: pwm@01c20e00 {
+			compatible = "allwinner,sun5i-a10s-pwm";
+			reg = <0x01c20e00 0xc>;
+			clocks = <&osc24M>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		timer@01c20c00 {
+			compatible = "allwinner,sun4i-a10-timer";
+			reg = <0x01c20c00 0x90>;
+			interrupts = <22>;
+			clocks = <&osc24M>;
+		};
+
+		wdt: watchdog@01c20c90 {
+			compatible = "allwinner,sun4i-a10-wdt";
+			reg = <0x01c20c90 0x10>;
+		};
+
+		spdif: spdif@01c21000 {
+			#sound-dai-cells = <0>;
+			compatible = "allwinner,sun4i-a10-spdif";
+			reg = <0x01c21000 0x400>;
+			interrupts = <13>;
+			clocks = <&apb0_gates 1>, <&spdif_clk>;
+			clock-names = "apb", "spdif";
+			dmas = <&dma SUN4I_DMA_NORMAL 2>,
+			       <&dma SUN4I_DMA_NORMAL 2>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		ir0: ir@01c21800 {
+			compatible = "allwinner,sun4i-a10-ir";
+			clocks = <&apb0_gates 6>, <&ir0_clk>;
+			clock-names = "apb", "ir";
+			interrupts = <5>;
+			reg = <0x01c21800 0x40>;
+			status = "disabled";
+		};
+
+		i2s0: i2s@01c22400 {
+			#sound-dai-cells = <0>;
+			compatible = "allwinner,sun4i-a10-i2s";
+			reg = <0x01c22400 0x400>;
+			interrupts = <16>;
+			clocks = <&apb0_gates 3>, <&i2s0_clk>;
+			clock-names = "apb", "mod";
+			dmas = <&dma SUN4I_DMA_NORMAL 3>,
+			       <&dma SUN4I_DMA_NORMAL 3>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		lradc: lradc@01c22800 {
+			compatible = "allwinner,sun4i-a10-lradc-keys";
+			reg = <0x01c22800 0x100>;
+			interrupts = <31>;
+			status = "disabled";
+		};
+
+		codec: codec@01c22c00 {
+			#sound-dai-cells = <0>;
+			compatible = "allwinner,sun4i-a10-codec";
+			reg = <0x01c22c00 0x40>;
+			interrupts = <30>;
+			clocks = <&apb0_gates 0>, <&codec_clk>;
+			clock-names = "apb", "codec";
+			dmas = <&dma SUN4I_DMA_NORMAL 19>,
+			       <&dma SUN4I_DMA_NORMAL 19>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		rtp: rtp@01c25000 {
+			compatible = "allwinner,sun5i-a13-ts";
+			reg = <0x01c25000 0x100>;
+			interrupts = <29>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		uart1: serial@01c28400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28400 0x400>;
+			interrupts = <2>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 17>;
+			status = "disabled";
+		};
+
+		uart2: serial@01c28800 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28800 0x400>;
+			interrupts = <3>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 18>;
+			status = "disabled";
+		};
+
+		uart3: serial@01c28c00 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28c00 0x400>;
+			interrupts = <4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 19>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@01c2ac00 {
+			compatible = "allwinner,sun4i-a10-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <7>;
+			clocks = <&apb1_gates 0>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@01c2b000 {
+			compatible = "allwinner,sun4i-a10-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <8>;
+			clocks = <&apb1_gates 1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@01c2b400 {
+			compatible = "allwinner,sun4i-a10-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <9>;
+			clocks = <&apb1_gates 2>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		timer@01c60000 {
+			compatible = "allwinner,sun5i-a13-hstimer";
+			reg = <0x01c60000 0x1000>;
+			interrupts = <82>, <83>;
+			clocks = <&ahb_gates 28>;
+		};
+
+		fe0: display-frontend@01e00000 {
+			compatible = "allwinner,sun5i-a13-display-frontend";
+			reg = <0x01e00000 0x20000>;
+			interrupts = <47>;
+			clocks = <&ahb_gates 46>, <&de_fe_clk>,
+				 <&dram_gates 25>;
+			clock-names = "ahb", "mod",
+				      "ram";
+			resets = <&de_fe_clk>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				fe0_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					fe0_out_be0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&be0_in_fe0>;
+					};
+				};
+			};
+		};
+
+		be0: display-backend@01e60000 {
+			compatible = "allwinner,sun5i-a13-display-backend";
+			reg = <0x01e60000 0x10000>;
+			clocks = <&ahb_gates 44>, <&de_be_clk>,
+				 <&dram_gates 26>;
+			clock-names = "ahb", "mod",
+				      "ram";
+			resets = <&de_be_clk>;
+			status = "disabled";
+
+			assigned-clocks = <&de_be_clk>;
+			assigned-clock-rates = <300000000>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				be0_in: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					be0_in_fe0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&fe0_out_be0>;
+					};
+				};
+
+				be0_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					be0_out_tcon0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&tcon0_in_be0>;
+					};
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
new file mode 100644
index 0000000..3ba081c
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2017 Jelle van der Waa <jelle@vdwaa.nl>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	model = "FriendlyARM NanoPi NEO Air";
+	compatible = "friendlyarm,nanopi-neo-air", "allwinner,sun8i-h3";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		pwr {
+			label = "nanopi:green:pwr";
+			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+			default-state = "on";
+		};
+
+		status {
+			label = "nanopi:blue:status";
+			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
+		};
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+	cd-inverted;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usbphy {
+	/* USB VBUS is always on */
+	status = "okay";
+};
diff --git a/arch/arm/dts/sun9i-a80-cx-a99.dts b/arch/arm/dts/sun9i-a80-cx-a99.dts
new file mode 100644
index 0000000..a30b6fe
--- /dev/null
+++ b/arch/arm/dts/sun9i-a80-cx-a99.dts
@@ -0,0 +1,380 @@
+/*
+ * sun9i-a80-cx-a99.dts - Device Tree file for the Sunchip CX-A99 board.
+ *
+ * Copyright (C) 2017 Rask Ingemann Lambertsen <rask@formelder.dk>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * The Sunchip CX-A99 board is found in several similar Android media
+ * players, such as:
+ *
+ * Instabox Fantasy A8 (no external antenna)
+ * Jesurun CS-Q8 (ships with larger remote control)
+ * Jesurun Maxone
+ * Rikomagic (RKM) MK80/MK80LE
+ * Tronsmart Draco AW80 Meta/Telos
+ *
+ * See the Sunchip CX-A99 page on the Linux-sunxi wiki for more information.
+ */
+
+/dts-v1/;
+#include "sun9i-a80.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Sunchip CX-A99";
+	compatible = "sunchip,cx-a99", "allwinner,sun9i-a80";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue {
+			gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>;	/* PG10 */
+			label = "cx-a99:blue:status";
+		};
+
+		red {
+			gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;	/* PG11 */
+			label = "cx-a99:red:status";
+		};
+	};
+
+	powerseq_wifi: powerseq-wifi {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&ac100_rtc 1>;
+		clock-names = "ext_clock";
+		reset-gpios = <&r_pio 1 0 GPIO_ACTIVE_LOW>;	/* PM0 */
+		post-power-on-delay-ms = <1>;	/* Minimum 2 cycles. */
+	};
+
+	/* USB 2.0 connector closest to the 12 V power connector. */
+	reg_usb1_vbus: regulator-usb1-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb1-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&r_pio 0 7 /* no flag support */ 0>;	/* PL7 */
+		enable-active-high;
+	};
+
+	/* USB 2.0 connector next to the SD card slot. */
+	reg_usb3_vbus: regulator-usb3-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb3-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&r_pio 0 8 /* no flag support */ 0>;	/* PL8 */
+		enable-active-high;
+	};
+
+	/*
+	 * OZ80120 voltage regulator for the four Cortex-A15 CPU cores.
+	 * Although the regulator can output 750 - 1200 mV, the permissible
+	 * range for the CPU cores is only 800 - 1100 mV.
+	 */
+	reg_vdd_cpub: regulator-vdd-cpub {
+		compatible = "regulator-gpio";
+
+		regulator-always-on;
+		regulator-min-microvolt = < 800000>;
+		regulator-max-microvolt = <1100000>;
+		regulator-name = "vdd-cpub";
+
+		/* Note: GPIO flags are not supported here . */
+		enable-gpio = <&r_pio 0 2 /* flags n/a */ 0>;	/* PL2 */
+		enable-active-high;
+		gpios = <&r_pio 0 3 /* no flag support */ 0>,	/* PL3 */
+			<&r_pio 0 4 /* no flag support */ 0>,	/* PL4 */
+			<&r_pio 0 5 /* no flag support */ 0>;	/* PL5 */
+
+		gpios-states = <1 0 0>;
+		states = <	 750000 0x7
+				 800000 0x3
+				 850000 0x5
+				 900000 0x1
+				 950000 0x6
+				1000000 0x2
+				1100000 0x4
+				1200000 0x0>;
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ehci2 {
+	status = "okay";
+};
+
+/*
+ * SD card slot. Although the GPIO pin for card detection is listed as capable
+ * of generating interrupts in the "A80 User Manual", this doesn't work for
+ * some unknown reason, so poll the GPIO for card detection. This is also what
+ * the vendor sys_config.fex file specifies.
+ */
+&mmc0 {
+	bus-width = <4>;
+	cd-gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;	/* PH17 */
+	broken-cd;				/* Poll. */
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>;
+	vmmc-supply = <&reg_dcdce>;
+	status = "okay";
+};
+
+/* Ampak AP6335 IEEE 802.11 a/b/g/n/ac Wifi. */
+&mmc1 {
+	bus-width = <4>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	vmmc-supply = <&reg_cldo3>;	/* See cldo2,cldo3 note. */
+	vqmmc-supply = <&reg_aldo2>;
+	mmc-pwrseq = <&powerseq_wifi>;
+	status = "okay";
+};
+
+/* On-board eMMC card. */
+&mmc2 {
+	bus-width = <8>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_8bit_pins>;
+	vmmc-supply = <&reg_dcdce>;
+	status = "okay";
+};
+
+&osc32k {
+	clocks = <&ac100_rtc 0>;
+};
+
+&r_ir {
+	status = "okay";
+};
+
+&r_rsb {
+	status = "okay";
+
+	ac100: codec@e89 {
+		compatible = "x-powers,ac100";
+		reg = <0xe89>;
+
+		ac100_codec: codec {
+			compatible = "x-powers,ac100-codec";
+			interrupt-parent = <&r_pio>;
+			interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>;	/* PL9 */
+			#clock-cells = <0>;
+			clock-output-names = "4M_adda";
+		};
+
+		ac100_rtc: rtc {
+			compatible = "x-powers,ac100-rtc";
+			interrupt-parent = <&nmi_intc>;
+			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&ac100_codec>;
+			#clock-cells = <1>;
+			clock-output-names = "cko1_rtc",
+					     "cko2_rtc",
+					     "cko3_rtc";
+		};
+	};
+
+	pmic@745 {
+		compatible = "x-powers,axp808", "x-powers,axp806";
+		x-powers,master-mode;
+		reg = <0x745>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		swin-supply = <&reg_dcdce>;
+
+		regulators {
+			reg_aldo1: aldo1 {
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc-3v0";
+			};
+
+			/* Supplies pin groups G and M. */
+			reg_aldo2: aldo2 {
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-name = "vddio-wifi-codec";
+			};
+
+			reg_aldo3: aldo3 {
+				regulator-boot-on;
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-name = "vddio-gmac";
+			};
+
+			reg_bldo1: bldo1 {
+				regulator-always-on;	/* Hang if disabled */
+				regulator-min-microvolt = <1700000>;
+				regulator-max-microvolt = <1900000>;
+				regulator-name = "vdd18-dll-vcc18-pll";
+			};
+
+			reg_bldo2: bldo2 {
+				regulator-always-on;	/* Hang if disabled */
+				regulator-min-microvolt = < 800000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-name = "vdd-cpus";
+			};
+
+			reg_bldo3: bldo3 {
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-name = "vcc12-hsic";
+			};
+
+			reg_bldo4: bldo4 {
+				regulator-boot-on;
+				regulator-min-microvolt = < 800000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-name = "vdd09-hdmi";
+			};
+
+			/* Supplies PLx pins which control some regulators. */
+			reg_cldo1: cldo1 {
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc-pl-led";
+			};
+
+			/*
+			 * cldo2 and cldo3 are connected in parallel.
+			 * There is currently no way to express that.
+			 * For now, use regulator-always-on on cldo2 and lock
+			 * the voltage on both to 3.3 V.
+			 */
+			reg_cldo2: cldo2 {
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vbat2-wifi+bt";
+			};
+
+			reg_cldo3: cldo3 {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vbat1-wifi+bt";
+			};
+
+			reg_dcdca: dcdca {
+				regulator-always-on;
+				regulator-min-microvolt = < 800000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-name = "vdd-cpua";
+			};
+
+			reg_dcdcb: dcdcb {
+				regulator-always-on;
+				regulator-min-microvolt = <1450000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-name = "vcc-dram";
+			};
+
+			reg_dcdcc: dcdcc {
+				regulator-min-microvolt = < 800000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-name = "vdd-gpu";
+			};
+
+			reg_dcdcd: dcdcd {
+				regulator-always-on;	/* Hang if disabled. */
+				regulator-min-microvolt = < 800000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-name = "vdd-sys";
+			};
+
+			/* Supplies pin groups B-F and H. */
+			reg_dcdce: dcdce {
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc-io-mmc-spdif";
+			};
+
+			reg_sw: sw {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc-gmac-codec";
+			};
+		};
+	};
+};
+
+/*
+ * 5-pin connector opposite of the SD card slot:
+ * 1 = GND (pointed to by small triangle), 2 = GND, 3 = 3.3 V, 4 = RX, 5 = TX.
+ */
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usbphy1 {
+	phy-supply = <&reg_usb1_vbus>;
+	status = "okay";
+};
+
+&usbphy3 {
+	phy-supply = <&reg_usb3_vbus>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/sun9i-a80.dtsi b/arch/arm/dts/sun9i-a80.dtsi
index f68b324..92412b2 100644
--- a/arch/arm/dts/sun9i-a80.dtsi
+++ b/arch/arm/dts/sun9i-a80.dtsi
@@ -701,6 +701,14 @@
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
+			mmc1_pins: mmc1 {
+				allwinner,pins = "PG0", "PG1" ,"PG2", "PG3",
+						 "PG4", "PG5";
+				allwinner,function = "mmc1";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			mmc2_8bit_pins: mmc2_8bit {
 				allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 						 "PC10", "PC11", "PC12",
diff --git a/arch/arm/dts/tegra124-apalis.dts b/arch/arm/dts/tegra124-apalis.dts
new file mode 100644
index 0000000..3853a28
--- /dev/null
+++ b/arch/arm/dts/tegra124-apalis.dts
@@ -0,0 +1,2203 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra124.dtsi"
+
+/ {
+	model = "Toradex Apalis TK1 on Apalis Evaluation Board";
+	compatible = "toradex,apalis-tk1-eval", "toradex,apalis-tk1",
+		     "nvidia,tegra124";
+
+	aliases {
+		i2c0 = "/i2c@7000d000";
+		i2c1 = "/i2c@7000c000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		mmc0 = "/sdhci@700b0600";
+		mmc1 = "/sdhci@700b0000";
+		mmc2 = "/sdhci@700b0400";
+		rtc0 = "/i2c@7000c000/rtc@68";
+		rtc1 = "/i2c@7000d000/pmic@40";
+		rtc2 = "/rtc@7000e000";
+		serial0 = &uarta;
+		serial1 = &uartb;
+		serial2 = &uartc;
+		serial3 = &uartd;
+		usb0 = "/usb@7d000000";
+		usb1 = "/usb@7d004000";
+		usb2 = "/usb@7d008000";
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+
+	pcie-controller@01003000 {
+		status = "okay";
+		avddio-pex-supply = <&vdd_1v05>;
+		avdd-pex-pll-supply = <&vdd_1v05>;
+		avdd-pll-erefe-supply = <&avdd_1v05>;
+		dvddio-pex-supply = <&vdd_1v05>;
+		hvdd-pex-pll-e-supply = <&reg_3v3>;
+		hvdd-pex-supply = <&reg_3v3>;
+		vddio-pex-ctl-supply = <&reg_3v3>;
+
+		/* Apalis PCIe (additional lane Apalis type specific) */
+		pci@1,0 {
+			/* PCIE1_RX/TX and TS_DIFF1/2 left disabled */
+		};
+
+		/* I210 Gigabit Ethernet Controller (On-module) */
+		pci@2,0 {
+			status = "okay";
+		};
+	};
+
+	host1x@50000000 {
+		hdmi@54280000 {
+			pll-supply = <&reg_1v05_avdd_hdmi_pll>;
+			vdd-supply = <&reg_3v3_avdd_hdmi>;
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+			nvidia,hpd-gpio =
+				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+			status = "okay";
+		};
+	};
+
+	gpu@0,57000000 {
+		/*
+		 * Node left disabled on purpose - the bootloader will enable
+		 * it after having set the VPR up
+		 */
+		vdd-supply = <&vdd_gpu>;
+	};
+
+	pinmux: pinmux@70000868 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			/* Analogue Audio (On-module) */
+			dap3_fs_pp0 {
+				nvidia,pins = "dap3_fs_pp0";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap3_din_pp1 {
+				nvidia,pins = "dap3_din_pp1";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap3_dout_pp2 {
+				nvidia,pins = "dap3_dout_pp2";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap3_sclk_pp3 {
+				nvidia,pins = "dap3_sclk_pp3";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap_mclk1_pw4 {
+				nvidia,pins = "dap_mclk1_pw4";
+				nvidia,function = "extperiph1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis BKL1_ON */
+			pbb5 {
+				nvidia,pins = "pbb5";
+				nvidia,function = "vgp5";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis BKL1_PWM */
+			pu6 {
+				nvidia,pins = "pu6";
+				nvidia,function = "pwm3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis CAM1_MCLK */
+			cam_mclk_pcc0 {
+				nvidia,pins = "cam_mclk_pcc0";
+				nvidia,function = "vi_alt3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis Digital Audio */
+			dap2_fs_pa2 {
+				nvidia,pins = "dap2_fs_pa2";
+				nvidia,function = "hda";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap2_sclk_pa3 {
+				nvidia,pins = "dap2_sclk_pa3";
+				nvidia,function = "hda";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap2_din_pa4 {
+				nvidia,pins = "dap2_din_pa4";
+				nvidia,function = "hda";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap2_dout_pa5 {
+				nvidia,pins = "dap2_dout_pa5";
+				nvidia,function = "hda";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pbb3 { /* DAP1_RESET */
+				nvidia,pins = "pbb3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			clk3_out_pee0 {
+				nvidia,pins = "clk3_out_pee0";
+				nvidia,function = "extperiph3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis GPIO */
+			ddc_scl_pv4 {
+				nvidia,pins = "ddc_scl_pv4";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ddc_sda_pv5 {
+				nvidia,pins = "ddc_sda_pv5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pex_l0_rst_n_pdd1 {
+				nvidia,pins = "pex_l0_rst_n_pdd1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pex_l0_clkreq_n_pdd2 {
+				nvidia,pins = "pex_l0_clkreq_n_pdd2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pex_l1_rst_n_pdd5 {
+				nvidia,pins = "pex_l1_rst_n_pdd5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pex_l1_clkreq_n_pdd6 {
+				nvidia,pins = "pex_l1_clkreq_n_pdd6";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dp_hpd_pff0 {
+				nvidia,pins = "dp_hpd_pff0";
+				nvidia,function = "dp";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pff2 {
+				nvidia,pins = "pff2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
+				nvidia,pins = "owr";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis HDMI1_CEC */
+			hdmi_cec_pee3 {
+				nvidia,pins = "hdmi_cec_pee3";
+				nvidia,function = "cec";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis HDMI1_HPD */
+			hdmi_int_pn7 {
+				nvidia,pins = "hdmi_int_pn7";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis I2C1 */
+			gen1_i2c_scl_pc4 {
+				nvidia,pins = "gen1_i2c_scl_pc4";
+				nvidia,function = "i2c1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			gen1_i2c_sda_pc5 {
+				nvidia,pins = "gen1_i2c_sda_pc5";
+				nvidia,function = "i2c1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* Apalis I2C2 (DDC) */
+			gen2_i2c_scl_pt5 {
+				nvidia,pins = "gen2_i2c_scl_pt5";
+				nvidia,function = "i2c2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			gen2_i2c_sda_pt6 {
+				nvidia,pins = "gen2_i2c_sda_pt6";
+				nvidia,function = "i2c2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* Apalis I2C3 (CAM) */
+			cam_i2c_scl_pbb1 {
+				nvidia,pins = "cam_i2c_scl_pbb1";
+				nvidia,function = "i2c3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			cam_i2c_sda_pbb2 {
+				nvidia,pins = "cam_i2c_sda_pbb2";
+				nvidia,function = "i2c3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* Apalis MMC1 */
+			sdmmc1_cd_n_pv3 { /* CD# GPIO */
+				nvidia,pins = "sdmmc1_wp_n_pv3";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			clk2_out_pw5 { /* D5 GPIO */
+				nvidia,pins = "clk2_out_pw5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc1_dat3_py4 {
+				nvidia,pins = "sdmmc1_dat3_py4";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc1_dat2_py5 {
+				nvidia,pins = "sdmmc1_dat2_py5";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc1_dat1_py6 {
+				nvidia,pins = "sdmmc1_dat1_py6";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc1_dat0_py7 {
+				nvidia,pins = "sdmmc1_dat0_py7";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc1_clk_pz0 {
+				nvidia,pins = "sdmmc1_clk_pz0";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc1_cmd_pz1 {
+				nvidia,pins = "sdmmc1_cmd_pz1";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			clk2_req_pcc5 { /* D4 GPIO */
+				nvidia,pins = "clk2_req_pcc5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
+				nvidia,pins = "sdmmc3_clk_lb_in_pee5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			usb_vbus_en2_pff1 { /* D7 GPIO */
+				nvidia,pins = "usb_vbus_en2_pff1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* Apalis PWM */
+			ph0 {
+				nvidia,pins = "ph0";
+				nvidia,function = "pwm0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ph1 {
+				nvidia,pins = "ph1";
+				nvidia,function = "pwm1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ph2 {
+				nvidia,pins = "ph2";
+				nvidia,function = "pwm2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			/* PWM3 active on pu6 being Apalis BKL1_PWM */
+			ph3 {
+				nvidia,pins = "ph3";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis SATA1_ACT# */
+			dap1_dout_pn2 {
+				nvidia,pins = "dap1_dout_pn2";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis SD1 */
+			sdmmc3_clk_pa6 {
+				nvidia,pins = "sdmmc3_clk_pa6";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_cmd_pa7 {
+				nvidia,pins = "sdmmc3_cmd_pa7";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_dat3_pb4 {
+				nvidia,pins = "sdmmc3_dat3_pb4";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_dat2_pb5 {
+				nvidia,pins = "sdmmc3_dat2_pb5";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_dat1_pb6 {
+				nvidia,pins = "sdmmc3_dat1_pb6";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_dat0_pb7 {
+				nvidia,pins = "sdmmc3_dat0_pb7";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_cd_n_pv2 { /* CD# GPIO */
+				nvidia,pins = "sdmmc3_cd_n_pv2";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* Apalis SPDIF */
+			spdif_out_pk5 {
+				nvidia,pins = "spdif_out_pk5";
+				nvidia,function = "spdif";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			spdif_in_pk6 {
+				nvidia,pins = "spdif_in_pk6";
+				nvidia,function = "spdif";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* Apalis SPI1 */
+			ulpi_clk_py0 {
+				nvidia,pins = "ulpi_clk_py0";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_dir_py1 {
+				nvidia,pins = "ulpi_dir_py1";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ulpi_nxt_py2 {
+				nvidia,pins = "ulpi_nxt_py2";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_stp_py3 {
+				nvidia,pins = "ulpi_stp_py3";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis SPI2 */
+			pg5 {
+				nvidia,pins = "pg5";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pg6 {
+				nvidia,pins = "pg6";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pg7 {
+				nvidia,pins = "pg7";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pi3 {
+				nvidia,pins = "pi3";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis UART1 */
+			pb1 { /* DCD GPIO */
+				nvidia,pins = "pb1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pk7 { /* RI GPIO */
+				nvidia,pins = "pk7";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			uart1_txd_pu0 {
+				nvidia,pins = "pu0";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			uart1_rxd_pu1 {
+				nvidia,pins = "pu1";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			uart1_cts_n_pu2 {
+				nvidia,pins = "pu2";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			uart1_rts_n_pu3 {
+				nvidia,pins = "pu3";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			uart3_cts_n_pa1 { /* DSR GPIO */
+				nvidia,pins = "uart3_cts_n_pa1";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			uart3_rts_n_pc0 { /* DTR GPIO */
+				nvidia,pins = "uart3_rts_n_pc0";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis UART2 */
+			uart2_txd_pc2 {
+				nvidia,pins = "uart2_txd_pc2";
+				nvidia,function = "irda";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			uart2_rxd_pc3 {
+				nvidia,pins = "uart2_rxd_pc3";
+				nvidia,function = "irda";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			uart2_cts_n_pj5 {
+				nvidia,pins = "uart2_cts_n_pj5";
+				nvidia,function = "uartb";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			uart2_rts_n_pj6 {
+				nvidia,pins = "uart2_rts_n_pj6";
+				nvidia,function = "uartb";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis UART3 */
+			uart3_txd_pw6 {
+				nvidia,pins = "uart3_txd_pw6";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			uart3_rxd_pw7 {
+				nvidia,pins = "uart3_rxd_pw7";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* Apalis UART4 */
+			uart4_rxd_pb0 {
+				nvidia,pins = "pb0";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			uart4_txd_pj7 {
+				nvidia,pins = "pj7";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis USBH_EN */
+			usb_vbus_en1_pn5 {
+				nvidia,pins = "usb_vbus_en1_pn5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis USBH_OC# */
+			pbb0 {
+				nvidia,pins = "pbb0";
+				nvidia,function = "vgp6";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* Apalis USBO1_EN */
+			usb_vbus_en0_pn4 {
+				nvidia,pins = "usb_vbus_en0_pn4";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Apalis USBO1_OC# */
+			pbb4 {
+				nvidia,pins = "pbb4";
+				nvidia,function = "vgp4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* Apalis WAKE1_MICO */
+			pex_wake_n_pdd3 {
+				nvidia,pins = "pex_wake_n_pdd3";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* CORE_PWR_REQ */
+			core_pwr_req {
+				nvidia,pins = "core_pwr_req";
+				nvidia,function = "pwron";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* CPU_PWR_REQ */
+			cpu_pwr_req {
+				nvidia,pins = "cpu_pwr_req";
+				nvidia,function = "cpu";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* DVFS */
+			dvfs_pwm_px0 {
+				nvidia,pins = "dvfs_pwm_px0";
+				nvidia,function = "cldvfs";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dvfs_clk_px2 {
+				nvidia,pins = "dvfs_clk_px2";
+				nvidia,function = "cldvfs";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* eMMC */
+			sdmmc4_dat0_paa0 {
+				nvidia,pins = "sdmmc4_dat0_paa0";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat1_paa1 {
+				nvidia,pins = "sdmmc4_dat1_paa1";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat2_paa2 {
+				nvidia,pins = "sdmmc4_dat2_paa2";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat3_paa3 {
+				nvidia,pins = "sdmmc4_dat3_paa3";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat4_paa4 {
+				nvidia,pins = "sdmmc4_dat4_paa4";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat5_paa5 {
+				nvidia,pins = "sdmmc4_dat5_paa5";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat6_paa6 {
+				nvidia,pins = "sdmmc4_dat6_paa6";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat7_paa7 {
+				nvidia,pins = "sdmmc4_dat7_paa7";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_clk_pcc4 {
+				nvidia,pins = "sdmmc4_clk_pcc4";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_cmd_pt7 {
+				nvidia,pins = "sdmmc4_cmd_pt7";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* JTAG_RTCK */
+			jtag_rtck {
+				nvidia,pins = "jtag_rtck";
+				nvidia,function = "rtck";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* LAN_DEV_OFF# */
+			ulpi_data5_po6 {
+				nvidia,pins = "ulpi_data5_po6";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* LAN_RESET# */
+			kb_row10_ps2 {
+				nvidia,pins = "kb_row10_ps2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* LAN_WAKE# */
+			ulpi_data4_po5 {
+				nvidia,pins = "ulpi_data4_po5";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* MCU_INT1# */
+			pk2 {
+				nvidia,pins = "pk2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* MCU_INT2# */
+			pj2 {
+				nvidia,pins = "pj2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* MCU_INT3# */
+			pi5 {
+				nvidia,pins = "pi5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* MCU_INT4# */
+			pj0 {
+				nvidia,pins = "pj0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* MCU_RESET */
+			pbb6 {
+				nvidia,pins = "pbb6";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* MCU SPI */
+			gpio_x4_aud_px4 {
+				nvidia,pins = "gpio_x4_aud_px4";
+				nvidia,function = "spi2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gpio_x5_aud_px5 {
+				nvidia,pins = "gpio_x5_aud_px5";
+				nvidia,function = "spi2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gpio_x6_aud_px6 { /* MCU_CS */
+				nvidia,pins = "gpio_x6_aud_px6";
+				nvidia,function = "spi2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gpio_x7_aud_px7 {
+				nvidia,pins = "gpio_x7_aud_px7";
+				nvidia,function = "spi2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gpio_w2_aud_pw2 { /* MCU_CSEZP */
+				nvidia,pins = "gpio_w2_aud_pw2";
+				nvidia,function = "spi2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* PMIC_CLK_32K */
+			clk_32k_in {
+				nvidia,pins = "clk_32k_in";
+				nvidia,function = "clk";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* PMIC_CPU_OC_INT */
+			clk_32k_out_pa0 {
+				nvidia,pins = "clk_32k_out_pa0";
+				nvidia,function = "soc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* PWR_I2C */
+			pwr_i2c_scl_pz6 {
+				nvidia,pins = "pwr_i2c_scl_pz6";
+				nvidia,function = "i2cpwr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			pwr_i2c_sda_pz7 {
+				nvidia,pins = "pwr_i2c_sda_pz7";
+				nvidia,function = "i2cpwr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* PWR_INT_N */
+			pwr_int_n {
+				nvidia,pins = "pwr_int_n";
+				nvidia,function = "pmi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* RESET_MOCI_CTRL */
+			pu4 {
+				nvidia,pins = "pu4";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* RESET_OUT_N */
+			reset_out_n {
+				nvidia,pins = "reset_out_n";
+				nvidia,function = "reset_out_n";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* SHIFT_CTRL_DIR_IN */
+			kb_row0_pr0 {
+				nvidia,pins = "kb_row0_pr0";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row1_pr1 {
+				nvidia,pins = "kb_row1_pr1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Configure level-shifter as output for HDA */
+			kb_row11_ps3 {
+				nvidia,pins = "kb_row11_ps3";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* SHIFT_CTRL_DIR_OUT */
+			kb_col5_pq5 {
+				nvidia,pins = "kb_col5_pq5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_col6_pq6 {
+				nvidia,pins = "kb_col6_pq6";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_col7_pq7 {
+				nvidia,pins = "kb_col7_pq7";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* SHIFT_CTRL_OE */
+			kb_col0_pq0 {
+				nvidia,pins = "kb_col0_pq0";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_col1_pq1 {
+				nvidia,pins = "kb_col1_pq1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_col2_pq2 {
+				nvidia,pins = "kb_col2_pq2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_col4_pq4 {
+				nvidia,pins = "kb_col4_pq4";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row2_pr2 {
+				nvidia,pins = "kb_row2_pr2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
+			pi6 {
+				nvidia,pins = "pi6";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* TOUCH_INT */
+			gpio_w3_aud_pw3 {
+				nvidia,pins = "gpio_w3_aud_pw3";
+				nvidia,function = "spi6";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			pc7 { /* NC */
+				nvidia,pins = "pc7";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pg0 { /* NC */
+				nvidia,pins = "pg0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pg1 { /* NC */
+				nvidia,pins = "pg1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pg2 { /* NC */
+				nvidia,pins = "pg2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pg3 { /* NC */
+				nvidia,pins = "pg3";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pg4 { /* NC */
+				nvidia,pins = "pg4";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ph4 { /* NC */
+				nvidia,pins = "ph4";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ph5 { /* NC */
+				nvidia,pins = "ph5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ph6 { /* NC */
+				nvidia,pins = "ph6";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ph7 { /* NC */
+				nvidia,pins = "ph7";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pi0 { /* NC */
+				nvidia,pins = "pi0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pi1 { /* NC */
+				nvidia,pins = "pi1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pi2 { /* NC */
+				nvidia,pins = "pi2";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pi4 { /* NC */
+				nvidia,pins = "pi4";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pi7 { /* NC */
+				nvidia,pins = "pi7";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pk0 { /* NC */
+				nvidia,pins = "pk0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pk1 { /* NC */
+				nvidia,pins = "pk1";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pk3 { /* NC */
+				nvidia,pins = "pk3";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pk4 { /* NC */
+				nvidia,pins = "pk4";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap1_fs_pn0 { /* NC */
+				nvidia,pins = "dap1_fs_pn0";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap1_din_pn1 { /* NC */
+				nvidia,pins = "dap1_din_pn1";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap1_sclk_pn3 { /* NC */
+				nvidia,pins = "dap1_sclk_pn3";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_data7_po0 { /* NC */
+				nvidia,pins = "ulpi_data7_po0";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_data0_po1 { /* NC */
+				nvidia,pins = "ulpi_data0_po1";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_data1_po2 { /* NC */
+				nvidia,pins = "ulpi_data1_po2";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_data2_po3 { /* NC */
+				nvidia,pins = "ulpi_data2_po3";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_data3_po4 { /* NC */
+				nvidia,pins = "ulpi_data3_po4";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_data6_po7 { /* NC */
+				nvidia,pins = "ulpi_data6_po7";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap4_fs_pp4 { /* NC */
+				nvidia,pins = "dap4_fs_pp4";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap4_din_pp5 { /* NC */
+				nvidia,pins = "dap4_din_pp5";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap4_dout_pp6 { /* NC */
+				nvidia,pins = "dap4_dout_pp6";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap4_sclk_pp7 { /* NC */
+				nvidia,pins = "dap4_sclk_pp7";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_col3_pq3 { /* NC */
+				nvidia,pins = "kb_col3_pq3";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row3_pr3 { /* NC */
+				nvidia,pins = "kb_row3_pr3";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row4_pr4 { /* NC */
+				nvidia,pins = "kb_row4_pr4";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row5_pr5 { /* NC */
+				nvidia,pins = "kb_row5_pr5";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row6_pr6 { /* NC */
+				nvidia,pins = "kb_row6_pr6";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row7_pr7 { /* NC */
+				nvidia,pins = "kb_row7_pr7";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row8_ps0 { /* NC */
+				nvidia,pins = "kb_row8_ps0";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row9_ps1 { /* NC */
+				nvidia,pins = "kb_row9_ps1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row12_ps4 { /* NC */
+				nvidia,pins = "kb_row12_ps4";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row13_ps5 { /* NC */
+				nvidia,pins = "kb_row13_ps5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row14_ps6 { /* NC */
+				nvidia,pins = "kb_row14_ps6";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row15_ps7 { /* NC */
+				nvidia,pins = "kb_row15_ps7";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row16_pt0 { /* NC */
+				nvidia,pins = "kb_row16_pt0";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row17_pt1 { /* NC */
+				nvidia,pins = "kb_row17_pt1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pu5 { /* NC */
+				nvidia,pins = "pu5";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pv0 { /* NC */
+				nvidia,pins = "pv0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pv1 { /* NC */
+				nvidia,pins = "pv1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gpio_x1_aud_px1 { /* NC */
+				nvidia,pins = "gpio_x1_aud_px1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gpio_x3_aud_px3 { /* NC */
+				nvidia,pins = "gpio_x3_aud_px3";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pbb7 { /* NC */
+				nvidia,pins = "pbb7";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pcc1 { /* NC */
+				nvidia,pins = "pcc1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pcc2 { /* NC */
+				nvidia,pins = "pcc2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			clk3_req_pee1 { /* NC */
+				nvidia,pins = "clk3_req_pee1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap_mclk1_req_pee2 { /* NC */
+				nvidia,pins = "dap_mclk1_req_pee2";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			/*
+			 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
+			 * driver enabled aka not tristated and input driver
+			 * enabled as well as it features some magic properties
+			 * even though the external loopback is disabled and the
+			 * internal loopback used as per
+			 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
+			 * bits being set to 0xfffd according to the TRM!
+			 */
+			sdmmc3_clk_lb_out_pee4 { /* NC */
+				nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+		};
+	};
+
+	/* Apalis UART1 */
+	serial@70006000 {
+		status = "okay";
+	};
+
+	/* Apalis UART2 */
+	serial@70006040 {
+		compatible = "nvidia,tegra124-hsuart";
+		status = "okay";
+	};
+
+	/* Apalis UART3 */
+	serial@70006200 {
+		compatible = "nvidia,tegra124-hsuart";
+		status = "okay";
+	};
+
+	/* Apalis UART4 */
+	serial@70006300 {
+		compatible = "nvidia,tegra124-hsuart";
+		status = "okay";
+	};
+
+	pwm@7000a000 {
+		status = "okay";
+	};
+
+	hdmi_ddc: i2c@7000c400 {
+		clock-frequency = <100000>;
+	};
+
+	/*
+	 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
+	 * board)
+	 */
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+
+		pcie-switch@58 {
+			compatible = "plx,pex8605";
+			reg = <0x58>;
+		};
+
+		/* M41T0M6 real time clock on carrier board */
+		rtc@68 {
+			compatible = "st,m41t00";
+			reg = <0x68>;
+		};
+	};
+
+	/*
+	 * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID)
+	 */
+	hdmi_ddc: i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/*
+	 * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor
+	 * on carrier board)
+	 */
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/* I2C4 (DDC): unused */
+
+	/* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		/* SGTL5000 audio codec */
+		sgtl5000: codec@a {
+			compatible = "fsl,sgtl5000";
+			reg = <0x0a>;
+			VDDA-supply = <&reg_3v3>;
+			VDDIO-supply = <&vddio_1v8>;
+			clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
+		};
+
+		pmic: pmic@40 {
+			compatible = "ams,as3722";
+			reg = <0x40>;
+			interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+			ams,system-power-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			gpio-controller;
+			#gpio-cells = <2>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&as3722_default>;
+
+			as3722_default: pinmux {
+				gpio2_7 {
+					pins = "gpio2", /* PWR_EN_+V3.3 */
+					       "gpio7"; /* +V1.6_LPO */
+					function = "gpio";
+					bias-pull-up;
+				};
+
+				gpio1_3_4_5_6 {
+					pins = "gpio1", "gpio3", "gpio4",
+					       "gpio5", "gpio6";
+					bias-high-impedance;
+				};
+			};
+
+			regulators {
+				vsup-sd2-supply = <&reg_3v3>;
+				vsup-sd3-supply = <&reg_3v3>;
+				vsup-sd4-supply = <&reg_3v3>;
+				vsup-sd5-supply = <&reg_3v3>;
+				vin-ldo0-supply = <&vddio_ddr_1v35>;
+				vin-ldo1-6-supply = <&reg_3v3>;
+				vin-ldo2-5-7-supply = <&vddio_1v8>;
+				vin-ldo3-4-supply = <&reg_3v3>;
+				vin-ldo9-10-supply = <&reg_3v3>;
+				vin-ldo11-supply = <&reg_3v3>;
+
+				vdd_cpu: sd0 {
+					regulator-name = "+VDD_CPU_AP";
+					regulator-min-microvolt = <700000>;
+					regulator-max-microvolt = <1400000>;
+					regulator-min-microamp = <3500000>;
+					regulator-max-microamp = <3500000>;
+					regulator-always-on;
+					regulator-boot-on;
+					ams,ext-control = <2>;
+				};
+
+				sd1 {
+					regulator-name = "+VDD_CORE";
+					regulator-min-microvolt = <700000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-min-microamp = <2500000>;
+					regulator-max-microamp = <4000000>;
+					regulator-always-on;
+					regulator-boot-on;
+					ams,ext-control = <1>;
+				};
+
+				vddio_ddr_1v35: sd2 {
+					regulator-name =
+						"+V1.35_VDDIO_DDR(sd2)";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				sd3 {
+					regulator-name =
+						"+V1.35_VDDIO_DDR(sd3)";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				vdd_1v05: sd4 {
+					regulator-name = "+V1.05";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+				};
+
+				vddio_1v8: sd5 {
+					regulator-name = "+V1.8";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				vdd_gpu: sd6 {
+					regulator-name = "+VDD_GPU_AP";
+					regulator-min-microvolt = <650000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-min-microamp = <3500000>;
+					regulator-max-microamp = <3500000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				avdd_1v05: ldo0 {
+					regulator-name = "+V1.05_AVDD";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+					regulator-boot-on;
+					regulator-always-on;
+					ams,ext-control = <1>;
+				};
+
+				vddio_sdmmc1: ldo1 {
+					regulator-name = "VDDIO_SDMMC1";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				ldo2 {
+					regulator-name = "+V1.2";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				ldo3 {
+					regulator-name = "+V1.05_RTC";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-boot-on;
+					regulator-always-on;
+					ams,enable-tracking;
+				};
+
+				/* 1.8V for LVDS, 3.3V for eDP */
+				ldo4 {
+					regulator-name = "AVDD_LVDS0_PLL";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				/* LDO5 not used */
+
+				vddio_sdmmc3: ldo6 {
+					regulator-name = "VDDIO_SDMMC3";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				/* LDO7 not used */
+
+				ldo9 {
+					regulator-name = "+V3.3_ETH(ldo9)";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				ldo10 {
+					regulator-name = "+V3.3_ETH(ldo10)";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				ldo11 {
+					regulator-name = "+V1.8_VPP_FUSE";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+			};
+		};
+
+		/*
+		 * TMP451 temperature sensor
+		 * Note: THERM_N directly connected to AS3722 PMIC THERM
+		 */
+		temperature-sensor@4c {
+			compatible = "ti,tmp451";
+			reg = <0x4c>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
+			#thermal-sensor-cells = <1>;
+		};
+	};
+
+	/* SPI1: Apalis SPI1 */
+	spi@7000d400 {
+		status = "okay";
+		spi-max-frequency = <50000000>;
+
+		spidev0: spidev@0 {
+			compatible = "spidev";
+			reg = <0>;
+			spi-max-frequency = <50000000>;
+		};
+	};
+
+	/* SPI2: MCU SPI */
+	spi@7000d600 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	/* SPI4: Apalis SPI2 */
+	spi@7000da00 {
+		status = "okay";
+		spi-max-frequency = <50000000>;
+
+		spidev1: spidev@0 {
+			compatible = "spidev";
+			reg = <0>;
+			spi-max-frequency = <50000000>;
+		};
+	};
+
+	pmc@7000e400 {
+		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <1>;
+		nvidia,cpu-pwr-good-time = <500>;
+		nvidia,cpu-pwr-off-time = <300>;
+		nvidia,core-pwr-good-time = <641 3845>;
+		nvidia,core-pwr-off-time = <61036>;
+		nvidia,core-power-req-active-high;
+		nvidia,sys-clock-req-active-high;
+
+		/* Set power_off bit in ResetControl register of AS3722 PMIC */
+		i2c-thermtrip {
+			nvidia,i2c-controller-id = <4>;
+			nvidia,bus-addr = <0x40>;
+			nvidia,reg-addr = <0x36>;
+			nvidia,reg-data = <0x2>;
+		};
+	};
+
+	/* Apalis Serial ATA */
+	sata@70020000 {
+		avdd-supply = <&vdd_1v05>;
+		hvdd-supply = <&reg_3v3>;
+		vddio-supply = <&vdd_1v05>;
+		status = "okay";
+	};
+
+	hda@70030000 {
+		status = "okay";
+	};
+
+	usb@70090000 {
+		/* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
+		avddio-pex-supply = <&vdd_1v05>;
+		avdd-pll-erefe-supply = <&avdd_1v05>;
+		avdd-pll-utmip-supply = <&vddio_1v8>;
+		avdd-usb-ss-pll-supply = <&vdd_1v05>;
+		avdd-usb-supply = <&reg_3v3>;
+		dvddio-pex-supply = <&vdd_1v05>;
+		hvdd-usb-ss-pll-e-supply = <&reg_3v3>;
+		hvdd-usb-ss-supply = <&reg_3v3>;
+		status = "okay";
+	};
+
+	padctl@7009f000 {
+		pinctrl-0 = <&padctl_default>;
+		pinctrl-names = "default";
+
+		padctl_default: pinmux {
+			usb3 {
+				nvidia,lanes = "pcie-0", "pcie-1";
+				nvidia,function = "usb3";
+				nvidia,iddq = <0>;
+			};
+
+			pcie {
+				nvidia,lanes = "pcie-2", "pcie-3",
+					       "pcie-4";
+				nvidia,function = "pcie";
+				nvidia,iddq = <0>;
+			};
+
+			sata {
+				nvidia,lanes = "sata-0";
+				nvidia,function = "sata";
+				nvidia,iddq = <0>;
+			};
+		};
+	};
+
+	/* Apalis MMC1 */
+	sdhci@700b0000 {
+		status = "okay";
+		/* MMC1_CD# */
+		cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+		bus-width = <4>;
+		vqmmc-supply = <&vddio_sdmmc1>;
+	};
+
+	/* Apalis SD1 */
+	sdhci@700b0400 {
+		status = "okay";
+		/* SD1_CD# */
+		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+		bus-width = <4>;
+		vqmmc-supply = <&vddio_sdmmc3>;
+	};
+
+	/* eMMC */
+	sdhci@700b0600 {
+		status = "okay";
+		bus-width = <8>;
+		non-removable;
+	};
+
+	/* CPU DFLL clock */
+	clock@70110000 {
+		status = "okay";
+		vdd-cpu-supply = <&vdd_cpu>;
+		nvidia,i2c-fs-rate = <400000>;
+	};
+
+	ahub@70300000 {
+		i2s@70301200 {
+			status = "okay";
+		};
+	};
+
+	/* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
+	usb@7d000000 {
+		status = "okay";
+		dr_mode = "otg";
+	};
+
+	usb-phy@7d000000 {
+		status = "okay";
+		vbus-supply = <&reg_usbo1_vbus>;
+	};
+
+	/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
+	usb@7d004000 {
+		status = "okay";
+	};
+
+	usb-phy@7d004000 {
+		status = "okay";
+		vbus-supply = <&reg_usbh_vbus>;
+	};
+
+	/* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */
+	usb@7d008000 {
+		status = "okay";
+	};
+
+	usb-phy@7d008000 {
+		status = "okay";
+		vbus-supply = <&reg_usbh_vbus>;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		/* BKL1_PWM */
+		pwms = <&pwm 3 5000000>;
+		brightness-levels = <255 231 223 207 191 159 127 0>;
+		default-brightness-level = <6>;
+		/* BKL1_ON */
+		enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>;
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clk32k_in: clock@0 {
+			compatible = "fixed-clock";
+			reg = <0>;
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+
+	cpus {
+		cpu@0 {
+			vdd-cpu-supply = <&vdd_cpu>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		wakeup {
+			label = "WAKE1_MICO";
+			gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WAKEUP>;
+			debounce-interval = <10>;
+			wakeup-source;
+		};
+	};
+
+	reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
+		compatible = "regulator-fixed";
+		regulator-name = "+V1.05_AVDD_HDMI_PLL";
+		regulator-min-microvolt = <1050000>;
+		regulator-max-microvolt = <1050000>;
+		gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+		vin-supply = <&vdd_1v05>;
+	};
+
+	reg_3v3_mxm: regulator-3v3-mxm {
+		compatible = "regulator-fixed";
+		regulator-name = "+V3.3_MXM";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	reg_3v3: regulator-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "+V3.3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+		/* PWR_EN_+V3.3 */
+		gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&reg_3v3_mxm>;
+	};
+
+	reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
+		compatible = "regulator-fixed";
+		regulator-name = "+V3.3_AVDD_HDMI";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vdd_1v05>;
+	};
+
+	reg_5v0: regulator-5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "5V_SW";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	/* USBO1_EN */
+	reg_usbo1_vbus: regulator-usbo1-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_USBO1";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&reg_5v0>;
+	};
+
+	/* USBH_EN */
+	reg_usbh_vbus: regulator-usbh-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&reg_5v0>;
+	};
+
+	sound {
+		compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
+			     "nvidia,tegra-audio-sgtl5000";
+		nvidia,model = "Toradex Apalis TK1";
+		nvidia,audio-routing =
+			"Headphone Jack", "HP_OUT",
+			"LINE_IN", "Line In Jack",
+			"MIC_IN", "Mic Jack";
+		nvidia,i2s-controller = <&tegra_i2s2>;
+		nvidia,audio-codec = <&sgtl5000>;
+		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA124_CLK_EXTERN1>;
+		clock-names = "pll_a", "pll_a_out0", "mclk";
+	};
+
+	thermal-zones {
+		cpu {
+			trips {
+				trip@0 {
+					temperature = <101000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				/*
+				 * There are currently no cooling maps because
+				 * there are no cooling devices
+				 */
+			};
+		};
+
+		mem {
+			trips {
+				trip@0 {
+					temperature = <101000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				/*
+				 * There are currently no cooling maps because
+				 * there are no cooling devices
+				 */
+			};
+		};
+
+		gpu {
+			trips {
+				trip@0 {
+					temperature = <101000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				/*
+				 * There are currently no cooling maps because
+				 * there are no cooling devices
+				 */
+			};
+		};
+	};
+};
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index dbed776..54f449f 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -66,29 +66,9 @@
 #define PRM_RSTCTRL_RESET		0x01
 #define PRM_RSTST_WARM_RESET_MASK	0x232
 
-/*
- * Watchdog:
- * Using the prescaler, the OMAP watchdog could go for many
- * months before firing.  These limits work without scaling,
- * with the 60 second default assumed by most tools and docs.
- */
-#define TIMER_MARGIN_MAX	(24 * 60 * 60)	/* 1 day */
-#define TIMER_MARGIN_DEFAULT	60	/* 60 secs */
-#define TIMER_MARGIN_MIN	1
-
-#define PTV			0	/* prescale */
-#define GET_WLDR_VAL(secs)	(0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
-#define WDT_WWPS_PEND_WCLR	BIT(0)
-#define WDT_WWPS_PEND_WLDR	BIT(2)
-#define WDT_WWPS_PEND_WTGR	BIT(3)
-#define WDT_WWPS_PEND_WSPR	BIT(4)
-
-#define WDT_WCLR_PRE		BIT(5)
-#define WDT_WCLR_PTV_OFF	2
-
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
-
+#include <asm/ti-common/omap_wdt.h>
 
 #ifndef CONFIG_AM43XX
 /* Encapsulating core pll registers */
@@ -422,32 +402,6 @@ struct cm_rtc {
 	unsigned int clkstctrl;		/* offset 0x4 */
 };
 
-/* Watchdog timer registers */
-struct wd_timer {
-	unsigned int resv1[4];
-	unsigned int wdtwdsc;	/* offset 0x010 */
-	unsigned int wdtwdst;	/* offset 0x014 */
-	unsigned int wdtwisr;	/* offset 0x018 */
-	unsigned int wdtwier;	/* offset 0x01C */
-	unsigned int wdtwwer;	/* offset 0x020 */
-	unsigned int wdtwclr;	/* offset 0x024 */
-	unsigned int wdtwcrr;	/* offset 0x028 */
-	unsigned int wdtwldr;	/* offset 0x02C */
-	unsigned int wdtwtgr;	/* offset 0x030 */
-	unsigned int wdtwwps;	/* offset 0x034 */
-	unsigned int resv2[3];
-	unsigned int wdtwdly;	/* offset 0x044 */
-	unsigned int wdtwspr;	/* offset 0x048 */
-	unsigned int resv3[1];
-	unsigned int wdtwqeoi;	/* offset 0x050 */
-	unsigned int wdtwqstar;	/* offset 0x054 */
-	unsigned int wdtwqsta;	/* offset 0x058 */
-	unsigned int wdtwqens;	/* offset 0x05C */
-	unsigned int wdtwqenc;	/* offset 0x060 */
-	unsigned int resv4[39];
-	unsigned int wdt_unfr;	/* offset 0x100 */
-};
-
 /* Timer 32 bit registers */
 struct gptimer {
 	unsigned int tidr;		/* offset 0x00 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index d9d948e..70181c5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -48,10 +48,10 @@ enum srds_prtcl {
 	SGMII14,
 	SGMII15,
 	SGMII16,
-	QSGMII_A, /* A indicates MACs 1-4 */
-	QSGMII_B, /* B indicates MACs 5-8 */
-	QSGMII_C, /* C indicates MACs 9-12 */
-	QSGMII_D, /* D indicates MACs 12-16 */
+	QSGMII_A,
+	QSGMII_B,
+	QSGMII_C,
+	QSGMII_D,
 	SERDES_PRCTL_COUNT
 };
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 08ea8fb..80c421f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -230,10 +230,19 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK	0x3f
 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT	18
 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK	0x3f
+
+#if defined(CONFIG_ARCH_LS2080A)
 #define	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK	0x00FF0000
 #define	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT	16
 #define	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK	0xFF000000
 #define	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT	24
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS2_PRTCL_MASK	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR	29
+#define FSL_CHASSIS3_SRDS2_REGSR	29
+#endif
 #define RCW_SB_EN_REG_INDEX	9
 #define RCW_SB_EN_MASK		0x00000400
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ppa.h b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h
index 1f1442b..da4098e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ppa.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h
@@ -7,10 +7,7 @@
 #ifndef __FSL_PPA_H_
 #define __FSL_PPA_H_
 
-#define SEC_FIRMWARE_FIT_IMAGE		"firmware"
-#define SEC_FIRMEWARE_FIT_CNF_NAME	"config@1"
-#define SEC_FIRMWARE_TARGET_EL		2
-
+#ifdef CONFIG_FSL_LS_PPA
 int ppa_init(void);
-
+#endif
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
new file mode 100644
index 0000000..b326fe5
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 NXP Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+#ifndef __FSL_STREAM_ID_H
+#define __FSL_STREAM_ID_H
+
+/*
+ * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices
+ * are not hardwired and are programmed by sw.  There are a limited number
+ * of stream IDs available, and the partitioning of them is scenario
+ * dependent. This header defines the partitioning between legacy, PCI,
+ * and DPAA1 devices.
+ *
+ * This partitioning can be customized in this file depending
+ * on the specific hardware config:
+ *
+ *  -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc)
+ *     -all legacy devices get a unique stream ID assigned and programmed in
+ *      their AMQR registers by u-boot
+ *
+ *  -PCIe
+ *     -there is a range of stream IDs set aside for PCI in this
+ *      file.  U-boot will scan the PCI bus and for each device discovered:
+ *         -allocate a streamID
+ *         -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
+ *         -set a msi-map entry in the PEXn controller node in the
+ *          device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
+ *          for more info on the msi-map definition)
+ *         -set a iommu-map entry in the PEXn controller node in the
+ *          device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
+ *          for more info on the iommu-map definition)
+ *
+ *  -DPAA1
+ *     - Stream ids for DPAA1 use are reserved for future usecase.
+ *
+ */
+
+
+#define FSL_INVALID_STREAM_ID		0
+
+/* legacy devices */
+#define FSL_USB1_STREAM_ID		1
+#define FSL_USB2_STREAM_ID		2
+#define FSL_USB3_STREAM_ID		3
+#define FSL_SDHC_STREAM_ID		4
+#define FSL_SATA_STREAM_ID		5
+#define FSL_QE_STREAM_ID		6
+#define FSL_QDMA_STREAM_ID		7
+#define FSL_EDMA_STREAM_ID		8
+#define FSL_ETR_STREAM_ID		9
+
+/* PCI - programmed in PEXn_LUT */
+#define FSL_PEX_STREAM_ID_START		11
+#define FSL_PEX_STREAM_ID_END		26
+
+/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */
+#define FSL_DPAA1_STREAM_ID_START	27
+#define FSL_DPAA1_STREAM_ID_END		63
+
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index ee28323..d7d527d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -8,11 +8,11 @@
 #define __FSL_STREAM_ID_H
 
 /*
- * Stream IDs on ls2080a devices are not hardwired and are
- * programmed by sw.  There are a limited number of stream IDs
- * available, and the partitioning of them is scenario dependent.
- * This header defines the partitioning between legacy, PCI,
- * and DPAA2 devices.
+ * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a)
+ * devices are not hardwired and are programmed by sw. There are a limited
+ * number of stream IDs available, and the partitioning of them is scenario
+ * dependent. This header defines the partitioning between legacy,
+ * PCI, and DPAA2 devices.
  *
  * This partitioning can be customized in this file depending
  * on the specific hardware config:
@@ -29,6 +29,9 @@
  *         -set a msi-map entry in the PEXn controller node in the
  *          device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
  *          for more info on the msi-map definition)
+ *         -set a iommu-map entry in the PEXn controller node in the
+ *          device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
+ *          for more info on the iommu-map definition)
  *
  *  -DPAA2
  *     -u-boot will allocate a range of stream IDs to be used by the Management
@@ -36,7 +39,7 @@
  *     -the MC is responsible for allocating and setting up 'isolation context
  *      IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
  *
- * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for
+ * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for
  * each of the different bus masters.  The relationship between
  * the AMQ registers and stream IDs is defined in the table below:
  *          AMQ bit    streamID bit
diff --git a/arch/arm/include/asm/arch-lpc32xx/i2c.h b/arch/arm/include/asm/arch-lpc32xx/i2c.h
new file mode 100644
index 0000000..5301d4c
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/i2c.h
@@ -0,0 +1,37 @@
+#ifndef _LPC32XX_I2C_H
+#define _LPC32XX_I2C_H
+
+#include <common.h>
+#include <asm/types.h>
+
+/* i2c register set */
+struct lpc32xx_i2c_base {
+	union {
+		u32 rx;
+		u32 tx;
+	};
+	u32 stat;
+	u32 ctrl;
+	u32 clk_hi;
+	u32 clk_lo;
+	u32 adr;
+	u32 rxfl;
+	u32 txfl;
+	u32 rxb;
+	u32 txb;
+	u32 stx;
+	u32 stxfl;
+};
+
+#ifdef CONFIG_DM_I2C
+enum {
+	I2C_0, I2C_1, I2C_2,
+};
+
+struct lpc32xx_i2c_dev {
+	struct lpc32xx_i2c_base *base;
+	int index;
+	uint speed;
+};
+#endif /* CONFIG_DM_I2C */
+#endif /* _LPC32XX_I2C_H */
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index 683d905..26e7417 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -18,6 +18,8 @@
 
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
+#include <asm/ti-common/omap_wdt.h>
+
 struct gptimer {
 	u32 tidr;		/* 0x00 r */
 	u8 res1[0xc];
@@ -44,6 +46,7 @@ struct gptimer {
 /* enable sys_clk NO-prescale /1 */
 #define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
 
+#define WDT_BASE                (OMAP54XX_L4_WKUP_BASE + 0x14000)
 /* Watchdog */
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h
index 9dd03c9..48e8ca5 100644
--- a/arch/arm/include/asm/arch-omap5/gpio.h
+++ b/arch/arm/include/asm/arch-omap5/gpio.h
@@ -34,4 +34,8 @@
 #define OMAP54XX_GPIO7_BASE		0x48051000
 #define OMAP54XX_GPIO8_BASE		0x48053000
 
+
+/* Get the GPIO index from the given bank number and bank gpio */
+#define GPIO_TO_PIN(bank, bank_gpio)	(32 * (bank - 1) + (bank_gpio))
+
 #endif /* _GPIO_OMAP5_H */
diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h
new file mode 100644
index 0000000..8d7bc9a
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/boot0.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Execution starts on the instruction following this 4-byte header
+ * (containing the magic 'RK33').
+ *
+ * To make life easier for everyone, we build the SPL binary with
+ * space for this 4-byte header already included in the binary.
+ */
+
+#ifdef CONFIG_SPL_BUILD
+	.space 0x4         /* space for the 'RK33' */
+#endif
+	b reset
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h
index 74f0fed..f5d6420 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h
@@ -9,6 +9,7 @@
 #define OSC_HZ		(24 * 1000 * 1000)
 
 #define APLL_HZ		(1608 * 1000000)
+#define APLL_SAFE_HZ	(600 * 1000000)
 #define GPLL_HZ		(594 * 1000000)
 #define CPLL_HZ		(384 * 1000000)
 
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index aaffd19..1a7c819 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -720,20 +720,20 @@ enum {
 
 /* GRF_SOC_CON1 */
 enum {
-	RMII_MODE_SHIFT = 0xe,
-	RMII_MODE_MASK = 1,
-	RMII_MODE = 1,
+	RK3288_RMII_MODE_SHIFT = 14,
+	RK3288_RMII_MODE_MASK  = (1 << RK3288_RMII_MODE_SHIFT),
+	RK3288_RMII_MODE       = (1 << RK3288_RMII_MODE_SHIFT),
 
-	GMAC_CLK_SEL_SHIFT	= 0xc,
-	GMAC_CLK_SEL_MASK	= 3,
-	GMAC_CLK_SEL_125M	= 0,
-	GMAC_CLK_SEL_25M	= 0x3,
-	GMAC_CLK_SEL_2_5M	= 0x2,
+	RK3288_GMAC_CLK_SEL_SHIFT = 12,
+	RK3288_GMAC_CLK_SEL_MASK  = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
+	RK3288_GMAC_CLK_SEL_125M  = (0 << RK3288_GMAC_CLK_SEL_SHIFT),
+	RK3288_GMAC_CLK_SEL_25M   = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
+	RK3288_GMAC_CLK_SEL_2_5M  = (2 << RK3288_GMAC_CLK_SEL_SHIFT),
 
-	RMII_CLK_SEL_SHIFT	= 0xb,
-	RMII_CLK_SEL_MASK	= 1,
-	RMII_CLK_SEL_2_5M	= 0,
-	RMII_CLK_SEL_25M,
+	RK3288_RMII_CLK_SEL_SHIFT = 11,
+	RK3288_RMII_CLK_SEL_MASK  = (1 << RK3288_RMII_CLK_SEL_SHIFT),
+	RK3288_RMII_CLK_SEL_2_5M  = (0 << RK3288_RMII_CLK_SEL_SHIFT),
+	RK3288_RMII_CLK_SEL_25M   = (1 << RK3288_RMII_CLK_SEL_SHIFT),
 
 	GMAC_SPEED_SHIFT	= 0xa,
 	GMAC_SPEED_MASK		= 1,
@@ -743,10 +743,10 @@ enum {
 	GMAC_FLOWCTRL_SHIFT	= 0x9,
 	GMAC_FLOWCTRL_MASK	= 1,
 
-	GMAC_PHY_INTF_SEL_SHIFT	= 0x6,
-	GMAC_PHY_INTF_SEL_MASK	= 0x7,
-	GMAC_PHY_INTF_SEL_RGMII	= 0x1,
-	GMAC_PHY_INTF_SEL_RMII	= 0x4,
+	RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,
+	RK3288_GMAC_PHY_INTF_SEL_MASK  = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3288_GMAC_PHY_INTF_SEL_RMII  = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
 
 	HOST_REMAP_SHIFT	= 0x5,
 	HOST_REMAP_MASK		= 1
@@ -801,21 +801,27 @@ enum {
 
 /* GRF_SOC_CON3 */
 enum {
-	RXCLK_DLY_ENA_GMAC_SHIFT	= 0xf,
-	RXCLK_DLY_ENA_GMAC_MASK		= 1,
-	RXCLK_DLY_ENA_GMAC_DISABLE	= 0,
-	RXCLK_DLY_ENA_GMAC_ENABLE,
-
-	TXCLK_DLY_ENA_GMAC_SHIFT	= 0xe,
-	TXCLK_DLY_ENA_GMAC_MASK		= 1,
-	TXCLK_DLY_ENA_GMAC_DISABLE	= 0,
-	TXCLK_DLY_ENA_GMAC_ENABLE,
-
-	CLK_RX_DL_CFG_GMAC_SHIFT	= 0x7,
-	CLK_RX_DL_CFG_GMAC_MASK		= 0x7f,
-
-	CLK_TX_DL_CFG_GMAC_SHIFT	= 0x0,
-	CLK_TX_DL_CFG_GMAC_MASK		= 0x7f,
+	RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf,
+	RK3288_RXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3288_RXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe,
+	RK3288_TXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+	RK3288_CLK_RX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT),
+
+	RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+	RK3288_CLK_TX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT),
 };
 
 #endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index 62d8496..b340b05 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -144,7 +144,9 @@ struct rk3399_grf_regs {
 	};
 	u32 gpio4d_iomux;
 	u32 reserved21[4];
-	u32 gpio2_p[3][4];
+	u32 gpio2_p[4];
+	u32 gpio3_p[4];
+	u32 gpio4_p[4];
 	u32 reserved22[4];
 	u32 gpio2_sr[3][4];
 	u32 reserved23[4];
@@ -215,7 +217,9 @@ struct rk3399_pmugrf_regs {
 	};
 	u32 gpio1d_iomux;
 	u32 reserved1[8];
-	u32 gpio0_p[2][4];
+	u32 gpio0_p[2];
+	u32 reserved2[2];
+	u32 gpio1_p[4];
 	u32 reserved3[8];
 	u32 gpio0a_e;
 	u32 reserved4;
@@ -334,23 +338,60 @@ enum {
 	GRF_SPI2TPM_CSN0	= 1,
 
 	/* GRF_GPIO3A_IOMUX */
+	GRF_GPIO3A0_SEL_SHIFT   = 0,
+	GRF_GPIO3A0_SEL_MASK    = 3 << GRF_GPIO3A0_SEL_SHIFT,
+	GRF_MAC_TXD2            = 1,
+	GRF_GPIO3A1_SEL_SHIFT   = 2,
+	GRF_GPIO3A1_SEL_MASK    = 3 << GRF_GPIO3A1_SEL_SHIFT,
+	GRF_MAC_TXD3            = 1,
+	GRF_GPIO3A2_SEL_SHIFT   = 4,
+	GRF_GPIO3A2_SEL_MASK    = 3 << GRF_GPIO3A2_SEL_SHIFT,
+	GRF_MAC_RXD2            = 1,
+	GRF_GPIO3A3_SEL_SHIFT   = 6,
+	GRF_GPIO3A3_SEL_MASK    = 3 << GRF_GPIO3A3_SEL_SHIFT,
+	GRF_MAC_RXD3            = 1,
 	GRF_GPIO3A4_SEL_SHIFT	= 8,
 	GRF_GPIO3A4_SEL_MASK	= 3 << GRF_GPIO3A4_SEL_SHIFT,
+	GRF_MAC_TXD0            = 1,
 	GRF_SPI0NORCODEC_RXD	= 2,
 	GRF_GPIO3A5_SEL_SHIFT	= 10,
 	GRF_GPIO3A5_SEL_MASK	= 3 << GRF_GPIO3A5_SEL_SHIFT,
+	GRF_MAC_TXD1            = 1,
 	GRF_SPI0NORCODEC_TXD	= 2,
 	GRF_GPIO3A6_SEL_SHIFT	= 12,
 	GRF_GPIO3A6_SEL_MASK	= 3 << GRF_GPIO3A6_SEL_SHIFT,
+	GRF_MAC_RXD0            = 1,
 	GRF_SPI0NORCODEC_CLK	= 2,
 	GRF_GPIO3A7_SEL_SHIFT	= 14,
 	GRF_GPIO3A7_SEL_MASK	= 3 << GRF_GPIO3A7_SEL_SHIFT,
+	GRF_MAC_RXD1            = 1,
 	GRF_SPI0NORCODEC_CSN0	= 2,
 
 	/* GRF_GPIO3B_IOMUX */
 	GRF_GPIO3B0_SEL_SHIFT	= 0,
 	GRF_GPIO3B0_SEL_MASK	= 3 << GRF_GPIO3B0_SEL_SHIFT,
+	GRF_MAC_MDC             = 1,
 	GRF_SPI0NORCODEC_CSN1	= 2,
+	GRF_GPIO3B1_SEL_SHIFT	= 2,
+	GRF_GPIO3B1_SEL_MASK	= 3 << GRF_GPIO3B1_SEL_SHIFT,
+	GRF_MAC_RXDV            = 1,
+	GRF_GPIO3B3_SEL_SHIFT	= 6,
+	GRF_GPIO3B3_SEL_MASK	= 3 << GRF_GPIO3B3_SEL_SHIFT,
+	GRF_MAC_CLK             = 1,
+	GRF_GPIO3B4_SEL_SHIFT	= 8,
+	GRF_GPIO3B4_SEL_MASK	= 3 << GRF_GPIO3B4_SEL_SHIFT,
+	GRF_MAC_TXEN            = 1,
+	GRF_GPIO3B5_SEL_SHIFT	= 10,
+	GRF_GPIO3B5_SEL_MASK	= 3 << GRF_GPIO3B5_SEL_SHIFT,
+	GRF_MAC_MDIO            = 1,
+	GRF_GPIO3B6_SEL_SHIFT   = 12,
+	GRF_GPIO3B6_SEL_MASK    = 3 << GRF_GPIO3B6_SEL_SHIFT,
+	GRF_MAC_RXCLK           = 1,
+
+	/* GRF_GPIO3C_IOMUX */
+	GRF_GPIO3C1_SEL_SHIFT	= 2,
+	GRF_GPIO3C1_SEL_MASK	= 3 << GRF_GPIO3C1_SEL_SHIFT,
+	GRF_MAC_TXCLK           = 1,
 
 	/* GRF_GPIO4B_IOMUX */
 	GRF_GPIO4B0_SEL_SHIFT	= 0,
@@ -436,4 +477,43 @@ enum {
 
 };
 
+/* GRF_SOC_CON5 */
+enum {
+	RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9,
+	RK3399_GMAC_PHY_INTF_SEL_MASK  = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3399_GMAC_PHY_INTF_SEL_RMII  = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+
+	RK3399_GMAC_CLK_SEL_SHIFT = 4,
+	RK3399_GMAC_CLK_SEL_MASK  = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
+	RK3399_GMAC_CLK_SEL_125M  = (0 << RK3399_GMAC_CLK_SEL_SHIFT),
+	RK3399_GMAC_CLK_SEL_25M	  = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
+	RK3399_GMAC_CLK_SEL_2_5M  = (2 << RK3399_GMAC_CLK_SEL_SHIFT),
+};
+
+/* GRF_SOC_CON6 */
+enum {
+	RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15,
+	RK3399_RXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3399_RXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3399_TXCLK_DLY_ENA_GMAC_SHIFT	= 7,
+	RK3399_TXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3399_TXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
+	RK3399_CLK_RX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT),
+
+	RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
+	RK3399_CLK_TX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT),
+};
+
 #endif	/* __SOC_ROCKCHIP_RK3399_GRF_H__ */
diff --git a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h b/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
deleted file mode 100644
index 0b51d40..0000000
--- a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- * Copyright 2014 Rockchip Inc.
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_HDMI_H
-#define _ASM_ARCH_HDMI_H
-
-
-#define HDMI_EDID_BLOCK_SIZE            128
-
-struct rk3288_hdmi {
-	u32 reserved0[0x100];
-	u32 ih_fc_stat0;
-	u32 ih_fc_stat1;
-	u32 ih_fc_stat2;
-	u32 ih_as_stat0;
-	u32 ih_phy_stat0;
-	u32 ih_i2cm_stat0;
-	u32 ih_cec_stat0;
-	u32 ih_vp_stat0;
-	u32 ih_i2cmphy_stat0;
-	u32 ih_ahbdmaaud_stat0;
-	u32 reserved1[0x17f-0x109];
-	u32 ih_mute_fc_stat0;
-	u32 ih_mute_fc_stat1;
-	u32 ih_mute_fc_stat2;
-	u32 ih_mute_as_stat0;
-	u32 ih_mute_phy_stat0;
-	u32 ih_mute_i2cm_stat0;
-	u32 ih_mute_cec_stat0;
-	u32 ih_mute_vp_stat0;
-	u32 ih_mute_i2cmphy_stat0;
-	u32 ih_mute_ahbdmaaud_stat0;
-	u32 reserved2[0x1fe - 0x189];
-	u32 ih_mute;
-	u32 tx_invid0;
-	u32 tx_instuffing;
-	u32 tx_gydata0;
-	u32 tx_gydata1;
-	u32 tx_rcrdata0;
-	u32 tx_rcrdata1;
-	u32 tx_bcbdata0;
-	u32 tx_bcbdata1;
-	u32 reserved3[0x7ff-0x207];
-	u32 vp_status;
-	u32 vp_pr_cd;
-	u32 vp_stuff;
-	u32 vp_remap;
-	u32 vp_conf;
-	u32 vp_stat;
-	u32 vp_int;
-	u32 vp_mask;
-	u32 vp_pol;
-	u32 reserved4[0xfff-0x808];
-	u32 fc_invidconf;
-	u32 fc_inhactv0;
-	u32 fc_inhactv1;
-	u32 fc_inhblank0;
-	u32 fc_inhblank1;
-	u32 fc_invactv0;
-	u32 fc_invactv1;
-	u32 fc_invblank;
-	u32 fc_hsyncindelay0;
-	u32 fc_hsyncindelay1;
-	u32 fc_hsyncinwidth0;
-	u32 fc_hsyncinwidth1;
-	u32 fc_vsyncindelay;
-	u32 fc_vsyncinwidth;
-	u32 fc_infreq0;
-	u32 fc_infreq1;
-	u32 fc_infreq2;
-	u32 fc_ctrldur;
-	u32 fc_exctrldur;
-	u32 fc_exctrlspac;
-	u32 fc_ch0pream;
-	u32 fc_ch1pream;
-	u32 fc_ch2pream;
-	u32 fc_aviconf3;
-	u32 fc_gcp;
-	u32 fc_aviconf0;
-	u32 fc_aviconf1;
-	u32 fc_aviconf2;
-	u32 fc_avivid;
-	u32 fc_avietb0;
-	u32 fc_avietb1;
-	u32 fc_avisbb0;
-	u32 fc_avisbb1;
-	u32 fc_avielb0;
-	u32 fc_avielb1;
-	u32 fc_avisrb0;
-	u32 fc_avisrb1;
-	u32 fc_audiconf0;
-	u32 fc_audiconf1;
-	u32 fc_audiconf2;
-	u32 fc_audiconf3;
-	u32 fc_vsdieeeid0;
-	u32 fc_vsdsize;
-	u32 reserved7[0x2fff-0x102a];
-	u32 phy_conf0;
-	u32 phy_tst0;
-	u32 phy_tst1;
-	u32 phy_tst2;
-	u32 phy_stat0;
-	u32 phy_int0;
-	u32 phy_mask0;
-	u32 phy_pol0;
-	u32 reserved8[0x301f-0x3007];
-	u32 phy_i2cm_slave_addr;
-	u32 phy_i2cm_address_addr;
-	u32 phy_i2cm_datao_1_addr;
-	u32 phy_i2cm_datao_0_addr;
-	u32 phy_i2cm_datai_1_addr;
-	u32 phy_i2cm_datai_0_addr;
-	u32 phy_i2cm_operation_addr;
-	u32 phy_i2cm_int_addr;
-	u32 phy_i2cm_ctlint_addr;
-	u32 phy_i2cm_div_addr;
-	u32 phy_i2cm_softrstz_addr;
-	u32 phy_i2cm_ss_scl_hcnt_1_addr;
-	u32 phy_i2cm_ss_scl_hcnt_0_addr;
-	u32 phy_i2cm_ss_scl_lcnt_1_addr;
-	u32 phy_i2cm_ss_scl_lcnt_0_addr;
-	u32 phy_i2cm_fs_scl_hcnt_1_addr;
-	u32 phy_i2cm_fs_scl_hcnt_0_addr;
-	u32 phy_i2cm_fs_scl_lcnt_1_addr;
-	u32 phy_i2cm_fs_scl_lcnt_0_addr;
-	u32 reserved9[0x30ff-0x3032];
-	u32 aud_conf0;
-	u32 aud_conf1;
-	u32 aud_int;
-	u32 aud_conf2;
-	u32 aud_int1;
-	u32 reserved32[0x31ff-0x3104];
-	u32 aud_n1;
-	u32 aud_n2;
-	u32 aud_n3;
-	u32 aud_cts1;
-	u32 aud_cts2;
-	u32 aud_cts3;
-	u32 aud_inputclkfs;
-	u32 reserved12[0x3fff-0x3206];
-	u32 mc_sfrdiv;
-	u32 mc_clkdis;
-	u32 mc_swrstz;
-	u32 mc_opctrl;
-	u32 mc_flowctrl;
-	u32 mc_phyrstz;
-	u32 mc_lockonclock;
-	u32 mc_heacphy_rst;
-	u32 reserved13[0x40ff-0x4007];
-	u32 csc_cfg;
-	u32 csc_scale;
-	struct {
-		u32 msb;
-		u32 lsb;
-	} csc_coef[3][4];
-	u32 reserved17[0x7dff-0x4119];
-	u32 i2cm_slave;
-	u32 i2c_address;
-	u32 i2cm_datao;
-	u32 i2cm_datai;
-	u32 i2cm_operation;
-	u32 i2cm_int;
-	u32 i2cm_ctlint;
-	u32 i2cm_div;
-	u32 i2cm_segaddr;
-	u32 i2cm_softrstz;
-	u32 i2cm_segptr;
-	u32 i2cm_ss_scl_hcnt_1_addr;
-	u32 i2cm_ss_scl_hcnt_0_addr;
-	u32 i2cm_ss_scl_lcnt_1_addr;
-	u32 i2cm_ss_scl_lcnt_0_addr;
-	u32 i2cm_fs_scl_hcnt_1_addr;
-	u32 i2cm_fs_scl_hcnt_0_addr;
-	u32 i2cm_fs_scl_lcnt_1_addr;
-	u32 i2cm_fs_scl_lcnt_0_addr;
-	u32 reserved18[0x7e1f-0x7e12];
-	u32 i2cm_buf0;
-};
-check_member(rk3288_hdmi, i2cm_buf0, 0x1f880);
-
-enum {
-	/* HDMI PHY registers define */
-	PHY_OPMODE_PLLCFG = 0x06,
-	PHY_CKCALCTRL = 0x05,
-	PHY_CKSYMTXCTRL = 0x09,
-	PHY_VLEVCTRL = 0x0e,
-	PHY_PLLCURRCTRL = 0x10,
-	PHY_PLLPHBYCTRL = 0x13,
-	PHY_PLLGMPCTRL = 0x15,
-	PHY_PLLCLKBISTPHASE = 0x17,
-	PHY_TXTERM = 0x19,
-
-	/* ih_phy_stat0 field values */
-	HDMI_IH_PHY_STAT0_HPD = 0x1,
-
-	/* ih_mute field values */
-	HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
-	HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
-
-	/* tx_invid0 field values */
-	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
-	HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
-	HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
-
-	/* tx_instuffing field values */
-	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
-	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
-	HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
-
-	/* vp_pr_cd field values */
-	HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
-	HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
-	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
-	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
-
-	/* vp_stuff field values */
-	HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
-	HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
-	HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
-	HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
-	HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
-	HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
-	HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
-	HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
-
-	/* vp_conf field values */
-	HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
-	HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
-	HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
-	HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
-	HDMI_VP_CONF_PR_EN_MASK = 0x10,
-	HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
-	HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
-	HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
-	HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
-	HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
-	HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
-	HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
-
-	/* vp_remap field values */
-	HDMI_VP_REMAP_YCC422_16BIT = 0x0,
-
-	/* fc_invidconf field values */
-	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
-	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
-	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
-	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
-	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
-	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
-	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
-	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
-	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
-	HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
-	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
-	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
-	HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
-	HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
-	HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
-	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
-	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
-	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
-	HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
-	HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
-	HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
-
-
-	/* fc_aviconf0-fc_aviconf3 field values */
-	HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
-	HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
-	HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
-	HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
-	HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
-	HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
-	HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
-	HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
-	HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
-	HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
-	HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
-	HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
-	HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
-	HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
-	HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
-	HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
-
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
-	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
-	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
-	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
-	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
-	HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
-	HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
-	HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
-	HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
-	HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
-
-	HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
-	HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
-	HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
-	HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
-	HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
-	HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
-	HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
-	HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
-	HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
-	HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
-	HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
-	HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
-
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
-	HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
-	HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
-	HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
-
-	/* fc_gcp field values*/
-	HDMI_FC_GCP_SET_AVMUTE = 0x02,
-	HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
-
-	/* phy_conf0 field values */
-	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
-	HDMI_PHY_CONF0_PDZ_OFFSET = 7,
-	HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
-	HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
-	HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
-	HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
-	HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
-	HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
-	HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
-	HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
-	HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
-	HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
-	HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
-	HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
-
-	/* phy_tst0 field values */
-	HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
-	HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
-
-	/* phy_stat0 field values */
-	HDMI_PHY_HPD = 0x02,
-	HDMI_PHY_TX_PHY_LOCK = 0x01,
-
-	/* phy_i2cm_slave_addr field values */
-	HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
-
-	/* phy_i2cm_operation_addr field values */
-	HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
-
-	/* hdmi_phy_i2cm_int_addr */
-	HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
-
-	/* hdmi_phy_i2cm_ctlint_addr */
-	HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
-	HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
-
-	/* aud_conf0 field values */
-	HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
-	HDMI_AUD_CONF0_I2S_SELECT = 0x20,
-	HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
-	HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
-	HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
-	HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
-
-	/* aud_conf0 field values */
-	HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
-	HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
-
-	/* aud_n3 field values */
-	HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
-	HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
-
-	/* aud_cts3 field values */
-	HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
-	HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
-	HDMI_AUD_CTS3_N_SHIFT_1 = 0,
-	HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
-	HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
-	HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
-	HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
-	HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
-	HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
-	HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
-
-	/* aud_inputclkfs filed values */
-	HDMI_AUD_INPUTCLKFS_128 = 0x0,
-
-	/* mc_clkdis field values */
-	HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
-	HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
-	HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
-
-	/* mc_swrstz field values */
-	HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
-	HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
-
-	/* mc_flowctrl field values */
-	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
-	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
-
-	/* mc_phyrstz field values */
-	HDMI_MC_PHYRSTZ_ASSERT = 0x0,
-	HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
-
-	/* mc_heacphy_rst field values */
-	HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
-
-	/* csc_cfg field values */
-	HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
-
-	/* csc_scale field values */
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xf0,
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
-	HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
-
-	/* i2cm filed values */
-	HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
-	HDMI_I2CM_SEGADDR_DDC = 0x30,
-	HDMI_I2CM_OPT_RD8_EXT = 0x8,
-	HDMI_I2CM_OPT_RD8 = 0x4,
-	HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
-	HDMI_I2CM_DIV_FAST_MODE = 0x8,
-	HDMI_I2CM_DIV_STD_MODE = 0x0,
-	HDMI_I2CM_SOFTRSTZ = 0x1,
-};
-
-/*
-struct display_timing;
-struct rk3288_grf;
-
-int rk_hdmi_init(struct rk3288_grf *grf, u32 vop_id);
-int rk_hdmi_enable(const struct display_timing *edid);
-int rk_hdmi_get_edid(struct rk3288_grf *grf, struct display_timing *edid);
-*/
-
-#endif
diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h
index fa6069b..239a274 100644
--- a/arch/arm/include/asm/arch-rockchip/periph.h
+++ b/arch/arm/include/asm/arch-rockchip/periph.h
@@ -38,6 +38,7 @@ enum periph_id {
 	PERIPH_ID_SDMMC1,
 	PERIPH_ID_SDMMC2,
 	PERIPH_ID_HDMI,
+	PERIPH_ID_GMAC,
 
 	PERIPH_ID_COUNT,
 
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 3f87672..1bfb48b 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -242,7 +242,7 @@ struct sunxi_ccm_reg {
 /* ahb_gate0 offsets */
 #define AHB_GATE_OFFSET_USB_OHCI1	30
 #define AHB_GATE_OFFSET_USB_OHCI0	29
-#ifdef CONFIG_MACH_SUN8I_H3
+#ifdef CONFIG_MACH_SUNXI_H3_H5
 /*
  * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
  * them 0 - 2 like they were called on older SoCs.
@@ -293,7 +293,7 @@ struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
 #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
-#ifdef CONFIG_MACH_SUN8I_H3
+#ifdef CONFIG_MACH_SUNXI_H3_H5
 /*
  * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
  * them 0 - 2 like they were called on older SoCs.
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index 6f96a97..e8e670e 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -15,5 +15,6 @@
 
 #define SOCID_A64	0x1689
 #define SOCID_H3	0x1680
+#define SOCID_H5	0x1718
 
 #endif /* _SUNXI_CPU_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 3c85222..ea672fe 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -56,7 +56,7 @@
 #define SUNXI_USB2_BASE			0x01c1c000
 #endif
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
 #define SUNXI_USBPHY_BASE		0x01c19000
 #define SUNXI_USB0_BASE			0x01c1a000
 #define SUNXI_USB1_BASE			0x01c1b000
@@ -94,7 +94,7 @@
 #define SUNXI_KEYPAD_BASE		0x01c23000
 #define SUNXI_TZPC_BASE			0x01c23400
 
-#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3) || \
+#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUNXI_H3_H5) || \
 defined(CONFIG_MACH_SUN50I)
 /* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */
 #define SUNXI_SIDC_BASE			0x01c14000
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index 53e6d47..1dc8220 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -24,7 +24,7 @@
 #include <asm/arch/dram_sun8i_a33.h>
 #elif defined(CONFIG_MACH_SUN8I_A83T)
 #include <asm/arch/dram_sun8i_a83t.h>
-#elif defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
+#elif defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
 #include <asm/arch/dram_sun8i_h3.h>
 #elif defined(CONFIG_MACH_SUN9I)
 #include <asm/arch/dram_sun9i.h>
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
index 5d7ab55..831d0c0 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -12,7 +12,7 @@
 #define SPL_SIGNATURE		"SPL" /* marks "sunxi" SPL header */
 #define SPL_HEADER_VERSION	1
 
-#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
+#ifdef CONFIG_SUNXI_HIGH_SRAM
 #define SPL_ADDR		0x10000
 #else
 #define SPL_ADDR		0x0
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index 64c848a..c40599a 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -108,6 +108,8 @@ struct tegra_mmc {
 #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT			8
 #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK			(0xff << 8)
 
+#define TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK			(1 << 17)
+
 #define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL			(1 << 0)
 #define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE			(1 << 1)
 #define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE			(1 << 2)
diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h
index 54d8a2b..ebf0f17 100644
--- a/arch/arm/include/asm/armv7m.h
+++ b/arch/arm/include/asm/armv7m.h
@@ -16,8 +16,15 @@
 .thumb
 #endif
 
-#define V7M_SCB_BASE		0xE000ED00
-#define V7M_MPU_BASE		0xE000ED90
+/* armv7m fixed base addresses */
+#define V7M_SCS_BASE		0xE000E000
+#define V7M_NVIC_BASE		(V7M_SCS_BASE + 0x0100)
+#define V7M_SCB_BASE		(V7M_SCS_BASE + 0x0D00)
+#define V7M_PROC_FTR_BASE	(V7M_SCS_BASE + 0x0D78)
+#define V7M_MPU_BASE		(V7M_SCS_BASE + 0x0D90)
+#define V7M_FPU_BASE		(V7M_SCS_BASE + 0x0F30)
+#define V7M_CACHE_MAINT_BASE	(V7M_SCS_BASE + 0x0F50)
+#define V7M_ACCESS_CNTL_BASE	(V7M_SCS_BASE + 0x0F90)
 
 #define V7M_SCB_VTOR		0x08
 
@@ -27,6 +34,18 @@ struct v7m_scb {
 	uint32_t icsr;		/* Interrupt Control and State Register */
 	uint32_t vtor;		/* Vector Table Offset Register */
 	uint32_t aircr;		/* App Interrupt and Reset Control Register */
+	uint32_t scr;		/* offset 0x10: System Control Register */
+	uint32_t ccr;		/* offset 0x14: Config and Control Register */
+	uint32_t shpr1;		/* offset 0x18: System Handler Priority Reg 1 */
+	uint32_t shpr2;		/* offset 0x1c: System Handler Priority Reg 2 */
+	uint32_t shpr3;		/* offset 0x20: System Handler Priority Reg 3 */
+	uint32_t shcrs;		/* offset 0x24: System Handler Control State */
+	uint32_t cfsr;		/* offset 0x28: Configurable Fault Status Reg */
+	uint32_t hfsr;		/* offset 0x2C: HardFault Status Register */
+	uint32_t res;		/* offset 0x30: reserved */
+	uint32_t mmar;		/* offset 0x34: MemManage Fault Address Reg */
+	uint32_t bfar;		/* offset 0x38: BusFault Address Reg */
+	uint32_t afsr;		/* offset 0x3C: Auxiliary Fault Status Reg */
 };
 #define V7M_SCB				((struct v7m_scb *)V7M_SCB_BASE)
 
@@ -39,6 +58,9 @@ struct v7m_scb {
 
 #define V7M_ICSR_VECTACT_MSK		0xFF
 
+#define V7M_CCR_DCACHE			16
+#define V7M_CCR_ICACHE			17
+
 struct v7m_mpu {
 	uint32_t type;		/* Type Register */
 	uint32_t ctrl;		/* Control Register */
diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h
index 5ae00fa..bcdb1b0 100644
--- a/arch/arm/include/asm/armv8/sec_firmware.h
+++ b/arch/arm/include/asm/armv8/sec_firmware.h
@@ -7,10 +7,6 @@
 #ifndef __SEC_FIRMWARE_H_
 #define __SEC_FIRMWARE_H_
 
-#ifdef CONFIG_FSL_LS_PPA
-#include <asm/arch/ppa.h>
-#endif
-
 int sec_firmware_init(const void *, u32 *, u32 *);
 int _sec_firmware_entry(const void *, u32 *, u32 *);
 bool sec_firmware_is_valid(const void *);
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index fd627c0..d98a1e8 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -38,11 +38,11 @@
  * in boot ROM of the SoC.
  * The feature is only applicable in case of NOR boot and is
  * not applicable in case of RAMBOOT (NAND, SD, SPI).
+ * For LS, this feature is available for all device if IE Table
+ * is copied to XIP memory
+ * Also, for LS, ISBC doesn't verify this table.
  */
-#ifndef CONFIG_ESBC_HDR_LS
-/* Current Key EXT feature not available in LS ESBC Header */
 #define CONFIG_FSL_ISBC_KEY_EXT
-#endif
 
 #endif
 
@@ -112,6 +112,8 @@
 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
 #ifdef CONFIG_LS1043A
 #define CONFIG_SYS_LS_PPA_ESBC_ADDR	0x600c0000
+#elif defined(CONFIG_FSL_LSCH3)
+#define CONFIG_SYS_LS_PPA_ESBC_ADDR     0x580c40000
 #endif
 #else
 #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 2034a5e..c1a70b1 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -767,9 +767,11 @@ static inline u8 is_dra72x(void)
 #define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
 #define OMAP_SRAM_SCRATCH_SYS_CTRL	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
 #define OMAP_SRAM_SCRATCH_BOOT_PARAMS	(SRAM_SCRATCH_SPACE_ADDR + 0x24)
-#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
-#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
-#define OMAP_SRAM_SCRATCH_SPACE_END	(OMAP_SRAM_SCRATCH_BOARD_EEPROM_END)
+#ifndef TI_SRAM_SCRATCH_BOARD_EEPROM_START
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
+#endif
+#define OMAP_SRAM_SCRATCH_SPACE_END	(TI_SRAM_SCRATCH_BOARD_EEPROM_END)
 
 /* Boot parameters */
 #define DEVICE_DATA_OFFSET	0x18
diff --git a/arch/arm/include/asm/ti-common/omap_wdt.h b/arch/arm/include/asm/ti-common/omap_wdt.h
new file mode 100644
index 0000000..b9f4c07
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/omap_wdt.h
@@ -0,0 +1,60 @@
+/*
+ * omap_wdt.h
+ *
+ * OMAP Watchdog header file
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __OMAP_WDT_H__
+#define __OMAP_WDT_H__
+
+/*
+ * Watchdog:
+ * Using the prescaler, the OMAP watchdog could go for many
+ * months before firing.  These limits work without scaling,
+ * with the 60 second default assumed by most tools and docs.
+ */
+#define TIMER_MARGIN_MAX	(24 * 60 * 60)	/* 1 day */
+#define TIMER_MARGIN_DEFAULT	60	/* 60 secs */
+#define TIMER_MARGIN_MIN	1
+
+#define PTV			0	/* prescale */
+#define GET_WLDR_VAL(secs)	(0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
+#define WDT_WWPS_PEND_WCLR	BIT(0)
+#define WDT_WWPS_PEND_WLDR	BIT(2)
+#define WDT_WWPS_PEND_WTGR	BIT(3)
+#define WDT_WWPS_PEND_WSPR	BIT(4)
+
+#define WDT_WCLR_PRE		BIT(5)
+#define WDT_WCLR_PTV_OFF	2
+
+/* Watchdog timer registers */
+struct wd_timer {
+	unsigned int resv1[4];
+	unsigned int wdtwdsc;	/* offset 0x010 */
+	unsigned int wdtwdst;	/* offset 0x014 */
+	unsigned int wdtwisr;	/* offset 0x018 */
+	unsigned int wdtwier;	/* offset 0x01C */
+	unsigned int wdtwwer;	/* offset 0x020 */
+	unsigned int wdtwclr;	/* offset 0x024 */
+	unsigned int wdtwcrr;	/* offset 0x028 */
+	unsigned int wdtwldr;	/* offset 0x02C */
+	unsigned int wdtwtgr;	/* offset 0x030 */
+	unsigned int wdtwwps;	/* offset 0x034 */
+	unsigned int resv2[3];
+	unsigned int wdtwdly;	/* offset 0x044 */
+	unsigned int wdtwspr;	/* offset 0x048 */
+	unsigned int resv3[1];
+	unsigned int wdtwqeoi;	/* offset 0x050 */
+	unsigned int wdtwqstar;	/* offset 0x054 */
+	unsigned int wdtwqsta;	/* offset 0x058 */
+	unsigned int wdtwqens;	/* offset 0x05C */
+	unsigned int wdtwqenc;	/* offset 0x060 */
+	unsigned int resv4[39];
+	unsigned int wdt_unfr;	/* offset 0x100 */
+};
+
+#endif /* __OMAP_WDT_H__ */
diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h
index 305a302..b931c22 100644
--- a/arch/arm/include/asm/u-boot-arm.h
+++ b/arch/arm/include/asm/u-boot-arm.h
@@ -36,7 +36,6 @@ int	arch_early_init_r(void);
 
 /* board/.../... */
 int	board_init(void);
-void	dram_init_banksize (void);
 void	board_quiesce_devices(void);
 
 /* cpu/.../interrupt.c */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index b95e105..6e96cfb 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -55,8 +55,10 @@ endif
 
 obj-y	+= cache.o
 ifndef CONFIG_ARM64
+ifndef CONFIG_CPU_V7M
 obj-y	+= cache-cp15.o
 endif
+endif
 
 obj-y	+= psci-dt.o
 
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 8125cf0..426bee6 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -14,6 +14,8 @@
 
 #include <common.h>
 #include <command.h>
+#include <dm/device.h>
+#include <dm/root.h>
 #include <image.h>
 #include <u-boot/zlib.h>
 #include <asm/byteorder.h>
@@ -91,6 +93,13 @@ static void announce_and_cleanup(int fake)
 
 	board_quiesce_devices();
 
+	/*
+	 * Call remove function of all devices with a removal flag set.
+	 * This may be useful for last-stage operations, like cancelling
+	 * of DMA operation or releasing device internal buffers.
+	 */
+	dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+
 	cleanup_before_linux();
 }
 
diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
index ed83043..066c172 100644
--- a/arch/arm/lib/interrupts.c
+++ b/arch/arm/lib/interrupts.c
@@ -26,75 +26,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_USE_IRQ
-int interrupt_init (void)
-{
-	unsigned long cpsr;
-
-	/*
-	 * setup up stacks if necessary
-	 */
-	IRQ_STACK_START = gd->irq_sp - 4;
-	IRQ_STACK_START_IN = gd->irq_sp + 8;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-
-
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     : "=r" (cpsr)
-			     :
-			     : "memory");
-
-	__asm__ __volatile__("msr cpsr_c, %0\n"
-			     "mov sp, %1\n"
-			     :
-			     : "r" (IRQ_MODE | I_BIT | F_BIT | (cpsr & ~FIQ_MODE)),
-			       "r" (IRQ_STACK_START)
-			     : "memory");
-
-	__asm__ __volatile__("msr cpsr_c, %0\n"
-			     "mov sp, %1\n"
-			     :
-			     : "r" (FIQ_MODE | I_BIT | F_BIT | (cpsr & ~IRQ_MODE)),
-			       "r" (FIQ_STACK_START)
-			     : "memory");
-
-	__asm__ __volatile__("msr cpsr_c, %0"
-			     :
-			     : "r" (cpsr)
-			     : "memory");
-
-	return arch_interrupt_init();
-}
-
-/* enable IRQ interrupts */
-void enable_interrupts (void)
-{
-	unsigned long temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "bic %0, %0, #0x80\n"
-			     "msr cpsr_c, %0"
-			     : "=r" (temp)
-			     :
-			     : "memory");
-}
-
-
-/*
- * disable IRQ/FIQ interrupts
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts (void)
-{
-	unsigned long old,temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "orr %1, %0, #0xc0\n"
-			     "msr cpsr_c, %1"
-			     : "=r" (old), "=r" (temp)
-			     :
-			     : "memory");
-	return (old & 0x80) == 0;
-}
-#else
 int interrupt_init (void)
 {
 	/*
@@ -113,8 +44,6 @@ int disable_interrupts (void)
 {
 	return 0;
 }
-#endif
-
 
 void bad_mode (void)
 {
@@ -212,7 +141,6 @@ void do_fiq (struct pt_regs *pt_regs)
 	bad_mode ();
 }
 
-#ifndef CONFIG_USE_IRQ
 void do_irq (struct pt_regs *pt_regs)
 {
 	efi_restore_gd();
@@ -220,4 +148,3 @@ void do_irq (struct pt_regs *pt_regs)
 	show_regs (pt_regs);
 	bad_mode ();
 }
-#endif
diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c
index 4614d26..737622d 100644
--- a/arch/arm/lib/stack.c
+++ b/arch/arm/lib/stack.c
@@ -25,14 +25,6 @@ int arch_reserve_stacks(void)
 	gd->irq_sp = gd->start_addr_sp;
 
 # if !defined(CONFIG_ARM64)
-#  ifdef CONFIG_USE_IRQ
-	gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
-	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
-	      CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp);
-
-	/* 8-byte alignment for ARM ABI compliance */
-	gd->start_addr_sp &= ~0x07;
-#  endif
 	/* leave 3 words for abort-stack, plus 1 for alignment */
 	gd->start_addr_sp -= 16;
 # endif
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index 9fe7415..f53b1e9 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -128,19 +128,6 @@ fiq:
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-
-#endif /* CONFIG_USE_IRQ */
-
 @
 @ IRQ stack frame.
 @
@@ -264,24 +251,6 @@ not_used:
 	bad_save_user_regs
 	bl	do_not_used
 
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
 
 	.align	5
 irq:
@@ -295,6 +264,4 @@ fiq:
 	bad_save_user_regs
 	bl	do_fiq
 
-#endif /* CONFIG_USE_IRQ */
-
 #endif	/* CONFIG_SPL_BUILD */
diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c
index e699d61..ec331ba 100644
--- a/arch/arm/mach-davinci/misc.c
+++ b/arch/arm/mach-davinci/misc.c
@@ -28,10 +28,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 #endif
 
@@ -105,7 +107,6 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
 #endif	/* CONFIG_DRIVER_TI_EMAC */
 
 #if defined(CONFIG_SOC_DA8XX)
-#ifndef CONFIG_USE_IRQ
 void irq_init(void)
 {
 	/*
@@ -120,7 +121,6 @@ void irq_init(void)
 	writel(0xffffffff, &davinci_aintc_regs->ecr2);
 	writel(0xffffffff, &davinci_aintc_regs->ecr3);
 }
-#endif
 
 /*
  * Enable PSC for various peripherals.
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index e1962c7..67f5fa0 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -15,6 +15,8 @@ config TARGET_K2L_EVM
 
 config TARGET_K2G_EVM
 	bool "TI Keystone 2 Galileo EVM"
+        select BOARD_LATE_INIT
+        select TI_I2C_BOARD_DETECT
 
 endchoice
 
diff --git a/arch/arm/mach-keystone/cmd_ddr3.c b/arch/arm/mach-keystone/cmd_ddr3.c
index ea78ad8..d3eab07 100644
--- a/arch/arm/mach-keystone/cmd_ddr3.c
+++ b/arch/arm/mach-keystone/cmd_ddr3.c
@@ -15,12 +15,13 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define DDR_MIN_ADDR		CONFIG_SYS_SDRAM_BASE
+#define STACKSIZE		(512 << 10)     /* 512 KiB */
 
 #define DDR_REMAP_ADDR		0x80000000
 #define ECC_START_ADDR1		((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
 
 #define ECC_END_ADDR1		(((gd->start_addr_sp - DDR_REMAP_ADDR - \
-				 CONFIG_STACKSIZE) >> 17) - 2)
+				 STACKSIZE) >> 17) - 2)
 
 #define DDR_TEST_BURST_SIZE	1024
 
diff --git a/arch/arm/mach-keystone/config.mk b/arch/arm/mach-keystone/config.mk
index 9ae1e9a..db556ea 100644
--- a/arch/arm/mach-keystone/config.mk
+++ b/arch/arm/mach-keystone/config.mk
@@ -5,9 +5,15 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
+include  $(srctree)/arch/arm/mach-omap2/config_secure.mk
+
 ifndef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ALL-y += u-boot_HS_MLO
+else
 ALL-y += MLO
 endif
+endif
 
 MKIMAGEFLAGS_u-boot-spl.gph = -A $(ARCH) -T gpimage -C none \
 	-a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n SPL
diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c
index 256f630..8100984 100644
--- a/arch/arm/mach-keystone/mon.c
+++ b/arch/arm/mach-keystone/mon.c
@@ -10,6 +10,7 @@
 #include <common.h>
 #include <command.h>
 #include <mach/mon.h>
+#include <spl.h>
 asm(".arch_extension sec\n\t");
 
 int mon_install(u32 addr, u32 dpsc, u32 freq)
@@ -61,3 +62,75 @@ int mon_power_off(int core_id)
 		: "cc", "r0", "r1", "memory");
 	return  result;
 }
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+#define KS2_HS_SEC_HEADER_LEN	0x60
+#define KS2_HS_SEC_TAG_OFFSET	0x34
+#define KS2_AUTH_CMD		130
+
+/**
+ * k2_hs_bm_auth() - Invokes security functions using a
+ * proprietary TI interface. This binary and source for
+ * this is available in the secure development package or
+ * SECDEV. For details on how to access this please refer
+ * doc/README.ti-secure
+ *
+ * @cmd: Secure monitor command
+ * @arg1: Argument for command
+ *
+ * returns non-zero value on success, zero on error
+ */
+static int k2_hs_bm_auth(int cmd, void *arg1)
+{
+	int result;
+
+	asm volatile (
+		"stmfd  r13!, {r4-r12, lr}\n"
+		"mov r0, %1\n"
+		"mov r1, %2\n"
+		"smc #2\n"
+		"ldmfd r13!, {r4-r12, lr}\n"
+		: "=&r" (result)
+		: "r" (cmd), "r" (arg1)
+		: "cc", "r0", "r1", "memory");
+
+	return  result;
+}
+
+void board_fit_image_post_process(void **p_image, size_t *p_size)
+{
+	int result = 0;
+	void *image = *p_image;
+
+	if (strncmp(image + KS2_HS_SEC_TAG_OFFSET, "KEYS", 4)) {
+		printf("No signature found in image!\n");
+		hang();
+	}
+
+	result = k2_hs_bm_auth(KS2_AUTH_CMD, image);
+	if (result == 0) {
+		printf("Authentication failed!\n");
+		hang();
+	}
+
+	/*
+	* Overwrite the image headers after authentication
+	* and decryption. Update size to reflect removal
+	* of header.
+	*/
+	memcpy(image, image + KS2_HS_SEC_HEADER_LEN, *p_size);
+	*p_size -= KS2_HS_SEC_HEADER_LEN;
+
+	/*
+	 * Output notification of successful authentication to re-assure the
+	 * user that the secure code is being processed as expected. However
+	 * suppress any such log output in case of building for SPL and booting
+	 * via YMODEM. This is done to avoid disturbing the YMODEM serial
+	 * protocol transactions.
+	 */
+	if (!(IS_ENABLED(CONFIG_SPL_BUILD) &&
+	      IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) &&
+	      spl_boot_device() == BOOT_DEVICE_UART))
+		printf("Authentication passed\n");
+}
+#endif
diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c
index f159cbf..273dbeb 100644
--- a/arch/arm/mach-meson/board.c
+++ b/arch/arm/mach-meson/board.c
@@ -34,11 +34,13 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	/* Reserve first 16 MiB of RAM for firmware */
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
 	gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024);
+
+	return 0;
 }
 
 void reset_cpu(ulong addr)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 412bda4..6ae54ef 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -74,8 +74,8 @@ config TARGET_CLEARFOG
 	bool "Support ClearFog"
 	select 88F6820
 
-config TARGET_MVEBU_DB_88F3720
-	bool "Support DB-88F3720 Armada 3720"
+config TARGET_MVEBU_ARMADA_37XX
+	bool "Support Armada 37xx platforms"
 	select ARMADA_3700
 
 config TARGET_DB_88F6720
@@ -112,11 +112,15 @@ config TARGET_THEADORABLE
 	select BOARD_LATE_INIT if USB
 	select MV78260
 
+config TARGET_CONTROLCENTERDC
+	bool "Support CONTROLCENTERDC"
+	select 88F6820
+
 endchoice
 
 config SYS_BOARD
 	default "clearfog" if TARGET_CLEARFOG
-	default "mvebu_db-88f3720" if TARGET_MVEBU_DB_88F3720
+	default "mvebu_armada-37xx" if TARGET_MVEBU_ARMADA_37XX
 	default "db-88f6720" if TARGET_DB_88F6720
 	default "db-88f6820-gp" if TARGET_DB_88F6820_GP
 	default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
@@ -128,7 +132,7 @@ config SYS_BOARD
 
 config SYS_CONFIG_NAME
 	default "clearfog" if TARGET_CLEARFOG
-	default "mvebu_db-88f3720" if TARGET_MVEBU_DB_88F3720
+	default "mvebu_armada-37xx" if TARGET_MVEBU_ARMADA_37XX
 	default "db-88f6720" if TARGET_DB_88F6720
 	default "db-88f6820-gp" if TARGET_DB_88F6820_GP
 	default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
@@ -140,7 +144,7 @@ config SYS_CONFIG_NAME
 
 config SYS_VENDOR
 	default "Marvell" if TARGET_DB_MV784MP_GP
-	default "Marvell" if TARGET_MVEBU_DB_88F3720
+	default "Marvell" if TARGET_MVEBU_ARMADA_37XX
 	default "Marvell" if TARGET_DB_88F6720
 	default "Marvell" if TARGET_DB_88F6820_GP
 	default "Marvell" if TARGET_DB_88F6820_AMC
diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index 8f02655..1c0477a 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -82,7 +82,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	const void *fdt = gd->fdt_blob;
 	const fdt32_t *val;
@@ -90,13 +90,13 @@ void dram_init_banksize(void)
 
 	val = get_memory_reg_prop(fdt, &len);
 	if (len < 0)
-		return;
+		return -ENXIO;
 
 	ac = fdt_address_cells(fdt, 0);
 	sc = fdt_size_cells(fdt, 0);
 	if (ac < 1 || sc > 2 || sc < 1 || sc > 2) {
 		printf("invalid address/size cells\n");
-		return;
+		return -ENXIO;
 	}
 
 	cells = ac + sc;
@@ -114,6 +114,8 @@ void dram_init_banksize(void)
 		      i, (unsigned long)gd->bd->bi_dram[i].start,
 		      (unsigned long)gd->bd->bi_dram[i].size);
 	}
+
+	return 0;
 }
 
 int arch_cpu_init(void)
diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c
index a8ec5ea..e3f304c 100644
--- a/arch/arm/mach-mvebu/dram.c
+++ b/arch/arm/mach-mvebu/dram.c
@@ -273,7 +273,7 @@ int dram_init(void)
  * If this function is not defined here,
  * board.c alters dram bank zero configuration defined above.
  */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	u64 size = 0;
 	int i;
@@ -287,6 +287,8 @@ void dram_init_banksize(void)
 		if (size > SDRAM_SIZE_MAX)
 			mvebu_sdram_bs_set(i, 0x40000000);
 	}
+
+	return 0;
 }
 
 #if defined(CONFIG_ARCH_MVEBU)
diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
index afc0cef..5925bae 100644
--- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
+++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
@@ -230,6 +230,20 @@ static int serdes_max_lines_get(void)
 	return 0;
 }
 
+/*
+ * Tests have shown that on some boards the default width of the
+ * configuration pulse for the PEX link detection might lead to
+ * non-established PCIe links (link down). Especially under certain
+ * conditions (higher temperature) and with specific PCIe devices.
+ * To enable a board-specific detection pulse width this weak
+ * array "serdes_pex_pulse_width[4]" is introduced which can be
+ * overwritten if needed by a board-specific version. If the board
+ * code does not provide a non-weak version of this variable, the
+ * default value will be used. So nothing is changed from the
+ * current setup on the supported board.
+ */
+__weak u8 serdes_pex_pulse_width[4] = { 2, 2, 2, 2 };
+
 int serdes_phy_config(void)
 {
 	int status = MV_OK;
@@ -891,6 +905,23 @@ int serdes_phy_config(void)
 			pex_unit = line_num >> 2;
 			pex_line_num = line_num % 4;
 			if (0 == pex_line_num) {
+				/*
+				 * Configure the detection pulse with before
+				 * the reset is deasserted
+				 */
+
+				/* Read the old value (indirect access) */
+				reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+					  (0x48 << 16) | (1 << 31) |
+					  (pex_line_num << 24));
+				tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
+				tmp &= ~(1 << 31);	/* Clear read */
+				tmp &= ~(3 << 6);	/* Mask width */
+				/* Insert new detection pulse width */
+				tmp |= serdes_pex_pulse_width[pex_unit] << 6;
+				/* Write value back */
+				reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+
 				reg_write(PEX_PHY_ACCESS_REG(pex_unit),
 					  (0xC1 << 16) | 0x24);
 				DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 24bc485..d74b068 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -1,6 +1,6 @@
 config TI_SECURE_DEVICE
 	bool "HS Device Type Support"
-	depends on OMAP54XX || AM43XX || AM33XX
+	depends on OMAP54XX || AM43XX || AM33XX || ARCH_KEYSTONE
 	help
 	  If a high secure (HS) device type is being used, this config
 	  must be set. This option impacts various aspects of the
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 865a8d2..cf5d95a 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -119,6 +119,11 @@ config TARGET_AM43XX_EVM
 	bool "Support am43xx_evm"
 	select BOARD_LATE_INIT
 	select TI_I2C_BOARD_DETECT
+	imply DM_ETH
+	imply DM_I2C
+	imply DM_SPI
+	imply DM_SPI_FLASH
+	imply SPI_FLASH_BAR
 	imply SPL_ENV_SUPPORT
 	imply SPL_EXT_SUPPORT
 	imply SPL_FAT_SUPPORT
diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c
index 27fa3fb..3a110f2 100644
--- a/arch/arm/mach-omap2/am33xx/emif4.c
+++ b/arch/arm/mach-omap2/am33xx/emif4.c
@@ -32,10 +32,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 
diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c
index f0f72fa..e4fc461 100644
--- a/arch/arm/mach-omap2/am33xx/sys_info.c
+++ b/arch/arm/mach-omap2/am33xx/sys_info.c
@@ -74,6 +74,10 @@ static char *cpu_revs[] = {
 		"2.0",
 		"2.1"};
 
+static char *cpu_revs_am43xx[] = {
+		"1.0",
+		"1.1",
+		"1.2"};
 
 static char *dev_types[] = {
 		"TST",
@@ -87,6 +91,7 @@ static char *dev_types[] = {
 int print_cpuinfo(void)
 {
 	char *cpu_s, *sec_s, *rev_s;
+	char **cpu_rev_arr = cpu_revs;
 
 	switch (get_cpu_type()) {
 	case AM335X:
@@ -97,6 +102,7 @@ int print_cpuinfo(void)
 		break;
 	case AM437X:
 		cpu_s = "AM437X";
+		cpu_rev_arr = cpu_revs_am43xx;
 		break;
 	default:
 		cpu_s = "Unknown CPU type";
@@ -104,7 +110,7 @@ int print_cpuinfo(void)
 	}
 
 	if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
-		rev_s = cpu_revs[get_cpu_rev()];
+		rev_s = cpu_rev_arr[get_cpu_rev()];
 	else
 		rev_s = "?";
 
diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c
index 84f93e7..93c4c6f 100644
--- a/arch/arm/mach-omap2/clocks-common.c
+++ b/arch/arm/mach-omap2/clocks-common.c
@@ -828,27 +828,29 @@ void do_enable_clocks(u32 const *clk_domains,
 	u32 i, max = 100;
 
 	/* Put the clock domains in SW_WKUP mode */
-	for (i = 0; (i < max) && clk_domains[i]; i++) {
+	for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
 		enable_clock_domain(clk_domains[i],
 				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
 	}
 
 	/* Clock modules that need to be put in HW_AUTO */
-	for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
+	for (i = 0; (i < max) && clk_modules_hw_auto &&
+		     clk_modules_hw_auto[i]; i++) {
 		enable_clock_module(clk_modules_hw_auto[i],
 				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
 				    wait_for_enable);
 	};
 
 	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
-	for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+	for (i = 0; (i < max) && clk_modules_explicit_en &&
+		     clk_modules_explicit_en[i]; i++) {
 		enable_clock_module(clk_modules_explicit_en[i],
 				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
 				    wait_for_enable);
 	};
 
 	/* Put the clock domains in HW_AUTO mode now */
-	for (i = 0; (i < max) && clk_domains[i]; i++) {
+	for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
 		enable_clock_domain(clk_domains[i],
 				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
 	}
diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk
index 0c84333..0346cb9 100644
--- a/arch/arm/mach-omap2/config_secure.mk
+++ b/arch/arm/mach-omap2/config_secure.mk
@@ -77,6 +77,12 @@ u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin FORCE
 u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin FORCE
 	$(call if_changed,mkomapsecimg)
 
+# For supporting single stage boot on keystone, the image is a full u-boot
+# file, not an SPL. This will work for all boot devices, other than SPI
+# flash
+u-boot_HS_MLO: $(obj)/u-boot.bin
+	$(call if_changed,mkomapsecimg)
+
 # For supporting single stage XiP QSPI on AM43xx, the image is a full u-boot
 # file, not an SPL. In this case the mkomapsecimg command looks for a
 # u-boot-HS_* prefix
diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c
index a2aadc9..d540cf0 100644
--- a/arch/arm/mach-omap2/omap3/emif4.c
+++ b/arch/arm/mach-omap2/omap3/emif4.c
@@ -142,7 +142,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize (void)
+int dram_init_banksize(void)
 {
 	unsigned int size0 = 0, size1 = 0;
 
@@ -153,6 +153,8 @@ void dram_init_banksize (void)
 	gd->bd->bi_dram[0].size = size0;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
 	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
 }
 
 /*
diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c
index 4f15ac9..f64cd91 100644
--- a/arch/arm/mach-omap2/omap3/sdrc.c
+++ b/arch/arm/mach-omap2/omap3/sdrc.c
@@ -216,7 +216,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize (void)
+int dram_init_banksize(void)
 {
 	unsigned int size0 = 0, size1 = 0;
 
@@ -227,6 +227,8 @@ void dram_init_banksize (void)
 	gd->bd->bi_dram[0].size = size0;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
 	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
 }
 
 /*
diff --git a/arch/arm/mach-omap2/u-boot-spl.lds b/arch/arm/mach-omap2/u-boot-spl.lds
index 8fec715..e9da2a9 100644
--- a/arch/arm/mach-omap2/u-boot-spl.lds
+++ b/arch/arm/mach-omap2/u-boot-spl.lds
@@ -46,6 +46,8 @@ SECTIONS
 		*(.__end)
 	}
 
+	_image_binary_end = .;
+
 	.bss :
 	{
 		. = ALIGN(4);
diff --git a/arch/arm/mach-orion5x/dram.c b/arch/arm/mach-orion5x/dram.c
index 9ed93d2..e9c03f3 100644
--- a/arch/arm/mach-orion5x/dram.c
+++ b/arch/arm/mach-orion5x/dram.c
@@ -42,7 +42,7 @@ int dram_init (void)
 	return 0;
 }
 
-void dram_init_banksize (void)
+int dram_init_banksize(void)
 {
 	int i;
 
@@ -52,4 +52,6 @@ void dram_init_banksize (void)
 			(long *) (gd->bd->bi_dram[i].start),
 			CONFIG_MAX_RAM_BANK_SIZE);
 	}
+
+	return 0;
 }
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index bf8e6be..af0796d 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -54,6 +54,7 @@ config ROCKCHIP_RK3399
 	select SUPPORT_SPL
 	select SPL
 	select SPL_SEPARATE_BSS
+	select ENABLE_ARM_SOC_BOOT0_HOOK
 	help
 	  The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
 	  and quad-core Cortex-A53.
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c
index f93feae..c3e174d 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
+#include <clk.h>
 #include <common.h>
 #include <debug_uart.h>
 #include <dm.h>
@@ -76,6 +77,27 @@ u32 spl_boot_mode(const u32 boot_device)
 	return MMCSD_MODE_RAW;
 }
 
+static int setup_arm_clock(void)
+{
+	struct udevice *dev;
+	struct clk clk;
+	int ret;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret)
+		return ret;
+
+	clk.id = CLK_ARM;
+	ret = clk_request(dev, &clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_set_rate(&clk, 600000000);
+
+	clk_free(&clk);
+	return ret;
+}
+
 void board_init_f(ulong dummy)
 {
 	struct udevice *pinctrl, *dev;
@@ -109,9 +131,9 @@ void board_init_f(ulong dummy)
 	printch('\n');
 #endif
 
-	ret = spl_init();
+	ret = spl_early_init();
 	if (ret) {
-		debug("spl_init() failed: %d\n", ret);
+		debug("spl_early_init() failed: %d\n", ret);
 		hang();
 	}
 
@@ -144,6 +166,8 @@ void board_init_f(ulong dummy)
 		return;
 	}
 
+	setup_arm_clock();
+
 #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
 	back_to_bootrom();
 #endif
diff --git a/arch/arm/mach-rockchip/rk3188-board-tpl.c b/arch/arm/mach-rockchip/rk3188-board-tpl.c
index 442bfe7..b458ef6 100644
--- a/arch/arm/mach-rockchip/rk3188-board-tpl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-tpl.c
@@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static int rk3188_num_entries __attribute__ ((section(".data")));
 
 #define PMU_BASE	0x20004000
-#define TPL_ENTRY	0x10080C00
+#define SPL_ENTRY	0x10080C00
 
 static void jump_to_spl(void)
 {
@@ -25,9 +25,9 @@ static void jump_to_spl(void)
 
 	struct rk3188_pmu * const pmu = (void *)PMU_BASE;
 	image_entry_noargs_t tpl_entry =
-		(image_entry_noargs_t)(unsigned long)TPL_ENTRY;
+		(image_entry_noargs_t)(unsigned long)SPL_ENTRY;
 
-	/* Store the SAVE_SP_ADDR in a location shared with TPL. */
+	/* Store the SAVE_SP_ADDR in a location shared with SPL. */
 	writel(SAVE_SP_ADDR, &pmu->sys_reg[2]);
 	tpl_entry();
 }
diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c
index 16f3855..c370156 100644
--- a/arch/arm/mach-rockchip/rk3188-board.c
+++ b/arch/arm/mach-rockchip/rk3188-board.c
@@ -56,8 +56,22 @@ err:
 
 int dram_init(void)
 {
-	/* FIXME: read back ram size from sys_reg2 */
-	gd->ram_size = 0x40000000;
+	struct ram_info ram;
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return ret;
+	}
+	ret = ram_get_info(dev, &ram);
+	if (ret) {
+		debug("Cannot get DRAM size: %d\n", ret);
+		return ret;
+	}
+	debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
+	gd->ram_size = ram.size;
 
 	return 0;
 }
diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig
index f8e1d03..d129fcd 100644
--- a/arch/arm/mach-rockchip/rk3188/Kconfig
+++ b/arch/arm/mach-rockchip/rk3188/Kconfig
@@ -1,5 +1,14 @@
 if ROCKCHIP_RK3188
 
+config TARGET_ROCK
+	bool "Radxa Rock"
+	help
+	  Rock is a RK3188-based development board with 2 USB and 1 otg
+	  ports, HDMI, TV-out, micro-SD card, audio, WiFi  and 100MBit
+	  Ethernet, It also includes on-board nand and 1GB of SDRAM.
+	  Expansion connectors provide access to display pins, I2C, SPI,
+	  UART and GPIOs.
+
 config SYS_SOC
 	default "rockchip"
 
@@ -18,7 +27,12 @@ config SPL_SERIAL_SUPPORT
 config TPL_LIBCOMMON_SUPPORT
 	default y
 
+config TPL_LIBGENERIC_SUPPORT
+	default y
+
 config TPL_SERIAL_SUPPORT
 	default y
 
+source "board/radxa/rock/Kconfig"
+
 endif
diff --git a/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c
index 461cfcd..fea8007 100644
--- a/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c
@@ -955,7 +955,7 @@ static int rk3188_dmc_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 #endif
-	priv->info.base = 0;
+	priv->info.base = CONFIG_SYS_SDRAM_BASE;
 	priv->info.size = sdram_size_mb(priv->pmu) << 20;
 
 	return 0;
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index 738a20d..8e7355e 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -1,13 +1,34 @@
 if ROCKCHIP_RK3288
 
-config TARGET_FIREFLY_RK3288
-	bool "Firefly-RK3288"
+config TARGET_CHROMEBOOK_JERRY
+	bool "Google/Rockchip Veyron-Jerry Chromebook"
 	select BOARD_LATE_INIT
 	help
-	  Firefly is a RK3288-based development board with 2 USB ports,
-	  HDMI, VGA, micro-SD card, audio, WiFi  and Gigabit Ethernet, It
-	  also includes on-board eMMC and 1GB of SDRAM. Expansion connectors
-	  provide access to display pins, I2C, SPI, UART and GPIOs.
+	  Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports,
+	  HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and
+	  WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
+	  the keyboard and battery functions.
+
+config TARGET_CHROMEBIT_MICKEY
+	bool "Google/Rockchip Veyron-Mickey Chromebit"
+	select BOARD_LATE_INIT
+	help
+	  Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
+	  and WiFi. It has a separate power port and is designed to connect
+	  to the HDMI input of a monitor or TV. It has no internal battery.
+	  Typically a USB hub or wireless keyboard/touchpad is used to get
+	  keyboard and mouse access.
+
+config TARGET_CHROMEBOOK_MINNIE
+	bool "Google/Rockchip Veyron-Minnie Chromebook"
+	select BOARD_LATE_INIT
+	help
+	  Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
+	  ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
+	  HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS
+	  EC (Cortex-M3) to provide access to the keyboard and battery
+	  functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of
+	  internal MMC. The product name is ASUS Chromebook Flip.
 
 config TARGET_EVB_RK3288
 	bool "Evb-RK3288"
@@ -27,6 +48,24 @@ config TARGET_FENNEC_RK3288
 	  includes on-board eMMC and 2GB of SDRAM. Expansion connectors
 	  provide access to display pins, I2C, SPI, UART and GPIOs.
 
+config TARGET_FIREFLY_RK3288
+	bool "Firefly-RK3288"
+	select BOARD_LATE_INIT
+	help
+	  Firefly is a RK3288-based development board with 2 USB ports,
+	  HDMI, VGA, micro-SD card, audio, WiFi  and Gigabit Ethernet, It
+	  also includes on-board eMMC and 1GB of SDRAM. Expansion connectors
+	  provide access to display pins, I2C, SPI, UART and GPIOs.
+
+config TARGET_MIQI_RK3288
+	bool "MiQi-RK3288"
+	select BOARD_LATE_INIT
+	help
+	  MiQi-RK3288 is a RK3288-based development board with 4 USB 2.0
+	  ports, HDMI, micro-SD card, 16 GB eMMC and Gigabit Ethernet. It
+	  has 1 or 2 GiB SDRAM. Expansion connectors provide access to
+	  I2C, SPI, UART, GPIOs and fan control.
+
 config TARGET_POPMETAL_RK3288
 	bool "PopMetal-RK3288"
 	select BOARD_LATE_INIT
@@ -37,45 +76,6 @@ config TARGET_POPMETAL_RK3288
 	  2GB DDR3. Expansion connectors provide access to I2C, SPI, UART,
 	  GPIOs and display interface.
 
-config TARGET_TINKER_RK3288
-	bool "Tinker-RK3288"
-        select BOARD_LATE_INIT
-	help
-	  Tinker is a RK3288-based development board with 2 USB ports, HDMI,
-	  micro-SD card, audio, Gigabit Ethernet. It also includes on-board
-	  8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to
-	  I2C, SPI, UART, GPIOs.
-
-config TARGET_CHROMEBOOK_JERRY
-	bool "Google/Rockchip Veyron-Jerry Chromebook"
-	select BOARD_LATE_INIT
-	help
-	  Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports,
-	  HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and
-	  WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
-	  the keyboard and battery functions.
-
-config TARGET_CHROMEBIT_MICKEY
-	bool "Google/Rockchip Veyron-Mickey Chromebit"
-	select BOARD_LATE_INIT
-	help
-	  Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
-	  and WiFi. It has a separate power port and is designed to connect
-	  to the HDMI input of a monitor or TV. It has no internal battery.
-	  Typically a USB hub or wireless keyboard/touchpad is used to get
-	  keyboard and mouse access.
-
-config TARGET_CHROMEBOOK_MINNIE
-	bool "Google/Rockchip Veyron-Minnie Chromebook"
-	select BOARD_LATE_INIT
-	help
-	  Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
-	  ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
-	  HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS
-	  EC (Cortex-M3) to provide access to the keyboard and battery
-	  functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of
-	  internal MMC. The product name is ASUS Chromebook Flip.
-
 config TARGET_ROCK2
 	bool "Radxa Rock 2"
 	select BOARD_LATE_INIT
@@ -85,6 +85,15 @@ config TARGET_ROCK2
 	  space for a real-time-clock battery. There is also an expansion
 	  interface which provides access to many pins.
 
+config TARGET_TINKER_RK3288
+	bool "Tinker-RK3288"
+        select BOARD_LATE_INIT
+	help
+	  Tinker is a RK3288-based development board with 2 USB ports, HDMI,
+	  micro-SD card, audio, Gigabit Ethernet. It also includes on-board
+	  8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to
+	  I2C, SPI, UART, GPIOs.
+
 config ROCKCHIP_FAST_SPL
 	bool "Change the CPU to full speed in SPL"
 	depends on TARGET_CHROMEBOOK_JERRY
@@ -118,6 +127,8 @@ source "board/firefly/firefly-rk3288/Kconfig"
 
 source "board/google/veyron/Kconfig"
 
+source "board/mqmaker/miqi_rk3288/Kconfig"
+
 source "board/radxa/rock2/Kconfig"
 
 source "board/rockchip/evb_rk3288/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
index 8ae3055..4f84ec1 100644
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -10,6 +10,7 @@
 #include <fdtdec.h>
 #include <led.h>
 #include <malloc.h>
+#include <mmc.h>
 #include <ram.h>
 #include <spl.h>
 #include <asm/gpio.h>
@@ -27,6 +28,104 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OF_CONTROL)
+static int spl_node_to_boot_device(int node)
+{
+	struct udevice *parent;
+
+	/*
+	 * This should eventually move into the SPL code, once SPL becomes
+	 * aware of the block-device layer.  Until then (and to avoid unneeded
+	 * delays in getting this feature out, it lives at the board-level).
+	 */
+	if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) {
+		struct udevice *dev;
+		struct blk_desc *desc = NULL;
+
+		for (device_find_first_child(parent, &dev);
+		     dev;
+		     device_find_next_child(&dev)) {
+			if (device_get_uclass_id(dev) == UCLASS_BLK) {
+				desc = dev_get_uclass_platdata(dev);
+				break;
+			}
+		}
+
+		if (!desc)
+			return -ENOENT;
+
+		switch (desc->devnum) {
+		case 0:
+			return BOOT_DEVICE_MMC1;
+		case 1:
+			return BOOT_DEVICE_MMC2;
+		default:
+			return -ENOSYS;
+		}
+	}
+
+	/*
+	 * SPL doesn't differentiate SPI flashes, so we keep the detection
+	 * brief and inaccurate... hopefully, the common SPL layer can be
+	 * extended with awareness of the BLK layer (and matching OF_CONTROL)
+	 * soon.
+	 */
+	if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
+		return BOOT_DEVICE_SPI;
+
+	return -1;
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	const void *blob = gd->fdt_blob;
+	int chosen_node = fdt_path_offset(blob, "/chosen");
+	int idx = 0;
+	int elem;
+	int boot_device;
+	int node;
+	const char *conf;
+
+	if (chosen_node < 0) {
+		debug("%s: /chosen not found, using spl_boot_device()\n",
+		      __func__);
+		spl_boot_list[0] = spl_boot_device();
+		return;
+	}
+
+	for (elem = 0;
+	     (conf = fdt_stringlist_get(blob, chosen_node,
+					"u-boot,spl-boot-order", elem, NULL));
+	     elem++) {
+		/* First check if the list element is an alias */
+		const char *alias = fdt_get_alias(blob, conf);
+		if (alias)
+			conf = alias;
+
+		/* Try to resolve the config item (or alias) as a path */
+		node = fdt_path_offset(blob, conf);
+		if (node < 0) {
+			debug("%s: could not find %s in FDT", __func__, conf);
+			continue;
+		}
+
+		/* Try to map this back onto SPL boot devices */
+		boot_device = spl_node_to_boot_device(node);
+		if (boot_device < 0) {
+			debug("%s: could not map node @%x to a boot-device\n",
+			      __func__, node);
+			continue;
+		}
+
+		spl_boot_list[idx++] = boot_device;
+	}
+
+	/* If we had no matches, fall back to spl_boot_device */
+	if (idx == 0)
+		spl_boot_list[0] = spl_boot_device();
+}
+#endif
+
 u32 spl_boot_device(void)
 {
 	return BOOT_DEVICE_MMC1;
@@ -96,9 +195,9 @@ void board_init_f(ulong dummy)
 	/*  Emmc clock generator: disable the clock multipilier */
 	rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
 
-	ret = spl_init();
+	ret = spl_early_init();
 	if (ret) {
-		debug("spl_init() failed: %d\n", ret);
+		debug("spl_early_init() failed: %d\n", ret);
 		hang();
 	}
 
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index cbfd3fa..8bb950e 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -40,6 +40,5 @@ int arch_cpu_init(void)
 	/* Emmc clock generator: disable the clock multipilier */
 	rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
 
-	printf("time %x, %x\n", readl(0xff8680a8), readl(0xff8680ac));
 	return 0;
 }
diff --git a/arch/arm/mach-stm32/stm32f7/soc.c b/arch/arm/mach-stm32/stm32f7/soc.c
index 06af631..6f9704a 100644
--- a/arch/arm/mach-stm32/stm32f7/soc.c
+++ b/arch/arm/mach-stm32/stm32f7/soc.c
@@ -58,6 +58,8 @@ int arch_cpu_init(void)
 		 (V7M_MPU_RASR_XN_ENABLE
 			 | V7M_MPU_RASR_AP_RW_RW
 			 | 0x01 << V7M_MPU_RASR_TEX_SHIFT
+			 | 0x01 << V7M_MPU_RASR_B_SHIFT
+			 | 0x01 << V7M_MPU_RASR_C_SHIFT
 			 | V7M_MPU_RASR_SIZE_8MB
 			 | V7M_MPU_RASR_EN)
 			 , &V7M_MPU->rasr
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7daba11..efab481 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -48,7 +48,7 @@ obj-$(CONFIG_MACH_SUN7I)	+= dram_sun4i.o
 obj-$(CONFIG_MACH_SUN8I_A23)	+= dram_sun8i_a23.o
 obj-$(CONFIG_MACH_SUN8I_A33)	+= dram_sun8i_a33.o
 obj-$(CONFIG_MACH_SUN8I_A83T)	+= dram_sun8i_a83t.o
-obj-$(CONFIG_MACH_SUN8I_H3)	+= dram_sun8i_h3.o
+obj-$(CONFIG_MACH_SUNXI_H3_H5)	+= dram_sun8i_h3.o
 obj-$(CONFIG_MACH_SUN9I)	+= dram_sun9i.o
 obj-$(CONFIG_MACH_SUN50I)	+= dram_sun8i_h3.o
 endif
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 52be5b0..5e03d03 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -40,7 +40,7 @@ struct fel_stash {
 
 struct fel_stash fel_stash __attribute__((section(".data")));
 
-#ifdef CONFIG_MACH_SUN50I
+#ifdef CONFIG_ARM64
 #include <asm/armv8/mmu.h>
 
 static struct mm_region sunxi_mem_map[] = {
@@ -98,7 +98,7 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
@@ -180,15 +180,13 @@ void s_init(void)
 	/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
 #endif
 
-#if defined CONFIG_MACH_SUN6I || \
-    defined CONFIG_MACH_SUN7I || \
-    defined CONFIG_MACH_SUN8I || \
-    defined CONFIG_MACH_SUN9I
+#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
 	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
 	asm volatile(
 		"mrc p15, 0, r0, c1, c0, 1\n"
 		"orr r0, r0, #1 << 6\n"
-		"mcr p15, 0, r0, c1, c0, 1\n");
+		"mcr p15, 0, r0, c1, c0, 1\n"
+		::: "r0");
 #endif
 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
 	/* Enable non-secure access to some peripherals */
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index d123b3a..4762fbf 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -22,7 +22,7 @@ void clock_init_safe(void)
 	struct sunxi_ccm_reg * const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
-#if !defined(CONFIG_MACH_SUN8I_H3) && !defined(CONFIG_MACH_SUN50I)
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
 	struct sunxi_prcm_reg * const prcm =
 		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 
@@ -51,7 +51,7 @@ void clock_init_safe(void)
 
 void clock_init_sec(void)
 {
-#ifdef CONFIG_MACH_SUN8I_H3
+#ifdef CONFIG_MACH_SUNXI_H3_H5
 	struct sunxi_ccm_reg * const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
@@ -152,7 +152,7 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
 	const int max_n = 32;
 	int k = 1, m = 2;
 
-#ifdef CONFIG_MACH_SUN8I_H3
+#ifdef CONFIG_MACH_SUNXI_H3_H5
 	clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK |
 			CCM_PLL5_TUN_INIT_FREQ_MASK,
 			CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16));
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index f1f6fd5..85633cc 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -91,6 +91,8 @@ int print_cpuinfo(void)
 	puts("CPU:   Allwinner A80 (SUN9I)\n");
 #elif defined CONFIG_MACH_SUN50I
 	puts("CPU:   Allwinner A64 (SUN50I)\n");
+#elif defined CONFIG_MACH_SUN50I_H5
+	puts("CPU:   Allwinner H5 (SUN50I)\n");
 #else
 #warning Please update cpu_info.c with correct CPU information
 	puts("CPU:   SUNXI Family\n");
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index 9f7cc7f..d681a9d 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -177,6 +177,34 @@ static void mctl_set_master_priority_a64(void)
 	writel(0x81000004, &mctl_com->mdfs_bwlr[2]);
 }
 
+static void mctl_set_master_priority_h5(void)
+{
+	struct sunxi_mctl_com_reg * const mctl_com =
+			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+	/* enable bandwidth limit windows and set windows size 1us */
+	writel(399, &mctl_com->tmr);
+	writel((1 << 16), &mctl_com->bwcr);
+
+	/* set cpu high priority */
+	writel(0x00000001, &mctl_com->mapr);
+
+	/* Port 2 is reserved per Allwinner's linux-3.10 source, yet
+	 * they initialise it */
+	MBUS_CONF(   CPU, true, HIGHEST, 0,  300,  260,  150);
+	MBUS_CONF(   GPU, true, HIGHEST, 0,  600,  400,  200);
+	MBUS_CONF(UNUSED, true, HIGHEST, 0,  512,  256,   96);
+	MBUS_CONF(   DMA, true, HIGHEST, 0,  256,  128,   32);
+	MBUS_CONF(    VE, true, HIGHEST, 0, 1900, 1500, 1000);
+	MBUS_CONF(   CSI, true, HIGHEST, 0,  150,  120,  100);
+	MBUS_CONF(  NAND, true,    HIGH, 0,  256,  128,   64);
+	MBUS_CONF(    SS, true, HIGHEST, 0,  256,  128,   64);
+	MBUS_CONF(    TS, true, HIGHEST, 0,  256,  128,   64);
+	MBUS_CONF(    DI, true,    HIGH, 0, 1024,  256,   64);
+	MBUS_CONF(    DE, true, HIGHEST, 3, 3400, 2400, 1024);
+	MBUS_CONF(DE_CFD, true, HIGHEST, 0,  600,  400,  200);
+}
+
 static void mctl_set_master_priority(uint16_t socid)
 {
 	switch (socid) {
@@ -186,6 +214,9 @@ static void mctl_set_master_priority(uint16_t socid)
 	case SOCID_A64:
 		mctl_set_master_priority_a64();
 		return;
+	case SOCID_H5:
+		mctl_set_master_priority_h5();
+		return;
 	}
 }
 
@@ -256,7 +287,7 @@ static void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
 
 	/* set two rank timing */
 	clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
-			(0x66 << 8) | (0x10 << 0));
+			((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0));
 
 	/* set PHY interface timing, write latency and read latency configure */
 	writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
@@ -391,7 +422,7 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para)
 				CCM_DRAMCLK_CFG_DIV(1) |
 				CCM_DRAMCLK_CFG_SRC_PLL11 |
 				CCM_DRAMCLK_CFG_UPD);
-	} else if (socid == SOCID_H3) {
+	} else if (socid == SOCID_H3 || socid == SOCID_H5) {
 		clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
 		clrsetbits_le32(&ccm->dram_clk_cfg,
 				CCM_DRAMCLK_CFG_DIV_MASK |
@@ -410,7 +441,7 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para)
 	setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
 	udelay(10);
 
-	writel(0xc00e, &mctl_ctl->clken);
+	writel(socid == SOCID_H5 ? 0x8000 : 0xc00e, &mctl_ctl->clken);
 	udelay(500);
 }
 
@@ -434,7 +465,10 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 
 	/* setting VTC, default disable all VT */
 	clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
-	clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
+	if (socid == SOCID_H5)
+		setbits_le32(&mctl_ctl->pgcr[1], (1 << 24) | (1 << 26));
+	else
+		clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
 
 	/* increase DFI_PHY_UPD clock */
 	writel(PROTECT_MAGIC, &mctl_com->protect);
@@ -444,15 +478,22 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 	udelay(100);
 
 	/* set dramc odt */
-	for (i = 0; i < 4; i++)
-		clrsetbits_le32(&mctl_ctl->dx[i].gcr, (0x3 << 4) |
-				(0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
-				(0x3 << 14),
-				IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
-					DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF);
+	for (i = 0; i < 4; i++) {
+		u32 clearmask = (0x3 << 4) | (0x1 << 1) | (0x3 << 2) |
+				(0x3 << 12) | (0x3 << 14);
+		u32 setmask = IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
+				DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF;
+
+		if (socid == SOCID_H5) {
+			clearmask |= 0x2 << 8;
+			setmask |= 0x4 << 8;
+		}
+		clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask);
+	}
 
 	/* AC PDR should always ON */
-	setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
+	clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11) : 0,
+			0x1 << 1);
 
 	/* set DQS auto gating PD mode */
 	setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
@@ -464,7 +505,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 		/* dphy & aphy phase select 270 degree */
 		clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
 				(0x1 << 10) | (0x2 << 8));
-	} else if (socid == SOCID_A64) {
+	} else if (socid == SOCID_A64 || socid == SOCID_H5) {
 		/* dphy & aphy phase select ? */
 		clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
 				(0x0 << 10) | (0x3 << 8));
@@ -488,11 +529,12 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 
 		mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
 			      PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
-	} else if (socid == SOCID_A64) {
+	} else if (socid == SOCID_A64 || socid == SOCID_H5) {
 		clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);
 
 		mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
 			      PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
+		/* no PIR_QSGATE for H5 ???? */
 	}
 
 	/* detect ranks and bus width */
@@ -533,7 +575,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 	/* set PGCR3, CKE polarity */
 	if (socid == SOCID_H3)
 		writel(0x00aa0060, &mctl_ctl->pgcr[3]);
-	else if (socid == SOCID_A64)
+	else if (socid == SOCID_A64 || socid == SOCID_H5)
 		writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
 
 	/* power down zq calibration module for power save */
@@ -604,6 +646,22 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
 	   3,  4,  0,  3,  4,  1,  4,  0,			\
 	   1,  1,  0,  1, 13,  5,  4      }
 
+#define SUN8I_H5_DX_READ_DELAYS					\
+	{{ 14, 15, 17, 17, 17, 17, 17, 18, 17,  3,  3 },	\
+	 { 21, 21, 12, 22, 21, 21, 21, 21, 21,  3,  3 },	\
+	 { 16, 19, 19, 17, 22, 22, 21, 22, 19,  3,  3 },	\
+	 { 21, 21, 22, 22, 20, 21, 19, 19, 19,  3,  3 } }
+#define SUN8I_H5_DX_WRITE_DELAYS				\
+	{{  1,  2,  3,  4,  3,  4,  4,  4,  6,  6,  6 },	\
+	 {  6,  6,  6,  5,  5,  5,  5,  5,  6,  6,  6 },	\
+	 {  0,  2,  4,  2,  6,  5,  5,  5,  6,  6,  6 },	\
+	 {  3,  3,  3,  2,  2,  1,  1,  1,  4,  4,  4 } }
+#define SUN8I_H5_AC_DELAYS					\
+	{  0,  0,  5,  5,  0,  0,  0,  0,			\
+	   0,  0,  0,  0,  3,  3,  3,  3,			\
+	   3,  3,  3,  3,  3,  3,  3,  3,			\
+	   3,  3,  3,  3,  2,  0,  0      }
+
 unsigned long sunxi_dram_init(void)
 {
 	struct sunxi_mctl_com_reg * const mctl_com =
@@ -625,6 +683,10 @@ unsigned long sunxi_dram_init(void)
 		.dx_read_delays  = SUN50I_A64_DX_READ_DELAYS,
 		.dx_write_delays = SUN50I_A64_DX_WRITE_DELAYS,
 		.ac_delays	 = SUN50I_A64_AC_DELAYS,
+#elif defined(CONFIG_MACH_SUN50I_H5)
+		.dx_read_delays  = SUN8I_H5_DX_READ_DELAYS,
+		.dx_write_delays = SUN8I_H5_DX_WRITE_DELAYS,
+		.ac_delays	 = SUN8I_H5_AC_DELAYS,
 #endif
 	};
 /*
@@ -636,6 +698,8 @@ unsigned long sunxi_dram_init(void)
 	uint16_t socid = SOCID_H3;
 #elif defined(CONFIG_MACH_SUN50I)
 	uint16_t socid = SOCID_A64;
+#elif defined(CONFIG_MACH_SUN50I_H5)
+	uint16_t socid = SOCID_H5;
 #endif
 
 	mctl_sys_init(socid, &para);
@@ -652,8 +716,9 @@ unsigned long sunxi_dram_init(void)
 	if (socid == SOCID_H3)
 		writel(0x0c000400, &mctl_ctl->odtcfg);
 
-	if (socid == SOCID_A64) {
-		setbits_le32(&mctl_ctl->vtfcr, 2 << 8);
+	if (socid == SOCID_A64 || socid == SOCID_H5) {
+		setbits_le32(&mctl_ctl->vtfcr,
+			     (socid == SOCID_H5 ? 3 : 2) << 8);
 		clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13));
 	}
 
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
index 278587b..9bf0b56 100644
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ b/arch/arm/mach-sunxi/usb_phy.c
@@ -146,10 +146,10 @@ __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
 	}
 }
 
-#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
 {
-#if defined CONFIG_MACH_SUN8I_H3
+#if defined CONFIG_MACH_SUNXI_H3_H5
 	if (phy->id == 0)
 		clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
 #endif
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 5a457b9..b73cd63 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -315,7 +315,7 @@ static ulong usable_ram_size_below_4g(void)
  * start address of that bank cannot be represented in the 32-bit .size
  * field.
  */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
@@ -334,6 +334,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[1].start = 0;
 		gd->bd->bi_dram[1].size = 0;
 	}
+
+	return 0;
 }
 
 /*
diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig
index ca96a26..a07add6 100644
--- a/arch/arm/mach-tegra/tegra124/Kconfig
+++ b/arch/arm/mach-tegra/tegra124/Kconfig
@@ -4,6 +4,12 @@ choice
 	prompt "Tegra124 board select"
 	optional
 
+config TARGET_APALIS_TK1
+	bool "Toradex Apalis TK1 module"
+	select CPU_V7_HAS_NONSEC
+	select CPU_V7_HAS_VIRT
+	select ARCH_SUPPORT_PSCI
+
 config TARGET_JETSON_TK1
 	bool "NVIDIA Tegra124 Jetson TK1 board"
 	select BOARD_LATE_INIT
@@ -46,5 +52,6 @@ source "board/cei/cei-tk1-som/Kconfig"
 source "board/nvidia/jetson-tk1/Kconfig"
 source "board/nvidia/nyan-big/Kconfig"
 source "board/nvidia/venice2/Kconfig"
+source "board/toradex/apalis-tk1/Kconfig"
 
 endif
diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c
index 37dd8d4..bf16166 100644
--- a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c
+++ b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c
@@ -72,7 +72,7 @@ int dram_init(void)
 
 extern unsigned long nvtboot_boot_x0;
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	int i;
 
@@ -80,6 +80,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[i].start = ram_banks[i].start;
 		gd->bd->bi_dram[i].size = ram_banks[i].size;
 	}
+
+	return 0;
 }
 
 ulong board_get_usable_ram_top(ulong total_size)
diff --git a/arch/arm/mach-tegra/tegra20/crypto.c b/arch/arm/mach-tegra/tegra20/crypto.c
index 1b82fbb..eae7921 100644
--- a/arch/arm/mach-tegra/tegra20/crypto.c
+++ b/arch/arm/mach-tegra/tegra20/crypto.c
@@ -8,7 +8,7 @@
 #include <common.h>
 #include <linux/errno.h>
 #include "crypto.h"
-#include "aes.h"
+#include "uboot_aes.h"
 
 static u8 zero_key[16];
 
diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c
index d9f6c16..f79b7cf 100644
--- a/arch/arm/mach-uniphier/dram_init.c
+++ b/arch/arm/mach-uniphier/dram_init.c
@@ -232,7 +232,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	struct uniphier_dram_map dram_map[3] = {};
 	int i;
@@ -246,6 +246,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[i].start = dram_map[i].base;
 		gd->bd->bi_dram[i].size = dram_map[i].size;
 	}
+
+	return 0;
 }
 
 #ifdef CONFIG_OF_BOARD_SETUP
diff --git a/arch/avr32/cpu/exception.c b/arch/avr32/cpu/exception.c
index d6991f6..22eab03 100644
--- a/arch/avr32/cpu/exception.c
+++ b/arch/avr32/cpu/exception.c
@@ -10,6 +10,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define STACKSIZE	2048
+
 static const char * const cpu_modes[8] = {
 	"Application", "Supervisor", "Interrupt level 0", "Interrupt level 1",
 	"Interrupt level 2", "Interrupt level 3", "Exception", "NMI"
@@ -96,7 +98,7 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
 	printf("CPU Mode: %s\n", cpu_modes[mode]);
 
 	/* Avoid exception loops */
-	if (regs->sp < (gd->start_addr_sp - CONFIG_STACKSIZE) ||
+	if (regs->sp < (gd->start_addr_sp - STACKSIZE) ||
 	    regs->sp >= gd->start_addr_sp)
 		printf("\nStack pointer seems bogus, won't do stack dump\n");
 	else
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
deleted file mode 100644
index 0a2fb4d..0000000
--- a/arch/blackfin/Kconfig
+++ /dev/null
@@ -1,150 +0,0 @@
-menu "Blackfin architecture"
-	depends on BLACKFIN
-
-config SYS_ARCH
-	default "blackfin"
-
-choice
-	prompt "Target select"
-	optional
-
-config TARGET_BCT_BRETTL2
-	bool "Support bct-brettl2"
-
-config TARGET_BF506F_EZKIT
-	bool "Support bf506f-ezkit"
-
-config TARGET_BF518F_EZBRD
-	bool "Support bf518f-ezbrd"
-
-config TARGET_BF525_UCR2
-	bool "Support bf525-ucr2"
-
-config TARGET_BF526_EZBRD
-	bool "Support bf526-ezbrd"
-
-config TARGET_BF527_AD7160_EVAL
-	bool "Support bf527-ad7160-eval"
-
-config TARGET_BF527_EZKIT
-	bool "Support bf527-ezkit"
-
-config TARGET_BF527_SDP
-	bool "Support bf527-sdp"
-
-config TARGET_BF533_EZKIT
-	bool "Support bf533-ezkit"
-
-config TARGET_BF533_STAMP
-	bool "Support bf533-stamp"
-
-config TARGET_BF537_MINOTAUR
-	bool "Support bf537-minotaur"
-
-config TARGET_BF537_PNAV
-	bool "Support bf537-pnav"
-
-config TARGET_BF537_SRV1
-	bool "Support bf537-srv1"
-
-config TARGET_BF537_STAMP
-	bool "Support bf537-stamp"
-
-config TARGET_BF538F_EZKIT
-	bool "Support bf538f-ezkit"
-
-config TARGET_BF548_EZKIT
-	bool "Support bf548-ezkit"
-
-config TARGET_BF561_ACVILON
-	bool "Support bf561-acvilon"
-
-config TARGET_BF561_EZKIT
-	bool "Support bf561-ezkit"
-
-config TARGET_BF609_EZKIT
-	bool "Support bf609-ezkit"
-
-config TARGET_BLACKSTAMP
-	bool "Support blackstamp"
-
-config TARGET_BLACKVME
-	bool "Support blackvme"
-
-config TARGET_BR4
-	bool "Support br4"
-
-config TARGET_CM_BF527
-	bool "Support cm-bf527"
-
-config TARGET_CM_BF533
-	bool "Support cm-bf533"
-
-config TARGET_CM_BF537E
-	bool "Support cm-bf537e"
-
-config TARGET_CM_BF537U
-	bool "Support cm-bf537u"
-
-config TARGET_CM_BF548
-	bool "Support cm-bf548"
-
-config TARGET_CM_BF561
-	bool "Support cm-bf561"
-
-config TARGET_DNP5370
-	bool "Support dnp5370"
-
-config TARGET_IBF_DSP561
-	bool "Support ibf-dsp561"
-
-config TARGET_IP04
-	bool "Support ip04"
-
-config TARGET_PR1
-	bool "Support pr1"
-
-config TARGET_TCM_BF518
-	bool "Support tcm-bf518"
-
-config TARGET_TCM_BF537
-	bool "Support tcm-bf537"
-
-endchoice
-
-source "board/bct-brettl2/Kconfig"
-source "board/bf506f-ezkit/Kconfig"
-source "board/bf518f-ezbrd/Kconfig"
-source "board/bf525-ucr2/Kconfig"
-source "board/bf526-ezbrd/Kconfig"
-source "board/bf527-ad7160-eval/Kconfig"
-source "board/bf527-ezkit/Kconfig"
-source "board/bf527-sdp/Kconfig"
-source "board/bf533-ezkit/Kconfig"
-source "board/bf533-stamp/Kconfig"
-source "board/bf537-minotaur/Kconfig"
-source "board/bf537-pnav/Kconfig"
-source "board/bf537-srv1/Kconfig"
-source "board/bf537-stamp/Kconfig"
-source "board/bf538f-ezkit/Kconfig"
-source "board/bf548-ezkit/Kconfig"
-source "board/bf561-acvilon/Kconfig"
-source "board/bf561-ezkit/Kconfig"
-source "board/bf609-ezkit/Kconfig"
-source "board/blackstamp/Kconfig"
-source "board/blackvme/Kconfig"
-source "board/br4/Kconfig"
-source "board/cm-bf527/Kconfig"
-source "board/cm-bf533/Kconfig"
-source "board/cm-bf537e/Kconfig"
-source "board/cm-bf537u/Kconfig"
-source "board/cm-bf548/Kconfig"
-source "board/cm-bf561/Kconfig"
-source "board/dnp5370/Kconfig"
-source "board/ibf-dsp561/Kconfig"
-source "board/ip04/Kconfig"
-source "board/pr1/Kconfig"
-source "board/tcm-bf518/Kconfig"
-source "board/tcm-bf537/Kconfig"
-
-endmenu
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
deleted file mode 100644
index 787475e..0000000
--- a/arch/blackfin/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-head-y := arch/blackfin/cpu/start.o
-
-libs-y += arch/blackfin/cpu/
-libs-y += arch/blackfin/lib/
diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk
deleted file mode 100644
index 7b17b75..0000000
--- a/arch/blackfin/config.mk
+++ /dev/null
@@ -1,68 +0,0 @@
-#
-# (C) Copyright 2000-2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := bfin-uclinux-
-endif
-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x1000 -m elf32bfin
-
-ifeq ($(CONFIG_BFIN_CPU),)
-CONFIG_BFIN_CPU := \
-	$(shell awk '$$2 == "CONFIG_BFIN_CPU" { print $$3 }' \
-		$(srctree)/include/configs/$(BOARD).h)
-else
-CONFIG_BFIN_CPU := $(strip $(CONFIG_BFIN_CPU:"%"=%))
-endif
-CONFIG_BFIN_BOOT_MODE := $(strip $(CONFIG_BFIN_BOOT_MODE:"%"=%))
-
-PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic
-
-LDFLAGS_FINAL += --gc-sections
-LDFLAGS += -m elf32bfin
-PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
-
-PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU)
-
-ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
-ALL-y += u-boot.ldr
-endif
-ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y)
-CREATE_LDR_ENV = tools/envcrc --binary > env-ldr.o
-HOSTCFLAGS_NOPED_ADSP := \
-	$(shell $(CPP) -dD - -mcpu=$(CONFIG_BFIN_CPU) </dev/null \
-		| awk '$$2 ~ /ADSP/ { print "-D" $$2 }')
-HOSTCFLAGS_NOPED += $(HOSTCFLAGS_NOPED_ADSP)
-else
-CREATE_LDR_ENV =
-endif
-
-SYM_PREFIX = _
-export SYM_PREFIX
-
-LDR_FLAGS-y :=
-LDR_FLAGS-$(CONFIG_BFIN_BOOTROM_USES_EVT1) += -J
-
-LDR_FLAGS += --bmode $(subst BFIN_BOOT_,,$(CONFIG_BFIN_BOOT_MODE))
-LDR_FLAGS += --use-vmas
-LDR_FLAGS += --initcode $(CPUDIR)/initcode.o
-ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_UART)
-LDR_FLAGS-$(CONFIG_ENV_IS_EMBEDDED_IN_LDR) += \
-	--punchit $$(($(CONFIG_ENV_OFFSET))):$$(($(CONFIG_ENV_SIZE))):env-ldr.o
-endif
-ifneq (,$(findstring s,$(MAKEFLAGS)))
-LDR_FLAGS += --quiet
-endif
-
-LDR_FLAGS += $(LDR_FLAGS-y)
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
-
-ifneq ($(CONFIG_SYS_TEXT_BASE),)
-$(error do not set CONFIG_SYS_TEXT_BASE for Blackfin boards)
-endif
diff --git a/arch/blackfin/cpu/.gitignore b/arch/blackfin/cpu/.gitignore
deleted file mode 100644
index 3df1fa2..0000000
--- a/arch/blackfin/cpu/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-init.lds
-init.elf
diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile
deleted file mode 100644
index 7ba5f1b..0000000
--- a/arch/blackfin/cpu/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-extra-y := init.elf
-extra-y += initcode.o
-extra-y += start.o
-obj-y    := interrupt.o cache.o
-obj-y  += cpu.o
-obj-y += gpio.o
-obj-y  += interrupts.o
-obj-$(CONFIG_JTAG_CONSOLE) += jtag-console.o
-obj-y  += os_log.o
-obj-y  += reset.o
-obj-y  += traps.o
-
-extra-y += check_initcode
-clean-files := init.lds
-
-# make sure our initcode (which goes into LDR) does not
-# have relocs or external references
-CFLAGS_REMOVE_initcode.o := -ffunction-sections -fdata-sections
-READINIT = env LC_ALL=C $(CROSS_COMPILE)readelf -s $<
-$(obj)/check_initcode: $(obj)/initcode.o
-ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
-	@if $(READINIT) | grep '\<GLOBAL\>.*\<UND\>' ; then \
-		echo "$< contains external references!" 1>&2 ; \
-		exit 1 ; \
-	fi
-endif
-
-CPPFLAGS_init.lds := -ansi
-
-quiet_cmd_link_init = LD      $@
-      cmd_link_init = $(LD) $(LDFLAGS) -T $^ -o $@
-$(obj)/init.elf: $(obj)/init.lds $(obj)/init.o $(obj)/initcode.o
-	$(call if_changed,link_init)
-targets += init.lds init.o
diff --git a/arch/blackfin/cpu/cache.S b/arch/blackfin/cpu/cache.S
deleted file mode 100644
index 5ca9e91..0000000
--- a/arch/blackfin/cpu/cache.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Blackfin cache control code
- *
- * Copyright 2003-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-
-.text
-/* Since all L1 caches work the same way, we use the same method for flushing
- * them.  Only the actual flush instruction differs.  We write this in asm as
- * GCC can be hard to coax into writing nice hardware loops.
- *
- * Also, we assume the following register setup:
- * R0 = start address
- * R1 = end address
- */
-.macro do_flush flushins:req optflushins optnopins label
-
-	R2 = -L1_CACHE_BYTES;
-
-	/* start = (start & -L1_CACHE_BYTES) */
-	R0 = R0 & R2;
-
-	/* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
-	R1 += -1;
-	R1 = R1 & R2;
-	R1 += L1_CACHE_BYTES;
-
-	/* count = (end - start) >> L1_CACHE_SHIFT */
-	R2 = R1 - R0;
-	R2 >>= L1_CACHE_SHIFT;
-	P1 = R2;
-
-.ifnb \label
-\label :
-.endif
-	P0 = R0;
-	LSETUP (1f, 2f) LC1 = P1;
-1:
-.ifnb \optflushins
-	\optflushins [P0];
-.endif
-#if ANOMALY_05000443
-.ifb \optnopins
-2:
-.endif
-	\flushins [P0++];
-.ifnb \optnopins
-2:	\optnopins;
-.endif
-#else
-2:	\flushins [P0++];
-#endif
-
-	RTS;
-.endm
-
-/* Invalidate all instruction cache lines assocoiated with this memory area */
-ENTRY(_blackfin_icache_flush_range)
-	do_flush IFLUSH, , nop
-ENDPROC(_blackfin_icache_flush_range)
-
-/* Flush all cache lines assocoiated with this area of memory. */
-ENTRY(_blackfin_icache_dcache_flush_range)
-	do_flush FLUSH, IFLUSH
-ENDPROC(_blackfin_icache_dcache_flush_range)
-
-/* Throw away all D-cached data in specified region without any obligation to
- * write them back.  Since the Blackfin ISA does not have an "invalidate"
- * instruction, we use flush/invalidate.  Perhaps as a speed optimization we
- * could bang on the DTEST MMRs ...
- */
-ENTRY(_blackfin_dcache_flush_invalidate_range)
-	do_flush FLUSHINV
-ENDPROC(_blackfin_dcache_flush_invalidate_range)
-
-/* Flush all data cache lines assocoiated with this memory area */
-ENTRY(_blackfin_dcache_flush_range)
-	do_flush FLUSH, , , .Ldfr
-ENDPROC(_blackfin_dcache_flush_range)
diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c
deleted file mode 100644
index 529322a..0000000
--- a/arch/blackfin/cpu/cpu.c
+++ /dev/null
@@ -1,415 +0,0 @@
-/*
- * U-Boot - cpu.c CPU specific functions
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <version.h>
-#include <i2c.h>
-
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-#include <asm/clock.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/trace.h>
-
-#include "cpu.h"
-#include "initcode.h"
-#include "exports.h"
-
-ulong bfin_poweron_retx;
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
-void bfin_core1_start(void)
-{
-#ifdef BF561_FAMILY
-	/* Enable core 1 */
-	bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
-#else
-	/* Enable core 1 */
-	bfin_write32(RCU0_SVECT1, COREB_L1_CODE_START);
-	bfin_write32(RCU0_CRCTL, 0);
-
-	bfin_write32(RCU0_CRCTL, 0x2);
-
-	/* Check if core 1 starts */
-	while (!(bfin_read32(RCU0_CRSTAT) & 0x2))
-		continue;
-
-	bfin_write32(RCU0_CRCTL, 0);
-
-	/* flag to notify cces core 1 application */
-	bfin_write32(SDU0_MSG_SET, (1 << 19));
-#endif
-}
-#endif
-
-__attribute__((always_inline))
-static inline void serial_early_puts(const char *s)
-{
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-	serial_puts("Early: ");
-	serial_puts(s);
-#endif
-}
-
-static int global_board_data_init(void)
-{
-#ifndef CONFIG_SYS_GBL_DATA_ADDR
-# define CONFIG_SYS_GBL_DATA_ADDR 0
-#endif
-#ifndef CONFIG_SYS_BD_INFO_ADDR
-# define CONFIG_SYS_BD_INFO_ADDR 0
-#endif
-
-	bd_t *bd;
-
-	if (CONFIG_SYS_GBL_DATA_ADDR) {
-		gd = (gd_t *)(CONFIG_SYS_GBL_DATA_ADDR);
-		memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
-	} else {
-		static gd_t _bfin_gd;
-		gd = &_bfin_gd;
-	}
-	if (CONFIG_SYS_BD_INFO_ADDR) {
-		bd = (bd_t *)(CONFIG_SYS_BD_INFO_ADDR);
-		memset(bd, 0, GENERATED_BD_INFO_SIZE);
-	} else {
-		static bd_t _bfin_bd;
-		bd = &_bfin_bd;
-	}
-
-	gd->bd = bd;
-
-	bd->bi_r_version = version_string;
-	bd->bi_cpu = __stringify(CONFIG_BFIN_CPU);
-	bd->bi_board_name = CONFIG_SYS_BOARD;
-	bd->bi_vco = get_vco();
-	bd->bi_cclk = get_cclk();
-	bd->bi_sclk = get_sclk();
-	bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
-
-	gd->ram_size = CONFIG_SYS_MAX_RAM_SIZE;
-
-	return 0;
-}
-
-static void display_global_data(void)
-{
-	bd_t *bd;
-
-#ifndef CONFIG_DEBUG_EARLY_SERIAL
-	return;
-#endif
-
-	bd = gd->bd;
-	printf(" gd: %p\n", gd);
-	printf(" |-flags: %lx\n", gd->flags);
-	printf(" |-board_type: %lx\n", gd->arch.board_type);
-	printf(" |-baudrate: %u\n", gd->baudrate);
-	printf(" |-have_console: %lx\n", gd->have_console);
-	printf(" |-ram_size: %lx\n", gd->ram_size);
-	printf(" |-env_addr: %lx\n", gd->env_addr);
-	printf(" |-env_valid: %lx\n", gd->env_valid);
-	printf(" |-jt(%p): %p\n", gd->jt, gd->jt->get_version);
-	printf(" \\-bd: %p\n", gd->bd);
-	printf("   |-bi_boot_params: %lx\n", bd->bi_boot_params);
-	printf("   |-bi_memstart: %lx\n", bd->bi_memstart);
-	printf("   |-bi_memsize: %lx\n", bd->bi_memsize);
-	printf("   |-bi_flashstart: %lx\n", bd->bi_flashstart);
-	printf("   |-bi_flashsize: %lx\n", bd->bi_flashsize);
-	printf("   \\-bi_flashoffset: %lx\n", bd->bi_flashoffset);
-}
-
-#define CPLB_PAGE_SIZE (4 * 1024 * 1024)
-#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1))
-#if defined(__ADSPBF60x__)
-#define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024)
-#define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1))
-#else
-#define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE
-#define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK
-#endif
-void init_cplbtables(void)
-{
-	uint32_t *ICPLB_ADDR, *ICPLB_DATA;
-	uint32_t *DCPLB_ADDR, *DCPLB_DATA;
-	uint32_t extern_memory;
-	size_t i;
-
-	void icplb_add(uint32_t addr, uint32_t data)
-	{
-		bfin_write32(ICPLB_ADDR + i, addr);
-		bfin_write32(ICPLB_DATA + i, data);
-	}
-	void dcplb_add(uint32_t addr, uint32_t data)
-	{
-		bfin_write32(DCPLB_ADDR + i, addr);
-		bfin_write32(DCPLB_DATA + i, data);
-	}
-
-	/* populate a few common entries ... we'll let
-	 * the memory map and cplb exception handler do
-	 * the rest of the work.
-	 */
-	i = 0;
-	ICPLB_ADDR = (uint32_t *)ICPLB_ADDR0;
-	ICPLB_DATA = (uint32_t *)ICPLB_DATA0;
-	DCPLB_ADDR = (uint32_t *)DCPLB_ADDR0;
-	DCPLB_DATA = (uint32_t *)DCPLB_DATA0;
-
-	icplb_add(0xFFA00000, L1_IMEMORY);
-	dcplb_add(0xFF800000, L1_DMEMORY);
-	++i;
-#if defined(__ADSPBF60x__)
-	icplb_add(0x0, 0x0);
-	dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY |
-		CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID);
-	++i;
-#endif
-
-	if (CONFIG_MEM_SIZE) {
-		uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
-		uint32_t mend  = mbase + CONFIG_SYS_MONITOR_LEN - 1;
-		mbase &= CPLB_PAGE_MASK;
-		mend &= CPLB_PAGE_MASK;
-
-		icplb_add(mbase, SDRAM_IKERNEL);
-		dcplb_add(mbase, SDRAM_DKERNEL);
-		++i;
-
-		/*
-		 * If the monitor crosses a 4 meg boundary, we'll need
-		 * to lock two entries for it.  We assume it doesn't
-		 * cross two 4 meg boundaries ...
-		 */
-		if (mbase != mend) {
-			icplb_add(mend, SDRAM_IKERNEL);
-			dcplb_add(mend, SDRAM_DKERNEL);
-			++i;
-		}
-	}
-
-#ifndef __ADSPBF60x__
-	icplb_add(0x20000000, SDRAM_INON_CHBL);
-	dcplb_add(0x20000000, SDRAM_EBIU);
-	++i;
-#endif
-
-	/* Add entries for the rest of external RAM up to the bootrom */
-	extern_memory = 0;
-
-#ifdef CONFIG_DEBUG_NULL_PTR
-	icplb_add(extern_memory,
-		  (SDRAM_IKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
-	dcplb_add(extern_memory,
-		  (SDRAM_DKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
-	++i;
-	icplb_add(extern_memory, SDRAM_IKERNEL);
-	dcplb_add(extern_memory, SDRAM_DKERNEL);
-	extern_memory += CPLB_PAGE_SIZE;
-	++i;
-#endif
-
-	while (i < 16 && extern_memory <
-		(CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) {
-		icplb_add(extern_memory, SDRAM_IGENERIC);
-		dcplb_add(extern_memory, SDRAM_DGENERIC);
-		extern_memory += CPLB_EX_PAGE_SIZE;
-		++i;
-	}
-	while (i < 16) {
-		icplb_add(0, 0);
-		dcplb_add(0, 0);
-		++i;
-	}
-}
-
-int print_cpuinfo(void)
-{
-	char buf[32];
-
-	printf("CPU:   ADSP %s (Detected Rev: 0.%d) (%s boot)\n",
-	       gd->bd->bi_cpu,
-	       bfin_revid(),
-	       get_bfin_boot_mode(CONFIG_BFIN_BOOT_MODE));
-
-	printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco()));
-	printf("Core: %s MHz, ", strmhz(buf, get_cclk()));
-#if defined(__ADSPBF60x__)
-	printf("System0: %s MHz, ", strmhz(buf, get_sclk0()));
-	printf("System1: %s MHz, ", strmhz(buf, get_sclk1()));
-	printf("Dclk: %s MHz\n", strmhz(buf, get_dclk()));
-#else
-	printf("System: %s MHz\n", strmhz(buf, get_sclk()));
-#endif
-
-	return 0;
-}
-
-int exception_init(void)
-{
-	bfin_write_EVT3(trap);
-	return 0;
-}
-
-int irq_init(void)
-{
-#ifdef SIC_IMASK0
-	bfin_write_SIC_IMASK0(0);
-	bfin_write_SIC_IMASK1(0);
-# ifdef SIC_IMASK2
-	bfin_write_SIC_IMASK2(0);
-# endif
-#elif defined(SICA_IMASK0)
-	bfin_write_SICA_IMASK0(0);
-	bfin_write_SICA_IMASK1(0);
-#elif defined(SIC_IMASK)
-	bfin_write_SIC_IMASK(0);
-#endif
-	/* Set up a dummy NMI handler if needed.  */
-	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
-		bfin_write_EVT2(evt_nmi);	/* NMI */
-	bfin_write_EVT5(evt_default);	/* hardware error */
-	bfin_write_EVT6(evt_default);	/* core timer */
-	bfin_write_EVT7(evt_default);
-	bfin_write_EVT8(evt_default);
-	bfin_write_EVT9(evt_default);
-	bfin_write_EVT10(evt_default);
-	bfin_write_EVT11(evt_default);
-	bfin_write_EVT12(evt_default);
-	bfin_write_EVT13(evt_default);
-	bfin_write_EVT14(evt_default);
-	bfin_write_EVT15(evt_default);
-	bfin_write_ILAT(0);
-	CSYNC();
-	/* enable hardware error irq */
-	irq_flags = 0x3f;
-	local_irq_enable();
-	return 0;
-}
-
-__attribute__ ((__noreturn__))
-void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
-{
-#ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
-	/* Build a NOP slide over the LDR jump block.  Whee! */
-	char nops[0xC];
-	serial_early_puts("NOP Slide\n");
-	memset(nops, 0x00, sizeof(nops));
-	memcpy((void *)L1_INST_SRAM, nops, sizeof(nops));
-#endif
-
-	if (!loaded_from_ldr) {
-		/* Relocate sections into L1 if the LDR didn't do it -- don't
-		 * check length because the linker script does the size
-		 * checking at build time.
-		 */
-		serial_early_puts("L1 Relocate\n");
-		extern char _stext_l1[], _text_l1_lma[], _text_l1_len[];
-		memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len);
-		extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
-		memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
-	}
-
-	/*
-	 * Make sure our async settings are committed.  Some bootroms
-	 * (like the BF537) will reset some registers on us after it
-	 * has finished loading the LDR.  Or if we're booting over
-	 * JTAG, the initcode never got a chance to run.  Or if we
-	 * aren't booting from parallel flash, the initcode skipped
-	 * this step completely.
-	 */
-	program_async_controller(NULL);
-
-	/* Save RETX so we can pass it while booting Linux */
-	bfin_poweron_retx = bootflag;
-
-#ifdef CONFIG_DEBUG_DUMP
-	/* Turn on hardware trace buffer */
-	bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
-#endif
-
-#ifndef CONFIG_PANIC_HANG
-	/* Reset upon a double exception rather than just hanging.
-	 * Do not do bfin_read on SWRST as that will reset status bits.
-	 */
-# ifdef SWRST
-	bfin_write_SWRST(DOUBLE_FAULT);
-# endif
-#endif
-
-#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
-	bfin_core1_start();
-#endif
-
-	serial_early_puts("Init global data\n");
-	global_board_data_init();
-
-	board_init_f(0);
-
-	/* should not be reached */
-	while (1);
-}
-
-int arch_cpu_init(void)
-{
-	serial_early_puts("Init CPLB tables\n");
-	init_cplbtables();
-
-	serial_early_puts("Exceptions setup\n");
-	exception_init();
-
-#ifndef CONFIG_ICACHE_OFF
-	serial_early_puts("Turn on ICACHE\n");
-	icache_enable();
-#endif
-#ifndef CONFIG_DCACHE_OFF
-	serial_early_puts("Turn on DCACHE\n");
-	dcache_enable();
-#endif
-
-#ifdef DEBUG
-	if (GENERATED_GBL_DATA_SIZE < sizeof(*gd))
-		hang();
-#endif
-
-	/* Initialize */
-	serial_early_puts("IRQ init\n");
-	irq_init();
-
-	return 0;
-}
-
-int arch_misc_init(void)
-{
-#if defined(CONFIG_SYS_I2C)
-	i2c_reloc_fixup();
-#endif
-
-	display_global_data();
-
-	if (CONFIG_MEM_SIZE && bfin_os_log_check()) {
-		puts("\nLog buffer from operating system:\n");
-		bfin_os_log_dump();
-		puts("\n");
-	}
-
-	return 0;
-}
-
-int interrupt_init(void)
-{
-	return 0;
-}
diff --git a/arch/blackfin/cpu/cpu.h b/arch/blackfin/cpu/cpu.h
deleted file mode 100644
index a5fe02e..0000000
--- a/arch/blackfin/cpu/cpu.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- *  U-Boot - cpu.h
- *
- *  Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _CPU_H_
-#define _CPU_H_
-
-#include <command.h>
-
-void board_reset(void) __attribute__((__weak__));
-void bfin_dump(struct pt_regs *reg);
-void bfin_panic(struct pt_regs *reg);
-void dump(struct pt_regs *regs);
-
-asmlinkage void trap(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_default(void);
-
-#endif
diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c
deleted file mode 100644
index 81b7090..0000000
--- a/arch/blackfin/cpu/gpio.c
+++ /dev/null
@@ -1,841 +0,0 @@
-/*
- * ADI GPIO1 Abstraction Layer
- * Support BF50x, BF51x, BF52x, BF53x and BF561 only.
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <common.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-
-#ifndef CONFIG_ADI_GPIO2
-#if ANOMALY_05000311 || ANOMALY_05000323
-enum {
-	AWA_data = SYSCR,
-	AWA_data_clear = SYSCR,
-	AWA_data_set = SYSCR,
-	AWA_toggle = SYSCR,
-	AWA_maska = UART_SCR,
-	AWA_maska_clear = UART_SCR,
-	AWA_maska_set = UART_SCR,
-	AWA_maska_toggle = UART_SCR,
-	AWA_maskb = UART_GCTL,
-	AWA_maskb_clear = UART_GCTL,
-	AWA_maskb_set = UART_GCTL,
-	AWA_maskb_toggle = UART_GCTL,
-	AWA_dir = SPORT1_STAT,
-	AWA_polar = SPORT1_STAT,
-	AWA_edge = SPORT1_STAT,
-	AWA_both = SPORT1_STAT,
-#if ANOMALY_05000311
-	AWA_inen = TIMER_ENABLE,
-#elif ANOMALY_05000323
-	AWA_inen = DMA1_1_CONFIG,
-#endif
-};
-	/* Anomaly Workaround */
-#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
-#else
-#define AWA_DUMMY_READ(...)  do { } while (0)
-#endif
-
-static struct gpio_port_t * const gpio_array[] = {
-#if defined(BF533_FAMILY)
-	(struct gpio_port_t *) FIO_FLAG_D,
-#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) \
-	|| defined(BF538_FAMILY) || defined(CONFIG_BF50x)
-	(struct gpio_port_t *) PORTFIO,
-# if !defined(BF538_FAMILY)
-	(struct gpio_port_t *) PORTGIO,
-	(struct gpio_port_t *) PORTHIO,
-# endif
-#elif defined(BF561_FAMILY)
-	(struct gpio_port_t *) FIO0_FLAG_D,
-	(struct gpio_port_t *) FIO1_FLAG_D,
-	(struct gpio_port_t *) FIO2_FLAG_D,
-#else
-# error no gpio arrays defined
-#endif
-};
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) || \
-    defined(CONFIG_BF50x)
-static unsigned short * const port_fer[] = {
-	(unsigned short *) PORTF_FER,
-	(unsigned short *) PORTG_FER,
-	(unsigned short *) PORTH_FER,
-};
-
-# if !defined(BF537_FAMILY)
-static unsigned short * const port_mux[] = {
-	(unsigned short *) PORTF_MUX,
-	(unsigned short *) PORTG_MUX,
-	(unsigned short *) PORTH_MUX,
-};
-
-static const
-u8 pmux_offset[][16] = {
-#  if defined(CONFIG_BF52x)
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
-	{ 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
-#  elif defined(CONFIG_BF51x)
-	{ 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */
-	{ 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */
-	{ 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */
-#  endif
-};
-# endif
-
-#elif defined(BF538_FAMILY)
-static unsigned short * const port_fer[] = {
-	(unsigned short *) PORTCIO_FER,
-	(unsigned short *) PORTDIO_FER,
-	(unsigned short *) PORTEIO_FER,
-};
-#endif
-
-#ifdef CONFIG_BFIN_GPIO_TRACK
-#define RESOURCE_LABEL_SIZE	16
-
-static struct str_ident {
-	char name[RESOURCE_LABEL_SIZE];
-} str_ident[MAX_RESOURCES];
-
-static void gpio_error(unsigned gpio)
-{
-	printf("bfin-gpio: GPIO %d wasn't requested!\n", gpio);
-}
-
-static void set_label(unsigned short ident, const char *label)
-{
-	if (label) {
-		strncpy(str_ident[ident].name, label,
-			 RESOURCE_LABEL_SIZE);
-		str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
-	}
-}
-
-static char *get_label(unsigned short ident)
-{
-	return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
-}
-
-static int cmp_label(unsigned short ident, const char *label)
-{
-	if (label == NULL)
-		printf("bfin-gpio: please provide none-null label\n");
-
-	if (label)
-		return strcmp(str_ident[ident].name, label);
-	else
-		return -EINVAL;
-}
-
-#define map_entry(m, i)      reserved_##m##_map[gpio_bank(i)]
-#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i))
-#define reserve(m, i)        (map_entry(m, i) |= gpio_bit(i))
-#define unreserve(m, i)      (map_entry(m, i) &= ~gpio_bit(i))
-#define DECLARE_RESERVED_MAP(m, c) static unsigned short reserved_##m##_map[c]
-#else
-#define is_reserved(m, i, e) (!(e))
-#define reserve(m, i)
-#define unreserve(m, i)
-#define DECLARE_RESERVED_MAP(m, c)
-#define gpio_error(gpio)
-#define set_label(...)
-#define get_label(...) ""
-#define cmp_label(...) 1
-#endif
-
-DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
-DECLARE_RESERVED_MAP(peri, gpio_bank(MAX_RESOURCES));
-
-inline int check_gpio(unsigned gpio)
-{
-	if (gpio >= MAX_BLACKFIN_GPIOS)
-		return -EINVAL;
-	return 0;
-}
-
-static void port_setup(unsigned gpio, unsigned short usage)
-{
-#if defined(BF538_FAMILY)
-	/*
-	 * BF538/9 Port C,D and E are special.
-	 * Inverted PORT_FER polarity on CDE and no PORF_FER on F
-	 * Regular PORT F GPIOs are handled here, CDE are exclusively
-	 * managed by GPIOLIB
-	 */
-
-	if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES)
-		return;
-
-	gpio -= MAX_BLACKFIN_GPIOS;
-
-	if (usage == GPIO_USAGE)
-		*port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
-	else
-		*port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
-	SSYNC();
-	return;
-#endif
-
-	if (check_gpio(gpio))
-		return;
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) || \
-    defined(CONFIG_BF50x)
-	if (usage == GPIO_USAGE)
-		*port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
-	else
-		*port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
-	SSYNC();
-#endif
-}
-
-#ifdef BF537_FAMILY
-static struct {
-	unsigned short res;
-	unsigned short offset;
-} port_mux_lut[] = {
-	{.res = P_PPI0_D13, .offset = 11},
-	{.res = P_PPI0_D14, .offset = 11},
-	{.res = P_PPI0_D15, .offset = 11},
-	{.res = P_SPORT1_TFS, .offset = 11},
-	{.res = P_SPORT1_TSCLK, .offset = 11},
-	{.res = P_SPORT1_DTPRI, .offset = 11},
-	{.res = P_PPI0_D10, .offset = 10},
-	{.res = P_PPI0_D11, .offset = 10},
-	{.res = P_PPI0_D12, .offset = 10},
-	{.res = P_SPORT1_RSCLK, .offset = 10},
-	{.res = P_SPORT1_RFS, .offset = 10},
-	{.res = P_SPORT1_DRPRI, .offset = 10},
-	{.res = P_PPI0_D8, .offset = 9},
-	{.res = P_PPI0_D9, .offset = 9},
-	{.res = P_SPORT1_DRSEC, .offset = 9},
-	{.res = P_SPORT1_DTSEC, .offset = 9},
-	{.res = P_TMR2, .offset = 8},
-	{.res = P_PPI0_FS3, .offset = 8},
-	{.res = P_TMR3, .offset = 7},
-	{.res = P_SPI0_SSEL4, .offset = 7},
-	{.res = P_TMR4, .offset = 6},
-	{.res = P_SPI0_SSEL5, .offset = 6},
-	{.res = P_TMR5, .offset = 5},
-	{.res = P_SPI0_SSEL6, .offset = 5},
-	{.res = P_UART1_RX, .offset = 4},
-	{.res = P_UART1_TX, .offset = 4},
-	{.res = P_TMR6, .offset = 4},
-	{.res = P_TMR7, .offset = 4},
-	{.res = P_UART0_RX, .offset = 3},
-	{.res = P_UART0_TX, .offset = 3},
-	{.res = P_DMAR0, .offset = 3},
-	{.res = P_DMAR1, .offset = 3},
-	{.res = P_SPORT0_DTSEC, .offset = 1},
-	{.res = P_SPORT0_DRSEC, .offset = 1},
-	{.res = P_CAN0_RX, .offset = 1},
-	{.res = P_CAN0_TX, .offset = 1},
-	{.res = P_SPI0_SSEL7, .offset = 1},
-	{.res = P_SPORT0_TFS, .offset = 0},
-	{.res = P_SPORT0_DTPRI, .offset = 0},
-	{.res = P_SPI0_SSEL2, .offset = 0},
-	{.res = P_SPI0_SSEL3, .offset = 0},
-};
-
-static void portmux_setup(unsigned short per)
-{
-	u16 y, offset, muxreg, mask;
-	u16 function = P_FUNCT2MUX(per);
-
-	for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
-		if (port_mux_lut[y].res == per) {
-
-			/* SET PORTMUX REG */
-
-			offset = port_mux_lut[y].offset;
-			muxreg = bfin_read_PORT_MUX();
-
-			if (offset == 1)
-				mask = 3;
-			else
-				mask = 1;
-
-			muxreg &= ~(mask << offset);
-			muxreg |= ((function & mask) << offset);
-			bfin_write_PORT_MUX(muxreg);
-		}
-	}
-}
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
-inline void portmux_setup(unsigned short per)
-{
-	u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per);
-	u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
-
-	pmux = *port_mux[gpio_bank(ident)];
-	pmux &= ~(3 << offset);
-	pmux |= (function & 3) << offset;
-	*port_mux[gpio_bank(ident)] = pmux;
-	SSYNC();
-}
-#else
-# define portmux_setup(...)  do { } while (0)
-#endif
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin General Purpose Ports Access Functions
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: These functions abstract direct register access
-*              to Blackfin processor General Purpose
-*              Ports Regsiters
-*
-* CAUTION: These functions do not belong to the GPIO Driver API
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-/* Set a specific bit */
-
-#define SET_GPIO(name) \
-void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
-{ \
-	unsigned long flags; \
-	local_irq_save(flags); \
-	if (arg) \
-		gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
-	else \
-		gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
-	AWA_DUMMY_READ(name); \
-	local_irq_restore(flags); \
-}
-
-SET_GPIO(dir)   /* set_gpio_dir() */
-SET_GPIO(inen)  /* set_gpio_inen() */
-SET_GPIO(polar) /* set_gpio_polar() */
-SET_GPIO(edge)  /* set_gpio_edge() */
-SET_GPIO(both)  /* set_gpio_both() */
-
-
-#define SET_GPIO_SC(name) \
-void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
-{ \
-	unsigned long flags; \
-	if (ANOMALY_05000311 || ANOMALY_05000323) \
-		local_irq_save(flags); \
-	if (arg) \
-		gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
-	else \
-		gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
-	if (ANOMALY_05000311 || ANOMALY_05000323) { \
-		AWA_DUMMY_READ(name); \
-		local_irq_restore(flags); \
-	} \
-}
-
-SET_GPIO_SC(maska)
-SET_GPIO_SC(maskb)
-SET_GPIO_SC(data)
-
-void set_gpio_toggle(unsigned gpio)
-{
-	unsigned long flags;
-	if (ANOMALY_05000311 || ANOMALY_05000323)
-		local_irq_save(flags);
-	gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
-	if (ANOMALY_05000311 || ANOMALY_05000323) {
-		AWA_DUMMY_READ(toggle);
-		local_irq_restore(flags);
-	}
-}
-
-/* Set current PORT date (16-bit word) */
-
-#define SET_GPIO_P(name) \
-void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
-{ \
-	unsigned long flags; \
-	if (ANOMALY_05000311 || ANOMALY_05000323) \
-		local_irq_save(flags); \
-	gpio_array[gpio_bank(gpio)]->name = arg; \
-	if (ANOMALY_05000311 || ANOMALY_05000323) { \
-		AWA_DUMMY_READ(name); \
-		local_irq_restore(flags); \
-	} \
-}
-
-SET_GPIO_P(data)
-SET_GPIO_P(dir)
-SET_GPIO_P(inen)
-SET_GPIO_P(polar)
-SET_GPIO_P(edge)
-SET_GPIO_P(both)
-SET_GPIO_P(maska)
-SET_GPIO_P(maskb)
-
-/* Get a specific bit */
-#define GET_GPIO(name) \
-unsigned short get_gpio_ ## name(unsigned gpio) \
-{ \
-	unsigned long flags; \
-	unsigned short ret; \
-	if (ANOMALY_05000311 || ANOMALY_05000323) \
-		local_irq_save(flags); \
-	ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
-	if (ANOMALY_05000311 || ANOMALY_05000323) { \
-		AWA_DUMMY_READ(name); \
-		local_irq_restore(flags); \
-	} \
-	return ret; \
-}
-
-GET_GPIO(data)
-GET_GPIO(dir)
-GET_GPIO(inen)
-GET_GPIO(polar)
-GET_GPIO(edge)
-GET_GPIO(both)
-GET_GPIO(maska)
-GET_GPIO(maskb)
-
-/* Get current PORT date (16-bit word) */
-
-#define GET_GPIO_P(name) \
-unsigned short get_gpiop_ ## name(unsigned gpio) \
-{ \
-	unsigned long flags; \
-	unsigned short ret; \
-	if (ANOMALY_05000311 || ANOMALY_05000323) \
-		local_irq_save(flags); \
-	ret = (gpio_array[gpio_bank(gpio)]->name); \
-	if (ANOMALY_05000311 || ANOMALY_05000323) { \
-		AWA_DUMMY_READ(name); \
-		local_irq_restore(flags); \
-	} \
-	return ret; \
-}
-
-GET_GPIO_P(data)
-GET_GPIO_P(dir)
-GET_GPIO_P(inen)
-GET_GPIO_P(polar)
-GET_GPIO_P(edge)
-GET_GPIO_P(both)
-GET_GPIO_P(maska)
-GET_GPIO_P(maskb)
-
-/***********************************************************
-*
-* FUNCTIONS:	Blackfin Peripheral Resource Allocation
-*		and PortMux Setup
-*
-* INPUTS/OUTPUTS:
-* per	Peripheral Identifier
-* label	String
-*
-* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int peripheral_request(unsigned short per, const char *label)
-{
-	unsigned short ident = P_IDENT(per);
-
-	/*
-	 * Don't cares are pins with only one dedicated function
-	 */
-
-	if (per & P_DONTCARE)
-		return 0;
-
-	if (!(per & P_DEFINED))
-		return -ENODEV;
-
-	BUG_ON(ident >= MAX_RESOURCES);
-
-	/* If a pin can be muxed as either GPIO or peripheral, make
-	 * sure it is not already a GPIO pin when we request it.
-	 */
-	if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) {
-		printf("%s: Peripheral %d is already reserved as GPIO by %s !\n",
-		       __func__, ident, get_label(ident));
-		return -EBUSY;
-	}
-
-	if (unlikely(is_reserved(peri, ident, 1))) {
-
-		/*
-		 * Pin functions like AMC address strobes my
-		 * be requested and used by several drivers
-		 */
-
-		if (!(per & P_MAYSHARE)) {
-			/*
-			 * Allow that the identical pin function can
-			 * be requested from the same driver twice
-			 */
-
-			if (cmp_label(ident, label) == 0)
-				goto anyway;
-
-			printf("%s: Peripheral %d function %d is already reserved by %s !\n",
-			       __func__, ident, P_FUNCT2MUX(per), get_label(ident));
-			return -EBUSY;
-		}
-	}
-
- anyway:
-	reserve(peri, ident);
-
-	portmux_setup(per);
-	port_setup(ident, PERIPHERAL_USAGE);
-
-	set_label(ident, label);
-
-	return 0;
-}
-
-int peripheral_request_list(const unsigned short per[], const char *label)
-{
-	u16 cnt;
-	int ret;
-
-	for (cnt = 0; per[cnt] != 0; cnt++) {
-
-		ret = peripheral_request(per[cnt], label);
-
-		if (ret < 0) {
-			for ( ; cnt > 0; cnt--)
-				peripheral_free(per[cnt - 1]);
-
-			return ret;
-		}
-	}
-
-	return 0;
-}
-
-void peripheral_free(unsigned short per)
-{
-	unsigned short ident = P_IDENT(per);
-
-	if (per & P_DONTCARE)
-		return;
-
-	if (!(per & P_DEFINED))
-		return;
-
-	if (unlikely(!is_reserved(peri, ident, 0)))
-		return;
-
-	if (!(per & P_MAYSHARE))
-		port_setup(ident, GPIO_USAGE);
-
-	unreserve(peri, ident);
-
-	set_label(ident, "free");
-}
-
-void peripheral_free_list(const unsigned short per[])
-{
-	u16 cnt;
-	for (cnt = 0; per[cnt] != 0; cnt++)
-		peripheral_free(per[cnt]);
-}
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin GPIO Driver
-*
-* INPUTS/OUTPUTS:
-* gpio	PIO Number between 0 and MAX_BLACKFIN_GPIOS
-* label	String
-*
-* DESCRIPTION: Blackfin GPIO Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int gpio_request(unsigned gpio, const char *label)
-{
-	if (check_gpio(gpio) < 0)
-		return -EINVAL;
-
-	/*
-	 * Allow that the identical GPIO can
-	 * be requested from the same driver twice
-	 * Do nothing and return -
-	 */
-
-	if (cmp_label(gpio, label) == 0)
-		return 0;
-
-	if (unlikely(is_reserved(gpio, gpio, 1))) {
-		printf("bfin-gpio: GPIO %d is already reserved by %s !\n",
-		       gpio, get_label(gpio));
-		return -EBUSY;
-	}
-	if (unlikely(is_reserved(peri, gpio, 1))) {
-		printf("bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
-		       gpio, get_label(gpio));
-		return -EBUSY;
-	}
-	else {	/* Reset POLAR setting when acquiring a gpio for the first time */
-		set_gpio_polar(gpio, 0);
-	}
-
-	reserve(gpio, gpio);
-	set_label(gpio, label);
-
-	port_setup(gpio, GPIO_USAGE);
-
-	return 0;
-}
-
-int gpio_free(unsigned gpio)
-{
-	if (check_gpio(gpio) < 0)
-		return -1;
-
-	if (unlikely(!is_reserved(gpio, gpio, 0))) {
-		gpio_error(gpio);
-		return -1;
-	}
-
-	unreserve(gpio, gpio);
-
-	set_label(gpio, "free");
-
-	return 0;
-}
-
-#ifdef ADI_SPECIAL_GPIO_BANKS
-DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
-
-int special_gpio_request(unsigned gpio, const char *label)
-{
-	/*
-	 * Allow that the identical GPIO can
-	 * be requested from the same driver twice
-	 * Do nothing and return -
-	 */
-
-	if (cmp_label(gpio, label) == 0)
-		return 0;
-
-	if (unlikely(is_reserved(special_gpio, gpio, 1))) {
-		printf("bfin-gpio: GPIO %d is already reserved by %s !\n",
-		       gpio, get_label(gpio));
-		return -EBUSY;
-	}
-	if (unlikely(is_reserved(peri, gpio, 1))) {
-		printf("bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
-		       gpio, get_label(gpio));
-
-		return -EBUSY;
-	}
-
-	reserve(special_gpio, gpio);
-	reserve(peri, gpio);
-
-	set_label(gpio, label);
-	port_setup(gpio, GPIO_USAGE);
-
-	return 0;
-}
-
-void special_gpio_free(unsigned gpio)
-{
-	if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
-		gpio_error(gpio);
-		return;
-	}
-
-	unreserve(special_gpio, gpio);
-	unreserve(peri, gpio);
-	set_label(gpio, "free");
-}
-#endif
-
-static inline void __gpio_direction_input(unsigned gpio)
-{
-	gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
-	gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
-}
-
-int gpio_direction_input(unsigned gpio)
-{
-	unsigned long flags;
-
-	if (!is_reserved(gpio, gpio, 0)) {
-		gpio_error(gpio);
-		return -EINVAL;
-	}
-
-	local_irq_save(flags);
-	__gpio_direction_input(gpio);
-	AWA_DUMMY_READ(inen);
-	local_irq_restore(flags);
-
-	return 0;
-}
-
-int gpio_set_value(unsigned gpio, int arg)
-{
-	if (arg)
-		gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
-	else
-		gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
-
-	return 0;
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-	unsigned long flags;
-
-	if (!is_reserved(gpio, gpio, 0)) {
-		gpio_error(gpio);
-		return -EINVAL;
-	}
-
-	local_irq_save(flags);
-
-	gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
-	gpio_set_value(gpio, value);
-	gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
-
-	AWA_DUMMY_READ(dir);
-	local_irq_restore(flags);
-
-	return 0;
-}
-
-int gpio_get_value(unsigned gpio)
-{
-	unsigned long flags;
-
-	if (unlikely(get_gpio_edge(gpio))) {
-		int ret;
-		local_irq_save(flags);
-		set_gpio_edge(gpio, 0);
-		ret = get_gpio_data(gpio);
-		set_gpio_edge(gpio, 1);
-		local_irq_restore(flags);
-		return ret;
-	} else
-		return get_gpio_data(gpio);
-}
-
-/* If we are booting from SPI and our board lacks a strong enough pull up,
- * the core can reset and execute the bootrom faster than the resistor can
- * pull the signal logically high.  To work around this (common) error in
- * board design, we explicitly set the pin back to GPIO mode, force /CS
- * high, and wait for the electrons to do their thing.
- *
- * This function only makes sense to be called from reset code, but it
- * lives here as we need to force all the GPIO states w/out going through
- * BUG() checks and such.
- */
-void bfin_reset_boot_spi_cs(unsigned short pin)
-{
-	unsigned short gpio = P_IDENT(pin);
-	port_setup(gpio, GPIO_USAGE);
-	gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
-	AWA_DUMMY_READ(data_set);
-	udelay(1);
-}
-
-int name_to_gpio(const char *name)
-{
-	int port_base;
-
-	if (tolower(*name) == 'p') {
-		++name;
-
-		switch (tolower(*name)) {
-#ifdef GPIO_PA0
-		case 'a': port_base = GPIO_PA0; break;
-#endif
-#ifdef GPIO_PB0
-		case 'b': port_base = GPIO_PB0; break;
-#endif
-#ifdef GPIO_PC0
-		case 'c': port_base = GPIO_PC0; break;
-#endif
-#ifdef GPIO_PD0
-		case 'd': port_base = GPIO_PD0; break;
-#endif
-#ifdef GPIO_PE0
-		case 'e': port_base = GPIO_PE0; break;
-#endif
-#ifdef GPIO_PF0
-		case 'f': port_base = GPIO_PF0; break;
-#endif
-#ifdef GPIO_PG0
-		case 'g': port_base = GPIO_PG0; break;
-#endif
-#ifdef GPIO_PH0
-		case 'h': port_base = GPIO_PH0; break;
-#endif
-#ifdef GPIO_PI0
-		case 'i': port_base = GPIO_PI0; break;
-#endif
-#ifdef GPIO_PJ
-		case 'j': port_base = GPIO_PJ0; break;
-#endif
-		default:  return -1;
-		}
-
-		++name;
-	} else
-		port_base = 0;
-
-	return port_base + simple_strtoul(name, NULL, 10);
-}
-
-void gpio_labels(void)
-{
-	int c, gpio;
-
-	for (c = 0; c < MAX_RESOURCES; c++) {
-		gpio = is_reserved(gpio, c, 1);
-		if (!check_gpio(c) && gpio)
-			printf("GPIO_%d:\t%s\tGPIO %s\n", c,
-				get_label(c),
-				get_gpio_dir(c) ? "OUTPUT" : "INPUT");
-		else if (is_reserved(peri, c, 1))
-			printf("GPIO_%d:\t%s\tPeripheral\n", c, get_label(c));
-		else
-			continue;
-	}
-}
-#else
-struct gpio_port_t * const gpio_array[] = {
-	(struct gpio_port_t *)PORTA_FER,
-	(struct gpio_port_t *)PORTB_FER,
-	(struct gpio_port_t *)PORTC_FER,
-	(struct gpio_port_t *)PORTD_FER,
-	(struct gpio_port_t *)PORTE_FER,
-	(struct gpio_port_t *)PORTF_FER,
-	(struct gpio_port_t *)PORTG_FER,
-#if defined(CONFIG_BF54x)
-	(struct gpio_port_t *)PORTH_FER,
-	(struct gpio_port_t *)PORTI_FER,
-	(struct gpio_port_t *)PORTJ_FER,
-#endif
-};
-#endif
diff --git a/arch/blackfin/cpu/init.S b/arch/blackfin/cpu/init.S
deleted file mode 100644
index f48c113..0000000
--- a/arch/blackfin/cpu/init.S
+++ /dev/null
@@ -1,9 +0,0 @@
-#include <asm/blackfin.h>
-ENTRY(_start)
-	sp.l = LO(L1_SRAM_SCRATCH_END - 20);
-	sp.h = HI(L1_SRAM_SCRATCH_END - 20);
-	call _initcode;
-1:
-	emuexcpt;
-	jump 1b;
-END(_start)
diff --git a/arch/blackfin/cpu/init.lds.S b/arch/blackfin/cpu/init.lds.S
deleted file mode 100644
index 602e7c8..0000000
--- a/arch/blackfin/cpu/init.lds.S
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * linker script for simple init.elf
- *
- * Copyright (c) 2005-2011 Analog Device Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#undef ALIGN
-#undef ENTRY
-
-OUTPUT_ARCH(bfin)
-
-MEMORY
-{
-	l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
-}
-
-ENTRY(_start)
-SECTIONS
-{
-	.text.l1 : { *(.text .text.*) } >l1_code
-}
diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c
deleted file mode 100644
index fde54ea..0000000
--- a/arch/blackfin/cpu/initcode.c
+++ /dev/null
@@ -1,1041 +0,0 @@
-/*
- * initcode.c - Initialize the processor.  This is usually entails things
- * like external memory, voltage regulators, etc...  Note that this file
- * cannot make any function calls as it may be executed all by itself by
- * the Blackfin's bootrom in LDR format.
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define BFIN_IN_INITCODE
-
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/watchdog.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/serial.h>
-
-#ifndef __ADSPBF60x__
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#else /* __ADSPBF60x__ */
-#include <asm/mach-common/bits/cgu.h>
-
-#define CONFIG_BFIN_GET_DCLK_M \
-	((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000))
-
-#ifndef CONFIG_DMC_DDRCFG
-#if ((CONFIG_BFIN_GET_DCLK_M != 125) && \
-	(CONFIG_BFIN_GET_DCLK_M != 133) && \
-	(CONFIG_BFIN_GET_DCLK_M != 150) && \
-	(CONFIG_BFIN_GET_DCLK_M != 166) && \
-	(CONFIG_BFIN_GET_DCLK_M != 200) && \
-	(CONFIG_BFIN_GET_DCLK_M != 225) && \
-	(CONFIG_BFIN_GET_DCLK_M != 250))
-#error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
-#endif
-#endif
-
-/* DMC control bits */
-#define SRREQ			0x8
-
-/* DMC status bits */
-#define IDLE                    0x1
-#define MEMINITDONE             0x4
-#define SRACK                   0x8
-#define PDACK                   0x10
-#define DPDACK                  0x20
-#define DLLCALDONE              0x2000
-#define PENDREF                 0xF0000
-#define PHYRDPHASE              0xF00000
-#define PHYRDPHASE_OFFSET       20
-
-/* DMC DLL control bits */
-#define DLLCALRDCNT             0xFF
-#define DATACYC_OFFSET          8
-
-struct ddr_config {
-	u32 ddr_clk;
-	u32 dmc_ddrctl;
-	u32 dmc_ddrcfg;
-	u32 dmc_ddrtr0;
-	u32 dmc_ddrtr1;
-	u32 dmc_ddrtr2;
-	u32 dmc_ddrmr;
-	u32 dmc_ddrmr1;
-};
-
-static struct ddr_config ddr_config_table[] = {
-	[0] = {
-		.ddr_clk    = 125,	/* 125MHz */
-		.dmc_ddrctl = 0x00000904,
-		.dmc_ddrcfg = 0x00000422,
-		.dmc_ddrtr0 = 0x20705212,
-		.dmc_ddrtr1 = 0x201003CF,
-		.dmc_ddrtr2 = 0x00320107,
-		.dmc_ddrmr  = 0x00000422,
-		.dmc_ddrmr1 = 0x4,
-	},
-	[1] = {
-		.ddr_clk    = 133,	/* 133MHz */
-		.dmc_ddrctl = 0x00000904,
-		.dmc_ddrcfg = 0x00000422,
-		.dmc_ddrtr0 = 0x20806313,
-		.dmc_ddrtr1 = 0x2013040D,
-		.dmc_ddrtr2 = 0x00320108,
-		.dmc_ddrmr  = 0x00000632,
-		.dmc_ddrmr1 = 0x4,
-	},
-	[2] = {
-		.ddr_clk    = 150,	/* 150MHz */
-		.dmc_ddrctl = 0x00000904,
-		.dmc_ddrcfg = 0x00000422,
-		.dmc_ddrtr0 = 0x20A07323,
-		.dmc_ddrtr1 = 0x20160492,
-		.dmc_ddrtr2 = 0x00320209,
-		.dmc_ddrmr  = 0x00000632,
-		.dmc_ddrmr1 = 0x4,
-	},
-	[3] = {
-		.ddr_clk    = 166,	/* 166MHz */
-		.dmc_ddrctl = 0x00000904,
-		.dmc_ddrcfg = 0x00000422,
-		.dmc_ddrtr0 = 0x20A07323,
-		.dmc_ddrtr1 = 0x2016050E,
-		.dmc_ddrtr2 = 0x00320209,
-		.dmc_ddrmr  = 0x00000632,
-		.dmc_ddrmr1 = 0x4,
-	},
-	[4] = {
-		.ddr_clk    = 200,	/* 200MHz */
-		.dmc_ddrctl = 0x00000904,
-		.dmc_ddrcfg = 0x00000422,
-		.dmc_ddrtr0 = 0x20a07323,
-		.dmc_ddrtr1 = 0x2016050f,
-		.dmc_ddrtr2 = 0x00320509,
-		.dmc_ddrmr  = 0x00000632,
-		.dmc_ddrmr1 = 0x4,
-	},
-	[5] = {
-		.ddr_clk    = 225,	/* 225MHz */
-		.dmc_ddrctl = 0x00000904,
-		.dmc_ddrcfg = 0x00000422,
-		.dmc_ddrtr0 = 0x20E0A424,
-		.dmc_ddrtr1 = 0x302006DB,
-		.dmc_ddrtr2 = 0x0032020D,
-		.dmc_ddrmr  = 0x00000842,
-		.dmc_ddrmr1 = 0x4,
-	},
-	[6] = {
-		.ddr_clk    = 250,	/* 250MHz */
-		.dmc_ddrctl = 0x00000904,
-		.dmc_ddrcfg = 0x00000422,
-		.dmc_ddrtr0 = 0x20E0A424,
-		.dmc_ddrtr1 = 0x3020079E,
-		.dmc_ddrtr2 = 0x0032050D,
-		.dmc_ddrmr  = 0x00000842,
-		.dmc_ddrmr1 = 0x4,
-	},
-};
-#endif /* __ADSPBF60x__ */
-
-__attribute__((always_inline))
-static inline void serial_init(void)
-{
-#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
-# ifdef BFIN_BOOT_UART_USE_RTS
-#  define BFIN_UART_USE_RTS 1
-# else
-#  define BFIN_UART_USE_RTS 0
-# endif
-	if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
-		uint32_t uart_base = UART_BASE;
-		size_t i;
-
-		/* force RTS rather than relying on auto RTS */
-#if BFIN_UART_HW_VER < 4
-		bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
-#else
-		bfin_write32(&pUART->control, bfin_read32(&pUART->control) |
-				FCPOL);
-#endif
-
-		/* Wait for the line to clear up.  We cannot rely on UART
-		 * registers as none of them reflect the status of the RSR.
-		 * Instead, we'll sleep for ~10 bit times at 9600 baud.
-		 * We can precalc things here by assuming boot values for
-		 * PLL rather than loading registers and calculating.
-		 *	baud    = SCLK / (16 ^ (1 - EDBO) * Divisor)
-		 *	EDB0    = 0
-		 *	Divisor = (SCLK / baud) / 16
-		 *	SCLK    = baud * 16 * Divisor
-		 *	SCLK    = (0x14 * CONFIG_CLKIN_HZ) / 5
-		 *	CCLK    = (16 * Divisor * 5) * (9600 / 10)
-		 * In reality, this will probably be just about 1 second delay,
-		 * so assuming 9600 baud is OK (both as a very low and too high
-		 * speed as this will buffer things enough).
-		 */
-#define _NUMBITS (10)                                   /* how many bits to delay */
-#define _LOWBAUD (9600)                                 /* low baud rate */
-#define _SCLK    ((0x14 * CONFIG_CLKIN_HZ) / 5)         /* SCLK based on PLL */
-#define _DIVISOR ((_SCLK / _LOWBAUD) / 16)              /* UART DLL/DLH */
-#define _NUMINS  (3)                                    /* how many instructions in loop */
-#define _CCLK    (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
-		i = _CCLK;
-		while (i--)
-			asm volatile("" : : : "memory");
-	}
-#endif
-
-#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS
-	if (BFIN_DEBUG_EARLY_SERIAL) {
-		serial_early_init(UART_BASE);
-		serial_early_set_baud(UART_BASE, CONFIG_BAUDRATE);
-	}
-#endif
-}
-
-__attribute__((always_inline))
-static inline void serial_deinit(void)
-{
-#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
-	uint32_t uart_base = UART_BASE;
-
-	if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
-		/* clear forced RTS rather than relying on auto RTS */
-#if BFIN_UART_HW_VER < 4
-		bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
-#else
-		bfin_write32(&pUART->control, bfin_read32(&pUART->control) &
-				~FCPOL);
-#endif
-	}
-#endif
-}
-
-__attribute__((always_inline))
-static inline void serial_putc(char c)
-{
-	uint32_t uart_base = UART_BASE;
-
-	if (!BFIN_DEBUG_EARLY_SERIAL)
-		return;
-
-	if (c == '\n')
-		serial_putc('\r');
-
-	bfin_write(&pUART->thr, c);
-
-	while (!(_lsr_read(pUART) & TEMT))
-		continue;
-}
-
-#include "initcode.h"
-
-__attribute__((always_inline)) static inline void
-program_nmi_handler(void)
-{
-	u32 tmp1, tmp2;
-
-	/* Older bootroms don't create a dummy NMI handler,
-	 * so make one ourselves ASAP in case it fires.
-	 */
-	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
-		return;
-
-	asm volatile (
-		"%0 = RETS;" /* Save current RETS */
-		"CALL 1f;"   /* Figure out current PC */
-		"RTN;"       /* The simple NMI handler */
-		"1:"
-		"%1 = RETS;" /* Load addr of NMI handler */
-		"RETS = %0;" /* Restore RETS */
-		"[%2] = %1;" /* Write NMI handler */
-		: "=d"(tmp1), "=d"(tmp2)
-		: "ab"(EVT2)
-	);
-}
-
-/* Max SCLK can be 133MHz ... dividing that by (2*4) gives
- * us a freq of 16MHz for SPI which should generally be
- * slow enough for the slow reads the bootrom uses.
- */
-#if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
-    ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
-     (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
-# define BOOTROM_SUPPORTS_SPI_FAST_READ 1
-#else
-# define BOOTROM_SUPPORTS_SPI_FAST_READ 0
-#endif
-#ifndef CONFIG_SPI_BAUD_INITBLOCK
-# define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
-#endif
-#ifdef SPI0_BAUD
-# define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
-#endif
-
-#ifdef __ADSPBF60x__
-
-#ifndef CONFIG_CGU_CTL_VAL
-# define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
-#endif
-
-#ifndef CONFIG_CGU_DIV_VAL
-# define CONFIG_CGU_DIV_VAL \
-	((CONFIG_CCLK_DIV   << CSEL_P)   | \
-	 (CONFIG_SCLK0_DIV  << S0SEL_P)  | \
-	 (CONFIG_SCLK_DIV << SYSSEL_P) | \
-	 (CONFIG_SCLK1_DIV  << S1SEL_P)  | \
-	 (CONFIG_DCLK_DIV   << DSEL_P)   | \
-	 (CONFIG_OCLK_DIV   << OSEL_P))
-#endif
-
-#else /* __ADSPBF60x__ */
-
-/* PLL_DIV defines */
-#ifndef CONFIG_PLL_DIV_VAL
-# if (CONFIG_CCLK_DIV == 1)
-#  define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-# elif (CONFIG_CCLK_DIV == 2)
-#  define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-# elif (CONFIG_CCLK_DIV == 4)
-#  define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-# elif (CONFIG_CCLK_DIV == 8)
-#  define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-# else
-#  define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-# endif
-# define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
-#endif
-
-#ifndef CONFIG_PLL_LOCKCNT_VAL
-# define CONFIG_PLL_LOCKCNT_VAL 0x0300
-#endif
-
-#ifndef CONFIG_PLL_CTL_VAL
-# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
-#endif
-
-/* Make sure our voltage value is sane so we don't blow up! */
-#ifndef CONFIG_VR_CTL_VAL
-# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
-# if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
-#  define CCLK_VLEV_120	400000000
-#  define CCLK_VLEV_125	533000000
-# elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
-#  define CCLK_VLEV_120	401000000
-#  define CCLK_VLEV_125	401000000
-# elif defined(__ADSPBF561__)
-#  define CCLK_VLEV_120	300000000
-#  define CCLK_VLEV_125	501000000
-# endif
-# if BFIN_CCLK < CCLK_VLEV_120
-#  define CONFIG_VR_CTL_VLEV VLEV_120
-# elif BFIN_CCLK < CCLK_VLEV_125
-#  define CONFIG_VR_CTL_VLEV VLEV_125
-# else
-#  define CONFIG_VR_CTL_VLEV VLEV_130
-# endif
-# if defined(__ADSPBF52x__)	/* TBD; use default */
-#  undef CONFIG_VR_CTL_VLEV
-#  define CONFIG_VR_CTL_VLEV VLEV_110
-# elif defined(__ADSPBF54x__)	/* TBD; use default */
-#  undef CONFIG_VR_CTL_VLEV
-#  define CONFIG_VR_CTL_VLEV VLEV_120
-# elif defined(__ADSPBF538__) || defined(__ADSPBF539__)	/* TBD; use default */
-#  undef CONFIG_VR_CTL_VLEV
-#  define CONFIG_VR_CTL_VLEV VLEV_125
-# endif
-
-# ifdef CONFIG_BFIN_MAC
-#  define CONFIG_VR_CTL_CLKBUF CLKBUFOE
-# else
-#  define CONFIG_VR_CTL_CLKBUF 0
-# endif
-
-# if defined(__ADSPBF52x__)
-#  define CONFIG_VR_CTL_FREQ FREQ_1000
-# else
-#  define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
-# endif
-
-# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
-#endif
-
-/* some parts do not have an on-chip voltage regulator */
-#if defined(__ADSPBF51x__)
-# define CONFIG_HAS_VR 0
-# undef CONFIG_VR_CTL_VAL
-# define CONFIG_VR_CTL_VAL 0
-#else
-# define CONFIG_HAS_VR 1
-#endif
-
-#if CONFIG_MEM_SIZE
-#ifndef EBIU_RSTCTL
-/* Blackfin with SDRAM */
-#ifndef CONFIG_EBIU_SDBCTL_VAL
-# if CONFIG_MEM_SIZE == 16
-#  define CONFIG_EBSZ_VAL EBSZ_16
-# elif CONFIG_MEM_SIZE == 32
-#  define CONFIG_EBSZ_VAL EBSZ_32
-# elif CONFIG_MEM_SIZE == 64
-#  define CONFIG_EBSZ_VAL EBSZ_64
-# elif CONFIG_MEM_SIZE == 128
-#  define CONFIG_EBSZ_VAL EBSZ_128
-# elif CONFIG_MEM_SIZE == 256
-#  define CONFIG_EBSZ_VAL EBSZ_256
-# elif CONFIG_MEM_SIZE == 512
-#  define CONFIG_EBSZ_VAL EBSZ_512
-# else
-#  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
-# endif
-# if CONFIG_MEM_ADD_WDTH == 8
-#  define CONFIG_EBCAW_VAL EBCAW_8
-# elif CONFIG_MEM_ADD_WDTH == 9
-#  define CONFIG_EBCAW_VAL EBCAW_9
-# elif CONFIG_MEM_ADD_WDTH == 10
-#  define CONFIG_EBCAW_VAL EBCAW_10
-# elif CONFIG_MEM_ADD_WDTH == 11
-#  define CONFIG_EBCAW_VAL EBCAW_11
-# else
-#  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
-# endif
-# define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
-#endif
-#endif
-#endif
-
-/* Conflicting Column Address Widths Causes SDRAM Errors:
- * EB2CAW and EB3CAW must be the same
- */
-#if ANOMALY_05000362
-# if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
-#  error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
-# endif
-#endif
-
-#endif /*  __ADSPBF60x__ */
-
-__attribute__((always_inline)) static inline void
-program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
-{
-	serial_putc('a');
-
-	/* Save the clock pieces that are used in baud rate calculation */
-	if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
-		serial_putc('b');
-#ifdef __ADSPBF60x__
-		*sdivB = bfin_read_CGU_DIV();
-		*sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7);
-		*vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f;
-#else
-		*sdivB = bfin_read_PLL_DIV() & 0xf;
-		*vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
-#endif
-		*divB = serial_early_get_div();
-		serial_putc('c');
-	}
-
-	serial_putc('d');
-
-#ifdef CONFIG_HW_WATCHDOG
-# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
-#  define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
-# endif
-	/* Program the watchdog with an initial timeout of ~20 seconds.
-	 * Hopefully that should be long enough to load the u-boot LDR
-	 * (from wherever) and then the common u-boot code can take over.
-	 * In bypass mode, the start.S would have already set a much lower
-	 * timeout, so don't clobber that.
-	 */
-	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
-		serial_putc('e');
-#ifdef __ADSPBF60x__
-		/* Reset system event controller */
-		bfin_write_SEC_GCTL(0x2);
-		bfin_write_SEC_CCTL(0x2);
-		SSYNC();
-
-		/* Enable fault event input and system reset action in fault
-		 * controller. Route watchdog timeout event to fault interface.
-		 */
-		bfin_write_SEC_FCTL(0xc1);
-		/* Enable watchdog interrupt source */
-		bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
-		SSYNC();
-
-		/* Enable system event controller */
-		bfin_write_SEC_GCTL(0x1);
-		bfin_write_SEC_CCTL(0x1);
-		SSYNC();
-#endif
-		bfin_write_WDOG_CTL(WDDIS);
-		SSYNC();
-		bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
-#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART
-		bfin_write_WDOG_CTL(WDEN);
-#endif
-		serial_putc('f');
-	}
-#endif
-
-	serial_putc('g');
-
-	/* Blackfin bootroms use the SPI slow read opcode instead of the SPI
-	 * fast read, so we need to slow down the SPI clock a lot more during
-	 * boot.  Once we switch over to u-boot's SPI flash driver, we'll
-	 * increase the speed appropriately.
-	 */
-#ifdef SPI_BAUD
-	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
-		serial_putc('h');
-		if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
-			bs->dFlags |= BFLAG_FASTREAD;
-		bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
-		serial_putc('i');
-	}
-#endif
-
-	serial_putc('j');
-}
-
-__attribute__((always_inline)) static inline bool
-maybe_self_refresh(ADI_BOOT_DATA *bs)
-{
-	serial_putc('a');
-
-	if (!CONFIG_MEM_SIZE)
-		return false;
-
-#ifdef __ADSPBF60x__
-	/* resume from hibernate, return false let ddr initialize */
-	if ((bfin_read32(DPM0_STAT) & 0xF0) == 0x50) {
-		serial_putc('b');
-		return false;
-	}
-
-#else /* __ADSPBF60x__ */
-
-	/* If external memory is enabled, put it into self refresh first. */
-#if defined(EBIU_RSTCTL)
-	if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
-		serial_putc('b');
-		bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
-		return true;
-	}
-#elif defined(EBIU_SDGCTL)
-	if (bfin_read_EBIU_SDBCTL() & EBE) {
-		serial_putc('b');
-		bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
-		return true;
-	}
-#endif
-
-#endif /* __ADSPBF60x__ */
-	serial_putc('c');
-
-	return false;
-}
-
-__attribute__((always_inline)) static inline u16
-program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
-{
-	u16 vr_ctl = 0;
-
-	serial_putc('a');
-
-#ifdef __ADSPBF60x__
-	if (bfin_read_DMC0_STAT() & MEMINITDONE) {
-		bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
-		SSYNC();
-		while (!(bfin_read_DMC0_STAT() & SRACK))
-			continue;
-	}
-
-	/* Don't set the same value of MSEL and DF to CGU_CTL */
-	if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK))
-			!= CONFIG_CGU_CTL_VAL) {
-		bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL);
-		bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL);
-		while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) ||
-				!(bfin_read_CGU_STAT() & PLLLK))
-			continue;
-	}
-
-	bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT);
-	while (bfin_read_CGU_STAT() & CLKSALGN)
-		continue;
-
-	if (bfin_read_DMC0_STAT() & MEMINITDONE) {
-		bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
-		SSYNC();
-		while (bfin_read_DMC0_STAT() & SRACK)
-			continue;
-	}
-
-#else /* __ADSPBF60x__ */
-
-	vr_ctl = bfin_read_VR_CTL();
-
-	serial_putc('b');
-
-	/* If we're entering self refresh, make sure it has happened. */
-	if (put_into_srfs)
-#if defined(EBIU_RSTCTL)
-		while (!(bfin_read_EBIU_RSTCTL() & SRACK))
-			continue;
-#elif defined(EBIU_SDGCTL)
-		while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
-			continue;
-#else
-		;
-#endif
-
-	serial_putc('c');
-
-	/* With newer bootroms, we use the helper function to set up
-	 * the memory controller.  Older bootroms lacks such helpers
-	 * so we do it ourselves.
-	 */
-	if (!ANOMALY_05000386) {
-		serial_putc('d');
-
-		/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
-		ADI_SYSCTRL_VALUES memory_settings;
-		uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
-		if (!ANOMALY_05000440)
-			actions |= SYSCTRL_PLLDIV;
-		if (CONFIG_HAS_VR) {
-			actions |= SYSCTRL_VRCTL;
-			if (CONFIG_VR_CTL_VAL & FREQ_MASK)
-				actions |= SYSCTRL_INTVOLTAGE;
-			else
-				actions |= SYSCTRL_EXTVOLTAGE;
-			memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
-		} else
-			actions |= SYSCTRL_EXTVOLTAGE;
-		memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
-		memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
-		memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
-#if ANOMALY_05000432
-		bfin_write_SIC_IWR1(0);
-#endif
-		serial_putc('e');
-		bfrom_SysControl(actions, &memory_settings, NULL);
-		serial_putc('f');
-		if (ANOMALY_05000440)
-			bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
-#if ANOMALY_05000432
-		bfin_write_SIC_IWR1(-1);
-#endif
-#if ANOMALY_05000171
-		bfin_write_SICA_IWR0(-1);
-		bfin_write_SICA_IWR1(-1);
-#endif
-		serial_putc('g');
-	} else {
-		serial_putc('h');
-
-		/* Disable all peripheral wakeups except for the PLL event. */
-#ifdef SIC_IWR0
-		bfin_write_SIC_IWR0(1);
-		bfin_write_SIC_IWR1(0);
-# ifdef SIC_IWR2
-		bfin_write_SIC_IWR2(0);
-# endif
-#elif defined(SICA_IWR0)
-		bfin_write_SICA_IWR0(1);
-		bfin_write_SICA_IWR1(0);
-#elif defined(SIC_IWR)
-		bfin_write_SIC_IWR(1);
-#endif
-
-		serial_putc('i');
-
-		/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
-		bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
-
-		serial_putc('j');
-
-		/* Only reprogram when needed to avoid triggering unnecessary
-		 * PLL relock sequences.
-		 */
-		if (vr_ctl != CONFIG_VR_CTL_VAL) {
-			serial_putc('?');
-			bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
-			asm("idle;");
-			serial_putc('!');
-		}
-
-		serial_putc('k');
-
-		bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
-
-		serial_putc('l');
-
-		/* Only reprogram when needed to avoid triggering unnecessary
-		 * PLL relock sequences.
-		 */
-		if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
-			serial_putc('?');
-			bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
-			asm("idle;");
-			serial_putc('!');
-		}
-
-		serial_putc('m');
-
-		/* Restore all peripheral wakeups. */
-#ifdef SIC_IWR0
-		bfin_write_SIC_IWR0(-1);
-		bfin_write_SIC_IWR1(-1);
-# ifdef SIC_IWR2
-		bfin_write_SIC_IWR2(-1);
-# endif
-#elif defined(SICA_IWR0)
-		bfin_write_SICA_IWR0(-1);
-		bfin_write_SICA_IWR1(-1);
-#elif defined(SIC_IWR)
-		bfin_write_SIC_IWR(-1);
-#endif
-
-		serial_putc('n');
-	}
-
-#endif /* __ADSPBF60x__ */
-
-	serial_putc('o');
-
-	return vr_ctl;
-}
-
-__attribute__((always_inline)) static inline void
-update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
-{
-	/* Since we've changed the SCLK above, we may need to update
-	 * the UART divisors (UART baud rates are based on SCLK).
-	 * Do the division by hand as there are no native instructions
-	 * for dividing which means we'd generate a libgcc reference.
-	 */
-	unsigned int sdivR, vcoR;
-	unsigned int dividend;
-	unsigned int divisor;
-	unsigned int quotient;
-
-	serial_putc('a');
-
-	if (BFIN_DEBUG_EARLY_SERIAL ||
-		CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
-#ifdef __ADSPBF60x__
-	sdivR = bfin_read_CGU_DIV();
-	sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
-	vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
-#else
-	sdivR = bfin_read_PLL_DIV() & 0xf;
-	vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
-#endif
-
-	dividend = sdivB * divB * vcoR;
-	divisor = vcoB * sdivR;
-	quotient = early_division(dividend, divisor);
-	serial_early_put_div(quotient - ANOMALY_05000230);
-	}
-
-	serial_putc('c');
-}
-
-__attribute__((always_inline)) static inline void
-program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
-{
-	serial_putc('a');
-
-	if (!CONFIG_MEM_SIZE)
-		return;
-
-	serial_putc('b');
-
-#ifdef __ADSPBF60x__
-	int dlldatacycle;
-	int dll_ctl;
-	int i = 0;
-
-	if (CONFIG_BFIN_GET_DCLK_M ==  125)
-		i = 0;
-	else if (CONFIG_BFIN_GET_DCLK_M ==  133)
-		i = 1;
-	else if (CONFIG_BFIN_GET_DCLK_M ==  150)
-		i = 2;
-	else if (CONFIG_BFIN_GET_DCLK_M ==  166)
-		i = 3;
-	else if (CONFIG_BFIN_GET_DCLK_M ==  200)
-		i = 4;
-	else if (CONFIG_BFIN_GET_DCLK_M ==  225)
-		i = 5;
-	else if (CONFIG_BFIN_GET_DCLK_M ==  250)
-		i = 6;
-
-#if 0
-	for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++)
-		if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk)
-			break;
-#endif
-
-#ifndef CONFIG_DMC_DDRCFG
-	bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
-#else
-	bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG);
-#endif
-#ifndef CONFIG_DMC_DDRTR0
-	bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
-#else
-	bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0);
-#endif
-#ifndef CONFIG_DMC_DDRTR1
-	bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
-#else
-	bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1);
-#endif
-#ifndef CONFIG_DMC_DDRTR2
-	bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
-#else
-	bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2);
-#endif
-#ifndef CONFIG_DMC_DDRMR
-	bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
-#else
-	bfin_write_DMC0_MR(CONFIG_DMC_DDRMR);
-#endif
-#ifndef CONFIG_DMC_DDREMR1
-	bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
-#else
-	bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1);
-#endif
-#ifndef CONFIG_DMC_DDRCTL
-	bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
-#else
-	bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL);
-#endif
-
-	SSYNC();
-	while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
-		continue;
-
-	dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >>
-			PHYRDPHASE_OFFSET;
-	dll_ctl = bfin_read_DMC0_DLLCTL();
-	dll_ctl &= 0x0ff;
-	bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
-
-	SSYNC();
-	while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
-		continue;
-	serial_putc('!');
-
-#else /* __ADSPBF60x__ */
-
-	/* Program the external memory controller before we come out of
-	 * self-refresh.  This only works with our SDRAM controller.
-	 */
-#ifdef EBIU_SDGCTL
-# ifdef CONFIG_EBIU_SDRRC_VAL
-	bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
-# endif
-# ifdef CONFIG_EBIU_SDBCTL_VAL
-	bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
-# endif
-# ifdef CONFIG_EBIU_SDGCTL_VAL
-	bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
-# endif
-#endif
-
-	serial_putc('c');
-
-	/* Now that we've reprogrammed, take things out of self refresh. */
-	if (put_into_srfs)
-#if defined(EBIU_RSTCTL)
-		bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
-#elif defined(EBIU_SDGCTL)
-		bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
-#endif
-
-	serial_putc('d');
-
-	/* Our DDR controller sucks and cannot be programmed while in
-	 * self-refresh.  So we have to pull it out before programming.
-	 */
-#ifdef EBIU_RSTCTL
-# ifdef CONFIG_EBIU_RSTCTL_VAL
-	bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRCTL0_VAL
-	bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRCTL1_VAL
-	bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRCTL2_VAL
-	bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRCTL3_VAL
-	/* default is disable, so don't need to force this */
-	bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRQUE_VAL
-	bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
-# endif
-#endif
-
-#endif /* __ADSPBF60x__ */
-	serial_putc('e');
-}
-
-__attribute__((always_inline)) static inline void
-check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
-{
-	serial_putc('a');
-
-	if (!CONFIG_MEM_SIZE)
-		return;
-
-	serial_putc('b');
-#ifdef __ADSPBF60x__
-	if (bfin_read32(DPM0_RESTORE0) != 0) {
-		uint32_t reg = bfin_read_DMC0_CTL();
-		reg &= ~0x8;
-		bfin_write_DMC0_CTL(reg);
-
-		while ((bfin_read_DMC0_STAT() & 0x8))
-			continue;
-		while (!(bfin_read_DMC0_STAT() & 0x1))
-			continue;
-
-		serial_putc('z');
-		uint32_t *hibernate_magic =
-			(uint32_t *)bfin_read32(DPM0_RESTORE4);
-		SSYNC(); /* make sure memory controller is done */
-		if (hibernate_magic[0] == 0xDEADBEEF) {
-			serial_putc('c');
-			SSYNC();
-			bfin_write_EVT15(hibernate_magic[1]);
-			bfin_write_IMASK(EVT_IVG15);
-			__asm__ __volatile__ (
-				/* load reti early to avoid anomaly 281 */
-				"reti = %2;"
-				/* clear hibernate magic */
-				"[%0] = %1;"
-				/* load stack pointer */
-				"SP = [%0 + 8];"
-				/* lower ourselves from reset ivg to ivg15 */
-				"raise 15;"
-				"nop;nop;nop;"
-				"rti;"
-				:
-				: "p"(hibernate_magic),
-				"d"(0x2000 /* jump.s 0 */),
-				"d"(0xffa00000)
-			);
-		}
-
-
-	}
-#else
-	/* Are we coming out of hibernate (suspend to memory) ?
-	 * The memory layout is:
-	 * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
-	 * 0x4: return address
-	 * 0x8: stack pointer
-	 *
-	 * SCKELOW is unreliable on older parts (anomaly 307)
-	 */
-	if (ANOMALY_05000307 || vr_ctl & 0x8000) {
-		uint32_t *hibernate_magic = 0;
-
-		SSYNC();
-		/* cppcheck-suppress nullPointer */
-		if (hibernate_magic[0] == 0xDEADBEEF) {
-			serial_putc('c');
-			bfin_write_EVT15(hibernate_magic[1]);
-			bfin_write_IMASK(EVT_IVG15);
-			__asm__ __volatile__ (
-				/* load reti early to avoid anomaly 281 */
-				"reti = %0;"
-				/* clear hibernate magic */
-				"[%0] = %1;"
-				/* load stack pointer */
-				"SP = [%0 + 8];"
-				/* lower ourselves from reset ivg to ivg15 */
-				"raise 15;"
-				"rti;"
-				:
-				: "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
-			);
-		}
-		serial_putc('d');
-	}
-#endif
-
-	serial_putc('e');
-}
-
-BOOTROM_CALLED_FUNC_ATTR
-void initcode(ADI_BOOT_DATA *bs)
-{
-	ADI_BOOT_DATA bootstruct_scratch;
-
-	/* Setup NMI handler before anything else */
-	program_nmi_handler();
-
-	serial_init();
-
-	serial_putc('A');
-
-	/* If the bootstruct is NULL, then it's because we're loading
-	 * dynamically and not via LDR (bootrom).  So set the struct to
-	 * some scratch space.
-	 */
-	if (!bs)
-		bs = &bootstruct_scratch;
-
-	serial_putc('B');
-	bool put_into_srfs = maybe_self_refresh(bs);
-
-	serial_putc('C');
-	uint sdivB, divB, vcoB;
-	program_early_devices(bs, &sdivB, &divB, &vcoB);
-
-	serial_putc('D');
-	u16 vr_ctl = program_clocks(bs, put_into_srfs);
-
-	serial_putc('E');
-	update_serial_clocks(bs, sdivB, divB, vcoB);
-
-	serial_putc('F');
-	program_memory_controller(bs, put_into_srfs);
-
-	serial_putc('G');
-	check_hibernation(bs, vr_ctl, put_into_srfs);
-
-	serial_putc('H');
-	program_async_controller(bs);
-
-#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
-	serial_putc('I');
-	/* Tell the bootrom where our entry point is so that it knows
-	 * where to jump to when finishing processing the LDR.  This
-	 * allows us to avoid small jump blocks in the LDR, and also
-	 * works around anomaly 05000389 (init address in external
-	 * memory causes bootrom to trigger external addressing IVHW).
-	 */
-	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
-		bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
-#endif
-
-	serial_putc('>');
-	serial_putc('\n');
-
-	serial_deinit();
-}
diff --git a/arch/blackfin/cpu/initcode.h b/arch/blackfin/cpu/initcode.h
deleted file mode 100644
index ab7fa45..0000000
--- a/arch/blackfin/cpu/initcode.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Code for early processor initialization
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_INITCODE_H__
-#define __BFIN_INITCODE_H__
-
-#include <asm/mach-common/bits/bootrom.h>
-
-#ifndef BFIN_IN_INITCODE
-# define serial_putc(c)
-#endif
-
-#ifndef __ADSPBF60x__
-
-#ifndef CONFIG_EBIU_RSTCTL_VAL
-# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
-#endif
-#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
-# error invalid EBIU_RSTCTL value: must not set reserved bits
-#endif
-
-#ifndef CONFIG_EBIU_MBSCTL_VAL
-# define CONFIG_EBIU_MBSCTL_VAL 0
-#endif
-
-#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
-# error invalid EBIU_DDRQUE value: must not set reserved bits
-#endif
-
-#endif /* __ADSPBF60x__ */
-
-__attribute__((always_inline)) static inline void
-program_async_controller(ADI_BOOT_DATA *bs)
-{
-#ifdef BFIN_IN_INITCODE
-	/*
-	 * We really only need to setup the async banks early if we're
-	 * booting out of it.  Otherwise, do it later on in cpu_init.
-	 */
-	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS &&
-	    CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_PARA)
-		return;
-#endif
-
-	serial_putc('a');
-
-#ifndef __ADSPBF60x__
-	/* Program the async banks controller. */
-#ifdef EBIU_AMGCTL
-	bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
-	bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
-	bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
-#endif
-
-	serial_putc('b');
-
-	/* Not all parts have these additional MMRs. */
-#ifdef EBIU_MBSCTL
-	bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
-#endif
-#ifdef EBIU_MODE
-# ifdef CONFIG_EBIU_MODE_VAL
-	bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
-# endif
-# ifdef CONFIG_EBIU_FCTL_VAL
-	bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
-# endif
-#endif
-
-	serial_putc('c');
-
-#else 	/* __ADSPBF60x__ */
-	/* Program the static memory controller. */
-# ifdef CONFIG_SMC_GCTL_VAL
-	bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B0CTL_VAL
-	bfin_write_SMC_B0CTL(CONFIG_SMC_B0CTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B0TIM_VAL
-	bfin_write_SMC_B0TIM(CONFIG_SMC_B0TIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B0ETIM_VAL
-	bfin_write_SMC_B0ETIM(CONFIG_SMC_B0ETIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B1CTL_VAL
-	bfin_write_SMC_B1CTL(CONFIG_SMC_B1CTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B1TIM_VAL
-	bfin_write_SMC_B1TIM(CONFIG_SMC_B1TIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B1ETIM_VAL
-	bfin_write_SMC_B1ETIM(CONFIG_SMC_B1ETIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B2CTL_VAL
-	bfin_write_SMC_B2CTL(CONFIG_SMC_B2CTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B2TIM_VAL
-	bfin_write_SMC_B2TIM(CONFIG_SMC_B2TIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B2ETIM_VAL
-	bfin_write_SMC_B2ETIM(CONFIG_SMC_B2ETIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B3CTL_VAL
-	bfin_write_SMC_B3CTL(CONFIG_SMC_B3CTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B3TIM_VAL
-	bfin_write_SMC_B3TIM(CONFIG_SMC_B3TIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B3ETIM_VAL
-	bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL);
-# endif
-
-#endif /* __ADSPBF60x__ */
-	serial_putc('d');
-}
-
-#endif
diff --git a/arch/blackfin/cpu/interrupt.S b/arch/blackfin/cpu/interrupt.S
deleted file mode 100644
index 0e5e59e..0000000
--- a/arch/blackfin/cpu/interrupt.S
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * interrupt.S - trampoline default exceptions/interrupts to C handlers
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/entry.h>
-#include <asm/ptrace.h>
-#include <asm/deferred.h>
-#include <asm/mach-common/bits/core.h>
-
-.text
-
-/* default entry point for exceptions */
-ENTRY(_trap)
-	CONFIG_BFIN_SCRATCH_REG = sp;
-	sp.l = LO(L1_SRAM_SCRATCH_END - 20);
-	sp.h = HI(L1_SRAM_SCRATCH_END - 20);
-	SAVE_ALL_SYS
-
-	r0 = sp;	/* stack frame pt_regs pointer argument ==> r0 */
-	r1 = 3;		/* EVT3 space */
-	sp += -12;
-	call _trap_c;
-	sp += 12;
-
-#ifdef CONFIG_EXCEPTION_DEFER
-	CC = R0 == 0;
-	IF CC JUMP .Lexit_trap;
-
-	/* To avoid double faults, lower our priority to IRQ5 */
-	p4.l = lo(COREMMR_BASE);
-	p4.h = hi(COREMMR_BASE);
-
-	r7.h = _exception_to_level5;
-	r7.l = _exception_to_level5;
-	[p4 + (EVT5 - COREMMR_BASE)] = r7;
-
-	/*
-	 * Save these registers, as they are only valid in exception context
-	 *  (where we are now - as soon as we defer to IRQ5, they can change)
-	 */
-	p5.l = _deferred_regs;
-	p5.h = _deferred_regs;
-	r6 = [p4 + (DCPLB_FAULT_ADDR - COREMMR_BASE)];
-	[p5 + (deferred_regs_DCPLB_FAULT_ADDR * 4)] = r6;
-
-	r6 = [p4 + (ICPLB_FAULT_ADDR - COREMMR_BASE)];
-	[p5 + (deferred_regs_ICPLB_FAULT_ADDR * 4)] = r6;
-
-	/* Save the state of single stepping */
-	r6 = SYSCFG;
-	[p5 + (deferred_regs_SYSCFG * 4)] = r6;
-	/* Clear it while we handle the exception in IRQ5 mode
-	 * RESTORE_ALL_SYS will load it, so all we need to do is store it
-	 * in the right place
-	 */
-	BITCLR(r6, SYSCFG_SSSTEP_P);
-	[SP + PT_SYSCFG] = r6;
-
-	/* Since we are going to clobber RETX, we need to save it */
-	r6 = retx;
-	[p5 + (deferred_regs_retx * 4)] = r6;
-
-	/* Save the current IMASK, since we change in order to jump to level 5 */
-	cli r6;
-	[p5 + (deferred_regs_IMASK * 4)] = r6;
-
-	/* Disable all interrupts, but make sure level 5 is enabled so
-	 * we can switch to that level.
-	 */
-	r6 = 0x3f;
-	sti r6;
-
-	/* Clobber RETX so we don't end up back at a faulting instruction */
-	[sp + PT_RETX] = r7;
-
-	/* In case interrupts are disabled IPEND[4] (global interrupt disable bit)
-	 * clear it (re-enabling interrupts again) by the special sequence of pushing
-	 * RETI onto the stack.  This way we can lower ourselves to IVG5 even if the
-	 * exception was taken after the interrupt handler was called but before it
-	 * got a chance to enable global interrupts itself.
-	 */
-	[--sp] = reti;
-	sp += 4;
-
-	RAISE 5;
-.Lexit_trap:
-#endif
-
-#if ANOMALY_05000257
-	R7  = LC0;
-	LC0 = R7;
-	R7  = LC1;
-	LC1 = R7;
-#endif
-
-	RESTORE_ALL_SYS
-	sp = CONFIG_BFIN_SCRATCH_REG;
-	rtx;
-ENDPROC(_trap)
-
-#ifdef CONFIG_EXCEPTION_DEFER
-/* Deferred (IRQ5) exceptions */
-ENTRY(_exception_to_level5)
-	SAVE_ALL_SYS
-
-	/* Now we have to fix things up */
-	p4.l = lo(EVT5);
-	p4.h = hi(EVT5);
-	r0.l = _evt_default;
-	r0.h = _evt_default;
-	[p4] = r0;
-	csync;
-
-	p4.l = _deferred_regs;
-	p4.h = _deferred_regs;
-	r0 = [p4 + (deferred_regs_retx * 4)];
-	[sp + PT_PC] = r0;
-
-	r0 = [p4 + (deferred_regs_SYSCFG * 4)];
-	[sp + PT_SYSCFG] = r0;
-
-	r0 = sp;	/* stack frame pt_regs pointer argument ==> r0 */
-	r1 = 5;	/* EVT5 space */
-	sp += -12;
-	call _trap_c;
-	sp += 12;
-
-	/* Restore IMASK */
-	r0 = [p4 + (deferred_regs_IMASK * 4)];
-	sti r0;
-
-	RESTORE_ALL_SYS
-
-	rti;
-ENDPROC(_exception_to_level5)
-#endif
-
-/* default entry point for interrupts */
-ENTRY(_evt_default)
-	SAVE_ALL_SYS
-	r0 = sp;	/* stack frame pt_regs pointer argument ==> r0 */
-	sp += -12;
-	call _bfin_panic;
-	sp += 12;
-	RESTORE_ALL_SYS
-	rti;
-ENDPROC(_evt_default)
-
-/* NMI handler */
-ENTRY(_evt_nmi)
-	rtn;
-ENDPROC(_evt_nmi)
diff --git a/arch/blackfin/cpu/interrupts.c b/arch/blackfin/cpu/interrupts.c
deleted file mode 100644
index abb7dc1..0000000
--- a/arch/blackfin/cpu/interrupts.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * U-Boot - interrupts.c Interrupt related routines
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * This file is based on interrupts.c
- * Copyright 1996 Roman Zippel
- * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * Copyright 2003 Metrowerks/Motorola
- * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
- *			BuyWays B.V. (www.buyways.nl)
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <watchdog.h>
-#include <asm/blackfin.h>
-#include "cpu.h"
-
-static ulong timestamp;
-static ulong last_time;
-static int int_flag;
-
-int irq_flags;			/* needed by asm-blackfin/system.h */
-
-/* Functions just to satisfy the linker */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On Blackfin it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On Blackfin it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
-
-void enable_interrupts(void)
-{
-	local_irq_restore(int_flag);
-}
-
-int disable_interrupts(void)
-{
-	local_irq_save(int_flag);
-	return 1;
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned long delay, start, stop;
-	unsigned long cclk;
-	cclk = (CONFIG_CCLK_HZ);
-
-	while (usec > 1) {
-		WATCHDOG_RESET();
-
-		/*
-		 * how many clock ticks to delay?
-		 *  - request(in useconds) * clock_ticks(Hz) / useconds/second
-		 */
-		if (usec < 1000) {
-			delay = (usec * (cclk / 244)) >> 12;
-			usec = 0;
-		} else {
-			delay = (1000 * (cclk / 244)) >> 12;
-			usec -= 1000;
-		}
-
-		asm volatile (" %0 = CYCLES;" : "=r" (start));
-		do {
-			asm volatile (" %0 = CYCLES; " : "=r" (stop));
-		} while (stop - start < delay);
-	}
-
-	return;
-}
-
-#define MAX_TIM_LOAD	0xFFFFFFFF
-int timer_init(void)
-{
-	bfin_write_TCNTL(0x1);
-	CSYNC();
-	bfin_write_TSCALE(0x0);
-	bfin_write_TCOUNT(MAX_TIM_LOAD);
-	bfin_write_TPERIOD(MAX_TIM_LOAD);
-	bfin_write_TCNTL(0x7);
-	CSYNC();
-
-	timestamp = 0;
-	last_time = 0;
-
-	return 0;
-}
-
-/*
- * Any network command or flash
- * command is started get_timer shall
- * be called before TCOUNT gets reset,
- * to implement the accurate timeouts.
- *
- * How ever milliconds doesn't return
- * the number that has been elapsed from
- * the last reset.
- *
- * As get_timer is used in the u-boot
- * only for timeouts this should be
- * sufficient
- */
-ulong get_timer(ulong base)
-{
-	ulong milisec;
-
-	/* Number of clocks elapsed */
-	ulong clocks = (MAX_TIM_LOAD - bfin_read_TCOUNT());
-
-	/*
-	 * Find if the TCOUNT is reset
-	 * timestamp gives the number of times
-	 * TCOUNT got reset
-	 */
-	if (clocks < last_time)
-		timestamp++;
-	last_time = clocks;
-
-	/* Get the number of milliseconds */
-	milisec = clocks / (CONFIG_CCLK_HZ / 1000);
-
-	/*
-	 * Find the number of millisonds that
-	 * got elapsed before this TCOUNT cycle
-	 */
-	milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
-
-	return (milisec - base);
-}
diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c
deleted file mode 100644
index 29e7a44..0000000
--- a/arch/blackfin/cpu/jtag-console.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * jtag-console.c - console driver over Blackfin JTAG
- *
- * Copyright (c) 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <asm/blackfin.h>
-
-#ifdef DEBUG
-# define dprintf(...) serial_printf(__VA_ARGS__)
-#else
-# define dprintf(...) do { if (0) printf(__VA_ARGS__); } while (0)
-#endif
-
-static inline void dprintf_decode(const char *s, uint32_t len)
-{
-	uint32_t i;
-	for (i = 0; i < len; ++i)
-		if (s[i] < 0x20 || s[i] >= 0x7f)
-			dprintf("\\%o", s[i]);
-		else
-			dprintf("%c", s[i]);
-}
-
-static inline uint32_t bfin_write_emudat(uint32_t emudat)
-{
-	__asm__ __volatile__("emudat = %0;" : : "d"(emudat));
-	return emudat;
-}
-
-static inline uint32_t bfin_read_emudat(void)
-{
-	uint32_t emudat;
-	__asm__ __volatile__("%0 = emudat;" : "=d"(emudat));
-	return emudat;
-}
-
-#ifndef CONFIG_JTAG_CONSOLE_TIMEOUT
-# define CONFIG_JTAG_CONSOLE_TIMEOUT 500
-#endif
-
-/* The Blackfin tends to be much much faster than the JTAG hardware. */
-static bool jtag_write_emudat(uint32_t emudat)
-{
-	static bool overflowed = false;
-	ulong timeout = get_timer(0);
-	while (bfin_read_DBGSTAT() & 0x1) {
-		if (overflowed)
-			return overflowed;
-		if (get_timer(timeout) > CONFIG_JTAG_CONSOLE_TIMEOUT)
-			overflowed = true;
-	}
-	overflowed = false;
-	bfin_write_emudat(emudat);
-	return overflowed;
-}
-/* Transmit a buffer.  The format is:
- * [32bit length][actual data]
- */
-static void jtag_send(const char *raw_str, uint32_t len)
-{
-	const char *cooked_str;
-	uint32_t i, ex;
-
-	if (len == 0)
-		return;
-
-	/* Ugh, need to output \r after \n */
-	ex = 0;
-	for (i = 0; i < len; ++i)
-		if (raw_str[i] == '\n')
-			++ex;
-	if (ex) {
-		char *c = malloc(len + ex);
-		cooked_str = c;
-		for (i = 0; i < len; ++i) {
-			*c++ = raw_str[i];
-			if (raw_str[i] == '\n')
-				*c++ = '\r';
-		}
-		len += ex;
-	} else
-		cooked_str = raw_str;
-
-	dprintf("%s(\"", __func__);
-	dprintf_decode(cooked_str, len);
-	dprintf("\", %i)\n", len);
-
-	/* First send the length */
-	if (jtag_write_emudat(len))
-		goto done;
-
-	/* Then send the data */
-	for (i = 0; i < len; i += 4) {
-		uint32_t emudat =
-			(cooked_str[i + 0] <<  0) |
-			(cooked_str[i + 1] <<  8) |
-			(cooked_str[i + 2] << 16) |
-			(cooked_str[i + 3] << 24);
-		if (jtag_write_emudat(emudat)) {
-			bfin_write_emudat(0);
-			goto done;
-		}
-	}
-
- done:
-	if (cooked_str != raw_str)
-		free((char *)cooked_str);
-}
-static void jtag_putc(struct stdio_dev *dev, const char c)
-{
-	jtag_send(&c, 1);
-}
-static void jtag_puts(struct stdio_dev *dev, const char *s)
-{
-	jtag_send(s, strlen(s));
-}
-
-static size_t inbound_len, leftovers_len;
-
-/* Lower layers want to know when jtag has data */
-static int jtag_tstc_dbg(void)
-{
-	int ret = (bfin_read_DBGSTAT() & 0x2);
-	if (ret)
-		dprintf("%s: ret:%i\n", __func__, ret);
-	return ret;
-}
-
-/* Higher layers want to know when any data is available */
-static int jtag_tstc(struct stdio_dev *dev)
-{
-	return jtag_tstc_dbg() || leftovers_len;
-}
-
-/* Receive a buffer.  The format is:
- * [32bit length][actual data]
- */
-static uint32_t leftovers;
-static int jtag_getc(struct stdio_dev *dev)
-{
-	int ret;
-	uint32_t emudat;
-
-	dprintf("%s: inlen:%zu leftlen:%zu left:%x\n", __func__,
-		inbound_len, leftovers_len, leftovers);
-
-	/* see if any data is left over */
-	if (leftovers_len) {
-		--leftovers_len;
-		ret = leftovers & 0xff;
-		leftovers >>= 8;
-		return ret;
-	}
-
-	/* wait for new data ! */
-	while (!jtag_tstc_dbg())
-		continue;
-	emudat = bfin_read_emudat();
-
-	if (inbound_len == 0) {
-		/* grab the length */
-		inbound_len = emudat;
-	} else {
-		/* store the bytes */
-		leftovers_len = min((size_t)4, inbound_len);
-		inbound_len -= leftovers_len;
-		leftovers = emudat;
-	}
-
-	return jtag_getc(dev);
-}
-
-int drv_jtag_console_init(void)
-{
-	struct stdio_dev dev;
-	int ret;
-
-	memset(&dev, 0x00, sizeof(dev));
-	strcpy(dev.name, "jtag");
-	dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
-	dev.putc = jtag_putc;
-	dev.puts = jtag_puts;
-	dev.tstc = jtag_tstc;
-	dev.getc = jtag_getc;
-
-	ret = stdio_register(&dev);
-	return (ret == 0 ? 1 : ret);
-}
-
-#ifdef CONFIG_UART_CONSOLE_IS_JTAG
-#include <serial.h>
-/* Since the JTAG is always available (at power on), allow it to fake a UART */
-void jtag_serial_setbrg(void)
-{
-}
-
-int jtag_serial_init(void)
-{
-	return 0;
-}
-
-static struct serial_device serial_jtag_drv = {
-	.name	= "jtag",
-	.start	= jtag_serial_init,
-	.stop	= NULL,
-	.setbrg	= jtag_serial_setbrg,
-	.putc	= jtag_putc,
-	.puts	= jtag_puts,
-	.tstc	= jtag_tstc,
-	.getc	= jtag_getc,
-};
-
-void bfin_jtag_initialize(void)
-{
-	serial_register(&serial_jtag_drv);
-}
-
-struct serial_device *default_serial_console(void)
-{
-	return &serial_jtag_drv;
-}
-#endif
diff --git a/arch/blackfin/cpu/os_log.c b/arch/blackfin/cpu/os_log.c
deleted file mode 100644
index 2092d9e..0000000
--- a/arch/blackfin/cpu/os_log.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * functions for handling OS log buffer
- *
- * Copyright (c) 2009 Analog Devices Inc.
- *
- * Licensed under the 2-clause BSD.
- */
-
-#include <common.h>
-
-#define OS_LOG_MAGIC       0xDEADBEEF
-#define OS_LOG_MAGIC_ADDR  ((unsigned long *)0x4f0)
-#define OS_LOG_PTR_ADDR    ((char **)0x4f4)
-
-int bfin_os_log_check(void)
-{
-	if (*OS_LOG_MAGIC_ADDR != OS_LOG_MAGIC)
-		return 0;
-	*OS_LOG_MAGIC_ADDR = 0;
-	return 1;
-}
-
-void bfin_os_log_dump(void)
-{
-	char *log = *OS_LOG_PTR_ADDR;
-	while (*log) {
-		puts(log);
-		log += strlen(log) + 1;
-	}
-}
diff --git a/arch/blackfin/cpu/reset.c b/arch/blackfin/cpu/reset.c
deleted file mode 100644
index b6718d3..0000000
--- a/arch/blackfin/cpu/reset.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * reset.c - logic for resetting the cpu
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include "cpu.h"
-
-/* A system soft reset makes external memory unusable so force
- * this function into L1.  We use the compiler ssync here rather
- * than SSYNC() because it's safe (no interrupts and such) and
- * we save some L1.  We do not need to force sanity in the SYSCR
- * register as the BMODE selection bit is cleared by the soft
- * reset while the Core B bit (on dual core parts) is cleared by
- * the core reset.
- */
-__attribute__ ((__l1_text__, __noreturn__))
-static void bfin_reset(void)
-{
-#ifdef SWRST
-	/* Wait for completion of "system" events such as cache line
-	 * line fills so that we avoid infinite stalls later on as
-	 * much as possible.  This code is in L1, so it won't trigger
-	 * any such event after this point in time.
-	 */
-	__builtin_bfin_ssync();
-
-	/* Initiate System software reset. */
-	bfin_write_SWRST(0x7);
-
-	/* Due to the way reset is handled in the hardware, we need
-	 * to delay for 10 SCLKS.  The only reliable way to do this is
-	 * to calculate the CCLK/SCLK ratio and multiply 10.  For now,
-	 * we'll assume worse case which is a 1:15 ratio.
-	 */
-	asm(
-		"LSETUP (1f, 1f) LC0 = %0\n"
-		"1: nop;"
-		:
-		: "a" (15 * 10)
-		: "LC0", "LB0", "LT0"
-	);
-
-	/* Clear System software reset */
-	bfin_write_SWRST(0);
-
-	/* The BF526 ROM will crash during reset */
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-	/* Seems to be fixed with newer parts though ... */
-	if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
-		bfin_read_SWRST();
-#endif
-
-	/* Wait for the SWRST write to complete.  Cannot rely on SSYNC
-	 * though as the System state is all reset now.
-	 */
-	asm(
-		"LSETUP (1f, 1f) LC1 = %0\n"
-		"1: nop;"
-		:
-		: "a" (15 * 1)
-		: "LC1", "LB1", "LT1"
-	);
-#endif
-
-	while (1)
-#if defined(__ADSPBF60x__)
-		bfin_write_RCU0_CTL(0x1);
-#else
-		/* Issue core reset */
-		asm("raise 1");
-#endif
-}
-
-/* We need to trampoline ourselves up into L1 since our linker
- * does not have relaxtion support and will only generate a
- * PC relative call with a 25 bit immediate.  This is not enough
- * to get us from the top of SDRAM into L1.
- */
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (board_reset)
-		board_reset();
-	if (ANOMALY_05000353 || ANOMALY_05000386)
-		while (1)
-			asm("jump (%0);" : : "a" (bfin_reset));
-	else
-		bfrom_SoftReset((void *)(L1_SRAM_SCRATCH_END - 20));
-	return 0;
-}
diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S
deleted file mode 100644
index 823a1df..0000000
--- a/arch/blackfin/cpu/start.S
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * U-Boot - start.S Startup file for Blackfin U-Boot
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * This file is based on head.S
- * Copyright (c) 2003  Metrowerks/Motorola
- * Copyright (C) 1998  D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- *                     Kenneth Albanowski <kjahds@kjahds.com>,
- *                     The Silver Hammer Group, Ltd.
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/watchdog.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/serial.h>
-
-/* It may seem odd that we make calls to functions even though we haven't
- * relocated ourselves yet out of {flash,ram,wherever}.  This is OK because
- * the "call" instruction in the Blackfin architecture is actually PC
- * relative.  So we can call functions all we want and not worry about them
- * not being relocated yet.
- */
-
-.text
-ENTRY(_start)
-
-	/* Set our initial stack to L1 scratch space */
-	sp.l = LO(L1_SRAM_SCRATCH_END - 20);
-	sp.h = HI(L1_SRAM_SCRATCH_END - 20);
-
-	/* Optimization register tricks: keep a base value in the
-	 * reserved P registers so we use the load/store with an
-	 * offset syntax.  R0 = [P5 + <constant>];
-	 *   P4 - system MMR base
-	 *   P5 - core MMR base
-	 */
-#ifdef CONFIG_HW_WATCHDOG
-	p4.l = 0;
-	p4.h = HI(SYSMMR_BASE);
-#endif
-	p5.l = 0;
-	p5.h = HI(COREMMR_BASE);
-
-#ifdef CONFIG_HW_WATCHDOG
-	/* Program the watchdog with default timeout of ~5 seconds.
-	 * That should be long enough to bootstrap ourselves up and
-	 * then the common U-Boot code can take over.
-	 */
-	r1 = WDDIS;
-# ifdef __ADSPBF60x__
-	[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
-# else
-	W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
-# endif
-	SSYNC;
-	r0 = 0;
-	r0.h = HI(MSEC_TO_SCLK(CONFIG_WATCHDOG_TIMEOUT_MSECS));
-	[p4 + (WDOG_CNT - SYSMMR_BASE)] = r0;
-	SSYNC;
-	r1 = WDEN;
-	/* fire up the watchdog - R0.L above needs to be 0x0000 */
-# ifdef __ADSPBF60x__
-	[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
-# else
-	W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
-# endif
-	SSYNC;
-#endif
-
-	/* Turn on the serial for debugging the init process */
-	serial_early_init
-	serial_early_set_baud
-
-	serial_early_puts("Init Registers");
-
-	/* Disable self-nested interrupts and enable CYCLES for udelay() */
-	R0 = CCEN | 0x30;
-	SYSCFG = R0;
-
-	/* Zero out registers required by Blackfin ABI.
-	 * http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
-	 */
-	r1 = 0 (x);
-	/* Disable circular buffers */
-	l0 = r1;
-	l1 = r1;
-	l2 = r1;
-	l3 = r1;
-	/* Disable hardware loops in case we were started by 'go' */
-	lc0 = r1;
-	lc1 = r1;
-
-	/* Save RETX so we can pass it while booting Linux */
-	r7 = RETX;
-
-#if CONFIG_MEM_SIZE
-	/* Figure out where we are currently executing so that we can decide
-	 * how to best reprogram and relocate things.  We'll pass below:
-	 *  R4: load address of _start
-	 *  R5: current (not load) address of _start
-	 */
-	serial_early_puts("Find ourselves");
-
-	call _get_pc;
-.Loffset:
-	r1.l = .Loffset;
-	r1.h = .Loffset;
-	r4.l = _start;
-	r4.h = _start;
-	r3 = r1 - r4;
-	r5 = r0 - r3;
-
-	/* Inform upper layers if we had to do the relocation ourselves.
-	 * This allows us to detect whether we were loaded by 'go 0x1000'
-	 * or by the bootrom from an LDR.  "R6" is "loaded_from_ldr".
-	 */
-	r6 = 1 (x);
-	cc = r4 == r5;
-	if cc jump .Lnorelocate;
-	r6 = 0 (x);
-
-	/* Turn off caches as they require CPLBs and a CPLB miss requires
-	 * a software exception handler to process it.  But we're about to
-	 * clobber any previous executing software (like U-Boot that just
-	 * launched a new U-Boot via 'go'), so any handler state will be
-	 * unreliable after the memcpy below.
-	 */
-	serial_early_puts("Kill Caches");
-	r0 = 0;
-	[p5 + (IMEM_CONTROL - COREMMR_BASE)] = r0;
-	[p5 + (DMEM_CONTROL - COREMMR_BASE)] = r0;
-	ssync;
-
-	/* In bypass mode, we don't have an LDR with an init block
-	 * so we need to explicitly call it ourselves.  This will
-	 * reprogram our clocks, memory, and setup our async banks.
-	 */
-	serial_early_puts("Program Clocks");
-
-	/* if we're executing >=0x20000000, then we dont need to dma */
-	r3 = 0x0;
-	r3.h = 0x2000;
-	cc = r5 < r3 (iu);
-	if cc jump .Ldma_and_reprogram;
-#else
-	r6 = 1 (x);	/* fake loaded_from_ldr = 1 */
-#endif
-	r0 = 0 (x);	/* set bootstruct to NULL */
-	call _initcode;
-	jump .Lprogrammed;
-
-	/* we're sitting in external memory, so dma into L1 and reprogram */
-.Ldma_and_reprogram:
-	r0.l = LO(L1_INST_SRAM);
-	r0.h = HI(L1_INST_SRAM);
-	r1.l = __initcode_lma;
-	r1.h = __initcode_lma;
-	r2.l = __initcode_len;
-	r2.h = __initcode_len;
-	r1 = r1 - r4;	/* convert r1 from load address of initcode ... */
-	r1 = r1 + r5;	/* ... to current (not load) address of initcode */
-	p3 = r0;
-	call _dma_memcpy_nocache;
-	r0 = 0 (x);	/* set bootstruct to NULL */
-	call (p3);
-
-	/* Since we reprogrammed SCLK, we need to update the serial divisor */
-.Lprogrammed:
-	serial_early_set_baud
-
-#if CONFIG_MEM_SIZE
-	/* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded
-	 * monitor location in the end of RAM.  We know that memcpy() only
-	 * uses registers, so it is safe to call here.  Note that this only
-	 * copies to external memory ... we do not start executing out of
-	 * it yet (see "lower to 15" below).
-	 */
-	serial_early_puts("Relocate");
-	r0 = r4;
-	r1 = r5;
-	r2.l = LO(CONFIG_SYS_MONITOR_LEN);
-	r2.h = HI(CONFIG_SYS_MONITOR_LEN);
-	call _memcpy_ASM;
-#endif
-
-.Lnorelocate:
-	/* Initialize BSS section ... we know that memset() does not
-	 * use the BSS, so it is safe to call here.  The bootrom LDR
-	 * takes care of clearing things for us.
-	 */
-	serial_early_puts("Zero BSS");
-	r0.l = __bss_start;
-	r0.h = __bss_start;
-	r1 = 0 (x);
-	r2.l = __bss_len;
-	r2.h = __bss_len;
-	call _memset;
-
-
-	/* Setup the actual stack in external memory */
-	sp.h = HI(CONFIG_STACKBASE);
-	sp.l = LO(CONFIG_STACKBASE);
-	fp = sp;
-
-	/* Now lower ourselves from the highest interrupt level to
-	 * the lowest.  We do this by masking all interrupts but 15,
-	 * setting the 15 handler to ".Lenable_nested", raising the 15
-	 * interrupt, and then returning from the highest interrupt
-	 * level to the dummy "jump" until the interrupt controller
-	 * services the pending 15 interrupt.  If executing out of
-	 * flash, these steps also changes the code flow from flash
-	 * to external memory.
-	 */
-	serial_early_puts("Lower to 15");
-	r0 = r7;
-	r1 = r6;
-	p1.l = .Lenable_nested;
-	p1.h = .Lenable_nested;
-	[p5 + (EVT15 - COREMMR_BASE)] = p1;
-	r7 = EVT_IVG15 (z);
-	sti r7;
-	raise 15;
-	p3.l = .LWAIT_HERE;
-	p3.h = .LWAIT_HERE;
-	reti = p3;
-	rti;
-
-	/* Enable nested interrupts before continuing with cpu init */
-.Lenable_nested:
-	cli r7;
-	[--sp] = reti;
-	jump.l _cpu_init_f;
-
-.LWAIT_HERE:
-	jump .LWAIT_HERE;
-ENDPROC(_start)
-
-LENTRY(_get_pc)
-	r0 = rets;
-#if ANOMALY_05000371
-	NOP;
-	NOP;
-	NOP;
-#endif
-	rts;
-ENDPROC(_get_pc)
-
-ENTRY(_relocate_code)
-	/* Fake relocate code. Setup the new stack only */
-	sp = r0;
-	fp = sp;
-	r0 = p3;
-	r1.h = 0x2000;
-	r1.l = 0x10;
-	jump.l _board_init_r
-ENDPROC(_relocate_code)
diff --git a/arch/blackfin/cpu/traps.c b/arch/blackfin/cpu/traps.c
deleted file mode 100644
index 21760d0..0000000
--- a/arch/blackfin/cpu/traps.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/*
- * U-Boot - traps.c Routines related to interrupts and exceptions
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * This file is based on
- * No original Copyright holder listed,
- * Probabily original (C) Roman Zippel (assigned DJD, 1999)
- *
- * Copyright 2003 Metrowerks - for Blackfin
- * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
- * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <kgdb.h>
-#include <linux/types.h>
-#include <asm/traps.h>
-#include <asm/cplb.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/mpu.h>
-#include <asm/mach-common/bits/trace.h>
-#include <asm/deferred.h>
-#include "cpu.h"
-
-#ifdef CONFIG_DEBUG_DUMP
-# define ENABLE_DUMP 1
-#else
-# define ENABLE_DUMP 0
-#endif
-
-#define trace_buffer_save(x) \
-	do { \
-		if (!ENABLE_DUMP) \
-			break; \
-		(x) = bfin_read_TBUFCTL(); \
-		bfin_write_TBUFCTL((x) & ~TBUFEN); \
-	} while (0)
-
-#define trace_buffer_restore(x) \
-	do { \
-		if (!ENABLE_DUMP) \
-			break; \
-		bfin_write_TBUFCTL((x)); \
-	} while (0);
-
-/* The purpose of this map is to provide a mapping of address<->cplb settings
- * rather than an exact map of what is actually addressable on the part.  This
- * map covers all current Blackfin parts.  If you try to access an address that
- * is in this map but not actually on the part, you won't get an exception and
- * reboot, you'll get an external hardware addressing error and reboot.  Since
- * only the ends matter (you did something wrong and the board reset), the means
- * are largely irrelevant.
- */
-struct memory_map {
-	uint32_t start, end;
-	uint32_t data_flags, inst_flags;
-};
-const struct memory_map const bfin_memory_map[] = {
-	{	/* external memory */
-		.start = 0x00000000,
-		.end   = 0x20000000,
-		.data_flags = SDRAM_DGENERIC,
-		.inst_flags = SDRAM_IGENERIC,
-	},
-	{	/* async banks */
-		.start = 0x20000000,
-		.end   = 0x30000000,
-		.data_flags = SDRAM_EBIU,
-		.inst_flags = SDRAM_INON_CHBL,
-	},
-	{	/* everything on chip */
-		.start = 0xE0000000,
-		.end   = 0xFFFFFFFF,
-		.data_flags = L1_DMEMORY,
-		.inst_flags = L1_IMEMORY,
-	}
-};
-
-#ifdef CONFIG_EXCEPTION_DEFER
-unsigned int deferred_regs[deferred_regs_last];
-#endif
-
-/*
- * Handle all exceptions while running in EVT3 or EVT5
- */
-int trap_c(struct pt_regs *regs, uint32_t level)
-{
-	uint32_t ret = 0;
-	uint32_t trapnr = (regs->seqstat & EXCAUSE);
-	unsigned long tflags;
-	bool data = false;
-
-	/*
-	 * Keep the trace buffer so that a miss here points people
-	 * to the right place (their code).  Crashes here rarely
-	 * happen.  If they do, only the Blackfin maintainer cares.
-	 */
-	trace_buffer_save(tflags);
-
-	switch (trapnr) {
-	/* 0x26 - Data CPLB Miss */
-	case VEC_CPLB_M:
-
-		if (ANOMALY_05000261) {
-			static uint32_t last_cplb_fault_retx;
-			/*
-			 * Work around an anomaly: if we see a new DCPLB fault,
-			 * return without doing anything. Then,
-			 * if we get the same fault again, handle it.
-			 */
-			if (last_cplb_fault_retx != regs->retx) {
-				last_cplb_fault_retx = regs->retx;
-				break;
-			}
-		}
-
-		data = true;
-		/* fall through */
-
-	/* 0x27 - Instruction CPLB Miss */
-	case VEC_CPLB_I_M: {
-		volatile uint32_t *CPLB_ADDR_BASE, *CPLB_DATA_BASE, *CPLB_ADDR, *CPLB_DATA;
-		uint32_t new_cplb_addr = 0, new_cplb_data = 0;
-		static size_t last_evicted;
-		size_t i;
-
-#ifdef CONFIG_EXCEPTION_DEFER
-		/* This should never happen */
-		if (level == 5)
-			bfin_panic(regs);
-#endif
-
-		new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1);
-
-		for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) {
-			/* if the exception is inside this range, lets use it */
-			if (new_cplb_addr >= bfin_memory_map[i].start &&
-			    new_cplb_addr < bfin_memory_map[i].end)
-				break;
-		}
-		if (i == ARRAY_SIZE(bfin_memory_map)) {
-			printf("%cCPLB exception outside of memory map at 0x%p\n",
-				(data ? 'D' : 'I'), (void *)new_cplb_addr);
-			bfin_panic(regs);
-		} else
-			debug("CPLB addr %p matches map 0x%p - 0x%p\n",
-				(void *)new_cplb_addr,
-				(void *)bfin_memory_map[i].start,
-				(void *)bfin_memory_map[i].end);
-		new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags);
-
-		if (data) {
-			CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0;
-			CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0;
-		} else {
-			CPLB_ADDR_BASE = (uint32_t *)ICPLB_ADDR0;
-			CPLB_DATA_BASE = (uint32_t *)ICPLB_DATA0;
-		}
-
-		/* find the next unlocked entry and evict it */
-		i = last_evicted & 0xF;
-		debug("last evicted = %zu\n", i);
-		CPLB_DATA = CPLB_DATA_BASE + i;
-		while (*CPLB_DATA & CPLB_LOCK) {
-			debug("skipping %zu %p - %08X\n", i, CPLB_DATA, *CPLB_DATA);
-			i = (i + 1) & 0xF;	/* wrap around */
-			CPLB_DATA = CPLB_DATA_BASE + i;
-		}
-		CPLB_ADDR = CPLB_ADDR_BASE + i;
-
-		debug("evicting entry %zu: 0x%p 0x%08X\n", i,
-			(void *)*CPLB_ADDR, *CPLB_DATA);
-		last_evicted = i + 1;
-
-		/* need to turn off cplbs whenever we muck with the cplb table */
-#if ENDCPLB != ENICPLB
-# error cplb enable bit violates my sanity
-#endif
-		uint32_t mem_control = (data ? DMEM_CONTROL : IMEM_CONTROL);
-		bfin_write32(mem_control, bfin_read32(mem_control) & ~ENDCPLB);
-		*CPLB_ADDR = new_cplb_addr;
-		*CPLB_DATA = new_cplb_data;
-		bfin_write32(mem_control, bfin_read32(mem_control) | ENDCPLB);
-		SSYNC();
-
-		/* dump current table for debugging purposes */
-		CPLB_ADDR = CPLB_ADDR_BASE;
-		CPLB_DATA = CPLB_DATA_BASE;
-		for (i = 0; i < 16; ++i)
-			debug("%2zu 0x%p 0x%08X\n", i,
-				(void *)*CPLB_ADDR++, *CPLB_DATA++);
-
-		break;
-	}
-#ifdef CONFIG_CMD_KGDB
-	/* Single step
-	 * if we are in IRQ5, just ignore, otherwise defer, and handle it in kgdb
-	 */
-	case VEC_STEP:
-		if (level == 3) {
-			/* If we just returned from an interrupt, the single step
-			 * event is for the RTI instruction.
-			 */
-			if (regs->retx == regs->pc)
-				break;
-			/* we just return if we are single stepping through IRQ5 */
-			if (regs->ipend & 0x20)
-				break;
-			/* Otherwise, turn single stepping off & fall through,
-			 * which defers to IRQ5
-			 */
-			regs->syscfg &= ~1;
-		}
-		/* fall through */
-#endif
-	default:
-#ifdef CONFIG_CMD_KGDB
-		if (level == 3) {
-			/* We need to handle this at EVT5, so try again */
-			bfin_dump(regs);
-			ret = 1;
-			break;
-		}
-		if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-			break;
-#endif
-		bfin_panic(regs);
-	}
-
-	trace_buffer_restore(tflags);
-
-	return ret;
-}
-
-#ifndef CONFIG_KALLSYMS
-const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
-{
-	*caddr = addr;
-	return "N/A";
-}
-#endif
-
-static void decode_address(char *buf, unsigned long address)
-{
-	unsigned long sym_addr;
-	void *paddr = (void *)address;
-	const char *sym = symbol_lookup(address, &sym_addr);
-
-	if (sym) {
-		sprintf(buf, "<0x%p> { %s + 0x%lx }", paddr, sym, address - sym_addr);
-		return;
-	}
-
-	if (!address)
-		sprintf(buf, "<0x%p> /* Maybe null pointer? */", paddr);
-	else if (address >= CONFIG_SYS_MONITOR_BASE &&
-		 address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-		sprintf(buf, "<0x%p> /* somewhere in u-boot */", paddr);
-	else
-		sprintf(buf, "<0x%p> /* unknown address */", paddr);
-}
-
-static char *strhwerrcause(uint16_t hwerrcause)
-{
-	switch (hwerrcause) {
-		case 0x02: return "system mmr error";
-		case 0x03: return "external memory addressing error";
-		case 0x12: return "performance monitor overflow";
-		case 0x18: return "raise 5 instruction";
-		default:   return "undef";
-	}
-}
-
-static char *strexcause(uint16_t excause)
-{
-	switch (excause) {
-		case 0x00 ... 0xf: return "custom exception";
-		case 0x10: return "single step";
-		case 0x11: return "trace buffer full";
-		case 0x21: return "undef inst";
-		case 0x22: return "illegal inst";
-		case 0x23: return "dcplb prot violation";
-		case 0x24: return "misaligned data";
-		case 0x25: return "unrecoverable event";
-		case 0x26: return "dcplb miss";
-		case 0x27: return "multiple dcplb hit";
-		case 0x28: return "emulation watchpoint";
-		case 0x2a: return "misaligned inst";
-		case 0x2b: return "icplb prot violation";
-		case 0x2c: return "icplb miss";
-		case 0x2d: return "multiple icplb hit";
-		case 0x2e: return "illegal use of supervisor resource";
-		default:   return "undef";
-	}
-}
-
-void dump(struct pt_regs *fp)
-{
-	char buf[150];
-	int i;
-	uint16_t hwerrcause, excause;
-
-	if (!ENABLE_DUMP)
-		return;
-
-#ifndef CONFIG_CMD_KGDB
-	/* fp->ipend is normally garbage, so load it ourself */
-	fp->ipend = bfin_read_IPEND();
-#endif
-
-	hwerrcause = (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P;
-	excause = (fp->seqstat & EXCAUSE) >> EXCAUSE_P;
-
-	printf("SEQUENCER STATUS:\n");
-	printf(" SEQSTAT: %08lx  IPEND: %04lx  SYSCFG: %04lx\n",
-		fp->seqstat, fp->ipend, fp->syscfg);
-	printf("  HWERRCAUSE: 0x%x: %s\n", hwerrcause, strhwerrcause(hwerrcause));
-	printf("  EXCAUSE   : 0x%x: %s\n", excause, strexcause(excause));
-	for (i = 6; i <= 15; ++i) {
-		if (fp->ipend & (1 << i)) {
-			decode_address(buf, bfin_read32(EVT0 + 4*i));
-			printf("  physical IVG%i asserted : %s\n", i, buf);
-		}
-	}
-	decode_address(buf, fp->rete);
-	printf(" RETE: %s\n", buf);
-	decode_address(buf, fp->retn);
-	printf(" RETN: %s\n", buf);
-	decode_address(buf, fp->retx);
-	printf(" RETX: %s\n", buf);
-	decode_address(buf, fp->rets);
-	printf(" RETS: %s\n", buf);
-	/* we lie and store RETI in "pc" */
-	decode_address(buf, fp->pc);
-	printf(" RETI: %s\n", buf);
-
-	if (fp->seqstat & EXCAUSE) {
-		decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
-		printf("DCPLB_FAULT_ADDR: %s\n", buf);
-		decode_address(buf, bfin_read_ICPLB_FAULT_ADDR());
-		printf("ICPLB_FAULT_ADDR: %s\n", buf);
-	}
-
-	printf("\nPROCESSOR STATE:\n");
-	printf(" R0 : %08lx    R1 : %08lx    R2 : %08lx    R3 : %08lx\n",
-		fp->r0, fp->r1, fp->r2, fp->r3);
-	printf(" R4 : %08lx    R5 : %08lx    R6 : %08lx    R7 : %08lx\n",
-		fp->r4, fp->r5, fp->r6, fp->r7);
-	printf(" P0 : %08lx    P1 : %08lx    P2 : %08lx    P3 : %08lx\n",
-		fp->p0, fp->p1, fp->p2, fp->p3);
-	printf(" P4 : %08lx    P5 : %08lx    FP : %08lx    SP : %08lx\n",
-		fp->p4, fp->p5, fp->fp, (unsigned long)fp);
-	printf(" LB0: %08lx    LT0: %08lx    LC0: %08lx\n",
-		fp->lb0, fp->lt0, fp->lc0);
-	printf(" LB1: %08lx    LT1: %08lx    LC1: %08lx\n",
-		fp->lb1, fp->lt1, fp->lc1);
-	printf(" B0 : %08lx    L0 : %08lx    M0 : %08lx    I0 : %08lx\n",
-		fp->b0, fp->l0, fp->m0, fp->i0);
-	printf(" B1 : %08lx    L1 : %08lx    M1 : %08lx    I1 : %08lx\n",
-		fp->b1, fp->l1, fp->m1, fp->i1);
-	printf(" B2 : %08lx    L2 : %08lx    M2 : %08lx    I2 : %08lx\n",
-		fp->b2, fp->l2, fp->m2, fp->i2);
-	printf(" B3 : %08lx    L3 : %08lx    M3 : %08lx    I3 : %08lx\n",
-		fp->b3, fp->l3, fp->m3, fp->i3);
-	printf("A0.w: %08lx   A0.x: %08lx   A1.w: %08lx   A1.x: %08lx\n",
-		fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
-	printf("USP : %08lx  ASTAT: %08lx\n",
-		fp->usp, fp->astat);
-
-	printf("\n");
-}
-
-static void _dump_bfin_trace_buffer(void)
-{
-	char buf[150];
-	int i = 0;
-
-	if (!ENABLE_DUMP)
-		return;
-
-	printf("Hardware Trace:\n");
-
-	if (bfin_read_TBUFSTAT() & TBUFCNT) {
-		for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
-			decode_address(buf, bfin_read_TBUF());
-			printf("%4i Target : %s\n", i, buf);
-			decode_address(buf, bfin_read_TBUF());
-			printf("     Source : %s\n", buf);
-		}
-	}
-}
-
-void dump_bfin_trace_buffer(void)
-{
-	unsigned long tflags;
-	trace_buffer_save(tflags);
-	_dump_bfin_trace_buffer();
-	trace_buffer_restore(tflags);
-}
-
-void bfin_dump(struct pt_regs *regs)
-{
-	unsigned long tflags;
-
-	trace_buffer_save(tflags);
-
-	puts(
-		"\n"
-		"\n"
-		"\n"
-		"Ack! Something bad happened to the Blackfin!\n"
-		"\n"
-	);
-	dump(regs);
-	_dump_bfin_trace_buffer();
-	puts("\n");
-
-	trace_buffer_restore(tflags);
-}
-
-void bfin_panic(struct pt_regs *regs)
-{
-	unsigned long tflags;
-	trace_buffer_save(tflags);
-	bfin_dump(regs);
-	panic("PANIC: Blackfin internal error");
-}
diff --git a/arch/blackfin/cpu/u-boot.lds b/arch/blackfin/cpu/u-boot.lds
deleted file mode 100644
index f407fb2..0000000
--- a/arch/blackfin/cpu/u-boot.lds
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * U-Boot - u-boot.lds.S
- *
- * Copyright (c) 2005-2010 Analog Device Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#undef ALIGN
-#undef ENTRY
-
-#ifndef LDS_BOARD_TEXT
-# define LDS_BOARD_TEXT
-#endif
-
-/* If we don't actually load anything into L1 data, this will avoid
- * a syntax error.  If we do actually load something into L1 data,
- * we'll get a linker memory load error (which is what we'd want).
- * This is here in the first place so we can quickly test building
- * for different CPU's which may lack non-cache L1 data.
- */
-#ifndef L1_DATA_A_SRAM
-# define L1_DATA_A_SRAM      0
-# define L1_DATA_A_SRAM_SIZE 0
-#endif
-#ifndef L1_DATA_B_SRAM
-# define L1_DATA_B_SRAM      L1_DATA_A_SRAM
-# define L1_DATA_B_SRAM_SIZE L1_DATA_A_SRAM_SIZE
-#endif
-
-/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
-#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
-# define L1_CODE_ORIGIN L1_INST_SRAM
-#else
-# define L1_CODE_ORIGIN L1_INST_SRAM + 0xC
-#endif
-
-OUTPUT_ARCH(bfin)
-
-MEMORY
-{
-#if CONFIG_MEM_SIZE
-	ram     : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
-# define ram_code ram
-# define ram_data ram
-#else
-# define ram_code l1_code
-# define ram_data l1_data
-#endif
-	l1_code : ORIGIN = L1_CODE_ORIGIN,          LENGTH = L1_INST_SRAM_SIZE
-	l1_data : ORIGIN = L1_DATA_B_SRAM,          LENGTH = L1_DATA_B_SRAM_SIZE
-}
-
-ENTRY(_start)
-SECTIONS
-{
-	.text.pre :
-	{
-		arch/blackfin/cpu/start.o (.text .text.*)
-
-		LDS_BOARD_TEXT
-	} >ram_code
-
-	.text.init :
-	{
-		arch/blackfin/cpu/initcode.o (.text .text.*)
-	} >ram_code
-	__initcode_lma = LOADADDR(.text.init);
-	__initcode_len = SIZEOF(.text.init);
-
-	.text :
-	{
-		*(.text .text.*)
-	} >ram_code
-
-	.rodata :
-	{
-		. = ALIGN(4);
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-		. = ALIGN(4);
-	} >ram_data
-
-	.data :
-	{
-		. = ALIGN(4);
-		*(.data .data.*)
-		*(.data1)
-		*(.sdata)
-		*(.sdata2)
-		*(.dynamic)
-		CONSTRUCTORS
-	} >ram_data
-
-
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	} >ram_data
-
-	.text_l1 :
-	{
-		. = ALIGN(4);
-		__stext_l1 = .;
-		*(.l1.text)
-		. = ALIGN(4);
-		__etext_l1 = .;
-	} >l1_code AT>ram_code
-	__text_l1_lma = LOADADDR(.text_l1);
-	__text_l1_len = SIZEOF(.text_l1);
-	ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!")
-
-	.data_l1 :
-	{
-		. = ALIGN(4);
-		__sdata_l1 = .;
-		*(.l1.data)
-		*(.l1.bss)
-		. = ALIGN(4);
-		__edata_l1 = .;
-	} >l1_data AT>ram_data
-	__data_l1_lma = LOADADDR(.data_l1);
-	__data_l1_len = SIZEOF(.data_l1);
-	ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data overflow!")
-
-	.bss :
-	{
-		. = ALIGN(4);
-		*(.sbss) *(.scommon)
-		*(.dynbss)
-		*(.bss .bss.*)
-		*(COMMON)
-		. = ALIGN(4);
-	} >ram_data
-	__bss_end = .;
-	__bss_start = ADDR(.bss);
-	__bss_len = SIZEOF(.bss);
-	__init_end = .;
-}
diff --git a/arch/blackfin/include/asm/bfin_logo_230x230_gzip.h b/arch/blackfin/include/asm/bfin_logo_230x230_gzip.h
deleted file mode 100644
index 3a79631..0000000
--- a/arch/blackfin/include/asm/bfin_logo_230x230_gzip.h
+++ /dev/null
@@ -1,2377 +0,0 @@
-/*
- * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
- *
- * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
- *
- * Where:	'screen'	is the pointer to the frame buffer
- *		'width'	is the screen width
- *		'x'		is the horizontal position
- *		'y'		is the vertical position
- */
-
-#define EASYLOGO_ENABLE_GZIP 37470
-
-static unsigned char EASYLOGO_DECOMP_BUFFER[158700];
-
-#include <video_easylogo.h>
-
-#define	DEF_BFIN_LOGO_WIDTH		230
-#define	DEF_BFIN_LOGO_HEIGHT		230
-#define	DEF_BFIN_LOGO_PIXELS		52900
-#define	DEF_BFIN_LOGO_BPP		24
-#define	DEF_BFIN_LOGO_PIXEL_SIZE	3
-#define	DEF_BFIN_LOGO_SIZE		158700
-
-unsigned char DEF_BFIN_LOGO_DATA[] = {
- 0x1f, 0x8b, 0x08, 0x00, 0x58, 0x7e, 0x68, 0x47, 0x00, 0x03, 0xec, 0x9d, 0x07, 0x5c, 0x53, 0xe7,
- 0xfe, 0xc6, 0x55, 0xb6, 0x04, 0x42, 0x80, 0x40, 0x26, 0x59, 0x24, 0x04, 0x02, 0x01, 0xc2, 0x86,
- 0x00, 0x61, 0x84, 0xbd, 0xf7, 0x5e, 0x22, 0x22, 0x88, 0xb6, 0x55, 0x71, 0xd4, 0x75, 0x6b, 0x7b,
- 0xfd, 0x54, 0x6b, 0xeb, 0xac, 0xb7, 0xe3, 0x52, 0xad, 0x5e, 0x57, 0xd5, 0xf6, 0xfe, 0x6b, 0x5b,
- 0xab, 0xd6, 0xd6, 0xb6, 0xee, 0x81, 0x5a, 0x95, 0xdb, 0xd6, 0x5d, 0x17, 0x52, 0x07, 0x60, 0xbc,
- 0xc5, 0xf5, 0xbf, 0x4f, 0x38, 0x35, 0x0d, 0x43, 0x2a, 0xdc, 0xaa, 0xb7, 0xf1, 0x3c, 0x9f, 0xa8,
- 0x90, 0x9c, 0x93, 0xf7, 0x3d, 0x9e, 0xef, 0x79, 0xde, 0xe7, 0xf7, 0xe6, 0x9c, 0x93, 0x41, 0x83,
- 0x48, 0xfd, 0x31, 0x1a, 0xdc, 0x9b, 0x9e, 0x76, 0xa7, 0x48, 0x91, 0xd2, 0x8a, 0xa0, 0x71, 0x48,
- 0xa7, 0x8c, 0x8d, 0x8d, 0x4d, 0x3a, 0x65, 0xd6, 0x43, 0xa6, 0xa6, 0xa6, 0x78, 0xde, 0xb8, 0x53,
- 0x46, 0x46, 0x46, 0x24, 0xc3, 0xa4, 0x9e, 0xa4, 0x74, 0x94, 0x82, 0x3d, 0xa0, 0x68, 0x6e, 0x6e,
- 0x6e, 0x61, 0x61, 0x61, 0x69, 0x69, 0x69, 0x6d, 0x6d, 0x6d, 0x63, 0x63, 0x63, 0x6b, 0x6b, 0x67,
- 0x6f, 0x4f, 0x77, 0xe8, 0x2a, 0x7b, 0x7b, 0x7b, 0x5b, 0x5b, 0x5b, 0xbc, 0x6a, 0x65, 0x65, 0x85,
- 0x25, 0xb1, 0x0a, 0x56, 0x24, 0xe8, 0xc5, 0xfb, 0x90, 0xf4, 0x92, 0x7a, 0x4c, 0x22, 0x40, 0x05,
- 0x69, 0xb0, 0xcd, 0xa1, 0x43, 0x87, 0x5a, 0x59, 0x59, 0x83, 0x43, 0x00, 0xc9, 0x62, 0xb1, 0x79,
- 0x3c, 0x9e, 0x48, 0x24, 0x92, 0x4a, 0xa5, 0xee, 0xee, 0xee, 0x5e, 0x5e, 0x5e, 0xde, 0xde, 0x0a,
- 0x85, 0xc2, 0x87, 0x78, 0x78, 0x7b, 0x7b, 0xcb, 0xe5, 0x9e, 0x32, 0x99, 0xcc, 0xc5, 0xc5, 0x45,
- 0x28, 0x14, 0x72, 0x38, 0x1c, 0x47, 0x47, 0x47, 0x80, 0x0d, 0xc2, 0x09, 0x7a, 0x61, 0xbf, 0x84,
- 0xf1, 0x3e, 0xed, 0xed, 0x23, 0x65, 0x38, 0x02, 0x4e, 0x80, 0x0a, 0x68, 0xc1, 0x4e, 0x41, 0x9a,
- 0x9d, 0x9d, 0x1d, 0x8b, 0xc5, 0x12, 0x08, 0x84, 0x6e, 0x6e, 0x6e, 0x00, 0x32, 0x30, 0x30, 0x30,
- 0x3c, 0x5c, 0x15, 0x13, 0x13, 0x9b, 0x9c, 0x9c, 0x9c, 0x99, 0x99, 0x99, 0x97, 0x97, 0x57, 0x58,
- 0x58, 0x58, 0xf4, 0x40, 0x05, 0x05, 0x05, 0xb9, 0xb9, 0xb9, 0x19, 0x19, 0x19, 0x89, 0x89, 0x89,
- 0x51, 0x51, 0xd1, 0x21, 0x21, 0x4a, 0x1f, 0x1f, 0x1f, 0x00, 0x0c, 0xc2, 0xd9, 0x6c, 0x36, 0x9d,
- 0x4e, 0xa7, 0x52, 0xa9, 0xe0, 0x1f, 0xae, 0x4b, 0x72, 0x4b, 0xea, 0xbf, 0x97, 0xce, 0x54, 0xe1,
- 0x87, 0x18, 0xd6, 0x99, 0x4c, 0x96, 0x50, 0x28, 0xf2, 0xf0, 0xf0, 0x08, 0x0c, 0x0c, 0x8a, 0x8e,
- 0x8e, 0x4e, 0x4d, 0x4d, 0xcd, 0xcf, 0xcf, 0x2f, 0x2f, 0x2f, 0xaf, 0xae, 0xae, 0xae, 0xa9, 0xa9,
- 0xc1, 0x0f, 0x59, 0x59, 0x59, 0x49, 0x49, 0xc9, 0xb1, 0xb1, 0xb1, 0x11, 0x11, 0x11, 0xa1, 0xa1,
- 0xa1, 0x51, 0x51, 0x51, 0x09, 0x09, 0x89, 0x19, 0x19, 0x99, 0xc5, 0xc5, 0x25, 0x58, 0xa6, 0xb6,
- 0xb6, 0x76, 0xd8, 0xb0, 0xca, 0x82, 0x82, 0xc2, 0xf4, 0xf4, 0x0c, 0x2c, 0x13, 0x12, 0x12, 0xe2,
- 0xe9, 0xe9, 0x29, 0x12, 0x39, 0x83, 0x7f, 0xd8, 0x35, 0x85, 0x42, 0x41, 0x43, 0x64, 0xd0, 0x25,
- 0x35, 0x30, 0x11, 0xac, 0x62, 0xd4, 0x46, 0xf8, 0xa4, 0xd3, 0x1d, 0x9c, 0x9c, 0x78, 0x6e, 0x6e,
- 0x32, 0x80, 0x0a, 0xd2, 0xb2, 0xb3, 0x73, 0x4a, 0x4a, 0x4a, 0x2b, 0x2a, 0x86, 0x95, 0x95, 0x95,
- 0xc5, 0xc7, 0x27, 0x20, 0x06, 0xc0, 0x2a, 0x41, 0xda, 0xef, 0xbe, 0x27, 0x98, 0x94, 0x48, 0x24,
- 0x6a, 0x75, 0x0c, 0xbc, 0xb7, 0xbc, 0xbc, 0xa2, 0xb4, 0xb4, 0x14, 0xc0, 0x27, 0x24, 0x24, 0x04,
- 0x07, 0x07, 0x23, 0x4e, 0xf0, 0xf9, 0x7c, 0x64, 0x0c, 0x78, 0xb8, 0x8e, 0xdb, 0x27, 0xb0, 0x99,
- 0xa4, 0x0c, 0x40, 0x44, 0x06, 0x00, 0x36, 0x60, 0x15, 0x08, 0x01, 0x24, 0xb9, 0x5c, 0x0e, 0xc3,
- 0x4c, 0x4e, 0x4e, 0x01, 0xa8, 0x70, 0xcb, 0xac, 0xac, 0x6c, 0x95, 0x4a, 0xe5, 0xec, 0xec, 0x8c,
- 0x9c, 0x30, 0xb0, 0x26, 0x70, 0x2c, 0x30, 0x99, 0xcc, 0x80, 0x80, 0x80, 0xf4, 0xf4, 0xf4, 0xa2,
- 0xa2, 0xe2, 0x92, 0x92, 0x92, 0xb4, 0xb4, 0xb4, 0xb0, 0xb0, 0x30, 0x34, 0x84, 0xe6, 0x50, 0xa9,
- 0xc1, 0xd2, 0x91, 0x13, 0xc8, 0xba, 0x8c, 0xd4, 0xef, 0x8a, 0xb0, 0x56, 0x04, 0x4b, 0x0c, 0xd3,
- 0xa8, 0xa7, 0x80, 0x50, 0x78, 0x78, 0x38, 0x06, 0x71, 0x8c, 0xe6, 0x30, 0xc6, 0xc8, 0xc8, 0x48,
- 0x57, 0x57, 0x57, 0x90, 0xfc, 0x47, 0x81, 0x04, 0x0f, 0x07, 0xf9, 0x88, 0x10, 0x88, 0xbe, 0x08,
- 0x15, 0x00, 0x58, 0xa9, 0x0c, 0x45, 0x13, 0xa8, 0xe6, 0x10, 0x42, 0x10, 0x9b, 0xd1, 0x19, 0x12,
- 0x5a, 0x52, 0x0f, 0x13, 0x70, 0x85, 0xb3, 0x61, 0xec, 0x86, 0xb5, 0x8a, 0xc5, 0x62, 0x0c, 0xd6,
- 0x48, 0xaa, 0x95, 0x95, 0x95, 0xa5, 0xa5, 0x65, 0xf0, 0x58, 0x00, 0x3c, 0x60, 0x53, 0xed, 0x5b,
- 0x78, 0x5b, 0x2e, 0x97, 0xab, 0x54, 0x2a, 0xcb, 0xca, 0x80, 0x6d, 0x39, 0x92, 0x86, 0xaf, 0xaf,
- 0x2f, 0x4a, 0x33, 0x74, 0x03, 0x9d, 0x21, 0xcc, 0xf6, 0x71, 0xb4, 0x4b, 0xea, 0x4f, 0x2d, 0x02,
- 0x57, 0xc4, 0x48, 0xd4, 0x41, 0xa8, 0xe5, 0x61, 0xa7, 0x18, 0xac, 0x47, 0x8d, 0x1a, 0x15, 0x1b,
- 0x1b, 0x87, 0x67, 0xf0, 0xd2, 0xe3, 0xee, 0x00, 0x9a, 0x60, 0x30, 0x18, 0x28, 0xe8, 0xd0, 0x68,
- 0x6e, 0x6e, 0x2e, 0x82, 0x07, 0xba, 0xc1, 0x66, 0xb3, 0xa9, 0x54, 0x2a, 0x99, 0x6c, 0x49, 0x75,
- 0x13, 0x81, 0x2b, 0xd8, 0x70, 0x72, 0x72, 0x52, 0x28, 0x14, 0x89, 0x89, 0x89, 0x55, 0x55, 0x55,
- 0x70, 0x3c, 0x81, 0x40, 0xf0, 0x18, 0xc7, 0xe5, 0xde, 0xde, 0x16, 0xcd, 0xc1, 0xcc, 0x8b, 0x8b,
- 0x8b, 0x87, 0x0d, 0x1b, 0x96, 0x9c, 0x9c, 0xec, 0xe7, 0xe7, 0x2f, 0x14, 0x0a, 0x11, 0x51, 0xc8,
- 0x84, 0x40, 0x4a, 0x27, 0xe0, 0x8a, 0x71, 0x19, 0xb8, 0x02, 0x15, 0x3f, 0x3f, 0x3f, 0x84, 0x49,
- 0xe0, 0x9a, 0x91, 0x91, 0x01, 0x67, 0x7b, 0x5c, 0x4d, 0xa2, 0xb8, 0x33, 0x33, 0xb3, 0xa0, 0x52,
- 0xcd, 0x29, 0x14, 0x23, 0x53, 0xd3, 0x9e, 0x1c, 0x22, 0x48, 0x87, 0x85, 0x85, 0x03, 0xda, 0xbc,
- 0xbc, 0x7c, 0x04, 0x69, 0x89, 0x44, 0x82, 0x84, 0x80, 0x72, 0x0c, 0xfd, 0x24, 0xa1, 0x7d, 0xc6,
- 0x05, 0x00, 0xe0, 0x5d, 0x88, 0x8b, 0x18, 0x7f, 0x7d, 0x7c, 0x7c, 0x80, 0x2b, 0x92, 0x24, 0xca,
- 0x76, 0xd4, 0x44, 0x8f, 0xaf, 0x51, 0x54, 0x77, 0x34, 0x16, 0x53, 0x22, 0x97, 0x4b, 0xbd, 0xbd,
- 0xb8, 0x62, 0x89, 0xb5, 0x9d, 0x9d, 0x09, 0x8e, 0x8e, 0xae, 0x28, 0xc2, 0xf3, 0x51, 0xf7, 0xa1,
- 0x22, 0x2b, 0x2d, 0x2d, 0x45, 0x69, 0x86, 0x72, 0xcc, 0xd1, 0xd1, 0x11, 0xd0, 0x92, 0xf1, 0xe0,
- 0x19, 0x17, 0x00, 0x80, 0xa1, 0xc1, 0xc1, 0x3c, 0x3c, 0x3c, 0x30, 0x0a, 0x23, 0x09, 0x04, 0x05,
- 0x05, 0x61, 0x08, 0x7e, 0xac, 0x8d, 0x9a, 0x98, 0x9b, 0xf3, 0xa4, 0xd2, 0xb0, 0x98, 0x98, 0xf8,
- 0xf4, 0xf4, 0xa8, 0xc4, 0x44, 0x45, 0x70, 0x30, 0x57, 0x2c, 0xa6, 0xd0, 0x68, 0x20, 0x59, 0x7f,
- 0x31, 0x90, 0x89, 0x94, 0x92, 0x9d, 0x9d, 0x53, 0x51, 0x51, 0x81, 0x5c, 0xed, 0xe2, 0x22, 0xb5,
- 0xb7, 0xa7, 0xa3, 0x6f, 0x8f, 0x32, 0xf7, 0x4b, 0xca, 0x20, 0x45, 0xc4, 0x57, 0xa4, 0x44, 0xb1,
- 0x58, 0xac, 0x56, 0xab, 0x4b, 0x4b, 0xcb, 0x30, 0x04, 0x03, 0xe0, 0xc7, 0xdd, 0x2e, 0xc2, 0x80,
- 0x1b, 0xfc, 0x3c, 0x37, 0xaf, 0xaa, 0xa6, 0x66, 0x04, 0xea, 0xac, 0x92, 0x92, 0xc8, 0x84, 0x04,
- 0x99, 0x8f, 0x8f, 0x1d, 0x8b, 0x65, 0xd4, 0xa3, 0xc4, 0x03, 0xa5, 0x28, 0xc4, 0xca, 0xca, 0xb4,
- 0x7d, 0x73, 0x76, 0x16, 0xa3, 0xb7, 0x88, 0x2b, 0xe4, 0xec, 0xc1, 0x33, 0x28, 0x22, 0x0f, 0x58,
- 0x59, 0x59, 0x71, 0xb9, 0xdc, 0xc0, 0xc0, 0xc0, 0xa2, 0xa2, 0xe2, 0xcc, 0xcc, 0xcc, 0x27, 0x80,
- 0x2b, 0x44, 0xb1, 0xb1, 0xf1, 0x0b, 0x0b, 0x2d, 0x19, 0x36, 0x6c, 0xca, 0xb4, 0xe9, 0xb3, 0x5e,
- 0x9d, 0x3d, 0xe1, 0xc5, 0x29, 0xc3, 0x46, 0x8c, 0x48, 0xcc, 0xc8, 0x80, 0xd9, 0x32, 0xf8, 0x3c,
- 0xa3, 0x1e, 0xf9, 0x19, 0x79, 0xa0, 0xa0, 0xa0, 0x00, 0x09, 0x21, 0x38, 0x38, 0x18, 0x61, 0x1b,
- 0x91, 0x9b, 0x0c, 0xb4, 0xcf, 0xa0, 0x60, 0x53, 0x18, 0x61, 0x01, 0x03, 0xe2, 0x62, 0x5a, 0x5a,
- 0x5a, 0x65, 0x65, 0xa5, 0x9d, 0x9d, 0xdd, 0x93, 0x68, 0x78, 0xf0, 0x60, 0xaa, 0x83, 0x03, 0x22,
- 0x41, 0xcd, 0xe8, 0xd1, 0xaf, 0xce, 0x79, 0x6d, 0xfe, 0xc2, 0x45, 0xb3, 0x5f, 0x9b, 0x3b, 0x61,
- 0xf2, 0xe4, 0x8a, 0xea, 0xea, 0xc4, 0x8c, 0x4c, 0xdf, 0x90, 0x10, 0x06, 0x9f, 0x6f, 0xd4, 0x35,
- 0x45, 0x03, 0x4e, 0x0e, 0x87, 0x53, 0x5c, 0x5c, 0x92, 0x93, 0x93, 0xe3, 0xef, 0xef, 0xcf, 0x66,
- 0x73, 0x10, 0x68, 0xc9, 0xa9, 0x83, 0x67, 0x4d, 0xd8, 0xe3, 0x30, 0x2b, 0x91, 0x48, 0x14, 0x11,
- 0x11, 0x39, 0x7c, 0x78, 0x95, 0xa7, 0xa7, 0xe7, 0x93, 0x69, 0x77, 0xf0, 0x90, 0x21, 0xf6, 0x6c,
- 0xb6, 0x3a, 0x29, 0xe9, 0xf9, 0xf1, 0xe3, 0xe7, 0xbe, 0xfe, 0xc6, 0xeb, 0xf3, 0xe6, 0xbf, 0x3c,
- 0x6b, 0xd6, 0xd8, 0x09, 0x13, 0x2b, 0x47, 0x8e, 0xcc, 0x2a, 0x28, 0x50, 0xc5, 0xc6, 0xba, 0x29,
- 0x14, 0x34, 0x16, 0x6b, 0x48, 0xd7, 0x78, 0x80, 0xe3, 0xcb, 0xdd, 0xdd, 0x1d, 0x55, 0x61, 0x4a,
- 0x4a, 0x0a, 0x22, 0x37, 0x9d, 0x4e, 0x47, 0x6d, 0x48, 0x66, 0x83, 0x67, 0x47, 0xd8, 0xd7, 0xd8,
- 0xe3, 0x30, 0x58, 0x6f, 0x6f, 0xef, 0xec, 0xec, 0xec, 0x92, 0x92, 0x92, 0x27, 0xf0, 0x19, 0xc1,
- 0xaf, 0x4d, 0x1b, 0x19, 0x39, 0xf2, 0x78, 0xf1, 0xa9, 0x69, 0xcf, 0x8f, 0x1b, 0xff, 0x97, 0x99,
- 0x33, 0x27, 0x4e, 0x99, 0x52, 0x3b, 0xe6, 0xb9, 0x92, 0xca, 0xca, 0xf4, 0xbc, 0x3c, 0x60, 0x1c,
- 0xa0, 0x52, 0x49, 0xbd, 0xbd, 0xe9, 0x3c, 0x27, 0xe3, 0x1e, 0xf9, 0x04, 0x1d, 0x8e, 0x8a, 0x8a,
- 0x2a, 0x2f, 0xd7, 0x56, 0x61, 0x42, 0xa1, 0xd0, 0xc6, 0xc6, 0xc6, 0xb4, 0xb7, 0x99, 0x31, 0x52,
- 0x06, 0x29, 0x94, 0xdb, 0x48, 0xb0, 0x7c, 0x3e, 0x5f, 0xa5, 0x52, 0x21, 0x0f, 0x78, 0x78, 0xc8,
- 0x9f, 0xd8, 0xae, 0x1f, 0x62, 0x6c, 0xcc, 0x12, 0x0a, 0xe3, 0xd3, 0xd2, 0x86, 0xd7, 0xd4, 0x54,
- 0xd5, 0xd6, 0xe6, 0x97, 0x95, 0x25, 0x65, 0x66, 0xa9, 0xe2, 0xe2, 0x7c, 0x95, 0x4a, 0xed, 0x64,
- 0x97, 0x44, 0x4c, 0x63, 0xb3, 0xcc, 0xa9, 0xd4, 0xc1, 0x5d, 0xe7, 0x0d, 0x08, 0xc1, 0x5a, 0x8b,
- 0x8a, 0x8a, 0xf2, 0xf2, 0xf2, 0x14, 0x0a, 0x05, 0x93, 0xc9, 0x44, 0xea, 0x26, 0xe7, 0x0d, 0x9e,
- 0x05, 0x01, 0x4e, 0xb8, 0x13, 0x52, 0xab, 0x4c, 0x26, 0x43, 0x82, 0xcd, 0xcf, 0x2f, 0xa0, 0xd1,
- 0x68, 0x4f, 0xac, 0x75, 0x10, 0xcb, 0x14, 0x0a, 0x22, 0xe2, 0xe3, 0xd3, 0x73, 0xf3, 0x62, 0x53,
- 0x52, 0x03, 0x23, 0x22, 0x64, 0xbe, 0x3e, 0x4e, 0x2e, 0x12, 0x5b, 0x0e, 0x7b, 0x28, 0xcd, 0xc6,
- 0xc4, 0xc2, 0x42, 0xcb, 0xea, 0x43, 0x0e, 0x1f, 0xf4, 0x1c, 0x83, 0x42, 0x75, 0x75, 0xb5, 0x5a,
- 0xad, 0x16, 0x8b, 0xc5, 0xe8, 0x36, 0x69, 0xb3, 0xcf, 0x82, 0xb0, 0x8b, 0x51, 0x73, 0xb1, 0x58,
- 0xac, 0x80, 0x80, 0x80, 0xd2, 0xd2, 0x32, 0xa5, 0x52, 0xf9, 0xc4, 0x22, 0xc1, 0xa0, 0xce, 0x54,
- 0x40, 0x77, 0x72, 0x52, 0x84, 0x84, 0xf8, 0x84, 0x84, 0x88, 0xe5, 0x72, 0x3b, 0x27, 0xae, 0x85,
- 0x0d, 0xd5, 0x18, 0xe0, 0xc1, 0x2d, 0x1f, 0x81, 0x3d, 0x13, 0x13, 0x13, 0xe2, 0xd2, 0x06, 0x3f,
- 0x3f, 0x3f, 0x6c, 0x02, 0x69, 0xb3, 0xcf, 0x82, 0xb0, 0x8b, 0x29, 0x14, 0x8a, 0x40, 0x20, 0x8c,
- 0x8e, 0x8e, 0x06, 0xb1, 0x02, 0x81, 0xe0, 0x49, 0xb6, 0x8e, 0xca, 0xcb, 0xd2, 0xd6, 0x96, 0x21,
- 0xe0, 0x5b, 0x3b, 0x38, 0x18, 0x0d, 0xe8, 0x93, 0x35, 0x0e, 0x87, 0x53, 0x57, 0x37, 0x3a, 0x2e,
- 0x2e, 0xce, 0xc5, 0xc5, 0x05, 0x36, 0x4b, 0xce, 0x74, 0x19, 0xb6, 0xb0, 0x73, 0xb1, 0x8b, 0x6d,
- 0x6c, 0x68, 0xae, 0xae, 0xae, 0xa9, 0x5a, 0xa5, 0x3d, 0xa1, 0x49, 0xad, 0xae, 0x3d, 0xd0, 0x4e,
- 0x05, 0x0c, 0x14, 0x33, 0x1c, 0x71, 0x59, 0x59, 0x59, 0x85, 0x85, 0x85, 0x84, 0xcd, 0x62, 0xbc,
- 0x20, 0x27, 0x0d, 0x0c, 0x58, 0x44, 0x88, 0x45, 0x09, 0xe3, 0xed, 0xad, 0x40, 0x82, 0x8d, 0x88,
- 0x88, 0x7c, 0x8c, 0x67, 0xbc, 0x3c, 0x1e, 0x61, 0x13, 0x24, 0x12, 0x49, 0x55, 0xd5, 0x08, 0x8c,
- 0x11, 0x22, 0x91, 0x88, 0x4a, 0xa5, 0x1a, 0xf7, 0x56, 0xa6, 0x91, 0x32, 0x0c, 0x11, 0xf3, 0x5a,
- 0xb0, 0xa6, 0xe0, 0xe0, 0xe0, 0xe2, 0xe2, 0x62, 0x5f, 0x5f, 0xdf, 0x3f, 0xe3, 0x90, 0x6a, 0x6d,
- 0x6d, 0x9d, 0x9d, 0x9d, 0x0d, 0xa7, 0x95, 0xcb, 0xe5, 0x38, 0xfa, 0x70, 0xd0, 0xfd, 0x19, 0xb7,
- 0x82, 0xd4, 0xa3, 0x08, 0xc4, 0x5a, 0x5a, 0x5a, 0xf2, 0x78, 0xbc, 0xc8, 0xc8, 0x28, 0x78, 0xac,
- 0x44, 0xe2, 0xf2, 0xb4, 0x7b, 0x34, 0x10, 0xc1, 0x54, 0x71, 0xac, 0x55, 0x54, 0x54, 0xe0, 0xb8,
- 0x43, 0xac, 0x45, 0xfd, 0x45, 0x06, 0x03, 0x43, 0x15, 0x31, 0x13, 0xeb, 0xec, 0xec, 0x9c, 0x90,
- 0x90, 0x90, 0x93, 0x93, 0x03, 0xb3, 0x7d, 0xda, 0x3d, 0x1a, 0xa0, 0x9c, 0x9c, 0x9c, 0x0a, 0x0b,
- 0x8b, 0x62, 0x63, 0xe3, 0x9c, 0x9d, 0xc5, 0xb0, 0x5c, 0x32, 0x18, 0x18, 0xaa, 0xb0, 0x67, 0x6d,
- 0x6c, 0x6c, 0x50, 0x76, 0xa5, 0x77, 0xca, 0xca, 0xca, 0xfa, 0x69, 0xf7, 0x68, 0x80, 0xb2, 0xb4,
- 0xa4, 0xc4, 0xc6, 0xc6, 0xe2, 0xa0, 0x23, 0x2e, 0x3f, 0x27, 0x27, 0x66, 0x0d, 0x52, 0xc4, 0x44,
- 0x81, 0xad, 0xad, 0xad, 0x87, 0x87, 0x47, 0x4e, 0x4e, 0x6e, 0x62, 0x62, 0xe2, 0x9f, 0x77, 0x32,
- 0x13, 0xdb, 0x82, 0x60, 0x80, 0x28, 0x1e, 0x12, 0x12, 0xc2, 0x66, 0xb3, 0xc9, 0x19, 0x03, 0x83,
- 0x14, 0xf6, 0x32, 0x8a, 0x14, 0x7b, 0x7b, 0x7b, 0x85, 0x42, 0x51, 0x50, 0x50, 0x10, 0x1d, 0xad,
- 0x7e, 0xda, 0x3d, 0xfa, 0xaf, 0x24, 0x14, 0x0a, 0xf3, 0xf2, 0xf2, 0x63, 0x62, 0x62, 0xf0, 0x03,
- 0x85, 0x42, 0xf9, 0xf3, 0x1e, 0x7d, 0xa4, 0x1e, 0x26, 0x10, 0x4b, 0x9c, 0x00, 0xe3, 0xef, 0xef,
- 0x0f, 0x77, 0x0a, 0x0f, 0x57, 0xfd, 0xce, 0x0a, 0x80, 0xc0, 0xc2, 0xc2, 0x94, 0x42, 0x31, 0xb6,
- 0xb0, 0x18, 0xf4, 0xc7, 0x39, 0xd8, 0x60, 0x23, 0x23, 0x1b, 0x3a, 0xdd, 0x45, 0x26, 0xf3, 0x0b,
- 0x0c, 0xf4, 0xf6, 0xf7, 0x67, 0x70, 0xb9, 0xc6, 0x03, 0xba, 0xae, 0x1c, 0xf1, 0x95, 0xc8, 0x36,
- 0x08, 0x39, 0x88, 0x3a, 0xe4, 0x47, 0x09, 0x86, 0x27, 0xe2, 0x9c, 0x58, 0x26, 0x93, 0x85, 0x91,
- 0xb4, 0xb4, 0xb4, 0x34, 0x28, 0x28, 0xa8, 0xef, 0xe5, 0x8d, 0xcd, 0xcd, 0xed, 0xb9, 0x5c, 0x81,
- 0x9b, 0x9b, 0x58, 0xee, 0x21, 0x90, 0x4a, 0x81, 0xd9, 0x1f, 0xc2, 0x2d, 0xb8, 0xa2, 0xd0, 0x68,
- 0x7e, 0xca, 0xd0, 0xca, 0xea, 0x91, 0x53, 0x67, 0xcc, 0x18, 0x3f, 0x71, 0x52, 0x4e, 0x41, 0x01,
- 0x97, 0xcf, 0x1f, 0xdc, 0xcf, 0x37, 0xc7, 0xe6, 0xc0, 0x60, 0xf3, 0xf3, 0xf3, 0x31, 0x64, 0x90,
- 0x73, 0x5c, 0x06, 0x29, 0xec, 0xe2, 0xa1, 0x43, 0x87, 0xb2, 0xd9, 0x9c, 0xb0, 0xb0, 0x30, 0x10,
- 0x8b, 0x1d, 0xfd, 0x3b, 0xcb, 0x1b, 0x19, 0xd1, 0x1c, 0x1d, 0x65, 0x3e, 0xbe, 0x11, 0x71, 0xf1,
- 0xa9, 0xd9, 0x39, 0xf1, 0x29, 0xa9, 0x52, 0x4f, 0x4f, 0xf3, 0x81, 0x5e, 0xa7, 0x40, 0xdc, 0x75,
- 0x56, 0x77, 0xe7, 0x58, 0xf8, 0x2a, 0xde, 0x4a, 0x19, 0x19, 0x39, 0x79, 0xea, 0xd4, 0xd9, 0xaf,
- 0xcd, 0x1d, 0x37, 0x61, 0x92, 0x4c, 0xee, 0x69, 0xd4, 0xcf, 0x92, 0xdf, 0xc7, 0xc7, 0x07, 0x83,
- 0x85, 0x52, 0xa9, 0x64, 0xb1, 0xd8, 0xe4, 0x1c, 0x97, 0xe1, 0x89, 0x20, 0x96, 0xc3, 0xe1, 0x22,
- 0x0f, 0x80, 0x58, 0x99, 0x4c, 0xf6, 0x28, 0x6b, 0x59, 0x52, 0xa9, 0x6e, 0x5e, 0x5e, 0x29, 0x59,
- 0x59, 0xb5, 0x63, 0xc6, 0x0c, 0x1f, 0x39, 0x32, 0x20, 0x34, 0x74, 0xa8, 0x95, 0xd5, 0xa3, 0x7f,
- 0xc6, 0x0a, 0x3e, 0xa9, 0x36, 0x36, 0x5c, 0x27, 0x27, 0x4f, 0x2f, 0x2f, 0x55, 0x44, 0x44, 0x4c,
- 0x6c, 0x6c, 0x58, 0x78, 0xb8, 0xbb, 0xbb, 0x3b, 0x8f, 0xc7, 0x83, 0x31, 0x82, 0x5b, 0x3b, 0x3a,
- 0xbd, 0xa8, 0xb4, 0x74, 0xd6, 0x9c, 0x39, 0xf5, 0x93, 0x5e, 0xe4, 0x8b, 0x44, 0xfd, 0xf2, 0x49,
- 0xbc, 0x09, 0x36, 0x44, 0xad, 0x56, 0xf3, 0xf9, 0x02, 0x2b, 0x2b, 0x2b, 0x72, 0x8e, 0xcb, 0xc0,
- 0xa4, 0x23, 0x56, 0xa5, 0x52, 0x95, 0x94, 0x94, 0xb8, 0xb8, 0x48, 0x7b, 0x5d, 0x0c, 0xcc, 0x58,
- 0x53, 0xa9, 0x60, 0x4c, 0x20, 0x10, 0xa0, 0x0c, 0xb7, 0xb2, 0xb6, 0xc6, 0x8a, 0x0e, 0x6c, 0x76,
- 0x74, 0x7c, 0xfc, 0xc8, 0xba, 0xba, 0xe1, 0x35, 0x35, 0x9e, 0xfe, 0xfe, 0x26, 0x8f, 0xf6, 0xd9,
- 0x2e, 0x9a, 0x53, 0xf8, 0xfa, 0x96, 0x95, 0x57, 0xbc, 0xfc, 0xca, 0x5f, 0x5f, 0x7f, 0x7d, 0xde,
- 0xc2, 0x85, 0x8b, 0x16, 0x2e, 0x5a, 0xbc, 0x60, 0xd1, 0xa2, 0x37, 0xe6, 0xcd, 0x7b, 0x75, 0xf6,
- 0x9c, 0xb1, 0xe3, 0xc6, 0x85, 0x28, 0x95, 0x54, 0x2a, 0xd5, 0xd6, 0xde, 0x3e, 0xaf, 0xa8, 0x68,
- 0xd6, 0xec, 0x39, 0x25, 0x95, 0x95, 0xfd, 0xf2, 0x70, 0x14, 0x5c, 0x20, 0x36, 0x25, 0x25, 0x45,
- 0x22, 0x91, 0x10, 0x51, 0xf6, 0xd1, 0xd7, 0x25, 0xf5, 0xbf, 0x2f, 0x3d, 0x62, 0x23, 0x30, 0x98,
- 0x3a, 0x3b, 0x3b, 0xf7, 0x5c, 0x06, 0x36, 0xe5, 0x21, 0x97, 0xe7, 0x17, 0x14, 0x00, 0xa7, 0x49,
- 0x93, 0x26, 0x3f, 0xf7, 0xfc, 0x0b, 0x45, 0xc5, 0x25, 0xd1, 0xd1, 0x6a, 0x1a, 0x8d, 0x66, 0x6e,
- 0x61, 0x11, 0x1c, 0x16, 0x56, 0x33, 0x7a, 0x74, 0x4e, 0x51, 0x11, 0x1b, 0xb1, 0xf3, 0xf7, 0xcc,
- 0x10, 0x6d, 0x65, 0x66, 0x65, 0x81, 0xcc, 0xbf, 0x37, 0x34, 0xac, 0x5e, 0xb5, 0x7a, 0xfd, 0xba,
- 0x0d, 0xff, 0xd4, 0xea, 0xff, 0xf0, 0x67, 0xc3, 0x86, 0x0f, 0xd7, 0xae, 0xfd, 0x60, 0xc5, 0x8a,
- 0x15, 0x00, 0x38, 0x27, 0x27, 0xc7, 0xde, 0xde, 0xde, 0x91, 0xc1, 0x2c, 0x1f, 0x3e, 0x1c, 0x09,
- 0x41, 0xda, 0x9f, 0xeb, 0x77, 0xd0, 0x87, 0xdc, 0xdc, 0xdc, 0xec, 0xec, 0x6c, 0x77, 0x77, 0x0f,
- 0x3b, 0x3b, 0x7b, 0x72, 0x56, 0xd6, 0xc0, 0x44, 0x10, 0xcb, 0xe5, 0x3a, 0x81, 0xd8, 0xa2, 0xa2,
- 0xa2, 0x9e, 0xe7, 0x19, 0x62, 0x77, 0x2b, 0x7c, 0x7c, 0xa6, 0x4e, 0x9b, 0xf6, 0xee, 0xdf, 0x1b,
- 0x56, 0xaf, 0x5e, 0xb3, 0x4e, 0xab, 0xf5, 0xab, 0xd7, 0xac, 0x05, 0x72, 0x63, 0xc6, 0x8c, 0xe1,
- 0x72, 0xb9, 0x14, 0x6b, 0x6b, 0x95, 0x5a, 0x9d, 0x55, 0x58, 0x24, 0xf7, 0xf7, 0x37, 0xea, 0xd3,
- 0xd0, 0xcc, 0xcd, 0xcd, 0x73, 0xf3, 0xf2, 0x1a, 0x1a, 0xde, 0xfb, 0xe8, 0xa3, 0x7f, 0x6e, 0xdd,
- 0xfa, 0xc5, 0xb7, 0xdf, 0x7c, 0xbb, 0x7b, 0xf7, 0xee, 0xbd, 0x7b, 0xf7, 0xee, 0xdb, 0xb7, 0x0f,
- 0x7f, 0xef, 0xd9, 0xbd, 0x7b, 0xe7, 0x8e, 0x1d, 0xdb, 0xb7, 0x6f, 0xff, 0xf4, 0xb3, 0x4d, 0x0d,
- 0x0d, 0x0d, 0x59, 0x59, 0x39, 0xe8, 0x18, 0x83, 0xc5, 0xca, 0x29, 0x2c, 0x8c, 0x4a, 0x4c, 0x34,
- 0xeb, 0x8f, 0xcd, 0xaa, 0xd5, 0x31, 0x85, 0x85, 0x45, 0x08, 0xb4, 0x8e, 0x8e, 0x8e, 0x68, 0x94,
- 0x24, 0xd6, 0x90, 0xa4, 0x4f, 0x6c, 0x01, 0xca, 0x73, 0x2e, 0xb7, 0xdb, 0x02, 0x70, 0xdd, 0x17,
- 0xa7, 0x4c, 0x59, 0xbb, 0x76, 0xed, 0xd6, 0xad, 0x5b, 0x77, 0xee, 0xdc, 0x09, 0xb6, 0xf6, 0xef,
- 0xd3, 0x6a, 0xe7, 0xae, 0x5d, 0x9b, 0x3f, 0xdf, 0x3c, 0x7d, 0xc6, 0x0c, 0x07, 0x07, 0x07, 0x3a,
- 0x83, 0xe1, 0x19, 0x10, 0xe8, 0x2c, 0x93, 0x0d, 0xe9, 0xf3, 0x3c, 0xf0, 0xb4, 0xf4, 0xf4, 0xf7,
- 0x97, 0x2f, 0xff, 0xfa, 0xeb, 0xaf, 0x0f, 0x35, 0x36, 0x36, 0x35, 0x35, 0x9d, 0x38, 0x71, 0xe2,
- 0xf4, 0xe9, 0xd3, 0x67, 0xce, 0x9c, 0x39, 0x8b, 0x3f, 0xa7, 0xcf, 0x9c, 0x3a, 0x75, 0xea, 0xc4,
- 0x89, 0x93, 0xdf, 0x7f, 0xff, 0xfd, 0x91, 0xc3, 0x87, 0x77, 0x7c, 0xfb, 0xed, 0xd2, 0x65, 0xcb,
- 0x94, 0xca, 0x50, 0xc0, 0x66, 0x4b, 0xa7, 0xfb, 0x84, 0x84, 0xd8, 0x31, 0x99, 0x8f, 0xbe, 0x51,
- 0x0a, 0x85, 0x4f, 0x59, 0x59, 0x79, 0x60, 0x60, 0x20, 0x71, 0x82, 0x37, 0x59, 0x7c, 0x19, 0x92,
- 0xba, 0x11, 0x8b, 0x8c, 0xaa, 0xff, 0xea, 0x50, 0x4b, 0xcb, 0xbc, 0xfc, 0x7c, 0x8c, 0xda, 0xfb,
- 0xf7, 0x1f, 0xf8, 0xe1, 0x87, 0x1f, 0xce, 0x9d, 0x3d, 0x77, 0xe1, 0xfc, 0x85, 0x4b, 0x17, 0x2f,
- 0x35, 0x5f, 0x6e, 0xbe, 0x74, 0xe9, 0xd2, 0xb9, 0x33, 0x67, 0x41, 0xd7, 0xcc, 0x99, 0x33, 0x11,
- 0x1d, 0x8d, 0xcd, 0xcd, 0x8d, 0x7a, 0xdc, 0x77, 0x48, 0x5f, 0x48, 0xa7, 0xcb, 0x97, 0x2f, 0xc7,
- 0xf2, 0x17, 0x2e, 0x5c, 0xb8, 0x7a, 0xf5, 0x6a, 0x6b, 0x6b, 0x6b, 0xfb, 0xcd, 0x9b, 0x37, 0x35,
- 0xd0, 0x2d, 0xfc, 0x7b, 0xb3, 0xfd, 0x66, 0x7b, 0x7b, 0x7b, 0x6b, 0x6b, 0xdb, 0xb5, 0x6b, 0xd7,
- 0x5b, 0xae, 0x5c, 0x39, 0x7b, 0xf6, 0xec, 0xc1, 0x83, 0x07, 0x17, 0x2c, 0x58, 0x88, 0xe3, 0x45,
- 0x7b, 0x17, 0x05, 0x33, 0x33, 0x53, 0x4b, 0xcb, 0x47, 0xdf, 0x28, 0x91, 0x48, 0x54, 0x55, 0x35,
- 0x22, 0x3c, 0x3c, 0xdc, 0xc9, 0xc9, 0x89, 0xb8, 0xcd, 0xd1, 0xc0, 0xff, 0x83, 0x48, 0xfd, 0x8f,
- 0xa9, 0x6f, 0x8f, 0x95, 0x48, 0x5c, 0xd6, 0xac, 0x5e, 0x7b, 0xfc, 0xd8, 0xf1, 0xcb, 0x97, 0x9b,
- 0x5b, 0xdb, 0xda, 0x6f, 0xdd, 0xba, 0xd5, 0xd1, 0xd1, 0x71, 0xfb, 0xf6, 0xed, 0x3b, 0x9d, 0xc2,
- 0x4f, 0x00, 0x0e, 0xdc, 0x8e, 0x1f, 0x37, 0xbe, 0xef, 0x1b, 0x71, 0xd0, 0x68, 0xb6, 0xd3, 0xa6,
- 0x4f, 0x87, 0xa9, 0x02, 0xcb, 0x3b, 0x77, 0xef, 0xde, 0xbb, 0x7f, 0xff, 0xff, 0x7b, 0x08, 0x4f,
- 0xdd, 0xbf, 0x7f, 0xff, 0xde, 0xbd, 0x7b, 0x78, 0xf7, 0x5b, 0x9a, 0x5b, 0x2d, 0x2d, 0x2d, 0xfb,
- 0xf7, 0xef, 0x2f, 0x29, 0x29, 0x1d, 0xc0, 0x0d, 0x94, 0xe8, 0x74, 0x7a, 0x4d, 0x4d, 0x6d, 0x74,
- 0x74, 0x34, 0x42, 0x8e, 0x95, 0x95, 0x15, 0x49, 0xac, 0x21, 0xa9, 0x8f, 0x1c, 0x8b, 0x82, 0x2b,
- 0x2d, 0x2d, 0x0d, 0xc3, 0x74, 0x7b, 0xfb, 0xcd, 0x3b, 0x77, 0xee, 0xde, 0xef, 0x0d, 0x33, 0xe8,
- 0xee, 0xbd, 0x7b, 0xf0, 0xc3, 0x90, 0x90, 0x90, 0x3e, 0x5a, 0x89, 0x8a, 0x8a, 0x3e, 0x78, 0xb0,
- 0xf1, 0x97, 0x8e, 0x8e, 0x5e, 0xdf, 0xa1, 0x57, 0x01, 0xec, 0xab, 0x57, 0xaf, 0x6d, 0xde, 0xbc,
- 0x05, 0x25, 0x7f, 0x7f, 0x37, 0xca, 0xcc, 0xcc, 0xac, 0xae, 0x6e, 0x74, 0x6c, 0x6c, 0x2c, 0x2c,
- 0xda, 0xda, 0xda, 0x9a, 0x24, 0xd6, 0x90, 0xd4, 0x07, 0xb1, 0x54, 0x2a, 0x75, 0xe9, 0xd2, 0x65,
- 0x9a, 0x5b, 0xb7, 0x08, 0x56, 0xf1, 0xf7, 0xc9, 0x93, 0x27, 0x8f, 0x1e, 0x3d, 0x8a, 0x31, 0xbd,
- 0x1b, 0xbd, 0x77, 0xef, 0xde, 0x9d, 0x30, 0x71, 0xe2, 0xc3, 0x6c, 0x16, 0x2e, 0x37, 0x79, 0xf2,
- 0xe4, 0xd6, 0xb6, 0xb6, 0x6e, 0xc4, 0xc3, 0x4e, 0x31, 0xfa, 0x6f, 0xdb, 0xb6, 0xed, 0xe3, 0x8f,
- 0x3f, 0xfe, 0xf2, 0xcb, 0x2f, 0xcf, 0x9f, 0x3f, 0x8f, 0x67, 0xba, 0x1d, 0x0b, 0x97, 0x2f, 0x5f,
- 0xae, 0xaf, 0xaf, 0x1f, 0x00, 0x72, 0xa8, 0x0a, 0xe3, 0xe3, 0xe3, 0xc5, 0x62, 0x31, 0x79, 0x3d,
- 0x82, 0x81, 0xa9, 0x0f, 0x62, 0x51, 0x52, 0x1d, 0x39, 0x72, 0x84, 0x18, 0xc1, 0x7f, 0xfe, 0xf9,
- 0xe7, 0x29, 0x53, 0xa6, 0x04, 0x05, 0x05, 0xf9, 0xf9, 0xf9, 0x25, 0x26, 0x26, 0xbe, 0xf3, 0xce,
- 0x3b, 0xd7, 0xaf, 0x5f, 0xd7, 0xa7, 0xeb, 0xd0, 0xa1, 0x43, 0x52, 0x69, 0xef, 0x73, 0xb9, 0xc0,
- 0x06, 0x56, 0x09, 0xaa, 0xf5, 0x97, 0xc7, 0xa0, 0x3f, 0x77, 0xee, 0x5c, 0x95, 0x4a, 0xe5, 0xea,
- 0xea, 0x8a, 0xd8, 0xe9, 0xea, 0xe6, 0xa6, 0x56, 0xab, 0x97, 0x2e, 0x5d, 0x8a, 0xd8, 0xd0, 0xc5,
- 0x69, 0xef, 0xdc, 0x39, 0x70, 0xe0, 0xc0, 0x00, 0xae, 0xe2, 0x19, 0x33, 0xe6, 0x39, 0x92, 0x58,
- 0x83, 0x94, 0x3e, 0xb1, 0xdd, 0xe6, 0x63, 0x99, 0x4c, 0x26, 0x40, 0x05, 0x36, 0xbf, 0xfc, 0xf2,
- 0xcb, 0xd8, 0xb1, 0x63, 0xb1, 0xeb, 0x75, 0xab, 0xd0, 0x68, 0xb4, 0x89, 0x13, 0x27, 0xa2, 0x60,
- 0xd2, 0xa1, 0x85, 0x88, 0xeb, 0xe7, 0xe7, 0xdf, 0x6b, 0x13, 0x3e, 0x3e, 0xbe, 0x27, 0x4f, 0x9c,
- 0xd4, 0xb7, 0x65, 0xa4, 0x5f, 0xe0, 0x6a, 0x6b, 0x6b, 0x4b, 0xcc, 0x3b, 0x71, 0xf9, 0xfc, 0x89,
- 0x93, 0x27, 0x97, 0x57, 0x54, 0x48, 0x5d, 0x5d, 0x97, 0x2c, 0x59, 0x82, 0x9c, 0xac, 0x0f, 0x6d,
- 0x5b, 0xdb, 0x4d, 0x77, 0x77, 0xf7, 0x7e, 0x6d, 0x14, 0x3c, 0xb9, 0x33, 0x15, 0x10, 0xa7, 0x76,
- 0x53, 0xc9, 0x54, 0x60, 0x48, 0xd2, 0x27, 0xb6, 0xf3, 0x33, 0xaf, 0xdf, 0x2e, 0x99, 0x61, 0xb3,
- 0xd9, 0x04, 0x93, 0x1b, 0x37, 0x6e, 0x84, 0x0d, 0x0e, 0xea, 0xcc, 0x09, 0x2f, 0xd4, 0x4f, 0x58,
- 0xb0, 0x70, 0x71, 0x6a, 0x7a, 0x86, 0x25, 0x85, 0xb2, 0x72, 0xe5, 0x4a, 0x7d, 0x33, 0x0c, 0x08,
- 0x08, 0x20, 0x56, 0x1c, 0xdc, 0x79, 0x86, 0x80, 0xf6, 0x86, 0x03, 0x9d, 0xd3, 0x4a, 0xc1, 0xc1,
- 0xc1, 0x3f, 0xb7, 0xb4, 0xe8, 0x96, 0x04, 0xba, 0xc8, 0x00, 0x3c, 0x1e, 0x4f, 0xd7, 0x90, 0xc8,
- 0xc5, 0x65, 0xd9, 0xfb, 0xcb, 0xd7, 0xad, 0x5f, 0x5f, 0x3f, 0x79, 0x32, 0x5f, 0x20, 0xd8, 0xb5,
- 0x6b, 0x57, 0xb7, 0xf0, 0xf0, 0xe6, 0x9b, 0x4b, 0xfa, 0xb5, 0x51, 0x36, 0x36, 0x36, 0x64, 0xe5,
- 0x65, 0xa8, 0x7a, 0x40, 0xac, 0xf6, 0x53, 0xda, 0xd2, 0xd2, 0x32, 0x7d, 0x37, 0x03, 0xb1, 0xa8,
- 0xd9, 0x01, 0xd8, 0xf4, 0xe9, 0xd3, 0x89, 0x1b, 0x74, 0xdb, 0xd9, 0xdb, 0xbf, 0x31, 0x7f, 0xc1,
- 0x86, 0x0f, 0x3f, 0x5a, 0xb9, 0x6a, 0x8d, 0x8f, 0xaf, 0x2f, 0x12, 0x02, 0xec, 0xb7, 0x1b, 0xb1,
- 0x46, 0xc6, 0xc6, 0x0c, 0x2e, 0x57, 0xee, 0xe7, 0xe7, 0x15, 0x14, 0xc4, 0x15, 0x89, 0x2c, 0x28,
- 0x94, 0xd0, 0xd0, 0xd0, 0xf6, 0xb6, 0xdf, 0xc6, 0x7a, 0x1c, 0x05, 0x33, 0x66, 0xcc, 0xd0, 0xef,
- 0x03, 0x85, 0x62, 0x55, 0x56, 0x31, 0x6c, 0xe5, 0xaa, 0xd5, 0x6b, 0xd6, 0x7e, 0x10, 0xaa, 0x52,
- 0xe5, 0xe6, 0xe6, 0xea, 0x47, 0x08, 0x74, 0x60, 0xcb, 0x96, 0x2d, 0xfd, 0xda, 0x28, 0x0e, 0x87,
- 0xa3, 0x3f, 0xbb, 0x45, 0xce, 0xc7, 0x1a, 0x92, 0xf4, 0xcf, 0x2b, 0x28, 0x2b, 0x2b, 0xd3, 0xbf,
- 0x9f, 0x21, 0xe1, 0xb1, 0x18, 0xa3, 0xeb, 0xea, 0xea, 0x88, 0x67, 0xc0, 0x6d, 0x76, 0x4e, 0x2e,
- 0xc0, 0x5a, 0xbf, 0xe1, 0xc3, 0x9a, 0x51, 0xa3, 0x30, 0xac, 0x23, 0xe8, 0x76, 0x23, 0x76, 0x28,
- 0x85, 0x12, 0x1e, 0x13, 0x53, 0x5e, 0x55, 0x35, 0xbc, 0xb6, 0xb6, 0xb0, 0xbc, 0x22, 0x28, 0x5c,
- 0x15, 0x19, 0x1d, 0xad, 0x9f, 0x4e, 0x9b, 0x9b, 0x9b, 0x93, 0x92, 0x92, 0xba, 0x75, 0x83, 0xc1,
- 0x64, 0xd6, 0x4f, 0x98, 0xf8, 0x8f, 0x7f, 0xac, 0x4a, 0xcb, 0xce, 0x41, 0x1a, 0x41, 0x89, 0xa7,
- 0x6f, 0xb3, 0xfb, 0xf6, 0xef, 0xef, 0xd7, 0x46, 0x49, 0x24, 0x2e, 0x15, 0x15, 0xc3, 0xc8, 0x4b,
- 0x14, 0x0d, 0x52, 0x7a, 0xe7, 0x6e, 0x85, 0x97, 0x97, 0x97, 0x2b, 0x14, 0x3e, 0xba, 0x97, 0x58,
- 0x2c, 0x56, 0x5b, 0x5b, 0x7b, 0x47, 0x47, 0x47, 0x6d, 0x6d, 0xad, 0xee, 0x49, 0x07, 0x07, 0xc7,
- 0xf1, 0xf5, 0x13, 0x40, 0xec, 0xe2, 0x25, 0x7f, 0xa3, 0xd3, 0xe9, 0x2b, 0x56, 0xac, 0x20, 0xa0,
- 0xea, 0xe8, 0xb8, 0x4d, 0x10, 0x8b, 0x3c, 0xc0, 0xe1, 0xf3, 0xfd, 0x42, 0x42, 0x62, 0x53, 0x52,
- 0xb2, 0x0a, 0x0b, 0xe3, 0x92, 0x53, 0xa2, 0xe2, 0xe2, 0x5a, 0x5b, 0x5b, 0x75, 0xf8, 0xfd, 0xf4,
- 0xd3, 0x4f, 0xbd, 0xde, 0xe7, 0x53, 0x20, 0x10, 0xc6, 0xc4, 0xc6, 0x71, 0x9c, 0x78, 0x70, 0xc5,
- 0x65, 0xcb, 0x96, 0xe9, 0x13, 0x7b, 0xf8, 0xf0, 0xe1, 0x7e, 0x6d, 0x94, 0xa7, 0xa7, 0x17, 0x12,
- 0x8e, 0xbf, 0xbf, 0x3f, 0xe0, 0xb7, 0xb0, 0xb0, 0x20, 0x3f, 0xa5, 0x35, 0x24, 0xe9, 0x9f, 0x1f,
- 0x5b, 0x51, 0x51, 0x11, 0x10, 0x10, 0xa8, 0x7b, 0x09, 0xbb, 0xfb, 0x4a, 0xf3, 0x15, 0x0c, 0xd0,
- 0x63, 0xc6, 0x8c, 0xd1, 0xed, 0x74, 0x2c, 0x1f, 0x9f, 0x90, 0x00, 0x9b, 0x7d, 0xeb, 0xed, 0x77,
- 0x41, 0xec, 0xbc, 0x79, 0xf3, 0x1e, 0x8c, 0xf5, 0x1a, 0x84, 0x84, 0x5f, 0xd7, 0xd4, 0x7e, 0x4a,
- 0x65, 0x6a, 0x69, 0x65, 0x45, 0xb3, 0xb3, 0xa3, 0xd2, 0x68, 0x81, 0x41, 0x41, 0x17, 0x2f, 0x5c,
- 0xd4, 0xe1, 0x77, 0xe6, 0xcc, 0x19, 0x22, 0x15, 0x77, 0x13, 0xf1, 0x5d, 0xa2, 0xc4, 0xed, 0x3e,
- 0xea, 0xeb, 0xeb, 0xf5, 0x89, 0x6d, 0x6c, 0x6c, 0xec, 0xd7, 0x46, 0xe1, 0xb8, 0x2b, 0x2c, 0x2c,
- 0x24, 0xcf, 0x2b, 0x30, 0x48, 0xe9, 0x5f, 0x83, 0x80, 0x54, 0xa0, 0x54, 0x2a, 0x75, 0x2f, 0x01,
- 0xc8, 0xc3, 0x87, 0x0e, 0x23, 0x46, 0xce, 0x9c, 0x39, 0x53, 0xff, 0x83, 0x27, 0x17, 0x37, 0xb7,
- 0x59, 0xb3, 0x67, 0x4f, 0x7f, 0xe9, 0x65, 0x1a, 0xcd, 0x76, 0xfe, 0xfc, 0xf9, 0x04, 0x54, 0x67,
- 0xcf, 0x9e, 0xf3, 0xf2, 0xf2, 0x34, 0x31, 0x1a, 0x6c, 0x6a, 0x3c, 0xc4, 0x8c, 0x78, 0x98, 0x68,
- 0x1f, 0xa6, 0xc6, 0x83, 0x79, 0x4e, 0x9c, 0x55, 0x2b, 0x57, 0xea, 0xe6, 0x0a, 0xce, 0x9d, 0x3b,
- 0xe7, 0xea, 0xea, 0xda, 0x47, 0x97, 0x8c, 0x8d, 0x8d, 0xab, 0xab, 0xab, 0xf5, 0x89, 0x45, 0x2d,
- 0xd6, 0xaf, 0x8d, 0x52, 0x28, 0x14, 0x3a, 0x62, 0xc9, 0xcb, 0x10, 0x0c, 0x4c, 0x7d, 0x5c, 0xe7,
- 0x85, 0x2a, 0xfb, 0xcd, 0x25, 0x7f, 0x43, 0xa9, 0xbe, 0x7e, 0xfd, 0x7a, 0x3e, 0x9f, 0xaf, 0xbf,
- 0x96, 0x4c, 0x2e, 0x77, 0x76, 0x75, 0xc5, 0x8a, 0x0d, 0x0d, 0x0d, 0x77, 0x7f, 0xd1, 0x68, 0x5a,
- 0x4e, 0xbc, 0xbf, 0x64, 0xea, 0xa8, 0x34, 0xe1, 0xbc, 0x0a, 0xfe, 0xba, 0x71, 0x92, 0x2f, 0xfe,
- 0xe2, 0xba, 0xe3, 0xaf, 0x6e, 0x7b, 0xe7, 0xb8, 0xef, 0x9e, 0x2d, 0xdb, 0x50, 0x2f, 0x99, 0x94,
- 0xc1, 0x9a, 0x3d, 0xa5, 0xe8, 0xe6, 0xe5, 0x63, 0x1d, 0xad, 0x57, 0xee, 0xdf, 0xbf, 0x77, 0xfe,
- 0xfc, 0xf9, 0xdf, 0xdc, 0xb8, 0x37, 0x81, 0xb1, 0x69, 0xd3, 0xa6, 0xe9, 0x57, 0x5e, 0xeb, 0xd7,
- 0xad, 0xef, 0xd7, 0x46, 0xb9, 0xbb, 0x7b, 0x60, 0x5b, 0xd0, 0x0a, 0x83, 0xc1, 0x20, 0x53, 0x81,
- 0x81, 0x89, 0xb8, 0x96, 0x16, 0x76, 0x0a, 0x5f, 0xca, 0xcf, 0x2f, 0x88, 0x8c, 0x8c, 0xd2, 0xbd,
- 0x04, 0xfb, 0x4d, 0x4e, 0x4e, 0x46, 0xe5, 0x85, 0xe4, 0x19, 0x13, 0x13, 0xd3, 0xb3, 0x7e, 0x31,
- 0x35, 0x35, 0xd9, 0xb8, 0xfa, 0x9d, 0x8b, 0x3b, 0x17, 0xfd, 0xb8, 0x2a, 0xa4, 0x79, 0xab, 0xa0,
- 0x75, 0x1f, 0xa7, 0xed, 0x20, 0xab, 0xed, 0x00, 0xab, 0x6d, 0x3f, 0x5b, 0xfb, 0x38, 0xc8, 0xd6,
- 0xfe, 0x7a, 0x90, 0x7d, 0x7d, 0x0f, 0xb7, 0x79, 0x9b, 0xe0, 0xd4, 0x5a, 0xe9, 0x4f, 0x5f, 0x54,
- 0xb5, 0xfe, 0xf8, 0xd1, 0xc5, 0x73, 0xa7, 0x7b, 0x56, 0x5e, 0xfa, 0xa2, 0x50, 0x28, 0x9f, 0x7c,
- 0xf2, 0x89, 0xfe, 0xec, 0xd6, 0x4b, 0x2f, 0xbd, 0xd4, 0xaf, 0x8d, 0x12, 0x8b, 0x25, 0xe5, 0xe5,
- 0xda, 0x9b, 0xc3, 0xa0, 0x78, 0x24, 0x2b, 0x2f, 0x03, 0x93, 0xee, 0x7e, 0x05, 0x72, 0xb9, 0x3c,
- 0x27, 0x27, 0x47, 0xad, 0xee, 0x72, 0xf5, 0x37, 0xa2, 0xc2, 0xb5, 0x6b, 0xd7, 0xe0, 0x72, 0x8b,
- 0x17, 0x2f, 0xb6, 0xb1, 0xb1, 0xe9, 0xba, 0xe2, 0xa0, 0x24, 0x2f, 0x87, 0x03, 0x0d, 0x19, 0xe7,
- 0x3e, 0x12, 0x5f, 0xdf, 0xc5, 0xbb, 0xb1, 0x87, 0xdb, 0xde, 0xc8, 0xd4, 0x7c, 0xe7, 0xa8, 0x7b,
- 0xb4, 0x1e, 0x64, 0x5d, 0xda, 0x24, 0xf8, 0x71, 0x95, 0xe8, 0xe4, 0x1a, 0x51, 0xf3, 0x36, 0xa7,
- 0xf6, 0x43, 0xcc, 0xb6, 0x83, 0xcc, 0xcb, 0x9b, 0x05, 0xe7, 0xf7, 0x4c, 0x7d, 0xa1, 0x24, 0xb6,
- 0x8f, 0x2e, 0x85, 0x86, 0x86, 0xde, 0xb8, 0x71, 0x43, 0x47, 0xec, 0xed, 0xdb, 0x77, 0xfc, 0xfc,
- 0x7b, 0xff, 0x6c, 0xe2, 0x61, 0xc2, 0x90, 0x51, 0x55, 0x55, 0xa5, 0x52, 0xa9, 0x78, 0x3c, 0x1e,
- 0xf8, 0x27, 0x89, 0x35, 0x24, 0x11, 0xc4, 0xd2, 0x68, 0x34, 0x99, 0x4c, 0x96, 0x95, 0x95, 0x15,
- 0x1b, 0xdb, 0x85, 0x25, 0x17, 0x17, 0x97, 0xaf, 0xbe, 0xda, 0x0e, 0x62, 0xaf, 0x5c, 0xb9, 0x82,
- 0x64, 0xa8, 0x7b, 0x9e, 0x6a, 0x61, 0x5c, 0x11, 0xc6, 0xfc, 0xea, 0x15, 0xb7, 0x9f, 0x3e, 0x94,
- 0x1c, 0x59, 0xe2, 0xba, 0xf7, 0x35, 0xb7, 0x43, 0x8b, 0x64, 0x2d, 0x5f, 0xf1, 0x35, 0x47, 0x7e,
- 0x23, 0xf6, 0xc6, 0x3e, 0x4e, 0xd3, 0xdb, 0xb2, 0x4d, 0xa3, 0xbd, 0x37, 0xd5, 0x79, 0xef, 0x7a,
- 0xc5, 0xfd, 0xd2, 0x16, 0x1e, 0xf1, 0x3c, 0x2c, 0x77, 0xd7, 0x7b, 0x92, 0xf2, 0x18, 0x7b, 0x5b,
- 0xcb, 0x5e, 0x4e, 0xff, 0x46, 0xfc, 0xd8, 0xbc, 0x79, 0xb3, 0x7e, 0x88, 0x6d, 0x6d, 0x6d, 0xb3,
- 0xec, 0xcf, 0xa9, 0x86, 0x83, 0x3a, 0x67, 0xe1, 0x6a, 0x6b, 0x6b, 0x31, 0x2e, 0x88, 0x44, 0xce,
- 0xe4, 0xed, 0x8c, 0x0c, 0x4f, 0x0f, 0xee, 0x62, 0xe4, 0x96, 0x99, 0x99, 0xd9, 0xed, 0x9e, 0x30,
- 0x08, 0x0c, 0xe3, 0xc7, 0xd7, 0x13, 0xf3, 0xf9, 0x67, 0xcf, 0x9e, 0xf5, 0xf0, 0xf0, 0xc0, 0x93,
- 0x5c, 0x9a, 0xf9, 0x94, 0x14, 0xde, 0xee, 0xb9, 0xb2, 0x0b, 0x9f, 0x39, 0x9f, 0xd9, 0x20, 0xfe,
- 0xb4, 0xd6, 0xfb, 0x93, 0x5a, 0xef, 0xa3, 0x6f, 0x4b, 0x6f, 0xec, 0x65, 0xff, 0x8a, 0xeb, 0x51,
- 0x86, 0xe6, 0x18, 0xeb, 0xe6, 0x77, 0xac, 0xab, 0x5f, 0x73, 0x8e, 0xbe, 0xe5, 0xbe, 0xf5, 0x05,
- 0xef, 0x2d, 0xcf, 0x7b, 0x9f, 0x5c, 0x23, 0xbe, 0x79, 0x98, 0x41, 0x2c, 0x00, 0x37, 0x3e, 0xbd,
- 0x99, 0xbd, 0x69, 0x01, 0xef, 0xc5, 0x4c, 0x8e, 0xb5, 0xc5, 0xaf, 0x38, 0xe1, 0xd8, 0x09, 0x0a,
- 0x0a, 0xda, 0xb8, 0x71, 0x63, 0x87, 0xde, 0x29, 0x5e, 0x88, 0x04, 0xab, 0x57, 0xaf, 0x31, 0x31,
- 0xe9, 0xdf, 0x0d, 0xc3, 0xf1, 0x56, 0x23, 0x47, 0x8e, 0x4c, 0x4e, 0x4e, 0x91, 0x4a, 0xa5, 0xc4,
- 0x0d, 0x90, 0xff, 0xc0, 0xff, 0x2e, 0x52, 0x4f, 0x5d, 0xc4, 0x97, 0x22, 0x75, 0xde, 0x77, 0x2b,
- 0x23, 0x25, 0x25, 0xa5, 0xdb, 0xf9, 0xa8, 0x88, 0x0a, 0x2d, 0x0f, 0x3e, 0x63, 0x3d, 0xd4, 0xd8,
- 0x58, 0x99, 0x11, 0xd5, 0x30, 0xdc, 0xf5, 0xd0, 0x22, 0xf7, 0x8b, 0x9f, 0x39, 0x23, 0xa6, 0xb6,
- 0x7c, 0xe3, 0xd4, 0x38, 0xcf, 0xe3, 0xd4, 0x07, 0xa2, 0xb6, 0x46, 0xc6, 0x03, 0x5c, 0x99, 0x9a,
- 0xe3, 0x42, 0x4d, 0x93, 0x54, 0xd3, 0x24, 0xd2, 0x7c, 0xc7, 0x6c, 0x3f, 0xc4, 0xb8, 0xb6, 0x8b,
- 0x73, 0xfe, 0x53, 0xe7, 0xab, 0xdf, 0xf0, 0x34, 0x47, 0x18, 0xfa, 0xb1, 0xe1, 0xe6, 0x61, 0xe6,
- 0xd5, 0x3d, 0xac, 0xd3, 0x9b, 0x38, 0x7b, 0x97, 0xb8, 0xac, 0x98, 0x18, 0xfe, 0xc1, 0xb2, 0x79,
- 0xe7, 0xcf, 0xfc, 0xab, 0xe3, 0x56, 0x7b, 0xe7, 0xa9, 0xb2, 0xbf, 0x0a, 0xde, 0xee, 0xed, 0xed,
- 0x3d, 0x80, 0x8d, 0x2a, 0x28, 0x28, 0xc8, 0xce, 0xce, 0x41, 0xd4, 0xb1, 0xb7, 0xb7, 0x27, 0xa7,
- 0x0b, 0x0c, 0x4c, 0x04, 0xb1, 0x52, 0xa9, 0x96, 0x58, 0x08, 0xc3, 0xa8, 0xfe, 0xab, 0xa6, 0xa6,
- 0xa6, 0xb3, 0xe7, 0xcc, 0x41, 0xfd, 0x75, 0xef, 0xce, 0xed, 0xcb, 0x8d, 0x9f, 0xef, 0x7c, 0x45,
- 0x79, 0xfc, 0x6d, 0xf7, 0x4b, 0x9b, 0xc4, 0xad, 0x07, 0xd8, 0xfa, 0xf8, 0xfd, 0xf6, 0x38, 0xca,
- 0xd6, 0x34, 0xb9, 0x6a, 0x9a, 0x64, 0x9a, 0x26, 0x89, 0x96, 0xde, 0x5e, 0x97, 0xe9, 0xf1, 0x80,
- 0xeb, 0x5e, 0xdd, 0xc1, 0x3b, 0xb5, 0x46, 0x7a, 0xfa, 0xb3, 0x51, 0xff, 0xbe, 0xb2, 0x47, 0xd3,
- 0xfc, 0xfd, 0x9d, 0x7f, 0x6b, 0x80, 0x6b, 0xf5, 0xc8, 0x91, 0x03, 0xfb, 0x4a, 0xdc, 0x88, 0x08,
- 0xed, 0x69, 0x12, 0xc4, 0x74, 0x01, 0xf9, 0x3d, 0x5f, 0x06, 0xa6, 0x07, 0xc4, 0x4a, 0xd3, 0xd3,
- 0xd3, 0xe1, 0xa8, 0x3d, 0x6f, 0x29, 0xaf, 0x8e, 0x56, 0xef, 0xdb, 0xf1, 0xf5, 0xb9, 0x1d, 0xeb,
- 0x76, 0xbc, 0xa4, 0x68, 0x7a, 0x57, 0x76, 0x69, 0x93, 0x73, 0xeb, 0x7e, 0x8e, 0x7e, 0x64, 0xed,
- 0x4a, 0x2c, 0x57, 0xd3, 0xe4, 0xd6, 0x49, 0xac, 0x73, 0x5f, 0xc4, 0x1e, 0x25, 0x1e, 0x8c, 0xce,
- 0xc7, 0x83, 0x27, 0x8f, 0x30, 0xda, 0x1b, 0x59, 0x2d, 0x5f, 0x0a, 0x4e, 0xad, 0x0f, 0x6b, 0xde,
- 0xbf, 0x70, 0xe9, 0xbc, 0x17, 0x79, 0x9c, 0x01, 0xde, 0x1a, 0x14, 0x43, 0xc6, 0x88, 0x11, 0x23,
- 0x94, 0x4a, 0x25, 0x97, 0xcb, 0x25, 0x2f, 0x9c, 0x31, 0x30, 0x11, 0xc4, 0xa2, 0xc8, 0x4a, 0x4d,
- 0x4d, 0xcd, 0xcf, 0xcf, 0x87, 0x29, 0x75, 0x5b, 0x80, 0x61, 0x6d, 0xf6, 0xd6, 0xd8, 0xb4, 0x5d,
- 0xb3, 0x82, 0xbe, 0x7f, 0xcf, 0xfd, 0xd2, 0xe7, 0xc0, 0x95, 0xdd, 0x6d, 0x7c, 0xd7, 0x7b, 0x30,
- 0x34, 0xc7, 0x05, 0x9d, 0xb8, 0xba, 0x69, 0x8e, 0xf3, 0xb4, 0xbf, 0x3e, 0x0c, 0xd7, 0x63, 0x08,
- 0x0f, 0x6c, 0xcd, 0x71, 0x8e, 0xe6, 0x38, 0x57, 0xfb, 0x03, 0x7e, 0x3d, 0xaa, 0x67, 0xb9, 0x87,
- 0x98, 0x2d, 0xdb, 0x79, 0x9b, 0x5e, 0xe3, 0x97, 0xa9, 0x1c, 0xac, 0xcc, 0x07, 0x02, 0x1b, 0x92,
- 0x79, 0x5d, 0xdd, 0xe8, 0xe8, 0x68, 0xb5, 0x50, 0x28, 0x24, 0x8b, 0x2f, 0x03, 0x53, 0xe7, 0x1d,
- 0x8f, 0xad, 0xc5, 0x62, 0x71, 0x52, 0x52, 0x52, 0xcf, 0x4b, 0xbd, 0xd8, 0x54, 0xb3, 0xfa, 0x38,
- 0xa7, 0x6d, 0xd3, 0x3d, 0x9a, 0xde, 0x73, 0xbf, 0xbc, 0xc5, 0x59, 0x1b, 0x06, 0x1e, 0xe6, 0xae,
- 0x04, 0x8a, 0x08, 0x03, 0x5a, 0x62, 0xa5, 0x9a, 0x63, 0x9c, 0x87, 0xe3, 0xca, 0xd6, 0xf2, 0x8c,
- 0xa0, 0xdb, 0x24, 0xee, 0x7c, 0x08, 0x34, 0xc7, 0xb8, 0x5a, 0xb3, 0xed, 0xba, 0x64, 0xeb, 0x3e,
- 0xf6, 0x77, 0x2b, 0x9c, 0x5f, 0x48, 0xe4, 0x18, 0x0f, 0xe9, 0x77, 0x0a, 0x45, 0x12, 0xa8, 0xaa,
- 0xaa, 0x42, 0x2c, 0x87, 0xd9, 0x92, 0xdf, 0x3e, 0x63, 0x60, 0x22, 0xbe, 0x1a, 0x09, 0x5e, 0x14,
- 0x17, 0x17, 0x57, 0x58, 0x58, 0x88, 0x1f, 0x74, 0x2f, 0x39, 0x5a, 0x9b, 0x4e, 0x4b, 0x12, 0x6c,
- 0x9f, 0x21, 0xff, 0xd7, 0x7f, 0xd8, 0xbb, 0x0e, 0xb0, 0xa8, 0xae, 0x75, 0x7b, 0xef, 0x7d, 0xc9,
- 0x0d, 0x49, 0x3e, 0x9f, 0x06, 0x91, 0x36, 0x74, 0x18, 0xca, 0x30, 0x0d, 0xa9, 0x62, 0x80, 0xa0,
- 0x51, 0xaa, 0x82, 0x80, 0x28, 0x02, 0x22, 0xd5, 0xf2, 0x14, 0xa3, 0x48, 0x50, 0x6f, 0xf4, 0x25,
- 0x7a, 0xed, 0x5e, 0x11, 0xa3, 0x80, 0x68, 0xac, 0x80, 0x05, 0xa5, 0x4a, 0x91, 0xde, 0x7b, 0x2f,
- 0x43, 0x93, 0x3e, 0x94, 0x81, 0xa1, 0xce, 0x00, 0x22, 0xe8, 0x7b, 0xff, 0xcc, 0xd1, 0x09, 0xc2,
- 0x00, 0x2a, 0x68, 0x84, 0xef, 0xac, 0xef, 0x7c, 0x80, 0x67, 0xce, 0x8c, 0x73, 0xf6, 0x59, 0x67,
- 0xed, 0xf5, 0xff, 0xfb, 0x3f, 0x7b, 0xdf, 0xc0, 0xb7, 0x45, 0xc9, 0xb2, 0xd4, 0x75, 0x7a, 0x47,
- 0x0a, 0x2c, 0x65, 0x59, 0x02, 0x10, 0x58, 0x69, 0xee, 0x96, 0xa0, 0x9c, 0x9f, 0x7d, 0x8c, 0x24,
- 0x3b, 0x34, 0xc3, 0xbd, 0x56, 0x63, 0x20, 0x2d, 0x10, 0x98, 0xdb, 0xf1, 0x70, 0x83, 0x14, 0xf9,
- 0x2a, 0x2c, 0xfe, 0xe6, 0xbd, 0x15, 0x12, 0xec, 0xf7, 0xc6, 0x8d, 0x1b, 0x37, 0x6f, 0xde, 0x4c,
- 0x26, 0x2b, 0xf1, 0xf3, 0xf3, 0xa3, 0xc1, 0xd7, 0x42, 0xc2, 0xb8, 0x75, 0x10, 0x56, 0x81, 0xc6,
- 0x72, 0x9e, 0x04, 0xfc, 0xfa, 0xcb, 0x7f, 0xec, 0xd4, 0x11, 0xc9, 0xf8, 0x8d, 0x5c, 0x79, 0x8d,
- 0x40, 0x7d, 0x22, 0xdf, 0x9b, 0x23, 0x3a, 0x9d, 0xba, 0x22, 0x5b, 0xa5, 0x04, 0x9b, 0x84, 0x72,
- 0x53, 0x0a, 0x2c, 0xa8, 0xeb, 0x6b, 0xba, 0x2a, 0x8e, 0xdb, 0xb0, 0x2c, 0x6f, 0xc0, 0xd1, 0xd8,
- 0x52, 0x81, 0x9e, 0x6c, 0xe1, 0xee, 0x6c, 0x21, 0xf8, 0x83, 0x59, 0x2a, 0x08, 0x51, 0x9e, 0xdd,
- 0xca, 0x89, 0x46, 0x65, 0x46, 0xc0, 0x6d, 0xa8, 0xa1, 0xa1, 0xe1, 0xe4, 0xe4, 0x8c, 0x8e, 0x7c,
- 0x2d, 0x3c, 0x20, 0xc5, 0x30, 0x22, 0x22, 0x22, 0x5a, 0x5a, 0xda, 0x56, 0x56, 0x5b, 0x70, 0x38,
- 0x1c, 0xb2, 0x5f, 0x62, 0xe9, 0xd7, 0x71, 0x07, 0x48, 0x25, 0x5e, 0xc4, 0x86, 0x87, 0x0a, 0x5d,
- 0x29, 0x52, 0xcc, 0xe2, 0x99, 0x02, 0x7f, 0xf0, 0xa2, 0xac, 0x8e, 0x5e, 0x8e, 0x2d, 0x98, 0xdc,
- 0x1c, 0x6c, 0x85, 0x30, 0x9b, 0xd2, 0x1c, 0x75, 0x45, 0x04, 0x56, 0x76, 0x90, 0x22, 0x36, 0x5e,
- 0x60, 0x29, 0x0f, 0xc4, 0x02, 0x1c, 0x88, 0x8f, 0x5d, 0xe5, 0x98, 0x05, 0x2c, 0xf6, 0xd2, 0xe2,
- 0xa5, 0x0f, 0x1b, 0x8a, 0x4f, 0x7f, 0x0a, 0x5c, 0x21, 0x26, 0x26, 0x86, 0x3c, 0x89, 0x20, 0x25,
- 0x25, 0x8d, 0x3e, 0x51, 0xbb, 0x90, 0x80, 0xac, 0x8e, 0x24, 0x24, 0x24, 0x04, 0x72, 0xb4, 0x65,
- 0x8b, 0x35, 0x91, 0xf8, 0xba, 0x78, 0xd5, 0x84, 0xc8, 0x9f, 0xf1, 0x2b, 0x99, 0x72, 0x8d, 0xd0,
- 0x1a, 0x25, 0xd7, 0x97, 0x37, 0x85, 0x66, 0x8e, 0xdf, 0x28, 0xec, 0xee, 0x7e, 0x8a, 0xfe, 0x9d,
- 0x1d, 0x6a, 0x49, 0xb0, 0xf8, 0xfc, 0xa7, 0xb4, 0x22, 0x74, 0xfd, 0x53, 0x5d, 0x1b, 0x63, 0x44,
- 0x73, 0xae, 0x4a, 0x9e, 0xfa, 0x81, 0x78, 0xc9, 0x80, 0x90, 0xeb, 0x2d, 0x31, 0x58, 0x20, 0x08,
- 0x1a, 0xdb, 0x16, 0x85, 0xdd, 0xaa, 0xf1, 0xde, 0x1a, 0x0b, 0xe0, 0xe3, 0x5b, 0x66, 0x67, 0x67,
- 0x67, 0x62, 0x62, 0x0a, 0xf7, 0x20, 0x2f, 0x2f, 0x2f, 0x1a, 0x7c, 0x2d, 0x18, 0x20, 0xc5, 0x30,
- 0x82, 0x82, 0x82, 0xea, 0xea, 0x1a, 0xe0, 0x63, 0x39, 0x53, 0xc8, 0xee, 0x5f, 0x25, 0x9e, 0x73,
- 0x82, 0x54, 0x73, 0x07, 0x4f, 0x8b, 0x97, 0x61, 0x14, 0x09, 0xbf, 0x13, 0x63, 0x41, 0x2d, 0x2b,
- 0xb8, 0xda, 0x57, 0x41, 0xd6, 0x4b, 0x6f, 0xd1, 0x15, 0x94, 0x56, 0x8a, 0x65, 0x1e, 0xde, 0xa4,
- 0x08, 0xaa, 0x1e, 0x89, 0xdd, 0x72, 0x50, 0x3c, 0xa1, 0x43, 0x0a, 0x76, 0xc2, 0x97, 0xdd, 0x92,
- 0x40, 0x76, 0x32, 0x4b, 0x04, 0x9b, 0x1e, 0xcb, 0x93, 0x45, 0x17, 0x7d, 0xc0, 0x79, 0x81, 0x39,
- 0x37, 0x32, 0x32, 0xb2, 0xb1, 0xb1, 0x51, 0x51, 0x51, 0x81, 0xb3, 0x43, 0xad, 0xec, 0x82, 0x01,
- 0xc2, 0x58, 0x01, 0x01, 0x41, 0x35, 0x35, 0x75, 0x5b, 0x5b, 0x56, 0xe9, 0x3e, 0xb2, 0xdf, 0xf5,
- 0x07, 0xb1, 0xdc, 0x93, 0xa4, 0x67, 0xfe, 0x8a, 0x9d, 0x29, 0x52, 0x8c, 0x92, 0x99, 0x2c, 0x01,
- 0x6b, 0x64, 0x16, 0x33, 0x58, 0x31, 0x45, 0x3a, 0x8b, 0x45, 0x57, 0xd9, 0x71, 0x66, 0x80, 0xed,
- 0x1c, 0x38, 0xdc, 0x2e, 0x16, 0xac, 0x09, 0x94, 0xbc, 0x62, 0xa6, 0x78, 0x52, 0x8b, 0x94, 0xea,
- 0x29, 0xd5, 0x19, 0x2f, 0xca, 0x79, 0x23, 0xa3, 0x50, 0xb8, 0xf2, 0x06, 0x9e, 0x33, 0x92, 0xfb,
- 0x5e, 0x80, 0xbe, 0x43, 0x59, 0x59, 0xd9, 0xc5, 0xc5, 0x45, 0x47, 0x47, 0x07, 0x5c, 0x3a, 0x9a,
- 0x95, 0x5d, 0x30, 0x78, 0xc3, 0x58, 0x01, 0x55, 0x55, 0x55, 0xa4, 0xa8, 0x1b, 0xd1, 0x22, 0x43,
- 0x1c, 0x5f, 0xe6, 0x31, 0x96, 0xc6, 0x76, 0x26, 0x4a, 0x33, 0x8a, 0x67, 0xd2, 0x58, 0x64, 0x44,
- 0x60, 0x66, 0xba, 0x22, 0x99, 0x81, 0x3f, 0xa5, 0x75, 0xa0, 0x48, 0xd0, 0xdf, 0x0e, 0xff, 0x1f,
- 0x3d, 0xc2, 0x35, 0x4b, 0x62, 0xf9, 0x1d, 0xa9, 0xfe, 0xc2, 0xb7, 0x38, 0x4f, 0x4f, 0x97, 0xc8,
- 0x3f, 0x87, 0xff, 0xea, 0xcb, 0x0f, 0x0c, 0x9a, 0xa4, 0xa5, 0xa5, 0xed, 0xed, 0xed, 0x8d, 0x8d,
- 0x8d, 0xe5, 0xe4, 0xe4, 0x91, 0x89, 0x0b, 0x50, 0x99, 0x5d, 0x00, 0x78, 0xb3, 0x2e, 0x2d, 0x3f,
- 0x32, 0x1f, 0xbb, 0xae, 0xae, 0x2e, 0x52, 0x3a, 0xc2, 0xbf, 0xe8, 0x9f, 0xd1, 0x6e, 0xa4, 0xb2,
- 0x2b, 0x44, 0xe8, 0x97, 0x7b, 0xb3, 0x44, 0x99, 0x53, 0x8e, 0x1a, 0xbc, 0x61, 0x2c, 0xf7, 0x70,
- 0x4c, 0x94, 0x9d, 0x71, 0x45, 0xb8, 0x2a, 0xc7, 0x0e, 0xb2, 0x5e, 0x7f, 0x0e, 0x3d, 0x53, 0xb8,
- 0x22, 0x50, 0xee, 0xfc, 0x5a, 0xe2, 0x45, 0x3d, 0xc2, 0xd3, 0x23, 0x32, 0x93, 0xdf, 0x3b, 0x50,
- 0x88, 0x69, 0x7c, 0x24, 0xf7, 0xdb, 0x06, 0x71, 0xae, 0xf9, 0xd8, 0x25, 0xbc, 0xbc, 0xfa, 0xeb,
- 0x4d, 0x6c, 0xec, 0xed, 0xe5, 0x89, 0x04, 0x9e, 0x29, 0x46, 0x72, 0x21, 0xe0, 0x32, 0x31, 0x31,
- 0xb1, 0xb6, 0x66, 0x19, 0x03, 0x34, 0xc7, 0xb5, 0x60, 0x80, 0x14, 0x1c, 0x2e, 0x5d, 0xca, 0x47,
- 0x26, 0x93, 0xad, 0xac, 0xac, 0xd6, 0xac, 0x59, 0x83, 0x0c, 0xe5, 0x7f, 0xfd, 0xe5, 0x7f, 0xed,
- 0xff, 0x51, 0x2c, 0xfd, 0x28, 0x39, 0xeb, 0x37, 0x72, 0xd5, 0x4d, 0x79, 0x5a, 0xa2, 0xd8, 0x0c,
- 0xa4, 0xe5, 0x9e, 0x1c, 0x10, 0x63, 0x0d, 0xd7, 0xbe, 0x1e, 0x26, 0x78, 0x2d, 0xad, 0x6c, 0xae,
- 0x4a, 0x04, 0x6e, 0xc7, 0x9d, 0x59, 0x4d, 0xba, 0xeb, 0xac, 0xd0, 0xfc, 0x40, 0x6a, 0xf2, 0x7b,
- 0xc1, 0x39, 0x77, 0xc4, 0x49, 0xe7, 0x7b, 0x2a, 0x11, 0xc4, 0xb8, 0xaf, 0x88, 0x27, 0x2a, 0x2e,
- 0xbe, 0xcb, 0xd5, 0xf5, 0xe7, 0x83, 0x07, 0xdd, 0xdc, 0xdd, 0x7f, 0xd4, 0xd7, 0x17, 0x14, 0x12,
- 0xfa, 0x62, 0xd2, 0x5c, 0xa0, 0x70, 0x6a, 0x9a, 0x9a, 0x2b, 0x1d, 0x1d, 0x9d, 0xe0, 0x36, 0x44,
- 0xe7, 0x39, 0x5c, 0x48, 0x80, 0xee, 0x12, 0xa2, 0x69, 0x3c, 0x1e, 0x6f, 0x61, 0x61, 0x61, 0x60,
- 0x60, 0xb0, 0x68, 0xd1, 0xeb, 0x48, 0x47, 0x5e, 0x78, 0x71, 0xc0, 0xff, 0xa8, 0x64, 0x1c, 0x55,
- 0x4a, 0xfa, 0x59, 0x29, 0xe3, 0x38, 0xb1, 0xee, 0x91, 0x34, 0x73, 0x46, 0x43, 0xfb, 0xa7, 0xea,
- 0xf2, 0xb3, 0xeb, 0xb8, 0x44, 0x59, 0x1b, 0x58, 0x5c, 0xb6, 0xb4, 0x32, 0xf2, 0x84, 0xb3, 0xbc,
- 0xa4, 0xc2, 0xdc, 0xe5, 0xce, 0xea, 0x92, 0xef, 0x3a, 0x29, 0xa4, 0x9c, 0xc7, 0xf6, 0xe5, 0x4f,
- 0xfc, 0x40, 0xb8, 0x2f, 0x06, 0x0a, 0x85, 0x69, 0xf1, 0x52, 0x15, 0x7e, 0xf8, 0x47, 0xc7, 0x2c,
- 0x56, 0xaa, 0x2a, 0x71, 0x15, 0x46, 0x21, 0x0c, 0xc6, 0x69, 0xc7, 0x0e, 0x60, 0x2c, 0x6c, 0x07,
- 0x3c, 0x3c, 0xb6, 0x39, 0x39, 0xad, 0xd0, 0xd6, 0x96, 0x91, 0x95, 0xfd, 0xfa, 0xed, 0xe9, 0xbf,
- 0x24, 0x25, 0x25, 0xed, 0xec, 0xb6, 0x99, 0x9a, 0x9a, 0x22, 0x95, 0x87, 0xe8, 0x94, 0xdd, 0x0b,
- 0x03, 0xac, 0xa5, 0x34, 0xd8, 0xc5, 0x30, 0xeb, 0xd7, 0xaf, 0x07, 0xd7, 0x07, 0x57, 0x16, 0xd9,
- 0x2f, 0x2c, 0xc8, 0x7f, 0x74, 0xbb, 0x79, 0xf4, 0x61, 0xed, 0xcc, 0x5f, 0xc9, 0x09, 0xee, 0x4a,
- 0x31, 0x6e, 0xe4, 0x62, 0x5f, 0xb9, 0xb6, 0x58, 0xf1, 0xf7, 0x90, 0x59, 0x20, 0x2d, 0x9b, 0xab,
- 0x1d, 0x29, 0x62, 0xc9, 0xe7, 0x64, 0x42, 0xf6, 0xc9, 0x9f, 0xd6, 0x26, 0xdd, 0xb4, 0xc1, 0xe7,
- 0xf8, 0x48, 0xb6, 0xc6, 0x4f, 0x1a, 0x41, 0x2b, 0x15, 0x04, 0xc3, 0xdc, 0x93, 0x29, 0x4e, 0x7d,
- 0x22, 0x5b, 0xea, 0x43, 0x8c, 0x3f, 0x6f, 0x79, 0xcb, 0xfb, 0xc2, 0x81, 0x03, 0xee, 0x5c, 0x13,
- 0x53, 0xff, 0xbd, 0x64, 0xc9, 0x7a, 0x73, 0x73, 0x77, 0x0f, 0x0f, 0x84, 0xb4, 0x2c, 0xb1, 0xfd,
- 0xf9, 0x67, 0x97, 0x5d, 0xbb, 0xbe, 0xd7, 0xd5, 0xfd, 0x7a, 0x5c, 0x05, 0x38, 0x0f, 0x0f, 0xcf,
- 0x86, 0x0d, 0x66, 0x48, 0x1d, 0x17, 0xf2, 0x30, 0x38, 0x3a, 0x94, 0xb0, 0x00, 0x00, 0x8c, 0x05,
- 0xcb, 0x87, 0xc5, 0x62, 0x0d, 0x0d, 0x0d, 0xc1, 0xf8, 0xf1, 0xf1, 0xf1, 0x21, 0xfb, 0x45, 0x44,
- 0x45, 0x7f, 0x39, 0x7c, 0xe8, 0xfa, 0xb1, 0xdd, 0xb1, 0xff, 0xfa, 0x3e, 0xfb, 0x38, 0x39, 0xe7,
- 0x24, 0x31, 0x7c, 0xb7, 0x52, 0xac, 0x07, 0xb1, 0xe1, 0xa1, 0x04, 0xb3, 0xe8, 0xdd, 0x18, 0x5b,
- 0x2a, 0x40, 0x8d, 0x10, 0x7b, 0xbc, 0x13, 0x77, 0xd5, 0x4a, 0xf1, 0xf4, 0x2a, 0xe2, 0x1f, 0x66,
- 0x4a, 0x55, 0x8f, 0x44, 0xa9, 0xb1, 0x13, 0xb3, 0xbb, 0xcc, 0x12, 0xc1, 0xfe, 0x7c, 0x0c, 0x3d,
- 0x55, 0xb2, 0xf5, 0x89, 0x6c, 0xf5, 0x2d, 0x7c, 0xce, 0x39, 0xb5, 0xa4, 0x2b, 0xbb, 0x9f, 0x86,
- 0xdc, 0x0b, 0x7e, 0xfc, 0xd8, 0xdb, 0xdb, 0x07, 0x33, 0x69, 0xe6, 0xf0, 0xbf, 0xb1, 0xd7, 0x69,
- 0x52, 0x51, 0x57, 0xdf, 0x77, 0xe0, 0x00, 0x87, 0xb1, 0xc8, 0xb6, 0xfb, 0xa7, 0x9f, 0x88, 0x2a,
- 0x2a, 0xff, 0x18, 0xd7, 0xfb, 0x83, 0x89, 0x75, 0x76, 0x76, 0x5e, 0xbd, 0x7a, 0x35, 0xa7, 0x2a,
- 0x06, 0x95, 0xd9, 0xf9, 0x0e, 0x90, 0x1d, 0x64, 0xf9, 0x6f, 0xb0, 0x04, 0xa6, 0xa6, 0x1b, 0x20,
- 0x48, 0x41, 0xf6, 0x8b, 0x89, 0x8b, 0x1f, 0x3f, 0x71, 0xc2, 0xcf, 0xc7, 0xe7, 0xd6, 0x69, 0x8f,
- 0xa7, 0x07, 0xbf, 0xcf, 0x3b, 0x4d, 0xca, 0x3b, 0x43, 0x8c, 0xf9, 0x89, 0x18, 0xb2, 0x8b, 0x1c,
- 0xba, 0x9b, 0x14, 0xe7, 0x41, 0x1c, 0xc8, 0xc6, 0x0c, 0x14, 0x0a, 0xb2, 0xb6, 0x22, 0x41, 0x06,
- 0x7b, 0x83, 0xbf, 0xfb, 0xd9, 0x1b, 0x35, 0x59, 0x3a, 0x74, 0x1f, 0xd1, 0x6b, 0x1d, 0xde, 0xd3,
- 0x00, 0x7f, 0x7e, 0x0d, 0x29, 0xd8, 0x95, 0x50, 0x1f, 0x26, 0x0e, 0x0e, 0x76, 0x12, 0x57, 0x85,
- 0xfa, 0x72, 0x45, 0xdb, 0xe3, 0xb0, 0x75, 0x0f, 0x70, 0x65, 0x3e, 0xe4, 0xac, 0x93, 0x6a, 0x29,
- 0x17, 0x1c, 0x72, 0x92, 0x22, 0x73, 0x32, 0xd2, 0x32, 0x33, 0x33, 0x13, 0x13, 0x13, 0x83, 0x82,
- 0x1e, 0xd9, 0xda, 0xd9, 0x71, 0xfd, 0xda, 0x18, 0x31, 0x31, 0x5b, 0x7b, 0x7b, 0xf7, 0xb7, 0x19,
- 0x0b, 0xdb, 0x8e, 0x5d, 0xbb, 0xbe, 0x5d, 0xf4, 0x67, 0x0a, 0x17, 0xec, 0xab, 0xa3, 0xa3, 0xa3,
- 0xb9, 0xb9, 0x05, 0x91, 0x48, 0x84, 0x00, 0x13, 0x2d, 0x97, 0x5d, 0x00, 0x40, 0x34, 0x56, 0x56,
- 0x56, 0xd6, 0xc8, 0xc8, 0xc8, 0xcc, 0xcc, 0x9c, 0xc3, 0x58, 0x71, 0x09, 0x89, 0x33, 0x67, 0xcf,
- 0x05, 0x04, 0x04, 0xf8, 0xfb, 0x07, 0x5c, 0xbf, 0x78, 0xfa, 0x89, 0x87, 0x0e, 0x28, 0x6d, 0xb9,
- 0x0f, 0xa1, 0xe1, 0x81, 0x62, 0xea, 0x71, 0x62, 0xf8, 0x4f, 0xc4, 0xd0, 0xbd, 0xc4, 0x20, 0x17,
- 0xb2, 0xbf, 0xed, 0xf2, 0xc0, 0xad, 0xcb, 0x83, 0x5d, 0x94, 0x82, 0x77, 0x2b, 0xf9, 0x59, 0x2a,
- 0x5d, 0x32, 0x22, 0x5f, 0x5e, 0x4f, 0xf2, 0xde, 0x48, 0xf0, 0xdd, 0x84, 0x0b, 0xda, 0xa3, 0x58,
- 0x1d, 0x28, 0xcb, 0xa5, 0xec, 0x90, 0x5d, 0x0a, 0xdb, 0x93, 0x23, 0xd6, 0xfe, 0x54, 0xa6, 0xfa,
- 0x0e, 0xbe, 0xd0, 0x4b, 0x3d, 0xe3, 0x9c, 0x69, 0x56, 0xe0, 0xf9, 0xb2, 0xc2, 0xbc, 0x4a, 0x0a,
- 0xa5, 0xaa, 0xb2, 0x12, 0xb6, 0x8a, 0xf2, 0xf2, 0xc2, 0xc2, 0xc2, 0xe4, 0xe4, 0xe4, 0x33, 0x67,
- 0xce, 0xfe, 0x73, 0x8a, 0x15, 0x16, 0x54, 0x34, 0x34, 0x5c, 0xf7, 0xed, 0x9b, 0xc0, 0x58, 0xb0,
- 0x0a, 0xca, 0x2b, 0x34, 0xc7, 0x1f, 0xa6, 0xa6, 0xa6, 0x06, 0x32, 0xab, 0xad, 0xad, 0x23, 0x21,
- 0x21, 0x81, 0x2c, 0xf2, 0x85, 0xca, 0xec, 0xbc, 0x06, 0x5c, 0x41, 0xf0, 0xae, 0x38, 0x1c, 0x0e,
- 0x04, 0xd6, 0xcc, 0xcc, 0x8c, 0xe3, 0x0a, 0xe0, 0xfa, 0x9e, 0xff, 0xcf, 0x85, 0x90, 0xd0, 0xd0,
- 0x88, 0x88, 0x27, 0xf7, 0xee, 0xdd, 0xbf, 0xee, 0x79, 0x2a, 0xe4, 0x90, 0x41, 0xc6, 0x6f, 0x4a,
- 0x65, 0x97, 0x09, 0xf5, 0x0f, 0x70, 0x9d, 0x09, 0xd2, 0xbd, 0x39, 0xa2, 0x2d, 0xe1, 0xb2, 0xf9,
- 0xbf, 0xcb, 0x27, 0x1c, 0x53, 0x88, 0xfa, 0x97, 0x7c, 0xe4, 0x61, 0xf9, 0xa8, 0xc3, 0xf2, 0x69,
- 0xa7, 0xe4, 0xab, 0x02, 0xb0, 0xf4, 0x2c, 0xee, 0xf5, 0xb1, 0x4c, 0x36, 0x57, 0x7b, 0xb3, 0xc4,
- 0x3a, 0x62, 0x65, 0xea, 0xef, 0xe3, 0x4a, 0x2e, 0x91, 0xb2, 0x3c, 0x4d, 0xb3, 0xfd, 0x4f, 0x94,
- 0xe7, 0xe7, 0xd4, 0xd6, 0xd6, 0x36, 0x34, 0x34, 0x34, 0x35, 0x35, 0x53, 0x5b, 0xa8, 0xd4, 0x96,
- 0x96, 0xc6, 0xc6, 0x46, 0xd8, 0x53, 0x54, 0x54, 0x14, 0x18, 0x78, 0x0f, 0x7a, 0x76, 0xae, 0xdf,
- 0xfc, 0x9b, 0x45, 0x8b, 0xf4, 0x8d, 0x8d, 0xf7, 0xbf, 0xed, 0x0d, 0x80, 0xb1, 0x3a, 0x6b, 0xd6,
- 0x8e, 0x3f, 0x0c, 0xec, 0x2b, 0x30, 0x16, 0xce, 0x8e, 0x40, 0x20, 0x2c, 0x5b, 0xb6, 0x0c, 0x95,
- 0xd9, 0x79, 0x8d, 0x37, 0xf9, 0xd8, 0x65, 0x4a, 0x4a, 0x4a, 0x56, 0x56, 0x56, 0x20, 0xb3, 0x9c,
- 0x5c, 0x01, 0x30, 0xf6, 0x82, 0xe7, 0xc5, 0xa8, 0xa8, 0xe8, 0xa4, 0xa4, 0xe4, 0xe8, 0xe8, 0xe8,
- 0xc0, 0x80, 0x40, 0x20, 0xed, 0xa3, 0xc3, 0x26, 0x69, 0xff, 0xbb, 0xbc, 0xf4, 0x32, 0xb1, 0xfe,
- 0x81, 0x22, 0x2d, 0x51, 0xba, 0x3f, 0x5f, 0xe4, 0x1d, 0xb3, 0x5e, 0x48, 0x12, 0x80, 0xc5, 0xd5,
- 0x38, 0x99, 0xc6, 0x20, 0x05, 0x8a, 0x2f, 0x21, 0xfb, 0x94, 0x5a, 0xf6, 0xf5, 0xfd, 0x45, 0x89,
- 0xe1, 0xb5, 0x35, 0xb5, 0x8d, 0x8d, 0x4d, 0x6d, 0xad, 0x6d, 0x9d, 0x9d, 0x9d, 0x74, 0x3a, 0xbd,
- 0xa7, 0xa7, 0x17, 0xb6, 0x6e, 0x7a, 0x77, 0x47, 0x7b, 0x47, 0x7d, 0x5d, 0x7d, 0x6a, 0x4a, 0xca,
- 0xee, 0xdd, 0x7b, 0xa6, 0x52, 0x45, 0xde, 0x65, 0xcb, 0xf4, 0xd6, 0xad, 0xdb, 0xef, 0xee, 0xce,
- 0x61, 0xec, 0x5e, 0x37, 0x37, 0x99, 0x49, 0xd3, 0xce, 0x68, 0x6a, 0x6a, 0x3a, 0x39, 0x39, 0x69,
- 0x69, 0x69, 0x89, 0x8b, 0x8b, 0xa3, 0x6b, 0x29, 0xce, 0x6b, 0x20, 0xb5, 0x5b, 0x18, 0x0c, 0x46,
- 0x53, 0x73, 0xa5, 0x83, 0x83, 0xa3, 0x8e, 0xce, 0x0f, 0x9c, 0xab, 0x29, 0x21, 0x29, 0xe9, 0x75,
- 0xe9, 0xf7, 0x84, 0xf8, 0x84, 0xdc, 0xdc, 0xdc, 0xf4, 0xf4, 0x8c, 0xc8, 0xc8, 0x28, 0xb0, 0x07,
- 0x7e, 0x9e, 0xa7, 0xef, 0x1f, 0x32, 0x4b, 0x39, 0xaa, 0x5c, 0xfa, 0x3b, 0xb1, 0xe1, 0x01, 0x8e,
- 0x16, 0x2f, 0xd3, 0x9b, 0x2b, 0x32, 0x4d, 0xd6, 0x8b, 0x25, 0xaa, 0xc5, 0x42, 0xfd, 0x05, 0x98,
- 0x9e, 0x4c, 0x71, 0x38, 0xb8, 0xf1, 0xb1, 0x42, 0xe5, 0x75, 0x42, 0xde, 0x19, 0x72, 0xfa, 0x05,
- 0x8b, 0xec, 0x20, 0xaf, 0x8a, 0xe2, 0xfc, 0xfa, 0xfa, 0xfa, 0x56, 0x6a, 0x6b, 0x67, 0x67, 0x57,
- 0x6f, 0x6f, 0x2f, 0x83, 0xc1, 0x18, 0x1a, 0x1e, 0x7e, 0x3e, 0x32, 0x02, 0xdb, 0xf0, 0xf3, 0xe7,
- 0x4c, 0x26, 0x93, 0x4e, 0xef, 0xae, 0xa4, 0x54, 0x42, 0xfc, 0x25, 0xcd, 0x6d, 0x75, 0x3c, 0x04,
- 0x8b, 0x96, 0x2c, 0xd1, 0xd2, 0xd5, 0xdd, 0xbd, 0x77, 0xaf, 0x9b, 0xbb, 0xbb, 0xeb, 0xfe, 0xfd,
- 0x6b, 0xd7, 0xad, 0x9b, 0x3c, 0xa6, 0xc0, 0xcb, 0xcb, 0xeb, 0xe8, 0xe8, 0x64, 0x6a, 0x6a, 0x8a,
- 0xc7, 0x13, 0xd0, 0x45, 0x96, 0xe7, 0x2f, 0x58, 0x6b, 0x0f, 0x7d, 0xf1, 0x05, 0x98, 0x58, 0x08,
- 0xbb, 0xf4, 0xf4, 0xf4, 0x41, 0x85, 0xc8, 0x64, 0x32, 0xe7, 0x55, 0x49, 0x49, 0xc9, 0xdf, 0x2f,
- 0x5f, 0x49, 0x4d, 0x49, 0x2d, 0x2b, 0x2d, 0x2d, 0x29, 0x2e, 0x4e, 0x4d, 0x4b, 0x03, 0x7b, 0x70,
- 0xe7, 0xce, 0x5d, 0x6f, 0xcf, 0xb3, 0x81, 0x1e, 0xe6, 0x40, 0xda, 0x32, 0x50, 0xda, 0xfb, 0xb8,
- 0xb6, 0xa7, 0xd8, 0xee, 0x0c, 0x09, 0x10, 0x5b, 0x60, 0x26, 0xa3, 0x44, 0x88, 0xf5, 0x93, 0xb5,
- 0x09, 0xf7, 0x17, 0x62, 0xfa, 0xf3, 0x44, 0x40, 0x54, 0xe9, 0x29, 0x92, 0xed, 0x31, 0xd8, 0xa6,
- 0xc7, 0x0a, 0xd5, 0xb7, 0xf0, 0x45, 0x17, 0x48, 0x69, 0xbf, 0x6a, 0xa4, 0x5e, 0x75, 0x2b, 0x4c,
- 0x8d, 0xa9, 0xa2, 0x54, 0x80, 0xb4, 0xd2, 0x3a, 0x68, 0x3d, 0x3d, 0x3d, 0x03, 0x4c, 0x26, 0xb0,
- 0xf4, 0xe5, 0xcb, 0x97, 0xaf, 0xc6, 0x01, 0xfe, 0x35, 0x32, 0x32, 0x02, 0x07, 0xa4, 0x24, 0xa7,
- 0x58, 0x5a, 0x5a, 0x4e, 0x73, 0x22, 0x5f, 0xf1, 0xf0, 0x08, 0x8b, 0x8a, 0xe2, 0x94, 0x94, 0x64,
- 0x70, 0xb8, 0x45, 0x8b, 0x17, 0x4f, 0x66, 0x23, 0x9c, 0xe6, 0x1b, 0x99, 0xd5, 0x86, 0xbe, 0x03,
- 0xa9, 0x3f, 0x44, 0x49, 0x3b, 0xef, 0x80, 0x94, 0x1a, 0x42, 0x04, 0x8d, 0x58, 0x02, 0x1b, 0x1b,
- 0x1b, 0x01, 0x01, 0x01, 0xce, 0xab, 0xc0, 0x58, 0x6f, 0x1f, 0xdf, 0xac, 0xac, 0xac, 0xda, 0xda,
- 0x67, 0x80, 0xe2, 0xa2, 0xa2, 0x94, 0x94, 0x94, 0xb0, 0xf0, 0x08, 0x20, 0xed, 0xe5, 0x4b, 0x5e,
- 0xb7, 0x0f, 0x59, 0x25, 0xff, 0xa2, 0x52, 0x78, 0x81, 0x54, 0x73, 0x13, 0xdf, 0xf8, 0x08, 0x47,
- 0x7d, 0x22, 0xd7, 0xf1, 0x54, 0x96, 0x16, 0x27, 0x43, 0x8b, 0x97, 0x86, 0x9f, 0x1d, 0xb1, 0xd8,
- 0xb6, 0x68, 0x2c, 0x35, 0x42, 0x1e, 0x5e, 0xaa, 0xf5, 0xc7, 0x53, 0xfc, 0xf0, 0x70, 0x64, 0xe6,
- 0x31, 0xd5, 0xf8, 0xe3, 0x66, 0xd9, 0x4f, 0x1f, 0x97, 0x15, 0x15, 0x82, 0x13, 0x68, 0x6e, 0x6e,
- 0x01, 0x1b, 0x30, 0xd0, 0xdf, 0x3f, 0x34, 0xfc, 0x7c, 0xec, 0xed, 0x65, 0x3b, 0xc6, 0x03, 0x48,
- 0xdb, 0xd4, 0xd8, 0x78, 0xc5, 0xdb, 0x5b, 0x06, 0x8b, 0x9d, 0xee, 0x64, 0xfe, 0xfe, 0x77, 0x38,
- 0x9d, 0x69, 0x16, 0xb8, 0x07, 0x69, 0xb5, 0xb4, 0xdc, 0x64, 0x6e, 0x6e, 0x01, 0x27, 0x8b, 0x3e,
- 0x63, 0x3b, 0x1f, 0x81, 0x8c, 0xcf, 0x82, 0xda, 0x00, 0x33, 0x57, 0xad, 0x5a, 0xb5, 0x7d, 0xfb,
- 0xf6, 0x35, 0x6b, 0xd6, 0x8e, 0x97, 0x1d, 0x49, 0x29, 0x29, 0xbf, 0x6b, 0xd7, 0x21, 0x60, 0x87,
- 0x38, 0x88, 0xd6, 0xde, 0x01, 0xa4, 0x45, 0x82, 0xf7, 0xb0, 0xd0, 0xb0, 0x3b, 0xb7, 0xef, 0x5c,
- 0xb9, 0x7c, 0xf9, 0xfa, 0x2f, 0x4e, 0xd1, 0x07, 0xbf, 0xcf, 0x3a, 0xae, 0x04, 0x6c, 0x2c, 0xbb,
- 0x42, 0xa8, 0xf0, 0x23, 0x52, 0xae, 0x11, 0x58, 0x9b, 0x1f, 0x9e, 0x72, 0x15, 0x5f, 0x7e, 0x95,
- 0x50, 0x7a, 0x99, 0x50, 0x78, 0x81, 0x98, 0x7d, 0x42, 0x29, 0xf5, 0x98, 0x56, 0xdc, 0x71, 0xd3,
- 0xa4, 0xbb, 0x9e, 0x05, 0xf9, 0xf9, 0x14, 0x0a, 0x05, 0xdc, 0x69, 0x1b, 0xb5, 0x15, 0x9c, 0x2a,
- 0xd8, 0x80, 0x91, 0x17, 0x2f, 0xa6, 0x5a, 0x7a, 0x89, 0x83, 0xa1, 0xc1, 0xa1, 0xe2, 0xa2, 0x62,
- 0x5b, 0x5b, 0x5b, 0x64, 0xb6, 0xf0, 0x0f, 0x03, 0xf0, 0x93, 0x44, 0x22, 0x39, 0x38, 0x38, 0xac,
- 0x5d, 0xbb, 0x56, 0x56, 0x56, 0x6e, 0xc9, 0x12, 0xd6, 0x10, 0x18, 0x4a, 0xda, 0x79, 0x04, 0xc4,
- 0xc1, 0x82, 0xa8, 0x92, 0x48, 0xe4, 0x8d, 0x1b, 0x2d, 0x5d, 0x5c, 0x5c, 0x26, 0x3c, 0x96, 0x28,
- 0x25, 0x25, 0x7d, 0xf3, 0xd6, 0x2d, 0x20, 0x58, 0x57, 0x17, 0x7d, 0x60, 0x60, 0xa0, 0xa3, 0xa3,
- 0xa3, 0xba, 0xba, 0x3a, 0x2f, 0x2f, 0x2f, 0x21, 0x21, 0x31, 0x24, 0x38, 0xf4, 0xce, 0xed, 0xbb,
- 0x57, 0x2e, 0xff, 0xee, 0x7b, 0xdc, 0xfd, 0xde, 0x61, 0x8b, 0x90, 0x7f, 0xe9, 0x47, 0xff, 0xa2,
- 0x1d, 0x7f, 0x64, 0x45, 0xd2, 0x11, 0xb5, 0xa4, 0x23, 0xea, 0xc9, 0x47, 0xd4, 0x92, 0x59, 0x7f,
- 0x68, 0x24, 0x1e, 0xd5, 0x8e, 0x3f, 0xb1, 0x21, 0xf6, 0xbc, 0x4b, 0xdc, 0xcd, 0xb3, 0xe9, 0x89,
- 0x71, 0x85, 0x05, 0x05, 0x95, 0x14, 0x4a, 0x43, 0x7d, 0x7d, 0x7b, 0x5b, 0x7b, 0x4f, 0x77, 0x0f,
- 0x93, 0x39, 0x38, 0x3a, 0x3a, 0x3a, 0x03, 0x59, 0xdf, 0x4c, 0x0e, 0x03, 0xf4, 0x0e, 0x7e, 0x1c,
- 0x8c, 0xc7, 0xe3, 0x67, 0xd3, 0x95, 0x2f, 0x59, 0xb2, 0xc4, 0xc4, 0xc4, 0xd4, 0xda, 0xda, 0x66,
- 0xc5, 0x8a, 0x15, 0x18, 0x8c, 0x08, 0x6b, 0xb5, 0x47, 0x34, 0xd3, 0x35, 0x4f, 0x80, 0xa4, 0x08,
- 0xe0, 0x0a, 0x82, 0x83, 0x05, 0x81, 0xdd, 0xb1, 0x63, 0xc7, 0xe4, 0x09, 0x0c, 0xe1, 0xa5, 0x7b,
- 0xf7, 0xef, 0x83, 0xd5, 0x64, 0x0e, 0xb2, 0xa8, 0x35, 0xc0, 0x60, 0xb4, 0x52, 0xa9, 0x94, 0x0a,
- 0x4a, 0x4e, 0x76, 0x4e, 0x7c, 0x7c, 0x7c, 0x48, 0x48, 0xc8, 0xed, 0xdb, 0x77, 0x7c, 0x7c, 0xaf,
- 0x7a, 0x79, 0x7a, 0x5e, 0x3c, 0x7d, 0xec, 0xf2, 0x31, 0x37, 0xbf, 0x5f, 0xf7, 0xdc, 0xf8, 0x6d,
- 0xf7, 0xed, 0x7f, 0xbb, 0x06, 0x9c, 0xdc, 0x77, 0xff, 0xec, 0x81, 0xc7, 0x9e, 0x87, 0xc2, 0xaf,
- 0x9e, 0x8a, 0x0e, 0xba, 0x9b, 0x94, 0x98, 0x90, 0x9d, 0x9d, 0x0d, 0x22, 0x59, 0x55, 0x59, 0xd9,
- 0xd8, 0xd8, 0x08, 0xcc, 0xef, 0xed, 0xe9, 0x1d, 0x1c, 0x1c, 0x1a, 0x7d, 0x7b, 0xc9, 0xa4, 0xe9,
- 0x01, 0x5f, 0x00, 0x62, 0x34, 0x37, 0xb7, 0x03, 0x40, 0xb3, 0xd9, 0x9c, 0x35, 0x0e, 0x87, 0x73,
- 0x74, 0x74, 0x64, 0x3f, 0x9b, 0xa0, 0x88, 0x66, 0xba, 0xe6, 0x0b, 0x90, 0x09, 0xb1, 0xe1, 0xd2,
- 0x8b, 0x88, 0x88, 0xa8, 0xaa, 0xaa, 0x6e, 0xde, 0x6c, 0xe5, 0xe2, 0xb2, 0x7d, 0xc2, 0xec, 0x85,
- 0x00, 0xb8, 0xb8, 0x71, 0x71, 0xf1, 0x3d, 0xbd, 0xbd, 0x88, 0xc9, 0x1c, 0x1b, 0x1b, 0xeb, 0xed,
- 0xeb, 0x6b, 0x6a, 0x6a, 0x2a, 0x2f, 0x2b, 0x03, 0x73, 0x1b, 0x17, 0x17, 0x17, 0x12, 0x1c, 0xec,
- 0xef, 0x1f, 0xf0, 0xc7, 0x1f, 0x37, 0x7c, 0x7d, 0xaf, 0xfa, 0x78, 0xfb, 0xf8, 0xf8, 0xf8, 0xfa,
- 0xf9, 0xf9, 0xfd, 0x71, 0xe3, 0xe6, 0xdd, 0xbb, 0xfe, 0x0f, 0x1f, 0x06, 0x85, 0x87, 0x85, 0xc7,
- 0xc6, 0xc6, 0xa6, 0xa6, 0xa6, 0xe6, 0xe4, 0xe6, 0x96, 0x96, 0x94, 0x54, 0x57, 0x55, 0xc3, 0x7b,
- 0x69, 0xb4, 0xce, 0xbe, 0xbe, 0xfe, 0xe1, 0x69, 0x8d, 0xeb, 0x94, 0xde, 0x60, 0x68, 0x28, 0x2d,
- 0x3d, 0x9d, 0xf3, 0x94, 0xc4, 0x87, 0x01, 0x28, 0x6a, 0x60, 0x60, 0x08, 0xa4, 0xd5, 0xd6, 0xd6,
- 0x96, 0x92, 0x92, 0x5a, 0xbc, 0x78, 0x31, 0xfa, 0x6c, 0xf8, 0xe7, 0x0f, 0xc4, 0x0f, 0xf0, 0xf3,
- 0xf3, 0x2b, 0x2a, 0xe2, 0x8d, 0x8c, 0x8c, 0x5c, 0x5d, 0xf7, 0x72, 0x9d, 0x37, 0x5b, 0x55, 0x45,
- 0x05, 0xbc, 0x2b, 0x88, 0x1b, 0x87, 0x33, 0x10, 0x04, 0xd1, 0xbb, 0xe8, 0xe0, 0x42, 0x59, 0x2b,
- 0x74, 0x67, 0x66, 0x02, 0x21, 0xc3, 0xc2, 0xc2, 0x81, 0x9c, 0xc0, 0x5b, 0x08, 0xc7, 0x80, 0xa8,
- 0x81, 0x81, 0xf7, 0x82, 0x82, 0x82, 0xc0, 0xe8, 0x46, 0x47, 0x45, 0x27, 0xc4, 0x27, 0x64, 0x64,
- 0x64, 0x80, 0x71, 0x2d, 0x2b, 0x2d, 0x43, 0x16, 0x62, 0xee, 0xa4, 0xd1, 0xfa, 0xfb, 0x07, 0x86,
- 0x9f, 0x8f, 0x70, 0x5d, 0x9a, 0x76, 0x46, 0x80, 0xdd, 0xa5, 0xd3, 0xe9, 0x3e, 0xbe, 0xbe, 0xb3,
- 0x3c, 0xfd, 0xef, 0xbe, 0xfb, 0x0e, 0x2c, 0x90, 0x85, 0xc5, 0xc6, 0xe5, 0xcb, 0x95, 0x85, 0x85,
- 0x85, 0xbf, 0xfd, 0xf6, 0x5b, 0x34, 0x3d, 0xfb, 0x39, 0x03, 0xe8, 0x0a, 0x7e, 0x60, 0xe9, 0xd2,
- 0xa5, 0xb2, 0xb2, 0xb2, 0xab, 0x57, 0xaf, 0x86, 0x6b, 0x07, 0x7e, 0x60, 0xf2, 0x04, 0x80, 0x20,
- 0xb9, 0x40, 0xc1, 0xe1, 0xe1, 0xe1, 0x09, 0x9c, 0x19, 0x1a, 0x1e, 0xa6, 0xd1, 0x68, 0xc0, 0xe4,
- 0x92, 0xe2, 0xe2, 0xcc, 0x0c, 0xd6, 0xd0, 0x7f, 0x4c, 0x74, 0x4c, 0x44, 0x78, 0x44, 0x58, 0x58,
- 0x18, 0xfc, 0x8c, 0x8a, 0x8c, 0x7c, 0x1a, 0xf3, 0x14, 0xb8, 0x9a, 0x92, 0x9a, 0xca, 0x76, 0x02,
- 0x45, 0x60, 0x83, 0xeb, 0x9e, 0xd5, 0x51, 0xa9, 0x54, 0x7a, 0x57, 0x17, 0xd0, 0xf5, 0xc5, 0x3b,
- 0xc4, 0x59, 0xd3, 0x00, 0x94, 0xb9, 0xaa, 0xaa, 0x1a, 0x3a, 0xf4, 0x59, 0x36, 0x02, 0x44, 0x5e,
- 0x7b, 0xf6, 0xb8, 0xc2, 0xdd, 0xaa, 0xa8, 0xa8, 0x08, 0x77, 0x2e, 0xdc, 0xbf, 0x68, 0xe9, 0xec,
- 0xe7, 0x09, 0x4e, 0x7e, 0x40, 0x42, 0x42, 0x62, 0xe5, 0xca, 0x95, 0x10, 0x7d, 0x5b, 0x5b, 0x5b,
- 0xf3, 0xf2, 0x4e, 0x9c, 0x6b, 0x0b, 0xa0, 0xa7, 0xa7, 0x07, 0x72, 0xca, 0x95, 0x33, 0x10, 0xe0,
- 0xb7, 0xb5, 0xb5, 0xd5, 0xd6, 0xd4, 0x02, 0x69, 0xb3, 0xb3, 0x73, 0x80, 0x9c, 0x10, 0x8b, 0x01,
- 0x4b, 0xe1, 0x67, 0x52, 0x52, 0x72, 0x5a, 0x5a, 0x1a, 0x78, 0x06, 0x96, 0xb4, 0xb2, 0x9d, 0x40,
- 0x43, 0x43, 0x63, 0x5b, 0x5b, 0x7b, 0x77, 0x77, 0xf7, 0x00, 0x83, 0x39, 0x61, 0x3d, 0xc4, 0x0f,
- 0x03, 0x18, 0x60, 0x2f, 0xaf, 0x4b, 0xb3, 0x27, 0xd8, 0xba, 0x75, 0xeb, 0x9d, 0x9c, 0x58, 0xc5,
- 0xde, 0x58, 0x2c, 0x96, 0x97, 0x97, 0x17, 0x2d, 0x9d, 0xfd, 0x0c, 0x81, 0x8c, 0x17, 0x40, 0x27,
- 0x08, 0x5d, 0xa1, 0x8a, 0x8a, 0x0a, 0x74, 0x8b, 0xdb, 0xb6, 0xd9, 0x83, 0xd2, 0x4e, 0x0e, 0x3d,
- 0xe4, 0xe5, 0xe5, 0xb3, 0x73, 0x72, 0x5e, 0x4e, 0x61, 0x35, 0x81, 0x78, 0x10, 0x3a, 0xb5, 0xb4,
- 0xb4, 0xd4, 0x54, 0x57, 0x83, 0x3d, 0xc8, 0xcf, 0xcf, 0xcf, 0xca, 0xce, 0xce, 0xcc, 0xcc, 0x04,
- 0xa2, 0xe6, 0xe6, 0xe6, 0x16, 0x14, 0x14, 0x94, 0x16, 0x97, 0x40, 0x80, 0x56, 0x53, 0x53, 0xdb,
- 0xd2, 0xdc, 0x4c, 0x63, 0xc7, 0x59, 0x10, 0xbb, 0xbd, 0x18, 0xe7, 0x2e, 0x66, 0x03, 0xf8, 0x56,
- 0x19, 0xe9, 0x19, 0x38, 0xc5, 0xd9, 0xca, 0x2c, 0x1f, 0x1f, 0x9f, 0x9d, 0x9d, 0xdd, 0x96, 0x2d,
- 0xd6, 0x1a, 0x1a, 0x1a, 0x62, 0x62, 0x62, 0x68, 0x85, 0xcc, 0x67, 0x08, 0xd0, 0x25, 0xe8, 0xfe,
- 0x20, 0x40, 0x86, 0x90, 0xca, 0xd8, 0xd8, 0xd8, 0xc1, 0xc1, 0x51, 0x5d, 0x5d, 0x7d, 0x72, 0x59,
- 0x14, 0x1c, 0xe0, 0x79, 0xf1, 0xe2, 0xf8, 0x65, 0x67, 0x27, 0x00, 0xba, 0x75, 0x08, 0x9d, 0x40,
- 0x36, 0x9b, 0x9b, 0x9b, 0xc1, 0xa0, 0x56, 0x94, 0x57, 0x94, 0x00, 0x8a, 0x8b, 0x4b, 0x8b, 0x8b,
- 0xcb, 0x4b, 0xcb, 0x28, 0x15, 0x15, 0xc0, 0x64, 0xf0, 0xba, 0xd4, 0x16, 0x6a, 0x57, 0x67, 0x17,
- 0xc4, 0x59, 0x10, 0x31, 0xbd, 0x57, 0x5a, 0x60, 0x46, 0x74, 0x76, 0x76, 0xba, 0xb9, 0x1d, 0x98,
- 0x7d, 0x6b, 0x10, 0x08, 0x04, 0x27, 0x27, 0x67, 0x13, 0x13, 0x13, 0x22, 0x91, 0x24, 0x20, 0x20,
- 0x80, 0x7a, 0x83, 0xcf, 0x0a, 0x20, 0xa4, 0x5f, 0x7d, 0xf5, 0x15, 0x74, 0x7f, 0x32, 0x32, 0x32,
- 0x3f, 0xfc, 0xa0, 0x0b, 0x74, 0x35, 0x30, 0x30, 0x98, 0x3c, 0x61, 0x3b, 0x5c, 0xb2, 0xad, 0x5b,
- 0xb7, 0x56, 0x57, 0x57, 0x4f, 0xef, 0x36, 0x41, 0xe8, 0x06, 0x07, 0x07, 0xe9, 0x9d, 0x5d, 0x40,
- 0x4b, 0x20, 0x27, 0xf0, 0x16, 0x0c, 0x00, 0xe0, 0x59, 0xed, 0xb3, 0x86, 0xfa, 0x86, 0x96, 0xe6,
- 0x96, 0x8e, 0xf6, 0xf6, 0xee, 0xae, 0xee, 0x81, 0x01, 0x76, 0x9c, 0xf5, 0xfe, 0x69, 0x81, 0xe9,
- 0x01, 0x01, 0xa0, 0xbf, 0xbf, 0x3f, 0x9c, 0xcb, 0x2c, 0xdb, 0x04, 0x28, 0x0a, 0x4e, 0x1e, 0xbc,
- 0xc1, 0x8f, 0x3f, 0xfe, 0x28, 0x23, 0x83, 0x05, 0xeb, 0x8e, 0x8e, 0x29, 0x7c, 0x26, 0x40, 0xb2,
- 0xaf, 0x8b, 0x17, 0x2f, 0x06, 0xfb, 0xba, 0x62, 0xc5, 0x0a, 0xf0, 0xae, 0x40, 0xcb, 0x09, 0x93,
- 0x1b, 0x23, 0xd0, 0xd6, 0xd1, 0x89, 0x8d, 0x8b, 0x9b, 0x10, 0x70, 0x71, 0xc5, 0xd8, 0xd8, 0xd8,
- 0x00, 0x83, 0x01, 0x5e, 0xb7, 0xbd, 0xad, 0x1d, 0x28, 0xda, 0xd4, 0xd8, 0x04, 0x3e, 0xa1, 0xb5,
- 0xb5, 0x15, 0xb8, 0x0a, 0x41, 0x16, 0xab, 0xac, 0x85, 0xbd, 0x48, 0xe8, 0x6c, 0xe2, 0xac, 0xa9,
- 0xf0, 0xf2, 0xd5, 0xab, 0xf2, 0x8a, 0x8a, 0xe9, 0xd7, 0xac, 0x79, 0x47, 0x40, 0x87, 0xb2, 0x69,
- 0xd3, 0x66, 0x1b, 0x1b, 0x5b, 0xf0, 0x06, 0x22, 0x22, 0xe8, 0x98, 0xc2, 0xe7, 0x02, 0x24, 0xda,
- 0x12, 0x15, 0x15, 0x55, 0x53, 0x53, 0xb3, 0xb4, 0xdc, 0xe4, 0xe2, 0xb2, 0x9d, 0xf3, 0x30, 0xd7,
- 0x78, 0xc8, 0x60, 0xb1, 0xbe, 0xbe, 0xbe, 0x9d, 0x5d, 0x5d, 0xef, 0x48, 0x33, 0xe8, 0xeb, 0xc1,
- 0x3c, 0x00, 0x39, 0xe9, 0x74, 0x20, 0x69, 0x17, 0xab, 0x50, 0xb0, 0xbb, 0xa7, 0xbf, 0xaf, 0x0f,
- 0x76, 0x0e, 0x3f, 0xff, 0x90, 0x8c, 0xeb, 0xbb, 0xa3, 0xbf, 0xbf, 0xff, 0xe0, 0xc1, 0x83, 0x73,
- 0xd2, 0x89, 0x43, 0xa7, 0x63, 0x6f, 0x6f, 0x6f, 0x6e, 0x6e, 0x4e, 0x22, 0x91, 0x04, 0x05, 0x05,
- 0xbf, 0xf9, 0xe6, 0x1b, 0xd4, 0x1b, 0xfc, 0xb5, 0x80, 0xf6, 0x87, 0xde, 0x5f, 0x48, 0x48, 0x88,
- 0x4c, 0x26, 0x9b, 0x98, 0x98, 0x02, 0x5d, 0x39, 0xd3, 0xc1, 0x8d, 0x07, 0x5c, 0xa9, 0x6d, 0xf6,
- 0xf6, 0x15, 0x15, 0x94, 0xf7, 0x8a, 0xe8, 0x47, 0x47, 0x47, 0x07, 0x87, 0x87, 0x07, 0x18, 0x4c,
- 0x30, 0x00, 0x8c, 0x01, 0xc6, 0xe0, 0xd0, 0x10, 0xd8, 0x00, 0x60, 0xf2, 0xc7, 0x90, 0xd6, 0x09,
- 0xff, 0xef, 0xc3, 0xa0, 0x20, 0xc9, 0x71, 0x73, 0x87, 0x7e, 0x30, 0xd8, 0x8b, 0x86, 0x68, 0xba,
- 0xb8, 0xb8, 0xe8, 0xe9, 0xe9, 0x29, 0x28, 0x28, 0xf0, 0xf1, 0x2d, 0xe3, 0xe1, 0x41, 0x1f, 0x60,
- 0xfc, 0xcb, 0x80, 0xd8, 0x57, 0x24, 0xda, 0xd2, 0xd7, 0xd7, 0x47, 0xaa, 0x9a, 0x27, 0x67, 0x5f,
- 0xe1, 0xaa, 0x41, 0x18, 0x12, 0x11, 0xf1, 0x04, 0x02, 0xa5, 0xf7, 0x25, 0x1b, 0xd8, 0xd4, 0x17,
- 0xa3, 0xa3, 0x2f, 0x58, 0x00, 0xaa, 0x7e, 0x74, 0xae, 0x22, 0x80, 0xff, 0xa5, 0xee, 0xd9, 0x33,
- 0x43, 0x43, 0xc3, 0x39, 0x69, 0x25, 0x68, 0x22, 0x88, 0xbf, 0xec, 0xed, 0x1d, 0xb4, 0xb5, 0xb5,
- 0xa5, 0xa5, 0xa5, 0x91, 0xe7, 0xc4, 0x51, 0xd2, 0x7e, 0x7a, 0x70, 0xec, 0xab, 0xb4, 0xb4, 0x0c,
- 0xb2, 0x1e, 0x3d, 0x78, 0x3f, 0xae, 0xf6, 0x15, 0x2e, 0x99, 0x87, 0x87, 0x47, 0x6d, 0x4d, 0xed,
- 0xd8, 0x9c, 0x06, 0xf5, 0x1f, 0x15, 0x20, 0xe9, 0xae, 0x7b, 0xf6, 0xc0, 0x37, 0x9f, 0x93, 0xb6,
- 0xe2, 0xe3, 0xe3, 0x83, 0x68, 0x74, 0xf3, 0xe6, 0xcd, 0x6a, 0x6a, 0xea, 0x48, 0xb2, 0x0b, 0x5d,
- 0x56, 0xe9, 0x13, 0x03, 0xc9, 0xbe, 0x42, 0x28, 0x81, 0xc1, 0x60, 0xd4, 0xd5, 0x35, 0xac, 0xac,
- 0xb6, 0x58, 0x59, 0x59, 0xc1, 0xdf, 0x5c, 0xc3, 0x0a, 0x49, 0x49, 0xc9, 0xa8, 0xa8, 0xa8, 0xf1,
- 0xcb, 0xca, 0x7f, 0xfe, 0x80, 0x9b, 0x2b, 0x3c, 0x3c, 0x5c, 0x6a, 0x2e, 0x8c, 0xc1, 0xdf, 0xde,
- 0x14, 0xc9, 0xec, 0xdc, 0xb9, 0x6b, 0xfd, 0x7a, 0x13, 0xc4, 0xd0, 0xa2, 0xc9, 0xae, 0x4f, 0x09,
- 0xa4, 0xd6, 0x05, 0xac, 0xa9, 0x80, 0x80, 0x00, 0x74, 0xf7, 0xa6, 0xa6, 0xa6, 0x0e, 0x0e, 0x0e,
- 0x8a, 0x8a, 0x78, 0xae, 0x3d, 0x1d, 0x1c, 0xec, 0xee, 0xee, 0x5e, 0x56, 0x5a, 0x36, 0x3a, 0x3a,
- 0x6f, 0x04, 0xf6, 0xff, 0xd8, 0xc6, 0x80, 0x4a, 0xa5, 0x42, 0x8c, 0x3f, 0x57, 0x8d, 0x06, 0x72,
- 0xad, 0xa3, 0xa3, 0xc3, 0xae, 0x13, 0x5e, 0x23, 0x27, 0x27, 0x87, 0x0e, 0x84, 0x7d, 0x4a, 0x20,
- 0x0f, 0x17, 0x40, 0x4f, 0x27, 0x2f, 0x2f, 0x0f, 0xed, 0xef, 0xec, 0xec, 0xc2, 0x99, 0xb4, 0x70,
- 0x32, 0x84, 0x31, 0x98, 0x1b, 0x7f, 0xdc, 0x6c, 0x6d, 0x6d, 0xfd, 0x34, 0x16, 0x74, 0x0e, 0x31,
- 0x32, 0x32, 0xb2, 0xdf, 0xcd, 0x6d, 0x36, 0x65, 0xde, 0x13, 0x00, 0x0e, 0x16, 0xee, 0x6e, 0x3b,
- 0x3b, 0x3b, 0x30, 0xb4, 0xc8, 0xc3, 0x35, 0x68, 0x65, 0xd7, 0x27, 0x00, 0xc7, 0xbe, 0x42, 0x5f,
- 0x0f, 0x44, 0x05, 0xfb, 0x6a, 0x6a, 0xba, 0x61, 0x2a, 0xbf, 0x07, 0x07, 0x5b, 0x6d, 0xd9, 0xf2,
- 0x24, 0x32, 0xaa, 0xbb, 0xbb, 0xfb, 0xaf, 0x26, 0xe0, 0x7b, 0x03, 0x82, 0xbe, 0xdc, 0xdc, 0x3c,
- 0x88, 0x2b, 0xe7, 0xb0, 0xf5, 0xa0, 0xd1, 0xb6, 0x6e, 0xdd, 0x6a, 0x69, 0x69, 0xa9, 0xac, 0xac,
- 0x2c, 0x24, 0x24, 0x84, 0x54, 0x76, 0xa1, 0xa4, 0xfd, 0xa8, 0x40, 0xd2, 0x59, 0xc2, 0xc2, 0xc2,
- 0xcb, 0x97, 0x2b, 0x5b, 0x58, 0x58, 0xb8, 0xb8, 0x6c, 0x9f, 0xe6, 0x9a, 0x82, 0xaa, 0x1c, 0x3c,
- 0x74, 0x38, 0x25, 0x25, 0xb5, 0xa7, 0xa7, 0xe7, 0xaf, 0x26, 0xe0, 0x87, 0xa0, 0xb7, 0xb7, 0x57,
- 0x57, 0x57, 0x77, 0x6e, 0x5b, 0x4f, 0x45, 0x45, 0xc5, 0xc9, 0xc9, 0xc9, 0xd0, 0xd0, 0x50, 0x41,
- 0x41, 0x01, 0x9a, 0x0e, 0x35, 0xb4, 0x1f, 0x15, 0x48, 0x3a, 0x0b, 0xfc, 0x80, 0x82, 0x02, 0x4e,
- 0x5f, 0xdf, 0x60, 0xc7, 0x8e, 0x1d, 0xd3, 0x97, 0x40, 0xaf, 0xd0, 0xd4, 0xf4, 0xf2, 0xf2, 0xca,
- 0xcc, 0xcc, 0xea, 0xea, 0xea, 0x9a, 0xf3, 0xe1, 0xd4, 0x59, 0xe3, 0xd5, 0xcb, 0x97, 0x63, 0x63,
- 0xa3, 0xac, 0xdc, 0x19, 0x18, 0x80, 0xe7, 0x6c, 0xc0, 0x2f, 0xd8, 0xc5, 0x39, 0x62, 0x74, 0x6c,
- 0xec, 0xe6, 0xcd, 0x9b, 0x73, 0xdb, 0x86, 0x40, 0x51, 0x23, 0x23, 0xa3, 0x09, 0xc9, 0x2e, 0x54,
- 0x66, 0x3f, 0x06, 0x38, 0x4f, 0x73, 0x43, 0xd7, 0xa6, 0xa5, 0xa5, 0x05, 0x6d, 0x0e, 0x42, 0x31,
- 0xcd, 0x6a, 0xef, 0x20, 0x1d, 0x66, 0xe6, 0xe6, 0x7e, 0x7e, 0xd7, 0xd2, 0x52, 0xd3, 0x9a, 0x9b,
- 0x9b, 0xc7, 0xaf, 0xbb, 0xfd, 0x57, 0x01, 0xbc, 0x34, 0x50, 0x14, 0xbe, 0xc9, 0xd0, 0xd0, 0x10,
- 0x93, 0xc9, 0xec, 0xef, 0xef, 0xef, 0xeb, 0xe9, 0x05, 0xc7, 0xd2, 0xd5, 0xd9, 0xd5, 0x49, 0xa3,
- 0xd1, 0x3a, 0x3a, 0xba, 0x68, 0x9d, 0xbd, 0x3d, 0x3d, 0xe3, 0xbf, 0x6a, 0x5d, 0x5d, 0x1d, 0xd7,
- 0x94, 0xdd, 0x6c, 0x00, 0x9e, 0xca, 0xd9, 0xd9, 0x79, 0xd3, 0xa6, 0xcd, 0xaa, 0xaa, 0xaa, 0x22,
- 0x22, 0xa2, 0xe8, 0xe8, 0xed, 0xc7, 0x00, 0x92, 0x1f, 0x00, 0x7d, 0x10, 0x14, 0x14, 0x02, 0x5d,
- 0xdd, 0xb8, 0xd1, 0xd2, 0xc6, 0xc6, 0x06, 0xbc, 0xc1, 0x34, 0x6f, 0x01, 0x9f, 0xb6, 0x7d, 0xe7,
- 0xce, 0xab, 0x7e, 0xd7, 0x62, 0xa2, 0x63, 0x28, 0x15, 0x94, 0x9e, 0xee, 0x9e, 0x77, 0xcc, 0xc7,
- 0xbe, 0x62, 0xa9, 0xdf, 0x4b, 0x64, 0x7a, 0x81, 0x09, 0x7c, 0xe3, 0xba, 0x7f, 0x46, 0x96, 0x82,
- 0x94, 0x82, 0x7a, 0x32, 0x18, 0x8c, 0xbe, 0xbe, 0x3e, 0x7a, 0x17, 0x1d, 0x98, 0xd9, 0x4a, 0xa5,
- 0x36, 0x37, 0x37, 0x35, 0x34, 0x34, 0x3c, 0x7b, 0x56, 0x57, 0x53, 0x53, 0x5b, 0x55, 0x55, 0x5d,
- 0x49, 0xa9, 0x64, 0x6d, 0x95, 0x95, 0xb5, 0xb5, 0xcf, 0xda, 0xdb, 0xdb, 0x9f, 0xbf, 0x29, 0x7e,
- 0x00, 0x6e, 0x1f, 0x39, 0x72, 0x64, 0xce, 0xdb, 0x13, 0x8b, 0xc5, 0xba, 0xba, 0xee, 0x5d, 0xb7,
- 0x6e, 0x3d, 0x81, 0x40, 0xe0, 0xe7, 0x17, 0x40, 0x67, 0xf2, 0x9c, 0x73, 0x20, 0xd5, 0xda, 0xd0,
- 0x85, 0xc9, 0xc9, 0xc9, 0xb1, 0x87, 0xb7, 0x9c, 0x21, 0x76, 0x98, 0xa6, 0x91, 0xe1, 0x78, 0x65,
- 0x15, 0x95, 0x5f, 0x8e, 0x1e, 0xf5, 0xf1, 0xf1, 0x0d, 0x09, 0x09, 0xc9, 0x64, 0xcd, 0x4b, 0x50,
- 0xdb, 0xdb, 0xd7, 0xf7, 0x2e, 0x95, 0x81, 0xd0, 0x4b, 0x77, 0xd3, 0xe9, 0xf5, 0xf5, 0xf5, 0x6d,
- 0xad, 0xad, 0x83, 0x83, 0x83, 0xc0, 0x99, 0xa1, 0xc1, 0x41, 0xe0, 0x1b, 0x9d, 0x4e, 0x6f, 0x05,
- 0x50, 0xa9, 0x7d, 0xbd, 0x7d, 0x33, 0x92, 0x9f, 0x4d, 0xef, 0x31, 0x20, 0xde, 0xc0, 0x40, 0x3f,
- 0x7c, 0x5a, 0x47, 0x47, 0x07, 0x95, 0x4a, 0x85, 0xcf, 0xac, 0xae, 0xae, 0xa9, 0xa8, 0xa8, 0x28,
- 0x66, 0x55, 0xde, 0x16, 0x40, 0x60, 0x95, 0x95, 0x95, 0x95, 0x9e, 0x91, 0x91, 0x96, 0x9e, 0x9e,
- 0x9a, 0x9a, 0x9a, 0x02, 0x48, 0x4d, 0xcd, 0xc8, 0xc8, 0x28, 0x29, 0x29, 0x69, 0x6f, 0x6b, 0x43,
- 0x94, 0x16, 0x6e, 0x90, 0xa4, 0xc4, 0xa4, 0xc9, 0x6b, 0x40, 0xcf, 0x12, 0x20, 0xaa, 0x7a, 0x7a,
- 0x7a, 0xce, 0xce, 0x2e, 0xab, 0x57, 0xaf, 0x06, 0xf6, 0x7e, 0xf7, 0x1d, 0x9a, 0xec, 0x9a, 0x4b,
- 0x70, 0x12, 0xb0, 0x20, 0xaa, 0x1a, 0x1a, 0x1a, 0xa0, 0xae, 0x66, 0x66, 0x66, 0x5c, 0xcb, 0x5d,
- 0x38, 0xe0, 0xe1, 0xe1, 0xd1, 0xd3, 0xd7, 0xff, 0xf7, 0xc9, 0x93, 0x3e, 0xde, 0xbe, 0x0f, 0x1e,
- 0x3c, 0x4c, 0x48, 0x48, 0x28, 0x28, 0x28, 0xa8, 0xab, 0xab, 0x87, 0x10, 0xec, 0x5d, 0xe6, 0x10,
- 0x18, 0x1e, 0x1a, 0x06, 0x66, 0x56, 0x52, 0x28, 0x65, 0x65, 0x65, 0xe5, 0x00, 0xf8, 0x55, 0x5a,
- 0x0a, 0x4c, 0x03, 0xca, 0x01, 0x6f, 0x47, 0x67, 0x2e, 0x4e, 0x78, 0xf5, 0xe2, 0xc5, 0x0b, 0x06,
- 0x63, 0xa0, 0x9b, 0xde, 0xdd, 0xde, 0xde, 0xd6, 0xd8, 0xd8, 0x58, 0x53, 0x53, 0x03, 0x1f, 0x53,
- 0x90, 0x5f, 0x90, 0x99, 0x91, 0x99, 0x94, 0x9c, 0x1c, 0x1b, 0x17, 0x1f, 0x1d, 0x1d, 0x13, 0x19,
- 0x19, 0x19, 0x1e, 0xf1, 0x24, 0x2c, 0x3c, 0x02, 0xd9, 0x42, 0xd9, 0x1b, 0x20, 0x2e, 0x2e, 0xbe,
- 0xa8, 0xa8, 0x08, 0x48, 0x8e, 0x3c, 0x86, 0x06, 0x92, 0x0b, 0x9d, 0xf8, 0x9c, 0xb7, 0x2a, 0x84,
- 0x5d, 0xb6, 0xb6, 0x5b, 0xad, 0xad, 0x6d, 0xa0, 0x49, 0xd1, 0x65, 0xc4, 0xe7, 0x16, 0x48, 0x46,
- 0x8b, 0x97, 0x97, 0x17, 0x04, 0xd6, 0xd8, 0xd8, 0xd8, 0xd1, 0xd1, 0x91, 0x6b, 0xb9, 0xcb, 0x78,
- 0x2c, 0xe3, 0xe7, 0xdf, 0xba, 0x6d, 0xdb, 0xa9, 0x33, 0x67, 0x7c, 0x7d, 0x7c, 0x03, 0x03, 0xef,
- 0x81, 0x31, 0x48, 0x4f, 0x4f, 0x07, 0xed, 0x02, 0xca, 0x75, 0xd1, 0xe9, 0x43, 0x43, 0xc3, 0x33,
- 0x16, 0x5f, 0xbd, 0x18, 0x79, 0x01, 0xde, 0xb2, 0xaa, 0xb2, 0xb2, 0xb4, 0xb4, 0x14, 0xe8, 0x5a,
- 0x5d, 0x5d, 0x0d, 0xe1, 0x1b, 0x04, 0x47, 0x33, 0x71, 0xf5, 0xb5, 0xc0, 0x02, 0xab, 0x99, 0x6c,
- 0x59, 0x06, 0xa1, 0xae, 0xaf, 0xab, 0x07, 0x5b, 0x52, 0x54, 0x58, 0x04, 0x72, 0x1a, 0x1f, 0x17,
- 0x1f, 0xf1, 0x24, 0x32, 0x24, 0x34, 0x3c, 0x38, 0x34, 0x2c, 0x38, 0x24, 0x94, 0xeb, 0x16, 0x12,
- 0x1a, 0x16, 0xf3, 0x34, 0x16, 0x48, 0x0b, 0x16, 0x02, 0x3e, 0x0a, 0xc4, 0x36, 0x20, 0x20, 0x40,
- 0x60, 0xd2, 0xc2, 0xe5, 0xb3, 0x04, 0xc8, 0x2c, 0x89, 0x44, 0x86, 0xde, 0x0a, 0xbc, 0x01, 0x1e,
- 0x8f, 0x87, 0x78, 0x16, 0xa2, 0x5a, 0xd4, 0x1b, 0xcc, 0x09, 0x90, 0x8c, 0x16, 0x06, 0x83, 0x61,
- 0x2f, 0xcb, 0x65, 0x0b, 0x2d, 0x3c, 0xe3, 0x80, 0xbb, 0x0c, 0x16, 0xeb, 0xee, 0xe1, 0x71, 0xee,
- 0xfc, 0xff, 0xb3, 0x77, 0x25, 0x40, 0x51, 0x9e, 0x69, 0x5a, 0x9a, 0x86, 0x96, 0xa3, 0x81, 0x06,
- 0x9b, 0xfb, 0xbe, 0x9b, 0x9b, 0x06, 0x69, 0xa0, 0x81, 0x46, 0x04, 0xb9, 0xef, 0x46, 0x6c, 0x4e,
- 0xc5, 0x08, 0x1a, 0x9d, 0x8a, 0x3b, 0x9b, 0xaa, 0x71, 0xa6, 0x6a, 0x92, 0xad, 0x49, 0x25, 0x66,
- 0x36, 0xd9, 0x35, 0xbb, 0xd9, 0x54, 0x8e, 0x29, 0x53, 0x93, 0x6c, 0x92, 0x9d, 0xac, 0x89, 0x07,
- 0x20, 0x28, 0x5e, 0x89, 0x78, 0x83, 0x47, 0x88, 0x8e, 0x20, 0x97, 0x1c, 0xa2, 0x80, 0x0a, 0x8a,
- 0x5c, 0x02, 0xba, 0x4f, 0xf7, 0x47, 0xff, 0x34, 0x88, 0xf4, 0x01, 0x6d, 0xd5, 0x2c, 0xfd, 0xd6,
- 0x5f, 0x14, 0x45, 0xff, 0xdd, 0xfc, 0xfd, 0xfd, 0xcf, 0xff, 0x7c, 0xcf, 0x7b, 0x7c, 0xef, 0xf7,
- 0x6f, 0x5f, 0xfc, 0xe5, 0x2f, 0xdf, 0x7f, 0xff, 0xfd, 0x91, 0x23, 0x47, 0x6b, 0x6b, 0x6b, 0xaf,
- 0x5e, 0xb9, 0xd2, 0xd8, 0xd8, 0xd8, 0xd5, 0xd5, 0x05, 0x4d, 0x3b, 0x3c, 0x3a, 0x26, 0x37, 0x7a,
- 0x00, 0xa8, 0x40, 0x05, 0x80, 0x69, 0xdb, 0x5a, 0x5a, 0x01, 0x3f, 0xe5, 0x72, 0x10, 0x70, 0xb2,
- 0x20, 0x5f, 0xc7, 0xc6, 0x1e, 0x3f, 0x7e, 0x7c, 0xbf, 0xbf, 0x1f, 0x92, 0xa0, 0xb5, 0xa5, 0x55,
- 0x4c, 0xb3, 0x97, 0x2f, 0x63, 0xde, 0x3f, 0x79, 0xf2, 0x27, 0x60, 0xb2, 0xf2, 0x70, 0x15, 0xa8,
- 0xf5, 0xc0, 0xa1, 0xf2, 0x03, 0x2f, 0xa0, 0x97, 0x80, 0x16, 0x04, 0x8f, 0xb7, 0xe3, 0xff, 0x42,
- 0xee, 0x0a, 0x85, 0x42, 0xd9, 0x2f, 0x48, 0xa3, 0xd3, 0x99, 0xa6, 0xa6, 0x46, 0x66, 0x66, 0xb4,
- 0x97, 0xb4, 0x9f, 0x55, 0xc4, 0x30, 0xaa, 0x89, 0x89, 0x49, 0x9b, 0x36, 0x6d, 0x22, 0xfb, 0x82,
- 0x91, 0x7a, 0x03, 0x8d, 0x36, 0x58, 0xa4, 0xc9, 0x12, 0x6c, 0x62, 0x62, 0x62, 0x69, 0x69, 0x99,
- 0x6c, 0xfb, 0xac, 0x79, 0x0d, 0xc3, 0x1e, 0xce, 0xe7, 0xbf, 0xf3, 0xee, 0xbb, 0x9f, 0x7c, 0xf2,
- 0xe9, 0x77, 0xdf, 0x7d, 0x87, 0xc9, 0x17, 0x2a, 0x11, 0x50, 0x01, 0x61, 0x76, 0xdc, 0xee, 0x00,
- 0x73, 0x02, 0x06, 0xe3, 0x4f, 0x27, 0xe4, 0x22, 0x50, 0xb2, 0x82, 0x66, 0xf4, 0xd1, 0xe0, 0xa0,
- 0x82, 0xd4, 0x3a, 0xff, 0x87, 0x4c, 0x89, 0xa1, 0x3b, 0x0e, 0xe8, 0x0e, 0x3e, 0xea, 0xef, 0xeb,
- 0x03, 0x74, 0xdb, 0xdb, 0xda, 0x9b, 0x1a, 0x9b, 0x1a, 0x7e, 0xfd, 0xb5, 0xbe, 0xbe, 0x1e, 0x02,
- 0xfb, 0xa7, 0x9f, 0x7f, 0x3e, 0x76, 0xfc, 0xf8, 0xe1, 0xaa, 0xaa, 0x83, 0x87, 0x2a, 0xe6, 0x82,
- 0xb6, 0xa6, 0xe6, 0x56, 0x73, 0x33, 0x04, 0x06, 0x2e, 0xe3, 0xf3, 0x2f, 0xbe, 0xb0, 0x94, 0xf1,
- 0x34, 0xe9, 0x0c, 0x86, 0xb3, 0xb7, 0x77, 0x4c, 0x62, 0x22, 0x3f, 0x26, 0xc6, 0xce, 0xd5, 0x95,
- 0xa6, 0x6a, 0x65, 0x0b, 0x80, 0xba, 0x71, 0xe3, 0x46, 0x3c, 0x0e, 0x7e, 0x7e, 0x7e, 0x64, 0xe1,
- 0xad, 0x86, 0x66, 0x17, 0x69, 0x84, 0x60, 0x6d, 0x6d, 0x6d, 0x21, 0xb7, 0x8a, 0x8b, 0x8b, 0x63,
- 0x63, 0xe3, 0xe4, 0xbe, 0xc5, 0xd8, 0xd8, 0xf8, 0xb5, 0xd2, 0xd2, 0xcf, 0x3e, 0xfb, 0x7c, 0xff,
- 0x8f, 0xfb, 0x4f, 0x9d, 0x3a, 0x75, 0xa5, 0xfe, 0x72, 0xf3, 0xad, 0x66, 0xf8, 0x32, 0x70, 0xd5,
- 0x47, 0x46, 0x47, 0xc5, 0x05, 0xae, 0x2a, 0xe3, 0x6f, 0x71, 0x06, 0x67, 0x0c, 0xf0, 0x23, 0x85,
- 0xe2, 0x7d, 0x12, 0xf4, 0xde, 0x6e, 0x6f, 0x6f, 0x6c, 0x6a, 0x82, 0x4c, 0xae, 0xaf, 0xab, 0x3f,
- 0x5d, 0x5b, 0x7b, 0xf4, 0xd8, 0xb1, 0x43, 0x15, 0x15, 0x14, 0xe5, 0xe2, 0x17, 0x80, 0xb9, 0xbb,
- 0xab, 0x73, 0x62, 0x62, 0xb2, 0xa3, 0xa3, 0x23, 0x2d, 0x2d, 0x4d, 0x16, 0x4e, 0x5a, 0x34, 0x9a,
- 0xa7, 0x8f, 0x4f, 0x4a, 0x56, 0x96, 0x50, 0x24, 0x12, 0xac, 0x8b, 0xb7, 0xb4, 0xb7, 0xd3, 0x56,
- 0xbe, 0x35, 0x01, 0x08, 0x41, 0x20, 0x88, 0x86, 0x0b, 0x16, 0x13, 0xb3, 0xd6, 0xc5, 0xc5, 0x85,
- 0x2c, 0xae, 0xd1, 0xd0, 0xac, 0xca, 0x46, 0x08, 0x16, 0x9e, 0x32, 0x87, 0xc3, 0x49, 0x4e, 0x4e,
- 0x2e, 0x2b, 0xdb, 0x0a, 0x34, 0xca, 0x7d, 0x17, 0x78, 0xe3, 0x3f, 0x3f, 0xfe, 0xb8, 0xbc, 0xbc,
- 0xe2, 0xe2, 0x85, 0x8b, 0xd0, 0x9f, 0xbd, 0xf7, 0x7a, 0xe1, 0xe9, 0x3f, 0x9d, 0x90, 0x4f, 0xaa,
- 0xaf, 0xcc, 0xc4, 0x42, 0x77, 0x62, 0x62, 0x6c, 0x64, 0xf4, 0xf1, 0x23, 0x68, 0x86, 0xfb, 0x3d,
- 0x3d, 0x3d, 0xed, 0x80, 0x6e, 0x63, 0xe3, 0xd5, 0xab, 0xd7, 0xa0, 0xb7, 0x8f, 0x1c, 0xa9, 0x39,
- 0x78, 0xa8, 0x9c, 0x02, 0x2d, 0xd4, 0xef, 0x7d, 0x89, 0x84, 0xde, 0xfb, 0xe5, 0x97, 0x96, 0x2f,
- 0xa8, 0x59, 0x63, 0x33, 0xb3, 0xc8, 0xd8, 0x58, 0x61, 0x5e, 0x7e, 0xfa, 0xfa, 0xf5, 0xde, 0x5c,
- 0xae, 0x9e, 0xa1, 0xe1, 0x0a, 0x25, 0xf1, 0x66, 0x64, 0x64, 0x04, 0x9a, 0x15, 0x89, 0x44, 0xc1,
- 0xc1, 0xc1, 0xa4, 0x29, 0x87, 0xc6, 0x05, 0x53, 0xd9, 0x08, 0xc1, 0xc2, 0x93, 0x0d, 0x0b, 0x0b,
- 0x2b, 0x2e, 0xde, 0xb8, 0x76, 0xed, 0xda, 0xb9, 0x73, 0x16, 0xee, 0xce, 0xec, 0x1b, 0x84, 0x13,
- 0xd2, 0x33, 0x32, 0xf6, 0xef, 0x3f, 0x50, 0x5f, 0x57, 0x07, 0x27, 0xfd, 0xd1, 0xe0, 0xa3, 0xa7,
- 0x62, 0x01, 0xb0, 0xa4, 0x78, 0x93, 0x1c, 0x52, 0xec, 0x4d, 0x1f, 0x2a, 0x7e, 0xd4, 0xd4, 0x14,
- 0x7c, 0xb4, 0x91, 0x91, 0x91, 0xc1, 0xc1, 0x01, 0xc8, 0x95, 0xce, 0x8e, 0x4e, 0x48, 0x17, 0xa8,
- 0x85, 0x93, 0x27, 0x4f, 0x96, 0x57, 0x54, 0x12, 0xd0, 0xc2, 0x53, 0xbb, 0x76, 0xed, 0xda, 0xd0,
- 0xe3, 0x21, 0x70, 0x32, 0x1e, 0xdb, 0x17, 0xe1, 0xc4, 0xd0, 0xd7, 0x0b, 0x58, 0x1d, 0x92, 0x96,
- 0x93, 0x03, 0xdc, 0x06, 0xf3, 0xf9, 0xcc, 0x17, 0x5a, 0x36, 0xc9, 0x35, 0x48, 0x82, 0xed, 0xdb,
- 0xb7, 0x27, 0x24, 0x24, 0x78, 0x7a, 0x7a, 0x42, 0x80, 0x69, 0x7a, 0x26, 0xab, 0x66, 0x24, 0x06,
- 0x8b, 0x01, 0x24, 0x04, 0x5b, 0x52, 0x52, 0x32, 0x27, 0x65, 0xa0, 0x45, 0xa7, 0xeb, 0xe8, 0xeb,
- 0x6b, 0xcd, 0x76, 0x3d, 0xf0, 0x96, 0x8f, 0x3e, 0xfa, 0x8f, 0xf3, 0xe7, 0xcf, 0x77, 0x75, 0x76,
- 0x0e, 0x3d, 0x79, 0xb2, 0x84, 0x0b, 0xb2, 0x9e, 0xcd, 0xb6, 0x29, 0x99, 0x63, 0x3e, 0x53, 0xee,
- 0x93, 0x27, 0x27, 0x27, 0xc6, 0xc7, 0xc7, 0x40, 0xb9, 0xf7, 0xee, 0xde, 0x6d, 0x6b, 0x6b, 0x6d,
- 0x68, 0x68, 0xf8, 0xf9, 0xf4, 0x69, 0x0a, 0xb4, 0x47, 0x6b, 0x8e, 0xb5, 0xb6, 0xb6, 0x0e, 0x0f,
- 0x0f, 0xef, 0xdb, 0xb7, 0x6f, 0xde, 0x34, 0x9f, 0x2e, 0x83, 0xe1, 0xe6, 0xed, 0x9d, 0x98, 0x91,
- 0x99, 0x25, 0xca, 0x03, 0x68, 0xf5, 0x98, 0xca, 0x6d, 0x29, 0x8e, 0x41, 0xcb, 0xcb, 0xcb, 0x2b,
- 0x2a, 0x2a, 0x22, 0x91, 0x2e, 0x43, 0x43, 0x43, 0x0d, 0xcd, 0xaa, 0x60, 0x54, 0x4f, 0x78, 0x1e,
- 0x8f, 0x07, 0x05, 0x4b, 0xed, 0xd1, 0x39, 0xfd, 0xaa, 0xb6, 0xb6, 0x11, 0x9b, 0xcd, 0xb6, 0xb3,
- 0xa3, 0xcf, 0xbe, 0x83, 0x41, 0xc1, 0xc1, 0x55, 0x55, 0x55, 0x6d, 0x6d, 0x6d, 0x4f, 0x86, 0x87,
- 0x97, 0xb0, 0x96, 0x60, 0x4e, 0x7b, 0x6d, 0x92, 0xfc, 0x9a, 0x9c, 0x92, 0x35, 0xc9, 0xdf, 0xe7,
- 0xc2, 0xf8, 0xb9, 0x52, 0xec, 0x8b, 0x4f, 0x19, 0x1b, 0x1b, 0x1d, 0x78, 0x38, 0xd0, 0x2d, 0x69,
- 0xb4, 0x58, 0x5b, 0x5b, 0x0b, 0x82, 0x05, 0x62, 0x21, 0x12, 0xce, 0x9e, 0x3d, 0xd7, 0xdf, 0x0f,
- 0xd7, 0xad, 0x2f, 0x2d, 0x3d, 0x7d, 0xde, 0xe1, 0xd2, 0xd1, 0xd5, 0xb5, 0x77, 0x75, 0x5d, 0x93,
- 0x98, 0x14, 0x97, 0x92, 0xea, 0x11, 0x10, 0xc0, 0x78, 0x79, 0xfe, 0x7a, 0x5e, 0x73, 0x72, 0x72,
- 0xda, 0xbe, 0x7d, 0x47, 0x72, 0x72, 0x8a, 0x97, 0x97, 0x17, 0x64, 0x98, 0x86, 0x66, 0x95, 0x35,
- 0x52, 0x45, 0x00, 0x47, 0xc0, 0xdd, 0xdd, 0x1d, 0xb3, 0xd5, 0x96, 0x2d, 0x5b, 0x3c, 0x3c, 0x3c,
- 0x66, 0xc6, 0x50, 0x4b, 0xcb, 0xc8, 0xcc, 0xcc, 0xd5, 0xd7, 0xd7, 0xc1, 0xd3, 0x83, 0x36, 0x7b,
- 0xef, 0xcb, 0x3f, 0xfd, 0xe9, 0x9d, 0x1b, 0x37, 0xfe, 0x3e, 0xa4, 0x6c, 0x30, 0x4a, 0x0e, 0x5c,
- 0x9f, 0x4f, 0x93, 0xaa, 0xd8, 0xf1, 0x9f, 0x82, 0xef, 0x26, 0x7b, 0xe0, 0x2f, 0x93, 0xe2, 0x5f,
- 0xf0, 0x93, 0x82, 0xf1, 0xb3, 0x29, 0xd9, 0x26, 0xf2, 0x4a, 0xfe, 0xb7, 0x49, 0xc9, 0x32, 0xde,
- 0x7b, 0xf7, 0x7a, 0x21, 0xc2, 0xcf, 0x9e, 0x3b, 0x07, 0x5f, 0x0c, 0xa0, 0x3d, 0x5c, 0x55, 0x7d,
- 0xfd, 0xfa, 0x75, 0xd0, 0x6c, 0x45, 0x45, 0xc5, 0xcb, 0x06, 0x0d, 0x4f, 0xb1, 0xa5, 0xbd, 0x3d,
- 0x4f, 0x20, 0xe0, 0xf2, 0x23, 0x6c, 0x9d, 0x9d, 0xe9, 0xca, 0x04, 0x10, 0x56, 0xae, 0x5c, 0x99,
- 0x92, 0x92, 0xb2, 0x69, 0xd3, 0xa6, 0xf0, 0xf0, 0x70, 0x92, 0x50, 0xd0, 0x04, 0x0d, 0x94, 0x32,
- 0x52, 0xa6, 0x65, 0x61, 0x61, 0xb9, 0x7a, 0xf5, 0xea, 0xfc, 0xfc, 0x7c, 0xb8, 0xc9, 0xb2, 0x3e,
- 0xd7, 0x4a, 0x43, 0x43, 0xc0, 0x95, 0xcb, 0xe7, 0xdb, 0xb8, 0xb9, 0xca, 0xea, 0x58, 0x8c, 0xf6,
- 0xd1, 0x9a, 0x9a, 0x47, 0x8f, 0x1e, 0x2f, 0xad, 0x93, 0x45, 0xf1, 0x2a, 0x81, 0x2b, 0x64, 0x67,
- 0x5f, 0x7f, 0x7f, 0x47, 0x67, 0xd7, 0xed, 0x0e, 0x08, 0xcf, 0xae, 0x9e, 0xbb, 0xf7, 0x1e, 0x3c,
- 0x1c, 0x10, 0x47, 0x21, 0x26, 0x26, 0x9f, 0x4e, 0x4c, 0x63, 0x78, 0x82, 0xe2, 0x5f, 0x15, 0x71,
- 0x2b, 0x4e, 0x61, 0x3c, 0x7c, 0xf0, 0xa0, 0xb5, 0xb5, 0x0d, 0xfe, 0x63, 0x55, 0x55, 0x35, 0x14,
- 0xc2, 0xe9, 0xda, 0xda, 0xee, 0xae, 0x2e, 0xc8, 0xdd, 0x8c, 0x8c, 0x8c, 0x05, 0x86, 0x8e, 0x65,
- 0x61, 0xe1, 0x19, 0x10, 0xe0, 0xe4, 0xe5, 0x65, 0x6c, 0x61, 0xa1, 0xa5, 0xcc, 0xe4, 0x0e, 0xa0,
- 0x96, 0x96, 0x96, 0xa5, 0xa7, 0xa7, 0x93, 0x84, 0x82, 0x66, 0x01, 0xa3, 0xe2, 0x46, 0x2d, 0xe3,
- 0xc2, 0x54, 0x15, 0x1b, 0x1b, 0x5b, 0x52, 0xb2, 0x19, 0x6e, 0x2c, 0x45, 0xb0, 0xda, 0x3a, 0x3a,
- 0x96, 0x4e, 0x4e, 0x80, 0xab, 0x3f, 0x2f, 0xd4, 0x48, 0xa6, 0x38, 0x16, 0x3e, 0xef, 0xfb, 0xef,
- 0xbf, 0x0f, 0x08, 0x2d, 0x6d, 0x61, 0xe1, 0xb3, 0xe7, 0xd3, 0x04, 0x0b, 0x0c, 0x02, 0x8d, 0xdd,
- 0x77, 0x7a, 0xbe, 0xfe, 0xfa, 0x6b, 0x70, 0x11, 0x24, 0x1f, 0x97, 0xcb, 0x85, 0x4b, 0x98, 0x99,
- 0x99, 0xf9, 0xdb, 0xdf, 0xfe, 0xf3, 0xde, 0xbd, 0x5f, 0xd6, 0xd6, 0x9e, 0x69, 0x69, 0x6d, 0x1b,
- 0x1a, 0x7a, 0x22, 0xe1, 0xde, 0xa9, 0x19, 0x06, 0x9e, 0xb5, 0x69, 0x87, 0x12, 0xff, 0x7a, 0x62,
- 0x62, 0xe2, 0xd1, 0xa3, 0x47, 0xed, 0xed, 0xed, 0xf5, 0x97, 0x2f, 0x9f, 0x3a, 0x75, 0xea, 0xf4,
- 0xe9, 0xd3, 0x37, 0x6e, 0xdc, 0xc0, 0x5f, 0xfe, 0xf6, 0xb7, 0xef, 0xe7, 0xe9, 0x8d, 0x2c, 0xe3,
- 0x84, 0x1a, 0x9b, 0x9b, 0x9b, 0x3b, 0x3a, 0x1a, 0x59, 0x58, 0xd0, 0x94, 0x59, 0xdb, 0x08, 0x5e,
- 0x8d, 0x8f, 0x8f, 0xc7, 0x57, 0x8b, 0x88, 0x88, 0xd0, 0xec, 0x27, 0xae, 0x94, 0x51, 0x59, 0x03,
- 0x3c, 0xec, 0xd9, 0xd9, 0x42, 0x91, 0x28, 0x6f, 0x26, 0xaa, 0xa3, 0xa5, 0x65, 0xc0, 0x62, 0x71,
- 0xb8, 0xdc, 0x90, 0xc8, 0x28, 0x27, 0x0e, 0x87, 0x2e, 0x73, 0x47, 0xe2, 0x13, 0x12, 0x80, 0x99,
- 0xc5, 0x44, 0xfb, 0x5f, 0x86, 0x58, 0xa2, 0x07, 0x00, 0xbf, 0x87, 0x0f, 0x07, 0x76, 0xef, 0xde,
- 0x6d, 0x65, 0x65, 0xc5, 0x98, 0xcf, 0x5c, 0x5d, 0xdd, 0x72, 0x72, 0x72, 0x76, 0xef, 0x7e, 0xbf,
- 0xe6, 0xd8, 0xb1, 0xde, 0xbe, 0xbe, 0xa7, 0x00, 0xdc, 0xb4, 0x72, 0x90, 0x4a, 0x05, 0xe5, 0x51,
- 0x0b, 0x5a, 0x87, 0x3b, 0xd6, 0xd1, 0xd1, 0xf1, 0x4b, 0x43, 0x43, 0x5d, 0x5d, 0x9d, 0xa4, 0x48,
- 0xe6, 0x6e, 0x53, 0xd3, 0xad, 0x94, 0xd4, 0xd4, 0x59, 0x23, 0x46, 0xa3, 0xc1, 0x09, 0xd5, 0x33,
- 0x31, 0x5e, 0xc9, 0x34, 0xd4, 0x96, 0x48, 0x50, 0x1d, 0x03, 0x03, 0x3c, 0xf3, 0xf0, 0x5d, 0xb5,
- 0x94, 0x09, 0xd2, 0x42, 0x83, 0x81, 0x1f, 0x40, 0xb3, 0xde, 0xde, 0xde, 0x9a, 0xd2, 0x59, 0xc5,
- 0x0d, 0x93, 0x11, 0xa9, 0x7b, 0x91, 0x04, 0xb5, 0x8a, 0xe3, 0xe3, 0x13, 0xa8, 0xb6, 0xbd, 0x34,
- 0x1d, 0x1d, 0x1b, 0x17, 0x97, 0x20, 0x3e, 0x3f, 0x30, 0x2c, 0x9c, 0xc5, 0x66, 0x53, 0xe3, 0x69,
- 0x6d, 0x63, 0xb3, 0x67, 0xcf, 0x1e, 0x92, 0x88, 0x5f, 0x62, 0xc4, 0x12, 0x82, 0x95, 0xc8, 0xd4,
- 0x2b, 0x57, 0xaf, 0xc6, 0xc4, 0xc4, 0xcc, 0x0b, 0x57, 0xca, 0x8c, 0x8c, 0x8c, 0xfd, 0xfd, 0xfd,
- 0x71, 0xd9, 0xdf, 0x7c, 0xfb, 0xed, 0x83, 0x07, 0x0f, 0xc5, 0x88, 0x9d, 0x10, 0x1f, 0x93, 0x52,
- 0xa1, 0x4b, 0xca, 0x15, 0x15, 0xbf, 0x4c, 0xbc, 0xe1, 0xc9, 0xd0, 0x93, 0x3b, 0xdd, 0x77, 0x20,
- 0x6b, 0x6f, 0xde, 0xbc, 0xd9, 0xd1, 0x71, 0xfb, 0xe1, 0xc3, 0x87, 0x7b, 0xfe, 0x7d, 0x8f, 0x6c,
- 0x1f, 0x3c, 0xed, 0x95, 0x2b, 0xcd, 0x6c, 0x6d, 0x1d, 0x3c, 0x3c, 0x70, 0x58, 0x38, 0x3a, 0x88,
- 0xdd, 0x2e, 0x1a, 0x0d, 0x70, 0xd5, 0x35, 0x34, 0x64, 0xae, 0x32, 0xd3, 0x56, 0x38, 0x93, 0x0b,
- 0x5e, 0x85, 0x9a, 0xdd, 0xb8, 0x71, 0x23, 0xf4, 0x95, 0x26, 0x36, 0xab, 0xa0, 0x51, 0x95, 0xdb,
- 0xce, 0xce, 0xce, 0xeb, 0xd6, 0xad, 0xdb, 0xbc, 0x79, 0xb3, 0xb7, 0x4c, 0x77, 0x4a, 0x03, 0x53,
- 0x53, 0xef, 0xe0, 0xe0, 0x90, 0x28, 0x81, 0x13, 0xc7, 0x4b, 0x87, 0x5a, 0xb5, 0xa7, 0xa5, 0x95,
- 0x94, 0x94, 0xd4, 0xd0, 0xd0, 0x30, 0xb1, 0x44, 0x5d, 0x31, 0xe7, 0x22, 0x56, 0xe2, 0x4f, 0x01,
- 0x75, 0x70, 0xd8, 0x43, 0x42, 0x42, 0x16, 0x46, 0x2c, 0x31, 0x3d, 0x3d, 0x3d, 0x48, 0x1a, 0x08,
- 0x86, 0x1f, 0x7f, 0xfc, 0xf1, 0xd1, 0xe3, 0x21, 0x02, 0x5a, 0x22, 0x12, 0x66, 0xc4, 0xad, 0x32,
- 0xd7, 0x30, 0x0a, 0xf1, 0xdc, 0xdb, 0x0b, 0xb8, 0x76, 0x75, 0x76, 0x0e, 0x3c, 0x1c, 0x80, 0xb8,
- 0xe5, 0xf3, 0xf9, 0xd4, 0xd7, 0x67, 0x18, 0x1b, 0xdb, 0x7b, 0x7a, 0x40, 0xbe, 0x72, 0x02, 0x02,
- 0x3c, 0x02, 0xfc, 0x6d, 0x5c, 0x5d, 0x75, 0x25, 0x64, 0x6b, 0x6a, 0x6d, 0x6d, 0xef, 0xe1, 0x61,
- 0x66, 0x6b, 0xa3, 0xf8, 0xf8, 0x63, 0xb4, 0x31, 0xe6, 0xc0, 0x2d, 0xf8, 0x56, 0x43, 0xb3, 0x8a,
- 0x18, 0xc6, 0x87, 0x2c, 0x8d, 0xf1, 0xf5, 0xf5, 0xc5, 0x24, 0x5b, 0x54, 0x54, 0x34, 0xb3, 0x9e,
- 0x94, 0x4e, 0xb7, 0x75, 0x71, 0x09, 0x8e, 0x88, 0x08, 0x0c, 0x0d, 0x33, 0x35, 0x67, 0x53, 0xb2,
- 0x0d, 0xd8, 0xf8, 0xef, 0x6f, 0xbe, 0x79, 0xf2, 0x64, 0x78, 0xc9, 0xe1, 0x2a, 0x45, 0xec, 0x33,
- 0x82, 0xd8, 0x86, 0x86, 0x5f, 0xa1, 0xf4, 0x14, 0x41, 0x2c, 0x85, 0x5b, 0x30, 0x95, 0x48, 0x24,
- 0xba, 0x78, 0xf1, 0x22, 0x71, 0xcd, 0x88, 0x48, 0x90, 0x11, 0xb6, 0x4a, 0x5c, 0xc6, 0xf8, 0xf8,
- 0x38, 0x49, 0xef, 0x0e, 0x0e, 0x0c, 0xf6, 0xf5, 0xf5, 0x96, 0x95, 0x96, 0x12, 0x2c, 0x41, 0x12,
- 0x18, 0xb2, 0xd9, 0xae, 0xbe, 0x3e, 0x9c, 0xc0, 0x40, 0x72, 0xb8, 0xfb, 0xfb, 0x99, 0xda, 0x58,
- 0x83, 0x63, 0xcd, 0x6d, 0x6c, 0x7c, 0x82, 0x83, 0xbd, 0x82, 0x57, 0xd3, 0x15, 0x5e, 0x93, 0x0b,
- 0x88, 0x0a, 0x85, 0x42, 0x0c, 0x3b, 0x7c, 0x07, 0xe8, 0x1f, 0x4d, 0xa5, 0x81, 0x5c, 0xa3, 0x0a,
- 0x09, 0x30, 0x31, 0xc1, 0x0b, 0x88, 0x8c, 0x8c, 0x9c, 0x7e, 0x01, 0x0a, 0xd6, 0xd4, 0xd4, 0x8b,
- 0x10, 0xac, 0xa7, 0x27, 0x35, 0xd3, 0x81, 0x90, 0x33, 0x32, 0x33, 0xbb, 0xba, 0xba, 0xd4, 0x94,
- 0x84, 0xa5, 0x10, 0x0b, 0x7a, 0x7c, 0xfc, 0x78, 0x68, 0xd7, 0xae, 0x5d, 0xb8, 0x3c, 0xc5, 0x41,
- 0x4b, 0x0c, 0x3a, 0xfc, 0xed, 0xb7, 0xff, 0xa5, 0xa5, 0xa5, 0x75, 0x5c, 0xdc, 0x0e, 0x69, 0x6a,
- 0xb6, 0x3b, 0xa6, 0x44, 0xcc, 0x76, 0x4a, 0x12, 0xa9, 0x18, 0x7e, 0xf2, 0x64, 0x74, 0x74, 0x74,
- 0xef, 0xde, 0xbd, 0x40, 0xd4, 0x0a, 0x09, 0x62, 0x99, 0x16, 0x16, 0x40, 0x29, 0x85, 0x58, 0x90,
- 0xad, 0x85, 0xa3, 0x23, 0xdc, 0x2e, 0x23, 0x16, 0x0b, 0xce, 0xe1, 0x9a, 0x84, 0x44, 0x67, 0x0e,
- 0x47, 0x71, 0xaa, 0xe4, 0x70, 0x38, 0xa5, 0xa5, 0x65, 0x92, 0x36, 0x9e, 0xae, 0x9a, 0xed, 0x3f,
- 0x16, 0x36, 0x92, 0xe7, 0x32, 0x31, 0x31, 0x71, 0x73, 0x73, 0x4b, 0x48, 0x48, 0x28, 0x2b, 0xdb,
- 0x4a, 0xed, 0xd6, 0x8d, 0xf1, 0xb7, 0x72, 0x76, 0x9e, 0x26, 0x58, 0x99, 0xf2, 0x2d, 0xdc, 0xb5,
- 0xca, 0xca, 0xc3, 0xea, 0x5b, 0xc6, 0x05, 0x44, 0x91, 0xd0, 0x16, 0x90, 0x06, 0xb4, 0x55, 0x56,
- 0x56, 0x62, 0xde, 0x54, 0x16, 0xb1, 0x30, 0xcc, 0x14, 0x09, 0x89, 0x89, 0xc7, 0x4f, 0x9c, 0x78,
- 0x3c, 0xf4, 0x64, 0x5a, 0x21, 0xc8, 0xba, 0x63, 0xca, 0x5c, 0x12, 0x09, 0xfa, 0x36, 0x37, 0x37,
- 0x47, 0x45, 0x09, 0xc8, 0xa8, 0x19, 0xac, 0x5a, 0xe5, 0xe6, 0xe7, 0x4b, 0x21, 0xd6, 0xcd, 0xcf,
- 0x0f, 0x7a, 0x80, 0xf8, 0x5c, 0x5e, 0x01, 0x01, 0xa9, 0xc2, 0x1c, 0x41, 0x5c, 0x9c, 0xbe, 0x02,
- 0x25, 0x19, 0xc4, 0x40, 0xb3, 0xe0, 0x58, 0x4c, 0x70, 0x01, 0x01, 0x01, 0xe6, 0xe6, 0xe6, 0x9a,
- 0x5d, 0x96, 0x16, 0x30, 0xd2, 0x3d, 0xc3, 0xc2, 0xc2, 0x22, 0x30, 0x30, 0x70, 0xfd, 0xfa, 0xdc,
- 0x99, 0x0d, 0x5b, 0x25, 0x04, 0xeb, 0xe1, 0xef, 0x0f, 0x82, 0xf5, 0xf0, 0xf3, 0xa3, 0xcb, 0xb8,
- 0x12, 0x79, 0x79, 0x79, 0x3d, 0x3d, 0x77, 0xd5, 0x57, 0xe5, 0x32, 0x9d, 0x3e, 0x90, 0xe6, 0x0e,
- 0x1e, 0x3c, 0x1c, 0xd8, 0xb1, 0x63, 0x07, 0x98, 0x47, 0x35, 0xd0, 0xc2, 0x29, 0xfb, 0xec, 0xf3,
- 0xcf, 0xef, 0xf5, 0xf6, 0x51, 0xb1, 0x2f, 0xe5, 0x05, 0xc2, 0xb4, 0x0d, 0x0d, 0x0d, 0x65, 0x65,
- 0x65, 0x11, 0xf6, 0xd3, 0x35, 0x30, 0x70, 0xf0, 0x70, 0xe7, 0x04, 0x06, 0x00, 0xae, 0x18, 0x25,
- 0x2b, 0x67, 0x27, 0x5d, 0x69, 0xce, 0x8b, 0x65, 0x6e, 0x9e, 0x96, 0x93, 0x93, 0x99, 0xbb, 0xc1,
- 0x85, 0xc3, 0x51, 0xbc, 0x48, 0x06, 0x58, 0x2d, 0x2b, 0x2b, 0x8b, 0x8a, 0x8a, 0xd2, 0xec, 0x27,
- 0xbe, 0xb0, 0x91, 0xad, 0xb8, 0x30, 0x4a, 0x18, 0x2b, 0x10, 0x2c, 0xe5, 0x73, 0x81, 0x60, 0x2d,
- 0x1c, 0x1c, 0x02, 0x42, 0x43, 0x57, 0x47, 0x46, 0x5a, 0x3a, 0x38, 0x50, 0xe7, 0xeb, 0xe8, 0xea,
- 0x56, 0x57, 0x1f, 0x59, 0x92, 0x5d, 0x33, 0x16, 0x30, 0x02, 0x28, 0x2a, 0xdb, 0x75, 0xf1, 0xd2,
- 0x25, 0xdc, 0x50, 0x15, 0x10, 0x4b, 0x40, 0xeb, 0xe8, 0xe8, 0x08, 0x85, 0xd0, 0xdd, 0xdd, 0x4d,
- 0xc2, 0x08, 0x93, 0x53, 0xaa, 0xf8, 0x62, 0xcf, 0x25, 0xd1, 0xda, 0x0f, 0x3f, 0xfc, 0x90, 0x6c,
- 0x55, 0x46, 0xd3, 0xd6, 0x66, 0x9a, 0x99, 0xd9, 0xb8, 0xba, 0xd8, 0xba, 0xba, 0x82, 0x5d, 0xc5,
- 0x3e, 0xa9, 0x4c, 0x7e, 0x30, 0x36, 0x29, 0x79, 0x43, 0x51, 0x51, 0x58, 0x74, 0x34, 0x63, 0x76,
- 0x7e, 0x70, 0x01, 0xc3, 0x75, 0x6e, 0xdd, 0xba, 0x2d, 0x35, 0x35, 0x95, 0xc3, 0x11, 0x27, 0x6d,
- 0x35, 0xfe, 0xd7, 0xbc, 0x46, 0x85, 0x61, 0xa1, 0xa3, 0x30, 0x56, 0x5b, 0xb6, 0x94, 0x4e, 0xc7,
- 0xc9, 0xb5, 0xb4, 0x56, 0x1a, 0x1b, 0x3b, 0x79, 0x79, 0x05, 0x47, 0x44, 0xfa, 0xf3, 0x78, 0x74,
- 0x99, 0xea, 0x02, 0x51, 0x41, 0x41, 0x6f, 0x6f, 0xaf, 0xba, 0x90, 0x2a, 0xb5, 0x67, 0xcf, 0x67,
- 0xd1, 0xec, 0xe8, 0xd8, 0xf8, 0x57, 0x5f, 0x7d, 0x8d, 0x6b, 0x53, 0x0d, 0xb4, 0x0c, 0x71, 0x2e,
- 0xcf, 0xe2, 0xf5, 0xd7, 0x5f, 0xbf, 0xd3, 0xd3, 0x23, 0x4e, 0x34, 0x4c, 0xa8, 0x28, 0x0f, 0x70,
- 0x6e, 0x5d, 0x5d, 0x1d, 0xbc, 0xce, 0xe9, 0xd1, 0xa3, 0xd1, 0x30, 0xf5, 0xe0, 0xa0, 0xbd, 0x10,
- 0x8f, 0x72, 0xf1, 0xf2, 0x12, 0x15, 0x17, 0xc7, 0xa7, 0xa5, 0xad, 0x92, 0xe8, 0x5e, 0x05, 0x2d,
- 0x21, 0x21, 0x11, 0xda, 0x80, 0xc7, 0xe3, 0xc1, 0x79, 0xd4, 0xd7, 0xd7, 0xd7, 0x08, 0x83, 0x17,
- 0x0d, 0x88, 0x25, 0xce, 0x75, 0x48, 0x48, 0x08, 0xc6, 0x2a, 0x2e, 0x2e, 0x8e, 0x4c, 0x46, 0x90,
- 0xb6, 0x2c, 0x6b, 0x6b, 0x2f, 0x6e, 0x10, 0x24, 0x81, 0x8b, 0x4c, 0xa4, 0x0b, 0x27, 0x7f, 0xf7,
- 0xdd, 0xff, 0x2c, 0xd5, 0x3e, 0x2f, 0x72, 0xe1, 0x21, 0xa6, 0x59, 0x71, 0x1e, 0x41, 0xac, 0x66,
- 0x47, 0x46, 0x46, 0xcb, 0xb6, 0x6e, 0xc5, 0x05, 0xa8, 0x0c, 0x5a, 0x00, 0x3e, 0x3b, 0x3b, 0xfb,
- 0xee, 0xdd, 0x7b, 0x54, 0xb4, 0x56, 0x05, 0x79, 0xf0, 0xe0, 0xc1, 0x03, 0x6f, 0x05, 0x36, 0xa6,
- 0xc1, 0x4c, 0xb4, 0xbe, 0xa0, 0x30, 0x3d, 0x37, 0xd7, 0xc1, 0xd5, 0x55, 0x71, 0x61, 0x80, 0x1b,
- 0xb1, 0x6d, 0xdb, 0xb6, 0xb8, 0xb8, 0x75, 0x94, 0xff, 0xa5, 0xda, 0x6d, 0xfd, 0x7f, 0x6c, 0xc0,
- 0x27, 0xe9, 0x07, 0x0b, 0xac, 0xc2, 0x57, 0xb5, 0xb7, 0xb7, 0x27, 0x33, 0x91, 0x0e, 0x60, 0xec,
- 0xe2, 0xe2, 0x0f, 0x49, 0x10, 0x15, 0x65, 0x20, 0x53, 0xfc, 0xb9, 0x3e, 0x37, 0x57, 0xbc, 0x0d,
- 0x87, 0x1a, 0x71, 0x3a, 0x63, 0x54, 0x31, 0xcc, 0xa4, 0x84, 0x15, 0x01, 0xb1, 0x8e, 0xce, 0x4e,
- 0x3e, 0x9f, 0xaf, 0x32, 0x62, 0x89, 0xa5, 0xa5, 0xa5, 0x35, 0x36, 0x35, 0x8d, 0x3f, 0x9d, 0x50,
- 0x4d, 0xd3, 0x42, 0x0e, 0x09, 0xa2, 0xa3, 0xe5, 0xce, 0xd7, 0xd0, 0x5a, 0x69, 0xc2, 0x9c, 0x9c,
- 0x82, 0x02, 0xaf, 0xc0, 0x00, 0x9a, 0xc2, 0x8a, 0xd4, 0xc0, 0xc0, 0x00, 0x3a, 0x19, 0xae, 0x04,
- 0xf1, 0xbf, 0x18, 0x9a, 0x6a, 0xae, 0xd9, 0x46, 0xc2, 0xb0, 0x6c, 0x36, 0xdb, 0xcf, 0xcf, 0x4f,
- 0x28, 0x14, 0x66, 0x67, 0x0b, 0xa7, 0x37, 0x93, 0xa5, 0xd1, 0xf4, 0x58, 0x2c, 0x07, 0x8e, 0x27,
- 0x10, 0xeb, 0x1b, 0x12, 0x42, 0xcd, 0x4d, 0x10, 0x5a, 0x7f, 0x7e, 0xff, 0xcf, 0x83, 0x83, 0x83,
- 0xea, 0x45, 0xaa, 0x8c, 0x49, 0x4b, 0x0d, 0xa7, 0x08, 0x68, 0x47, 0xc7, 0xc6, 0xf6, 0xed, 0xfb,
- 0xc1, 0xc6, 0xc6, 0x66, 0x31, 0x88, 0x05, 0x2a, 0xd2, 0xd3, 0xd3, 0x2f, 0xd5, 0xd5, 0x8d, 0x8d,
- 0x3f, 0x95, 0x56, 0x7f, 0x29, 0x01, 0x5a, 0x9c, 0xfd, 0xee, 0x7b, 0xef, 0xc9, 0x75, 0x8b, 0x30,
- 0x68, 0xfc, 0x98, 0x98, 0xf5, 0x85, 0x85, 0xdc, 0xf0, 0x70, 0x86, 0xbe, 0xde, 0xc2, 0x27, 0x53,
- 0x86, 0x8f, 0xe5, 0x72, 0x83, 0x36, 0x6f, 0x16, 0x77, 0x3e, 0xb7, 0xb3, 0xb3, 0xd7, 0x54, 0x73,
- 0xcd, 0x31, 0x92, 0x99, 0xb5, 0xb3, 0xb3, 0xe3, 0xf3, 0x23, 0x36, 0x6d, 0x2a, 0xe1, 0xf1, 0x42,
- 0xc9, 0x34, 0xa4, 0x45, 0xa7, 0x1b, 0x59, 0x58, 0x38, 0x7b, 0x7b, 0xfb, 0x04, 0x07, 0xc3, 0xf9,
- 0xa2, 0x1e, 0x73, 0x38, 0xdd, 0x55, 0x55, 0x55, 0xaf, 0xb8, 0x37, 0x11, 0x89, 0x74, 0x91, 0xd8,
- 0x2c, 0x10, 0xd6, 0xd9, 0xd5, 0xb5, 0x71, 0xe3, 0xc6, 0x45, 0xd2, 0x2c, 0x3c, 0xf1, 0x94, 0x94,
- 0x94, 0xda, 0xda, 0x33, 0xe2, 0x4d, 0x16, 0x94, 0x94, 0x07, 0x38, 0xe5, 0xe2, 0xc5, 0x8b, 0x0c,
- 0x79, 0xe5, 0x2e, 0x18, 0x34, 0x47, 0x0f, 0x0f, 0x08, 0x03, 0x5e, 0x54, 0x94, 0xbe, 0x32, 0xc5,
- 0xde, 0xb8, 0x1d, 0xf8, 0x82, 0x49, 0x49, 0x49, 0xee, 0xee, 0x1e, 0x20, 0x10, 0x4d, 0xc4, 0x80,
- 0x32, 0xaa, 0x1a, 0xd6, 0xd3, 0xd3, 0x33, 0x39, 0x39, 0xb9, 0xa0, 0xa0, 0x10, 0x0e, 0x35, 0x79,
- 0x89, 0xc6, 0x60, 0xb0, 0x6c, 0x6c, 0x1c, 0x39, 0x1c, 0x57, 0x5f, 0xdf, 0x95, 0x32, 0x55, 0xca,
- 0xb9, 0xb9, 0x1b, 0x20, 0x09, 0x5e, 0x71, 0xff, 0x37, 0x31, 0x62, 0x65, 0x52, 0x60, 0xc0, 0xd8,
- 0xb7, 0xdf, 0x7e, 0x8b, 0xdb, 0xba, 0x78, 0xd0, 0xc6, 0xc6, 0xc6, 0x9e, 0xae, 0xad, 0x1d, 0x9b,
- 0xd6, 0x07, 0x4a, 0x80, 0xf6, 0x7e, 0x7f, 0xbf, 0x6c, 0xa1, 0xfb, 0xcb, 0xcc, 0x94, 0xcd, 0xce,
- 0x16, 0x89, 0x78, 0xd1, 0x02, 0x03, 0x85, 0xa3, 0xb2, 0x2b, 0x24, 0xe5, 0x70, 0x78, 0x9a, 0x36,
- 0x6c, 0x10, 0x05, 0x06, 0x06, 0x62, 0xfa, 0xd3, 0x44, 0x0c, 0x28, 0x93, 0x86, 0x61, 0x49, 0x35,
- 0x6c, 0x41, 0x7c, 0x7c, 0x3c, 0x75, 0x17, 0xb4, 0xf5, 0xf4, 0x4c, 0xe0, 0x03, 0xb8, 0xb8, 0x98,
- 0xdb, 0xdb, 0x53, 0x25, 0xca, 0x10, 0x66, 0x6f, 0xec, 0xdc, 0xd9, 0xd7, 0xd7, 0xa7, 0x8e, 0x30,
- 0x2c, 0x99, 0xfb, 0x17, 0x78, 0x75, 0x4a, 0x1a, 0xe9, 0x02, 0xcd, 0x5e, 0xbf, 0x7e, 0x23, 0x31,
- 0x31, 0x71, 0x91, 0x88, 0x65, 0x48, 0xe4, 0x01, 0xfc, 0xcd, 0xf3, 0xe7, 0x2f, 0x4c, 0x47, 0x0f,
- 0x14, 0x06, 0xed, 0xc8, 0xc8, 0x88, 0x22, 0x88, 0x35, 0x32, 0x36, 0x4e, 0xca, 0xcc, 0x5c, 0x1d,
- 0x15, 0x69, 0xa8, 0xcc, 0x2a, 0x30, 0xdc, 0x97, 0x90, 0x10, 0x1e, 0xa6, 0xbc, 0x88, 0x88, 0x08,
- 0x5b, 0x5b, 0x5b, 0x4d, 0xc4, 0x80, 0x18, 0xb5, 0x03, 0xb2, 0x8b, 0x8b, 0x0b, 0xb0, 0x5a, 0x58,
- 0x58, 0x38, 0xb3, 0xbf, 0xbc, 0x96, 0x96, 0x38, 0x65, 0xcb, 0x66, 0xb3, 0xac, 0xad, 0x64, 0x63,
- 0x89, 0x4e, 0x4e, 0x4e, 0x7f, 0xfd, 0xeb, 0x57, 0xc3, 0xc3, 0x6a, 0x29, 0x24, 0x90, 0xf4, 0x28,
- 0x78, 0xe9, 0xa6, 0x09, 0xe2, 0xe2, 0xc3, 0x29, 0x29, 0xcd, 0x4a, 0x22, 0x5d, 0x7f, 0x7c, 0xeb,
- 0x2d, 0x5c, 0xfc, 0xe2, 0x41, 0x8b, 0x67, 0x16, 0xdf, 0xab, 0xbe, 0xbe, 0x5e, 0x29, 0xa6, 0x9d,
- 0x98, 0x98, 0x30, 0x59, 0xb0, 0xa1, 0x13, 0x31, 0x43, 0x26, 0x53, 0xb0, 0x6e, 0x5d, 0x60, 0x68,
- 0xa8, 0xa1, 0x32, 0x1c, 0xbb, 0x42, 0xb2, 0x23, 0x18, 0xee, 0x08, 0x84, 0x01, 0x7e, 0xc1, 0xd7,
- 0xd4, 0x08, 0x83, 0x15, 0xd2, 0xf5, 0x5c, 0x24, 0xcf, 0x25, 0x12, 0x89, 0x32, 0x33, 0x33, 0xf5,
- 0x65, 0xc0, 0x09, 0x7f, 0x8c, 0xce, 0x64, 0x02, 0xd0, 0xb2, 0x75, 0x9e, 0x51, 0x02, 0x41, 0x5d,
- 0x7d, 0xfd, 0xa4, 0x1a, 0xb6, 0x36, 0x00, 0x4a, 0xfa, 0xfb, 0xfb, 0x7a, 0xee, 0x74, 0x2f, 0x70,
- 0xce, 0x33, 0x69, 0x93, 0x43, 0x42, 0xb3, 0xfb, 0xf7, 0x1f, 0x70, 0x77, 0x77, 0x5f, 0x3c, 0x62,
- 0x89, 0x41, 0x9f, 0x9f, 0x38, 0x79, 0x72, 0x64, 0x64, 0x54, 0x41, 0x47, 0x0c, 0x67, 0xa4, 0xce,
- 0xae, 0x95, 0x9d, 0xd7, 0xf4, 0x0c, 0x0c, 0x82, 0x22, 0x22, 0xbc, 0xb8, 0x41, 0x06, 0x4a, 0xf6,
- 0xf6, 0x84, 0x54, 0x23, 0x11, 0x03, 0x5f, 0x5f, 0x3f, 0x53, 0x53, 0x4d, 0x2a, 0x61, 0xa6, 0x90,
- 0xc0, 0xd9, 0xd9, 0x39, 0x26, 0x66, 0x6d, 0x49, 0xc9, 0xe6, 0x80, 0x80, 0x80, 0x99, 0x97, 0xb5,
- 0xb5, 0xc5, 0x07, 0xc4, 0x00, 0x0e, 0xe9, 0x40, 0xe1, 0x2d, 0xe9, 0x19, 0x19, 0xb7, 0x6f, 0xdf,
- 0x56, 0x87, 0x24, 0x18, 0x1b, 0x1b, 0x6b, 0x69, 0x69, 0x81, 0x42, 0x5e, 0xa0, 0x80, 0x55, 0x1a,
- 0x34, 0x98, 0x8e, 0xcd, 0x36, 0x37, 0xb7, 0x08, 0x04, 0x82, 0xa5, 0x42, 0x2c, 0x1e, 0xde, 0xb0,
- 0xb0, 0xb0, 0xea, 0xea, 0xea, 0xe1, 0xe1, 0x11, 0x45, 0x40, 0x8b, 0x3f, 0xff, 0xeb, 0x07, 0x1f,
- 0xc8, 0x1d, 0x67, 0x7c, 0x2e, 0x27, 0x90, 0xeb, 0xe2, 0xe3, 0xa3, 0xc7, 0x7c, 0x61, 0xf1, 0xc2,
- 0x82, 0x06, 0x3e, 0x81, 0xc6, 0x06, 0xcd, 0xf2, 0x78, 0x3c, 0x4b, 0x4b, 0x4b, 0x4d, 0x8d, 0x01,
- 0x69, 0x5a, 0x68, 0x65, 0x65, 0x05, 0x82, 0xcd, 0xc9, 0xc1, 0xa3, 0x9c, 0x2b, 0x4b, 0xb0, 0xba,
- 0x4c, 0xa6, 0x21, 0x8b, 0xa5, 0xa3, 0xaf, 0x27, 0xbb, 0x5e, 0xc9, 0xc0, 0xc0, 0xf0, 0xcd, 0x37,
- 0xdf, 0x1c, 0x18, 0x18, 0x58, 0x72, 0xb8, 0x3e, 0x97, 0xec, 0xb0, 0x59, 0x5f, 0x57, 0x77, 0xe5,
- 0xca, 0x15, 0xf9, 0x88, 0x95, 0xc6, 0x66, 0x47, 0x47, 0xc7, 0x8a, 0x8a, 0x8a, 0x54, 0x28, 0xe8,
- 0x7a, 0x99, 0x61, 0x04, 0xa0, 0x1b, 0xab, 0xaa, 0xab, 0xc5, 0x4c, 0xab, 0x80, 0x3c, 0x38, 0x78,
- 0xf0, 0xa0, 0xdc, 0x71, 0xd6, 0x61, 0x30, 0xec, 0x3d, 0xdc, 0xad, 0x5d, 0x5d, 0x74, 0x15, 0x8e,
- 0x6e, 0x51, 0xc6, 0xe5, 0x72, 0x8b, 0x8b, 0x8b, 0xd7, 0xac, 0x59, 0xa3, 0x69, 0x81, 0x48, 0xd2,
- 0xb2, 0x2c, 0x16, 0x0b, 0xb3, 0x6a, 0x5c, 0x5c, 0xdc, 0xb6, 0x6d, 0xaf, 0xe3, 0x17, 0xd9, 0x97,
- 0x59, 0xd6, 0xd6, 0x0e, 0x9e, 0x9e, 0x16, 0x0e, 0x0e, 0xba, 0x32, 0x30, 0x76, 0x74, 0x74, 0xfc,
- 0xdf, 0x7d, 0xfb, 0xd4, 0x14, 0xd7, 0xea, 0xef, 0xef, 0x3f, 0x75, 0xea, 0xa7, 0x33, 0x67, 0xcf,
- 0x2e, 0x7c, 0xda, 0x4c, 0xd1, 0xac, 0x84, 0x66, 0xdf, 0xdb, 0xbd, 0x9b, 0xac, 0x98, 0x5e, 0x42,
- 0xd0, 0x86, 0x86, 0x86, 0x9e, 0x38, 0x71, 0x42, 0x11, 0x4d, 0x7b, 0xfe, 0xfc, 0x79, 0xb9, 0x43,
- 0x4d, 0xa3, 0xd3, 0xe1, 0xc0, 0x62, 0x3c, 0xe9, 0xca, 0xef, 0x6a, 0x07, 0x9f, 0x0b, 0x8f, 0x24,
- 0xa4, 0x2c, 0x1c, 0x0d, 0x22, 0x65, 0x97, 0xad, 0x30, 0xa0, 0x4a, 0x61, 0xe1, 0x90, 0xe6, 0x4b,
- 0x6c, 0xd6, 0xf3, 0xab, 0xad, 0x6d, 0xeb, 0xe6, 0xe6, 0xcf, 0xe3, 0x89, 0xe3, 0x5a, 0x32, 0x51,
- 0x44, 0x3f, 0x3f, 0x3f, 0x70, 0x20, 0x6e, 0xe2, 0x92, 0xc3, 0x15, 0x70, 0xe8, 0xee, 0xea, 0x3e,
- 0x7a, 0xb4, 0xe6, 0xcc, 0x99, 0x33, 0x72, 0xce, 0x9c, 0x59, 0xfc, 0x25, 0x56, 0xb3, 0x15, 0x15,
- 0x15, 0xf8, 0x16, 0x4b, 0x88, 0x58, 0x86, 0x44, 0x1e, 0xe0, 0x9b, 0x5e, 0xba, 0x74, 0x49, 0x6e,
- 0xf4, 0xe0, 0x97, 0x5f, 0x7e, 0x91, 0x3f, 0xd6, 0x50, 0x5f, 0x86, 0x86, 0xba, 0x26, 0x26, 0x4a,
- 0x2d, 0xfb, 0x22, 0x06, 0x56, 0xc1, 0xad, 0xc9, 0xce, 0x16, 0x7a, 0x79, 0x79, 0x99, 0x9a, 0x9a,
- 0x2e, 0xdb, 0x72, 0x59, 0x6a, 0xad, 0x81, 0xb7, 0xb7, 0x77, 0x4a, 0x4a, 0xca, 0xf6, 0xed, 0x3b,
- 0x6c, 0x6c, 0x66, 0x2d, 0xee, 0x80, 0x3f, 0x06, 0xac, 0x46, 0x27, 0x24, 0xf8, 0x05, 0x07, 0x53,
- 0x0b, 0x64, 0x24, 0x9d, 0xcd, 0x04, 0x3d, 0x3d, 0x3d, 0xea, 0x10, 0xb1, 0xf0, 0xbb, 0x9b, 0x9a,
- 0x6e, 0x55, 0x56, 0x56, 0x5d, 0xb8, 0x70, 0x41, 0x0e, 0x62, 0xa5, 0x52, 0x76, 0x52, 0xbc, 0x71,
- 0xed, 0x64, 0x4b, 0x6b, 0x9b, 0x9b, 0x9b, 0xdb, 0xd2, 0x22, 0x96, 0x98, 0x83, 0x83, 0xc3, 0xd9,
- 0x73, 0xe7, 0x16, 0x4e, 0x2e, 0xdc, 0xb8, 0xf1, 0x77, 0xf9, 0xa3, 0x2d, 0x09, 0x20, 0xae, 0x00,
- 0x5c, 0x55, 0x02, 0x5b, 0x4a, 0x4a, 0x6a, 0x5e, 0x5e, 0x3e, 0x94, 0xdb, 0x72, 0x4e, 0xd7, 0x82,
- 0x4e, 0x99, 0x4c, 0x26, 0xee, 0x88, 0x64, 0x5b, 0xae, 0x4d, 0xeb, 0xd6, 0xc5, 0xeb, 0xce, 0x5e,
- 0x40, 0xc7, 0x30, 0x36, 0xf6, 0x0e, 0x0e, 0x4e, 0x13, 0xe6, 0x04, 0x85, 0x87, 0x53, 0xd9, 0x70,
- 0x30, 0xcf, 0xae, 0x5d, 0xbb, 0x86, 0xd5, 0xb3, 0x40, 0x06, 0x6e, 0x17, 0xf8, 0xea, 0x50, 0x79,
- 0x05, 0xa4, 0xac, 0x3c, 0xc4, 0xce, 0x2a, 0x33, 0x18, 0x19, 0x1d, 0x5d, 0xbd, 0x7a, 0xb5, 0x3a,
- 0x10, 0x0b, 0x4f, 0x07, 0xae, 0x68, 0x4d, 0x4d, 0xcd, 0xf0, 0xcb, 0xa3, 0x07, 0x8d, 0x8d, 0x4d,
- 0x72, 0x47, 0x1b, 0xb2, 0x4a, 0x5c, 0x85, 0xa8, 0x40, 0xe4, 0x76, 0x5e, 0xe3, 0xf3, 0xf9, 0x45,
- 0x45, 0xc5, 0x70, 0xbe, 0x96, 0xed, 0x3a, 0x1a, 0xa2, 0x60, 0xd9, 0x6c, 0xb6, 0x8f, 0x8f, 0x4f,
- 0x7a, 0x7a, 0x46, 0x61, 0x61, 0x91, 0xb5, 0xf5, 0xdc, 0xd5, 0x73, 0x06, 0xab, 0x56, 0x71, 0xc3,
- 0xf9, 0xc2, 0xfc, 0x82, 0x10, 0x7e, 0x04, 0xe5, 0x79, 0x99, 0x98, 0x98, 0xfc, 0xf0, 0xc3, 0x8f,
- 0x6a, 0x2a, 0x88, 0x1d, 0x19, 0x19, 0xa9, 0xab, 0xab, 0x3b, 0x78, 0xa8, 0xfc, 0xea, 0xb5, 0x6b,
- 0x72, 0x4f, 0x7e, 0x46, 0x35, 0x31, 0x90, 0x14, 0xc6, 0x88, 0x44, 0x22, 0x75, 0x20, 0x96, 0x21,
- 0x91, 0x07, 0xe1, 0xe1, 0xe1, 0x47, 0x8e, 0x1c, 0x91, 0x84, 0xbc, 0xe6, 0x61, 0xda, 0xa6, 0xa6,
- 0xa6, 0x85, 0x49, 0x0f, 0xaf, 0x9a, 0xdb, 0xd9, 0xb9, 0xf9, 0xfa, 0x1a, 0x99, 0x99, 0xa9, 0xc6,
- 0xb1, 0x9e, 0x9e, 0x9e, 0x25, 0x25, 0xd3, 0x79, 0x84, 0xe5, 0xe9, 0x7c, 0x11, 0x05, 0x0b, 0x82,
- 0x8d, 0x8c, 0x8c, 0x84, 0xaa, 0x0f, 0x0b, 0x0b, 0xd7, 0x7d, 0x61, 0x85, 0x32, 0xcb, 0xd2, 0x92,
- 0x27, 0x10, 0xac, 0x2f, 0x28, 0x0c, 0x89, 0x88, 0xa4, 0xd4, 0x17, 0x54, 0xc4, 0xf9, 0x0b, 0x17,
- 0xd4, 0xb4, 0x8b, 0xf7, 0xd0, 0xd0, 0xd0, 0xb9, 0xf3, 0xe7, 0x0f, 0x1c, 0x2a, 0xbf, 0x7e, 0xfd,
- 0x86, 0x22, 0x88, 0x7d, 0x26, 0x6d, 0xbb, 0x81, 0x63, 0xd7, 0xae, 0xdf, 0xab, 0x09, 0xb1, 0x0c,
- 0x49, 0x46, 0x2c, 0x4a, 0x20, 0x38, 0x7e, 0xfc, 0xc4, 0xbc, 0xf2, 0xe0, 0x56, 0x73, 0xf3, 0xc2,
- 0xde, 0x10, 0x24, 0x81, 0x57, 0x70, 0x70, 0x70, 0x44, 0x84, 0x52, 0xf5, 0xb1, 0xb2, 0x06, 0x31,
- 0x50, 0x5a, 0x5a, 0x1a, 0x13, 0x13, 0x03, 0xb7, 0x77, 0x19, 0xf6, 0x91, 0xa3, 0x2a, 0xb7, 0xbd,
- 0xbd, 0x41, 0xb0, 0xe9, 0x42, 0x61, 0x8e, 0xd5, 0x8b, 0x23, 0x49, 0xa3, 0xad, 0xb2, 0xb5, 0x0d,
- 0x97, 0x54, 0x1c, 0x01, 0xb1, 0x54, 0x0f, 0x6a, 0x0c, 0xdd, 0xcd, 0x9b, 0x37, 0xd5, 0x21, 0x62,
- 0x61, 0x83, 0x83, 0x83, 0xb5, 0x67, 0xce, 0x80, 0x63, 0x6f, 0x35, 0xdd, 0x92, 0x8f, 0x58, 0x69,
- 0x2a, 0x81, 0x20, 0xf6, 0xe3, 0x8f, 0x3f, 0x56, 0x1f, 0x62, 0x09, 0x68, 0xf1, 0x74, 0xe3, 0x69,
- 0x7d, 0x4a, 0x3a, 0x77, 0xc8, 0x80, 0xb6, 0xb9, 0xa5, 0x45, 0x5f, 0x5f, 0x7f, 0x01, 0xd0, 0xd2,
- 0xb4, 0xb5, 0xa3, 0x13, 0x13, 0xe1, 0x11, 0xb0, 0xad, 0x55, 0x44, 0x2c, 0x2e, 0x60, 0xdb, 0xb6,
- 0xd7, 0xe3, 0xe3, 0xe3, 0xa9, 0x70, 0x81, 0x6a, 0x9f, 0xf3, 0x0f, 0x6a, 0xd4, 0xbe, 0x06, 0x50,
- 0x47, 0xf9, 0xf9, 0x05, 0x61, 0x61, 0x61, 0xf3, 0xe8, 0x22, 0x3a, 0x9d, 0x6d, 0x6f, 0xc7, 0x5f,
- 0xbb, 0x16, 0x88, 0x0d, 0x8d, 0x8a, 0xa2, 0x56, 0xce, 0xda, 0xda, 0xd9, 0x75, 0xab, 0x6d, 0xd9,
- 0xec, 0xfd, 0xfb, 0xf7, 0x4f, 0xfe, 0xf4, 0xd3, 0xc1, 0xf2, 0x8a, 0xb6, 0xb6, 0x76, 0x45, 0xce,
- 0xa7, 0xf2, 0x08, 0x00, 0xd0, 0x81, 0x03, 0x07, 0xd5, 0x8a, 0x58, 0x86, 0x44, 0x1e, 0x04, 0x05,
- 0x05, 0xdd, 0x6c, 0x6c, 0x7c, 0x2a, 0x53, 0x04, 0x0e, 0xd8, 0xb6, 0xb6, 0xb6, 0x5a, 0x58, 0x5a,
- 0x2e, 0x00, 0x5a, 0x6d, 0x3a, 0x3d, 0xb7, 0xa0, 0x30, 0x21, 0x35, 0xd5, 0x64, 0x11, 0xbb, 0x2c,
- 0x6d, 0xd9, 0x52, 0x9a, 0x9a, 0x9a, 0xea, 0xe1, 0xe1, 0x69, 0x62, 0xc2, 0x5a, 0x56, 0xd5, 0xdd,
- 0x54, 0x92, 0xcb, 0xdd, 0xdd, 0x1d, 0x1e, 0x28, 0x08, 0x16, 0x64, 0x3b, 0xcf, 0x69, 0x62, 0xc4,
- 0xda, 0x87, 0x46, 0xaf, 0xc9, 0xc9, 0x2f, 0x00, 0x6e, 0x19, 0x86, 0xd3, 0x55, 0x5b, 0x80, 0x77,
- 0x7f, 0x7f, 0xbf, 0x3a, 0xe0, 0x0a, 0xeb, 0xed, 0xed, 0x3d, 0x76, 0xfc, 0xc4, 0xc1, 0xf2, 0xf2,
- 0xee, 0xee, 0x85, 0xb2, 0xb4, 0x73, 0x10, 0x4b, 0xaa, 0x62, 0x2e, 0x5f, 0xbe, 0xac, 0x6e, 0xc4,
- 0x12, 0xe3, 0x72, 0xb9, 0xbf, 0x34, 0x34, 0xc8, 0xae, 0x22, 0x6f, 0xbf, 0x7d, 0xdb, 0xc7, 0xd7,
- 0x17, 0x7a, 0x09, 0x6e, 0xda, 0xbc, 0xf3, 0xb5, 0x3e, 0x93, 0x59, 0xb6, 0xe3, 0x37, 0x6b, 0x13,
- 0x12, 0x54, 0x08, 0xc6, 0x52, 0x56, 0x5c, 0xbc, 0x31, 0x2b, 0x2b, 0xcb, 0xdb, 0xdb, 0x9b, 0x04,
- 0xb8, 0x54, 0xfe, 0x9c, 0x7f, 0x38, 0x03, 0x62, 0x31, 0xb0, 0x98, 0xdc, 0xe1, 0x02, 0xe7, 0xe6,
- 0xe6, 0x46, 0x47, 0x47, 0xcf, 0x7f, 0x1e, 0x8d, 0x66, 0x6a, 0x6d, 0xb5, 0x3a, 0x32, 0x2a, 0x3b,
- 0x2f, 0x2f, 0x26, 0x31, 0xd1, 0x58, 0x8a, 0xea, 0x8c, 0xac, 0x2c, 0x35, 0x65, 0xbb, 0xc4, 0xc1,
- 0xd8, 0x3b, 0x77, 0x8e, 0x1c, 0xad, 0x39, 0x54, 0x5e, 0xde, 0xd3, 0x73, 0x47, 0x59, 0xc4, 0xde,
- 0xbb, 0x77, 0xef, 0xd5, 0x20, 0x16, 0x4c, 0x1b, 0x1b, 0x1b, 0x7b, 0xf1, 0xd2, 0xa5, 0x71, 0x71,
- 0x11, 0xb8, 0x98, 0x69, 0x3b, 0x3a, 0x3b, 0x13, 0x12, 0x13, 0xc9, 0x26, 0xb3, 0x8c, 0xf9, 0x76,
- 0x38, 0xf2, 0xe1, 0x72, 0xb7, 0xbf, 0xf1, 0x06, 0x97, 0xc7, 0x5b, 0xcc, 0x8d, 0x83, 0x77, 0x2c,
- 0x14, 0x0a, 0x7d, 0x7c, 0x7c, 0x97, 0xdb, 0x42, 0x45, 0x52, 0xb9, 0x0d, 0x49, 0x10, 0x1a, 0x1a,
- 0x9a, 0x97, 0x97, 0xe7, 0x20, 0xb3, 0x30, 0x76, 0x8e, 0x19, 0xae, 0x32, 0xf3, 0xe3, 0xf1, 0xd2,
- 0x72, 0x72, 0x12, 0x33, 0x32, 0x2d, 0xa4, 0xa1, 0xda, 0xd7, 0x4a, 0x4b, 0xd5, 0x87, 0xd8, 0x8e,
- 0x8e, 0x8e, 0xaa, 0xea, 0xea, 0x43, 0xe5, 0x15, 0x77, 0xef, 0xde, 0x55, 0x14, 0xb1, 0xd2, 0xca,
- 0xc3, 0xb1, 0xf1, 0x71, 0x4c, 0x1c, 0xaf, 0x06, 0xb4, 0x4c, 0x26, 0x13, 0x13, 0xf4, 0x85, 0x0b,
- 0x17, 0x25, 0xa0, 0x9d, 0xc2, 0x83, 0xf6, 0xda, 0x96, 0x2d, 0x92, 0x4d, 0x66, 0x6d, 0xc9, 0x26,
- 0xb3, 0x73, 0x46, 0x32, 0x5b, 0x24, 0xda, 0x5c, 0x56, 0x66, 0x65, 0xff, 0xd2, 0xa1, 0x56, 0xc4,
- 0x44, 0xa2, 0x3c, 0x4c, 0x88, 0xcb, 0x10, 0xb1, 0x12, 0x11, 0x6b, 0x68, 0x6f, 0xef, 0x20, 0x10,
- 0x08, 0x48, 0x44, 0xe8, 0x65, 0x67, 0xea, 0x18, 0x18, 0xb8, 0xf9, 0xfb, 0xc7, 0xa7, 0xa5, 0x67,
- 0xe6, 0x6e, 0x70, 0x76, 0x73, 0x23, 0x7f, 0xdc, 0xb9, 0xf3, 0x9f, 0xd4, 0xb4, 0xf5, 0x3c, 0x44,
- 0x61, 0x7b, 0x7b, 0x7b, 0xe5, 0xe1, 0xaa, 0xf2, 0x8a, 0x0a, 0x05, 0xd7, 0xe7, 0x4e, 0x2f, 0x49,
- 0x90, 0xae, 0x0a, 0x77, 0x71, 0x75, 0x7d, 0x35, 0x88, 0x65, 0x88, 0xfb, 0xd1, 0x19, 0x65, 0x64,
- 0x64, 0x5c, 0xb9, 0x7a, 0x15, 0x7e, 0xd8, 0xbd, 0xde, 0xde, 0x3f, 0xbe, 0xf5, 0x36, 0xdc, 0x22,
- 0xd2, 0x29, 0x6b, 0xce, 0x94, 0x6d, 0xc4, 0x62, 0x6d, 0xd9, 0xb6, 0x2d, 0x2b, 0x37, 0x77, 0x31,
- 0x92, 0x00, 0x06, 0x8f, 0x23, 0x3b, 0x3b, 0xdb, 0xc7, 0xc7, 0x67, 0x19, 0x22, 0xd6, 0xd0, 0x90,
- 0xe9, 0xe8, 0xe8, 0xb4, 0x66, 0x4d, 0xcc, 0x9c, 0x5d, 0xd5, 0xe6, 0x18, 0xa4, 0xac, 0x8d, 0x9b,
- 0x8b, 0x20, 0x3e, 0x5e, 0x98, 0x97, 0xef, 0x1b, 0x18, 0x48, 0xb6, 0xfe, 0x79, 0xe3, 0x8d, 0x9d,
- 0xf0, 0x8f, 0xd4, 0x84, 0xd8, 0xd6, 0xd6, 0xb6, 0x8a, 0xca, 0xc3, 0xe5, 0x95, 0x87, 0xef, 0xf7,
- 0x2b, 0xf4, 0x2f, 0xe6, 0x20, 0x16, 0x0a, 0xf3, 0x95, 0x21, 0x96, 0x80, 0x36, 0x2d, 0x2d, 0xad,
- 0xb9, 0xa5, 0x05, 0xc2, 0x7e, 0xcf, 0x9e, 0x8f, 0x40, 0x80, 0x7e, 0x7e, 0xfe, 0xec, 0x17, 0x72,
- 0x52, 0x61, 0x91, 0x91, 0xbf, 0xd9, 0xb9, 0x93, 0x1b, 0x16, 0xb6, 0xc8, 0x1b, 0x57, 0x5c, 0x5c,
- 0x8c, 0x67, 0xc4, 0xcb, 0xcb, 0x8b, 0xc5, 0x5a, 0x5e, 0x3a, 0x96, 0xa4, 0xba, 0x08, 0x62, 0x73,
- 0x72, 0x72, 0x16, 0x3e, 0x99, 0xc9, 0x5e, 0x15, 0xc4, 0xe7, 0x67, 0xe4, 0xe6, 0xc6, 0x25, 0x27,
- 0xb3, 0x24, 0x7e, 0xee, 0xf6, 0x1d, 0x3b, 0xa0, 0x18, 0xd5, 0x11, 0x2b, 0x80, 0x22, 0xbc, 0x75,
- 0xab, 0xb9, 0xbc, 0xa2, 0x12, 0x34, 0xab, 0x20, 0x8d, 0x93, 0x45, 0x34, 0x14, 0x62, 0x97, 0xb0,
- 0xe6, 0x50, 0xd6, 0x20, 0x5c, 0x01, 0x4e, 0xf8, 0x3b, 0x10, 0xff, 0xb6, 0xb6, 0x76, 0x98, 0xfd,
- 0x41, 0xa7, 0x19, 0x99, 0x99, 0x38, 0xb2, 0xb2, 0xb2, 0xdf, 0x79, 0xe7, 0x9d, 0xde, 0xbe, 0xbe,
- 0xff, 0xfa, 0xe4, 0x93, 0x0d, 0x22, 0x11, 0x97, 0x1b, 0x64, 0x69, 0x69, 0x89, 0xf3, 0x31, 0xc8,
- 0x04, 0xb4, 0x74, 0x1d, 0x9d, 0xec, 0xdc, 0xdc, 0xd7, 0xb6, 0x6e, 0xd3, 0x7b, 0xb1, 0x43, 0xb2,
- 0x32, 0x86, 0x4f, 0x2b, 0x29, 0xd9, 0x9c, 0x94, 0x94, 0x0c, 0x1a, 0x5f, 0x6e, 0x0b, 0xbe, 0xa8,
- 0xae, 0x2f, 0xf0, 0xb9, 0x0a, 0x0b, 0x0b, 0x19, 0x0b, 0x4e, 0x55, 0x34, 0x5d, 0x5d, 0x47, 0x4f,
- 0xcf, 0xb8, 0xd4, 0x54, 0x61, 0x7e, 0xbe, 0x8b, 0xbb, 0x07, 0x34, 0x70, 0xd9, 0xd6, 0xad, 0x77,
- 0xd5, 0x53, 0x54, 0x00, 0xd0, 0x35, 0x36, 0x36, 0x42, 0xc4, 0x56, 0x1e, 0xae, 0x1e, 0x18, 0x50,
- 0x68, 0x89, 0xee, 0x34, 0x62, 0xa7, 0xd3, 0x5e, 0xe2, 0xca, 0xea, 0x25, 0x04, 0x2a, 0xe9, 0xa0,
- 0xeb, 0xef, 0xef, 0x9f, 0x99, 0x99, 0xf9, 0xee, 0x7b, 0xef, 0x95, 0x97, 0x57, 0xe0, 0x81, 0x1a,
- 0x1e, 0x1e, 0x91, 0x69, 0xa4, 0x4c, 0x3a, 0x81, 0x4f, 0xf5, 0xf6, 0xf5, 0x7f, 0xf0, 0xc1, 0x87,
- 0xe0, 0x58, 0x90, 0x3c, 0x1c, 0x04, 0xc0, 0x1b, 0xbe, 0x2d, 0x68, 0x10, 0xb8, 0x72, 0xe1, 0x70,
- 0x36, 0x95, 0x96, 0x86, 0x91, 0xf6, 0x5c, 0x8b, 0x30, 0xdc, 0xb2, 0xd2, 0xd2, 0x52, 0x78, 0x7c,
- 0xce, 0xce, 0xce, 0x20, 0x9c, 0x65, 0x95, 0x41, 0x90, 0x78, 0x5e, 0xe2, 0x2d, 0xba, 0x22, 0x23,
- 0x23, 0x31, 0xd1, 0xc0, 0x59, 0x58, 0xe8, 0x6c, 0x2d, 0x2d, 0xe6, 0x2a, 0x33, 0xd0, 0x6c, 0x66,
- 0x6e, 0x6e, 0x7c, 0x5a, 0x9a, 0xa1, 0xb1, 0x71, 0x41, 0x61, 0xe1, 0x9d, 0xee, 0x3b, 0x6a, 0x2a,
- 0x83, 0xb9, 0x79, 0x93, 0x20, 0xb6, 0x4a, 0x41, 0xe7, 0x6e, 0x76, 0xa2, 0x76, 0x6a, 0xa9, 0x12,
- 0xb5, 0x80, 0x1c, 0x80, 0x8a, 0x6f, 0xfa, 0xe9, 0xa7, 0x9f, 0x35, 0xfc, 0xfa, 0x2b, 0x89, 0x09,
- 0x90, 0x96, 0x47, 0x4f, 0xa5, 0xc7, 0xc4, 0xc4, 0x4c, 0x23, 0xe5, 0xae, 0xee, 0x9e, 0xdf, 0xfd,
- 0x6e, 0x57, 0x52, 0x52, 0x12, 0x10, 0x0b, 0x44, 0x59, 0x59, 0x59, 0xb3, 0xd9, 0x6c, 0x73, 0x4b,
- 0x4b, 0x3b, 0x47, 0xa7, 0x88, 0x98, 0x98, 0x9c, 0xbc, 0x3c, 0x4b, 0x3b, 0xbb, 0x15, 0x92, 0x3c,
- 0xc2, 0x4a, 0x08, 0x32, 0x53, 0x53, 0x26, 0x3c, 0x44, 0x3d, 0x3d, 0xa5, 0x84, 0x28, 0x3e, 0x56,
- 0xd2, 0x6d, 0x3e, 0x72, 0x19, 0x96, 0xc8, 0x52, 0x8d, 0x5f, 0x78, 0x3c, 0x1e, 0x69, 0x52, 0xba,
- 0xf0, 0xf9, 0xda, 0x3a, 0x3a, 0x56, 0x4e, 0x4e, 0x51, 0xeb, 0xd6, 0x65, 0xe7, 0xe5, 0xf9, 0x70,
- 0xb9, 0x59, 0xd9, 0xd9, 0x6a, 0xca, 0x20, 0x48, 0x11, 0x5b, 0x09, 0xc8, 0x3e, 0x78, 0xf0, 0x40,
- 0x41, 0xc4, 0x3e, 0x93, 0x41, 0x6c, 0x59, 0x59, 0xd9, 0xe2, 0xe1, 0x1a, 0x14, 0x14, 0xf4, 0xfb,
- 0x3f, 0xfc, 0xa1, 0xa6, 0xa6, 0xa6, 0xaf, 0xbf, 0xff, 0xa9, 0xb4, 0x4f, 0xf2, 0xc4, 0xcc, 0x06,
- 0x37, 0x53, 0xff, 0x47, 0xde, 0x75, 0x40, 0x45, 0x91, 0x6d, 0xdb, 0xf5, 0x27, 0x3c, 0xc3, 0x8c,
- 0x3e, 0x05, 0x1c, 0x92, 0x80, 0x0a, 0x92, 0x04, 0x0c, 0x04, 0x9d, 0x51, 0x0c, 0x28, 0x20, 0x06,
- 0x90, 0x31, 0x83, 0x0a, 0x88, 0x01, 0x45, 0x31, 0x47, 0x40, 0x11, 0x45, 0x47, 0x40, 0x51, 0x4c,
- 0x38, 0x32, 0x98, 0xc5, 0x38, 0x0a, 0x88, 0x24, 0x45, 0xcc, 0x80, 0x12, 0xa5, 0x69, 0xb2, 0xb4,
- 0x48, 0x14, 0x90, 0x54, 0xd5, 0x01, 0x9d, 0xf5, 0x77, 0x55, 0x75, 0x37, 0x0d, 0x8d, 0x0c, 0x86,
- 0x79, 0x8f, 0xbf, 0xfe, 0x5d, 0x77, 0xf5, 0xc2, 0xae, 0xea, 0x6b, 0xd5, 0xb9, 0xfb, 0xee, 0xb3,
- 0xcf, 0x8d, 0xef, 0xc5, 0xf9, 0x83, 0xf0, 0x0f, 0x70, 0x2f, 0xc2, 0xa2, 0x09, 0x66, 0x66, 0x30,
- 0x29, 0x40, 0x3b, 0x6a, 0xf4, 0x98, 0x59, 0x73, 0xe7, 0x2e, 0x74, 0x72, 0x5a, 0xee, 0xba, 0x6a,
- 0xc5, 0x6a, 0x37, 0x70, 0xec, 0x10, 0x43, 0x23, 0x10, 0xc5, 0x8f, 0x7d, 0xfa, 0x18, 0x98, 0x98,
- 0x8c, 0x9b, 0x3c, 0x79, 0x9c, 0x85, 0x85, 0x89, 0xa9, 0xa9, 0xde, 0xb0, 0xe1, 0x83, 0x34, 0x35,
- 0xa1, 0x36, 0xa4, 0x77, 0x3d, 0x92, 0x4e, 0x74, 0xc7, 0x8e, 0xbd, 0x91, 0x91, 0xf1, 0xff, 0xc3,
- 0x65, 0x08, 0x4c, 0x7f, 0xac, 0xbc, 0xbc, 0x3c, 0x6c, 0xbb, 0x70, 0xe1, 0x22, 0xc9, 0x35, 0x4a,
- 0xea, 0x4a, 0xdd, 0x4f, 0xef, 0x95, 0x3d, 0xe7, 0xd7, 0xf7, 0xbc, 0x7f, 0x9f, 0x73, 0x7e, 0x7d,
- 0x82, 0x77, 0xc9, 0xfd, 0xd0, 0xe3, 0x1b, 0xfc, 0xe0, 0x5f, 0x3d, 0x7b, 0x0e, 0xd4, 0xd1, 0x31,
- 0x9f, 0x3a, 0xcd, 0x7a, 0xf6, 0xec, 0x5f, 0xc6, 0x8c, 0x29, 0x29, 0x29, 0xf9, 0xea, 0x70, 0x65,
- 0x10, 0x9b, 0xc3, 0xce, 0x05, 0xc7, 0x46, 0x74, 0x3e, 0xf2, 0x62, 0x0e, 0x8f, 0x13, 0x21, 0x76,
- 0xc3, 0x86, 0x0d, 0x5f, 0x82, 0x55, 0x10, 0xe3, 0x8a, 0x15, 0x2b, 0x9e, 0x3e, 0x7d, 0x56, 0x53,
- 0xfb, 0xae, 0x85, 0x45, 0x25, 0xf1, 0xd9, 0xe6, 0xec, 0x30, 0xd1, 0x02, 0xc9, 0x94, 0x94, 0x94,
- 0x89, 0x13, 0x27, 0x01, 0xb1, 0xe6, 0x16, 0x16, 0x0b, 0x1c, 0x1c, 0xbd, 0x7c, 0xf6, 0x06, 0x9d,
- 0x0a, 0x0e, 0x08, 0x3c, 0xb2, 0xd5, 0xd3, 0xd3, 0x69, 0xf9, 0x72, 0xeb, 0x59, 0xb3, 0x06, 0x0f,
- 0xd1, 0x83, 0x48, 0xe8, 0xd9, 0xab, 0xd7, 0x90, 0x11, 0x86, 0x93, 0x6d, 0x6d, 0x67, 0xce, 0x9f,
- 0x3f, 0x7b, 0xc1, 0x82, 0xb9, 0x0b, 0x16, 0xda, 0xce, 0x9b, 0x37, 0x71, 0xca, 0x14, 0xa3, 0x9f,
- 0x7f, 0xe9, 0x3f, 0x68, 0x50, 0x07, 0xf3, 0x66, 0xa9, 0x63, 0x28, 0xe9, 0xc1, 0xf4, 0xff, 0x5b,
- 0x1d, 0x05, 0xff, 0xf3, 0x29, 0xa9, 0xe3, 0x72, 0x50, 0x3b, 0xcc, 0x08, 0xc2, 0x82, 0x05, 0x0b,
- 0x1d, 0x1c, 0x1c, 0x7b, 0xd1, 0xb3, 0xb5, 0x0f, 0xbb, 0xcb, 0xa4, 0x87, 0xff, 0xd4, 0x94, 0xa1,
- 0x40, 0xbc, 0x94, 0xa7, 0x72, 0xa6, 0x7c, 0x63, 0xba, 0xc2, 0xd3, 0x2b, 0xfd, 0xd6, 0xce, 0x95,
- 0xa3, 0x76, 0x4d, 0xff, 0xf1, 0x47, 0x75, 0x5d, 0xdd, 0xb1, 0xe6, 0xe6, 0xc6, 0x63, 0xc6, 0x14,
- 0x17, 0x17, 0xff, 0x53, 0x88, 0xcd, 0xc9, 0x81, 0x28, 0x08, 0xbf, 0x1d, 0x59, 0x55, 0x59, 0xd5,
- 0x29, 0xc4, 0xb6, 0x9a, 0x0c, 0xf3, 0x61, 0xe7, 0xce, 0x9d, 0x9f, 0x0d, 0x57, 0xc4, 0x53, 0x57,
- 0xaf, 0x5e, 0xab, 0xa8, 0xa8, 0x14, 0x88, 0x8e, 0x58, 0x6a, 0x96, 0x40, 0xe9, 0x7b, 0x31, 0x4a,
- 0xa5, 0x4e, 0x69, 0x04, 0xaa, 0x63, 0x63, 0xe3, 0x10, 0xf4, 0x4d, 0x9f, 0x6e, 0xed, 0xba, 0xda,
- 0xed, 0xc4, 0xef, 0xa7, 0xae, 0xdf, 0xba, 0x75, 0x2a, 0x24, 0x64, 0xc7, 0x4e, 0xaf, 0x65, 0xcb,
- 0x97, 0x4f, 0x9d, 0x36, 0x7d, 0x84, 0x91, 0x91, 0x32, 0x3d, 0xe1, 0x0a, 0xa0, 0xed, 0xd6, 0xbd,
- 0xfb, 0x8f, 0xbd, 0x7b, 0xff, 0x5b, 0x4e, 0x4e, 0x49, 0x43, 0x63, 0xd8, 0xc8, 0x91, 0x16, 0x54,
- 0x80, 0xb0, 0x60, 0xbe, 0x83, 0xc3, 0x92, 0x95, 0x2b, 0xcd, 0xac, 0xa6, 0x28, 0x7c, 0x44, 0xa1,
- 0xc9, 0xc9, 0xc9, 0x41, 0xf0, 0x30, 0xcb, 0x69, 0xbb, 0xf2, 0x06, 0xc8, 0x0c, 0xf6, 0xa0, 0x58,
- 0x20, 0xe0, 0xd1, 0xac, 0x3a, 0x6f, 0x7c, 0xdc, 0xcc, 0xc8, 0x7e, 0xb4, 0x4d, 0xe9, 0x57, 0x63,
- 0x56, 0xce, 0xc2, 0xb9, 0xd0, 0xab, 0x87, 0x1c, 0x37, 0x6e, 0x58, 0xbb, 0x78, 0x96, 0x41, 0x5c,
- 0x70, 0xbf, 0x86, 0x74, 0x79, 0x21, 0x56, 0x5b, 0xe7, 0xda, 0xe7, 0x8a, 0x27, 0x3c, 0xe5, 0x7a,
- 0xfd, 0xf0, 0x0d, 0x75, 0x38, 0x85, 0xb2, 0xf2, 0x20, 0x6d, 0xed, 0x94, 0x94, 0xd4, 0x7f, 0xe2,
- 0xbc, 0x03, 0x28, 0xc2, 0x82, 0x82, 0x82, 0xdb, 0xb7, 0x23, 0xc3, 0x22, 0x6e, 0x77, 0x7e, 0xbf,
- 0x44, 0x06, 0xb1, 0xcc, 0x01, 0x5e, 0xde, 0xde, 0xde, 0x9f, 0x81, 0x55, 0xb0, 0x96, 0xd3, 0xe2,
- 0xc5, 0xd9, 0x6c, 0x36, 0x9f, 0x1e, 0x79, 0x15, 0x1f, 0x97, 0x20, 0xdc, 0xc7, 0x5b, 0x92, 0x51,
- 0xdb, 0x3b, 0x57, 0xb4, 0xbe, 0xa1, 0xe1, 0x60, 0xc0, 0x21, 0x6b, 0x6b, 0xeb, 0x55, 0x6e, 0x6e,
- 0xa0, 0xd6, 0xa8, 0x98, 0xb8, 0xa8, 0x98, 0x58, 0xf8, 0x89, 0x0b, 0x17, 0x2f, 0xf9, 0xfa, 0xfa,
- 0xad, 0x74, 0x75, 0x9d, 0x3a, 0x75, 0x1a, 0x54, 0xb1, 0x82, 0xa2, 0x22, 0xa2, 0x27, 0xd4, 0x0b,
- 0xe5, 0xd0, 0xe9, 0x73, 0x94, 0xa8, 0x39, 0xde, 0xdf, 0x7e, 0xdb, 0xa3, 0x77, 0xaf, 0x61, 0x26,
- 0x26, 0x6b, 0x36, 0x6c, 0x38, 0xf9, 0x7b, 0xf0, 0xee, 0xbd, 0x7b, 0x87, 0x19, 0x1b, 0x7f, 0xd7,
- 0xad, 0xed, 0x24, 0x3a, 0x08, 0x15, 0x70, 0x0b, 0xe2, 0x0e, 0x84, 0x75, 0x88, 0x07, 0xbb, 0xa6,
- 0x88, 0x65, 0xb0, 0xda, 0x8d, 0x9e, 0x32, 0x84, 0x66, 0x85, 0x56, 0x06, 0x56, 0x94, 0xa7, 0x92,
- 0xc2, 0xc7, 0x12, 0x2e, 0xe1, 0x32, 0xee, 0x82, 0x77, 0x93, 0x81, 0xbc, 0xef, 0xd5, 0x0b, 0xc8,
- 0x6c, 0x33, 0x37, 0x83, 0xd9, 0xfb, 0x85, 0x9e, 0xc8, 0x3d, 0x00, 0x16, 0x58, 0xe5, 0xba, 0xfc,
- 0x6a, 0xd0, 0xe2, 0x57, 0x77, 0xb5, 0xdb, 0xc5, 0xaa, 0x38, 0x37, 0xa4, 0x29, 0x1d, 0x71, 0x97,
- 0xe9, 0xd7, 0xf7, 0x5b, 0xfc, 0xbe, 0x4f, 0x9f, 0x3e, 0x67, 0xce, 0x9c, 0x29, 0x2f, 0x2f, 0xff,
- 0xea, 0xbb, 0xc1, 0xa0, 0x40, 0x0e, 0x87, 0x13, 0x15, 0x1d, 0x0d, 0x61, 0x50, 0xda, 0xe1, 0xea,
- 0x6f, 0x09, 0xb8, 0x7e, 0x29, 0x62, 0x95, 0x94, 0x95, 0x3d, 0x3c, 0x3c, 0xab, 0xab, 0x6b, 0x5a,
- 0xe2, 0x29, 0xba, 0xa8, 0xf7, 0x92, 0xbc, 0x4a, 0xbb, 0x7e, 0x49, 0x25, 0x20, 0x3e, 0x66, 0x94,
- 0xc7, 0x17, 0x64, 0x64, 0x66, 0x2e, 0x72, 0x70, 0x5c, 0xed, 0xe6, 0x16, 0x10, 0x18, 0x18, 0x71,
- 0x27, 0x2a, 0x29, 0xf9, 0x79, 0x68, 0xe8, 0x65, 0x7f, 0x7f, 0xff, 0x67, 0x89, 0x49, 0x90, 0x37,
- 0x87, 0x0f, 0x07, 0xba, 0xb9, 0xad, 0x01, 0x68, 0xf5, 0xf5, 0xf5, 0x5b, 0x81, 0xb6, 0x75, 0x52,
- 0x53, 0x57, 0x77, 0x5a, 0xb6, 0x3c, 0x38, 0x24, 0x64, 0xe3, 0xd6, 0x6d, 0xaa, 0x83, 0x07, 0x4b,
- 0x2a, 0x5b, 0x3c, 0xe4, 0xd4, 0xa9, 0x53, 0xed, 0xec, 0xec, 0xc0, 0x30, 0xa8, 0xd9, 0x6e, 0x5d,
- 0x72, 0x01, 0x02, 0x03, 0x57, 0xa8, 0xcd, 0x3e, 0x7d, 0xfb, 0x2a, 0x29, 0x29, 0x6b, 0x68, 0x0c,
- 0xc6, 0xfb, 0x0e, 0x1f, 0x31, 0xc2, 0x10, 0x61, 0x92, 0x91, 0xf1, 0xc7, 0x12, 0x2e, 0xe1, 0x32,
- 0xda, 0x23, 0x5a, 0xb4, 0x8e, 0x8e, 0x8e, 0xda, 0x80, 0x01, 0x78, 0x41, 0xc6, 0x44, 0x2d, 0x87,
- 0xc7, 0xa1, 0x51, 0xf7, 0xe8, 0x01, 0x54, 0x1b, 0x18, 0x18, 0xd8, 0xd8, 0xcc, 0x08, 0xdc, 0xbd,
- 0xb8, 0x34, 0x41, 0xab, 0x15, 0x3e, 0xb3, 0x90, 0x15, 0x5a, 0xb2, 0x18, 0xb4, 0xe9, 0x8a, 0x87,
- 0xb6, 0xf5, 0x95, 0xf9, 0xf7, 0x37, 0x28, 0x6d, 0xfc, 0xf8, 0xf1, 0xa7, 0x4e, 0x9d, 0x42, 0x60,
- 0xf2, 0x75, 0xe3, 0x2f, 0x94, 0x56, 0x5e, 0x5e, 0x11, 0x77, 0xf7, 0x6e, 0x58, 0x58, 0x78, 0x71,
- 0xf1, 0xab, 0xce, 0xff, 0xea, 0xb3, 0x11, 0xab, 0xa8, 0xa8, 0xb8, 0xdf, 0xd7, 0x17, 0x24, 0xd9,
- 0xdc, 0x46, 0xb5, 0x7e, 0x68, 0xc9, 0x1f, 0x3e, 0xb4, 0x84, 0x5a, 0x02, 0x6e, 0x1d, 0x9f, 0xe4,
- 0x08, 0xc8, 0x57, 0x02, 0xb2, 0x48, 0x40, 0x16, 0x08, 0x88, 0xdc, 0xa6, 0xda, 0x8c, 0xb4, 0xe4,
- 0xeb, 0xe7, 0xfe, 0xd8, 0x77, 0xf8, 0xc8, 0xd1, 0xeb, 0x37, 0x6f, 0x01, 0xae, 0xe9, 0xe9, 0x19,
- 0x56, 0x56, 0x53, 0x54, 0x55, 0x55, 0x03, 0x8f, 0x1c, 0x81, 0xbe, 0xbd, 0x73, 0x27, 0x0a, 0xa0,
- 0x5d, 0xb5, 0x6a, 0xb5, 0xa5, 0xe5, 0xe4, 0x21, 0x43, 0x86, 0x80, 0x58, 0x98, 0x61, 0x5c, 0x69,
- 0xd4, 0x19, 0x9b, 0x9a, 0xae, 0x5e, 0xb7, 0xde, 0x65, 0xb5, 0xdb, 0x50, 0x13, 0x93, 0xee, 0xad,
- 0x37, 0x33, 0x71, 0x74, 0x14, 0xce, 0x81, 0x61, 0x06, 0xd4, 0xba, 0x20, 0x62, 0x99, 0x13, 0x36,
- 0xf1, 0x78, 0x40, 0x1d, 0x5a, 0x16, 0x54, 0x3d, 0x1e, 0x18, 0xad, 0x6c, 0x21, 0x62, 0x7b, 0x07,
- 0x24, 0xc7, 0x76, 0x33, 0x2e, 0xe1, 0x32, 0xdc, 0xc7, 0x9c, 0x39, 0x73, 0xa6, 0x4d, 0x9b, 0x36,
- 0x7a, 0xf4, 0x68, 0x6d, 0x6d, 0x6d, 0x98, 0x08, 0x2c, 0xcd, 0x98, 0x88, 0x51, 0xb0, 0x28, 0x16,
- 0x72, 0x68, 0xc2, 0x04, 0xb3, 0xe5, 0xcb, 0x5d, 0x58, 0xb7, 0x4d, 0xa0, 0x57, 0x25, 0xe0, 0xaa,
- 0x48, 0x64, 0x2b, 0x11, 0xd9, 0xfd, 0x89, 0x6c, 0x15, 0xfa, 0x53, 0x99, 0x60, 0x29, 0xb6, 0x80,
- 0x36, 0x55, 0xe9, 0x98, 0xbb, 0xdc, 0xf7, 0xdf, 0x51, 0xad, 0x49, 0x4b, 0x4b, 0xeb, 0xc0, 0x81,
- 0x83, 0x5f, 0x7d, 0x28, 0xa1, 0xba, 0xba, 0x3a, 0x21, 0xe1, 0x01, 0x10, 0x9b, 0x9f, 0x97, 0xff,
- 0x4f, 0x23, 0x16, 0x6e, 0x6b, 0xf7, 0x9e, 0x3d, 0x0d, 0x8d, 0x8d, 0x02, 0x89, 0xd3, 0xbe, 0xde,
- 0x4b, 0xe0, 0x93, 0x29, 0x53, 0xd4, 0xaf, 0xc5, 0x17, 0xf0, 0x6a, 0x79, 0x8d, 0x85, 0xbc, 0xfa,
- 0x14, 0x7e, 0x43, 0x32, 0xbf, 0x21, 0x91, 0x57, 0xff, 0x88, 0xf7, 0xee, 0x2e, 0xaf, 0xe6, 0x0e,
- 0xb7, 0x26, 0xbc, 0xbe, 0x2c, 0x32, 0xe5, 0x79, 0x5c, 0xd2, 0xf3, 0x17, 0xf9, 0x05, 0x85, 0xfb,
- 0xf6, 0xfd, 0x26, 0x27, 0xd7, 0x0f, 0x6c, 0xa3, 0xab, 0xab, 0x1b, 0x14, 0x14, 0x94, 0x96, 0x96,
- 0x1e, 0x19, 0x79, 0x27, 0x20, 0xe0, 0xd0, 0xb2, 0x65, 0xcb, 0xcd, 0xcd, 0xcd, 0xf1, 0x25, 0x7c,
- 0x65, 0xbb, 0x9e, 0x5d, 0x55, 0x53, 0xd3, 0xca, 0x66, 0x86, 0xa5, 0xb5, 0xb5, 0xae, 0xa1, 0x61,
- 0xf7, 0x1f, 0x84, 0x88, 0x05, 0x3e, 0x27, 0x4e, 0x9c, 0xb8, 0x71, 0xe3, 0x46, 0xa8, 0x0e, 0xd4,
- 0x26, 0x1c, 0x5c, 0x17, 0x44, 0xac, 0xd8, 0x71, 0xab, 0xa8, 0xa8, 0x82, 0x36, 0xc1, 0x84, 0x2b,
- 0x57, 0xba, 0x7a, 0x79, 0x79, 0xc1, 0xd1, 0x1c, 0x42, 0x73, 0x45, 0xd3, 0xfd, 0x48, 0xc2, 0x15,
- 0x5c, 0x3e, 0x18, 0x10, 0xb0, 0x77, 0xef, 0xbe, 0x2d, 0x5b, 0xb6, 0x02, 0xde, 0x80, 0x25, 0xc8,
- 0x16, 0x4c, 0xcb, 0x8c, 0xc2, 0x88, 0x8a, 0x55, 0x31, 0x31, 0x31, 0x99, 0x3f, 0xdf, 0x2e, 0xfc,
- 0xa8, 0x79, 0x4b, 0x9c, 0x45, 0x51, 0xab, 0x12, 0x05, 0x54, 0xb6, 0x1a, 0xc1, 0x1e, 0x48, 0xb0,
- 0x07, 0x11, 0x6c, 0x75, 0x2a, 0x67, 0xab, 0x4a, 0x32, 0x6d, 0x7d, 0x8a, 0xe2, 0xde, 0x95, 0xc2,
- 0x83, 0x3c, 0x40, 0x50, 0xdb, 0xdd, 0xdd, 0x21, 0x0f, 0xbe, 0x22, 0x68, 0xeb, 0xeb, 0xeb, 0x13,
- 0x13, 0x13, 0xa1, 0x0a, 0xb2, 0x59, 0xd9, 0xff, 0x28, 0x62, 0xd1, 0x6c, 0xb7, 0x6d, 0xdf, 0x5e,
- 0x5e, 0x51, 0x21, 0x90, 0xa6, 0x56, 0x49, 0xa0, 0xd2, 0x8b, 0xc8, 0xaa, 0xaa, 0xaa, 0x1e, 0x24,
- 0xdc, 0x3b, 0xfd, 0xc7, 0x31, 0xbf, 0xfd, 0x5e, 0x3b, 0x3d, 0x37, 0x79, 0x7a, 0x6c, 0xf0, 0xdd,
- 0xbf, 0xf3, 0x74, 0x48, 0x60, 0x7c, 0xdc, 0xb5, 0x37, 0x9c, 0xe7, 0xbc, 0xa6, 0x7c, 0x3e, 0x91,
- 0x47, 0x36, 0x14, 0x55, 0xbf, 0x2d, 0xbb, 0x79, 0x2b, 0x6c, 0xf8, 0xf0, 0xe1, 0x80, 0x6b, 0x37,
- 0x7a, 0xa4, 0x0c, 0xb1, 0xed, 0xf9, 0xf3, 0xe7, 0x21, 0x1b, 0xc2, 0x23, 0x22, 0x7e, 0xdb, 0xbf,
- 0xdf, 0xd9, 0x79, 0x89, 0x99, 0x99, 0x19, 0x1a, 0x7b, 0xbb, 0xf3, 0x12, 0x11, 0x23, 0x50, 0x47,
- 0x30, 0xff, 0xf2, 0x8b, 0x92, 0xba, 0xba, 0xf8, 0x98, 0x09, 0x18, 0x79, 0xdd, 0xba, 0xf5, 0x3b,
- 0x76, 0xec, 0xa0, 0x39, 0xb6, 0x8b, 0x76, 0x14, 0x88, 0xf7, 0x71, 0xd5, 0xd3, 0xd3, 0x83, 0xfe,
- 0x59, 0xb3, 0x66, 0xed, 0x91, 0xa3, 0x47, 0xc3, 0xc2, 0xc3, 0x1f, 0x3c, 0x7c, 0xf8, 0xf4, 0xd9,
- 0xb3, 0xc4, 0xc4, 0xa4, 0x0e, 0x32, 0x2e, 0x3f, 0x7e, 0xf2, 0x24, 0x36, 0x2e, 0xee, 0xe2, 0xc5,
- 0x4b, 0x7b, 0x7c, 0x7c, 0xc0, 0xba, 0xa6, 0xa6, 0x63, 0x07, 0x0d, 0x1a, 0xf4, 0x6f, 0x7a, 0x52,
- 0x13, 0xad, 0x07, 0x7e, 0x82, 0xc0, 0x40, 0x54, 0xbb, 0x6b, 0x9d, 0x33, 0x27, 0x5e, 0xab, 0x05,
- 0xae, 0x2c, 0x06, 0xae, 0x00, 0xaa, 0x26, 0xc1, 0xd6, 0x21, 0xd8, 0xba, 0xa2, 0xac, 0x49, 0x83,
- 0x56, 0x49, 0x0c, 0xda, 0xc2, 0x38, 0x85, 0x51, 0xba, 0xc2, 0x95, 0xe0, 0x70, 0x70, 0xb6, 0xb6,
- 0xbf, 0xd6, 0xd6, 0xd6, 0x7e, 0x2d, 0xd0, 0x92, 0x04, 0x99, 0x95, 0x95, 0x15, 0x15, 0x15, 0x9d,
- 0x99, 0x99, 0xf9, 0xcf, 0x21, 0x16, 0x68, 0x81, 0xb3, 0x2a, 0x2a, 0x7a, 0x45, 0x8d, 0x5e, 0xb5,
- 0x16, 0xae, 0xc2, 0x01, 0xdf, 0x66, 0xe1, 0x60, 0x41, 0x52, 0x52, 0xf2, 0xfa, 0xf5, 0xeb, 0xf5,
- 0xf5, 0xf4, 0xd4, 0xd4, 0xd4, 0x10, 0x28, 0xc8, 0xc9, 0xca, 0xf6, 0xa5, 0x52, 0x1f, 0x20, 0x07,
- 0xff, 0x54, 0x55, 0x55, 0xd1, 0xd2, 0xd4, 0x98, 0x34, 0x71, 0x82, 0xef, 0xfe, 0x3d, 0xe9, 0x69,
- 0xc9, 0xc9, 0x49, 0xcf, 0x2c, 0x2d, 0x2d, 0x25, 0x37, 0xfa, 0xa0, 0x40, 0x3b, 0x7c, 0xf8, 0xed,
- 0xc8, 0xc8, 0xcc, 0x97, 0x59, 0xd7, 0xae, 0xdf, 0xd8, 0xe3, 0xb3, 0x97, 0xae, 0x11, 0x53, 0x75,
- 0x75, 0x0d, 0x04, 0x1a, 0x6d, 0x40, 0xfb, 0xe3, 0x4f, 0xfd, 0x20, 0xfe, 0x54, 0x34, 0x35, 0x7b,
- 0xf4, 0xed, 0x7b, 0x70, 0x8b, 0x5c, 0x7a, 0x78, 0xbf, 0xf4, 0xdb, 0x72, 0xac, 0x68, 0xc5, 0xd7,
- 0x8f, 0xb5, 0x43, 0x4f, 0xd9, 0x2f, 0x5a, 0xb4, 0x10, 0x3c, 0x03, 0x00, 0x77, 0xc1, 0xc8, 0x4b,
- 0x3c, 0x8a, 0x6a, 0x3a, 0x76, 0xec, 0x92, 0xa5, 0x4b, 0x0f, 0x1d, 0x3a, 0x1c, 0x1b, 0x1b, 0x77,
- 0xe0, 0xc0, 0x81, 0x81, 0x9d, 0x4e, 0x50, 0x4d, 0x0f, 0x1f, 0x3e, 0xba, 0x7e, 0xe3, 0x86, 0x97,
- 0xd7, 0xae, 0x79, 0xf3, 0xe6, 0x31, 0xb3, 0xe0, 0x60, 0x22, 0xb4, 0x02, 0x78, 0x16, 0x0b, 0x0b,
- 0x8b, 0x35, 0x2b, 0x97, 0x3e, 0x3b, 0x3b, 0xa6, 0x21, 0x45, 0xe4, 0xf1, 0x29, 0xb8, 0xaa, 0xd2,
- 0x70, 0xd5, 0x26, 0xd8, 0x43, 0xa4, 0xb2, 0x26, 0xc1, 0x52, 0x91, 0x64, 0xda, 0xf8, 0xf3, 0xb2,
- 0xfd, 0x64, 0x5a, 0x8c, 0xc6, 0x6c, 0x5f, 0xf0, 0x55, 0xd6, 0x2a, 0x02, 0x40, 0xaf, 0x39, 0xaf,
- 0x13, 0x9f, 0x3d, 0xeb, 0xcc, 0x3a, 0x2f, 0x69, 0xc4, 0xee, 0xdb, 0xb7, 0xef, 0x6f, 0xe1, 0x0a,
- 0x14, 0xc1, 0xcf, 0x3e, 0x7f, 0xfe, 0xa2, 0x4d, 0x17, 0x96, 0x50, 0x06, 0xd0, 0x58, 0x6d, 0x6a,
- 0x22, 0x9e, 0x3c, 0x7d, 0x66, 0x6f, 0x6f, 0xcf, 0xcc, 0x77, 0xed, 0x4c, 0x42, 0xb1, 0x1f, 0x3b,
- 0x97, 0x01, 0x36, 0x47, 0x1b, 0x04, 0xd3, 0xde, 0xb8, 0x71, 0x63, 0xcf, 0x1e, 0x1f, 0xa8, 0xba,
- 0x71, 0xe3, 0xc6, 0x0d, 0x1e, 0xac, 0x09, 0xa6, 0x65, 0x96, 0x2d, 0x30, 0x81, 0xd8, 0x77, 0x3f,
- 0xfc, 0x00, 0xd0, 0x7e, 0xdf, 0xab, 0xd7, 0xe4, 0x51, 0x7d, 0x5e, 0xde, 0x52, 0x20, 0x58, 0xca,
- 0x44, 0xf6, 0x00, 0xc6, 0xcd, 0x35, 0x65, 0x2a, 0x05, 0xf9, 0x4e, 0x9d, 0x62, 0x65, 0x49, 0xf7,
- 0x6e, 0x75, 0x2d, 0x61, 0xc0, 0x2c, 0x10, 0x80, 0xa1, 0x98, 0xb3, 0x33, 0xb6, 0x6e, 0xdb, 0x76,
- 0x29, 0x34, 0x34, 0x3d, 0x23, 0xf3, 0x93, 0xc6, 0x1f, 0x81, 0xcf, 0xcb, 0x57, 0xae, 0x80, 0x8f,
- 0x83, 0x83, 0xff, 0x80, 0x4f, 0x41, 0xa4, 0x69, 0x60, 0x30, 0x14, 0x4c, 0x0b, 0x7f, 0x84, 0xa0,
- 0xc9, 0xd9, 0x71, 0xd1, 0x79, 0x2f, 0xdb, 0xd2, 0x38, 0x4d, 0xe2, 0x25, 0x98, 0x53, 0x81, 0xd6,
- 0xae, 0x6a, 0xb4, 0x06, 0x68, 0x03, 0x57, 0x3d, 0x51, 0xc6, 0xdf, 0x1a, 0x34, 0x68, 0x81, 0x70,
- 0x2a, 0xc3, 0x80, 0xd7, 0x03, 0xfb, 0x0d, 0x54, 0xee, 0xc6, 0xf4, 0x9e, 0x21, 0x81, 0xb7, 0xef,
- 0x44, 0x45, 0x35, 0x36, 0x35, 0x7d, 0x21, 0xd5, 0x22, 0x02, 0xaf, 0xa9, 0xa9, 0x61, 0xb3, 0xd9,
- 0x85, 0x85, 0x85, 0x9f, 0x84, 0x58, 0x66, 0x09, 0x0b, 0xb4, 0xd3, 0xdf, 0x1a, 0x07, 0x76, 0x80,
- 0x49, 0x45, 0x9d, 0xae, 0x6d, 0xc5, 0x00, 0xbe, 0x7c, 0x57, 0x57, 0x17, 0x12, 0x12, 0xf2, 0xd9,
- 0x67, 0xd9, 0xb4, 0x9b, 0x46, 0x18, 0x1a, 0xde, 0xbb, 0x77, 0x2f, 0x25, 0x35, 0x2d, 0xf4, 0xf2,
- 0xe5, 0x5d, 0xde, 0xde, 0x0e, 0x8e, 0x8e, 0xe3, 0xc7, 0x4f, 0x40, 0x75, 0xc8, 0xcb, 0xcb, 0xb7,
- 0xf4, 0x1e, 0x20, 0x7f, 0xfb, 0xad, 0xa2, 0xec, 0xf7, 0xe7, 0xf6, 0xc9, 0x35, 0xa1, 0x6a, 0x28,
- 0x02, 0xd1, 0xa5, 0x8d, 0xaf, 0x4b, 0xb0, 0x06, 0x54, 0x3f, 0x51, 0x5b, 0xea, 0x68, 0xd3, 0x05,
- 0x8f, 0xf7, 0x12, 0x75, 0xef, 0xcb, 0x23, 0xe4, 0xb7, 0xb7, 0x5f, 0xb0, 0xdf, 0xd7, 0x2f, 0x3a,
- 0x26, 0x26, 0xbf, 0xa0, 0x00, 0x6f, 0xf7, 0x49, 0x26, 0x82, 0xec, 0xc9, 0xc8, 0xc8, 0x04, 0x8a,
- 0xfc, 0x0f, 0x1c, 0x58, 0xba, 0x6c, 0x99, 0x95, 0x95, 0xd5, 0x98, 0x31, 0x63, 0x26, 0x4d, 0x9a,
- 0x84, 0x08, 0x2d, 0xc0, 0xc3, 0x25, 0xfd, 0xc2, 0x84, 0xfa, 0x94, 0xc1, 0x44, 0xd6, 0x40, 0x98,
- 0x82, 0x56, 0xad, 0x1a, 0xb4, 0x12, 0x90, 0xc4, 0xaa, 0x3e, 0xc1, 0x1e, 0x4a, 0xe4, 0x0c, 0x23,
- 0x72, 0x46, 0x10, 0xb9, 0x46, 0x44, 0xee, 0x70, 0x22, 0x47, 0x87, 0xc8, 0x1e, 0x44, 0xb0, 0x06,
- 0x32, 0xb9, 0x31, 0x5d, 0x3d, 0x70, 0xbb, 0x4a, 0x7f, 0x85, 0x5e, 0xdd, 0x7b, 0xf4, 0x80, 0xb2,
- 0x02, 0x51, 0x18, 0x0c, 0x1d, 0x7a, 0xe6, 0xcc, 0x19, 0xe0, 0xed, 0x0b, 0x15, 0x02, 0x49, 0x92,
- 0xe5, 0x65, 0xe5, 0x15, 0x9d, 0x9d, 0xd1, 0x2d, 0x46, 0x2c, 0x95, 0xb7, 0x6f, 0xdf, 0xde, 0xb1,
- 0x59, 0x00, 0x0f, 0x57, 0x57, 0x57, 0x61, 0xe7, 0x40, 0xeb, 0x6e, 0x01, 0x46, 0x0c, 0xf0, 0xf8,
- 0x7c, 0x04, 0x0b, 0x5f, 0xbe, 0x85, 0x72, 0x9b, 0x04, 0x06, 0x86, 0x6b, 0x8b, 0x8a, 0x8e, 0x4e,
- 0x4c, 0x4a, 0xba, 0x74, 0x29, 0x14, 0x82, 0x6d, 0xf1, 0xe2, 0xc5, 0xa0, 0x7a, 0x84, 0xff, 0x70,
- 0xf4, 0x08, 0x2e, 0x18, 0xda, 0xfc, 0xd7, 0x77, 0xdf, 0xb8, 0xd8, 0xc8, 0xbc, 0x7d, 0xac, 0x42,
- 0xbb, 0x3c, 0x9d, 0x56, 0x6e, 0xee, 0xa5, 0xf2, 0xa6, 0x75, 0x0b, 0x51, 0x89, 0x5d, 0x6d, 0x5e,
- 0x01, 0xd3, 0xbd, 0x8f, 0xa7, 0x1a, 0x3b, 0x76, 0xec, 0x8a, 0x15, 0x2b, 0x83, 0x4e, 0x9e, 0x84,
- 0x7b, 0x7a, 0xfc, 0xf8, 0xf1, 0xa7, 0x1e, 0xb8, 0x86, 0xa0, 0xf2, 0xfc, 0x85, 0x0b, 0x08, 0x54,
- 0xaf, 0x5c, 0xbd, 0xe6, 0xe3, 0xb3, 0xd7, 0xd5, 0x75, 0x95, 0xa3, 0x93, 0x13, 0x3e, 0xfd, 0xbc,
- 0xb7, 0x25, 0x1c, 0xb7, 0xab, 0x4c, 0x30, 0x25, 0xb2, 0x0d, 0x09, 0x36, 0x70, 0x68, 0x40, 0xe5,
- 0x5c, 0x80, 0x93, 0xfe, 0x9b, 0x21, 0x55, 0xea, 0xcb, 0x11, 0x64, 0xae, 0x09, 0x91, 0x37, 0x9a,
- 0xc8, 0x1b, 0x47, 0xe6, 0x4f, 0xa4, 0xf3, 0x58, 0x32, 0x6f, 0x24, 0x99, 0x63, 0x28, 0xca, 0x23,
- 0x38, 0x0f, 0x0d, 0x6d, 0x2d, 0x07, 0x29, 0x28, 0x28, 0x32, 0x7d, 0xbf, 0x68, 0xf8, 0x70, 0x7f,
- 0x3e, 0x3e, 0x3e, 0xd5, 0x00, 0xad, 0x70, 0xfc, 0x54, 0x88, 0x28, 0xd1, 0xa7, 0x38, 0xb5, 0x73,
- 0xaa, 0xe6, 0x5f, 0x62, 0xf8, 0xbd, 0x7f, 0xdf, 0x48, 0xa7, 0x96, 0x9b, 0xff, 0x12, 0x8e, 0xc6,
- 0x4a, 0x14, 0xd8, 0x92, 0x3e, 0x48, 0x20, 0x16, 0x9a, 0xb3, 0x63, 0xb3, 0xc0, 0x73, 0x65, 0xb1,
- 0x58, 0x2d, 0xd3, 0x03, 0xe8, 0x5e, 0x56, 0xd1, 0xcf, 0x29, 0x91, 0x70, 0xe5, 0xca, 0x95, 0xaf,
- 0x0e, 0x57, 0x26, 0xc1, 0x44, 0x36, 0x36, 0x36, 0xe0, 0x1f, 0x68, 0xe3, 0xab, 0xd7, 0xae, 0xfd,
- 0xf6, 0xdb, 0xfe, 0xa5, 0x4b, 0x97, 0x59, 0x5a, 0x4e, 0xd6, 0x37, 0x30, 0x50, 0x52, 0x52, 0x62,
- 0xce, 0x98, 0xd3, 0x56, 0xe9, 0x71, 0xef, 0x98, 0x4a, 0xd3, 0x4b, 0xe8, 0x01, 0x0d, 0x11, 0xc1,
- 0x0e, 0x11, 0xd1, 0x6c, 0xff, 0xf0, 0x20, 0x33, 0xc0, 0x5e, 0x5d, 0x5d, 0x1d, 0x60, 0xe8, 0x3a,
- 0xb3, 0x0d, 0x99, 0x70, 0x1e, 0x4f, 0x35, 0x79, 0xf2, 0xe4, 0xcd, 0x9b, 0x37, 0x5f, 0xbc, 0x14,
- 0x0a, 0xaa, 0x3c, 0x76, 0xec, 0xd8, 0x67, 0x9c, 0x5d, 0x05, 0x19, 0x9c, 0x97, 0x9f, 0xff, 0xf4,
- 0xe9, 0xb3, 0xcb, 0x97, 0xaf, 0x20, 0x76, 0x83, 0x12, 0xfe, 0xfd, 0xf8, 0xb1, 0xfb, 0x21, 0x9e,
- 0x9c, 0x68, 0xc7, 0x86, 0xec, 0x59, 0x64, 0xe1, 0x0c, 0xb2, 0x60, 0x3a, 0x51, 0x68, 0x49, 0x16,
- 0x4c, 0x22, 0xf3, 0xc7, 0x91, 0x79, 0xbf, 0x50, 0x74, 0x4a, 0x61, 0x15, 0xe8, 0x35, 0x24, 0xf3,
- 0x46, 0x93, 0xf9, 0x93, 0xc8, 0x42, 0x6b, 0xe2, 0xd5, 0x5c, 0xb2, 0x78, 0x21, 0xb7, 0xd8, 0x81,
- 0x2c, 0x5e, 0x44, 0x16, 0xcf, 0x23, 0x0b, 0x7f, 0x25, 0x0b, 0x6d, 0xe9, 0x8c, 0x9f, 0xcf, 0x48,
- 0x8d, 0x9e, 0x62, 0x31, 0xd1, 0x58, 0x53, 0x53, 0x53, 0x59, 0x59, 0x59, 0x56, 0x56, 0xae, 0xaf,
- 0x8c, 0x0c, 0xfe, 0x5e, 0xbb, 0x6e, 0x1d, 0x42, 0x7e, 0xe6, 0x4c, 0x37, 0x66, 0x6b, 0xac, 0x56,
- 0xb9, 0xf5, 0x80, 0x91, 0x34, 0xfc, 0x98, 0x71, 0x4f, 0x08, 0x5a, 0xf1, 0x37, 0x1f, 0x5a, 0x5f,
- 0x95, 0x2a, 0x53, 0xa4, 0x3f, 0xdf, 0x7f, 0x00, 0x7f, 0x76, 0x6c, 0x93, 0x83, 0x07, 0x03, 0x04,
- 0xe2, 0x21, 0x2d, 0xe1, 0xa0, 0x80, 0x88, 0x60, 0xdf, 0xbf, 0x87, 0xa9, 0x8d, 0x3b, 0x77, 0xb0,
- 0xf8, 0xe7, 0x25, 0x20, 0x6d, 0xee, 0xdc, 0xb9, 0x8f, 0x1e, 0x3d, 0x4e, 0x49, 0x4d, 0xbd, 0xf1,
- 0xe7, 0x4d, 0x5f, 0x3f, 0x7f, 0x97, 0x15, 0x2b, 0x26, 0x4f, 0xb6, 0xd2, 0xd3, 0xd7, 0xa7, 0x06,
- 0x80, 0x64, 0x7a, 0x1d, 0x71, 0x19, 0x50, 0x97, 0x24, 0x4d, 0xb0, 0x74, 0xce, 0x56, 0xe1, 0xc4,
- 0x6a, 0x40, 0x28, 0xd2, 0x7d, 0x5c, 0x5d, 0x65, 0x2d, 0xad, 0x78, 0xa7, 0x41, 0x5d, 0x5d, 0xdd,
- 0x5f, 0x67, 0xce, 0x84, 0xe0, 0x09, 0x0b, 0x0b, 0xcf, 0xcb, 0xcb, 0x87, 0x56, 0xff, 0x8c, 0x83,
- 0xab, 0x64, 0x64, 0x65, 0xcf, 0x9e, 0x3d, 0x57, 0x58, 0x54, 0x94, 0x94, 0x9c, 0x7c, 0x2f, 0x3e,
- 0x1e, 0xe1, 0x5b, 0x4a, 0x74, 0x28, 0x27, 0xe1, 0x40, 0x1d, 0x7b, 0x37, 0x59, 0xe2, 0xc1, 0x7d,
- 0xb3, 0x8d, 0x5b, 0xb2, 0x89, 0x2c, 0x71, 0x25, 0x39, 0x8e, 0x64, 0xd1, 0x2c, 0xb2, 0xc0, 0x82,
- 0xcc, 0xfd, 0x99, 0x06, 0x2d, 0x0d, 0xd7, 0x02, 0x2b, 0xf2, 0x95, 0x1d, 0xf9, 0xda, 0x95, 0xfb,
- 0x66, 0x2b, 0xb7, 0x6c, 0x17, 0x59, 0xee, 0xc3, 0x2d, 0xdf, 0xcb, 0x2d, 0xdf, 0xcd, 0x2d, 0xf3,
- 0xe2, 0x96, 0x7a, 0xd0, 0xd9, 0x9d, 0xba, 0xf4, 0x7a, 0x7d, 0x46, 0xcc, 0x8a, 0x49, 0xe6, 0xe6,
- 0x23, 0x46, 0x8c, 0x00, 0x56, 0xd1, 0xd0, 0xe0, 0xe6, 0x20, 0x95, 0x77, 0xec, 0xd8, 0x59, 0x55,
- 0xf9, 0x96, 0x39, 0xd9, 0x4d, 0x3a, 0xb7, 0x0c, 0xd3, 0xb7, 0x42, 0xa0, 0xf0, 0xfb, 0x36, 0x77,
- 0x4a, 0xcc, 0x3c, 0xf9, 0xd0, 0xee, 0x3d, 0xe2, 0xed, 0xe5, 0xf1, 0xe9, 0xe4, 0xe4, 0xd4, 0x81,
- 0x41, 0xf4, 0xf4, 0xf4, 0xca, 0xca, 0xca, 0xc4, 0x88, 0x15, 0x0f, 0x66, 0x31, 0x0a, 0xb6, 0xae,
- 0xae, 0x1e, 0x9e, 0xfa, 0x4b, 0x4e, 0xb5, 0xeb, 0x4c, 0x02, 0x1d, 0xa1, 0x36, 0x53, 0xd3, 0xd2,
- 0xd3, 0xd2, 0x33, 0x6e, 0x85, 0x85, 0x1f, 0x38, 0x70, 0xd0, 0xc5, 0x65, 0x85, 0xb9, 0x85, 0x85,
- 0xde, 0x10, 0x5d, 0xb7, 0xe9, 0xba, 0xc5, 0xb7, 0xf4, 0x88, 0x2c, 0x15, 0x5a, 0xa4, 0xe9, 0xd2,
- 0xa0, 0xd5, 0x6a, 0x81, 0x2e, 0x4b, 0xb5, 0xe2, 0xe1, 0x40, 0xd1, 0x5a, 0x5a, 0xd9, 0xae, 0x83,
- 0xd8, 0x6e, 0xf4, 0x1c, 0x15, 0x43, 0x43, 0x23, 0x07, 0x07, 0xc7, 0x83, 0x01, 0x01, 0x77, 0xef,
- 0xc5, 0x67, 0xb3, 0xd9, 0xc3, 0x87, 0x7f, 0xce, 0x62, 0x10, 0x59, 0x59, 0xd9, 0xb8, 0xb8, 0xbb,
- 0xd5, 0x35, 0xb5, 0x6f, 0x4a, 0xcb, 0x5e, 0x15, 0x17, 0x97, 0xe4, 0xbd, 0xac, 0xca, 0x49, 0xa8,
- 0x7f, 0x1d, 0xc3, 0xad, 0x8e, 0xe0, 0xd5, 0xdc, 0xe2, 0xd5, 0xdc, 0xe4, 0x55, 0x5f, 0xe1, 0x56,
- 0x9d, 0x24, 0xcb, 0x77, 0x93, 0xaf, 0x57, 0x91, 0x45, 0x33, 0xc9, 0xfc, 0x09, 0x44, 0xee, 0x48,
- 0x8a, 0x6c, 0x0b, 0x26, 0x93, 0xaf, 0x16, 0x90, 0x6f, 0x36, 0x73, 0x2b, 0x02, 0xb8, 0x6f, 0x2f,
- 0x72, 0x6b, 0xc3, 0xb8, 0xb5, 0x91, 0xbc, 0xda, 0x28, 0x3a, 0xdf, 0xe6, 0xd5, 0x86, 0xd1, 0x19,
- 0x25, 0x5c, 0xe7, 0xbd, 0x3d, 0xc7, 0xad, 0x38, 0xbc, 0x6d, 0xcb, 0x4a, 0xf8, 0x3b, 0x00, 0x75,
- 0xdc, 0xf8, 0xf1, 0xd3, 0xa6, 0x4f, 0x77, 0x76, 0x76, 0xf6, 0xdc, 0xb1, 0x03, 0xde, 0xa1, 0xac,
- 0xbc, 0x5c, 0xbc, 0xda, 0x54, 0xd4, 0x21, 0x2f, 0x44, 0x8b, 0xf4, 0xd0, 0x52, 0x73, 0xeb, 0x1e,
- 0x7b, 0xc9, 0xfb, 0x25, 0x7e, 0xd5, 0x66, 0xe2, 0x9f, 0xb0, 0x63, 0x4a, 0x3c, 0xc0, 0x6a, 0x67,
- 0x6f, 0xff, 0x31, 0x6b, 0x00, 0x8a, 0xc7, 0x8f, 0x9f, 0x20, 0xb9, 0x3c, 0xc9, 0x7d, 0x06, 0xc4,
- 0x5b, 0xd3, 0xe3, 0xe7, 0xf0, 0xd4, 0xe2, 0xbd, 0xe6, 0x80, 0xab, 0x7e, 0xfd, 0xfa, 0x21, 0x80,
- 0x45, 0x98, 0x86, 0x66, 0x88, 0x4f, 0x35, 0x35, 0x35, 0x08, 0x4e, 0x90, 0x24, 0xd3, 0xd7, 0xfa,
- 0x25, 0x09, 0x25, 0x38, 0x39, 0x2d, 0x86, 0x38, 0xc9, 0xc8, 0x7c, 0x09, 0xd0, 0xfa, 0xfb, 0x1f,
- 0x70, 0x73, 0x75, 0xf1, 0x77, 0x9b, 0x93, 0x77, 0xc9, 0xaa, 0x21, 0x73, 0x88, 0x28, 0x04, 0xd6,
- 0xa0, 0x3b, 0xc6, 0x41, 0xb6, 0x08, 0x34, 0x06, 0x53, 0x00, 0xce, 0x56, 0x2d, 0x8d, 0x57, 0xef,
- 0x6a, 0x2b, 0x13, 0x45, 0x1b, 0x5f, 0xf4, 0x37, 0x35, 0x1d, 0x0b, 0x07, 0xf7, 0xfb, 0xa9, 0xe0,
- 0xc4, 0xa4, 0xe4, 0x88, 0x88, 0xdb, 0x30, 0x9a, 0xf4, 0x8b, 0x83, 0x8a, 0x55, 0xe8, 0x04, 0x4b,
- 0xb6, 0xbb, 0xd9, 0xef, 0xc0, 0x81, 0x03, 0xab, 0xde, 0xbe, 0x6d, 0x6a, 0x22, 0x1a, 0xea, 0xeb,
- 0x0b, 0x73, 0xd9, 0xf1, 0xd1, 0xe1, 0x71, 0x91, 0x57, 0xef, 0x45, 0x87, 0xc6, 0xc7, 0x5d, 0x8c,
- 0x8f, 0xbb, 0x10, 0x1f, 0x7b, 0x2e, 0x3e, 0x26, 0xa4, 0xae, 0x22, 0x9a, 0xf7, 0xf6, 0x34, 0x59,
- 0xea, 0x09, 0xa7, 0x4f, 0x14, 0x58, 0x92, 0x79, 0xa6, 0x64, 0xbe, 0x19, 0x59, 0x34, 0x9b, 0x2c,
- 0x59, 0x0b, 0x28, 0x02, 0x99, 0x65, 0xc5, 0x71, 0xd4, 0x9d, 0xd4, 0x4f, 0x42, 0xe9, 0x7c, 0x49,
- 0xf8, 0xf3, 0xb8, 0xf3, 0xf1, 0xb1, 0x67, 0x5f, 0xa6, 0x5c, 0x6b, 0xaa, 0x0a, 0x2b, 0xcf, 0x09,
- 0xf4, 0xde, 0xe1, 0xb6, 0x60, 0xc1, 0xc2, 0x45, 0x0e, 0x0e, 0x90, 0x04, 0x7e, 0x7e, 0xfe, 0xa8,
- 0xfd, 0xf8, 0xf8, 0xfb, 0xb1, 0x71, 0x71, 0x31, 0xb1, 0xb1, 0xf7, 0xef, 0x27, 0xdc, 0x4f, 0x78,
- 0x80, 0x9c, 0x40, 0x67, 0xfc, 0x91, 0x96, 0x9e, 0xce, 0xec, 0xc9, 0x2a, 0x89, 0x52, 0x92, 0xe4,
- 0xe2, 0x7b, 0xc9, 0xdb, 0x90, 0x9f, 0x25, 0x26, 0x56, 0x54, 0x54, 0x8a, 0x87, 0x50, 0xeb, 0xea,
- 0x1b, 0xf0, 0xcd, 0x7d, 0xd1, 0x55, 0x26, 0xc3, 0xc3, 0x22, 0xba, 0x17, 0x08, 0x9a, 0x81, 0x3a,
- 0x5b, 0x5b, 0xdb, 0x8f, 0xe1, 0xe4, 0xe7, 0x9f, 0x7f, 0x66, 0xb3, 0xd9, 0xc2, 0xfe, 0x81, 0x0f,
- 0xad, 0x10, 0x8b, 0x67, 0x40, 0x09, 0x3b, 0x77, 0x7a, 0x99, 0x98, 0x98, 0x98, 0x99, 0x99, 0x01,
- 0x15, 0xab, 0x56, 0xad, 0xf6, 0xf5, 0xf3, 0x43, 0x20, 0x80, 0xe7, 0x87, 0x7b, 0x8a, 0x89, 0x89,
- 0xbd, 0x79, 0xf3, 0x66, 0x50, 0x50, 0x10, 0x1a, 0x23, 0xac, 0xfd, 0x85, 0x88, 0xed, 0x46, 0x07,
- 0x62, 0x6b, 0xd7, 0xae, 0xcd, 0xce, 0x66, 0xa7, 0xa6, 0xa5, 0xdd, 0x0e, 0xfb, 0xf3, 0x6e, 0xe8,
- 0xd1, 0xbc, 0x30, 0xf7, 0xea, 0xc4, 0xd9, 0x44, 0x8e, 0x31, 0x99, 0xab, 0x27, 0xea, 0x99, 0x51,
- 0xa2, 0xb2, 0xb0, 0xe3, 0x51, 0x83, 0xc8, 0xee, 0x5f, 0x12, 0x37, 0x78, 0xf6, 0xec, 0x39, 0x06,
- 0x06, 0x06, 0x10, 0x60, 0x5d, 0x04, 0xb1, 0x10, 0xb1, 0xbd, 0x7b, 0xf7, 0x46, 0x8b, 0x86, 0x20,
- 0xdf, 0xbc, 0x65, 0x0b, 0x82, 0x4a, 0x34, 0x43, 0x98, 0x4e, 0x5e, 0x5e, 0x5e, 0xfa, 0xad, 0xe1,
- 0x5c, 0x42, 0x42, 0x4e, 0x23, 0x43, 0xee, 0xb6, 0x1b, 0x2c, 0x80, 0xf7, 0xf8, 0x02, 0x01, 0x97,
- 0xc7, 0xe3, 0x91, 0xe4, 0xc9, 0xa0, 0x13, 0xc6, 0x46, 0x46, 0x3a, 0xda, 0xda, 0x3a, 0xda, 0x5a,
- 0x3a, 0x3a, 0x74, 0xd6, 0xd6, 0xd2, 0xd7, 0xd7, 0xad, 0x7c, 0x93, 0xc8, 0xab, 0xbd, 0xc9, 0x2d,
- 0xff, 0x8d, 0xe4, 0x2c, 0x25, 0x0a, 0xa6, 0x12, 0x80, 0x6b, 0xc1, 0x54, 0x92, 0xb3, 0x98, 0x5b,
- 0xb6, 0x9b, 0x5b, 0x7d, 0x99, 0xdf, 0xf8, 0xe2, 0x64, 0x90, 0x7f, 0xcb, 0x4f, 0x24, 0xb3, 0x36,
- 0x95, 0x77, 0x78, 0x6e, 0xac, 0x2e, 0x4b, 0x20, 0xab, 0x42, 0x5f, 0x3c, 0x38, 0xe8, 0xe1, 0xb1,
- 0xdd, 0x6b, 0xd7, 0xae, 0xa3, 0xc7, 0x8e, 0x85, 0x47, 0x44, 0xa0, 0x22, 0xc2, 0xc2, 0xc3, 0x67,
- 0xce, 0x9c, 0x89, 0x48, 0x07, 0xba, 0x4b, 0xa7, 0x75, 0x02, 0x2a, 0x8a, 0x39, 0x9c, 0x96, 0x49,
- 0x7d, 0x34, 0x1a, 0x4b, 0xde, 0x94, 0x5a, 0xdb, 0xd8, 0xb4, 0xb9, 0x73, 0xda, 0xb4, 0x69, 0x4f,
- 0x9e, 0x3c, 0x65, 0xee, 0xe4, 0xf1, 0xf8, 0x91, 0x77, 0xa2, 0x8c, 0xf0, 0x16, 0x12, 0x49, 0x5f,
- 0x5f, 0x7f, 0xd3, 0xa6, 0x4d, 0x65, 0xe5, 0x15, 0x7c, 0x1a, 0xb1, 0x10, 0xff, 0xed, 0x22, 0xa4,
- 0x67, 0xcf, 0x9e, 0xde, 0xde, 0xde, 0xef, 0xea, 0xea, 0xc5, 0x27, 0xd4, 0x8b, 0x13, 0x83, 0xd8,
- 0x9a, 0x9a, 0xda, 0x87, 0x8f, 0x1e, 0x27, 0x3c, 0x78, 0x90, 0x93, 0x93, 0xdb, 0xd0, 0xd0, 0x28,
- 0x90, 0x58, 0x6b, 0xc0, 0x64, 0x40, 0x1a, 0xb2, 0x6a, 0xdd, 0xba, 0x75, 0xaa, 0xaa, 0xaa, 0x5f,
- 0x8e, 0xd8, 0x6e, 0x74, 0x68, 0xec, 0xee, 0xee, 0xce, 0xce, 0x66, 0xbd, 0xc9, 0xcf, 0xa8, 0x78,
- 0x19, 0xf9, 0x36, 0xfd, 0x48, 0x63, 0xde, 0x72, 0xca, 0xbb, 0xe5, 0x19, 0x53, 0x61, 0x57, 0x96,
- 0x32, 0xd5, 0xf1, 0x28, 0x1c, 0xdc, 0x51, 0xa4, 0x06, 0x77, 0x58, 0x4a, 0x45, 0x91, 0x3a, 0x90,
- 0xc1, 0x06, 0x06, 0x43, 0xe5, 0xe4, 0xba, 0x04, 0x62, 0xc5, 0x3d, 0xb1, 0xa8, 0xe1, 0x19, 0xb6,
- 0xb6, 0xde, 0xde, 0xbb, 0x51, 0xe9, 0x30, 0xe0, 0x62, 0x67, 0xe7, 0x76, 0xc5, 0x15, 0x48, 0x8c,
- 0x31, 0xe6, 0x1f, 0x7f, 0x84, 0xb4, 0x8b, 0x58, 0x5f, 0x5f, 0x3f, 0x30, 0x0f, 0x9f, 0xcf, 0x27,
- 0x49, 0x72, 0xc9, 0x92, 0x25, 0xd2, 0x3c, 0x6c, 0x60, 0xa0, 0xc7, 0x6b, 0xca, 0xe5, 0xd5, 0x46,
- 0x70, 0xcb, 0x7d, 0x49, 0xce, 0x32, 0x02, 0x71, 0x56, 0xbe, 0x05, 0x08, 0x96, 0x5b, 0xb2, 0x8e,
- 0x5b, 0x79, 0x8c, 0x1a, 0x34, 0x6f, 0x2c, 0x9c, 0x68, 0xd6, 0xd1, 0x5a, 0x3f, 0xef, 0x5d, 0xdb,
- 0xdf, 0x55, 0xbd, 0x80, 0x5a, 0xa8, 0xe6, 0x5c, 0x8c, 0x8e, 0x38, 0x75, 0xee, 0xdc, 0xf9, 0xe8,
- 0xe8, 0x98, 0xac, 0x2c, 0x16, 0x9e, 0x1c, 0x22, 0xe1, 0x63, 0x9a, 0x10, 0x6e, 0xd1, 0xc3, 0xc3,
- 0x83, 0x7e, 0xf8, 0x66, 0x21, 0x24, 0x04, 0xcd, 0xa0, 0x4a, 0x19, 0x19, 0x99, 0x36, 0x77, 0x4e,
- 0x9a, 0x34, 0x29, 0xbf, 0xa0, 0x80, 0xe2, 0x4f, 0x41, 0x33, 0x40, 0x05, 0x00, 0xb7, 0xb9, 0x01,
- 0xe2, 0xf9, 0xe6, 0xad, 0x5b, 0x3c, 0xbe, 0x80, 0x41, 0xec, 0xa8, 0x51, 0xa3, 0xda, 0xfd, 0x1f,
- 0x35, 0xb5, 0xb4, 0xee, 0x44, 0x45, 0x09, 0xc4, 0xe7, 0x7c, 0x4b, 0xc6, 0x7a, 0x12, 0xc2, 0xa0,
- 0x65, 0x51, 0x8c, 0xa0, 0x19, 0x65, 0x0a, 0x8b, 0x15, 0x34, 0xb3, 0x58, 0xac, 0xf5, 0xeb, 0xd7,
- 0x0f, 0x1b, 0x36, 0x0c, 0x6a, 0x41, 0xba, 0x70, 0xe8, 0x87, 0xcf, 0xdb, 0x1e, 0x1c, 0xe1, 0xea,
- 0x9e, 0xdd, 0xbb, 0xca, 0x39, 0xb9, 0x8d, 0xe5, 0xa9, 0x8d, 0x25, 0xd7, 0xb8, 0x25, 0x5e, 0x24,
- 0x22, 0xdc, 0xbc, 0x89, 0x24, 0xdb, 0x80, 0x60, 0x0d, 0x6a, 0x01, 0x2d, 0x35, 0xc4, 0xa3, 0x00,
- 0xdc, 0xe6, 0x47, 0xe8, 0xdb, 0xd9, 0xd9, 0x75, 0x9d, 0x2d, 0x64, 0x45, 0xfb, 0x0f, 0xf7, 0x1b,
- 0x3a, 0x74, 0xd8, 0x7c, 0x3b, 0x3b, 0xc8, 0x9b, 0xbb, 0xf7, 0xee, 0x25, 0x27, 0x3f, 0xb7, 0xb0,
- 0xb0, 0x90, 0x7e, 0x59, 0xb4, 0x50, 0x44, 0x0a, 0xa8, 0x02, 0x1e, 0x9f, 0xbf, 0x69, 0xf3, 0xe6,
- 0x76, 0x2d, 0x49, 0xb1, 0x13, 0x10, 0x2b, 0x68, 0x2e, 0x2a, 0x7a, 0x65, 0x69, 0x69, 0x29, 0x7d,
- 0xc3, 0xb2, 0x65, 0xce, 0x7c, 0x82, 0x0d, 0x41, 0xcb, 0x2d, 0xdb, 0x4b, 0x72, 0x96, 0x90, 0x85,
- 0xd6, 0x14, 0xc1, 0x16, 0x3b, 0x72, 0x4b, 0xbd, 0xb8, 0x6f, 0x2f, 0xf1, 0x1b, 0x5e, 0xa4, 0xbe,
- 0xb8, 0x8f, 0x18, 0xb6, 0x03, 0x9b, 0x07, 0x07, 0x1f, 0x23, 0xea, 0xf3, 0x78, 0xf5, 0x4f, 0x79,
- 0xb5, 0xb1, 0x6f, 0x5f, 0xc7, 0xa5, 0xa7, 0x3c, 0x61, 0xe7, 0xe4, 0x42, 0xc6, 0x80, 0xfa, 0x3a,
- 0x0e, 0x15, 0x35, 0x34, 0x34, 0xa8, 0x2d, 0xd7, 0xa8, 0xf9, 0x25, 0xcd, 0x0c, 0xd8, 0xe0, 0x2c,
- 0xda, 0xdc, 0x03, 0x62, 0x44, 0x24, 0x45, 0x72, 0xb9, 0xcc, 0x0d, 0xf0, 0xd1, 0x6d, 0x8e, 0x40,
- 0xc2, 0x5b, 0xaf, 0x5a, 0xb5, 0xaa, 0xbe, 0xbe, 0x41, 0x5c, 0x08, 0xd8, 0xbc, 0xdd, 0xff, 0x6e,
- 0xfe, 0xfc, 0xf9, 0xc5, 0xc5, 0x1c, 0x31, 0xc1, 0xb6, 0x42, 0x6c, 0xcb, 0xae, 0x32, 0x42, 0x79,
- 0x8c, 0x72, 0x50, 0x1a, 0x28, 0x9d, 0x47, 0x4d, 0x97, 0x6d, 0x4e, 0x4c, 0x4a, 0x1a, 0x3d, 0x7a,
- 0xb4, 0xf4, 0xde, 0x1d, 0x68, 0x8f, 0xa6, 0xa6, 0xa6, 0x47, 0x8f, 0x1e, 0x7d, 0xf2, 0xe4, 0x09,
- 0x64, 0x83, 0xc9, 0xa7, 0x77, 0x32, 0xa0, 0xe5, 0xaa, 0xa9, 0xa9, 0x1e, 0x0e, 0xf0, 0xab, 0xad,
- 0xcc, 0xe3, 0xbe, 0x7b, 0xca, 0xad, 0x0a, 0x41, 0x38, 0x4c, 0x16, 0xcd, 0x23, 0xf3, 0xc6, 0x52,
- 0x7d, 0x8c, 0xac, 0x01, 0xf4, 0xe0, 0x78, 0xcb, 0xc4, 0x8f, 0x37, 0x77, 0x07, 0x3b, 0x3a, 0x3a,
- 0xa1, 0x55, 0x32, 0xb3, 0x64, 0xff, 0xeb, 0x83, 0x08, 0x54, 0x4f, 0x6c, 0xcf, 0x9e, 0x8a, 0xf4,
- 0xf2, 0x2b, 0x67, 0xe7, 0x25, 0xc7, 0x4f, 0x9c, 0x00, 0xe4, 0xae, 0x5d, 0xbf, 0x31, 0x74, 0xe8,
- 0x50, 0xe9, 0x97, 0x35, 0x37, 0x37, 0x67, 0x0c, 0x5b, 0xcc, 0x79, 0x3d, 0x73, 0xe6, 0x2c, 0xe9,
- 0x1b, 0x20, 0x2d, 0x2a, 0xab, 0xde, 0x32, 0x55, 0x09, 0x31, 0x06, 0xf1, 0x23, 0x7d, 0xcf, 0xc5,
- 0x0b, 0xc1, 0xfc, 0xc6, 0x54, 0x6e, 0xf5, 0x25, 0x6e, 0xe9, 0x4e, 0xaa, 0x75, 0x17, 0xda, 0x90,
- 0x45, 0xbf, 0x72, 0x11, 0x85, 0x55, 0x1c, 0xe2, 0xd5, 0xde, 0xe1, 0x37, 0xe5, 0xed, 0xf2, 0xda,
- 0xde, 0x6e, 0x5b, 0x10, 0x57, 0xd9, 0xed, 0x88, 0x1b, 0x02, 0x6e, 0x19, 0xaf, 0x89, 0xc5, 0x6b,
- 0x4c, 0xe3, 0x35, 0x66, 0x95, 0x97, 0xe6, 0x9f, 0x3d, 0x7b, 0x16, 0xff, 0xf5, 0xdf, 0x56, 0x16,
- 0x0c, 0x3e, 0x6f, 0xde, 0xbc, 0xda, 0x77, 0xef, 0xc4, 0x60, 0x43, 0x5d, 0xb4, 0xb9, 0x07, 0x4c,
- 0x72, 0xe8, 0xd0, 0x21, 0x86, 0xf4, 0xe0, 0xf7, 0xd1, 0x0a, 0xda, 0xdc, 0x80, 0xa8, 0xb9, 0xa8,
- 0xa8, 0x88, 0xb1, 0x03, 0x53, 0x48, 0x1b, 0xf9, 0x84, 0x87, 0x87, 0xec, 0x44, 0x6b, 0x8d, 0x8a,
- 0x8a, 0x16, 0x08, 0x19, 0xf6, 0xaf, 0x0f, 0xad, 0x3b, 0xd7, 0xc4, 0x1d, 0x5c, 0x62, 0xd0, 0xf2,
- 0x19, 0x82, 0xe5, 0xf1, 0x09, 0x92, 0xbc, 0x15, 0x16, 0x86, 0x70, 0xac, 0x4d, 0xb4, 0x85, 0x17,
- 0x1f, 0x39, 0xd2, 0x24, 0x34, 0x34, 0xb4, 0xaa, 0xaa, 0x8a, 0x20, 0x09, 0x81, 0x40, 0x50, 0x57,
- 0x57, 0xf7, 0xb7, 0x5d, 0xc1, 0xed, 0x26, 0x94, 0x0c, 0xf8, 0xfd, 0x7e, 0x32, 0xb0, 0xae, 0x9a,
- 0xc5, 0xab, 0xbb, 0xcb, 0xad, 0x0c, 0x22, 0xdf, 0x6c, 0x22, 0x8b, 0xe6, 0x10, 0x79, 0xa6, 0x14,
- 0x68, 0xb3, 0x07, 0x12, 0xac, 0xfe, 0xf4, 0x38, 0x23, 0x85, 0xdb, 0x9a, 0x64, 0x15, 0x37, 0x37,
- 0x37, 0xf8, 0x1d, 0xb4, 0x77, 0xb4, 0xa0, 0xff, 0xba, 0x30, 0x10, 0x6d, 0x7c, 0x31, 0x00, 0x11,
- 0xb7, 0xdb, 0x9a, 0x35, 0x67, 0xcf, 0x9d, 0x4f, 0x4d, 0x4b, 0xf7, 0xf7, 0xf7, 0x6f, 0x97, 0xe5,
- 0xf6, 0xec, 0xd9, 0xc3, 0xd4, 0x14, 0x42, 0x0f, 0xa3, 0xf6, 0xf6, 0xa6, 0xb6, 0xb7, 0xb7, 0xaf,
- 0x13, 0x92, 0x8f, 0xe0, 0xc8, 0x91, 0x23, 0x8c, 0x1f, 0x91, 0x4c, 0xf0, 0x65, 0xac, 0x97, 0x4f,
- 0x78, 0xf5, 0x8f, 0x79, 0x55, 0xa7, 0xb8, 0x6f, 0x36, 0x53, 0x7d, 0x59, 0x85, 0x36, 0x04, 0x3e,
- 0x4b, 0xb6, 0xa2, 0xb1, 0xe3, 0xfb, 0xca, 0x32, 0xd6, 0x58, 0xd3, 0xd1, 0x1d, 0x84, 0xc6, 0x88,
- 0xec, 0x12, 0x12, 0xee, 0xf2, 0x79, 0x35, 0x7c, 0xa2, 0x94, 0x4f, 0xbe, 0x6e, 0x6a, 0x28, 0x09,
- 0x0e, 0x3e, 0x8e, 0x98, 0xba, 0x93, 0x95, 0x85, 0x37, 0xbd, 0x70, 0xf1, 0x22, 0xe3, 0x05, 0x00,
- 0x0f, 0xe9, 0x03, 0xb9, 0x50, 0x2f, 0x08, 0xc1, 0xf0, 0x9a, 0x04, 0x41, 0x42, 0x45, 0xb4, 0x69,
- 0x3b, 0xe0, 0xdb, 0xb3, 0x67, 0xcf, 0x89, 0xe1, 0xca, 0x14, 0xc2, 0x10, 0x3b, 0x3e, 0x01, 0x54,
- 0x93, 0x91, 0x23, 0x3d, 0x3d, 0x3d, 0xd3, 0xd2, 0x33, 0x60, 0x01, 0x46, 0x30, 0xb7, 0x11, 0x04,
- 0x12, 0xdd, 0xc5, 0x12, 0xf3, 0x0a, 0xde, 0x0b, 0x09, 0x96, 0x20, 0xb9, 0xe1, 0xe1, 0x11, 0x3a,
- 0x52, 0xa4, 0x0d, 0x01, 0xe0, 0xe2, 0xb2, 0xbc, 0xb2, 0xb2, 0x82, 0xcf, 0xe7, 0xd2, 0x99, 0xd2,
- 0x0e, 0x88, 0x70, 0x6d, 0x66, 0xcc, 0xe8, 0xe4, 0x8b, 0x4b, 0x27, 0x3c, 0xed, 0xe9, 0x90, 0x13,
- 0x4d, 0x75, 0x59, 0xfc, 0x77, 0x31, 0xdc, 0xca, 0xe3, 0x64, 0xe9, 0x36, 0x92, 0xe3, 0x40, 0x14,
- 0x4c, 0xa1, 0x46, 0x70, 0x72, 0x47, 0x10, 0x39, 0xba, 0xd4, 0x88, 0x2d, 0x4b, 0xb9, 0x21, 0x5d,
- 0x39, 0x70, 0xbf, 0x0b, 0x5a, 0x3a, 0xc4, 0x3c, 0x70, 0xfe, 0xb1, 0x79, 0xb6, 0xff, 0xb1, 0xc4,
- 0x88, 0x58, 0x2d, 0x2d, 0xea, 0x58, 0x58, 0x77, 0x77, 0x8f, 0x1b, 0x7f, 0xfe, 0x09, 0x6b, 0xaf,
- 0x5e, 0xed, 0x26, 0xed, 0x5e, 0xa1, 0x48, 0x21, 0x18, 0x98, 0xca, 0x3a, 0x73, 0xf6, 0x6c, 0xbb,
- 0xd1, 0xeb, 0xe1, 0xc3, 0x81, 0xb0, 0x39, 0x6e, 0x40, 0xc8, 0x80, 0xb0, 0x54, 0x1a, 0x78, 0x13,
- 0x26, 0x8c, 0x7f, 0x5d, 0x9c, 0x4a, 0xb5, 0xeb, 0x8a, 0x40, 0xb2, 0x64, 0x0d, 0x59, 0x34, 0x97,
- 0x1a, 0x17, 0xe0, 0x38, 0x71, 0xcb, 0x7c, 0xb8, 0xd5, 0xd7, 0xf8, 0x4d, 0x19, 0xb7, 0x6e, 0x5e,
- 0x54, 0x57, 0xef, 0x88, 0x2d, 0x8d, 0x8d, 0x8d, 0x9f, 0x3f, 0x4f, 0xe2, 0xf3, 0x1b, 0x79, 0xdc,
- 0x77, 0x7c, 0x5e, 0x2d, 0x8b, 0x95, 0x66, 0x65, 0xd5, 0x7e, 0xe0, 0xd3, 0x6e, 0x52, 0x52, 0x52,
- 0x82, 0x1f, 0xa1, 0x63, 0xfc, 0xe6, 0x82, 0xc2, 0x42, 0xe9, 0x27, 0x44, 0xf9, 0x95, 0x95, 0x55,
- 0x78, 0xcd, 0x47, 0x8f, 0x1e, 0xeb, 0xe9, 0xe9, 0xb5, 0xb9, 0x6a, 0x6d, 0x6d, 0x83, 0x26, 0x29,
- 0x10, 0x88, 0x75, 0x45, 0x73, 0xd5, 0xff, 0x12, 0x77, 0xa5, 0x41, 0x51, 0x5c, 0xed, 0xfa, 0x67,
- 0xee, 0xad, 0xa4, 0xea, 0xab, 0xfa, 0x72, 0xab, 0x72, 0x73, 0x5d, 0xbe, 0xba, 0x31, 0x1a, 0xaf,
- 0x89, 0x0b, 0x5a, 0x51, 0xf3, 0x89, 0x1a, 0x35, 0x5e, 0x83, 0x71, 0x41, 0xa2, 0x46, 0x13, 0x8d,
- 0x6b, 0xdc, 0x89, 0x1b, 0x0a, 0xa2, 0xc1, 0x2d, 0x8a, 0xb8, 0xc6, 0x25, 0xc6, 0x0d, 0x41, 0x11,
- 0x05, 0x5c, 0x40, 0x04, 0x11, 0x86, 0x5d, 0x51, 0x01, 0x05, 0x91, 0x7d, 0x9b, 0x61, 0x99, 0x7d,
- 0x5f, 0xfb, 0x74, 0x0f, 0x5a, 0x75, 0x9f, 0xd3, 0xad, 0xed, 0xd0, 0x33, 0xf1, 0xc3, 0x84, 0xd4,
- 0x3d, 0x35, 0x65, 0x8d, 0x43, 0x4f, 0x4f, 0xf7, 0x39, 0xcf, 0x79, 0xdf, 0xe7, 0x79, 0xdf, 0xf7,
- 0x9c, 0xd6, 0x1b, 0xde, 0xe2, 0x67, 0xe2, 0xe4, 0xc9, 0x93, 0x8f, 0x1e, 0x3b, 0xd6, 0xd4, 0x2c,
- 0xe7, 0x17, 0xc1, 0xbc, 0x2a, 0x26, 0xf4, 0x34, 0xb0, 0x9e, 0xa1, 0x5e, 0x49, 0xf0, 0x8d, 0x9e,
- 0x90, 0x73, 0x57, 0x55, 0x57, 0x4f, 0x99, 0x32, 0x55, 0xd2, 0xf9, 0xd0, 0x0b, 0xa1, 0xa1, 0xa1,
- 0x26, 0x93, 0x1e, 0xe2, 0x80, 0xe3, 0x5c, 0xfc, 0x0b, 0x9d, 0xcc, 0x95, 0x95, 0x95, 0xfd, 0xc9,
- 0xe7, 0x86, 0xe0, 0xcc, 0x37, 0x93, 0xe3, 0x19, 0x5b, 0x15, 0x6b, 0xc9, 0x22, 0xfa, 0xb3, 0x8c,
- 0x2a, 0xc2, 0xd5, 0xba, 0xd4, 0xd5, 0x34, 0x85, 0x1a, 0xdb, 0xfa, 0x61, 0xae, 0xba, 0x81, 0x34,
- 0xe4, 0x55, 0xdd, 0xb3, 0xfd, 0xde, 0x87, 0x91, 0xdb, 0xbe, 0x01, 0x42, 0xd0, 0x21, 0x70, 0x28,
- 0x42, 0x1d, 0xd7, 0xff, 0x0b, 0x68, 0xc5, 0xf5, 0xad, 0xe0, 0xd5, 0x98, 0x44, 0xfb, 0xa2, 0xa2,
- 0x64, 0xb2, 0x6c, 0xa8, 0xd7, 0xe9, 0xd3, 0x7d, 0xcc, 0x5c, 0x98, 0x23, 0x0c, 0x31, 0x46, 0x03,
- 0x14, 0x6e, 0xfb, 0xf6, 0xed, 0xde, 0x90, 0x86, 0x84, 0x81, 0x2e, 0xc3, 0x78, 0xa1, 0xf3, 0x6b,
- 0xeb, 0xea, 0xa0, 0xc1, 0xbd, 0x4f, 0xb2, 0x7e, 0x7d, 0xb0, 0x51, 0xf7, 0x94, 0x35, 0xa7, 0x11,
- 0xed, 0x01, 0xa6, 0x6d, 0x15, 0x45, 0xac, 0x7c, 0x36, 0x4d, 0x19, 0x68, 0x8f, 0xb1, 0x96, 0x3b,
- 0x2e, 0x5b, 0xed, 0xa6, 0x90, 0x1f, 0xc5, 0xd4, 0x30, 0xec, 0x3c, 0x94, 0x14, 0x18, 0xb5, 0xa7,
- 0x38, 0x0a, 0x08, 0x08, 0xa8, 0xae, 0xa9, 0xe6, 0xed, 0x0c, 0x06, 0x8e, 0xb9, 0x73, 0xe7, 0xf6,
- 0xa0, 0x41, 0x9d, 0x1c, 0x37, 0xbe, 0x1e, 0x14, 0x14, 0xb4, 0x89, 0x6f, 0xf3, 0xe6, 0xcd, 0x43,
- 0xf7, 0x7a, 0xfe, 0x15, 0x3e, 0x3d, 0x3b, 0x27, 0x57, 0xe4, 0xa8, 0x92, 0xcb, 0xc3, 0x4d, 0xcd,
- 0x9f, 0x3f, 0x9f, 0xd6, 0xa6, 0x1a, 0x0c, 0xab, 0x56, 0xad, 0x92, 0x30, 0x58, 0x10, 0x0f, 0x99,
- 0x4c, 0x26, 0x18, 0x4f, 0x51, 0xc1, 0xd5, 0x37, 0x34, 0x60, 0xdc, 0x77, 0xee, 0xdc, 0x59, 0x5d,
- 0x53, 0x4b, 0xf8, 0x67, 0xcf, 0xbf, 0xaa, 0x7d, 0x15, 0xf2, 0x11, 0x9d, 0x13, 0x16, 0x2f, 0x69,
- 0x80, 0xe4, 0x45, 0xbf, 0xe5, 0x70, 0x3a, 0xbd, 0x1d, 0x53, 0x9f, 0x3e, 0x7d, 0xf6, 0xed, 0xdb,
- 0xc7, 0x5b, 0x57, 0xc0, 0xd5, 0xc9, 0xbf, 0xe8, 0x8d, 0x13, 0xc2, 0xac, 0x5c, 0xb9, 0xd2, 0x27,
- 0x0e, 0xdf, 0xa8, 0xf9, 0xf9, 0x0d, 0xbe, 0x9d, 0x96, 0xc8, 0x81, 0x62, 0x51, 0xd0, 0x9e, 0x63,
- 0xd4, 0xa0, 0x6a, 0x8b, 0xa0, 0x2c, 0x5c, 0x0d, 0xfe, 0xae, 0xba, 0x61, 0x7c, 0xa5, 0x47, 0x3f,
- 0xe7, 0xd3, 0x1e, 0x15, 0x37, 0xfd, 0xb6, 0xac, 0x9d, 0x0d, 0x5a, 0x28, 0x56, 0x3e, 0xd3, 0x05,
- 0x8f, 0x3c, 0xc1, 0x90, 0xb4, 0xbf, 0xb4, 0xc4, 0x4b, 0x88, 0xc4, 0xa2, 0xc3, 0xfd, 0xfd, 0xfd,
- 0x7f, 0xf8, 0x61, 0xd9, 0x6f, 0xa7, 0x4e, 0x3d, 0x78, 0xf0, 0x10, 0x8a, 0x7b, 0xc8, 0x10, 0x3f,
- 0xef, 0x5b, 0x9b, 0xfd, 0xcd, 0x37, 0x1a, 0x2d, 0x8d, 0xe7, 0x34, 0xcb, 0x15, 0x80, 0xb7, 0xf7,
- 0x01, 0x50, 0x01, 0xd5, 0x35, 0x35, 0x82, 0xf1, 0x01, 0x74, 0xbd, 0x19, 0x20, 0x6e, 0x33, 0x36,
- 0xe6, 0xb4, 0xcb, 0x5a, 0xc5, 0x9a, 0xae, 0x12, 0xcd, 0xcf, 0x4c, 0xeb, 0x32, 0x46, 0x31, 0x87,
- 0x51, 0x2c, 0x60, 0x94, 0x61, 0xc4, 0x10, 0x03, 0x25, 0x55, 0x53, 0x75, 0x77, 0xd2, 0xa4, 0x2f,
- 0xc4, 0xe3, 0x03, 0x02, 0x26, 0xe3, 0x7a, 0xd2, 0xd3, 0x6f, 0x7f, 0xe8, 0xb1, 0x15, 0x1b, 0x10,
- 0xd5, 0xd2, 0xda, 0x02, 0x0b, 0xc3, 0xbf, 0xdc, 0x67, 0xcf, 0x9e, 0x95, 0x48, 0xe6, 0x01, 0x03,
- 0x06, 0xa4, 0xa7, 0xa7, 0x83, 0xe3, 0x99, 0xcc, 0x96, 0x4b, 0x97, 0x2e, 0x49, 0x66, 0x16, 0xee,
- 0xb4, 0x5d, 0xa9, 0x12, 0x10, 0xeb, 0x3d, 0xe2, 0xe8, 0x8d, 0x5f, 0x7f, 0xfd, 0x15, 0x50, 0xbc,
- 0x71, 0x23, 0x59, 0x52, 0x05, 0x04, 0xe4, 0x87, 0x87, 0x6f, 0x35, 0x99, 0xcc, 0x22, 0x26, 0x05,
- 0xd0, 0x56, 0x55, 0x55, 0x45, 0x9f, 0x3f, 0x6f, 0x30, 0x9a, 0x84, 0xd8, 0xac, 0x58, 0x9d, 0xf5,
- 0x22, 0x00, 0xeb, 0x03, 0xae, 0xf4, 0x99, 0xb6, 0x75, 0xf5, 0xf5, 0xf7, 0xef, 0x3f, 0xc8, 0x92,
- 0xc9, 0xd0, 0xdb, 0x19, 0x19, 0x19, 0x78, 0x83, 0x57, 0xd2, 0xd5, 0xab, 0xd3, 0xa6, 0x4d, 0xf3,
- 0xfc, 0x51, 0x78, 0xe1, 0xbd, 0x7b, 0xf7, 0xea, 0x0d, 0x7a, 0x1a, 0x42, 0x78, 0x61, 0x60, 0x29,
- 0x62, 0xdd, 0x6e, 0xf6, 0xea, 0xd5, 0x24, 0x9f, 0xe1, 0xc7, 0x37, 0x6d, 0xb8, 0xaf, 0xcf, 0xc7,
- 0x8e, 0x2e, 0xc8, 0xbb, 0xc5, 0x39, 0x6b, 0x58, 0xb3, 0x8c, 0x82, 0x56, 0x19, 0x0e, 0x21, 0x0c,
- 0x7a, 0xc0, 0x80, 0x1e, 0xd4, 0xf9, 0xf1, 0xcc, 0xb6, 0x8f, 0xe5, 0xf1, 0x3f, 0x6e, 0x45, 0x4f,
- 0xfe, 0x61, 0xf1, 0xa2, 0x71, 0xe3, 0xc6, 0xc1, 0x76, 0xc1, 0x98, 0x80, 0x5f, 0x41, 0xfb, 0x4c,
- 0x98, 0x30, 0x61, 0xe2, 0xcb, 0x06, 0xae, 0x8b, 0xbf, 0x42, 0x01, 0xc1, 0xc2, 0xfc, 0x45, 0x02,
- 0x8d, 0x46, 0x62, 0xff, 0xf6, 0xb7, 0x0f, 0xfb, 0xf6, 0x85, 0x4c, 0xd8, 0x18, 0x12, 0x12, 0x7f,
- 0xf9, 0x72, 0xc5, 0xd3, 0xca, 0xe8, 0xe8, 0xf3, 0xde, 0x01, 0x1f, 0xb4, 0x7d, 0xfb, 0xa2, 0x84,
- 0x98, 0x61, 0x71, 0x71, 0x89, 0xcf, 0xa2, 0xb8, 0xa5, 0x4b, 0x97, 0xaa, 0x54, 0x6a, 0x41, 0x41,
- 0xc4, 0xc5, 0xc5, 0x79, 0x57, 0xd1, 0xe0, 0x1e, 0xf3, 0x72, 0x6e, 0x71, 0xf6, 0x72, 0x62, 0x88,
- 0xa3, 0xe9, 0x83, 0xd6, 0xa5, 0x34, 0xc9, 0xd5, 0xba, 0x8a, 0x68, 0x22, 0x89, 0x39, 0x99, 0x75,
- 0x56, 0x25, 0x5c, 0x89, 0xfe, 0xe0, 0x83, 0xff, 0x16, 0x0e, 0x06, 0x57, 0xd9, 0xba, 0x6d, 0x1b,
- 0x40, 0x79, 0xfb, 0xf6, 0x6d, 0x70, 0x57, 0xf1, 0x24, 0x1b, 0x36, 0x6c, 0x04, 0x3c, 0x84, 0x79,
- 0x61, 0xb6, 0x58, 0xb7, 0x6c, 0xd9, 0x22, 0xf1, 0xec, 0x53, 0xa6, 0x4c, 0xa9, 0xaa, 0xa6, 0x13,
- 0xc7, 0xe1, 0x74, 0x49, 0xaa, 0xaa, 0x30, 0x3a, 0xf3, 0xe6, 0xcd, 0x67, 0x79, 0x2b, 0xe9, 0x74,
- 0xb9, 0xbc, 0x1f, 0x13, 0x03, 0xa3, 0xfa, 0xf8, 0xf1, 0x63, 0x45, 0x4b, 0xcb, 0xf7, 0xdf, 0x7f,
- 0x2f, 0x31, 0xce, 0x63, 0xc6, 0x8e, 0x2d, 0x29, 0x2d, 0x15, 0xa0, 0xde, 0xe1, 0x11, 0x92, 0x72,
- 0x3a, 0x5d, 0xf8, 0x21, 0x91, 0x24, 0x88, 0xf1, 0xde, 0x17, 0xd9, 0x5e, 0x8f, 0x58, 0x96, 0x10,
- 0xce, 0x02, 0x59, 0xc5, 0x4c, 0x81, 0xa9, 0xef, 0xdb, 0xb7, 0x1f, 0x8c, 0x36, 0xfa, 0x04, 0x77,
- 0xf7, 0x01, 0xdf, 0xc0, 0xc6, 0x3d, 0x83, 0x03, 0x60, 0x8c, 0xb8, 0x0c, 0xad, 0x4e, 0x47, 0xdd,
- 0x16, 0x88, 0x2b, 0x75, 0x2b, 0x00, 0x2d, 0xe3, 0x76, 0x93, 0xdc, 0xdc, 0x9c, 0xa1, 0x43, 0x87,
- 0xfe, 0xf9, 0x44, 0x98, 0xf8, 0x43, 0x5f, 0x7d, 0xf5, 0xe5, 0xa3, 0x92, 0x3c, 0xce, 0x59, 0x4b,
- 0xcc, 0x59, 0xac, 0xee, 0x24, 0x51, 0x86, 0x31, 0x8a, 0xf9, 0x34, 0x4e, 0x4b, 0x73, 0xe8, 0x7e,
- 0x7c, 0x81, 0xc1, 0x07, 0x86, 0xd2, 0x3e, 0xe7, 0x8f, 0x7f, 0xb7, 0x70, 0xe1, 0x42, 0xc0, 0x72,
- 0xcc, 0x98, 0x31, 0xcb, 0x97, 0x2f, 0x8f, 0x8e, 0x8e, 0x86, 0x71, 0xb8, 0xe3, 0xd1, 0x52, 0x53,
- 0x53, 0xa1, 0x5b, 0xc1, 0x1f, 0x70, 0x23, 0xdd, 0x0e, 0x5a, 0xf1, 0xb9, 0x5a, 0x03, 0x07, 0x0e,
- 0x9a, 0x39, 0x73, 0xe6, 0xae, 0x5d, 0xbb, 0xd2, 0xd2, 0xd2, 0x2a, 0x2b, 0xab, 0x80, 0x01, 0x9f,
- 0xf7, 0x85, 0x49, 0xb4, 0x78, 0x09, 0xda, 0x52, 0x5c, 0x8f, 0x44, 0x8f, 0xe0, 0x96, 0xa7, 0x4e,
- 0x9d, 0x5a, 0x56, 0x5e, 0xce, 0x53, 0x02, 0xb7, 0xd1, 0x68, 0x0a, 0x0d, 0x0d, 0xf3, 0x3e, 0x43,
- 0x40, 0xc0, 0xa4, 0xea, 0xca, 0xbb, 0xac, 0xbd, 0x88, 0x17, 0xa7, 0xa1, 0x4c, 0xeb, 0x12, 0xa6,
- 0x65, 0x09, 0x69, 0xdf, 0x8c, 0xff, 0xb2, 0xd6, 0x02, 0x93, 0xbe, 0x66, 0xe3, 0xc6, 0xb5, 0xe2,
- 0x28, 0xc0, 0xae, 0xa6, 0xa5, 0xa5, 0x03, 0x18, 0x87, 0x0e, 0x1d, 0x12, 0x1d, 0x25, 0xfe, 0x0a,
- 0x17, 0x29, 0x84, 0x9e, 0xf0, 0xaa, 0xaf, 0x6f, 0x98, 0xde, 0x99, 0x7b, 0xe0, 0x00, 0xf0, 0x67,
- 0xb0, 0x68, 0x8a, 0x67, 0xb3, 0x45, 0xb2, 0x87, 0x1b, 0x66, 0xe2, 0x91, 0x97, 0x71, 0x80, 0x87,
- 0xc5, 0x25, 0x9e, 0x13, 0x41, 0x68, 0x70, 0xc1, 0x0e, 0x87, 0x33, 0x26, 0x26, 0x46, 0x32, 0x67,
- 0xa9, 0xb2, 0x3e, 0x73, 0x06, 0x60, 0xf3, 0xdc, 0xa1, 0x45, 0x70, 0xe5, 0x22, 0xa7, 0xe5, 0x3a,
- 0xdb, 0x58, 0xcf, 0x9c, 0xc1, 0xab, 0x42, 0x82, 0x8e, 0x67, 0x18, 0xe2, 0xae, 0x84, 0x35, 0x84,
- 0x8b, 0xc9, 0xe1, 0x09, 0x0c, 0xdf, 0xab, 0x1c, 0x0f, 0x5a, 0xd6, 0x66, 0xb3, 0x5e, 0xbd, 0x7a,
- 0x15, 0x76, 0xac, 0xbb, 0xe0, 0x2a, 0x34, 0x78, 0xa2, 0xa0, 0xa0, 0xc0, 0xca, 0xa7, 0xf7, 0x59,
- 0x67, 0x2d, 0x6b, 0x4e, 0x27, 0xda, 0x5f, 0x31, 0x2e, 0x8c, 0xe2, 0x3b, 0x1a, 0x2a, 0xaf, 0x1f,
- 0x49, 0xeb, 0x3f, 0x79, 0x4b, 0x6b, 0xaf, 0xe8, 0x75, 0xe1, 0xe4, 0xa2, 0x4d, 0x21, 0x1b, 0x0f,
- 0x1c, 0x38, 0x50, 0x58, 0x58, 0x68, 0x30, 0x18, 0x6c, 0x36, 0x9b, 0x46, 0xa3, 0x69, 0x6b, 0x6b,
- 0x53, 0xa9, 0x54, 0xf0, 0x6b, 0x2e, 0x97, 0x0b, 0xef, 0x13, 0x13, 0x13, 0xc1, 0xe5, 0x60, 0xb2,
- 0xba, 0x97, 0x1e, 0x08, 0xdb, 0x0a, 0x51, 0x79, 0x3b, 0x7c, 0xf8, 0x82, 0x85, 0xb4, 0x9c, 0x20,
- 0x2f, 0x3f, 0xbf, 0xb4, 0xb4, 0xd4, 0x27, 0x89, 0x7d, 0x4d, 0xc3, 0x85, 0x81, 0x24, 0x54, 0x54,
- 0x54, 0x60, 0xc4, 0x04, 0x67, 0x0d, 0xba, 0x0b, 0x19, 0xe2, 0x7d, 0xe4, 0xba, 0x75, 0x6b, 0x74,
- 0xea, 0x27, 0x94, 0x2f, 0x69, 0x8e, 0x30, 0xed, 0xeb, 0x28, 0x62, 0x5b, 0x57, 0x31, 0xea, 0xdd,
- 0x2c, 0xcd, 0x73, 0x95, 0x3f, 0x2e, 0xc9, 0x1b, 0x33, 0x66, 0xb4, 0x70, 0x24, 0x86, 0x03, 0xee,
- 0x5b, 0xa3, 0x01, 0x79, 0x73, 0xaf, 0x58, 0xb1, 0x42, 0x4c, 0x0a, 0x00, 0x48, 0x67, 0xce, 0x9c,
- 0x15, 0x41, 0x72, 0xaf, 0xa8, 0x48, 0x22, 0xab, 0x81, 0xed, 0xe3, 0xc7, 0x4f, 0x08, 0xc1, 0x7f,
- 0xb9, 0x42, 0x21, 0x29, 0xe6, 0x87, 0xec, 0x02, 0x4b, 0x17, 0x40, 0x75, 0xea, 0xf4, 0x69, 0xef,
- 0x50, 0x06, 0x28, 0x07, 0x88, 0x0d, 0x0c, 0x88, 0xe7, 0x87, 0xf8, 0xf5, 0xf9, 0xf3, 0xbf, 0x57,
- 0x2a, 0x55, 0x9d, 0xd6, 0x12, 0x8a, 0x88, 0xed, 0x78, 0x85, 0x58, 0x40, 0x0a, 0xaa, 0x0d, 0x96,
- 0xff, 0x95, 0xe6, 0xea, 0x14, 0x7a, 0xa5, 0x39, 0xac, 0xae, 0xd7, 0xbd, 0x00, 0x96, 0xe8, 0x81,
- 0x97, 0x37, 0x4b, 0x21, 0xab, 0x68, 0x51, 0x44, 0xee, 0x8b, 0xec, 0x7a, 0x60, 0xe4, 0x8d, 0x1a,
- 0xfa, 0xfc, 0xbb, 0xef, 0xe6, 0x36, 0xd4, 0x3d, 0xe6, 0x1c, 0x15, 0xac, 0xf9, 0x26, 0xd1, 0x1d,
- 0x25, 0xca, 0x8d, 0xa0, 0x6d, 0xae, 0xc6, 0x2f, 0x98, 0xfa, 0x11, 0x3c, 0x68, 0xf9, 0x8a, 0xd9,
- 0x3a, 0xbf, 0x7c, 0x59, 0x74, 0x65, 0x65, 0x25, 0xb0, 0xaa, 0x54, 0x2a, 0x01, 0xce, 0xad, 0x5b,
- 0xb7, 0xae, 0x5e, 0xbd, 0x1a, 0xaa, 0x21, 0x36, 0x36, 0xb6, 0xa9, 0xa9, 0x89, 0x10, 0x82, 0xcf,
- 0xa3, 0xa2, 0xa2, 0xe0, 0x47, 0xba, 0xb7, 0x72, 0x06, 0x46, 0x1b, 0xb4, 0xad, 0x77, 0xef, 0xde,
- 0xf0, 0x77, 0x50, 0x19, 0x40, 0x42, 0x71, 0x49, 0x69, 0x41, 0x41, 0xe1, 0x1b, 0x55, 0x71, 0xa3,
- 0xf3, 0x97, 0x2c, 0x59, 0x5c, 0x53, 0x5b, 0xed, 0x76, 0xb3, 0x62, 0xd4, 0x05, 0xb0, 0x87, 0xb3,
- 0x93, 0x1c, 0x09, 0x37, 0x71, 0xe2, 0xf8, 0x41, 0xe2, 0x00, 0x59, 0x4a, 0x25, 0xea, 0x48, 0xa6,
- 0x7d, 0x0d, 0x65, 0x05, 0x6d, 0xeb, 0x69, 0xdd, 0x0b, 0x26, 0xb5, 0xbd, 0xee, 0x72, 0x7c, 0x0c,
- 0x0c, 0xbe, 0x70, 0xf0, 0xdb, 0xef, 0xbc, 0xb3, 0x26, 0x38, 0x18, 0x78, 0xd0, 0xe9, 0x0d, 0x53,
- 0xa7, 0xbe, 0xa2, 0x76, 0xb0, 0x8a, 0xf4, 0xd1, 0xb4, 0xfc, 0x20, 0x12, 0x96, 0x4d, 0x4c, 0x4c,
- 0x92, 0x58, 0x7b, 0x61, 0x55, 0x02, 0xcb, 0xcf, 0x9c, 0x1b, 0xc9, 0xc9, 0x92, 0x6b, 0xf8, 0xa8,
- 0x7f, 0x7f, 0x81, 0x70, 0xe2, 0x00, 0xb8, 0x66, 0xef, 0xa8, 0x2f, 0x48, 0xec, 0x9e, 0x3d, 0x7b,
- 0x24, 0xd4, 0xf7, 0x7f, 0x06, 0x0c, 0xb8, 0x93, 0x99, 0xf9, 0xaa, 0x5c, 0xf0, 0x59, 0xa7, 0xda,
- 0x2d, 0x21, 0x78, 0x62, 0xb1, 0x58, 0x4b, 0x4b, 0x1f, 0x5d, 0xbc, 0x18, 0xb7, 0x7e, 0xfd, 0x86,
- 0xf2, 0x27, 0x4f, 0x7c, 0xd6, 0xbd, 0xe0, 0xc3, 0xcc, 0x4c, 0xdf, 0x31, 0x6a, 0x9f, 0x0d, 0xc2,
- 0xbc, 0xa9, 0xa9, 0x99, 0x32, 0x0d, 0xca, 0x61, 0x98, 0xec, 0xec, 0xec, 0x45, 0x8b, 0x16, 0xf9,
- 0x24, 0x6c, 0x5d, 0x69, 0x3d, 0x7b, 0xf6, 0x9c, 0x30, 0x61, 0x7c, 0x60, 0xe0, 0x74, 0x00, 0xe9,
- 0xf7, 0xec, 0x33, 0x88, 0xd0, 0x8a, 0x15, 0x3f, 0x68, 0xd5, 0xd5, 0xac, 0xe3, 0x11, 0x31, 0x5d,
- 0x23, 0x9a, 0x43, 0x4c, 0xdb, 0x5a, 0x46, 0x3e, 0xcb, 0x45, 0xab, 0x95, 0x86, 0xf3, 0x95, 0xf6,
- 0xc3, 0x48, 0xcb, 0x1c, 0xb7, 0x25, 0x99, 0x71, 0xd9, 0xd5, 0x6a, 0x35, 0xdc, 0x1f, 0x5c, 0x33,
- 0x6c, 0x7e, 0x41, 0x41, 0xc1, 0xdd, 0xbb, 0x77, 0x4f, 0x9d, 0x3a, 0x05, 0x05, 0xda, 0xdc, 0xdc,
- 0xcc, 0x30, 0x50, 0xc4, 0x77, 0x40, 0xcf, 0xde, 0xf9, 0x73, 0x7b, 0x81, 0x4a, 0x1a, 0x64, 0x17,
- 0x68, 0x1b, 0x9c, 0x2f, 0x48, 0x6c, 0x48, 0xc8, 0xa6, 0x4b, 0xf1, 0xf1, 0x15, 0x4f, 0x9f, 0x26,
- 0x25, 0x25, 0x75, 0xbd, 0xf2, 0x0d, 0x47, 0x82, 0xcc, 0x28, 0x14, 0x72, 0x1e, 0xae, 0x2e, 0x51,
- 0xc3, 0x26, 0x5d, 0x4d, 0x92, 0x90, 0xc0, 0xb7, 0x68, 0x55, 0x73, 0xff, 0x5b, 0xa9, 0x57, 0x38,
- 0x67, 0x39, 0x2c, 0x2a, 0xa3, 0xda, 0x4e, 0xad, 0x6b, 0xeb, 0x0a, 0xa2, 0x0c, 0x27, 0xfa, 0x33,
- 0xc4, 0x56, 0xa0, 0x53, 0x57, 0x07, 0x07, 0xaf, 0x12, 0x0f, 0xc6, 0xb8, 0x40, 0xfb, 0x00, 0x0c,
- 0x8f, 0x1f, 0x97, 0x8d, 0x1a, 0x35, 0x4a, 0xfc, 0x1c, 0xfc, 0x59, 0x26, 0xcb, 0x16, 0x10, 0x6b,
- 0xb1, 0xda, 0x22, 0x22, 0xa4, 0xdb, 0x07, 0x41, 0x08, 0x34, 0x34, 0xd4, 0x03, 0xcc, 0x0c, 0x61,
- 0xbd, 0xb7, 0xc3, 0x0a, 0x0c, 0x0c, 0xe4, 0x8d, 0x95, 0x5b, 0xad, 0xd6, 0xe0, 0xae, 0x25, 0x03,
- 0x07, 0x00, 0x27, 0x24, 0x24, 0x48, 0x5c, 0x36, 0x3e, 0x04, 0x4d, 0x02, 0xe9, 0x15, 0x17, 0x67,
- 0x89, 0xc5, 0x87, 0x02, 0x43, 0x78, 0xf8, 0xb0, 0xf8, 0xdc, 0xb9, 0x68, 0xcc, 0xaf, 0xcf, 0x3f,
- 0xff, 0x1c, 0x7a, 0x04, 0x78, 0x68, 0x69, 0x6d, 0xeb, 0x78, 0x45, 0x65, 0x5f, 0x56, 0x6e, 0x77,
- 0x3c, 0x33, 0x99, 0xcd, 0x9b, 0x37, 0x6f, 0x96, 0xc4, 0x1f, 0x5e, 0xd3, 0x20, 0xc9, 0xd7, 0xae,
- 0x5d, 0x9b, 0x98, 0x94, 0x74, 0xe1, 0xc2, 0xc5, 0xb0, 0xb0, 0x2d, 0x7f, 0x78, 0x5f, 0x65, 0x38,
- 0x1a, 0x10, 0xb9, 0x73, 0xe7, 0xce, 0x94, 0x97, 0x3f, 0x6a, 0x6e, 0x6e, 0xbc, 0x7e, 0xe3, 0x3a,
- 0x5c, 0xf6, 0xef, 0x81, 0x16, 0xf7, 0x1b, 0x1e, 0x1e, 0x62, 0xd4, 0xd7, 0xb0, 0xf6, 0x87, 0xb4,
- 0xca, 0x4e, 0xb3, 0x9f, 0x96, 0xd8, 0x35, 0xcf, 0x70, 0x09, 0x25, 0x76, 0x8d, 0x63, 0x39, 0x75,
- 0xf8, 0x33, 0xa6, 0xf2, 0x59, 0x07, 0xb9, 0x79, 0xf3, 0x66, 0x44, 0x44, 0xc4, 0x93, 0x27, 0x4f,
- 0x40, 0xc3, 0xa0, 0x70, 0xa1, 0x10, 0x81, 0x5b, 0xb0, 0x85, 0xcb, 0x97, 0x2f, 0x3b, 0x9d, 0x4e,
- 0x7c, 0x0e, 0x06, 0x09, 0x51, 0xdc, 0x5d, 0xc4, 0x40, 0x28, 0x27, 0x00, 0x30, 0xa0, 0xac, 0x31,
- 0x8e, 0x3f, 0x45, 0x6c, 0x07, 0x42, 0x20, 0x58, 0xb6, 0x6d, 0xdb, 0xd6, 0xf5, 0xae, 0x00, 0x1f,
- 0x80, 0x2c, 0xa2, 0x64, 0xc0, 0x23, 0xf0, 0xe2, 0x70, 0xd8, 0x42, 0x43, 0x43, 0xbd, 0x0f, 0xfe,
- 0xe2, 0x8b, 0xf1, 0x15, 0x65, 0xf9, 0xac, 0xed, 0x21, 0x31, 0xc4, 0x00, 0xa8, 0x14, 0xb1, 0x6d,
- 0xc1, 0x44, 0xfd, 0x33, 0x31, 0x5e, 0x66, 0xed, 0x8f, 0x6a, 0xab, 0x8b, 0x3f, 0xf9, 0xe4, 0x63,
- 0xf1, 0x60, 0x98, 0x68, 0x28, 0x0e, 0x20, 0x36, 0x25, 0xe5, 0xa6, 0xa7, 0xdf, 0x07, 0x2f, 0x85,
- 0x29, 0x13, 0x10, 0xab, 0x52, 0x6b, 0x02, 0x3b, 0xc7, 0xcf, 0x31, 0x4d, 0x16, 0x2e, 0x5c, 0xe0,
- 0x72, 0xd9, 0x59, 0xd6, 0x01, 0x9f, 0xf5, 0xdb, 0xa9, 0x53, 0x21, 0x2f, 0x1b, 0x0d, 0x75, 0x6d,
- 0xde, 0x7c, 0x23, 0x39, 0xc5, 0x05, 0x28, 0xb3, 0x5c, 0x61, 0xe1, 0x5d, 0x3f, 0x3f, 0x69, 0x3c,
- 0xe4, 0x83, 0x3e, 0x7d, 0x82, 0x82, 0x82, 0x24, 0x1f, 0x62, 0x8e, 0x40, 0x88, 0x89, 0xdc, 0x55,
- 0xac, 0xeb, 0x16, 0x37, 0xdd, 0x9a, 0x33, 0x67, 0x6e, 0xaf, 0x5e, 0xbd, 0xc4, 0x19, 0x1a, 0x1c,
- 0xfc, 0xa3, 0x55, 0x28, 0x7d, 0x79, 0x26, 0xad, 0xa4, 0x05, 0x87, 0x79, 0xd3, 0x47, 0x82, 0x62,
- 0x80, 0x60, 0x52, 0x40, 0x03, 0x5e, 0x93, 0x04, 0x7c, 0x7d, 0x03, 0x66, 0xd6, 0xad, 0x0b, 0xae,
- 0xaa, 0x7c, 0xe4, 0x72, 0xe8, 0x39, 0xd6, 0xc2, 0x71, 0x76, 0x86, 0xb1, 0x03, 0x54, 0xde, 0x4e,
- 0x50, 0x6c, 0xef, 0xbf, 0xff, 0x9f, 0x91, 0x7b, 0xb6, 0x5b, 0x8d, 0x35, 0x9c, 0xad, 0x88, 0xa6,
- 0x26, 0x35, 0x91, 0x4c, 0xdb, 0x0a, 0x17, 0x05, 0xed, 0x78, 0x46, 0x3e, 0x83, 0x33, 0x9c, 0x7e,
- 0xee, 0x56, 0x83, 0x4e, 0x1f, 0x3f, 0x7e, 0xfc, 0xc2, 0x85, 0x0b, 0x0a, 0x85, 0x02, 0x96, 0x1f,
- 0x76, 0x15, 0xf3, 0x3a, 0x25, 0x25, 0x25, 0x37, 0x37, 0x17, 0x4e, 0x0a, 0xfc, 0x56, 0x2e, 0x97,
- 0x03, 0xcf, 0x98, 0xfe, 0xdd, 0xb5, 0xd0, 0x46, 0x7c, 0xda, 0xe6, 0x90, 0x21, 0x7e, 0xe8, 0xf3,
- 0x7d, 0xfb, 0xa2, 0xe0, 0xf8, 0x6a, 0xeb, 0xea, 0x02, 0x02, 0x02, 0xba, 0xde, 0x1b, 0x02, 0xdb,
- 0x34, 0x99, 0xe1, 0x67, 0x89, 0x88, 0x58, 0xb3, 0xd9, 0x08, 0x6b, 0xe3, 0x7d, 0xf0, 0xa2, 0x85,
- 0xf3, 0xcc, 0x86, 0x1a, 0xd6, 0x9a, 0x47, 0xf4, 0xa7, 0x68, 0xb6, 0xab, 0x75, 0x35, 0xd3, 0x1e,
- 0x02, 0x4a, 0x40, 0x4b, 0x62, 0x1c, 0xb5, 0x09, 0x97, 0x63, 0x3d, 0xcd, 0xf2, 0xec, 0xd9, 0xb3,
- 0x85, 0x60, 0xd1, 0x89, 0x13, 0x27, 0x3c, 0xd9, 0x26, 0x18, 0x42, 0x63, 0x63, 0x93, 0x80, 0x58,
- 0x78, 0x4c, 0x49, 0xb7, 0xe3, 0x76, 0xf6, 0xef, 0x8f, 0xc2, 0xa0, 0x70, 0xc4, 0xa0, 0x56, 0xb7,
- 0x63, 0x02, 0x3e, 0x79, 0x52, 0x51, 0x0e, 0x27, 0x5d, 0xf1, 0x14, 0xef, 0x1b, 0x1a, 0x1a, 0x60,
- 0x5a, 0x61, 0x99, 0x01, 0xda, 0x73, 0xe7, 0xce, 0x79, 0x97, 0xf1, 0xc0, 0x65, 0x48, 0x80, 0x81,
- 0x1b, 0x8c, 0x8f, 0x8f, 0x17, 0xc5, 0x94, 0x67, 0x35, 0xb8, 0xb0, 0xb1, 0x21, 0x8c, 0x89, 0x67,
- 0x96, 0x01, 0x5f, 0xc7, 0x14, 0xe3, 0x5e, 0x3e, 0x68, 0x5e, 0x4c, 0x69, 0xe1, 0xeb, 0x36, 0xbb,
- 0x1d, 0x9d, 0xec, 0xb3, 0x3e, 0xf3, 0xaf, 0x6b, 0x30, 0x29, 0x27, 0x8e, 0x1f, 0x36, 0xea, 0x9a,
- 0x38, 0x57, 0x1b, 0xe7, 0x6a, 0xe5, 0x18, 0x25, 0x7a, 0xc6, 0xcd, 0x39, 0x65, 0xb2, 0x2c, 0x58,
- 0xaa, 0xdf, 0xfb, 0x96, 0x50, 0x78, 0x00, 0x0a, 0xe7, 0xb4, 0x35, 0xb2, 0x14, 0xb4, 0xf1, 0x44,
- 0xbd, 0x9b, 0xd6, 0x2c, 0xc9, 0x83, 0x48, 0xcb, 0x77, 0x6e, 0x63, 0xec, 0x73, 0xb7, 0xce, 0x68,
- 0x34, 0x1c, 0x3e, 0x7c, 0x18, 0x10, 0x05, 0x62, 0xc7, 0x8d, 0x1b, 0x37, 0x6b, 0xd6, 0xac, 0x79,
- 0xf3, 0xe6, 0x01, 0xa8, 0x30, 0xad, 0xe1, 0xe1, 0xe1, 0xd0, 0x62, 0x78, 0x7f, 0xf6, 0xec, 0x59,
- 0xf8, 0x85, 0xee, 0xa2, 0xb2, 0xfc, 0x13, 0xa1, 0xff, 0x0d, 0x4a, 0x64, 0xe4, 0xc8, 0x91, 0x8b,
- 0x97, 0x2c, 0x39, 0x76, 0xfc, 0x38, 0x24, 0xc9, 0xd3, 0xca, 0xaa, 0x37, 0x2d, 0x07, 0x02, 0xe5,
- 0x9b, 0x35, 0x6b, 0xa6, 0x56, 0xab, 0xe1, 0x41, 0xcb, 0x80, 0x1e, 0x34, 0xcb, 0x9b, 0xbd, 0x1d,
- 0x1f, 0xc5, 0x52, 0xd4, 0x2e, 0xce, 0x55, 0xcf, 0xe7, 0x0e, 0x8e, 0x90, 0xf6, 0x10, 0xa6, 0x6d,
- 0x1d, 0x51, 0x6d, 0x67, 0x69, 0x66, 0xb6, 0xd0, 0x69, 0x93, 0x07, 0x06, 0x76, 0x8a, 0x43, 0x26,
- 0x24, 0x26, 0x0a, 0x11, 0xf5, 0x8d, 0x21, 0x21, 0x9e, 0xfe, 0x6b, 0xc1, 0x82, 0x05, 0x26, 0x93,
- 0x59, 0x88, 0x23, 0xdd, 0x4a, 0x4b, 0x93, 0xfc, 0x0a, 0xc4, 0x75, 0x6e, 0x4e, 0x26, 0x06, 0x85,
- 0x73, 0x35, 0xb3, 0xf6, 0xca, 0xd2, 0x92, 0x22, 0x59, 0x76, 0x4e, 0x66, 0x96, 0x0c, 0x8a, 0xfb,
- 0x5e, 0xd1, 0xfd, 0xf2, 0x27, 0x15, 0xcd, 0x72, 0x85, 0xde, 0x60, 0x04, 0x68, 0x37, 0x6c, 0xdc,
- 0xe8, 0xcd, 0x5b, 0xbc, 0x07, 0x8e, 0x4f, 0x3a, 0xdb, 0x5e, 0x45, 0xab, 0x24, 0x8b, 0xbc, 0x3a,
- 0xe8, 0x76, 0xf4, 0x9e, 0xb1, 0xe2, 0xf1, 0xe3, 0xc7, 0xd7, 0xd4, 0xd4, 0xbe, 0x12, 0x68, 0x1e,
- 0x06, 0x16, 0x13, 0xa7, 0x7b, 0xd7, 0xc9, 0xbe, 0xbe, 0x61, 0xf6, 0x0d, 0x1e, 0x3c, 0x28, 0x47,
- 0x96, 0xea, 0x66, 0x14, 0x9c, 0xe3, 0x29, 0x6b, 0x2f, 0x65, 0xed, 0xe5, 0x9c, 0xb3, 0x9e, 0x65,
- 0xd4, 0x84, 0xb1, 0xc4, 0xc5, 0x5d, 0x90, 0xf0, 0x61, 0x8c, 0x23, 0xa6, 0x1b, 0xbe, 0x25, 0xf6,
- 0x36, 0x40, 0x7b, 0xf6, 0xcc, 0x09, 0x9b, 0x99, 0xaf, 0x38, 0x32, 0x5c, 0x82, 0x37, 0x04, 0x8b,
- 0x63, 0x14, 0xf3, 0x39, 0xed, 0xde, 0x67, 0xa4, 0xd6, 0xe5, 0xb4, 0x9f, 0x3e, 0x7d, 0xfa, 0xe4,
- 0xc9, 0x93, 0xb0, 0xae, 0x4b, 0x97, 0x2e, 0xd5, 0xe9, 0x74, 0x60, 0xb0, 0xe0, 0xae, 0xc0, 0x30,
- 0x90, 0x6c, 0x36, 0x9b, 0xdb, 0xdb, 0xdb, 0x0f, 0x1e, 0x3c, 0x88, 0x79, 0xd1, 0x5d, 0x4b, 0xc3,
- 0x84, 0x67, 0x15, 0x09, 0x7b, 0xbc, 0xaf, 0x5e, 0x13, 0x7c, 0x2e, 0xfa, 0x3c, 0xbc, 0xed, 0xb5,
- 0xeb, 0xd7, 0xff, 0x40, 0xe7, 0x00, 0xe4, 0x61, 0x61, 0x61, 0x3a, 0x1d, 0x54, 0x2d, 0x0b, 0x92,
- 0x08, 0x1e, 0xee, 0x7d, 0xcc, 0x47, 0xfd, 0xfa, 0xa5, 0xa6, 0x5c, 0x61, 0xd1, 0x75, 0xc6, 0x6b,
- 0x94, 0x1a, 0x01, 0xb1, 0xed, 0x9b, 0x88, 0x26, 0x8a, 0x35, 0x26, 0x71, 0xf6, 0x32, 0x79, 0x53,
- 0xc5, 0xbb, 0xef, 0xbe, 0xea, 0x40, 0x18, 0x55, 0x50, 0x41, 0x8c, 0xb2, 0xa2, 0xa5, 0x75, 0xee,
- 0xb7, 0xdf, 0x8a, 0x9f, 0xe3, 0x82, 0xd7, 0xae, 0x5d, 0x27, 0xd6, 0xf8, 0x85, 0x87, 0x6f, 0x95,
- 0xfc, 0xca, 0xb0, 0x61, 0xc3, 0x34, 0x9a, 0x16, 0x8e, 0x2f, 0x92, 0xe1, 0xac, 0x45, 0x9a, 0xe6,
- 0xcc, 0x84, 0x84, 0xc4, 0xcb, 0x57, 0xae, 0x40, 0xac, 0xa5, 0xa5, 0xa5, 0x63, 0x4a, 0x56, 0xd7,
- 0xd4, 0xaa, 0x35, 0x9a, 0x9a, 0xda, 0x3a, 0x9f, 0x65, 0x3c, 0x92, 0x86, 0x11, 0xcc, 0x92, 0xc9,
- 0x84, 0xdd, 0x30, 0x04, 0x3e, 0xe0, 0xb5, 0x2c, 0xf1, 0x59, 0x41, 0x61, 0xa1, 0xa8, 0xdc, 0x31,
- 0xe8, 0x34, 0xc5, 0xc0, 0xef, 0x01, 0x2b, 0x0a, 0x34, 0x81, 0xc1, 0x32, 0x0c, 0x39, 0x78, 0xf0,
- 0x50, 0xd7, 0xe3, 0x51, 0x38, 0x12, 0xe0, 0xf9, 0x03, 0x4b, 0x96, 0x84, 0x06, 0x34, 0xce, 0x98,
- 0x31, 0xbd, 0xa4, 0x38, 0x97, 0x38, 0xea, 0x38, 0xe0, 0xcd, 0x92, 0xc5, 0x5a, 0xb3, 0x60, 0x19,
- 0xd0, 0xff, 0x1c, 0xa3, 0x52, 0x29, 0x29, 0xc6, 0xc4, 0x83, 0xd1, 0xdb, 0x9f, 0x7d, 0x36, 0x72,
- 0xe6, 0xcc, 0xa0, 0xd5, 0xab, 0x56, 0xac, 0x58, 0xb1, 0x6c, 0xda, 0xb4, 0xa9, 0xe2, 0x1c, 0xec,
- 0xd7, 0xaf, 0x5f, 0xc2, 0x95, 0x0b, 0x4e, 0x5b, 0x13, 0x6b, 0x2b, 0x20, 0x86, 0x58, 0x5a, 0x5c,
- 0xd7, 0xba, 0x82, 0x55, 0x85, 0x76, 0xd8, 0x73, 0x9e, 0x77, 0xd8, 0xee, 0xde, 0x2d, 0x04, 0x13,
- 0xc8, 0xcc, 0xcc, 0x8c, 0x8a, 0x8a, 0x82, 0xaf, 0xc1, 0x1b, 0x38, 0x44, 0xb0, 0x4a, 0xe0, 0x96,
- 0x10, 0x02, 0x63, 0x0b, 0x6d, 0xfb, 0xde, 0x7b, 0xef, 0x75, 0x17, 0x8f, 0x15, 0x9e, 0xa3, 0xf1,
- 0x61, 0xdf, 0xbe, 0x5f, 0x06, 0x04, 0x40, 0x0e, 0x60, 0x58, 0xab, 0x6b, 0x6a, 0x7c, 0xf2, 0x4f,
- 0xdc, 0xfe, 0xe4, 0xc9, 0x93, 0x83, 0x83, 0x83, 0x21, 0x2e, 0x3c, 0x65, 0xbb, 0x67, 0xeb, 0xdf,
- 0xbf, 0x7f, 0x72, 0x72, 0x32, 0x1f, 0x3f, 0x77, 0x43, 0x2c, 0x78, 0x1f, 0x30, 0x72, 0xe4, 0xf0,
- 0x86, 0xba, 0x62, 0xd6, 0x56, 0x4c, 0x97, 0xc3, 0xa8, 0xf7, 0x12, 0xc0, 0x55, 0xf5, 0x13, 0xd1,
- 0xfd, 0x4a, 0x2c, 0x19, 0x9c, 0xab, 0xe1, 0xe4, 0xc9, 0xa3, 0x9e, 0x07, 0x4f, 0x9f, 0x3e, 0xdd,
- 0xc2, 0xd7, 0x34, 0x96, 0x3e, 0x7a, 0xe4, 0x19, 0x50, 0xc5, 0x95, 0xd0, 0x52, 0x9c, 0x97, 0x91,
- 0x4f, 0x38, 0x23, 0xcf, 0x6f, 0x61, 0x7c, 0xe7, 0xce, 0x9d, 0xe3, 0xe6, 0x6c, 0x1c, 0xd3, 0xce,
- 0x3a, 0x2a, 0x59, 0x6b, 0xa1, 0x53, 0x9f, 0x9e, 0x27, 0x4b, 0xb8, 0x18, 0x17, 0x77, 0x25, 0x21,
- 0xe1, 0x66, 0x6a, 0x6a, 0x7e, 0x41, 0x21, 0xb8, 0x81, 0x46, 0xa3, 0xcd, 0xce, 0xc9, 0xe9, 0xca,
- 0x4a, 0x40, 0x78, 0xf0, 0xbc, 0xfc, 0xfc, 0x17, 0x0f, 0x83, 0xed, 0x8c, 0x58, 0x71, 0x19, 0x2c,
- 0x66, 0x04, 0xfc, 0x94, 0x70, 0x7c, 0xef, 0xde, 0xbd, 0x31, 0x5b, 0xc5, 0xa7, 0xc7, 0x7a, 0xee,
- 0xa0, 0xa5, 0x54, 0xa9, 0xbc, 0x69, 0xb3, 0xcf, 0x86, 0x41, 0x19, 0x3e, 0x7c, 0xf8, 0xb2, 0x65,
- 0xcb, 0xb6, 0x84, 0x87, 0xa3, 0x27, 0x47, 0x8f, 0x1e, 0xdd, 0x75, 0xa5, 0x26, 0x34, 0x20, 0x70,
- 0xe5, 0xca, 0xe5, 0xd5, 0x95, 0xc5, 0xac, 0xab, 0x91, 0x6e, 0xd2, 0x65, 0x4e, 0x26, 0xa6, 0x04,
- 0x62, 0xbe, 0xce, 0x5a, 0xb3, 0x81, 0x58, 0xc2, 0xa8, 0x33, 0x32, 0x6e, 0x09, 0x81, 0x68, 0xdc,
- 0xe0, 0x67, 0x23, 0x47, 0x1c, 0x3c, 0xb0, 0xf7, 0x49, 0x59, 0x91, 0xd3, 0xa6, 0xa2, 0xbe, 0x89,
- 0x35, 0xdb, 0x6c, 0xfa, 0x98, 0xf3, 0xe7, 0x44, 0xf9, 0xe9, 0xe7, 0x37, 0xe4, 0x76, 0xfa, 0x0d,
- 0x37, 0x4e, 0x65, 0x91, 0x11, 0xfd, 0x69, 0xa2, 0xdc, 0x4a, 0xda, 0xd7, 0x72, 0xfa, 0x93, 0xcf,
- 0x48, 0x9d, 0xc3, 0x6e, 0x02, 0x1f, 0x86, 0x69, 0x8d, 0x8e, 0x8e, 0xce, 0xcf, 0xcf, 0xbf, 0x76,
- 0xed, 0x1a, 0xde, 0x83, 0x6e, 0xc1, 0xde, 0x9a, 0x4c, 0xa6, 0xc4, 0xc4, 0xc4, 0x2f, 0xbf, 0xfc,
- 0x12, 0x17, 0xdf, 0x2d, 0x88, 0x15, 0x1f, 0xb8, 0x09, 0x61, 0x3b, 0x63, 0x46, 0xd0, 0x8e, 0x1d,
- 0x3b, 0x52, 0x6e, 0xde, 0x6c, 0x96, 0xcb, 0xc7, 0xfa, 0xe2, 0x9f, 0x03, 0x3e, 0xfe, 0x18, 0xd3,
- 0xc7, 0xe9, 0x62, 0xf0, 0x3a, 0x72, 0xe4, 0x17, 0x9f, 0xbd, 0x84, 0x59, 0x99, 0x94, 0x94, 0xc4,
- 0x47, 0x26, 0xdd, 0x23, 0x46, 0x8c, 0x90, 0xfc, 0x15, 0xb6, 0x71, 0xd6, 0xac, 0x20, 0x97, 0x5d,
- 0x8e, 0x69, 0x4e, 0x65, 0x97, 0x7a, 0x37, 0x5d, 0x9f, 0xa8, 0x8e, 0x24, 0x86, 0x8b, 0xa0, 0x49,
- 0x2e, 0x47, 0xcb, 0xa4, 0x49, 0x13, 0x3d, 0x8f, 0xff, 0xe5, 0x97, 0xa3, 0x42, 0x39, 0x4d, 0x46,
- 0xc6, 0x1d, 0x71, 0x0d, 0xd4, 0x5b, 0x7c, 0x7c, 0xe6, 0xcc, 0x99, 0x33, 0xee, 0x97, 0xd9, 0x2e,
- 0x09, 0x81, 0x41, 0xff, 0x1f, 0x3d, 0xfa, 0x8b, 0x1b, 0x24, 0x96, 0x81, 0x8d, 0x6d, 0x80, 0x9a,
- 0x63, 0x2d, 0x05, 0x86, 0xb6, 0x2c, 0x59, 0x66, 0x5a, 0xfa, 0xed, 0xdb, 0xb9, 0x79, 0x79, 0x25,
- 0xfc, 0x8e, 0x6a, 0x06, 0xa3, 0x31, 0x2e, 0xee, 0xd2, 0xeb, 0xeb, 0x6f, 0xc5, 0x76, 0xe5, 0x4a,
- 0x02, 0xcb, 0x71, 0x12, 0xc4, 0x3e, 0xf7, 0xd8, 0xeb, 0xf8, 0xf0, 0x91, 0x23, 0x62, 0x44, 0x6e,
- 0xd2, 0xa4, 0x49, 0xa0, 0x55, 0x9d, 0xb6, 0x81, 0x7d, 0x59, 0xe5, 0x12, 0x17, 0x17, 0xd7, 0x15,
- 0x83, 0x89, 0x29, 0x39, 0x77, 0xee, 0xb7, 0x19, 0x19, 0x19, 0xed, 0x4a, 0x15, 0x6e, 0xd0, 0x66,
- 0x31, 0x17, 0x16, 0x16, 0x4c, 0xf7, 0x55, 0x9e, 0xf1, 0x7b, 0x0d, 0x70, 0x8d, 0x88, 0xd8, 0xda,
- 0xdc, 0x54, 0xc5, 0x31, 0xad, 0xac, 0xbd, 0x84, 0xae, 0x95, 0x83, 0x6d, 0x34, 0xc4, 0xb0, 0xa6,
- 0x24, 0x28, 0x08, 0xce, 0x59, 0x67, 0xd0, 0x2b, 0x02, 0x03, 0xe9, 0x09, 0x71, 0xd9, 0x4b, 0x97,
- 0x2e, 0xca, 0xcf, 0xbb, 0xcd, 0x38, 0x5a, 0xc1, 0xd6, 0x38, 0x47, 0x25, 0xe7, 0xa8, 0x66, 0x5d,
- 0x4d, 0xf0, 0x50, 0x46, 0x83, 0x72, 0xdd, 0xba, 0x1f, 0xc5, 0x73, 0x0e, 0x1f, 0xfe, 0x69, 0x69,
- 0x71, 0x0e, 0xe7, 0xac, 0xe2, 0x19, 0xdd, 0x09, 0x8c, 0x1d, 0xab, 0xda, 0xda, 0x61, 0xbd, 0xf9,
- 0x9c, 0x53, 0x39, 0x1c, 0x96, 0xc2, 0xc2, 0xc2, 0x4b, 0x97, 0x2e, 0xc5, 0xc6, 0xc6, 0xe2, 0xdf,
- 0xec, 0x6c, 0x99, 0xc9, 0xa8, 0x73, 0x33, 0xfa, 0x87, 0x0f, 0x8b, 0x60, 0xe2, 0x60, 0xc7, 0xfe,
- 0xfd, 0x0d, 0x1f, 0xbb, 0xf0, 0x1a, 0xc4, 0x42, 0x76, 0xe1, 0x9a, 0x85, 0xfd, 0x34, 0xf6, 0xef,
- 0x3f, 0x20, 0xcb, 0xce, 0x7e, 0x52, 0x51, 0xd1, 0xa3, 0x47, 0x0f, 0xef, 0x4e, 0x18, 0x3d, 0x66,
- 0x8c, 0x8a, 0x2e, 0x05, 0xa5, 0x96, 0x03, 0x07, 0xfb, 0xec, 0xa8, 0x51, 0xa3, 0xfc, 0xcb, 0xca,
- 0xca, 0x61, 0xf7, 0x00, 0x09, 0xef, 0x9a, 0x2e, 0x4c, 0x8d, 0xdd, 0xbb, 0x23, 0xc0, 0x2d, 0x09,
- 0xe6, 0xa9, 0xee, 0x34, 0xa3, 0xda, 0xc5, 0xa8, 0xb6, 0x13, 0xed, 0x31, 0x62, 0xba, 0x09, 0x8a,
- 0x55, 0x5a, 0x9c, 0xd7, 0xbb, 0xf7, 0x2b, 0x11, 0x84, 0xaf, 0xdf, 0xbb, 0x77, 0x4f, 0x48, 0xf5,
- 0x42, 0x8a, 0x7a, 0x4a, 0x21, 0xa0, 0x37, 0x39, 0x25, 0x45, 0x50, 0x64, 0x05, 0x05, 0x85, 0x92,
- 0x5f, 0xc1, 0x74, 0x2e, 0x2e, 0x7e, 0x08, 0x59, 0xc1, 0x11, 0x13, 0x47, 0x34, 0x1c, 0xd3, 0xc2,
- 0x39, 0x1b, 0x88, 0xad, 0x46, 0xd9, 0x06, 0x2e, 0x50, 0xd7, 0xd2, 0xd2, 0xaa, 0xd1, 0x6a, 0x2d,
- 0x16, 0x2b, 0x68, 0x30, 0x0c, 0x75, 0x17, 0x1d, 0xee, 0x81, 0x03, 0x07, 0x5c, 0x0c, 0x23, 0x20,
- 0xb0, 0xd3, 0xf2, 0x81, 0x17, 0x50, 0x7c, 0xbe, 0x71, 0x63, 0x88, 0x90, 0x8c, 0x86, 0x13, 0x0f,
- 0x09, 0x09, 0x01, 0xf1, 0xf6, 0x7c, 0x66, 0x81, 0xb0, 0x7a, 0xd1, 0xe9, 0x72, 0x49, 0x52, 0x12,
- 0x3e, 0x1b, 0xe0, 0xba, 0x76, 0xdd, 0xba, 0x47, 0x8f, 0x1f, 0xcb, 0xe5, 0x0a, 0x88, 0xca, 0x96,
- 0x96, 0x16, 0xa7, 0xd5, 0xe8, 0x72, 0xd8, 0x22, 0x23, 0xf7, 0x76, 0x51, 0xaf, 0xe1, 0x4a, 0x7e,
- 0xfb, 0xed, 0xa4, 0x56, 0xdb, 0xce, 0x11, 0x1d, 0xe7, 0xa8, 0x61, 0x2d, 0x39, 0x2c, 0x94, 0xbe,
- 0xee, 0x34, 0xd1, 0x47, 0xc3, 0xd2, 0x72, 0xf6, 0x62, 0x37, 0x69, 0x3f, 0x7d, 0xea, 0x04, 0x3a,
- 0x0a, 0x73, 0x7f, 0xe7, 0xce, 0xed, 0x0a, 0x79, 0x25, 0x71, 0xc2, 0xe3, 0x97, 0x52, 0xf3, 0x6b,
- 0xce, 0xa0, 0x99, 0x1d, 0x50, 0x08, 0x67, 0x3d, 0x61, 0xf4, 0xd7, 0xae, 0x25, 0x8a, 0x3d, 0x0f,
- 0x8a, 0x12, 0x10, 0xf0, 0xbf, 0x15, 0xe5, 0x05, 0x9c, 0xa3, 0x9c, 0x98, 0x52, 0x88, 0xe6, 0x17,
- 0xa2, 0x0c, 0x67, 0xb5, 0xfb, 0x3a, 0x6c, 0x99, 0xcf, 0xb9, 0xf6, 0xe7, 0xcf, 0x1c, 0x8c, 0xd3,
- 0x64, 0x32, 0x28, 0x1d, 0x76, 0xc3, 0xf3, 0x0e, 0xc7, 0x73, 0x4e, 0xed, 0xb6, 0xa4, 0x47, 0x9f,
- 0x3d, 0x3a, 0x71, 0xe2, 0x44, 0xfc, 0x0a, 0xfa, 0xb9, 0x5b, 0x72, 0xb5, 0x02, 0x89, 0xfd, 0xaf,
- 0x1e, 0x3d, 0x46, 0xf9, 0xfb, 0x2f, 0x5b, 0xb6, 0xfc, 0xe4, 0x6f, 0xb4, 0x00, 0x06, 0xc4, 0xc0,
- 0x3b, 0x3a, 0x8d, 0xbe, 0x5a, 0xbc, 0x78, 0x09, 0xc7, 0x27, 0xe2, 0xc1, 0xd0, 0xbc, 0x8b, 0x5b,
- 0x84, 0x3b, 0x82, 0x54, 0x14, 0x14, 0x0a, 0x4e, 0xe2, 0xbd, 0x67, 0x14, 0x0c, 0x5a, 0x46, 0xc6,
- 0x0d, 0xce, 0x59, 0x49, 0x73, 0x07, 0xba, 0xe3, 0x44, 0xb5, 0x93, 0x51, 0xef, 0xa1, 0xdd, 0x68,
- 0xcd, 0xe5, 0x5c, 0xf2, 0xdd, 0xbb, 0x7e, 0xf2, 0x4c, 0xa6, 0x07, 0x4c, 0x9e, 0x0c, 0xd8, 0x0b,
- 0xe1, 0x56, 0x78, 0x19, 0xcf, 0xf3, 0x0c, 0x1e, 0x3c, 0xf8, 0xfe, 0xfd, 0x07, 0x02, 0x25, 0xd8,
- 0xeb, 0xb5, 0xd5, 0x15, 0x9c, 0xb2, 0xd3, 0xe5, 0x14, 0x6a, 0xba, 0x22, 0x23, 0x77, 0x7f, 0xfa,
- 0xe9, 0xd0, 0x21, 0x43, 0x06, 0x0e, 0x19, 0xf2, 0xc9, 0xe0, 0xc1, 0x9f, 0x0c, 0x1a, 0x34, 0x30,
- 0x2c, 0x6c, 0x8b, 0x46, 0xab, 0x83, 0xbd, 0x6c, 0x69, 0x6d, 0x85, 0xaa, 0xf5, 0x46, 0x8b, 0xb0,
- 0xef, 0x9f, 0xe4, 0x73, 0xf8, 0x65, 0x0a, 0x42, 0x0f, 0xdd, 0xe5, 0x99, 0x11, 0x80, 0xf9, 0xc5,
- 0x8d, 0x0b, 0xdf, 0x82, 0xe8, 0x83, 0x1f, 0x14, 0x1f, 0xb7, 0xe1, 0xb1, 0xb8, 0xe0, 0x79, 0x72,
- 0x72, 0xca, 0xbb, 0xef, 0xfe, 0xc7, 0xef, 0x03, 0x8d, 0x36, 0xf4, 0xc0, 0xb1, 0x63, 0xc7, 0xeb,
- 0xeb, 0x1b, 0x20, 0x0f, 0xc1, 0xb7, 0xf3, 0xf2, 0xf2, 0xcb, 0x1e, 0x95, 0x58, 0x35, 0x0a, 0xc6,
- 0x6e, 0xde, 0x1f, 0x15, 0xf9, 0x2f, 0x11, 0x8b, 0x6b, 0x00, 0x3c, 0x2e, 0x5d, 0x8a, 0x77, 0x38,
- 0x1d, 0xb4, 0x0e, 0x93, 0x51, 0xd3, 0xbc, 0x95, 0x25, 0x83, 0x35, 0x5c, 0xa0, 0x88, 0x35, 0x5c,
- 0x24, 0x96, 0x3b, 0xac, 0xb3, 0xa6, 0xb1, 0xa1, 0xfc, 0xa3, 0x8f, 0xfa, 0x61, 0xe2, 0xc7, 0xc4,
- 0x44, 0x5b, 0x2d, 0x6a, 0xd6, 0xd5, 0xf2, 0xd2, 0x0e, 0xe3, 0xb0, 0x33, 0x44, 0x1f, 0xcb, 0x9a,
- 0x52, 0xe1, 0x9b, 0xdc, 0x44, 0x93, 0x97, 0x9b, 0xe5, 0x99, 0x59, 0x7b, 0xe7, 0xed, 0xb7, 0xbf,
- 0x0e, 0x9a, 0x5e, 0x5f, 0xfb, 0x80, 0xcf, 0x2c, 0x5c, 0x67, 0xb5, 0x07, 0x18, 0x65, 0x28, 0xab,
- 0xd9, 0xed, 0x36, 0xc5, 0xb9, 0xad, 0xb7, 0xdc, 0xd6, 0x34, 0xfe, 0xdf, 0x54, 0xb7, 0x25, 0xc5,
- 0x6d, 0x8c, 0x66, 0xdb, 0x97, 0xef, 0xde, 0xb1, 0x06, 0x7c, 0x06, 0x97, 0xd4, 0x2d, 0xfb, 0xcb,
- 0x89, 0xbb, 0x6e, 0x82, 0xab, 0x80, 0x69, 0x84, 0x6c, 0xda, 0x14, 0x1f, 0x7f, 0x19, 0xee, 0x0c,
- 0xf2, 0xd9, 0x3b, 0xe8, 0x87, 0x71, 0x3c, 0x73, 0xf6, 0xac, 0x60, 0xd6, 0x72, 0xf3, 0xf2, 0x7b,
- 0xf7, 0xf6, 0x91, 0x1f, 0xc4, 0x70, 0xef, 0xd8, 0xb9, 0x53, 0xc8, 0x57, 0xae, 0x59, 0xb3, 0xc6,
- 0xbb, 0x7b, 0xfb, 0xf6, 0xfd, 0x50, 0xaf, 0x6b, 0xe0, 0xec, 0xa5, 0xc4, 0x98, 0x48, 0xb4, 0x87,
- 0xa9, 0x8d, 0xd5, 0x1e, 0x22, 0xc6, 0x04, 0x74, 0x97, 0x46, 0x55, 0x3d, 0x7e, 0xdc, 0x58, 0x4f,
- 0xa8, 0x6c, 0xda, 0xbc, 0xb9, 0xb1, 0xb1, 0x49, 0xa5, 0xd6, 0xc0, 0xe6, 0xcf, 0x9a, 0x3d, 0xdb,
- 0xf3, 0x3c, 0x9f, 0xfd, 0xf3, 0x9f, 0xa0, 0x2e, 0x7c, 0xc6, 0x8a, 0x0b, 0xf0, 0xca, 0x02, 0xcf,
- 0x99, 0x33, 0xd7, 0xcd, 0xe7, 0xdf, 0xd5, 0x6a, 0x95, 0x64, 0x71, 0x2b, 0xce, 0x0f, 0x6b, 0x69,
- 0xb3, 0x3b, 0x80, 0xf6, 0xc7, 0x8f, 0xcb, 0x24, 0x9a, 0x1d, 0x7f, 0x5d, 0xbc, 0x78, 0x71, 0xf8,
- 0xd6, 0xad, 0xc2, 0x4e, 0xd4, 0x9e, 0x2d, 0x70, 0xc6, 0x0c, 0xcc, 0x44, 0x2f, 0xc4, 0xbe, 0x48,
- 0x1f, 0x28, 0x95, 0xca, 0x09, 0x13, 0x26, 0x08, 0x67, 0x80, 0x49, 0x69, 0x6d, 0x6b, 0xeb, 0x5c,
- 0x75, 0x40, 0x8f, 0xb1, 0xd9, 0xec, 0x81, 0x81, 0x81, 0xaf, 0x31, 0xe9, 0xf8, 0x13, 0x04, 0xf5,
- 0xf5, 0xeb, 0xd7, 0x61, 0x5a, 0x8b, 0xee, 0x3f, 0xb8, 0x76, 0xed, 0x7a, 0x74, 0xf4, 0x79, 0x08,
- 0xe1, 0xdc, 0xdb, 0xa9, 0x46, 0x79, 0x85, 0x4d, 0xdf, 0x16, 0xb1, 0xed, 0x5f, 0x6f, 0x91, 0x34,
- 0x62, 0xc4, 0xc8, 0xac, 0x2c, 0x19, 0x21, 0xfc, 0x2a, 0x31, 0xca, 0x8b, 0xb4, 0x9c, 0x83, 0x2f,
- 0x79, 0x35, 0x5c, 0x26, 0xfa, 0x18, 0xd6, 0x98, 0x48, 0x59, 0xbd, 0xb5, 0x21, 0x38, 0x78, 0x25,
- 0xac, 0xfd, 0xfd, 0xfb, 0x45, 0x6e, 0xb7, 0x8b, 0x25, 0x7a, 0xd6, 0x59, 0xc7, 0x5a, 0xf3, 0x89,
- 0x21, 0x8e, 0x68, 0x0f, 0xd2, 0xad, 0x21, 0xb4, 0x87, 0x69, 0x20, 0xcb, 0x7a, 0xd7, 0xcd, 0xb4,
- 0x17, 0xe4, 0xcb, 0x24, 0x2b, 0xa9, 0x31, 0xac, 0xf3, 0xe6, 0xcd, 0xa9, 0xaf, 0xb9, 0x4f, 0xec,
- 0xa5, 0xac, 0x29, 0x91, 0xd1, 0x44, 0x32, 0xed, 0xeb, 0x49, 0xdb, 0x72, 0xd2, 0xba, 0x80, 0x28,
- 0x66, 0x13, 0xc5, 0x0c, 0x22, 0x9f, 0x46, 0x9a, 0xa7, 0xd2, 0x8d, 0x53, 0xea, 0x06, 0x46, 0x84,
- 0x2f, 0x1c, 0x3d, 0x7a, 0x4c, 0xaf, 0x5e, 0xbd, 0xbb, 0x65, 0xe3, 0x23, 0x81, 0x12, 0xfc, 0xfd,
- 0xef, 0xef, 0x82, 0xc4, 0xce, 0x9c, 0x39, 0x6b, 0xd7, 0xee, 0x9f, 0x53, 0x6f, 0xa5, 0xd5, 0xd6,
- 0xd6, 0xf9, 0xcc, 0x83, 0x60, 0x9a, 0x08, 0xee, 0x1e, 0x2f, 0xd0, 0x4b, 0xef, 0x31, 0x7d, 0x8b,
- 0x86, 0x41, 0xfe, 0x01, 0x33, 0x22, 0x2c, 0xfc, 0xfc, 0x7c, 0xdc, 0x38, 0xef, 0x93, 0x4c, 0x9f,
- 0x36, 0x05, 0xfe, 0x08, 0x2a, 0xe0, 0x45, 0xe7, 0xc0, 0xc0, 0xea, 0x4e, 0xb2, 0xe6, 0x5b, 0x9c,
- 0xb3, 0x3a, 0x25, 0x39, 0xbe, 0x9f, 0x07, 0x53, 0xc5, 0x77, 0x31, 0x37, 0xe7, 0xcf, 0xa7, 0x5b,
- 0x2c, 0x7f, 0xfd, 0xf5, 0xd7, 0x92, 0x09, 0xf2, 0xc5, 0xc4, 0x89, 0x36, 0xbb, 0x1d, 0xf3, 0xa2,
- 0xad, 0x5d, 0xe9, 0x9d, 0x4a, 0xa6, 0xe5, 0x04, 0x3c, 0x91, 0x2e, 0xba, 0x5f, 0x24, 0x59, 0x2a,
- 0x88, 0xcb, 0xa6, 0x61, 0x52, 0x9a, 0x99, 0x73, 0xa7, 0xa7, 0xdf, 0x96, 0x14, 0x95, 0xc1, 0xbe,
- 0xfd, 0xfc, 0xf3, 0x1e, 0xc8, 0x07, 0xef, 0x08, 0x2d, 0x44, 0x90, 0xd9, 0x6c, 0x91, 0xa4, 0x5c,
- 0x45, 0x56, 0x50, 0x52, 0x5a, 0xfa, 0xe9, 0xa7, 0x54, 0xc1, 0xe1, 0x84, 0x50, 0xaf, 0x42, 0xe1,
- 0x96, 0xb8, 0xb3, 0x81, 0xd0, 0x69, 0x10, 0x08, 0x3e, 0x17, 0xd1, 0x0b, 0x0d, 0x60, 0xf3, 0xf7,
- 0x1f, 0x7d, 0xeb, 0x56, 0x5a, 0x4b, 0x6b, 0xdb, 0xc3, 0xe2, 0x92, 0xc4, 0xc4, 0xa4, 0x43, 0x87,
- 0x0e, 0xff, 0x14, 0xb1, 0x7d, 0xfb, 0x8e, 0x1d, 0x99, 0x49, 0xb1, 0xba, 0xda, 0x07, 0xda, 0x96,
- 0xda, 0x0d, 0x1e, 0x94, 0xd2, 0xbb, 0xe1, 0xa7, 0xbf, 0xfa, 0xea, 0x2b, 0x08, 0x1f, 0xa0, 0x95,
- 0xa7, 0x52, 0x44, 0xa3, 0x69, 0x6f, 0x6a, 0xac, 0xb0, 0x1a, 0xab, 0x58, 0xeb, 0x5d, 0x62, 0xba,
- 0xca, 0x1a, 0x2e, 0xb1, 0xa6, 0x1b, 0x9c, 0xed, 0xfe, 0xd3, 0xf2, 0x9c, 0xb0, 0xd0, 0x90, 0xaa,
- 0xaa, 0xa7, 0x7c, 0x82, 0xd2, 0x01, 0xe6, 0xc0, 0x23, 0x36, 0x8f, 0x1a, 0x58, 0xcd, 0x7e, 0x46,
- 0xb5, 0x13, 0xff, 0xb2, 0x86, 0x38, 0xd6, 0x5a, 0x40, 0x9c, 0xad, 0xc9, 0x37, 0x12, 0xbd, 0xe3,
- 0x9c, 0x30, 0x68, 0xab, 0x57, 0x2d, 0x6b, 0x6f, 0x29, 0x83, 0xfa, 0x60, 0xf5, 0x17, 0x19, 0x1a,
- 0xa4, 0x5d, 0xc9, 0xc8, 0xbf, 0x76, 0x35, 0x4e, 0x70, 0xd1, 0xc2, 0x03, 0x3f, 0xba, 0xb1, 0x0f,
- 0xdd, 0xf8, 0xa8, 0x77, 0xf8, 0xe6, 0x6f, 0xfd, 0xfd, 0xfd, 0x7b, 0xf6, 0xec, 0x9e, 0xad, 0xba,
- 0x5e, 0x3e, 0x41, 0xe3, 0x7d, 0xe8, 0x65, 0x78, 0xfc, 0xa3, 0x47, 0x8f, 0xe5, 0xe5, 0x83, 0x15,
- 0x16, 0xfa, 0xcc, 0x77, 0x0f, 0x1d, 0x3a, 0xd4, 0xe1, 0x70, 0xba, 0x69, 0x12, 0x9f, 0x5b, 0xbc,
- 0x64, 0x89, 0x4f, 0xf7, 0xf4, 0xc9, 0xc0, 0x81, 0xb4, 0xd2, 0xbb, 0xe3, 0x59, 0x49, 0x49, 0x89,
- 0x77, 0xd1, 0x3e, 0xda, 0xfe, 0xa8, 0x3d, 0x1c, 0x23, 0x07, 0x07, 0xa0, 0x9d, 0xa3, 0x3d, 0x42,
- 0xe7, 0x32, 0xfc, 0x94, 0x35, 0xdf, 0x69, 0x6b, 0x08, 0x0b, 0xdd, 0xd0, 0xc5, 0xad, 0xbd, 0xe8,
- 0x12, 0xad, 0xff, 0x6b, 0xef, 0x3b, 0xc0, 0xa2, 0xba, 0xd6, 0x76, 0xef, 0xf3, 0xdf, 0xfb, 0x9f,
- 0xfc, 0xf7, 0x9c, 0x93, 0xe4, 0xc4, 0xc4, 0x24, 0xf6, 0xae, 0x51, 0xda, 0x0c, 0x88, 0x80, 0x18,
- 0xb1, 0xc6, 0xde, 0x42, 0x11, 0x1b, 0x22, 0x22, 0x28, 0x4d, 0x69, 0x02, 0xa2, 0xc4, 0x8a, 0x20,
- 0x60, 0x17, 0x1b, 0x52, 0x14, 0x05, 0x11, 0x91, 0x5e, 0xa5, 0xf7, 0xde, 0x19, 0x7a, 0xef, 0x33,
- 0xc0, 0x30, 0xc3, 0x34, 0x92, 0xe7, 0x3e, 0xf7, 0xdd, 0x7b, 0xcb, 0x88, 0x33, 0x68, 0x6c, 0x49,
- 0x4e, 0x9e, 0x93, 0xef, 0x59, 0x31, 0xcc, 0xec, 0x32, 0x7b, 0xaf, 0xf5, 0xae, 0xf7, 0x7b, 0xbf,
- 0x55, 0x77, 0xec, 0x20, 0x91, 0x40, 0xb4, 0xc4, 0x4a, 0x8c, 0xbd, 0x47, 0xd1, 0xe7, 0xe6, 0xe5,
- 0x51, 0x41, 0x99, 0xff, 0xc3, 0x87, 0x12, 0x63, 0x45, 0x00, 0xbc, 0x9c, 0x9c, 0x1c, 0x1c, 0xe2,
- 0x70, 0x87, 0x5c, 0x5d, 0x5d, 0x25, 0xee, 0x8c, 0xb0, 0x11, 0x50, 0x81, 0x42, 0x1e, 0x1d, 0xe5,
- 0x51, 0x06, 0x61, 0x8f, 0x48, 0xed, 0x15, 0xc4, 0xbe, 0x5c, 0x84, 0xf3, 0x97, 0xf0, 0xf0, 0x08,
- 0x04, 0x17, 0x9f, 0x90, 0x23, 0xf9, 0xe3, 0xe2, 0xe3, 0x47, 0xd6, 0x87, 0xff, 0x45, 0x0c, 0x57,
- 0xe8, 0xa8, 0x31, 0x47, 0x2f, 0x50, 0x06, 0x3d, 0xb9, 0x7e, 0xfd, 0xfa, 0xe7, 0xcf, 0x13, 0x7b,
- 0x7a, 0x7b, 0x6b, 0xeb, 0xea, 0x63, 0xe3, 0xe2, 0x3d, 0x3d, 0x6f, 0xda, 0xd9, 0xdb, 0x1b, 0x1b,
- 0x1f, 0x34, 0x35, 0x33, 0x4b, 0x7c, 0xe8, 0xd9, 0x5d, 0x91, 0xda, 0x5c, 0x5d, 0x78, 0xc0, 0xf0,
- 0xb5, 0x0b, 0xce, 0xe0, 0x0e, 0xa8, 0xdb, 0xe4, 0x18, 0xc8, 0x61, 0xf2, 0xdd, 0x87, 0x23, 0x22,
- 0x22, 0x0e, 0x1d, 0x3a, 0xa8, 0xa3, 0xa3, 0x15, 0xfc, 0xe4, 0x1e, 0x87, 0x95, 0x45, 0xc8, 0x4e,
- 0x48, 0x59, 0xf8, 0xf1, 0xc1, 0xf4, 0xa6, 0xba, 0xcc, 0xee, 0xae, 0x46, 0xb2, 0x27, 0x9d, 0xec,
- 0x52, 0x17, 0xf6, 0x11, 0x52, 0x9f, 0x93, 0x47, 0xb4, 0x37, 0x42, 0xaa, 0x75, 0x5d, 0x20, 0x06,
- 0xd5, 0x23, 0x40, 0x1b, 0xcc, 0xe9, 0x63, 0xd6, 0xd9, 0xda, 0x8e, 0xb1, 0xdf, 0x13, 0xf8, 0x64,
- 0xc5, 0x8a, 0xe5, 0x15, 0xe5, 0xf9, 0x08, 0x10, 0x20, 0x92, 0x11, 0xd3, 0xf1, 0x3b, 0x4f, 0xf3,
- 0x5b, 0x8c, 0xf9, 0x0d, 0x5b, 0x79, 0xb5, 0x1a, 0xc4, 0xca, 0x7e, 0x04, 0x62, 0xe7, 0x0d, 0x55,
- 0x4c, 0xb2, 0x32, 0xdf, 0xb6, 0x70, 0xe1, 0x42, 0x84, 0x24, 0x1f, 0x45, 0xc7, 0x8e, 0xde, 0x6d,
- 0xf3, 0xc8, 0x11, 0x4b, 0x5f, 0x5f, 0xbf, 0xfc, 0x82, 0x02, 0xaf, 0x7b, 0xf7, 0xc6, 0xec, 0xb6,
- 0x33, 0x32, 0x32, 0xa2, 0x06, 0xd4, 0xb5, 0xb6, 0xb6, 0x51, 0x1e, 0x50, 0xfa, 0x2d, 0x36, 0x6e,
- 0xdc, 0x08, 0x7f, 0x04, 0x20, 0x79, 0x7b, 0x7b, 0x8f, 0x39, 0x89, 0x23, 0x33, 0x23, 0x51, 0xc4,
- 0xab, 0x17, 0x0e, 0x24, 0x0b, 0x99, 0x54, 0x20, 0xe0, 0x45, 0xc4, 0x5c, 0x9c, 0xa2, 0xaa, 0x8a,
- 0xac, 0xf5, 0xeb, 0xdf, 0x76, 0xc2, 0x0b, 0x4a, 0xc7, 0xda, 0xda, 0x9a, 0x7a, 0x18, 0x50, 0xa2,
- 0x84, 0xe4, 0x86, 0xbf, 0x68, 0xef, 0x20, 0xc6, 0x69, 0xf3, 0x78, 0xfc, 0x33, 0x67, 0xce, 0x48,
- 0x0c, 0x8d, 0x40, 0x00, 0xde, 0xd8, 0xd4, 0x8c, 0xa3, 0x4c, 0x56, 0xdf, 0xf6, 0xed, 0xdb, 0x25,
- 0xee, 0x0c, 0x42, 0x2e, 0x2e, 0x2e, 0x49, 0x4b, 0x4f, 0x97, 0x93, 0xaa, 0xb3, 0xa8, 0x26, 0x0d,
- 0xe4, 0x24, 0x44, 0xf1, 0x74, 0xad, 0x11, 0x49, 0x40, 0x84, 0x54, 0xb7, 0xef, 0xdc, 0xa1, 0x62,
- 0x55, 0x75, 0x75, 0xf5, 0x7e, 0x6a, 0x2b, 0xae, 0x57, 0xb7, 0x38, 0x4c, 0x4a, 0x4e, 0x46, 0x6c,
- 0x3b, 0xe6, 0xeb, 0xe0, 0x09, 0xb5, 0xb4, 0xb4, 0x72, 0x73, 0xf3, 0x38, 0x1c, 0x6e, 0x2f, 0x93,
- 0x49, 0xcc, 0x05, 0x8e, 0x8c, 0x82, 0x17, 0x83, 0x72, 0x86, 0x7f, 0x81, 0x4a, 0xc9, 0x0c, 0xbc,
- 0xda, 0x5d, 0x9e, 0x58, 0x53, 0x9a, 0xb5, 0x43, 0x57, 0x67, 0xcc, 0x3b, 0xe0, 0xd9, 0x8e, 0x58,
- 0x5a, 0xd6, 0xd6, 0xd6, 0x91, 0xdc, 0xfe, 0x33, 0x8f, 0x2f, 0xf0, 0xf1, 0xf5, 0x05, 0x63, 0x50,
- 0x3e, 0xce, 0xc1, 0xfe, 0x08, 0xab, 0x33, 0x03, 0xf9, 0x4c, 0x70, 0x2c, 0x2b, 0x50, 0x40, 0xcc,
- 0xa9, 0xaf, 0x22, 0x22, 0x32, 0x21, 0xa4, 0x3e, 0x4c, 0xd0, 0xd8, 0x50, 0xf3, 0xe8, 0xa1, 0x57,
- 0x69, 0x61, 0x34, 0xbf, 0xff, 0xb9, 0x80, 0xe9, 0x4f, 0x14, 0x0a, 0x21, 0x77, 0x63, 0x84, 0xdc,
- 0xf2, 0x86, 0xfa, 0x52, 0x05, 0x05, 0xc9, 0xac, 0x00, 0x59, 0x11, 0xcb, 0x24, 0xc6, 0x44, 0x73,
- 0x38, 0x2c, 0x91, 0x80, 0x54, 0x1d, 0x6c, 0x5c, 0xe8, 0x33, 0x02, 0xda, 0xcd, 0xbc, 0xda, 0xa5,
- 0xc4, 0x44, 0x1b, 0xc6, 0xdc, 0x8c, 0xa7, 0xea, 0x3b, 0xb7, 0x6f, 0x80, 0xd4, 0xf9, 0x28, 0x6b,
- 0xc8, 0x88, 0xdb, 0xb5, 0xe0, 0x55, 0x37, 0x6c, 0xdc, 0x78, 0xc2, 0xc9, 0xe9, 0x69, 0x48, 0x08,
- 0x42, 0x69, 0x3b, 0x3b, 0xbb, 0x31, 0x57, 0xd9, 0xf5, 0xbb, 0x7f, 0xff, 0xe7, 0x91, 0xcc, 0x1f,
- 0x73, 0x76, 0x2d, 0xf2, 0x4d, 0x2c, 0x62, 0xad, 0x6d, 0x6c, 0xa4, 0x1b, 0x0f, 0x51, 0xd1, 0x58,
- 0xcc, 0x36, 0xa2, 0x13, 0x8a, 0x98, 0xac, 0x1d, 0x0e, 0x29, 0x0b, 0x27, 0x25, 0x24, 0xc4, 0x52,
- 0xfd, 0x93, 0xa0, 0xfb, 0x33, 0xa5, 0x46, 0xa8, 0xbe, 0xce, 0x00, 0x51, 0x6a, 0xbd, 0x35, 0x3e,
- 0x5f, 0x00, 0xb2, 0x95, 0x50, 0x86, 0x10, 0x12, 0x2c, 0xb2, 0x2f, 0x0c, 0x82, 0x41, 0x5f, 0x5f,
- 0x7f, 0xf4, 0x21, 0x72, 0x99, 0x82, 0x13, 0xf0, 0x14, 0x38, 0x0a, 0x54, 0xcf, 0x7e, 0x75, 0x67,
- 0x79, 0x1c, 0xdd, 0xb2, 0x65, 0x0b, 0xc4, 0x46, 0x45, 0x65, 0xd5, 0x98, 0x8d, 0xb4, 0xf0, 0x3e,
- 0xa3, 0x46, 0x68, 0xff, 0xbf, 0xd1, 0x23, 0x5b, 0xe0, 0xbb, 0x29, 0xfe, 0x44, 0x84, 0x48, 0x61,
- 0x78, 0x34, 0xc1, 0x72, 0xb8, 0x5c, 0x7c, 0xff, 0xba, 0xd6, 0xd4, 0xdd, 0xbb, 0xf7, 0x20, 0xc0,
- 0x14, 0x08, 0x85, 0x43, 0x3c, 0x3e, 0x9e, 0xbc, 0xbe, 0xa1, 0x31, 0xe1, 0x79, 0xa2, 0xe7, 0xcd,
- 0x9b, 0x08, 0x2b, 0xf6, 0xed, 0xdb, 0x77, 0xc8, 0xd8, 0xa8, 0x20, 0xf8, 0x5a, 0x4f, 0x45, 0x62,
- 0x45, 0x61, 0xda, 0xb6, 0xad, 0x63, 0xb4, 0x6e, 0xc1, 0x31, 0x1d, 0x3f, 0x71, 0xa2, 0xb3, 0xb3,
- 0x8b, 0x82, 0x2b, 0x7b, 0x90, 0xe3, 0xe6, 0xe6, 0x2e, 0x96, 0x1f, 0x08, 0x75, 0x7d, 0x7d, 0xae,
- 0xf1, 0xd8, 0x79, 0x44, 0x56, 0x43, 0xc7, 0x42, 0x8c, 0xf5, 0x47, 0x0b, 0xb9, 0x25, 0x22, 0x7e,
- 0xc7, 0xb0, 0x08, 0xa1, 0x24, 0x37, 0x34, 0x34, 0x74, 0xcd, 0x9a, 0x35, 0x60, 0xad, 0x6b, 0x57,
- 0x5c, 0xf8, 0xec, 0x7c, 0xe1, 0x40, 0x34, 0xc1, 0xc3, 0xfd, 0x11, 0x28, 0x23, 0x11, 0xbf, 0x29,
- 0x28, 0xc8, 0x5f, 0xc2, 0x99, 0xa2, 0x7e, 0xfd, 0xf8, 0xe3, 0x8f, 0x05, 0x85, 0x05, 0xe4, 0x1c,
- 0x5e, 0xc1, 0xb0, 0x68, 0x90, 0x3f, 0xd4, 0x81, 0x2a, 0x20, 0x64, 0x27, 0x92, 0xa0, 0x3d, 0x45,
- 0xce, 0xe2, 0xdf, 0xc4, 0xab, 0x55, 0x1d, 0x28, 0x9a, 0x7f, 0xe1, 0xc4, 0xfa, 0x65, 0xcb, 0x34,
- 0x10, 0x08, 0x53, 0x0b, 0x27, 0x7e, 0x20, 0xc1, 0x8a, 0x47, 0x71, 0x43, 0x03, 0xe8, 0xe8, 0x6c,
- 0xbf, 0x70, 0xc1, 0x2d, 0x2e, 0x2e, 0xbe, 0xac, 0xac, 0x0c, 0xf5, 0x5d, 0x5a, 0x7f, 0xe2, 0x9b,
- 0xd2, 0xd2, 0xb2, 0xbe, 0xbe, 0x7e, 0xa4, 0xcb, 0x57, 0xae, 0x88, 0x9b, 0xca, 0x47, 0x1b, 0x9e,
- 0x2a, 0x31, 0x31, 0x69, 0x98, 0x5c, 0x5c, 0x65, 0xeb, 0x58, 0x8b, 0xf9, 0x00, 0x0f, 0x43, 0x43,
- 0x2c, 0x11, 0xbf, 0x5d, 0x88, 0x5a, 0x39, 0x98, 0x25, 0x60, 0xa7, 0x12, 0xd0, 0x1d, 0x62, 0xf4,
- 0x31, 0x1b, 0xec, 0xec, 0x6c, 0xde, 0xbe, 0x1b, 0xe8, 0xeb, 0xaf, 0xbf, 0x26, 0xda, 0xe7, 0x7f,
- 0xfe, 0xa5, 0xba, 0xba, 0x06, 0x5a, 0x57, 0xe2, 0xe8, 0xd5, 0x6b, 0xd7, 0x50, 0xf4, 0xc0, 0x64,
- 0x5e, 0x7e, 0xc1, 0xe2, 0x51, 0x63, 0xbd, 0x3e, 0x21, 0x3d, 0x3b, 0xc8, 0x87, 0x6a, 0x61, 0x00,
- 0x91, 0x4a, 0xfc, 0x22, 0xb9, 0x46, 0x0a, 0xb1, 0xec, 0x46, 0x77, 0x4f, 0xcf, 0x98, 0x6d, 0x50,
- 0x7e, 0x7e, 0xf7, 0x29, 0xda, 0x1c, 0x99, 0x54, 0xf0, 0x22, 0xec, 0x62, 0xb1, 0xfa, 0xa8, 0x9e,
- 0x23, 0xd4, 0xd9, 0x4a, 0x72, 0xa5, 0x4d, 0xf1, 0x52, 0x33, 0x14, 0x62, 0x8b, 0x4b, 0x4a, 0x56,
- 0xac, 0x58, 0x21, 0x7d, 0x43, 0x80, 0x0d, 0xf1, 0x29, 0x55, 0xbf, 0x20, 0x3d, 0xb9, 0x43, 0x3c,
- 0x68, 0x2a, 0xd4, 0x0b, 0x9c, 0x1f, 0x14, 0xf4, 0xc4, 0xd9, 0xf9, 0x3c, 0x1c, 0xdf, 0x99, 0x63,
- 0x36, 0x65, 0xe1, 0xb7, 0x7a, 0xab, 0x92, 0x8a, 0x73, 0x13, 0xd7, 0xbf, 0x3a, 0xef, 0x12, 0x55,
- 0x75, 0xea, 0xb4, 0x69, 0xd7, 0xaf, 0xdf, 0x20, 0xe7, 0xef, 0x10, 0x4a, 0xa0, 0xbd, 0xbd, 0xc3,
- 0xd6, 0xf6, 0xe8, 0x37, 0xdf, 0x7c, 0x23, 0xde, 0x07, 0x41, 0x57, 0x57, 0xab, 0xb1, 0x2e, 0x97,
- 0x1c, 0x12, 0xf0, 0x98, 0x68, 0x93, 0x01, 0x62, 0x07, 0x08, 0xc4, 0x0e, 0xf3, 0xbb, 0x7a, 0xba,
- 0xdb, 0xec, 0xed, 0xed, 0x71, 0x32, 0x4e, 0xc3, 0x93, 0xc7, 0x44, 0x05, 0x0b, 0xb9, 0x0c, 0xc1,
- 0x60, 0x86, 0x70, 0x20, 0x89, 0x98, 0xe0, 0x3c, 0x54, 0x39, 0x2c, 0xe8, 0xd1, 0xd4, 0x7c, 0x65,
- 0x38, 0x10, 0xb2, 0xc8, 0xc4, 0xc4, 0xa4, 0xb3, 0xab, 0x9b, 0xec, 0x6d, 0x1c, 0x16, 0x08, 0x05,
- 0x95, 0x95, 0xe5, 0x9a, 0x9a, 0xdb, 0x7c, 0xee, 0xdd, 0xe0, 0x0f, 0x32, 0x88, 0xd8, 0x8d, 0xe5,
- 0xc7, 0xef, 0x3c, 0xc9, 0x6f, 0xde, 0xd7, 0x5f, 0xbe, 0xe6, 0xc1, 0x75, 0x44, 0xbd, 0x9b, 0xe5,
- 0xe4, 0xe4, 0x28, 0x19, 0xfc, 0xe1, 0x92, 0x80, 0x9a, 0x8a, 0x48, 0x89, 0x58, 0x7d, 0xfd, 0x7d,
- 0x37, 0x6e, 0x78, 0xa6, 0x67, 0x64, 0xc4, 0xc6, 0xc6, 0x2d, 0x5e, 0xbc, 0x58, 0x3a, 0x6f, 0xf1,
- 0x52, 0xb2, 0x10, 0xa9, 0x72, 0xf2, 0x48, 0x28, 0xf7, 0x31, 0xd1, 0x05, 0x0a, 0xa5, 0xfa, 0xa7,
- 0x20, 0x85, 0xc7, 0x1c, 0x98, 0x74, 0xe1, 0xc2, 0x05, 0x81, 0x80, 0x4b, 0xaa, 0xa6, 0x0e, 0x11,
- 0xaf, 0x49, 0x08, 0x79, 0xc0, 0x6b, 0x44, 0x7c, 0x50, 0x5c, 0x9c, 0xf3, 0x36, 0xad, 0x94, 0x62,
- 0x9b, 0x38, 0x71, 0x52, 0x4e, 0x4e, 0x2e, 0x35, 0x9a, 0x8b, 0x52, 0x8f, 0x62, 0x43, 0x05, 0x84,
- 0x0b, 0xa0, 0xc6, 0x91, 0x86, 0x87, 0x87, 0x4b, 0xf4, 0x0e, 0x40, 0xc4, 0xa6, 0xa5, 0x67, 0x50,
- 0x88, 0x95, 0x5e, 0xfe, 0x1d, 0xef, 0x15, 0x42, 0x86, 0x8d, 0x54, 0xfb, 0x83, 0xf4, 0x3b, 0x9e,
- 0x3a, 0x7d, 0xfa, 0xe5, 0xc8, 0xd8, 0x91, 0x39, 0xb0, 0xf8, 0x58, 0x51, 0x59, 0x49, 0x8d, 0x1a,
- 0x42, 0xd6, 0xfd, 0x32, 0xb2, 0xb4, 0x8b, 0x18, 0xb1, 0xb8, 0x5b, 0x40, 0x60, 0xa0, 0x74, 0xdf,
- 0xfd, 0xdc, 0xb9, 0x73, 0x2f, 0x5d, 0xbe, 0x3c, 0x30, 0xc0, 0xa6, 0x46, 0xd5, 0x42, 0xa5, 0x3c,
- 0x7d, 0xfa, 0x54, 0x45, 0x45, 0x05, 0xe5, 0x5b, 0x58, 0x58, 0x08, 0xdc, 0xde, 0xf3, 0xf6, 0x3e,
- 0x73, 0xf6, 0xac, 0xef, 0x15, 0xe7, 0x9a, 0x78, 0x1f, 0x26, 0x23, 0xb9, 0x34, 0x3f, 0x69, 0xd3,
- 0xc6, 0x97, 0xad, 0x22, 0x60, 0x6c, 0x64, 0xda, 0xd3, 0xa7, 0x21, 0x43, 0xe4, 0x56, 0xe0, 0xa0,
- 0x68, 0xc4, 0xc5, 0xfb, 0x0c, 0x0c, 0x46, 0xb7, 0x9d, 0xca, 0xc8, 0x2c, 0x08, 0x0b, 0x0d, 0x18,
- 0xe6, 0xd5, 0x12, 0x81, 0x03, 0x3c, 0x1a, 0xd3, 0x8f, 0x6c, 0x2b, 0x48, 0x12, 0xf1, 0xaa, 0x9b,
- 0x1b, 0x2b, 0x76, 0xec, 0x78, 0x39, 0x41, 0x4f, 0x45, 0x65, 0x51, 0x6d, 0x4d, 0xb1, 0x90, 0x47,
- 0xf6, 0xb6, 0x0c, 0xe6, 0x09, 0xb9, 0xa5, 0x22, 0x7e, 0x4b, 0x53, 0x13, 0x43, 0xec, 0x17, 0x70,
- 0xb7, 0x19, 0x33, 0x66, 0x9c, 0x73, 0x76, 0xa6, 0x66, 0x5c, 0x8a, 0xc8, 0x49, 0xa9, 0x50, 0xec,
- 0xd4, 0x28, 0x1a, 0x59, 0x59, 0x99, 0xa0, 0x40, 0x5f, 0x6e, 0x7f, 0x25, 0x82, 0x35, 0x7e, 0x8f,
- 0x57, 0x7b, 0xc5, 0xc9, 0x10, 0xbf, 0xa3, 0x86, 0x86, 0x07, 0x34, 0x34, 0x34, 0xa0, 0x30, 0x3f,
- 0xd6, 0x24, 0x71, 0x6a, 0x14, 0x37, 0x39, 0x15, 0xf1, 0x7b, 0x04, 0x05, 0xde, 0xde, 0x3e, 0xf9,
- 0x05, 0x85, 0xc8, 0xa5, 0x37, 0xc4, 0xb3, 0x6f, 0xb6, 0x75, 0xeb, 0xd6, 0x53, 0xf4, 0xe2, 0xeb,
- 0xeb, 0x3b, 0x66, 0x07, 0x84, 0xa5, 0x25, 0xa4, 0xb2, 0xb7, 0xaf, 0x8f, 0x97, 0xaf, 0xcf, 0x9d,
- 0xfb, 0x7e, 0xb7, 0x1b, 0x1b, 0xca, 0x45, 0x82, 0x3e, 0x3e, 0x7f, 0x20, 0x28, 0x28, 0x60, 0xf4,
- 0x58, 0x02, 0x94, 0x26, 0x9e, 0x61, 0xe5, 0xca, 0x55, 0x64, 0x5a, 0xa9, 0xfe, 0x2a, 0x4f, 0x7e,
- 0x42, 0xb6, 0x48, 0xb4, 0xb5, 0xb5, 0x03, 0x93, 0x70, 0x7f, 0xe2, 0x6e, 0x26, 0xf1, 0xa1, 0x33,
- 0x67, 0xce, 0xfa, 0xf9, 0xf9, 0x79, 0xfb, 0xf8, 0x40, 0x78, 0x4b, 0x5c, 0x08, 0x92, 0x87, 0x08,
- 0xa7, 0x10, 0x2b, 0xbd, 0x1e, 0x11, 0xd4, 0x51, 0x43, 0x43, 0x23, 0xd5, 0x7c, 0x07, 0x01, 0x29,
- 0x1d, 0x5a, 0x82, 0x48, 0xa9, 0x17, 0xfc, 0xe5, 0xd5, 0x7e, 0x01, 0xd4, 0x11, 0xaa, 0xe3, 0xf5,
- 0xbc, 0x8b, 0xcb, 0xcf, 0x2f, 0xe7, 0xcf, 0xbe, 0x20, 0x58, 0x48, 0x53, 0x0b, 0x8b, 0x57, 0x7a,
- 0xab, 0x71, 0x67, 0xd4, 0x9d, 0x87, 0x0f, 0x1f, 0xa1, 0xd0, 0x89, 0x45, 0x75, 0x84, 0xa2, 0xca,
- 0xaa, 0x2a, 0xe8, 0x0a, 0x71, 0xce, 0x7b, 0x7a, 0x7a, 0x96, 0x95, 0x57, 0xa0, 0x3e, 0x5e, 0xbf,
- 0xe1, 0x19, 0xe7, 0xef, 0xd9, 0x98, 0xec, 0xcf, 0xac, 0x4e, 0x6c, 0xad, 0xc9, 0x33, 0x33, 0x31,
- 0xc6, 0xb5, 0xe0, 0xc3, 0xf9, 0xf3, 0xe7, 0x83, 0x9c, 0xa9, 0xc1, 0x96, 0xc3, 0xa4, 0x62, 0x47,
- 0xf5, 0x5c, 0xb5, 0x6a, 0xd5, 0xe8, 0x5a, 0x36, 0x6e, 0xdc, 0x17, 0x27, 0x4e, 0x1c, 0x1b, 0x64,
- 0xb7, 0x88, 0xb8, 0xe5, 0xc2, 0x81, 0xe7, 0x82, 0xbe, 0x10, 0x41, 0x5f, 0xb0, 0x70, 0x20, 0x56,
- 0xc8, 0x29, 0xaa, 0x2c, 0x4b, 0xd3, 0xd3, 0xdb, 0x29, 0x7e, 0x41, 0x5c, 0x75, 0xcc, 0xc1, 0x0e,
- 0x9e, 0x8e, 0x58, 0x51, 0x8a, 0x53, 0x4c, 0x24, 0x5e, 0xad, 0x48, 0xd8, 0xe3, 0xee, 0xee, 0x42,
- 0x9d, 0x00, 0xc8, 0x2d, 0x5e, 0xac, 0xfe, 0x28, 0x20, 0x60, 0x68, 0x88, 0x47, 0x85, 0x0f, 0x3d,
- 0x3d, 0xbd, 0x77, 0xef, 0x7a, 0xe1, 0x31, 0xc4, 0xbf, 0xa8, 0xb2, 0x48, 0x39, 0x3a, 0xf2, 0x09,
- 0xb7, 0xbf, 0xaa, 0xbb, 0x2d, 0x25, 0x36, 0x9a, 0x58, 0x2f, 0x71, 0xdf, 0x3e, 0x03, 0x94, 0x1d,
- 0xb5, 0xa0, 0xf7, 0x47, 0x41, 0x2c, 0x35, 0x9c, 0x60, 0xe6, 0xcc, 0x99, 0x00, 0x86, 0xa5, 0x95,
- 0x55, 0x40, 0x40, 0x20, 0x82, 0x0e, 0xe4, 0xdb, 0xbb, 0x76, 0x5e, 0x53, 0x86, 0x0a, 0xf8, 0xf0,
- 0xd1, 0x23, 0xe4, 0x3f, 0x54, 0xa2, 0x93, 0x93, 0xd3, 0xaf, 0x8e, 0x86, 0x82, 0xae, 0x88, 0x8b,
- 0x8b, 0x11, 0x89, 0xf8, 0x4c, 0x66, 0x8f, 0xb9, 0xb9, 0xf9, 0xe8, 0x43, 0x00, 0xa1, 0xe3, 0xf1,
- 0xe3, 0x15, 0x15, 0x95, 0xe5, 0xe5, 0x15, 0xe5, 0x15, 0x95, 0xf0, 0x8f, 0x12, 0xd7, 0xa2, 0x5e,
- 0xf3, 0x05, 0x82, 0xfe, 0x01, 0x36, 0x2a, 0xda, 0xdb, 0x6b, 0x09, 0xbc, 0xac, 0xc5, 0xe1, 0xc3,
- 0x7c, 0x04, 0x86, 0x64, 0x97, 0x84, 0x74, 0xfb, 0x15, 0xe4, 0x9c, 0x90, 0x6c, 0x17, 0xc2, 0x5b,
- 0xd8, 0x8e, 0x35, 0xdc, 0x1a, 0xe1, 0xc6, 0x88, 0xc7, 0x7f, 0xb9, 0xcb, 0x06, 0x3e, 0x06, 0x06,
- 0x06, 0xc2, 0xbf, 0xe0, 0xb1, 0xb3, 0xb3, 0x73, 0x5e, 0xce, 0xf8, 0x1e, 0x91, 0x04, 0x55, 0x0c,
- 0xc6, 0xe8, 0xb6, 0x17, 0xe4, 0x0c, 0xaa, 0x61, 0x74, 0x74, 0x0c, 0x55, 0xfa, 0x60, 0xc8, 0xa0,
- 0x27, 0x4f, 0x50, 0x95, 0x46, 0xc7, 0x0e, 0x08, 0x09, 0x9b, 0x9b, 0x5b, 0x52, 0x52, 0xd3, 0x1e,
- 0xf8, 0xfb, 0xe7, 0x84, 0xf9, 0x35, 0xa7, 0x05, 0x30, 0xab, 0xe2, 0x06, 0x3b, 0x4b, 0xd3, 0x53,
- 0xa2, 0x4f, 0x9d, 0x3c, 0x71, 0xf6, 0xec, 0xe9, 0xb0, 0xf0, 0x30, 0x32, 0xbe, 0xfb, 0x99, 0xd4,
- 0x30, 0xbd, 0xd7, 0xaf, 0x5f, 0x97, 0x5e, 0x88, 0x63, 0xdd, 0xba, 0xb5, 0x8d, 0x8d, 0x0c, 0x72,
- 0x64, 0x45, 0x09, 0xfc, 0x35, 0x81, 0x55, 0x76, 0xa2, 0x88, 0x53, 0x50, 0x52, 0x98, 0xb0, 0x67,
- 0xb7, 0xee, 0x17, 0xa3, 0x7a, 0x6a, 0xa6, 0x4e, 0x9d, 0x12, 0x1e, 0x16, 0x24, 0xe0, 0xb5, 0x12,
- 0x63, 0x30, 0xc0, 0xb1, 0x20, 0x58, 0x5e, 0x63, 0x1f, 0xab, 0x05, 0x12, 0xf4, 0x13, 0x32, 0x6a,
- 0xd0, 0xd1, 0xd1, 0x49, 0x49, 0x49, 0xa5, 0xb4, 0x16, 0x52, 0x4b, 0x6b, 0xdb, 0xa9, 0x53, 0xa7,
- 0x25, 0x86, 0xbb, 0xa3, 0x20, 0x96, 0x2f, 0x5f, 0x96, 0x9e, 0x96, 0x84, 0xc0, 0x36, 0x31, 0x29,
- 0xf9, 0x86, 0xa7, 0xa7, 0xa9, 0xa9, 0xd9, 0xea, 0xd5, 0xab, 0xe7, 0xcc, 0x99, 0x43, 0xf5, 0x0a,
- 0x7d, 0xb8, 0x2a, 0x20, 0xc2, 0x2e, 0x62, 0x3d, 0x8d, 0x79, 0x1b, 0x36, 0x6c, 0x38, 0x76, 0xcc,
- 0x11, 0x35, 0x1a, 0x19, 0x2e, 0x11, 0xaa, 0xbc, 0xa5, 0x21, 0x3c, 0xbf, 0x77, 0xcf, 0x6b, 0x80,
- 0x0d, 0x3d, 0x36, 0xdc, 0xd8, 0xd4, 0xb4, 0x73, 0xd4, 0x20, 0xab, 0xd7, 0x19, 0xf4, 0x67, 0x71,
- 0x71, 0x31, 0xd0, 0x51, 0x57, 0x5f, 0x2f, 0x91, 0xdb, 0x78, 0xc7, 0x8c, 0xcc, 0x4c, 0x4a, 0x98,
- 0xe1, 0x5f, 0xe0, 0x41, 0xe2, 0x5a, 0x72, 0x01, 0x25, 0x62, 0x39, 0x8b, 0x03, 0x07, 0x0e, 0xbc,
- 0x65, 0x1f, 0x2b, 0xb1, 0x1d, 0x9b, 0xcc, 0x82, 0xc8, 0xa8, 0x48, 0xea, 0x9e, 0x99, 0x99, 0x59,
- 0xd2, 0x80, 0x74, 0x72, 0xfa, 0x49, 0xbc, 0xc0, 0x0b, 0x28, 0xe2, 0x8b, 0x2f, 0x24, 0x7b, 0xfd,
- 0xa0, 0x40, 0x46, 0x35, 0xb4, 0xbe, 0xf0, 0xfb, 0xe0, 0x37, 0x0f, 0x0f, 0x0f, 0xe0, 0x70, 0xd5,
- 0xea, 0xd5, 0xd4, 0xfc, 0xaf, 0x17, 0x53, 0x14, 0x45, 0x90, 0x79, 0x22, 0x94, 0x72, 0x40, 0x40,
- 0xc0, 0x68, 0xba, 0x06, 0xb7, 0x83, 0x1b, 0x49, 0xdf, 0xfa, 0x33, 0x88, 0xd4, 0xda, 0xda, 0x5a,
- 0xba, 0x3d, 0x19, 0x61, 0x3e, 0x94, 0x46, 0x61, 0x51, 0x71, 0x44, 0x78, 0x78, 0x69, 0xfc, 0xe3,
- 0xd6, 0xcc, 0xc0, 0xde, 0x8a, 0xc8, 0xc1, 0xf6, 0x5c, 0xde, 0x40, 0x13, 0x87, 0xdd, 0xcd, 0xe7,
- 0x73, 0xc9, 0x99, 0x40, 0x44, 0xcd, 0x2a, 0xaf, 0xa8, 0x00, 0xd9, 0x4a, 0x7b, 0x34, 0x48, 0x8b,
- 0xb4, 0xb4, 0x14, 0x91, 0x68, 0x80, 0x18, 0x54, 0x80, 0xa8, 0x81, 0x93, 0x27, 0x1c, 0xcc, 0x11,
- 0x72, 0xcb, 0xca, 0x8a, 0x93, 0x76, 0xe8, 0x6a, 0x49, 0x44, 0xd6, 0xdb, 0xb6, 0x6d, 0xa9, 0x61,
- 0xe4, 0x93, 0x04, 0x9b, 0x43, 0x44, 0x16, 0x9c, 0x22, 0x11, 0xbf, 0x39, 0x3e, 0x2e, 0x02, 0x48,
- 0xc6, 0x7d, 0x6c, 0x6d, 0x6d, 0x19, 0x8c, 0x6a, 0xaa, 0x8d, 0x97, 0x9a, 0xef, 0x6f, 0x6c, 0x6c,
- 0x3c, 0xe6, 0x9a, 0x2a, 0x28, 0x0b, 0x14, 0x0d, 0x78, 0xa6, 0x88, 0xdc, 0x4a, 0x00, 0x61, 0x38,
- 0x90, 0xa0, 0xaa, 0xaa, 0x0a, 0x72, 0xf8, 0xec, 0xf3, 0xcf, 0xff, 0xf6, 0xb7, 0xbf, 0x7d, 0x08,
- 0x68, 0xc5, 0xc3, 0x09, 0xa0, 0x4b, 0x35, 0x35, 0x35, 0xe1, 0x49, 0xa1, 0x49, 0x62, 0x62, 0xe3,
- 0xc6, 0x1c, 0x80, 0xfd, 0x66, 0x53, 0x54, 0xa4, 0x3f, 0x7d, 0x1a, 0xc4, 0x19, 0x64, 0x89, 0x84,
- 0xc8, 0x49, 0x41, 0x4e, 0x4e, 0xb6, 0xf4, 0x00, 0x18, 0x69, 0x33, 0x30, 0x30, 0x40, 0x2c, 0x8f,
- 0xc2, 0x05, 0xb7, 0x8f, 0x26, 0x64, 0xb2, 0xaa, 0x2e, 0xe7, 0x70, 0x39, 0xd4, 0xc4, 0x46, 0x14,
- 0xcb, 0x4f, 0x52, 0xbb, 0xb7, 0x00, 0xa8, 0xf8, 0x1e, 0xb2, 0x3f, 0x26, 0x26, 0x66, 0xcc, 0xce,
- 0x62, 0x69, 0x9b, 0x3d, 0x7b, 0x76, 0x5c, 0x5c, 0x2c, 0x87, 0xc3, 0x16, 0x89, 0x04, 0xc3, 0xc3,
- 0xa2, 0x8b, 0x17, 0x2f, 0x4a, 0x3b, 0xfd, 0x98, 0xd8, 0x58, 0xf1, 0xf0, 0xc5, 0x07, 0x0f, 0x1e,
- 0x48, 0x77, 0x91, 0xa0, 0x98, 0x98, 0x2c, 0xd6, 0xf0, 0xab, 0x6d, 0xad, 0x08, 0x43, 0x0e, 0x1e,
- 0x24, 0xd6, 0x3a, 0x80, 0xca, 0x05, 0xed, 0x83, 0xc3, 0x41, 0xe0, 0x88, 0xdc, 0x6b, 0x6b, 0xeb,
- 0xaa, 0x6b, 0x6a, 0xdb, 0x3b, 0x3a, 0x47, 0x0f, 0xc0, 0xd8, 0xb4, 0x79, 0x73, 0x75, 0x4d, 0x0d,
- 0xb5, 0x4c, 0xe2, 0xdd, 0xbb, 0x77, 0x55, 0xd5, 0xd4, 0xc6, 0x6c, 0x82, 0x86, 0x03, 0x82, 0x66,
- 0xa8, 0xa9, 0xad, 0xcd, 0x48, 0x4b, 0xae, 0xc9, 0x08, 0x6f, 0xcf, 0x7d, 0xca, 0xac, 0x8c, 0x18,
- 0x6c, 0xcd, 0xe4, 0xf5, 0xd7, 0x0a, 0x79, 0xbd, 0x22, 0xd1, 0x10, 0x5e, 0x81, 0xcf, 0x17, 0xc4,
- 0xc7, 0x27, 0x00, 0x21, 0xd2, 0x2b, 0xc8, 0x7d, 0x42, 0xd4, 0x3e, 0x27, 0x84, 0x0c, 0x42, 0x61,
- 0xbf, 0x90, 0xdf, 0x41, 0xc4, 0x0b, 0x43, 0xd5, 0x22, 0x5e, 0x7d, 0x6b, 0x53, 0x09, 0xe0, 0xfa,
- 0xf9, 0xab, 0x55, 0x15, 0x97, 0xbb, 0xba, 0x9e, 0xe1, 0x71, 0x1a, 0x88, 0x71, 0xb3, 0x03, 0x09,
- 0x44, 0x1a, 0xcc, 0x19, 0xe6, 0x37, 0x3a, 0x39, 0xd9, 0x43, 0x62, 0xf9, 0xf8, 0xf8, 0x40, 0xd5,
- 0x88, 0x67, 0x07, 0x43, 0x53, 0x41, 0xb1, 0x8f, 0xf9, 0x8b, 0x94, 0xa1, 0x28, 0x41, 0xc8, 0x8c,
- 0xea, 0x6a, 0xc4, 0x44, 0xf7, 0xee, 0x79, 0xdb, 0xd9, 0xdb, 0x6b, 0x6a, 0x6a, 0xd1, 0x15, 0x15,
- 0x27, 0x4f, 0x9e, 0x0c, 0x8a, 0xf8, 0x90, 0x06, 0x2e, 0x6a, 0x14, 0x37, 0xe2, 0x44, 0x45, 0x45,
- 0xa5, 0x9d, 0xe4, 0x32, 0x86, 0x90, 0xfa, 0xfe, 0x0f, 0x1f, 0xbe, 0xd3, 0x4a, 0x38, 0x28, 0xf4,
- 0x95, 0x2b, 0x97, 0x67, 0x66, 0x24, 0x09, 0xf9, 0x3d, 0x22, 0x7e, 0x17, 0xd1, 0xd9, 0x27, 0x64,
- 0x07, 0x07, 0x3f, 0xfe, 0xd5, 0x2d, 0xa8, 0xf0, 0x5e, 0xae, 0x17, 0x5c, 0xe1, 0xd9, 0x41, 0x78,
- 0x12, 0xeb, 0x48, 0xe0, 0x9e, 0x2e, 0x2e, 0x2e, 0x23, 0x73, 0x1b, 0x05, 0xa0, 0x34, 0x2d, 0x2d,
- 0xc9, 0xf1, 0xab, 0xce, 0xce, 0xce, 0xd4, 0x6c, 0x32, 0xa1, 0x90, 0xe7, 0xe9, 0x79, 0x7d, 0xe2,
- 0xc4, 0x37, 0xad, 0x00, 0x4c, 0x68, 0x30, 0x35, 0xd5, 0xb2, 0xb2, 0x42, 0xa1, 0x60, 0x40, 0x28,
- 0x1c, 0x10, 0x09, 0x39, 0x90, 0x22, 0x08, 0x81, 0x25, 0xe4, 0x04, 0x90, 0xc3, 0xea, 0xeb, 0xe3,
- 0x70, 0x87, 0x06, 0xf1, 0x1f, 0x8f, 0x9f, 0x90, 0x90, 0x20, 0x4d, 0x23, 0xc0, 0x70, 0x51, 0x51,
- 0x11, 0x50, 0xcd, 0xe7, 0x0b, 0xe1, 0xd3, 0x89, 0xc4, 0xe3, 0x23, 0xae, 0x87, 0x5a, 0xc3, 0xa1,
- 0xb0, 0xf0, 0x70, 0x00, 0x35, 0x2b, 0x27, 0x37, 0x32, 0x32, 0x2a, 0x22, 0x22, 0x32, 0x29, 0x39,
- 0xa5, 0xa2, 0xb2, 0xaa, 0xba, 0xba, 0x46, 0xdc, 0x61, 0xb4, 0x71, 0xd3, 0xa6, 0x9a, 0xda, 0x3a,
- 0xdc, 0x1f, 0x1e, 0x04, 0x6f, 0x4d, 0x6d, 0x35, 0x32, 0xe6, 0x33, 0xe3, 0xd0, 0xc1, 0x43, 0x87,
- 0x5a, 0x5a, 0x5b, 0x19, 0xe5, 0xc5, 0xad, 0x25, 0x29, 0xdd, 0x65, 0x31, 0x7d, 0xb5, 0x09, 0x9c,
- 0x8e, 0x5c, 0xfe, 0x40, 0xbd, 0x90, 0xcf, 0x04, 0x14, 0x5b, 0x5a, 0x9a, 0x8f, 0x1e, 0x3d, 0x4a,
- 0xed, 0x52, 0x24, 0x71, 0x2d, 0x88, 0x0e, 0x21, 0x7a, 0x5b, 0x7b, 0xdb, 0xf0, 0x30, 0x5f, 0x24,
- 0x1c, 0x14, 0x0a, 0x98, 0x88, 0x6d, 0x87, 0x05, 0xdd, 0xac, 0xde, 0xa6, 0xbd, 0x7b, 0x77, 0x4b,
- 0xbb, 0x24, 0x3a, 0x9d, 0xf6, 0x3c, 0x21, 0x94, 0x58, 0x52, 0x63, 0x20, 0x51, 0xd0, 0xf7, 0x54,
- 0x40, 0xb4, 0x37, 0x26, 0x0a, 0x87, 0x18, 0x8c, 0xca, 0xbc, 0xd6, 0xd6, 0x46, 0xa1, 0x50, 0x48,
- 0xf6, 0x77, 0x13, 0x6d, 0xbc, 0xb9, 0x79, 0xf9, 0x08, 0xa8, 0x7f, 0x55, 0x86, 0x01, 0x99, 0xa0,
- 0xa3, 0x92, 0x92, 0x52, 0x20, 0xca, 0xeb, 0xde, 0x3d, 0x80, 0x76, 0xcb, 0xd6, 0xad, 0x8a, 0x24,
- 0x68, 0x3f, 0xfd, 0xec, 0xb3, 0xf7, 0x5e, 0x25, 0x86, 0x42, 0x2c, 0x42, 0xe9, 0x85, 0x0b, 0x17,
- 0xee, 0xde, 0xbd, 0xe7, 0xd2, 0xa5, 0xcb, 0xc9, 0x29, 0xa9, 0x08, 0x9f, 0xdf, 0x5e, 0x16, 0x02,
- 0x5a, 0x5a, 0x9a, 0xdb, 0x2a, 0xca, 0xb3, 0x89, 0x91, 0xed, 0xc4, 0xd2, 0x82, 0xe5, 0xa2, 0xa1,
- 0x9a, 0x81, 0xfe, 0xc6, 0xb3, 0x67, 0x7e, 0x7d, 0x43, 0x2b, 0xc4, 0x8f, 0x41, 0x41, 0x81, 0x40,
- 0x5d, 0x4b, 0x4b, 0x8b, 0x04, 0xc9, 0x00, 0xed, 0x25, 0xc5, 0xf9, 0xc8, 0x6a, 0x62, 0x22, 0x12,
- 0x32, 0x5c, 0xc8, 0x95, 0x93, 0x93, 0xec, 0x3b, 0x0b, 0x08, 0x78, 0x30, 0x2c, 0x64, 0x0b, 0x05,
- 0x2c, 0x91, 0x80, 0xc5, 0xe5, 0x30, 0xcd, 0xcd, 0x4c, 0x5e, 0xa7, 0x0d, 0x10, 0xd0, 0xe9, 0x68,
- 0x6b, 0x56, 0x56, 0xe4, 0x13, 0x93, 0x44, 0x88, 0xd6, 0x89, 0x16, 0x91, 0xa0, 0xbb, 0xad, 0xb5,
- 0x4e, 0x62, 0xb1, 0x23, 0x18, 0x9c, 0xcb, 0x00, 0x9b, 0x0d, 0x4d, 0xd8, 0xd5, 0xd5, 0xdd, 0xcb,
- 0x64, 0x15, 0x8e, 0xb5, 0x8c, 0x15, 0x14, 0x1d, 0xc2, 0x79, 0x90, 0x6a, 0x5d, 0x7d, 0x03, 0xd0,
- 0x58, 0x59, 0xc5, 0x80, 0xda, 0x04, 0x38, 0x01, 0x57, 0x5c, 0x9e, 0x96, 0x9e, 0x01, 0xd5, 0x1d,
- 0x9f, 0xf0, 0x1c, 0xfa, 0x0a, 0xa0, 0x85, 0xf0, 0x68, 0x68, 0x6c, 0xbc, 0x7e, 0xfd, 0x86, 0xf8,
- 0x72, 0x08, 0x80, 0xd4, 0xd4, 0xb4, 0xb3, 0x67, 0xcf, 0xbe, 0x0d, 0x2d, 0xa8, 0xa9, 0xa9, 0xe5,
- 0xe4, 0xe4, 0x76, 0xb5, 0x36, 0x31, 0x1b, 0x4a, 0xfb, 0x1a, 0x72, 0xd9, 0xad, 0xf9, 0x43, 0x4c,
- 0x86, 0x80, 0xd3, 0xd1, 0xd5, 0xd1, 0x14, 0x11, 0x11, 0xa6, 0xae, 0x3e, 0x46, 0x7b, 0x0e, 0x65,
- 0x0a, 0x0a, 0x0a, 0x29, 0xa9, 0xa9, 0x42, 0xb2, 0x6b, 0x80, 0x98, 0xbb, 0x44, 0xd4, 0xd0, 0x41,
- 0x16, 0xb3, 0xd3, 0xd1, 0x71, 0xec, 0xa5, 0x27, 0x36, 0x6d, 0xda, 0xd0, 0xdc, 0x88, 0x68, 0xab,
- 0x48, 0xd0, 0x1f, 0x41, 0x2c, 0xd1, 0xcf, 0xf4, 0x17, 0xf4, 0x47, 0x0a, 0xb9, 0x85, 0x44, 0x8e,
- 0xa1, 0x14, 0x44, 0x42, 0x90, 0x2b, 0x7b, 0x70, 0x30, 0x34, 0x34, 0x54, 0xbc, 0x79, 0xe8, 0xaf,
- 0x1a, 0x32, 0xc4, 0xc6, 0xc6, 0x06, 0x79, 0x88, 0x27, 0x41, 0x80, 0x76, 0xc4, 0xd2, 0x12, 0xce,
- 0x45, 0x81, 0x46, 0x9b, 0x30, 0x61, 0x22, 0x15, 0x85, 0xbd, 0x37, 0x62, 0x51, 0x49, 0xe9, 0x74,
- 0xc5, 0xed, 0xba, 0xba, 0xa0, 0xb5, 0x67, 0xa1, 0xa1, 0x86, 0x86, 0x07, 0x40, 0x08, 0x5f, 0x7e,
- 0xf5, 0xeb, 0x06, 0xfe, 0xd9, 0xbd, 0x7b, 0x7b, 0x73, 0x63, 0xe1, 0x30, 0xb7, 0x52, 0xc8, 0x4e,
- 0x23, 0xb7, 0x27, 0x88, 0xc6, 0x1f, 0xed, 0xcd, 0x99, 0xfb, 0xf4, 0x77, 0x7d, 0xf5, 0x95, 0xf8,
- 0x1e, 0x5f, 0x7e, 0x26, 0x69, 0xc4, 0x74, 0x0c, 0x75, 0x75, 0xb5, 0xec, 0xac, 0xe4, 0x61, 0xd1,
- 0xc0, 0x8d, 0x1b, 0x57, 0x25, 0x5e, 0x56, 0x59, 0x59, 0x49, 0xc0, 0xeb, 0x16, 0x22, 0x5e, 0xe0,
- 0xb5, 0x08, 0x05, 0xed, 0xed, 0x6d, 0x35, 0xd2, 0xeb, 0xf3, 0x64, 0x65, 0xc4, 0x91, 0x03, 0x08,
- 0x6b, 0x88, 0xc4, 0x6f, 0x6a, 0x6b, 0x29, 0xff, 0x7e, 0xc9, 0x18, 0x25, 0x88, 0xfa, 0x68, 0x66,
- 0x66, 0x5c, 0x5d, 0x99, 0x25, 0x1a, 0xaa, 0x26, 0x85, 0x5c, 0x86, 0x70, 0x30, 0x57, 0x34, 0xc4,
- 0x88, 0x8a, 0x0c, 0x98, 0x31, 0x43, 0xb2, 0x53, 0xcf, 0xc1, 0xce, 0xb6, 0xa3, 0xad, 0xb5, 0xaa,
- 0x8a, 0x81, 0x88, 0xaf, 0xb6, 0xae, 0x1e, 0xbe, 0x5b, 0x7a, 0x29, 0x6c, 0x54, 0x2e, 0x37, 0x37,
- 0x37, 0x60, 0x35, 0x27, 0x37, 0x0f, 0x09, 0xf8, 0x04, 0x62, 0xaf, 0x5c, 0x21, 0x5e, 0x01, 0x31,
- 0x20, 0xf4, 0x5b, 0x7e, 0x01, 0xb1, 0xd1, 0x76, 0x58, 0x58, 0x38, 0xb1, 0x47, 0x49, 0x51, 0x31,
- 0xe5, 0x43, 0xc5, 0x97, 0x23, 0xd3, 0xe0, 0x67, 0xdf, 0x52, 0x78, 0x43, 0x9a, 0x42, 0x1e, 0x33,
- 0xbb, 0x3b, 0x39, 0xcc, 0x76, 0x6e, 0x6f, 0x13, 0xaf, 0xaf, 0x69, 0x90, 0xd5, 0x92, 0x97, 0x9d,
- 0x76, 0xf4, 0xa8, 0xcd, 0x1b, 0xf6, 0x4e, 0xc2, 0x4f, 0x5c, 0xba, 0x74, 0x89, 0xcd, 0x1e, 0x14,
- 0x2f, 0xc4, 0x31, 0x3c, 0x2c, 0x60, 0x32, 0xbb, 0x3d, 0x3c, 0x24, 0x1b, 0x55, 0xc4, 0xb6, 0x6b,
- 0x97, 0x2e, 0x87, 0xdd, 0x08, 0x49, 0x20, 0xe8, 0x0f, 0x17, 0xf6, 0xfa, 0x12, 0x63, 0x68, 0xfb,
- 0x42, 0x09, 0xd1, 0xcb, 0x6b, 0x86, 0xa8, 0x10, 0x0d, 0x0b, 0x21, 0x84, 0xee, 0x7a, 0x79, 0x21,
- 0x78, 0x7c, 0xa7, 0x75, 0x3c, 0xf0, 0xa6, 0x20, 0x40, 0x30, 0x6d, 0x52, 0x72, 0xf2, 0xd5, 0x6b,
- 0xd7, 0x4c, 0xcd, 0xcc, 0xd6, 0xac, 0x59, 0xbb, 0x60, 0x81, 0x0c, 0x20, 0x47, 0xed, 0x50, 0xfc,
- 0xae, 0x4c, 0x4b, 0xe9, 0x58, 0xc0, 0x73, 0x81, 0x8c, 0xcc, 0xa6, 0x4d, 0x9b, 0x40, 0xdd, 0x3e,
- 0x3e, 0xbe, 0x17, 0x2f, 0x5d, 0x82, 0x68, 0x3c, 0x03, 0x51, 0x3b, 0x86, 0x9d, 0x3b, 0x77, 0xce,
- 0xf9, 0xfc, 0x79, 0x97, 0x0b, 0x6e, 0x6e, 0x37, 0xae, 0x5d, 0xf0, 0xf3, 0x76, 0x6b, 0xaa, 0x4b,
- 0x21, 0x66, 0x61, 0xf4, 0x85, 0x09, 0x7b, 0xbd, 0x89, 0xc1, 0xbd, 0x3d, 0x37, 0x50, 0x43, 0xfb,
- 0xda, 0xc3, 0xc3, 0x83, 0x2f, 0x7b, 0xdd, 0x3a, 0xe3, 0x75, 0xdb, 0xd9, 0xeb, 0xf6, 0xf9, 0xbb,
- 0xb7, 0x9c, 0x6f, 0x5c, 0x3d, 0x29, 0x91, 0xae, 0x5d, 0x76, 0x7a, 0x12, 0x70, 0xbd, 0xa7, 0xa3,
- 0x40, 0xc4, 0xab, 0x89, 0x8b, 0xf6, 0xf3, 0x70, 0x73, 0xa0, 0xd2, 0x45, 0x22, 0xd9, 0x87, 0x85,
- 0xdc, 0x14, 0x0e, 0x95, 0x12, 0x9a, 0x6a, 0x30, 0x57, 0xc8, 0x2d, 0xea, 0x6a, 0xcb, 0xbe, 0x7e,
- 0xc5, 0xc9, 0xc3, 0xcd, 0xf1, 0x22, 0x99, 0x3c, 0xdc, 0x8e, 0x79, 0x5c, 0xb0, 0xeb, 0x69, 0x4b,
- 0x27, 0x9a, 0xc4, 0xd9, 0x89, 0x02, 0xf6, 0x73, 0xe1, 0x60, 0x9a, 0x88, 0x5b, 0x9c, 0x91, 0x1c,
- 0x48, 0xde, 0xc4, 0x51, 0x9c, 0x70, 0xb2, 0xaf, 0xb7, 0x5b, 0x23, 0x1e, 0x92, 0x9b, 0x47, 0xf4,
- 0xe3, 0xb0, 0x02, 0x05, 0xcc, 0x07, 0x42, 0x56, 0x90, 0x70, 0x20, 0xae, 0x24, 0x2f, 0xd0, 0xf3,
- 0xea, 0x09, 0x0f, 0x57, 0x07, 0x77, 0x97, 0x63, 0xee, 0xe7, 0x1d, 0xdd, 0xce, 0x39, 0xba, 0x9e,
- 0x39, 0x96, 0x9d, 0x18, 0x5e, 0x5f, 0x96, 0x17, 0x1b, 0x17, 0x1f, 0x15, 0x1d, 0xf3, 0x3c, 0x31,
- 0x09, 0x1e, 0xf0, 0x84, 0x93, 0x13, 0x31, 0xe7, 0x96, 0x30, 0xbb, 0x17, 0xff, 0xb3, 0xb3, 0x87,
- 0x70, 0x02, 0xf5, 0x65, 0x66, 0x65, 0x01, 0x9c, 0x70, 0xf1, 0x4d, 0x4d, 0x4d, 0x88, 0x55, 0xc1,
- 0xbd, 0x40, 0x57, 0x6d, 0x5d, 0x5d, 0x46, 0x66, 0x16, 0x28, 0x17, 0x09, 0x0e, 0x0b, 0x0c, 0x9c,
- 0x9e, 0x91, 0xf9, 0xde, 0x2b, 0xc0, 0xa3, 0x58, 0xe1, 0x82, 0x5d, 0x5d, 0xce, 0x87, 0x85, 0x3c,
- 0x8d, 0x8d, 0x0a, 0xbf, 0xef, 0x7b, 0xd7, 0xde, 0xce, 0x66, 0x99, 0x86, 0xc6, 0x1b, 0x34, 0x24,
- 0xa8, 0x60, 0xe7, 0xae, 0x5d, 0x54, 0x03, 0x1d, 0xb5, 0x10, 0x07, 0xb5, 0xae, 0xec, 0x8d, 0x1b,
- 0x37, 0xa4, 0x57, 0xbc, 0x11, 0x9b, 0xae, 0xae, 0x76, 0x3f, 0xab, 0x41, 0xc4, 0x2d, 0x11, 0x0e,
- 0xc4, 0x10, 0xe3, 0xb5, 0x58, 0xfe, 0x44, 0x87, 0x17, 0x27, 0x17, 0x88, 0x85, 0x9b, 0x63, 0xb1,
- 0x7a, 0x9d, 0xcf, 0x3b, 0xcf, 0x91, 0x5a, 0xa7, 0xf4, 0x6d, 0x6c, 0xee, 0xdc, 0xb9, 0xb7, 0x6e,
- 0xdd, 0xaa, 0xac, 0xac, 0x8c, 0x88, 0x8c, 0x74, 0x73, 0x73, 0x37, 0x34, 0x34, 0x44, 0x84, 0x32,
- 0x67, 0xce, 0xdc, 0x71, 0xa4, 0x4c, 0x7a, 0x8f, 0x51, 0x31, 0xd4, 0x96, 0x07, 0xd3, 0x67, 0xcc,
- 0x58, 0xb2, 0x64, 0x89, 0x9e, 0x9e, 0xde, 0xa9, 0x53, 0xa7, 0x6f, 0xdf, 0xb9, 0x13, 0x10, 0x18,
- 0xf8, 0xf4, 0x69, 0x48, 0x48, 0xc8, 0x33, 0x29, 0x0b, 0x25, 0xd6, 0x31, 0x8b, 0x8d, 0x45, 0x59,
- 0x94, 0x15, 0x67, 0xb1, 0xbb, 0x62, 0x89, 0x7d, 0x5e, 0x7a, 0xee, 0x0a, 0xbb, 0x5c, 0x88, 0x49,
- 0x04, 0xad, 0x47, 0xf8, 0x6d, 0x56, 0x82, 0x76, 0x27, 0x02, 0xba, 0xcc, 0x47, 0xc4, 0x2e, 0x30,
- 0xfd, 0x51, 0xc0, 0xc9, 0xeb, 0x53, 0x14, 0xb9, 0x65, 0x4c, 0x04, 0xf1, 0xc7, 0x40, 0xcc, 0xcb,
- 0x2f, 0x07, 0x22, 0x05, 0xfd, 0xcf, 0x04, 0xac, 0x00, 0x21, 0xf2, 0x0d, 0xa9, 0x2f, 0x48, 0x88,
- 0x8a, 0x8f, 0x13, 0x80, 0x4c, 0x22, 0x25, 0x10, 0xa3, 0xe6, 0x70, 0x1a, 0xeb, 0x09, 0x41, 0x05,
- 0xbd, 0xb7, 0x89, 0xa9, 0xb8, 0xbd, 0xf7, 0x88, 0xc1, 0x8a, 0x7d, 0xb8, 0x55, 0xdc, 0xc8, 0x69,
- 0x89, 0x64, 0x4a, 0x20, 0x2e, 0xec, 0x0f, 0x11, 0xb2, 0x7c, 0x05, 0xdd, 0x1e, 0xc4, 0x40, 0xdc,
- 0x8e, 0x13, 0xc4, 0x04, 0xf3, 0xee, 0xab, 0x24, 0x74, 0x43, 0xf9, 0xcc, 0x98, 0xa1, 0xae, 0x78,
- 0x4e, 0xeb, 0xf3, 0x81, 0xc6, 0xe7, 0x4c, 0x46, 0x7c, 0x67, 0x51, 0x54, 0x51, 0x6c, 0xe0, 0xe5,
- 0xcb, 0x57, 0x2e, 0x5e, 0xba, 0x7c, 0xed, 0xfa, 0xf5, 0x7b, 0xde, 0xde, 0xc8, 0x8a, 0x60, 0x22,
- 0x2f, 0x5e, 0xbc, 0x7f, 0x08, 0x91, 0x42, 0xe1, 0x89, 0xc2, 0xc3, 0x23, 0xe0, 0xfa, 0x01, 0x69,
- 0x60, 0x03, 0x54, 0x8c, 0x72, 0x41, 0x68, 0xff, 0x24, 0x38, 0x18, 0x10, 0x4d, 0x4c, 0x4a, 0xc6,
- 0x51, 0xd0, 0x6c, 0x56, 0x76, 0x4e, 0x63, 0x53, 0x33, 0x6a, 0xf9, 0xdb, 0xef, 0x2a, 0x2b, 0x6d,
- 0x54, 0xa0, 0x41, 0x6c, 0xb5, 0x20, 0x2b, 0x0b, 0xa7, 0xf0, 0xab, 0xad, 0x8e, 0xf3, 0xe6, 0xcd,
- 0x43, 0x19, 0x51, 0xc1, 0x23, 0xd5, 0x4e, 0x0b, 0xb8, 0x22, 0xbe, 0xc3, 0xf7, 0x6f, 0xa0, 0xc7,
- 0xa5, 0x4b, 0xbf, 0x2f, 0x2c, 0x48, 0x23, 0x06, 0x7b, 0x70, 0xb2, 0xc8, 0xb2, 0x88, 0x12, 0x0e,
- 0xa6, 0x0a, 0x87, 0x2a, 0xa0, 0x7e, 0x07, 0xd9, 0x2c, 0x0b, 0x0b, 0x8b, 0x31, 0xfb, 0x37, 0xdf,
- 0xd2, 0xbe, 0xfb, 0xee, 0xbb, 0x00, 0x62, 0x8b, 0xd8, 0xd2, 0xa0, 0x27, 0x4f, 0x4e, 0x9f, 0x39,
- 0xb3, 0x67, 0xcf, 0x1e, 0x75, 0xf5, 0x25, 0x33, 0x66, 0xce, 0x7c, 0xbf, 0xf6, 0x2e, 0x6a, 0x2c,
- 0x37, 0x58, 0x1a, 0x79, 0x02, 0xf0, 0xeb, 0xee, 0xd8, 0x01, 0xd7, 0x66, 0x65, 0x65, 0x0d, 0x2a,
- 0x01, 0xe5, 0xda, 0x3b, 0x38, 0x8c, 0x4e, 0x0e, 0xc7, 0x8e, 0x1d, 0x3f, 0x71, 0xe2, 0xcc, 0xd9,
- 0x73, 0x97, 0x2f, 0x5f, 0xbd, 0xff, 0xe0, 0x41, 0x5d, 0xfe, 0x15, 0x7e, 0xeb, 0x09, 0x02, 0xa8,
- 0xcd, 0x06, 0x82, 0x46, 0x6d, 0x62, 0x35, 0xf8, 0x86, 0xad, 0xe4, 0x52, 0x6f, 0xa6, 0x82, 0x36,
- 0x7b, 0x7e, 0xfb, 0x49, 0x41, 0xc7, 0x59, 0x02, 0x1e, 0x9d, 0xe7, 0xde, 0x3a, 0x51, 0xe7, 0x9f,
- 0xe2, 0x03, 0xf6, 0xed, 0xf6, 0x82, 0x76, 0x3b, 0x41, 0x87, 0x83, 0xa0, 0xf3, 0xb8, 0xa0, 0xeb,
- 0x14, 0xbf, 0xfb, 0x3c, 0xbf, 0xdb, 0x8d, 0x18, 0xe5, 0xd5, 0x7d, 0x91, 0xdf, 0xed, 0x2e, 0x40,
- 0x1d, 0xe9, 0x3c, 0xcd, 0x6f, 0x77, 0x20, 0xa7, 0x34, 0x5a, 0xf3, 0x89, 0x33, 0x7f, 0xe2, 0x77,
- 0x9e, 0xe7, 0x77, 0xb9, 0x93, 0xe7, 0x5c, 0x7a, 0x91, 0xba, 0xdc, 0xf9, 0x5d, 0xce, 0x82, 0x0e,
- 0x27, 0x01, 0xce, 0x69, 0x39, 0xc0, 0x6f, 0xda, 0x25, 0x20, 0xd7, 0x4e, 0x14, 0xb4, 0x98, 0xf0,
- 0xdb, 0x8e, 0xf2, 0xda, 0x4e, 0x72, 0x1a, 0x5d, 0x06, 0x18, 0xee, 0xcc, 0x92, 0x8b, 0x5d, 0xb9,
- 0x97, 0x5a, 0x93, 0x2e, 0xd6, 0x45, 0xb8, 0xa5, 0x78, 0x9d, 0x34, 0xdc, 0x6f, 0x68, 0x60, 0xb0,
- 0xff, 0x80, 0x91, 0x91, 0x99, 0x99, 0x99, 0x95, 0x95, 0x15, 0x28, 0x96, 0xca, 0x0a, 0x22, 0x03,
- 0x1c, 0x1d, 0xe1, 0x80, 0x5c, 0x5d, 0x2f, 0xdc, 0xbe, 0x73, 0x17, 0x30, 0xce, 0xce, 0xce, 0x81,
- 0x24, 0x40, 0x45, 0x06, 0x19, 0xc2, 0xf5, 0x67, 0xe7, 0xe4, 0x14, 0x97, 0x94, 0xc6, 0xc5, 0x27,
- 0x10, 0x78, 0x26, 0x25, 0x41, 0x5d, 0x5d, 0xfd, 0xda, 0xb5, 0x6b, 0x3f, 0xee, 0x8a, 0x58, 0x6f,
- 0x30, 0x3c, 0x06, 0x7c, 0x25, 0x04, 0xa7, 0x18, 0xae, 0x5c, 0xee, 0xd0, 0xcd, 0x9b, 0x37, 0x41,
- 0xf2, 0x6f, 0x7e, 0x06, 0xa8, 0x85, 0xcb, 0x97, 0xdc, 0xf9, 0x43, 0x9d, 0xc4, 0x96, 0xf7, 0x9c,
- 0x22, 0xb2, 0x3d, 0xb6, 0x4a, 0xc4, 0xef, 0x68, 0x6f, 0xab, 0xd7, 0xdf, 0xab, 0xf7, 0xae, 0x1b,
- 0x65, 0x4a, 0xdb, 0xac, 0x59, 0xb3, 0xd2, 0xd3, 0xd3, 0x73, 0x73, 0xf3, 0xee, 0x3f, 0xf0, 0x3f,
- 0x7e, 0xfc, 0x04, 0x24, 0xa8, 0x8a, 0x8a, 0x0a, 0xd1, 0xde, 0x45, 0x46, 0x61, 0xef, 0x04, 0x5a,
- 0x6a, 0x24, 0x0c, 0x5c, 0x09, 0x40, 0x8b, 0xdb, 0x42, 0x57, 0x2f, 0x56, 0x57, 0xd7, 0x58, 0xb6,
- 0x6c, 0xc5, 0x8a, 0x95, 0x23, 0xfd, 0x4d, 0x2f, 0xd3, 0xaa, 0x55, 0xab, 0xa1, 0x43, 0x36, 0x6f,
- 0xde, 0xb2, 0x6b, 0xd7, 0x6e, 0x0b, 0x8b, 0xc3, 0x2e, 0xe7, 0x5d, 0x8a, 0xc2, 0x4c, 0xfb, 0x8b,
- 0x36, 0x71, 0xca, 0x96, 0x71, 0xcb, 0xd4, 0x38, 0x65, 0xca, 0x9c, 0x32, 0x15, 0x4e, 0xb9, 0x06,
- 0xb7, 0x62, 0x1d, 0xb7, 0x72, 0x1b, 0xa7, 0x4a, 0x67, 0xb0, 0x6a, 0xc7, 0x60, 0xe5, 0xce, 0xc1,
- 0x2a, 0x32, 0x31, 0x76, 0x72, 0xab, 0x77, 0x10, 0xa9, 0x46, 0x97, 0x5b, 0xab, 0x3b, 0x54, 0xbb,
- 0x1d, 0x89, 0x57, 0xa7, 0xc3, 0xab, 0xd7, 0xe1, 0x37, 0x68, 0x8f, 0x4a, 0x5a, 0xfc, 0x06, 0x4d,
- 0x72, 0x27, 0xc4, 0x8d, 0xc4, 0xea, 0xd0, 0xf5, 0xeb, 0xf9, 0x0d, 0x1b, 0xf9, 0x8d, 0xdb, 0xf8,
- 0x4d, 0xda, 0xc4, 0x42, 0x9d, 0xcd, 0xbb, 0xf8, 0xcd, 0x7b, 0xc8, 0x6d, 0x13, 0x77, 0xf3, 0xf0,
- 0xb1, 0x91, 0xdc, 0x72, 0x11, 0xa9, 0x51, 0x93, 0xf8, 0x48, 0x1c, 0xd2, 0xe7, 0x37, 0xef, 0x27,
- 0xd3, 0x3e, 0x9c, 0x26, 0x68, 0xde, 0xc9, 0x6f, 0xda, 0xce, 0x6b, 0xdc, 0xc2, 0x27, 0x76, 0x5c,
- 0xd2, 0xe0, 0xd7, 0xa8, 0xf1, 0xab, 0x55, 0xf8, 0x35, 0x4b, 0xf8, 0xb5, 0xab, 0x86, 0x6a, 0x37,
- 0x0e, 0x32, 0xb4, 0xfb, 0x4b, 0x76, 0x33, 0xb3, 0xf5, 0x3b, 0x92, 0xf6, 0x37, 0x47, 0x1a, 0x56,
- 0x07, 0x1a, 0x16, 0xdf, 0xd9, 0x1f, 0x7e, 0x72, 0xe7, 0xd2, 0x25, 0x6a, 0xca, 0x8b, 0x16, 0xa9,
- 0xa8, 0xaa, 0xaa, 0x2f, 0x59, 0x42, 0x66, 0xc5, 0x0a, 0xea, 0xdd, 0x57, 0xaf, 0xfe, 0x61, 0xfd,
- 0xfa, 0x0d, 0xda, 0xda, 0x3a, 0x87, 0x4c, 0x4c, 0xce, 0x39, 0x3b, 0x3f, 0x7c, 0xf8, 0x28, 0x2b,
- 0x3b, 0xbb, 0xad, 0xbd, 0x63, 0xdf, 0x3e, 0x03, 0x84, 0x12, 0xe6, 0xe6, 0xe6, 0x60, 0x54, 0xb0,
- 0x6e, 0x6c, 0x6c, 0x5c, 0x54, 0x54, 0x34, 0xc2, 0x2b, 0x46, 0x75, 0x35, 0x58, 0xe5, 0x5d, 0x77,
- 0xf2, 0xfd, 0x10, 0x03, 0x00, 0x6c, 0x5f, 0x8c, 0xcb, 0x25, 0x26, 0x19, 0xf5, 0xf4, 0xf4, 0x22,
- 0xf6, 0xf9, 0xd5, 0x7e, 0x1c, 0xca, 0xf0, 0x9c, 0xc1, 0x4f, 0x02, 0xd8, 0xec, 0xce, 0x61, 0x41,
- 0xb7, 0x80, 0xd7, 0xc9, 0xec, 0x69, 0x8a, 0x8a, 0x0c, 0x5d, 0xbc, 0x58, 0xed, 0xbd, 0x27, 0xf0,
- 0x4a, 0x18, 0x34, 0xf0, 0xf3, 0xe7, 0x89, 0xf0, 0x3b, 0x0f, 0x08, 0xd0, 0x1e, 0xd7, 0xd1, 0xd1,
- 0x51, 0x52, 0x52, 0x9a, 0x3c, 0x79, 0xca, 0xa7, 0x9f, 0xbe, 0x33, 0x68, 0x71, 0x32, 0xd4, 0x2c,
- 0xde, 0xeb, 0x5f, 0xff, 0xfa, 0xe2, 0x9b, 0x6f, 0xbf, 0xc5, 0x4d, 0xa6, 0x4d, 0x9b, 0x3e, 0xb2,
- 0xe1, 0xfc, 0x4c, 0x89, 0x34, 0x7b, 0xf6, 0x6c, 0xb0, 0x31, 0x7e, 0x0b, 0x80, 0xde, 0xb9, 0x73,
- 0x97, 0xbd, 0x8d, 0x75, 0xac, 0x87, 0x56, 0x85, 0xdf, 0xf2, 0xa6, 0x27, 0x2a, 0xad, 0xa1, 0xca,
- 0xed, 0x11, 0x0b, 0x3b, 0xa2, 0x54, 0x3b, 0x63, 0x97, 0x74, 0xc6, 0x6b, 0x74, 0x25, 0xae, 0xe8,
- 0x4a, 0x5a, 0xd9, 0x9d, 0xbc, 0xb2, 0x27, 0x65, 0x65, 0x4f, 0xea, 0xca, 0xde, 0xb4, 0x95, 0xcc,
- 0x8c, 0x15, 0xac, 0xac, 0x15, 0x7d, 0xd9, 0xcb, 0xfb, 0x73, 0x97, 0xf5, 0xe7, 0x2d, 0x1b, 0xc8,
- 0x5f, 0x3a, 0x50, 0xf8, 0x3d, 0xbb, 0x78, 0x09, 0xa7, 0x54, 0x9d, 0x5b, 0xbe, 0x98, 0x5b, 0xa1,
- 0x36, 0x54, 0xa9, 0xc2, 0x63, 0x2c, 0xe2, 0x31, 0x94, 0x79, 0x0c, 0x25, 0x72, 0xc9, 0x47, 0x05,
- 0x1e, 0x83, 0x46, 0xfe, 0xa1, 0xc4, 0xaf, 0x5e, 0xc8, 0xaf, 0x51, 0xe6, 0xd7, 0xa8, 0xf2, 0x6b,
- 0xd5, 0xf8, 0x75, 0x6a, 0x3c, 0xa4, 0x5a, 0xfc, 0xab, 0xc2, 0xab, 0x55, 0x46, 0xe2, 0xd7, 0xaa,
- 0xf2, 0xea, 0xd4, 0x79, 0x75, 0x1a, 0xfc, 0xba, 0x65, 0xc4, 0x56, 0xa1, 0x75, 0x4b, 0xc9, 0xa4,
- 0x8e, 0xef, 0x89, 0x6d, 0x6d, 0xab, 0x15, 0x79, 0x0c, 0x79, 0x3e, 0x31, 0xb4, 0x78, 0x1e, 0xaf,
- 0x72, 0x2e, 0xaf, 0x6a, 0xfe, 0x50, 0xb9, 0x02, 0xa7, 0x44, 0x79, 0xa0, 0x60, 0x31, 0x33, 0x6b,
- 0x59, 0x57, 0xe2, 0xea, 0x96, 0xb0, 0x1f, 0xea, 0x1e, 0xad, 0x2d, 0xbf, 0xbd, 0x3e, 0xd7, 0x75,
- 0x5d, 0xa0, 0xd9, 0xf2, 0x79, 0x33, 0xa6, 0x4c, 0x80, 0x17, 0x9c, 0x34, 0x09, 0x24, 0x30, 0x92,
- 0x15, 0xc4, 0x06, 0x70, 0x70, 0xfd, 0xf2, 0x0a, 0x0a, 0xcb, 0x96, 0x2d, 0xdb, 0xb3, 0x47, 0xef,
- 0xe4, 0xc9, 0x53, 0x8f, 0x02, 0x02, 0xa0, 0x63, 0x1b, 0x1a, 0x1b, 0x71, 0x08, 0x67, 0x42, 0x28,
- 0x42, 0x21, 0xa0, 0x44, 0xc0, 0xb1, 0x10, 0x0c, 0x79, 0xf9, 0x05, 0x0d, 0x8d, 0x4d, 0xa0, 0xe6,
- 0x0f, 0x91, 0x04, 0xef, 0x6a, 0x28, 0xc4, 0x0d, 0x1b, 0x36, 0x24, 0xa7, 0xa4, 0xe4, 0xe4, 0xe4,
- 0x84, 0x85, 0x47, 0x48, 0xef, 0xe9, 0xf0, 0x66, 0x83, 0xfb, 0xbe, 0x70, 0xc1, 0x25, 0x3e, 0x2e,
- 0x3a, 0xe4, 0x69, 0x90, 0xa9, 0xc9, 0xa1, 0x29, 0x53, 0x3e, 0x68, 0xb9, 0x6f, 0x09, 0x43, 0xa5,
- 0x5e, 0xb3, 0x76, 0x6d, 0xc2, 0xf3, 0x44, 0xe8, 0x7c, 0x6f, 0x1f, 0x1f, 0x44, 0x07, 0xa0, 0x3e,
- 0x1a, 0x8d, 0x86, 0x7c, 0x16, 0xef, 0xe0, 0xfc, 0x4e, 0x4c, 0x0b, 0x0d, 0x0c, 0xdc, 0xa2, 0x42,
- 0xe1, 0xce, 0xff, 0x24, 0xed, 0xd3, 0xd7, 0x18, 0x8a, 0x00, 0xca, 0x0a, 0xc5, 0xb4, 0x70, 0xe1,
- 0xc2, 0xf5, 0xeb, 0xd7, 0x1f, 0x32, 0xdc, 0x77, 0xc3, 0x46, 0x27, 0xec, 0xd4, 0xfa, 0x0c, 0x67,
- 0xb5, 0x02, 0x77, 0xa5, 0xb2, 0xab, 0x4a, 0x95, 0xb7, 0x94, 0x19, 0xf7, 0x16, 0xd5, 0xf8, 0xaa,
- 0xd4, 0x3e, 0x50, 0xa9, 0xf3, 0x57, 0x69, 0x08, 0x50, 0x69, 0x7c, 0xbc, 0xa8, 0xe9, 0xc9, 0xa2,
- 0x96, 0x10, 0xe5, 0xd6, 0x67, 0xca, 0x6d, 0xe1, 0xca, 0xed, 0x51, 0x0b, 0x3b, 0x62, 0x94, 0xba,
- 0xe2, 0x14, 0xbb, 0x9f, 0xd3, 0x7b, 0x92, 0x69, 0xcc, 0x34, 0x79, 0x56, 0x86, 0x5c, 0x5f, 0xb6,
- 0x6c, 0x7f, 0xce, 0x02, 0x76, 0xfe, 0xfc, 0xc1, 0xc2, 0x79, 0x9c, 0xe2, 0x39, 0xdc, 0xd2, 0x59,
- 0x43, 0xe5, 0x33, 0x78, 0x15, 0x33, 0xf8, 0x95, 0x54, 0x9a, 0xf9, 0x22, 0x55, 0x21, 0xcd, 0x42,
- 0x22, 0x37, 0xf9, 0x9d, 0x45, 0xee, 0xa5, 0x3e, 0x8b, 0x57, 0x3d, 0x9b, 0x57, 0x3d, 0x97, 0x5f,
- 0x3d, 0x8f, 0x5f, 0xfd, 0x1d, 0xf1, 0x2f, 0x63, 0x2e, 0x99, 0x66, 0x13, 0x27, 0x57, 0x52, 0x1b,
- 0x85, 0x4f, 0xe7, 0x55, 0x4e, 0xe5, 0x55, 0x4c, 0x1e, 0x2a, 0x9f, 0xc2, 0x29, 0x99, 0xce, 0x2e,
- 0x98, 0xd3, 0x9f, 0x3d, 0x9f, 0x95, 0x2a, 0xd7, 0x95, 0x40, 0xc7, 0xf3, 0x34, 0x04, 0x2e, 0x62,
- 0xdc, 0x53, 0x29, 0xbe, 0xac, 0x96, 0x71, 0x72, 0xb1, 0x9f, 0x81, 0xe2, 0x37, 0x5f, 0x7c, 0xfa,
- 0x7f, 0x49, 0xfb, 0xfb, 0xdf, 0xff, 0x41, 0xe5, 0x03, 0xb8, 0x4b, 0xfc, 0xd6, 0x10, 0xfc, 0x7b,
- 0xf5, 0xf5, 0x11, 0x7e, 0x86, 0x86, 0x86, 0x41, 0xb5, 0x3e, 0xf0, 0xf7, 0x27, 0x17, 0xaf, 0x50,
- 0x48, 0x4a, 0x4a, 0xaa, 0xad, 0xab, 0xcf, 0xce, 0xc9, 0x4d, 0x4a, 0x4e, 0x41, 0xb4, 0x55, 0x59,
- 0x55, 0x55, 0x58, 0x54, 0x04, 0x1f, 0xfd, 0x11, 0x0b, 0xfd, 0x6d, 0x0c, 0x0f, 0x03, 0x56, 0xc1,
- 0xf3, 0x8c, 0x1f, 0x3f, 0xfe, 0x3d, 0xd4, 0x08, 0xd5, 0x76, 0xf4, 0x86, 0xc8, 0xee, 0x43, 0x0c,
- 0xb7, 0xdd, 0xb5, 0x6b, 0x57, 0x4a, 0x6a, 0x2a, 0xd2, 0xcd, 0x5b, 0xb7, 0xcc, 0x2d, 0x2c, 0xe0,
- 0xb3, 0xc0, 0xbd, 0x13, 0x26, 0x4c, 0x78, 0xbf, 0x71, 0x32, 0x38, 0x1f, 0x7c, 0xfb, 0xbf, 0x49,
- 0xfb, 0x3f, 0xaf, 0x37, 0x54, 0x07, 0x94, 0x26, 0xb4, 0x0d, 0x78, 0x08, 0x7c, 0xbb, 0x74, 0xa9,
- 0x86, 0xb6, 0x96, 0xd6, 0x91, 0x03, 0x7a, 0xae, 0x47, 0x76, 0xf9, 0x38, 0x6c, 0x8f, 0x3a, 0xb6,
- 0x2a, 0xc5, 0x61, 0x61, 0xba, 0x93, 0x52, 0xf6, 0x19, 0xa5, 0x3c, 0x17, 0xa5, 0x42, 0x77, 0xc5,
- 0x92, 0xcb, 0x8a, 0x65, 0x57, 0xe9, 0xe5, 0x37, 0xe8, 0x95, 0xb7, 0x69, 0x55, 0x77, 0xe9, 0xd5,
- 0xde, 0xb4, 0x1a, 0x3f, 0x5a, 0x9d, 0xbf, 0x42, 0xc3, 0x23, 0xf9, 0xa6, 0xc7, 0xf2, 0xcd, 0x4f,
- 0xe5, 0x5b, 0x43, 0xe5, 0xda, 0xc2, 0x65, 0x3b, 0xa2, 0x65, 0xba, 0xe2, 0xe6, 0x77, 0x3f, 0xff,
- 0xae, 0x37, 0x79, 0x2e, 0x2b, 0x7d, 0x76, 0x7f, 0xe6, 0x4c, 0x76, 0xee, 0xf4, 0xc1, 0xc2, 0xa9,
- 0x9c, 0x92, 0x29, 0x43, 0xa5, 0x93, 0x86, 0xca, 0x27, 0xf2, 0x5e, 0x49, 0x13, 0xc8, 0xbd, 0xfc,
- 0x26, 0x8c, 0x24, 0x72, 0x5f, 0xbf, 0x8a, 0x49, 0xa3, 0x12, 0xf9, 0x8d, 0xf8, 0x64, 0x72, 0x9f,
- 0x94, 0xa1, 0xb2, 0x09, 0x9c, 0xe2, 0x49, 0x03, 0xb9, 0xd3, 0xfa, 0x32, 0x66, 0xf6, 0x26, 0xcd,
- 0xe9, 0x8a, 0x9d, 0xdf, 0x1a, 0x26, 0xd7, 0xf8, 0x58, 0xa1, 0xd6, 0x57, 0xa1, 0xdc, 0x93, 0x5e,
- 0xe0, 0xaa, 0x98, 0xea, 0xa8, 0xe4, 0xb5, 0x5b, 0xf6, 0x9f, 0xff, 0x43, 0x38, 0x29, 0x2a, 0x2b,
- 0xa8, 0xf7, 0xfd, 0x84, 0x6c, 0xcf, 0x87, 0x03, 0x5a, 0xb0, 0x60, 0x01, 0xf4, 0xea, 0x11, 0x4b,
- 0xcb, 0xdb, 0xb7, 0xef, 0xa4, 0xa4, 0xa6, 0x01, 0xa2, 0xdb, 0xb6, 0x6d, 0x03, 0xb3, 0xfd, 0xb0,
- 0x66, 0x4d, 0x53, 0x53, 0x73, 0x75, 0x4d, 0x2d, 0xa8, 0x15, 0x1c, 0x52, 0x50, 0x58, 0x04, 0x85,
- 0xf0, 0xf8, 0xf1, 0xe3, 0xdf, 0x53, 0x12, 0xfc, 0x29, 0x0c, 0x82, 0xd9, 0xc4, 0xc4, 0x04, 0xf5,
- 0x3a, 0x2e, 0x3e, 0xfe, 0xd2, 0xa5, 0xcb, 0xd0, 0x57, 0xd0, 0xf9, 0x32, 0xa3, 0x36, 0x53, 0x78,
- 0x27, 0xc4, 0x4a, 0xa0, 0xf7, 0x0d, 0x86, 0xd2, 0x44, 0x39, 0x82, 0x8d, 0xbf, 0xfc, 0xf2, 0x4b,
- 0xb8, 0x4c, 0x70, 0x3b, 0xa2, 0x36, 0x94, 0x9d, 0xa1, 0xbe, 0x9e, 0xbd, 0xa9, 0x81, 0xab, 0xed,
- 0x81, 0xbb, 0x8e, 0xfa, 0xc1, 0x76, 0x1b, 0xa3, 0xad, 0xd4, 0x12, 0xac, 0xe8, 0xc9, 0xf6, 0xf4,
- 0xf4, 0x13, 0xf4, 0xac, 0x53, 0xb4, 0x9c, 0x73, 0xb4, 0x7c, 0x17, 0x5a, 0x91, 0xbb, 0x42, 0xc9,
- 0x25, 0x85, 0xb2, 0xab, 0x0a, 0xe5, 0x37, 0xe4, 0x2b, 0x6f, 0xc9, 0x31, 0xee, 0xca, 0xd5, 0xf8,
- 0xc8, 0xd5, 0xf9, 0xc9, 0x36, 0xf8, 0xcb, 0x36, 0x06, 0xca, 0x36, 0x07, 0xcb, 0xb4, 0x86, 0x2e,
- 0x68, 0x8b, 0x9c, 0xdf, 0x19, 0x3b, 0xaf, 0x27, 0x71, 0x0e, 0x2b, 0x75, 0x66, 0x7f, 0xe6, 0xf4,
- 0x81, 0xdc, 0xa9, 0x83, 0x85, 0x93, 0xb9, 0x25, 0x93, 0x86, 0xca, 0xbe, 0x7d, 0xb9, 0xb1, 0xd4,
- 0x6b, 0xd3, 0xb7, 0xaf, 0xa6, 0x17, 0xdf, 0x0f, 0x95, 0x7e, 0xcb, 0x29, 0x02, 0x5c, 0xa7, 0xb2,
- 0xd2, 0xa7, 0xf7, 0x24, 0xce, 0xea, 0x8c, 0xfe, 0xae, 0xed, 0x99, 0x4c, 0x63, 0xa0, 0x5c, 0xad,
- 0x9f, 0x6c, 0xd5, 0x1d, 0xb9, 0x92, 0xcb, 0x0a, 0xb9, 0xe7, 0x68, 0x49, 0x76, 0xf4, 0x5b, 0xdb,
- 0xe7, 0xff, 0xd7, 0xa8, 0x9a, 0x4e, 0x4d, 0xdb, 0x44, 0x0d, 0xc5, 0x9b, 0x82, 0xbb, 0xbe, 0xff,
- 0xfe, 0xfb, 0x7d, 0x06, 0x06, 0x17, 0xdc, 0xdc, 0x11, 0x8f, 0x57, 0x54, 0x56, 0x45, 0x44, 0x46,
- 0xce, 0x99, 0x33, 0x07, 0x0c, 0x7c, 0xe4, 0x88, 0x65, 0x57, 0x77, 0x37, 0x10, 0x5b, 0x54, 0x5c,
- 0x02, 0xb8, 0x32, 0xaa, 0x6b, 0x80, 0x58, 0xa7, 0x9f, 0x7e, 0xfa, 0xad, 0x37, 0x44, 0xfe, 0x33,
- 0x1a, 0x38, 0xdc, 0xf1, 0xf8, 0x71, 0x72, 0x3b, 0xcb, 0x08, 0x77, 0x77, 0x0f, 0x23, 0x23, 0x63,
- 0xc4, 0x08, 0x10, 0x24, 0x54, 0x5b, 0xf1, 0x6f, 0xb7, 0x3b, 0x98, 0x58, 0x48, 0xa0, 0xbc, 0x50,
- 0x41, 0xa6, 0x4f, 0x9f, 0x2e, 0x23, 0x23, 0x83, 0x00, 0x10, 0xf1, 0x89, 0xa6, 0xa6, 0xe6, 0xbe,
- 0xbd, 0x7a, 0x16, 0x87, 0x0e, 0x38, 0x58, 0x99, 0xb9, 0x38, 0x98, 0x7b, 0xd9, 0xeb, 0x05, 0x5b,
- 0xad, 0x89, 0x30, 0x57, 0x8d, 0x39, 0xa2, 0x94, 0x60, 0xa3, 0x94, 0x64, 0xa7, 0x98, 0xee, 0x48,
- 0xcf, 0xfa, 0x89, 0x96, 0x7b, 0x86, 0x96, 0xef, 0xac, 0x50, 0x70, 0x41, 0xa1, 0xc8, 0x43, 0xa1,
- 0xf4, 0x8a, 0x7c, 0xc5, 0x75, 0xf9, 0xca, 0x9b, 0x72, 0x0c, 0x2f, 0xd9, 0x5a, 0x1f, 0xd9, 0xba,
- 0x07, 0x2f, 0xd0, 0xdb, 0x16, 0x36, 0x1f, 0xd0, 0xea, 0x4e, 0x98, 0xcd, 0x24, 0xa1, 0xcb, 0xce,
- 0x9b, 0xca, 0x29, 0x9c, 0x34, 0x54, 0x32, 0x81, 0x57, 0xf6, 0xab, 0xb8, 0x7d, 0x99, 0x80, 0x73,
- 0x6e, 0xc9, 0x04, 0x02, 0xae, 0x39, 0xd3, 0xfa, 0xd2, 0x66, 0xf4, 0x26, 0xcc, 0xe9, 0x88, 0xfa,
- 0xae, 0xe5, 0xa9, 0x4c, 0xc3, 0x23, 0xfc, 0x96, 0x4c, 0xe5, 0x6d, 0x39, 0xfc, 0x7a, 0xa1, 0xab,
- 0x42, 0xd6, 0x4f, 0xf4, 0x04, 0x2b, 0x9a, 0xf3, 0xc6, 0xd9, 0xa3, 0x5f, 0x93, 0xea, 0x64, 0x19,
- 0x37, 0x6e, 0x1c, 0xa5, 0x07, 0x10, 0x72, 0x9e, 0x3e, 0x7d, 0x26, 0x28, 0xe8, 0x49, 0x7e, 0x7e,
- 0x41, 0x53, 0x73, 0x8b, 0x91, 0xf1, 0x41, 0x6a, 0xb3, 0xe3, 0xfb, 0x0f, 0x1e, 0x00, 0xb1, 0x75,
- 0xf5, 0xf5, 0x54, 0x2f, 0x58, 0x4b, 0x4b, 0x6b, 0x61, 0x61, 0xa1, 0xf4, 0x50, 0xc6, 0xbf, 0x8c,
- 0x32, 0xe4, 0x27, 0x54, 0x41, 0x59, 0x59, 0x39, 0x94, 0x95, 0x8b, 0xeb, 0x05, 0x03, 0x83, 0xfd,
- 0x88, 0x0e, 0x40, 0x08, 0x94, 0xe6, 0xff, 0x4d, 0x41, 0x8b, 0x9b, 0x83, 0x82, 0xa8, 0x55, 0xa1,
- 0xf0, 0x18, 0x10, 0x24, 0xa0, 0x5c, 0xb8, 0x4e, 0x48, 0x5c, 0xd0, 0xd1, 0x0f, 0x3f, 0xfc, 0xb0,
- 0x75, 0xeb, 0xd6, 0x1d, 0x3b, 0x76, 0x1a, 0x1a, 0x1e, 0x38, 0x6c, 0x61, 0x71, 0xd2, 0xc6, 0xe2,
- 0xaa, 0xad, 0x81, 0xaf, 0xe5, 0xd6, 0xc7, 0xe6, 0xcb, 0x9e, 0x1d, 0x5e, 0x12, 0x65, 0xb5, 0x38,
- 0xde, 0x46, 0x39, 0xe9, 0xa8, 0x62, 0x9a, 0x03, 0x2d, 0xc3, 0x89, 0x96, 0x7d, 0x8a, 0x60, 0xb9,
- 0xfc, 0x0b, 0xb4, 0xa2, 0x8b, 0x0a, 0xa5, 0x57, 0xe5, 0x2b, 0x3d, 0x49, 0xf4, 0xfa, 0xca, 0xd6,
- 0x3f, 0x94, 0x6d, 0x0a, 0x22, 0xa0, 0xdb, 0x11, 0x3d, 0xaf, 0x27, 0x61, 0x0e, 0x2b, 0x65, 0x66,
- 0x1f, 0x58, 0x37, 0x67, 0xda, 0x60, 0xc1, 0x64, 0x6e, 0xd1, 0x24, 0x6e, 0xc9, 0x44, 0x6e, 0xe9,
- 0x04, 0xf0, 0x27, 0x91, 0xca, 0x5e, 0x4d, 0x25, 0x13, 0x70, 0x88, 0x5b, 0x3c, 0x11, 0x58, 0x65,
- 0xe7, 0x4d, 0xe9, 0xcb, 0x9e, 0x0e, 0xd8, 0xf7, 0xc4, 0xcf, 0x6d, 0x8f, 0x9c, 0xdf, 0xfc, 0x44,
- 0x06, 0xb7, 0xad, 0xf1, 0x96, 0xad, 0xb8, 0x29, 0x07, 0xc2, 0x07, 0xf3, 0xc3, 0x05, 0x24, 0xdb,
- 0xd1, 0x63, 0xcc, 0x68, 0xdb, 0xe4, 0xbf, 0x16, 0x63, 0x15, 0x4e, 0x04, 0x95, 0x11, 0x2c, 0xaa,
- 0xac, 0xac, 0xbc, 0x69, 0xd3, 0x66, 0xe8, 0xae, 0xcb, 0x57, 0xae, 0x44, 0x46, 0x46, 0x95, 0x95,
- 0x57, 0xb4, 0xb7, 0x77, 0xf8, 0xfb, 0x3f, 0xa4, 0x9c, 0xfe, 0xb4, 0x69, 0xd3, 0x18, 0x8c, 0x6a,
- 0x16, 0xab, 0xaf, 0xb3, 0xab, 0xbb, 0xa3, 0xb3, 0xb3, 0xbb, 0xa7, 0xa7, 0xbf, 0x7f, 0x20, 0x2c,
- 0x2c, 0x4c, 0x7a, 0xc5, 0xef, 0xbf, 0x4c, 0x6c, 0x60, 0xd4, 0xc0, 0xc7, 0x8f, 0x8b, 0x8b, 0x4b,
- 0x42, 0x9e, 0x85, 0x3a, 0x3b, 0x9f, 0x47, 0x68, 0x00, 0x42, 0x00, 0x78, 0x00, 0x5a, 0xc0, 0xe9,
- 0x63, 0xad, 0xd8, 0xf9, 0x06, 0xdc, 0x8a, 0x03, 0x37, 0x70, 0xce, 0xb8, 0x71, 0x5f, 0x7e, 0xf3,
- 0xcd, 0xb7, 0x08, 0x9f, 0xc1, 0x4b, 0x40, 0x2f, 0x9d, 0x4e, 0x57, 0x53, 0x53, 0x5b, 0xb1, 0x62,
- 0xe5, 0xc6, 0x8d, 0x9b, 0x74, 0x74, 0x74, 0xf6, 0xee, 0xdd, 0x6b, 0x6a, 0x62, 0xe2, 0x68, 0x69,
- 0xea, 0x66, 0x6d, 0x70, 0xcb, 0x52, 0xc7, 0xf7, 0xf0, 0xc6, 0x40, 0xab, 0x35, 0xe1, 0xd6, 0xcb,
- 0x62, 0xad, 0x55, 0x13, 0x6d, 0x14, 0x01, 0x9b, 0xb4, 0xe3, 0x40, 0x2f, 0x2d, 0xcf, 0x99, 0x56,
- 0xe4, 0xa6, 0x50, 0x7a, 0x59, 0xbe, 0xc2, 0x53, 0x9e, 0x71, 0x57, 0x16, 0xbe, 0xbb, 0x21, 0x40,
- 0xb6, 0x25, 0x58, 0xa6, 0x3d, 0x7c, 0x7e, 0x67, 0xcc, 0xbc, 0xee, 0x84, 0x39, 0xcc, 0x94, 0x99,
- 0xac, 0xf4, 0x19, 0x7d, 0x59, 0x04, 0x7a, 0x07, 0xf2, 0xa6, 0x02, 0x93, 0x83, 0xf9, 0x53, 0xd8,
- 0xa3, 0x53, 0xde, 0x14, 0xe2, 0xfb, 0xdc, 0x69, 0xfd, 0xd9, 0xd3, 0xfa, 0xd2, 0x67, 0x30, 0x53,
- 0x66, 0x75, 0xc5, 0xcd, 0xc5, 0xe5, 0x4d, 0x80, 0xeb, 0x03, 0xd9, 0xea, 0x7b, 0xb2, 0xb8, 0x73,
- 0x31, 0xe0, 0x7a, 0x9e, 0x06, 0x76, 0xc5, 0xef, 0xc6, 0x1d, 0xa6, 0xdd, 0xd6, 0x9d, 0x3f, 0xee,
- 0xef, 0xff, 0x8d, 0x3a, 0x08, 0xa0, 0xca, 0xc9, 0xc9, 0x81, 0x24, 0x8d, 0x8c, 0x8c, 0x8e, 0x1f,
- 0x3f, 0xee, 0xe6, 0xe6, 0x7e, 0xcf, 0xdb, 0x07, 0x5e, 0x2c, 0x3b, 0x27, 0xa7, 0xbe, 0xa1, 0xb1,
- 0xbb, 0xbb, 0x27, 0x39, 0x39, 0x45, 0x3c, 0x3b, 0x5e, 0x5d, 0x5d, 0x9d, 0x3d, 0xc8, 0xe9, 0x65,
- 0x32, 0x01, 0x57, 0xa4, 0x9e, 0x9e, 0x5e, 0x40, 0x57, 0x7a, 0xd9, 0xba, 0xbf, 0x4c, 0xc2, 0x64,
- 0x65, 0x65, 0x83, 0x83, 0x83, 0xf3, 0x0b, 0x0a, 0x03, 0x03, 0x1f, 0xff, 0x74, 0xf2, 0xe4, 0x8e,
- 0x1d, 0x3b, 0xe0, 0xa3, 0xe1, 0xac, 0xff, 0x45, 0x82, 0xf6, 0x77, 0xd8, 0x3c, 0x54, 0x4c, 0xb9,
- 0x80, 0x2e, 0x7e, 0x11, 0x04, 0x85, 0xe8, 0x0c, 0xc4, 0x0b, 0xaa, 0x99, 0x34, 0x69, 0x12, 0xaa,
- 0x0f, 0xb4, 0x0a, 0x62, 0xd8, 0x45, 0x8b, 0x16, 0x69, 0x68, 0x68, 0x40, 0x6f, 0xff, 0xf8, 0xe3,
- 0x8f, 0xbb, 0x77, 0xef, 0x01, 0x24, 0x6c, 0xcc, 0x0f, 0x9d, 0xb5, 0x34, 0xbc, 0x6c, 0xb9, 0xeb,
- 0x8e, 0xb5, 0xf6, 0x43, 0xdb, 0xad, 0xa1, 0xd6, 0x2b, 0xe3, 0x2c, 0x95, 0x13, 0x6d, 0xe8, 0x69,
- 0xc7, 0x80, 0x25, 0x5a, 0xde, 0x39, 0x5a, 0xa1, 0x1b, 0x21, 0x1b, 0xa0, 0x19, 0xaa, 0xbd, 0xe4,
- 0xea, 0xee, 0xcb, 0x36, 0x06, 0xc8, 0x34, 0x53, 0xd0, 0x8d, 0x9e, 0xd7, 0x1d, 0x3f, 0xa7, 0x27,
- 0x71, 0x76, 0x6f, 0xf2, 0x2c, 0x02, 0xc0, 0xa9, 0x33, 0x59, 0x69, 0x33, 0x88, 0x94, 0x8e, 0x7f,
- 0xc9, 0x8f, 0x48, 0x29, 0x33, 0x99, 0x49, 0xb3, 0x7a, 0x9e, 0x23, 0xce, 0x9a, 0x07, 0xa2, 0x06,
- 0x5d, 0x43, 0x72, 0x80, 0xbd, 0xa1, 0xa2, 0x8b, 0x2f, 0x2a, 0xa0, 0x5e, 0x64, 0x3a, 0xd1, 0x93,
- 0x6c, 0xe9, 0xb1, 0xe6, 0xb4, 0xeb, 0xda, 0xdf, 0x2d, 0x99, 0x35, 0x0e, 0x39, 0x86, 0xca, 0xbe,
- 0x7d, 0xbb, 0x2e, 0x02, 0x84, 0x43, 0x87, 0x0e, 0xe1, 0xf1, 0x0e, 0x1f, 0x3e, 0x02, 0x25, 0x70,
- 0xf7, 0xae, 0x57, 0x4c, 0x6c, 0x1c, 0xd8, 0x15, 0x7e, 0xff, 0xe6, 0xcd, 0x9b, 0x10, 0x3f, 0xe2,
- 0x91, 0x8a, 0x96, 0x96, 0x96, 0x03, 0x6c, 0x36, 0x50, 0xda, 0xd6, 0x06, 0xea, 0xed, 0xe8, 0xed,
- 0x65, 0xd6, 0xd4, 0xd6, 0xbd, 0xcd, 0x60, 0xcb, 0xff, 0x70, 0x43, 0xa8, 0x85, 0xf0, 0x27, 0x2a,
- 0x2a, 0x2a, 0x3b, 0x3b, 0xc7, 0xcf, 0xef, 0xbe, 0xc3, 0xb1, 0x63, 0x5a, 0x5a, 0xda, 0x2f, 0x40,
- 0xfb, 0x91, 0x86, 0x7f, 0xbf, 0x25, 0x6e, 0xc5, 0xac, 0x4b, 0xa1, 0x97, 0x7a, 0x36, 0xaa, 0x59,
- 0x0c, 0x92, 0x0f, 0xca, 0x61, 0xea, 0xd4, 0xa9, 0x70, 0xb5, 0x32, 0x32, 0xb2, 0x4a, 0x4a, 0x4a,
- 0x20, 0xa8, 0x55, 0xab, 0x56, 0x6d, 0xde, 0xbc, 0x59, 0x57, 0x57, 0x77, 0xbf, 0xc1, 0x3e, 0x4b,
- 0x13, 0xa3, 0x93, 0x87, 0xf7, 0x7b, 0x58, 0xeb, 0x7b, 0xdb, 0xed, 0x0c, 0xb1, 0x5e, 0x13, 0x7b,
- 0x58, 0xf9, 0xb9, 0x35, 0x3d, 0x15, 0xd0, 0x3d, 0x49, 0x2f, 0x38, 0xaf, 0x50, 0xec, 0x21, 0x5f,
- 0x76, 0x95, 0x88, 0xd7, 0xaa, 0xbd, 0xe5, 0xea, 0x09, 0xad, 0x2b, 0x43, 0x45, 0x6a, 0xed, 0x11,
- 0xf3, 0xdb, 0xa3, 0xbe, 0x83, 0xe2, 0xed, 0x8a, 0x9d, 0x0b, 0x64, 0x8a, 0x13, 0xc2, 0x37, 0x10,
- 0x32, 0x54, 0x6b, 0x5b, 0xf8, 0xfc, 0x96, 0x10, 0xc4, 0x59, 0x32, 0x08, 0xf1, 0x10, 0xeb, 0x95,
- 0x5d, 0x97, 0x47, 0x00, 0x88, 0xba, 0x90, 0x71, 0x9c, 0x86, 0xaa, 0x11, 0x65, 0x4a, 0x73, 0xd7,
- 0x92, 0xd1, 0x5d, 0xa1, 0xb4, 0x61, 0xdd, 0xda, 0x9d, 0x3b, 0x77, 0xea, 0xeb, 0xeb, 0x6b, 0x6b,
- 0xeb, 0xac, 0x5f, 0xbf, 0x01, 0xd5, 0x0a, 0xaa, 0xc6, 0xd8, 0xf8, 0x20, 0xdc, 0x16, 0x5c, 0x58,
- 0x5e, 0x5e, 0x7e, 0x46, 0x66, 0x26, 0xa4, 0xec, 0x94, 0x29, 0xaf, 0x8c, 0x13, 0x08, 0x0c, 0x0c,
- 0xec, 0xeb, 0xef, 0xef, 0xe8, 0xec, 0x6a, 0x05, 0x64, 0x3b, 0x3a, 0x21, 0x0f, 0x22, 0x22, 0x22,
- 0x3f, 0xfd, 0xf4, 0x7d, 0x26, 0x71, 0xfc, 0xa7, 0x19, 0x38, 0x4d, 0x53, 0x4b, 0x2b, 0x31, 0x31,
- 0x29, 0x3d, 0x3d, 0xc3, 0xeb, 0xde, 0x3d, 0xdb, 0xa3, 0x47, 0xf1, 0x51, 0x79, 0xd1, 0x22, 0x20,
- 0x04, 0x87, 0x7e, 0xd3, 0xad, 0xeb, 0xde, 0x06, 0xc0, 0xe2, 0x3d, 0xf5, 0xc4, 0xf4, 0x0b, 0xe7,
- 0x3b, 0x79, 0xf2, 0x64, 0x31, 0xfd, 0xaa, 0xaa, 0xaa, 0xae, 0x58, 0xb1, 0x02, 0xbe, 0x18, 0xe8,
- 0x3d, 0x68, 0xb8, 0xdf, 0xde, 0xdc, 0xc8, 0xd5, 0xf6, 0xa0, 0xb7, 0x83, 0x5e, 0xa8, 0xe5, 0xf2,
- 0x38, 0x0b, 0x7a, 0xd2, 0x51, 0x7a, 0xfa, 0x71, 0x5a, 0xce, 0x19, 0x5a, 0x81, 0x0b, 0x0d, 0xf4,
- 0x08, 0xd4, 0x21, 0xc6, 0xaf, 0xf1, 0x26, 0x58, 0xb7, 0xe1, 0x91, 0x4c, 0x43, 0x20, 0x21, 0x77,
- 0x01, 0x60, 0xa9, 0x84, 0xef, 0x89, 0x38, 0xae, 0xfe, 0xa1, 0x0c, 0x54, 0x31, 0x2e, 0x01, 0xe6,
- 0xa1, 0x37, 0x72, 0xcf, 0xd2, 0xd2, 0x8f, 0x23, 0xd4, 0xa2, 0x47, 0x99, 0x2d, 0x0c, 0xb0, 0xfd,
- 0xf1, 0x94, 0xb5, 0xa9, 0xe1, 0x7e, 0x83, 0xdd, 0xbb, 0x77, 0x6f, 0xd8, 0xb0, 0x11, 0x0a, 0x5c,
- 0x51, 0x51, 0x51, 0x5e, 0x5e, 0x01, 0x59, 0x87, 0x87, 0x01, 0xc7, 0x7a, 0xde, 0xbc, 0x09, 0x19,
- 0x90, 0x97, 0x9f, 0xaf, 0xa5, 0xad, 0x2d, 0xb1, 0x3e, 0x06, 0xde, 0xa5, 0xae, 0xae, 0x9e, 0xc9,
- 0xea, 0x03, 0x62, 0xc1, 0xb0, 0x5d, 0xdd, 0x3d, 0x03, 0xec, 0xc1, 0x43, 0x87, 0x4c, 0x5e, 0x53,
- 0x44, 0x7f, 0x99, 0xa4, 0x81, 0x4e, 0xf7, 0xef, 0xdf, 0x8f, 0x48, 0x36, 0x39, 0x25, 0xf5, 0xf6,
- 0xed, 0x3b, 0x36, 0x36, 0xb6, 0xdb, 0xb6, 0xfd, 0xa8, 0xa8, 0xa8, 0x04, 0x60, 0xfc, 0xe1, 0x3b,
- 0xde, 0xfe, 0xaf, 0x11, 0xe5, 0x40, 0x89, 0x07, 0x00, 0x18, 0xe8, 0x05, 0xfd, 0xe2, 0xc1, 0xf0,
- 0xd8, 0x5f, 0x7d, 0x35, 0x9e, 0x1a, 0x89, 0x37, 0x77, 0xee, 0x5c, 0xa0, 0x77, 0xf1, 0xe2, 0xc5,
- 0x10, 0x8a, 0x9a, 0x9a, 0x9a, 0x06, 0xfa, 0xfa, 0x56, 0x16, 0xa6, 0x17, 0xec, 0x4d, 0xfd, 0xad,
- 0xb7, 0x86, 0x99, 0xab, 0xc5, 0x5a, 0x2e, 0x4c, 0xb2, 0x53, 0xcc, 0x38, 0x41, 0x03, 0xe4, 0x0a,
- 0x2f, 0x90, 0x0d, 0x65, 0xd7, 0xe4, 0x2a, 0x6e, 0xca, 0x33, 0xee, 0x80, 0x78, 0x89, 0x60, 0xaa,
- 0xd6, 0x87, 0x10, 0xbd, 0xe0, 0xd2, 0x5a, 0x3f, 0x99, 0xda, 0xfb, 0xe4, 0x1f, 0x3e, 0x32, 0x35,
- 0xde, 0x32, 0x55, 0x77, 0xe5, 0xca, 0x3d, 0xe5, 0x21, 0x8c, 0x0b, 0x5c, 0x09, 0xd8, 0xa7, 0x1d,
- 0x23, 0xe0, 0x1a, 0x69, 0xb6, 0xc8, 0xc7, 0x76, 0x87, 0x83, 0xad, 0x95, 0x9e, 0x9e, 0x1e, 0x18,
- 0x15, 0x8a, 0x05, 0xbf, 0x8e, 0x0a, 0x3e, 0x69, 0x12, 0xea, 0xd1, 0x4c, 0xc4, 0x8f, 0x20, 0x5b,
- 0x48, 0x82, 0x90, 0x90, 0x67, 0xa5, 0xa5, 0x65, 0xb6, 0xb6, 0xb6, 0xd2, 0x2b, 0xf9, 0x00, 0xdb,
- 0x88, 0xb3, 0xfa, 0x07, 0xd8, 0xbd, 0x4c, 0x56, 0x4f, 0x2f, 0xb3, 0xaf, 0xaf, 0x9f, 0xd5, 0xd7,
- 0xf7, 0x21, 0xe3, 0x46, 0xfe, 0x03, 0x0d, 0x00, 0xb0, 0xb3, 0xb3, 0xaf, 0xac, 0x62, 0x24, 0x25,
- 0x25, 0xdf, 0xba, 0x75, 0xdb, 0xca, 0xca, 0x9a, 0xea, 0x0e, 0xfb, 0xf6, 0xdb, 0x6f, 0x01, 0x8f,
- 0x3f, 0x1c, 0xb4, 0xa3, 0x6d, 0x34, 0x80, 0xc5, 0xea, 0xf7, 0xb3, 0xcf, 0x3e, 0x43, 0x20, 0x89,
- 0x42, 0x07, 0xf7, 0x52, 0x2d, 0x66, 0x2b, 0x57, 0xae, 0x44, 0xbd, 0x33, 0x30, 0x30, 0x38, 0x7a,
- 0xc4, 0xec, 0x8a, 0xcd, 0x5e, 0xff, 0xc3, 0x6b, 0x9f, 0x1d, 0xd1, 0x88, 0xb7, 0x56, 0x46, 0xb8,
- 0x94, 0xe1, 0x04, 0xf8, 0x21, 0x7a, 0x52, 0x28, 0x24, 0x9a, 0x79, 0xe5, 0xcb, 0xae, 0xc8, 0x97,
- 0x5d, 0x93, 0x2f, 0xbf, 0x2e, 0x0f, 0x99, 0x8a, 0xc0, 0x8a, 0x4a, 0xf8, 0x08, 0x5e, 0x2d, 0xbd,
- 0x44, 0x50, 0x6b, 0xbe, 0x33, 0x04, 0x06, 0x2d, 0xc5, 0x9e, 0x1e, 0x7f, 0x84, 0x16, 0x66, 0xa6,
- 0x7a, 0xd3, 0x66, 0x8f, 0xa9, 0xa9, 0x09, 0xf2, 0x07, 0xbf, 0x02, 0xac, 0xa2, 0xca, 0xa0, 0xee,
- 0x50, 0x02, 0x66, 0xfa, 0x74, 0x62, 0x3c, 0xdb, 0x01, 0x23, 0x23, 0xe4, 0x61, 0x66, 0x66, 0x56,
- 0x78, 0x78, 0xf8, 0x98, 0x93, 0xd9, 0xf7, 0xed, 0xdb, 0xc7, 0xe1, 0x70, 0x07, 0x39, 0x5c, 0x62,
- 0x79, 0x57, 0x36, 0x31, 0x77, 0x21, 0x68, 0xac, 0x35, 0xc9, 0xff, 0xb2, 0x37, 0x1b, 0xca, 0xdd,
- 0xc3, 0xc3, 0x83, 0x51, 0x5d, 0x9d, 0x98, 0x94, 0xe4, 0xe9, 0xe9, 0x69, 0x41, 0x74, 0x87, 0xad,
- 0x9f, 0x3f, 0x7f, 0x3e, 0x90, 0x40, 0x8d, 0xa4, 0xfd, 0xa3, 0xa1, 0x3a, 0x86, 0x49, 0xa0, 0x17,
- 0x95, 0x0b, 0xd0, 0x05, 0xa7, 0x01, 0xba, 0x33, 0x67, 0xce, 0x44, 0xe4, 0xae, 0xa6, 0xb6, 0x78,
- 0xcd, 0x9a, 0xb5, 0x88, 0x89, 0x0e, 0x19, 0x1b, 0x9f, 0xb4, 0x3c, 0x78, 0xeb, 0x88, 0x76, 0x80,
- 0xe5, 0xfa, 0x48, 0xeb, 0xa5, 0x09, 0xd6, 0x4a, 0x80, 0x6e, 0x3a, 0xd9, 0xc2, 0x00, 0xe2, 0x45,
- 0xec, 0x5f, 0xe0, 0xa2, 0x50, 0xe0, 0xaa, 0x00, 0x06, 0x16, 0xa7, 0x7c, 0x17, 0x22, 0x82, 0xcb,
- 0x39, 0x4d, 0x4b, 0x3f, 0x41, 0xa8, 0x8b, 0x58, 0x0b, 0x7a, 0x88, 0xc5, 0xd2, 0xeb, 0x36, 0x7a,
- 0x46, 0x07, 0x0c, 0xd7, 0xac, 0x59, 0x03, 0x4a, 0x9f, 0x32, 0x65, 0x0a, 0x50, 0x8a, 0x1f, 0xa5,
- 0xa4, 0x0b, 0x70, 0x3b, 0x87, 0xdc, 0xea, 0xd4, 0xc6, 0xd6, 0x36, 0x28, 0xe8, 0x49, 0x41, 0x61,
- 0x91, 0xa3, 0xe3, 0xf1, 0x31, 0xfb, 0x2e, 0x2f, 0x5e, 0xbc, 0x48, 0x2d, 0xfe, 0xcc, 0x25, 0x37,
- 0xf7, 0xe4, 0x0e, 0x0d, 0x49, 0xaf, 0xed, 0xf9, 0x97, 0xbd, 0x8d, 0x81, 0x2e, 0xbc, 0xbc, 0xbc,
- 0x10, 0xda, 0x46, 0x45, 0x47, 0xbb, 0x7b, 0x5c, 0x3c, 0x70, 0xc0, 0xe8, 0xfb, 0xa5, 0x4b, 0xc1,
- 0x5a, 0xc8, 0xf6, 0x3f, 0x44, 0xd0, 0xbe, 0x93, 0x8d, 0x6e, 0x76, 0x20, 0x5b, 0xcc, 0x08, 0xd6,
- 0x85, 0xb0, 0x01, 0x0d, 0xd2, 0xe9, 0xf4, 0xa5, 0x4b, 0x97, 0x6e, 0xda, 0xb4, 0x69, 0xaf, 0x9e,
- 0x9e, 0xb5, 0xa9, 0xb1, 0xab, 0xe5, 0xbe, 0x3b, 0x36, 0xba, 0x41, 0xb6, 0x1b, 0xa2, 0x0f, 0xab,
- 0x24, 0x58, 0x12, 0x51, 0x7f, 0x8a, 0x03, 0x3d, 0xcd, 0x91, 0x0e, 0xd9, 0x90, 0xe9, 0x44, 0xcb,
- 0xfc, 0x89, 0x4e, 0xa5, 0x8c, 0x13, 0x74, 0xc8, 0x00, 0x00, 0x1b, 0xe7, 0x44, 0x9b, 0x29, 0x3e,
- 0xb6, 0x58, 0xe5, 0x66, 0xa5, 0x7f, 0xc0, 0x40, 0x1f, 0xec, 0xbd, 0x60, 0xc1, 0x02, 0xe4, 0x15,
- 0x15, 0x28, 0x51, 0xa3, 0xe2, 0xc9, 0x95, 0x1e, 0xc7, 0x81, 0xde, 0x11, 0x76, 0x9d, 0x3c, 0x79,
- 0x2a, 0x3a, 0x26, 0x36, 0x2e, 0x2e, 0x7e, 0xcc, 0x45, 0xc6, 0x60, 0xd1, 0xd1, 0xd1, 0x00, 0x2a,
- 0xa8, 0x15, 0x09, 0xb8, 0xad, 0xaa, 0x62, 0x48, 0x4f, 0xc1, 0xfe, 0xcb, 0xde, 0xc6, 0xe0, 0x61,
- 0xc1, 0x4b, 0x0f, 0x1f, 0x3e, 0x2c, 0x2c, 0x2a, 0x86, 0x9f, 0x42, 0xce, 0x23, 0x0a, 0xa3, 0xd1,
- 0xe9, 0xd0, 0x06, 0xff, 0xb6, 0x34, 0x2b, 0x6d, 0x62, 0xe8, 0x7e, 0x42, 0x3a, 0x0e, 0x54, 0x37,
- 0x04, 0x6b, 0xd0, 0xba, 0x40, 0x05, 0x34, 0xe7, 0xaa, 0x55, 0xab, 0xb4, 0xb4, 0xb4, 0x0e, 0xec,
- 0x37, 0x70, 0xb0, 0x30, 0x76, 0xb3, 0x36, 0xf4, 0xb1, 0xdf, 0xf5, 0xd4, 0x7a, 0x5d, 0xa4, 0xb9,
- 0x4a, 0x8c, 0x19, 0xd1, 0xb8, 0x1a, 0x6f, 0x29, 0x4e, 0xd0, 0x00, 0xe0, 0x55, 0x5a, 0xb4, 0x29,
- 0x3d, 0xd4, 0x6c, 0xb1, 0x97, 0x95, 0xf6, 0x09, 0x73, 0x83, 0xdd, 0x3b, 0x77, 0x2c, 0x5f, 0xbe,
- 0x7c, 0xde, 0xbc, 0x79, 0x5f, 0x7f, 0xfd, 0xf5, 0x3f, 0xfe, 0xf1, 0x4f, 0xf1, 0x80, 0xb7, 0x91,
- 0x79, 0x19, 0x5f, 0xc9, 0xc9, 0x13, 0x9b, 0xf3, 0x9e, 0x3b, 0xe7, 0x9c, 0xf0, 0xfc, 0xf9, 0xed,
- 0x3b, 0x77, 0xc6, 0xec, 0x0e, 0x00, 0x2d, 0xe7, 0xe4, 0xe6, 0xf6, 0x0f, 0x0c, 0x40, 0xc4, 0x22,
- 0xf8, 0x1a, 0x20, 0x86, 0xfa, 0x7b, 0xfe, 0xd5, 0x71, 0xf0, 0xde, 0x86, 0x22, 0x06, 0x1d, 0x3d,
- 0x09, 0x0e, 0x4e, 0x4d, 0x4d, 0xbb, 0x79, 0xeb, 0x96, 0x91, 0x91, 0xd1, 0xf7, 0xdf, 0x2f, 0x9d,
- 0x3e, 0x7d, 0xfa, 0x47, 0x59, 0xb0, 0xeb, 0x77, 0x36, 0xf1, 0x60, 0x06, 0x71, 0xff, 0x1a, 0xd4,
- 0xc2, 0xac, 0x59, 0xb3, 0xe4, 0xe5, 0xe5, 0xd5, 0xd5, 0xd5, 0xd7, 0xad, 0x5b, 0xa7, 0xbb, 0x5d,
- 0xf7, 0xe0, 0x81, 0xfd, 0x76, 0x16, 0x07, 0xcf, 0xda, 0x98, 0x5c, 0xb3, 0x3b, 0xe0, 0x6b, 0xb7,
- 0xeb, 0xb1, 0xcd, 0xe6, 0x10, 0x8b, 0x15, 0xa1, 0x16, 0x1a, 0xa1, 0x16, 0xcb, 0x42, 0x8e, 0xac,
- 0x0e, 0xb0, 0xd9, 0x7a, 0xcb, 0x4e, 0xdf, 0xe9, 0x88, 0x91, 0xf1, 0x7e, 0xfd, 0x2d, 0x5b, 0xb6,
- 0xa8, 0xaa, 0xaa, 0xc1, 0xef, 0x83, 0xba, 0x25, 0xb4, 0xbd, 0x78, 0x26, 0x91, 0xac, 0xac, 0x2c,
- 0xb9, 0x25, 0xc4, 0xa9, 0xe0, 0xa7, 0x21, 0xe6, 0xe6, 0xe6, 0xe3, 0xc7, 0x8f, 0x97, 0x9e, 0xe9,
- 0x86, 0xe8, 0x20, 0x27, 0x37, 0xaf, 0xb1, 0xa9, 0xa9, 0xba, 0xa6, 0xb6, 0xa6, 0xb6, 0xae, 0xbe,
- 0xbe, 0x01, 0x92, 0x00, 0x75, 0xea, 0x2d, 0x26, 0xc9, 0xbd, 0xd6, 0x50, 0x2b, 0x3f, 0xd6, 0x90,
- 0xd4, 0x3f, 0xa3, 0xa1, 0x70, 0x21, 0xc6, 0x1e, 0x3f, 0x0e, 0xba, 0x7f, 0xff, 0x81, 0xc5, 0xe1,
- 0xc3, 0x2b, 0x57, 0xae, 0x9a, 0x3d, 0x7b, 0x36, 0x25, 0x0c, 0xfe, 0x58, 0x04, 0xbe, 0xb7, 0x89,
- 0x1b, 0xca, 0x00, 0x5d, 0x54, 0x3d, 0x4a, 0xe8, 0x02, 0xba, 0xa4, 0xd0, 0x55, 0x83, 0xef, 0x26,
- 0x7a, 0xd6, 0xb4, 0x75, 0xf4, 0xf6, 0xec, 0x3e, 0x60, 0xb8, 0xdf, 0xe4, 0xa0, 0xb1, 0xb9, 0xe9,
- 0x21, 0x73, 0x93, 0x43, 0x26, 0x07, 0x8d, 0x0c, 0x0d, 0xf6, 0xed, 0xd0, 0xd5, 0x85, 0x9e, 0x5f,
- 0xbc, 0x78, 0x31, 0x94, 0x00, 0x34, 0x06, 0xf2, 0x81, 0xea, 0x10, 0x94, 0xd0, 0x48, 0xd4, 0x62,
- 0x8f, 0x73, 0xe7, 0xcd, 0xfb, 0xe1, 0x87, 0x35, 0x87, 0x8f, 0x1c, 0xb9, 0x77, 0xcf, 0x3b, 0x2e,
- 0x3e, 0x3e, 0x2b, 0x2b, 0x3b, 0xbf, 0xa0, 0xb0, 0xb0, 0xa8, 0x08, 0x3e, 0x8b, 0x48, 0x85, 0x45,
- 0x05, 0x05, 0x85, 0x79, 0x79, 0xf9, 0x59, 0xd9, 0x39, 0xf1, 0x09, 0xcf, 0xa3, 0xa0, 0xbd, 0x62,
- 0x62, 0x93, 0x93, 0x53, 0x10, 0xa3, 0xe1, 0x4b, 0x1c, 0x7d, 0x71, 0xda, 0xfb, 0xa4, 0x22, 0xc8,
- 0x66, 0x89, 0x84, 0x2f, 0x8b, 0x8a, 0x8a, 0x8b, 0x8a, 0x4b, 0x88, 0xcd, 0xf3, 0xca, 0xca, 0xc9,
- 0x7e, 0x0c, 0x08, 0x90, 0xea, 0xea, 0xea, 0x1a, 0xd4, 0x14, 0xd4, 0x95, 0xba, 0xfa, 0x06, 0xa4,
- 0xfa, 0x86, 0x17, 0x89, 0xf8, 0x58, 0x57, 0x5f, 0x43, 0xae, 0x96, 0x80, 0xb3, 0xaa, 0x18, 0x8c,
- 0x8a, 0xca, 0xca, 0xb2, 0xf2, 0x8a, 0xd2, 0xd2, 0xb2, 0xe2, 0x92, 0x52, 0xdc, 0xa7, 0xe8, 0x35,
- 0x3f, 0xf4, 0x1e, 0x09, 0x5e, 0x26, 0x35, 0x2d, 0x8d, 0x1a, 0x43, 0xf8, 0xa1, 0x29, 0x25, 0x35,
- 0x31, 0x31, 0x09, 0x1a, 0x2c, 0x3c, 0x22, 0xe2, 0x86, 0xa7, 0xe7, 0xc1, 0x43, 0x87, 0x96, 0x2d,
- 0x5b, 0x8e, 0x28, 0xe6, 0xf3, 0xcf, 0x3f, 0xff, 0xd3, 0x71, 0xac, 0x84, 0x8d, 0x16, 0xba, 0x20,
- 0x49, 0xbc, 0x11, 0xfc, 0x38, 0xa0, 0x0b, 0x0f, 0x02, 0x47, 0x0f, 0xe2, 0x5d, 0xb8, 0x70, 0x21,
- 0x00, 0x8c, 0x60, 0x7f, 0xe9, 0x52, 0x0d, 0x38, 0x1a, 0xfc, 0xa1, 0xa2, 0xa2, 0x02, 0x4a, 0x84,
- 0x12, 0x46, 0x90, 0x05, 0x2a, 0x43, 0x5d, 0xa6, 0xd6, 0x27, 0x91, 0x96, 0xf4, 0xd4, 0x82, 0xba,
- 0x38, 0x0d, 0xc2, 0x43, 0x5b, 0x5b, 0xdb, 0xf6, 0xe8, 0x51, 0x77, 0x77, 0x8f, 0xdb, 0xb7, 0x6f,
- 0x7b, 0xfb, 0xf8, 0xf8, 0xfa, 0xfa, 0x51, 0xe6, 0xeb, 0xeb, 0x8b, 0x4f, 0x77, 0xef, 0x7a, 0x5d,
- 0xbf, 0x71, 0x03, 0x61, 0xc2, 0x79, 0x17, 0x57, 0xd7, 0x0b, 0x6e, 0x97, 0x2e, 0x5f, 0xf6, 0xf4,
- 0xbc, 0x79, 0xd7, 0xcb, 0x0b, 0xe7, 0x8d, 0x9c, 0xf8, 0xf1, 0xec, 0x3e, 0x58, 0xe7, 0xc1, 0x03,
- 0x7f, 0xff, 0x87, 0x8f, 0x1e, 0x05, 0x04, 0x06, 0x3e, 0x46, 0x40, 0x18, 0x1c, 0x1c, 0xf2, 0xec,
- 0x59, 0x58, 0x58, 0x18, 0xca, 0x37, 0x22, 0x32, 0x32, 0x32, 0x8a, 0xa8, 0x37, 0x54, 0xc2, 0x47,
- 0x7c, 0x19, 0x16, 0x1e, 0x8e, 0x13, 0x82, 0x9f, 0x3e, 0x85, 0x2c, 0xa4, 0x36, 0x32, 0xf3, 0x7f,
- 0xf8, 0x10, 0x37, 0xc1, 0xad, 0x3e, 0xfa, 0xd3, 0x7d, 0x14, 0x43, 0xae, 0x79, 0x7b, 0x7b, 0x43,
- 0x0f, 0x20, 0x33, 0xad, 0x6d, 0x6c, 0x7e, 0xd4, 0xd4, 0x54, 0x5a, 0xb8, 0x90, 0x6a, 0x98, 0xfd,
- 0xb3, 0xe8, 0xd8, 0x37, 0x1b, 0xd5, 0x3d, 0x41, 0x75, 0xae, 0x7d, 0x32, 0xd2, 0xb3, 0x46, 0x36,
- 0xed, 0x7e, 0x05, 0xd7, 0x3c, 0x71, 0x22, 0x31, 0x89, 0x60, 0x2a, 0x69, 0x93, 0x27, 0x4f, 0x01,
- 0x9e, 0xc9, 0xb1, 0xca, 0x5f, 0x50, 0x23, 0x00, 0xdf, 0xd0, 0xca, 0x47, 0x8d, 0xd7, 0x42, 0x15,
- 0x80, 0x3f, 0x02, 0xec, 0x37, 0x6f, 0xd9, 0xb2, 0x67, 0x8f, 0x9e, 0x91, 0x91, 0xb1, 0x89, 0x89,
- 0xa9, 0xa9, 0xa9, 0x99, 0xa9, 0x19, 0x99, 0x4c, 0xcd, 0xf0, 0xd1, 0xc8, 0xd8, 0xd8, 0xc0, 0x60,
- 0xff, 0x1e, 0x3d, 0xbd, 0x9d, 0xbb, 0x76, 0xed, 0xda, 0xbd, 0x5b, 0x6f, 0xef, 0xde, 0xfd, 0x86,
- 0x86, 0x07, 0x0f, 0x1e, 0x7a, 0x79, 0xda, 0xc7, 0x4b, 0x66, 0x66, 0xc4, 0x06, 0x6a, 0xe6, 0x16,
- 0xb0, 0xc3, 0x87, 0x41, 0xfd, 0x96, 0x96, 0xd6, 0xd6, 0x36, 0xb6, 0xb6, 0xc4, 0xdc, 0x5e, 0x7b,
- 0x87, 0x63, 0xc7, 0x8e, 0x39, 0x3a, 0x3a, 0x1e, 0x3f, 0x7e, 0xfc, 0x04, 0x12, 0xfe, 0x8f, 0x4f,
- 0xf8, 0x0e, 0x07, 0x50, 0xdd, 0x50, 0xf4, 0x96, 0x56, 0x56, 0x38, 0x1f, 0xd7, 0xe1, 0x62, 0xdc,
- 0x02, 0xb7, 0xfa, 0xe8, 0x8f, 0xf7, 0x71, 0x12, 0x95, 0xab, 0x46, 0x46, 0x7b, 0xf6, 0xec, 0xd9,
- 0xbc, 0x79, 0xb3, 0xaa, 0x9a, 0x1a, 0x8a, 0x00, 0x6e, 0xf4, 0xf7, 0x19, 0x66, 0xf0, 0x7b, 0x9a,
- 0x44, 0xcf, 0x1a, 0xd5, 0xb4, 0x4b, 0x2d, 0x88, 0xfa, 0x0f, 0xd2, 0xf0, 0x07, 0x25, 0x0e, 0x71,
- 0x14, 0xe7, 0x8c, 0x49, 0xad, 0xa3, 0xef, 0x06, 0x3c, 0xe3, 0xaa, 0xaf, 0xc6, 0x8f, 0x9f, 0x3e,
- 0x7d, 0x06, 0xf4, 0x06, 0xc8, 0x56, 0x5d, 0x7d, 0x09, 0xa2, 0x00, 0x98, 0x86, 0x86, 0x06, 0xc5,
- 0xdb, 0xf8, 0xa8, 0xbe, 0x64, 0x89, 0xaa, 0xaa, 0xaa, 0xb2, 0xb2, 0xb2, 0xa2, 0x12, 0x61, 0xca,
- 0x8b, 0x16, 0x8d, 0x10, 0x3b, 0x75, 0xe2, 0x6f, 0x67, 0xcb, 0x60, 0xcb, 0x97, 0xaf, 0xa0, 0xa6,
- 0xe3, 0xad, 0x26, 0xec, 0x07, 0x68, 0x18, 0xca, 0xf0, 0x07, 0x3e, 0xe0, 0x2b, 0x44, 0xa6, 0x38,
- 0x8c, 0x93, 0x70, 0x2e, 0xce, 0xc7, 0x55, 0xbf, 0xe9, 0x33, 0x7d, 0xb8, 0xbd, 0xc8, 0x55, 0xf5,
- 0x25, 0xc8, 0x70, 0x64, 0x3b, 0x32, 0xff, 0xab, 0xaf, 0xc6, 0x7f, 0xac, 0x45, 0x11, 0xff, 0x9d,
- 0x4d, 0x0c, 0x60, 0xf1, 0x94, 0x0a, 0xea, 0x6f, 0xea, 0xfb, 0xb7, 0xbc, 0x83, 0x78, 0xaa, 0xc5,
- 0xf8, 0xf1, 0x5f, 0x4f, 0x98, 0x30, 0x11, 0xbe, 0x09, 0x84, 0x3d, 0xc2, 0xd9, 0x53, 0xa9, 0xbf,
- 0xf1, 0x25, 0x98, 0xfc, 0xdb, 0x09, 0x13, 0xbe, 0x21, 0x6d, 0x02, 0xce, 0x23, 0x89, 0x7d, 0xf4,
- 0x99, 0xbf, 0xa9, 0x4d, 0x23, 0x6d, 0xfa, 0x88, 0x8d, 0xcc, 0xce, 0x9b, 0x41, 0x7d, 0x9c, 0x36,
- 0x62, 0xbf, 0xc7, 0xa3, 0x7c, 0x0c, 0x13, 0xe7, 0x2a, 0x32, 0x12, 0xd9, 0x8e, 0xcc, 0x47, 0x11,
- 0xfc, 0xfb, 0x37, 0xc6, 0xfe, 0x9b, 0x18, 0xa5, 0x37, 0xa8, 0x0e, 0x05, 0x8a, 0xae, 0xc7, 0x34,
- 0x1c, 0xfa, 0x9f, 0x51, 0xf6, 0x86, 0x33, 0x7f, 0x07, 0x13, 0x3b, 0x94, 0x3f, 0xbb, 0x8d, 0x76,
- 0x88, 0xa3, 0xe1, 0xfa, 0xff, 0x01, 0x00, 0x07, 0xdb, 0x50, 0xec, 0x6b, 0x02, 0x00
-};
-
-fastimage_t bfin_logo = {
-		DEF_BFIN_LOGO_DATA,
-		DEF_BFIN_LOGO_WIDTH,
-		DEF_BFIN_LOGO_HEIGHT,
-		DEF_BFIN_LOGO_BPP,
-		DEF_BFIN_LOGO_PIXEL_SIZE,
-		DEF_BFIN_LOGO_SIZE
-};
diff --git a/arch/blackfin/include/asm/bfin_logo_230x230_lzma.h b/arch/blackfin/include/asm/bfin_logo_230x230_lzma.h
deleted file mode 100644
index ae9554f..0000000
--- a/arch/blackfin/include/asm/bfin_logo_230x230_lzma.h
+++ /dev/null
@@ -1,1819 +0,0 @@
-/*
- * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
- *
- * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
- *
- * Where:	'screen'	is the pointer to the frame buffer
- *		'width'	is the screen width
- *		'x'		is the horizontal position
- *		'y'		is the vertical position
- */
-
-#define EASYLOGO_ENABLE_LZMA 28532
-
-static unsigned char EASYLOGO_DECOMP_BUFFER[158700];
-
-#include <video_easylogo.h>
-
-#define	DEF_BFIN_LOGO_WIDTH		230
-#define	DEF_BFIN_LOGO_HEIGHT		230
-#define	DEF_BFIN_LOGO_PIXELS		52900
-#define	DEF_BFIN_LOGO_BPP		24
-#define	DEF_BFIN_LOGO_PIXEL_SIZE	3
-#define	DEF_BFIN_LOGO_SIZE		158700
-
-unsigned char DEF_BFIN_LOGO_DATA[] = {
- 0x5d, 0x00, 0x00, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x6f,
- 0xfd, 0xf8, 0xb8, 0x51, 0x47, 0x76, 0x83, 0x1a, 0x36, 0xff, 0xdf, 0x25, 0x3b, 0x9e, 0x1e, 0xfc,
- 0x17, 0x17, 0x7c, 0x3f, 0x4c, 0x3f, 0x42, 0x00, 0x19, 0xe1, 0x7c, 0x13, 0xce, 0xa1, 0xb5, 0xdf,
- 0x06, 0x70, 0x2e, 0xb6, 0x6c, 0xe0, 0xcb, 0x11, 0xf6, 0x92, 0x94, 0x8a, 0x99, 0x3e, 0x21, 0xb2,
- 0x27, 0xe8, 0x4c, 0x5d, 0x4c, 0x45, 0x6d, 0xfa, 0x0d, 0x07, 0x51, 0x9c, 0xc1, 0xf2, 0x53, 0x6d,
- 0x9e, 0x57, 0xb5, 0x3a, 0x93, 0x8c, 0x7e, 0x3d, 0x18, 0x78, 0x1a, 0x13, 0x72, 0x7a, 0xa6, 0x0f,
- 0x90, 0x31, 0x39, 0xfe, 0xe1, 0x4c, 0x12, 0xda, 0x4f, 0xe8, 0xe7, 0x3f, 0x68, 0xe5, 0xc3, 0x2e,
- 0x8c, 0xeb, 0x62, 0x9a, 0x99, 0x26, 0xf6, 0x64, 0x2e, 0x15, 0x1f, 0xd6, 0xa2, 0xbd, 0xe9, 0xa2,
- 0x87, 0x70, 0xd8, 0x35, 0x60, 0x6d, 0x05, 0x11, 0x97, 0x62, 0x11, 0x11, 0x31, 0x08, 0xb8, 0xe5,
- 0xe1, 0x76, 0x47, 0x2d, 0x42, 0x5d, 0x06, 0xa1, 0x5c, 0x30, 0xf0, 0x11, 0x9d, 0xf7, 0x13, 0x4d,
- 0xbd, 0x5f, 0x8f, 0x2b, 0xb2, 0x2e, 0x47, 0x7e, 0x21, 0x1e, 0xce, 0x05, 0x29, 0x0d, 0x38, 0xcb,
- 0x05, 0xc9, 0x55, 0xde, 0xc9, 0x66, 0xb3, 0xf9, 0x0b, 0xbb, 0x76, 0x6b, 0x36, 0x81, 0x16, 0x59,
- 0xce, 0xbf, 0x02, 0x66, 0x52, 0xa1, 0x75, 0xff, 0xb0, 0xb7, 0x8e, 0x5b, 0x56, 0xaf, 0xdc, 0x62,
- 0x7a, 0xc5, 0xf0, 0xa8, 0xc3, 0xf8, 0xf5, 0x32, 0xef, 0xd7, 0x65, 0xdf, 0x2b, 0x64, 0x9d, 0x1b,
- 0x99, 0x63, 0x0d, 0x11, 0xb2, 0xc8, 0x4a, 0xf6, 0x27, 0xb7, 0xa1, 0xfb, 0x25, 0x7a, 0xfd, 0x69,
- 0x01, 0xfa, 0xc8, 0x2b, 0xe8, 0x44, 0x83, 0x66, 0x72, 0xb6, 0xa9, 0x8a, 0xb2, 0x2a, 0x6f, 0xfe,
- 0xe8, 0xca, 0x85, 0x21, 0x83, 0x77, 0x08, 0x03, 0xc2, 0xd5, 0xd0, 0x68, 0xc4, 0xb3, 0xca, 0x54,
- 0x9b, 0xa9, 0x2b, 0x3e, 0x59, 0xf7, 0x99, 0xa6, 0xed, 0x02, 0xb3, 0x37, 0x4f, 0x2c, 0x2f, 0x79,
- 0x09, 0x6e, 0x68, 0x64, 0xe4, 0xee, 0x3e, 0x25, 0x59, 0x6c, 0x19, 0xfa, 0x8e, 0x03, 0xb1, 0x1a,
- 0x47, 0xc6, 0x7f, 0xea, 0xe9, 0x6a, 0x5b, 0xff, 0x94, 0x8d, 0x93, 0xfd, 0x7e, 0x45, 0x39, 0x81,
- 0xe5, 0xbe, 0xe0, 0xa1, 0x9f, 0x08, 0xd6, 0x71, 0x5f, 0xd9, 0xa8, 0x99, 0x3b, 0xae, 0x4e, 0x03,
- 0xc9, 0x2c, 0x86, 0x61, 0xae, 0xe4, 0x33, 0x72, 0xed, 0xac, 0x53, 0x49, 0x7e, 0xb2, 0xc1, 0xab,
- 0xad, 0x71, 0x70, 0xff, 0x22, 0xff, 0xe6, 0x4f, 0x55, 0x3c, 0xf8, 0xb2, 0xc5, 0x55, 0x2a, 0x7e,
- 0x0f, 0x34, 0x9f, 0x64, 0x54, 0x2c, 0x91, 0x9e, 0xeb, 0x31, 0xa7, 0x83, 0x5f, 0x69, 0x97, 0xee,
- 0xc5, 0x24, 0x62, 0x3a, 0xa3, 0x69, 0x47, 0x06, 0x59, 0x56, 0x60, 0x5f, 0x74, 0xb3, 0x8f, 0x4f,
- 0xf5, 0x8e, 0xbe, 0xaa, 0x9d, 0xba, 0x6c, 0x27, 0xf7, 0x0b, 0x7b, 0xd6, 0x94, 0x73, 0x34, 0xc5,
- 0xa5, 0x3c, 0xbf, 0x4a, 0xde, 0x3f, 0x04, 0x74, 0x67, 0xeb, 0xc9, 0x9f, 0x93, 0x0e, 0xa0, 0xed,
- 0x1c, 0x17, 0x23, 0xb6, 0xac, 0x37, 0x41, 0xdc, 0x24, 0xc4, 0x10, 0xab, 0x0a, 0x14, 0x2c, 0xe8,
- 0x00, 0x34, 0x71, 0xe5, 0x21, 0x22, 0x84, 0x4b, 0x26, 0xf5, 0x59, 0x87, 0x39, 0xda, 0x59, 0x9d,
- 0xbb, 0x22, 0x63, 0x1b, 0x34, 0xfe, 0xb8, 0xba, 0xdf, 0x3c, 0x58, 0x68, 0xa1, 0x73, 0xab, 0x68,
- 0x3f, 0xba, 0xad, 0x30, 0x0d, 0x35, 0x75, 0xca, 0xa7, 0x54, 0xda, 0x8e, 0xdf, 0x43, 0x98, 0xc7,
- 0x72, 0xa3, 0x3b, 0x96, 0x93, 0x5d, 0x86, 0x1f, 0xa7, 0xe0, 0x97, 0x2c, 0xc7, 0x59, 0x30, 0x88,
- 0xec, 0xc2, 0x89, 0x56, 0x1d, 0xda, 0x76, 0xed, 0xf3, 0x53, 0xd5, 0x38, 0x63, 0x70, 0x36, 0x5d,
- 0x89, 0xb1, 0xa9, 0x1f, 0x99, 0x2d, 0x95, 0x89, 0xf3, 0x3f, 0xa7, 0x1a, 0x6b, 0x6a, 0xda, 0xb8,
- 0xba, 0x62, 0x87, 0x28, 0xac, 0x21, 0x7b, 0x47, 0xc2, 0x17, 0xb1, 0x1c, 0x97, 0x63, 0xf6, 0x43,
- 0xb2, 0x62, 0x28, 0x26, 0x0e, 0x76, 0x8c, 0x48, 0x92, 0x1a, 0xde, 0xa7, 0x54, 0xb7, 0xba, 0x4b,
- 0x87, 0xf1, 0xdf, 0xae, 0x4d, 0x72, 0xd4, 0x5d, 0x55, 0x60, 0x39, 0x04, 0x2c, 0xe6, 0x61, 0x09,
- 0x04, 0x74, 0xf9, 0x64, 0x40, 0x52, 0x40, 0xca, 0x04, 0xbb, 0xec, 0x1f, 0xe0, 0x65, 0x21, 0x6f,
- 0x11, 0x69, 0xe5, 0xca, 0xc1, 0xce, 0x70, 0xe0, 0x56, 0x2e, 0x40, 0x38, 0xeb, 0x74, 0x1b, 0x2e,
- 0xef, 0x4f, 0x2b, 0x6b, 0x9b, 0xa9, 0xbe, 0xa1, 0x83, 0x7e, 0x6c, 0x08, 0x1f, 0xc9, 0x2e, 0xf9,
- 0xc7, 0x41, 0xc5, 0xa4, 0xe4, 0x76, 0x0d, 0xca, 0x44, 0x23, 0x4f, 0x60, 0xb5, 0x11, 0x2d, 0xa0,
- 0x6d, 0x28, 0xf2, 0xc5, 0x46, 0x52, 0xe9, 0xfd, 0xa9, 0x9a, 0xf8, 0x5b, 0x9d, 0x60, 0x06, 0x0c,
- 0x25, 0x6c, 0xb6, 0x61, 0x86, 0x56, 0xf5, 0x07, 0x8d, 0xaa, 0xd7, 0x88, 0x9d, 0xc4, 0x40, 0x4a,
- 0x53, 0xd5, 0xe6, 0x3d, 0x06, 0xae, 0x77, 0xf4, 0x27, 0xa5, 0x65, 0x74, 0x98, 0xc7, 0xfe, 0x79,
- 0xca, 0x55, 0xce, 0x49, 0x26, 0x72, 0xd3, 0x54, 0xa9, 0x12, 0xac, 0xa0, 0xf1, 0xe6, 0x73, 0x17,
- 0xc2, 0xfa, 0x9b, 0x0f, 0x0c, 0xcc, 0x92, 0x0a, 0x53, 0x56, 0x4d, 0x8f, 0x58, 0x2d, 0xcb, 0xc0,
- 0x8c, 0xf9, 0x65, 0x24, 0xa4, 0xf0, 0xd4, 0x37, 0xa4, 0x3f, 0xd7, 0x46, 0xe7, 0x16, 0xcc, 0xf1,
- 0x52, 0x3f, 0xf8, 0xa0, 0x7a, 0xb3, 0x21, 0x39, 0x31, 0xfa, 0x6c, 0x23, 0xb2, 0xf8, 0x81, 0xf1,
- 0xc5, 0x53, 0xa5, 0x06, 0xaf, 0x01, 0x10, 0x7e, 0x80, 0xed, 0xe6, 0x04, 0xac, 0x32, 0x28, 0xb2,
- 0xaa, 0x9b, 0x8e, 0x58, 0xfa, 0x54, 0x43, 0xeb, 0x6c, 0x6e, 0xf9, 0x6d, 0x9a, 0x6b, 0x8c, 0xb1,
- 0x98, 0x6d, 0xf4, 0xd9, 0xd0, 0x0c, 0xba, 0x29, 0x01, 0x06, 0x7c, 0x8c, 0xb6, 0x55, 0xe1, 0x06,
- 0xa1, 0xed, 0x96, 0x13, 0x53, 0x33, 0x9e, 0x2a, 0xb3, 0x91, 0xc4, 0xbd, 0x1a, 0x86, 0xea, 0xaf,
- 0xa3, 0xb4, 0xf2, 0xa2, 0xc3, 0xe4, 0x09, 0x70, 0xe1, 0x2d, 0xd1, 0xf2, 0xf1, 0x32, 0xbd, 0x97,
- 0x7f, 0xfd, 0x80, 0x33, 0xa5, 0x5c, 0xf4, 0xf0, 0xba, 0x25, 0xb2, 0x6a, 0x7f, 0xe7, 0x1f, 0x22,
- 0x42, 0xa9, 0x0e, 0xa5, 0x1f, 0x12, 0x11, 0xe9, 0xa2, 0x1e, 0x53, 0x82, 0x64, 0x1b, 0x06, 0x3e,
- 0x69, 0x00, 0xb3, 0x7b, 0x82, 0xfa, 0x53, 0xc2, 0xab, 0x2c, 0xb0, 0x56, 0xda, 0xe9, 0x64, 0x25,
- 0x08, 0x8e, 0x85, 0x48, 0xd4, 0xd7, 0x7e, 0x0f, 0xa6, 0x59, 0xf3, 0xdf, 0x0f, 0x95, 0x88, 0x3f,
- 0x4f, 0xbd, 0xa6, 0x0e, 0x87, 0x53, 0xd0, 0x8c, 0x4f, 0x92, 0xe7, 0x80, 0xaf, 0x1e, 0x89, 0x83,
- 0x6c, 0x69, 0x5c, 0xe7, 0xc6, 0x19, 0x12, 0x31, 0xe8, 0x3a, 0x2c, 0x55, 0x9b, 0x40, 0xaf, 0xb3,
- 0xaf, 0x47, 0xcb, 0x1a, 0x66, 0x60, 0x79, 0x4c, 0x1b, 0x93, 0xbd, 0xf9, 0x03, 0x75, 0xce, 0xa1,
- 0xc1, 0x0c, 0x52, 0xd5, 0x82, 0x9f, 0xb3, 0x5c, 0xaf, 0x4c, 0x15, 0xef, 0x38, 0x00, 0xdc, 0x4b,
- 0x1d, 0x93, 0x7c, 0xc1, 0xa0, 0xe9, 0x0a, 0x2f, 0xa6, 0xf1, 0x0f, 0x3a, 0xfb, 0xe3, 0x31, 0xf8,
- 0x7d, 0x79, 0x83, 0xde, 0x23, 0x14, 0xfc, 0x74, 0x28, 0x7d, 0xad, 0x02, 0x53, 0x37, 0x50, 0x63,
- 0xc5, 0xa9, 0x80, 0x4c, 0x26, 0xf8, 0x30, 0xa7, 0xa5, 0x0d, 0xcf, 0x91, 0xd5, 0x7b, 0x82, 0x1e,
- 0xcd, 0x8c, 0x49, 0xde, 0x02, 0x9c, 0x95, 0x8f, 0xd0, 0x5b, 0x80, 0xaf, 0xd9, 0xc6, 0x62, 0x70,
- 0x1e, 0x41, 0x19, 0xe5, 0x36, 0xce, 0x06, 0x34, 0xc5, 0xe6, 0x16, 0x4b, 0x42, 0xfa, 0xca, 0x73,
- 0xdc, 0x1c, 0x74, 0xd5, 0x23, 0xcc, 0xde, 0x96, 0x57, 0x88, 0x8f, 0x12, 0x47, 0x24, 0xa3, 0x4e,
- 0x50, 0x17, 0xb0, 0x31, 0xe2, 0x89, 0x68, 0xd0, 0x29, 0xb4, 0x25, 0x01, 0xf7, 0x9d, 0x1b, 0xa1,
- 0x0d, 0xcf, 0xa3, 0x46, 0x83, 0xd0, 0x41, 0x00, 0x84, 0xd3, 0x6a, 0xe6, 0xd4, 0xff, 0x0a, 0x88,
- 0x9e, 0x4a, 0xd5, 0x57, 0xa0, 0x86, 0xe3, 0x35, 0x75, 0x95, 0x2a, 0x35, 0xaf, 0x93, 0x8c, 0x63,
- 0x14, 0x40, 0xc5, 0xe9, 0x74, 0xe7, 0xf6, 0x55, 0x38, 0xe1, 0x26, 0xb1, 0xc9, 0x03, 0x97, 0x5b,
- 0x23, 0xd5, 0xe8, 0x7b, 0xfe, 0xe5, 0xdd, 0x4d, 0x1b, 0x1a, 0x37, 0xb6, 0x12, 0x3a, 0xb4, 0x74,
- 0x9c, 0x08, 0xc1, 0x76, 0x77, 0xb7, 0x2f, 0xd7, 0xa7, 0x48, 0x1d, 0xa2, 0x3d, 0x68, 0x6b, 0x5d,
- 0xf1, 0xba, 0x82, 0x50, 0xe4, 0x80, 0x63, 0xdd, 0x47, 0xe8, 0xdf, 0x19, 0xb7, 0x26, 0x9b, 0x1a,
- 0xdf, 0x6a, 0x81, 0x3f, 0x0d, 0xe1, 0xa7, 0x9f, 0x7e, 0x1c, 0x5e, 0xbb, 0xe7, 0x9d, 0xff, 0x9d,
- 0x66, 0x82, 0xaf, 0x12, 0x49, 0xb2, 0xaa, 0xdb, 0xd1, 0x82, 0xe2, 0x22, 0xcb, 0xbc, 0xbf, 0x3f,
- 0xd2, 0xa7, 0x5f, 0xb7, 0x0e, 0x57, 0x5a, 0x24, 0xb2, 0xe8, 0x8c, 0x0f, 0x7f, 0xd6, 0x70, 0x50,
- 0x2c, 0x40, 0x5a, 0x8d, 0x97, 0x01, 0xe7, 0x21, 0x1c, 0xab, 0xa7, 0x55, 0x3e, 0x4e, 0xe2, 0x70,
- 0xf9, 0xb4, 0x69, 0x5b, 0xe1, 0x64, 0x12, 0xd3, 0x23, 0x26, 0x78, 0x2c, 0x60, 0xb4, 0xb1, 0xba,
- 0x1a, 0xff, 0x59, 0x26, 0x7a, 0x54, 0xa8, 0x8f, 0x4b, 0x2c, 0x6d, 0xe4, 0xeb, 0xb2, 0x12, 0xc6,
- 0x3d, 0x7b, 0xa8, 0x6d, 0x70, 0xd3, 0xcf, 0x73, 0x38, 0xf4, 0xab, 0x50, 0x1d, 0x49, 0xe0, 0xb0,
- 0x85, 0xd1, 0x9a, 0x8e, 0x14, 0x3e, 0x0c, 0x2b, 0x26, 0x61, 0x50, 0x48, 0x3d, 0xbe, 0xae, 0x53,
- 0xd8, 0xc1, 0x49, 0xe3, 0x58, 0x06, 0x9c, 0xd0, 0xdc, 0x4e, 0xc7, 0x8e, 0x43, 0xd1, 0x76, 0x0b,
- 0x27, 0xbe, 0x89, 0x96, 0x46, 0xdc, 0x66, 0x2f, 0x6c, 0xbf, 0xd9, 0x08, 0xf9, 0x04, 0xf8, 0x7e,
- 0x6b, 0x63, 0xb5, 0x2c, 0x4d, 0x4c, 0x91, 0x89, 0x62, 0xb2, 0x2e, 0x85, 0x95, 0x52, 0x38, 0x1a,
- 0xea, 0xac, 0x50, 0x2a, 0x33, 0x03, 0xe4, 0x0b, 0x78, 0x97, 0xaa, 0x35, 0xf5, 0x04, 0x6e, 0xf4,
- 0x5b, 0xf8, 0xb6, 0x1b, 0x3b, 0xf3, 0xf6, 0x99, 0xf5, 0x31, 0xf2, 0x96, 0xe4, 0x26, 0x7b, 0x00,
- 0x3a, 0x08, 0x7a, 0x94, 0xeb, 0xce, 0x61, 0xd4, 0x3b, 0x93, 0x4f, 0x86, 0x84, 0xaf, 0xee, 0x23,
- 0x8a, 0x8d, 0x7d, 0xab, 0x2d, 0xc0, 0xc6, 0x8d, 0x27, 0x0b, 0x80, 0x96, 0xb0, 0x6e, 0x86, 0xa7,
- 0xf1, 0xbc, 0x48, 0x3e, 0x74, 0x25, 0x8c, 0x5b, 0x74, 0xa1, 0xc4, 0xeb, 0xab, 0x09, 0xb8, 0xd2,
- 0x15, 0xa0, 0x7f, 0x20, 0x91, 0x6b, 0x09, 0xda, 0xbc, 0x98, 0x06, 0xec, 0xea, 0xdd, 0xae, 0xcd,
- 0xe8, 0xb6, 0x85, 0x26, 0x61, 0xb9, 0xa5, 0xc5, 0x4e, 0xae, 0xfc, 0x0f, 0x2b, 0x9c, 0x42, 0xc6,
- 0x8b, 0x28, 0x60, 0x04, 0x7d, 0x67, 0x23, 0x6a, 0xfd, 0xa3, 0x60, 0x19, 0x97, 0x50, 0x04, 0xd1,
- 0xb1, 0x7b, 0x6a, 0xa7, 0x0a, 0x44, 0x61, 0xfe, 0xeb, 0xe6, 0xcf, 0x42, 0x7c, 0x3b, 0x82, 0xcc,
- 0x41, 0x52, 0x82, 0xe0, 0xbd, 0xa2, 0x05, 0xf3, 0x98, 0xd3, 0xdc, 0x95, 0x6c, 0x59, 0x4b, 0x31,
- 0xdc, 0x5e, 0x1e, 0x4e, 0x3d, 0x18, 0x95, 0xe6, 0xc3, 0xcd, 0xa9, 0x9e, 0xf4, 0xfe, 0xf0, 0x85,
- 0xf8, 0xb1, 0xd0, 0x2f, 0x7d, 0x9c, 0xb5, 0x83, 0xde, 0xd7, 0x80, 0x0a, 0x56, 0xcd, 0xe8, 0x5b,
- 0xbd, 0xdc, 0x60, 0xce, 0x26, 0xf7, 0xc9, 0x11, 0xd7, 0x2a, 0x69, 0xf0, 0xa3, 0x62, 0x83, 0x2c,
- 0xe8, 0x9a, 0xec, 0x43, 0x91, 0x12, 0x2b, 0x2a, 0x41, 0x50, 0x67, 0x02, 0x30, 0xc0, 0x4d, 0xb4,
- 0xc8, 0x6c, 0x40, 0x25, 0x55, 0xf1, 0x67, 0x7a, 0x11, 0x05, 0x3b, 0x9f, 0x55, 0xce, 0xec, 0x69,
- 0x13, 0x68, 0x1a, 0x8c, 0x7d, 0xba, 0x3f, 0x98, 0x4a, 0xf7, 0x9a, 0x44, 0x31, 0x2a, 0x3d, 0x3b,
- 0xe6, 0x0e, 0x6a, 0x71, 0x1b, 0xea, 0xf9, 0x19, 0x9a, 0x09, 0x1a, 0x4d, 0xe9, 0xef, 0x39, 0xf2,
- 0x80, 0x77, 0x0e, 0x4e, 0x54, 0x0f, 0xc4, 0x8f, 0xdc, 0xa4, 0xb7, 0xb5, 0x63, 0xdd, 0x3a, 0x4f,
- 0xdc, 0xd2, 0x17, 0x3b, 0x1c, 0xbc, 0xfa, 0xa2, 0x15, 0x69, 0x26, 0x8c, 0x1e, 0x68, 0xc9, 0x14,
- 0xc5, 0x4e, 0x69, 0x98, 0xc1, 0x3c, 0x5d, 0x8b, 0x02, 0x70, 0xb5, 0x94, 0x90, 0x71, 0x1e, 0xb6,
- 0xd9, 0x10, 0x5d, 0x67, 0x37, 0x75, 0x38, 0x8e, 0x0e, 0x75, 0xf8, 0xcd, 0x67, 0x94, 0xdd, 0x82,
- 0xd6, 0xec, 0xc2, 0x91, 0xf6, 0x10, 0x5d, 0x9c, 0xf7, 0x28, 0xed, 0x5d, 0x70, 0x4c, 0x92, 0x45,
- 0xd8, 0x86, 0xbe, 0x9a, 0x3c, 0x31, 0x76, 0x18, 0x80, 0x0a, 0xdd, 0x7e, 0x06, 0x95, 0xc6, 0x14,
- 0x7e, 0x7d, 0xce, 0x1f, 0xd1, 0x66, 0xc6, 0xef, 0xc5, 0x63, 0x25, 0x95, 0x39, 0x64, 0x14, 0x28,
- 0xae, 0x51, 0x6d, 0x0d, 0x9c, 0xc0, 0x5a, 0x3a, 0xdb, 0x02, 0xae, 0x50, 0x43, 0x34, 0x3b, 0x49,
- 0x31, 0xf4, 0x6b, 0x4f, 0x85, 0xf6, 0x1d, 0x53, 0x88, 0x76, 0xd3, 0x01, 0x71, 0xfc, 0x23, 0x06,
- 0x63, 0x9f, 0x3d, 0xd2, 0x00, 0x8d, 0xc7, 0x5a, 0x2f, 0x8a, 0x54, 0xfc, 0x76, 0x0f, 0x7a, 0x76,
- 0x0f, 0xfb, 0x2f, 0x1c, 0x0a, 0x3b, 0x3f, 0xd6, 0xad, 0xfc, 0xcf, 0x68, 0x6b, 0x0b, 0xae, 0x9c,
- 0xda, 0xeb, 0x8d, 0x8f, 0x7f, 0x7d, 0x1a, 0x55, 0x28, 0x90, 0xa8, 0xc0, 0x04, 0x25, 0xa2, 0x7b,
- 0xb3, 0x3b, 0xd0, 0x9d, 0x79, 0xc0, 0xb5, 0x7f, 0x84, 0x7c, 0x85, 0xda, 0x59, 0xda, 0xfb, 0xb3,
- 0xab, 0x26, 0x51, 0x9e, 0x92, 0x6f, 0xce, 0x53, 0x8c, 0xf8, 0x72, 0x1b, 0xcf, 0x31, 0x41, 0x04,
- 0x9f, 0x7e, 0x8f, 0x9e, 0xc4, 0xfe, 0x56, 0xd3, 0x54, 0x1e, 0x1d, 0xe8, 0x3e, 0x49, 0xd3, 0x41,
- 0xf1, 0x37, 0x1e, 0xb1, 0xa9, 0x5d, 0x59, 0x5f, 0x17, 0x34, 0x0a, 0x86, 0x01, 0xb5, 0x71, 0xa0,
- 0x22, 0xe7, 0x35, 0x6f, 0xf1, 0x50, 0x55, 0x38, 0xa6, 0x4e, 0x80, 0x8a, 0xd4, 0x25, 0x67, 0x81,
- 0xa5, 0xc6, 0x3c, 0x45, 0x31, 0xf4, 0x1d, 0x31, 0x69, 0xf3, 0x25, 0xe2, 0xde, 0x0f, 0xb3, 0xc6,
- 0x44, 0x73, 0x7a, 0xd0, 0xf2, 0xac, 0x2e, 0xbf, 0xf7, 0xad, 0x8c, 0xe1, 0x33, 0x66, 0xf2, 0x03,
- 0x67, 0xbe, 0x4a, 0xbf, 0x4e, 0x3a, 0xf5, 0x99, 0x15, 0x55, 0x8f, 0xac, 0xe2, 0xa4, 0x82, 0x4e,
- 0x44, 0xbb, 0xd8, 0xa1, 0x26, 0x32, 0x5f, 0xf8, 0x54, 0x16, 0x96, 0x43, 0x37, 0x3d, 0x98, 0x6e,
- 0xec, 0x3a, 0xa4, 0x66, 0x65, 0x6a, 0xbc, 0x1e, 0xd1, 0xe8, 0xde, 0x44, 0x74, 0x1f, 0x32, 0x12,
- 0x3c, 0xe7, 0x4c, 0x1c, 0x15, 0x46, 0x9c, 0xa2, 0x27, 0x54, 0x64, 0x48, 0xe4, 0x36, 0xc2, 0x7d,
- 0xb4, 0xd7, 0xc9, 0xf7, 0xd2, 0x5c, 0x80, 0x0b, 0xe6, 0x52, 0x96, 0x42, 0x9e, 0xb3, 0x03, 0x60,
- 0x67, 0x29, 0x4f, 0x6a, 0xab, 0x62, 0x32, 0x0d, 0x9c, 0x20, 0x9e, 0xa9, 0x6c, 0x48, 0x51, 0x70,
- 0xe6, 0x17, 0x83, 0xfc, 0x56, 0xf4, 0xcc, 0xba, 0x06, 0x9d, 0x37, 0x7a, 0x55, 0xe3, 0xf0, 0xda,
- 0xe7, 0x27, 0x57, 0x3b, 0x35, 0x32, 0x9e, 0x13, 0xa5, 0x14, 0x2e, 0x1f, 0x88, 0xe5, 0xb8, 0x2c,
- 0x45, 0x16, 0x24, 0x7d, 0x1e, 0x28, 0x63, 0xdb, 0x67, 0x43, 0xcf, 0xda, 0x19, 0x99, 0x96, 0x3d,
- 0x6d, 0x06, 0x65, 0x8c, 0xce, 0x73, 0x51, 0x8c, 0x4f, 0xaf, 0x5c, 0xa8, 0x85, 0xce, 0x12, 0xe6,
- 0xf0, 0xfe, 0x20, 0x09, 0x08, 0xd0, 0x18, 0xdb, 0x61, 0x0e, 0x95, 0x5f, 0xa0, 0x48, 0xb9, 0xbb,
- 0xfe, 0x45, 0x15, 0x7d, 0x2f, 0x74, 0x88, 0x24, 0x14, 0xb3, 0x60, 0x39, 0x7b, 0x86, 0x3c, 0x8a,
- 0x3c, 0x81, 0x01, 0xc7, 0xbf, 0xc6, 0xd3, 0xf8, 0x36, 0xc7, 0x8b, 0x52, 0xec, 0x86, 0x9c, 0x01,
- 0x5b, 0xb6, 0x1a, 0x97, 0xc9, 0xc9, 0x5d, 0x26, 0x35, 0xb1, 0x33, 0x5b, 0x7b, 0xd3, 0x94, 0xb8,
- 0xe6, 0x32, 0xb6, 0x8c, 0x92, 0x95, 0x10, 0x8f, 0x20, 0xe9, 0x07, 0xf8, 0x4b, 0xb6, 0x45, 0xd0,
- 0x39, 0xed, 0xdb, 0xe5, 0x51, 0xf7, 0xa4, 0x02, 0x91, 0x29, 0x7c, 0xe6, 0x14, 0x52, 0x2a, 0x79,
- 0xcf, 0xe0, 0xcf, 0x16, 0x48, 0x90, 0x44, 0xcd, 0x34, 0x65, 0xef, 0x1f, 0xea, 0x26, 0xfd, 0x19,
- 0x0c, 0xea, 0x4b, 0x34, 0x2d, 0x39, 0x08, 0xd5, 0x48, 0xbf, 0xdc, 0x41, 0x7d, 0xb6, 0xa5, 0x92,
- 0x2a, 0xde, 0xf9, 0x99, 0xbe, 0xc8, 0x36, 0xd3, 0x31, 0x77, 0x3c, 0x2b, 0x2f, 0xa9, 0x1c, 0x80,
- 0x5b, 0xc9, 0x40, 0x21, 0xb8, 0x3e, 0xa4, 0x2f, 0x01, 0xe7, 0x2c, 0xce, 0x64, 0xdc, 0x1b, 0xfb,
- 0x10, 0xc5, 0x08, 0x18, 0x3a, 0x3b, 0x0d, 0x41, 0x32, 0xd3, 0x7c, 0x13, 0xb9, 0x85, 0x59, 0x94,
- 0x5e, 0x27, 0x0b, 0x77, 0x34, 0x33, 0xd7, 0x59, 0xee, 0x65, 0xab, 0xc3, 0xaf, 0xd2, 0xd3, 0x19,
- 0x6e, 0xcb, 0x09, 0x30, 0x46, 0x14, 0x69, 0x91, 0xb5, 0x0b, 0x61, 0x40, 0x55, 0xce, 0x49, 0x5d,
- 0x95, 0xfe, 0x81, 0xcb, 0xbe, 0x20, 0x59, 0x11, 0xa8, 0x89, 0xc1, 0xab, 0xf2, 0xcf, 0x8f, 0xf5,
- 0xe1, 0x67, 0x03, 0xb0, 0xf8, 0x5b, 0x23, 0x5b, 0x9c, 0x73, 0xb3, 0xb4, 0xb3, 0x71, 0x6e, 0xd7,
- 0x46, 0xed, 0x61, 0x1d, 0xd2, 0x37, 0x99, 0xa4, 0xe9, 0x3b, 0x60, 0xf1, 0x33, 0x7d, 0x6b, 0xda,
- 0xb7, 0xd9, 0x7c, 0xc6, 0x5d, 0x89, 0xbd, 0xcf, 0xc4, 0x94, 0x51, 0xc2, 0x94, 0xed, 0x09, 0x04,
- 0x4a, 0x98, 0x96, 0xd5, 0x96, 0xc5, 0xcc, 0x14, 0xc4, 0x37, 0xae, 0x61, 0x04, 0xe4, 0x20, 0xef,
- 0x75, 0x90, 0x84, 0xcb, 0x9f, 0xca, 0x6a, 0xb0, 0x00, 0xfb, 0x37, 0xfb, 0x95, 0xe1, 0xe1, 0xbc,
- 0xee, 0x71, 0xd1, 0xdb, 0xa9, 0x53, 0xf7, 0x5c, 0x81, 0x27, 0x72, 0x90, 0x2f, 0x06, 0x2c, 0xbf,
- 0x7a, 0x0a, 0xf0, 0x10, 0xb7, 0xd2, 0x31, 0xbd, 0xc8, 0x80, 0x90, 0x27, 0x87, 0x0a, 0x61, 0x67,
- 0x76, 0x4d, 0xeb, 0x96, 0xb7, 0x83, 0xfe, 0xf0, 0xac, 0x70, 0x59, 0xf8, 0xd6, 0x51, 0xe3, 0xb9,
- 0x02, 0x3e, 0xbc, 0xef, 0xdf, 0xc2, 0x08, 0x17, 0x72, 0x2c, 0xa5, 0xf8, 0xf8, 0xb6, 0xfb, 0x1b,
- 0x58, 0x47, 0x03, 0x92, 0xb0, 0xa9, 0xfd, 0x18, 0xd1, 0x6d, 0xad, 0x1d, 0xca, 0x71, 0xff, 0x3c,
- 0x1b, 0xa8, 0x61, 0xa8, 0x18, 0xad, 0x4a, 0xe8, 0xbb, 0xb9, 0x34, 0xda, 0xa3, 0x30, 0x2e, 0xd9,
- 0x30, 0x6b, 0x4d, 0xc9, 0xb7, 0xc8, 0x76, 0xd1, 0xe5, 0x51, 0x14, 0x1c, 0x17, 0x3e, 0x52, 0xf6,
- 0xd7, 0x70, 0xde, 0xe7, 0x25, 0xa6, 0x27, 0x6f, 0xba, 0x13, 0xc3, 0x91, 0x99, 0xaa, 0x42, 0x3d,
- 0xb2, 0xa3, 0x0b, 0xbe, 0x9a, 0xa7, 0x51, 0x75, 0xcf, 0x54, 0x4f, 0x39, 0x62, 0xe0, 0x72, 0x82,
- 0x24, 0x19, 0x69, 0x6e, 0x23, 0x2d, 0x7c, 0xfb, 0xd6, 0xf9, 0x68, 0xa3, 0x5d, 0x71, 0x5d, 0x21,
- 0x47, 0x05, 0x08, 0x0f, 0xed, 0x47, 0xa1, 0xd9, 0x6b, 0x42, 0xcf, 0x8e, 0xb8, 0x73, 0x12, 0x58,
- 0x90, 0x71, 0x0f, 0xf6, 0xfc, 0x4a, 0x33, 0xc9, 0xc9, 0xd6, 0xc6, 0xd7, 0x71, 0x3b, 0xfb, 0xd4,
- 0xbf, 0x87, 0x43, 0x37, 0xf6, 0x18, 0xe6, 0x5c, 0xaa, 0x0f, 0x33, 0x02, 0x9e, 0x34, 0xd4, 0xb0,
- 0xa8, 0x7c, 0xdb, 0x37, 0x2d, 0x8a, 0xf3, 0xba, 0x57, 0xb8, 0xc1, 0xcb, 0xea, 0x40, 0x26, 0x28,
- 0xae, 0xda, 0xe4, 0x96, 0x09, 0xea, 0x78, 0xe3, 0x70, 0xc6, 0x61, 0x17, 0x47, 0x9f, 0xd4, 0xd8,
- 0x01, 0x0c, 0x78, 0xc6, 0xba, 0x5a, 0xc2, 0x20, 0x33, 0x60, 0xe1, 0x4f, 0x59, 0x45, 0x41, 0xda,
- 0x75, 0xcb, 0x5f, 0x46, 0x1c, 0xdd, 0xa2, 0x2e, 0xd5, 0x5d, 0xba, 0x49, 0x7a, 0x34, 0x6b, 0x02,
- 0x7e, 0xe6, 0xaa, 0x08, 0x74, 0x60, 0xa9, 0x6d, 0xab, 0x9f, 0xfe, 0x72, 0xbf, 0x98, 0x1a, 0xec,
- 0x7a, 0x4d, 0x3b, 0xf9, 0x98, 0x6f, 0x58, 0x2c, 0xc9, 0x9c, 0xe2, 0xcc, 0xc0, 0x06, 0x2a, 0x4a,
- 0x57, 0x29, 0xdc, 0x83, 0xc9, 0xbd, 0x99, 0x67, 0xcb, 0x97, 0x1c, 0x6a, 0xd6, 0xf2, 0xbe, 0x95,
- 0xeb, 0xa4, 0xab, 0xae, 0xb3, 0xb3, 0x0d, 0x3a, 0xfb, 0x63, 0xfe, 0x57, 0xa3, 0xcb, 0x37, 0x3c,
- 0x7b, 0xc0, 0xd4, 0xf8, 0x3b, 0x1e, 0x66, 0x1a, 0xa4, 0xb0, 0xa6, 0x2f, 0x1b, 0x2f, 0x8a, 0xfd,
- 0x5e, 0xe7, 0x91, 0x5b, 0x38, 0x32, 0x08, 0xab, 0xad, 0xa0, 0x39, 0xab, 0xe7, 0xb1, 0x25, 0xfb,
- 0x57, 0x5e, 0xff, 0xc8, 0x98, 0xe2, 0xde, 0xd7, 0x82, 0x21, 0x86, 0x66, 0x04, 0xf3, 0x73, 0x82,
- 0x7b, 0x10, 0x11, 0x33, 0x7d, 0x44, 0x6e, 0xc4, 0x67, 0xf8, 0xca, 0x4d, 0x30, 0x29, 0xfe, 0x24,
- 0xa3, 0x2d, 0xd5, 0xfa, 0x48, 0x25, 0x9e, 0xa4, 0x1f, 0xc0, 0x43, 0xdb, 0x9c, 0x7e, 0x89, 0xe9,
- 0xf9, 0x9a, 0x5c, 0x16, 0xf3, 0xef, 0x59, 0xe9, 0xdf, 0x0f, 0x5d, 0xda, 0x61, 0x8d, 0x4c, 0xc1,
- 0x0e, 0xb4, 0xa2, 0x4d, 0x0d, 0xb3, 0x55, 0x31, 0x95, 0xa2, 0xf9, 0xaa, 0xee, 0xa8, 0xa6, 0xc9,
- 0x47, 0xec, 0x97, 0xe6, 0x10, 0xb5, 0x3f, 0xc5, 0xcf, 0x90, 0x46, 0xf6, 0xb0, 0xb5, 0xa3, 0x24,
- 0x35, 0xa5, 0x9a, 0xde, 0xe0, 0xda, 0x18, 0xd6, 0xdb, 0x47, 0x8b, 0xa0, 0x5c, 0x43, 0x6c, 0x9d,
- 0x44, 0x3d, 0xb5, 0xb5, 0x26, 0x13, 0xda, 0xe8, 0x60, 0x42, 0xa5, 0x85, 0x5b, 0x7e, 0x3a, 0x34,
- 0xb1, 0x28, 0x83, 0x8c, 0x09, 0x34, 0xd8, 0x2c, 0x74, 0xa9, 0x42, 0x9b, 0xa8, 0xd4, 0xb7, 0xa9,
- 0x4b, 0xdf, 0xa6, 0x6e, 0x2b, 0x44, 0xae, 0xb9, 0x36, 0xb8, 0xc9, 0x22, 0x03, 0xd7, 0x20, 0x59,
- 0x90, 0x8a, 0x92, 0xab, 0x88, 0x18, 0x8c, 0xeb, 0x72, 0x88, 0xa1, 0x96, 0x46, 0xad, 0x94, 0x92,
- 0xb6, 0x69, 0x73, 0x93, 0xe0, 0xd9, 0x79, 0x7b, 0x48, 0xb0, 0xa1, 0x28, 0x2d, 0x2d, 0x92, 0x84,
- 0x60, 0x37, 0x8b, 0xc6, 0x35, 0x8d, 0x70, 0x6a, 0x18, 0x12, 0xd6, 0xce, 0x58, 0x58, 0x6e, 0x67,
- 0xea, 0xb0, 0xdc, 0x79, 0x86, 0xe2, 0x5c, 0x6a, 0x39, 0x08, 0x38, 0x01, 0x31, 0x78, 0xcc, 0x18,
- 0x88, 0xde, 0x36, 0xbc, 0x82, 0xd2, 0xb4, 0x21, 0x67, 0x4e, 0x8d, 0x5a, 0x4a, 0x53, 0xbf, 0x77,
- 0x86, 0xf7, 0xf5, 0x6c, 0x47, 0x18, 0xee, 0xe6, 0xd3, 0xde, 0x2b, 0xcf, 0x1d, 0x39, 0x79, 0x7c,
- 0xd5, 0x52, 0xaf, 0x58, 0xbf, 0x6f, 0xfd, 0x62, 0x36, 0x33, 0xf2, 0xb1, 0x08, 0x7d, 0x67, 0x64,
- 0xea, 0x96, 0x48, 0x5f, 0xf6, 0x9e, 0x63, 0x51, 0xdc, 0x14, 0xae, 0x76, 0xbc, 0x8e, 0x89, 0x37,
- 0x9e, 0x1e, 0xae, 0xaa, 0x11, 0x9c, 0x11, 0xc2, 0x7e, 0xab, 0x32, 0x90, 0xdf, 0xb4, 0x02, 0x93,
- 0x45, 0x33, 0x81, 0x83, 0x00, 0x28, 0x78, 0xf6, 0x17, 0xad, 0x0c, 0x73, 0x19, 0x7b, 0x32, 0x5b,
- 0xe6, 0x9a, 0x35, 0x3d, 0x12, 0xe0, 0x29, 0xdd, 0xb4, 0xb5, 0xce, 0xcf, 0xc1, 0x75, 0xe9, 0x24,
- 0x8b, 0x02, 0x91, 0xdb, 0x1c, 0xb5, 0x03, 0xc7, 0xf0, 0xfd, 0xc5, 0xa0, 0x5e, 0xea, 0xa2, 0xfb,
- 0x80, 0xd2, 0xc4, 0x78, 0xd8, 0xb8, 0x85, 0x42, 0xc1, 0x3b, 0xf2, 0x46, 0x61, 0x32, 0xdb, 0xec,
- 0x57, 0x68, 0x56, 0x6d, 0x8e, 0x35, 0x56, 0x37, 0x92, 0x36, 0x73, 0x6c, 0xcd, 0x63, 0x82, 0x4f,
- 0xda, 0x29, 0xd7, 0x75, 0x8f, 0xef, 0x9a, 0xe3, 0x3d, 0x5c, 0xf5, 0x37, 0xf3, 0xd1, 0x82, 0x55,
- 0xeb, 0xcc, 0xa4, 0x22, 0x5e, 0x72, 0x9b, 0xcd, 0xdb, 0x9d, 0x49, 0x00, 0xeb, 0xe1, 0x43, 0x93,
- 0xdc, 0x5c, 0x18, 0x0a, 0xbb, 0xfb, 0x78, 0x26, 0xaf, 0x0a, 0x6a, 0x11, 0x52, 0xe0, 0xf5, 0xd3,
- 0xbc, 0x5d, 0x32, 0xbe, 0x69, 0xa6, 0x13, 0x67, 0xae, 0xf1, 0x7f, 0x00, 0x0d, 0x5a, 0xaa, 0x8c,
- 0x4a, 0xee, 0x44, 0x27, 0xa3, 0x02, 0x25, 0x7e, 0x5b, 0xb6, 0xcd, 0xd2, 0xea, 0x15, 0x2b, 0x6b,
- 0x9e, 0x66, 0x23, 0x31, 0x80, 0xb7, 0xee, 0x01, 0x80, 0x0d, 0x85, 0x51, 0xd7, 0x10, 0x6d, 0x0e,
- 0x64, 0x38, 0x3e, 0x3b, 0x87, 0x9c, 0x5e, 0xfc, 0xea, 0xb6, 0xd1, 0x9a, 0x46, 0x83, 0x53, 0x14,
- 0x85, 0x13, 0xce, 0x8f, 0x96, 0xf5, 0xa1, 0x6a, 0x2f, 0x68, 0x3f, 0xd4, 0xd7, 0xb2, 0x22, 0x3d,
- 0x3c, 0xf7, 0x0f, 0x90, 0x52, 0x73, 0xbb, 0x17, 0x7c, 0x76, 0xe1, 0x4f, 0x21, 0xed, 0x7a, 0xce,
- 0x0c, 0xf7, 0x7d, 0x38, 0x7f, 0xa3, 0x7b, 0x11, 0xbb, 0x0f, 0x81, 0xbe, 0xde, 0x98, 0x99, 0x0e,
- 0x7e, 0xeb, 0x0a, 0x21, 0x09, 0x32, 0xcf, 0xc2, 0x53, 0x47, 0x45, 0xfa, 0x16, 0x84, 0x3f, 0xf5,
- 0x8b, 0x11, 0x4a, 0x46, 0xa9, 0xbb, 0x5d, 0x2d, 0xa4, 0xeb, 0x6a, 0x8b, 0x5f, 0xc8, 0xab, 0xb1,
- 0xe1, 0xe4, 0x3d, 0x2b, 0xdd, 0x34, 0xd3, 0x35, 0x2a, 0x86, 0xf5, 0x5f, 0xf0, 0xd3, 0xc1, 0x6d,
- 0xd3, 0x6a, 0xec, 0x1d, 0x79, 0x4c, 0xdd, 0xa0, 0x3d, 0x8a, 0x8b, 0xa1, 0xc7, 0x4b, 0x3a, 0x94,
- 0x48, 0x9e, 0x88, 0xfe, 0xfd, 0x1c, 0x32, 0x75, 0xae, 0x7b, 0xaa, 0xe4, 0x06, 0xc8, 0x5a, 0x00,
- 0xc0, 0x66, 0x69, 0x46, 0xd2, 0x45, 0xd7, 0xc0, 0x9b, 0xe7, 0xb5, 0xd6, 0x45, 0x4f, 0xd5, 0x04,
- 0xd1, 0xa3, 0x33, 0xbb, 0x9b, 0x6d, 0xc2, 0xa1, 0xb1, 0x83, 0x5e, 0x9f, 0xd7, 0x94, 0xca, 0xe2,
- 0x7a, 0x00, 0x60, 0xf2, 0x8b, 0x68, 0xe2, 0xb2, 0x4e, 0x83, 0x7a, 0x5b, 0xa0, 0x68, 0xa1, 0xa8,
- 0x51, 0x3d, 0x52, 0x71, 0xe5, 0x04, 0x0e, 0x07, 0x26, 0xec, 0x5e, 0x71, 0xfa, 0x0b, 0x31, 0xbc,
- 0xbb, 0xc2, 0xf7, 0x7e, 0x2b, 0xca, 0xb7, 0xe7, 0x17, 0x24, 0x47, 0x5e, 0x78, 0x86, 0xf7, 0xd7,
- 0xe6, 0x9b, 0x7f, 0x6a, 0x72, 0xb0, 0x36, 0xf0, 0xdd, 0x86, 0x92, 0x01, 0x0e, 0xf3, 0xa0, 0x09,
- 0x4f, 0xd6, 0xbb, 0x68, 0x28, 0x3d, 0x5e, 0x93, 0x09, 0x59, 0x64, 0xa3, 0xa0, 0xad, 0x42, 0x4d,
- 0x65, 0xf7, 0xf4, 0x29, 0xea, 0x4f, 0x67, 0x23, 0xf3, 0x92, 0x3a, 0x08, 0x29, 0xe4, 0xdc, 0x73,
- 0x26, 0xa1, 0xd6, 0x4c, 0x13, 0x82, 0x3d, 0xe1, 0x9b, 0x8f, 0x5e, 0x5c, 0x9e, 0x49, 0xe5, 0x0e,
- 0x63, 0xd4, 0x7e, 0xd5, 0x46, 0x6f, 0xfd, 0xc1, 0x0f, 0x35, 0x3d, 0x37, 0xf8, 0xe3, 0x19, 0xe7,
- 0x7d, 0x3a, 0x79, 0x42, 0x9e, 0xc8, 0xff, 0x91, 0xbd, 0xdc, 0x62, 0xe5, 0xc8, 0x7a, 0xd2, 0x2f,
- 0xd0, 0xbf, 0x01, 0xad, 0x0f, 0x69, 0x54, 0x2e, 0x06, 0x41, 0xd0, 0x2b, 0x12, 0x4f, 0x4a, 0x13,
- 0xcd, 0xe7, 0x04, 0x49, 0x1b, 0x0a, 0x09, 0x11, 0xcc, 0x35, 0x33, 0xb6, 0xb9, 0xec, 0xc9, 0x39,
- 0xf5, 0x5f, 0x30, 0x7a, 0x9d, 0x2f, 0xbf, 0xee, 0xf8, 0xf0, 0x5e, 0x27, 0x3c, 0x82, 0xee, 0xbc,
- 0xc9, 0xa6, 0xec, 0x42, 0x1c, 0x5a, 0x57, 0x50, 0x47, 0xa6, 0x17, 0x2f, 0x68, 0x0a, 0xba, 0xe1,
- 0x8e, 0x39, 0x15, 0xf2, 0x33, 0x41, 0x2d, 0x6c, 0xe2, 0xac, 0x49, 0x81, 0x35, 0x4d, 0xb9, 0xf3,
- 0x0b, 0xf1, 0x49, 0xda, 0x68, 0x91, 0xf5, 0x9a, 0x09, 0x6b, 0x14, 0x49, 0x59, 0x60, 0x64, 0x43,
- 0x71, 0xa3, 0xff, 0xff, 0x82, 0xa7, 0xb9, 0x8d, 0x7d, 0x0d, 0x91, 0x9f, 0x05, 0xb0, 0xdd, 0xa8,
- 0x4b, 0xf5, 0xb7, 0xbd, 0x68, 0xed, 0xce, 0xa9, 0x66, 0x16, 0x67, 0x82, 0xc9, 0x7c, 0x22, 0xe4,
- 0x34, 0xab, 0xb9, 0x34, 0x5a, 0x5f, 0x67, 0x89, 0x34, 0x6b, 0x53, 0x4c, 0x2f, 0xb9, 0xf6, 0x11,
- 0x1e, 0x2f, 0xe3, 0xa6, 0x26, 0x42, 0x45, 0xe1, 0x62, 0x68, 0xbd, 0x16, 0xe1, 0xed, 0x74, 0xfa,
- 0x0c, 0xa5, 0x87, 0xd9, 0xbc, 0x80, 0xe2, 0xb8, 0xc1, 0x53, 0xe7, 0x66, 0x7f, 0x7c, 0x67, 0x1d,
- 0x43, 0x74, 0x9b, 0x94, 0x57, 0xd9, 0xb1, 0x86, 0x0d, 0xa1, 0xcf, 0x07, 0x87, 0x94, 0x0d, 0xca,
- 0xac, 0x01, 0xa5, 0x81, 0x09, 0xfc, 0x0a, 0x62, 0x7a, 0xe5, 0x31, 0xcc, 0xb9, 0x9f, 0xc2, 0x40,
- 0xd3, 0x33, 0xbc, 0x95, 0xce, 0x9f, 0x85, 0xf6, 0xf4, 0xbc, 0x44, 0xe5, 0x20, 0xa8, 0xba, 0x9b,
- 0x5c, 0x7d, 0x58, 0x8c, 0x9f, 0x35, 0xe7, 0x91, 0x64, 0xb8, 0x1f, 0x86, 0xe6, 0xca, 0xe5, 0x73,
- 0x08, 0xe5, 0x0b, 0xd2, 0x7b, 0x98, 0xe1, 0xb8, 0x6d, 0x19, 0x9e, 0xe5, 0xa7, 0x54, 0x7b, 0xdd,
- 0x24, 0x80, 0xd5, 0x6c, 0x27, 0x36, 0x75, 0x0b, 0x57, 0xc7, 0xd8, 0xde, 0xa6, 0xee, 0x02, 0xeb,
- 0xa2, 0x9d, 0xa3, 0xa2, 0x35, 0x5f, 0x65, 0xca, 0x24, 0x9a, 0xe1, 0xe0, 0x99, 0x6a, 0xd1, 0x25,
- 0x50, 0xd6, 0xed, 0x3e, 0x20, 0x52, 0xe6, 0xec, 0x14, 0x41, 0xf7, 0xbb, 0x2c, 0x53, 0x95, 0x70,
- 0x08, 0x02, 0xd3, 0x3c, 0xd2, 0x21, 0xa4, 0x8d, 0xaa, 0xc9, 0x31, 0x8e, 0x9e, 0xc9, 0x9d, 0x40,
- 0x8b, 0x8b, 0xc0, 0x63, 0x5a, 0xeb, 0xcb, 0x71, 0xa9, 0x7b, 0x30, 0xc3, 0xc0, 0xd6, 0x57, 0x00,
- 0x4b, 0x58, 0x9a, 0xce, 0x36, 0xd1, 0x06, 0xfb, 0xc2, 0xcd, 0x34, 0x2f, 0x6d, 0x14, 0x75, 0x46,
- 0xa0, 0xe2, 0x68, 0x9c, 0x5e, 0xcd, 0x13, 0xaf, 0xb4, 0xb3, 0xa3, 0xec, 0x48, 0x3a, 0x17, 0x8d,
- 0x98, 0xe3, 0xdc, 0x41, 0x62, 0x14, 0x17, 0xcc, 0x55, 0x7d, 0xdb, 0xd8, 0x96, 0x07, 0x02, 0xb0,
- 0x2a, 0xb8, 0x71, 0xc2, 0x79, 0x50, 0x5b, 0x7a, 0x84, 0x43, 0x4a, 0xc4, 0x14, 0xd3, 0x18, 0x7e,
- 0x5e, 0x4a, 0x9f, 0x90, 0x0e, 0x37, 0xbf, 0xcf, 0x15, 0xcd, 0xfd, 0x33, 0x91, 0x58, 0xdc, 0x78,
- 0x9e, 0x7f, 0x9a, 0xbc, 0xb5, 0x6e, 0x66, 0xa4, 0xed, 0x7d, 0xd7, 0x51, 0x7b, 0x21, 0x3b, 0x5b,
- 0x2c, 0xc3, 0xa3, 0x4f, 0x33, 0x5c, 0x49, 0xc2, 0x81, 0xf7, 0xc6, 0x78, 0x89, 0x93, 0x2b, 0xd2,
- 0xbf, 0x4b, 0x40, 0x26, 0xf5, 0x39, 0x18, 0xc9, 0x2c, 0xc1, 0xae, 0xb4, 0xa9, 0x20, 0xab, 0x6f,
- 0x89, 0x46, 0x56, 0xb7, 0xc6, 0xfc, 0xbb, 0x3a, 0x15, 0x73, 0x68, 0x12, 0xab, 0xfa, 0x76, 0x1d,
- 0x9f, 0x80, 0x78, 0xdf, 0x1e, 0x52, 0xc5, 0xa1, 0x73, 0xc4, 0x88, 0xf6, 0xb3, 0xe4, 0x94, 0x10,
- 0x1c, 0xe5, 0x70, 0x3f, 0x26, 0xf5, 0x46, 0x78, 0x97, 0xb6, 0xaf, 0x75, 0xf9, 0x2d, 0x5f, 0x13,
- 0x56, 0xb5, 0x27, 0x2e, 0x3c, 0x36, 0x18, 0xad, 0x10, 0x8e, 0xa9, 0x92, 0x39, 0x7d, 0x8b, 0x81,
- 0x43, 0x03, 0xbd, 0x65, 0x22, 0xd3, 0x1b, 0x80, 0xc6, 0xbc, 0xbd, 0x90, 0x1f, 0x59, 0xf8, 0xd7,
- 0xa4, 0xdc, 0x29, 0xfc, 0xd2, 0xb2, 0x73, 0x6b, 0x60, 0xd6, 0x2e, 0xe1, 0x1e, 0xc7, 0x1e, 0xf7,
- 0xea, 0xd1, 0x19, 0xfb, 0x5a, 0x23, 0x57, 0x9d, 0xbf, 0xdb, 0x41, 0xb9, 0x44, 0xe0, 0x8e, 0xe1,
- 0xc9, 0x9b, 0x6c, 0x0b, 0x33, 0xf5, 0x92, 0xe7, 0x33, 0xbc, 0x3b, 0x00, 0x00, 0x3f, 0x22, 0xd5,
- 0x27, 0xf0, 0xf7, 0x9f, 0x9a, 0x88, 0xc3, 0x3f, 0x0d, 0x5c, 0xff, 0x7b, 0x30, 0xd0, 0x58, 0x8d,
- 0xea, 0x52, 0xac, 0x57, 0xa8, 0x7f, 0x19, 0x84, 0x80, 0x70, 0x18, 0x6d, 0xb5, 0x8c, 0xfa, 0x03,
- 0x1c, 0xad, 0x0b, 0x75, 0x3f, 0xe9, 0x19, 0xf0, 0xb2, 0xb9, 0x64, 0xb4, 0xfe, 0xd8, 0x93, 0x09,
- 0xd9, 0x52, 0xde, 0x8a, 0x8d, 0x33, 0xf6, 0xfe, 0x03, 0xd6, 0x6f, 0x4a, 0x57, 0xcb, 0xc7, 0x80,
- 0x2b, 0x10, 0xed, 0xe7, 0x2d, 0x32, 0xf4, 0x15, 0x06, 0xf6, 0xf9, 0xa4, 0x70, 0x69, 0xd2, 0x74,
- 0x91, 0x33, 0xa0, 0xb6, 0xc9, 0x31, 0x8a, 0x46, 0xe3, 0xa9, 0x15, 0x04, 0xc5, 0xc4, 0xec, 0x04,
- 0x53, 0x1b, 0x0e, 0xe0, 0xf2, 0x8d, 0x78, 0x1c, 0xdc, 0x49, 0x91, 0x6f, 0x36, 0xd3, 0xf7, 0xe3,
- 0x3b, 0x69, 0x2a, 0xdb, 0x53, 0xdf, 0x2f, 0xb8, 0xe2, 0xdc, 0x20, 0x67, 0x09, 0x10, 0x81, 0xcf,
- 0xde, 0x25, 0xdd, 0xcf, 0x2d, 0x3c, 0x62, 0xff, 0xaf, 0x7d, 0xb0, 0xbe, 0x1b, 0x09, 0x62, 0xdb,
- 0x45, 0xc9, 0x2c, 0x56, 0x58, 0xe6, 0x2b, 0xed, 0x28, 0x12, 0xe6, 0x92, 0x7d, 0x77, 0x9c, 0x61,
- 0xe7, 0xbc, 0xa7, 0x4b, 0x2d, 0xb1, 0x79, 0xf8, 0x09, 0x6a, 0x7e, 0x9f, 0xf1, 0x68, 0x2c, 0x58,
- 0x4b, 0xa9, 0x28, 0x70, 0x3e, 0x17, 0xa3, 0x5b, 0xaf, 0xc0, 0x1d, 0x9c, 0x12, 0xa5, 0xd5, 0x77,
- 0x20, 0x24, 0x52, 0xcb, 0xd4, 0xbb, 0xd2, 0x1f, 0x6b, 0x0a, 0x60, 0x9c, 0x21, 0xa0, 0x3e, 0xd3,
- 0x1e, 0xf2, 0xae, 0x47, 0xe3, 0xf3, 0x70, 0x6f, 0x02, 0x1b, 0x35, 0xd4, 0xf6, 0x5a, 0xad, 0x94,
- 0xd6, 0xab, 0x1f, 0x52, 0x3f, 0x34, 0xfc, 0x9d, 0x4b, 0x65, 0x1c, 0x23, 0xaa, 0x7a, 0x5a, 0x65,
- 0x15, 0x0e, 0x71, 0xa4, 0x06, 0x18, 0xfc, 0xa6, 0xa4, 0xc3, 0x7f, 0x7c, 0x58, 0x3a, 0xbd, 0x91,
- 0x20, 0xe0, 0xdd, 0xf9, 0x35, 0xe4, 0x2b, 0x06, 0x1c, 0x60, 0x91, 0x1d, 0x8a, 0x3b, 0xea, 0x00,
- 0xb4, 0x2f, 0xcb, 0xd5, 0x92, 0xa4, 0x66, 0xc6, 0x54, 0x60, 0x15, 0x76, 0xbf, 0x9c, 0x73, 0xaf,
- 0x64, 0xab, 0x41, 0xc7, 0x54, 0xbf, 0xca, 0x97, 0xef, 0x1f, 0xc5, 0x55, 0xaf, 0x08, 0x52, 0x36,
- 0x64, 0xf4, 0x29, 0x9f, 0xa8, 0x53, 0xd6, 0x7e, 0x91, 0xd2, 0x17, 0xfa, 0x9e, 0xf7, 0x37, 0x09,
- 0x7d, 0x01, 0xf6, 0xd4, 0x29, 0x8c, 0xfd, 0x56, 0x56, 0x2f, 0x5f, 0xf5, 0xbe, 0x6f, 0xe1, 0xb9,
- 0x82, 0x00, 0x15, 0x1d, 0xdb, 0x4a, 0xde, 0xa1, 0x34, 0x80, 0x2e, 0x4a, 0xc9, 0xc5, 0x06, 0x60,
- 0xd2, 0x80, 0x3a, 0x71, 0x6a, 0x9f, 0x5a, 0x54, 0xa2, 0x2b, 0xf2, 0x0d, 0xcc, 0x46, 0x3e, 0x7c,
- 0x0c, 0x6c, 0x15, 0xe1, 0xe1, 0x5b, 0x3f, 0xe9, 0x76, 0x01, 0x00, 0x60, 0xc2, 0x61, 0x4f, 0xa1,
- 0x0e, 0x50, 0xc4, 0x28, 0xd4, 0xe6, 0x11, 0x2e, 0xcc, 0x8f, 0xf8, 0x40, 0x7a, 0x69, 0x47, 0x58,
- 0xd4, 0x31, 0xb9, 0xe7, 0x85, 0x76, 0xe3, 0x6c, 0x7a, 0x4b, 0xe6, 0x4b, 0x75, 0xe1, 0x6a, 0xa0,
- 0x7c, 0x30, 0xa5, 0x18, 0xc1, 0xb4, 0xf8, 0xc1, 0x3e, 0x13, 0x69, 0x0f, 0xc1, 0xef, 0xe2, 0x8c,
- 0x13, 0x0d, 0xbe, 0x09, 0x1c, 0x00, 0x8d, 0xc8, 0x95, 0x79, 0xe7, 0x18, 0xb2, 0x59, 0xc4, 0x0d,
- 0xba, 0xbe, 0x06, 0x3a, 0x97, 0x42, 0xd7, 0x00, 0x53, 0x49, 0x85, 0xf6, 0xb5, 0x4f, 0x6a, 0x9f,
- 0x81, 0xca, 0x49, 0x2d, 0xb3, 0x28, 0x81, 0x27, 0x8d, 0xec, 0x0a, 0x62, 0x95, 0xce, 0x1d, 0xf9,
- 0x24, 0xd5, 0x87, 0xb1, 0x82, 0x2f, 0xd5, 0x27, 0xb9, 0xbb, 0xb7, 0x36, 0x2d, 0xbc, 0xe7, 0xa7,
- 0xca, 0xf2, 0xaf, 0x61, 0x82, 0x3d, 0x1f, 0x05, 0x3e, 0x0b, 0x61, 0xf0, 0xd6, 0x37, 0x65, 0x61,
- 0xad, 0x5d, 0x4c, 0x4b, 0x3e, 0xee, 0x1e, 0xed, 0xaa, 0x28, 0x27, 0x4c, 0x89, 0x76, 0x84, 0x88,
- 0x46, 0xee, 0x7a, 0x9a, 0x7c, 0x66, 0x80, 0xa9, 0x0c, 0x90, 0xc9, 0x6e, 0x51, 0x33, 0x49, 0xdb,
- 0x2d, 0xde, 0x20, 0x03, 0xc0, 0x07, 0x31, 0x6f, 0xc6, 0x30, 0xd8, 0x3b, 0xdd, 0xe1, 0x51, 0x22,
- 0xb6, 0x73, 0x2a, 0x02, 0x49, 0x5e, 0xa9, 0x63, 0x4f, 0xbd, 0xb6, 0x40, 0x45, 0x79, 0x2f, 0x98,
- 0xd3, 0x72, 0xbd, 0x16, 0xed, 0xa0, 0x29, 0xcb, 0x08, 0xf3, 0x01, 0x48, 0x20, 0xb2, 0x9a, 0x94,
- 0x87, 0xf8, 0x1c, 0x26, 0x76, 0xa5, 0x96, 0x39, 0xd4, 0x12, 0xe2, 0xae, 0x8b, 0x32, 0xde, 0xcc,
- 0x05, 0x02, 0x76, 0x8f, 0x2b, 0x06, 0xc8, 0xfa, 0xe6, 0xd5, 0xbd, 0x79, 0x8d, 0xc3, 0x4d, 0xb4,
- 0x29, 0x9e, 0x24, 0x20, 0x13, 0x5c, 0xc2, 0xec, 0xc4, 0x53, 0x89, 0x6c, 0x25, 0xc0, 0xa9, 0xcc,
- 0xab, 0x09, 0x45, 0x6e, 0x78, 0x50, 0x2d, 0xae, 0xdd, 0x2b, 0xc7, 0xe6, 0x03, 0x15, 0xdc, 0xd6,
- 0x51, 0x58, 0x21, 0x50, 0xc2, 0x32, 0x98, 0x80, 0x7c, 0x37, 0x37, 0x10, 0x3f, 0x08, 0x93, 0x63,
- 0x5c, 0x91, 0x41, 0xe1, 0xd4, 0x6e, 0xaa, 0xaa, 0x37, 0x02, 0x42, 0xc9, 0x81, 0xad, 0x74, 0x34,
- 0x2e, 0x9c, 0xd3, 0x33, 0xf1, 0xe2, 0x28, 0xce, 0x9e, 0x26, 0x66, 0xdf, 0x19, 0x93, 0xea, 0x51,
- 0x51, 0x4f, 0x49, 0x70, 0xc2, 0x77, 0x0d, 0x28, 0xe2, 0x91, 0xf1, 0xf0, 0xe3, 0x54, 0x71, 0x42,
- 0x4b, 0xa7, 0xd1, 0x91, 0x15, 0x0e, 0x4e, 0x3c, 0x6f, 0x13, 0xd5, 0xc9, 0xae, 0xd4, 0x38, 0xef,
- 0xb1, 0x9d, 0x71, 0x58, 0x44, 0xa8, 0xdf, 0xd3, 0x2e, 0x7e, 0x2d, 0x59, 0xc2, 0x4f, 0x07, 0x6c,
- 0xc1, 0xc0, 0x5e, 0xcd, 0x14, 0x49, 0x88, 0x58, 0xc3, 0xa7, 0x55, 0x06, 0xed, 0x40, 0xab, 0xfc,
- 0x31, 0x71, 0xf3, 0x21, 0xad, 0xf4, 0xe9, 0x56, 0x59, 0x16, 0xc2, 0x19, 0xf9, 0x69, 0x67, 0x2c,
- 0xfa, 0xff, 0x36, 0x40, 0x79, 0x9c, 0x8f, 0xf7, 0xd8, 0xae, 0x03, 0x0b, 0x4b, 0x90, 0xad, 0x46,
- 0xbb, 0x90, 0x17, 0xad, 0xfb, 0xd8, 0xed, 0x87, 0xa8, 0xad, 0x9b, 0x20, 0x2d, 0xc0, 0x1f, 0x87,
- 0xe3, 0x8c, 0x7a, 0x34, 0x36, 0xc1, 0x33, 0x66, 0xad, 0x37, 0xd9, 0x94, 0xe0, 0x82, 0xbd, 0xca,
- 0xa9, 0xf5, 0xcc, 0xc0, 0xf5, 0x9a, 0xbf, 0xfa, 0x1b, 0x92, 0x39, 0x94, 0x29, 0x58, 0xd3, 0x87,
- 0x7c, 0x02, 0x54, 0xe0, 0x07, 0xbc, 0x3a, 0xb9, 0xd4, 0x16, 0x5a, 0x66, 0x96, 0x45, 0xe8, 0xed,
- 0x20, 0x2e, 0xf3, 0x60, 0x3e, 0x28, 0x1c, 0xfb, 0xd9, 0x20, 0xf2, 0x6b, 0x8c, 0x3b, 0x3e, 0x19,
- 0x3d, 0x3a, 0xad, 0xe5, 0xe6, 0x3d, 0x14, 0x04, 0x46, 0x39, 0xef, 0xba, 0x6f, 0x90, 0x9c, 0x3a,
- 0x2d, 0x34, 0x80, 0xbb, 0x8a, 0xbe, 0xe2, 0xd0, 0x9e, 0x06, 0xfb, 0xc8, 0xd6, 0x10, 0x19, 0xd3,
- 0x16, 0xd0, 0x3e, 0xa9, 0x7a, 0x54, 0xec, 0xa4, 0x11, 0x61, 0xbb, 0xc1, 0x16, 0x30, 0xa5, 0xe8,
- 0x70, 0xfb, 0x7d, 0xaf, 0x16, 0x36, 0x4e, 0xd7, 0x90, 0x2e, 0xc3, 0x80, 0x4b, 0xa0, 0xf0, 0x64,
- 0x4b, 0xa2, 0x6f, 0x19, 0x1a, 0x8a, 0x53, 0x86, 0xf5, 0x58, 0x81, 0xe1, 0x85, 0xc6, 0xe0, 0x7e,
- 0x1e, 0xf0, 0x53, 0x45, 0x52, 0x08, 0xbc, 0x42, 0xc2, 0x99, 0x4b, 0xc8, 0x7f, 0xbe, 0xb6, 0xdc,
- 0x80, 0xd9, 0xe7, 0x4d, 0x4f, 0x29, 0x24, 0xca, 0x5f, 0x32, 0xf7, 0x65, 0xad, 0x66, 0xf6, 0x24,
- 0x7e, 0x91, 0xae, 0xbc, 0xfb, 0xea, 0x8b, 0x1a, 0x8a, 0x37, 0xc2, 0x47, 0x4f, 0xe9, 0xdd, 0xcd,
- 0x4b, 0x10, 0x23, 0x7b, 0xee, 0x0f, 0x54, 0x09, 0x77, 0xd3, 0x67, 0xe1, 0x54, 0x20, 0x51, 0x2b,
- 0xfa, 0xc7, 0x9a, 0xec, 0xfe, 0x28, 0x1c, 0xc7, 0x96, 0x75, 0x8c, 0x6d, 0x07, 0xf5, 0xa2, 0xb9,
- 0x55, 0x74, 0xd1, 0x43, 0x5e, 0x52, 0x6c, 0xfb, 0xf1, 0xcb, 0x4a, 0x47, 0x2a, 0xe8, 0xf9, 0x5e,
- 0x89, 0x43, 0x51, 0x3c, 0x3e, 0xe1, 0xd2, 0xa4, 0x6e, 0xe2, 0x3f, 0x4c, 0x52, 0x17, 0x93, 0xd1,
- 0x2e, 0x63, 0xd4, 0x4e, 0x59, 0xd6, 0x9f, 0xa8, 0x9d, 0x2e, 0x04, 0x76, 0x06, 0x40, 0x9f, 0xe4,
- 0xc8, 0x11, 0xcb, 0x78, 0xf3, 0xf5, 0x66, 0xd9, 0xce, 0xe7, 0x1f, 0x43, 0x93, 0x7a, 0xca, 0xe5,
- 0x6d, 0x00, 0xfc, 0x18, 0xf6, 0xc4, 0xe3, 0x92, 0x2d, 0x46, 0xd4, 0x95, 0x70, 0x95, 0xae, 0x70,
- 0x8a, 0x78, 0xf4, 0x94, 0x74, 0x8f, 0x39, 0x8e, 0x7e, 0xdd, 0xc7, 0x69, 0x1a, 0x55, 0x77, 0xde,
- 0xff, 0xbb, 0x9a, 0x86, 0x43, 0x19, 0x78, 0xca, 0xbd, 0xff, 0x26, 0x88, 0xd9, 0xf7, 0x9f, 0x01,
- 0x37, 0xc4, 0x5c, 0xfc, 0xe6, 0x3f, 0x02, 0x01, 0x94, 0x90, 0xa4, 0xd2, 0xa2, 0xb4, 0xc0, 0x1a,
- 0xe5, 0x2e, 0xcf, 0x3a, 0x2e, 0x20, 0xb5, 0x40, 0xf7, 0x93, 0x82, 0x41, 0x9e, 0xfc, 0xeb, 0x02,
- 0xc6, 0x92, 0x07, 0xdb, 0x07, 0x3e, 0xe7, 0x8f, 0x9d, 0x2d, 0xff, 0x6d, 0x5f, 0x20, 0xee, 0x61,
- 0x15, 0xd8, 0xc1, 0xcc, 0xf0, 0x43, 0xdc, 0xe6, 0x70, 0xfd, 0x63, 0x76, 0xae, 0x09, 0xcb, 0x4d,
- 0x0a, 0x2c, 0x3c, 0x9f, 0xfe, 0xca, 0xb2, 0x5f, 0x1d, 0x37, 0xe9, 0x52, 0xcd, 0x90, 0x79, 0x45,
- 0x0f, 0x87, 0x3a, 0xb4, 0xd7, 0x90, 0xdd, 0x3e, 0x94, 0xf9, 0x51, 0x75, 0xdc, 0xff, 0xd9, 0xec,
- 0x4b, 0x6f, 0x61, 0x4d, 0xcb, 0x88, 0xf6, 0xaa, 0x78, 0xb1, 0xa1, 0xd4, 0xb1, 0xa6, 0x41, 0xdf,
- 0x96, 0xef, 0x16, 0x31, 0x49, 0x58, 0x7b, 0xdc, 0x94, 0x18, 0x8d, 0x15, 0xad, 0xff, 0x81, 0xa9,
- 0x66, 0x22, 0x12, 0x84, 0x9e, 0x59, 0xd3, 0x13, 0xcb, 0xad, 0x27, 0x3b, 0xbe, 0x2b, 0x2b, 0xaf,
- 0x2e, 0xfe, 0x6f, 0x73, 0x5f, 0x8c, 0xd2, 0x83, 0x5d, 0x60, 0xbc, 0x3b, 0xf5, 0x77, 0xdc, 0xe4,
- 0x03, 0xbe, 0xce, 0x8b, 0xf4, 0x28, 0x56, 0x53, 0x20, 0x2d, 0x7c, 0x8e, 0x66, 0x69, 0x4b, 0x12,
- 0xc4, 0x6e, 0xff, 0x6b, 0x6a, 0x0e, 0xba, 0x0a, 0x99, 0x43, 0xe3, 0x74, 0xf0, 0xe8, 0x5d, 0x3c,
- 0x32, 0x01, 0x3d, 0xf4, 0x96, 0xcd, 0x37, 0x69, 0xd3, 0x86, 0x71, 0xce, 0x58, 0xd9, 0xf2, 0x3d,
- 0xd8, 0x1b, 0xa0, 0x27, 0xcd, 0xd7, 0xb1, 0xcf, 0xac, 0xf1, 0x1f, 0x00, 0x8a, 0x84, 0x57, 0x1c,
- 0x47, 0xac, 0x31, 0x14, 0xf7, 0x06, 0x86, 0xcc, 0x4e, 0x00, 0x3e, 0x5b, 0xdf, 0x87, 0xe7, 0x98,
- 0x26, 0xd6, 0x90, 0xd5, 0x89, 0xa0, 0xcb, 0xa9, 0x58, 0x60, 0xfb, 0xd5, 0xc8, 0x1c, 0x85, 0x54,
- 0x5b, 0xf7, 0x2c, 0xde, 0xd9, 0x3c, 0xd1, 0xca, 0xfb, 0xc2, 0x71, 0x51, 0xe7, 0x91, 0xb0, 0x6d,
- 0x65, 0xea, 0x84, 0xd1, 0x3b, 0x4b, 0xb0, 0xd4, 0x2e, 0xe5, 0xc8, 0xcc, 0x4a, 0x0e, 0xc1, 0x73,
- 0x4d, 0x3b, 0x55, 0xfc, 0x96, 0xeb, 0xfa, 0x79, 0xd2, 0xe9, 0xe3, 0xfa, 0xef, 0x2c, 0x6f, 0xbf,
- 0x1a, 0x27, 0x4d, 0x3e, 0x35, 0x3a, 0x76, 0xbe, 0xde, 0xe7, 0x4a, 0x00, 0x5e, 0xf9, 0x7b, 0xcf,
- 0xb4, 0x17, 0x1e, 0xc6, 0x67, 0x5e, 0xb1, 0x65, 0xb5, 0x49, 0xba, 0xdc, 0xd3, 0x39, 0x7d, 0xab,
- 0x47, 0x42, 0x0a, 0xfa, 0x73, 0xb4, 0x25, 0x41, 0xbc, 0xb4, 0xfe, 0x38, 0xd1, 0xed, 0xc6, 0x64,
- 0x96, 0xe6, 0x61, 0x41, 0xfd, 0xfc, 0x6f, 0xd0, 0x03, 0xe9, 0x2d, 0x02, 0x06, 0xdc, 0x67, 0xf4,
- 0xbf, 0x8a, 0xaf, 0x0d, 0x47, 0x66, 0x77, 0xed, 0x12, 0x4c, 0x85, 0x23, 0xf7, 0xc4, 0x91, 0x8a,
- 0x9a, 0x18, 0xd2, 0x38, 0x8f, 0x16, 0xb4, 0xe5, 0xc1, 0xff, 0x72, 0xa6, 0x05, 0x3a, 0xa0, 0x30,
- 0x83, 0x78, 0x2f, 0xe4, 0x68, 0xbd, 0xbe, 0x6e, 0xce, 0x11, 0x82, 0x3c, 0x43, 0x66, 0xa0, 0xf4,
- 0x25, 0x59, 0xdd, 0xd5, 0x85, 0xd6, 0x0a, 0xdc, 0x0a, 0x51, 0x3c, 0xe7, 0xb4, 0x66, 0x87, 0xfe,
- 0x69, 0x75, 0xc1, 0x33, 0x5b, 0xce, 0x89, 0x76, 0xa8, 0x51, 0xd2, 0x6d, 0x6f, 0x07, 0x88, 0x7f,
- 0xe0, 0xfa, 0xbf, 0x1b, 0x00, 0x64, 0x19, 0xc1, 0x48, 0x35, 0x6f, 0x8d, 0x64, 0x9e, 0xc1, 0x5d,
- 0xee, 0x1b, 0xa7, 0xf3, 0xcd, 0xff, 0x40, 0x1a, 0xac, 0xd0, 0xc9, 0x76, 0xfe, 0xdf, 0xca, 0x49,
- 0x9b, 0xb0, 0xdd, 0x2f, 0x7d, 0x1f, 0x3c, 0x7c, 0x85, 0xf9, 0x49, 0x9c, 0x01, 0x28, 0x1c, 0xfe,
- 0x73, 0x5c, 0xc7, 0x3c, 0xa0, 0xeb, 0xd8, 0xc6, 0x2b, 0x80, 0xe7, 0x66, 0x57, 0xa2, 0x2c, 0xd1,
- 0x5c, 0x34, 0x3e, 0x66, 0xeb, 0xee, 0xca, 0x78, 0x4f, 0x96, 0xeb, 0x00, 0x5c, 0x42, 0x21, 0x7f,
- 0x9e, 0xee, 0xdd, 0xca, 0x5f, 0x4f, 0x46, 0x6c, 0x68, 0x5f, 0xbf, 0x6e, 0xa7, 0x38, 0x9b, 0x3a,
- 0xa1, 0xfd, 0xf8, 0xdd, 0xa1, 0x66, 0x12, 0x36, 0x3c, 0x81, 0xc5, 0x80, 0x9b, 0xf2, 0x52, 0x0e,
- 0xac, 0xf4, 0xbc, 0xc2, 0x6d, 0x48, 0x0c, 0x90, 0x41, 0xab, 0xa8, 0xce, 0xdd, 0x72, 0x3a, 0x59,
- 0x3a, 0x5c, 0xd4, 0xff, 0x76, 0xef, 0x05, 0x8e, 0x33, 0xf9, 0x63, 0x5c, 0x32, 0x52, 0x8a, 0xf0,
- 0xd3, 0x09, 0x77, 0x02, 0x34, 0x25, 0x23, 0x3c, 0x90, 0x01, 0x74, 0xdc, 0x6e, 0x78, 0x58, 0x90,
- 0x63, 0x4b, 0x8d, 0x38, 0x7a, 0x4a, 0x3f, 0x19, 0x4f, 0xfb, 0xdb, 0x31, 0x2c, 0xac, 0xd9, 0x84,
- 0x4d, 0x27, 0x4f, 0x9b, 0xdc, 0x97, 0xdd, 0xae, 0x6a, 0x97, 0xf3, 0x9e, 0xe6, 0xf2, 0xf9, 0x68,
- 0x68, 0xd1, 0x68, 0x4e, 0x1b, 0x78, 0xdd, 0xa6, 0xec, 0xf2, 0xe0, 0xf2, 0xa0, 0xc2, 0x74, 0xff,
- 0x62, 0xdd, 0xdf, 0xa0, 0x56, 0x86, 0x09, 0x89, 0x4b, 0x14, 0x61, 0x9a, 0x5a, 0x08, 0x14, 0xb2,
- 0xad, 0x6e, 0x5e, 0x4b, 0x55, 0x95, 0x11, 0x21, 0x8f, 0xbb, 0x01, 0xe7, 0x76, 0x18, 0x7a, 0x88,
- 0x0d, 0x36, 0xa4, 0x84, 0x0d, 0xbd, 0xa9, 0x1f, 0xf4, 0x78, 0x82, 0x72, 0xc2, 0x0c, 0x4c, 0xa2,
- 0x9b, 0x9a, 0xbe, 0xf7, 0x8e, 0xc4, 0xf1, 0xe3, 0xfe, 0xf8, 0x1a, 0x8f, 0xb8, 0xca, 0x2f, 0xb3,
- 0xf3, 0xb3, 0xc7, 0xfd, 0x05, 0x30, 0x1a, 0xc9, 0x03, 0x0c, 0xe2, 0x9e, 0xa3, 0x86, 0x45, 0x20,
- 0x78, 0x3a, 0xa4, 0xd6, 0xfb, 0xd7, 0xda, 0xe0, 0x1c, 0xe9, 0x85, 0x42, 0xa5, 0xab, 0xdf, 0x69,
- 0x8e, 0x45, 0xe6, 0x67, 0x0f, 0xc9, 0xd0, 0x20, 0xfd, 0xf5, 0x84, 0x00, 0xd3, 0x9c, 0xb9, 0x08,
- 0xe9, 0x75, 0xfe, 0xe9, 0x69, 0x79, 0x08, 0xb9, 0xc1, 0x3c, 0x46, 0x87, 0x02, 0xfc, 0x72, 0x65,
- 0x22, 0x2a, 0x76, 0x59, 0xcb, 0xd0, 0x70, 0xcf, 0xc7, 0xae, 0xd2, 0x34, 0x1d, 0x43, 0x8d, 0x47,
- 0x76, 0x10, 0x73, 0xf1, 0x84, 0x4c, 0x8d, 0x61, 0x5b, 0x42, 0x96, 0xdd, 0xa9, 0x1e, 0x47, 0x68,
- 0x22, 0xca, 0x3f, 0xfe, 0xb4, 0xfe, 0x80, 0xec, 0xcb, 0x1e, 0xa3, 0xbf, 0x77, 0x84, 0x04, 0x72,
- 0x48, 0x7a, 0xcf, 0x0a, 0xda, 0xe8, 0x24, 0xab, 0x58, 0x79, 0x3a, 0x9f, 0x33, 0x02, 0x82, 0xe7,
- 0x38, 0xe9, 0x31, 0x2e, 0x7a, 0x65, 0x25, 0x70, 0xfc, 0xe6, 0x93, 0x94, 0xf4, 0xfa, 0x20, 0x2a,
- 0xaa, 0x64, 0x85, 0xf7, 0xac, 0x7f, 0xdc, 0xc0, 0x0b, 0xa4, 0x34, 0x94, 0x33, 0xd9, 0x35, 0x35,
- 0x4c, 0x84, 0x55, 0x87, 0x7b, 0xa3, 0xb8, 0x55, 0x26, 0xec, 0x1d, 0x8e, 0xf6, 0x5d, 0x0b, 0x52,
- 0x37, 0x29, 0x69, 0x18, 0x2d, 0xcf, 0x37, 0xf9, 0x9d, 0x3d, 0x85, 0x4a, 0x81, 0xab, 0xd0, 0x2b,
- 0x2a, 0x0a, 0x8e, 0x17, 0xf9, 0x91, 0xfe, 0x91, 0x07, 0xfd, 0xe6, 0x2a, 0x07, 0xa1, 0x53, 0x06,
- 0xdf, 0x8f, 0x90, 0xb4, 0xbd, 0xfe, 0x8b, 0x93, 0xd8, 0xa2, 0x4c, 0x6a, 0xba, 0x0a, 0x6d, 0x09,
- 0x93, 0xb3, 0xaf, 0xd5, 0x5a, 0xad, 0xac, 0x97, 0x03, 0x1d, 0xea, 0x00, 0x1a, 0x60, 0x24, 0x6a,
- 0x5d, 0xcb, 0xa3, 0xd9, 0xd7, 0x67, 0xb3, 0xea, 0x21, 0x49, 0xc7, 0x14, 0x5a, 0x43, 0x68, 0xa6,
- 0x2e, 0xd7, 0xbf, 0x42, 0x95, 0x4c, 0x2e, 0xa6, 0x9e, 0xac, 0xf6, 0xf6, 0xb2, 0xb7, 0xe6, 0xa9,
- 0x3c, 0x7d, 0xd6, 0x74, 0x31, 0x7b, 0x9c, 0xab, 0x31, 0x33, 0xfc, 0xce, 0x39, 0x9b, 0x28, 0xd6,
- 0xd2, 0x97, 0x6c, 0xb4, 0xb4, 0x16, 0xd1, 0x9d, 0xff, 0x17, 0x0b, 0x49, 0x33, 0xec, 0x74, 0x49,
- 0x44, 0xa5, 0xa1, 0x24, 0x9a, 0x34, 0x77, 0x50, 0x2c, 0x4a, 0x25, 0x40, 0x64, 0xb3, 0x1a, 0x50,
- 0x0d, 0x0b, 0x1e, 0xca, 0xb5, 0x55, 0x68, 0x84, 0x9c, 0x4f, 0xdc, 0x68, 0xea, 0x9b, 0x58, 0x9a,
- 0x8d, 0x73, 0x9e, 0x82, 0xff, 0x39, 0xca, 0x76, 0x57, 0x7a, 0x7d, 0x3a, 0x71, 0x8c, 0x61, 0x5e,
- 0x20, 0x03, 0x58, 0xd5, 0x9f, 0x75, 0x1a, 0xec, 0xfb, 0x00, 0x81, 0x38, 0xdf, 0x0e, 0x43, 0x80,
- 0x05, 0xe0, 0xc9, 0xa0, 0xec, 0xe2, 0x6a, 0x5d, 0xbc, 0x46, 0xb4, 0xce, 0xf2, 0xdc, 0x3e, 0x99,
- 0x32, 0xd1, 0x3e, 0xf6, 0xd7, 0x88, 0x1f, 0xb8, 0x6a, 0x10, 0x2e, 0x7a, 0xd1, 0x51, 0xcb, 0xe4,
- 0x72, 0xd8, 0x12, 0x5d, 0x81, 0xf8, 0x66, 0x76, 0x94, 0x9f, 0x15, 0xce, 0x62, 0xa6, 0x63, 0x15,
- 0x85, 0x89, 0x6c, 0xbb, 0x18, 0x5d, 0xdf, 0x67, 0xdc, 0xc6, 0x23, 0xae, 0xb9, 0xa6, 0x0b, 0x65,
- 0xf4, 0xb0, 0xd6, 0x16, 0xf4, 0xae, 0xbe, 0x03, 0x04, 0xc6, 0xfa, 0x2a, 0x67, 0x07, 0x53, 0x0d,
- 0xb3, 0x9b, 0x73, 0x59, 0xa5, 0x17, 0x0c, 0x0b, 0x15, 0x25, 0xda, 0x3f, 0xe1, 0x89, 0x89, 0x09,
- 0xe6, 0x50, 0xec, 0x38, 0xc5, 0x4e, 0xae, 0xbd, 0xe7, 0x09, 0x7a, 0xc5, 0x3a, 0x09, 0xa5, 0xac,
- 0x22, 0x78, 0xca, 0x7b, 0xca, 0xe0, 0xee, 0x74, 0x61, 0xdb, 0xf5, 0xaf, 0xfb, 0x31, 0x08, 0x84,
- 0xb7, 0x63, 0xa6, 0x25, 0xc2, 0x0f, 0x2a, 0x6d, 0xf4, 0x4c, 0xf4, 0xae, 0x71, 0xe5, 0x9b, 0x1f,
- 0xd5, 0x1b, 0x76, 0x7b, 0xc7, 0xa1, 0x84, 0xdb, 0xa6, 0x4a, 0x82, 0xbe, 0x0c, 0x5d, 0xb4, 0x3a,
- 0x81, 0xb8, 0x75, 0x76, 0x72, 0xd8, 0xd4, 0x51, 0x86, 0x90, 0x28, 0x0f, 0xe6, 0xc8, 0xe3, 0xc3,
- 0xaf, 0x92, 0xa8, 0x36, 0xb2, 0x17, 0x65, 0x27, 0x87, 0xca, 0xe5, 0xdd, 0xea, 0x9a, 0x56, 0xaf,
- 0xf3, 0x1b, 0xa6, 0xd3, 0xbc, 0xb1, 0x60, 0xb4, 0x1c, 0xd1, 0xff, 0x6f, 0x25, 0x3e, 0x4d, 0x62,
- 0x14, 0x25, 0x27, 0xbd, 0x41, 0x76, 0xea, 0xeb, 0xb0, 0x01, 0xaa, 0xce, 0x4f, 0xe4, 0xd9, 0x0c,
- 0x6e, 0x4d, 0xe8, 0x83, 0x19, 0xf3, 0x34, 0x65, 0x47, 0x4b, 0x74, 0x91, 0x6b, 0xac, 0xcc, 0x2c,
- 0xe3, 0x6e, 0xef, 0x22, 0x74, 0x29, 0x9a, 0xc9, 0xe3, 0x58, 0xfa, 0xe0, 0x92, 0x0e, 0x65, 0x74,
- 0x58, 0x98, 0x2f, 0x61, 0x72, 0x29, 0xd3, 0x2e, 0x6d, 0x72, 0x5b, 0xc4, 0x45, 0x15, 0xd9, 0xca,
- 0xfe, 0x35, 0x3c, 0xf0, 0x18, 0xfc, 0xa5, 0xa9, 0x56, 0x4d, 0x80, 0xc9, 0xcd, 0xb5, 0x2c, 0x7c,
- 0x02, 0xff, 0x22, 0x4a, 0x1b, 0xef, 0x03, 0xe6, 0xd8, 0xfd, 0x68, 0x9d, 0x32, 0xdc, 0x92, 0x9f,
- 0x83, 0xef, 0xfb, 0xcc, 0xad, 0xfa, 0x27, 0x40, 0x2f, 0x17, 0x70, 0x5c, 0x0b, 0x78, 0xac, 0x5f,
- 0x9f, 0x72, 0xdb, 0x02, 0x24, 0xe6, 0x15, 0x1c, 0x35, 0xa3, 0xff, 0xff, 0x5c, 0xaf, 0x2e, 0x80,
- 0x03, 0x6f, 0x1f, 0x68, 0x35, 0x5d, 0x5a, 0xf3, 0x9e, 0x1e, 0xa5, 0x72, 0x50, 0x45, 0x43, 0x4e,
- 0x4a, 0x1e, 0x7f, 0x29, 0x39, 0xf7, 0xa8, 0x6d, 0x44, 0x40, 0x7e, 0x09, 0x53, 0x25, 0xb8, 0x82,
- 0xec, 0xa6, 0x79, 0x73, 0xf2, 0x9c, 0x57, 0xd8, 0xd6, 0x1b, 0x80, 0x84, 0x63, 0x47, 0xcb, 0xa8,
- 0x76, 0xd4, 0x4f, 0x18, 0xeb, 0xa0, 0xc8, 0xdd, 0xb4, 0x1d, 0xc5, 0xb0, 0x4d, 0x11, 0xaa, 0xdc,
- 0x94, 0x73, 0xf9, 0x33, 0x68, 0x43, 0x77, 0x71, 0x08, 0xde, 0xa1, 0x80, 0xeb, 0x42, 0xad, 0x44,
- 0x34, 0xf3, 0x13, 0x05, 0x7c, 0x1c, 0x9c, 0x34, 0xc6, 0xb5, 0x8f, 0xe7, 0xb3, 0xf8, 0x75, 0x0a,
- 0x28, 0x8b, 0x6b, 0x5f, 0xc8, 0xd5, 0x4e, 0x40, 0xfc, 0xc1, 0x20, 0xf4, 0xe9, 0x90, 0x74, 0x4c,
- 0x84, 0x4b, 0x10, 0xd8, 0x6f, 0xbf, 0xc7, 0x3c, 0xab, 0x3f, 0xec, 0xa2, 0xbf, 0x09, 0xf4, 0xf4,
- 0x35, 0xaa, 0xbb, 0x02, 0x21, 0x86, 0x83, 0xc6, 0x06, 0x9c, 0x10, 0x5c, 0x65, 0xc6, 0x06, 0x7a,
- 0xa7, 0xd5, 0x71, 0x2d, 0x5b, 0xc4, 0xdf, 0x70, 0xe3, 0x46, 0x81, 0x2c, 0x98, 0xd0, 0xb3, 0x72,
- 0x9c, 0xe4, 0xfd, 0xec, 0x69, 0x49, 0x57, 0x9c, 0xf0, 0x49, 0x55, 0x31, 0x19, 0xaa, 0xf7, 0xc8,
- 0x53, 0xe5, 0xb6, 0xc4, 0xd7, 0x3c, 0xab, 0xc7, 0x98, 0x4b, 0x63, 0x3b, 0xd6, 0x7f, 0x98, 0xef,
- 0x1e, 0x0d, 0xa8, 0xaa, 0xca, 0x79, 0xb4, 0xb0, 0x89, 0x50, 0xbf, 0x6f, 0x42, 0x9b, 0x16, 0x66,
- 0x86, 0xf6, 0x6a, 0x4a, 0x64, 0x9b, 0x1a, 0x9d, 0x33, 0x17, 0x2e, 0x4e, 0xdc, 0xa2, 0x7a, 0xfa,
- 0x17, 0xca, 0x33, 0x9e, 0xe7, 0xdd, 0x0c, 0x13, 0x3b, 0xf2, 0xc9, 0x8d, 0xc6, 0xae, 0x2d, 0x6f,
- 0x3e, 0xdc, 0xcb, 0x7f, 0xdd, 0xf0, 0x1e, 0x1b, 0xa3, 0xc7, 0x8f, 0x61, 0x94, 0xfb, 0x8c, 0xdf,
- 0xce, 0x5a, 0xac, 0x2b, 0x40, 0x98, 0x55, 0x93, 0xe8, 0xb5, 0x2a, 0x4c, 0xa0, 0x20, 0x00, 0x36,
- 0x2f, 0x17, 0x7f, 0x63, 0x48, 0xf6, 0xbc, 0x3b, 0xc2, 0x20, 0x17, 0x1a, 0x56, 0x3d, 0x68, 0x6d,
- 0xd7, 0x75, 0xd1, 0x9b, 0xf1, 0x62, 0x2d, 0xf9, 0x98, 0xe8, 0x7f, 0xf8, 0x63, 0xf8, 0x9f, 0x3c,
- 0x76, 0xd4, 0x91, 0x1a, 0x9b, 0x73, 0x30, 0xd8, 0xf6, 0xf5, 0x58, 0xac, 0xb4, 0x29, 0xda, 0xa1,
- 0x66, 0xfe, 0x1f, 0x49, 0x0f, 0x66, 0xa1, 0x4f, 0x31, 0x3b, 0x65, 0x93, 0xf8, 0x19, 0x2d, 0xe0,
- 0x8b, 0x79, 0xcf, 0x4a, 0x20, 0x2c, 0x52, 0x61, 0x37, 0x7c, 0xae, 0x8a, 0x52, 0xd4, 0x66, 0x50,
- 0xa7, 0xd9, 0x20, 0x96, 0x3f, 0xa5, 0x17, 0x31, 0x93, 0x29, 0xbc, 0xdb, 0x18, 0x6f, 0xdb, 0xc6,
- 0x0a, 0xa6, 0xb0, 0x0d, 0x41, 0xc1, 0x37, 0xab, 0x1e, 0xa4, 0x75, 0xe7, 0x33, 0x9d, 0x1a, 0x90,
- 0x29, 0x6e, 0x4e, 0x85, 0x57, 0x4b, 0x64, 0x0d, 0x7e, 0x98, 0x19, 0xa8, 0x1a, 0x84, 0xc9, 0x2b,
- 0xac, 0x83, 0x66, 0x28, 0x09, 0x2c, 0x8e, 0x16, 0x91, 0x13, 0xf5, 0x1a, 0x5e, 0xcc, 0xc7, 0x60,
- 0xfb, 0xea, 0x8f, 0xa5, 0x77, 0xf4, 0xa3, 0x31, 0xb8, 0x5f, 0x7a, 0x0a, 0xd7, 0x19, 0x13, 0x17,
- 0x5c, 0xc3, 0x64, 0x21, 0xba, 0x27, 0xef, 0xc9, 0xf9, 0xab, 0x51, 0x8d, 0x5a, 0x44, 0x4c, 0x79,
- 0x34, 0x05, 0xe0, 0xf7, 0x5b, 0xc8, 0x8e, 0xe7, 0xcf, 0x91, 0xe9, 0x35, 0x75, 0x0b, 0xc5, 0x5b,
- 0xad, 0xbd, 0x2e, 0xe6, 0xe2, 0x42, 0x70, 0x3d, 0x6d, 0xc4, 0x4b, 0xe1, 0x9c, 0x9c, 0x22, 0x9b,
- 0x9e, 0x85, 0x66, 0x85, 0x81, 0xf7, 0x3e, 0xf5, 0x59, 0x79, 0x6d, 0x2e, 0xc8, 0x80, 0x12, 0xd5,
- 0x53, 0xc7, 0x56, 0x61, 0xb2, 0xf9, 0x94, 0x86, 0xe3, 0xfd, 0x2b, 0x99, 0xdc, 0xeb, 0xb8, 0xeb,
- 0x73, 0xe0, 0xd7, 0xe2, 0xdc, 0xe8, 0x5d, 0x9e, 0x13, 0x5f, 0x66, 0x4e, 0x89, 0x4b, 0x41, 0x3d,
- 0xdf, 0xb8, 0x70, 0xe6, 0xce, 0xb3, 0x54, 0x91, 0xec, 0x53, 0x97, 0x6c, 0x01, 0xb2, 0xc8, 0x89,
- 0x9d, 0xad, 0x24, 0xfc, 0x58, 0x63, 0xc8, 0x4b, 0x39, 0xfb, 0xe4, 0x6a, 0x76, 0x9c, 0x11, 0x06,
- 0x37, 0x73, 0xc0, 0x35, 0x9a, 0x36, 0x62, 0x70, 0xe9, 0xb6, 0xc6, 0x9f, 0x53, 0xcf, 0x5d, 0x39,
- 0x13, 0x48, 0x49, 0x5c, 0xbb, 0xfd, 0x05, 0x2f, 0xb5, 0x00, 0x16, 0xe6, 0x59, 0x8c, 0x05, 0x86,
- 0xaf, 0x25, 0xe5, 0x4d, 0x64, 0x6f, 0x73, 0x6b, 0x8e, 0xad, 0x06, 0x37, 0x03, 0xaa, 0xa9, 0x0e,
- 0x39, 0x73, 0xac, 0xdd, 0x52, 0x5c, 0xea, 0x1e, 0x07, 0x6a, 0x7a, 0x58, 0x32, 0x84, 0xbb, 0x78,
- 0xa4, 0xa9, 0x7c, 0xfa, 0xcc, 0xa8, 0xa0, 0x10, 0xcf, 0x8c, 0xbd, 0x36, 0x34, 0x03, 0x6d, 0xe8,
- 0xba, 0xd5, 0x17, 0x88, 0x51, 0xb1, 0x8f, 0xd8, 0x8d, 0x4a, 0xa4, 0xf8, 0x19, 0xb6, 0x69, 0x68,
- 0xa8, 0x03, 0x89, 0x18, 0x99, 0xdb, 0x82, 0xd9, 0x78, 0x97, 0x6e, 0x31, 0xcb, 0xc3, 0x18, 0x8b,
- 0xc9, 0x2a, 0x3c, 0x4d, 0x64, 0x95, 0x88, 0x86, 0x4a, 0xca, 0xc3, 0xa5, 0x9a, 0x9b, 0xf4, 0xcf,
- 0x73, 0x0a, 0xb2, 0xd8, 0x33, 0x5a, 0x02, 0x84, 0xaa, 0xdd, 0x4f, 0xc6, 0xdf, 0x68, 0xca, 0xe0,
- 0x29, 0x73, 0x30, 0xd0, 0xe6, 0x9e, 0x5a, 0xb6, 0xb4, 0x4f, 0x09, 0xa8, 0x19, 0x3f, 0x90, 0xba,
- 0x73, 0x8c, 0xa5, 0xb8, 0x7d, 0xc4, 0x82, 0xb5, 0xfa, 0x3c, 0x00, 0x1b, 0xac, 0x94, 0x28, 0x89,
- 0x43, 0x0d, 0xbd, 0x88, 0x9d, 0xc7, 0xe4, 0xd9, 0xdc, 0x62, 0x8a, 0x5d, 0x39, 0x45, 0xa1, 0x12,
- 0xc9, 0xb0, 0x2f, 0x53, 0xf6, 0xd9, 0xee, 0xd6, 0x7a, 0xcf, 0x2f, 0xab, 0xdb, 0xa3, 0xec, 0x4a,
- 0x69, 0xa3, 0x77, 0x73, 0x84, 0x9f, 0x4b, 0x27, 0xfc, 0x01, 0xe1, 0x95, 0x92, 0xc7, 0x0c, 0x88,
- 0x88, 0xaa, 0x6f, 0xcf, 0x75, 0xd7, 0x1f, 0xb5, 0xb5, 0xaf, 0xca, 0x77, 0x28, 0x6e, 0xa8, 0xd1,
- 0x06, 0x25, 0x04, 0x32, 0xe9, 0x47, 0x28, 0x35, 0xab, 0xaf, 0x7b, 0x0b, 0x24, 0x0f, 0xbf, 0x58,
- 0xde, 0xb8, 0x24, 0x12, 0xeb, 0x74, 0xf9, 0x40, 0xc6, 0xcd, 0x24, 0x2d, 0x62, 0x7b, 0xbf, 0x35,
- 0x76, 0xf2, 0x6a, 0x62, 0xe2, 0x5a, 0x25, 0x13, 0x63, 0x52, 0x4d, 0x28, 0x55, 0x59, 0x6e, 0x14,
- 0x5c, 0x77, 0x0d, 0x39, 0xfd, 0x5d, 0xbe, 0xe4, 0x0f, 0x51, 0x2a, 0xc1, 0xe2, 0x04, 0x9a, 0x83,
- 0x6f, 0x78, 0x4b, 0x44, 0x70, 0xc2, 0x4b, 0x97, 0xae, 0xfe, 0x87, 0x85, 0xc0, 0xb8, 0x82, 0x95,
- 0xc3, 0x8e, 0x2a, 0x63, 0x05, 0x1a, 0x30, 0x9f, 0xcd, 0x95, 0x66, 0xc0, 0x1d, 0x37, 0x80, 0x41,
- 0x61, 0xe7, 0xea, 0xb8, 0x37, 0x61, 0x9b, 0x4b, 0xe8, 0xec, 0x01, 0x48, 0x3f, 0xbd, 0xfb, 0x3a,
- 0x0d, 0x7a, 0x2c, 0x5c, 0x27, 0xed, 0x8e, 0x14, 0xa1, 0x43, 0xd7, 0x22, 0x5e, 0xe4, 0x76, 0xe0,
- 0x78, 0xb3, 0x09, 0xeb, 0xf3, 0x10, 0xcf, 0x60, 0x9a, 0x88, 0xb0, 0xaa, 0xa8, 0x87, 0x0a, 0xf5,
- 0xd6, 0xf5, 0x42, 0xbc, 0x82, 0x89, 0x55, 0xd1, 0x03, 0x98, 0xa6, 0x47, 0x76, 0x03, 0x62, 0x5d,
- 0x19, 0xa5, 0x21, 0x99, 0x46, 0x12, 0x5d, 0x26, 0x17, 0xc4, 0xbe, 0x3c, 0x86, 0xac, 0xe3, 0x17,
- 0xc7, 0xf5, 0x5d, 0x88, 0x0f, 0x45, 0x0b, 0xf2, 0x71, 0x31, 0xe3, 0x7b, 0x15, 0xc1, 0x98, 0x51,
- 0xb0, 0xd2, 0xe3, 0x78, 0x50, 0x3d, 0x97, 0x55, 0x9d, 0x74, 0xc3, 0x1c, 0x47, 0x54, 0xb4, 0xb2,
- 0xfd, 0xe6, 0x7d, 0xa1, 0x09, 0x58, 0xe6, 0x1e, 0x99, 0xb3, 0x2d, 0xe3, 0xe7, 0x84, 0xdc, 0xd2,
- 0xa0, 0x92, 0x58, 0x00, 0x6c, 0x1f, 0x0c, 0xd5, 0xe1, 0x3e, 0x75, 0x77, 0x92, 0x34, 0x94, 0xac,
- 0x2f, 0x0c, 0xfb, 0xf8, 0x66, 0x52, 0x86, 0x61, 0xcf, 0x64, 0x13, 0xf8, 0xa0, 0x3e, 0x0e, 0xc8,
- 0xf0, 0xed, 0xeb, 0xa0, 0x60, 0x9f, 0x19, 0xdc, 0x3c, 0x79, 0xfe, 0x79, 0x6a, 0x96, 0x5b, 0x2e,
- 0x24, 0x12, 0x56, 0xc9, 0xf3, 0x66, 0x81, 0x8f, 0x50, 0xd7, 0x5c, 0x5f, 0x7a, 0x42, 0xec, 0x5a,
- 0xa0, 0x22, 0xc3, 0x07, 0xb5, 0x95, 0xdc, 0x3f, 0x2b, 0xca, 0x40, 0x3a, 0x23, 0xac, 0xdd, 0x1d,
- 0x44, 0x2b, 0xb4, 0x09, 0x3c, 0x1b, 0xd5, 0xee, 0xe0, 0xc4, 0x19, 0x57, 0x36, 0x13, 0xf2, 0x2e,
- 0xb8, 0xf4, 0xfd, 0xc5, 0x76, 0x69, 0xa8, 0xc9, 0x4f, 0x52, 0x40, 0x8a, 0x86, 0x71, 0xf4, 0xc1,
- 0x8d, 0x11, 0xcf, 0xba, 0xc7, 0x60, 0x7e, 0xc4, 0xb1, 0x96, 0xa3, 0x0d, 0xc4, 0x71, 0x69, 0x07,
- 0x66, 0x13, 0xa1, 0x10, 0x73, 0x98, 0xb4, 0xe8, 0xf4, 0x77, 0x39, 0xe6, 0xe2, 0x00, 0x1b, 0x1d,
- 0x09, 0x4a, 0x74, 0xaa, 0x62, 0xba, 0x36, 0x60, 0x83, 0xa5, 0xad, 0xfa, 0xfb, 0xac, 0xde, 0x25,
- 0x0f, 0x7d, 0x63, 0xc6, 0x8f, 0xa5, 0xd3, 0x52, 0xec, 0xc6, 0xde, 0x56, 0x18, 0x95, 0x3d, 0x3b,
- 0xdf, 0xd8, 0x0e, 0x0e, 0x89, 0xa1, 0xb0, 0xc6, 0x94, 0x02, 0x5a, 0x7f, 0x83, 0x32, 0x02, 0x1e,
- 0x31, 0x2e, 0x96, 0x5f, 0xb6, 0xb7, 0x39, 0x65, 0x94, 0xbc, 0xf2, 0x81, 0x7b, 0xd6, 0xc6, 0xcc,
- 0x7f, 0x0a, 0x26, 0x26, 0x0a, 0x9b, 0xbe, 0xa8, 0x39, 0x7d, 0xc3, 0x76, 0x33, 0x82, 0x83, 0x57,
- 0x8b, 0x5c, 0x25, 0xf7, 0x3b, 0xb1, 0x93, 0xa8, 0xd7, 0x72, 0x2d, 0x8e, 0xf2, 0xdc, 0x16, 0xb4,
- 0x37, 0x1f, 0x24, 0x2b, 0x27, 0xe2, 0x6d, 0x7c, 0xed, 0x4c, 0xde, 0x1e, 0xe7, 0x61, 0xd9, 0x1b,
- 0xc4, 0x78, 0xc9, 0xa2, 0x87, 0x5e, 0xed, 0xfa, 0x76, 0x5e, 0x25, 0x17, 0xd6, 0x5c, 0x61, 0xc6,
- 0x2c, 0x0a, 0x33, 0xfe, 0xc7, 0x47, 0xa3, 0x23, 0xa8, 0x07, 0x00, 0x0a, 0x52, 0x8a, 0xca, 0xd4,
- 0x7c, 0xc5, 0xe4, 0xf9, 0x79, 0x8d, 0xd8, 0x69, 0x79, 0x5a, 0x32, 0x6e, 0x19, 0x06, 0x5c, 0x22,
- 0xfe, 0x6e, 0xb9, 0x95, 0x07, 0x7b, 0x04, 0xdd, 0xbd, 0x09, 0x07, 0xa4, 0x86, 0x02, 0xd5, 0xcc,
- 0xdb, 0xef, 0xd4, 0xcb, 0x33, 0xce, 0xfd, 0x88, 0xc2, 0x36, 0x15, 0x76, 0xed, 0xe2, 0xa9, 0x23,
- 0xee, 0x23, 0x3e, 0xaf, 0x69, 0x0f, 0xb6, 0x43, 0x5e, 0x44, 0x3c, 0x37, 0x60, 0xe6, 0xe6, 0xe8,
- 0xed, 0x2b, 0x08, 0xf9, 0x63, 0x50, 0x0b, 0x86, 0x96, 0x07, 0xaa, 0xee, 0xa7, 0xae, 0x92, 0x8a,
- 0x5c, 0x4f, 0xdc, 0x74, 0x0f, 0xa2, 0xbd, 0x82, 0x46, 0x11, 0xbb, 0x36, 0x7d, 0x66, 0xf6, 0x88,
- 0x9b, 0x6c, 0x0d, 0x59, 0xcb, 0x99, 0x0b, 0xc2, 0x81, 0x88, 0xc7, 0xf3, 0x97, 0x2c, 0xae, 0x3a,
- 0x74, 0x3e, 0x32, 0x2b, 0x36, 0xd8, 0x43, 0xdc, 0x36, 0x07, 0x07, 0x49, 0xae, 0x36, 0x48, 0xad,
- 0x81, 0x76, 0xcd, 0xd4, 0xde, 0x8f, 0xb6, 0x8e, 0x8b, 0xf3, 0x3c, 0x22, 0xbf, 0xad, 0xad, 0x26,
- 0x9d, 0x37, 0xd7, 0xb3, 0x1c, 0x22, 0x9e, 0x4f, 0xaf, 0x86, 0x4b, 0xa6, 0x66, 0xe4, 0x3e, 0x91,
- 0xdb, 0xfe, 0xf0, 0x60, 0x49, 0x92, 0x83, 0x8b, 0xa2, 0x56, 0xb7, 0xac, 0x62, 0x2b, 0xfd, 0x0c,
- 0xde, 0x51, 0x26, 0x81, 0xf6, 0x8a, 0x8b, 0x5e, 0x41, 0xd1, 0x86, 0x48, 0x8c, 0x69, 0x44, 0x28,
- 0xc8, 0xdd, 0x74, 0xe6, 0xbf, 0xdf, 0x69, 0x5a, 0xcb, 0xd2, 0x0b, 0xcc, 0x84, 0x45, 0x17, 0xc7,
- 0x2c, 0x14, 0xf6, 0x79, 0x9d, 0xac, 0x03, 0x8f, 0x11, 0x8d, 0xf3, 0xef, 0x79, 0xa3, 0x00, 0xaf,
- 0xcd, 0x8c, 0x57, 0xe2, 0x0f, 0x31, 0x77, 0x9f, 0x5e, 0x59, 0xcb, 0x50, 0xd2, 0xdf, 0x36, 0x90,
- 0xb0, 0x9e, 0xbe, 0xf8, 0xc0, 0xac, 0xea, 0xa2, 0x8f, 0xae, 0xfd, 0x06, 0xe8, 0x19, 0x0b, 0x06,
- 0xec, 0x86, 0x6c, 0xd2, 0x41, 0xab, 0x60, 0x7f, 0x76, 0xb7, 0x88, 0x1e, 0xcc, 0xab, 0x5a, 0x46,
- 0x43, 0x4b, 0x94, 0x33, 0xa6, 0x5b, 0x5d, 0x6e, 0xb6, 0xa0, 0x78, 0x99, 0xf6, 0x15, 0xb4, 0x07,
- 0x71, 0xbc, 0xd1, 0x9f, 0x0e, 0xa8, 0x1e, 0xa9, 0x73, 0x60, 0x8e, 0x76, 0xe8, 0x8d, 0x01, 0x91,
- 0x4f, 0x18, 0x43, 0xab, 0x11, 0xe8, 0x6b, 0xa6, 0x02, 0xe3, 0x8e, 0xe4, 0xca, 0x7f, 0x79, 0x52,
- 0x44, 0x47, 0x05, 0x1e, 0x75, 0x72, 0x00, 0xdf, 0x0c, 0x25, 0x4d, 0xaf, 0xc7, 0x61, 0x2f, 0x76,
- 0x29, 0x95, 0x5c, 0x0d, 0x92, 0x67, 0xd9, 0xc7, 0x8a, 0xe8, 0x30, 0x68, 0x3e, 0x48, 0x0d, 0x17,
- 0x5a, 0x65, 0x70, 0xce, 0x84, 0xba, 0x23, 0x81, 0x42, 0xd2, 0x01, 0x23, 0x02, 0xf0, 0xb8, 0x2a,
- 0x6f, 0xa3, 0xc3, 0x97, 0x42, 0x18, 0xcd, 0xab, 0x37, 0x48, 0x55, 0x4b, 0x5a, 0x1a, 0xd5, 0x23,
- 0xf8, 0xe8, 0x2e, 0xc7, 0xb1, 0x05, 0x37, 0xac, 0xb7, 0x4a, 0xe9, 0xfb, 0xc2, 0xb6, 0x80, 0x82,
- 0x48, 0xd6, 0x71, 0xaa, 0xe8, 0x78, 0xca, 0x8b, 0x5e, 0x69, 0x5a, 0x02, 0x89, 0x5b, 0x0c, 0x67,
- 0x7a, 0x93, 0x05, 0x31, 0x23, 0x82, 0x4e, 0xf5, 0x59, 0xf3, 0xf4, 0xc2, 0xb1, 0x47, 0xc6, 0xd8,
- 0xc1, 0xcd, 0x2b, 0x4b, 0x59, 0x1a, 0xcd, 0xdd, 0x03, 0x52, 0x14, 0x28, 0x94, 0xf6, 0xdc, 0xb2,
- 0xfd, 0x4e, 0xa5, 0x5e, 0xeb, 0x03, 0x4e, 0x7c, 0x4b, 0x9a, 0x23, 0x4f, 0x8c, 0xb4, 0xf3, 0x7f,
- 0x3e, 0x84, 0x04, 0x70, 0x6f, 0x04, 0x35, 0x2a, 0x66, 0xcf, 0xab, 0x51, 0x3f, 0xef, 0xb2, 0x5c,
- 0xba, 0xaa, 0x88, 0xf4, 0x80, 0xb1, 0x35, 0x83, 0xdc, 0xe4, 0xb7, 0xa8, 0xe9, 0x5e, 0x08, 0x91,
- 0x10, 0xf9, 0x7b, 0x97, 0x54, 0x60, 0x40, 0x83, 0xc8, 0xb8, 0xa8, 0x6c, 0xc3, 0x19, 0xf2, 0xbb,
- 0xc6, 0xea, 0xa2, 0x5e, 0x5f, 0x56, 0xba, 0xfc, 0x46, 0x32, 0xa7, 0x78, 0x0a, 0x8e, 0x0d, 0x2f,
- 0x74, 0xc4, 0x76, 0x01, 0x7f, 0x01, 0x83, 0xac, 0xa6, 0x96, 0x39, 0xff, 0xe3, 0x1f, 0x63, 0x26,
- 0x8d, 0x33, 0xb2, 0x22, 0xab, 0x97, 0x7d, 0xcf, 0x6b, 0x88, 0x41, 0x3c, 0x70, 0x5a, 0x73, 0x70,
- 0x2d, 0x72, 0x9a, 0xcf, 0x0d, 0xc1, 0x03, 0x8b, 0x81, 0x43, 0xa0, 0xd5, 0xac, 0xa7, 0xab, 0xfb,
- 0xc4, 0x6b, 0xf7, 0x06, 0xf6, 0x4a, 0xff, 0x2f, 0xad, 0x42, 0x50, 0xa9, 0x88, 0x02, 0x98, 0xf3,
- 0xd2, 0x6e, 0xc6, 0xe0, 0x2b, 0xf9, 0x2b, 0x8e, 0x6f, 0x4e, 0x47, 0x85, 0xe2, 0x67, 0xfb, 0xd7,
- 0xb9, 0x17, 0x6c, 0x9e, 0x26, 0xde, 0x56, 0xce, 0xf0, 0x77, 0xaa, 0xe8, 0xfd, 0x9c, 0x60, 0x34,
- 0x92, 0x36, 0x3d, 0xfc, 0xf6, 0xc6, 0xf0, 0xbd, 0xb7, 0x59, 0x96, 0x3d, 0xdd, 0xcf, 0x93, 0x30,
- 0xf3, 0xed, 0x3c, 0x69, 0xa0, 0x4e, 0xa8, 0x02, 0xcf, 0x87, 0xde, 0x94, 0x23, 0x1e, 0x68, 0xe6,
- 0xb6, 0x4f, 0xee, 0x59, 0xdc, 0xfe, 0x1f, 0xc9, 0xff, 0x02, 0x02, 0x0b, 0x10, 0x23, 0xee, 0xde,
- 0xe0, 0x18, 0x79, 0x78, 0x6f, 0x0f, 0x19, 0x8c, 0x8c, 0x8e, 0x2f, 0x7f, 0x22, 0xab, 0xab, 0x37,
- 0x89, 0xc7, 0x4b, 0x85, 0x68, 0x66, 0xd8, 0x37, 0x23, 0x17, 0x71, 0xc5, 0x4b, 0x6d, 0xe6, 0x92,
- 0xe5, 0xbf, 0xbc, 0x1f, 0xa4, 0x34, 0x19, 0x70, 0x59, 0x0b, 0x47, 0x4f, 0xa5, 0x60, 0x75, 0xb2,
- 0xc8, 0x11, 0x28, 0x22, 0x53, 0xfd, 0x6f, 0xf0, 0x22, 0xb0, 0x5b, 0xed, 0x8b, 0xd0, 0xbd, 0x54,
- 0xd3, 0x0f, 0x89, 0xf7, 0xd8, 0xde, 0x14, 0x15, 0x57, 0x2e, 0xf8, 0xe9, 0x54, 0xd9, 0xde, 0x5e,
- 0xa8, 0x3f, 0x0e, 0xf1, 0xbe, 0x16, 0x35, 0x37, 0x11, 0xab, 0xc2, 0xaa, 0x2e, 0x29, 0x5f, 0xb2,
- 0x93, 0x70, 0x73, 0x10, 0x03, 0xa1, 0x4c, 0x79, 0x0d, 0xd7, 0x62, 0x18, 0x41, 0xcc, 0x6d, 0x17,
- 0x03, 0x5f, 0x75, 0xb0, 0x7d, 0x11, 0x18, 0x46, 0x4f, 0x3c, 0xf0, 0xdc, 0x1b, 0x28, 0xc9, 0xbb,
- 0x62, 0x49, 0x4d, 0xfc, 0xba, 0xae, 0xff, 0xf3, 0x12, 0x9e, 0x4c, 0x86, 0x17, 0x38, 0x2e, 0x45,
- 0x48, 0xc0, 0x9b, 0x27, 0x3e, 0x7b, 0x91, 0xd2, 0xa0, 0xad, 0x77, 0x69, 0x22, 0x56, 0xad, 0x0b,
- 0xd3, 0xc6, 0x50, 0x57, 0xd5, 0xc7, 0x57, 0x35, 0xff, 0xb5, 0x5d, 0xb4, 0xa0, 0x05, 0x31, 0xf2,
- 0x55, 0x50, 0x98, 0xf3, 0x99, 0xbc, 0x23, 0x66, 0x64, 0x20, 0x1b, 0xaf, 0xa3, 0xdb, 0xc7, 0xe3,
- 0xdc, 0xd4, 0xb3, 0x73, 0x1a, 0xf1, 0x9d, 0xd9, 0x8a, 0xab, 0x85, 0x26, 0xf9, 0xab, 0xf4, 0xec,
- 0xca, 0x35, 0x08, 0x0e, 0x7b, 0xca, 0xf9, 0xa9, 0xb0, 0x42, 0xca, 0x1c, 0x33, 0xec, 0x97, 0x15,
- 0xad, 0x28, 0x8f, 0x01, 0x50, 0xc1, 0xdd, 0xb5, 0xcc, 0xd2, 0xf9, 0xb6, 0x03, 0xf8, 0x5b, 0x41,
- 0xf6, 0x98, 0x55, 0xf6, 0xfe, 0xe9, 0x4a, 0x11, 0xac, 0xed, 0xc1, 0x18, 0x95, 0xeb, 0x7b, 0x7c,
- 0xf6, 0xc8, 0x10, 0xe5, 0xfd, 0x0d, 0x78, 0xcf, 0x73, 0x20, 0xab, 0xed, 0xad, 0x89, 0x29, 0x58,
- 0x7e, 0x47, 0x0d, 0x0e, 0x19, 0x2b, 0xc6, 0x93, 0x46, 0x5d, 0xb0, 0xd1, 0x73, 0x8c, 0x41, 0x0a,
- 0xb4, 0x38, 0x04, 0x1b, 0x14, 0x02, 0xf5, 0x23, 0x08, 0xea, 0xac, 0x2f, 0x50, 0xfd, 0x13, 0xe8,
- 0xb7, 0xbc, 0x4c, 0x57, 0xfa, 0x12, 0xc1, 0x47, 0x48, 0x9d, 0xe3, 0xff, 0x69, 0x35, 0x22, 0xc0,
- 0x47, 0x83, 0x1d, 0x25, 0x6c, 0x2c, 0x16, 0xe4, 0x0f, 0x43, 0x69, 0x7b, 0xa0, 0x4d, 0x5e, 0x53,
- 0x6f, 0x35, 0xcd, 0x3c, 0xcb, 0x89, 0x2f, 0x9e, 0xdf, 0x88, 0x6d, 0xeb, 0xda, 0xcd, 0x91, 0x22,
- 0xf9, 0xd3, 0x13, 0xb1, 0xd4, 0xfe, 0x15, 0xe2, 0xcb, 0x14, 0x5d, 0x41, 0x79, 0xce, 0xbb, 0x71,
- 0xb0, 0x96, 0xba, 0x07, 0x36, 0xa6, 0xe2, 0x91, 0xda, 0x19, 0xe0, 0x8d, 0x0b, 0xcb, 0x42, 0xd0,
- 0x6c, 0xcf, 0x44, 0xa6, 0x8e, 0x1b, 0x9c, 0x2b, 0x02, 0xdb, 0xec, 0xd0, 0x5b, 0xbe, 0x30, 0x8a,
- 0xd0, 0x1c, 0x61, 0x02, 0x2a, 0x9c, 0x1a, 0xc8, 0x71, 0x47, 0xa3, 0x49, 0x45, 0x92, 0x4c, 0xea,
- 0xd4, 0x9c, 0x96, 0xf2, 0x6c, 0xf0, 0x53, 0x63, 0xcc, 0x70, 0xe2, 0x38, 0x0f, 0xc3, 0x22, 0xd5,
- 0x91, 0x27, 0xc3, 0x98, 0x16, 0xb8, 0x1d, 0xbf, 0x13, 0x69, 0x77, 0x97, 0x87, 0x87, 0x23, 0xc5,
- 0xe1, 0x66, 0x94, 0x4c, 0x9f, 0x27, 0x32, 0x88, 0x3d, 0xef, 0xfb, 0xcc, 0x71, 0x4f, 0x24, 0xb1,
- 0x06, 0xdb, 0xc3, 0x88, 0x33, 0xc5, 0x47, 0xca, 0xbc, 0x16, 0x6e, 0xdc, 0x55, 0x75, 0x2a, 0xa1,
- 0x28, 0x73, 0xb3, 0x7e, 0xe8, 0x1c, 0x23, 0x2a, 0xee, 0x69, 0x5f, 0xf8, 0x5c, 0x79, 0x73, 0x87,
- 0x7f, 0x4d, 0x72, 0xba, 0x7e, 0x5e, 0xdc, 0x47, 0xba, 0xc4, 0x83, 0xd7, 0x62, 0x9c, 0x89, 0x62,
- 0xea, 0xbe, 0xc5, 0x45, 0xee, 0xa3, 0xde, 0x89, 0x03, 0x16, 0x1f, 0xee, 0x48, 0x94, 0x9e, 0x5a,
- 0xb4, 0x06, 0x70, 0x3d, 0xe0, 0x58, 0xe4, 0xd6, 0xc7, 0xf3, 0xdc, 0x31, 0xa1, 0xa2, 0x9f, 0x93,
- 0x41, 0x45, 0x98, 0x23, 0xc8, 0x69, 0x34, 0x9e, 0x8e, 0xf5, 0x01, 0x61, 0x4a, 0xbc, 0x94, 0xa9,
- 0x69, 0x40, 0xea, 0x9f, 0xa0, 0xd8, 0xb4, 0x96, 0x0d, 0xf7, 0x78, 0xd6, 0xdf, 0xdc, 0x45, 0x26,
- 0xfc, 0x39, 0x83, 0xde, 0xa3, 0x94, 0x27, 0xf9, 0xed, 0x72, 0xae, 0xd9, 0x40, 0x27, 0xe3, 0xc6,
- 0x3c, 0x69, 0x98, 0x6a, 0xd9, 0x8f, 0x4d, 0x7d, 0x71, 0xd4, 0xc8, 0x42, 0xfa, 0x37, 0xaa, 0x68,
- 0x7e, 0x7d, 0xab, 0x40, 0xfd, 0x8b, 0x88, 0xae, 0x4d, 0xe4, 0x0f, 0x20, 0x3e, 0x61, 0x35, 0x62,
- 0xe2, 0xf0, 0x19, 0x84, 0xf8, 0x77, 0x85, 0x9d, 0x9f, 0xb7, 0x5c, 0x07, 0x89, 0x80, 0x7f, 0xa6,
- 0x64, 0xf3, 0x33, 0xdc, 0x27, 0x8b, 0x08, 0xe6, 0xf0, 0xb2, 0xc7, 0xd1, 0x30, 0xe5, 0x72, 0xb1,
- 0x24, 0x6d, 0x5d, 0xcb, 0x45, 0x77, 0x7a, 0xbf, 0x61, 0x8b, 0xaf, 0xd1, 0x80, 0xf2, 0x6a, 0x63,
- 0xb5, 0x15, 0xe4, 0x86, 0xc5, 0xa7, 0x82, 0x28, 0x99, 0x78, 0x03, 0xcb, 0x53, 0x80, 0xf4, 0xb4,
- 0x7d, 0x5a, 0x26, 0x2a, 0x04, 0xb5, 0x57, 0xdf, 0x02, 0x16, 0x3b, 0xa0, 0x24, 0x39, 0xdd, 0x9b,
- 0xd4, 0x27, 0x3a, 0x3b, 0xd6, 0x0d, 0x6f, 0xa6, 0x8d, 0x36, 0xc5, 0x20, 0x6b, 0x5b, 0xc0, 0x68,
- 0xd6, 0x32, 0x29, 0x91, 0x0c, 0xbe, 0xf4, 0x50, 0xeb, 0xbf, 0xb2, 0x72, 0xa4, 0xcc, 0xcd, 0x90,
- 0x36, 0x56, 0xee, 0x4e, 0xd3, 0x2f, 0x22, 0x27, 0x97, 0x7f, 0xd1, 0xb2, 0x8a, 0x84, 0xce, 0xee,
- 0xd0, 0x57, 0xb6, 0xea, 0xf6, 0x01, 0x7e, 0x69, 0xd8, 0xcb, 0xe0, 0x91, 0xfa, 0x8d, 0xed, 0xee,
- 0x5f, 0xdb, 0x2d, 0xb3, 0xc8, 0x78, 0x69, 0x93, 0x35, 0x0c, 0x2a, 0x26, 0x22, 0xa8, 0x4d, 0xea,
- 0x95, 0x8c, 0x94, 0x84, 0x70, 0xd1, 0xfc, 0x4c, 0xbb, 0xf7, 0xca, 0xce, 0x47, 0x16, 0xa2, 0x9e,
- 0x49, 0x3b, 0x3e, 0x13, 0xd3, 0xf0, 0xa3, 0xc2, 0x56, 0x29, 0xb2, 0xa3, 0xee, 0x55, 0x7a, 0x42,
- 0x9b, 0x01, 0xd7, 0x59, 0xe8, 0x34, 0xa5, 0x6b, 0xb0, 0xf0, 0x76, 0xff, 0x59, 0xb5, 0x09, 0x47,
- 0x1c, 0x88, 0xd4, 0xb8, 0xec, 0x3b, 0x75, 0xf7, 0xbc, 0x13, 0x80, 0x95, 0x0c, 0x9b, 0x5d, 0x43,
- 0xa4, 0x59, 0xa5, 0xd9, 0x08, 0xe3, 0x39, 0x23, 0xf9, 0xb7, 0xdb, 0x60, 0xbe, 0x4d, 0xd9, 0x8a,
- 0x94, 0xb7, 0xb6, 0x5c, 0x5f, 0x2d, 0x02, 0xeb, 0x90, 0x31, 0x91, 0x22, 0xc2, 0x9d, 0xcf, 0xaa,
- 0x41, 0x31, 0xf9, 0x8b, 0x91, 0x18, 0x70, 0x36, 0xbe, 0x50, 0x10, 0x02, 0xf1, 0x56, 0x15, 0x7c,
- 0x18, 0x28, 0x31, 0x70, 0xed, 0x29, 0x69, 0xde, 0xb4, 0xf5, 0x35, 0x6d, 0x99, 0x38, 0xcf, 0x20,
- 0x18, 0xc3, 0xf4, 0x1d, 0xde, 0xdc, 0x90, 0x67, 0x61, 0xba, 0x8a, 0x45, 0xc2, 0xf9, 0xad, 0x6e,
- 0x41, 0x4f, 0x07, 0x75, 0xe3, 0x18, 0xb0, 0xe7, 0x4a, 0xe3, 0x03, 0xf7, 0xfe, 0x69, 0x69, 0x3b,
- 0xea, 0x74, 0x4c, 0xc8, 0x47, 0x9f, 0x70, 0xe9, 0x00, 0xc4, 0xce, 0xcc, 0x90, 0x73, 0x45, 0xb1,
- 0xe6, 0xee, 0xd5, 0x74, 0xce, 0xca, 0x39, 0x5c, 0xcd, 0x9a, 0xe3, 0x70, 0x70, 0x91, 0x5b, 0xc3,
- 0x49, 0x99, 0x71, 0x67, 0x7e, 0x4f, 0x37, 0xf3, 0x92, 0x75, 0xc8, 0x2b, 0x1a, 0x33, 0xf7, 0xd7,
- 0x6b, 0x83, 0x35, 0xac, 0xba, 0x36, 0x1b, 0x66, 0x30, 0xee, 0x66, 0x8b, 0xeb, 0x82, 0xc7, 0x1d,
- 0x9c, 0xdf, 0xeb, 0x2c, 0x60, 0x4c, 0xb5, 0x41, 0xe0, 0x3e, 0xe3, 0xeb, 0x79, 0x57, 0x0a, 0x1c,
- 0x02, 0x05, 0xba, 0xc0, 0xcd, 0x78, 0x60, 0xa3, 0x87, 0x99, 0x65, 0x04, 0x3b, 0x62, 0x01, 0x06,
- 0x7f, 0xe0, 0xe9, 0x36, 0x25, 0xf9, 0x97, 0x1b, 0x77, 0x33, 0x97, 0xdc, 0x12, 0x42, 0x50, 0xe5,
- 0x95, 0xb5, 0x7e, 0xf2, 0x70, 0xb3, 0x06, 0x60, 0x7f, 0xd7, 0x5e, 0xc6, 0xff, 0x73, 0x22, 0x03,
- 0x6b, 0xc7, 0x05, 0x98, 0x5b, 0x7e, 0xc5, 0x54, 0xaf, 0x9d, 0xe5, 0xa1, 0xc9, 0x64, 0xca, 0x43,
- 0xca, 0xec, 0xfa, 0x74, 0xaa, 0x50, 0x82, 0x68, 0x8c, 0xd1, 0x01, 0x60, 0x02, 0xce, 0x97, 0x09,
- 0x7e, 0x3a, 0xc3, 0x6b, 0x8a, 0x67, 0x91, 0x34, 0x06, 0xbc, 0xc5, 0x3e, 0xf9, 0x7e, 0xe6, 0xdd,
- 0x84, 0xa8, 0xbc, 0xc4, 0x5c, 0xcc, 0xb4, 0xaa, 0xd0, 0xe1, 0x06, 0xc1, 0x9d, 0x06, 0xdd, 0x4a,
- 0xa1, 0x39, 0x30, 0x02, 0xe8, 0xfc, 0x40, 0x85, 0x96, 0x10, 0x14, 0x14, 0x54, 0xc9, 0x9e, 0x9c,
- 0x5b, 0xe8, 0x13, 0x2e, 0xaa, 0x93, 0x71, 0xde, 0xb3, 0x71, 0xbf, 0x6a, 0x12, 0xac, 0x26, 0x70,
- 0x55, 0x62, 0x04, 0x49, 0x2e, 0x05, 0xbc, 0x57, 0x1c, 0xa9, 0xe6, 0x57, 0xdc, 0x9a, 0xea, 0x92,
- 0x76, 0xe9, 0x4a, 0x5e, 0x09, 0x0f, 0x2e, 0xd1, 0x0d, 0xc2, 0x54, 0xf3, 0x14, 0xcb, 0x8b, 0xe3,
- 0x05, 0x0a, 0xdd, 0x2e, 0xeb, 0x7e, 0x2b, 0x2c, 0xb0, 0x53, 0xf1, 0xd2, 0x2c, 0x76, 0x6a, 0xa9,
- 0x06, 0x77, 0x15, 0x70, 0x9a, 0x71, 0x0d, 0x3a, 0x27, 0x1b, 0x00, 0x09, 0x35, 0xeb, 0x07, 0x74,
- 0xb3, 0x1c, 0x77, 0x77, 0x5c, 0xc8, 0xe3, 0xe5, 0xb1, 0xa9, 0x35, 0x69, 0xc9, 0x49, 0xad, 0xeb,
- 0xbb, 0x52, 0x50, 0x8c, 0x03, 0x6f, 0x40, 0x20, 0xc0, 0xdd, 0xbe, 0xe8, 0x60, 0x23, 0xdc, 0x2c,
- 0x69, 0x35, 0x8a, 0xfa, 0x4a, 0x40, 0xee, 0xf6, 0xc0, 0xd7, 0xce, 0x54, 0x4a, 0x99, 0x81, 0x81,
- 0xef, 0x95, 0xec, 0x1b, 0x1d, 0xd5, 0xcf, 0xf2, 0xf2, 0xd3, 0xa2, 0x93, 0x84, 0xa9, 0x36, 0xd9,
- 0x1a, 0x41, 0xff, 0xe8, 0x25, 0xfd, 0xf8, 0x49, 0xef, 0xb1, 0x1a, 0xf3, 0x54, 0x31, 0xcf, 0x4e,
- 0xc7, 0x12, 0xbc, 0xac, 0xa2, 0x98, 0xa9, 0x7a, 0xa9, 0x47, 0x65, 0x0e, 0xf0, 0x29, 0xc5, 0xf3,
- 0x2c, 0x90, 0x20, 0x29, 0xcc, 0x28, 0x9c, 0x02, 0x22, 0x2d, 0x07, 0xab, 0x30, 0xfd, 0x52, 0x0b,
- 0xde, 0x85, 0x00, 0x01, 0xdf, 0x8a, 0x2d, 0x22, 0xcb, 0x7e, 0xce, 0xe0, 0xf3, 0x12, 0x19, 0x14,
- 0x78, 0x88, 0x19, 0x3e, 0x11, 0x66, 0x22, 0x00, 0x20, 0x85, 0x98, 0xa2, 0xd3, 0x92, 0x56, 0x68,
- 0x6e, 0x44, 0xc2, 0xc2, 0x2e, 0x56, 0x1c, 0x3e, 0x47, 0x87, 0x95, 0x6c, 0xe4, 0x11, 0xea, 0xf6,
- 0x0b, 0x84, 0x2f, 0xce, 0x0f, 0x62, 0x00, 0xa5, 0x4a, 0x5d, 0xda, 0x68, 0x66, 0x20, 0xe5, 0x24,
- 0xaf, 0x08, 0xe0, 0x6f, 0xdd, 0xa5, 0xc1, 0x62, 0x11, 0x27, 0x0f, 0xd4, 0x88, 0x8f, 0x4e, 0x9c,
- 0xfc, 0x52, 0x41, 0x93, 0x93, 0x43, 0xcf, 0xec, 0x73, 0x0a, 0x26, 0x7d, 0x9e, 0x1d, 0x16, 0xc5,
- 0xf6, 0x4d, 0x24, 0x3c, 0xdd, 0x5f, 0x4d, 0x14, 0xb7, 0x90, 0x63, 0xa9, 0x59, 0x57, 0x66, 0x81,
- 0xd5, 0x29, 0x09, 0x8d, 0x9d, 0x08, 0xf2, 0xbe, 0xb2, 0xe2, 0xed, 0x09, 0xda, 0x2b, 0x4a, 0x86,
- 0xbf, 0x85, 0xb7, 0x5c, 0x91, 0x38, 0x32, 0x4c, 0xcc, 0x26, 0x72, 0x97, 0xa9, 0xcb, 0x50, 0x75,
- 0x52, 0xc4, 0x99, 0x75, 0xef, 0x04, 0x9e, 0xf0, 0xff, 0xe8, 0x11, 0xcd, 0x85, 0x3b, 0xfb, 0x98,
- 0xcb, 0x65, 0x4a, 0xe3, 0x3d, 0xf6, 0x05, 0x67, 0x72, 0x5e, 0x24, 0xb2, 0x89, 0x0e, 0x19, 0xc9,
- 0xeb, 0x4e, 0x34, 0xc6, 0xc6, 0xe5, 0xc2, 0x93, 0xca, 0x1c, 0xc4, 0x47, 0x2b, 0x21, 0xe6, 0x5b,
- 0x0d, 0x0d, 0x38, 0xb1, 0xbd, 0xd4, 0xe1, 0x38, 0xce, 0x53, 0xcc, 0xa8, 0xf3, 0x2a, 0x16, 0x55,
- 0x10, 0x77, 0xe1, 0xe9, 0x63, 0xdd, 0xe0, 0xd0, 0xd2, 0xff, 0x87, 0x21, 0xca, 0x09, 0xd9, 0xd1,
- 0xc6, 0x35, 0x24, 0x26, 0x22, 0xdf, 0xc0, 0xe6, 0x7f, 0xe7, 0x33, 0xbf, 0x7b, 0x54, 0x98, 0x7b,
- 0x88, 0x3c, 0x3a, 0x0c, 0x1e, 0x9f, 0x39, 0x02, 0xc1, 0xce, 0x06, 0xbe, 0x2e, 0xb7, 0xb6, 0x21,
- 0xe6, 0x4b, 0xb4, 0x65, 0x3a, 0x77, 0xe3, 0xca, 0xe0, 0x83, 0x75, 0xd4, 0x5d, 0xbc, 0x77, 0x24,
- 0x69, 0x9b, 0xd4, 0x77, 0x23, 0x49, 0x0e, 0x9a, 0xf3, 0x26, 0x9d, 0xa9, 0x31, 0x81, 0x0d, 0xba,
- 0x94, 0x58, 0x9a, 0x82, 0x8a, 0x4e, 0x6a, 0x65, 0x90, 0xbf, 0x4a, 0x85, 0x51, 0x65, 0x3a, 0x1d,
- 0xac, 0xbf, 0x39, 0x11, 0xf6, 0xe2, 0x1f, 0x6c, 0xeb, 0x96, 0xde, 0x7a, 0x59, 0x83, 0x6d, 0x8f,
- 0x3b, 0xd5, 0xb9, 0x54, 0x5a, 0x05, 0xe7, 0x11, 0xd8, 0x52, 0x12, 0x2e, 0xf5, 0x44, 0x99, 0x55,
- 0xf7, 0xcd, 0xb8, 0x37, 0x16, 0xa7, 0xaa, 0xc0, 0x9a, 0x64, 0x44, 0x1e, 0xd7, 0x48, 0x40, 0x52,
- 0xdd, 0xcc, 0x99, 0x98, 0x33, 0x06, 0xe7, 0xec, 0x00, 0x91, 0x81, 0x48, 0x27, 0xdf, 0xb2, 0xe1,
- 0xfd, 0x87, 0x22, 0x66, 0x81, 0xde, 0x0b, 0xcd, 0xb2, 0xaf, 0x8c, 0xaf, 0xd4, 0xe6, 0xc9, 0xb9,
- 0xd9, 0xb9, 0x16, 0x84, 0xcb, 0xb3, 0x65, 0xb9, 0x6c, 0x00, 0xcb, 0x31, 0x22, 0x36, 0xa9, 0x1a,
- 0xfb, 0xf7, 0x3a, 0xd2, 0x70, 0xf7, 0x97, 0x63, 0xbf, 0x35, 0x8c, 0x17, 0xd7, 0x10, 0x05, 0x32,
- 0xfe, 0x80, 0xd9, 0x04, 0x02, 0x1a, 0xc9, 0xb1, 0xcf, 0xa6, 0x26, 0x0e, 0x99, 0xf8, 0x6c, 0x32,
- 0x27, 0x2f, 0xac, 0xf2, 0x17, 0x95, 0xcf, 0x11, 0x97, 0x10, 0x26, 0x17, 0xe8, 0x78, 0xc2, 0xaf,
- 0x3a, 0x53, 0x71, 0x96, 0x41, 0x55, 0x6a, 0xdc, 0x9a, 0xbc, 0x57, 0x5c, 0x5a, 0x10, 0x97, 0x50,
- 0xa4, 0x08, 0x4c, 0x21, 0x6c, 0x95, 0xfa, 0xff, 0xdd, 0xf8, 0xd2, 0xf0, 0x6d, 0x6d, 0x24, 0x19,
- 0x9a, 0x42, 0x0a, 0xe8, 0xef, 0x90, 0xf7, 0xb0, 0xe0, 0xfa, 0xbe, 0xf8, 0xf1, 0x47, 0xff, 0xe6,
- 0x23, 0x23, 0x97, 0x42, 0xde, 0x35, 0x89, 0xf0, 0xd2, 0x1b, 0xee, 0x1f, 0x2c, 0xd1, 0xb1, 0x85,
- 0xbf, 0x1a, 0x08, 0x15, 0xc1, 0x7e, 0xcc, 0x85, 0xc2, 0xec, 0x50, 0x8c, 0x97, 0xe4, 0xf7, 0x5d,
- 0x0a, 0x39, 0x00, 0x57, 0x56, 0x0f, 0x35, 0x0b, 0x7d, 0x8d, 0x68, 0x32, 0x85, 0x70, 0x55, 0x83,
- 0x9a, 0x31, 0x62, 0x25, 0x01, 0xb2, 0xc6, 0x54, 0xbc, 0xf0, 0x98, 0xdd, 0x78, 0xe9, 0xa1, 0x6c,
- 0x8e, 0x2c, 0x74, 0x17, 0xe9, 0xec, 0x0e, 0x7b, 0x64, 0xa0, 0x70, 0xe7, 0xab, 0x12, 0xf0, 0x5f,
- 0xa6, 0x7d, 0x9b, 0xa6, 0x86, 0xbc, 0x4c, 0x22, 0x88, 0x11, 0x54, 0x53, 0x6a, 0x55, 0x09, 0x7f,
- 0xd9, 0xab, 0xaf, 0x2e, 0x29, 0xa3, 0xc0, 0x75, 0xbe, 0x67, 0x8e, 0x49, 0x1c, 0xb5, 0x59, 0x85,
- 0xbf, 0xfe, 0x68, 0x84, 0x75, 0xf5, 0xa6, 0xd1, 0xe5, 0x29, 0xd9, 0x43, 0xf6, 0xc2, 0x8a, 0xd8,
- 0xe8, 0xfa, 0x14, 0x4f, 0x71, 0xa7, 0x24, 0x5a, 0xff, 0xe8, 0x01, 0x50, 0x5e, 0x37, 0x00, 0x96,
- 0xbf, 0x17, 0xf6, 0x17, 0xce, 0x18, 0xd0, 0x25, 0x07, 0x6a, 0x8a, 0x51, 0xd4, 0x4a, 0xde, 0x16,
- 0x10, 0x83, 0x1f, 0x68, 0xcf, 0xe6, 0xcb, 0xea, 0xe0, 0x8d, 0x43, 0x46, 0x41, 0x7c, 0xf2, 0x40,
- 0xcb, 0xa8, 0x79, 0x00, 0xe5, 0xec, 0xb3, 0x4d, 0x74, 0x7f, 0x3e, 0xee, 0xee, 0x70, 0x33, 0xfc,
- 0x94, 0x6c, 0x08, 0x8a, 0xb2, 0x75, 0x74, 0x3e, 0xc7, 0x90, 0xd2, 0xdd, 0x4a, 0x5d, 0x51, 0x5b,
- 0xa5, 0x3a, 0xb4, 0x4b, 0xd9, 0xf4, 0xf0, 0xe5, 0xc5, 0x54, 0x74, 0x16, 0x03, 0x99, 0x0b, 0x92,
- 0x4a, 0x91, 0x93, 0x29, 0x83, 0x9c, 0x89, 0x41, 0xb0, 0x88, 0x5c, 0x10, 0x55, 0xda, 0x32, 0x2c,
- 0x07, 0x37, 0x4a, 0xee, 0x4b, 0xc2, 0xaf, 0x42, 0x7b, 0x68, 0x7e, 0xc3, 0xe1, 0x2c, 0x1f, 0x81,
- 0xf2, 0xee, 0xea, 0x89, 0x4a, 0xf4, 0x9c, 0x60, 0x75, 0xea, 0x90, 0x0a, 0x7f, 0x89, 0x7e, 0xbd,
- 0x05, 0x6e, 0x81, 0xc1, 0x9c, 0x8d, 0x65, 0xa0, 0x52, 0xb5, 0xc4, 0x74, 0x97, 0x47, 0xff, 0x55,
- 0x85, 0x8c, 0x78, 0x99, 0xb7, 0x32, 0xda, 0x11, 0x7a, 0xf4, 0x4f, 0x29, 0xd9, 0x3f, 0x51, 0x82,
- 0xac, 0xdb, 0x5e, 0x1a, 0xef, 0x9b, 0xbf, 0x97, 0xad, 0x0c, 0x42, 0x2e, 0xe2, 0x17, 0x52, 0x25,
- 0xa9, 0x2d, 0xcb, 0xa4, 0x0a, 0x2f, 0xb7, 0xe0, 0xe4, 0xdc, 0xab, 0xe0, 0x4d, 0x88, 0xf3, 0x00,
- 0x15, 0x52, 0x2e, 0x4d, 0x52, 0xe1, 0xe0, 0x84, 0x61, 0xcd, 0x78, 0x42, 0x38, 0x2e, 0xa2, 0x57,
- 0xc5, 0x56, 0x7c, 0x5e, 0x90, 0xfa, 0x77, 0xa3, 0x0c, 0x86, 0xc1, 0x2b, 0x8e, 0x2a, 0x80, 0x64,
- 0x69, 0x10, 0xcb, 0x0e, 0x09, 0xd6, 0x40, 0x60, 0x28, 0x76, 0x01, 0x18, 0xb0, 0x7f, 0xf6, 0x30,
- 0x5f, 0x04, 0x2c, 0x51, 0x01, 0xfa, 0xc1, 0x3a, 0x07, 0x60, 0x52, 0x44, 0xfe, 0xc9, 0x69, 0xcd,
- 0x52, 0x5a, 0xa8, 0x1d, 0x67, 0xc6, 0xee, 0x79, 0x98, 0x5a, 0xff, 0x80, 0x5b, 0x3a, 0x57, 0x49,
- 0xfa, 0x18, 0xf6, 0x6d, 0x51, 0x15, 0xc6, 0x0e, 0xb9, 0x35, 0xff, 0x88, 0xef, 0xa9, 0x4f, 0xf5,
- 0x0f, 0x87, 0x5a, 0x58, 0x30, 0x3e, 0xde, 0xee, 0xff, 0x06, 0x7b, 0xa6, 0x20, 0x24, 0xd6, 0x12,
- 0x4c, 0x3f, 0x1d, 0x3d, 0x4d, 0xc9, 0xd9, 0x23, 0x4d, 0x18, 0x92, 0xf7, 0xa8, 0x45, 0xb0, 0x18,
- 0x47, 0x66, 0xd1, 0x30, 0x0d, 0x8d, 0x14, 0x6c, 0xdd, 0xf8, 0x34, 0x05, 0x25, 0x11, 0x1e, 0x3b,
- 0xf6, 0xb2, 0xe1, 0xdf, 0x77, 0xba, 0xd1, 0x82, 0x2d, 0xe7, 0xc2, 0x92, 0x38, 0x6e, 0xda, 0x53,
- 0xa3, 0xba, 0x92, 0x3e, 0x55, 0xd8, 0x6a, 0xf0, 0xfa, 0x88, 0x4c, 0x1f, 0xaf, 0x73, 0x59, 0x33,
- 0x88, 0xa5, 0xe8, 0xe5, 0x85, 0x4f, 0x4d, 0x93, 0x1c, 0x89, 0x88, 0x71, 0xff, 0x47, 0x0b, 0xf8,
- 0xfb, 0x20, 0x44, 0x26, 0x57, 0x01, 0x45, 0x08, 0xf5, 0x4a, 0x51, 0x67, 0x4a, 0xc7, 0xe4, 0x4d,
- 0xd6, 0x93, 0x42, 0x6b, 0x90, 0x0b, 0x09, 0x18, 0x02, 0x23, 0x5b, 0x05, 0x45, 0x0e, 0xda, 0x57,
- 0xc1, 0xa8, 0x7b, 0xe4, 0x98, 0x80, 0x12, 0x2d, 0x11, 0xaf, 0x8c, 0x0c, 0xb9, 0xb2, 0x2f, 0xf5,
- 0xad, 0xce, 0x4c, 0x3a, 0x0a, 0x32, 0x67, 0x87, 0x1c, 0x85, 0x57, 0x1d, 0x4a, 0x26, 0x52, 0xe6,
- 0x89, 0xef, 0x75, 0x19, 0x08, 0x9d, 0x05, 0x9d, 0x08, 0xa9, 0xc0, 0x15, 0x39, 0x98, 0x44, 0x71,
- 0x35, 0xa3, 0xe2, 0x94, 0x37, 0x00, 0x11, 0x6d, 0xed, 0x20, 0x83, 0x51, 0x21, 0xd1, 0x60, 0x94,
- 0xe8, 0x41, 0x91, 0x8a, 0x4b, 0xc7, 0x80, 0x2d, 0x46, 0xfe, 0x57, 0xed, 0x5c, 0x37, 0xeb, 0xaa,
- 0x8a, 0x73, 0x64, 0xd6, 0xa3, 0x9d, 0x6b, 0x7f, 0x57, 0xf0, 0x2d, 0xae, 0xfb, 0x11, 0x62, 0x6a,
- 0x61, 0x5a, 0x48, 0xa5, 0x07, 0xb1, 0x4d, 0x79, 0x40, 0x5c, 0x34, 0x2d, 0xcc, 0x87, 0xbb, 0xcd,
- 0xe5, 0x7f, 0xa6, 0x09, 0xcd, 0x90, 0xdb, 0xf6, 0xdc, 0x3a, 0xa7, 0xa4, 0x20, 0x9c, 0x3f, 0x4c,
- 0x24, 0x10, 0x7c, 0x75, 0x35, 0x10, 0x4a, 0xc5, 0x6f, 0x2e, 0xc4, 0x98, 0x84, 0x0d, 0x86, 0xf3,
- 0xc6, 0xb1, 0x4a, 0x54, 0xac, 0x08, 0x6e, 0x13, 0xd2, 0xbe, 0x14, 0x39, 0xb9, 0xa9, 0x4f, 0xb9,
- 0x85, 0xbf, 0xf5, 0x18, 0x4b, 0x4f, 0x26, 0x2a, 0x39, 0x50, 0xf5, 0x01, 0x58, 0x8a, 0xbd, 0x22,
- 0xd0, 0x29, 0xa6, 0x53, 0x40, 0xc0, 0x73, 0xdc, 0xd9, 0x03, 0x6a, 0xfd, 0x57, 0xdc, 0x2b, 0x4b,
- 0xd0, 0xe7, 0x4c, 0xed, 0xa7, 0x2a, 0x88, 0x37, 0x4f, 0x75, 0x43, 0x8b, 0x5e, 0xae, 0x1c, 0xc5,
- 0xad, 0xbb, 0xbe, 0x43, 0x59, 0xc4, 0x5d, 0xa1, 0x1f, 0xb0, 0xbb, 0x71, 0xb5, 0x13, 0x74, 0xce,
- 0x0b, 0x62, 0x36, 0x66, 0x9d, 0x0d, 0xe5, 0x5a, 0x34, 0xd1, 0x6d, 0xec, 0xab, 0x92, 0x7c, 0xf1,
- 0xed, 0x5c, 0xe5, 0x61, 0x14, 0xf5, 0x72, 0xe5, 0xbf, 0x92, 0xc2, 0xb3, 0x3a, 0x82, 0xcb, 0xef,
- 0xa0, 0xbf, 0xa7, 0x88, 0x06, 0x6a, 0x20, 0x9d, 0xb8, 0x04, 0xb1, 0x52, 0x5f, 0x7f, 0x16, 0x74,
- 0x98, 0xbe, 0xf6, 0x02, 0x0c, 0x42, 0x91, 0xaf, 0x8d, 0x1e, 0x24, 0x19, 0x04, 0x27, 0x2b, 0x8a,
- 0x73, 0xb5, 0x7a, 0x61, 0x86, 0x4b, 0x1d, 0xa2, 0xff, 0xe9, 0xe9, 0x04, 0x50, 0x04, 0x22, 0xa6,
- 0xe1, 0xa2, 0xa6, 0xfd, 0xc5, 0x87, 0xbf, 0x2e, 0xab, 0x92, 0xc4, 0xf1, 0xf5, 0x9d, 0xe8, 0xfa,
- 0x67, 0x3a, 0xb1, 0x75, 0x38, 0x76, 0x2c, 0xce, 0x4a, 0x55, 0xc5, 0xa9, 0x0b, 0x91, 0x72, 0x40,
- 0x78, 0x61, 0x87, 0xb1, 0x3d, 0x85, 0xfc, 0x59, 0x5f, 0x80, 0x9b, 0x9d, 0xc8, 0x07, 0x93, 0x4a,
- 0x61, 0x7f, 0xed, 0xaa, 0x01, 0x2d, 0x2d, 0x5b, 0x49, 0xf6, 0xa9, 0x91, 0x6c, 0xda, 0x67, 0xe5,
- 0xcb, 0x64, 0xc5, 0x12, 0x14, 0xa4, 0x6e, 0x04, 0x68, 0xa9, 0xe2, 0xc2, 0x58, 0xe8, 0x95, 0xe5,
- 0x35, 0x73, 0xbf, 0x85, 0x09, 0x21, 0xb9, 0xd3, 0x57, 0xda, 0xb7, 0xa5, 0xfe, 0x12, 0x7f, 0xf4,
- 0xa5, 0x75, 0x03, 0xe5, 0x6b, 0x1a, 0x4e, 0x10, 0xcc, 0x06, 0x6e, 0x7f, 0xac, 0x14, 0x8b, 0xdd,
- 0xa7, 0x52, 0xa5, 0xfb, 0xc7, 0x5c, 0xe5, 0x3c, 0x6d, 0xd8, 0xf4, 0xaa, 0x28, 0x42, 0xb3, 0x78,
- 0x2c, 0x37, 0x00, 0x3e, 0xb2, 0x12, 0x44, 0x91, 0x43, 0xa0, 0xe4, 0xcc, 0x3a, 0x46, 0xa4, 0x69,
- 0xe8, 0x41, 0xb5, 0xee, 0x1e, 0xbb, 0x24, 0xa3, 0x2f, 0xf8, 0x8c, 0x02, 0x90, 0xae, 0x05, 0xb4,
- 0xd5, 0xaa, 0x76, 0x5b, 0x66, 0x5e, 0x3e, 0x45, 0x0e, 0x6a, 0xd6, 0xbd, 0x5c, 0xab, 0x7a, 0xb8,
- 0x71, 0xa1, 0xf5, 0xf0, 0x96, 0xc7, 0xa6, 0x1b, 0xf7, 0x71, 0xbc, 0xa6, 0x71, 0x10, 0x9f, 0x35,
- 0xca, 0x1d, 0xf6, 0x24, 0x22, 0x49, 0xd5, 0xdc, 0xbf, 0x35, 0x01, 0xc4, 0x69, 0xce, 0x31, 0x72,
- 0x38, 0xee, 0x05, 0x18, 0x75, 0xcd, 0xed, 0x40, 0xd7, 0x14, 0xa3, 0x53, 0x74, 0x47, 0xc6, 0x40,
- 0x60, 0x5c, 0x34, 0x1a, 0x98, 0x31, 0x37, 0xa7, 0x5e, 0x21, 0x20, 0xaf, 0x9e, 0xc8, 0x59, 0x54,
- 0x2a, 0xde, 0x34, 0xc4, 0x3a, 0x9d, 0x66, 0x64, 0x8b, 0x1f, 0x1d, 0x4a, 0xad, 0x6b, 0xb1, 0x7e,
- 0x8c, 0x17, 0x18, 0x4d, 0x41, 0x32, 0x68, 0xf8, 0x44, 0x0d, 0x7f, 0x21, 0x77, 0x95, 0x09, 0x70,
- 0xc3, 0xe3, 0xe3, 0xf8, 0x01, 0xe3, 0xa4, 0xdd, 0x53, 0x96, 0x1b, 0x2e, 0xcd, 0xd3, 0xc3, 0xf1,
- 0x5c, 0xdf, 0xf9, 0x78, 0xd5, 0x2b, 0xfc, 0x6f, 0xbe, 0xe8, 0x3f, 0x64, 0x2b, 0xc1, 0xd9, 0xf7,
- 0xc3, 0xad, 0xad, 0x44, 0x55, 0xa4, 0xac, 0xab, 0xfa, 0xe8, 0x39, 0xd7, 0xd3, 0xfa, 0x28, 0x7f,
- 0x7f, 0xca, 0x98, 0xbf, 0x2a, 0xe6, 0xef, 0xd0, 0x4d, 0xb4, 0x52, 0x5b, 0x34, 0x38, 0x8f, 0x96,
- 0xa3, 0x76, 0x4d, 0x73, 0x43, 0xe9, 0x1d, 0x36, 0x2b, 0xc4, 0xb3, 0x0b, 0xe8, 0x4c, 0xb2, 0xca,
- 0x5a, 0x00, 0xdf, 0x84, 0x83, 0xaf, 0x74, 0xfe, 0xe4, 0x17, 0x00, 0x28, 0xe8, 0xb4, 0x51, 0x0d,
- 0xc0, 0xb8, 0x32, 0xbb, 0xc0, 0xb0, 0xd7, 0x8b, 0x95, 0x82, 0xe4, 0xf2, 0x30, 0xac, 0x80, 0x5e,
- 0x07, 0xe5, 0xe7, 0x33, 0x6c, 0xc4, 0xd2, 0x25, 0xe7, 0x73, 0x7c, 0x33, 0xe8, 0x2e, 0x47, 0xca,
- 0x90, 0x72, 0x4d, 0x58, 0xad, 0x09, 0xbb, 0x69, 0x19, 0x64, 0x08, 0xd9, 0x0c, 0xdc, 0x13, 0x47,
- 0x8b, 0xe3, 0x0d, 0x83, 0xcc, 0x32, 0x8f, 0xf5, 0x53, 0xec, 0x6f, 0xe9, 0xa7, 0xa3, 0x48, 0x92,
- 0x91, 0x4b, 0xe2, 0xc0, 0x5f, 0x0e, 0xe2, 0x4b, 0xd0, 0xaa, 0x33, 0x05, 0x5f, 0x88, 0x77, 0xc0,
- 0x5c, 0x06, 0xa3, 0x2f, 0x4e, 0x7d, 0x9e, 0xbf, 0x10, 0x18, 0x68, 0x74, 0x54, 0x09, 0xb0, 0x52,
- 0x21, 0x72, 0x1c, 0x6b, 0x6f, 0x22, 0x9c, 0x7c, 0xe8, 0x0b, 0x98, 0x1a, 0x96, 0x0a, 0xd4, 0xd4,
- 0x5a, 0x08, 0x3c, 0xf9, 0x93, 0x2c, 0xde, 0x49, 0x3d, 0xed, 0xe4, 0x7a, 0xeb, 0x31, 0x51, 0x47,
- 0xa9, 0xcd, 0xd5, 0x1d, 0xaa, 0x8e, 0x95, 0x03, 0x2c, 0x7e, 0xd3, 0x24, 0x1c, 0x4d, 0xeb, 0x5d,
- 0xda, 0x57, 0x6e, 0xb0, 0x5a, 0xf2, 0x1a, 0x2a, 0x78, 0x5c, 0xcf, 0x3c, 0xc0, 0xe1, 0x2d, 0x2b,
- 0xb3, 0xe6, 0xde, 0x25, 0x0f, 0x61, 0x5a, 0x9a, 0x88, 0xba, 0x91, 0x0d, 0xd1, 0x63, 0x96, 0x20,
- 0x59, 0xa0, 0xe8, 0x14, 0x40, 0x42, 0x3f, 0xa5, 0x4b, 0xf1, 0x0e, 0xc0, 0xa1, 0x7f, 0x92, 0xd6,
- 0x89, 0xd6, 0x64, 0x12, 0x31, 0x75, 0xb5, 0x82, 0x82, 0xab, 0xba, 0xbd, 0xdf, 0x0d, 0x7e, 0x53,
- 0x39, 0x84, 0x8d, 0x8c, 0x2e, 0xa6, 0xc3, 0xa4, 0x3c, 0x68, 0x5a, 0x8c, 0xff, 0x47, 0xca, 0xca,
- 0x27, 0x43, 0x5a, 0x7b, 0x0b, 0xbe, 0xff, 0x02, 0x7d, 0x42, 0xe6, 0x44, 0xb5, 0x73, 0xdc, 0xa9,
- 0x6d, 0x54, 0x0e, 0x4e, 0x04, 0x24, 0x01, 0x87, 0x6f, 0x10, 0x2b, 0x43, 0x08, 0xf2, 0x8a, 0xe7,
- 0x60, 0xb9, 0xd4, 0x09, 0xce, 0x66, 0x42, 0xde, 0xa7, 0xa6, 0xaa, 0x4a, 0xc7, 0x81, 0x5b, 0xdc,
- 0x66, 0xd0, 0x7a, 0x90, 0x24, 0xf5, 0x6a, 0xf1, 0x7e, 0xe8, 0x35, 0x0d, 0x66, 0x15, 0x9b, 0x54,
- 0xe8, 0xbe, 0x99, 0xcf, 0x59, 0x0f, 0x30, 0x43, 0x36, 0x6c, 0xb0, 0xb9, 0xf5, 0xcc, 0x32, 0x19,
- 0x11, 0x06, 0x6c, 0x7f, 0xec, 0x34, 0x0c, 0xf6, 0xab, 0x31, 0xaa, 0xe0, 0xd5, 0xd4, 0x99, 0xd7,
- 0x39, 0x22, 0x3f, 0xa8, 0x7e, 0x79, 0xf1, 0x0e, 0x33, 0x0b, 0xe2, 0x28, 0xbf, 0xfb, 0x94, 0x3c,
- 0x58, 0xf8, 0x79, 0xb3, 0x4b, 0xbc, 0x1c, 0x50, 0xe9, 0x39, 0x41, 0xd5, 0xe3, 0x6c, 0x5c, 0x07,
- 0x9a, 0x12, 0x74, 0x71, 0x54, 0xaf, 0x14, 0x3a, 0x67, 0x0b, 0xb8, 0x40, 0xe1, 0x64, 0x96, 0x2a,
- 0x28, 0x9a, 0x86, 0xe6, 0x0f, 0x48, 0x57, 0x60, 0xd9, 0xf4, 0x95, 0xd5, 0x02, 0xa7, 0x80, 0x2c,
- 0xfd, 0x33, 0xf5, 0xb7, 0xc6, 0x30, 0xf4, 0x1f, 0xee, 0xdc, 0x60, 0xcc, 0x8a, 0xfa, 0x85, 0x23,
- 0x00, 0x3a, 0x04, 0xc0, 0xf3, 0x8f, 0xd6, 0x59, 0xf5, 0x1a, 0xcf, 0x07, 0xaf, 0xac, 0xab, 0x01,
- 0x5b, 0xf7, 0x3d, 0x5b, 0xeb, 0xf4, 0x01, 0xf3, 0xa3, 0x1f, 0xb9, 0xea, 0xf1, 0xcc, 0xb4, 0x10,
- 0x46, 0x2f, 0x46, 0xb3, 0xd2, 0x36, 0x40, 0x9c, 0x8c, 0xa4, 0xdc, 0xb3, 0x8c, 0xfc, 0xa8, 0xdd,
- 0xce, 0x82, 0xe3, 0x4c, 0x08, 0xf7, 0x94, 0x0a, 0x4d, 0x92, 0x1e, 0x62, 0xfb, 0xfa, 0x90, 0xf4,
- 0x10, 0x4e, 0x65, 0x04, 0x7b, 0x8e, 0xd7, 0x18, 0x02, 0x24, 0xf5, 0xf3, 0x93, 0xe8, 0x5b, 0x00,
- 0x94, 0xc8, 0xbb, 0x7e, 0xd6, 0x7b, 0xa5, 0x85, 0x3f, 0x56, 0xe1, 0x37, 0xb0, 0x47, 0x98, 0x5d,
- 0x9e, 0x22, 0x7e, 0x25, 0x3a, 0x7c, 0x44, 0xb1, 0xbf, 0xfd, 0x09, 0x61, 0xbb, 0x86, 0x45, 0xa4,
- 0xbc, 0x7c, 0x6c, 0xb3, 0x25, 0xb1, 0x45, 0x5c, 0x92, 0x3e, 0x4b, 0xf4, 0xa3, 0x7f, 0x5d, 0x0a,
- 0x58, 0xee, 0x28, 0xbc, 0xac, 0x77, 0x4f, 0xcf, 0xb8, 0x72, 0x1d, 0x2c, 0x2c, 0x2e, 0x3d, 0x41,
- 0xb7, 0xe3, 0x77, 0xe4, 0x31, 0xdd, 0x6e, 0xf2, 0x6a, 0x20, 0x0b, 0x2a, 0x55, 0xdf, 0x29, 0x9a,
- 0xfd, 0xf9, 0x15, 0x2b, 0x3e, 0xe9, 0xa8, 0xb3, 0xff, 0x85, 0x4c, 0x53, 0xb7, 0x8a, 0xb8, 0x99,
- 0xde, 0x88, 0x27, 0xa6, 0xa9, 0xd2, 0x4a, 0xe1, 0xac, 0xb4, 0xff, 0x12, 0xc8, 0x55, 0xe2, 0x58,
- 0x95, 0xf5, 0xdd, 0x3d, 0xcf, 0xa0, 0xba, 0x8a, 0x20, 0xb7, 0xe8, 0x2b, 0x7e, 0xd9, 0x5a, 0x07,
- 0xa0, 0x1f, 0xec, 0x0f, 0x89, 0x1c, 0xc4, 0xae, 0xcd, 0xdd, 0x97, 0x08, 0x02, 0xca, 0x02, 0x70,
- 0x24, 0xc4, 0x83, 0xcb, 0xc8, 0x19, 0x52, 0x6f, 0xe7, 0x9a, 0x05, 0xa7, 0x89, 0xa4, 0xc1, 0xc4,
- 0x15, 0x12, 0x95, 0x04, 0x16, 0xc8, 0x07, 0xe2, 0xb2, 0x76, 0x5c, 0x67, 0x96, 0x35, 0x23, 0xda,
- 0x1a, 0xd7, 0xe8, 0xb5, 0xa9, 0x98, 0x31, 0x5f, 0x6d, 0xfd, 0xae, 0xf1, 0xc2, 0x44, 0x49, 0x7f,
- 0x58, 0x9b, 0x07, 0x4c, 0x84, 0xf4, 0x24, 0x70, 0x1e, 0xe0, 0xfb, 0xa3, 0xa1, 0xfc, 0x6c, 0x8d,
- 0xaa, 0x2f, 0xef, 0xa7, 0x2d, 0x2f, 0x01, 0x2b, 0xed, 0x73, 0xf6, 0xc6, 0x89, 0x52, 0x2e, 0xf5,
- 0x91, 0x87, 0x00, 0x79, 0x3a, 0xec, 0xb9, 0xe9, 0x71, 0x98, 0xdf, 0x7b, 0x01, 0x8e, 0x21, 0x1f,
- 0x50, 0xab, 0xd4, 0x2a, 0x82, 0x62, 0xbf, 0x8a, 0x8d, 0x24, 0x13, 0x95, 0xd0, 0xe9, 0x93, 0x39,
- 0x3e, 0x73, 0x1a, 0x4e, 0xb4, 0x41, 0xca, 0x08, 0x79, 0xea, 0x14, 0x29, 0xaa, 0x0d, 0xff, 0x12,
- 0x85, 0x5c, 0xc2, 0x5e, 0xea, 0x54, 0xa2, 0x4c, 0xf1, 0x3f, 0xdc, 0x73, 0x38, 0x12, 0xec, 0x02,
- 0x67, 0x8e, 0x7b, 0xca, 0x41, 0x15, 0xfe, 0xa1, 0x59, 0x12, 0x5d, 0xd4, 0x23, 0x12, 0x19, 0x81,
- 0x2c, 0x58, 0x5b, 0x1a, 0x78, 0x51, 0xe3, 0xb7, 0xb2, 0xdc, 0xbd, 0x9b, 0xa4, 0x74, 0x6d, 0xa5,
- 0xda, 0x5d, 0x6c, 0xbf, 0x0c, 0x50, 0xd4, 0xf9, 0x34, 0xab, 0x9f, 0x2f, 0xc2, 0x81, 0x48, 0x2f,
- 0x09, 0x23, 0x0f, 0xbf, 0x58, 0x07, 0x20, 0x53, 0x88, 0xe1, 0x54, 0x1e, 0x17, 0xe9, 0x04, 0xdf,
- 0x48, 0xc3, 0x04, 0x89, 0xa9, 0x5e, 0x4f, 0x0e, 0xb8, 0xc4, 0x67, 0x0d, 0x7e, 0x55, 0xe6, 0x1b,
- 0x1a, 0x3e, 0xd4, 0x1f, 0x94, 0xf4, 0x56, 0x2f, 0x70, 0x68, 0x6d, 0xa0, 0xaa, 0xa0, 0x5b, 0xf2,
- 0x97, 0xa7, 0x0a, 0x56, 0x7a, 0xa3, 0x4b, 0x9d, 0x48, 0xce, 0xe0, 0xac, 0xe2, 0x1e, 0xb4, 0x73,
- 0x55, 0xdd, 0xad, 0x09, 0xb0, 0x5a, 0x6d, 0x8c, 0x34, 0xd0, 0x20, 0x6b, 0x71, 0x18, 0x4c, 0xb9,
- 0x7f, 0x8e, 0xdc, 0x05, 0x2d, 0xea, 0x77, 0xe5, 0xa4, 0xab, 0xbb, 0x33, 0xb9, 0x03, 0x87, 0x62,
- 0x60, 0x13, 0xfd, 0x3b, 0x4e, 0x3f, 0x20, 0x1c, 0xb2, 0x11, 0x42, 0xda, 0xc7, 0xe5, 0x1c, 0x4e,
- 0x40, 0xfd, 0x61, 0xa6, 0x07, 0x51, 0x97, 0x91, 0x31, 0xd1, 0xf6, 0xe7, 0xed, 0xaa, 0x56, 0xcf,
- 0x91, 0x17, 0xa5, 0x7f, 0x7e, 0xce, 0xd2, 0x31, 0x54, 0xb7, 0xca, 0xf8, 0xdd, 0x05, 0x4a, 0xf5,
- 0x81, 0xd3, 0x6b, 0x49, 0x18, 0x57, 0xfa, 0x0e, 0x9b, 0xdb, 0xf5, 0x16, 0x51, 0xc4, 0xa4, 0x4a,
- 0xe6, 0x64, 0x86, 0xe7, 0x2b, 0x66, 0x53, 0x1e, 0x71, 0xe7, 0x37, 0xf3, 0xb6, 0x06, 0x0e, 0x3e,
- 0x98, 0x09, 0x9e, 0x97, 0xc6, 0x26, 0xc8, 0x3f, 0x4a, 0x27, 0xbc, 0xd5, 0x32, 0x0b, 0x9c, 0xba,
- 0xe1, 0xc7, 0xaf, 0x1f, 0x30, 0x3d, 0xf2, 0xf0, 0x4f, 0x34, 0x45, 0x88, 0x3f, 0xb5, 0x7c, 0x44,
- 0xc2, 0x68, 0x5e, 0xe0, 0x36, 0x3a, 0x82, 0x93, 0xd7, 0x89, 0xb6, 0xbd, 0x2b, 0xb9, 0x02, 0x9d,
- 0x31, 0x55, 0x30, 0xf6, 0xe2, 0x7f, 0x1e, 0x65, 0x70, 0xf6, 0x41, 0x7f, 0x33, 0x3c, 0xa2, 0x31,
- 0x35, 0x66, 0x1b, 0x51, 0xb2, 0xa0, 0xf8, 0x9a, 0x8a, 0xa9, 0xa8, 0x48, 0x6d, 0x8b, 0xeb, 0x70,
- 0x46, 0x55, 0xd5, 0x81, 0x0b, 0xdf, 0x3f, 0xe5, 0xf7, 0xb4, 0xd1, 0x58, 0xe5, 0x7e, 0xc3, 0xc5,
- 0x69, 0x19, 0xa7, 0xdf, 0xc0, 0x4c, 0xf0, 0x05, 0x2c, 0x8b, 0xbb, 0x01, 0xe2, 0x21, 0x96, 0x57,
- 0x06, 0x22, 0xe1, 0xcf, 0x59, 0x61, 0x8a, 0x7f, 0x9c, 0x30, 0xf1, 0x63, 0xca, 0x47, 0xfd, 0x77,
- 0xf0, 0x00, 0xff, 0xa0, 0xe8, 0xd4, 0xc1, 0x9c, 0xb9, 0xba, 0x48, 0xb9, 0x3d, 0xef, 0x54, 0xd7,
- 0xe3, 0x8c, 0x25, 0x3a, 0x2b, 0x8d, 0x1c, 0x67, 0xc7, 0xe9, 0xf4, 0x22, 0x37, 0xa9, 0xa7, 0x9f,
- 0xd9, 0x0c, 0x4d, 0xea, 0x84, 0x70, 0xfb, 0x7f, 0x8c, 0x7d, 0xbe, 0x28, 0x88, 0x50, 0xff, 0x87,
- 0xcd, 0x85, 0x5f, 0x15, 0xac, 0xc2, 0x97, 0xb0, 0x6e, 0x83, 0x9b, 0xe5, 0x7e, 0xc2, 0x54, 0x38,
- 0x0b, 0xeb, 0x7a, 0x22, 0xb2, 0xe7, 0x1f, 0x3d, 0xe6, 0x7f, 0x2e, 0x34, 0x5f, 0xea, 0x27, 0x7e,
- 0x17, 0xd5, 0xf1, 0xcc, 0x25, 0x90, 0x9d, 0xa3, 0x87, 0xf8, 0x3b, 0xf3, 0x3e, 0x55, 0x3a, 0xbd,
- 0xdd, 0x76, 0x26, 0x30, 0x45, 0xa1, 0x2c, 0x1f, 0x2b, 0x64, 0xd2, 0xf1, 0x1a, 0x6d, 0x54, 0x53,
- 0x55, 0x5e, 0xde, 0x63, 0x86, 0x90, 0x6b, 0x37, 0x29, 0xc2, 0xb1, 0x75, 0x82, 0xf6, 0x59, 0xc2,
- 0x40, 0xc1, 0x95, 0x6f, 0x85, 0xbc, 0x22, 0x64, 0x97, 0xba, 0x56, 0x63, 0x9b, 0x3f, 0xe8, 0xda,
- 0x68, 0xe1, 0xed, 0x4c, 0x53, 0xb8, 0x8f, 0x12, 0x59, 0x12, 0xf1, 0x52, 0x91, 0x06, 0x17, 0x01,
- 0x64, 0xa8, 0xe2, 0xa7, 0x48, 0xb7, 0x99, 0x00, 0x6f, 0x67, 0x59, 0x3d, 0x82, 0x34, 0xfe, 0x7d,
- 0x82, 0xd9, 0x79, 0x4a, 0xbd, 0xad, 0x91, 0x3c, 0xb2, 0xd2, 0xde, 0x1e, 0x46, 0xae, 0xd0, 0x2b,
- 0xe7, 0x2f, 0x60, 0x72, 0x0b, 0x07, 0xc8, 0x05, 0x4b, 0xed, 0xeb, 0x31, 0x83, 0x9d, 0x48, 0x06,
- 0x24, 0x4f, 0x9c, 0xcb, 0x35, 0x63, 0x1c, 0x01, 0x8f, 0x75, 0xa1, 0x65, 0xd1, 0xac, 0xe1, 0x26,
- 0x92, 0x43, 0xb8, 0x2d, 0x1a, 0x30, 0xf9, 0x9f, 0x82, 0xdc, 0xbf, 0x84, 0xc4, 0x72, 0x2b, 0x42,
- 0x9e, 0xc9, 0x55, 0x14, 0x35, 0xf3, 0x40, 0xbb, 0x20, 0x8a, 0xbf, 0x2c, 0x3a, 0x2f, 0x80, 0x00,
- 0xe3, 0x80, 0x0f, 0x91, 0x7a, 0xfd, 0xf6, 0xf2, 0x36, 0x24, 0x42, 0x36, 0xdd, 0xdd, 0xf3, 0x68,
- 0x7a, 0xf3, 0x75, 0x63, 0x50, 0x0b, 0x34, 0x22, 0x70, 0xa3, 0x51, 0x9a, 0x2f, 0x47, 0xbf, 0x76,
- 0x26, 0x74, 0x3e, 0xf2, 0x9b, 0x4b, 0x7a, 0x82, 0x2b, 0x48, 0x99, 0x90, 0x91, 0xd4, 0xb4, 0xc4,
- 0xcd, 0x09, 0xe0, 0x56, 0x1f, 0x0b, 0x88, 0x2f, 0xfb, 0xc7, 0x41, 0x39, 0x2e, 0x98, 0xd3, 0xc1,
- 0x9b, 0xd2, 0xba, 0x9d, 0xd3, 0xf3, 0x08, 0xce, 0x64, 0x0f, 0x85, 0xd1, 0x17, 0x6d, 0x11, 0xbf,
- 0x1b, 0x07, 0x07, 0x6d, 0x1d, 0x4b, 0x71, 0xd0, 0x86, 0xa6, 0x30, 0x0f, 0x44, 0xa5, 0x6b, 0x41,
- 0x78, 0x9e, 0xe8, 0xc9, 0x1c, 0xa0, 0x54, 0x04, 0x4a, 0x8b, 0x7f, 0x1b, 0x41, 0xe3, 0x13, 0xe3,
- 0xca, 0xf1, 0x4b, 0x6a, 0xa4, 0x16, 0x77, 0x02, 0xe2, 0x69, 0x8d, 0x02, 0x5a, 0xe2, 0x46, 0x29,
- 0x3e, 0xee, 0x14, 0x59, 0xd0, 0x05, 0x9a, 0x67, 0xda, 0x01, 0x0a, 0xce, 0x95, 0xb3, 0x90, 0xef,
- 0x47, 0x3d, 0x86, 0xab, 0xa3, 0xed, 0x71, 0xa7, 0xb7, 0x3e, 0xfd, 0x88, 0x6a, 0xe8, 0xf1, 0x1e,
- 0x65, 0x63, 0x39, 0x3f, 0x06, 0x9b, 0x81, 0x6c, 0x22, 0x69, 0x67, 0xb9, 0x02, 0x1b, 0x16, 0x5e,
- 0xe8, 0x7b, 0xf7, 0x5c, 0x37, 0x78, 0x0c, 0x84, 0x43, 0xef, 0x4d, 0xf7, 0xf0, 0xe6, 0x3d, 0xde,
- 0x8c, 0xbb, 0x7d, 0xcc, 0xe3, 0x3a, 0xf8, 0x97, 0xab, 0xe8, 0xed, 0xdf, 0x67, 0x46, 0xfc, 0x6f,
- 0x07, 0x02, 0xaa, 0x83, 0xbe, 0xd0, 0x0b, 0xe3, 0x7d, 0x4f, 0xaa, 0xf1, 0x1d, 0x70, 0x5b, 0x7b,
- 0xb4, 0xab, 0x35, 0xc3, 0x3e, 0x36, 0x8b, 0xb0, 0x18, 0x3d, 0x3c, 0x89, 0x3d, 0x3b, 0xdf, 0x89,
- 0xed, 0x6c, 0x21, 0xc3, 0xc9, 0x57, 0x11, 0x42, 0x55, 0xb2, 0x51, 0x7b, 0x5e, 0x04, 0x8c, 0x20,
- 0xea, 0xa0, 0xfd, 0x57, 0xf4, 0x2e, 0x5f, 0xee, 0x07, 0x10, 0xd5, 0xa9, 0x89, 0x23, 0x84, 0x5c,
- 0x7d, 0x12, 0x8b, 0x83, 0x70, 0x77, 0x40, 0x5a, 0x60, 0xa3, 0x13, 0x9d, 0x14, 0x5f, 0xaf, 0x74,
- 0x83, 0xfe, 0xda, 0xcc, 0xf7, 0xfb, 0x7d, 0x62, 0xbd, 0x42, 0x55, 0x44, 0xc5, 0xde, 0x55, 0xd3,
- 0xb0, 0x0b, 0xd3, 0xea, 0x7d, 0x96, 0xe5, 0xee, 0xe1, 0x45, 0x6d, 0xe0, 0x3d, 0x9e, 0x62, 0xd4,
- 0xef, 0xb5, 0x0a, 0x32, 0x05, 0xcd, 0x38, 0x99, 0x61, 0xdd, 0xf6, 0xf3, 0x85, 0xce, 0x1a, 0xb3,
- 0x57, 0xfc, 0xd1, 0x63, 0x7c, 0x84, 0xb6, 0xa2, 0x84, 0xf4, 0x3e, 0x34, 0xb9, 0x3f, 0xb9, 0x8e,
- 0xd0, 0x30, 0x23, 0x0a, 0x27, 0x3c, 0x19, 0xc6, 0xd2, 0x8e, 0xb9, 0x55, 0xb7, 0x34, 0xab, 0x60,
- 0x52, 0xd3, 0x45, 0x09, 0xde, 0x0b, 0x41, 0x66, 0x04, 0x71, 0x1e, 0x4e, 0xba, 0x09, 0x7b, 0xab,
- 0x3a, 0x85, 0x7d, 0xfc, 0x95, 0x9b, 0x71, 0xb9, 0x78, 0x3f, 0x41, 0x44, 0x5c, 0xd2, 0x5f, 0x9f,
- 0xe7, 0xc7, 0xf4, 0x6c, 0x52, 0x07, 0xda, 0xb2, 0x39, 0xc8, 0xd9, 0x77, 0x60, 0x12, 0xd3, 0x7b,
- 0x70, 0x5a, 0x7e, 0x66, 0xb1, 0x0b, 0x4e, 0x86, 0xa4, 0x31, 0x47, 0x1c, 0x72, 0x8a, 0x89, 0x96,
- 0x8e, 0x24, 0xa4, 0x1f, 0x07, 0x11, 0x50, 0xc3, 0x05, 0x77, 0x82, 0xfa, 0x98, 0xba, 0xec, 0xa0,
- 0x71, 0x59, 0x95, 0x6f, 0xa3, 0x2d, 0x1f, 0x26, 0xc0, 0x73, 0x2e, 0x13, 0x38, 0xdc, 0x57, 0x46,
- 0xec, 0x4d, 0x4f, 0x11, 0xa4, 0x35, 0x5e, 0x37, 0x0e, 0x1b, 0xe7, 0x32, 0x02, 0xf8, 0x81, 0x67,
- 0xb1, 0x51, 0x1f, 0x34, 0xe5, 0xad, 0xa0, 0x07, 0xd8, 0xc0, 0xae, 0x52, 0xed, 0x4e, 0xbe, 0x6e,
- 0xe8, 0x92, 0x85, 0x76, 0x8d, 0x71, 0xd6, 0xac, 0x21, 0x61, 0x14, 0x75, 0xf3, 0xb7, 0x66, 0x8e,
- 0xf5, 0xd1, 0x8b, 0x7a, 0xfd, 0xc6, 0x39, 0x2d, 0x0a, 0x0e, 0x63, 0x86, 0x1e, 0x0c, 0x55, 0xbc,
- 0xf3, 0x52, 0xf8, 0x8e, 0x9e, 0x94, 0xae, 0xa9, 0x29, 0x28, 0x98, 0x8c, 0x64, 0x2a, 0x8c, 0x87,
- 0x21, 0x01, 0x5d, 0xd3, 0x79, 0xbf, 0x09, 0x1f, 0x8c, 0xe4, 0xa2, 0xf7, 0xc6, 0x49, 0xa9, 0xe1,
- 0xea, 0x6d, 0x6d, 0xc6, 0x40, 0x4a, 0x02, 0x25, 0x2a, 0xb2, 0xc5, 0x29, 0x87, 0x00, 0x21, 0x40,
- 0x88, 0x6b, 0x18, 0xea, 0x19, 0x09, 0xec, 0x39, 0x54, 0x33, 0xea, 0x10, 0x6b, 0x5a, 0x10, 0x50,
- 0x3b, 0x5a, 0xd6, 0x1e, 0x12, 0x02, 0xc4, 0x09, 0x12, 0x01, 0xc1, 0x2a, 0x31, 0xd1, 0x73, 0xa3,
- 0xf8, 0xcf, 0x28, 0x05, 0xe5, 0xb3, 0x46, 0x90, 0x35, 0xf2, 0x7f, 0xd5, 0x1b, 0x5f, 0xe5, 0x11,
- 0x5a, 0x47, 0x6f, 0xa0, 0xf8, 0x59, 0x94, 0xeb, 0xd7, 0x08, 0x64, 0x6f, 0x3a, 0x97, 0x86, 0xeb,
- 0xad, 0xa0, 0x72, 0x8d, 0xac, 0x55, 0xc5, 0xd1, 0xd4, 0xa0, 0xb9, 0x0e, 0xc0, 0x9b, 0x03, 0xd3,
- 0x01, 0xef, 0xdd, 0xa9, 0x2a, 0x98, 0x11, 0xfa, 0xd6, 0x2b, 0xc2, 0x51, 0xe8, 0xed, 0x0e, 0x34,
- 0x2a, 0x16, 0x04, 0xbf, 0x6f, 0x46, 0x15, 0x57, 0x26, 0xee, 0xd1, 0x6b, 0xd9, 0x06, 0x1d, 0x8c,
- 0x52, 0xf3, 0xa0, 0x56, 0xe8, 0x5d, 0xb2, 0xbd, 0x95, 0x0f, 0x08, 0x14, 0xa0, 0x5b, 0x08, 0xd9,
- 0x89, 0x21, 0x38, 0x39, 0x5f, 0x1a, 0x22, 0xc1, 0x20, 0x00, 0x8f, 0x98, 0x8d, 0xd1, 0x5e, 0xc7,
- 0xc0, 0x97, 0x59, 0xb4, 0xe4, 0xe5, 0x69, 0xbd, 0x33, 0x75, 0xbe, 0x86, 0x0d, 0xbb, 0x28, 0xe0,
- 0x3e, 0xf5, 0x09, 0xb7, 0x8f, 0xbd, 0xca, 0x27, 0x5d, 0x1d, 0x9b, 0x80, 0x89, 0x44, 0xc2, 0xc6,
- 0xc6, 0x93, 0x9c, 0x3f, 0x1e, 0x5d, 0x41, 0xc4, 0xb3, 0x73, 0x1f, 0x22, 0x0d, 0x49, 0x6b, 0x68,
- 0x5d, 0xb2, 0x4a, 0xba, 0x9e, 0xe8, 0x63, 0x3c, 0xa3, 0x67, 0x59, 0x5e, 0xea, 0x88, 0x35, 0xbf,
- 0xc4, 0xfe, 0xb4, 0xa5, 0x93, 0x1f, 0x1e, 0x8e, 0x79, 0x5e, 0x0c, 0x64, 0x12, 0x9e, 0xf5, 0x04,
- 0xf2, 0x9c, 0x29, 0x01, 0xb9, 0xf3, 0xc2, 0x33, 0xa5, 0xbb, 0xc5, 0x1f, 0x72, 0x1c, 0x73, 0x78,
- 0xc1, 0x21, 0x50, 0x1d, 0x41, 0x47, 0xad, 0x5c, 0x0e, 0x7b, 0x55, 0xb9, 0x75, 0x8f, 0x56, 0xd3,
- 0x0d, 0xb2, 0x4c, 0x61, 0x40, 0x83, 0xe8, 0xd7, 0xa6, 0x7b, 0x67, 0xd6, 0xac, 0x60, 0xb2, 0x04,
- 0x6d, 0x1c, 0x3a, 0x59, 0x28, 0x20, 0x23, 0x6a, 0xdc, 0x1c, 0x59, 0xc2, 0x0f, 0xc4, 0xb4, 0xe9,
- 0x31, 0xec, 0x91, 0xa8, 0x31, 0xb9, 0x28, 0x86, 0xb4, 0xe4, 0x15, 0xf2, 0x71, 0x71, 0xcc, 0xfc,
- 0x7d, 0xf7, 0x6d, 0x6a, 0x21, 0x1b, 0x36, 0x35, 0x3e, 0xe9, 0x81, 0x3b, 0x65, 0xdd, 0x2b, 0x59,
- 0xd6, 0x26, 0xf3, 0xb0, 0x02, 0xc8, 0x89, 0x4a, 0xf8, 0x12, 0x87, 0x97, 0xb8, 0x05, 0x8d, 0xea,
- 0xff, 0x07, 0xe6, 0x22, 0x58, 0x34, 0x4c, 0x13, 0xf1, 0x9e, 0xf4, 0x39, 0x49, 0x60, 0x92, 0x63,
- 0x21, 0x53, 0x17, 0x2d, 0x48, 0x18, 0xf4, 0x19, 0x71, 0xf1, 0xae, 0x18, 0x67, 0x33, 0xbc, 0x97,
- 0xcf, 0x83, 0x5f, 0x05, 0xf1, 0xe6, 0x61, 0x07, 0x1d, 0x8c, 0xd6, 0x6e, 0x5a, 0xb9, 0xdd, 0xdc,
- 0xa7, 0x58, 0x25, 0xa2, 0x32, 0xee, 0x48, 0x49, 0x86, 0x1b, 0x15, 0x5e, 0x56, 0x31, 0x91, 0x28,
- 0x94, 0xf8, 0xde, 0x07, 0x70, 0x30, 0x98, 0x67, 0xa9, 0x47, 0xc0, 0x19, 0x82, 0xcf, 0x0b, 0x55,
- 0x2a, 0xe6, 0x7f, 0xd2, 0x96, 0x14, 0x2a, 0xbe, 0xb5, 0x4b, 0x82, 0xe7, 0x80, 0x4b, 0x11, 0xeb,
- 0x25, 0xfe, 0xdd, 0xc8, 0xdc, 0xb6, 0xa2, 0x74, 0x8c, 0x61, 0xab, 0xc5, 0x08, 0x4a, 0xcd, 0x51,
- 0x94, 0x2b, 0xf6, 0xcc, 0x1c, 0x09, 0xc7, 0x84, 0xb5, 0x96, 0x24, 0xdf, 0x5a, 0x2d, 0x73, 0xb0,
- 0xe1, 0xaa, 0x19, 0xca, 0x0f, 0x31, 0x28, 0xd1, 0xea, 0xe4, 0x48, 0x12, 0x0b, 0xe0, 0xb5, 0x31,
- 0x70, 0x58, 0xd9, 0x80, 0xf1, 0x31, 0xff, 0xa3, 0x60, 0x0c, 0x58, 0x7d, 0x18, 0x06, 0x4d, 0x54,
- 0x04, 0x3e, 0x8d, 0xb1, 0x5b, 0x4c, 0xde, 0x1c, 0x35, 0xf7, 0xab, 0x5a, 0x5e, 0x1e, 0x25, 0x41,
- 0x22, 0xc4, 0xd7, 0x46, 0x52, 0x6c, 0xe3, 0xbf, 0xd6, 0xc0, 0x4a, 0x9a, 0x66, 0x0f, 0xe0, 0xa9,
- 0xcb, 0x0f, 0x7b, 0xcb, 0x3e, 0xa2, 0x8f, 0xd3, 0x93, 0x2c, 0xec, 0x92, 0xf1, 0x51, 0x51, 0x6f,
- 0x5e, 0x84, 0x4c, 0x41, 0x07, 0x8c, 0xa6, 0x82, 0x63, 0x80, 0x7e, 0x95, 0x94, 0xaf, 0x63, 0xc6,
- 0x2a, 0x26, 0x0d, 0x01, 0x8d, 0x6a, 0x86, 0x7c, 0xaf, 0x55, 0x3b, 0x6b, 0xc6, 0x81, 0xfb, 0xe8,
- 0x64, 0x12, 0xef, 0x81, 0x38, 0x2b, 0xaf, 0xd9, 0x57, 0x56, 0xb6, 0xe2, 0x83, 0x7e, 0x7d, 0x19,
- 0x63, 0xd5, 0x10, 0x4f, 0x14, 0xfe, 0xb0, 0x57, 0x87, 0x5e, 0x6e, 0xe7, 0xb3, 0xb6, 0xd3, 0x0d,
- 0x6e, 0x18, 0xcf, 0xa5, 0x0f, 0x5d, 0x71, 0x8d, 0x6b, 0xc7, 0xb4, 0xb1, 0x54, 0x0e, 0xe4, 0x2d,
- 0xf2, 0xff, 0x0a, 0xa0, 0x75, 0xee, 0xc7, 0x37, 0xd0, 0xbd, 0xba, 0xd7, 0x35, 0x89, 0xf8, 0x7d,
- 0x4b, 0x32, 0x83, 0x4f, 0x41, 0xca, 0xd9, 0xc7, 0x4b, 0xee, 0x1d, 0x95, 0xf7, 0xab, 0xdf, 0x8f,
- 0x53, 0xaf, 0xac, 0x77, 0x47, 0xea, 0x92, 0x47, 0xa4, 0x25, 0xd7, 0x19, 0x8c, 0x99, 0xf7, 0x59,
- 0x74, 0xb4, 0x9b, 0xe2, 0xcc, 0x6c, 0x56, 0xdc, 0xc1, 0x30, 0xa1, 0x85, 0x5b, 0xdd, 0xfa, 0x91,
- 0x59, 0x2d, 0xd9, 0xce, 0x93, 0x0c, 0x31, 0xa8, 0x85, 0xcf, 0xb3, 0xb4, 0x64, 0x32, 0xa3, 0x7b,
- 0xc7, 0xd4, 0x16, 0xc2, 0x57, 0x20, 0x60, 0x9b, 0x5b, 0x79, 0x4a, 0xab, 0xe1, 0xc3, 0x41, 0x30,
- 0xc9, 0xe2, 0x4d, 0x60, 0x8f, 0xab, 0x0a, 0xbf, 0x42, 0x80, 0xc2, 0xc6, 0x51, 0xa2, 0xa2, 0x6a,
- 0x9d, 0x5f, 0xab, 0x69, 0x7f, 0x5c, 0x7d, 0x3a, 0x13, 0xce, 0x99, 0x31, 0x55, 0x59, 0x09, 0x89,
- 0xda, 0x17, 0x7d, 0x1e, 0xea, 0x7a, 0xe0, 0x75, 0x4b, 0xba, 0xb1, 0x93, 0xbc, 0xc7, 0xc5, 0x84,
- 0xc7, 0x15, 0xb0, 0x9e, 0xc1, 0xd5, 0x36, 0x67, 0xe6, 0x27, 0xb4, 0xb2, 0xcc, 0xd8, 0x9b, 0x8d,
- 0x58, 0x62, 0x90, 0x3b, 0x89, 0x3c, 0x84, 0x0a, 0x69, 0x7a, 0xc9, 0x24, 0x52, 0xf3, 0x50, 0x51,
- 0x23, 0x52, 0x0d, 0x3d, 0xbf, 0x12, 0x0a, 0x92, 0x50, 0xae, 0xb1, 0xb5, 0xa9, 0xc9, 0x46, 0x0c,
- 0xf6, 0x09, 0xdc, 0x86, 0x6b, 0x67, 0x2e, 0x8d, 0x8d, 0x93, 0x21, 0x85, 0x34, 0xdb, 0x98, 0x21,
- 0x6a, 0x32, 0xa1, 0x9d, 0xec, 0x09, 0xc0, 0x92, 0x60, 0x65, 0xd8, 0xad, 0xad, 0x7b, 0xda, 0xd6,
- 0xb2, 0xe5, 0xe5, 0x33, 0xd0, 0xe6, 0x85, 0x9e, 0xf6, 0x34, 0xba, 0x5e, 0xf2, 0x9f, 0x05, 0x6e,
- 0x95, 0xd6, 0xfd, 0xc6, 0x18, 0x22, 0x74, 0x1a, 0x33, 0xa6, 0xad, 0x68, 0x13, 0x85, 0x05, 0xdc,
- 0xb3, 0xc1, 0x76, 0xee, 0xf5, 0x6f, 0xd9, 0x27, 0x82, 0xa5, 0x28, 0x80, 0xf7, 0x0d, 0xf9, 0x80,
- 0xeb, 0x41, 0x66, 0xe9, 0x7f, 0x53, 0x1c, 0x1d, 0x1c, 0x53, 0xfa, 0x55, 0xe6, 0xc0, 0x2b, 0x80,
- 0xe1, 0x47, 0x5a, 0xce, 0x4b, 0x6e, 0xab, 0x20, 0xa5, 0x43, 0x34, 0xec, 0x24, 0x12, 0xc8, 0x40,
- 0x86, 0x54, 0x82, 0x46, 0xe4, 0x1f, 0x8b, 0x0b, 0x5f, 0x54, 0xa1, 0xfc, 0xfd, 0xee, 0x71, 0x64,
- 0x49, 0xc8, 0xd7, 0x38, 0x89, 0xea, 0x6e, 0xf4, 0x66, 0x8d, 0x1c, 0xee, 0x8d, 0xa8, 0xa0, 0x6c,
- 0x15, 0xdc, 0xe6, 0x41, 0xac, 0x6b, 0x9a, 0xbb, 0x9e, 0xe7, 0x10, 0xea, 0x6e, 0x37, 0xe1, 0x9f,
- 0x3d, 0x17, 0xa5, 0x93, 0x54, 0x92, 0xc2, 0x2e, 0xe9, 0x08, 0x57, 0x6c, 0x46, 0xff, 0x2e, 0xd9,
- 0x80, 0x03, 0xdf, 0x99, 0xa4, 0xf4, 0xde, 0x11, 0xc6, 0x5b, 0xe0, 0x88, 0x0f, 0x87, 0x6b, 0x20,
- 0x61, 0xf5, 0x37, 0x74, 0x64, 0x35, 0x62, 0xb9, 0x36, 0xcc, 0x95, 0x2a, 0xaf, 0x0e, 0x95, 0x09,
- 0xe2, 0x61, 0xb2, 0xa3, 0x85, 0x21, 0x24, 0xd6, 0x5d, 0xeb, 0x7d, 0x13, 0xe4, 0xd9, 0x2e, 0xec,
- 0x64, 0x24, 0x2d, 0x01, 0x07, 0xc2, 0xba, 0x5c, 0xc1, 0x2a, 0x77, 0x88, 0xf0, 0x01, 0x75, 0xf1,
- 0x7b, 0xe3, 0x63, 0x67, 0x5a, 0x7c, 0x97, 0x61, 0x43, 0x36, 0x40, 0x43, 0x31, 0x40, 0x76, 0x2c,
- 0x26, 0x62, 0xb1, 0xc3, 0x82, 0xc3, 0xc1, 0xec, 0xe4, 0xd6, 0x3f, 0x57, 0x41, 0xfb, 0xbc, 0x00,
- 0xa4, 0x49, 0xf5, 0xd1, 0x16, 0x3a, 0x2b, 0x7c, 0x67, 0x52, 0x7a, 0x03, 0xa7, 0xf3, 0xb2, 0xa1,
- 0x31, 0x18, 0x67, 0x41, 0x26, 0x59, 0x26, 0xc9, 0x1f, 0x94, 0x37, 0x72, 0xfd, 0xf8, 0x75, 0xae,
- 0x63, 0xe2, 0x6b, 0xb0, 0x33, 0x6d, 0x14, 0x15, 0xf3, 0x63, 0xc4, 0xe0, 0x10, 0x77, 0xf8, 0xc8,
- 0x3b, 0xc2, 0xd5, 0x5a, 0x8a, 0x6f, 0xea, 0x2a, 0xa2, 0xa0, 0xcf, 0x2f, 0xd2, 0xaf, 0x03, 0x51,
- 0x97, 0x31, 0x55, 0x75, 0x4e, 0xa3, 0xa5, 0xe7, 0x2b, 0xb9, 0x1f, 0x31, 0x23, 0x78, 0x7f, 0xff,
- 0x63, 0x63, 0x77, 0x5b, 0x28, 0x2d, 0xe1, 0x12, 0x6a, 0xe7, 0xf3, 0xca, 0xd0, 0x20, 0x18, 0x86,
- 0x9e, 0x1b, 0xbc, 0xb4, 0x0e, 0x94, 0xbb, 0x64, 0xf3, 0x38, 0x70, 0x55, 0x6b, 0xf4, 0x5f, 0xfb,
- 0x1c, 0x66, 0x4c, 0xb1, 0xe4, 0x7c, 0xea, 0x26, 0x39, 0x24, 0xe6, 0xda, 0x1f, 0x7e, 0x7f, 0x13,
- 0x18, 0xf1, 0x8b, 0x5d, 0x53, 0xd3, 0xc1, 0xf9, 0xe9, 0x7c, 0x4d, 0x62, 0xeb, 0x21, 0x63, 0x90,
- 0xe0, 0x5b, 0x14, 0x63, 0xed, 0xa6, 0xfc, 0x69, 0xd4, 0x29, 0x03, 0xb8, 0xfd, 0x14, 0x30, 0xd3,
- 0x45, 0x18, 0x40, 0x58, 0xb5, 0x93, 0xe7, 0x5e, 0x97, 0xcf, 0x77, 0x7a, 0x14, 0x5a, 0x9c, 0x92,
- 0xb5, 0xe0, 0x63, 0xa0, 0x89, 0x41, 0xf2, 0xfe, 0xe2, 0x96, 0x7e, 0x63, 0x70, 0xec, 0x72, 0x91,
- 0x57, 0x6b, 0xe1, 0x3e, 0x44, 0x87, 0xdd, 0x42, 0xd2, 0x41, 0x4e, 0x9e, 0x6d, 0x6f, 0x75, 0x87,
- 0xca, 0x35, 0xab, 0x46, 0xe3, 0xa4, 0x69, 0x55, 0x92, 0x60, 0x66, 0x26, 0x33, 0x66, 0xbd, 0x52,
- 0x64, 0x44, 0xcf, 0x67, 0x12, 0xaa, 0x65, 0x90, 0x39, 0xe6, 0x3b, 0x7d, 0xdf, 0x77, 0xb3, 0xaa,
- 0x4b, 0x31, 0x0f, 0x90, 0x76, 0x55, 0x7b, 0xd0, 0xfc, 0x6c, 0x44, 0x96, 0xd7, 0xf1, 0xd0, 0x4e,
- 0xa3, 0x6c, 0xf4, 0xf5, 0xdd, 0xa9, 0xb2, 0x79, 0x32, 0x9a, 0xc7, 0x71, 0xac, 0xd1, 0x88, 0x91,
- 0x11, 0x1b, 0x87, 0x08, 0x46, 0xca, 0x53, 0xed, 0x3c, 0x06, 0xed, 0x5f, 0xd7, 0xd5, 0xe9, 0x5b,
- 0xdb, 0xb9, 0xfa, 0xc1, 0x90, 0x2a, 0xb2, 0x75, 0xbb, 0xb4, 0xd3, 0xf7, 0xa2, 0xd7, 0x28, 0xbe,
- 0x5d, 0xa6, 0x1d, 0x02, 0x33, 0x6b, 0x43, 0x82, 0x08, 0x49, 0xe0, 0x62, 0x1c, 0x9d, 0x54, 0x1b,
- 0x6b, 0xa9, 0x75, 0xe5, 0xf8, 0x17, 0xf4, 0x0f, 0x1f, 0x8b, 0x5d, 0x02, 0x6c, 0xca, 0x2a, 0x99,
- 0x88, 0xa7, 0xcf, 0x05, 0xe9, 0x40, 0xe6, 0x46, 0xa5, 0xf6, 0x8a, 0x1c, 0x84, 0x1f, 0x2a, 0x17,
- 0x01, 0xc8, 0xd0, 0x9d, 0x9f, 0xd2, 0x41, 0x91, 0xe6, 0xdb, 0xd2, 0xc0, 0x9c, 0xf3, 0x27, 0xe1,
- 0x45, 0x75, 0x7d, 0x31, 0x25, 0x14, 0x8c, 0xc5, 0xb0, 0x76, 0x35, 0xa3, 0x93, 0xf4, 0xcc, 0xd8,
- 0xa1, 0x1e, 0x10, 0x5c, 0x17, 0x9d, 0x7d, 0xc1, 0x37, 0xb7, 0xa1, 0xd7, 0xbf, 0x3a, 0x58, 0x7e,
- 0x30, 0x3b, 0x24, 0xbd, 0x4d, 0xa7, 0x96, 0xa7, 0x5a, 0x48, 0xc6, 0x91, 0x7b, 0x03, 0x05, 0xf1,
- 0xa8, 0xd8, 0x1b, 0xd4, 0xf1, 0x3d, 0xc0, 0x02, 0x2d, 0xc8, 0xec, 0x74, 0x18, 0xc9, 0x77, 0xd0,
- 0x18, 0x2f, 0xba, 0x2e, 0x1b, 0x5b, 0xe8, 0x68, 0x7b, 0xec, 0xe7, 0xde, 0x59, 0xe0, 0x10, 0x9e,
- 0x9d, 0xd8, 0x7e, 0x41, 0x6d, 0xc3, 0x23, 0x21, 0x84, 0xa5, 0x90, 0xb9, 0x35, 0x69, 0x43, 0x0c,
- 0x03, 0xc2, 0x82, 0x52, 0xbe, 0x69, 0x2f, 0x25, 0x4c, 0x8b, 0x1b, 0x6f, 0xe9, 0xf4, 0x51, 0xce,
- 0xe7, 0xe4, 0x96, 0x57, 0x6b, 0x51, 0x6c, 0x2f, 0x1e, 0xd5, 0x4d, 0xea, 0xdf, 0xbf, 0x06, 0x12,
- 0x84, 0x9d, 0xe5, 0x7e, 0x98, 0x49, 0xff, 0xa5, 0x1b, 0x3c, 0x72, 0x30, 0xac, 0xe3, 0xf4, 0xba,
- 0xe4, 0x07, 0x59, 0xba, 0x57, 0x41, 0x21, 0x5f, 0xc2, 0x4d, 0x2c, 0x3f, 0xcf, 0x74, 0xdf, 0xc9,
- 0xf4, 0x50, 0x0a, 0x20, 0x24, 0x56, 0xec, 0xec, 0xd3, 0xfd, 0x3c, 0xdb, 0x46, 0x86, 0x4d, 0x0b,
- 0x8c, 0xc0, 0xe0, 0x67, 0x4c, 0x78, 0x25, 0x9a, 0xc8, 0xfc, 0x77, 0xa8, 0xf4, 0xf8, 0x43, 0x87,
- 0xdc, 0x66, 0xbd, 0x34, 0x26, 0x06, 0xc8, 0x5d, 0x66, 0x63, 0x80, 0x45, 0x09, 0x8f, 0x57, 0xfd,
- 0xd9, 0x80, 0x67, 0x8e, 0x62, 0xf1, 0x70, 0xee, 0x7e, 0x43, 0xd5, 0x3d, 0x11, 0x35, 0x5b, 0xf9,
- 0xb9, 0xb7, 0x56, 0x4c, 0x9c, 0x59, 0x71, 0x80, 0xfb, 0x35, 0xcb, 0x58, 0xb3, 0xdb, 0x0c, 0xf3,
- 0x29, 0xe6, 0x38, 0x93, 0x72, 0xef, 0x19, 0x24, 0x71, 0xa4, 0x7e, 0xc2, 0x0f, 0xa7, 0x88, 0x60,
- 0xa7, 0x0e, 0x65, 0x7f, 0xd7, 0x60, 0x30, 0x7a, 0xe8, 0xf0, 0x37, 0xee, 0x68, 0x87, 0x31, 0xc8,
- 0x32, 0xe4, 0xa1, 0x71, 0xd2, 0xdb, 0x86, 0x9b, 0xe2, 0xf5, 0x63, 0xe6, 0x70, 0x79, 0x79, 0xa6,
- 0x79, 0xab, 0x44, 0xdc, 0xe5, 0xe7, 0xe2, 0x95, 0x9a, 0x07, 0x50, 0x4a, 0xc9, 0x95, 0xa7, 0x39,
- 0x8b, 0xcb, 0xb7, 0xa2, 0xf1, 0xc5, 0x37, 0x96, 0x58, 0x29, 0xd7, 0x05, 0x9b, 0xf7, 0x39, 0x9c,
- 0xef, 0xbb, 0x0d, 0xde, 0xb7, 0xb1, 0xab, 0xa1, 0x31, 0xc2, 0xe1, 0x01, 0xfb, 0x76, 0xfe, 0x2a,
- 0x61, 0x35, 0x8f, 0x50, 0x93, 0x48, 0xbb, 0x44, 0xb0, 0xfc, 0x78, 0xd7, 0xef, 0x34, 0x98, 0x49,
- 0xbb, 0x96, 0x59, 0x25, 0x37, 0x26, 0x04, 0x86, 0x97, 0x0c, 0x0f, 0xd4, 0x20, 0xb1, 0x80, 0x23,
- 0xd2, 0x33, 0x98, 0xad, 0x1d, 0xb5, 0xc4, 0x7d, 0x74, 0x69, 0xa8, 0x73, 0xba, 0xb5, 0x71, 0xfe,
- 0xd9, 0x5c, 0xfe, 0xd2, 0x4b, 0x6a, 0xa9, 0x0d, 0xfc, 0x19, 0x2f, 0x7c, 0x6e, 0x73, 0xab, 0xa9,
- 0xbb, 0x1e, 0xe4, 0x50, 0xc0, 0x58, 0xab, 0xef, 0xf6, 0xe8, 0x48, 0x04, 0x8a, 0x97, 0xbb, 0x0d,
- 0x8c, 0x10, 0x9c, 0x68, 0xed, 0xe7, 0x18, 0x8b, 0xcd, 0x6d, 0xcb, 0x14, 0x5b, 0xba, 0x08, 0x61,
- 0x0d, 0xbb, 0x4a, 0xe1, 0x13, 0x67, 0xca, 0x68, 0x4d, 0x36, 0x69, 0xe3, 0xab, 0x01, 0x00, 0x97,
- 0x1e, 0x7e, 0xb0, 0x09, 0x24, 0x13, 0xf2, 0xce, 0xda, 0x34, 0xdf, 0x91, 0x60, 0x2b, 0xdc, 0x58,
- 0xe2, 0xf1, 0x39, 0xe0, 0x6c, 0x7d, 0x38, 0xd0, 0x6a, 0xeb, 0xa7, 0xb1, 0x6e, 0xa6, 0x2a, 0x62,
- 0x25, 0x41, 0xb3, 0x30, 0x96, 0x34, 0xb0, 0x46, 0x0d, 0x37, 0x4c, 0x28, 0x66, 0x49, 0x5a, 0x5e,
- 0x86, 0x3b, 0x3d, 0x02, 0xa3, 0x4a, 0x08, 0xd8, 0xb1, 0xdd, 0x64, 0x61, 0xaa, 0xb9, 0x41, 0xdb,
- 0x60, 0xe7, 0xc1, 0x40, 0x90, 0xe1, 0xce, 0x48, 0x5a, 0x13, 0x58, 0xd2, 0x55, 0x07, 0x08, 0xa4,
- 0xeb, 0x7c, 0x43, 0x17, 0x31, 0x5c, 0xb2, 0x28, 0x76, 0x37, 0x81, 0x50, 0x94, 0xf8, 0xa3, 0x3a,
- 0x0f, 0xe1, 0x36, 0x01, 0x68, 0xe5, 0x0d, 0x27, 0x88, 0xeb, 0xec, 0x56, 0x69, 0x31, 0xd7, 0x18,
- 0xb9, 0x02, 0x95, 0xb0, 0xe9, 0xca, 0x32, 0x69, 0xd1, 0x27, 0x3a, 0x9b, 0x07, 0xdc, 0x2f, 0xc4,
- 0x70, 0x68, 0x5d, 0xbd, 0x11, 0x83, 0x4c, 0x71, 0x1a, 0x5d, 0x0a, 0xde, 0xc2, 0x14, 0x52, 0xc6,
- 0x7a, 0xa5, 0x73, 0x3e, 0x78, 0x16, 0xaa, 0x76, 0x77, 0xeb, 0x99, 0x13, 0xfe, 0x9b, 0x2b, 0x7b,
- 0x4d, 0x86, 0xc7, 0x1e, 0x4e, 0x05, 0x10, 0x6a, 0xc9, 0x29, 0xb0, 0xa9, 0xbe, 0x20, 0x01, 0x87,
- 0x21, 0x70, 0xf8, 0xe1, 0x69, 0xe9, 0xd0, 0x96, 0x4f, 0x03, 0xd3, 0x76, 0xa8, 0x0b, 0x71, 0x6d,
- 0x9b, 0x5e, 0x9f, 0xd0, 0x50, 0x19, 0x8a, 0x39, 0x71, 0x78, 0xab, 0x7f, 0xbf, 0x3d, 0xae, 0x8a,
- 0xb7, 0xfe, 0xe8, 0x38, 0x53, 0xab, 0xfb, 0x2f, 0x04, 0xc5, 0x2e, 0x72, 0xde, 0x74, 0x7f, 0x01,
- 0x50, 0x01, 0xf9, 0x8f, 0x8b, 0x34, 0x41, 0xe6, 0x6f, 0x9f, 0x98, 0xa4, 0xb1, 0x7d, 0x2e, 0x78,
- 0xbc, 0x8e, 0xce, 0x8f, 0xe2, 0x28, 0xbd, 0x24, 0x8b, 0x3e, 0x6b, 0x9c, 0xad, 0x16, 0x85, 0x48,
- 0x34, 0x52, 0xeb, 0x5e, 0x32, 0x79, 0x42, 0xaa, 0x97, 0xd8, 0x32, 0x46, 0x38, 0x22, 0x69, 0x81,
- 0x11, 0xdc, 0xf3, 0x65, 0x03, 0xa7, 0x98, 0xdf, 0xd3, 0x1b, 0xfd, 0x89, 0x45, 0x89, 0x60, 0xb4,
- 0x53, 0xd4, 0xb8, 0xec, 0xae, 0x33, 0x41, 0x56, 0x62, 0x57, 0x7c, 0x55, 0x2f, 0x2b, 0x31, 0x20,
- 0xef, 0xc1, 0x23, 0x55, 0x01, 0xc5, 0xf3, 0x99, 0x41, 0x05, 0xc1, 0x12, 0x02, 0x02, 0x27, 0xcb,
- 0x63, 0x41, 0x5f, 0x66, 0x3c, 0xce, 0x2a, 0x1f, 0xe8, 0xc4, 0x82, 0x8e, 0xf7, 0x06, 0xa8, 0x17,
- 0xc6, 0xf7, 0x13, 0xca, 0xf0, 0x10, 0x92, 0xec, 0xa9, 0xf3, 0x74, 0x9d, 0xf7, 0xdb, 0x71, 0xb5,
- 0x51, 0x9d, 0xe0, 0xfd, 0x76, 0x90, 0x3f, 0x05, 0x22, 0xf4, 0xf2, 0x21, 0x81, 0x75, 0xdb, 0x5c,
- 0x2b, 0xd1, 0x08, 0xbe, 0x9c, 0x5b, 0x7b, 0x28, 0xc5, 0xf9, 0xe9, 0xb2, 0xd2, 0x12, 0xaa, 0x74,
- 0xad, 0xde, 0xfb, 0xbe, 0xc0, 0x1c, 0x96, 0xce, 0x7d, 0xef, 0xf4, 0xf8, 0x5f, 0xf6, 0x75, 0xa9,
- 0x2f, 0x5d, 0xa4, 0x7d, 0xb0, 0xb3, 0xbc, 0x95, 0x23, 0xd4, 0x19, 0xfd, 0x00, 0xed, 0xf7, 0x05,
- 0x0a, 0x66, 0x36, 0x58, 0x0f, 0x83, 0xdb, 0x9e, 0x33, 0x35, 0x52, 0x7d, 0x7f, 0xe5, 0xa9, 0x76,
- 0xe2, 0x6b, 0x67, 0x41, 0xf9, 0x1f, 0x37, 0x8e, 0xd2, 0x16, 0x08, 0x64, 0x3f, 0xff, 0xd5, 0x09,
- 0x21, 0xa9, 0xf5, 0xcc, 0xd6, 0x33, 0x97, 0x17, 0xfd, 0x01, 0x2b, 0xf8, 0xf6, 0xe7, 0xd6, 0xfd,
- 0xa6, 0xcc, 0x7a, 0xcc, 0xac, 0x69, 0x6e, 0x03, 0x02, 0x32, 0xd1, 0x24, 0xfa, 0x6e, 0xd5, 0xbc,
- 0x0b, 0x38, 0x9b, 0x46, 0xdc, 0x88, 0x84, 0x55, 0x5c, 0x44, 0x4d, 0x87, 0xac, 0xb4, 0xc4, 0x23,
- 0xda, 0x69, 0x74, 0x85, 0xb6, 0xca, 0xce, 0xec, 0x0a, 0x0e, 0x74, 0x2d, 0xff, 0x87, 0x6f, 0xa6,
- 0xf3, 0xc2, 0xcb, 0x64, 0x5e, 0x5c, 0x4f, 0xde, 0xb0, 0x2b, 0xb7, 0x16, 0x0f, 0x4c, 0xea, 0x5f,
- 0x45, 0x6f, 0x50, 0x9c, 0xc8, 0x3c, 0x4e, 0xb4, 0x0a, 0xb2, 0xbb, 0xf7, 0xf4, 0xa3, 0x28, 0x72,
- 0xe3, 0x0b, 0xed, 0x4e, 0x9d, 0x06, 0x95, 0xbd, 0xc5, 0x14, 0x29, 0x0a, 0x34, 0x97, 0xdb, 0x2e,
- 0xa7, 0x85, 0xcd, 0xa5, 0x95, 0xdc, 0x05, 0x0d, 0xea, 0xaa, 0x2f, 0x25, 0x48, 0xca, 0x69, 0xa4,
- 0xaa, 0xec, 0x34, 0xae, 0x68, 0x1a, 0x93, 0x2f, 0x84, 0x96, 0xa8, 0x50, 0x48, 0x89, 0x44, 0x62,
- 0xa9, 0xcf, 0x20, 0x8d, 0xfa, 0x38, 0x41, 0x56, 0xf4, 0xb8, 0x86, 0xce, 0x15, 0xcc, 0x25, 0xfb,
- 0xe1, 0xa2, 0x1a, 0x4b, 0x49, 0x80, 0x64, 0x37, 0x60, 0x3c, 0xb3, 0x67, 0xee, 0x48, 0xf0, 0xfd,
- 0x0e, 0x92, 0x57, 0x68, 0xf4, 0xf1, 0x57, 0x9c, 0x73, 0x9c, 0xe7, 0xc8, 0x1d, 0xa0, 0x10, 0xf4,
- 0x0d, 0x38, 0x06, 0x41, 0x7a, 0x60, 0x6e, 0x37, 0xc5, 0x50, 0x62, 0xbe, 0x4e, 0x59, 0x3a, 0xba,
- 0x70, 0x43, 0xc5, 0x51, 0xec, 0x7b, 0xb5, 0xa2, 0xb8, 0x88, 0x4d, 0xb2, 0xf7, 0x11, 0xe0, 0xa3,
- 0x04, 0xd0, 0xe7, 0x0b, 0x37, 0xa4, 0xf3, 0xa1, 0xb1, 0x15, 0xa0, 0x1f, 0x03, 0x8f, 0xeb, 0xa2,
- 0x50, 0x58, 0x93, 0x49, 0xa8, 0x0b, 0x20, 0x23, 0x3c, 0x3f, 0xd7, 0xc3, 0xf1, 0xac, 0x40, 0x46,
- 0x9e, 0xf6, 0xa7, 0x34, 0x22, 0xd8, 0x39, 0x2e, 0x7b, 0xb2, 0x1d, 0x81, 0x36, 0x63, 0x4b, 0x37,
- 0x5d, 0x22, 0x6a, 0x74, 0x21, 0x7a, 0x9a, 0xc9, 0x96, 0x2d, 0xaa, 0x6a, 0xa3, 0x42, 0x23, 0x63,
- 0xfc, 0xe1, 0x2c, 0xba, 0x79, 0x9c, 0x9f, 0xf6, 0x07, 0x04, 0xdd, 0xcc, 0xed, 0xf5, 0x21, 0x54,
- 0xf9, 0xf4, 0x4d, 0xb6, 0xe7, 0x78, 0xd5, 0x0a, 0xc7, 0x16, 0x93, 0x00, 0x7b, 0x30, 0xc9, 0x33,
- 0xa6, 0x39, 0xa8, 0x07, 0x32, 0xeb, 0xf9, 0x3c, 0x6a, 0xee, 0x85, 0xbe, 0x6e, 0x27, 0xd2, 0x15,
- 0xa0, 0xbd, 0x14, 0xac, 0x7a, 0x14, 0xf6, 0xea, 0xcd, 0xda, 0xdd, 0x75, 0xf2, 0x66, 0xbf, 0xef,
- 0x56, 0x06, 0x09, 0xbc, 0xab, 0x64, 0x6b, 0xf6, 0x7e, 0x14, 0x9f, 0x84, 0x4d, 0x63, 0xd3, 0xc9,
- 0x85, 0x94, 0x44, 0x84, 0xeb, 0xae, 0x5f, 0xd2, 0xba, 0xfa, 0xd7, 0xf5, 0x60, 0x17, 0x84, 0xd9,
- 0x15, 0xc8, 0x54, 0x6c, 0x57, 0x69, 0x82, 0xc1, 0xe7, 0xd8, 0xfa, 0xcd, 0x67, 0x2a, 0x3c, 0xbe,
- 0x5d, 0xd4, 0x4a, 0xfd, 0xa6, 0x0a, 0xa6, 0x8a, 0xfa, 0xbb, 0x2e, 0x3b, 0x05, 0xaa, 0xc2, 0xd9,
- 0x9a, 0x54, 0x7a, 0xc0, 0x27, 0x15, 0x97, 0xda, 0x59, 0xd7, 0x24, 0x08, 0x6a, 0x92, 0xd4, 0xee,
- 0x31, 0xf2, 0x6c, 0x1f, 0x19, 0xe6, 0x9d, 0x3e, 0xab, 0xa6, 0x47, 0xb3, 0xab, 0x66, 0x81, 0xa3,
- 0x2a, 0xda, 0x66, 0xf4, 0x4e, 0x54, 0xe5, 0xcc, 0x58, 0x8c, 0x56, 0x74, 0xc3, 0xb4, 0x96, 0x43,
- 0x9f, 0x3d, 0x2a, 0x73, 0x97, 0xcb, 0x75, 0xf1, 0x54, 0x75, 0x0b, 0x7a, 0xce, 0x12, 0xb2, 0x3f,
- 0x22, 0xfe, 0xc3, 0x99, 0x14, 0xd4, 0x8b, 0x52, 0x8d, 0xc2, 0x33, 0xe2, 0xfb, 0x28, 0xfd, 0xc0,
- 0xec, 0x55, 0x88, 0x09, 0xd8, 0x3a, 0x70, 0xf4, 0x13, 0x46, 0xe6, 0x39, 0x65, 0x25, 0x19, 0xbb,
- 0x2a, 0xc4, 0x9e, 0x79, 0x11, 0xac, 0x58, 0xd3, 0x43, 0x12, 0x2b, 0x58, 0xe6, 0xad, 0x70, 0x6f,
- 0x03, 0xfc, 0xf2, 0xd0, 0x13, 0x69, 0xd6, 0xe2, 0x97, 0x49, 0xbd, 0xe9, 0x76, 0x3d, 0x5e, 0xd7,
- 0xf1, 0xae, 0x3a, 0xab, 0xa3, 0xa9, 0xbe, 0x25, 0x4f, 0xdd, 0xf3, 0xdd, 0x85, 0xd8, 0xad, 0x3c,
- 0x86, 0xe2, 0x32, 0x1d, 0xd9, 0x42, 0x04, 0x66, 0x48, 0x90, 0xfb, 0x69, 0x3d, 0x84, 0x03, 0xa0,
- 0xc2, 0x1d, 0x35, 0xcb, 0xd9, 0xf3, 0xc7, 0xa6, 0x4a, 0x49, 0x68, 0x5e, 0x6e, 0xa6, 0x09, 0x89,
- 0xa6, 0x3f, 0xb5, 0xc4, 0x15, 0x9a, 0xb5, 0x9b, 0xa8, 0x7c, 0xe8, 0x23, 0x8e, 0x1c, 0x9a, 0xaa,
- 0xf5, 0x2b, 0xf2, 0xfa, 0x74, 0x54, 0x8d, 0xe7, 0xfa, 0x23, 0x70, 0x31, 0x0e, 0x42, 0xfc, 0xad,
- 0x55, 0x68, 0x97, 0x79, 0xf0, 0xf4, 0xa7, 0xed, 0x91, 0x78, 0xac, 0xe6, 0x84, 0x55, 0xf8, 0x27,
- 0x22, 0x3d, 0xcb, 0x44, 0xb7, 0x44, 0xe9, 0xa8, 0xe4, 0x68, 0xc2, 0xa1, 0xbd, 0x8d, 0xec, 0x48,
- 0xa1, 0x07, 0x23, 0x66, 0xbd, 0x2b, 0x4b, 0x32, 0x49, 0xb2, 0x61, 0x84, 0x6b, 0xb3, 0x46, 0xbf,
- 0xbb, 0x5d, 0x21, 0xe0, 0x84, 0x1c, 0x43, 0x35, 0xb9, 0x45, 0x58, 0x24, 0xa0, 0x83, 0xac, 0xb8,
- 0x9d, 0xa3, 0x1d, 0xa4, 0xd5, 0x2c, 0x67, 0x2a, 0x6a, 0x44, 0x57, 0xc4, 0x12, 0x64, 0x5f, 0xb2,
- 0xa6, 0xa9, 0x53, 0x24, 0xa0, 0x19, 0x37, 0x08, 0x33, 0x1e, 0x91, 0x5f, 0x8f, 0x44, 0x55, 0xf2,
- 0xb8, 0x0b, 0x39, 0xac, 0x26, 0x4a, 0x4e, 0x8d, 0xbc, 0xbf, 0x59, 0x85, 0xa9, 0x5e, 0x04, 0x4f,
- 0x30, 0x48, 0x7f, 0xac, 0x37, 0x1b, 0x44, 0x2b, 0xac, 0x48, 0xc1, 0x07, 0xec, 0xc8, 0x9d, 0xc6,
- 0x59, 0x6f, 0x4b, 0xa2, 0x56, 0x0a, 0xba, 0x77, 0xbe, 0x84, 0xba, 0x63, 0x43, 0xb4, 0xd9, 0xa7,
- 0xa8, 0xaf, 0x17, 0xc9, 0x3e, 0xa1, 0xfc, 0xc9, 0xf1, 0x86, 0x85, 0x25, 0x0e, 0x81, 0x1c, 0x25,
- 0x1a, 0x6d, 0x36, 0x89, 0x7e, 0xe8, 0x63, 0x46, 0x55, 0x3a, 0x99, 0x50, 0xa6, 0xbf, 0xef, 0x72,
- 0x5f, 0xb6, 0x48, 0x7d, 0x5e, 0x40, 0x7f, 0x21, 0x81, 0xbc, 0x0d, 0x0b, 0xad, 0x57, 0xdc, 0x4d,
- 0xbe, 0x7c, 0x7d, 0x54, 0x18, 0x34, 0xf3, 0x40, 0xc2, 0xc9, 0x93, 0xf1, 0x50, 0x23, 0xcd, 0x18,
- 0x68, 0xf0, 0xad, 0x52, 0x9d, 0x90, 0x07, 0x8d, 0x5f, 0x60, 0xca, 0xb2, 0xb6, 0x35, 0x3a, 0xe5,
- 0xe7, 0x80, 0x44, 0xd3, 0x62, 0x12, 0x25, 0x0d, 0x0c, 0xc5, 0x8c, 0x39, 0x3e, 0x59, 0x1c, 0x70,
- 0x76, 0x99, 0x8a, 0x29, 0x4b, 0xbe, 0x09, 0x58, 0x19, 0x99, 0xaa, 0x7f, 0x78, 0x2b, 0xc8, 0x55,
- 0x9e, 0xd6, 0xef, 0x18, 0xb9, 0xd7, 0xd2, 0x47, 0x8c, 0xdd, 0xbd, 0x80, 0xed, 0x9b, 0x79, 0x80,
- 0x46, 0x35, 0x1c, 0xbb, 0x4b, 0xbd, 0x14, 0x6f, 0x68, 0x87, 0x26, 0x34, 0xf6, 0x76, 0x3f, 0x47,
- 0x67, 0xa1, 0x19, 0x4e, 0x46, 0x91, 0xc0, 0x37, 0xa3, 0xd3, 0x4d, 0xdd, 0x54, 0xd4, 0x5a, 0x2b,
- 0x7d, 0xad, 0x42, 0x0d, 0x35, 0x9a, 0xca, 0xd9, 0x61, 0x9a, 0xf4, 0x52, 0x51, 0x94, 0x4b, 0xa2,
- 0x08, 0xde, 0xa8, 0x4b, 0xe9, 0xe6, 0x7f, 0x93, 0xa0, 0x7c, 0x7b, 0x39, 0x59, 0xc8, 0xc2, 0xa3,
- 0xc7, 0x46, 0xf0, 0x99, 0xdb, 0x62, 0x57, 0x01, 0x91, 0x20, 0xe6, 0x8d, 0x14, 0xc1, 0x13, 0xfd,
- 0xd1, 0x5d, 0x84, 0xb7, 0xf5, 0xd3, 0x56, 0x49, 0x6d, 0x32, 0x24, 0x1a, 0x4e, 0xbd, 0x19, 0xb0,
- 0x90, 0x12, 0x32, 0x2f, 0x89, 0x72, 0x66, 0xc3, 0x2a, 0x18, 0x44, 0xea, 0x6e, 0x6c, 0x28, 0x20,
- 0x8e, 0x59, 0x93, 0xc2, 0x9b, 0x94, 0xea, 0x6f, 0x85, 0x32, 0xff, 0x4a, 0xce, 0xd6, 0x20, 0x8d,
- 0x43, 0x24, 0x8c, 0xf1, 0x48, 0xec, 0x63, 0x95, 0xd3, 0x26, 0xb5, 0xc0, 0xc4, 0xe9, 0xdc, 0x95,
- 0x66, 0xef, 0xd8, 0xf3, 0x82, 0x1c, 0xf0, 0x5b, 0xb5, 0xf0, 0xd9, 0x8e, 0x8b, 0x62, 0xd8, 0x81,
- 0xd1, 0xd6, 0x17, 0xca, 0x22, 0x79, 0x11, 0xcd, 0x09, 0x1d, 0x66, 0x80, 0xdf, 0xe4, 0xc3, 0x17,
- 0x30, 0x27, 0x15, 0x7a, 0x22, 0x42, 0xa2, 0x21, 0x24, 0x6f, 0x63, 0xb3, 0xb1, 0x18, 0x03, 0x30,
- 0xb1, 0x5e, 0x9d, 0x79, 0xeb, 0xaf, 0x24, 0x3c, 0xc7, 0xaf, 0x3b, 0x5b, 0xac, 0xf1, 0xdf, 0x9f,
- 0x3d, 0xfa, 0x52, 0xae, 0x91, 0x0b, 0xe0, 0x2e, 0x93, 0x6f, 0x6b, 0xac, 0x5b, 0xe3, 0x3c, 0x0d,
- 0x2a, 0x95, 0x89, 0x12, 0xa5, 0x6b, 0xb7, 0xdc, 0xc7, 0x22, 0xac, 0xce, 0xe9, 0xf6, 0x08, 0xe9,
- 0x16, 0xcf, 0x03, 0x4a, 0xdb, 0x43, 0x47, 0x82, 0x4e, 0x55, 0x46, 0x20, 0x4b, 0xeb, 0xc4, 0xd6,
- 0x0e, 0xc1, 0xff, 0xb7, 0x40, 0x4d, 0xfb, 0x49, 0xc0, 0xbb, 0xdb, 0x4e, 0xa3, 0x64, 0x36, 0x7c,
- 0x69, 0xe6, 0xf4, 0x1b, 0xad, 0x4f, 0xa5, 0xcf, 0x68, 0xd2, 0xbc, 0x71, 0x18, 0xad, 0xbc, 0x35,
- 0xab, 0x4e, 0xd2, 0xcd, 0x26, 0xe8, 0x27, 0x82, 0xc5, 0x37, 0xeb, 0x90, 0xa1, 0x4d, 0x2a, 0xf7,
- 0xf5, 0x40, 0xf9, 0x28, 0xc8, 0x96, 0x9b, 0xa4, 0xff, 0x4f, 0x6f, 0x1e, 0x6b, 0x51, 0xa5, 0xc1,
- 0xe1, 0x11, 0xba, 0x00, 0xa8, 0x63, 0xc6, 0xd1, 0xaa, 0x97, 0x61, 0x6d, 0xb2, 0xf1, 0x2f, 0x9b,
- 0x90, 0x32, 0xd8, 0x6b, 0xba, 0x00, 0xa7, 0xcb, 0xe1, 0xcd, 0xb7, 0xb8, 0x80, 0x5b, 0x60, 0x9a,
- 0x04, 0xb1, 0x59, 0x00, 0x1f, 0x45, 0xc7, 0x2a, 0x08, 0xcb, 0xc1, 0xee, 0x0d, 0xb4, 0x71, 0xdf,
- 0x7a, 0xdc, 0xa6, 0xbb, 0xfe, 0xa0, 0x4d, 0x49, 0xbb, 0x2c, 0x13, 0x25, 0x2e, 0x9f, 0x55, 0xaa,
- 0x73, 0x16, 0x39, 0xd5, 0x83, 0x35, 0x2f, 0xb4, 0xef, 0x69, 0x9e, 0x3e, 0x4c, 0x67, 0x00, 0x05,
- 0x59, 0xc3, 0x38, 0x77, 0x1e, 0x9d, 0x93, 0xfa, 0x3f, 0x49, 0x9f, 0x58, 0x1d, 0xa3, 0x05, 0xec,
- 0xd7, 0x51, 0x30, 0xe1, 0x34, 0x83, 0xb3, 0xd1, 0x54, 0x84, 0x63, 0xd6, 0xb7, 0x0c, 0x61, 0xa5,
- 0x36, 0x12, 0xf8, 0x6d, 0xc6, 0xb8, 0xdc, 0x5d, 0x97, 0x9a, 0x7a, 0x81, 0xaa, 0x39, 0xfa, 0xef,
- 0x46, 0x82, 0x7c, 0xc0, 0x5b, 0xbe, 0x66, 0xd9, 0x06, 0xe5, 0xe1, 0x91, 0xdb, 0xa6, 0x33, 0x80,
- 0x69, 0x8c, 0xcd, 0x9d, 0x52, 0x59, 0x95, 0x06, 0xa5, 0x26, 0x62, 0x38, 0xa0, 0x20, 0x6b, 0x98,
- 0x14, 0xed, 0xf2, 0xda, 0x70, 0x10, 0x6c, 0x79, 0x6b, 0x4c, 0x18, 0xa4, 0x72, 0x08, 0x27, 0x8b,
- 0x42, 0x27, 0x4f, 0x0a, 0x0c, 0xf1, 0xe6, 0x5d, 0x0b, 0xda, 0x6c, 0x2c, 0x18, 0x91, 0xbe, 0x62,
- 0xfe, 0x2f, 0xee, 0xdf, 0x12, 0xcb, 0x16, 0xcc, 0x73, 0x4a, 0x13, 0xe9, 0x31, 0x3b, 0xbe, 0x68,
- 0x2d, 0x1c, 0xa0, 0xfc, 0x70, 0x11, 0x45, 0xcd, 0x47, 0x6c, 0x3e, 0x6f, 0xdc, 0xc6, 0xa3, 0x25,
- 0x0e, 0xa5, 0xff, 0xff, 0x3d, 0x55, 0x04, 0xbc, 0xfe, 0x60, 0x3d, 0xbd, 0x31, 0x95, 0xa5, 0x02,
- 0xdc, 0x42, 0x26, 0x15, 0x6f, 0x33, 0x77, 0x67, 0xb2, 0x36, 0x46, 0x1d, 0x1c, 0x3e, 0x2b, 0x80,
- 0x59, 0xac, 0x12, 0xa8, 0x0f, 0x64, 0xb3, 0xa9, 0x8b, 0x58, 0xef, 0x27, 0x43, 0xcc, 0x99, 0x7e,
- 0x38, 0x61, 0xcb, 0x47, 0xbe, 0x1f, 0x00, 0xe5, 0x2a, 0xb2, 0x1b, 0x56, 0x56, 0x7c, 0xfe, 0xcb,
- 0x0a, 0x89, 0xf6, 0xfc, 0x83, 0xe8, 0x82, 0xf2, 0xbe, 0xc8, 0xca, 0x32, 0xf0, 0x9c, 0x7a, 0x84,
- 0x4f, 0xef, 0xc0, 0xdf, 0x99, 0xf5, 0x7b, 0x51, 0xd6, 0x4f, 0x9d, 0xac, 0xb0, 0x28, 0x6b, 0x0c,
- 0x47, 0x12, 0xc0, 0xf8, 0x79, 0xec, 0x6f, 0x7a, 0x7c, 0xa6, 0x37, 0xd2, 0xe2, 0x8a, 0x74, 0x45,
- 0x5a, 0x49, 0x7b, 0xb2, 0x74, 0x96, 0xb4, 0x9f, 0xeb, 0x3d, 0x45, 0x8e, 0x4d, 0x7e, 0x67, 0x97,
- 0x06, 0x9a, 0x8c, 0xac, 0x43, 0x55, 0xa1, 0x9a, 0x60, 0xb9, 0xa1, 0x79, 0xcd, 0xa2, 0xef, 0x72,
- 0x45, 0xe3, 0x79, 0xab, 0x6f, 0x7a, 0xa1, 0x9e, 0x11, 0x88, 0x14, 0xe8, 0xce, 0xd1, 0xce, 0x52,
- 0x5c, 0x4d, 0xa6, 0xf8, 0x78, 0x71, 0x26, 0xb0, 0x56, 0xcf, 0xdc, 0x87, 0xb9, 0xc1, 0xf0, 0xdf,
- 0x71, 0x4b, 0xfb, 0x9c, 0x9e, 0xce, 0x2d, 0x32, 0x85, 0xd4, 0x89, 0x1f, 0x1e, 0x42, 0x3f, 0xd4,
- 0x75, 0xfa, 0x41, 0x1d, 0x9f, 0x47, 0x9e, 0x4b, 0x3a, 0x71, 0xdf, 0x8d, 0x5a, 0x9a, 0x3a, 0x94,
- 0x46, 0xe0, 0xe6, 0x10, 0xcf, 0x6b, 0xe1, 0x37, 0x94, 0x2b, 0x18, 0xbd, 0x41, 0x18, 0x06, 0xdd,
- 0x1d, 0x3c, 0x57, 0x9f, 0x42, 0xcc, 0x1b, 0xfa, 0x0b, 0x2b, 0xc8, 0xb4, 0x14, 0x3c, 0x2d, 0x4b,
- 0x90, 0x23, 0xf3, 0xcf, 0xca, 0x8d, 0x14, 0x2d, 0xcd, 0x3a, 0x5d, 0x4e, 0x30, 0x72, 0x87, 0x4b,
- 0xd7, 0xe0, 0xf1, 0x2d, 0x0c, 0x20, 0xd4, 0x9d, 0x58, 0xa2, 0xf2, 0x1b, 0x7b, 0xa5, 0x99, 0x55,
- 0x4a, 0x1a, 0xe8, 0x56, 0xf6, 0xa8, 0x2a, 0x79, 0xc9, 0xb5, 0x6a, 0x35, 0x41, 0x0a, 0x74, 0x84,
- 0xca, 0x13, 0xdc, 0x9d, 0x6f, 0xae, 0x69, 0x4a, 0x11, 0xa2, 0x51, 0x65, 0x26, 0x80, 0x8f, 0x7a,
- 0x24, 0xd4, 0x4f, 0x51, 0xe1, 0x4e, 0xa9, 0x1c, 0xe5, 0x2a, 0x5e, 0x64, 0x0e, 0x8b, 0x8d, 0xf9,
- 0xa9, 0x8b, 0x5d, 0x65, 0x05, 0xe1, 0xf6, 0xc4, 0x8d, 0x47, 0x3d, 0x9a, 0xc8, 0xdc, 0x58, 0xb6,
- 0x8a, 0x68, 0x30, 0x9b, 0x03, 0x8d, 0x21, 0x3c, 0xa8, 0x40, 0x7b, 0x57, 0x69, 0xec, 0xbc, 0xcf,
- 0x5e, 0x20, 0x3d, 0x30, 0xd7, 0x55, 0x5c, 0x51, 0xd4, 0x39, 0x4e, 0xf0, 0x01, 0xca, 0x68, 0x20,
- 0xec, 0x78, 0x8a, 0xf0, 0x54, 0x56, 0xe3, 0xa7, 0x87, 0x58, 0xcc, 0x1d, 0x15, 0xe5, 0x3d, 0x0b,
- 0x76, 0x21, 0x05, 0xd8, 0xcd, 0x60, 0x38, 0x3f, 0x6c, 0x20, 0xc7, 0x56, 0xe8, 0x3c, 0x9c, 0x54,
- 0xc4, 0xd1, 0x17, 0x36, 0xce, 0xaa, 0x69, 0xbc, 0x4d, 0x43, 0x90, 0x80, 0x7d, 0xf9, 0xd3, 0x2c,
- 0x46, 0x0c, 0x9e, 0x02, 0x91, 0xbb, 0x51, 0x9b, 0x45, 0x3f, 0xe2, 0xc0, 0x8c, 0x35, 0xc7, 0x98,
- 0xb9, 0xe1, 0xc6, 0x5f, 0x26, 0x40, 0xa7, 0x4e, 0x01, 0xa9, 0xae, 0x28, 0xd1, 0x05, 0xaa, 0xe9,
- 0x8e, 0xc4, 0x68, 0xb6, 0xe4, 0x01, 0x9a, 0x3c, 0x6c, 0x55, 0x3e, 0x39, 0x2c, 0x7e, 0xee, 0x48,
- 0xda, 0x2d, 0x4e, 0xb1, 0xd6, 0x3e, 0xb9, 0xfc, 0x91, 0x36, 0x77, 0xb1, 0xaf, 0x8d, 0x92, 0xca,
- 0xb3, 0xbc, 0xc6, 0x88, 0xfc, 0xe8, 0x2e, 0xa5, 0x6b, 0x63, 0xc3, 0xe4, 0xd3, 0xbf, 0xd0, 0xe9,
- 0x55, 0x3d, 0x97, 0x69, 0x7a, 0xf7, 0xa6, 0x4d, 0x96, 0xb7, 0x37, 0x22, 0x86, 0x39, 0x72, 0x2a,
- 0x4f, 0x96, 0xf7, 0x9e, 0x99, 0xf6, 0x8f, 0x71, 0xec, 0xee, 0x0e, 0xe7, 0x85, 0x04, 0xd3, 0x06,
- 0xd5, 0xe8, 0x13, 0xe0, 0x9c, 0x2a, 0xef, 0x3e, 0x2d, 0xdd, 0x08, 0x89, 0x43, 0x3e, 0x93, 0xe2,
- 0x9e, 0x17, 0xbc, 0xd6, 0x0f, 0xbd, 0x72, 0x93, 0xd0, 0x79, 0xcf, 0xd8, 0xce, 0x3c, 0x28, 0x45,
- 0x73, 0x49, 0x1c, 0x89, 0x76, 0xeb, 0x1c, 0xc9, 0x1f, 0xb9, 0x4c, 0xf2, 0x2b, 0x22, 0x40, 0xef,
- 0xe1, 0x03, 0xd0, 0x5b, 0xb4, 0x60, 0xb4, 0x39, 0x7b, 0x63, 0x24, 0xba, 0x1a, 0x32, 0xc8, 0x50,
- 0xbb, 0x39, 0x10, 0xe6, 0x26, 0x36, 0x82, 0x37, 0x04, 0xd1, 0x33, 0x32, 0x4e, 0x01, 0x02, 0x1e,
- 0x6b, 0x15, 0xc9, 0x6a, 0xf9, 0x59, 0x28, 0x90, 0x3b, 0xa9, 0xb0, 0xf8, 0x31, 0x00, 0xbd, 0xa8,
- 0xe3, 0x26, 0x42, 0x89, 0xfe, 0x84, 0xfb, 0xab, 0xb9, 0xc1, 0x31, 0xca, 0x04, 0xcf, 0x72, 0x9b,
- 0x44, 0xa7, 0xd5, 0x5b, 0x43, 0x93, 0x51, 0x17, 0x73, 0x02, 0x64, 0x98, 0xd0, 0xfd, 0x23, 0x0f,
- 0x6d, 0x50, 0x30, 0x9f, 0xaa, 0xaf, 0xc7, 0x7b, 0x7c, 0x4b, 0xa1, 0x94, 0xd4, 0x0e, 0xa3, 0x8f,
- 0xe5, 0x1c, 0xf9, 0x2a, 0xf8, 0xe4, 0x7f, 0xd2, 0x75, 0x31, 0xfa, 0x7d, 0x50, 0x4d, 0x1c, 0x47,
- 0x8d, 0x50, 0x31, 0xd4, 0x97, 0x08, 0xb2, 0x57, 0x83, 0xaf, 0x99, 0x6c, 0x54, 0xb0, 0x6a, 0x91,
- 0xf1, 0x3d, 0xf3, 0x99, 0x7e, 0x6d, 0x35, 0xc7, 0xee, 0x09, 0xa2, 0xf7, 0x5e, 0xba, 0x4a, 0x50,
- 0x8c, 0xbe, 0xd0, 0x74, 0x66, 0x18, 0xcb, 0x94, 0x44, 0xbf, 0x48, 0x9f, 0x35, 0xde, 0xe8, 0x68,
- 0x2b, 0x4c, 0x1e, 0x2a, 0x27, 0x33, 0x0c, 0x1c, 0x12, 0x27, 0xd3, 0x54, 0x77, 0xc3, 0xba, 0x51,
- 0xfe, 0xf9, 0x22, 0xcb, 0x11, 0x6d, 0x03, 0xbe, 0xad, 0x35, 0x3d, 0x8c, 0x8a, 0x9a, 0x18, 0x0a,
- 0xbb, 0x97, 0xf5, 0xa3, 0x77, 0x10, 0xa1, 0x8a, 0x65, 0x9c, 0x50, 0x41, 0xdf, 0xcf, 0x41, 0xf0,
- 0x26, 0xb5, 0x40, 0xa7, 0x87, 0xbe, 0xdb, 0x61, 0xce, 0x19, 0x75, 0x8d, 0xa3, 0x25, 0x14, 0x70,
- 0x40, 0x2a, 0x51, 0x7c, 0x4b, 0x40, 0x05, 0x48, 0x90, 0x65, 0xcc, 0x52, 0x40, 0x9f, 0xe6, 0x66,
- 0x0c, 0xa7, 0x35, 0xe3, 0xc3, 0x74, 0x10, 0x60, 0x45, 0x9e, 0xef, 0x1b, 0x10, 0xf0, 0x00, 0x76,
- 0x8f, 0xf0, 0x4d, 0x7e, 0x11, 0x49, 0x1b, 0x6a, 0x4e, 0xcf, 0xc9, 0xde, 0x0e, 0x53, 0x99, 0x24,
- 0x26, 0x77, 0xaf, 0x74, 0x0d, 0x9c, 0x22, 0xd8, 0x49, 0x8c, 0x7b, 0x8b, 0x99, 0x45, 0xfe, 0x03,
- 0xf4, 0x63, 0xe0, 0xf0, 0x15, 0xf9, 0x94, 0xd4, 0x4a, 0xc0, 0xcd, 0x06, 0xaf, 0xee, 0x6d, 0x27,
- 0xae, 0xcc, 0xa7, 0x30, 0xae, 0x04, 0x63, 0xca, 0x32, 0x35, 0x92, 0x4c, 0xed, 0xcb, 0x61, 0x9b,
- 0xfe, 0x3e, 0x6d, 0x05, 0x33, 0x26, 0xee, 0xaa, 0x90, 0xb1, 0x43, 0x70, 0x38, 0x98, 0x94, 0x46,
- 0xfd, 0x10, 0x1e, 0xdf, 0xe8, 0x8e, 0x25, 0x63, 0x90, 0x6f, 0x73, 0xc3, 0xc8, 0x91, 0x17, 0xad,
- 0x75, 0xf4, 0x0e, 0x98, 0x81, 0x40, 0x63, 0xb8, 0x30, 0xae, 0x1b, 0xc4, 0x07, 0xe6, 0x61, 0x23,
- 0xc1, 0x99, 0x18, 0x73, 0xd6, 0xa8, 0xee, 0x69, 0xa3, 0xec, 0x03, 0x8a, 0x46, 0x44, 0x52, 0x9a,
- 0x24, 0xe2, 0xc7, 0x50, 0xe4, 0xf4, 0xe2, 0xbd, 0x35, 0x41, 0xd7, 0x52, 0x6d, 0xb3, 0x49, 0xcf,
- 0x14, 0xc0, 0x73, 0xc8, 0x8e, 0xf6, 0x49, 0xf3, 0x35, 0xf9, 0x76, 0x20, 0x27, 0x82, 0x77, 0xae,
- 0xba, 0x6e, 0xc6, 0xba, 0x9d, 0xe1, 0x1e, 0xee, 0x87, 0x50, 0x56, 0x6a, 0x38, 0xfb, 0xc6, 0x0b,
- 0xd2, 0x8a, 0x17, 0x48, 0x28, 0x51, 0x5a, 0xa4, 0xbb, 0x7f, 0x4e, 0xb8, 0xc3, 0x26, 0x07, 0x24,
- 0xa6, 0x4a, 0x41, 0xf2, 0x5f, 0x75, 0xa1, 0x2b, 0x86, 0xc7, 0x29, 0xba, 0xac, 0x5f, 0x02, 0xec,
- 0xac, 0x9b, 0xa9, 0x7f, 0x89, 0xea, 0x53, 0xc1, 0x12, 0xe1, 0x34, 0xde, 0xe5, 0xd3, 0x7f, 0x5d,
- 0x16, 0x51, 0xba, 0xed, 0xda, 0xf8, 0x3a, 0xe8, 0x84, 0xfe, 0xde, 0xf0, 0x83, 0xbd, 0x10, 0xa3,
- 0xcf, 0xdc, 0x2f, 0x25, 0xe0, 0x94, 0x0a, 0x30, 0xda, 0x62, 0x31, 0xd5, 0x7e, 0xa3, 0xfb, 0xe0,
- 0xe0, 0x2d, 0x26, 0xe9, 0x14, 0xa2, 0x6f, 0x4e, 0x19, 0xf5, 0x09, 0xba, 0x67, 0x89, 0x79, 0x6f,
- 0x14, 0xe0, 0xd6, 0xac, 0x94, 0x2d, 0x65, 0x10, 0x76, 0x62, 0xb9, 0xa3, 0xcd, 0x20, 0xfe, 0xeb,
- 0x10, 0x5c, 0xe0, 0x75, 0xd3, 0x5d, 0xad, 0x39, 0x07, 0xd9, 0x1d, 0x6e, 0xb0, 0xe5, 0xa5, 0x79,
- 0x0d, 0xc3, 0xb9, 0xdd, 0xca, 0xbb, 0xa0, 0x5d, 0xa0, 0x16, 0xb6, 0xb9, 0xd6, 0x4c, 0xdb, 0x6f,
- 0xb2, 0x5a, 0xa9, 0x55, 0x00, 0x96, 0x14, 0xec, 0x31, 0xe6, 0x79, 0x0f, 0xd1, 0x9d, 0xde, 0xbb,
- 0x27, 0x8d, 0x44, 0xee, 0xec, 0xf2, 0xa3, 0x80, 0xbb, 0x21, 0xd3, 0xe7, 0xd3, 0xbe, 0xb3, 0x86,
- 0x6c, 0xa8, 0x7a, 0xab, 0xbf, 0xa7, 0x22, 0xcd, 0x4c, 0x25, 0x36, 0x03, 0x02, 0xe4, 0x11, 0xbf,
- 0xed, 0x06, 0x90, 0x0c, 0xf0, 0x30, 0xc7, 0x86, 0x7e, 0xaa, 0xc5, 0x84, 0x14, 0x54, 0xf7, 0x56,
- 0x17, 0x02, 0x88, 0xf5, 0xe1, 0xe7, 0xa7, 0xef, 0xe6, 0x71, 0xbc, 0x65, 0x65, 0x1e, 0x40, 0x97,
- 0x86, 0x5f, 0x8c, 0x44, 0xda, 0xa1, 0x38, 0x54, 0x1e, 0xdd, 0x39, 0xaa, 0x9e, 0x9e, 0xa6, 0x41,
- 0x4a, 0xf3, 0xb6, 0xde, 0x19, 0x74, 0x00, 0xfc, 0x2f, 0xf6, 0x0c, 0x00, 0x95, 0xfb, 0x50, 0x66,
- 0xa9, 0xc2, 0x3f, 0xaa, 0x48, 0x00, 0xa1, 0x4d, 0x6a, 0x80, 0x03, 0x00, 0x96, 0xcf, 0x1b, 0x9a,
- 0xb8, 0x9f, 0xde, 0x10, 0x98, 0x3e, 0x37, 0xf4, 0xc3, 0x30, 0xe6, 0xed, 0x7c, 0x2e, 0x53, 0x0e,
- 0xf4, 0xbe, 0xe2, 0x7e, 0xf6, 0x7d, 0xa7, 0x50, 0x43, 0xd7, 0x33, 0x15, 0xc5, 0x62, 0xae, 0xe5,
- 0xe2, 0xc5, 0x40, 0xe6, 0xa3, 0x63, 0x0f, 0x85, 0xd2, 0x33, 0xe6, 0x8d, 0xdc, 0x80, 0x3d, 0x79,
- 0x27, 0x21, 0x9c, 0x4f, 0xae, 0x14, 0x36, 0x4d, 0x36, 0x30, 0xa1, 0x1e, 0xf5, 0x8e, 0xb5, 0xbd,
- 0xa8, 0xc5, 0xe4, 0xb7, 0x96, 0xed, 0x10, 0x5b, 0x8c, 0xee, 0xc6, 0x8c, 0x93, 0xe9, 0xd9, 0x72,
- 0xb3, 0x10, 0xd1, 0x3e, 0x5b, 0x31, 0xc1, 0x27, 0xa4, 0x84, 0xe3, 0xc0, 0xf0, 0x1f, 0x27, 0xb7,
- 0x1f, 0x05, 0xed, 0x7c, 0xcd, 0x65, 0x01, 0xbf, 0x8d, 0x56, 0xe9, 0xfe, 0x9e, 0x53, 0x71, 0x93,
- 0x6c, 0xe0, 0x9c, 0x6e, 0x99, 0x56, 0xbb, 0x45, 0x87, 0x1f, 0x6a, 0x96, 0xac, 0x24, 0xf9, 0x7f,
- 0xbf, 0x10, 0x8c, 0x5e, 0x08, 0x12, 0x07, 0xcf, 0x8b, 0x4b, 0xcb, 0xd1, 0x6a, 0xce, 0x3d, 0x92,
- 0x81, 0x5d, 0x1d, 0x96, 0x72, 0xa8, 0xef, 0xdd, 0xb2, 0x13, 0xa8, 0xc6, 0xea, 0x07, 0x64, 0x8b,
- 0xd2, 0xe1, 0x79, 0x24, 0x0a, 0xf2, 0x92, 0xa8, 0x37, 0xe2, 0x5c, 0x89, 0xd3, 0x09, 0x60, 0x7d,
- 0xbf, 0xac, 0xff, 0xde, 0xe6, 0x8b, 0x1b, 0x38, 0x33, 0xd7, 0xa1, 0x9d, 0x05, 0xe8, 0x69, 0x27,
- 0xd9, 0xb7, 0xae, 0x72, 0xbb, 0x05, 0xee, 0x77, 0x96, 0x48, 0xa2, 0x02, 0x0d, 0x88, 0x1c, 0x4f,
- 0x22, 0xf9, 0xcd, 0xd3, 0xe1, 0x50, 0x08, 0xb6, 0xea, 0x2a, 0x96, 0x43, 0xf3, 0x8a, 0x92, 0x3b,
- 0x2b, 0x5e, 0xbc, 0xa0, 0x4f, 0xd3, 0xf1, 0xcc, 0x1c, 0xde, 0xc4, 0x91, 0x35, 0x33, 0x51, 0xe5,
- 0xe0, 0xa9, 0x75, 0xfe, 0x0a, 0x5d, 0xc8, 0x8b, 0x63, 0x33, 0xd9, 0xe0, 0x73, 0xcb, 0xdb, 0x70,
- 0x0a, 0x82, 0xb7, 0x7a, 0x5c, 0x27, 0xbf, 0xd1, 0xdc, 0x62, 0xa3, 0x20, 0x63, 0x5f, 0x54, 0x4a,
- 0xaf, 0xa3, 0xe0, 0x77, 0xbb, 0xcd, 0xab, 0x62, 0x73, 0x31, 0x72, 0x2a, 0x1d, 0x02, 0x87, 0x88,
- 0x02, 0x24, 0x10, 0x9c, 0x35, 0x5c, 0x72, 0x04, 0x1c, 0x1a, 0xea, 0x44, 0xf4, 0x41, 0xc6, 0x20,
- 0xde, 0x91, 0xf7, 0x0c, 0x4a, 0xae, 0xca, 0xb7, 0x73, 0x59, 0xf6, 0xdd, 0x8e, 0x58, 0xae, 0x8a,
- 0xcd, 0x62, 0xa6, 0x22, 0xef, 0x79, 0xbb, 0xf9, 0x4b, 0xf9, 0x71, 0x6b, 0xab, 0xe5, 0x02, 0x13,
- 0xe3, 0x35, 0xd9, 0xea, 0x95, 0x33, 0x1a, 0x22, 0x1c, 0x45, 0xe6, 0x9b, 0xfb, 0x61, 0xaf, 0x3d,
- 0xbe, 0xbe, 0x9f, 0xb8, 0x83, 0x33, 0x31, 0x5b, 0x14, 0x38, 0x2d, 0xcf, 0xe7, 0xce, 0xd3, 0xab,
- 0xca, 0xbc, 0xec, 0x30, 0x17, 0x36, 0x1d, 0x1a, 0xb7, 0x2b, 0xee, 0x53, 0x34, 0xfc, 0x63, 0x9f,
- 0x95, 0xe1, 0xf0, 0x8b, 0xdb, 0x74, 0x0c, 0x44, 0xd3, 0x04, 0x76, 0x3a, 0x41, 0xdf, 0xd0, 0x8f,
- 0xa9, 0x93, 0xd6, 0x14, 0x73, 0xc7, 0x7f, 0x2b, 0xa6, 0xb2, 0x79, 0xe4, 0x4a, 0xc8, 0xb0, 0x5e,
- 0x9a, 0xce, 0xc4, 0xf6, 0x8a, 0xeb, 0x8c, 0xa7, 0x86, 0xa6, 0x4f, 0x5f, 0x48, 0xff, 0xb4, 0x05,
- 0xf3, 0xc8, 0x81, 0x75, 0x37, 0xd5, 0x8b, 0x40, 0xdf, 0x3e, 0x20, 0x37, 0xf5, 0x5a, 0xcf, 0xbe,
- 0x6f, 0x7e, 0x22, 0xc4, 0xf7, 0xfa, 0x34, 0x4a, 0x81, 0x0a, 0x44, 0x3d, 0x1d, 0xe9, 0x6c, 0xb1,
- 0xe1, 0xd6, 0x81, 0xd4, 0x98, 0x7c, 0x65, 0xa2, 0x26, 0x97, 0x84, 0x80, 0x76, 0x58, 0x53, 0x0b,
- 0x94, 0x82, 0x08, 0x66, 0x80, 0x63, 0xf9, 0x01, 0x4a, 0xee, 0xb5, 0xe2, 0x8a, 0xfa, 0xce, 0xee,
- 0x7c, 0x97, 0xb6, 0x91, 0xe9, 0xb3, 0x5e, 0x14, 0x50, 0xd5, 0xf1, 0xdf, 0x8f, 0x5d, 0x0e, 0x78,
- 0x2f, 0xdd, 0xb2, 0x82, 0x98, 0x73, 0xc5, 0xf4, 0x32, 0x1c, 0x65, 0x6d, 0xa4, 0xe3, 0xba, 0xdb,
- 0xfa, 0x65, 0x37, 0xee, 0x57, 0x2b, 0xfa, 0x38, 0x2f, 0x14, 0x2d, 0xf6, 0x19, 0x0b, 0xe0, 0x59,
- 0xb9, 0x95, 0x02, 0xfa, 0x2f, 0x84, 0x56, 0x41, 0x76, 0xa3, 0xca, 0x30, 0xf5, 0x4b, 0x97, 0x2d,
- 0x33, 0x3b, 0x71, 0x09, 0x49, 0x48, 0x46, 0xa0, 0x79, 0xd3, 0xce, 0x32, 0x35, 0xa4, 0xb2, 0x05,
- 0x5d, 0xaf, 0x1f, 0x22, 0x48, 0xcb, 0xca, 0x5b, 0xaa, 0x69, 0x6e, 0x6f, 0x23, 0x6f, 0xcd, 0x67,
- 0x06, 0x71, 0xf1, 0x6a, 0x5f, 0x65, 0xbe, 0xb0, 0x5f, 0x7b, 0xec, 0x9e, 0x1d, 0xa4, 0xf2, 0x4b,
- 0xbc, 0xde, 0xc0, 0x84, 0x87, 0xa3, 0x2f, 0x97, 0x12, 0xc5, 0xf9, 0x34, 0x54, 0x0a, 0xf1, 0x7c,
- 0x95, 0x16, 0xe7, 0xf9, 0x83, 0x40, 0xcf, 0x42, 0xc9, 0x5b, 0xff, 0x0e, 0x01, 0xf0, 0x1b, 0xe5,
- 0x75, 0xee, 0x7c, 0x33, 0x1f, 0x00, 0x03, 0x2f, 0x92, 0xa7, 0x3d, 0x51, 0xac, 0x43, 0x67, 0xb8,
- 0x45, 0x4f, 0xde, 0x10, 0xee, 0xeb, 0x5b, 0x62, 0x65, 0x6b, 0x70, 0xc3, 0x3d, 0x46, 0x1f, 0x00,
- 0x0f, 0x08, 0xeb, 0xca, 0x33, 0xd5, 0x7d, 0x97, 0x84, 0x88, 0x8a, 0x24, 0x4d, 0x02, 0xcd, 0xee,
- 0xa0, 0x11, 0xb1, 0x2d, 0xb6, 0xf5, 0x18, 0x68, 0xb5, 0x79, 0x15, 0x5b, 0x44, 0xb3, 0xba, 0x8b,
- 0x78, 0x28, 0x08, 0x32, 0xf1, 0x25, 0x4f, 0xde, 0x48, 0x80, 0x5e, 0x9f, 0x1b, 0xc9, 0x39, 0xd3,
- 0x87, 0x9f, 0xae, 0x66, 0xf2, 0x12, 0x92, 0x17, 0xec, 0xaa, 0xbd, 0x00, 0x93, 0x00, 0x09, 0x76,
- 0xab, 0xfb, 0x2a, 0xda, 0x34, 0xe5, 0xa6, 0x2a, 0xfa, 0x9a, 0x88, 0x39, 0x66, 0xa2, 0x47, 0x2f,
- 0x71, 0x40, 0xa6, 0x7e, 0x7d, 0x52, 0x1d, 0x12, 0x21, 0x5f, 0xca, 0xe8, 0xba, 0x5a, 0x80, 0x88,
- 0x5f, 0xb0, 0x1f, 0xc1, 0x12, 0x58, 0xbd, 0x35, 0x13, 0xfb, 0x7d, 0x38, 0xea, 0x5a, 0x79, 0x4f,
- 0x37, 0x87, 0xd0, 0xbe, 0x92, 0xe1, 0x5b, 0xbe, 0x84, 0x2a, 0x40, 0x13, 0xd1, 0xe1, 0xdf, 0x39,
- 0x0b, 0x11, 0x45, 0xe9, 0x0e, 0x09, 0x9d, 0xfc, 0xeb, 0xc4, 0xc3, 0xf8, 0x26, 0xbd, 0x80, 0x38,
- 0xf7, 0x04, 0x13, 0x4f, 0x3c, 0x3d, 0x7e, 0xa3, 0xbe, 0x54, 0x1b, 0x1f, 0xf6, 0xc2, 0x11, 0x93,
- 0xd9, 0x41, 0x0f, 0x64, 0x3a, 0x1c, 0x6e, 0x19, 0x6e, 0xbf, 0x79, 0x3b, 0xbd, 0xa8, 0x03, 0xae,
- 0xf2, 0x62, 0x7f, 0xda, 0xf6, 0xe8, 0x84, 0xd9, 0xd9, 0xdb, 0xfd, 0xa2, 0x6a, 0x38, 0x60, 0x2a,
- 0x30, 0xf2, 0x1f, 0x1f, 0x63, 0xb1, 0x46, 0x7e, 0x78, 0x3e, 0x2c, 0xd9, 0xf4, 0x56, 0xdb, 0xa7,
- 0x5e, 0x67, 0x8a, 0x16, 0x9b, 0xc8, 0xea, 0x78, 0x35, 0xc2, 0xef, 0x1a, 0xb5, 0x17, 0x4e, 0xba,
- 0x17, 0x04, 0xb8, 0xd7, 0x70, 0x30, 0xb4, 0x4f, 0xb0, 0x91, 0x92, 0x73, 0x2f, 0x0a, 0xff, 0xd7,
- 0x8b, 0xcf, 0x43, 0x7d, 0xfe, 0x9e, 0xca, 0xfa, 0x69, 0x12, 0x0f, 0x51, 0xe9, 0xa4, 0x13, 0x6a,
- 0x2a, 0x4f, 0xaa, 0x5f, 0x13, 0xef, 0x45, 0x05, 0xd9, 0xaa, 0xc8, 0x28, 0x84, 0x7e, 0xc9, 0xca,
- 0xba, 0x3d, 0x93, 0xb1, 0x38, 0x16, 0x3f, 0xf1, 0x18, 0x1b, 0x32, 0xa8, 0xc2, 0xdf, 0xe3, 0x21,
- 0x8e, 0x8b, 0x70, 0x6e, 0x58, 0x65, 0x70, 0x93, 0xa5, 0xcc, 0x15, 0x2a, 0xd6, 0xb0, 0xc3, 0xcf,
- 0x6b, 0xf5, 0x09, 0xa4, 0x6c, 0x29, 0xc7, 0xcd, 0x19, 0xf6, 0x4d, 0x15, 0xb1, 0x77, 0x65, 0xdb,
- 0x7e, 0x55, 0x24, 0x05, 0x39, 0xa7, 0xf8, 0xdc, 0x16, 0x44, 0xf5, 0xf2, 0x69, 0x9f, 0x6f, 0x8e,
- 0xaf, 0x6e, 0xfc, 0x9a, 0x75, 0x57, 0x22, 0x2f, 0x33, 0xf8, 0xaa, 0x3d, 0x4e, 0x70, 0x2d, 0x74,
- 0x33, 0xbc, 0xea, 0xcf, 0x48, 0xe7, 0xb8, 0xd0, 0xf5, 0xda, 0xd3, 0xe3, 0xa7, 0x43, 0x4f, 0xdd,
- 0x7c, 0x80, 0x07, 0x69, 0xc9, 0x2d, 0x2c, 0x58, 0xa1, 0x4d, 0x9c, 0xd7, 0x20, 0xb6, 0xaf, 0xb0,
- 0x5f, 0x3d, 0x5b, 0x35, 0x3f, 0xf4, 0x51, 0x52, 0x47, 0xc5, 0xaa, 0x9c, 0x4d, 0x9c, 0xa4, 0x73,
- 0x35, 0xd9, 0xa0, 0xa4, 0x52, 0x0a, 0x7b, 0xcb, 0x6c, 0xef, 0xb4, 0x65, 0x06, 0xc4, 0x95, 0x3b,
- 0x59, 0xf2, 0xd1, 0x09, 0x0b, 0x22, 0x9c, 0x72, 0xac, 0x4d, 0xb1, 0xb6, 0x3b, 0x72, 0xcd, 0xad,
- 0x91, 0x95, 0x49, 0x30, 0x43, 0x54, 0x0e, 0xf3, 0x53, 0x89, 0xd2, 0x13, 0x40, 0xca, 0x44, 0x90,
- 0x37, 0x11, 0xf8, 0x9a, 0xbf, 0xf5, 0x6f, 0x0b, 0xa4, 0x47, 0x03, 0x59, 0x6a, 0x48, 0xdc, 0x11,
- 0xeb, 0x51, 0x1b, 0x56, 0x42, 0x03, 0xc9, 0x4e, 0xbc, 0x4c, 0x3f, 0x05, 0x48, 0x32, 0x48, 0x7d,
- 0x5b, 0x77, 0x4b, 0x75, 0xbf, 0x14, 0x72, 0x31, 0x86, 0x10, 0x99, 0x87, 0x33, 0x4c, 0x3c, 0xc2,
- 0x8a, 0x76, 0x36, 0xfc, 0x44, 0x19, 0xe4, 0xd1, 0x9d, 0x29, 0x7c, 0x17, 0xea, 0xa6, 0x3a, 0x90,
- 0x4b, 0x01, 0x5b, 0x37, 0x45, 0xc6, 0x4f, 0x59, 0xb0, 0x6a, 0xeb, 0xe4, 0x2c, 0x0c, 0x87, 0x91,
- 0x06, 0x6d, 0xeb, 0xea, 0x3b, 0x3d, 0xbc, 0x1a, 0x0a, 0xd8, 0x1b, 0xd6, 0x71, 0xa5, 0x6c, 0x4c,
- 0x1c, 0xde, 0x46, 0xb4, 0x2c, 0x15, 0xc3, 0xe8, 0x7d, 0x70, 0x96, 0x85, 0x1d, 0xc3, 0x53, 0x3c,
- 0xdc, 0x1b, 0x4f, 0xe2, 0x79, 0x39, 0x74, 0xe5, 0x49, 0x8e, 0xd4, 0xb5, 0x59, 0x19, 0xc1, 0xe9,
- 0x37, 0xbd, 0xad, 0x90, 0x33, 0x9f, 0xaf, 0x46, 0xfe, 0xd8, 0xcd, 0x30, 0x04, 0x1d, 0x96, 0xf8,
- 0x2d, 0xe6, 0xc4, 0xfb, 0xac, 0x56, 0xb1, 0x26, 0x33, 0xc0, 0x38, 0x19, 0x3b, 0xe3, 0xf4, 0xaf,
- 0x4f, 0x77, 0x5c, 0xe3, 0xc0, 0x0b, 0x81, 0x29, 0x7f, 0xd4, 0x43, 0x4d, 0x7b, 0x87, 0xd4, 0x28,
- 0x37, 0x22, 0xbb, 0x16, 0x54, 0xe6, 0xe2, 0x55, 0x11, 0xda, 0xf4, 0xc5, 0xe1, 0xbb, 0xdb, 0xf9,
- 0xb4, 0xd7, 0x25, 0x27, 0x09, 0x4d, 0x37, 0x82, 0x9b, 0x64, 0x31, 0xbc, 0x3d, 0x2c, 0x66, 0xcd,
- 0x60, 0x3a, 0x74, 0x7d, 0xfd, 0xdb, 0x74, 0x31, 0x4e, 0x35, 0x98, 0x76, 0x84, 0x87, 0x49, 0x2d,
- 0xce, 0x50, 0x57, 0xbd, 0x12, 0x65, 0xfb, 0xa4, 0x7b, 0x4e, 0xb6, 0x8a, 0x4d, 0x73, 0xf2, 0xfb,
- 0xc0, 0x35, 0xcf, 0xf7, 0x79, 0xb2, 0x5d, 0x8d, 0xbc, 0xd3, 0x7d, 0x0c, 0xa7, 0xd1, 0xf1, 0xdb,
- 0x10, 0xa3, 0x91, 0xae, 0x99, 0xc5, 0xed, 0x80, 0x15, 0xb7, 0x5e, 0xea, 0x11, 0xa7, 0xb1, 0x64,
- 0x7c, 0x3b, 0x08, 0xfd, 0xf0, 0xa1, 0x2a, 0x9f, 0xaf, 0xf0, 0x9b, 0x43, 0x43, 0x4f, 0xc1, 0xd5,
- 0x39, 0xba, 0xda, 0x3f, 0x49, 0x5d, 0x13, 0x53, 0xa1, 0x3d, 0x34, 0xc4, 0xd2, 0xdb, 0xf5, 0x76,
- 0x42, 0x37, 0x07, 0x2e, 0xd6, 0x0a, 0x3d, 0x12, 0xe4, 0x6f, 0x68, 0x4e, 0x70, 0x0d, 0x29, 0x9e,
- 0x54, 0x07, 0x48, 0xba, 0xc7, 0xfa, 0xfd, 0x73, 0x7d, 0x6d, 0x0d, 0x07, 0x98, 0xeb, 0x5e, 0x67,
- 0xa5, 0x6a, 0x6a, 0x91, 0x87, 0x23, 0x59, 0xf6, 0x9c, 0x90, 0xa2, 0xd7, 0x07, 0x93, 0xb6, 0xed,
- 0xe2, 0x38, 0x2b, 0xc0, 0x2d, 0x08, 0x98, 0x6c, 0x11, 0x45, 0x05, 0x8d, 0xa8, 0x17, 0xf1, 0x10,
- 0xcb, 0xca, 0xf5, 0x90, 0x41, 0x15, 0x75, 0x22, 0x62, 0xd2, 0x0c, 0xc2, 0xf7, 0x5a, 0xb0, 0x64,
- 0xbe, 0xf7, 0x6d, 0x57, 0xa6, 0x64, 0x28, 0x12, 0x1d, 0x98, 0x93, 0x2b, 0xf5, 0xd7, 0xa2, 0x3f,
- 0x35, 0x1b, 0xd4, 0x49, 0x68, 0x15, 0xa9, 0x19, 0xa1, 0x8c, 0x03, 0xe7, 0x83, 0x4d, 0x2d, 0xf3,
- 0xe8, 0xc3, 0xbd, 0xec, 0x1d, 0x7e, 0x3f, 0x68, 0x3a, 0x66, 0xac, 0xbe, 0xb5, 0xcc, 0xd3, 0x57,
- 0xf7, 0x84, 0xac, 0xd4, 0x32, 0x21, 0xed, 0xb1, 0x2b, 0xe7, 0x4c, 0x8d, 0x5a, 0xeb, 0xf6, 0x06,
- 0xcd, 0xa7, 0xad, 0x7e, 0x78, 0xc5, 0x1f, 0xce, 0x35, 0x02, 0x47, 0xd3, 0x20, 0x73, 0x0f, 0x26,
- 0xfc, 0x23, 0xa8, 0x84, 0xf5, 0x58, 0xc0, 0xc1, 0x43, 0x60, 0x47, 0x61, 0x1f, 0x8a, 0xe7, 0xe9,
- 0x9a, 0x6e, 0x7f, 0xba, 0xb4, 0x06, 0xc3, 0x9b, 0x1e, 0x5b, 0x98, 0xbc, 0x0e, 0x52, 0x3f, 0x4c,
- 0x40, 0xd9, 0xbc, 0x7b, 0x85, 0x9e, 0x39, 0x36, 0xba, 0x2a, 0x63, 0xa5, 0xe4, 0x97, 0xad, 0xfc,
- 0xbd, 0xa2, 0xd1, 0x80, 0x3b, 0x0c, 0xe6, 0xc8, 0x08, 0x62, 0xe1, 0x24, 0x9a, 0x90, 0x7e, 0xb2,
- 0x6f, 0x09, 0xac, 0xbc, 0x89, 0xc2, 0x8b, 0xc5, 0x07, 0xc7, 0x4e, 0x20, 0xf1, 0xe8, 0x81, 0x61,
- 0x67, 0xf1, 0x7d, 0x93, 0xdb, 0xb8, 0x31, 0xde, 0xd4, 0x90, 0x8e, 0x49, 0x30, 0xeb, 0xc1, 0xff,
- 0x9f, 0x73, 0xd6, 0x75, 0x0e, 0x2f, 0x38, 0xe5, 0x86, 0xb6, 0x5f, 0x35, 0x35, 0x0e, 0xd9, 0xea,
- 0x73, 0xe8, 0xf3, 0xe2, 0x7a, 0x08, 0xe0, 0x9c, 0x9a, 0xbd, 0xc8, 0x5d, 0xd3, 0xda, 0x4c, 0x7b,
- 0x13, 0xac, 0x71, 0x28, 0xf6, 0x8f, 0xcf, 0xcb, 0x4d, 0x70, 0x7e, 0x8f, 0x02, 0x44, 0xfa, 0xdf,
- 0x41, 0x18, 0x02, 0xa4, 0x3f, 0xed, 0xdc, 0x0a, 0x5c, 0x84, 0x45, 0xaa, 0x2c, 0x35, 0x97, 0x4d,
- 0x29, 0x7d, 0x78, 0xc8, 0x04, 0xe4, 0x8c, 0xb5, 0xa9, 0xed, 0xd9, 0x54, 0x25, 0xca, 0x9a, 0x91,
- 0xb4, 0x98, 0xd9, 0x5e, 0xba, 0x54, 0x3b, 0x8b, 0xec, 0x3c, 0xa3, 0xcc, 0xfa, 0x08, 0xa0, 0x2e,
- 0xe3, 0x0d, 0xa3, 0x21, 0xaa, 0x9a, 0x3d, 0x7f, 0xdd, 0x09, 0xfc, 0xae, 0xa8, 0x4f, 0xd1, 0x4d,
- 0xd2, 0xc6, 0x8b, 0x17, 0xae, 0x3c, 0xb7, 0x38, 0xcc, 0xd0, 0xa1, 0x21, 0x98, 0x20, 0xbd, 0xbb,
- 0x03, 0xa4, 0x47, 0x24, 0x37, 0x7f, 0xd5, 0xdb, 0xdf, 0x84, 0x5d, 0xd9, 0x19, 0x17, 0xde, 0xb8,
- 0x51, 0x09, 0xed, 0x02, 0xc6, 0x72, 0x9a, 0xd2, 0xfa, 0x01, 0x81, 0xe6, 0xbd, 0x7a, 0x58, 0x17,
- 0xed, 0x88, 0xb1, 0x83, 0x16, 0x82, 0x73, 0xf0, 0xa7, 0xc2, 0xe6, 0x67, 0x8e, 0x4a, 0xb1, 0xac,
- 0x76, 0x66, 0xa8, 0xe2, 0x35, 0xcc, 0x13, 0xfe, 0x5b, 0xed, 0x9d, 0x60, 0x24, 0x5b, 0x74, 0x3c,
- 0x81, 0xd6, 0x1c, 0x31, 0xdf, 0xc8, 0xd5, 0x74, 0xbf, 0xcb, 0x4f, 0x53, 0x68, 0x05, 0x90, 0xa5,
- 0xba, 0xd5, 0x4f, 0x80, 0x43, 0x50, 0x65, 0x29, 0x42, 0xf2, 0x1a, 0x88, 0xb8, 0x61, 0xbf, 0x65,
- 0x59, 0xad, 0x2f, 0x2e, 0xf1, 0x4f, 0xef, 0xe4, 0xc0, 0xde, 0x37, 0xb5, 0xfb, 0xd9, 0x2e, 0x50,
- 0x2a, 0x3e, 0xac, 0xe4, 0x45, 0xa4, 0xd5, 0x2f, 0xac, 0x9a, 0xc1, 0x7c, 0xd4, 0x95, 0xe1, 0x86,
- 0x4d, 0xae, 0x2b, 0x5e, 0x11, 0x7b, 0xe7, 0x38, 0x5e, 0x93, 0x53, 0x95, 0x9c, 0x65, 0xcc, 0x8b,
- 0x78, 0x6a, 0x0e, 0x28, 0x68, 0xba, 0x50, 0xd0, 0x74, 0x5d, 0x7c, 0x62, 0x2b, 0xa3, 0xb4, 0xe0,
- 0x96, 0x8e, 0x2b, 0x0b, 0xcc, 0xbc, 0x0c, 0x4f, 0xcb, 0xe6, 0x89, 0x4e, 0xd0, 0x2e, 0x17, 0x9a,
- 0x37, 0x13, 0x55, 0x68, 0x2c, 0x67, 0xf2, 0x12, 0x92, 0x35, 0x08, 0x93, 0x17, 0xaf, 0x70, 0x8b,
- 0x08, 0x8e, 0x4e, 0x5e, 0x91, 0x1d, 0x8e, 0x8e, 0x5a, 0xb3, 0xf8, 0xa0, 0x11, 0x1f, 0xe0, 0xfb,
- 0xf3, 0xf1, 0xb2, 0x1c, 0x56, 0x97, 0x6d, 0xd4, 0x6d, 0xa3, 0x19, 0x50, 0x00, 0xf4, 0xef, 0x7c,
- 0x90, 0xe8, 0x89, 0x33, 0x6d, 0xf9, 0x90, 0x44, 0xa0, 0x7d, 0xa2, 0x6e, 0xab, 0x87, 0xe5, 0xc9,
- 0xe8, 0xc5, 0x28, 0x64, 0xf6, 0x29, 0x95, 0xf4, 0x69, 0xb3, 0xa1, 0xbc, 0x14, 0xc2, 0x2f, 0x30,
- 0x50, 0x80, 0x08, 0x58, 0xae, 0x0d, 0x72, 0x66, 0x2c, 0x30, 0x43, 0xfe, 0x07, 0x0d, 0xa3, 0x1d,
- 0x58, 0x1c, 0x16, 0x5e, 0x1d, 0x80, 0xf6, 0x99, 0x53, 0x92, 0xd6, 0x57, 0x6c, 0x83, 0xae, 0x80,
- 0x83, 0x69, 0xa9, 0x22, 0x7b, 0xbc, 0x6f, 0x11, 0x94, 0x8c, 0xab, 0xa5, 0x25, 0x8d, 0x52, 0x66,
- 0x33, 0x09, 0xb6, 0x67, 0x93, 0x9d, 0x44, 0x09, 0xf8, 0xf0, 0xdc, 0x06, 0x5d, 0xb3, 0x49, 0x50,
- 0xcc, 0x9a, 0xf8, 0x85, 0xc1, 0x5f, 0xf7, 0x43, 0xa4, 0x72, 0xb9, 0x05, 0xad, 0xcd, 0x5e, 0x29,
- 0x1c, 0x37, 0xd2, 0x0b, 0xac, 0x73, 0xd4, 0x75, 0x4f, 0x26, 0x06, 0x1e, 0x4b, 0x9f, 0xef, 0xea,
- 0xb0, 0xee, 0x3f, 0xd9, 0xb4, 0x11, 0xd0, 0x25, 0x18, 0x00, 0x09, 0x21, 0xe2, 0x60, 0x67, 0x18,
- 0x7e, 0x87, 0x87, 0xb0, 0x14, 0xaf, 0x4d, 0xa2, 0x88, 0x81, 0x77, 0x71, 0x33, 0x5c, 0xb8, 0x0d,
- 0x12, 0x3c, 0x5e, 0xb0, 0x52, 0xb0, 0x29, 0x39, 0xf2, 0xed, 0x6a, 0xe0, 0x94, 0x58, 0xd7, 0x23,
- 0x4b, 0xa7, 0x3d, 0x93, 0xc9, 0x05, 0x06, 0xba, 0x32, 0x73, 0x00, 0x1e, 0xeb, 0x6f, 0x64, 0xd5,
- 0x89, 0x17, 0x45, 0xcd, 0x91, 0x13, 0x42, 0xb5, 0xd3, 0x6f, 0x9d, 0xa2, 0xde, 0xbc, 0x07, 0x23,
- 0x4f, 0x1d, 0xf9, 0x89, 0x99, 0x8c, 0x9e, 0xde, 0xa4, 0x7f, 0xab, 0xfc, 0x54, 0x04, 0x0f, 0x11,
- 0x5c, 0xbc, 0xd6, 0xd3, 0x54, 0x13, 0xe9, 0x7a, 0x99, 0x04, 0x57, 0xf2, 0xf0, 0x7c, 0xb7, 0x56,
- 0x5c, 0x9c, 0x37, 0xbd, 0xfc, 0xa5, 0xb0, 0x8d, 0x3d, 0x02, 0x0e, 0x61, 0xdd, 0x20, 0xd6, 0x44,
- 0x8a, 0x0b, 0x58, 0xd8, 0x33, 0x17, 0x2d, 0x85, 0x0c, 0xb1, 0x7f, 0x6a, 0xb1, 0xca, 0x37, 0xb8,
- 0xba, 0x10, 0x09, 0x12, 0x28, 0xac, 0x00, 0x2b, 0x3e, 0x5e, 0x0e, 0x92, 0xe3, 0x6b, 0xef, 0xe6,
- 0xc6, 0x8e, 0x28, 0xfa, 0xc2, 0x58, 0x55, 0x09, 0x94, 0xe9, 0xaa, 0xad, 0x4e, 0x2d, 0x93, 0xd7,
- 0x2d, 0xdb, 0xfb, 0xce, 0x3b, 0x7d, 0x47, 0x4c, 0xa7, 0x1f, 0x07, 0x8d, 0x6b, 0x09, 0x81, 0xf8,
- 0x72, 0x76, 0x84, 0xc8, 0xc1, 0xf9, 0x95, 0x4b, 0x8e, 0xb0, 0xaa, 0xe6, 0x37, 0xad, 0xcd, 0x21,
- 0x92, 0xd8, 0x45, 0x2d, 0xda, 0xda, 0xa1, 0x2f, 0x85, 0x89, 0x16, 0x68, 0x5d, 0x41, 0x8a, 0x98,
- 0x09, 0x8c, 0xcc, 0x32, 0xa2, 0xc8, 0xfc, 0xea, 0x3d, 0x55, 0xda, 0x4d, 0x53, 0x17, 0x93, 0xbc,
- 0x5b, 0x59, 0x9f, 0x50, 0x5c, 0xcf, 0x03, 0x6b, 0x94, 0x5d, 0xbc, 0x6d, 0xe7, 0x9c, 0x6d, 0x62,
- 0x95, 0xaa, 0x35, 0xa3, 0x23, 0x42, 0x9f, 0xfb, 0x5e, 0xc1, 0xd7, 0x49, 0x89, 0xbd, 0xc4, 0xe8,
- 0xcf, 0x22, 0xd3, 0xcf, 0x3d, 0x2f, 0x6d, 0x08, 0x0c, 0x4c, 0x17, 0x5b, 0x87, 0x44, 0x9f, 0x8b,
- 0x73, 0xe0, 0xe9, 0x36, 0xb7, 0x92, 0x5b, 0xfd, 0x62, 0x76, 0x7b, 0x67, 0xc0, 0x47, 0xff, 0x68,
- 0x01, 0x91, 0x85, 0x3a, 0x95, 0xc7, 0x19, 0xf7, 0xb0, 0x72, 0x83, 0x88, 0x5a, 0xdc, 0x58, 0x14,
- 0xe8, 0xa7, 0x53, 0x9e, 0x69, 0xe4, 0x6c, 0x39, 0x3d, 0xbe, 0x5f, 0x72, 0x6b, 0xb4, 0xd5, 0x80,
- 0xfb, 0x44, 0x24, 0x88, 0x08, 0x14, 0xf6, 0xe8, 0xd8, 0x2c, 0x1a, 0x5c, 0xf0, 0x86, 0x79, 0xc4,
- 0x40, 0x5c, 0xc8, 0xab, 0x53, 0x27, 0xd3, 0xce, 0x00, 0x99, 0x7f, 0x6a, 0x91, 0x35, 0x81, 0x90,
- 0x8a, 0x5f, 0x2d, 0xf6, 0x12, 0x06, 0xa5, 0x75, 0x04, 0x85, 0x35, 0x66, 0x23, 0x5f, 0xc6, 0x00,
- 0x69, 0x67, 0xf6, 0x5e, 0x7b, 0x18, 0x92, 0x80, 0x26, 0x03, 0xb0, 0x73, 0xcb, 0x8e, 0xba, 0xf7,
- 0xda, 0x6f, 0xee, 0x8f, 0x6c, 0x3f, 0xcd, 0xc6, 0x73, 0x51, 0x5d, 0xdc, 0x55, 0x69, 0xcd, 0x02,
- 0x24, 0x52, 0x62, 0x83, 0xba, 0x27, 0xaa, 0x73, 0x15, 0xe7, 0xd4, 0x7a, 0xc1, 0xd5, 0x8e, 0xad,
- 0xb4, 0x68, 0xb9, 0x40, 0xcb, 0x5d, 0x9e, 0x67, 0x84, 0x2b, 0x14, 0x78, 0xcd, 0xa5, 0xc2, 0x81,
- 0x91, 0x3b, 0x0f, 0x70, 0x43, 0x26, 0xba, 0x24, 0x3d, 0x14, 0x08, 0x13, 0xba, 0xf9, 0x7c, 0x38,
- 0x55, 0x51, 0x57, 0x6e, 0xef, 0xf0, 0x92, 0xd1, 0x06, 0xb4, 0x06, 0xd5, 0xf1, 0xf5, 0xb4, 0xda,
- 0x1b, 0xad, 0x52, 0xc2, 0x6d, 0x1e, 0x82, 0xb0, 0x04, 0x5f, 0x5d, 0x92, 0x8d, 0x98, 0x9d, 0x30,
- 0x24, 0x5f, 0x47, 0x9f, 0x34, 0x02, 0x9a, 0x83, 0x82, 0x5e, 0xcd, 0xeb, 0x13, 0x40, 0x15, 0xa5,
- 0x13, 0xd3, 0xff, 0x19, 0x1c, 0x67, 0x74, 0xf5, 0xf3, 0x50, 0xb9, 0xbf, 0xa9, 0x64, 0x8a, 0x90,
- 0x69, 0xc2, 0x93, 0xf9, 0xfc, 0xca, 0xa5, 0x2a, 0xb7, 0x99, 0x70, 0x93, 0x2a, 0x4b, 0x57, 0x77,
- 0x8f, 0xc9, 0x58, 0xc5, 0x18, 0xff, 0x8d, 0xdc, 0x02, 0x41, 0xac, 0x93, 0xee, 0x5b, 0x14, 0xd8,
- 0xfe, 0x92, 0x49, 0x61, 0xc3, 0xda, 0xfe, 0xf9, 0x70, 0x17, 0x87, 0xe2, 0x34, 0xd6, 0xac, 0x96,
- 0x49, 0xfc, 0x61, 0xf0, 0x72, 0x44, 0x95, 0x88, 0x34, 0x2c, 0x68, 0x0d, 0x42, 0x62, 0xb2, 0x0a,
- 0x53, 0x58, 0xb1, 0x56, 0x14, 0x08, 0x66, 0x86, 0x39, 0x0a, 0xd5, 0x41, 0xb6, 0x24, 0x52, 0xd2,
- 0xfb, 0x68, 0x77, 0xac, 0x63, 0xfb, 0x60, 0xe4, 0x31, 0x24, 0xdd, 0x5d, 0x35, 0xc2, 0x64, 0x8a,
- 0xd2, 0x2f, 0xe8, 0xd4, 0x22, 0xc2, 0xcc, 0x7e, 0x7d, 0x83, 0x05, 0x58, 0x62, 0xe6, 0xc9, 0x9b,
- 0xf9, 0xd4, 0x60, 0xa2, 0x38, 0x4b, 0x6c, 0x3b, 0x50, 0xe3, 0x02, 0x4e, 0xa3, 0x7c, 0x2c, 0x7f,
- 0x50, 0xd8, 0x53, 0xa5, 0x88, 0x42, 0x4a, 0x67, 0x76, 0x94, 0x44, 0x08, 0x89, 0x23, 0x1f, 0x99,
- 0x5d, 0x53, 0xec, 0x25, 0x38, 0x73, 0x85, 0xd2, 0xe2, 0x15, 0x6a, 0xd6, 0x5d, 0x93, 0xf2, 0xca,
- 0x9d, 0x2a, 0x51, 0x39, 0xae, 0xad, 0xe4, 0xb7, 0xf2, 0x44, 0x1c, 0x1f, 0xcf, 0x98, 0xb5, 0x13,
- 0x7d, 0xa5, 0x2f, 0xf7, 0x4b, 0x14, 0xab, 0x4d, 0xa7, 0x0c, 0x6c, 0x32, 0x13, 0x86, 0xcf, 0x04,
- 0x26, 0x2d, 0xe6, 0x35, 0xef, 0x50, 0xc5, 0x48, 0x7d, 0x72, 0x08, 0x46, 0xc5, 0xa8, 0xdf, 0x0e,
- 0x54, 0xe7, 0x19, 0xd2, 0xbc, 0xbf, 0x45, 0x3b, 0x23, 0xed, 0xbb, 0xdd, 0x0d, 0x33, 0x2c, 0x92,
- 0x4d, 0x55, 0x80, 0x13, 0xaa, 0xf7, 0x0c, 0xd0, 0x2d, 0xf7, 0x65, 0xaa, 0xac, 0xa5, 0x32, 0xc1,
- 0xaa, 0xf4, 0xae, 0x79, 0xc7, 0x57, 0x32, 0xa0, 0x5e, 0xf0, 0x75, 0x87, 0x54, 0xb9, 0x42, 0x6a,
- 0xe3, 0x27, 0x52, 0xd9, 0x40, 0x01, 0x0e, 0x86, 0x70, 0x43, 0xd9, 0x47, 0x0a, 0xd4, 0x4a, 0x8a,
- 0xd4, 0xd8, 0x57, 0x65, 0x6c, 0x19, 0x5d, 0x4b, 0x87, 0x7e, 0xb3, 0x6e, 0x7c, 0xc6, 0xd6, 0x05,
- 0x56, 0xef, 0x34, 0x2c, 0x38, 0xa5, 0x4d, 0xec, 0x30, 0x8f, 0x46, 0x7b, 0x07, 0x7a, 0x6e, 0xdf,
- 0x05, 0xfe, 0xeb, 0x1d, 0xe1, 0xae, 0x9e, 0xa4, 0xbd, 0x9d, 0x51, 0x08, 0xd3, 0xf2, 0xa7, 0x3e,
- 0x68, 0x33, 0x63, 0xd6, 0x0f, 0xf0, 0xd8, 0x07, 0x4f, 0x52, 0x98, 0x43, 0xb0, 0x2e, 0x95, 0x50,
- 0x89, 0x1c, 0x1e, 0x2f, 0xb2, 0xcd, 0xbd, 0x4c, 0xbb, 0x67, 0x35, 0x86, 0x38, 0xa9, 0xd7, 0x38,
- 0xa0, 0x19, 0x9c, 0x1f, 0xfd, 0x7d, 0xde, 0x03, 0xab, 0x46, 0xec, 0xf5, 0x62, 0x22, 0xc5, 0xaa,
- 0x87, 0xd4, 0x59, 0x57, 0x1a, 0xdb, 0xd4, 0xfa, 0xe3, 0x24, 0xa7, 0x35, 0xa3, 0xf0, 0x35, 0xe6,
- 0x8b, 0x95, 0xc2, 0x84, 0xe5, 0x9a, 0x01, 0xc1, 0x1b, 0x31, 0x63, 0x32, 0xa7, 0x6b, 0xeb, 0x89,
- 0x1f, 0xab, 0xdd, 0x3f, 0xb9, 0x34, 0xda, 0x2d, 0x3b, 0x5b, 0xb4, 0xf8, 0x04, 0xc8, 0xed, 0x60,
- 0xc3, 0x2e, 0x11, 0x38, 0x8b, 0x7a, 0xcd, 0x28, 0xab, 0xee, 0x6b, 0x0c, 0xd0, 0x13, 0x2a, 0x65,
- 0xee, 0xc8, 0xfb, 0x6b, 0x87, 0xd3, 0xe5, 0x39, 0x8b, 0xf7, 0xef, 0xab, 0x46, 0xac, 0x56, 0xf9,
- 0x4d, 0xc9, 0x2d, 0xa7, 0x69, 0x8b, 0x5f, 0x8e, 0x4d, 0xa4, 0xda, 0xeb, 0x57, 0x44, 0xb2, 0xef,
- 0x97, 0xd8, 0xea, 0xed, 0x86, 0x8b, 0xdc, 0x44, 0x83, 0xcc, 0xa3, 0xdf, 0xea, 0xd8, 0xdc, 0x74,
- 0xf2, 0x8e, 0xe6, 0x65, 0x26, 0x74, 0x0a, 0x2a, 0x17, 0x11, 0xee, 0x21, 0xc5, 0x0a, 0x06, 0xbb,
- 0xc9, 0xaa, 0xee, 0x40, 0x01, 0x12, 0x86, 0x93, 0xdb, 0x90, 0x24, 0x10, 0xad, 0xbf, 0x8d, 0x19,
- 0x34, 0x0f, 0xf9, 0xe9, 0xb7, 0x7f, 0xb9, 0xab, 0x9a, 0xf3, 0x71, 0x13, 0x1d, 0x79, 0xcf, 0xe8,
- 0xe7, 0x69, 0x67, 0x0f, 0xfe, 0xea, 0x69, 0x4e, 0xb6, 0x2d, 0x36, 0x49, 0x75, 0x45, 0x7e, 0x85,
- 0xd2, 0x4c, 0x4f, 0xb3, 0xc9, 0x21, 0xed, 0xb3, 0x17, 0x33, 0xba, 0x40, 0x6f, 0x14, 0x36, 0x49,
- 0x84, 0x4b, 0xa7, 0x21, 0x2e, 0x40, 0xd4, 0xb8, 0x05, 0x3a, 0x2e, 0x4f, 0x43, 0xa5, 0x69, 0xdf,
- 0xc3, 0x2d, 0x62, 0x41, 0xec, 0x86, 0xcc, 0xd1, 0x81, 0x93, 0x03, 0xb4, 0x5e, 0x2a, 0xed, 0xfa,
- 0x77, 0xa4, 0x4e, 0xdd, 0x71, 0xce, 0x7a, 0xe4, 0x45, 0x56, 0x48, 0x08, 0x1b, 0x13, 0xef, 0xc2,
- 0x19, 0x53, 0x69, 0xb4, 0xf6, 0xd8, 0x95, 0x9b, 0x46, 0x9d, 0x04, 0x23, 0xbd, 0x9a, 0xf0, 0xe9,
- 0x31, 0xe2, 0xa4, 0x93, 0x6b, 0xed, 0xe2, 0x22, 0x81, 0x6e, 0xdb, 0x5e, 0x1a, 0xe9, 0x9a, 0x58,
- 0xcb, 0xa7, 0x86, 0x73, 0x3d, 0x5b, 0xed, 0xc4, 0x44, 0x83, 0x4c, 0x0e, 0x9b, 0x8e, 0x82, 0x5d,
- 0x5e, 0xae, 0x2a, 0xf5, 0x5b, 0xe5, 0x91, 0xef, 0x53, 0xd9, 0x7e, 0x93, 0xe5, 0x66, 0x9a, 0x63,
- 0x78, 0x78, 0x58, 0x8a, 0x63, 0x5f, 0x8c, 0xf6, 0x8a, 0xd9, 0x2d, 0xaa, 0xbe, 0x67, 0x56, 0x67,
- 0x20, 0x9d, 0x39, 0xfd, 0x4c, 0xae, 0xd3, 0x70, 0x86, 0x7e, 0x20, 0x78, 0x6d, 0xe2, 0x44, 0x13,
- 0x90, 0x62, 0x7f, 0x02, 0xcc, 0xde, 0x97, 0xf4, 0x4e, 0x76, 0xb5, 0xd2, 0xb4, 0x4d, 0x9b, 0x74,
- 0x8a, 0xb4, 0x80, 0x83, 0x40, 0xc2, 0x94, 0x02, 0x9a, 0x71, 0xe0, 0x79, 0x3d, 0x77, 0xb5, 0x3d,
- 0xb2, 0xea, 0x12, 0x98, 0x05, 0x47, 0x1d, 0x5c, 0x79, 0x94, 0xdc, 0x55, 0xa7, 0x6f, 0x30, 0x7f,
- 0x83, 0x50, 0xd1, 0x95, 0x21, 0x87, 0x0b, 0x89, 0x86, 0x15, 0x25, 0x35, 0x74, 0xcd, 0x1d, 0x38,
- 0x48, 0x2a, 0xcf, 0xb3, 0x97, 0xbc, 0x2b, 0xb7, 0xab, 0x10, 0x8d, 0x17, 0x5d, 0xef, 0xad, 0xf2,
- 0xe3, 0x1b, 0x56, 0x23, 0x8d, 0x2c, 0x33, 0x59, 0x3a, 0x99, 0x86, 0x6e, 0xd6, 0xcb, 0xc5, 0x8c,
- 0x43, 0x1b, 0x5e, 0x26, 0x88, 0xf1, 0x3e, 0xf8, 0x3e, 0xa7, 0xb9, 0xc6, 0xb5, 0xac, 0x3b, 0xb7,
- 0x38, 0x0d, 0xb2, 0xc5, 0x15, 0xb4, 0x55, 0x97, 0xc3, 0x14, 0x0c, 0x19, 0x93, 0x21, 0xba, 0xb9,
- 0xd6, 0x1f, 0x28, 0x8b, 0x87, 0xfe, 0x20, 0x21, 0x08, 0xfb, 0x32, 0x16, 0xf7, 0xa4, 0xa7, 0x30,
- 0x6a, 0x02, 0xd5, 0x67, 0xf6, 0xff, 0x37, 0xee, 0xd7, 0x1b, 0x34, 0x6f, 0x0b, 0xc2, 0x94, 0x91,
- 0xa6, 0x78, 0x50, 0xf2, 0x9e, 0x58, 0x44, 0x11, 0xe4, 0x8b, 0x23, 0x3c, 0xe6, 0xa2, 0x8c, 0x1e,
- 0x96, 0xdf, 0x41, 0x11, 0x47, 0x89, 0x2a, 0x2a, 0xe4, 0xc8, 0xd2, 0x12, 0x98, 0xb0, 0x37, 0x02,
- 0xf6, 0xa6, 0x3b, 0xa1, 0xf3, 0x30, 0x9c, 0xda, 0x35, 0x0c, 0xef, 0xc2, 0x36, 0xaf, 0xb7, 0x2c,
- 0xe9, 0xf6, 0x64, 0x0d, 0x05, 0x84, 0xf6, 0x8d, 0x61, 0xeb, 0xda, 0x36, 0x05, 0x42, 0x56, 0xde,
- 0xfe, 0x36, 0x7c, 0x42, 0x1c, 0x5e, 0xfb, 0x9b, 0xe2, 0x22, 0xcc, 0x42, 0xff, 0xb1, 0xe6, 0xfd,
- 0x02, 0x4a, 0x1c, 0x44, 0xa8, 0x78, 0x87, 0xc5, 0x58, 0xed, 0x55, 0x0f, 0x29, 0x3b, 0x50, 0xf8,
- 0x93, 0x05, 0xa5, 0x3c, 0x1a, 0xd5, 0x7c, 0xcd, 0x5f, 0xab, 0x8a, 0x95, 0xb0, 0x65, 0x86, 0x86,
- 0x3d, 0x8c, 0x05, 0x21, 0x46, 0xfa, 0xf7, 0x7a, 0x2a, 0xa6, 0x09, 0x0f, 0xf4, 0xaa, 0x2d, 0x3d,
- 0xf9, 0x63, 0x66, 0x22, 0x9b, 0xc7, 0x74, 0x3f, 0xbc, 0x97, 0x58, 0xbb, 0x41, 0x02, 0x60, 0xd1,
- 0xe2, 0xfe, 0x26, 0x22, 0x91, 0x76, 0x44, 0xce, 0x94, 0x2c, 0xd1, 0x13, 0x56, 0x06, 0xc0, 0xa4,
- 0xc4, 0x36, 0xe9, 0x84, 0x78, 0xa0, 0xc6, 0x02, 0x97, 0xa5, 0x27, 0xd4, 0x9e, 0x78, 0x51, 0xca,
- 0x7e, 0x55, 0x94, 0xcd, 0xf3, 0x64, 0xe9, 0x0f, 0xf5, 0x37, 0xe6, 0x15, 0x09, 0xed, 0x72, 0xd2,
- 0x25, 0xd6, 0xf2, 0xde, 0x93, 0xbc, 0xc3, 0x7c, 0x27, 0x63, 0x5e, 0x50, 0x2b, 0xf4, 0x17, 0xd0,
- 0x09, 0x3a, 0xca, 0xb5, 0xad, 0x92, 0xf8, 0x9a, 0x52, 0x5d, 0x74, 0x24, 0x6a, 0x3b, 0x59, 0x2a,
- 0x88, 0x17, 0xc7, 0xee, 0x78, 0xfb, 0x78, 0x06, 0x16, 0x6a, 0xad, 0x0b, 0xa5, 0x9c, 0xab, 0x5c,
- 0x78, 0x3a, 0xc5, 0x7d, 0x9e, 0x1e, 0xb7, 0x82, 0x57, 0x6f, 0xe5, 0xd0, 0x43, 0x2d, 0x71, 0x20,
- 0xd7, 0x16, 0x54, 0x59, 0x75, 0x15, 0x8f, 0x47, 0x90, 0x31, 0xb9, 0x9a, 0x0d, 0x85, 0x7d, 0x01,
- 0x58, 0x67, 0x40, 0x07, 0xec, 0x72, 0xaf, 0x41, 0x01, 0x3e, 0x61, 0x0c, 0xe4, 0x12, 0x1c, 0x30,
- 0xd3, 0x37, 0xf7, 0xdf, 0xf4, 0x2e, 0xa0, 0x62, 0xd5, 0xba, 0x1c, 0xc9, 0x70, 0x31, 0x2e, 0x10,
- 0xa9, 0xf0, 0x31, 0x53, 0x69, 0xea, 0x2b, 0xbc, 0xbe, 0x5d, 0xbb, 0xa7, 0xdf, 0x62, 0xf0, 0x28,
- 0x18, 0x66, 0xa6, 0xd3, 0x74, 0x86, 0x11, 0x4c, 0x6e, 0x57, 0xdd, 0x0c, 0x86, 0xc2, 0xa5, 0x3b,
- 0x0f, 0x92, 0x19, 0x24, 0x90, 0x82, 0xdd, 0xc5, 0x48, 0xdb, 0x72, 0xb8, 0xda, 0x38, 0x95, 0xa8,
- 0xa0, 0x80, 0xe2, 0x4e, 0x93, 0x44, 0xb8, 0x4f, 0xe9, 0xc1, 0xd9, 0x2c, 0x90, 0x4e, 0xed, 0x6f,
- 0x9d, 0x3e, 0x7b, 0x66, 0x53, 0xa9, 0xd3, 0xc5, 0x18, 0x95, 0x05, 0xbe, 0xfe, 0xbd, 0xee, 0xb6,
- 0x2a, 0x1e, 0x29, 0x23, 0xff, 0x44, 0x6b, 0x02, 0x3c, 0xbe, 0xac, 0x12, 0x1f, 0xed, 0x0d, 0x3b,
- 0x3b, 0xc9, 0x3e, 0x84, 0xa7, 0x3c, 0x00, 0x0d, 0x15, 0x07, 0x83, 0xa1, 0x7f, 0x4f, 0xc1, 0x13,
- 0x51, 0x67, 0x1e, 0x7c, 0xf8, 0xe2, 0xac, 0xb4, 0xd1, 0x49, 0x78, 0xd4, 0x01, 0xb1, 0x55, 0xba,
- 0xa5, 0xa4, 0xf8, 0x85, 0x95, 0x7f, 0xf6, 0x4d, 0xda, 0xd3, 0x44, 0x46, 0xfd, 0xac, 0xa5, 0xc1,
- 0xd5, 0xfc, 0x87, 0xea, 0x9e, 0xdd, 0xbe, 0xf5, 0x52, 0x58, 0xed, 0xfd, 0xde, 0x80, 0x3a, 0x07,
- 0x77, 0x05, 0xcd, 0xd8, 0x29, 0x4e, 0x28, 0x22, 0x66, 0x39, 0x17, 0xcd, 0x56, 0x6b, 0x52, 0x6c,
- 0x1c, 0xe8, 0x22, 0x74, 0xa2, 0xcf, 0xc8, 0x72, 0x11, 0x36, 0x4f, 0xe1, 0xf6, 0x52, 0x31, 0xfb,
- 0x8b, 0x06, 0x11, 0xf7, 0x89, 0xb9, 0x96, 0x9b, 0x1c, 0x99, 0x7a, 0xd4, 0xa0, 0x8f, 0x2c, 0x26,
- 0x62, 0xe7, 0x4e, 0xaf, 0x0e, 0xbd, 0xc3, 0xce, 0x2e, 0x67, 0xd1, 0x86, 0x3b, 0xe9, 0xc4, 0x39,
- 0x75, 0x5e, 0xbd, 0x0a, 0x06, 0xac, 0xd9, 0x0d, 0xe4, 0xb0, 0x86, 0xaa, 0x1f, 0xb7, 0x9a, 0x26,
- 0x7a, 0xac, 0x5b, 0x38, 0x30, 0x6e, 0x4e, 0xb9, 0xe3, 0xa6, 0x23, 0xe1, 0xa4, 0x73, 0x1d, 0x50,
- 0xcc, 0x1c, 0xef, 0xe6, 0x73, 0xf7, 0x8b, 0xeb, 0xbe, 0x69, 0x81, 0xeb, 0x74, 0x87, 0x68, 0x4e,
- 0x4a, 0x2b, 0xfc, 0xa0, 0x0b, 0x30, 0x6d, 0x5e, 0x81, 0xe2, 0xd9, 0xa6, 0xba, 0x1e, 0x5b, 0x09,
- 0x2e, 0xe3, 0x67, 0x0d, 0x75, 0x65, 0x76, 0x5c, 0x61, 0xf4, 0x19, 0xd8, 0x6d, 0xfa, 0xfe, 0xa6,
- 0x11, 0x1a, 0xaf, 0xca, 0x1c, 0xff, 0x74, 0xe7, 0x85, 0xb3, 0x3d, 0xb9, 0x67, 0x7c, 0xf7, 0x16,
- 0xf8, 0xf6, 0x6b, 0xac, 0xb8, 0x85, 0x7c, 0x1e, 0x02, 0x53, 0x67, 0xac, 0x29, 0xd2, 0x72, 0x97,
- 0x91, 0x43, 0x81, 0xc2, 0xde, 0xc6, 0x41, 0x3c, 0x96, 0xd6, 0xdf, 0x19, 0x3e, 0x18, 0x2e, 0xbf,
- 0xcb, 0xb4, 0xec, 0x20, 0xd8, 0xa7, 0x48, 0x46, 0x62, 0x9d, 0x44, 0x23, 0x0e, 0x72, 0x3b, 0xec,
- 0x4e, 0x7d, 0x2e, 0x92, 0x71, 0xd7, 0xa8, 0x4b, 0x3c, 0x6c, 0x39, 0x72, 0xb0, 0xc2, 0x97, 0x67,
- 0xde, 0x80, 0x30, 0x0a, 0x36, 0x49, 0xe2, 0x31, 0xa3, 0x70, 0x7d, 0xe3, 0x28, 0xf7, 0xa5, 0xe6,
- 0xb0, 0xe4, 0xc6, 0x65, 0x43, 0xd3, 0x12, 0x77, 0xa4, 0x1a, 0x92, 0xa6, 0x1c, 0xd7, 0x7d, 0x6d,
- 0xc9, 0x49, 0xdb, 0x55, 0x45, 0xf4, 0xae, 0x67, 0x69, 0xc1, 0xf0, 0xe4, 0xa4, 0x3e, 0x18, 0xae,
- 0x08, 0x18, 0xc0, 0xf8, 0xa6, 0x87, 0xa8, 0x71, 0xa9, 0xd2, 0x12, 0x3c, 0xa3, 0xd8, 0x9f, 0xe2,
- 0x28, 0x30, 0x46, 0xb7, 0x92, 0x33, 0x2d, 0x4b, 0x1a, 0xc7, 0x3e, 0x1f, 0x19, 0x66, 0xd8, 0xd5,
- 0x03, 0x34, 0x39, 0x6b, 0xe5, 0x0e, 0xea, 0x0d, 0x90, 0xba, 0x26, 0xbd, 0x53, 0xc3, 0x44, 0xe7,
- 0x6c, 0x51, 0x38, 0xc4, 0x73, 0x85, 0xa6, 0x10, 0xa8, 0x36, 0xbe, 0x75, 0x26, 0xe2, 0xfd, 0xd0,
- 0x59, 0x8d, 0xf7, 0xb5, 0x81, 0xcd, 0x2b, 0x25, 0x16, 0x7c, 0x0b, 0x5f, 0x24, 0x07, 0x9b, 0x77,
- 0x45, 0x63, 0x5a, 0x15, 0x62, 0xaa, 0xa1, 0x44, 0x66, 0x72, 0xda, 0x35, 0x94, 0x6a, 0xe6, 0xa8,
- 0x69, 0xcd, 0xe0, 0x64, 0x6b, 0xde, 0xbb, 0xde, 0xae, 0x82, 0x89, 0x36, 0x16, 0xf0, 0x13, 0x41,
- 0xa7, 0x42, 0x2e, 0xaf, 0x8a, 0xed, 0x22, 0xd2, 0xc6, 0x91, 0x5f, 0x2a, 0x25, 0x06, 0x52, 0x03,
- 0xc5, 0xcb, 0x78, 0xe4, 0x7a, 0xef, 0x1c, 0xb3, 0x3f, 0xbc, 0xfa, 0x29, 0xfc, 0xc6, 0x73, 0x68,
- 0x9e, 0x80, 0x0c, 0xc2, 0xfa, 0x11, 0xdc, 0xde, 0xa0, 0x8f, 0x5b, 0x53, 0x80, 0xcd, 0x4e, 0x4c,
- 0xd2, 0x15, 0x40, 0xa4, 0x18, 0x4e, 0x70, 0xf7, 0x0c, 0xc5, 0xe8, 0xc4, 0xbd, 0x6f, 0xc4, 0x46,
- 0x12, 0x45, 0xfe, 0xa8, 0x11, 0xd0, 0xd1, 0x4c, 0x1a, 0x99, 0x99, 0xf1, 0x3c, 0xdc, 0xb5, 0x8a,
- 0xef, 0xa6, 0x22, 0xd4, 0x9e, 0x75, 0x3f, 0x37, 0x73, 0x3c, 0x62, 0xb3, 0xc3, 0xa5, 0x87, 0xdd,
- 0xc2, 0x96, 0x8b, 0x02, 0xf1, 0x10, 0xf8, 0xed, 0x8b, 0x56, 0x29, 0x5b, 0xdc, 0x67, 0xbf, 0x39,
- 0x8d, 0x01, 0xc8, 0x8a, 0x89, 0x2e, 0xf2, 0x05, 0x43, 0xf6, 0x2b, 0x9b, 0x4e, 0xca, 0xd4, 0xca,
- 0x4c, 0xf8, 0xc1, 0xf7, 0xc2, 0x4a, 0x55, 0x87, 0xc0, 0xb4, 0xd4, 0xc6, 0xdf, 0xc5, 0xaf, 0xc0,
- 0x23, 0x90, 0x6f, 0x93, 0x25, 0x17, 0x52, 0xa2, 0xed, 0x90, 0x14, 0x8f, 0xdc, 0x74, 0xb1, 0x71,
- 0x3c, 0xaa, 0xfb, 0x60, 0x76, 0xd6, 0xc8, 0x17, 0x15, 0x5e, 0xae, 0xa3, 0xb7, 0xdd, 0x2e, 0x10,
- 0xe9, 0x3d, 0x33, 0x00, 0x7a, 0xd4, 0x8f, 0xda, 0x3a, 0x03, 0xeb, 0x2e, 0x01, 0x7c, 0xf8, 0xed,
- 0x50, 0x01, 0x65, 0x29, 0x94, 0x77, 0xf8, 0x97, 0x20, 0xca, 0xa2, 0xa9, 0x6a, 0xee, 0xbf, 0x4e,
- 0x74, 0x52, 0x5f, 0x5f, 0xc4, 0xc1, 0xb7, 0x43, 0x4c, 0x06, 0xd0, 0x2b, 0x77, 0x9a, 0x82, 0x01,
- 0x3b, 0x5a, 0x15, 0x6a, 0x40, 0x99, 0x50, 0xdb, 0x0c, 0x95, 0xa4, 0x97, 0xbf, 0x8a, 0x63, 0xd2,
- 0xd8, 0x06, 0xf1, 0x2c, 0xe0, 0x5a, 0xe2, 0x0e, 0x9a, 0xca, 0x1a, 0x9f, 0x71, 0xe1, 0x41, 0x86,
- 0x92, 0xd2, 0x0d, 0x6c, 0x40, 0xa9, 0x0b, 0xd9, 0x33, 0x0d, 0xaf, 0x6c, 0xdb, 0x69, 0xeb, 0x26,
- 0x8e, 0x29, 0xb3, 0xd0, 0x9f, 0x9c, 0xce, 0xb8, 0x95, 0x2f, 0xd0, 0x2b, 0x56, 0x94, 0xf1, 0xe7,
- 0x46, 0xff, 0x88, 0xd1, 0x93, 0x65, 0x79, 0x92, 0x57, 0x62, 0x12, 0x1d, 0x82, 0x4f, 0x80, 0xef,
- 0x98, 0x45, 0x09, 0xea, 0x7d, 0x04, 0xf1, 0xce, 0x03, 0xe3, 0x6a, 0x22, 0xdd, 0x3b, 0x80, 0x95,
- 0x87, 0x7e, 0x8b, 0xfc, 0xd8, 0xf6, 0x32, 0xeb, 0x45, 0xd8, 0x7d, 0xeb, 0x81, 0x11, 0xcb, 0x5d,
- 0x10, 0x35, 0x6b, 0xbe, 0x9c, 0x01, 0x7c, 0xfb, 0xb5, 0xc6, 0xb5, 0x9c, 0x87, 0x1b, 0xd9, 0xe0,
- 0xe4, 0x45, 0x67, 0xca, 0xd8, 0xf9, 0x18, 0x05, 0xea, 0x48, 0x8b, 0x45, 0x19, 0x03, 0xda, 0x5b,
- 0x68, 0x45, 0x23, 0xaf, 0xf7, 0xce, 0xae, 0x4e, 0xd8, 0xf8, 0xd3, 0x7c, 0xde, 0x41, 0x61, 0x01,
- 0xbe, 0xcf, 0x2b, 0x11, 0x6c, 0x40, 0xb3, 0x50, 0x0e, 0x77, 0xf5, 0xd8, 0x59, 0xac, 0x18, 0x95,
- 0xb5, 0x92, 0xa1, 0xce, 0x5c, 0x4b, 0xe5, 0xd2, 0x95, 0xef, 0xf4, 0x31, 0x6d, 0x45, 0x50, 0xe1,
- 0xbf, 0x43, 0x24, 0xbb, 0xe5, 0xb7, 0x1e, 0x92, 0x25, 0x7b, 0x39, 0x1d, 0x34, 0xd1, 0xdd, 0xf5,
- 0x25, 0xb8, 0x4b, 0x4e, 0x1e, 0xe5, 0xce, 0xb1, 0xb2, 0x5b, 0x8e, 0x7e, 0xbf, 0xad, 0xae, 0x61,
- 0xf9, 0xdc, 0xc1, 0xc7, 0x92, 0x86, 0xea, 0x2d, 0x2a, 0x1c, 0x07, 0xad, 0x94, 0xf2, 0x15, 0x6d,
- 0x61, 0xb0, 0xf1, 0xe8, 0x23, 0xdf, 0x0b, 0x79, 0x7b, 0x43, 0xda, 0x88, 0x74, 0xd4, 0xaf, 0x37,
- 0x16, 0xdb, 0x81, 0x1b, 0xf8, 0x0f, 0x3b, 0x7b, 0x2a, 0x0b, 0xbe, 0x7c, 0xd0, 0x92, 0x8c, 0x43,
- 0xc8, 0x95, 0xf8, 0x7f, 0xc0, 0x2a, 0x6d, 0xf5, 0xbc, 0xaf, 0x2e, 0x7f, 0xdb, 0xa2, 0xfe, 0x37,
- 0xc6, 0xe1, 0x6b, 0x8a, 0x38, 0xea, 0x60, 0x94, 0x2f, 0xb7, 0xdd, 0x14, 0x5a, 0x9a, 0xf6, 0x21,
- 0xda, 0x30, 0xbe, 0x1f, 0xe4, 0xa2, 0xc1, 0x3b, 0xfa, 0x5d, 0x98, 0xf3, 0x56, 0x7f, 0xe8, 0xb2,
- 0x33, 0x25, 0xce, 0xff, 0x64, 0xeb, 0xd8, 0x4c, 0xb9, 0x0c, 0x5d, 0xae, 0xc8, 0x43, 0x8e, 0x4c,
- 0x4c, 0x09, 0x7a, 0x42, 0x06, 0xe0, 0x04, 0xcc, 0x09, 0xe5, 0x68, 0x1a, 0x55, 0x5c, 0xfc, 0x15,
- 0x86, 0xe3, 0xe7, 0xf2, 0xb6, 0x15, 0x31, 0x56, 0xaf, 0xa7, 0x13, 0x35, 0x90, 0xe7, 0xec, 0xfa,
- 0x82, 0xea, 0x54, 0x22, 0xfc, 0x08, 0x1a, 0xb0, 0x55, 0xf3, 0x75, 0x08, 0x94, 0x33, 0x08, 0x6f,
- 0xfd, 0x1d, 0x69, 0x8c, 0x63, 0xb3, 0x4a, 0xd5, 0x50, 0xe9, 0xca, 0xeb, 0x42, 0xf1, 0x7c, 0x39,
- 0x1c, 0xcd, 0x95, 0x0a, 0xd3, 0xa0, 0xcd, 0xed, 0x43, 0x35, 0x05, 0x3e, 0x35, 0x21, 0x01, 0x6d,
- 0x23, 0x11, 0xd7, 0x49, 0xdb, 0xf2, 0xb7, 0xbe, 0x33, 0x38, 0x85, 0x74, 0xa6, 0x2c, 0x0b, 0x17,
- 0x4e, 0xd4, 0x12, 0x0d, 0xcb, 0xd7, 0x91, 0xad, 0x4f, 0xab, 0x53, 0x43, 0x50, 0x10, 0xf7, 0xc3,
- 0x02, 0x4e, 0xe8, 0x72, 0xef, 0x00, 0xd2, 0x9a, 0xd7, 0x9e, 0x3f, 0x2b, 0x33, 0x6a, 0x71, 0xc4,
- 0x6b, 0x21, 0x10, 0x1a, 0x0b, 0x8e, 0xe8, 0xcb, 0x34, 0x07, 0xa9, 0xf4, 0xb2, 0x55, 0x0b, 0x44,
- 0x35, 0x08, 0xbd, 0x21, 0xe6, 0x7a, 0x6f, 0xd2, 0xda, 0xc0, 0x09, 0x04, 0xda, 0xeb, 0x99, 0x35,
- 0x0c, 0xd4, 0x5f, 0xca, 0x32, 0x4f, 0xad, 0x5c, 0xe3, 0x1c, 0x4b, 0x10, 0x48, 0xf7, 0xa7, 0x1d,
- 0x30, 0xa2, 0x5b, 0xba, 0x2c, 0x36, 0x77, 0x99, 0x15, 0x18, 0xe2, 0xe0, 0x14, 0x30, 0x77, 0xb1,
- 0xed, 0xee, 0x1f, 0x28, 0x91, 0xf8, 0x55, 0xbe, 0xd7, 0xe4, 0x76, 0x04, 0x5f, 0x6b, 0xbb, 0xbf,
- 0xfe, 0xfe, 0xec, 0x70, 0x54, 0xaf, 0xf2, 0x8f, 0x69, 0x93, 0x1a, 0x5d, 0x0e, 0xf0, 0xd6, 0x30,
- 0x71, 0xa6, 0xdd, 0x20, 0x3b, 0x9f, 0xa7, 0xac, 0xe7, 0x83, 0xe9, 0x7b, 0x41, 0x9f, 0x82, 0xd9,
- 0xe2, 0x50, 0x65, 0xe1, 0x2a, 0x1c, 0xee, 0x8d, 0x84, 0xc9, 0xe8, 0x08, 0x0e, 0x0a, 0x33, 0x01,
- 0xd3, 0x76, 0x54, 0x99, 0x16, 0x2d, 0x72, 0xfd, 0x69, 0xf4, 0xe1, 0xd3, 0xd6, 0xf3, 0xa4, 0x8f,
- 0xc7, 0xb7, 0x2b, 0x59, 0x23, 0xcb, 0xf3, 0x1a, 0xe1, 0xad, 0x8b, 0x48, 0xc0, 0x39, 0x38, 0xae,
- 0x84, 0xc6, 0x75, 0xa6, 0x04, 0x2b, 0x29, 0xc1, 0xc3, 0x2a, 0x4f, 0x05, 0x1f, 0xb0, 0xa7, 0x0c,
- 0x6a, 0xe2, 0xec, 0x44, 0x44, 0x35, 0x39, 0xbc, 0x16, 0x82, 0x52, 0xcc, 0x92, 0xe9, 0x4b, 0x16,
- 0x23, 0x6a, 0xcc, 0x1d, 0xfe, 0xd1, 0xc4, 0xd7, 0xe6, 0x26, 0xd1, 0xa8, 0x4d, 0x3c, 0x8f, 0x9d,
- 0x6c, 0xab, 0xb3, 0x79, 0x09, 0xd6, 0xd4, 0x31, 0xc4, 0x1c, 0xd7, 0x4a, 0xda, 0x46, 0x43, 0xa4,
- 0x16, 0x21, 0xff, 0xc9, 0x43, 0xe5, 0x27, 0x4f, 0x32, 0x05, 0x0b, 0x03, 0x76, 0x36, 0x7a, 0xf6,
- 0x8a, 0x90, 0x20, 0xfa, 0xaa, 0x69, 0x2d, 0x0a, 0x49, 0x87, 0xfc, 0xf1, 0xb2, 0x2c, 0xf2, 0xba,
- 0xeb, 0xaa, 0x61, 0xed, 0x35, 0x18, 0xa4, 0x41, 0x4a, 0xf7, 0x89, 0x45, 0xc2, 0xdf, 0x80, 0x44,
- 0x8a, 0xcb, 0x49, 0xef, 0x61, 0x5e, 0xa6, 0x22, 0x2c, 0x55, 0x77, 0x0e, 0xe0, 0xfc, 0x35, 0xc3,
- 0x56, 0xdb, 0xe0, 0x19, 0xe2, 0xe1, 0xb0, 0xe3, 0x39, 0xa1, 0xc4, 0xcc, 0xa4, 0xdf, 0xca, 0xd2,
- 0x75, 0x9d, 0x99, 0x41, 0xc3, 0x98, 0xfd, 0xd8, 0x19, 0x20, 0x51, 0x37, 0xec, 0x8d, 0x74, 0x13,
- 0x0f, 0x42, 0x11, 0x75, 0x68, 0x58, 0x65, 0xcd, 0xbf, 0xfc, 0x16, 0xea, 0x37, 0xd6, 0x56, 0x59,
- 0xc3, 0x69, 0x4d, 0x49, 0x4d, 0x7c, 0x98, 0xaf, 0x85, 0x93, 0x8e, 0x2a, 0xea, 0x86, 0x19, 0x0c,
- 0x64, 0x2d, 0xc5, 0x79, 0xd8, 0xbd, 0xdc, 0x91, 0x53, 0x3c, 0x48, 0x41, 0xad, 0xd8, 0xdd, 0x09,
- 0x2e, 0xfd, 0x32, 0x71, 0xe3, 0xd7, 0x81, 0x26, 0x34, 0xeb, 0xc8, 0x5c, 0x68, 0x67, 0xd4, 0x5e,
- 0x1f, 0x47, 0xbc, 0xd5, 0x96, 0x72, 0x6a, 0xfb, 0x23, 0x3a, 0xbd, 0xdc, 0x32, 0x09, 0x61, 0x0a,
- 0xb1, 0xbf, 0x02, 0x51, 0x1b, 0x24, 0xe7, 0x4d, 0x27, 0xd3, 0x38, 0x1e, 0x7a, 0x76, 0x2c, 0xbe,
- 0xdc, 0x11, 0x8f, 0x6a, 0x82, 0x6e, 0xf5, 0x55, 0xf7, 0xf7, 0x8e, 0x2c, 0x5d, 0xa1, 0x52, 0xe5,
- 0xb0, 0x3e, 0xaa, 0x39, 0xa1, 0x04, 0xf1, 0x09, 0xec, 0xa6, 0x34, 0x1c, 0xaa, 0xaa, 0x3a, 0xdf,
- 0xad, 0x65, 0xce, 0x2f, 0x19, 0x30, 0x34, 0x38, 0x44, 0x7c, 0xd6, 0x4d, 0x46, 0x8a, 0xd6, 0xcd,
- 0xd0, 0xcd, 0x36, 0xb2, 0x28, 0xa2, 0x44, 0xe9, 0xda, 0x1c, 0xa5, 0xd5, 0xa6, 0x90, 0x48, 0xf6,
- 0xf4, 0xad, 0x4b, 0x02, 0x89, 0x81, 0xcc, 0x90, 0x57, 0x0c, 0x0c, 0xf5, 0x28, 0xf5, 0xfc, 0xca,
- 0x66, 0x5b, 0x61, 0x2c, 0x7c, 0x3e, 0x3d, 0x2e, 0x35, 0x9f, 0xc2, 0xb1, 0x72, 0x77, 0x7b, 0x3b,
- 0x00, 0x15, 0x51, 0x59, 0xd5, 0xc8, 0x21, 0x5c, 0x36, 0xf0, 0xa2, 0x9d, 0xdb, 0xd9, 0x8b, 0xef,
- 0x95, 0xbd, 0x9b, 0x0e, 0x4a, 0xb7, 0xfd, 0x27, 0xe1, 0x36, 0xab, 0x02, 0x07, 0x5e, 0xba, 0x55,
- 0x26, 0x02, 0xc3, 0xd6, 0xde, 0xfd, 0x15, 0x5f, 0xef, 0x10, 0x5a, 0x93, 0x3e, 0x68, 0x5f, 0x19,
- 0xbd, 0x8e, 0x6a, 0x4b, 0x7f, 0x82, 0x93, 0x62, 0x42, 0x8d, 0x0e, 0x7c, 0x42, 0x98, 0x2d, 0x48,
- 0x8e, 0x02, 0x40, 0xa7, 0xa1, 0xc0, 0x0b, 0x7a, 0xe0, 0x79, 0x65, 0x8c, 0x02, 0xa7, 0x3e, 0x4e,
- 0x1d, 0xca, 0x14, 0x8d, 0x1b, 0xde, 0x0a, 0x80, 0xc4, 0x0c, 0xef, 0xeb, 0x05, 0xa0, 0x18, 0x05,
- 0x83, 0xa5, 0x3d, 0xd8, 0x19, 0xd3, 0x36, 0xa3, 0x8d, 0x96, 0xbe, 0x2a, 0xa4, 0x6e, 0x7a, 0x78,
- 0xa1, 0xb9, 0x1c, 0x44, 0xaf, 0x62, 0x7d, 0x1b, 0x32, 0xd0, 0x81, 0x06, 0x9c, 0x98, 0x3c, 0x4f,
- 0x87, 0x34, 0x05, 0x11, 0xb4, 0x86, 0x6e, 0x73, 0x63, 0xb1, 0xe0, 0x8c, 0x2a, 0x4d, 0xb0, 0xec,
- 0x7b, 0xba, 0x19, 0x0b, 0x61, 0x1d, 0xa4, 0xa6, 0xd8, 0x53, 0xcf, 0x0b, 0x97, 0xf4, 0x55, 0xca,
- 0x02, 0xbf, 0x8a, 0x3d, 0xb7, 0x4d, 0x32, 0x61, 0xbc, 0xee, 0x2b, 0x86, 0x67, 0xc1, 0x15, 0x10,
- 0xcf, 0xbd, 0x62, 0x69, 0xca, 0x9f, 0xe5, 0xcb, 0x18, 0xd4, 0x2d, 0xd5, 0xd9, 0x03, 0x44, 0x1f,
- 0xa3, 0xdb, 0x71, 0x2c, 0x74, 0x14, 0x06, 0x52, 0x9e, 0xf8, 0x4b, 0x35, 0x78, 0xe4, 0x27, 0xf2,
- 0x60, 0x22, 0x31, 0x80, 0x3b, 0xd7, 0x95, 0xa2, 0xc4, 0x89, 0xfb, 0x0b, 0x23, 0xf0, 0x4c, 0x48,
- 0x5e, 0x19, 0x92, 0x35, 0x3c, 0x58, 0x47, 0x55, 0x35, 0x31, 0x31, 0x2f, 0x96, 0x6f, 0xa8, 0xe9,
- 0x66, 0x78, 0x8b, 0x0f, 0x7e, 0x7e, 0xcd, 0x75, 0x85, 0x34, 0x67, 0xb1, 0xcf, 0x47, 0x3d, 0x39,
- 0x2a, 0x3f, 0x40, 0x6c, 0x40, 0x03, 0xa8, 0xd9, 0x73, 0xc0, 0xc9, 0xa9, 0x06, 0xb0, 0x57, 0x98,
- 0xd7, 0xab, 0xaf, 0x4c, 0xa0, 0x28, 0x4a, 0x09, 0xe3, 0x21, 0xd6, 0xa3, 0x7b, 0x9e, 0xae, 0x69,
- 0x72, 0x42, 0xd8, 0xac, 0xe7, 0x20, 0x57, 0x82, 0x42, 0xd0, 0xb8, 0x05, 0x7d, 0xb3, 0xb1, 0x57,
- 0x0a, 0x60, 0xa2, 0xa0, 0x42, 0x2e, 0x18, 0x84, 0x29, 0xc7, 0xdc, 0xfb, 0x34, 0x7f, 0x41, 0xc8,
- 0x29, 0x31, 0xe5, 0x00, 0x1c, 0x11, 0x23, 0x30, 0x84, 0xd4, 0x8e, 0xf4, 0x24, 0xfb, 0x51, 0xb6,
- 0x33, 0xac, 0x37, 0x4d, 0x42, 0xa5, 0x18, 0x05, 0x79, 0x61, 0x19, 0xeb, 0xc0, 0x1f, 0x62, 0x79,
- 0x7e, 0x1c, 0xf0, 0xa2, 0x72, 0x5a, 0xaf, 0x90, 0xe5, 0x14, 0x90, 0xb3, 0xe7, 0x6a, 0x29, 0xde,
- 0xe3, 0x0a, 0xc3, 0x8e, 0x3d, 0x5d, 0x7a, 0xab, 0x5e, 0x04, 0xa1, 0xda, 0x73, 0xde, 0x24, 0x04,
- 0xe0, 0x92, 0xe5, 0x40, 0x46, 0x6e, 0x0c, 0xec, 0xd0, 0x1d, 0xf9, 0x45, 0x12, 0xb5, 0xf3, 0x23,
- 0x0c, 0xd7, 0x3a, 0x5c, 0xbb, 0x72, 0x57, 0x32, 0x7c, 0x3b, 0x94, 0x67, 0x80, 0x2e, 0x5b, 0xbc,
- 0x61, 0x15, 0x6f, 0xa0, 0x5b, 0xcb, 0xef, 0x91, 0x46, 0xcf, 0xd5, 0x35, 0xf0, 0x2e, 0x9e, 0xc6,
- 0x9b, 0x93, 0x6d, 0x52, 0xf3, 0xa1, 0xf6, 0x70, 0x04, 0xd7, 0x9d, 0x81, 0xad, 0xb6, 0x9c, 0x67,
- 0x26, 0x28, 0x4e, 0x79, 0x12, 0xac, 0x72, 0x2f, 0x38, 0xe8, 0xe2, 0x9e, 0xcb, 0xca, 0x47, 0xc5,
- 0x0f, 0xc5, 0x5e, 0x7e, 0x67, 0xd9, 0x0a, 0xa8, 0xda, 0x3b, 0xaf, 0xed, 0x2d, 0x77, 0xf5, 0x48,
- 0xc6, 0x32, 0x96, 0x2a, 0xf2, 0x71, 0x65, 0x90, 0x82, 0xae, 0xe6, 0xf3, 0x2b, 0x72, 0x96, 0x88,
- 0xe8, 0x14, 0x5b, 0x42, 0x92, 0xcb, 0xf8, 0x86, 0x22, 0xab, 0x38, 0x1c, 0x13, 0x8b, 0xf8, 0xe3,
- 0xd2, 0xe0, 0xe7, 0x5a, 0xea, 0xb0, 0x48, 0xda, 0x2e, 0xe5, 0x2e, 0x3f, 0x71, 0xe8, 0x7d, 0x5a,
- 0x1d, 0x7d, 0xea, 0x98, 0x77, 0xe1, 0x38, 0xa7, 0x3b, 0xa4, 0xb4, 0xb1, 0xa7, 0x19, 0xa0, 0x08,
- 0x5a, 0x9a, 0xb9, 0x6d, 0x60, 0xb0, 0xf2, 0x8c, 0xb8, 0x5e, 0x69, 0x6a, 0x8d, 0xdd, 0xcb, 0x5f,
- 0xe2, 0x6b, 0x28, 0x13, 0xd3, 0xcb, 0xb2, 0x64, 0xa0, 0x98, 0x38, 0x91, 0x4c, 0x87, 0x52, 0xad,
- 0x35, 0x25, 0x12, 0x4f, 0x85, 0xb1, 0x10, 0x4f, 0x2f, 0x26, 0xfc, 0x20, 0xc4, 0x6f, 0xd2, 0xf0,
- 0x19, 0x54, 0xb4, 0xa0, 0xbc, 0xb3, 0x8d, 0xaa, 0xbf, 0xb4, 0xec, 0x1e, 0x53, 0x03, 0x1b, 0xcb,
- 0xd0, 0xa0, 0xb7, 0xbd, 0xf7, 0x79, 0x07, 0xc2, 0x0c, 0xde, 0x77, 0x78, 0xa3, 0x3a, 0x90, 0x72,
- 0x15, 0x74, 0x8f, 0xeb, 0x3e, 0x75, 0xa9, 0x4d, 0x09, 0x1b, 0xb7, 0xd0, 0xcf, 0x3e, 0x2d, 0x41,
- 0x74, 0x66, 0x6f, 0xb2, 0x48, 0x9f, 0xf3, 0xe7, 0x32, 0x2d, 0x60, 0xde, 0x84, 0x35, 0xd3, 0xbf,
- 0xd6, 0xd3, 0x03, 0x7b, 0xbc, 0xa0, 0x6d, 0x0b, 0xf9, 0xd9, 0x20, 0x06, 0xad, 0xac, 0x8a, 0x8d,
- 0xaa, 0x10, 0xdb, 0xe9, 0x12, 0x4a, 0xc4, 0xc0, 0xa4, 0xee, 0x69, 0x83, 0xd6, 0xf8, 0x10, 0x1d,
- 0xf6, 0x2f, 0xc1, 0xd2, 0x50, 0x8a, 0x18, 0xc9, 0xca, 0x76, 0x98, 0x98, 0x92, 0xbe, 0xb2, 0xf2,
- 0x44, 0x6d, 0x6e, 0xf1, 0xf6, 0xe0, 0x1b, 0x44, 0x7f, 0xe9, 0x7e, 0x2b, 0x10, 0x96, 0xb6, 0x2b,
- 0xd5, 0x55, 0xd4, 0x68, 0x3a, 0x7b, 0xb4, 0x94, 0xda, 0xbe, 0xec, 0xb0, 0xbd, 0x5a, 0xab, 0x15,
- 0xcf, 0x7d, 0x3b, 0x8c, 0x15, 0x89, 0xb2, 0x0c, 0x0c, 0xa7, 0x3b, 0xba, 0x32, 0x47, 0x25, 0x69,
- 0x55, 0xbb, 0xf7, 0x59, 0x2a, 0xfb, 0x77, 0x80, 0xf8, 0x16, 0xe4, 0xd6, 0xa7, 0x3e, 0x61, 0xc7,
- 0xce, 0xd2, 0x9c, 0x76, 0x85, 0x4f, 0x41, 0x66, 0x4b, 0x21, 0xf1, 0x69, 0x41, 0x4a, 0x79, 0x3a,
- 0x84, 0x96, 0x3d, 0x92, 0xa2, 0x1b, 0x08, 0x26, 0x29, 0x63, 0x42, 0x98, 0x1a, 0xdc, 0xa7, 0x84,
- 0x74, 0xc9, 0x65, 0xf2, 0x2f, 0x74, 0xab, 0xa6, 0xfc, 0x86, 0xcd, 0x61, 0xba, 0xcd, 0x1a, 0x4e,
- 0xdf, 0xfb, 0x79, 0x2c, 0x5c, 0x9e, 0x40, 0x36, 0x07, 0x5f, 0xc6, 0x08, 0x32, 0x36, 0x7a, 0x82,
- 0xa9, 0x42, 0x8b, 0x8b, 0x9e, 0xe2, 0xfc, 0xaf, 0x59, 0x53, 0xeb, 0x73, 0xbe, 0xc2, 0x9b, 0xc2,
- 0xa8, 0x36, 0x79, 0xcb, 0xd7, 0x2d, 0x95, 0xcd, 0xf3, 0x32, 0xa1, 0xde, 0x37, 0x2d, 0x4b, 0x31,
- 0x6f, 0x6b, 0x72, 0x23, 0x92, 0xe9, 0x8c, 0x7b, 0xc5, 0x0b, 0x66, 0x43, 0xaf, 0xa4, 0x4b, 0xc0,
- 0x58, 0xe4, 0xc4, 0x3d, 0x70, 0x4b, 0x44, 0x39, 0xc3, 0xcd, 0x63, 0xbb, 0x9d, 0xe6, 0xf9, 0xfb,
- 0x31, 0x38, 0x18, 0x94, 0xb0, 0xaa, 0x5a, 0x76, 0xf1, 0xd2, 0xe1, 0xac, 0x71, 0x31, 0xb7, 0x6e,
- 0xf8, 0x4e, 0x78, 0x50, 0xc1, 0x13, 0x6e, 0xac, 0x59, 0x66, 0x62, 0xbc, 0xf4, 0x30, 0x3f, 0xda,
- 0xb2, 0xff, 0x8d, 0x6c, 0x93, 0xb9, 0xd8, 0x54, 0x2c, 0x21, 0xd2, 0x34, 0xd2, 0x65, 0xd3, 0xd2,
- 0x30, 0x3f, 0x36, 0x20, 0x28, 0x65, 0xb9, 0xa4, 0x68, 0x4c, 0x1f, 0x4f, 0xe3, 0xca, 0xa5, 0xbe,
- 0x0f, 0x28, 0x9a, 0xf8, 0xf8, 0xe3, 0xdf, 0xa6, 0xc9, 0x9d, 0x95, 0x09, 0x6f, 0xc6, 0x37, 0xf8,
- 0x20, 0xd2, 0x51, 0xf2, 0xc0, 0x6d, 0x33, 0x75, 0xd3, 0x00, 0xea, 0x3d, 0xf7, 0x1e, 0xc0, 0x5b,
- 0xf0, 0x17, 0xff, 0x14, 0x8c, 0xa8, 0xf0, 0xb5, 0xfe, 0xc9, 0x53, 0x08, 0xca, 0x48, 0xa4, 0x6c,
- 0xc7, 0x7e, 0x4a, 0x5c, 0x31, 0x01, 0xce, 0xa6, 0x68, 0x97, 0x9b, 0xc6, 0x1f, 0xe2, 0x20, 0x54,
- 0x3d, 0xde, 0xc8, 0x80, 0x86, 0xe9, 0xc5, 0x0a, 0x2c, 0xb6, 0x2e, 0xb3, 0xb6, 0x1d, 0xbf, 0x79,
- 0x12, 0x27, 0x69, 0x1f, 0xc2, 0x1f, 0xa3, 0xd5, 0x22, 0xab, 0x4f, 0x1c, 0x9f, 0x35, 0xc1, 0xe3,
- 0x0d, 0xd5, 0x5b, 0xd5, 0xa4, 0x72, 0x8c, 0x7c, 0x5c, 0x8b, 0xd0, 0x1c, 0xfc, 0x8f, 0x2e, 0x95,
- 0x59, 0x0f, 0x2e, 0xc5, 0xd7, 0x7b, 0x58, 0xbe, 0x27, 0x91, 0x2b, 0x09, 0x4a, 0x7c, 0x3b, 0x21,
- 0x19, 0x07, 0x32, 0xc5, 0x37, 0xc2, 0x69, 0x7f, 0x10, 0x53, 0xa7, 0xcf, 0x2e, 0x0b, 0x87, 0xb4,
- 0x39, 0x6e, 0x49, 0xb7, 0xfb, 0x1d, 0x29, 0xf1, 0x9e, 0x70, 0xdd, 0x61, 0x70, 0xe1, 0x63, 0x23,
- 0xcd, 0x7f, 0x7e, 0x33, 0xf0, 0x29, 0x5a, 0x5e, 0x19, 0xe4, 0xc7, 0xed, 0xf1, 0x80, 0x9e, 0xaa,
- 0xe9, 0xa8, 0xd8, 0x07, 0x4a, 0x03, 0xab, 0x13, 0x50, 0x72, 0x59, 0x26, 0x62, 0x0e, 0xff, 0xa4,
- 0xaf, 0x05, 0x73, 0x0e, 0xf6, 0xdc, 0x06, 0xa2, 0xb8, 0xd3, 0x64, 0x22, 0xa8, 0x58, 0x6b, 0x44,
- 0xa7, 0x9e, 0x14, 0xde, 0x79, 0x87, 0xed, 0x13, 0xee, 0xad, 0xbd, 0x87, 0xed, 0xe8, 0x82, 0xa7,
- 0x20, 0x8c, 0x81, 0xd4, 0x7b, 0x45, 0xe1, 0x19, 0xda, 0x17, 0x4a, 0xdb, 0xc6, 0xb3, 0xf7, 0x6b,
- 0xc9, 0x17, 0x53, 0x96, 0x58, 0x00, 0x21, 0x5a, 0x52, 0xdd, 0xf7, 0xb7, 0xf3, 0x64, 0x8b, 0xfd,
- 0x40, 0x70, 0x10, 0xd7, 0xd3, 0x7e, 0xa7, 0x6b, 0xb2, 0xb5, 0xbf, 0x02, 0x0a, 0x63, 0xb8, 0x6c,
- 0xa9, 0xb0, 0x6d, 0x84, 0x1e, 0x81, 0x1d, 0x69, 0xe5, 0x02, 0xd2, 0x81, 0x63, 0x28, 0x9e, 0x58,
- 0xfc, 0x20, 0xcc, 0xaa, 0xbc, 0x3e, 0x0b, 0x61, 0x24, 0xea, 0x41, 0x6c, 0xf5, 0x24, 0x64, 0x4e,
- 0xee, 0x3a, 0xaf, 0xb3, 0xec, 0xf3, 0xe2, 0x73, 0x66, 0x7f, 0x1d, 0x1e, 0xd3, 0x5d, 0xfc, 0x0c,
- 0x20, 0xb9, 0xca, 0xe8, 0x61, 0x8a, 0x82, 0xb7, 0xc3, 0x80, 0x3c, 0x5e, 0x09, 0x08, 0x88, 0x5a,
- 0x92, 0xdd, 0xfc, 0x42, 0xa0, 0xb1, 0x42, 0x6d, 0xbf, 0xd8, 0x06, 0x6b, 0x5a, 0xa3, 0x9a, 0x1b,
- 0xf7, 0x97, 0x35, 0xef, 0x31, 0xb0, 0x05, 0x95, 0x89, 0x5a, 0x37, 0xd2, 0x4c, 0x77, 0xe2, 0x51,
- 0xc9, 0x54, 0x6e, 0xab, 0x0d, 0x69, 0xa6, 0xa0, 0xa0, 0x20, 0xa7, 0xfc, 0xa9, 0x6c, 0x1b, 0x19,
- 0x97, 0x8d, 0xa6, 0xac, 0xed, 0x6f, 0x25, 0xbc, 0xac, 0x5d, 0x2c, 0x95, 0xc3, 0xaa, 0xca, 0x9b,
- 0x7d, 0x4b, 0x88, 0x72, 0x6a, 0x2f, 0xe8, 0x50, 0x70, 0x45, 0xf3, 0x09, 0xfe, 0x5e, 0xb8, 0xe5,
- 0xe8, 0x4b, 0xc8, 0xc1, 0xc8, 0x07, 0x5c, 0x94, 0xe2, 0xc6, 0x8e, 0xdd, 0x50, 0xa2, 0xee, 0x67,
- 0x85, 0xac, 0x0a, 0x91, 0x69, 0x9f, 0xc4, 0x02, 0x66, 0x59, 0xd8, 0x7c, 0x37, 0xb3, 0xab, 0x93,
- 0xc4, 0x83, 0xfc, 0xa0, 0x72, 0x0e, 0x3d, 0x16, 0x5a, 0x9e, 0xf8, 0xb6, 0x9b, 0xeb, 0x68, 0xa2,
- 0xa4, 0xd5, 0x93, 0x16, 0x4e, 0x69, 0xd5, 0xca, 0xa5, 0x5b, 0x33, 0xce, 0x91, 0x0f, 0x8a, 0xc3,
- 0x1c, 0x80, 0xbe, 0x66, 0x1d, 0xc9, 0xec, 0x17, 0x46, 0x51, 0x50, 0x92, 0x1c, 0x31, 0x7d, 0xfc,
- 0x72, 0x25, 0xb3, 0x38, 0xe6, 0x8a, 0x08, 0xc7, 0x1a, 0x8a, 0x7e, 0x51, 0x35, 0xe7, 0x8b, 0xec,
- 0xb7, 0x2f, 0xf7, 0x10, 0x10, 0x37, 0x16, 0x5c, 0xfe, 0xc0, 0xf3, 0x68, 0x50, 0x7a, 0x46, 0x5c,
- 0x5e, 0xbe, 0x97, 0xc3, 0xde, 0x11, 0xfc, 0x9d, 0x0d, 0x3a, 0xd5, 0xfd, 0x76, 0xeb, 0x89, 0xd7,
- 0x2d, 0xb7, 0x65, 0x3f, 0xd5, 0x23, 0xad, 0xba, 0xb7, 0xca, 0x4a, 0x4f, 0x79, 0x8d, 0x3b, 0x64,
- 0xf5, 0xf5, 0xfa, 0x80, 0xb0, 0xf3, 0x24, 0x9e, 0x5a, 0x91, 0xb1, 0xb5, 0x20, 0x06, 0x56, 0x70,
- 0xb4, 0x57, 0x6f, 0x0f, 0xad, 0x06, 0x3b, 0xc0, 0xa5, 0x59, 0xf6, 0x1b, 0x03, 0x4e, 0xe6, 0xb8,
- 0x9f, 0xff, 0xe8, 0x41, 0x78, 0xd1, 0x98, 0xc1, 0xaa, 0x70, 0xd0, 0xc3, 0x10, 0xcd, 0x49, 0x1b,
- 0x68, 0x20, 0x89, 0x00, 0x52, 0xf0, 0xa5, 0x5c, 0xfe, 0x75, 0x69, 0x43, 0x29, 0x9e, 0x54, 0xdc,
- 0xfc, 0x6b, 0xee, 0xe7, 0x9e, 0xba, 0x19, 0xe3, 0x9c, 0x32, 0xbf, 0xde, 0xec, 0xc3, 0x59, 0xdc,
- 0x2a, 0x76, 0x85, 0x4c, 0x5d, 0x78, 0x28, 0xda, 0xca, 0xd8, 0xa2, 0xf2, 0x2a, 0xc2, 0x0e, 0x88,
- 0xb5, 0x66, 0x4b, 0x3f, 0xca, 0x43, 0xd0, 0x46, 0x8c, 0xb0, 0xe1, 0x81, 0x64, 0x07, 0x41, 0xa5,
- 0x21, 0xed, 0x9a, 0x56, 0x5e, 0x36, 0x4a, 0x5c, 0xf5, 0xa7, 0x3f, 0xd9, 0x9a, 0xb8, 0x8a, 0xea,
- 0x5a, 0x7a, 0x7b, 0x2d, 0x3d, 0xc9, 0x70, 0x43, 0x7f, 0x42, 0xf8, 0xa5, 0xf3, 0x00, 0x32, 0x0e,
- 0xf8, 0x20, 0x90, 0xc1, 0x72, 0xbc, 0x12, 0xcb, 0x22, 0xa3, 0xf3, 0x97, 0xb8, 0x58, 0xea, 0xeb,
- 0xea, 0xd0, 0x8c, 0x34, 0xb3, 0x36, 0x37, 0x1c, 0x43, 0xe7, 0x7c, 0x93, 0x65, 0x41, 0x00, 0xf0,
- 0xb2, 0xe4, 0xae, 0x31, 0x58, 0x06, 0x7a, 0x35, 0x89, 0xdf, 0x6e, 0x38, 0x96, 0x3f, 0xb0, 0xa5,
- 0x5c, 0xcb, 0x87, 0x96, 0x9b, 0x64, 0xa0, 0x7a, 0xfd, 0x48, 0x8b, 0xd3, 0xf0, 0xa1, 0x67, 0x32,
- 0x77, 0x0b, 0x24, 0x21, 0x79, 0xb0, 0xef, 0x66, 0x6d, 0x1a, 0x53, 0x11, 0xad, 0x0d, 0xd8, 0x31,
- 0x8c, 0xc0, 0xb3, 0x2c, 0xf0, 0x44, 0x45, 0x0a, 0xc0, 0x7b, 0xa5, 0xf0, 0x37, 0x3f, 0xea, 0xb3,
- 0xf5, 0x58, 0x18, 0x51, 0x04, 0x7f, 0x23, 0xf8, 0xbb, 0xcc, 0x6a, 0xdc, 0xf0, 0x30, 0xfa, 0x87,
- 0x3d, 0xc4, 0x75, 0x04, 0x1e, 0x2d, 0x45, 0xf0, 0xe2, 0x42, 0x67, 0xd2, 0x88, 0xc0, 0x04, 0x44,
- 0xe7, 0xab, 0x02, 0xf0, 0xbe, 0x86, 0x1a, 0x1d, 0xc0, 0x9b, 0x28, 0x04, 0x05, 0x39, 0x28, 0xf2,
- 0xfb, 0x3f, 0x2d, 0x79, 0x3e, 0xcf, 0x0a, 0xef, 0x65, 0x23, 0xf4, 0x3c, 0x41, 0xbc, 0xb0, 0x0f,
- 0xae, 0x26, 0xb8, 0x58, 0xa1, 0x75, 0xdf, 0x27, 0xcd, 0x4a, 0xbd, 0xa3, 0x6a, 0x9e, 0xe7, 0x32,
- 0x13, 0x65, 0x71, 0x75, 0x21, 0xa6, 0xbe, 0xb3, 0xcd, 0x9c, 0x42, 0xa1, 0x62, 0x6b, 0x9c, 0x79,
- 0xbf, 0xef, 0x93, 0xc3, 0x7c, 0xf2, 0x57, 0x70, 0x68, 0x14, 0x5d, 0xf1, 0xb7, 0x2a, 0x71, 0x11,
- 0xfc, 0x7a, 0xdd, 0x0e, 0xdf, 0xa1, 0xef, 0xca, 0x5e, 0xb3, 0x2e, 0x67, 0xf1, 0x82, 0x25, 0x84,
- 0x20, 0x11, 0x07, 0x6a, 0xe5, 0x4d, 0x63, 0xe9, 0xb0, 0x39, 0xf3, 0x42, 0x13, 0x8e, 0xc3, 0x39,
- 0x0a, 0x18, 0x8c, 0x15, 0x37, 0x1b, 0xec, 0x2d, 0x9b, 0x4b, 0x97, 0x20, 0x8b, 0x67, 0x34, 0xcb,
- 0xa2, 0x5b, 0x3d, 0xce, 0xdd, 0xb5, 0xd6, 0xbe, 0xf1, 0x75, 0x3c, 0x15, 0x93, 0xd7, 0x47, 0xd8,
- 0x0a, 0x97, 0xd1, 0xe4, 0x68, 0xb8, 0x16, 0xa8, 0x64, 0xb7, 0x9e, 0x8e, 0x55, 0x2c, 0x45, 0xab,
- 0xc4, 0xb8, 0xaa, 0xc7, 0x26, 0x69, 0x92, 0x7d, 0x47, 0x53, 0x11, 0x07, 0x04, 0x18, 0x70, 0x7b,
- 0xcb, 0xbb, 0x5f, 0x60, 0x55, 0x07, 0xbb, 0x28, 0x2a, 0x74, 0x09, 0x2f, 0x6f, 0x91, 0x19, 0xf3,
- 0x5c, 0xcb, 0x29, 0x1e, 0xef, 0x87, 0xd4, 0xa4, 0x83, 0x1c, 0xe7, 0x8a, 0x61, 0xb4, 0xfe, 0x7a,
- 0xa4, 0x2c, 0xc0, 0x63, 0x47, 0x53, 0x93, 0x24, 0xde, 0x1e, 0x46, 0x62, 0x7e, 0xb2, 0x76, 0x58,
- 0x39, 0x80, 0x3a, 0x54, 0x41, 0xa4, 0xa5, 0xaf, 0xa5, 0x7f, 0x18, 0xcf, 0xca, 0xe6, 0x17, 0x5e,
- 0xc8, 0x0a, 0x54, 0x9e, 0x24, 0x35, 0xa5, 0x85, 0x1e, 0x4e, 0xe4, 0x00, 0xd4, 0xfc, 0xb2, 0x08,
- 0x5d, 0xef, 0x99, 0x28, 0xe9, 0xcf, 0x5c, 0xa2, 0x89, 0x4c, 0x10, 0xba, 0x4c, 0xa3, 0x35, 0x35,
- 0x99, 0xb7, 0x5e, 0xfd, 0x5e, 0x5e, 0x63, 0xd5, 0x3a, 0x6e, 0xf9, 0x2a, 0xf1, 0x0b, 0x34, 0xfc,
- 0x40, 0x8f, 0xe8, 0x85, 0xc5, 0x82, 0x16, 0xa0, 0xfc, 0x39, 0x94, 0xbb, 0xb0, 0x6a, 0x3d, 0x9a,
- 0xe0, 0x04, 0xf4, 0x90, 0x04, 0x57, 0x70, 0x99, 0xc3, 0x98, 0x35, 0x37, 0x3f, 0x2e, 0x36, 0x27,
- 0x81, 0x27, 0xbb, 0x5f, 0x33, 0x32, 0xe3, 0x93, 0xd3, 0x1d, 0x79, 0xa9, 0x0e, 0x43, 0x0b, 0x02,
- 0xa5, 0x31, 0x2f, 0x96, 0x93, 0x8f, 0xea, 0x2a, 0x84, 0x68, 0x52, 0x2f, 0x89, 0x1a, 0xfe, 0xb4,
- 0xc6, 0x11, 0xd5, 0x64, 0xe3, 0x44, 0xc5, 0xe9, 0xfe, 0x17, 0x7f, 0x03, 0xd6, 0x9b, 0x62, 0xff,
- 0xd0, 0xf5, 0xdc, 0x9f, 0x04, 0x0c, 0xe3, 0x0f, 0x41, 0x6f, 0x48, 0x62, 0x79, 0x6d, 0xd2, 0xc1,
- 0x51, 0x76, 0xc3, 0x4e, 0x6b, 0x54, 0x54, 0x42, 0xb9, 0xa5, 0x82, 0x47, 0x48, 0x8b, 0x91, 0x63,
- 0xba, 0xcb, 0x34, 0x8c, 0x2e, 0x36, 0x09, 0x85, 0x44, 0x1e, 0x1d, 0x1f, 0x28, 0x90, 0x60, 0xbc,
- 0x58, 0xb9, 0xd7, 0xfe, 0xe6, 0x12, 0xe8, 0xe2, 0x5f, 0x4b, 0x80, 0x0b, 0x90, 0x10, 0x39, 0xd2,
- 0x2e, 0x84, 0xd1, 0x99, 0x3d, 0xe6, 0x84, 0xdb, 0x41, 0x17, 0x73, 0x28, 0xfc, 0xc5, 0x15, 0x08,
- 0xb0, 0x15, 0x61, 0x69, 0x90, 0x29, 0xea, 0xdb, 0xa9, 0xac, 0xe6, 0x4f, 0x26, 0xbb, 0xde, 0x50,
- 0xa0, 0xcc, 0xd8, 0x3d, 0x4b, 0x5d, 0xe2, 0xb7, 0x87, 0x3f, 0x42, 0x81, 0x67, 0x91, 0xc4, 0x54,
- 0x18, 0xe7, 0x39, 0x6a, 0x3a, 0xc9, 0xc9, 0x87, 0xd5, 0x55, 0x54, 0x06, 0xab, 0xd1, 0x44, 0xf0,
- 0x9d, 0x03, 0x78, 0x9b, 0x7a, 0xd0, 0x40, 0x72, 0xd8, 0x37, 0xc5, 0x77, 0x3d, 0xbf, 0x7f, 0x2c,
- 0xc4, 0xce, 0x96, 0x16, 0x17, 0xe6, 0x12, 0x6b, 0x84, 0x20, 0x82, 0x47, 0xbc, 0xc3, 0x9b, 0x21,
- 0xed, 0x60, 0x75, 0x37, 0xac, 0x94, 0x71, 0x46, 0xb3, 0xdc, 0x6e, 0x6a, 0x71, 0x84, 0x5d, 0xef,
- 0x0e, 0x92, 0x87, 0x21, 0xc4, 0x1a, 0x06, 0xad, 0xff, 0x0f, 0x34, 0xfa, 0x75, 0x10, 0xc8, 0x08,
- 0x3b, 0x7a, 0x8b, 0x0d, 0x16, 0xb6, 0x9c, 0x93, 0xe3, 0x42, 0xc4, 0x65, 0x5d, 0x40, 0x62, 0x7f,
- 0xc6, 0x3e, 0xd1, 0xd5, 0x3e, 0x39, 0x34, 0xfe, 0xb7, 0x96, 0xd7, 0xaf, 0xc3, 0xa4, 0x1c, 0x8c,
- 0x11, 0xa8, 0xd9, 0xce, 0x54, 0x03, 0x8c, 0xc9, 0x93, 0xfc, 0xbf, 0x06, 0xe0, 0x66, 0xbf, 0xb7,
- 0xca, 0x54, 0xf4, 0x9e, 0x98, 0x14, 0x53, 0x78, 0x3b, 0xf8, 0x3a, 0x7f, 0xa2, 0x36, 0xa1, 0x3c,
- 0xf0, 0x3d, 0x61, 0x20, 0x6c, 0x89, 0x63, 0x83, 0x22, 0xd6, 0xae, 0xef, 0x90, 0x70, 0x88, 0x89,
- 0xa6, 0xca, 0x38, 0x7f, 0x12, 0x8c, 0x31, 0x6d, 0x0e, 0xc9, 0x73, 0x61, 0xa9, 0x39, 0x4b, 0x14,
- 0x5b, 0xcc, 0xea, 0xd7, 0xe1, 0xaf, 0x01, 0x9f, 0x89, 0x12, 0xe5, 0x9d, 0xa9, 0x4e, 0xf0, 0xbf,
- 0x6d, 0xff, 0x97, 0x48, 0x3c, 0xd9, 0x20, 0x61, 0x2c, 0x87, 0x6e, 0x2b, 0xcb, 0x0f, 0x87, 0x36,
- 0xc0, 0x12, 0x9f, 0xa1, 0xad, 0x33, 0x59, 0x7c, 0x12, 0x5a, 0x8a, 0xe0, 0x54, 0x58, 0xe6, 0x4c,
- 0x08, 0x01, 0x8d, 0xb9, 0x27, 0x4d, 0x9c, 0xbc, 0xca, 0x14, 0x39, 0x71, 0x43, 0xf1, 0xa7, 0x02,
- 0x58, 0x85, 0x99, 0x54, 0x41, 0x14, 0xb2, 0xab, 0xdf, 0x7e, 0x89, 0xc2, 0x96, 0x24, 0xeb, 0x67,
- 0x8b, 0x43, 0xda, 0x27, 0x91, 0xe1, 0x2a, 0x0f, 0xf5, 0xc9, 0x25, 0x21, 0xc8, 0x5c, 0xe3, 0x81,
- 0x02, 0x3c, 0xa1, 0xbf, 0x99, 0x16, 0x69, 0x63, 0x68, 0xf3, 0xa1, 0xe9, 0x2e, 0xd4, 0xb9, 0xda,
- 0x28, 0x00, 0x06, 0x8a, 0xc1, 0xbe, 0xaf, 0x89, 0xa2, 0x79, 0x06, 0xb8, 0x64, 0x9f, 0x79, 0xbb,
- 0xe7, 0x34, 0x69, 0x73, 0x79, 0xc1, 0xac, 0x2f, 0x69, 0x64, 0x90, 0x7a, 0x02, 0x99, 0x4d, 0xe9,
- 0x7c, 0xab, 0x57, 0x7a, 0x3c, 0x38, 0x0a, 0xd0, 0x57, 0x74, 0x1e, 0x1e, 0x57, 0xdb, 0xe4, 0x8d,
- 0x44, 0x22, 0x08, 0xc3, 0x55, 0xbf, 0xb9, 0xeb, 0xd9, 0xdf, 0xc3, 0x98, 0x8a, 0x83, 0x62, 0x94,
- 0x95, 0x61, 0xa2, 0x3b, 0x71, 0x7e, 0x18, 0x5b, 0x92, 0x79, 0x69, 0xc8, 0x4b, 0xea, 0x25, 0x81,
- 0xb8, 0xfa, 0xcb, 0x42, 0x41, 0xea, 0xb8, 0xe8, 0xb3, 0xf2, 0x34, 0x96, 0x7b, 0xcf, 0x29, 0x15,
- 0xd4, 0x9f, 0xc1, 0x14, 0xb1, 0x57, 0x59, 0xa1, 0xb0, 0xaa, 0xd6, 0xaf, 0x74, 0xd7, 0xde, 0x34,
- 0xa5, 0x09, 0x43, 0x88, 0x72, 0x43, 0x6d, 0x13, 0xb3, 0xcb, 0xb9, 0xaf, 0x45, 0xb4, 0x7f, 0xe3,
- 0xe5, 0x7f, 0xb3, 0x14, 0x06, 0x39, 0xfe, 0x52, 0xdf, 0x6a, 0x0b, 0x40, 0x1a, 0xf4, 0x8e, 0xd2,
- 0x9b, 0xa6, 0x3d, 0x96, 0x4d, 0xce, 0x54, 0x0c, 0x65, 0x41, 0x8e, 0x56, 0x8f, 0xcb, 0x00, 0x8f,
- 0xba, 0xdb, 0x17, 0x1b, 0x94, 0xa1, 0xd8, 0x9e, 0xfb, 0x63, 0x8c, 0x01, 0xd4, 0x89, 0xf5, 0x81,
- 0x16, 0xfa, 0x43, 0xd6, 0xfe, 0x4c, 0x44, 0x3d, 0x16, 0x26, 0x4c, 0x58, 0x07, 0x9f, 0xcd, 0xb5,
- 0x35, 0xb3, 0xf9, 0xd4, 0xb3, 0x90, 0x43, 0x04, 0x74, 0x20, 0x2a, 0xfe, 0x62, 0xfa, 0x17, 0x97,
- 0xbe, 0x0a, 0xa3, 0xb7, 0x48, 0xe7, 0x67, 0x32, 0xaa, 0x9c, 0x64, 0x99, 0x8a, 0x1b, 0x07, 0x3a,
- 0x0e, 0x3c, 0x0f, 0x84, 0x5b, 0x01, 0x10, 0x85, 0x9e, 0x27, 0x09, 0xd4, 0xae, 0x91, 0xdb, 0x65,
- 0xcd, 0xdd, 0xe2, 0xf1, 0x08, 0x00, 0x3b, 0xe4, 0xe4, 0x2c, 0xf7, 0x5e, 0xfe, 0x45, 0x19, 0x9a,
- 0x69, 0x7c, 0x61, 0xdb, 0x29, 0xf8, 0x97, 0xd7, 0x49, 0x52, 0xde, 0x80, 0x2c, 0x5e, 0x55, 0x60,
- 0xc9, 0xbc, 0x9a, 0x56, 0x4d, 0x01, 0x6e, 0x4e, 0x36, 0x85, 0x4a, 0x11, 0x12, 0x5e, 0xb7, 0x7d,
- 0x96, 0x23, 0x89, 0x3c, 0x14, 0x14, 0x0f, 0xad, 0x40, 0x7f, 0x0c, 0x88, 0xb8, 0x07, 0xa2, 0x70,
- 0x2c, 0x69, 0xa9, 0xec, 0x87, 0x45, 0x99, 0x33, 0x06, 0xca, 0xad, 0xb4, 0x5c, 0x44, 0x1c, 0x37,
- 0x7b, 0xfb, 0x6a, 0x3b, 0x23, 0x74, 0x60, 0xc5, 0xa6, 0x69, 0x9c, 0x0c, 0x23, 0x95, 0x69, 0x27,
- 0x39, 0xb8, 0x29, 0x81, 0x55, 0x59, 0x53, 0xc2, 0xe9, 0xf3, 0x25, 0x63, 0xa0, 0x25, 0xc3, 0x79,
- 0x78, 0x62, 0x7f, 0x37, 0x0f, 0xe9, 0x8c, 0xec, 0xf1, 0x43, 0x4d, 0x40, 0x6c, 0x4f, 0xa1, 0xff,
- 0xe7, 0x1c, 0xb2, 0xe4, 0xde, 0x7b, 0x34, 0xb1, 0x4b, 0x16, 0x3d, 0x7f, 0xba, 0xac, 0x99, 0xd8,
- 0xa8, 0xa1, 0x7f, 0xf5, 0xfc, 0x08, 0x14, 0xb6, 0x5c, 0x62, 0x1a, 0x53, 0x7b, 0x76, 0x00, 0x32,
- 0xbe, 0xba, 0xbb, 0x50, 0xb9, 0xa2, 0x4c, 0xf2, 0x4a, 0x00, 0xc5, 0xc6, 0x7c, 0x91, 0xb9, 0xa6,
- 0x86, 0x72, 0x35, 0x2d, 0xe1, 0x7a, 0xb9, 0xd2, 0xd0, 0x62, 0x22, 0xf0, 0x87, 0xe4, 0xbc, 0x89,
- 0x3b, 0xb8, 0xac, 0xb2, 0x91, 0xa1, 0xdc, 0x4c, 0xdd, 0xab, 0x2b, 0xcd, 0x0e, 0x94, 0xb4, 0x17,
- 0x4b, 0x01, 0xcf, 0xec, 0x76, 0xe9, 0x2f, 0x0f, 0x56, 0xc4, 0x75, 0x76, 0x9d, 0xfe, 0x44, 0x5c,
- 0x63, 0x5d, 0x5d, 0xd9, 0x9a, 0x59, 0x6f, 0xba, 0xf4, 0x96, 0xa1, 0x47, 0xee, 0x94, 0xe9, 0xe6,
- 0x0a, 0x55, 0x00, 0x89, 0x8d, 0x2d, 0x69, 0x1b, 0x34, 0x4a, 0xd2, 0x3f, 0xa8, 0x3c, 0x9c, 0x1a,
- 0x66, 0x25, 0x68, 0x4b, 0xdc, 0x84, 0xe2, 0xe1, 0xc1, 0xbf, 0xc2, 0xe3, 0x5d, 0xc5, 0xd7, 0x34,
- 0x03, 0xd1, 0x8f, 0xf0, 0xae, 0x1b, 0x25, 0x13, 0x45, 0xc1, 0x64, 0x18, 0x55, 0x27, 0x2d, 0xac,
- 0xd3, 0x5d, 0x94, 0xab, 0x66, 0xb4, 0xef, 0x1c, 0xca, 0x95, 0x44, 0xb1, 0x95, 0xd2, 0x73, 0x66,
- 0x3e, 0x7c, 0xc7, 0x5f, 0x86, 0x0e, 0xb4, 0x81, 0x15, 0xa8, 0x0f, 0xba, 0x0c, 0x0e, 0xf1, 0x1b,
- 0xec, 0x3f, 0x2f, 0x08, 0x26, 0xef, 0x2b, 0x13, 0x96, 0x98, 0xec, 0x16, 0x88, 0xe8, 0x30, 0x49,
- 0xe8, 0xa7, 0x69, 0x3c, 0x10, 0x7d, 0x3c, 0x5c, 0x73, 0xd2, 0x9d, 0xf3, 0xd6, 0x3e, 0x8a, 0xcb,
- 0x05, 0xb0, 0x24, 0x3b, 0x99, 0xa7, 0x2b, 0x05, 0x96, 0x9a, 0x7d, 0x1e, 0xbd, 0x93, 0x0a, 0x2d,
- 0x79, 0xdf, 0x4f, 0xb3, 0x43, 0xf0, 0x44, 0x4f, 0xe0, 0xac, 0x78, 0x9c, 0x64, 0x85, 0x9b, 0x5e,
- 0x11, 0x0e, 0xea, 0x78, 0x59, 0xf1, 0xaf, 0x80, 0x10, 0xf4, 0xd9, 0x74, 0x0b, 0x18, 0x56, 0x58,
- 0xaa, 0xd7, 0xea, 0xc6, 0xd7, 0x8d, 0x72, 0x0b, 0x82, 0x44, 0x1e, 0x41, 0x9a, 0xbe, 0x41, 0x9b,
- 0xe4, 0x36, 0x27, 0x02, 0x5d, 0xd3, 0x00, 0x60, 0xaa, 0xa1, 0x16, 0x5c, 0xa7, 0x22, 0x2b, 0x2a,
- 0xcb, 0xe0, 0xed, 0xd2, 0xfb, 0xfd, 0x7a, 0x82, 0x21, 0xc0, 0x5d, 0xa6, 0x68, 0x5c, 0x81, 0xe0,
- 0xa4, 0xf8, 0xb5, 0x25, 0x7f, 0xfc, 0x72, 0x8a, 0x91, 0x1f, 0xad, 0x86, 0xcc, 0xa9, 0xe8, 0x67,
- 0x60, 0xfa, 0xdc, 0x07, 0x0e, 0x38, 0x4c, 0x6e, 0x6e, 0x2f, 0xad, 0xcc, 0x43, 0x92, 0x73, 0xe4,
- 0xa7, 0x05, 0x96, 0x43, 0x44, 0x30, 0x75, 0x8c, 0x18, 0xd0, 0x78, 0x04, 0xcb, 0x03, 0xf3, 0x2c,
- 0xce, 0x19, 0xc6, 0x15, 0xd1, 0x9c, 0x14, 0xd5, 0xf5, 0x3e, 0x57, 0x16, 0x15, 0xa8, 0xeb, 0xa7,
- 0xac, 0x18, 0x86, 0x41, 0x16, 0x55, 0x48, 0x3d, 0xa9, 0xb2, 0xdf, 0xc7, 0x6b, 0xef, 0xbf, 0x6c,
- 0xa1, 0x59, 0x59, 0x2c, 0xa7, 0x57, 0xad, 0x35, 0xe8, 0x75, 0x3e, 0xe3, 0x7b, 0xae, 0x48, 0xf4,
- 0x41, 0x1b, 0x84, 0xae, 0x7c, 0xeb, 0x85, 0x07, 0x2f, 0x65, 0xef, 0x55, 0x4d, 0x82, 0x9c, 0xef,
- 0xaa, 0xcc, 0x66, 0x6e, 0xc4, 0xdb, 0x15, 0xf7, 0x7b, 0x62, 0x42, 0x0b, 0x3a, 0x1d, 0xd3, 0x18,
- 0x12, 0xdb, 0x08, 0x50, 0xb2, 0x37, 0xd8, 0x2c, 0x55, 0x47, 0xb6, 0xf6, 0xc1, 0x3a, 0x9b, 0x59,
- 0x00, 0xe4, 0x25, 0x6e, 0x40, 0xdf, 0xb4, 0x38, 0x1f, 0x00, 0x17, 0x6c, 0x20, 0x59, 0x97, 0x46,
- 0xb9, 0xff, 0xea, 0x9e, 0x57, 0x34, 0x19, 0x54, 0xdd, 0x7f, 0xa0, 0x5f, 0x74, 0x72, 0x1b, 0xf2,
- 0xc1, 0x93, 0xed, 0x91, 0xa8, 0x15, 0x5e, 0x10, 0xfc, 0x24, 0xe1, 0xe6, 0x9b, 0xdb, 0x52, 0x2c,
- 0x44, 0x5c, 0xef, 0xdb, 0x6e, 0xc4, 0x50, 0x3f, 0x11, 0xd6, 0x7b, 0x36, 0xfc, 0x05, 0xb2, 0x55,
- 0x53, 0x2e, 0xb5, 0x43, 0x50, 0xd7, 0x56, 0x95, 0xc4, 0x5c, 0xe1, 0x26, 0xe3, 0x82, 0x63, 0x4f,
- 0xb3, 0x9e, 0x4c, 0x87, 0x3e, 0xab, 0x89, 0x33, 0x77, 0xab, 0xb9, 0xcf, 0xba, 0x1e, 0x7c, 0xc3,
- 0x41, 0x2f, 0xe2, 0x2b, 0x14, 0xd6, 0xd3, 0x55, 0x7f, 0x68, 0x37, 0x0c, 0x42, 0x2d, 0xbf, 0x9a,
- 0x51, 0x6c, 0xfe, 0x70, 0x45, 0xc2, 0x4f, 0x5d, 0xf4, 0x0a, 0x08, 0x2a, 0xd8, 0x89, 0xf1, 0x08,
- 0x2e, 0xbd, 0x70, 0x5b, 0xf5, 0x53, 0xf8, 0x5e, 0xc6, 0xec, 0x5c, 0x7b, 0xdc, 0x81, 0x16, 0xba,
- 0xc7, 0x52, 0x64, 0x7b, 0x0f, 0x2d, 0x41, 0x22, 0x60, 0x15, 0x58, 0x3d, 0xa0, 0x45, 0x16, 0x7d,
- 0xdd, 0xcc, 0xe5, 0x00, 0xc5, 0xd8, 0x0e, 0x9b, 0x88, 0x99, 0xde, 0xa4, 0xcd, 0x8b, 0x3c, 0xeb,
- 0x6c, 0x3f, 0x98, 0xec, 0xf9, 0x9a, 0x21, 0xb0, 0xd4, 0xd1, 0x42, 0x0c, 0xe0, 0x09, 0x79, 0x2a,
- 0x28, 0xf9, 0x2e, 0x25, 0x6e, 0xf4, 0x5d, 0xc5, 0xd5, 0xba, 0x0d, 0x94, 0xd5, 0x02, 0xfa, 0xa3,
- 0xab, 0xcf, 0xb6, 0xf5, 0xab, 0x1d, 0x32, 0xc3, 0x98, 0xc8, 0x54, 0x4c, 0xd1, 0xff, 0xfe, 0x4d,
- 0x5e, 0xc8, 0xeb, 0x18, 0x7e, 0xa7, 0x09, 0x54, 0xf5, 0x20, 0x39, 0x36, 0xee, 0x6c, 0x67, 0x9c,
- 0x88, 0x08, 0xf4, 0xdf, 0xae, 0x77, 0x4a, 0x14, 0x29, 0x5e, 0x13, 0xc4, 0x18, 0x55, 0x8e, 0xdf,
- 0x1b, 0x91, 0xb7, 0x6f, 0x43, 0x92, 0x00, 0x0d, 0xd0, 0xcf, 0xdb, 0x32, 0x70, 0xc0, 0xf3, 0x51,
- 0xea, 0xa8, 0xf8, 0xb9, 0x97, 0x16, 0x68, 0xa6, 0xf3, 0xc1, 0xbf, 0xdb, 0x59, 0x71, 0xb2, 0xb0,
- 0x94, 0xbc, 0x2f, 0xdf, 0xf9, 0xa3, 0x4d, 0x29, 0x04, 0xfe, 0xf6, 0xf0, 0x2f, 0x51, 0x58, 0xe9,
- 0xa2, 0x5b, 0x2a, 0xc0, 0xcf, 0x35, 0xba, 0x35, 0x5a, 0x4f, 0x66, 0x7f, 0x4d, 0xa5, 0x25, 0x75,
- 0x5d, 0xff, 0x53, 0x02, 0x8b, 0x0b, 0x4d, 0x50, 0x7a, 0x9e, 0xf2, 0x94, 0xb8, 0x61, 0x35, 0x87,
- 0xc5, 0x7f, 0x89, 0x4f, 0xeb, 0xc6, 0x2a, 0x48, 0x22, 0xe4, 0x2f, 0x78, 0x7e, 0xa0, 0x2d, 0x98,
- 0x21, 0x62, 0xd8, 0xf7, 0xbd, 0x2b, 0xde, 0x77, 0x07, 0xde, 0x55, 0xa2, 0xb2, 0xb9, 0x4a, 0x68,
- 0x5e, 0x4a, 0x0a, 0x0b, 0xc9, 0x49, 0x8e, 0xce, 0x57, 0x83, 0xb5, 0xca, 0xa0, 0x1c, 0x9b, 0xbb,
- 0x5f, 0x6a, 0xf1, 0x92, 0xac, 0x04, 0x8c, 0x1b, 0x46, 0x15, 0x99, 0x14, 0xe6, 0x06, 0xd1, 0x46,
- 0x77, 0x76, 0x3f, 0x2e, 0x37, 0x5b, 0x39, 0xdd, 0x3d, 0x96, 0x95, 0xd9, 0xe5, 0x8c, 0x03, 0x86,
- 0xc6, 0x02, 0x17, 0x95, 0x9a, 0x1c, 0x8c, 0x77, 0xe4, 0x47, 0xfe, 0xe3, 0x87, 0xe5, 0x28, 0xd5,
- 0xcf, 0x48, 0xce, 0x1c, 0x2f, 0xda, 0x23, 0x6c, 0xbc, 0xdf, 0xa7, 0x3f, 0x24, 0x82, 0x65, 0xb7,
- 0xe1, 0x49, 0x07, 0x0f, 0x67, 0x5d, 0x25, 0x05, 0x23, 0xb3, 0x5f, 0xe1, 0xf3, 0xb2, 0x5d, 0xf2,
- 0x22, 0x0b, 0xa3, 0x16, 0xc3, 0xdc, 0xa0, 0xa8, 0x29, 0xb3, 0xf2, 0xc6, 0xdc, 0x98, 0x98, 0xd0,
- 0x78, 0x83, 0xda, 0xea, 0x5e, 0x17, 0x37, 0x30, 0xcf, 0xb0, 0x5c, 0xec, 0xa1, 0xee, 0x70, 0xd5,
- 0x19, 0x0d, 0x86, 0x07, 0x2f, 0x4a, 0x97, 0x5e, 0xa2, 0xf4, 0x53, 0x4b, 0x38, 0x15, 0x53, 0x5b,
- 0xe5, 0xa1, 0x08, 0x43, 0xf8, 0x44, 0x04, 0x5e, 0xe4, 0xf7, 0x68, 0xcf, 0x85, 0xca, 0x25, 0x10,
- 0xed, 0xcc, 0xfa, 0x69, 0x1a, 0x39, 0x51, 0x1f, 0x92, 0xbd, 0xbe, 0xc7, 0x90, 0x1e, 0xb8, 0xde,
- 0x26, 0x2b, 0xc7, 0x5e, 0xb9, 0x2c, 0x36, 0x51, 0xe2, 0x6e, 0x1c, 0xe0, 0xd6, 0x4c, 0x0c, 0x11,
- 0x0d, 0x8f, 0x47, 0x6d, 0xb5, 0xc2, 0xb1, 0xfb, 0x0a, 0xef, 0xec, 0x0e, 0x2b, 0x00, 0xef, 0x1f,
- 0x0d, 0x5b, 0xd8, 0x6a, 0xba, 0xdb, 0x09, 0x3c, 0x6c, 0x50, 0x7a, 0x80, 0xda, 0xd1, 0xbc, 0x11,
- 0x91, 0xd6, 0x6c, 0xf5, 0x04, 0x9b, 0x0c, 0xbc, 0xc9, 0x15, 0x7e, 0x03, 0xbe, 0xe6, 0x6a, 0x31,
- 0x23, 0xef, 0x02, 0xfb, 0xb6, 0xc4, 0xfa, 0xf7, 0xe0, 0xf7, 0x29, 0x7f, 0x75, 0x71, 0x4d, 0x07,
- 0xea, 0x81, 0xea, 0x16, 0x70, 0xd6, 0xea, 0xb1, 0x6b, 0x44, 0x7d, 0xe8, 0xeb, 0x14, 0xfb, 0x7e,
- 0xd8, 0x68, 0xb4, 0x41, 0x60, 0x47, 0xa9, 0x93, 0xc5, 0x78, 0xc2, 0xc7, 0xb5, 0xcd, 0xe7, 0x6f,
- 0x11, 0x9c, 0x72, 0x6b, 0x99, 0x9f, 0xc0, 0x9c, 0x32, 0x01, 0x64, 0x1b, 0x7f, 0x0d, 0x00, 0xbf,
- 0x1d, 0xa1, 0x81, 0x51, 0x0f, 0x96, 0x2e, 0x02, 0x80, 0x26, 0xc1, 0x90, 0x70, 0x81, 0xfd, 0x20,
- 0x79, 0xd1, 0x61, 0x06, 0x0a, 0xab, 0x43, 0x02, 0xc1, 0x80, 0x0e, 0xbb, 0x1a, 0xb1, 0xfa, 0x98,
- 0x64, 0xcc, 0xbb, 0xe3, 0xf3, 0x58, 0x23, 0x7e, 0xfa, 0x91, 0x22, 0x5e, 0x61, 0x11, 0xe5, 0xff,
- 0xfa, 0xe5, 0x64, 0xa4
-};
-
-fastimage_t bfin_logo = {
-		DEF_BFIN_LOGO_DATA,
-		DEF_BFIN_LOGO_WIDTH,
-		DEF_BFIN_LOGO_HEIGHT,
-		DEF_BFIN_LOGO_BPP,
-		DEF_BFIN_LOGO_PIXEL_SIZE,
-		DEF_BFIN_LOGO_SIZE
-};
diff --git a/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_gzip.h b/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_gzip.h
deleted file mode 100644
index c5b0be9..0000000
--- a/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_gzip.h
+++ /dev/null
@@ -1,1242 +0,0 @@
-/*
- * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
- *
- * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
- *
- * Where:	'screen'	is the pointer to the frame buffer
- *		'width'	is the screen width
- *		'x'		is the horizontal position
- *		'y'		is the vertical position
- */
-
-#define EASYLOGO_ENABLE_GZIP 19303
-
-static unsigned char EASYLOGO_DECOMP_BUFFER[105800];
-
-#include <video_easylogo.h>
-
-#define	DEF_BFIN_LOGO_WIDTH		230
-#define	DEF_BFIN_LOGO_HEIGHT		230
-#define	DEF_BFIN_LOGO_PIXELS		52900
-#define	DEF_BFIN_LOGO_BPP		16
-#define	DEF_BFIN_LOGO_PIXEL_SIZE	2
-#define	DEF_BFIN_LOGO_SIZE		105800
-
-unsigned char DEF_BFIN_LOGO_DATA[] = {
- 0x1f, 0x8b, 0x08, 0x00, 0x9d, 0x56, 0x26, 0x4b, 0x00, 0x03, 0xec, 0x5d, 0x7f, 0x4c, 0x1b, 0x77,
- 0x96, 0xb7, 0x2e, 0xe8, 0x3a, 0x52, 0xb8, 0xd3, 0x64, 0xc3, 0x36, 0xd3, 0x14, 0xac, 0xf1, 0xc6,
- 0xa6, 0x36, 0x0c, 0xbd, 0x3a, 0xb8, 0x5a, 0x66, 0x01, 0x29, 0xb6, 0x82, 0x14, 0x5c, 0xb8, 0xdb,
- 0xb8, 0xa1, 0x5b, 0x9c, 0x3a, 0x77, 0xc4, 0x41, 0x2a, 0x72, 0xd1, 0x2a, 0x75, 0x68, 0xeb, 0x38,
- 0x20, 0x85, 0x23, 0x48, 0x45, 0x24, 0x77, 0x65, 0x09, 0x55, 0x59, 0x97, 0x53, 0x2d, 0x99, 0x53,
- 0x39, 0x99, 0x3f, 0xd2, 0x42, 0x6e, 0x49, 0xcc, 0x4a, 0x41, 0x35, 0x52, 0x90, 0x1c, 0xa9, 0xd9,
- 0x9a, 0xdb, 0x90, 0x18, 0xa9, 0xd6, 0xc5, 0x52, 0xb9, 0x3b, 0x77, 0xc5, 0xea, 0x9c, 0x86, 0xe6,
- 0x72, 0xdf, 0x37, 0x5f, 0x0f, 0xe3, 0xdf, 0x36, 0xb6, 0x93, 0xb4, 0x61, 0x3e, 0x5f, 0x85, 0xc4,
- 0x63, 0x67, 0xfc, 0xb5, 0x3f, 0xbc, 0xf7, 0x7d, 0xdf, 0xf7, 0xde, 0xf7, 0x3d, 0x89, 0x44, 0x84,
- 0x88, 0x1f, 0x32, 0xe8, 0x34, 0x43, 0xc4, 0x8f, 0x05, 0x98, 0x2f, 0x2d, 0xa1, 0x25, 0x3a, 0x88,
- 0x7e, 0xb2, 0x9f, 0x74, 0xc6, 0x0c, 0x78, 0xdc, 0x81, 0xae, 0xc3, 0xb3, 0x22, 0xab, 0x3f, 0x64,
- 0x60, 0x0e, 0x81, 0x41, 0x27, 0xb9, 0x40, 0x05, 0xa9, 0x12, 0x99, 0x5c, 0xd6, 0xa4, 0xea, 0x54,
- 0x0f, 0x6e, 0x8e, 0x4e, 0x55, 0x93, 0x4a, 0x2e, 0x2b, 0x91, 0x05, 0x29, 0x27, 0xc7, 0x2a, 0xe6,
- 0x54, 0xc4, 0x0f, 0x0b, 0x3c, 0x8b, 0x0b, 0x88, 0xc1, 0x26, 0xd5, 0xa0, 0x7a, 0x91, 0x0d, 0xb1,
- 0x4a, 0x5d, 0x97, 0x7e, 0xc8, 0xb0, 0x64, 0x14, 0xc6, 0x94, 0x61, 0xc8, 0xd0, 0xac, 0x27, 0x74,
- 0x8b, 0xec, 0xa0, 0xba, 0x49, 0x85, 0x39, 0xed, 0x10, 0xf9, 0xfc, 0xc1, 0x00, 0x4b, 0x23, 0x66,
- 0xb1, 0x53, 0x35, 0xc9, 0x12, 0x88, 0xc1, 0x25, 0x63, 0xa9, 0xb9, 0xd5, 0xd2, 0x6a, 0x29, 0x35,
- 0x4f, 0x19, 0xba, 0xf4, 0xc0, 0x1e, 0xcf, 0xec, 0x9a, 0xb1, 0xd5, 0xd2, 0x6d, 0x61, 0xcc, 0x4b,
- 0xc6, 0x21, 0x83, 0x12, 0x71, 0xda, 0x89, 0x18, 0x5d, 0xa0, 0xfa, 0x49, 0x51, 0xe7, 0x3e, 0x69,
- 0x60, 0x69, 0x74, 0x92, 0x41, 0xaa, 0x49, 0xb5, 0x88, 0xd8, 0x9a, 0x42, 0x5c, 0x95, 0x9a, 0x4b,
- 0xcd, 0xcd, 0xfa, 0x41, 0xb5, 0x93, 0x4c, 0xf7, 0xbf, 0x3a, 0x08, 0xb9, 0x4c, 0xa9, 0x83, 0x57,
- 0xae, 0x21, 0x59, 0x6d, 0xd6, 0x2f, 0xb2, 0x20, 0xa3, 0x58, 0x42, 0x1f, 0xe7, 0xec, 0x45, 0x08,
- 0xa0, 0x25, 0xc0, 0x23, 0x48, 0x63, 0x88, 0xed, 0xd2, 0xaf, 0x19, 0xd7, 0x90, 0x0e, 0x25, 0x74,
- 0x72, 0x19, 0x9d, 0xe3, 0xff, 0x5e, 0xa0, 0x16, 0x59, 0x90, 0xd4, 0x35, 0x63, 0x97, 0x3e, 0x84,
- 0x24, 0x34, 0x18, 0x95, 0x4f, 0x11, 0x8f, 0x17, 0x58, 0xaf, 0x06, 0x29, 0xe0, 0x71, 0xc8, 0x00,
- 0x12, 0xa6, 0xd4, 0x35, 0xa9, 0x3a, 0xb6, 0x2c, 0x57, 0x5a, 0x24, 0xa3, 0x84, 0x0e, 0x74, 0xf2,
- 0x90, 0x21, 0x84, 0xe4, 0x73, 0x41, 0xe4, 0xf3, 0x31, 0x03, 0x4b, 0xa4, 0x5c, 0xb6, 0x88, 0xe4,
- 0x91, 0x31, 0xaf, 0x1d, 0x0f, 0xb1, 0x25, 0x32, 0xba, 0x80, 0xbb, 0x05, 0xa9, 0x10, 0x8b, 0x75,
- 0xf3, 0xa4, 0x1a, 0x6b, 0xdb, 0xfc, 0xef, 0x26, 0x62, 0x2b, 0x00, 0x26, 0x17, 0xd0, 0x0a, 0x49,
- 0xa0, 0x35, 0xaf, 0xdb, 0xd2, 0xac, 0x5f, 0xa0, 0xe8, 0x22, 0xdc, 0x73, 0x81, 0x52, 0xea, 0xba,
- 0x2d, 0x53, 0x86, 0x90, 0x16, 0xa4, 0x53, 0x64, 0xf3, 0x71, 0x00, 0x98, 0x0c, 0x52, 0x83, 0xea,
- 0x66, 0x24, 0x91, 0xa5, 0xe6, 0x42, 0xe4, 0x31, 0xf9, 0xce, 0x25, 0x32, 0xb0, 0x88, 0xba, 0x38,
- 0xe9, 0x14, 0x75, 0xed, 0xa3, 0x06, 0x66, 0x72, 0x52, 0x3d, 0x64, 0x60, 0xd0, 0x0a, 0x47, 0x17,
- 0x7c, 0xaf, 0x44, 0xf9, 0xd3, 0x12, 0xa0, 0x6d, 0xa7, 0x8c, 0x21, 0x56, 0x8e, 0x74, 0xad, 0xc8,
- 0xe6, 0xa3, 0x03, 0x2f, 0x93, 0x60, 0xed, 0x84, 0xd8, 0xc2, 0x76, 0x10, 0xb4, 0xe4, 0x1a, 0x75,
- 0x42, 0x35, 0xa0, 0xde, 0x27, 0x3b, 0x4b, 0xd2, 0x71, 0xd7, 0x3b, 0x55, 0x60, 0xdb, 0x12, 0xc8,
- 0x96, 0x02, 0x36, 0x0b, 0x9b, 0xb1, 0x88, 0x74, 0xd0, 0x22, 0x8b, 0xa7, 0x53, 0xd5, 0xa5, 0x2f,
- 0x35, 0x2f, 0x16, 0xc8, 0xa4, 0x44, 0x72, 0x80, 0x38, 0xa8, 0x7a, 0x41, 0xf7, 0xbe, 0xe1, 0x90,
- 0xde, 0xcb, 0x26, 0xf2, 0x19, 0xa4, 0xa6, 0xd0, 0x6f, 0x0b, 0xec, 0x6f, 0x44, 0x36, 0x1f, 0x0d,
- 0x68, 0x49, 0x3f, 0x89, 0x77, 0xf9, 0x85, 0xca, 0x24, 0xa0, 0x83, 0x70, 0xa9, 0xaf, 0x1b, 0x5b,
- 0x2c, 0x2d, 0x96, 0x6f, 0x8c, 0x87, 0xf4, 0xe7, 0xd4, 0xd7, 0xe2, 0x2c, 0x28, 0x27, 0x39, 0x65,
- 0x04, 0xd9, 0x97, 0x73, 0xeb, 0x66, 0xa1, 0xef, 0x25, 0x22, 0x1e, 0xfc, 0x4a, 0xb9, 0x66, 0x1c,
- 0x32, 0x14, 0xe3, 0xdb, 0x3d, 0x4b, 0xde, 0x65, 0x77, 0x9a, 0xc3, 0xf6, 0x5f, 0x0e, 0xfb, 0xec,
- 0x8c, 0xf9, 0x7d, 0x83, 0x97, 0x0d, 0xc6, 0xb1, 0xb9, 0x40, 0x81, 0x07, 0x77, 0x11, 0x5d, 0x15,
- 0x6d, 0xda, 0x62, 0x83, 0xd7, 0xaf, 0x8c, 0x39, 0xbd, 0x77, 0x6e, 0x2b, 0xf8, 0x84, 0x7c, 0x01,
- 0xed, 0x41, 0x0e, 0x0f, 0x8f, 0x8c, 0x1e, 0x8e, 0x61, 0xf3, 0x40, 0xcc, 0x6f, 0x49, 0x90, 0x02,
- 0x4f, 0xd2, 0xa4, 0x7a, 0x81, 0x12, 0x6d, 0xa0, 0x62, 0x02, 0xa4, 0xb2, 0x44, 0x46, 0xe8, 0x18,
- 0x73, 0xa7, 0xaa, 0x38, 0x77, 0xbc, 0x46, 0xbd, 0xa9, 0x9f, 0xb6, 0x9e, 0x1c, 0xfe, 0x60, 0xf4,
- 0xa5, 0x81, 0x69, 0x7b, 0x8b, 0xe5, 0xba, 0x51, 0xa9, 0x4b, 0xd4, 0xb4, 0x9d, 0x2a, 0xd8, 0xa1,
- 0x74, 0x8a, 0x36, 0x50, 0x51, 0x01, 0x52, 0x39, 0xa8, 0x06, 0xdf, 0x39, 0x5d, 0xa4, 0x3b, 0xfe,
- 0x85, 0xec, 0x7d, 0xc3, 0xb4, 0x95, 0x1c, 0x08, 0xdb, 0xcf, 0x5b, 0xab, 0xcd, 0xd7, 0x8d, 0x6f,
- 0xea, 0xff, 0x12, 0x71, 0xf9, 0x75, 0x9c, 0x64, 0x6a, 0x09, 0xa5, 0x0e, 0x6c, 0x20, 0xd8, 0x6d,
- 0x16, 0xeb, 0x7d, 0x45, 0x14, 0x5b, 0x2a, 0x69, 0xc9, 0x0e, 0xc4, 0x25, 0x58, 0x3e, 0x3b, 0xcd,
- 0x9f, 0x22, 0x5b, 0xf6, 0x2e, 0x7b, 0x0e, 0xed, 0x4e, 0xae, 0x25, 0xad, 0x8d, 0x4e, 0x12, 0xf4,
- 0xec, 0x20, 0xa7, 0x67, 0x8b, 0xf3, 0xce, 0xdb, 0x1d, 0x60, 0xc1, 0x36, 0xa9, 0x20, 0xae, 0xdc,
- 0x5f, 0x94, 0xb5, 0x12, 0x73, 0x79, 0x48, 0x8f, 0xa4, 0xd1, 0xf0, 0x8c, 0xce, 0x85, 0x58, 0xfc,
- 0x9a, 0x3a, 0x4b, 0x1e, 0x48, 0xb9, 0x2a, 0x0e, 0xaa, 0x5b, 0x2d, 0x4a, 0x9d, 0x5c, 0x94, 0xcc,
- 0x22, 0x41, 0x4b, 0x2c, 0x80, 0x05, 0x7b, 0x3c, 0xc4, 0xd2, 0x45, 0xbb, 0xe7, 0xd7, 0x94, 0x97,
- 0xbd, 0xcb, 0x9e, 0x50, 0x01, 0x8b, 0x99, 0xee, 0x4a, 0x4b, 0x20, 0xca, 0x39, 0x29, 0x4a, 0x66,
- 0x91, 0x80, 0x35, 0xec, 0xda, 0xf1, 0x12, 0x59, 0xf1, 0xee, 0x79, 0x96, 0xdc, 0x21, 0xfb, 0x84,
- 0x3c, 0x90, 0x03, 0x3f, 0x41, 0xaa, 0xdb, 0xa2, 0xd4, 0x8b, 0x92, 0x59, 0x0c, 0x60, 0x0d, 0xdb,
- 0x65, 0xe8, 0x32, 0x14, 0x4b, 0xc3, 0xe2, 0xbb, 0xd2, 0x39, 0xbf, 0x72, 0xca, 0x20, 0x4a, 0x66,
- 0x71, 0x40, 0x4b, 0xc0, 0x86, 0x5d, 0x32, 0x12, 0x3a, 0xfa, 0x09, 0xcd, 0x40, 0x2e, 0x63, 0xcc,
- 0x4a, 0x64, 0xcd, 0x8a, 0x5e, 0x83, 0x42, 0x01, 0xab, 0xe5, 0x22, 0xbb, 0x86, 0x24, 0xe3, 0x49,
- 0xcd, 0xa0, 0x83, 0x80, 0x0c, 0x3e, 0xd8, 0x67, 0xd2, 0x4f, 0x6a, 0x0a, 0x4f, 0x09, 0xb4, 0x44,
- 0x90, 0x82, 0x3c, 0x0e, 0x79, 0x11, 0x57, 0xcb, 0xad, 0x81, 0x96, 0x4c, 0xaa, 0xc1, 0x9f, 0x1f,
- 0x14, 0xb5, 0x6c, 0x41, 0xa0, 0xb9, 0xbc, 0xb9, 0x66, 0xfd, 0x94, 0x61, 0x81, 0x7a, 0x72, 0xb3,
- 0x08, 0x52, 0x4b, 0x46, 0xd8, 0x99, 0x88, 0x5a, 0xb6, 0x10, 0x00, 0x97, 0xb0, 0xb7, 0x1c, 0x32,
- 0x6c, 0x3d, 0x33, 0xab, 0x78, 0xe8, 0x20, 0x94, 0x7a, 0xf0, 0x19, 0x88, 0x5a, 0xb6, 0x10, 0x80,
- 0x15, 0xdb, 0xa9, 0x9a, 0x32, 0x34, 0xeb, 0x9f, 0xec, 0x3c, 0x20, 0x42, 0xb3, 0xc8, 0x8a, 0xb6,
- 0x6c, 0x21, 0xe0, 0xad, 0x58, 0xa5, 0xee, 0xc9, 0xce, 0xa3, 0x44, 0x06, 0x73, 0x00, 0x5b, 0xf6,
- 0xc9, 0xce, 0xe3, 0xc7, 0x0c, 0x2d, 0xe1, 0xe4, 0xa2, 0x96, 0x21, 0x36, 0xf5, 0xf3, 0x07, 0x88,
- 0x7f, 0x20, 0x72, 0xd9, 0xf1, 0x27, 0xc3, 0x49, 0x1e, 0x54, 0x4d, 0xb2, 0x93, 0xea, 0x60, 0x4e,
- 0x79, 0x7c, 0x1d, 0x04, 0xe8, 0x79, 0xc8, 0xc1, 0xcd, 0xe5, 0xd5, 0x22, 0x52, 0x81, 0xdf, 0x91,
- 0x2c, 0xa6, 0xe4, 0xf2, 0x00, 0xf1, 0x35, 0x75, 0x50, 0x75, 0x42, 0x75, 0x50, 0xf5, 0xc9, 0x96,
- 0xfd, 0x08, 0x10, 0x8d, 0x6e, 0xb1, 0x84, 0xed, 0xd3, 0xf6, 0xeb, 0xc6, 0x1d, 0x39, 0xd8, 0xc8,
- 0x4a, 0x64, 0x4b, 0x8b, 0x2b, 0x66, 0x21, 0x00, 0x2e, 0x43, 0x88, 0xcb, 0xc1, 0x34, 0xbb, 0xcb,
- 0x6b, 0x94, 0x4b, 0x7d, 0x48, 0xff, 0xa9, 0xe1, 0x4d, 0xfd, 0x09, 0xd5, 0x56, 0xe5, 0x13, 0xec,
- 0xaa, 0x17, 0x74, 0x61, 0xfb, 0xc9, 0xe1, 0x69, 0x7b, 0xf6, 0x08, 0x8c, 0xb8, 0x62, 0x16, 0x0a,
- 0xd8, 0x5d, 0x86, 0xb4, 0x6b, 0xc6, 0xa6, 0xb4, 0xdf, 0xf5, 0x59, 0xf2, 0x9c, 0xfa, 0x53, 0x43,
- 0xb7, 0xa5, 0xc5, 0x72, 0x97, 0xcd, 0xb6, 0x9a, 0x41, 0x9e, 0x49, 0xa7, 0xea, 0x19, 0x9d, 0x52,
- 0x07, 0x27, 0x0e, 0xe0, 0xcc, 0x1e, 0xac, 0xc7, 0x3b, 0xcd, 0x90, 0x5b, 0x90, 0x4d, 0x36, 0x21,
- 0x7b, 0x56, 0x5c, 0x31, 0x0b, 0x01, 0xf6, 0x14, 0xac, 0xa5, 0xf0, 0x14, 0x00, 0x2f, 0x70, 0xe2,
- 0x0e, 0xbe, 0xdb, 0x6b, 0xd4, 0x21, 0x3d, 0xb0, 0xe9, 0x52, 0xd3, 0x19, 0xee, 0x34, 0xa8, 0xde,
- 0x69, 0x7e, 0x69, 0xe0, 0xe4, 0xe8, 0xc8, 0xe8, 0x25, 0xf4, 0xe7, 0x83, 0xd1, 0xc3, 0xc3, 0x17,
- 0xac, 0x8b, 0x2c, 0x9c, 0x67, 0x58, 0x33, 0x1e, 0x1e, 0xde, 0x69, 0xce, 0x2c, 0xd7, 0x1d, 0xc4,
- 0xda, 0xf1, 0x2e, 0xd1, 0xc7, 0x5e, 0x00, 0x52, 0x73, 0x09, 0x59, 0xac, 0x4b, 0xc6, 0x0b, 0xd6,
- 0x1b, 0xf6, 0x0b, 0x56, 0xc8, 0x65, 0x85, 0x6c, 0xb9, 0x10, 0xdb, 0x6d, 0xf9, 0x26, 0xed, 0xca,
- 0xa7, 0x25, 0xa6, 0x0c, 0x87, 0x87, 0xd7, 0x1d, 0x1a, 0x77, 0x8f, 0x7b, 0x6c, 0x06, 0x46, 0x8f,
- 0xbb, 0xcd, 0x5d, 0xe6, 0x1a, 0x19, 0x9d, 0x32, 0xc0, 0xe9, 0x4d, 0xc6, 0x1c, 0xb6, 0x9f, 0xc8,
- 0xa2, 0x67, 0xa7, 0x8c, 0x53, 0x86, 0x4e, 0x95, 0xc8, 0x65, 0xbe, 0xe0, 0xb9, 0x8c, 0x8f, 0x77,
- 0x0d, 0xaa, 0xc3, 0xf6, 0x75, 0x47, 0x1b, 0xe2, 0x05, 0x18, 0x59, 0x77, 0x74, 0x5b, 0x20, 0x5f,
- 0x4e, 0xa9, 0xfb, 0xc6, 0x98, 0x5a, 0x32, 0xb5, 0xc4, 0x75, 0xe3, 0xba, 0x63, 0x6c, 0x26, 0xe2,
- 0xa1, 0xbc, 0xac, 0xb7, 0xdd, 0x87, 0x47, 0x9d, 0x97, 0xf2, 0xce, 0x7a, 0xd6, 0x1d, 0x90, 0xd9,
- 0xb7, 0x40, 0x41, 0x6e, 0x65, 0x66, 0xc9, 0xe4, 0xad, 0x1f, 0x71, 0xc5, 0xcc, 0x0f, 0xbc, 0x37,
- 0x36, 0x18, 0xe3, 0xc1, 0x93, 0xcb, 0xc2, 0xf6, 0x36, 0xf7, 0xb2, 0xa7, 0xce, 0xcb, 0x73, 0xb2,
- 0xec, 0x09, 0xdb, 0x9d, 0xe4, 0x35, 0xea, 0x0b, 0xf6, 0x84, 0x8a, 0x4e, 0x71, 0x97, 0x21, 0x43,
- 0x99, 0x8b, 0xf2, 0x9e, 0xf6, 0xcd, 0xf9, 0x57, 0x02, 0x1b, 0x81, 0x8d, 0xbb, 0xe5, 0xa1, 0xef,
- 0xd1, 0xdf, 0x2b, 0x68, 0x8c, 0xfb, 0x29, 0xef, 0x6e, 0x17, 0x58, 0xc9, 0x4e, 0xd2, 0xcb, 0x5e,
- 0xcb, 0xe8, 0x27, 0x1c, 0xe4, 0xbc, 0xb2, 0xa2, 0xf5, 0x93, 0x2f, 0x78, 0x2e, 0x05, 0x6f, 0x2c,
- 0xc8, 0xd8, 0xd8, 0x4c, 0xbb, 0x6f, 0x25, 0x50, 0x1e, 0x6a, 0x40, 0xc3, 0x14, 0x6e, 0x08, 0x7d,
- 0x7f, 0x77, 0xdc, 0x4f, 0x0e, 0x68, 0x89, 0xd4, 0x79, 0x1e, 0x8b, 0x6c, 0x99, 0x6b, 0xdc, 0xdf,
- 0x10, 0xea, 0x0d, 0x4f, 0x44, 0x26, 0x22, 0xf3, 0xdc, 0x98, 0xe0, 0x46, 0x6f, 0xd8, 0x14, 0x2e,
- 0x0f, 0xd9, 0x7c, 0x23, 0xa3, 0x20, 0xf7, 0x07, 0xb2, 0xec, 0x54, 0x4b, 0x64, 0x8c, 0x39, 0x24,
- 0x7a, 0xd8, 0xf3, 0x46, 0xb2, 0x5c, 0xca, 0x65, 0x6d, 0xee, 0x39, 0xbf, 0x29, 0x0c, 0xac, 0xac,
- 0x3e, 0xe4, 0xc7, 0x7c, 0xa4, 0x3c, 0x74, 0xc1, 0x9a, 0xea, 0x5b, 0xee, 0x27, 0xc3, 0xf6, 0x8d,
- 0xc0, 0x04, 0x7a, 0x6d, 0x2a, 0xc0, 0xff, 0x34, 0x85, 0xdb, 0x7d, 0x6b, 0xc6, 0xec, 0x0c, 0x39,
- 0xc9, 0x56, 0x0b, 0x21, 0x5a, 0xb2, 0x79, 0x83, 0xe7, 0x92, 0x5f, 0x2f, 0x69, 0xa4, 0x2f, 0x57,
- 0x10, 0x33, 0xa9, 0x78, 0xb1, 0xf9, 0x52, 0x79, 0x14, 0x94, 0x3a, 0x9b, 0x2f, 0x35, 0x8f, 0x02,
- 0x7a, 0xc3, 0xcb, 0x9e, 0xec, 0x31, 0x35, 0x5a, 0xd2, 0x6d, 0x11, 0x77, 0x25, 0xf9, 0x23, 0x91,
- 0xcb, 0x0e, 0xa2, 0xcc, 0x35, 0x1f, 0x65, 0x72, 0x23, 0x30, 0xe7, 0xef, 0x0d, 0xc7, 0x72, 0x32,
- 0x9d, 0x24, 0x99, 0x1d, 0xc4, 0x0d, 0x7b, 0x3c, 0xf3, 0xe5, 0xa1, 0x88, 0x67, 0x76, 0x86, 0xf2,
- 0x36, 0x84, 0x62, 0xaf, 0x9a, 0xc2, 0xd3, 0xd6, 0xec, 0xb3, 0xe9, 0xb6, 0x36, 0xeb, 0xc5, 0xc8,
- 0x57, 0xbe, 0x48, 0xe4, 0xd2, 0x49, 0x8e, 0xfb, 0xb1, 0x24, 0x85, 0xed, 0x21, 0x76, 0x52, 0xdd,
- 0xa5, 0x5f, 0x77, 0x08, 0x5c, 0xd9, 0x7c, 0x89, 0xd2, 0x25, 0x97, 0x2d, 0x7b, 0x62, 0x19, 0x3b,
- 0x39, 0x0c, 0xa7, 0xf1, 0xa0, 0x8a, 0x93, 0x52, 0x27, 0xfc, 0x56, 0x80, 0xae, 0xb5, 0xf9, 0xe8,
- 0xac, 0xb3, 0x11, 0xb9, 0x2c, 0x04, 0x89, 0xfb, 0xcb, 0x05, 0x0a, 0x24, 0x71, 0xf5, 0xe1, 0x05,
- 0x2b, 0xaf, 0xe9, 0xfa, 0xc9, 0x1b, 0x76, 0x9e, 0x93, 0xf9, 0x48, 0x62, 0x26, 0xc9, 0xa4, 0x7a,
- 0x23, 0xc0, 0xf3, 0x35, 0x1f, 0x39, 0x39, 0x8c, 0xf3, 0xbf, 0x76, 0xc8, 0x7c, 0xf6, 0x9d, 0xe6,
- 0x26, 0xd5, 0x4d, 0x87, 0xa0, 0x7d, 0x27, 0x22, 0xe9, 0x7d, 0x4b, 0x3c, 0x44, 0x1d, 0x5b, 0x08,
- 0x12, 0xb9, 0x0c, 0x52, 0xc0, 0xdb, 0xec, 0x0c, 0x3c, 0x3e, 0x4b, 0x4e, 0x5b, 0x47, 0x46, 0xbb,
- 0x0c, 0x1d, 0x44, 0x9b, 0x9b, 0x97, 0x2e, 0x9e, 0x4b, 0x3e, 0xcf, 0x6e, 0x91, 0x15, 0xb4, 0x70,
- 0xc4, 0xc3, 0x4b, 0xf7, 0x41, 0x55, 0x99, 0xab, 0xc7, 0xed, 0xb3, 0x97, 0xc8, 0xda, 0x7d, 0x82,
- 0xd4, 0x8e, 0x8c, 0x66, 0x9e, 0x4b, 0xbf, 0x68, 0xfb, 0x14, 0x04, 0xcc, 0x65, 0xe9, 0xe6, 0xe9,
- 0x03, 0xcc, 0x65, 0xd8, 0x0e, 0xeb, 0xa2, 0x93, 0x1c, 0x19, 0xed, 0x71, 0x6b, 0xdc, 0x83, 0xea,
- 0x49, 0xf5, 0x6a, 0x0c, 0x97, 0x50, 0x19, 0xc4, 0xa5, 0xf6, 0xb2, 0x3b, 0x64, 0xe0, 0x0d, 0x9a,
- 0xd8, 0x94, 0xd9, 0xb0, 0x9d, 0xbf, 0x6b, 0x07, 0xc1, 0x98, 0x8f, 0xb8, 0xdb, 0xdc, 0x21, 0x76,
- 0xc9, 0x28, 0x70, 0xb9, 0xec, 0xc9, 0x3c, 0x97, 0x20, 0xc5, 0x58, 0xc4, 0x3d, 0x49, 0xfe, 0x48,
- 0xc5, 0xe5, 0xea, 0xc3, 0x6e, 0x0b, 0x7e, 0xee, 0xba, 0x11, 0x7c, 0x3f, 0xad, 0x96, 0xfe, 0xe8,
- 0x2a, 0x8a, 0xb9, 0x84, 0xe8, 0x07, 0x63, 0x86, 0xb3, 0x22, 0x50, 0x3b, 0x8d, 0xd7, 0xbf, 0xa6,
- 0x70, 0x6c, 0x6e, 0xc2, 0x02, 0xe5, 0xb3, 0x6b, 0x5c, 0x9f, 0x1a, 0x16, 0x28, 0x41, 0x07, 0xb7,
- 0xfb, 0x32, 0xcf, 0x45, 0x2e, 0x13, 0x33, 0xb8, 0x0a, 0x01, 0x17, 0x27, 0x61, 0x4b, 0xcd, 0x7c,
- 0xcc, 0x2b, 0x48, 0xc1, 0x4e, 0xb1, 0xd5, 0x82, 0x1f, 0x39, 0x49, 0x9f, 0xbd, 0xc7, 0x7d, 0x69,
- 0xd4, 0x49, 0x6a, 0x5c, 0xb1, 0x72, 0xb9, 0x43, 0x76, 0x97, 0xed, 0xd2, 0x5f, 0x37, 0x76, 0xe9,
- 0x0f, 0xe9, 0x79, 0xb9, 0x2c, 0x0f, 0xc5, 0xc7, 0xb5, 0x4a, 0x64, 0xcd, 0x7a, 0xf0, 0xfc, 0x95,
- 0xb9, 0x04, 0xcb, 0x29, 0xf3, 0x5c, 0x3a, 0xd5, 0x6b, 0x62, 0xce, 0x73, 0x01, 0xc0, 0xf1, 0xcb,
- 0x52, 0x33, 0xbf, 0x0e, 0x2e, 0x50, 0x26, 0xb4, 0xfe, 0x75, 0x5b, 0xf8, 0xe7, 0x9b, 0xf5, 0x6d,
- 0xee, 0x9b, 0x0e, 0xd0, 0xb6, 0xf1, 0xb6, 0x0f, 0xae, 0xe7, 0x74, 0x96, 0x5c, 0x64, 0xf9, 0xbd,
- 0xc7, 0x46, 0x20, 0xf1, 0x0c, 0x03, 0xcd, 0xfd, 0x99, 0xb6, 0xe6, 0xca, 0xe5, 0xa0, 0x7a, 0x4d,
- 0x8c, 0x46, 0x17, 0x00, 0x9c, 0x57, 0x00, 0xba, 0x0d, 0x3f, 0xc6, 0x7b, 0x12, 0xf0, 0xd7, 0xe1,
- 0xc7, 0x4d, 0xaa, 0xc3, 0xc3, 0xe4, 0x40, 0x7f, 0x94, 0xcb, 0x58, 0xd9, 0xa3, 0xb9, 0x9f, 0x41,
- 0x8a, 0xb7, 0x8b, 0xca, 0x43, 0xa9, 0xec, 0x54, 0x5a, 0xd2, 0x6a, 0xe1, 0xb9, 0xac, 0xf3, 0x66,
- 0x9e, 0x0b, 0xe4, 0x1d, 0x89, 0x5c, 0xe6, 0x8f, 0xe8, 0x19, 0x2f, 0x63, 0x48, 0x8b, 0x1f, 0x77,
- 0x10, 0x37, 0x1d, 0x0f, 0x1f, 0xf6, 0xb8, 0x05, 0x9f, 0x5e, 0xa7, 0xea, 0xa0, 0x4a, 0x4b, 0xac,
- 0x3b, 0x56, 0x23, 0x7d, 0xab, 0x9f, 0x9f, 0xe9, 0xfe, 0xd9, 0xae, 0x7d, 0x17, 0xf7, 0xed, 0x61,
- 0xea, 0x98, 0x76, 0x34, 0x66, 0xf6, 0x5d, 0xd8, 0xfb, 0xa7, 0xa3, 0xc7, 0x96, 0xff, 0x25, 0x0c,
- 0x5c, 0xa6, 0xca, 0x7c, 0xa7, 0x25, 0x61, 0x3b, 0xcf, 0x65, 0x9b, 0x3b, 0xf3, 0x5c, 0xa0, 0x5a,
- 0x8c, 0xa8, 0x63, 0xf3, 0x87, 0x70, 0x9a, 0x84, 0xbf, 0xd2, 0xa5, 0x5f, 0x45, 0xbc, 0xc4, 0xe7,
- 0xe5, 0xd1, 0x92, 0xd7, 0x3e, 0x6e, 0x18, 0xab, 0x6f, 0x7c, 0xa0, 0x38, 0x26, 0xed, 0x8b, 0x1b,
- 0x26, 0xe9, 0x03, 0xc5, 0xd1, 0x9a, 0xef, 0xbb, 0xff, 0x6f, 0xb6, 0x7c, 0x35, 0x55, 0x5e, 0x66,
- 0x07, 0x31, 0x3b, 0xc3, 0x73, 0x49, 0x0e, 0x64, 0x9e, 0x0b, 0xb6, 0x7d, 0x44, 0x2e, 0xf3, 0x05,
- 0x9f, 0x1f, 0x2b, 0x70, 0x17, 0xe2, 0x76, 0x8c, 0x23, 0xa3, 0xb1, 0xbb, 0xbc, 0xf7, 0x77, 0x7d,
- 0x77, 0xe4, 0x8c, 0xa2, 0x11, 0x31, 0xd7, 0x27, 0x9d, 0x78, 0x16, 0x8f, 0x3e, 0xe9, 0x6d, 0x45,
- 0xbd, 0xe2, 0xa8, 0xe2, 0x41, 0xc5, 0x04, 0xba, 0x7a, 0x47, 0xf1, 0x46, 0xdf, 0xff, 0xa4, 0xc8,
- 0xcb, 0x14, 0xf6, 0x2c, 0xc2, 0xde, 0x34, 0x1d, 0x20, 0x62, 0x1d, 0xe2, 0x2a, 0x8b, 0x14, 0xeb,
- 0xd3, 0x6d, 0x2f, 0xe0, 0x13, 0x7b, 0xb1, 0x5c, 0x36, 0xa9, 0x28, 0x2f, 0xec, 0x30, 0x96, 0x8c,
- 0xf8, 0xb1, 0x56, 0xf2, 0x5f, 0xcf, 0xd5, 0x31, 0x67, 0x14, 0xb7, 0x18, 0x1b, 0x33, 0xc7, 0x54,
- 0x54, 0xf2, 0x5c, 0x1e, 0x93, 0xde, 0x62, 0xde, 0xad, 0x7d, 0xb7, 0x96, 0x65, 0x10, 0x9b, 0xe8,
- 0xb1, 0x49, 0x7a, 0x4f, 0x5e, 0xfd, 0x93, 0x78, 0x3a, 0x4b, 0x62, 0x3c, 0x7c, 0x13, 0x91, 0x6c,
- 0xf2, 0xa6, 0x25, 0x5a, 0x2d, 0xe2, 0x79, 0xaf, 0xfc, 0x81, 0xec, 0x51, 0xee, 0x7c, 0xbb, 0xa0,
- 0x1f, 0x79, 0xcb, 0x73, 0x23, 0x00, 0x76, 0xce, 0x3f, 0x12, 0xbf, 0xde, 0xfb, 0x1e, 0x73, 0x55,
- 0x71, 0x46, 0xf1, 0x5a, 0xed, 0x6b, 0xb5, 0xb7, 0x98, 0x63, 0x9c, 0x5c, 0xce, 0x4b, 0xe7, 0xa5,
- 0x13, 0xd2, 0x0a, 0xc4, 0xe6, 0x87, 0xb5, 0x1f, 0xd6, 0x1e, 0x55, 0x4c, 0x48, 0xb1, 0xa4, 0xae,
- 0x54, 0x8c, 0x95, 0xff, 0xd3, 0xde, 0xe8, 0xd2, 0x2b, 0x59, 0x64, 0xc7, 0x66, 0x04, 0x1f, 0x5e,
- 0x9b, 0x9b, 0xce, 0x3a, 0x9b, 0x56, 0x4b, 0x97, 0xbe, 0x49, 0xcc, 0x12, 0xc9, 0x13, 0xfc, 0x79,
- 0x92, 0x2e, 0xbd, 0x20, 0x35, 0x4b, 0x46, 0xec, 0x97, 0xb3, 0xf9, 0x86, 0x75, 0xb5, 0xd5, 0x73,
- 0x88, 0xc9, 0x3e, 0xc4, 0x9b, 0x8d, 0x39, 0xaa, 0xe8, 0xe3, 0x99, 0xac, 0x9c, 0x7f, 0x11, 0xfd,
- 0x41, 0x7c, 0x36, 0x4a, 0xaf, 0x2a, 0x2a, 0xa4, 0x13, 0x9b, 0x9a, 0x77, 0x02, 0xe9, 0xe1, 0x2b,
- 0x15, 0xff, 0x2e, 0xff, 0xbc, 0xfe, 0xa7, 0x17, 0xbf, 0x0f, 0xfc, 0x7e, 0xd3, 0xb7, 0x6e, 0x0a,
- 0xa7, 0xcb, 0xda, 0x8c, 0xc5, 0x12, 0x97, 0xf1, 0x23, 0x5a, 0xb2, 0xf9, 0x21, 0xd5, 0xd9, 0x20,
- 0x5a, 0x72, 0x72, 0x18, 0xe2, 0xcf, 0x1f, 0xcf, 0xd7, 0x35, 0xdc, 0x62, 0x6e, 0x2b, 0x84, 0x35,
- 0x12, 0x0f, 0xc4, 0xe5, 0x8b, 0x51, 0x2e, 0x9f, 0x4d, 0x3b, 0x10, 0xcb, 0x47, 0x6b, 0xae, 0x74,
- 0xff, 0xfd, 0x8d, 0x63, 0xab, 0xab, 0x11, 0x53, 0xb8, 0xd5, 0x92, 0x8b, 0x45, 0x03, 0x9e, 0x61,
- 0xd1, 0x92, 0xcd, 0x17, 0x3c, 0x97, 0x53, 0x71, 0x27, 0xdc, 0x95, 0x3a, 0xd6, 0xdb, 0x30, 0x4d,
- 0x69, 0xee, 0x23, 0x26, 0x8f, 0xc5, 0x4a, 0x5d, 0x76, 0x2e, 0xa5, 0xa0, 0x7f, 0xe7, 0xa3, 0xff,
- 0x9e, 0x40, 0x56, 0xae, 0xbd, 0xb1, 0x77, 0xec, 0x37, 0x67, 0x82, 0x39, 0x9d, 0x08, 0x6c, 0x52,
- 0x89, 0x59, 0x22, 0xf9, 0x03, 0x9f, 0xbf, 0x84, 0x3e, 0x15, 0xb1, 0xe7, 0x2f, 0xcd, 0x92, 0xcf,
- 0x5e, 0xad, 0x6b, 0x78, 0xbe, 0x86, 0x63, 0x32, 0x99, 0xad, 0x4a, 0x8e, 0xcb, 0x64, 0x8e, 0xb9,
- 0x75, 0x74, 0x73, 0x6c, 0xbe, 0xbe, 0x42, 0xfa, 0x9a, 0x7c, 0x6d, 0x97, 0x36, 0xfd, 0x24, 0x36,
- 0xd1, 0x4f, 0x76, 0x8b, 0xd6, 0x4f, 0x01, 0xe0, 0xb9, 0x14, 0x24, 0xc7, 0x2c, 0x79, 0x71, 0x6f,
- 0xa4, 0xfa, 0x3e, 0x73, 0x07, 0xb4, 0x6b, 0x12, 0x97, 0x88, 0x31, 0x9e, 0xcb, 0x54, 0x4c, 0x56,
- 0x46, 0x87, 0x34, 0xf6, 0xf9, 0x63, 0xd2, 0xbd, 0x8a, 0xbf, 0xdd, 0x9b, 0x7d, 0x2e, 0x5a, 0x82,
- 0x31, 0x8b, 0xd6, 0x4f, 0xfe, 0x80, 0x8a, 0x30, 0xcd, 0x7a, 0x21, 0xb3, 0xe0, 0xb8, 0xe4, 0xd7,
- 0x3f, 0xa3, 0x98, 0x0d, 0xce, 0xe2, 0x49, 0x66, 0x32, 0x9d, 0x86, 0x9d, 0xe7, 0x2d, 0xa2, 0x17,
- 0xf9, 0x67, 0xe3, 0x9f, 0xef, 0x93, 0xfe, 0x8e, 0xc9, 0x2e, 0x99, 0x50, 0x53, 0x64, 0x4a, 0xcc,
- 0x91, 0xcd, 0x1b, 0xf1, 0xf5, 0x0a, 0x64, 0x92, 0xff, 0x7e, 0x8e, 0xd2, 0xdc, 0x62, 0xae, 0xd6,
- 0x98, 0xd2, 0x58, 0x36, 0x9b, 0x36, 0x6c, 0x22, 0xc3, 0x02, 0x93, 0x71, 0x5c, 0x9a, 0xa4, 0xdc,
- 0x9d, 0xa4, 0xb7, 0x15, 0x4b, 0xbb, 0xb2, 0xcf, 0x66, 0x91, 0x65, 0x44, 0xdf, 0x4f, 0xde, 0xc0,
- 0x51, 0xaf, 0xa5, 0xe8, 0xe9, 0xa0, 0x01, 0xe2, 0x72, 0xf5, 0x38, 0x73, 0xb4, 0xa6, 0xa2, 0x32,
- 0x95, 0x4c, 0x46, 0x39, 0xab, 0x8c, 0x5f, 0x2b, 0xe7, 0xf9, 0xab, 0x71, 0x4c, 0xe2, 0xf5, 0xd2,
- 0x58, 0x51, 0x56, 0xdd, 0xb3, 0xaf, 0x0f, 0xfd, 0xeb, 0x81, 0xe2, 0xef, 0x72, 0xd0, 0xb2, 0x41,
- 0xaa, 0x55, 0xcc, 0x13, 0xc9, 0x1b, 0x38, 0x52, 0xb2, 0x64, 0xc4, 0x11, 0x90, 0xae, 0x5d, 0xf7,
- 0xaa, 0x91, 0x54, 0xa6, 0xb2, 0x79, 0xe2, 0xb9, 0x4c, 0xbe, 0x96, 0x24, 0x93, 0xb7, 0x2b, 0xfe,
- 0x28, 0xff, 0x56, 0x65, 0xa8, 0xfa, 0x9d, 0x1c, 0xb4, 0xf5, 0x55, 0xc5, 0xbf, 0x3d, 0x97, 0x7d,
- 0x36, 0x70, 0x8e, 0x48, 0x5c, 0x31, 0xf3, 0x05, 0xf4, 0x0e, 0x99, 0xe4, 0xa2, 0x4d, 0xf0, 0xe8,
- 0xaf, 0xf7, 0xb2, 0xcc, 0xf3, 0x35, 0x0f, 0x92, 0xf6, 0x94, 0xf1, 0x96, 0x6a, 0x02, 0x93, 0x89,
- 0x2b, 0x25, 0x77, 0xdd, 0x8e, 0x24, 0xf2, 0x5b, 0xd5, 0xcb, 0xd5, 0xf7, 0xe5, 0xd8, 0x9a, 0x3d,
- 0x53, 0x73, 0x37, 0x07, 0x59, 0xeb, 0x20, 0xa0, 0xdf, 0x14, 0x54, 0xae, 0xa4, 0x1f, 0xf1, 0xe7,
- 0x7e, 0x1a, 0x41, 0x4b, 0xf0, 0x29, 0x77, 0xec, 0xf9, 0xfe, 0x2b, 0xc4, 0x65, 0x7d, 0x26, 0x0d,
- 0x1b, 0xbb, 0xdb, 0x48, 0xb4, 0x79, 0x84, 0x55, 0x52, 0x5a, 0xaf, 0x18, 0xa9, 0xfa, 0x56, 0xf5,
- 0x9e, 0xfc, 0x4e, 0x05, 0x6f, 0xfb, 0xdc, 0xcf, 0xc1, 0xf6, 0x01, 0x4c, 0xaa, 0xc5, 0x3d, 0x66,
- 0xbe, 0x80, 0xa8, 0x17, 0xae, 0x95, 0x04, 0x8f, 0x9a, 0x77, 0x51, 0x9c, 0x5c, 0xa6, 0xe1, 0xf2,
- 0xd9, 0xf9, 0x64, 0x76, 0x2b, 0x13, 0x25, 0xb2, 0x4f, 0x5a, 0x56, 0xad, 0xae, 0xfa, 0xac, 0x6a,
- 0x6f, 0x8c, 0x74, 0x37, 0x56, 0xb6, 0x33, 0x74, 0x4e, 0xf3, 0x81, 0xc8, 0x57, 0xb3, 0x5e, 0x2e,
- 0x56, 0x2e, 0xc8, 0x03, 0x98, 0xcb, 0xb5, 0x68, 0x3d, 0xbc, 0xe3, 0x92, 0x0f, 0xab, 0xe7, 0x98,
- 0x33, 0x69, 0xac, 0xd8, 0x04, 0x26, 0x05, 0xed, 0xba, 0x29, 0x91, 0x8d, 0x52, 0xa3, 0x42, 0x5d,
- 0xb5, 0xbf, 0x2a, 0xb2, 0x2f, 0xf6, 0x95, 0x7d, 0xd2, 0x33, 0x8a, 0x7f, 0x4e, 0xb0, 0x7c, 0xfa,
- 0xc9, 0x2e, 0xfd, 0x4e, 0x73, 0xf2, 0xc9, 0x79, 0xa8, 0x42, 0x21, 0xe6, 0x17, 0xe4, 0x07, 0xa1,
- 0x2a, 0x0c, 0x68, 0x35, 0x99, 0xe4, 0xc5, 0xbd, 0xf7, 0x6a, 0x29, 0x0d, 0x92, 0xcd, 0x8a, 0xd4,
- 0xb2, 0x99, 0xb4, 0x52, 0x56, 0xf2, 0x12, 0xd9, 0x28, 0xfd, 0x45, 0x85, 0xa6, 0x7a, 0x57, 0x95,
- 0xa6, 0xfa, 0x0d, 0x45, 0x3c, 0x93, 0x77, 0x14, 0x36, 0xcd, 0x7f, 0x26, 0x70, 0x06, 0xb5, 0x46,
- 0x7d, 0xf6, 0x69, 0xab, 0x52, 0x77, 0x2d, 0x61, 0x6d, 0x84, 0x9c, 0x15, 0x42, 0x27, 0x6a, 0xd9,
- 0xad, 0x43, 0xa8, 0xd6, 0x84, 0xf7, 0x01, 0x5f, 0x10, 0xa7, 0x6a, 0xef, 0xd5, 0x5e, 0xae, 0xa5,
- 0x18, 0x7b, 0x1a, 0x4d, 0x1b, 0x6f, 0x07, 0x61, 0x89, 0x3c, 0x26, 0xfd, 0x48, 0x3e, 0xbb, 0x6f,
- 0xd7, 0x7e, 0x4d, 0xf5, 0xeb, 0xf2, 0xbe, 0x04, 0x2f, 0xc1, 0x03, 0xc5, 0x2d, 0xe6, 0xa7, 0x47,
- 0xfe, 0x35, 0x21, 0x1b, 0x28, 0x48, 0xb5, 0x20, 0x2e, 0x81, 0x4d, 0x86, 0xeb, 0x54, 0x22, 0x30,
- 0x57, 0x22, 0x83, 0x1e, 0x8b, 0xe2, 0x69, 0xf7, 0x7c, 0xc0, 0xd5, 0x8f, 0xd5, 0x37, 0xeb, 0xb1,
- 0x77, 0x7d, 0x81, 0xfc, 0x9b, 0x57, 0xfd, 0xf5, 0x94, 0xe6, 0x72, 0xed, 0x87, 0xb5, 0xb7, 0xe4,
- 0xb7, 0x2b, 0xb2, 0x49, 0xe6, 0xc4, 0xb3, 0x15, 0xd2, 0xf7, 0xe4, 0x63, 0xfb, 0xfe, 0xa4, 0x5a,
- 0x47, 0xbb, 0x8f, 0xef, 0x63, 0x5f, 0x1f, 0x8d, 0x89, 0xcd, 0x31, 0xef, 0x1e, 0xf9, 0x7c, 0x38,
- 0xf1, 0x6c, 0xd0, 0x59, 0xf2, 0x53, 0xc3, 0xb4, 0x15, 0xd8, 0x04, 0x3e, 0x5b, 0x2c, 0xcf, 0xe8,
- 0x78, 0x36, 0xb5, 0x04, 0xf4, 0x40, 0x15, 0xe3, 0x25, 0xf9, 0x00, 0x57, 0x37, 0xec, 0xd2, 0xe3,
- 0xce, 0x24, 0x41, 0xea, 0x86, 0x7d, 0xf7, 0x5b, 0x91, 0xfa, 0xe7, 0x34, 0x2c, 0xf3, 0x4e, 0xed,
- 0x72, 0xf5, 0x51, 0x45, 0x5f, 0x06, 0x36, 0x1d, 0x15, 0x6d, 0xd5, 0x37, 0xab, 0x76, 0x55, 0xfd,
- 0x66, 0xbf, 0xb1, 0x22, 0x8e, 0x77, 0x69, 0x9f, 0xb4, 0xa2, 0xf2, 0xaa, 0xe2, 0xf9, 0x9a, 0x76,
- 0xcd, 0xe5, 0xb7, 0xde, 0x75, 0x41, 0x96, 0x6d, 0x62, 0xf5, 0x44, 0x2f, 0xcb, 0x73, 0x09, 0xa3,
- 0xdb, 0x72, 0x6e, 0x33, 0xc2, 0x09, 0xb6, 0x2c, 0x21, 0xfa, 0xd8, 0xf3, 0x00, 0xe6, 0x72, 0xc8,
- 0xe0, 0x8c, 0x9e, 0xeb, 0x79, 0x69, 0xe0, 0xb3, 0xd1, 0x23, 0xa7, 0x96, 0xeb, 0xdb, 0x35, 0xed,
- 0xcc, 0xbb, 0xd5, 0x6d, 0xb5, 0xef, 0x54, 0x2f, 0x57, 0xe3, 0x9c, 0xad, 0x89, 0xe8, 0x80, 0x7f,
- 0x97, 0x57, 0x8e, 0x55, 0xbf, 0x5d, 0x75, 0xb8, 0x4a, 0x5d, 0xd5, 0x53, 0xfd, 0xdb, 0x8a, 0xc6,
- 0x58, 0xbd, 0x2a, 0x3d, 0xc6, 0x65, 0x74, 0xcd, 0x31, 0x75, 0x9a, 0xf7, 0x4e, 0x7c, 0x37, 0xc3,
- 0x7a, 0xeb, 0xbc, 0x11, 0x4f, 0x9b, 0x7b, 0xcd, 0x18, 0xff, 0xbe, 0x41, 0x6a, 0xa7, 0x59, 0xe0,
- 0xd2, 0x67, 0x6f, 0xb1, 0x74, 0x6c, 0x4a, 0x26, 0xf4, 0xf9, 0x13, 0x3b, 0x97, 0x6c, 0x1d, 0xf1,
- 0x5c, 0x96, 0xc8, 0x0e, 0x0f, 0x6b, 0x5c, 0x1a, 0x97, 0x75, 0x60, 0x16, 0xc9, 0xe6, 0x2d, 0xe6,
- 0x68, 0x0d, 0xc5, 0xbc, 0x53, 0xdd, 0x53, 0xfd, 0x72, 0xed, 0x9f, 0xf7, 0xff, 0x79, 0xff, 0xcb,
- 0xb5, 0x3d, 0xb5, 0x9f, 0xed, 0x37, 0xec, 0x7f, 0xbb, 0x6a, 0xa4, 0xea, 0x12, 0x62, 0xb1, 0x3e,
- 0x7e, 0x4d, 0x95, 0x42, 0x5e, 0xc1, 0x6d, 0x24, 0x8d, 0x1f, 0x69, 0x5e, 0x6f, 0xa9, 0x3b, 0x0f,
- 0x15, 0x0c, 0xae, 0xa0, 0x31, 0xe7, 0xb7, 0xf9, 0xf6, 0x78, 0x0f, 0x0f, 0xd3, 0x09, 0xef, 0xec,
- 0x65, 0xcf, 0xc7, 0x48, 0xe6, 0xb4, 0xd5, 0xbb, 0x79, 0x56, 0x37, 0xba, 0xcb, 0xa4, 0x45, 0xc9,
- 0xdc, 0x0a, 0xf8, 0x8e, 0x16, 0x02, 0x97, 0x27, 0x87, 0x7b, 0x66, 0xc6, 0x66, 0x34, 0x6e, 0xeb,
- 0x80, 0xff, 0x15, 0x4a, 0x33, 0x87, 0xd8, 0x7c, 0xa0, 0x30, 0x49, 0x1d, 0x8a, 0x8f, 0x98, 0x3d,
- 0x8c, 0xbf, 0x1a, 0x46, 0x1d, 0xf3, 0x0b, 0x45, 0x63, 0x62, 0x14, 0x05, 0xc9, 0x6a, 0x23, 0xb2,
- 0x58, 0x8f, 0xd6, 0x8c, 0x33, 0xef, 0x1d, 0x61, 0xcf, 0x9d, 0xf6, 0x41, 0x1d, 0x8a, 0xf2, 0x10,
- 0x1e, 0x2b, 0x01, 0x9b, 0x4f, 0xe3, 0x4a, 0xcc, 0x13, 0x01, 0x2f, 0x8f, 0xa0, 0x67, 0xa7, 0xad,
- 0x2f, 0x6c, 0xa6, 0x7e, 0x89, 0x92, 0x99, 0x0f, 0xf8, 0x3d, 0x09, 0x6f, 0xc7, 0x22, 0x2e, 0x47,
- 0x67, 0x67, 0x22, 0x5f, 0xcc, 0xce, 0x80, 0x6c, 0x7e, 0xf5, 0xca, 0xbd, 0x5a, 0xcc, 0x66, 0xea,
- 0x08, 0x58, 0x2c, 0x8f, 0x0f, 0x14, 0x6f, 0xd4, 0xdc, 0x62, 0x58, 0xcd, 0x77, 0xa7, 0xbe, 0x9b,
- 0xc1, 0x95, 0x2b, 0x4c, 0xe1, 0xde, 0xe8, 0x30, 0x85, 0x37, 0x02, 0x94, 0xb7, 0xd5, 0x92, 0xf8,
- 0xee, 0x4e, 0x52, 0x60, 0xf3, 0xbc, 0xf5, 0x60, 0x8c, 0xad, 0x0b, 0x3b, 0x93, 0x90, 0xd8, 0xbb,
- 0x6d, 0x4b, 0xe0, 0x4f, 0x21, 0xf0, 0xdd, 0x49, 0x4a, 0x64, 0x23, 0xa3, 0x11, 0x0f, 0x54, 0x82,
- 0x99, 0x9d, 0x29, 0x73, 0x59, 0x87, 0xbf, 0x7a, 0xf5, 0x5e, 0xed, 0x38, 0xc7, 0x66, 0x72, 0xb6,
- 0x08, 0xd6, 0xaa, 0x98, 0xc7, 0x33, 0x35, 0xf7, 0x99, 0x76, 0x24, 0x91, 0xed, 0x17, 0xc7, 0x7d,
- 0x1b, 0x01, 0xcc, 0x23, 0x5f, 0xbf, 0x62, 0x9e, 0xab, 0x40, 0x31, 0xe7, 0xbf, 0x34, 0x9a, 0xdc,
- 0x37, 0xe3, 0x2c, 0xf9, 0x8c, 0xae, 0xdb, 0x32, 0x6d, 0x3d, 0x6f, 0x7d, 0x33, 0xae, 0xfe, 0x4f,
- 0x3f, 0xc9, 0x77, 0xfb, 0xa2, 0x1f, 0xd3, 0x37, 0xf1, 0x63, 0x07, 0xce, 0x11, 0x51, 0xea, 0x98,
- 0xcd, 0x93, 0x5e, 0x25, 0xb2, 0x4b, 0xa3, 0x94, 0x77, 0xdc, 0x0f, 0x95, 0x79, 0xc6, 0x10, 0x9b,
- 0x6f, 0x0f, 0x7f, 0xfe, 0x2a, 0x96, 0xcd, 0xdb, 0x8a, 0xc6, 0x4a, 0xc1, 0xfe, 0x01, 0x0e, 0x8f,
- 0x21, 0x16, 0x2b, 0x2a, 0xef, 0x20, 0x1e, 0x9f, 0xaf, 0xb1, 0x31, 0x54, 0xc3, 0x7f, 0x9c, 0x7a,
- 0x6e, 0xfe, 0x8a, 0xbf, 0x3c, 0xca, 0xa3, 0x90, 0x4f, 0x89, 0x73, 0x9d, 0x4d, 0xe1, 0x7b, 0x5f,
- 0x4c, 0x19, 0x92, 0xe7, 0x70, 0x80, 0x08, 0x52, 0xe7, 0xd4, 0x07, 0x55, 0xf1, 0x71, 0x2e, 0x3a,
- 0x2a, 0x99, 0xa2, 0x35, 0x9b, 0x2b, 0x70, 0x57, 0xb6, 0x25, 0xe3, 0x9a, 0x91, 0xef, 0x95, 0x88,
- 0xb8, 0x74, 0xd4, 0x79, 0x61, 0xad, 0x3b, 0xed, 0xc3, 0x6c, 0x8e, 0x8c, 0xfe, 0xe1, 0xe8, 0xbd,
- 0x5a, 0x1b, 0xb3, 0xc1, 0x9c, 0xa9, 0xb9, 0xaa, 0xb8, 0x83, 0xc6, 0x03, 0x34, 0xee, 0x28, 0x6e,
- 0x2b, 0x1c, 0x88, 0xc5, 0xfa, 0x1a, 0xc8, 0x82, 0xa6, 0x34, 0x7b, 0x8e, 0xfc, 0xd1, 0x7d, 0x9a,
- 0xab, 0x0a, 0xc4, 0xd5, 0x93, 0x79, 0x98, 0x0c, 0x38, 0xdb, 0x70, 0x69, 0x34, 0xf7, 0x1a, 0xfd,
- 0xd0, 0xf1, 0x74, 0x48, 0xec, 0xf6, 0x95, 0x23, 0x84, 0x5e, 0x89, 0x42, 0xde, 0x7a, 0x89, 0x6c,
- 0xdd, 0x61, 0xf3, 0x95, 0x87, 0x1a, 0xd1, 0x0a, 0x67, 0xdb, 0x64, 0x73, 0xdd, 0xbc, 0x5c, 0x4f,
- 0x69, 0x20, 0x73, 0xfd, 0x16, 0x1a, 0xf7, 0xb9, 0x9f, 0xb7, 0xd0, 0x23, 0x1b, 0x5a, 0x1f, 0xa9,
- 0x86, 0x3d, 0x2d, 0x3f, 0x3f, 0x6f, 0x43, 0x36, 0x2b, 0xe8, 0xd6, 0xde, 0xf0, 0x7c, 0x9a, 0x5a,
- 0x3f, 0x70, 0xe6, 0xef, 0xb4, 0x7f, 0xc9, 0x98, 0x7b, 0xed, 0xd2, 0x4e, 0x75, 0xa9, 0x59, 0xec,
- 0xf6, 0x95, 0x1b, 0xa0, 0xaa, 0x33, 0xf4, 0x4a, 0x64, 0xcc, 0x42, 0xe6, 0x56, 0x89, 0x6c, 0xb7,
- 0x0b, 0xd7, 0x6a, 0x32, 0x85, 0x57, 0x02, 0xed, 0xbe, 0x88, 0xa7, 0x87, 0xab, 0x51, 0xb8, 0xfb,
- 0xd4, 0x1f, 0x5e, 0xfd, 0xea, 0x95, 0xff, 0xad, 0x8f, 0xd4, 0x47, 0x6a, 0x23, 0xb5, 0xf7, 0xd0,
- 0x40, 0xff, 0xaa, 0xff, 0xf9, 0x91, 0x5f, 0x9d, 0x88, 0x0c, 0xdf, 0xf3, 0xe4, 0xc2, 0x24, 0xa0,
- 0x37, 0xdc, 0xe3, 0xce, 0x5e, 0x83, 0x82, 0x47, 0x3f, 0x09, 0x7e, 0x76, 0xc8, 0x19, 0x11, 0xf5,
- 0x6c, 0x66, 0xe0, 0x0e, 0xd1, 0x84, 0x0e, 0xb2, 0x32, 0x84, 0xab, 0x50, 0x77, 0xab, 0x3c, 0x04,
- 0x8c, 0x4c, 0x44, 0x1a, 0x42, 0x73, 0x7e, 0x8e, 0x4d, 0x24, 0x9b, 0x5f, 0x3a, 0x46, 0x86, 0x0d,
- 0x03, 0x3f, 0x39, 0xb5, 0xfb, 0xad, 0xdd, 0x6f, 0x95, 0xbd, 0xa5, 0x39, 0xd5, 0x76, 0xaa, 0xe7,
- 0x8c, 0x7f, 0xe0, 0x57, 0xae, 0x88, 0xe7, 0x75, 0xdf, 0x69, 0x3f, 0xbf, 0x4a, 0xce, 0xa7, 0xac,
- 0xf2, 0x14, 0xab, 0x67, 0x37, 0x02, 0xa9, 0xeb, 0x77, 0xa5, 0x46, 0x13, 0xd7, 0xef, 0x54, 0xec,
- 0xf9, 0x9e, 0x0d, 0xb8, 0x43, 0xf4, 0x92, 0x91, 0x31, 0xc7, 0xe6, 0x39, 0x37, 0xa9, 0x96, 0x3d,
- 0x7c, 0x6d, 0x90, 0x8f, 0x23, 0xe5, 0xa1, 0x71, 0x3f, 0xd4, 0x36, 0xec, 0x71, 0x6b, 0x5c, 0xeb,
- 0x8e, 0x9b, 0x8e, 0x4b, 0xa3, 0x97, 0xd0, 0xcf, 0x75, 0x47, 0x99, 0xab, 0xcd, 0x3d, 0x36, 0xb3,
- 0xec, 0xa1, 0xbc, 0xed, 0xbe, 0x71, 0x7f, 0xa6, 0x55, 0x32, 0x59, 0xcf, 0x52, 0xde, 0x5c, 0xce,
- 0x23, 0x60, 0x68, 0x89, 0x66, 0xbd, 0x68, 0x01, 0x65, 0x03, 0xee, 0x10, 0xdd, 0xac, 0xef, 0xb6,
- 0xc4, 0xeb, 0x3c, 0xa8, 0xd8, 0xc3, 0x6b, 0x49, 0xb0, 0x3d, 0x37, 0x02, 0x98, 0xcd, 0xb1, 0x99,
- 0x36, 0xc4, 0x67, 0x19, 0x1a, 0x1a, 0x17, 0xd4, 0x88, 0x45, 0x7b, 0x50, 0x4f, 0x9d, 0xd7, 0x16,
- 0xc3, 0x64, 0x20, 0x03, 0x83, 0xb1, 0x30, 0x85, 0x2f, 0x65, 0xa9, 0x0e, 0x13, 0x8b, 0x7e, 0x92,
- 0x31, 0xf3, 0xfd, 0x4e, 0xe9, 0x22, 0x7f, 0x07, 0x4f, 0x07, 0x78, 0xfd, 0x0a, 0x56, 0x0f, 0x1d,
- 0x73, 0xbd, 0x9f, 0x8c, 0xad, 0x96, 0xf5, 0x90, 0xdb, 0x17, 0x62, 0x36, 0x23, 0x9e, 0x59, 0x0f,
- 0xae, 0xf2, 0x3b, 0x8b, 0xe4, 0x31, 0xc2, 0x49, 0x24, 0xae, 0x32, 0x8a, 0x99, 0x5c, 0x4d, 0xcb,
- 0x5d, 0x32, 0xe6, 0xfc, 0xb9, 0xaf, 0x99, 0x48, 0xeb, 0xab, 0xba, 0x2d, 0xcd, 0xa2, 0x9e, 0x4d,
- 0x03, 0x6c, 0xbf, 0x42, 0xff, 0x83, 0xc4, 0x5e, 0xb4, 0x4a, 0x9d, 0x29, 0x1c, 0xff, 0xbd, 0xc3,
- 0xaa, 0x09, 0x75, 0x60, 0xdb, 0x91, 0x4d, 0x1b, 0xf1, 0x44, 0x38, 0x16, 0xa1, 0xe2, 0x2f, 0x96,
- 0xc8, 0x8d, 0xbb, 0xd9, 0xed, 0x9d, 0x64, 0xcc, 0x47, 0xde, 0xde, 0x82, 0x64, 0xc2, 0x59, 0x6d,
- 0x88, 0x9b, 0x88, 0xf6, 0x6c, 0x32, 0xe8, 0x68, 0x95, 0x82, 0x29, 0x43, 0xa9, 0x39, 0x7e, 0xb7,
- 0x77, 0x50, 0x15, 0x5b, 0x27, 0x0b, 0x63, 0x15, 0xd9, 0x9e, 0xe5, 0x1c, 0x9b, 0x36, 0x5f, 0x9d,
- 0xaf, 0xce, 0x0b, 0x15, 0x82, 0x81, 0x47, 0x5e, 0x22, 0xb7, 0xce, 0x24, 0x80, 0xf2, 0x6e, 0x45,
- 0x32, 0x21, 0xd3, 0x12, 0xec, 0x59, 0xd1, 0xa3, 0x97, 0x08, 0x58, 0x29, 0x21, 0xfa, 0x0c, 0x95,
- 0x60, 0xe8, 0x98, 0xeb, 0x4e, 0xf2, 0x83, 0xd1, 0x54, 0x76, 0xe8, 0x7c, 0x04, 0xb3, 0x39, 0xe7,
- 0x1f, 0xf7, 0x9f, 0x46, 0x03, 0xf3, 0xb8, 0xc1, 0xdb, 0x3b, 0x59, 0x2c, 0xd7, 0xd4, 0x30, 0x85,
- 0x2f, 0xe4, 0x50, 0xb7, 0x52, 0x40, 0xa7, 0x8a, 0x89, 0x7a, 0xf4, 0x44, 0x3d, 0x2b, 0x80, 0x5f,
- 0x29, 0x21, 0xdb, 0x2d, 0xfe, 0x7b, 0x59, 0x33, 0xae, 0xa4, 0x31, 0x5f, 0x60, 0xd5, 0x2c, 0x0f,
- 0xe1, 0xaa, 0xdb, 0x30, 0x80, 0xc7, 0xc6, 0x2d, 0xaf, 0x92, 0xb1, 0x58, 0x7d, 0x58, 0xe6, 0xda,
- 0x4a, 0x1f, 0x5c, 0x2d, 0xa1, 0xd4, 0x95, 0x8a, 0x7a, 0x36, 0x0e, 0xfc, 0x4a, 0x09, 0x5e, 0xbb,
- 0x78, 0xff, 0x67, 0x88, 0x5d, 0xf6, 0xa4, 0x97, 0x31, 0xf0, 0x1c, 0x34, 0x44, 0xe3, 0x57, 0x0d,
- 0xa1, 0xc6, 0x70, 0xbe, 0xba, 0x55, 0xc0, 0x9c, 0x7f, 0x6b, 0xfd, 0xe0, 0x9c, 0x24, 0xcc, 0x19,
- 0x32, 0x47, 0x44, 0x3d, 0x0b, 0xa0, 0xa3, 0x7b, 0x4a, 0xf0, 0xf4, 0xc4, 0x4b, 0x85, 0x5c, 0xf6,
- 0xa5, 0x23, 0xd1, 0xea, 0x89, 0x97, 0x23, 0xd0, 0xb4, 0xbd, 0x61, 0x1c, 0xc5, 0x02, 0xcd, 0x9a,
- 0xeb, 0x0e, 0x24, 0x1d, 0x26, 0x22, 0xb9, 0x54, 0x07, 0x8e, 0x9f, 0x63, 0x29, 0x17, 0xd3, 0x14,
- 0xfd, 0xb3, 0x00, 0xb0, 0x79, 0x06, 0xd5, 0x5d, 0x88, 0xc9, 0x78, 0xcb, 0x43, 0x4b, 0xec, 0x34,
- 0xcf, 0xf9, 0x57, 0x33, 0x7e, 0xf7, 0xc0, 0x26, 0xae, 0x88, 0x5f, 0x38, 0x8f, 0xf8, 0x7e, 0x6d,
- 0xee, 0xad, 0x76, 0x8e, 0x87, 0x53, 0x60, 0x4a, 0x9d, 0xb8, 0x3b, 0xc1, 0x51, 0x67, 0xa8, 0xb7,
- 0x2c, 0xc4, 0x2a, 0x79, 0x74, 0xaa, 0xc6, 0x66, 0x52, 0xd7, 0x58, 0x4f, 0xfc, 0xfe, 0x61, 0x14,
- 0x0b, 0x2b, 0x81, 0xad, 0x76, 0xdd, 0x84, 0x6a, 0xf0, 0xd8, 0x0b, 0xb4, 0xbd, 0x57, 0x4d, 0x3e,
- 0x26, 0x02, 0x36, 0x4f, 0x62, 0xa4, 0x70, 0xda, 0x9a, 0xce, 0xea, 0x79, 0x94, 0x98, 0x88, 0x74,
- 0x5b, 0xe8, 0x2d, 0x7e, 0x0a, 0x27, 0x59, 0x6a, 0x9e, 0x32, 0x42, 0x27, 0xc6, 0xed, 0xbb, 0x6a,
- 0xd2, 0x9b, 0xde, 0xd7, 0xf8, 0xca, 0x04, 0x80, 0x12, 0xd9, 0x6c, 0x4e, 0x52, 0x59, 0x6c, 0xac,
- 0x3e, 0x1c, 0x9b, 0xd9, 0xaa, 0x96, 0x05, 0x7f, 0x31, 0x54, 0x01, 0xda, 0xbe, 0xab, 0x26, 0x1d,
- 0xf5, 0xbe, 0x82, 0x86, 0x4a, 0xee, 0x5e, 0x38, 0x6d, 0x1d, 0xcf, 0xb2, 0x56, 0x3e, 0x2a, 0xa4,
- 0xae, 0x87, 0x98, 0x19, 0x5a, 0x02, 0x7b, 0x1e, 0xb7, 0xeb, 0xee, 0x44, 0x4b, 0xf4, 0x73, 0x2b,
- 0x25, 0xe4, 0x29, 0x26, 0x3e, 0xb7, 0x40, 0xad, 0x3b, 0xe2, 0xfb, 0x4f, 0x3c, 0x3e, 0x40, 0x8d,
- 0x7e, 0x7a, 0xcb, 0x9f, 0x06, 0xa2, 0x9a, 0xd0, 0x49, 0x77, 0x3b, 0xc6, 0x4e, 0xf0, 0x4a, 0x09,
- 0x1d, 0x4b, 0x87, 0x0c, 0x74, 0xd2, 0xb3, 0x4b, 0xc6, 0xd9, 0x99, 0xde, 0x0c, 0xbb, 0x91, 0x47,
- 0x8b, 0x76, 0xdf, 0x56, 0x3c, 0x06, 0x3c, 0xa0, 0x57, 0x26, 0x8e, 0x9d, 0x6c, 0x37, 0x36, 0xf1,
- 0x4e, 0x04, 0xf6, 0x94, 0xce, 0xa4, 0xef, 0x0d, 0x3a, 0x56, 0x50, 0xde, 0x27, 0xc7, 0x65, 0x6f,
- 0x38, 0x5d, 0xa7, 0xea, 0xcc, 0x80, 0x5c, 0xe8, 0xed, 0x17, 0x3b, 0xc1, 0x3b, 0x91, 0x66, 0x7d,
- 0xab, 0x25, 0x55, 0x04, 0x78, 0x91, 0x1d, 0x19, 0xad, 0xf3, 0x66, 0xf2, 0x12, 0x14, 0x0f, 0xab,
- 0x31, 0x43, 0xb8, 0xb6, 0xee, 0xc8, 0xe7, 0x53, 0x69, 0x89, 0x2e, 0xfd, 0x76, 0xdb, 0x9d, 0xf0,
- 0xfa, 0x35, 0xd9, 0xfb, 0x8a, 0x31, 0x65, 0xb8, 0xe9, 0xa0, 0xbc, 0xe5, 0xa1, 0xd5, 0xb4, 0x0c,
- 0x14, 0x83, 0x43, 0xdc, 0x79, 0xaf, 0x8f, 0xf3, 0x1b, 0xe1, 0xd1, 0x1b, 0xe6, 0xdf, 0x71, 0x25,
- 0x90, 0x5f, 0xcd, 0x10, 0x1c, 0xa3, 0xde, 0x4e, 0x3e, 0x3d, 0x5e, 0xbf, 0xae, 0x25, 0xed, 0x44,
- 0x00, 0x0b, 0x54, 0x8b, 0xe5, 0xa6, 0xe3, 0xb2, 0x27, 0xb1, 0x6f, 0x57, 0xb1, 0x38, 0x04, 0x2f,
- 0x91, 0x29, 0xdc, 0xc8, 0x79, 0x72, 0x37, 0xa2, 0x1d, 0x31, 0xe7, 0xfc, 0x73, 0x5c, 0x9c, 0xa5,
- 0x21, 0x84, 0xab, 0x58, 0xce, 0x47, 0x6e, 0xd8, 0x93, 0x67, 0x96, 0x0b, 0xe4, 0xb2, 0x6e, 0xcb,
- 0xf6, 0x89, 0x9d, 0xe0, 0x98, 0x48, 0xb3, 0x5e, 0xc8, 0x64, 0x8e, 0xc7, 0xa4, 0x3a, 0x6c, 0xbf,
- 0xe9, 0xe8, 0x71, 0x43, 0x3e, 0x6c, 0x5f, 0xda, 0x1d, 0x26, 0x44, 0x30, 0x21, 0xc7, 0x6e, 0x3e,
- 0xda, 0xdb, 0xb2, 0x37, 0x0c, 0x7d, 0x31, 0x33, 0xed, 0x48, 0x7f, 0x1f, 0xed, 0x7d, 0xd9, 0xc0,
- 0xc5, 0x56, 0x20, 0x56, 0x66, 0xf3, 0xb5, 0xfb, 0xe0, 0xbc, 0x17, 0xf4, 0xaa, 0x85, 0x51, 0xe7,
- 0x85, 0x8e, 0x99, 0xab, 0xdc, 0xab, 0x23, 0x9e, 0x7c, 0xec, 0x1f, 0xf8, 0x74, 0xcd, 0xdb, 0x28,
- 0x46, 0x8d, 0xcf, 0x17, 0x80, 0xfd, 0x9a, 0xea, 0xdb, 0x3a, 0x40, 0x1c, 0xd2, 0xbf, 0x34, 0x70,
- 0xc9, 0xd1, 0xe6, 0x8e, 0x78, 0x6c, 0xbe, 0x8d, 0x80, 0xa0, 0xf7, 0x12, 0x01, 0xdd, 0x2f, 0xaf,
- 0x70, 0x71, 0xcb, 0x71, 0xee, 0x67, 0xa6, 0xd7, 0x82, 0x34, 0xf6, 0x72, 0x92, 0x08, 0x2c, 0xda,
- 0x7c, 0x75, 0xde, 0x3d, 0xde, 0x65, 0x8f, 0xdf, 0x33, 0x3b, 0x33, 0x16, 0x37, 0x96, 0xd1, 0x7b,
- 0x9a, 0xb8, 0xbb, 0x34, 0x84, 0x4a, 0xcd, 0xf9, 0x7d, 0x3e, 0x1c, 0xa3, 0x06, 0x2f, 0xd0, 0xd3,
- 0x2e, 0x99, 0x58, 0x2a, 0xc1, 0x46, 0x48, 0x1d, 0xc3, 0x77, 0x92, 0x3b, 0xcd, 0xbf, 0x1c, 0xfe,
- 0xcc, 0xa1, 0x71, 0x5d, 0x9e, 0x01, 0x39, 0x01, 0x86, 0xd2, 0x45, 0xbd, 0x20, 0x8b, 0xeb, 0x4a,
- 0x00, 0x98, 0x5c, 0x09, 0x98, 0xd2, 0xf2, 0x18, 0xcb, 0xe5, 0x46, 0x94, 0xc9, 0x65, 0xc4, 0xe2,
- 0x45, 0x34, 0x7a, 0x12, 0xc6, 0x45, 0x60, 0xd3, 0x6f, 0x0a, 0xe3, 0x58, 0x66, 0xb2, 0x85, 0x9d,
- 0xdb, 0x27, 0x84, 0xbe, 0xc4, 0xdb, 0xe1, 0xd4, 0x09, 0xdf, 0xaf, 0xa2, 0x2b, 0xa5, 0xd5, 0x03,
- 0xeb, 0xcd, 0xb4, 0xf5, 0xe4, 0xf0, 0x4d, 0x07, 0xf4, 0x86, 0xa6, 0xbc, 0x36, 0xee, 0xfc, 0x00,
- 0x62, 0x33, 0x2d, 0x47, 0x90, 0x2d, 0xbb, 0x91, 0xa6, 0xcf, 0x69, 0x32, 0x9f, 0xa6, 0x18, 0x3e,
- 0x23, 0x9e, 0x65, 0x4e, 0x2e, 0xe3, 0x39, 0x05, 0x36, 0xc7, 0xfd, 0x70, 0xbf, 0x8d, 0xc0, 0xd0,
- 0xe6, 0x39, 0x13, 0x5a, 0x72, 0x96, 0x3c, 0x9b, 0x33, 0x33, 0x1d, 0xd1, 0x9c, 0xcb, 0xa7, 0xdb,
- 0x3f, 0x2b, 0xac, 0x95, 0xa9, 0x7f, 0xe7, 0xe1, 0xec, 0x0d, 0xd2, 0xb0, 0xa3, 0x1a, 0x17, 0x74,
- 0x1e, 0xb5, 0xf9, 0x70, 0xb6, 0x72, 0xa6, 0x4c, 0x01, 0xb0, 0x45, 0x33, 0x49, 0x64, 0x7a, 0x46,
- 0xa3, 0xd9, 0x42, 0x5e, 0xc8, 0xfe, 0x02, 0x4e, 0x63, 0xd9, 0x5c, 0x09, 0x80, 0x9d, 0xfb, 0xa5,
- 0x83, 0xb7, 0xcd, 0x68, 0xc9, 0x41, 0xd5, 0x21, 0xfd, 0x33, 0xba, 0x7d, 0x32, 0x3a, 0xa7, 0xcf,
- 0x09, 0x95, 0x2a, 0xa6, 0x9e, 0xf2, 0x93, 0x9a, 0x50, 0xb3, 0x10, 0xd6, 0x4a, 0x65, 0x8a, 0x4e,
- 0x13, 0x00, 0xe8, 0x85, 0x07, 0x76, 0x0f, 0xac, 0x95, 0x2b, 0x39, 0x9c, 0x1e, 0xc8, 0x17, 0x38,
- 0x8a, 0xcd, 0x75, 0x10, 0x0f, 0xf0, 0xf9, 0x7c, 0x90, 0x6d, 0x7b, 0x31, 0xca, 0x66, 0xc4, 0x03,
- 0x36, 0x50, 0x79, 0xa8, 0x2b, 0x26, 0xfe, 0xd5, 0xa9, 0x7a, 0xff, 0xff, 0xb9, 0xbb, 0xfe, 0x98,
- 0x36, 0xae, 0x3c, 0x8f, 0x1a, 0xa4, 0xce, 0x69, 0xf9, 0x63, 0xb6, 0xa1, 0xed, 0x54, 0x25, 0x96,
- 0xe7, 0x70, 0x13, 0x5c, 0xd1, 0x0a, 0xdf, 0xd1, 0x1c, 0xee, 0x11, 0x14, 0xbb, 0x21, 0x0a, 0x56,
- 0xa9, 0x0e, 0xb7, 0x44, 0xc1, 0x0d, 0x24, 0x8e, 0x61, 0x53, 0xe4, 0xa2, 0x0a, 0x59, 0x5c, 0xc4,
- 0x51, 0x60, 0x43, 0x0d, 0x55, 0x23, 0x97, 0xbd, 0x72, 0x0e, 0x51, 0x59, 0xc7, 0x28, 0x9c, 0x4c,
- 0x14, 0x24, 0x13, 0x5d, 0x2a, 0xc3, 0x2d, 0x2b, 0x1b, 0x6d, 0xd8, 0x1a, 0x5d, 0x90, 0xcc, 0x5d,
- 0x73, 0x67, 0x6b, 0x4b, 0xce, 0x96, 0x82, 0x2e, 0x96, 0xca, 0x49, 0xde, 0x3b, 0xaa, 0xf3, 0x4a,
- 0x59, 0xc5, 0x37, 0xdf, 0x79, 0x33, 0x9e, 0x19, 0xff, 0x9a, 0x31, 0x06, 0xee, 0xcc, 0x7b, 0xaa,
- 0x54, 0x83, 0x89, 0x3d, 0xef, 0xf3, 0xbe, 0xef, 0xfb, 0xe3, 0x7d, 0xbf, 0x9f, 0xaf, 0xfe, 0x81,
- 0xe1, 0x98, 0xf6, 0xb1, 0x24, 0x26, 0x35, 0x88, 0xcf, 0x02, 0xbb, 0xc1, 0x41, 0xb5, 0x80, 0xb8,
- 0x08, 0x41, 0x36, 0xef, 0xed, 0x10, 0x39, 0x61, 0x47, 0xfd, 0xda, 0x0b, 0xc9, 0xdb, 0x91, 0x8e,
- 0xe8, 0x72, 0x9c, 0x93, 0xd2, 0xfe, 0x20, 0xc2, 0x13, 0xa1, 0x59, 0xe7, 0x07, 0x4b, 0x6a, 0xdb,
- 0xc1, 0x3f, 0x3f, 0x66, 0xf0, 0x63, 0xda, 0x07, 0x86, 0x3b, 0xfa, 0x51, 0x95, 0xb8, 0xb4, 0x19,
- 0xb1, 0x32, 0xd3, 0xda, 0x01, 0xe6, 0x1d, 0x31, 0x32, 0x52, 0x89, 0x65, 0x91, 0xca, 0x92, 0x92,
- 0x2f, 0xf4, 0x7d, 0xee, 0xb6, 0x40, 0x45, 0x74, 0xef, 0x71, 0xe4, 0x23, 0x4a, 0x9d, 0xd3, 0x31,
- 0xc8, 0x03, 0x03, 0x3d, 0x1a, 0x67, 0xa4, 0x73, 0xc1, 0x03, 0x5a, 0xb3, 0x22, 0x2a, 0xbc, 0x99,
- 0x3e, 0x89, 0xcd, 0xaa, 0xee, 0x50, 0xd2, 0xe9, 0x57, 0x5f, 0x15, 0xb5, 0x8b, 0xba, 0x94, 0xcd,
- 0x66, 0xe8, 0x4e, 0x7c, 0x10, 0x25, 0x13, 0x71, 0x10, 0x80, 0x55, 0xc0, 0x45, 0x08, 0xe4, 0xd4,
- 0xea, 0xc8, 0x79, 0xef, 0x80, 0xd8, 0x1d, 0xd4, 0x00, 0xed, 0x1b, 0x90, 0x3c, 0x44, 0x9d, 0xf1,
- 0x13, 0x51, 0xc8, 0x86, 0x27, 0xfc, 0x0b, 0xb4, 0x6c, 0x86, 0xbc, 0x4f, 0xc3, 0xbe, 0x78, 0xab,
- 0x5b, 0x93, 0x72, 0x47, 0xde, 0x49, 0x9f, 0xb5, 0x7e, 0xb5, 0x58, 0x64, 0x48, 0x5e, 0x42, 0xe7,
- 0x75, 0xd1, 0x8c, 0x88, 0xf2, 0xdc, 0x6f, 0x2d, 0xba, 0xc1, 0x5a, 0xb0, 0x55, 0x5a, 0x6e, 0x75,
- 0x6e, 0xe1, 0x8f, 0x09, 0xae, 0xf2, 0x71, 0x56, 0xb5, 0xe0, 0x81, 0xf5, 0xdb, 0x7f, 0x24, 0x19,
- 0x3c, 0xe9, 0x9c, 0xdb, 0x25, 0xba, 0xf6, 0x1a, 0x98, 0x2e, 0x20, 0x26, 0xdc, 0x1e, 0xeb, 0x4e,
- 0xc9, 0x19, 0x91, 0x97, 0x54, 0x92, 0x67, 0x74, 0x1f, 0xe9, 0xd2, 0x59, 0xf3, 0x52, 0x47, 0x29,
- 0xd9, 0x4c, 0xd7, 0x29, 0x1c, 0x34, 0xc9, 0xe4, 0x2c, 0x58, 0x2e, 0x2b, 0xfd, 0x16, 0xde, 0xa9,
- 0x7c, 0x87, 0xe4, 0x56, 0x04, 0xb7, 0x2e, 0x05, 0xff, 0x2f, 0x72, 0x09, 0x78, 0x68, 0xd2, 0x59,
- 0xb7, 0x1b, 0xe1, 0x3a, 0x1a, 0xcd, 0x05, 0xcf, 0x52, 0xd0, 0x17, 0x9f, 0xf4, 0xa4, 0x3f, 0xcd,
- 0x26, 0xf1, 0x44, 0x03, 0xfd, 0x8c, 0xe5, 0x39, 0x9f, 0x19, 0xc5, 0xda, 0x0f, 0x5e, 0x57, 0x5b,
- 0xc4, 0x08, 0xbb, 0x46, 0xf9, 0x95, 0xec, 0xd9, 0x64, 0xc4, 0x3a, 0x95, 0x7e, 0x75, 0x65, 0x12,
- 0xd9, 0x55, 0x75, 0xc8, 0x5b, 0x28, 0x92, 0x28, 0x9b, 0x1d, 0xe6, 0x79, 0xc8, 0x95, 0xdd, 0x51,
- 0x56, 0x17, 0x8a, 0x0e, 0xb6, 0x05, 0xc0, 0x4f, 0x21, 0xfc, 0xc0, 0x57, 0x91, 0x2a, 0x99, 0x30,
- 0xee, 0xd3, 0x6c, 0x06, 0xb7, 0x44, 0xb4, 0x26, 0x74, 0x9b, 0x3e, 0x68, 0x51, 0x03, 0x74, 0x33,
- 0x02, 0xd9, 0x76, 0x5c, 0x0f, 0xd9, 0x43, 0xa4, 0x5f, 0xed, 0x52, 0xb3, 0xab, 0x61, 0xc4, 0x5a,
- 0x6c, 0x15, 0x05, 0x66, 0x12, 0xd4, 0x47, 0xcb, 0x5d, 0x20, 0x07, 0x63, 0xaa, 0x55, 0xf5, 0x35,
- 0xfd, 0xbc, 0xe5, 0xb0, 0xab, 0xce, 0x2f, 0x2d, 0x8e, 0x90, 0x8a, 0xa6, 0x33, 0x0e, 0xb5, 0xf4,
- 0x7f, 0xf0, 0x12, 0x7e, 0x38, 0x29, 0x6a, 0x5d, 0x99, 0x74, 0xe3, 0x2d, 0xfc, 0x39, 0xf2, 0x96,
- 0x08, 0x46, 0xa8, 0x52, 0xf3, 0x60, 0x49, 0x26, 0xe2, 0x9d, 0x84, 0xda, 0x70, 0xd6, 0xee, 0xb9,
- 0x8a, 0x8f, 0xaa, 0x9e, 0xa8, 0x4f, 0x29, 0xe5, 0xcc, 0x3b, 0x9a, 0x74, 0x84, 0x3f, 0x52, 0x10,
- 0x92, 0x83, 0xb1, 0x1a, 0x2b, 0xb0, 0x68, 0xf3, 0xa7, 0x82, 0x9c, 0xd3, 0xb7, 0xd8, 0xe2, 0xde,
- 0xdc, 0x11, 0xbe, 0x4c, 0xc3, 0x49, 0x57, 0xec, 0x42, 0x4d, 0xee, 0x89, 0xa8, 0x30, 0xcf, 0xf2,
- 0x24, 0x76, 0x15, 0x43, 0xf1, 0x9c, 0x8b, 0xd8, 0x45, 0x51, 0xab, 0x46, 0xc1, 0xd4, 0x50, 0x1f,
- 0x1c, 0x9d, 0xc9, 0xc6, 0xd3, 0xab, 0x74, 0x72, 0xfa, 0x35, 0x92, 0x4a, 0xbf, 0x9a, 0xf5, 0xde,
- 0x56, 0x88, 0x5e, 0x7b, 0xa1, 0x77, 0xcf, 0xfd, 0x01, 0x60, 0x0e, 0x4e, 0x9f, 0x46, 0x6c, 0x54,
- 0x55, 0x66, 0xaa, 0x75, 0x0d, 0xc6, 0x12, 0x79, 0x9d, 0xb9, 0xa8, 0x2e, 0x70, 0x29, 0x08, 0x31,
- 0xc4, 0xde, 0x24, 0xd3, 0xda, 0x49, 0xec, 0x31, 0x51, 0x49, 0x56, 0x92, 0xcf, 0xbd, 0x02, 0x7a,
- 0x5e, 0x4e, 0xe1, 0x99, 0x5b, 0x36, 0x59, 0x9d, 0x79, 0x50, 0xfc, 0x4c, 0xee, 0x84, 0x65, 0xe3,
- 0xe9, 0x57, 0x71, 0x17, 0x2d, 0x95, 0xac, 0xdd, 0xd3, 0xa4, 0x2b, 0x34, 0xeb, 0x2e, 0x92, 0xa8,
- 0xf3, 0x43, 0x85, 0x58, 0xe6, 0xa9, 0xa1, 0x3e, 0xff, 0x1a, 0xe5, 0xbb, 0x3a, 0xe3, 0xf9, 0xa0,
- 0x89, 0xaa, 0x8f, 0x00, 0x4b, 0x75, 0x80, 0xed, 0x5d, 0xfd, 0x73, 0xfc, 0x1d, 0x72, 0x54, 0x35,
- 0xaa, 0xb2, 0x2a, 0x2b, 0x49, 0x90, 0xca, 0xfb, 0x14, 0xb2, 0xf7, 0x73, 0xf6, 0x05, 0x43, 0xec,
- 0x06, 0x07, 0xc5, 0xcf, 0x84, 0x78, 0x0f, 0x30, 0xfb, 0x6e, 0x19, 0xd0, 0xde, 0x04, 0xa9, 0x7c,
- 0xc2, 0x93, 0xca, 0x52, 0x52, 0x58, 0xf7, 0xbc, 0x33, 0x2c, 0xa7, 0x82, 0x55, 0x19, 0xe5, 0x92,
- 0xc3, 0x73, 0x85, 0x58, 0x33, 0xb4, 0x05, 0x7c, 0x79, 0xa0, 0x09, 0x76, 0x50, 0x7b, 0x6c, 0x88,
- 0xc2, 0xb4, 0x9a, 0xb9, 0x01, 0x03, 0xdb, 0x1b, 0xb0, 0x1c, 0x55, 0x75, 0x2a, 0x81, 0xfb, 0xf9,
- 0x31, 0xe1, 0xa2, 0xfe, 0x3f, 0x97, 0x77, 0x02, 0x7d, 0x87, 0x0e, 0x0e, 0xf3, 0x2c, 0x8a, 0xc2,
- 0x96, 0x25, 0x73, 0x27, 0x59, 0xa9, 0x94, 0xd3, 0xaf, 0x20, 0x87, 0xbf, 0x50, 0xab, 0x07, 0x06,
- 0xd4, 0xf5, 0x80, 0x57, 0x9e, 0x7b, 0xae, 0x10, 0xb8, 0x95, 0xe3, 0x3e, 0x90, 0x32, 0xd0, 0x5d,
- 0xf7, 0x43, 0x26, 0xce, 0xfe, 0x9b, 0x24, 0x96, 0x56, 0xd5, 0x73, 0x24, 0xdc, 0x9f, 0xf8, 0xd5,
- 0x67, 0x74, 0xa7, 0x72, 0xd6, 0xe0, 0x42, 0xa7, 0xbe, 0x83, 0xd1, 0xdd, 0x2d, 0xe9, 0x59, 0x9a,
- 0x91, 0x1c, 0xa6, 0x4a, 0xe5, 0x0a, 0xb1, 0xc0, 0xeb, 0x14, 0xbb, 0xf3, 0x01, 0x19, 0xe7, 0x8d,
- 0x4a, 0x31, 0x2c, 0xe5, 0xb4, 0x6d, 0x19, 0xf7, 0xe6, 0x1b, 0x25, 0xdc, 0x08, 0xa3, 0x9d, 0x98,
- 0x2a, 0x97, 0x25, 0x25, 0xa3, 0xaa, 0x3b, 0xfa, 0x63, 0xda, 0x5c, 0x51, 0x20, 0x79, 0x09, 0xca,
- 0xb6, 0x2c, 0xfe, 0x5b, 0x13, 0xc4, 0x88, 0x36, 0xa7, 0x67, 0x59, 0xe7, 0xae, 0x52, 0xab, 0xf1,
- 0x44, 0xdd, 0x99, 0xb4, 0x60, 0xd7, 0x0c, 0xbb, 0x93, 0xd5, 0x0c, 0xe7, 0x21, 0x44, 0xed, 0xa5,
- 0xa0, 0x39, 0xa6, 0x7a, 0x98, 0xb3, 0x1a, 0x30, 0x7d, 0x38, 0xe3, 0xe8, 0x36, 0xf3, 0x24, 0x56,
- 0x49, 0x22, 0x24, 0x0f, 0x31, 0x51, 0x8e, 0x19, 0xfc, 0x0e, 0xf5, 0x6c, 0xb9, 0x25, 0x73, 0x4c,
- 0x75, 0x30, 0x3a, 0x88, 0x1b, 0xe9, 0xde, 0x5c, 0xd5, 0x0c, 0xcb, 0x0b, 0x68, 0x18, 0xbf, 0xfa,
- 0x89, 0x7a, 0x33, 0x79, 0x33, 0xb8, 0xe0, 0x8d, 0xec, 0x06, 0x94, 0xf4, 0x68, 0x0b, 0x74, 0x49,
- 0x90, 0x4c, 0x64, 0x0b, 0xe1, 0x56, 0xd8, 0x43, 0x52, 0x3f, 0x3b, 0x92, 0x68, 0xb1, 0x21, 0x24,
- 0xae, 0xe2, 0x60, 0xc7, 0xde, 0xe7, 0xc5, 0x1e, 0xcf, 0xe8, 0x20, 0x63, 0x3d, 0x97, 0xce, 0x84,
- 0x0e, 0xe2, 0xc5, 0xef, 0x99, 0xc8, 0x19, 0x16, 0xfc, 0x6a, 0x13, 0x5a, 0x09, 0x23, 0x76, 0x8a,
- 0x92, 0xca, 0xd9, 0xa4, 0xb5, 0xb0, 0x65, 0xd8, 0xbd, 0x3c, 0xd8, 0x48, 0x22, 0x9c, 0x28, 0x77,
- 0x89, 0xeb, 0x4c, 0x34, 0x67, 0xf0, 0x66, 0x73, 0x3e, 0x68, 0xb6, 0x05, 0xb8, 0xfd, 0x27, 0x17,
- 0x3c, 0x63, 0xa7, 0x72, 0xcb, 0xf0, 0x91, 0x2e, 0xb7, 0x35, 0xdb, 0xa4, 0x2b, 0x7e, 0xfb, 0x87,
- 0x8b, 0xa8, 0xcb, 0x4b, 0x60, 0x15, 0x20, 0xf6, 0xf5, 0x44, 0xc3, 0x9e, 0x48, 0x1a, 0xac, 0xd6,
- 0x25, 0x75, 0x2d, 0xa5, 0x60, 0x09, 0xf1, 0xd4, 0x6a, 0x93, 0x54, 0x34, 0x8d, 0xd8, 0x9c, 0x1e,
- 0xa2, 0x08, 0xd2, 0xbe, 0xc1, 0x60, 0x2c, 0x1b, 0xcb, 0x88, 0xbc, 0xe4, 0x07, 0xc3, 0x1d, 0xfd,
- 0x21, 0x32, 0xd7, 0x3a, 0xac, 0xd0, 0xbd, 0xfa, 0x14, 0x45, 0x6c, 0xff, 0xb0, 0x9e, 0x25, 0xcb,
- 0x53, 0x78, 0x12, 0x3b, 0x44, 0x7e, 0x4b, 0x9d, 0xb0, 0xec, 0xed, 0xdf, 0x9c, 0x7e, 0x77, 0x6b,
- 0x2c, 0x01, 0x95, 0x8a, 0xe8, 0xaa, 0x5a, 0x2a, 0x9a, 0x60, 0x43, 0x43, 0x3e, 0x88, 0xb4, 0x7f,
- 0x3b, 0x5b, 0x65, 0x82, 0xbc, 0xe4, 0x8e, 0xfe, 0x07, 0xc3, 0xa8, 0x80, 0xff, 0x24, 0x75, 0x40,
- 0xe7, 0x21, 0x64, 0xff, 0xe4, 0x7a, 0xd7, 0xff, 0xe7, 0xc1, 0x7a, 0x96, 0x6c, 0xfe, 0xe4, 0x55,
- 0xfc, 0x1d, 0xe5, 0xb7, 0x6a, 0x17, 0x13, 0x93, 0xd5, 0x60, 0x2d, 0xb6, 0xdd, 0xbe, 0x17, 0x81,
- 0x73, 0xb6, 0xd5, 0x9d, 0x1a, 0xcb, 0xcb, 0x25, 0x9b, 0xd7, 0xf4, 0xfd, 0x01, 0x69, 0x68, 0xd6,
- 0x58, 0xb3, 0x3d, 0xe7, 0xf3, 0xda, 0x1f, 0x0c, 0xfe, 0x9c, 0x1a, 0x53, 0x5e, 0x02, 0xfd, 0xc9,
- 0x8a, 0xb9, 0xbf, 0x1b, 0xeb, 0x59, 0x22, 0xce, 0x1e, 0x39, 0x65, 0xd1, 0x9f, 0x52, 0xba, 0x54,
- 0x8f, 0x19, 0xcd, 0xf2, 0x33, 0xd5, 0xee, 0x78, 0x23, 0xa9, 0x68, 0x56, 0x44, 0xb7, 0x0c, 0x52,
- 0xb1, 0x94, 0xd3, 0x5c, 0xf9, 0x75, 0x7e, 0x29, 0x27, 0x6d, 0x5b, 0x40, 0x9e, 0xe5, 0x39, 0x4f,
- 0x29, 0x7f, 0x30, 0x3c, 0x11, 0xb9, 0x9d, 0xde, 0x24, 0xe8, 0xfe, 0x6e, 0x45, 0x7a, 0xca, 0xb2,
- 0x99, 0x04, 0x5b, 0x86, 0x4d, 0x39, 0x7a, 0x7d, 0x9f, 0x38, 0xa5, 0xec, 0x54, 0xb2, 0x3b, 0x73,
- 0x2d, 0x2b, 0x77, 0x4f, 0x61, 0x58, 0x82, 0x05, 0xb4, 0x29, 0x59, 0x32, 0x01, 0xcd, 0x2a, 0xad,
- 0x14, 0x34, 0xdb, 0x63, 0xf2, 0x2c, 0x4f, 0x3a, 0x83, 0x3f, 0x10, 0xc5, 0x12, 0xf6, 0x4c, 0xf1,
- 0xf6, 0x77, 0x03, 0xcf, 0x72, 0x36, 0xd9, 0x61, 0x0d, 0xb4, 0x25, 0x44, 0x2f, 0xb9, 0x3c, 0xb6,
- 0x2f, 0x2d, 0x7b, 0x53, 0xcb, 0x45, 0xc7, 0xf3, 0x74, 0xd2, 0xb1, 0x04, 0x1f, 0x65, 0x56, 0x05,
- 0x4c, 0x6d, 0xb9, 0xd1, 0xf4, 0xc5, 0xe5, 0x59, 0x9e, 0xf4, 0x2a, 0xfe, 0x85, 0x9e, 0xb2, 0x02,
- 0x44, 0x4e, 0x4f, 0xb6, 0x8b, 0x42, 0xf1, 0x9d, 0xb2, 0xac, 0xdd, 0xb3, 0x65, 0x60, 0xed, 0xbf,
- 0x93, 0xd8, 0x2d, 0x9c, 0xf3, 0xcb, 0x0a, 0x8b, 0xc2, 0x42, 0x06, 0x5d, 0xf6, 0xdf, 0x86, 0x13,
- 0xb1, 0x01, 0x29, 0x51, 0x03, 0x3e, 0x9a, 0xa5, 0x24, 0xe8, 0xcd, 0x5c, 0x68, 0x46, 0x12, 0xd9,
- 0x24, 0xcf, 0x88, 0x1d, 0xd3, 0x8a, 0x67, 0x00, 0x29, 0xc8, 0x2d, 0x43, 0x93, 0xae, 0x18, 0x63,
- 0x79, 0x2c, 0x03, 0xfe, 0x35, 0x3d, 0xbb, 0x0f, 0xe5, 0x82, 0x1b, 0xbf, 0xa8, 0x5a, 0xaa, 0xcd,
- 0x91, 0x69, 0x40, 0x26, 0x64, 0xae, 0x55, 0xef, 0x73, 0x2b, 0xc8, 0x7c, 0xb0, 0x84, 0x39, 0xa6,
- 0x8a, 0xe7, 0x60, 0xf9, 0x82, 0x91, 0x8d, 0x2f, 0x46, 0x83, 0x3d, 0x51, 0x8f, 0xaa, 0xc4, 0xb0,
- 0x84, 0x3a, 0x78, 0xc8, 0x80, 0x2e, 0xb6, 0x88, 0x01, 0xe8, 0x4a, 0xc4, 0xf6, 0xc2, 0xaf, 0xe6,
- 0x82, 0x15, 0x63, 0x47, 0x21, 0x11, 0x75, 0x60, 0xd5, 0xce, 0xa5, 0x6b, 0x23, 0x74, 0xfc, 0x34,
- 0x5f, 0x2c, 0x35, 0xd8, 0x6a, 0x4e, 0xce, 0xb6, 0x44, 0xa2, 0xc5, 0x96, 0xf9, 0x69, 0x35, 0x18,
- 0x44, 0xf5, 0xc4, 0x23, 0x74, 0x70, 0x4a, 0xcd, 0x16, 0x5d, 0x5c, 0x96, 0xad, 0xb1, 0x9c, 0x4b,
- 0x4a, 0xe5, 0x45, 0xec, 0x2a, 0xce, 0x59, 0xed, 0x46, 0x6c, 0xde, 0xb2, 0xf3, 0xfa, 0x4a, 0x67,
- 0x1c, 0x38, 0x46, 0x73, 0xbd, 0xc3, 0x97, 0x80, 0x1b, 0xb6, 0xfc, 0xd1, 0xa4, 0x19, 0xf8, 0xb2,
- 0x9e, 0xb4, 0x7d, 0xee, 0xcc, 0x4f, 0x0b, 0xb9, 0x79, 0x95, 0xa4, 0x78, 0x2f, 0x85, 0x31, 0xba,
- 0xd7, 0x6e, 0x71, 0x69, 0x4c, 0x74, 0x37, 0x52, 0xa5, 0x6d, 0x36, 0x73, 0x59, 0x77, 0xf7, 0x89,
- 0x77, 0x94, 0x8f, 0x79, 0xda, 0xb2, 0xd5, 0x9d, 0x6d, 0xc5, 0xc4, 0x47, 0x7b, 0x0c, 0xb8, 0xb8,
- 0x73, 0xbd, 0x23, 0x42, 0x79, 0x83, 0x70, 0x96, 0xed, 0x44, 0x36, 0xe3, 0xde, 0x6c, 0x7a, 0xb3,
- 0xce, 0x9f, 0xed, 0x79, 0xef, 0x13, 0xa9, 0x9d, 0x6c, 0x33, 0x8d, 0x4d, 0xa2, 0xd8, 0x34, 0x26,
- 0x9f, 0x83, 0x89, 0xfb, 0x69, 0x25, 0xe9, 0xe2, 0x9d, 0x43, 0x5d, 0xca, 0xdc, 0x72, 0x95, 0x7b,
- 0x54, 0x44, 0x43, 0x22, 0x58, 0x26, 0x12, 0x93, 0x1e, 0xe9, 0x11, 0x03, 0x21, 0x9a, 0xe8, 0xbb,
- 0x65, 0x42, 0xb3, 0x3f, 0x98, 0xed, 0x99, 0x2f, 0x62, 0x3f, 0x97, 0xa0, 0x05, 0xe1, 0xf6, 0xeb,
- 0x9a, 0xbe, 0x98, 0x62, 0xec, 0xa8, 0x6e, 0xa4, 0x5b, 0xd7, 0x63, 0xe6, 0x32, 0xd4, 0x4f, 0x62,
- 0x9d, 0xca, 0x2a, 0x9d, 0x2b, 0x19, 0x53, 0x8f, 0xaa, 0x77, 0x7e, 0xd3, 0x05, 0xda, 0x70, 0xc1,
- 0x93, 0xce, 0xf6, 0x2c, 0x7c, 0xcf, 0xd3, 0x70, 0xfe, 0xd6, 0x0f, 0x3b, 0x4b, 0xc9, 0xcc, 0xfe,
- 0xe6, 0x54, 0x56, 0x2c, 0x4f, 0x4a, 0x94, 0xb4, 0x62, 0xf3, 0x31, 0xd1, 0x2d, 0x57, 0x99, 0x80,
- 0x01, 0xff, 0x22, 0xe6, 0x52, 0xdd, 0xd1, 0xb3, 0xbd, 0x24, 0x35, 0xd8, 0xfa, 0xc0, 0xce, 0xfd,
- 0x11, 0xf0, 0x1f, 0x27, 0x45, 0xb1, 0xf4, 0xc5, 0xb3, 0xe7, 0xff, 0x88, 0xcb, 0x66, 0x66, 0x9b,
- 0x76, 0x29, 0x0b, 0x96, 0xe0, 0x39, 0x4b, 0xeb, 0x3c, 0x04, 0x8c, 0x46, 0xc5, 0x73, 0x5f, 0x82,
- 0x62, 0xb0, 0xdd, 0x3a, 0x21, 0xb3, 0xc4, 0x2d, 0xdc, 0xaf, 0x86, 0x2a, 0x0c, 0xf4, 0x6a, 0x04,
- 0xef, 0x2b, 0x40, 0x5b, 0xfa, 0x28, 0xcb, 0x67, 0xd2, 0x33, 0x15, 0xcc, 0x8d, 0x65, 0x22, 0x31,
- 0xa7, 0xdf, 0x29, 0x96, 0xd9, 0x6c, 0xda, 0x6c, 0x58, 0x3e, 0x26, 0x3a, 0x95, 0xe2, 0xd5, 0x42,
- 0x30, 0x20, 0x93, 0xab, 0x78, 0xe2, 0x05, 0x48, 0x2a, 0xb7, 0x0c, 0xab, 0x02, 0x0e, 0xd1, 0xfb,
- 0xc4, 0x13, 0x35, 0xc4, 0x2c, 0xd1, 0xcf, 0x66, 0xf0, 0x73, 0x05, 0x68, 0x4b, 0x67, 0x1c, 0x6a,
- 0x04, 0x96, 0x72, 0x62, 0x09, 0x63, 0xde, 0xb2, 0x73, 0x2c, 0xe5, 0x34, 0xc7, 0x5d, 0xdc, 0x1b,
- 0x16, 0x9c, 0xb4, 0x1b, 0xe1, 0xcc, 0xcf, 0x0c, 0xb9, 0xbe, 0xb9, 0xef, 0x2f, 0xd9, 0x31, 0x83,
- 0xb3, 0x5d, 0xa7, 0x0b, 0x5b, 0xe5, 0xfd, 0x18, 0xec, 0xdd, 0xf3, 0x9c, 0x5e, 0xc8, 0xf7, 0xf2,
- 0x98, 0x80, 0xbb, 0x04, 0x0e, 0x4b, 0x71, 0x24, 0x72, 0x61, 0x09, 0xd5, 0x3b, 0xe2, 0xb1, 0xdc,
- 0x09, 0x7b, 0x21, 0x58, 0x22, 0x0f, 0xa5, 0x4d, 0x10, 0x0b, 0xda, 0x08, 0x67, 0x96, 0xa7, 0x33,
- 0xba, 0x2a, 0x91, 0xbb, 0x68, 0x6e, 0x7d, 0xe0, 0x1e, 0xb3, 0x38, 0x2c, 0x59, 0x94, 0xd5, 0x0c,
- 0xbd, 0x1e, 0xf8, 0x3f, 0x95, 0x33, 0x58, 0xb2, 0x7c, 0xbf, 0x9b, 0x44, 0x21, 0x99, 0x77, 0x83,
- 0xb1, 0xf8, 0xb7, 0x93, 0x9e, 0xa7, 0xa2, 0x58, 0xf6, 0xb9, 0x0b, 0xc3, 0x12, 0xc5, 0x69, 0xe1,
- 0x7e, 0x93, 0x45, 0x73, 0x23, 0x7c, 0x3f, 0x43, 0x05, 0x1e, 0xdc, 0x45, 0x7f, 0xa4, 0x93, 0x76,
- 0xc6, 0x96, 0x94, 0x40, 0xef, 0x04, 0x45, 0x11, 0x58, 0xb2, 0x2c, 0x4b, 0xc8, 0x5c, 0x0a, 0xdf,
- 0x0b, 0xc2, 0xf2, 0x81, 0xe1, 0x79, 0x2d, 0xb2, 0x10, 0x56, 0xd5, 0x85, 0x44, 0xd5, 0xc1, 0xbb,
- 0x9c, 0xf4, 0x88, 0xdb, 0xc1, 0xfd, 0x81, 0x42, 0xb1, 0x84, 0x39, 0xab, 0xe2, 0xf2, 0xb0, 0x9f,
- 0x86, 0x33, 0x71, 0x10, 0x18, 0xb1, 0x8f, 0xcd, 0x67, 0x98, 0x8c, 0x7c, 0xf1, 0x01, 0xfc, 0xec,
- 0xc5, 0xe0, 0x95, 0xa0, 0x3e, 0xcf, 0x73, 0x86, 0xa8, 0x26, 0xf5, 0x37, 0xa0, 0x2f, 0x1f, 0x18,
- 0xce, 0x30, 0xbb, 0xf7, 0x9a, 0xbe, 0x10, 0x4e, 0xad, 0xfa, 0x68, 0x48, 0x12, 0x96, 0xf5, 0xd1,
- 0xdd, 0xc0, 0x12, 0x3a, 0x57, 0xb4, 0x31, 0x91, 0x63, 0xa8, 0x93, 0x4e, 0xe7, 0x20, 0x18, 0x55,
- 0xf5, 0x98, 0xa5, 0x73, 0xce, 0x42, 0x7e, 0x65, 0x31, 0xc4, 0x64, 0xd9, 0x13, 0x16, 0xdd, 0x57,
- 0xf2, 0xc7, 0x2d, 0x1c, 0x7c, 0x92, 0x2f, 0xf4, 0x48, 0xab, 0x54, 0x9b, 0x0a, 0xc9, 0x27, 0xa8,
- 0x88, 0x42, 0x3d, 0xdd, 0x09, 0x11, 0x2c, 0xc1, 0x2b, 0xd9, 0x49, 0xe4, 0x27, 0x7d, 0xc2, 0xcd,
- 0x23, 0x42, 0xb3, 0x3e, 0x5a, 0x6d, 0x9a, 0x4d, 0xeb, 0xc8, 0xf6, 0xc0, 0xc0, 0xef, 0xd5, 0x29,
- 0x36, 0xd6, 0x8a, 0x04, 0x4b, 0x64, 0xc3, 0xae, 0x19, 0xd2, 0x2d, 0x04, 0x88, 0x15, 0x50, 0x67,
- 0xaf, 0x01, 0xc5, 0xf4, 0xc6, 0x0b, 0x88, 0xc5, 0xc2, 0x49, 0x07, 0x58, 0x8a, 0x9d, 0xd2, 0xa0,
- 0xe5, 0x76, 0x1e, 0x2d, 0x48, 0x45, 0xf3, 0x9a, 0x1e, 0x4e, 0xda, 0xf3, 0xb1, 0xd8, 0x40, 0x2a,
- 0x7b, 0xf3, 0x55, 0xfc, 0x5d, 0xf3, 0x5c, 0x06, 0x0e, 0xdc, 0x6c, 0xa3, 0x58, 0x22, 0x3f, 0x88,
- 0x09, 0x3f, 0x53, 0x2f, 0x6d, 0x88, 0x3e, 0x03, 0x0b, 0x07, 0xca, 0x70, 0xfa, 0xb2, 0x60, 0x2c,
- 0xa5, 0x70, 0x05, 0x47, 0x12, 0x63, 0x3b, 0x8e, 0x16, 0x64, 0x92, 0xcd, 0xa7, 0xe1, 0xf6, 0x58,
- 0xaf, 0x0d, 0xf1, 0xf6, 0xc8, 0x93, 0x4f, 0x16, 0x55, 0x7f, 0x69, 0xf1, 0xe7, 0xc1, 0x37, 0x5b,
- 0x2c, 0xfa, 0x32, 0x3b, 0x96, 0x28, 0x5a, 0x30, 0xa7, 0x3f, 0xa3, 0x03, 0xab, 0xa8, 0xc7, 0x5c,
- 0x88, 0xed, 0xb3, 0x11, 0x9e, 0x94, 0x88, 0x65, 0xfe, 0xf7, 0x5e, 0xec, 0xd4, 0x60, 0x46, 0x6c,
- 0x04, 0x9f, 0xc1, 0x21, 0x23, 0xb4, 0x4a, 0xdb, 0xad, 0xeb, 0xd6, 0x5f, 0xd3, 0xd7, 0x58, 0xa1,
- 0x4b, 0x26, 0xc4, 0xe0, 0xee, 0x13, 0xdc, 0x9d, 0x2c, 0x75, 0xc2, 0x66, 0xe5, 0xb8, 0xc9, 0x34,
- 0x50, 0xd6, 0x4f, 0xb1, 0x60, 0x09, 0x99, 0x53, 0xe9, 0x03, 0xb8, 0xab, 0x3e, 0xd2, 0x3d, 0xa0,
- 0x4f, 0x59, 0x94, 0x65, 0xbc, 0xb3, 0x11, 0x61, 0xb0, 0x14, 0xd3, 0xb8, 0x70, 0xc6, 0x76, 0xe7,
- 0x95, 0x29, 0xc2, 0xa2, 0xb8, 0x42, 0x40, 0xdd, 0x6f, 0x8d, 0x15, 0x7c, 0x58, 0x21, 0x57, 0x54,
- 0x7b, 0xac, 0xc5, 0xc6, 0xf2, 0x70, 0xa3, 0x1b, 0xb5, 0x53, 0xca, 0x4c, 0x7c, 0xf1, 0xb9, 0x56,
- 0x88, 0xad, 0x13, 0xda, 0xad, 0x35, 0xdf, 0xab, 0xa1, 0x61, 0x62, 0x3e, 0x99, 0x78, 0x61, 0x59,
- 0xc9, 0xfc, 0x48, 0x67, 0xc4, 0xb6, 0x0a, 0xa8, 0x21, 0x89, 0x24, 0x96, 0x68, 0x2c, 0x87, 0x24,
- 0xe8, 0xcb, 0xb5, 0x3c, 0xf2, 0xf1, 0xd0, 0x49, 0xda, 0xa5, 0xdc, 0x32, 0xdc, 0xb3, 0xb3, 0x5e,
- 0x48, 0x44, 0x30, 0xc1, 0xea, 0x9a, 0x1f, 0x68, 0xd2, 0x8d, 0xa9, 0x4a, 0xc9, 0x15, 0x62, 0x06,
- 0xbf, 0x4f, 0x1c, 0x22, 0xc1, 0xd3, 0x42, 0x79, 0x85, 0x46, 0x0c, 0x38, 0xf3, 0xc4, 0xb9, 0x45,
- 0x8a, 0x25, 0x86, 0xc7, 0x66, 0xa9, 0x67, 0xb6, 0xd0, 0xa1, 0xc2, 0x0b, 0xe9, 0xcc, 0xc2, 0x72,
- 0x0a, 0x96, 0x24, 0x9d, 0xb1, 0xb0, 0xfa, 0xd5, 0xa6, 0x7c, 0x90, 0x1c, 0x53, 0xad, 0x0f, 0x84,
- 0xbc, 0xb9, 0x32, 0xd9, 0x37, 0xc2, 0x6b, 0x06, 0x4c, 0x3b, 0xab, 0x1a, 0x53, 0x45, 0xa9, 0x5d,
- 0xf9, 0x13, 0xd3, 0xbb, 0xe6, 0x1e, 0x73, 0xb5, 0x69, 0x54, 0x85, 0xea, 0x10, 0x8f, 0xe9, 0x8e,
- 0x69, 0x21, 0x57, 0x44, 0x41, 0x66, 0x8f, 0x1b, 0x80, 0x95, 0x5f, 0x1c, 0x99, 0x05, 0x28, 0xc7,
- 0x07, 0x58, 0x28, 0xd1, 0xeb, 0xdf, 0x62, 0x7f, 0x5e, 0xfe, 0x01, 0x3d, 0x0f, 0x97, 0x6b, 0x4a,
- 0xc0, 0x9a, 0x05, 0x8e, 0xc0, 0x3b, 0xfa, 0xa8, 0xba, 0x10, 0x2c, 0x7f, 0x4d, 0x63, 0x29, 0xae,
- 0x71, 0x51, 0x77, 0x0a, 0x69, 0x13, 0xaa, 0x4b, 0x10, 0x6f, 0x5a, 0x36, 0x1c, 0x61, 0x40, 0x1d,
- 0x3d, 0xa6, 0xad, 0xd2, 0xfe, 0xc4, 0x54, 0x63, 0x7d, 0xe8, 0xf8, 0xca, 0x1e, 0x1b, 0xa8, 0x36,
- 0xdd, 0xd1, 0x43, 0x25, 0x29, 0x54, 0xd2, 0x03, 0x87, 0xd3, 0x0f, 0xd4, 0x04, 0x3f, 0x1a, 0x18,
- 0x63, 0x32, 0xad, 0x50, 0xf1, 0x64, 0xfc, 0xa0, 0x3b, 0x92, 0x2d, 0xa6, 0xf7, 0xe1, 0x77, 0x87,
- 0xbf, 0x7e, 0xd1, 0x29, 0xa3, 0xe6, 0x4b, 0xd4, 0x94, 0xd5, 0xbd, 0x38, 0xff, 0x02, 0xdc, 0x7d,
- 0x9d, 0x52, 0xc2, 0xee, 0x2d, 0x04, 0x4b, 0xd0, 0x97, 0xe2, 0x3e, 0x09, 0xbc, 0x33, 0x36, 0x20,
- 0x0d, 0xc9, 0x59, 0x55, 0xab, 0xbb, 0x5e, 0x42, 0x65, 0x49, 0xc8, 0x1b, 0x55, 0xc3, 0xbd, 0xec,
- 0x77, 0x8e, 0xeb, 0x9e, 0x6d, 0x47, 0xec, 0x33, 0x88, 0xc7, 0x8d, 0xa9, 0x10, 0xb3, 0xd6, 0x49,
- 0xca, 0x5a, 0x9a, 0xc1, 0x2b, 0xc9, 0x59, 0x15, 0x58, 0x05, 0x5b, 0x86, 0x77, 0xcd, 0x67, 0x74,
- 0x8f, 0x53, 0x74, 0x0d, 0xf4, 0x58, 0xdc, 0xff, 0x7c, 0x67, 0x69, 0x6b, 0x90, 0x3a, 0x50, 0x96,
- 0xcf, 0xd6, 0xa5, 0x71, 0xb3, 0xed, 0xf5, 0x78, 0x39, 0x8d, 0x21, 0x6f, 0xb6, 0xcb, 0xfe, 0xfb,
- 0xb0, 0x86, 0x66, 0x6f, 0x38, 0xa5, 0x2c, 0x24, 0x07, 0x6f, 0x43, 0x92, 0x7f, 0x09, 0x58, 0xe2,
- 0x56, 0x29, 0x12, 0x59, 0x46, 0xf7, 0xf3, 0x13, 0x47, 0xd2, 0x19, 0xef, 0xb5, 0x01, 0x92, 0xdb,
- 0x8e, 0xa0, 0x17, 0x22, 0x4f, 0xb5, 0xae, 0x16, 0x1b, 0x30, 0x6b, 0x41, 0xef, 0x27, 0x21, 0x3a,
- 0x46, 0x6c, 0x56, 0x35, 0x6f, 0x79, 0xe8, 0xa8, 0xb1, 0xba, 0x04, 0x55, 0x26, 0xa0, 0x7f, 0xf6,
- 0x57, 0x5b, 0x22, 0x8b, 0x7c, 0x06, 0xa7, 0x27, 0xb1, 0x92, 0x32, 0x67, 0x08, 0xf4, 0x9b, 0x11,
- 0x1c, 0xd9, 0x72, 0xfc, 0xbf, 0x33, 0x62, 0x9b, 0xf2, 0xa8, 0xba, 0xd9, 0xf4, 0x6f, 0x9d, 0x4f,
- 0xdf, 0x48, 0x45, 0x12, 0xe6, 0x90, 0xec, 0xbb, 0xc3, 0x23, 0x25, 0xa8, 0x33, 0x7b, 0xfd, 0x8e,
- 0xbd, 0x92, 0x8a, 0x68, 0x50, 0x52, 0x0c, 0x4f, 0x0a, 0x96, 0x2b, 0x44, 0x6c, 0x00, 0x9d, 0xac,
- 0x62, 0x48, 0xc2, 0x0d, 0xf8, 0x96, 0xa1, 0xc7, 0xfc, 0x95, 0x1d, 0x72, 0x1a, 0x6a, 0xdd, 0xbd,
- 0xb6, 0x73, 0x81, 0x49, 0xcf, 0x84, 0xbd, 0x27, 0x23, 0x9a, 0xc0, 0xb9, 0x59, 0x4d, 0xa1, 0x3e,
- 0x3f, 0xc0, 0xb1, 0x51, 0xc9, 0xf7, 0x3d, 0xab, 0x00, 0x7a, 0x33, 0xad, 0x10, 0x0a, 0xb2, 0x4b,
- 0x39, 0x46, 0xe9, 0xf8, 0xd9, 0x8c, 0x73, 0x4c, 0xd5, 0xa5, 0x6c, 0x54, 0x6e, 0x12, 0xa0, 0xc3,
- 0xe5, 0xbc, 0xbf, 0xa4, 0x6f, 0xa1, 0xf5, 0x2f, 0x74, 0x56, 0x1c, 0x65, 0xd1, 0xf3, 0xbd, 0xe4,
- 0x93, 0xa1, 0xc9, 0xa2, 0xf9, 0x2f, 0x87, 0x2f, 0x51, 0x4f, 0x85, 0x69, 0xf3, 0xad, 0x4c, 0xe6,
- 0x46, 0x7d, 0x14, 0x62, 0xeb, 0xe2, 0xa7, 0xb4, 0x38, 0x96, 0x2b, 0x04, 0x54, 0x27, 0x65, 0x47,
- 0x32, 0x12, 0x5f, 0x8e, 0x2e, 0x47, 0xd0, 0x1c, 0x0a, 0xb5, 0xcd, 0xff, 0x68, 0x9d, 0xb0, 0x5f,
- 0xf7, 0x00, 0xeb, 0x4f, 0x93, 0xee, 0x10, 0x79, 0xcf, 0xde, 0x1f, 0x58, 0xa0, 0xd0, 0x84, 0x5b,
- 0xac, 0x46, 0x65, 0x6a, 0x64, 0xaf, 0xa4, 0xe4, 0x89, 0xfa, 0x4b, 0xcb, 0xc7, 0x66, 0x2e, 0x2f,
- 0xa6, 0x94, 0xdc, 0xdf, 0x38, 0x01, 0x20, 0x79, 0x88, 0x1c, 0x53, 0x61, 0x5a, 0x60, 0x56, 0x02,
- 0xcd, 0xb7, 0x75, 0x29, 0x65, 0xd2, 0x3f, 0x9d, 0xd3, 0x37, 0xe9, 0x56, 0xd5, 0xfc, 0x27, 0x60,
- 0x7b, 0x3e, 0x57, 0x9b, 0xa7, 0xde, 0x4a, 0xc5, 0x91, 0x99, 0x49, 0xd9, 0x84, 0xbf, 0x68, 0x54,
- 0xf6, 0xda, 0x76, 0x86, 0xe6, 0x60, 0x4c, 0xda, 0xfd, 0xa5, 0x18, 0x96, 0x33, 0x78, 0x8d, 0xd5,
- 0x97, 0x91, 0x25, 0x86, 0xf1, 0x42, 0x62, 0xd3, 0x91, 0xe9, 0x75, 0x7a, 0xae, 0x0e, 0x2f, 0x0f,
- 0x2f, 0x0e, 0x2d, 0x36, 0x2c, 0xb6, 0xf9, 0xda, 0x02, 0x4f, 0xc3, 0x35, 0x56, 0xd8, 0xc5, 0x8d,
- 0xca, 0x87, 0x0e, 0x40, 0xb3, 0xd7, 0x9e, 0xb9, 0x9b, 0x69, 0x25, 0xf9, 0x05, 0xe5, 0x81, 0xb1,
- 0x6c, 0xb3, 0xf2, 0x92, 0x2a, 0xed, 0xb8, 0x65, 0x3f, 0xd9, 0x61, 0x50, 0x06, 0x5d, 0xb7, 0xae,
- 0xd9, 0x8c, 0x5b, 0x7b, 0x6d, 0x13, 0xf6, 0xcc, 0xb3, 0xd7, 0x56, 0x63, 0x9d, 0xb7, 0x40, 0xae,
- 0x27, 0xfb, 0x04, 0x5c, 0xee, 0xdd, 0xc2, 0x29, 0x64, 0xed, 0x24, 0x11, 0x3c, 0xca, 0x4c, 0x9e,
- 0x6c, 0xfe, 0xd5, 0x61, 0xf8, 0x2c, 0x38, 0xdf, 0x4e, 0xec, 0x00, 0x4d, 0x67, 0xbc, 0x2e, 0x20,
- 0x25, 0xaf, 0x20, 0x37, 0x96, 0xd0, 0x69, 0xea, 0x7c, 0x9a, 0xbd, 0xc3, 0xbe, 0x6e, 0x8f, 0x11,
- 0xbe, 0x6d, 0x7b, 0x8b, 0x35, 0x66, 0x89, 0x59, 0x5a, 0x3e, 0xfd, 0xd1, 0x1e, 0x77, 0x57, 0xac,
- 0x83, 0x74, 0x3a, 0x23, 0xed, 0xd1, 0x3e, 0xcf, 0x98, 0x0a, 0x76, 0x30, 0x64, 0x05, 0xd5, 0xba,
- 0x20, 0xf7, 0xa8, 0xc5, 0xc6, 0xf6, 0x00, 0xe7, 0xa3, 0x09, 0x77, 0x43, 0x1c, 0x03, 0xe2, 0x0a,
- 0x31, 0x6e, 0x89, 0x0d, 0xec, 0x9f, 0x5c, 0xb2, 0xcc, 0xcb, 0x3d, 0x16, 0xe0, 0x57, 0x86, 0x8e,
- 0x1d, 0x6d, 0x81, 0xf4, 0x79, 0x8e, 0xee, 0x24, 0x50, 0xeb, 0xaa, 0xb1, 0x72, 0x9d, 0xe5, 0x98,
- 0xf3, 0x55, 0xf7, 0xb7, 0xa6, 0x3f, 0xbe, 0xc6, 0x93, 0x49, 0xc0, 0xf0, 0x4d, 0x66, 0xf2, 0xd0,
- 0xdc, 0x38, 0x72, 0xfa, 0x4f, 0xd0, 0xce, 0xd9, 0xc9, 0xed, 0x97, 0x2f, 0x3e, 0x15, 0x0c, 0x7a,
- 0x73, 0xe7, 0xfb, 0x88, 0x61, 0xa9, 0xc1, 0xb6, 0x0c, 0xc0, 0x0d, 0x93, 0x8e, 0x64, 0x24, 0xd1,
- 0x16, 0x18, 0xb7, 0x74, 0x29, 0x4b, 0x5f, 0x81, 0x78, 0xc0, 0x08, 0x8e, 0x22, 0x79, 0x9b, 0x04,
- 0xe4, 0xfb, 0xb6, 0x58, 0xa7, 0x02, 0x6d, 0x7e, 0xa8, 0x75, 0x62, 0xff, 0x95, 0x31, 0x15, 0xb0,
- 0x06, 0xb7, 0xba, 0xd9, 0xb5, 0xe0, 0xa3, 0x09, 0x9c, 0x23, 0x95, 0x94, 0xaf, 0xf9, 0x0f, 0x94,
- 0x3d, 0xff, 0xf5, 0x8b, 0xdf, 0x1f, 0xa9, 0x78, 0xf3, 0x5f, 0xcf, 0xef, 0x5f, 0xe6, 0x16, 0xc3,
- 0x13, 0x61, 0x9a, 0xb0, 0x87, 0xbc, 0xbd, 0xb6, 0x52, 0x32, 0xfb, 0xec, 0x31, 0x13, 0xfe, 0x3e,
- 0x37, 0x6e, 0x45, 0x9d, 0x38, 0xe0, 0x79, 0xa1, 0xff, 0x61, 0xb3, 0x89, 0x38, 0x31, 0xc4, 0x49,
- 0x25, 0x87, 0x63, 0x12, 0x4d, 0xc6, 0x43, 0x79, 0xe9, 0xe5, 0x17, 0x47, 0x98, 0xcf, 0x1c, 0x53,
- 0xe5, 0x6b, 0xd3, 0x42, 0x85, 0xa5, 0xda, 0x2f, 0x45, 0x2e, 0x6b, 0xb2, 0x60, 0x09, 0x77, 0x92,
- 0xa9, 0x9f, 0x8a, 0x2a, 0xe4, 0xeb, 0xfc, 0x6b, 0x86, 0x5c, 0x37, 0x65, 0x1a, 0x2c, 0xb5, 0xe6,
- 0xa8, 0x51, 0x09, 0x9d, 0x13, 0xfa, 0x18, 0x34, 0x15, 0x24, 0x67, 0x43, 0x40, 0x2d, 0xd4, 0x45,
- 0xec, 0x9f, 0x7e, 0x3a, 0x75, 0x84, 0xd9, 0xd5, 0xd4, 0xd3, 0xeb, 0xdf, 0x6d, 0x82, 0x4a, 0xf7,
- 0x3d, 0x97, 0x4c, 0x36, 0x57, 0x67, 0x7d, 0x00, 0x4e, 0x8e, 0xdc, 0xf1, 0xaf, 0x4d, 0xa2, 0xd5,
- 0x5d, 0xe7, 0xdf, 0x76, 0x8c, 0x5b, 0xc0, 0x8a, 0x2b, 0x25, 0x15, 0xd0, 0x9f, 0xeb, 0xc3, 0xf2,
- 0x0f, 0x1e, 0xbd, 0x06, 0x1e, 0x65, 0x46, 0x24, 0x39, 0xd9, 0xa4, 0xe7, 0xf5, 0xf2, 0xdf, 0x32,
- 0x9f, 0xdb, 0xa5, 0x5c, 0xf0, 0xe4, 0x97, 0x61, 0x39, 0x18, 0x83, 0x4e, 0x16, 0xe2, 0xef, 0xcb,
- 0x26, 0x97, 0xa5, 0xe4, 0x07, 0xee, 0x74, 0x99, 0x1c, 0x8c, 0x6f, 0x3b, 0x76, 0x72, 0xb3, 0x32,
- 0xab, 0x02, 0xae, 0xff, 0x5a, 0x6a, 0x67, 0x6f, 0x19, 0x9e, 0xd7, 0x02, 0x9a, 0x9c, 0x4d, 0xfb,
- 0x59, 0xc9, 0x07, 0xe5, 0x4e, 0x6e, 0x2d, 0x8e, 0x9e, 0x90, 0xfd, 0xa7, 0x6e, 0x3f, 0x98, 0x7e,
- 0x50, 0x56, 0xc0, 0x9a, 0xa1, 0xc5, 0x06, 0xfc, 0xd4, 0x62, 0xbc, 0x47, 0x70, 0xa3, 0x47, 0xe9,
- 0x7d, 0x1b, 0xf4, 0x09, 0x8c, 0xaa, 0xab, 0xb4, 0x65, 0x1f, 0xfe, 0x97, 0xf9, 0xed, 0xc6, 0xa1,
- 0xa3, 0x49, 0xfd, 0x28, 0x40, 0x31, 0x7c, 0x9c, 0x99, 0x6f, 0xb2, 0xbf, 0x77, 0x1e, 0xfd, 0xee,
- 0xd5, 0xbf, 0x67, 0x22, 0xd4, 0x5d, 0xca, 0x72, 0x57, 0x3e, 0x67, 0xad, 0x2f, 0x0e, 0xbc, 0xae,
- 0x62, 0xef, 0x8a, 0x24, 0xd6, 0x33, 0xc6, 0x0a, 0x8c, 0x58, 0xb3, 0x59, 0xc8, 0xd5, 0x14, 0xa1,
- 0x2b, 0x70, 0x27, 0xec, 0xf9, 0x54, 0xe0, 0x0a, 0xa5, 0x3c, 0xe4, 0xa5, 0xfc, 0x14, 0x4a, 0xeb,
- 0x80, 0xde, 0x6c, 0xe4, 0x79, 0x28, 0x5f, 0xbe, 0x70, 0x02, 0xf6, 0x75, 0x72, 0x2f, 0x3b, 0x65,
- 0xe3, 0x1f, 0xee, 0x07, 0x07, 0x29, 0x8a, 0x8c, 0x37, 0x9b, 0x1f, 0x3a, 0xa0, 0xc7, 0x95, 0x58,
- 0xfd, 0xe2, 0x08, 0x5e, 0xeb, 0xea, 0xa7, 0x35, 0x45, 0xb3, 0xb9, 0xcc, 0xd4, 0x6c, 0xfe, 0xe9,
- 0xa7, 0xff, 0x78, 0xfe, 0x48, 0x83, 0xef, 0xb8, 0x8f, 0xc2, 0x8b, 0x9e, 0x80, 0x1b, 0xa0, 0x88,
- 0x70, 0x6c, 0xa0, 0xe6, 0x69, 0x6a, 0x36, 0x24, 0x51, 0x3d, 0x5e, 0x71, 0xfc, 0xf5, 0x3f, 0x5d,
- 0x21, 0x90, 0x9f, 0xda, 0xa8, 0xac, 0xb1, 0xe6, 0x83, 0xa6, 0x33, 0x67, 0xfd, 0x25, 0x8b, 0x50,
- 0xe6, 0x18, 0x5e, 0xa3, 0x32, 0xf5, 0x7c, 0x06, 0x5c, 0x5b, 0xdd, 0x3b, 0x43, 0x12, 0xed, 0x8e,
- 0x6b, 0x7a, 0x40, 0x93, 0x5a, 0x0d, 0x6a, 0x6f, 0x57, 0x25, 0xfd, 0xcd, 0xff, 0xc0, 0x16, 0x2b,
- 0x9c, 0xc2, 0x13, 0x4a, 0xb6, 0x70, 0x6a, 0xef, 0xf3, 0xf0, 0x50, 0xed, 0x6b, 0x93, 0x6e, 0xde,
- 0x02, 0x27, 0xec, 0x3d, 0xbb, 0x78, 0x2d, 0x6a, 0x54, 0x0d, 0x6c, 0xd6, 0xad, 0xee, 0x7b, 0x94,
- 0x5d, 0xfb, 0x8d, 0xfd, 0x0f, 0x9f, 0x3e, 0xea, 0xf2, 0x9d, 0x7d, 0x76, 0xf6, 0xd9, 0x7b, 0xcf,
- 0x4e, 0x3f, 0x3b, 0x4d, 0x63, 0x77, 0x9c, 0xc1, 0x94, 0x42, 0x91, 0xfa, 0xe9, 0x59, 0xd9, 0x05,
- 0x98, 0xcf, 0x3a, 0x9e, 0x9d, 0x65, 0xe6, 0x7b, 0xbf, 0x6a, 0xc6, 0xfe, 0x4c, 0x41, 0x02, 0x9e,
- 0xe0, 0xcf, 0x8c, 0x5b, 0xa4, 0x67, 0x8e, 0x48, 0xf1, 0xed, 0x23, 0x89, 0x66, 0x73, 0xa6, 0xef,
- 0xdd, 0x6b, 0x4f, 0xff, 0xeb, 0xa9, 0xe0, 0xce, 0xb3, 0xdc, 0xd1, 0xce, 0x5e, 0x33, 0xd4, 0xf9,
- 0xfb, 0x03, 0x7d, 0x6e, 0x88, 0x05, 0x9d, 0xa1, 0xd1, 0x1c, 0xc1, 0xf4, 0x95, 0x1d, 0x7c, 0xa9,
- 0xa4, 0xb1, 0x7c, 0xf4, 0xda, 0xde, 0xfb, 0x25, 0x48, 0x5b, 0x5e, 0xd3, 0xe3, 0xf4, 0xbd, 0x9d,
- 0x94, 0x8a, 0x37, 0x88, 0xde, 0x00, 0x9b, 0x35, 0x74, 0x53, 0xfa, 0x9d, 0xbb, 0x62, 0xdc, 0x37,
- 0x26, 0x1b, 0x6e, 0x18, 0x96, 0x5d, 0x91, 0x7d, 0x22, 0xbb, 0x4c, 0x21, 0xc5, 0xca, 0x60, 0xc3,
- 0xb3, 0xf7, 0x28, 0x0c, 0x3f, 0x69, 0x18, 0x6e, 0xf8, 0x3c, 0x39, 0x87, 0xd1, 0x94, 0x5d, 0xf9,
- 0x5d, 0x4f, 0x95, 0x76, 0x4c, 0xa5, 0xa0, 0xac, 0xa9, 0x46, 0x25, 0xa6, 0x8d, 0x7d, 0x96, 0x3f,
- 0x6b, 0x6f, 0x76, 0x24, 0x23, 0x89, 0xb2, 0x0c, 0xf7, 0x24, 0x5d, 0xca, 0xfa, 0xb4, 0xce, 0x9a,
- 0xce, 0x78, 0x99, 0x29, 0xbf, 0x3a, 0xea, 0x4c, 0xb2, 0x59, 0x66, 0xfa, 0x3a, 0xd8, 0x1f, 0xbc,
- 0x4e, 0xe9, 0x1d, 0x14, 0x3d, 0xe8, 0x79, 0xdd, 0xf1, 0x46, 0xd2, 0x6e, 0x60, 0x65, 0x53, 0x56,
- 0x71, 0x74, 0xef, 0xfd, 0x12, 0xd0, 0x96, 0xb3, 0xaa, 0xad, 0x4b, 0xbd, 0xf6, 0xb8, 0x77, 0x29,
- 0x2c, 0xc5, 0x06, 0x98, 0xc1, 0x43, 0x5e, 0xe8, 0x78, 0xf6, 0x6a, 0xf4, 0x51, 0xf0, 0xdf, 0x7d,
- 0xb2, 0xe5, 0x8e, 0xc5, 0xe1, 0xc5, 0xe1, 0xbb, 0xc3, 0x77, 0x3b, 0xa6, 0x1b, 0x3e, 0x97, 0x7d,
- 0xf2, 0xec, 0x2c, 0x75, 0xa2, 0x32, 0x48, 0x36, 0x5c, 0xb9, 0xf0, 0x8b, 0x8e, 0xdb, 0x43, 0x94,
- 0xb7, 0x3d, 0xcc, 0x9f, 0x77, 0x3b, 0x6e, 0x37, 0xdc, 0xb8, 0x6b, 0xee, 0xd6, 0x61, 0xda, 0xe7,
- 0xb5, 0xc0, 0x99, 0x1b, 0x1b, 0xa8, 0xa5, 0x63, 0xdc, 0xbb, 0x85, 0x65, 0xba, 0xfd, 0x66, 0xc4,
- 0xee, 0x39, 0xc2, 0x69, 0x56, 0x4f, 0x2b, 0x53, 0x45, 0x0d, 0x91, 0xcb, 0x4d, 0x02, 0x59, 0xea,
- 0x9b, 0x04, 0x77, 0xe3, 0x2c, 0x6d, 0x6a, 0x30, 0x88, 0xec, 0x82, 0xbf, 0x09, 0x68, 0xf6, 0xbe,
- 0xff, 0x97, 0xcd, 0x4e, 0x84, 0xe1, 0x51, 0x9e, 0x7f, 0x26, 0xfb, 0xe3, 0x6b, 0x7b, 0x7f, 0x53,
- 0x02, 0x71, 0x71, 0xa4, 0x2d, 0x81, 0x37, 0xbe, 0x94, 0x14, 0x4a, 0xe0, 0x26, 0x01, 0xcf, 0x26,
- 0x7c, 0xb2, 0x52, 0xb2, 0x3d, 0x06, 0xfd, 0xb4, 0x36, 0x82, 0x21, 0xcf, 0xa2, 0x3b, 0xe4, 0x62,
- 0xe6, 0xcd, 0x8e, 0x45, 0x0a, 0xcd, 0x61, 0xea, 0x34, 0x3d, 0x4d, 0x9f, 0xae, 0x67, 0x65, 0x57,
- 0x3a, 0x6e, 0x0c, 0x2f, 0x56, 0x2c, 0xc3, 0x6f, 0xe3, 0xcc, 0x0c, 0xd1, 0xff, 0xfd, 0xcd, 0x7c,
- 0xc7, 0xe2, 0xa3, 0xc9, 0xdf, 0x9b, 0x21, 0x92, 0x34, 0x6e, 0xe9, 0xb5, 0x41, 0xa7, 0xc4, 0x90,
- 0x17, 0xba, 0xb2, 0x71, 0x53, 0xc8, 0x12, 0xec, 0x8b, 0x7f, 0x1d, 0xe4, 0x7e, 0xd7, 0x16, 0x68,
- 0x67, 0x62, 0xa9, 0xce, 0xf8, 0xb9, 0x00, 0xf7, 0xf3, 0xfe, 0xc0, 0x4d, 0x3a, 0x9e, 0x73, 0x2d,
- 0xad, 0xa2, 0x64, 0x55, 0x9d, 0xce, 0xcd, 0x74, 0x33, 0x1e, 0x1b, 0x98, 0x55, 0x41, 0x6e, 0x4b,
- 0x8f, 0xb9, 0xc5, 0x56, 0xeb, 0x0a, 0x79, 0xe1, 0x5b, 0xf4, 0xb9, 0xef, 0x39, 0xa0, 0x97, 0x4a,
- 0x3e, 0xb2, 0xa9, 0xc1, 0xc6, 0x2d, 0xd0, 0xb1, 0x66, 0xd2, 0xfd, 0x17, 0xd7, 0x7f, 0x39, 0xd8,
- 0x7e, 0x96, 0xb1, 0xf5, 0x64, 0xbc, 0xb8, 0x09, 0x75, 0xc6, 0xee, 0x3d, 0x96, 0x34, 0x53, 0x84,
- 0x6e, 0x9e, 0xf6, 0x47, 0x5a, 0x6c, 0x33, 0x02, 0x1f, 0x6b, 0xcb, 0xb0, 0xed, 0xd8, 0x76, 0xcc,
- 0x5b, 0x84, 0xd6, 0x41, 0xb7, 0x0e, 0x3c, 0xb2, 0xe5, 0xf8, 0x43, 0xfb, 0xac, 0xaa, 0x51, 0xd9,
- 0x48, 0xa2, 0xd9, 0xa5, 0x3c, 0xb1, 0x3e, 0x7c, 0x97, 0x92, 0xcc, 0xcb, 0xcf, 0xde, 0x03, 0x3d,
- 0x29, 0xbb, 0xdc, 0xf0, 0xf9, 0xd0, 0xdd, 0xe9, 0xf5, 0x6f, 0x6c, 0xec, 0x3b, 0xb8, 0x19, 0xb3,
- 0x9c, 0x58, 0xed, 0xb8, 0xfd, 0xca, 0x78, 0x6c, 0x00, 0xb7, 0xde, 0xb3, 0x4f, 0x7a, 0xa8, 0x55,
- 0xf0, 0xcc, 0x51, 0x27, 0x10, 0x7f, 0x62, 0x5a, 0xe8, 0x36, 0x1c, 0x61, 0x64, 0xad, 0x3e, 0x0a,
- 0x1c, 0x81, 0xec, 0x64, 0x99, 0x79, 0xc2, 0x89, 0x05, 0x0f, 0xfd, 0x1d, 0xe8, 0xd9, 0xa5, 0x9c,
- 0xb7, 0xa0, 0x88, 0x4e, 0x93, 0x2e, 0x75, 0xad, 0x71, 0x6b, 0x3a, 0xdb, 0x28, 0xc4, 0x04, 0x09,
- 0xff, 0x46, 0x98, 0x8d, 0xcc, 0xa2, 0x39, 0x18, 0x0f, 0x79, 0xc7, 0x2d, 0xf9, 0xda, 0x43, 0x23,
- 0x78, 0x6c, 0x60, 0x29, 0xf8, 0x28, 0x78, 0x73, 0xe1, 0xe6, 0x64, 0xf8, 0x67, 0xd4, 0x0a, 0x1c,
- 0xa7, 0xfd, 0x4a, 0x5e, 0x44, 0xf3, 0xd7, 0x6f, 0xa4, 0x66, 0x7f, 0xed, 0xf6, 0x10, 0x6a, 0xcb,
- 0x54, 0xed, 0x81, 0x2a, 0x85, 0xb7, 0x1d, 0xc2, 0x27, 0x6b, 0xb1, 0x65, 0x62, 0xa0, 0xeb, 0x52,
- 0x2e, 0x47, 0x86, 0x17, 0x1b, 0x7e, 0xc1, 0x60, 0x49, 0x49, 0xe5, 0x85, 0x1b, 0xc3, 0xcb, 0xce,
- 0x08, 0xf6, 0x76, 0xfa, 0x93, 0xe3, 0x9f, 0xb6, 0xaf, 0x0f, 0x2f, 0x1e, 0xb9, 0x3d, 0x79, 0xb3,
- 0x9c, 0x92, 0x86, 0x25, 0xea, 0x74, 0xc2, 0xb4, 0xa9, 0x7a, 0x4b, 0x83, 0xc5, 0x06, 0xb8, 0x15,
- 0xee, 0x0f, 0xf0, 0x3d, 0xf9, 0x2a, 0x2d, 0x8a, 0xdd, 0x0c, 0xc6, 0xf8, 0x99, 0x3d, 0x0a, 0xf2,
- 0xba, 0x07, 0xbd, 0x7b, 0x35, 0x25, 0x77, 0x4b, 0x41, 0x06, 0x33, 0xb2, 0x62, 0x46, 0xd2, 0xe6,
- 0x52, 0x70, 0xdc, 0x32, 0xa6, 0x12, 0x7e, 0x17, 0x88, 0x02, 0x89, 0xa3, 0xb9, 0x49, 0xd4, 0x58,
- 0x2b, 0x22, 0x0d, 0xeb, 0xb2, 0xbb, 0x70, 0x36, 0x85, 0x4f, 0xf3, 0x63, 0x24, 0x80, 0xe5, 0x2f,
- 0xdf, 0xd8, 0xeb, 0xbb, 0x12, 0x74, 0x8b, 0xbc, 0x66, 0xe8, 0xb5, 0xc5, 0x29, 0xdb, 0x5a, 0xc8,
- 0x76, 0x3d, 0x82, 0xa3, 0x1d, 0x3b, 0x6f, 0x11, 0x3e, 0x1b, 0x92, 0x89, 0xa7, 0x61, 0xe1, 0xbb,
- 0xab, 0x4d, 0xcb, 0x21, 0x56, 0x2e, 0x19, 0xa9, 0xbc, 0x3d, 0xbd, 0xde, 0xef, 0x5b, 0xc9, 0xb0,
- 0x0e, 0xdb, 0x76, 0x67, 0x04, 0xe2, 0xd6, 0x47, 0x96, 0xfb, 0xfd, 0xdf, 0x87, 0x27, 0x3d, 0x5d,
- 0xca, 0x4c, 0xfa, 0x49, 0x41, 0x9e, 0x0b, 0xb0, 0x6b, 0xbc, 0xed, 0xe0, 0xa3, 0x5c, 0x66, 0x42,
- 0xb1, 0xf1, 0x72, 0x17, 0xf7, 0xcd, 0x8c, 0x58, 0x8f, 0x99, 0x95, 0xb0, 0x54, 0x1f, 0x79, 0xcd,
- 0x90, 0xeb, 0x76, 0x85, 0x43, 0xf2, 0x5c, 0x20, 0xaa, 0xe6, 0xe3, 0x66, 0xc4, 0xa2, 0xea, 0x7b,
- 0x76, 0x88, 0x5c, 0x8a, 0x5b, 0xbb, 0xe0, 0xd9, 0x4d, 0xd8, 0xda, 0x23, 0x43, 0xab, 0xa0, 0x69,
- 0x9e, 0x75, 0x84, 0x1b, 0x04, 0x68, 0xbe, 0xf4, 0xe8, 0xb5, 0x32, 0xd3, 0xde, 0xc6, 0xf1, 0x50,
- 0xa6, 0x4e, 0x99, 0x09, 0xbe, 0x71, 0x9f, 0x5b, 0xc8, 0xc2, 0x5a, 0xa5, 0x8d, 0xd0, 0x71, 0x33,
- 0x61, 0x3d, 0x23, 0x68, 0x4b, 0xf8, 0x79, 0xc8, 0xcb, 0x7f, 0xb7, 0x06, 0xab, 0xbd, 0x39, 0xbd,
- 0x3e, 0x74, 0x9b, 0xd6, 0x97, 0xe0, 0x87, 0x7c, 0xd2, 0x71, 0x63, 0x68, 0x71, 0x39, 0xf2, 0xfb,
- 0x0c, 0x7c, 0x3b, 0x46, 0x6c, 0xc1, 0xbd, 0x1c, 0x5d, 0x0e, 0x4d, 0xaf, 0x4f, 0x87, 0xea, 0x23,
- 0xe5, 0xae, 0x52, 0x32, 0xb3, 0xa5, 0xa1, 0xc1, 0xd6, 0x0c, 0xec, 0x1d, 0x23, 0xdf, 0x32, 0x9d,
- 0xc1, 0x27, 0x68, 0xef, 0xa2, 0x3e, 0xc6, 0xff, 0x06, 0x5d, 0x4a, 0x24, 0xab, 0x30, 0x39, 0x4d,
- 0x61, 0xa4, 0x9e, 0xaf, 0x4a, 0x9b, 0x9b, 0xab, 0x16, 0x9d, 0xd6, 0xd0, 0x29, 0x48, 0xc1, 0xfb,
- 0x26, 0x70, 0xaf, 0xdc, 0xea, 0x6a, 0xa7, 0xbb, 0x37, 0x0e, 0xc6, 0xa4, 0x64, 0x9d, 0x00, 0x9a,
- 0x0f, 0xed, 0x43, 0xa1, 0xe1, 0xe5, 0x8e, 0x69, 0xd9, 0x15, 0xca, 0x06, 0x14, 0xa0, 0xd9, 0x2e,
- 0xeb, 0x31, 0xef, 0x6d, 0x37, 0x45, 0xd0, 0x96, 0xcf, 0x6b, 0x7b, 0xcc, 0xe5, 0x94, 0xff, 0xdf,
- 0x6b, 0x13, 0x6a, 0xfc, 0x1a, 0x2b, 0x3c, 0xe5, 0xcb, 0x29, 0x7d, 0x06, 0xd6, 0x0c, 0x68, 0xf7,
- 0x4f, 0xd8, 0xf9, 0xba, 0x75, 0x06, 0x9f, 0xf2, 0x4f, 0xaf, 0x5e, 0x98, 0x6e, 0xb8, 0x42, 0xf9,
- 0x91, 0xef, 0x3d, 0xeb, 0x90, 0x0d, 0x77, 0x4c, 0x4f, 0xaf, 0x9e, 0x08, 0x45, 0x33, 0x70, 0x47,
- 0x96, 0x92, 0x84, 0x6f, 0x39, 0x46, 0xa1, 0x19, 0x75, 0x46, 0x1f, 0xe6, 0x8c, 0xb9, 0x94, 0x92,
- 0xc0, 0x4d, 0x4a, 0x9d, 0xe7, 0x82, 0x4c, 0x74, 0x05, 0x09, 0x3d, 0x4d, 0x7c, 0x71, 0x3e, 0x2f,
- 0x93, 0x11, 0x2b, 0x77, 0xb1, 0x48, 0xfa, 0x12, 0xe8, 0x36, 0x03, 0x76, 0x69, 0x6c, 0x60, 0x2a,
- 0x28, 0xe6, 0x93, 0xb2, 0x48, 0xf2, 0xa5, 0x19, 0xf2, 0x80, 0xa8, 0x3d, 0xcb, 0xc8, 0x79, 0x7b,
- 0xec, 0x0b, 0x89, 0xf5, 0xb9, 0x2b, 0x44, 0xf9, 0x4d, 0x27, 0xa0, 0x79, 0x03, 0xed, 0x6a, 0xe4,
- 0x6d, 0x03, 0xa2, 0x43, 0x32, 0xfd, 0xc7, 0x73, 0xfa, 0x59, 0x55, 0xfa, 0xed, 0xf5, 0xee, 0x0c,
- 0x96, 0x13, 0x7d, 0x7d, 0xa0, 0xcf, 0xfd, 0x75, 0xb0, 0xc7, 0xcc, 0x5f, 0x77, 0x0d, 0x86, 0xb4,
- 0x65, 0xb9, 0x4b, 0x88, 0xf0, 0x84, 0x1d, 0x76, 0xea, 0xcd, 0xf8, 0xb8, 0x80, 0xb1, 0x1e, 0x7b,
- 0xbb, 0x62, 0x7d, 0x9a, 0x7a, 0x02, 0xf0, 0x49, 0x28, 0xa9, 0xa4, 0xed, 0x9e, 0xe5, 0xd0, 0x5f,
- 0xbb, 0x84, 0x76, 0x31, 0x9a, 0xb3, 0x10, 0x55, 0x8f, 0x53, 0x68, 0xc6, 0x96, 0x02, 0x4d, 0x39,
- 0x7b, 0x18, 0xac, 0x10, 0xf7, 0xec, 0xe8, 0x3c, 0xe7, 0x7f, 0xd6, 0xac, 0x0a, 0x4e, 0x06, 0xc2,
- 0xcf, 0x5f, 0xfb, 0x6e, 0x1d, 0x67, 0xc1, 0x00, 0x7f, 0xdd, 0x0c, 0xde, 0xa4, 0x9b, 0xb0, 0x23,
- 0xb6, 0x7c, 0x71, 0x2c, 0x41, 0x4f, 0x36, 0xe9, 0xb8, 0xcf, 0xd8, 0x24, 0xd6, 0x2d, 0x83, 0x80,
- 0x24, 0x9a, 0x94, 0xb6, 0x96, 0x6e, 0x0b, 0x6d, 0x12, 0x93, 0x2e, 0x1a, 0x4d, 0xb0, 0xe9, 0x2f,
- 0x23, 0x34, 0x59, 0x0f, 0xf3, 0x9f, 0xdf, 0x6f, 0xd2, 0xed, 0x55, 0xd7, 0x5a, 0x96, 0x23, 0x0b,
- 0x22, 0xb1, 0x84, 0x5f, 0xb8, 0xf7, 0x14, 0x24, 0xac, 0x84, 0x93, 0xda, 0xfd, 0xfc, 0x75, 0x1c,
- 0xc1, 0x11, 0xc2, 0xdf, 0x87, 0x85, 0xf9, 0xc4, 0xe3, 0xe6, 0xf6, 0x10, 0x6d, 0xf9, 0x20, 0x2c,
- 0xa9, 0x13, 0x96, 0xb2, 0x7b, 0x42, 0xf3, 0x0c, 0x0f, 0xfa, 0x0a, 0x01, 0x59, 0x6c, 0xac, 0x26,
- 0x6a, 0xd2, 0x2d, 0x05, 0xd1, 0x2a, 0x85, 0x3c, 0xdc, 0x29, 0x09, 0xf1, 0xb0, 0x79, 0x0b, 0xdc,
- 0x8e, 0x72, 0x9f, 0xd7, 0xa5, 0x64, 0xf7, 0x13, 0x7f, 0x8f, 0x6d, 0x19, 0xe0, 0x9e, 0x91, 0xcf,
- 0xb1, 0x5e, 0x4a, 0x86, 0xbc, 0x9c, 0xd6, 0xdb, 0x08, 0x6f, 0x12, 0xd0, 0xef, 0x2d, 0x9c, 0x90,
- 0x92, 0x03, 0x92, 0xa0, 0xed, 0x38, 0xfe, 0x29, 0xa3, 0x20, 0x5b, 0x6c, 0xed, 0x1c, 0x92, 0x71,
- 0xb0, 0xf2, 0xa4, 0x22, 0x09, 0x73, 0x4c, 0x45, 0xe9, 0x90, 0x74, 0x34, 0x8f, 0x3a, 0x65, 0x53,
- 0x6f, 0x7d, 0xf2, 0x3e, 0x7b, 0x7b, 0x8d, 0x9e, 0x85, 0x9b, 0xf2, 0x82, 0xb1, 0x44, 0x77, 0x5d,
- 0xdf, 0x39, 0xe0, 0x96, 0x57, 0x18, 0x27, 0x98, 0xd3, 0x83, 0x7d, 0xff, 0x34, 0x2c, 0xf4, 0xbb,
- 0x67, 0x55, 0x28, 0xdf, 0x29, 0x9e, 0xa2, 0x2d, 0x7f, 0x74, 0x38, 0x59, 0xcb, 0xa7, 0x43, 0x76,
- 0xa1, 0x81, 0x3e, 0x61, 0x97, 0xfc, 0xac, 0x75, 0xd4, 0xa4, 0xab, 0xa3, 0x7c, 0x57, 0xf6, 0x9c,
- 0xdc, 0x32, 0x20, 0x6f, 0x23, 0x92, 0x78, 0xe8, 0xe0, 0x2c, 0x8d, 0x46, 0x25, 0xe4, 0xa4, 0x0f,
- 0xc6, 0xf8, 0x6c, 0xdb, 0xc0, 0x3a, 0x92, 0x1a, 0x93, 0xa3, 0xbc, 0x7e, 0xbb, 0x90, 0x2b, 0x0d,
- 0x18, 0x2d, 0x58, 0xbd, 0x0a, 0x73, 0x2a, 0xb8, 0xed, 0xe0, 0x5e, 0x67, 0x1a, 0xe1, 0x04, 0x44,
- 0x21, 0x21, 0x0f, 0x6b, 0x81, 0xf6, 0x6b, 0x5b, 0xdd, 0xdc, 0xce, 0x5c, 0x21, 0xa0, 0xe6, 0x80,
- 0xfa, 0xcb, 0xa4, 0x54, 0xb6, 0xba, 0x67, 0x24, 0xd8, 0xb1, 0xfc, 0xd5, 0xc0, 0xde, 0x26, 0x16,
- 0x92, 0x68, 0x5e, 0xe0, 0xd0, 0x1c, 0x94, 0xfd, 0xcf, 0xbb, 0xe8, 0xf6, 0x7a, 0x06, 0x2f, 0x25,
- 0xc1, 0xb7, 0xad, 0x62, 0x26, 0xa6, 0x05, 0xdf, 0x73, 0xe7, 0x48, 0xc2, 0xba, 0xc0, 0x4d, 0x2b,
- 0x8a, 0xc4, 0x6e, 0x3b, 0x84, 0x96, 0x37, 0xca, 0x88, 0x69, 0x0b, 0x08, 0x11, 0xae, 0x36, 0xa1,
- 0xd5, 0xe5, 0x5b, 0x90, 0x20, 0x17, 0x71, 0xcf, 0xf4, 0x7a, 0x07, 0x58, 0x3e, 0x97, 0xe9, 0xb8,
- 0x1d, 0x78, 0x96, 0xa1, 0xb7, 0x6e, 0xa2, 0x13, 0x16, 0x7c, 0xaf, 0x48, 0x82, 0x8b, 0x43, 0x40,
- 0xb5, 0x17, 0xf2, 0xe4, 0xd6, 0x79, 0x32, 0xdf, 0x0d, 0xd2, 0x4a, 0x9d, 0x03, 0xdc, 0x1d, 0x07,
- 0x48, 0x20, 0xf2, 0x7e, 0xf8, 0x1a, 0xdb, 0x88, 0xf5, 0x07, 0x5e, 0x8d, 0xf2, 0xa5, 0x97, 0xad,
- 0x48, 0x67, 0xcf, 0x53, 0xe8, 0x2b, 0xc2, 0x21, 0x9b, 0x49, 0x0e, 0x9b, 0xcd, 0x8d, 0x4a, 0x85,
- 0xe0, 0x5e, 0x96, 0x7d, 0x76, 0xc8, 0xad, 0x67, 0xe2, 0x10, 0x0c, 0x96, 0x71, 0x2f, 0xca, 0x26,
- 0xc8, 0x67, 0xd2, 0xd5, 0x7e, 0xbe, 0xe5, 0xd0, 0xd0, 0xf2, 0x85, 0x1b, 0x32, 0xca, 0xa6, 0x45,
- 0x71, 0x4d, 0x40, 0xb3, 0xfd, 0xe8, 0xdf, 0x9d, 0xdf, 0xba, 0x84, 0x69, 0x21, 0x3a, 0xb3, 0xed,
- 0x58, 0xf0, 0x84, 0xbc, 0x68, 0x42, 0xcc, 0xa8, 0x49, 0xb7, 0x73, 0x34, 0x59, 0xf6, 0x65, 0xdc,
- 0x0a, 0x77, 0xe4, 0xa9, 0xf7, 0x44, 0xd0, 0xbb, 0x09, 0xea, 0x59, 0xf8, 0xf6, 0x45, 0xb7, 0x0e,
- 0x71, 0x3a, 0x0e, 0xc6, 0x84, 0xfc, 0x0e, 0x4d, 0x3a, 0xb0, 0x7c, 0xa8, 0x5d, 0x78, 0x85, 0xc2,
- 0xf2, 0xb2, 0xec, 0x4a, 0xc7, 0xf4, 0xf0, 0x6a, 0x7b, 0x68, 0x9c, 0xd1, 0xbf, 0x0a, 0x12, 0xb8,
- 0x7f, 0x7b, 0x99, 0x38, 0x04, 0xb0, 0x3a, 0xa3, 0xb5, 0xde, 0xe0, 0x9d, 0xd3, 0x10, 0x39, 0xb9,
- 0x49, 0x5b, 0x8c, 0x5c, 0x5d, 0xcf, 0x08, 0xfe, 0x15, 0xad, 0x2d, 0xdb, 0x02, 0x7c, 0xad, 0xab,
- 0x20, 0x9d, 0x71, 0xfe, 0xbe, 0x5b, 0x21, 0x1e, 0x3a, 0x22, 0x02, 0xa4, 0x84, 0x33, 0x7d, 0xa4,
- 0x46, 0xb7, 0xf8, 0x53, 0x41, 0xc6, 0x79, 0xa7, 0xb5, 0x33, 0xde, 0xea, 0xce, 0xec, 0x2f, 0x89,
- 0xcb, 0xe6, 0x9c, 0x9e, 0x5a, 0x13, 0x4a, 0xef, 0x50, 0x36, 0x04, 0x65, 0x0f, 0x86, 0x4f, 0x73,
- 0x27, 0xed, 0x37, 0x9d, 0xf3, 0x96, 0x16, 0x1b, 0xe1, 0x87, 0xde, 0xd8, 0xf5, 0xd1, 0x8a, 0x68,
- 0x7d, 0xd4, 0x49, 0xed, 0xbe, 0x8a, 0x68, 0xad, 0xab, 0x2a, 0x67, 0xbf, 0x93, 0x5c, 0x83, 0xa9,
- 0x1c, 0xb8, 0xd4, 0x6b, 0x7f, 0xd9, 0xdf, 0x1f, 0x10, 0xab, 0xa7, 0x31, 0xfe, 0x2f, 0x75, 0xd7,
- 0x1b, 0xd3, 0xd6, 0xb9, 0xde, 0xf7, 0x21, 0xd2, 0xfc, 0x21, 0x52, 0x7d, 0x75, 0xd9, 0x7a, 0xba,
- 0x10, 0x6e, 0x33, 0xa5, 0x51, 0xb8, 0x82, 0x28, 0x08, 0x37, 0x17, 0x6e, 0x80, 0x0a, 0x22, 0x2a,
- 0x85, 0x96, 0xae, 0xd0, 0x90, 0xc5, 0x21, 0x36, 0x62, 0x5e, 0x5a, 0xa5, 0x16, 0xb7, 0xca, 0xb8,
- 0xb4, 0x23, 0x80, 0x2d, 0x51, 0x2f, 0xd1, 0x45, 0x2e, 0x59, 0x99, 0x21, 0x0a, 0x35, 0xb6, 0x84,
- 0xe6, 0x20, 0xa5, 0x72, 0xd8, 0x98, 0x6c, 0x26, 0xdf, 0xfa, 0xf8, 0x03, 0xba, 0xf6, 0x87, 0x48,
- 0xc7, 0x9b, 0x90, 0xec, 0xde, 0x90, 0x1c, 0x7f, 0x40, 0xca, 0x99, 0x94, 0x49, 0xe7, 0x4e, 0x54,
- 0x73, 0x54, 0x27, 0x61, 0xef, 0xef, 0x7d, 0x7d, 0x7c, 0xce, 0xf1, 0x1f, 0x02, 0xac, 0xba, 0x52,
- 0x79, 0xd4, 0x2a, 0xc1, 0xc4, 0x1c, 0xbf, 0xcf, 0xfb, 0xfc, 0xff, 0x3d, 0xcf, 0x43, 0x22, 0x84,
- 0xf9, 0x3c, 0x9e, 0x34, 0x27, 0x9e, 0x2d, 0xb2, 0x96, 0xad, 0x49, 0x67, 0x8c, 0x58, 0x4b, 0xf0,
- 0x92, 0x48, 0xa5, 0x73, 0xd9, 0x9f, 0x34, 0xf3, 0x8c, 0x2b, 0x98, 0xe4, 0x80, 0x5c, 0xab, 0x62,
- 0xdf, 0x26, 0x8d, 0x38, 0x7b, 0x50, 0x93, 0xc6, 0x7b, 0x59, 0x34, 0x2a, 0x5e, 0x8e, 0x96, 0x4b,
- 0x5c, 0x9c, 0x69, 0x62, 0xad, 0x8e, 0x7b, 0x72, 0x31, 0x92, 0x52, 0xf9, 0xcd, 0x7a, 0x54, 0xb4,
- 0x3c, 0xd3, 0xf2, 0xd1, 0x22, 0x4f, 0x94, 0x54, 0x60, 0x26, 0x76, 0xcc, 0xa7, 0x5f, 0x6f, 0xb0,
- 0x14, 0xb4, 0x73, 0xb5, 0x74, 0xd2, 0xb5, 0xff, 0x7a, 0x18, 0xb4, 0xca, 0x86, 0xc0, 0xb8, 0xd9,
- 0xc6, 0xb8, 0x79, 0x8a, 0x71, 0x53, 0x3c, 0x95, 0x5e, 0xc0, 0x56, 0xea, 0x16, 0xa9, 0x2f, 0x98,
- 0x1c, 0xeb, 0xb6, 0xdf, 0x1b, 0x46, 0xad, 0x02, 0xbf, 0xaf, 0xc7, 0xdd, 0x59, 0xd8, 0xdf, 0xb2,
- 0x57, 0x5e, 0x6e, 0x16, 0x32, 0xb1, 0x5c, 0x7c, 0xe7, 0xfe, 0x53, 0x96, 0x3f, 0xa6, 0x9a, 0xa7,
- 0x44, 0x52, 0x26, 0x8d, 0x2b, 0x6e, 0x5f, 0xda, 0xb1, 0x8a, 0xcc, 0x3a, 0x95, 0xca, 0x9b, 0x8e,
- 0x55, 0x5f, 0xc6, 0xb4, 0xc0, 0x38, 0x80, 0x18, 0x1e, 0xbe, 0x8a, 0x72, 0x57, 0xd8, 0x44, 0x3c,
- 0x44, 0x0e, 0x7d, 0xc1, 0x41, 0x8d, 0x97, 0x13, 0xa6, 0xf2, 0xa0, 0x9d, 0x1b, 0xd1, 0x59, 0xcb,
- 0x74, 0xb1, 0x7e, 0x93, 0xcc, 0x8a, 0xe7, 0xa4, 0x4b, 0x95, 0x14, 0x20, 0x35, 0xf4, 0xb2, 0xc7,
- 0xf8, 0x30, 0x91, 0x1d, 0x15, 0xaa, 0x02, 0xd3, 0xc3, 0xc5, 0xbb, 0xdf, 0x8a, 0xe3, 0xe2, 0x62,
- 0x52, 0xa2, 0x54, 0x9e, 0xe8, 0xd6, 0x83, 0xb6, 0xdd, 0xf5, 0x57, 0x6f, 0x12, 0xcf, 0x0e, 0x19,
- 0xc6, 0x62, 0xf9, 0x6d, 0x37, 0x74, 0xdb, 0x5a, 0x49, 0x14, 0xed, 0x58, 0x66, 0x3e, 0x21, 0xe3,
- 0xa6, 0x78, 0xaa, 0x66, 0xc0, 0xb9, 0x8a, 0xaa, 0xfa, 0x55, 0xb7, 0xd1, 0x35, 0x12, 0x44, 0x1e,
- 0x71, 0xc5, 0x83, 0x0d, 0x55, 0x7c, 0x36, 0x1c, 0x82, 0x37, 0xbd, 0x77, 0x4e, 0xea, 0xad, 0xa5,
- 0xf6, 0x5c, 0x4b, 0x09, 0x1d, 0x67, 0xf4, 0x33, 0xe6, 0xfd, 0x3a, 0x6c, 0xc6, 0xd6, 0x9e, 0xf9,
- 0x5c, 0x20, 0x86, 0x27, 0x06, 0x2f, 0x3f, 0x81, 0xdf, 0xe3, 0x23, 0x91, 0xe5, 0x90, 0x5d, 0xe1,
- 0x34, 0xe6, 0x33, 0x8d, 0x0a, 0x4a, 0x5e, 0x0d, 0x93, 0xad, 0x70, 0x5a, 0xc8, 0x6c, 0xab, 0xef,
- 0x71, 0xbc, 0x63, 0x43, 0x24, 0x51, 0x9e, 0xae, 0x8a, 0x3c, 0xd5, 0x4b, 0x33, 0x02, 0x92, 0x8a,
- 0x99, 0xc2, 0x93, 0xf4, 0x05, 0xd5, 0x7b, 0x34, 0x58, 0x76, 0x8e, 0xd7, 0x05, 0x61, 0xcb, 0x8b,
- 0xb8, 0x7c, 0x8d, 0xeb, 0xac, 0xad, 0xd6, 0xd5, 0xb9, 0x98, 0x75, 0xd8, 0xe9, 0x93, 0x2e, 0x1a,
- 0xa7, 0x87, 0xfb, 0x82, 0x55, 0x81, 0xe4, 0xd8, 0xee, 0x50, 0x23, 0x93, 0x24, 0xf6, 0xd9, 0xf2,
- 0x8e, 0x0a, 0x39, 0x71, 0x24, 0xa8, 0x7d, 0xce, 0xc2, 0xf3, 0x0d, 0x5b, 0xd2, 0xfe, 0x84, 0x53,
- 0xcb, 0xcd, 0xb6, 0xb7, 0x9c, 0xb1, 0x74, 0x26, 0x3b, 0x17, 0x44, 0xec, 0x3b, 0x64, 0x07, 0x2a,
- 0x81, 0x8b, 0x23, 0xb7, 0xcf, 0x93, 0xfb, 0x87, 0xfb, 0xb3, 0x1f, 0x5e, 0x22, 0x13, 0xfb, 0x9b,
- 0x5e, 0x99, 0xc4, 0x96, 0x91, 0xd4, 0xce, 0x1d, 0x18, 0x83, 0x06, 0x58, 0x3c, 0xc5, 0x1b, 0xc0,
- 0x36, 0x34, 0xed, 0xab, 0xc7, 0x3b, 0xae, 0xc5, 0x89, 0xe7, 0x03, 0x9f, 0xed, 0x13, 0xea, 0xf7,
- 0x2c, 0xf9, 0x93, 0x91, 0xc2, 0x26, 0x1f, 0x96, 0x27, 0x52, 0x23, 0x71, 0x36, 0x0b, 0x98, 0x65,
- 0xcb, 0xd5, 0x1b, 0x4c, 0xb3, 0x72, 0xe4, 0x9d, 0x57, 0xbc, 0x88, 0x4b, 0x18, 0x8d, 0x84, 0x60,
- 0x57, 0xb9, 0xb8, 0xf6, 0x54, 0xb1, 0x03, 0x51, 0xfd, 0xdb, 0xf5, 0x86, 0xdc, 0xe3, 0x62, 0xbf,
- 0x06, 0x73, 0xb7, 0x36, 0xf3, 0x95, 0x1d, 0x64, 0xf5, 0xf4, 0xaf, 0xee, 0xb4, 0x61, 0x91, 0x3d,
- 0x09, 0x22, 0xee, 0x4d, 0x6e, 0x77, 0x55, 0x4d, 0xc2, 0x79, 0xfb, 0xbc, 0xc0, 0xcb, 0x19, 0x19,
- 0x37, 0xdc, 0x54, 0x26, 0x9a, 0x5e, 0xe3, 0x1a, 0x5c, 0x0e, 0xc2, 0x4d, 0xc7, 0x12, 0xf5, 0xf1,
- 0xcf, 0x23, 0x53, 0xed, 0xf4, 0x67, 0x24, 0x9f, 0x3c, 0xe3, 0x81, 0x66, 0x3d, 0x48, 0x64, 0x24,
- 0x39, 0x36, 0x17, 0xca, 0x46, 0x81, 0xaf, 0xc8, 0x89, 0xf2, 0xd8, 0x81, 0x23, 0xfb, 0xe1, 0x25,
- 0x8b, 0x2d, 0xdf, 0x27, 0xb1, 0xe5, 0x03, 0xb1, 0xb8, 0xb2, 0x50, 0xfc, 0x09, 0xa5, 0x66, 0x35,
- 0x76, 0x9e, 0x90, 0xb5, 0xdb, 0x43, 0x09, 0x1f, 0xfa, 0x2d, 0xcc, 0xff, 0x46, 0x35, 0x9a, 0x68,
- 0x58, 0xa2, 0x41, 0xd2, 0xa6, 0x05, 0xe5, 0x8e, 0xde, 0xa5, 0xd2, 0xb5, 0x52, 0x88, 0xdf, 0xae,
- 0x74, 0xb1, 0xc9, 0x39, 0x88, 0x02, 0xd5, 0x33, 0xe9, 0x71, 0x23, 0x7b, 0xd0, 0x22, 0xa1, 0x0e,
- 0x38, 0x4a, 0xfe, 0x8b, 0xa4, 0x36, 0xc4, 0x16, 0x69, 0x81, 0x6e, 0xba, 0xd3, 0xda, 0xac, 0x41,
- 0x0d, 0x1e, 0x8e, 0x6d, 0xac, 0x29, 0xd6, 0xa1, 0x7c, 0x56, 0xb9, 0x35, 0x83, 0x86, 0xb9, 0x90,
- 0xde, 0x92, 0xfa, 0xb2, 0x27, 0xdd, 0xfb, 0xf1, 0x64, 0xca, 0xd3, 0xa4, 0x11, 0xf9, 0x57, 0xe4,
- 0xaf, 0x08, 0x91, 0xd3, 0x49, 0x47, 0x4b, 0xb1, 0x52, 0xed, 0x86, 0x03, 0xaf, 0x11, 0x0b, 0x94,
- 0x21, 0x9e, 0x61, 0x9e, 0x9b, 0x44, 0xc3, 0x2e, 0x65, 0x64, 0x74, 0xcd, 0x63, 0x56, 0x11, 0x2a,
- 0x6e, 0xf0, 0x9c, 0x47, 0x85, 0xe4, 0x18, 0xb6, 0xc7, 0xaf, 0x53, 0x14, 0xd9, 0x5e, 0xbf, 0xd8,
- 0xec, 0x8f, 0x83, 0xb6, 0x19, 0x0f, 0x6a, 0x85, 0x2f, 0xb3, 0x0c, 0xf0, 0xcb, 0x2c, 0x12, 0x8b,
- 0xb7, 0x72, 0xa2, 0xf6, 0xd6, 0x12, 0x3e, 0xb8, 0x50, 0x21, 0xb1, 0xc2, 0xf3, 0x21, 0x1a, 0x76,
- 0x80, 0x44, 0x96, 0xbe, 0xcc, 0x54, 0xe1, 0x6e, 0xc0, 0x3a, 0xf2, 0x9a, 0x2c, 0xd1, 0x93, 0x7c,
- 0x8e, 0x75, 0x2e, 0xa4, 0xbe, 0x07, 0xf5, 0x1e, 0xe5, 0x58, 0xc6, 0x97, 0x36, 0xc7, 0x51, 0x43,
- 0xc4, 0x94, 0xd8, 0xdb, 0x29, 0xcc, 0x09, 0x28, 0xce, 0x2f, 0x69, 0x9f, 0x48, 0xc9, 0x26, 0xea,
- 0x79, 0xb9, 0x21, 0x2a, 0xd2, 0x61, 0xe8, 0x88, 0x88, 0x7a, 0x5e, 0x8e, 0x0a, 0x3f, 0xd4, 0x24,
- 0x03, 0x74, 0xdf, 0x66, 0x43, 0xb1, 0x8c, 0x1f, 0x59, 0x65, 0xa0, 0xa1, 0x25, 0x3e, 0x5b, 0xb5,
- 0xa0, 0x9e, 0x22, 0x30, 0x98, 0x4a, 0x45, 0xfb, 0xc0, 0x6b, 0x5b, 0x1e, 0x07, 0xe1, 0xe6, 0xc0,
- 0x12, 0xad, 0xd5, 0x5b, 0x07, 0x6e, 0xc4, 0x32, 0x7c, 0x76, 0xc5, 0xb3, 0xee, 0x85, 0x5c, 0x5a,
- 0x64, 0xa3, 0x0b, 0x55, 0xd3, 0xab, 0x6e, 0xec, 0x2f, 0xdf, 0x9f, 0xf7, 0x03, 0xcf, 0xc7, 0xd0,
- 0x81, 0xee, 0x25, 0xb3, 0xb0, 0x9b, 0x49, 0x55, 0xc0, 0x7b, 0x33, 0x1f, 0xaf, 0x4f, 0xf7, 0xd3,
- 0x47, 0x8f, 0xcc, 0x05, 0x88, 0xb7, 0xb6, 0x4c, 0x79, 0xf9, 0x59, 0xdb, 0x4d, 0xf8, 0xb0, 0xb9,
- 0xc2, 0xdd, 0x58, 0x34, 0xc2, 0x62, 0x1d, 0x92, 0x94, 0x8c, 0x03, 0x62, 0x0f, 0xe6, 0x9d, 0x68,
- 0x63, 0xa0, 0x3b, 0x0d, 0x2d, 0x19, 0x9a, 0x6d, 0x4f, 0x3c, 0xe3, 0xcf, 0x05, 0x4d, 0x81, 0xbe,
- 0x60, 0x38, 0x84, 0xfd, 0xdb, 0x44, 0x4e, 0xc5, 0xd2, 0xba, 0xb2, 0x72, 0x9a, 0xe5, 0x66, 0xf7,
- 0x42, 0x27, 0x33, 0x39, 0x56, 0x32, 0x08, 0x5a, 0x89, 0xed, 0xd9, 0x51, 0x2a, 0x95, 0xfc, 0xcb,
- 0x6e, 0xce, 0x62, 0x8a, 0xc4, 0x8f, 0xac, 0xd6, 0xe3, 0x8c, 0xf9, 0x13, 0xb1, 0x74, 0x4c, 0xaa,
- 0xce, 0x28, 0xf9, 0xff, 0x45, 0x63, 0xa2, 0x61, 0xaa, 0xb7, 0xdb, 0x56, 0x4f, 0xf7, 0xd2, 0xb2,
- 0x33, 0xea, 0x0b, 0x50, 0xd9, 0xa4, 0xc8, 0x8b, 0xb7, 0x3e, 0xf3, 0xc7, 0xb6, 0xb3, 0x5c, 0x1c,
- 0x1d, 0xbc, 0x88, 0xcf, 0xc2, 0xa1, 0x15, 0x0f, 0xfe, 0x0c, 0x7b, 0xd9, 0x6d, 0x5f, 0xdc, 0x87,
- 0xbd, 0x84, 0xe7, 0x03, 0xc4, 0xd6, 0x39, 0x62, 0x2d, 0xf5, 0xf6, 0x0f, 0xf6, 0x7c, 0xc8, 0x3e,
- 0x64, 0x2f, 0x8e, 0x52, 0x88, 0x8f, 0x43, 0x75, 0xd6, 0x90, 0x0e, 0x19, 0x95, 0x68, 0x20, 0x9e,
- 0x77, 0x92, 0x6a, 0x90, 0xcf, 0x88, 0xdf, 0x43, 0xab, 0x23, 0x2b, 0x85, 0x89, 0x74, 0x2c, 0x4f,
- 0x6a, 0x16, 0x94, 0x28, 0x62, 0xd2, 0xc8, 0x32, 0xf6, 0x99, 0x6d, 0x55, 0x4f, 0x43, 0xc2, 0xd0,
- 0x8d, 0x43, 0xee, 0x78, 0xc2, 0xba, 0x9a, 0x26, 0x9e, 0xc7, 0xb9, 0xe0, 0x1c, 0xe3, 0xa5, 0x9c,
- 0xad, 0x58, 0x6d, 0x6a, 0x37, 0x94, 0xdf, 0x1a, 0x7e, 0x2e, 0xbf, 0x3d, 0x68, 0x93, 0x1b, 0x09,
- 0xea, 0xa5, 0xb2, 0x5a, 0xaa, 0x2c, 0x95, 0xa8, 0x8a, 0xd4, 0xd9, 0x92, 0x63, 0x43, 0x76, 0xa9,
- 0xf9, 0x65, 0xb6, 0x72, 0xd1, 0xd8, 0x6d, 0x8b, 0x08, 0x31, 0x70, 0x72, 0xd9, 0xb9, 0xec, 0x58,
- 0xf6, 0xc7, 0xfc, 0x69, 0x5e, 0x62, 0x51, 0x2b, 0xe6, 0x5c, 0x5e, 0x75, 0x5d, 0x8b, 0xfb, 0xa0,
- 0x75, 0x65, 0x9f, 0xbc, 0xe5, 0x65, 0x5a, 0x82, 0xe6, 0xf5, 0x32, 0x2c, 0x13, 0xf4, 0xb3, 0x4f,
- 0x06, 0x6e, 0x11, 0x1d, 0x24, 0x9b, 0x02, 0x46, 0xd7, 0x96, 0x97, 0x61, 0xc7, 0xb7, 0xbc, 0x24,
- 0x7e, 0x92, 0xfb, 0x82, 0xfb, 0x89, 0x30, 0x95, 0x0d, 0xeb, 0xaf, 0xb8, 0xa0, 0xb5, 0xf5, 0x73,
- 0x37, 0xe0, 0xe7, 0x23, 0x77, 0x82, 0xcd, 0xd7, 0x7a, 0x09, 0x64, 0xd1, 0x84, 0xf6, 0x74, 0xa1,
- 0x7b, 0x95, 0x1b, 0x07, 0x94, 0x96, 0x75, 0x89, 0x68, 0x58, 0x49, 0xad, 0x6c, 0xb2, 0x4c, 0x7c,
- 0x38, 0xaa, 0x44, 0x3c, 0x9b, 0x1c, 0x8b, 0x2e, 0x27, 0x64, 0x6d, 0x5d, 0x6a, 0xc6, 0xc3, 0x3a,
- 0xab, 0xfc, 0x49, 0x67, 0xe2, 0x70, 0x2c, 0x1d, 0x0a, 0x87, 0x50, 0x4d, 0xcd, 0x89, 0xc8, 0xe8,
- 0x55, 0x46, 0x6b, 0xf4, 0x95, 0xe0, 0x96, 0xf1, 0xa5, 0xe4, 0x24, 0xf4, 0xbb, 0xa8, 0xf1, 0xa7,
- 0xca, 0xbb, 0xf8, 0x80, 0xa6, 0x0b, 0x47, 0x61, 0x9f, 0x1d, 0x32, 0x17, 0xdf, 0x39, 0xd2, 0x5e,
- 0x34, 0xca, 0x63, 0xb9, 0x14, 0xb9, 0x79, 0x49, 0xc7, 0xea, 0xc0, 0x92, 0xd5, 0x4f, 0xf4, 0x50,
- 0x2c, 0x96, 0xb1, 0x64, 0x3e, 0xee, 0x7a, 0x9d, 0x4e, 0xa3, 0xe4, 0xc2, 0x3c, 0x3e, 0x49, 0x9a,
- 0xc8, 0x2a, 0xd1, 0x35, 0x16, 0x49, 0xb9, 0xf9, 0x89, 0x06, 0x33, 0x9f, 0x8f, 0x36, 0x9d, 0x6f,
- 0x39, 0xfd, 0xab, 0xf0, 0x7f, 0xb8, 0x78, 0x55, 0xa0, 0x2a, 0x60, 0x0a, 0x64, 0xa3, 0x13, 0x72,
- 0x4c, 0x6e, 0x8a, 0x0f, 0xd9, 0x3b, 0x6b, 0xf7, 0x1e, 0x93, 0xa8, 0xf8, 0xe6, 0x6c, 0x74, 0x3e,
- 0xa5, 0x3f, 0x2f, 0x96, 0x05, 0xdd, 0x2e, 0x41, 0x40, 0x31, 0x0f, 0x34, 0x27, 0x6a, 0x7f, 0x7a,
- 0xd2, 0x68, 0x1c, 0x8f, 0x65, 0x1c, 0x31, 0xc6, 0x4b, 0x48, 0xa5, 0x9f, 0xd8, 0x3c, 0xc5, 0x5b,
- 0x59, 0xe3, 0x58, 0xdd, 0x5a, 0xcd, 0xf8, 0x11, 0x8d, 0x4c, 0x65, 0x9b, 0x8b, 0x6b, 0x65, 0xc2,
- 0x2c, 0x10, 0x3b, 0x4c, 0xab, 0x60, 0xb0, 0x99, 0xd5, 0xe9, 0x88, 0x58, 0x2d, 0x5d, 0x22, 0x71,
- 0xfe, 0x04, 0xb1, 0x25, 0x95, 0xb5, 0x1e, 0xf4, 0x53, 0xa9, 0x5c, 0x4e, 0xd3, 0x98, 0x03, 0x33,
- 0xfa, 0xb5, 0xaf, 0x42, 0xc3, 0x56, 0x9a, 0x14, 0x33, 0x49, 0xe2, 0x10, 0x44, 0x15, 0x39, 0xf2,
- 0x5b, 0x7d, 0x32, 0xf1, 0x8f, 0x76, 0xf8, 0x9d, 0x24, 0x96, 0xf6, 0x58, 0x88, 0xcc, 0x11, 0x1d,
- 0x12, 0x73, 0x12, 0x4e, 0x5a, 0xfd, 0xe4, 0x13, 0x27, 0x63, 0x12, 0xb0, 0xa8, 0x9b, 0x9c, 0x71,
- 0x3c, 0x97, 0xe2, 0x71, 0x23, 0x63, 0xce, 0x55, 0x67, 0xcc, 0x97, 0x20, 0x76, 0x51, 0xee, 0xcb,
- 0x7f, 0x76, 0xec, 0xc5, 0x85, 0xbf, 0x4f, 0xe2, 0x70, 0xc2, 0xcd, 0x81, 0x9b, 0xfe, 0x58, 0x46,
- 0xda, 0xce, 0xf2, 0xb2, 0x85, 0xfc, 0x4e, 0xf2, 0xe9, 0x25, 0xe7, 0xea, 0xba, 0xe7, 0xf8, 0xbe,
- 0xe6, 0xeb, 0x33, 0xcf, 0xa7, 0xce, 0xb6, 0xe2, 0x6d, 0x12, 0x4c, 0x01, 0xad, 0xe7, 0x83, 0xf8,
- 0x80, 0x49, 0x8e, 0x3e, 0xa6, 0xa6, 0x12, 0x48, 0x64, 0x4c, 0xff, 0xd3, 0x6b, 0x1c, 0xad, 0x09,
- 0xe0, 0xb6, 0xdd, 0x20, 0x52, 0xe9, 0xc7, 0x1d, 0x35, 0x8e, 0xab, 0x15, 0x11, 0x44, 0xa5, 0x0b,
- 0x59, 0xb5, 0x27, 0xe0, 0x72, 0x03, 0xe3, 0xae, 0xb6, 0xe3, 0x63, 0x93, 0xe3, 0xa9, 0x7f, 0x7c,
- 0xd2, 0x75, 0xa7, 0xe1, 0x7a, 0xed, 0xf5, 0xda, 0x0f, 0x6b, 0x2f, 0xd7, 0x32, 0xdb, 0xac, 0xdf,
- 0xd0, 0x85, 0xee, 0x15, 0xed, 0x29, 0x0f, 0xd9, 0xf9, 0x12, 0x0c, 0x4f, 0x66, 0x1b, 0x1b, 0x18,
- 0x14, 0x1d, 0xa2, 0xfd, 0x1a, 0x09, 0x95, 0xf7, 0xef, 0x88, 0x37, 0xea, 0xd9, 0x10, 0x81, 0x0c,
- 0x43, 0xf6, 0xab, 0x8d, 0xe8, 0xbe, 0x86, 0x0a, 0xbc, 0x84, 0x87, 0x81, 0x28, 0x90, 0xd9, 0x03,
- 0x27, 0x95, 0x4a, 0xeb, 0x92, 0x23, 0x16, 0x4b, 0x6f, 0x08, 0x47, 0x8f, 0x1c, 0x3d, 0xb2, 0xe5,
- 0x75, 0x48, 0x4c, 0x5e, 0xad, 0xf4, 0x15, 0x27, 0xe5, 0x72, 0x36, 0xaa, 0xdc, 0x6c, 0x9c, 0x20,
- 0xec, 0x91, 0x63, 0x79, 0x80, 0xf8, 0x16, 0x6f, 0xdd, 0x70, 0x2e, 0xf9, 0x57, 0x15, 0x72, 0xfa,
- 0x7f, 0xf6, 0xd1, 0x1f, 0xec, 0xfb, 0xe9, 0x9d, 0xd6, 0xe3, 0x9b, 0xa7, 0x87, 0xf5, 0x7e, 0x29,
- 0xd3, 0x82, 0xea, 0x33, 0x14, 0x24, 0xd0, 0xc5, 0xac, 0xa5, 0xf6, 0x93, 0x1e, 0x3d, 0x62, 0xc9,
- 0xe0, 0xe9, 0xac, 0x37, 0x09, 0x2f, 0x6f, 0x5a, 0x89, 0xdf, 0xd3, 0x92, 0x36, 0xfc, 0x52, 0xf9,
- 0x89, 0x7b, 0xc3, 0x39, 0x12, 0x59, 0xcc, 0xa7, 0x54, 0x64, 0x42, 0xa2, 0x99, 0xe5, 0x55, 0xb4,
- 0x31, 0xd0, 0xfd, 0x8b, 0x2c, 0xde, 0x54, 0xbd, 0x9c, 0x76, 0xc3, 0x55, 0x9a, 0xd9, 0xd7, 0xfa,
- 0x9d, 0xb8, 0x63, 0xc9, 0x31, 0x6d, 0x36, 0x6f, 0xaa, 0xb7, 0x14, 0x8f, 0x55, 0x2d, 0xc1, 0x0e,
- 0xa3, 0x3b, 0x40, 0x8f, 0x0a, 0xf1, 0x65, 0xaf, 0x74, 0x95, 0x72, 0x08, 0xb8, 0xf9, 0x91, 0x60,
- 0xee, 0x31, 0x30, 0x15, 0x40, 0xa9, 0xad, 0x86, 0x9e, 0xa7, 0xac, 0x52, 0xa5, 0x0e, 0x06, 0x4c,
- 0x7c, 0xa6, 0x75, 0xb4, 0x2c, 0xe4, 0x92, 0xd8, 0x3e, 0xa6, 0x61, 0x13, 0x8e, 0x4c, 0x37, 0xe1,
- 0x02, 0xb9, 0xa3, 0xa8, 0xc9, 0x66, 0xfc, 0xf8, 0x3e, 0x39, 0x0d, 0xeb, 0x4d, 0xc7, 0x12, 0x91,
- 0x4c, 0xc2, 0x4b, 0x35, 0xea, 0x44, 0x5e, 0xef, 0xb7, 0x71, 0x1f, 0xc3, 0xb8, 0x21, 0xdf, 0x39,
- 0xc0, 0xb0, 0xdf, 0xc0, 0x89, 0x8b, 0x27, 0x92, 0xfb, 0x9a, 0x1a, 0xc3, 0xf2, 0x04, 0x77, 0x29,
- 0x62, 0x2b, 0x22, 0xea, 0xf3, 0x15, 0x9b, 0xdc, 0x28, 0xcd, 0xba, 0xea, 0x71, 0x03, 0xf8, 0x3e,
- 0x90, 0x51, 0x0b, 0x59, 0x83, 0xee, 0xa7, 0xaf, 0x74, 0x91, 0x9b, 0x98, 0xc8, 0x3f, 0xfd, 0x2d,
- 0xe7, 0x2a, 0xea, 0xcf, 0x6a, 0x36, 0x10, 0x33, 0x7f, 0x30, 0x07, 0x4e, 0xbd, 0x15, 0xc7, 0x3b,
- 0x70, 0xfe, 0xd5, 0x92, 0x36, 0x63, 0xc8, 0x10, 0x1f, 0x4d, 0x71, 0x15, 0x71, 0xb5, 0x68, 0x64,
- 0x9a, 0x38, 0x1c, 0x52, 0x6f, 0x19, 0xbc, 0x26, 0x3d, 0x8a, 0xec, 0x4e, 0xc3, 0x44, 0x09, 0xa6,
- 0xd6, 0x2c, 0xc0, 0x9a, 0x43, 0xc3, 0xea, 0xfd, 0x9e, 0xb9, 0x32, 0xf9, 0x74, 0xa0, 0x79, 0xc2,
- 0xa1, 0x6a, 0x09, 0x3d, 0x04, 0x57, 0xdd, 0xf2, 0x98, 0xfc, 0xf9, 0x5f, 0x07, 0x1e, 0x09, 0x87,
- 0xd3, 0xbf, 0x2a, 0x83, 0x7a, 0x47, 0x5d, 0x81, 0x8b, 0xb3, 0x8a, 0x68, 0x8b, 0xb4, 0x91, 0xa2,
- 0xf1, 0xff, 0xf2, 0xc0, 0x12, 0x78, 0x79, 0x8d, 0xbf, 0x37, 0xcc, 0xf2, 0x9b, 0x0a, 0x2f, 0xdb,
- 0xe8, 0xcd, 0x1e, 0x20, 0xbe, 0x03, 0x2f, 0x8d, 0x04, 0xf4, 0x08, 0xa2, 0x21, 0x7b, 0x75, 0xb2,
- 0x10, 0x9f, 0x28, 0x79, 0x3d, 0x5a, 0xab, 0x5e, 0xde, 0x57, 0xc7, 0x89, 0x82, 0xf2, 0x99, 0xf1,
- 0xbc, 0x1a, 0xe7, 0xe2, 0x7a, 0x5d, 0x7a, 0xbd, 0x01, 0x9a, 0x4b, 0xdc, 0x3e, 0x58, 0xb4, 0xe7,
- 0x95, 0x65, 0x2a, 0x8b, 0x37, 0x33, 0x23, 0xb6, 0x64, 0x37, 0x91, 0x10, 0xb9, 0x87, 0xbe, 0xcc,
- 0xf2, 0x0e, 0x39, 0x32, 0x78, 0xac, 0xdb, 0x94, 0x47, 0x2a, 0x4f, 0xda, 0x0d, 0xac, 0x62, 0x65,
- 0xd2, 0xec, 0xc8, 0xc3, 0xc6, 0x34, 0x44, 0xf6, 0x3d, 0x1a, 0xef, 0x0b, 0x5a, 0x73, 0x36, 0xa4,
- 0xbd, 0x03, 0x6b, 0x5c, 0x29, 0x2f, 0x59, 0x7e, 0x69, 0x93, 0x4b, 0x47, 0xb7, 0x0b, 0xbc, 0x2c,
- 0xbf, 0x1d, 0x7c, 0x90, 0xee, 0x75, 0xb7, 0xc8, 0x1b, 0x62, 0x3a, 0xba, 0xe2, 0x11, 0xc6, 0xea,
- 0xec, 0xdd, 0xf6, 0x5f, 0xcc, 0x46, 0xe3, 0x0f, 0x85, 0x52, 0xd4, 0x3b, 0x32, 0xf8, 0x4a, 0x5d,
- 0x6d, 0x2e, 0xd4, 0x6d, 0xbf, 0xdb, 0x3b, 0xb2, 0x60, 0x25, 0xbc, 0x74, 0x2c, 0x11, 0x2f, 0x36,
- 0xb1, 0x11, 0xb7, 0x64, 0x68, 0x9e, 0x1a, 0xbc, 0x24, 0x3a, 0x96, 0xc4, 0x67, 0xb7, 0x88, 0x8e,
- 0xba, 0xe5, 0x5c, 0xf6, 0x25, 0x2d, 0x19, 0x3d, 0x52, 0x08, 0x13, 0xc0, 0xe1, 0x03, 0x53, 0x8f,
- 0x96, 0x65, 0x82, 0x0a, 0x28, 0x92, 0xf7, 0x3e, 0xd8, 0x0f, 0xb6, 0x6b, 0x90, 0xc6, 0x96, 0xd3,
- 0xc3, 0x55, 0x81, 0x51, 0x41, 0xf1, 0x9a, 0x15, 0xaa, 0xb3, 0xb1, 0x1a, 0x81, 0xa1, 0x43, 0xff,
- 0x0c, 0x57, 0xba, 0xb0, 0x57, 0xa7, 0x18, 0x5f, 0xd9, 0xc4, 0xe3, 0xb9, 0x06, 0x0a, 0x5e, 0x40,
- 0x24, 0xbe, 0x13, 0xea, 0x63, 0x30, 0x1f, 0x5d, 0x6a, 0xf7, 0xc1, 0x74, 0xd2, 0xde, 0x00, 0x9e,
- 0xd8, 0x54, 0xf5, 0xb4, 0xef, 0x5f, 0xcc, 0x3d, 0x46, 0x95, 0x43, 0x8b, 0x1a, 0x4b, 0x34, 0xcf,
- 0xa7, 0xf4, 0xf7, 0xae, 0xdd, 0xc0, 0x30, 0x20, 0x5a, 0x6b, 0xb9, 0xee, 0x85, 0x67, 0x46, 0xb3,
- 0x54, 0xf9, 0xef, 0x30, 0x7b, 0x51, 0x1c, 0x8d, 0x60, 0xcf, 0xb0, 0x59, 0xf0, 0x65, 0x2d, 0x72,
- 0x44, 0x0c, 0x87, 0xbe, 0xf4, 0x0c, 0xd9, 0x9f, 0x5c, 0x3c, 0x68, 0xbb, 0x30, 0xbb, 0xc0, 0x7f,
- 0x15, 0xff, 0xba, 0x28, 0xa2, 0x45, 0x4c, 0xcc, 0x72, 0x55, 0x7c, 0x76, 0xcb, 0xcb, 0x6a, 0x60,
- 0xc9, 0xe1, 0xd6, 0x04, 0xfc, 0x58, 0x12, 0x93, 0x10, 0x7b, 0x19, 0x63, 0xc8, 0xa0, 0x6c, 0x4e,
- 0x34, 0x2d, 0x5c, 0x0b, 0x3b, 0x62, 0xcc, 0x5e, 0xc2, 0x0f, 0xdc, 0x48, 0xe9, 0x9f, 0xf8, 0x78,
- 0x47, 0x3a, 0xe4, 0x93, 0xa9, 0xbd, 0x55, 0xb8, 0xc9, 0x2a, 0xd5, 0xc7, 0xfe, 0xbe, 0xf5, 0xeb,
- 0x7d, 0x6c, 0x09, 0x57, 0xa6, 0x30, 0xd3, 0x4c, 0xac, 0x78, 0x6f, 0x58, 0xef, 0x13, 0x30, 0x0c,
- 0x54, 0x36, 0x5a, 0xec, 0xf9, 0x30, 0x6b, 0xa9, 0xcf, 0x4c, 0xaf, 0x71, 0x16, 0xf8, 0xdf, 0xe4,
- 0x53, 0x39, 0x96, 0xa1, 0x6d, 0x62, 0x99, 0xbe, 0xb2, 0x08, 0x1f, 0x85, 0x26, 0x8d, 0xe8, 0xcf,
- 0xe1, 0xb7, 0xef, 0x6b, 0x2a, 0xc9, 0x2c, 0x0f, 0xa4, 0xf5, 0x72, 0x80, 0x8c, 0x85, 0x26, 0x6e,
- 0x91, 0xb4, 0xd8, 0x01, 0x58, 0xc7, 0x48, 0x51, 0x27, 0x4f, 0xf1, 0x36, 0x91, 0x0c, 0xdd, 0xb3,
- 0x87, 0x67, 0x55, 0xa4, 0x92, 0x55, 0x21, 0xb5, 0xf7, 0x44, 0xf9, 0xad, 0x39, 0xe4, 0xf2, 0xb3,
- 0xc8, 0x81, 0x66, 0x89, 0x5c, 0xde, 0x1b, 0x3e, 0x48, 0x62, 0xfb, 0xd1, 0xd9, 0x28, 0x7f, 0x2d,
- 0xfe, 0xb1, 0x2e, 0x26, 0x19, 0x24, 0x4f, 0xc3, 0x66, 0x00, 0x41, 0x4f, 0xb0, 0x4f, 0xb7, 0xc6,
- 0x55, 0xcd, 0xc2, 0xea, 0x0d, 0xf8, 0x07, 0x28, 0xc7, 0x62, 0x12, 0xf2, 0xb1, 0x73, 0x24, 0x3a,
- 0x3c, 0xf0, 0xda, 0x8c, 0x9b, 0xbc, 0x82, 0xf3, 0x58, 0x65, 0xe7, 0xa1, 0xad, 0x0b, 0x60, 0x17,
- 0x2e, 0xf3, 0xf3, 0x78, 0x44, 0xd3, 0x1a, 0x6e, 0x4e, 0x9c, 0xf8, 0x9f, 0x77, 0x60, 0x2d, 0xf7,
- 0x8a, 0xeb, 0x52, 0x6a, 0xd0, 0x40, 0xf9, 0xc0, 0x2f, 0xd1, 0x23, 0xb6, 0xe6, 0x53, 0x13, 0x24,
- 0x6a, 0x9d, 0xf1, 0xe8, 0xe3, 0x14, 0x96, 0x65, 0xd1, 0xfa, 0x27, 0x20, 0x22, 0xab, 0x32, 0x8b,
- 0xf1, 0x7d, 0x09, 0x3c, 0xb9, 0x25, 0x73, 0xaf, 0x42, 0xc6, 0x8d, 0xd1, 0xa2, 0x11, 0xde, 0xa5,
- 0x76, 0x7f, 0x5a, 0xbb, 0x81, 0x45, 0xa0, 0x66, 0x41, 0xb5, 0x96, 0x9b, 0x1c, 0xbb, 0x4f, 0x5c,
- 0xbc, 0x5d, 0x63, 0x2d, 0x81, 0x4d, 0xb8, 0x24, 0xeb, 0xe3, 0x8a, 0xaa, 0xc0, 0xb6, 0x8e, 0x97,
- 0x13, 0x32, 0xf4, 0x63, 0xbb, 0x01, 0xbd, 0x79, 0x99, 0x82, 0x54, 0x62, 0x6a, 0x96, 0xf6, 0x13,
- 0xc2, 0x66, 0xb1, 0x3c, 0x22, 0x4f, 0x24, 0x89, 0x8b, 0xdf, 0xa6, 0x1d, 0x88, 0x5f, 0x0c, 0xff,
- 0xc7, 0xf0, 0xfc, 0x42, 0x94, 0x37, 0xf3, 0x67, 0x35, 0x59, 0x8c, 0x4d, 0x6e, 0xc5, 0xc3, 0x7e,
- 0xb6, 0x45, 0xba, 0x37, 0xcc, 0xfc, 0x68, 0x62, 0x29, 0xe0, 0x8f, 0x12, 0x1d, 0x6b, 0x2d, 0xf0,
- 0xb2, 0x35, 0xff, 0x6a, 0xbb, 0x61, 0x95, 0xf8, 0xf5, 0xbe, 0x44, 0x3e, 0x1b, 0x24, 0xab, 0xe7,
- 0x35, 0x69, 0xec, 0xb6, 0x33, 0x54, 0xbd, 0x98, 0xc5, 0xa9, 0x7f, 0xe7, 0xf1, 0x11, 0x6e, 0x22,
- 0xe7, 0xfe, 0xe2, 0xc3, 0x85, 0xb7, 0x3d, 0xe7, 0xa6, 0xba, 0xf6, 0xd3, 0xa1, 0xa0, 0xc5, 0xc4,
- 0xa6, 0xa3, 0x7a, 0x8c, 0x37, 0x36, 0x21, 0x81, 0x8a, 0x7b, 0x48, 0xd6, 0xb8, 0x05, 0x5a, 0xb3,
- 0xd0, 0xcb, 0x05, 0x45, 0x08, 0xc8, 0x85, 0xf9, 0x29, 0xd2, 0xa8, 0xb0, 0xf3, 0xb4, 0xcf, 0x35,
- 0x0e, 0x56, 0x67, 0x4e, 0x63, 0xf5, 0x16, 0xf3, 0x58, 0xb0, 0xb9, 0x90, 0xea, 0x69, 0xdd, 0x29,
- 0x1b, 0xb7, 0x30, 0x4c, 0xfa, 0x59, 0x9d, 0x37, 0x0a, 0x5d, 0xa1, 0xfd, 0x02, 0x9a, 0x0e, 0x1a,
- 0x76, 0x3b, 0x8f, 0x28, 0x60, 0xbc, 0xd4, 0x46, 0x51, 0xed, 0x86, 0xa3, 0x47, 0x66, 0x3c, 0x13,
- 0x59, 0x16, 0x75, 0x8d, 0x04, 0x31, 0xa3, 0x6e, 0x54, 0xe0, 0xe2, 0x5b, 0xde, 0x93, 0x2e, 0x8f,
- 0x6b, 0x23, 0x10, 0xe5, 0x2f, 0xf2, 0x8a, 0x8f, 0x0d, 0xdf, 0x68, 0x24, 0xc8, 0xbc, 0x07, 0x54,
- 0xa3, 0x94, 0x38, 0x91, 0xd6, 0xf8, 0x88, 0x97, 0xc0, 0x7c, 0x1f, 0x1f, 0x89, 0xc2, 0x9e, 0x15,
- 0x3c, 0xf5, 0xa5, 0x86, 0x8d, 0x54, 0x8c, 0x4d, 0x21, 0x21, 0x1c, 0xce, 0xa5, 0x94, 0x7f, 0x73,
- 0xe0, 0xc8, 0xfb, 0x6e, 0x05, 0xab, 0xc0, 0x72, 0xf0, 0x97, 0x6b, 0xfb, 0x02, 0xf0, 0xa0, 0xac,
- 0xfe, 0x6f, 0xae, 0xff, 0xd9, 0x48, 0x9d, 0x6d, 0x3f, 0x52, 0xa9, 0xd6, 0xa0, 0xb7, 0xfe, 0xb9,
- 0xd4, 0x5a, 0x56, 0xa2, 0xb3, 0x5d, 0x38, 0x99, 0x9f, 0x16, 0x65, 0x61, 0x88, 0xc5, 0x5d, 0x60,
- 0x94, 0x4b, 0xc5, 0x64, 0xc4, 0xc5, 0xca, 0xa9, 0xb5, 0xd3, 0x29, 0xa4, 0x20, 0xed, 0x5d, 0xc1,
- 0x1e, 0x84, 0xcc, 0xb6, 0xb6, 0x6b, 0x05, 0xc8, 0xfd, 0xaa, 0xc0, 0x4f, 0x03, 0xda, 0x7e, 0x06,
- 0x4c, 0x40, 0x2c, 0x8e, 0x5b, 0x3a, 0xf3, 0x35, 0x62, 0x7d, 0x4f, 0x61, 0x9d, 0x4d, 0x2b, 0x97,
- 0x8a, 0x5d, 0xec, 0xc9, 0x9f, 0xda, 0x76, 0x1e, 0x5b, 0xa0, 0xe6, 0x1c, 0xb1, 0xdf, 0xc0, 0x14,
- 0x60, 0x19, 0xf9, 0x48, 0x4a, 0xfe, 0x9c, 0x65, 0xdd, 0x30, 0x9f, 0x72, 0x2e, 0xb4, 0xe2, 0xf9,
- 0xc5, 0xec, 0xa1, 0x3b, 0x8f, 0xf8, 0x87, 0x42, 0xb7, 0xad, 0x9d, 0x76, 0xf9, 0x0e, 0xd9, 0x59,
- 0x75, 0x0e, 0xd8, 0x59, 0xd5, 0xd7, 0x87, 0x86, 0xf0, 0x51, 0x7b, 0x47, 0x7c, 0x1f, 0x62, 0x2d,
- 0xfd, 0xc9, 0xf9, 0xb8, 0xf2, 0x54, 0x34, 0x07, 0x9c, 0x61, 0xbc, 0x24, 0x77, 0x5b, 0xee, 0x71,
- 0xb1, 0x3b, 0x91, 0x68, 0x3e, 0x17, 0x64, 0xb8, 0x18, 0x54, 0x42, 0x94, 0xaa, 0xf5, 0x52, 0x43,
- 0x38, 0xe8, 0x48, 0x1f, 0x4e, 0x84, 0xe9, 0x3c, 0x12, 0xe6, 0xc3, 0xee, 0x8d, 0x97, 0xaf, 0xe7,
- 0xa7, 0xbd, 0x4e, 0x0f, 0x9b, 0x82, 0xa3, 0xa9, 0x52, 0x4b, 0x52, 0x8e, 0x18, 0xe6, 0xb8, 0x18,
- 0x5f, 0xa9, 0x95, 0xb7, 0x74, 0x28, 0x93, 0xd5, 0x9e, 0xda, 0x22, 0xed, 0x95, 0x99, 0x4f, 0xa1,
- 0xca, 0xad, 0xe5, 0x08, 0xbf, 0x3d, 0x91, 0xed, 0xb6, 0xef, 0xa4, 0x87, 0xa1, 0x01, 0x79, 0x5a,
- 0xab, 0xd6, 0x7a, 0x59, 0x67, 0xbb, 0x18, 0x7f, 0xf4, 0xf6, 0xfa, 0x78, 0x87, 0xd6, 0x5b, 0x85,
- 0x04, 0x62, 0x06, 0x88, 0xb9, 0xd0, 0xb9, 0xc0, 0x78, 0xa6, 0x58, 0x7e, 0x78, 0x1e, 0x61, 0x5a,
- 0x13, 0x45, 0x35, 0xfd, 0x4a, 0x97, 0x72, 0xef, 0xd0, 0xa1, 0xc0, 0xc5, 0x4d, 0x81, 0xdb, 0x81,
- 0xea, 0x3b, 0x51, 0xbe, 0x2d, 0xfd, 0x34, 0xf4, 0x87, 0x31, 0x44, 0x6b, 0x4c, 0xb7, 0x5a, 0x88,
- 0xbd, 0xd1, 0xd6, 0xb2, 0xce, 0x76, 0xd1, 0x0c, 0x1e, 0xd3, 0xa3, 0x31, 0x74, 0x59, 0x3c, 0xe9,
- 0x55, 0xde, 0x69, 0x93, 0x9b, 0x0b, 0x52, 0x9b, 0x03, 0xa9, 0xcc, 0x4c, 0x48, 0xd0, 0x52, 0x93,
- 0xc6, 0xbb, 0xbd, 0x5c, 0x9c, 0x71, 0xb2, 0x5a, 0x32, 0xba, 0xb4, 0xd1, 0xa6, 0xa1, 0xa3, 0x89,
- 0x67, 0xf6, 0x1a, 0x9d, 0x9b, 0x7b, 0xef, 0xb4, 0x55, 0xf1, 0xcd, 0x73, 0xa1, 0xa6, 0x32, 0xfe,
- 0x77, 0x29, 0x75, 0xd6, 0x6e, 0x79, 0x7d, 0x65, 0xf0, 0x95, 0x2a, 0x49, 0xcd, 0xb7, 0x05, 0xd8,
- 0x41, 0xf5, 0x33, 0x1f, 0xcd, 0x6f, 0x39, 0xc3, 0xf9, 0x6a, 0xcf, 0x1e, 0x67, 0x53, 0x67, 0xab,
- 0xcc, 0x4b, 0xc8, 0x03, 0xad, 0x7b, 0x6f, 0xeb, 0xbb, 0xed, 0xe5, 0xcf, 0xd9, 0xbb, 0xf5, 0xb8,
- 0xb5, 0x9e, 0x5a, 0x67, 0x6d, 0x46, 0xc3, 0x4b, 0x64, 0x90, 0xc1, 0xaf, 0x16, 0x49, 0xe1, 0x23,
- 0xbc, 0x1b, 0x53, 0xc1, 0xfb, 0x50, 0x90, 0x67, 0xc8, 0x8e, 0x68, 0xbb, 0x0d, 0x2e, 0xd7, 0xd2,
- 0x7e, 0xbb, 0xd0, 0x83, 0x60, 0xcb, 0xbd, 0x68, 0xb8, 0x2d, 0xe9, 0xc8, 0xf8, 0x64, 0x05, 0xc9,
- 0x37, 0x9f, 0xea, 0xb6, 0x6b, 0x75, 0xd1, 0xa2, 0x91, 0x8b, 0x53, 0xab, 0x92, 0x66, 0x7a, 0xf4,
- 0x1a, 0xff, 0x75, 0xaf, 0xfa, 0x44, 0x53, 0xc4, 0x8e, 0x52, 0xa9, 0x4c, 0x20, 0xe3, 0x93, 0x0e,
- 0x61, 0x42, 0xd9, 0xbd, 0xe1, 0x07, 0x22, 0x8b, 0x4b, 0x73, 0x62, 0x5d, 0x51, 0x2f, 0x20, 0x9e,
- 0x96, 0xfc, 0x6e, 0x72, 0xdf, 0x31, 0x99, 0x25, 0xb1, 0x67, 0x2d, 0xab, 0xa2, 0xef, 0xd2, 0xd1,
- 0x54, 0xf4, 0xe5, 0xd3, 0xac, 0xaf, 0x37, 0x8c, 0x04, 0x69, 0xc6, 0x30, 0x6b, 0xae, 0x58, 0x93,
- 0x3f, 0x68, 0x83, 0x56, 0x54, 0x4f, 0x0d, 0x37, 0x4e, 0xc1, 0x91, 0x6b, 0x11, 0x0b, 0x88, 0x77,
- 0xc4, 0x6c, 0x38, 0x54, 0x19, 0x71, 0x73, 0xf4, 0x48, 0x3a, 0x4a, 0x7f, 0xdb, 0xf6, 0x55, 0x4d,
- 0x7d, 0xaa, 0xdd, 0x90, 0xca, 0xa3, 0xe3, 0xaa, 0x02, 0x8b, 0xba, 0x0c, 0xa2, 0x3a, 0x2d, 0x14,
- 0xfd, 0x25, 0x75, 0x76, 0xd8, 0xd0, 0x85, 0x2c, 0x4f, 0xa4, 0x9a, 0x44, 0xf4, 0x22, 0xea, 0xd9,
- 0xca, 0xfd, 0x63, 0x35, 0xf0, 0x09, 0xa2, 0xe3, 0x12, 0x45, 0x95, 0x90, 0x35, 0xce, 0x14, 0xd8,
- 0x10, 0x39, 0xfe, 0x74, 0xf8, 0x12, 0xe1, 0x65, 0x4d, 0xc2, 0x91, 0x61, 0x31, 0x06, 0x4f, 0x2c,
- 0xdb, 0xf1, 0xa2, 0xfe, 0xb3, 0x57, 0xc6, 0xb5, 0x1e, 0xc2, 0x33, 0xe1, 0x7e, 0xaf, 0x36, 0x9b,
- 0xd1, 0xe3, 0xf2, 0xb1, 0x6c, 0x6c, 0x0c, 0x3a, 0x56, 0x1e, 0x86, 0x17, 0xa7, 0x60, 0xc1, 0xb0,
- 0x17, 0xa3, 0x34, 0x8b, 0x88, 0x88, 0xfb, 0x81, 0x08, 0x7b, 0x2d, 0x8c, 0x4d, 0xf5, 0x62, 0xf6,
- 0xe5, 0x5e, 0xb8, 0xa9, 0x60, 0xd5, 0xaf, 0xba, 0xa1, 0x57, 0x76, 0xc6, 0x99, 0x31, 0x2d, 0x80,
- 0x6e, 0x01, 0x54, 0x70, 0x46, 0x82, 0xe5, 0x33, 0x9a, 0x0a, 0x4a, 0x52, 0x8b, 0xf9, 0xe8, 0x41,
- 0x04, 0x53, 0xd2, 0xd7, 0x7a, 0xd2, 0xc5, 0x90, 0x09, 0x2b, 0x9e, 0x72, 0xd5, 0x0f, 0xd4, 0x8b,
- 0x14, 0xc4, 0x45, 0x26, 0x3b, 0xd5, 0xab, 0xf5, 0x62, 0x27, 0x64, 0x4c, 0x9d, 0xc0, 0xe9, 0xea,
- 0xa5, 0x04, 0x92, 0x86, 0x9a, 0x0e, 0x08, 0x98, 0x22, 0x64, 0x8c, 0x5a, 0xa4, 0x0b, 0x02, 0x26,
- 0x5a, 0x66, 0x7f, 0x17, 0x49, 0x3d, 0xc8, 0xe3, 0xfa, 0xc0, 0x49, 0xec, 0x03, 0xbb, 0xd2, 0x55,
- 0xda, 0xf3, 0x8c, 0xf9, 0x22, 0xd5, 0xd2, 0xbc, 0xe0, 0x8d, 0x2f, 0x84, 0x1f, 0xf1, 0x90, 0x4b,
- 0x62, 0xfb, 0xb3, 0xd5, 0x19, 0xc5, 0x6f, 0x55, 0x9f, 0x6f, 0xaa, 0xb7, 0x85, 0xd6, 0xe3, 0x69,
- 0x37, 0x8c, 0x6c, 0xc9, 0xe8, 0xad, 0xf7, 0xf5, 0x86, 0x6c, 0x28, 0x96, 0xb7, 0xa3, 0x7e, 0x12,
- 0x75, 0x46, 0x84, 0xea, 0x0c, 0x93, 0x6f, 0x6c, 0x95, 0xbb, 0x53, 0x01, 0x65, 0x8b, 0x1e, 0x79,
- 0x44, 0xce, 0xe8, 0x73, 0xfd, 0xcd, 0x1e, 0xb9, 0xa9, 0xcc, 0x60, 0x06, 0x92, 0x72, 0xa7, 0x8a,
- 0x80, 0x82, 0xf1, 0xa4, 0xb5, 0x73, 0xa2, 0xfd, 0x1d, 0x99, 0xca, 0x53, 0x73, 0x10, 0x69, 0x54,
- 0x4b, 0xda, 0x1b, 0x3a, 0x4f, 0x3b, 0x46, 0xf0, 0xb9, 0xb5, 0x32, 0xd8, 0x17, 0x60, 0x7d, 0x24,
- 0x3e, 0xb9, 0xd4, 0x66, 0xc2, 0xae, 0x44, 0x04, 0x7a, 0xe3, 0xc9, 0x39, 0x55, 0x67, 0xb4, 0xff,
- 0xce, 0xd0, 0xb1, 0x40, 0xac, 0x71, 0x8b, 0x0c, 0x2c, 0x85, 0xbe, 0x4a, 0x33, 0x12, 0x6c, 0x91,
- 0x72, 0x62, 0x24, 0x15, 0x49, 0x55, 0x4b, 0xf0, 0x85, 0xc9, 0xdd, 0x8b, 0x47, 0x52, 0x14, 0x91,
- 0x1e, 0x6a, 0x8a, 0xe7, 0x44, 0x65, 0xb7, 0xd7, 0xbd, 0x61, 0x2e, 0x6e, 0xac, 0x88, 0x90, 0x4c,
- 0x34, 0x9b, 0xc9, 0xb9, 0x3f, 0x4f, 0x3d, 0x17, 0x6a, 0x92, 0xd6, 0xb4, 0x4f, 0x6a, 0x21, 0xef,
- 0x55, 0xdc, 0xc3, 0x09, 0x5d, 0xcc, 0x30, 0x9e, 0xec, 0x3e, 0x5a, 0xa4, 0x64, 0x51, 0xef, 0xd7,
- 0x95, 0xae, 0x67, 0x02, 0xab, 0x84, 0x39, 0x96, 0x58, 0xf5, 0x84, 0xdd, 0x66, 0x5f, 0x56, 0x99,
- 0xbe, 0x56, 0x9e, 0xa0, 0x87, 0x47, 0x85, 0x57, 0xe3, 0xeb, 0x5e, 0xcc, 0xcd, 0xfb, 0x87, 0x92,
- 0x3d, 0x28, 0x2f, 0x97, 0xcb, 0x1e, 0xf7, 0x6c, 0xa8, 0xce, 0x36, 0x69, 0x5c, 0xac, 0x40, 0x6b,
- 0xdc, 0x93, 0xde, 0x67, 0x02, 0x6a, 0xfd, 0x98, 0x31, 0xe0, 0x4f, 0x3c, 0x8b, 0x1f, 0xec, 0x57,
- 0x5e, 0x1b, 0x34, 0xa8, 0x04, 0x69, 0x6a, 0xe2, 0x33, 0xf2, 0x8a, 0x66, 0x23, 0xda, 0x9d, 0x06,
- 0x9e, 0x55, 0xb0, 0xa4, 0xea, 0x8c, 0x56, 0x27, 0x12, 0x19, 0xcf, 0x6b, 0xa7, 0xea, 0xb4, 0x5e,
- 0xbb, 0xaf, 0x71, 0x43, 0xb6, 0xdf, 0xc6, 0x0b, 0xb6, 0x26, 0x1d, 0x0e, 0x1c, 0x78, 0x4d, 0x7d,
- 0x35, 0x39, 0x0c, 0x24, 0x10, 0x30, 0x40, 0x5a, 0x94, 0x10, 0xcd, 0x3d, 0xb8, 0x23, 0x29, 0xcc,
- 0x77, 0x03, 0x2f, 0xc1, 0xb7, 0x6e, 0x3b, 0x6c, 0x1f, 0xa4, 0x32, 0x1d, 0x1d, 0x15, 0xa0, 0xd7,
- 0x94, 0xf7, 0xdf, 0xe4, 0x2a, 0x9f, 0xe6, 0x1a, 0x77, 0xd5, 0x6d, 0x91, 0xac, 0x92, 0x95, 0xdc,
- 0x58, 0x87, 0xd4, 0x1c, 0x2f, 0xee, 0x04, 0x67, 0x3f, 0x33, 0xe3, 0xd1, 0xf6, 0x1f, 0x5d, 0x75,
- 0x17, 0x6b, 0xa9, 0x27, 0x17, 0xa1, 0x61, 0x09, 0x2f, 0x59, 0xce, 0x07, 0xbc, 0x94, 0x81, 0x8e,
- 0x5a, 0xf7, 0xbe, 0x0c, 0x2f, 0xbd, 0xc9, 0xf5, 0xb8, 0xe7, 0x53, 0xd9, 0x28, 0x9d, 0x7d, 0xd9,
- 0x55, 0x3a, 0x2d, 0xb1, 0xd2, 0x97, 0x32, 0x65, 0x4b, 0x18, 0xdb, 0xf2, 0x5e, 0x75, 0xcb, 0x9f,
- 0x1b, 0x5d, 0x27, 0x8b, 0xc9, 0xdd, 0xe3, 0x9e, 0x71, 0x7f, 0xe7, 0x7e, 0xc8, 0x83, 0x8f, 0xe4,
- 0xc9, 0x6e, 0x59, 0x6f, 0x0d, 0x2c, 0xb5, 0xae, 0x7e, 0x3a, 0xbb, 0xee, 0x62, 0x34, 0xa3, 0xa1,
- 0xbf, 0x1b, 0x7f, 0x73, 0xb6, 0x95, 0x58, 0x87, 0xd5, 0x40, 0xcf, 0xb8, 0x42, 0x9f, 0xce, 0xe6,
- 0x7d, 0x83, 0x64, 0x75, 0x62, 0xa6, 0xf0, 0xdd, 0x9e, 0x5f, 0x1f, 0x4e, 0xf8, 0x13, 0xbe, 0x98,
- 0x2f, 0x06, 0x7e, 0x3d, 0x0d, 0xaa, 0x3f, 0xdf, 0x33, 0xfe, 0x9d, 0x7b, 0x83, 0xd6, 0xf6, 0x1c,
- 0x4b, 0x56, 0x12, 0xb3, 0x39, 0x63, 0xe6, 0x3b, 0xec, 0xdf, 0x35, 0x10, 0xfa, 0xc9, 0xf8, 0xd3,
- 0xd0, 0x57, 0x42, 0x3a, 0xca, 0x2a, 0xd4, 0xf2, 0x98, 0x8a, 0xd4, 0x43, 0x67, 0xbe, 0x59, 0xc0,
- 0x4c, 0x96, 0x0d, 0x31, 0x27, 0x3e, 0xf9, 0x1b, 0xf0, 0x16, 0x9d, 0x22, 0xe0, 0xe5, 0xab, 0x44,
- 0x3e, 0x9b, 0xe2, 0xbb, 0xc3, 0x2a, 0x23, 0x56, 0xe9, 0x71, 0x7f, 0x1a, 0x0c, 0x87, 0xaa, 0x16,
- 0x96, 0x87, 0xff, 0xab, 0xb9, 0xd4, 0x96, 0x0c, 0x16, 0xe6, 0xe8, 0x31, 0x49, 0x5b, 0xf1, 0x94,
- 0xc6, 0x72, 0xf7, 0x7b, 0x27, 0x32, 0xa8, 0x85, 0x11, 0xa9, 0xcc, 0xd7, 0xbb, 0x80, 0xd1, 0x3a,
- 0xe9, 0xda, 0xcd, 0xe6, 0x9b, 0xa3, 0x47, 0xd6, 0xbd, 0x11, 0x3a, 0x2d, 0xb1, 0x2e, 0x3f, 0x2d,
- 0x71, 0x37, 0x92, 0xc9, 0x62, 0x12, 0x54, 0x30, 0x8c, 0xae, 0x75, 0xef, 0xb9, 0xe0, 0x88, 0x8e,
- 0x66, 0xc9, 0x29, 0xa4, 0xa2, 0x5c, 0xfc, 0x5a, 0xbc, 0x2d, 0x86, 0x1c, 0xd5, 0x5b, 0x37, 0x6b,
- 0x9c, 0x14, 0xc7, 0xe3, 0x24, 0x1c, 0x5d, 0x72, 0xae, 0xee, 0x8e, 0x90, 0x75, 0x76, 0x32, 0xae,
- 0x40, 0xa6, 0xe1, 0xbb, 0x13, 0x7f, 0xc0, 0x41, 0x27, 0x88, 0x20, 0x73, 0x6b, 0xf5, 0x23, 0xc7,
- 0x45, 0x7d, 0xfa, 0x3c, 0x61, 0xba, 0x08, 0xb9, 0x35, 0x37, 0xf3, 0xe8, 0x84, 0x5b, 0x88, 0xc2,
- 0xad, 0xab, 0x6d, 0xb1, 0x9a, 0xd8, 0x73, 0x3e, 0xca, 0x8f, 0x87, 0x7f, 0x1f, 0xc4, 0x94, 0xcc,
- 0x15, 0xcf, 0x96, 0xfe, 0x89, 0x43, 0x23, 0x41, 0x48, 0x20, 0x30, 0x08, 0x11, 0x11, 0xb3, 0x6f,
- 0x81, 0x0f, 0xcd, 0x32, 0x0d, 0x2b, 0xe4, 0x1e, 0xef, 0x7e, 0x0f, 0x38, 0xb4, 0x15, 0x26, 0x1e,
- 0xb0, 0x69, 0x4a, 0xa5, 0xa4, 0xe0, 0x63, 0x32, 0x34, 0x5a, 0x5a, 0xf7, 0x6a, 0xfd, 0x60, 0x85,
- 0x0c, 0xbf, 0x1c, 0x8d, 0x53, 0xe4, 0x08, 0xd5, 0x63, 0xc8, 0x15, 0x4c, 0xc8, 0x43, 0xf6, 0xca,
- 0xb8, 0x88, 0xe2, 0xdf, 0xd0, 0x17, 0x9c, 0xa7, 0x1e, 0x2d, 0x76, 0x88, 0xee, 0xb6, 0xe7, 0x96,
- 0x3d, 0xb7, 0xa1, 0xe3, 0xfe, 0xc5, 0x6e, 0xfb, 0x34, 0xb9, 0xdd, 0xc2, 0x58, 0x52, 0x43, 0xf2,
- 0xd8, 0x49, 0x17, 0xb0, 0x9b, 0xfd, 0x73, 0x94, 0x8b, 0x1f, 0xd1, 0xfa, 0xda, 0xf9, 0x17, 0xd6,
- 0x9a, 0x4f, 0x30, 0xc5, 0x47, 0x33, 0xab, 0x67, 0x27, 0x72, 0x16, 0xe8, 0x86, 0xf5, 0x06, 0xad,
- 0xa1, 0x10, 0xa2, 0x95, 0xa0, 0xfc, 0xcd, 0x20, 0x44, 0xfe, 0x6e, 0xa5, 0xff, 0x69, 0x5e, 0xf9,
- 0xe8, 0x85, 0x15, 0x04, 0x6c, 0x66, 0xcd, 0x8d, 0x17, 0xd3, 0xd1, 0xe9, 0x85, 0xe9, 0x4b, 0xd3,
- 0xcf, 0xbe, 0xf8, 0xea, 0x8b, 0x6f, 0x5d, 0xe8, 0x6e, 0xa9, 0xb3, 0x0d, 0x69, 0x9e, 0x58, 0x1e,
- 0x7b, 0xc5, 0xd5, 0xe3, 0x5e, 0xf7, 0x8e, 0x04, 0x9b, 0x88, 0x36, 0x1d, 0x09, 0xa2, 0x72, 0x7f,
- 0x41, 0xb8, 0x4d, 0xad, 0x25, 0x34, 0xec, 0x86, 0x58, 0x8a, 0x3e, 0xde, 0x1f, 0xa1, 0xb2, 0xb0,
- 0x90, 0x55, 0x65, 0xb2, 0xbc, 0xbe, 0x5e, 0x34, 0xce, 0xb8, 0x29, 0x3e, 0x04, 0x99, 0x02, 0x8a,
- 0xe6, 0xc2, 0xfc, 0xf9, 0xdd, 0xff, 0x16, 0xf4, 0x08, 0x9b, 0x85, 0xaa, 0x80, 0x3c, 0x76, 0x97,
- 0x4e, 0x8e, 0xdc, 0x8d, 0x0f, 0xc4, 0xe6, 0xd9, 0x1c, 0x38, 0x72, 0xbd, 0x21, 0xd1, 0xfc, 0xa7,
- 0x1d, 0x06, 0x1d, 0x1d, 0xef, 0x38, 0xde, 0x85, 0x89, 0xd2, 0x43, 0xf6, 0x06, 0xf7, 0xed, 0xa1,
- 0x89, 0xf7, 0x7c, 0x6f, 0xfb, 0xda, 0x7c, 0xa7, 0x08, 0xb5, 0xf1, 0xef, 0xf1, 0xe7, 0x09, 0x59,
- 0x15, 0x12, 0x55, 0x3a, 0x2f, 0x9e, 0x7f, 0x51, 0x4c, 0xef, 0xe5, 0xe9, 0x3c, 0xbd, 0x07, 0x03,
- 0xf8, 0x4f, 0x37, 0x7b, 0x0b, 0x1c, 0xfb, 0xe8, 0xc5, 0x87, 0xb4, 0x97, 0x68, 0x80, 0xd6, 0x64,
- 0x51, 0x8f, 0x65, 0x73, 0x9e, 0x30, 0x75, 0xed, 0x3d, 0xf1, 0xfc, 0x82, 0xd5, 0xf2, 0xe1, 0xb3,
- 0xcb, 0x5f, 0x5d, 0xee, 0xbf, 0xfc, 0xfb, 0xbf, 0xfd, 0xdf, 0xfe, 0x44, 0xf3, 0x9d, 0x86, 0x78,
- 0xb3, 0x54, 0x78, 0xe2, 0xe3, 0x1d, 0x67, 0xbb, 0xee, 0xf6, 0x76, 0xdb, 0x4f, 0xba, 0x4c, 0x81,
- 0xa6, 0x78, 0x8b, 0x84, 0x1c, 0xdb, 0x90, 0x3d, 0xf7, 0xd8, 0x4c, 0xb5, 0x31, 0x17, 0x8f, 0x88,
- 0x7d, 0xc1, 0xdd, 0x68, 0xb7, 0xdd, 0x90, 0x52, 0x0f, 0x85, 0x9d, 0xac, 0x84, 0xf1, 0x64, 0xb2,
- 0x45, 0xe2, 0x37, 0xe2, 0xb9, 0xf1, 0x92, 0x25, 0x33, 0x17, 0x4c, 0x94, 0xe9, 0x09, 0xdf, 0x99,
- 0x80, 0xe9, 0x6f, 0x8a, 0x53, 0x6e, 0xee, 0xda, 0xa3, 0x7d, 0x3d, 0x3f, 0x91, 0x7b, 0x93, 0xdb,
- 0x7c, 0xbd, 0x74, 0xae, 0x68, 0x67, 0x2d, 0xe6, 0x3b, 0xdf, 0xbf, 0xb8, 0x3c, 0xfc, 0xd9, 0xb9,
- 0xbf, 0xe8, 0xec, 0x7f, 0xd3, 0x4b, 0xe8, 0x9b, 0xd6, 0x87, 0x84, 0x9e, 0x75, 0x3e, 0xeb, 0x7c,
- 0xde, 0x79, 0xf8, 0x6d, 0x50, 0x2b, 0x25, 0x0b, 0xa1, 0x89, 0x36, 0x07, 0x21, 0xc2, 0xf3, 0x36,
- 0x1e, 0x74, 0x8a, 0xce, 0xc6, 0x63, 0xbd, 0xc0, 0xf4, 0x4f, 0xf9, 0xa9, 0x78, 0x6d, 0xf9, 0xf9,
- 0x6a, 0xea, 0xdf, 0x19, 0xef, 0x0a, 0xdf, 0xcf, 0xcf, 0xa9, 0x3a, 0xc6, 0x9f, 0xf0, 0x9d, 0xf0,
- 0x9d, 0x9a, 0x68, 0x6b, 0x6d, 0x7b, 0xd6, 0xe9, 0xed, 0x3c, 0xdd, 0xfd, 0xe0, 0x5d, 0xf3, 0xbb,
- 0x23, 0x67, 0x30, 0xd7, 0x55, 0xfb, 0xc4, 0xd0, 0xa8, 0xd8, 0x55, 0xf4, 0x0a, 0xe1, 0x25, 0xd0,
- 0x3a, 0x98, 0xb2, 0xb4, 0xe2, 0xc9, 0x89, 0x4d, 0x02, 0xf0, 0xb5, 0xd0, 0xba, 0xc2, 0xd8, 0x0f,
- 0xb3, 0x6f, 0x8f, 0xc9, 0xe5, 0xab, 0x71, 0x6c, 0xab, 0x7e, 0xf2, 0x92, 0x2d, 0x36, 0x9d, 0xb5,
- 0x3d, 0xee, 0x34, 0xd1, 0xfc, 0xdd, 0xf6, 0xfd, 0x74, 0x15, 0xb5, 0xd3, 0x9a, 0x6a, 0x13, 0x8d,
- 0x4f, 0xae, 0x74, 0x5d, 0xde, 0x75, 0x3f, 0x3c, 0xc3, 0x83, 0x0e, 0x96, 0x21, 0xf8, 0xb6, 0xe8,
- 0xf4, 0x3c, 0xdb, 0x55, 0x6f, 0x5b, 0xf9, 0xe0, 0xcf, 0xdf, 0x6d, 0x6a, 0x31, 0x9b, 0xe6, 0x4d,
- 0x0f, 0x4c, 0xdf, 0x9b, 0x0e, 0xb5, 0x1e, 0x7a, 0xf3, 0x34, 0xa1, 0x7e, 0x42, 0xe3, 0x84, 0x08,
- 0x8f, 0x09, 0x3d, 0x7c, 0xf3, 0x39, 0xa1, 0xc3, 0x27, 0x0e, 0x9f, 0x68, 0x3d, 0x61, 0x39, 0x61,
- 0x3d, 0xe1, 0x38, 0xe6, 0xa3, 0xc4, 0x57, 0x24, 0x91, 0xd1, 0x09, 0xb1, 0xf8, 0x15, 0x36, 0x99,
- 0xf4, 0x98, 0xe3, 0x58, 0x2b, 0x79, 0xb7, 0x47, 0xe4, 0xfd, 0xfb, 0xdf, 0xfc, 0xbe, 0x65, 0xb4,
- 0x85, 0x6b, 0xa9, 0x6a, 0x9c, 0xcc, 0xf7, 0x0f, 0x6b, 0x9f, 0x11, 0x5b, 0xe3, 0xdf, 0x77, 0x63,
- 0xd6, 0x33, 0x30, 0x76, 0xb8, 0xd5, 0x1b, 0xe2, 0x05, 0x21, 0xfb, 0x3b, 0xc4, 0x25, 0x2f, 0xef,
- 0x5c, 0xdb, 0x0b, 0x01, 0x81, 0x7a, 0xb9, 0x56, 0x1f, 0x6f, 0x56, 0xe2, 0xc7, 0xee, 0x66, 0xc8,
- 0x94, 0xa7, 0x49, 0xe3, 0x93, 0x8b, 0xac, 0x5b, 0xa8, 0xd2, 0x6c, 0xfe, 0x9d, 0x79, 0x5a, 0xee,
- 0x79, 0x30, 0x7f, 0xa3, 0xb3, 0x16, 0x5b, 0x72, 0xea, 0xfb, 0xbf, 0xec, 0x5f, 0xff, 0x20, 0x75,
- 0xe6, 0xdb, 0xc6, 0xa7, 0x8d, 0x9c, 0xc9, 0x6c, 0x1a, 0x25, 0x7c, 0x9d, 0x37, 0x45, 0x08, 0x6f,
- 0x1f, 0x98, 0x72, 0x26, 0xc2, 0xdb, 0xfa, 0xd3, 0xf5, 0xfd, 0xf5, 0xe3, 0xf5, 0x5e, 0x42, 0xdf,
- 0xd4, 0x3f, 0xac, 0x7f, 0x5e, 0xff, 0xfc, 0x8d, 0xc3, 0xc7, 0x5a, 0x8f, 0x59, 0x8e, 0x39, 0x6a,
- 0x1c, 0xf9, 0x99, 0xb1, 0x0a, 0xf1, 0x15, 0x48, 0xfb, 0x33, 0x8e, 0x1a, 0x4b, 0x4d, 0xeb, 0xb1,
- 0xe7, 0x6f, 0x3c, 0x24, 0xef, 0xd7, 0x5f, 0x7f, 0xa8, 0x3e, 0x42, 0x7e, 0xe7, 0xb7, 0x8d, 0xeb,
- 0x3f, 0x6f, 0xd7, 0x3d, 0x2f, 0x7b, 0xbe, 0xb3, 0x5d, 0xd3, 0xc3, 0xeb, 0x5e, 0xcc, 0x5b, 0x42,
- 0x66, 0xe1, 0x6c, 0x57, 0xee, 0xf1, 0x86, 0xc8, 0xfc, 0xda, 0xdc, 0xe3, 0x1f, 0x4e, 0xc3, 0xfe,
- 0x71, 0x69, 0xd1, 0x38, 0x64, 0x87, 0x9d, 0xb8, 0xea, 0xc1, 0xac, 0xc4, 0xdd, 0xc7, 0x27, 0x3b,
- 0x4b, 0xed, 0x24, 0xb9, 0xf9, 0x97, 0xe9, 0x34, 0xfd, 0x83, 0xfd, 0x7f, 0x65, 0xfb, 0x57, 0xdb,
- 0xba, 0x2d, 0xf4, 0xce, 0xdc, 0xe9, 0x5b, 0x8d, 0x69, 0xca, 0xd5, 0x66, 0x72, 0xc6, 0xe6, 0xba,
- 0x6b, 0x75, 0xf3, 0x75, 0x91, 0xba, 0x07, 0x84, 0x72, 0x75, 0x87, 0xf2, 0x5c, 0x1d, 0x07, 0x4f,
- 0xdf, 0xc8, 0x73, 0x54, 0xe5, 0x67, 0x99, 0x5d, 0x17, 0x3a, 0x4e, 0xd3, 0xbf, 0x83, 0x93, 0x87,
- 0x09, 0x27, 0xbf, 0x21, 0xef, 0x02, 0x4e, 0x3e, 0x20, 0xef, 0xdf, 0x6c, 0x5a, 0x6d, 0x5c, 0xf9,
- 0x79, 0xf1, 0xb3, 0xd1, 0x29, 0xc4, 0xb6, 0x1e, 0x2a, 0x95, 0x40, 0xf3, 0x00, 0xb3, 0x70, 0x49,
- 0xde, 0x10, 0x47, 0x89, 0x44, 0x3e, 0x10, 0x73, 0x8f, 0xe5, 0x32, 0xd3, 0x68, 0x7e, 0x1c, 0x84,
- 0xba, 0x04, 0xf2, 0xc3, 0x88, 0x4f, 0xca, 0xcd, 0xe6, 0xdf, 0x1f, 0x3f, 0x99, 0x8f, 0xd4, 0x59,
- 0x8b, 0xfd, 0x81, 0x53, 0xbd, 0xff, 0x7d, 0xb1, 0xdb, 0x76, 0xd3, 0xfe, 0x9f, 0xf6, 0xf5, 0xfe,
- 0xd9, 0x33, 0x9f, 0x36, 0xce, 0x35, 0xae, 0x12, 0x82, 0xb4, 0xbe, 0x66, 0x6a, 0xae, 0x33, 0xd7,
- 0x8d, 0x52, 0xae, 0x46, 0xea, 0xbe, 0xa7, 0x5c, 0x65, 0x92, 0xfa, 0xcd, 0x1b, 0x8f, 0xf4, 0x1c,
- 0x2d, 0xc7, 0x4f, 0x0d, 0x67, 0x19, 0x27, 0x1f, 0x51, 0x4e, 0x9e, 0xce, 0x73, 0xd2, 0x6c, 0x7a,
- 0xda, 0x78, 0xab, 0xf1, 0xfd, 0xbf, 0x54, 0x9f, 0x8b, 0xdd, 0x32, 0xec, 0x4e, 0x35, 0xba, 0xfa,
- 0x82, 0x66, 0xe1, 0x90, 0x54, 0x67, 0xc3, 0x93, 0x62, 0xf7, 0xc9, 0x46, 0x3e, 0x07, 0xf4, 0xc3,
- 0x6a, 0xd8, 0x3f, 0x36, 0xa1, 0xdf, 0x58, 0x9d, 0xcd, 0xff, 0xc3, 0xcc, 0x04, 0x62, 0xda, 0x16,
- 0x5e, 0x12, 0xe3, 0x28, 0xe6, 0x38, 0xc3, 0xcb, 0x45, 0x6c, 0xf0, 0x2f, 0xf6, 0x15, 0x9b, 0xe7,
- 0x83, 0x91, 0x33, 0x23, 0xa7, 0xe7, 0x4e, 0x2b, 0x5c, 0xe5, 0xea, 0x54, 0xae, 0x2a, 0x72, 0x0a,
- 0xcd, 0xab, 0x72, 0xb4, 0x58, 0xeb, 0xaa, 0x9a, 0xd5, 0x51, 0x63, 0x25, 0xba, 0x55, 0xe5, 0x64,
- 0x8e, 0xbc, 0xc7, 0x35, 0xc2, 0x49, 0xce, 0x94, 0x6e, 0x3c, 0xdf, 0xf8, 0xf1, 0x4f, 0x14, 0x3e,
- 0x2e, 0x12, 0x89, 0xc4, 0xc6, 0x86, 0x21, 0xfb, 0x8c, 0x27, 0x1c, 0x42, 0xcf, 0x49, 0x15, 0x45,
- 0xfe, 0x1d, 0x38, 0x12, 0x11, 0x27, 0xe4, 0x16, 0x19, 0x93, 0x9f, 0x27, 0xb2, 0xda, 0xda, 0xf6,
- 0x8f, 0x91, 0x80, 0xc0, 0x18, 0xcd, 0x4f, 0x73, 0x67, 0xd1, 0xe6, 0xcb, 0x36, 0xf9, 0xed, 0x95,
- 0xa3, 0x9b, 0x1c, 0xf3, 0x72, 0x13, 0xcd, 0xe8, 0x04, 0x46, 0xb7, 0x59, 0xb7, 0xfd, 0xa6, 0xfd,
- 0x4b, 0xdb, 0x3f, 0x7d, 0xf0, 0xeb, 0x77, 0x66, 0xcf, 0x84, 0xcf, 0xdc, 0x22, 0x5c, 0xfd, 0x77,
- 0x45, 0x03, 0xe7, 0xb5, 0x2f, 0x38, 0xaa, 0xca, 0x28, 0xe3, 0xa9, 0xb5, 0x40, 0x0e, 0xfa, 0x7f,
- 0x7c, 0xa7, 0xb5, 0x06, 0xaf, 0x3e, 0x7c, 0xc3, 0x5b, 0x7f, 0x89, 0x48, 0x24, 0x38, 0x39, 0x4a,
- 0x6e, 0xc6, 0x53, 0x72, 0x4b, 0x3e, 0x6b, 0xfc, 0xb7, 0x9f, 0x77, 0xfc, 0x09, 0xab, 0xef, 0x5c,
- 0xe9, 0x42, 0xd7, 0x47, 0x8f, 0x7b, 0xcb, 0x3b, 0x17, 0xba, 0x40, 0x7c, 0xd5, 0x4b, 0x72, 0x36,
- 0xca, 0xa2, 0x48, 0xa9, 0x19, 0x48, 0xac, 0x16, 0x09, 0xbc, 0x6c, 0xa9, 0x80, 0x71, 0xfd, 0xf1,
- 0x10, 0xf0, 0x1d, 0x23, 0xc1, 0x51, 0xa1, 0x2f, 0x28, 0x7f, 0x8e, 0x3d, 0x05, 0xfa, 0x4d, 0x0b,
- 0xff, 0x5f, 0x7e, 0x2a, 0x7e, 0x2f, 0xdb, 0xf5, 0x00, 0x9e, 0x5e, 0x86, 0xa4, 0xb6, 0x9f, 0xed,
- 0x9a, 0x22, 0x3c, 0xad, 0xb3, 0xfd, 0xca, 0xfe, 0x8f, 0xff, 0x57, 0xde, 0xd5, 0x84, 0x44, 0x15,
- 0x45, 0x61, 0x77, 0x05, 0x09, 0x19, 0xb5, 0x50, 0x6a, 0x61, 0xe1, 0xa6, 0x18, 0x41, 0xd3, 0x8d,
- 0x4c, 0x9b, 0xc9, 0x55, 0xfe, 0x91, 0x4e, 0x06, 0x3a, 0xab, 0xb8, 0xb8, 0x90, 0x47, 0x98, 0x3c,
- 0x66, 0x44, 0x6a, 0x16, 0x89, 0xb8, 0x88, 0xc9, 0x1c, 0x1d, 0x47, 0x90, 0x71, 0x13, 0xe5, 0x62,
- 0x60, 0xac, 0x46, 0xa7, 0x62, 0xc0, 0x36, 0x81, 0x2e, 0x02, 0x23, 0x05, 0x93, 0x04, 0x37, 0x2d,
- 0x5c, 0xb8, 0x70, 0xe1, 0x62, 0x20, 0x11, 0x3a, 0xdf, 0xb9, 0xef, 0xfa, 0xde, 0x1b, 0xb5, 0x9c,
- 0x71, 0xfc, 0xab, 0xfb, 0x21, 0x38, 0xef, 0xcd, 0x8f, 0xe3, 0xf7, 0xce, 0x3d, 0x3f, 0xf7, 0xbc,
- 0xfb, 0x89, 0x41, 0xcf, 0x90, 0x7b, 0xca, 0x1d, 0xae, 0x1e, 0x31, 0xec, 0x14, 0x56, 0x6a, 0xda,
- 0xa8, 0x62, 0x74, 0x8b, 0x39, 0x4d, 0xc7, 0x16, 0x1d, 0x07, 0x93, 0xf0, 0x92, 0xbf, 0xd8, 0x26,
- 0xab, 0x2a, 0x25, 0x93, 0xf1, 0x6b, 0x67, 0x2e, 0x60, 0x4e, 0x8d, 0xd2, 0x95, 0x53, 0xaf, 0xd1,
- 0x9c, 0xa0, 0xe3, 0x5e, 0x1a, 0xa8, 0x5b, 0x24, 0x17, 0xe3, 0x21, 0x55, 0x0f, 0xc0, 0xde, 0x15,
- 0xb7, 0xd6, 0xaf, 0x30, 0x97, 0xcb, 0x2b, 0x07, 0xdb, 0xad, 0xf9, 0x24, 0x00, 0x6b, 0x54, 0x58,
- 0x1f, 0xc0, 0x3d, 0xda, 0xd8, 0xaf, 0x0b, 0xaa, 0x13, 0xc5, 0xb9, 0x21, 0xd3, 0xc2, 0xa9, 0xb2,
- 0x53, 0xa5, 0xdf, 0x21, 0x2d, 0x55, 0xce, 0xbe, 0xf9, 0xa2, 0x41, 0x3c, 0x12, 0x41, 0x31, 0x49,
- 0x3e, 0xb5, 0x8b, 0xfc, 0xdc, 0x12, 0xdb, 0xa8, 0x39, 0xeb, 0x9a, 0x11, 0x2f, 0x81, 0xb8, 0x53,
- 0xc0, 0xe3, 0x88, 0x25, 0xde, 0xe9, 0xa6, 0x57, 0x2d, 0xd1, 0xeb, 0xef, 0x57, 0x04, 0x6f, 0x9c,
- 0xbb, 0x79, 0x87, 0xdf, 0x19, 0x9a, 0x45, 0xb8, 0x72, 0xea, 0xb4, 0x32, 0xf6, 0x93, 0xd0, 0xa1,
- 0x30, 0xb3, 0xb8, 0xe6, 0x18, 0xf6, 0x27, 0x06, 0x97, 0xfe, 0xf5, 0x70, 0xe2, 0xb4, 0xc6, 0x3d,
- 0x56, 0xa0, 0xef, 0x33, 0x35, 0x5d, 0x38, 0xb3, 0x40, 0xd9, 0xe6, 0xb3, 0xa6, 0xfd, 0x56, 0x82,
- 0xb2, 0x65, 0xd5, 0xb4, 0xd4, 0x9f, 0x86, 0xa5, 0xca, 0xd9, 0xf7, 0x4b, 0x6b, 0xa9, 0xe8, 0x10,
- 0xef, 0x28, 0x4a, 0x0a, 0x13, 0xa3, 0x1f, 0x38, 0x3e, 0xa2, 0x6c, 0x86, 0xe7, 0x5c, 0xe5, 0x47,
- 0x3d, 0x34, 0x97, 0x3e, 0xb1, 0x00, 0x47, 0xb6, 0xe3, 0x1d, 0xb6, 0xc9, 0x91, 0x0a, 0x5f, 0xc5,
- 0x94, 0x7b, 0x40, 0xcb, 0x17, 0x6b, 0xad, 0xd0, 0x5c, 0x80, 0x9a, 0x18, 0x7b, 0x4a, 0x3d, 0x1e,
- 0x41, 0xe6, 0x1e, 0xb5, 0xac, 0x03, 0xa3, 0x57, 0xd6, 0x6f, 0xcc, 0xb0, 0xe8, 0x42, 0x39, 0x6e,
- 0x1e, 0x72, 0x83, 0x9e, 0x02, 0x87, 0xe8, 0xa6, 0x7c, 0x59, 0xb2, 0xa9, 0x54, 0x1a, 0x0f, 0x73,
- 0xc8, 0xff, 0xa5, 0x39, 0xfb, 0x22, 0xab, 0x86, 0x9d, 0x52, 0x2e, 0x43, 0x33, 0xef, 0x37, 0x2d,
- 0xe4, 0xf6, 0x39, 0x47, 0x98, 0xd1, 0x2a, 0x4b, 0x16, 0xb3, 0xc9, 0xb8, 0x5c, 0x6a, 0x62, 0x93,
- 0x8e, 0x26, 0x39, 0x72, 0x2d, 0x32, 0x6c, 0x72, 0xd2, 0xf3, 0x46, 0x07, 0x8f, 0xe3, 0xe5, 0x25,
- 0xbc, 0x77, 0x36, 0x2a, 0x18, 0xe8, 0x88, 0xf0, 0xc6, 0x46, 0x17, 0xed, 0x7d, 0xbd, 0x7d, 0xe5,
- 0xfe, 0x94, 0x3f, 0x85, 0xbb, 0xc4, 0xfd, 0xf4, 0x93, 0xd9, 0xae, 0xcc, 0x27, 0x19, 0xd8, 0x5d,
- 0x23, 0xb9, 0x92, 0x9a, 0x96, 0x6b, 0x9b, 0x6d, 0x47, 0xa6, 0x6c, 0x2b, 0x39, 0x95, 0xba, 0x8b,
- 0x2a, 0xf2, 0xe5, 0xec, 0x54, 0xf4, 0x6b, 0x83, 0x1e, 0x8a, 0x8e, 0x0c, 0x46, 0x8b, 0xb6, 0xa3,
- 0x5d, 0x99, 0xc5, 0x28, 0x8c, 0x22, 0x6e, 0x25, 0x8b, 0x2c, 0x64, 0x26, 0x7d, 0xce, 0xb8, 0xa7,
- 0x5e, 0x6b, 0x67, 0x1e, 0x51, 0xfd, 0x78, 0x60, 0x64, 0x22, 0x0e, 0x01, 0xed, 0x8d, 0x70, 0xc2,
- 0xee, 0x11, 0xf3, 0x05, 0xfa, 0x0e, 0xc6, 0x08, 0xd8, 0x5f, 0xe9, 0xb8, 0x19, 0xc8, 0x25, 0xd0,
- 0x41, 0x9c, 0xe4, 0xfe, 0x2e, 0x54, 0x82, 0x72, 0x93, 0x6d, 0x66, 0xca, 0xa9, 0xca, 0x65, 0xd8,
- 0x46, 0x6b, 0xa2, 0x34, 0xeb, 0x0e, 0x68, 0x43, 0xee, 0x10, 0x57, 0x1b, 0x3e, 0x1a, 0x7e, 0x14,
- 0x76, 0x6a, 0x01, 0x3d, 0x2e, 0x32, 0xe2, 0x1d, 0x2f, 0x31, 0x89, 0x4c, 0xb9, 0xed, 0x3a, 0x7c,
- 0xbe, 0xcb, 0xd8, 0xe5, 0xa9, 0x04, 0xbb, 0x89, 0xeb, 0x14, 0xad, 0xcf, 0x7d, 0x4d, 0xab, 0xb5,
- 0x76, 0x06, 0x54, 0xa7, 0xc8, 0xa7, 0x54, 0xa6, 0xca, 0xdf, 0x27, 0x1d, 0x9f, 0x0b, 0x37, 0x22,
- 0x49, 0x43, 0xdf, 0x47, 0xe9, 0xa8, 0x1d, 0xed, 0x50, 0x8c, 0xc2, 0x97, 0x96, 0x5c, 0x85, 0x6a,
- 0x76, 0x7b, 0xcd, 0x5a, 0x6b, 0x03, 0xc7, 0x45, 0x89, 0x5a, 0x39, 0xeb, 0x2e, 0x71, 0xb4, 0x6b,
- 0x62, 0x89, 0x8e, 0xc1, 0x4b, 0x7a, 0xab, 0x83, 0x22, 0x5d, 0x89, 0xc7, 0xdc, 0x4d, 0x1c, 0xea,
- 0xb0, 0x67, 0xd3, 0xee, 0x5a, 0x41, 0xaf, 0xa4, 0xec, 0x08, 0x4a, 0x2e, 0xfe, 0x4d, 0xf9, 0xe8,
- 0xb4, 0x01, 0xf9, 0x09, 0xd6, 0x0f, 0x9a, 0x63, 0xe7, 0x7b, 0xe1, 0x35, 0x8f, 0x46, 0xe3, 0x6d,
- 0x2f, 0x46, 0x65, 0x74, 0x24, 0xeb, 0x47, 0x51, 0x9a, 0x73, 0x3b, 0x88, 0xd1, 0x05, 0xcf, 0x70,
- 0xad, 0x8f, 0x78, 0x43, 0xb4, 0xab, 0xd0, 0x45, 0x3e, 0xd2, 0xe7, 0x1c, 0x72, 0x77, 0x08, 0xe8,
- 0xa6, 0x5b, 0xf5, 0xce, 0xf0, 0x4e, 0xb2, 0x7f, 0xb0, 0xac, 0x17, 0xde, 0xc3, 0x5e, 0x09, 0xe8,
- 0x29, 0x68, 0x99, 0x83, 0xb7, 0xf4, 0xaf, 0x8f, 0xa5, 0xe2, 0xa1, 0xd3, 0x5d, 0x25, 0xd8, 0x9d,
- 0x4d, 0x74, 0xd0, 0x17, 0xce, 0xcc, 0x47, 0x8e, 0xcb, 0x32, 0xad, 0x8c, 0xda, 0xe7, 0x5c, 0xac,
- 0x3c, 0x96, 0x52, 0x5c, 0xf4, 0x56, 0x9b, 0x17, 0x53, 0x64, 0xa5, 0xde, 0x6a, 0x9f, 0xd3, 0xe7,
- 0x1c, 0xae, 0x9e, 0x72, 0xc7, 0xc5, 0x0b, 0xb2, 0xc8, 0xf6, 0x9a, 0xd9, 0x2a, 0x3b, 0x93, 0x79,
- 0x79, 0x6a, 0x87, 0x05, 0x44, 0x3e, 0x0f, 0x35, 0x7b, 0x6f, 0x52, 0x5f, 0x39, 0xd6, 0xb8, 0xd0,
- 0x0d, 0x84, 0x1e, 0xde, 0xbd, 0x3a, 0x98, 0x76, 0xa2, 0x67, 0x1f, 0xeb, 0x1e, 0x27, 0x03, 0xb8,
- 0xc3, 0x10, 0xfb, 0x81, 0x61, 0x3f, 0xb1, 0xa3, 0x53, 0x45, 0xdd, 0x7b, 0xa4, 0x33, 0xaa, 0x6a,
- 0x47, 0x0e, 0x51, 0x2f, 0x50, 0x05, 0xa8, 0x27, 0x16, 0xa1, 0x77, 0x0e, 0xdd, 0x5b, 0xe9, 0x25,
- 0xed, 0xaf, 0x66, 0x7f, 0x79, 0xbb, 0x5f, 0xdf, 0x88, 0x7c, 0x9f, 0xc6, 0x5a, 0x88, 0x09, 0xca,
- 0x35, 0x79, 0x05, 0xfa, 0xfd, 0x34, 0xd6, 0xbb, 0x5a, 0xe6, 0xba, 0xb3, 0x07, 0xf7, 0xda, 0xa3,
- 0xa6, 0x9b, 0xe4, 0x6b, 0x03, 0x57, 0x87, 0xc2, 0xb2, 0x81, 0x1f, 0x5c, 0xf3, 0xc5, 0xf3, 0xa0,
- 0x17, 0x94, 0xf9, 0x67, 0x58, 0x15, 0x55, 0xf6, 0x8b, 0x14, 0xef, 0x4b, 0x8a, 0xfe, 0xf6, 0xb3,
- 0x87, 0xae, 0x0a, 0xb6, 0xdf, 0x51, 0x6c, 0x63, 0x14, 0xd9, 0xcb, 0x78, 0xf9, 0x6c, 0xd5, 0xaa,
- 0x01, 0x28, 0x52, 0x23, 0xfb, 0xe8, 0x29, 0xd8, 0xf9, 0xd7, 0x2a, 0x05, 0xdc, 0x68, 0xd3, 0x84,
- 0xde, 0x19, 0x58, 0x88, 0x6c, 0xbc, 0xc2, 0x1e, 0x1c, 0x00, 0xee, 0x4e, 0x87, 0xb6, 0xd8, 0xdd,
- 0x40, 0x63, 0x20, 0x18, 0x42, 0x4f, 0xd0, 0xc5, 0xd7, 0x97, 0xb2, 0x46, 0x25, 0xe1, 0x5e, 0xac,
- 0x99, 0xfb, 0x89, 0xc2, 0x09, 0x74, 0x0e, 0x99, 0xc0, 0xe3, 0xe1, 0x84, 0x97, 0xce, 0x36, 0xc7,
- 0x2a, 0xf9, 0x99, 0xd9, 0x7f, 0x4e, 0x66, 0xd8, 0x88, 0xcc, 0x47, 0x1a, 0x03, 0x66, 0xcd, 0xe0,
- 0x38, 0xb8, 0xdb, 0x7d, 0x98, 0x8c, 0xbe, 0x34, 0xaa, 0x47, 0x12, 0x52, 0x11, 0x56, 0x56, 0x00,
- 0x76, 0x0e, 0xb9, 0xd2, 0x35, 0xcb, 0x31, 0x94, 0x83, 0x2d, 0x19, 0xbb, 0x10, 0xc9, 0xba, 0x1e,
- 0xea, 0x09, 0x52, 0xe7, 0xda, 0x21, 0xea, 0x34, 0x75, 0x2e, 0x5b, 0x3c, 0xd7, 0xfb, 0x75, 0x6b,
- 0x27, 0xd4, 0x3a, 0x03, 0xbf, 0xcd, 0x3d, 0x9e, 0xe0, 0x73, 0xfd, 0xfa, 0x41, 0xde, 0x3f, 0x53,
- 0xc8, 0xef, 0xb8, 0xd6, 0x2a, 0x7d, 0x4f, 0xee, 0x2a, 0xb3, 0xb9, 0x1c, 0x92, 0x53, 0x3b, 0x8a,
- 0xff, 0xf0, 0x6c, 0x17, 0xaf, 0xc1, 0xd9, 0x6d, 0x59, 0x62, 0x96, 0x6d, 0x1a, 0xfa, 0xf3, 0xe9,
- 0x67, 0xb2, 0x82, 0xcb, 0xd2, 0xff, 0x94, 0x06, 0x79, 0x7c, 0xd5, 0x95, 0x83, 0x4f, 0xc9, 0x08,
- 0xf8, 0x86, 0xe8, 0x13, 0xb4, 0x47, 0x11, 0xa7, 0x77, 0xa8, 0x98, 0xd8, 0xb4, 0x64, 0xd3, 0xa2,
- 0x61, 0xd3, 0x38, 0xb3, 0xf3, 0xdc, 0x41, 0x90, 0xde, 0x0b, 0x95, 0xcb, 0xf7, 0xce, 0x14, 0xf8,
- 0x86, 0x4f, 0xff, 0x11, 0x26, 0xe5, 0xd8, 0xcd, 0x96, 0xff, 0x17, 0xd8, 0x7d, 0xcf, 0x6f, 0x5c,
- 0xec, 0xa7, 0xa1, 0x48, 0x9d, 0x01, 0x00
-};
-
-fastimage_t bfin_logo = {
-		DEF_BFIN_LOGO_DATA,
-		DEF_BFIN_LOGO_WIDTH,
-		DEF_BFIN_LOGO_HEIGHT,
-		DEF_BFIN_LOGO_BPP,
-		DEF_BFIN_LOGO_PIXEL_SIZE,
-		DEF_BFIN_LOGO_SIZE
-};
diff --git a/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_lzma.h b/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_lzma.h
deleted file mode 100644
index 1955f66..0000000
--- a/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_lzma.h
+++ /dev/null
@@ -1,1079 +0,0 @@
-/*
- * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
- *
- * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
- *
- * Where:	'screen'	is the pointer to the frame buffer
- *		'width'	is the screen width
- *		'x'		is the horizontal position
- *		'y'		is the vertical position
- */
-
-#define EASYLOGO_ENABLE_LZMA 16703
-
-static unsigned char EASYLOGO_DECOMP_BUFFER[105800];
-
-#include <video_easylogo.h>
-
-#define	DEF_BFIN_LOGO_WIDTH		230
-#define	DEF_BFIN_LOGO_HEIGHT		230
-#define	DEF_BFIN_LOGO_PIXELS		52900
-#define	DEF_BFIN_LOGO_BPP		16
-#define	DEF_BFIN_LOGO_PIXEL_SIZE	2
-#define	DEF_BFIN_LOGO_SIZE		105800
-
-unsigned char DEF_BFIN_LOGO_DATA[] = {
- 0x5d, 0x00, 0x00, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x6f,
- 0xfd, 0xff, 0xff, 0x86, 0x51, 0xd0, 0x3c, 0xfc, 0x65, 0xea, 0x02, 0x56, 0x77, 0x71, 0xde, 0xb1,
- 0x96, 0x62, 0x13, 0xa4, 0x11, 0xbb, 0x19, 0xd3, 0x9a, 0xab, 0x0c, 0x4c, 0x38, 0xa6, 0xe4, 0x24,
- 0x50, 0x2c, 0xfd, 0x3f, 0xd2, 0xc8, 0x41, 0x4b, 0xb3, 0x73, 0x7a, 0xdd, 0x22, 0x8d, 0x88, 0xd2,
- 0x32, 0x18, 0x2e, 0x8a, 0x93, 0x47, 0xf5, 0x99, 0xc7, 0x3f, 0x9c, 0xf5, 0xe7, 0x24, 0xbe, 0xe2,
- 0xbd, 0x73, 0xa7, 0x5a, 0xa6, 0x8d, 0x39, 0xa0, 0x0b, 0xfc, 0x62, 0x94, 0x5d, 0x17, 0xa1, 0x97,
- 0x72, 0xa9, 0xd4, 0xc5, 0xe3, 0x2e, 0x63, 0x86, 0x09, 0x55, 0x3c, 0xd5, 0xc2, 0xe4, 0x56, 0x1d,
- 0x05, 0xc5, 0x76, 0xe7, 0x35, 0x0c, 0x83, 0xbd, 0x33, 0x9b, 0x9f, 0xed, 0x10, 0xb2, 0x96, 0x1a,
- 0xe3, 0x9f, 0x16, 0x88, 0x0b, 0x5b, 0x7e, 0x9c, 0x8e, 0xd4, 0xd1, 0xc0, 0x1b, 0x36, 0xee, 0x23,
- 0xf3, 0xf9, 0xd7, 0x6e, 0xe0, 0x42, 0xe2, 0x99, 0xbe, 0x90, 0xb0, 0x6c, 0xc7, 0x2c, 0xa3, 0x75,
- 0xf6, 0xb6, 0x9d, 0x30, 0x18, 0x87, 0x9c, 0x49, 0x07, 0xf7, 0x78, 0x49, 0x72, 0xa3, 0x62, 0x28,
- 0x7d, 0xa1, 0xc9, 0x15, 0x76, 0x75, 0x63, 0xf7, 0xdf, 0xf4, 0x99, 0x81, 0xa7, 0x1f, 0xfd, 0x93,
- 0xfa, 0x71, 0x91, 0x1b, 0xbe, 0x3e, 0x38, 0xcf, 0x84, 0x51, 0x34, 0x43, 0x23, 0xa7, 0x31, 0x61,
- 0x44, 0x1b, 0x4d, 0x5c, 0x17, 0xcb, 0x39, 0xc6, 0x81, 0x8f, 0x10, 0xb1, 0x73, 0xa0, 0x51, 0x3e,
- 0xba, 0x38, 0xd1, 0x0f, 0x9a, 0x84, 0xc3, 0xa6, 0x30, 0x30, 0x27, 0x4a, 0x01, 0xf8, 0xca, 0xbf,
- 0xea, 0x0e, 0x6f, 0xe3, 0xeb, 0x7d, 0x8a, 0x59, 0x22, 0x07, 0x15, 0xe0, 0xcf, 0x04, 0xb6, 0x03,
- 0xdd, 0x71, 0xef, 0x6a, 0x25, 0xc2, 0x9d, 0x8f, 0xc1, 0x63, 0x2a, 0xec, 0xb8, 0x3e, 0x32, 0xee,
- 0xda, 0x98, 0x28, 0xc0, 0x60, 0x42, 0xe7, 0x0d, 0x38, 0x1b, 0xd0, 0xaa, 0x4c, 0xc4, 0x93, 0x19,
- 0x7a, 0x42, 0x41, 0xe5, 0xf8, 0xa8, 0x42, 0xbc, 0x9c, 0xb4, 0xd8, 0xd2, 0x85, 0xe6, 0x2d, 0xd6,
- 0xad, 0x5c, 0x6d, 0xaa, 0xf8, 0xa5, 0x81, 0xf8, 0x38, 0x05, 0xd9, 0x7c, 0xe2, 0x37, 0x5a, 0x47,
- 0x9d, 0xe7, 0x60, 0x1c, 0xbc, 0x02, 0x2b, 0x66, 0x3a, 0x49, 0xdb, 0xa0, 0xd3, 0x5d, 0x4c, 0xaf,
- 0x8c, 0x01, 0x4d, 0xe3, 0xce, 0xe7, 0x5a, 0xf1, 0x5e, 0x82, 0xd6, 0xcf, 0x69, 0x0c, 0x74, 0x42,
- 0x0a, 0xb3, 0xa3, 0x5a, 0x30, 0x40, 0xee, 0xf6, 0xea, 0xa6, 0xcc, 0x30, 0x44, 0x8c, 0x0f, 0xbc,
- 0x68, 0x0c, 0x49, 0x76, 0x06, 0x1c, 0x76, 0x91, 0xe2, 0xd4, 0x53, 0xc4, 0x29, 0x74, 0x2d, 0x81,
- 0x2e, 0x1f, 0x55, 0x27, 0x36, 0x73, 0x50, 0x24, 0x75, 0xcb, 0x5b, 0x3a, 0xc8, 0x82, 0x0a, 0xf7,
- 0x93, 0x25, 0x94, 0x3d, 0x4a, 0x85, 0x6c, 0xcc, 0x84, 0x1c, 0x5b, 0x58, 0xa9, 0x61, 0xe0, 0xde,
- 0xc2, 0x9e, 0xc6, 0x35, 0xaa, 0x9f, 0x2c, 0x98, 0x5b, 0xd7, 0x74, 0x10, 0x9f, 0x61, 0x8c, 0x67,
- 0x04, 0x3a, 0x1c, 0x37, 0x69, 0x3d, 0xb0, 0x07, 0x8c, 0xfc, 0x22, 0x65, 0x2d, 0x7c, 0x83, 0x91,
- 0x02, 0xc7, 0x4c, 0x59, 0xd3, 0x9e, 0x63, 0x44, 0x64, 0x3f, 0xb8, 0xc4, 0x24, 0x8e, 0xe4, 0xb9,
- 0x64, 0x11, 0x8a, 0x4e, 0x4f, 0xd7, 0x88, 0xb3, 0x5d, 0xb8, 0xe0, 0x19, 0x04, 0xf7, 0x47, 0xec,
- 0xf9, 0xa8, 0x4f, 0x6a, 0xa6, 0x66, 0x49, 0x1b, 0x34, 0xe9, 0xf9, 0x3c, 0x44, 0x51, 0x05, 0x1d,
- 0xb6, 0x81, 0x82, 0xc8, 0xc1, 0x26, 0x3c, 0x1d, 0x8a, 0xa8, 0x2d, 0x80, 0xc7, 0xc9, 0x47, 0x32,
- 0x67, 0x32, 0x05, 0xc1, 0xb1, 0x0a, 0x7e, 0x9b, 0x1e, 0x62, 0xb6, 0x6c, 0x1a, 0x82, 0xf2, 0x49,
- 0xbf, 0x14, 0x0d, 0x7f, 0x0f, 0x61, 0xf9, 0x6e, 0x9f, 0xfa, 0x6b, 0x63, 0x18, 0xfd, 0x36, 0x46,
- 0x1b, 0xc4, 0x76, 0x0e, 0x30, 0x60, 0x29, 0x31, 0x23, 0x42, 0x95, 0x99, 0xbd, 0x9f, 0x5b, 0xe3,
- 0xc8, 0xbd, 0xa4, 0xf9, 0xae, 0xce, 0xcf, 0x9e, 0x43, 0x8f, 0xe3, 0x9d, 0x5b, 0x3b, 0x4e, 0x87,
- 0xe9, 0x58, 0xda, 0x8d, 0xd7, 0x78, 0x43, 0x78, 0x52, 0x01, 0xf2, 0x31, 0xa4, 0x43, 0xeb, 0x84,
- 0x00, 0xf7, 0x5f, 0x2b, 0x63, 0x9d, 0xb9, 0x34, 0x86, 0x9c, 0x94, 0x33, 0xa4, 0x60, 0x36, 0xe0,
- 0x17, 0xf3, 0x6a, 0x7c, 0x0d, 0x3b, 0xe7, 0x7d, 0x2c, 0xc2, 0x92, 0x83, 0x5f, 0xc7, 0x39, 0x2d,
- 0xc6, 0x48, 0x61, 0xc4, 0xde, 0x32, 0x49, 0x8e, 0xbc, 0x7c, 0xf0, 0x18, 0xda, 0xe7, 0x7c, 0xef,
- 0x49, 0xd1, 0xa7, 0xf9, 0xa9, 0x11, 0x67, 0x33, 0x28, 0xee, 0x65, 0x47, 0x99, 0xa7, 0x83, 0xdf,
- 0x3f, 0x8c, 0x23, 0x2f, 0xb5, 0x55, 0xff, 0x79, 0x0b, 0xc0, 0xc7, 0x3d, 0x1e, 0x2b, 0xf9, 0x20,
- 0x93, 0x6b, 0x05, 0x50, 0x94, 0x0c, 0x5c, 0x3f, 0x94, 0x4b, 0x99, 0x10, 0x25, 0x4b, 0xb7, 0x1a,
- 0x8c, 0xe1, 0xaf, 0xe9, 0x8b, 0xde, 0x89, 0x50, 0xa8, 0x08, 0xbb, 0x1a, 0xec, 0xdf, 0xe8, 0x95,
- 0x06, 0x51, 0xe6, 0xb7, 0x26, 0x07, 0xeb, 0x5b, 0x8e, 0x4b, 0x50, 0x64, 0x5c, 0x8d, 0xb5, 0x52,
- 0x30, 0xf5, 0xc9, 0x07, 0xf2, 0x54, 0x4f, 0x7c, 0xb0, 0xfb, 0xa4, 0x48, 0xfd, 0x3c, 0x50, 0xbb,
- 0xcb, 0x39, 0xbe, 0x9a, 0x74, 0x44, 0x85, 0x01, 0x0f, 0x77, 0x1d, 0x86, 0x1f, 0x9a, 0x35, 0x06,
- 0x14, 0x48, 0x08, 0x6d, 0xc1, 0x89, 0xc6, 0x38, 0x5c, 0x8f, 0x1a, 0xc4, 0x89, 0xe7, 0x29, 0xa2,
- 0x87, 0x8a, 0xf2, 0xf7, 0x13, 0x5c, 0x2b, 0x0c, 0x17, 0x22, 0xc6, 0x02, 0x97, 0x5c, 0xe9, 0x10,
- 0xc4, 0xbd, 0x6b, 0x91, 0x9a, 0x0b, 0x70, 0x85, 0xd3, 0x91, 0xce, 0x12, 0x34, 0xef, 0xe3, 0xf7,
- 0xf6, 0xbf, 0x55, 0x0a, 0x67, 0xdd, 0x42, 0x7c, 0xa0, 0x46, 0xad, 0x30, 0xa1, 0xdf, 0x73, 0x6d,
- 0x93, 0x26, 0x57, 0xae, 0x2a, 0xe6, 0xea, 0x2c, 0xe5, 0xf3, 0x09, 0xaa, 0xdd, 0x09, 0xc7, 0xa0,
- 0x0c, 0xef, 0x86, 0xa8, 0x42, 0x93, 0x5e, 0x61, 0xe4, 0xa4, 0x08, 0xaa, 0x37, 0x4b, 0xd4, 0x94,
- 0x83, 0xe1, 0x42, 0x06, 0x65, 0x11, 0x4e, 0xbf, 0xc3, 0xfb, 0xbf, 0x86, 0x4f, 0x01, 0x69, 0x93,
- 0xd5, 0xc8, 0xb4, 0x5d, 0x23, 0x79, 0x38, 0x8a, 0x6b, 0x9f, 0xfb, 0x56, 0xb0, 0x16, 0x6e, 0x9f,
- 0xdf, 0x40, 0x96, 0x9c, 0x92, 0x17, 0xae, 0xdb, 0xba, 0x4e, 0xd6, 0x88, 0x44, 0x2f, 0xaf, 0x84,
- 0xa3, 0xb6, 0x04, 0xa1, 0x59, 0x42, 0x3f, 0xd4, 0x45, 0x0d, 0x76, 0xb2, 0x67, 0x6f, 0xab, 0xad,
- 0xe8, 0xda, 0x1d, 0x8e, 0x07, 0x96, 0xc5, 0x1c, 0xf9, 0x97, 0xe2, 0x21, 0x97, 0xd9, 0x4c, 0x79,
- 0x02, 0xe5, 0x0c, 0x57, 0x59, 0x1b, 0xcb, 0x09, 0x9a, 0xb3, 0x34, 0xc7, 0x0b, 0x66, 0x8a, 0xc9,
- 0x38, 0xa6, 0x2c, 0x27, 0xac, 0x20, 0xbd, 0x69, 0x54, 0xa1, 0x33, 0x9a, 0x70, 0x4f, 0x9d, 0xe2,
- 0x6e, 0x79, 0x72, 0x17, 0xfc, 0x12, 0xe9, 0x96, 0x0c, 0x12, 0x5d, 0x44, 0xb7, 0x71, 0x87, 0x03,
- 0xeb, 0x2d, 0x30, 0x1f, 0xe8, 0xa0, 0x70, 0x60, 0xb4, 0x4d, 0x98, 0xcb, 0xa3, 0x58, 0x94, 0x04,
- 0xa2, 0xae, 0x14, 0xca, 0xf4, 0x6b, 0x22, 0x12, 0x04, 0xcc, 0x28, 0x7e, 0xea, 0x66, 0xb6, 0x18,
- 0x86, 0xdc, 0xcc, 0xef, 0xeb, 0x3a, 0x3e, 0x4e, 0xcc, 0xd5, 0x94, 0xc7, 0x5e, 0xdd, 0x1f, 0x96,
- 0xd0, 0x8f, 0x18, 0xe9, 0xbf, 0xe0, 0xda, 0x0c, 0x80, 0xaa, 0x29, 0xef, 0x31, 0xd7, 0x69, 0xfc,
- 0x35, 0xa5, 0xb6, 0x91, 0x0f, 0x44, 0x8f, 0x32, 0x34, 0x69, 0x6d, 0xc7, 0x44, 0xa7, 0xa6, 0x58,
- 0x01, 0xef, 0x51, 0x41, 0xef, 0x5c, 0xa6, 0xff, 0x92, 0xcd, 0xc7, 0x4c, 0xc8, 0x2a, 0x0d, 0x9c,
- 0xdb, 0x05, 0x55, 0x31, 0xfb, 0x74, 0x2b, 0x87, 0x3b, 0x2e, 0x38, 0x71, 0x15, 0xff, 0xa2, 0x51,
- 0xcc, 0x3d, 0xa7, 0xfc, 0xc3, 0xfd, 0x8e, 0x24, 0x1d, 0x5f, 0x61, 0x4a, 0x4b, 0x5d, 0xd8, 0x9b,
- 0x46, 0x72, 0x48, 0xf3, 0xcf, 0xbc, 0x41, 0xde, 0xc7, 0x44, 0xf1, 0x29, 0xfc, 0x14, 0xa6, 0x76,
- 0x5a, 0xec, 0x23, 0x38, 0xa1, 0xee, 0xd8, 0x46, 0x2a, 0x6e, 0xf2, 0x0e, 0x45, 0xa6, 0x11, 0x21,
- 0xfd, 0x3a, 0xc2, 0x1b, 0xdb, 0xb3, 0x0b, 0x1f, 0xe0, 0xc4, 0xf6, 0x75, 0xf7, 0x0f, 0xee, 0x15,
- 0xc3, 0x83, 0x65, 0xc4, 0x0c, 0x59, 0x6e, 0xdc, 0x43, 0x25, 0x2a, 0x66, 0x6d, 0x32, 0x3b, 0x0c,
- 0xb6, 0x78, 0xe3, 0xde, 0x21, 0xc3, 0xcf, 0xb8, 0x70, 0x8d, 0xcf, 0xd8, 0x5e, 0x18, 0xb1, 0x89,
- 0x6e, 0x99, 0xb6, 0x02, 0x36, 0xde, 0x1b, 0x85, 0xb4, 0xd7, 0x71, 0x89, 0x0e, 0x70, 0x4d, 0x7f,
- 0x44, 0xa0, 0xcc, 0x2d, 0xb3, 0xfb, 0x3a, 0x99, 0x7e, 0xea, 0x16, 0xda, 0x1d, 0x88, 0x8b, 0x03,
- 0xf6, 0x74, 0x1c, 0xd9, 0x2b, 0x84, 0xb4, 0xa9, 0x65, 0xab, 0x5d, 0xa6, 0x7f, 0x1f, 0x29, 0x3b,
- 0x9c, 0x85, 0x08, 0x75, 0x85, 0x6e, 0xb8, 0xc9, 0x0c, 0x50, 0xb9, 0x04, 0x3d, 0x38, 0x90, 0x78,
- 0x55, 0x27, 0x71, 0xc4, 0xec, 0x18, 0x6e, 0x60, 0xd5, 0xa0, 0x63, 0xd0, 0x93, 0xa0, 0x5f, 0x51,
- 0xf0, 0x1f, 0x6a, 0x9b, 0x5a, 0xb4, 0x65, 0x6a, 0x67, 0x4e, 0x1d, 0x40, 0xaa, 0x9a, 0x31, 0x84,
- 0xf4, 0xd2, 0xd7, 0x4f, 0x09, 0x0f, 0x02, 0xe9, 0xc6, 0x1b, 0x20, 0x9a, 0xe5, 0x11, 0x21, 0x0d,
- 0x13, 0x5c, 0xc6, 0x93, 0x26, 0xb5, 0xb3, 0x95, 0x3b, 0xf0, 0x93, 0x7e, 0x8c, 0xdc, 0xe1, 0xfe,
- 0x58, 0x18, 0xb1, 0xb0, 0xd9, 0x0f, 0x9e, 0xad, 0x51, 0x05, 0x41, 0x24, 0xb6, 0xb8, 0xbe, 0xc2,
- 0x84, 0x30, 0x82, 0xf6, 0x3b, 0x4e, 0x84, 0xf7, 0xe6, 0xc5, 0x20, 0x1e, 0x53, 0x42, 0xad, 0x0b,
- 0x39, 0x97, 0x70, 0xbf, 0x59, 0xf9, 0x24, 0xbb, 0x03, 0x07, 0xed, 0xc2, 0xf0, 0xf0, 0x91, 0x8f,
- 0x6b, 0x1f, 0x70, 0x49, 0x0a, 0x52, 0x99, 0x4e, 0xcf, 0x9b, 0x22, 0x0b, 0x26, 0xae, 0x0d, 0xe6,
- 0x23, 0x36, 0x7c, 0xd5, 0xbe, 0x65, 0x1c, 0xdb, 0x68, 0x2d, 0x12, 0xe2, 0x1a, 0xc8, 0xd9, 0x74,
- 0x25, 0x3a, 0x44, 0x8e, 0x84, 0x35, 0xf6, 0x6c, 0x96, 0x71, 0x19, 0xdf, 0x58, 0x6a, 0xf2, 0xbc,
- 0x6f, 0x5a, 0xfe, 0xd2, 0x77, 0x68, 0x8e, 0xae, 0xab, 0x9e, 0x3c, 0xd7, 0xc5, 0x15, 0xe4, 0xc2,
- 0xe1, 0xa2, 0xb1, 0xa8, 0xfe, 0x7b, 0xb1, 0x0e, 0x21, 0x39, 0xa9, 0xe4, 0xa8, 0xcc, 0xa7, 0x12,
- 0xc6, 0x64, 0x6b, 0xf8, 0x85, 0xed, 0xfc, 0x8e, 0x17, 0x7c, 0x8e, 0xd0, 0x7a, 0xfb, 0x53, 0x99,
- 0x1c, 0x36, 0xe3, 0x39, 0x32, 0xd2, 0x56, 0x16, 0xcb, 0xba, 0x03, 0x05, 0xfc, 0x65, 0x25, 0x83,
- 0xec, 0xe6, 0x92, 0x84, 0xbf, 0x8b, 0x4f, 0x89, 0x75, 0x4f, 0x5b, 0x9e, 0xd4, 0x79, 0x1e, 0xc7,
- 0xee, 0xb2, 0x44, 0xcd, 0x59, 0x45, 0x34, 0xc9, 0xe8, 0x03, 0xca, 0x99, 0x19, 0x56, 0x62, 0x51,
- 0xc5, 0x40, 0xd2, 0xfb, 0x85, 0xb2, 0xf0, 0x02, 0xab, 0x58, 0x98, 0x60, 0x42, 0xda, 0x81, 0xbb,
- 0x63, 0x45, 0x85, 0x62, 0x21, 0x6b, 0xa9, 0x95, 0x12, 0x0a, 0x25, 0xb3, 0x99, 0xfa, 0x5f, 0x3a,
- 0xb2, 0xc5, 0xdb, 0x92, 0x21, 0x19, 0x8d, 0x38, 0x45, 0xbb, 0xa4, 0xa3, 0xf2, 0xb5, 0xdf, 0xe2,
- 0x94, 0xd8, 0xed, 0xf7, 0xf8, 0x85, 0x80, 0xb5, 0x87, 0xf1, 0x1a, 0xd0, 0xfb, 0x71, 0x4e, 0x2b,
- 0xd8, 0xdf, 0x96, 0x73, 0x31, 0xf2, 0x3f, 0x4b, 0x76, 0xac, 0xd1, 0xdd, 0x0c, 0x47, 0x78, 0x4e,
- 0xc6, 0x13, 0x14, 0x13, 0xf5, 0xa5, 0xde, 0x87, 0x55, 0xd1, 0xdc, 0x13, 0x56, 0x54, 0x8a, 0x17,
- 0xd8, 0x0d, 0x72, 0x6a, 0x60, 0x84, 0xd1, 0x07, 0xfd, 0x0b, 0x99, 0x77, 0x66, 0x96, 0x9b, 0x22,
- 0x23, 0x04, 0xc1, 0x21, 0x1c, 0x90, 0x65, 0x24, 0x63, 0xc8, 0xaf, 0x1a, 0xdb, 0xe0, 0xe0, 0x66,
- 0xf4, 0x34, 0xeb, 0x35, 0x28, 0x61, 0xbc, 0x20, 0x7a, 0xdc, 0x77, 0x1b, 0xf0, 0xd4, 0xbd, 0xb8,
- 0xb3, 0xaa, 0x61, 0x59, 0x45, 0x9e, 0x89, 0x77, 0xc4, 0xfd, 0xbc, 0x5c, 0xb0, 0xcf, 0x76, 0x0f,
- 0x49, 0xa8, 0xa4, 0x23, 0x34, 0x81, 0x41, 0xc7, 0xc8, 0x81, 0x5a, 0xb8, 0xf7, 0x20, 0x8c, 0xed,
- 0xc2, 0x59, 0x97, 0xa0, 0x9e, 0x1c, 0x27, 0xaf, 0x43, 0xcd, 0x8a, 0xb0, 0x6c, 0x6d, 0xbc, 0x75,
- 0x4c, 0x8f, 0x66, 0x6a, 0x7c, 0xb7, 0x8a, 0x40, 0xcb, 0xed, 0xce, 0xe7, 0x82, 0xfe, 0x33, 0x6e,
- 0xc2, 0xf6, 0xa0, 0x9a, 0xcb, 0x01, 0xa2, 0xd6, 0xb0, 0xf8, 0x2a, 0x97, 0xfb, 0x8e, 0xbd, 0x39,
- 0xd5, 0xfb, 0x95, 0xdf, 0xe3, 0x3b, 0x72, 0x46, 0x06, 0x5f, 0xd5, 0xb2, 0x70, 0xb8, 0x9d, 0x9b,
- 0xee, 0x7e, 0xeb, 0x9b, 0x84, 0xb2, 0x47, 0x56, 0xc7, 0xc6, 0x3e, 0xcd, 0x0d, 0x83, 0x83, 0x5c,
- 0x0f, 0x2b, 0x37, 0x7b, 0x09, 0x35, 0xc7, 0x9c, 0x96, 0x00, 0xbe, 0x91, 0xaf, 0x3e, 0xa4, 0xff,
- 0xd9, 0x73, 0x3f, 0x19, 0x57, 0xd1, 0xf6, 0xcc, 0x72, 0xbc, 0x5a, 0xfd, 0x15, 0x57, 0xd0, 0x0b,
- 0x79, 0xfb, 0x14, 0x3e, 0x67, 0x19, 0x9f, 0xec, 0x07, 0xe2, 0x48, 0x51, 0x1d, 0x4d, 0x70, 0xfa,
- 0x0d, 0xe5, 0xa7, 0x9c, 0x05, 0x8a, 0x81, 0x7d, 0x94, 0x0d, 0x96, 0x69, 0xf7, 0xc7, 0x7c, 0xe1,
- 0x26, 0xf8, 0x58, 0xf5, 0xad, 0x41, 0x36, 0xdd, 0xc2, 0xe6, 0x34, 0xa3, 0x2e, 0x35, 0x2a, 0x80,
- 0x12, 0x3b, 0x71, 0x86, 0xb5, 0x14, 0xc9, 0x38, 0x50, 0x6a, 0xd4, 0xa1, 0x24, 0x8c, 0xe8, 0xa6,
- 0x20, 0x6a, 0xfa, 0x3e, 0xc3, 0x64, 0xc4, 0x02, 0xa3, 0xe8, 0xa3, 0xb8, 0x6a, 0x29, 0xfe, 0x76,
- 0xbb, 0x3e, 0xaa, 0x11, 0xc5, 0x64, 0x76, 0xcc, 0x75, 0xc1, 0xfe, 0xe6, 0x8b, 0xf3, 0x47, 0x80,
- 0x11, 0xf3, 0x69, 0x2b, 0x90, 0x31, 0xb5, 0xc6, 0x85, 0x08, 0xe6, 0xb6, 0x2e, 0xe2, 0x05, 0xf5,
- 0x64, 0xbe, 0x2d, 0xb9, 0xba, 0xcb, 0x84, 0xba, 0x30, 0x5e, 0xb1, 0xbe, 0x59, 0xa7, 0x7e, 0x0d,
- 0x9f, 0xc0, 0xb0, 0x5e, 0x21, 0x3b, 0x18, 0xf2, 0x98, 0x23, 0x78, 0xfd, 0xbd, 0xb8, 0xbf, 0x54,
- 0xaf, 0xe8, 0xe4, 0x40, 0x60, 0xfa, 0x41, 0x65, 0xc2, 0x41, 0x5f, 0x59, 0xd4, 0xef, 0xb1, 0x20,
- 0x0c, 0x5a, 0xf2, 0xa0, 0x90, 0xfc, 0x21, 0xec, 0xa1, 0x78, 0xd4, 0x89, 0xc2, 0x55, 0x55, 0x0c,
- 0x50, 0x65, 0x80, 0x5f, 0x0a, 0x9b, 0xd1, 0xa7, 0xdd, 0xc4, 0x8b, 0x62, 0xe5, 0xfd, 0x80, 0x19,
- 0x33, 0x92, 0x0a, 0xad, 0xac, 0x7d, 0x16, 0xe3, 0xe2, 0xcb, 0xc3, 0x53, 0x66, 0x94, 0xe1, 0xbe,
- 0x84, 0xd1, 0xcd, 0xbf, 0x21, 0x8b, 0x83, 0x44, 0xde, 0xa6, 0x73, 0x45, 0x40, 0xf6, 0x63, 0xc7,
- 0x07, 0x20, 0x35, 0x98, 0xc2, 0x03, 0x2d, 0xd7, 0xdd, 0xb8, 0xe6, 0x77, 0x37, 0xfb, 0x00, 0x18,
- 0x47, 0x0b, 0x22, 0xaa, 0x1e, 0x97, 0x5c, 0x57, 0x44, 0xa5, 0x86, 0xb5, 0x0f, 0xdc, 0x2c, 0x17,
- 0x37, 0xbe, 0x8c, 0x55, 0x5c, 0x09, 0x4b, 0xa5, 0x82, 0xce, 0x2f, 0xd4, 0xa9, 0x1b, 0x87, 0x85,
- 0x36, 0xde, 0x43, 0x4d, 0xab, 0xc8, 0xa7, 0xc6, 0x13, 0xe0, 0xbe, 0x56, 0x6e, 0xeb, 0xa9, 0xeb,
- 0xad, 0x39, 0x8b, 0x46, 0x4a, 0xc3, 0xa7, 0xe3, 0x6f, 0xca, 0x48, 0x2c, 0x9d, 0x33, 0x49, 0xc3,
- 0xf6, 0xc9, 0x50, 0xc4, 0x85, 0x6a, 0x0f, 0x07, 0x3d, 0x65, 0x1c, 0x36, 0xe9, 0x3a, 0x68, 0x79,
- 0x53, 0x41, 0xc0, 0x28, 0x04, 0x34, 0x03, 0xbc, 0x56, 0xe6, 0x7e, 0x8b, 0x98, 0x15, 0xb8, 0x21,
- 0x55, 0x39, 0x79, 0x44, 0xb9, 0x39, 0x9e, 0x7a, 0xd6, 0xde, 0x70, 0x59, 0xe4, 0x5f, 0x54, 0x14,
- 0xae, 0x3c, 0xd5, 0x59, 0x28, 0x21, 0x71, 0xa4, 0xa0, 0xc7, 0xf5, 0x09, 0xa0, 0xa2, 0x5f, 0x88,
- 0x56, 0xe7, 0xb5, 0x10, 0x4d, 0xf5, 0x9d, 0x27, 0xb0, 0x45, 0x91, 0x6c, 0x85, 0x41, 0xc6, 0x05,
- 0x5e, 0x90, 0x58, 0x65, 0x6b, 0x3b, 0x8a, 0x44, 0xff, 0xdd, 0xeb, 0x1b, 0xb7, 0xfd, 0x0c, 0xef,
- 0x7d, 0x19, 0xc8, 0x13, 0x0b, 0x5c, 0x93, 0x73, 0x8a, 0x7e, 0x5a, 0x1f, 0x87, 0x37, 0x36, 0xd2,
- 0xc5, 0x1f, 0xfb, 0xc9, 0x7c, 0x15, 0xf5, 0xc9, 0x5e, 0xec, 0x14, 0x07, 0xcf, 0x9b, 0xd4, 0x99,
- 0xa8, 0x48, 0xa1, 0xf1, 0xbe, 0xc6, 0xdd, 0xde, 0x94, 0x38, 0x2a, 0xfe, 0x1a, 0xf0, 0x43, 0x9d,
- 0x14, 0x98, 0x8c, 0xec, 0xc1, 0xd2, 0x09, 0xab, 0xc2, 0xd1, 0x16, 0x7c, 0xe7, 0xf5, 0x63, 0x09,
- 0xb5, 0xdc, 0x4e, 0xea, 0x22, 0xff, 0xd2, 0x16, 0x02, 0x66, 0x12, 0x54, 0x74, 0xe5, 0x51, 0xa0,
- 0xc8, 0x66, 0x80, 0x0b, 0x6f, 0x0a, 0x03, 0x5a, 0x01, 0xd8, 0xf1, 0x4e, 0xf1, 0x5e, 0xff, 0x42,
- 0x2e, 0x6d, 0x30, 0x59, 0x5a, 0x66, 0xe0, 0x8f, 0xb2, 0x98, 0x97, 0x48, 0x55, 0x0a, 0x65, 0x7d,
- 0xdd, 0x2b, 0x1d, 0xcb, 0x7b, 0x5b, 0x06, 0x0c, 0xfe, 0xf3, 0x41, 0x2f, 0x2d, 0xa5, 0xc6, 0xc0,
- 0xf4, 0xdb, 0xb0, 0xe1, 0xe1, 0xed, 0xbe, 0x20, 0x48, 0xdb, 0x97, 0x69, 0x2b, 0x10, 0x24, 0x77,
- 0x66, 0x65, 0xeb, 0x91, 0x85, 0xc6, 0x23, 0xcf, 0xbc, 0xb7, 0x2c, 0x6a, 0x9d, 0x68, 0xce, 0xa7,
- 0x47, 0x09, 0x48, 0xa4, 0xc3, 0xec, 0x33, 0x91, 0xf6, 0x8e, 0x65, 0x25, 0xe8, 0x2f, 0xa9, 0xeb,
- 0xf8, 0x3b, 0x12, 0xdd, 0xaa, 0x27, 0x5e, 0x40, 0xa8, 0x6f, 0xc4, 0xf4, 0x97, 0x50, 0xbf, 0xd2,
- 0xc0, 0x37, 0x73, 0xdb, 0x01, 0x87, 0x03, 0xc3, 0x50, 0x85, 0x60, 0xae, 0x52, 0x8c, 0xf2, 0x7b,
- 0xe8, 0x3b, 0x63, 0xc0, 0x62, 0x62, 0x23, 0x24, 0xb9, 0xe8, 0x9a, 0xd7, 0xb5, 0xd9, 0x0c, 0x1e,
- 0x0d, 0xf1, 0xdd, 0xb6, 0xf1, 0xde, 0x1e, 0x79, 0xa7, 0xf1, 0xfb, 0x94, 0xb3, 0x6e, 0x96, 0x8c,
- 0x6d, 0xdd, 0x05, 0x0c, 0xa3, 0xc6, 0xce, 0x52, 0xe8, 0x55, 0x4a, 0xef, 0x6b, 0x00, 0x96, 0x13,
- 0x8a, 0x2c, 0xfe, 0xab, 0x4f, 0xed, 0xb3, 0x64, 0xd6, 0x72, 0x54, 0x36, 0x2f, 0x85, 0xb6, 0x8b,
- 0xfd, 0x91, 0x37, 0xec, 0x72, 0xb1, 0xf0, 0xe6, 0xc1, 0x21, 0x3d, 0x1c, 0x45, 0x05, 0x37, 0x9f,
- 0xbe, 0x2d, 0x32, 0xfa, 0x30, 0xa9, 0x1d, 0x02, 0x14, 0xe4, 0x94, 0xaa, 0x61, 0x32, 0x23, 0x2a,
- 0x47, 0x01, 0xba, 0x7c, 0x80, 0x80, 0xaa, 0xfa, 0xa8, 0xaf, 0xba, 0xfe, 0xdc, 0x3d, 0x75, 0x85,
- 0x49, 0x34, 0x04, 0x13, 0xbf, 0xfa, 0x87, 0x2e, 0x17, 0x48, 0xef, 0xcb, 0xc9, 0x63, 0xad, 0xae,
- 0x97, 0xb9, 0x2e, 0x9d, 0x4a, 0xcc, 0x3f, 0x10, 0x8a, 0x9e, 0x62, 0x5a, 0x9f, 0x3c, 0x52, 0x5d,
- 0xf0, 0xa9, 0xb9, 0x64, 0x4c, 0xad, 0x4d, 0x12, 0x99, 0xb7, 0x30, 0x8a, 0x59, 0xb8, 0xff, 0xcd,
- 0x96, 0xc1, 0x0d, 0x22, 0xef, 0xd1, 0x45, 0xa5, 0x95, 0x5d, 0x24, 0x15, 0x59, 0x28, 0x09, 0xfe,
- 0x9b, 0xa7, 0x5c, 0x10, 0x23, 0x75, 0x57, 0xcc, 0x12, 0x69, 0xc2, 0x89, 0x9b, 0xac, 0x01, 0x8b,
- 0x20, 0x24, 0x77, 0x7c, 0x74, 0x6d, 0x7e, 0x34, 0x9c, 0x6b, 0xf8, 0x39, 0x2f, 0x8f, 0x16, 0x85,
- 0x84, 0xa5, 0x43, 0x90, 0xe2, 0xd2, 0x89, 0x1e, 0xa4, 0x3a, 0x27, 0x8f, 0xfc, 0xe2, 0x00, 0xbd,
- 0x12, 0x66, 0x63, 0x65, 0x85, 0xc2, 0x79, 0x4a, 0xf6, 0xb2, 0xbb, 0x45, 0x1e, 0x6e, 0xe8, 0x09,
- 0x91, 0xe4, 0x68, 0x5d, 0x2a, 0x0e, 0xc4, 0xab, 0x31, 0x99, 0xf2, 0x68, 0x01, 0x0a, 0x18, 0xab,
- 0xb4, 0x3a, 0xb5, 0x3e, 0x4c, 0xb8, 0x87, 0x9c, 0xff, 0xa5, 0x35, 0xfd, 0x5b, 0xf0, 0x17, 0xc1,
- 0x58, 0xff, 0xfe, 0xcb, 0x54, 0x72, 0x4f, 0xdc, 0xbf, 0xd8, 0x14, 0x6d, 0xfb, 0x7f, 0xbc, 0xd9,
- 0xc3, 0x7b, 0x87, 0x55, 0x7a, 0x1f, 0x71, 0xae, 0xe7, 0xd9, 0x17, 0xc3, 0x34, 0x49, 0x82, 0x92,
- 0x25, 0xd2, 0xce, 0xba, 0x17, 0x98, 0x48, 0x9e, 0x04, 0x4c, 0x67, 0xb1, 0xfa, 0x3d, 0xe5, 0x8d,
- 0xa1, 0x08, 0x79, 0x7c, 0xd0, 0x22, 0x57, 0xc4, 0x16, 0x11, 0xd3, 0xb1, 0xe4, 0xac, 0x7d, 0x38,
- 0xee, 0x3a, 0xf2, 0x47, 0x6b, 0xf9, 0x7f, 0x88, 0xbe, 0x86, 0x10, 0x6f, 0x19, 0x52, 0x86, 0x7c,
- 0x25, 0xbc, 0x13, 0x4f, 0x02, 0x30, 0x85, 0xca, 0x2b, 0x62, 0x41, 0x7e, 0xd3, 0x69, 0x76, 0x9f,
- 0xb6, 0x17, 0x68, 0x36, 0xd3, 0x87, 0x59, 0x9d, 0x8c, 0x62, 0xa9, 0x4b, 0x0c, 0x68, 0x76, 0xaf,
- 0xc1, 0x0e, 0xb9, 0x36, 0xea, 0x4f, 0xd1, 0x29, 0x68, 0xfc, 0x55, 0x7b, 0xac, 0x35, 0xb3, 0xff,
- 0xa3, 0xcd, 0x5e, 0xf4, 0x63, 0x9c, 0x51, 0x92, 0x66, 0x9b, 0x45, 0xf0, 0x5f, 0xce, 0x9f, 0x63,
- 0x04, 0x42, 0x1c, 0x07, 0x6f, 0xa7, 0x6e, 0xbf, 0xd6, 0xd1, 0x96, 0x74, 0x76, 0x8d, 0x82, 0xb1,
- 0x2b, 0x50, 0xcd, 0xfa, 0x3b, 0x16, 0x9a, 0xf6, 0x92, 0xb5, 0xa2, 0x6f, 0x95, 0x87, 0xf0, 0xc7,
- 0x07, 0x0d, 0x75, 0x0c, 0x21, 0x94, 0xf5, 0x6a, 0x3a, 0x7f, 0xc1, 0xcd, 0x1a, 0x10, 0x1c, 0x94,
- 0x18, 0x02, 0x4c, 0xa5, 0x17, 0x1e, 0x26, 0x1c, 0x38, 0x02, 0x5d, 0x5a, 0xd7, 0x9b, 0xf2, 0xfd,
- 0x49, 0x09, 0x64, 0xf5, 0x27, 0x66, 0x06, 0x75, 0x59, 0x66, 0xf2, 0xc5, 0xf3, 0xdb, 0x25, 0x16,
- 0x05, 0x6d, 0xc2, 0xf7, 0xbb, 0x27, 0xa2, 0x20, 0x40, 0x9e, 0x0d, 0xe8, 0x30, 0x9c, 0xfb, 0xff,
- 0xc2, 0xee, 0xc1, 0x13, 0x18, 0x8a, 0x57, 0x3b, 0x8f, 0x36, 0xc8, 0x56, 0xfe, 0xfb, 0x79, 0x3b,
- 0x3d, 0xbf, 0x21, 0x89, 0x7f, 0x8e, 0xcd, 0xdd, 0x25, 0x1f, 0x82, 0xca, 0x36, 0x9a, 0x17, 0x60,
- 0xb1, 0x12, 0xd3, 0x12, 0x0b, 0x9d, 0x29, 0xcf, 0x2c, 0xe5, 0xa6, 0xe5, 0xbe, 0xe2, 0xba, 0x0b,
- 0xc2, 0x05, 0x30, 0xa6, 0x25, 0x25, 0xa1, 0xfa, 0xff, 0x50, 0xae, 0x1a, 0xed, 0x57, 0xc6, 0x48,
- 0x1f, 0x60, 0x76, 0xe9, 0xfc, 0x95, 0xbb, 0x4e, 0xea, 0x6d, 0xeb, 0xf7, 0xb9, 0x9e, 0x55, 0x3d,
- 0xad, 0x27, 0x11, 0x55, 0x71, 0xc7, 0x5f, 0x29, 0xc8, 0xbf, 0x9d, 0xcb, 0x66, 0x4f, 0xc3, 0x8a,
- 0x9b, 0x9d, 0x4e, 0x45, 0x00, 0x7d, 0x6c, 0xf8, 0xb9, 0x53, 0x23, 0x7a, 0x28, 0xaf, 0x7c, 0x7a,
- 0xcf, 0x40, 0xf7, 0x90, 0xeb, 0x8c, 0x5b, 0x62, 0x0a, 0x63, 0x31, 0xa0, 0x1e, 0x42, 0xf2, 0x9c,
- 0xa6, 0x87, 0x68, 0x8d, 0xad, 0x77, 0x6f, 0xed, 0x11, 0x5e, 0x94, 0x09, 0x30, 0x78, 0x4c, 0xae,
- 0x8c, 0xdf, 0xda, 0x48, 0xd3, 0x2e, 0x61, 0x90, 0x77, 0x33, 0xe8, 0x78, 0xa4, 0xdd, 0x3b, 0x73,
- 0xd7, 0xc6, 0xb3, 0xbc, 0x9d, 0x72, 0x8d, 0x2d, 0xec, 0x46, 0x1f, 0x4e, 0xe3, 0xc3, 0x69, 0x0e,
- 0x67, 0xe3, 0x04, 0x55, 0x3b, 0xb0, 0x7e, 0xb3, 0x68, 0x67, 0x3f, 0x2e, 0xd8, 0xee, 0x40, 0xfd,
- 0xbc, 0x77, 0xd8, 0x83, 0xa5, 0x9d, 0xde, 0xd8, 0x93, 0x89, 0x22, 0xdb, 0x05, 0x01, 0x1d, 0x14,
- 0x71, 0x84, 0xed, 0x8f, 0x36, 0x14, 0x12, 0x6f, 0xfa, 0x89, 0x60, 0x79, 0x73, 0x0c, 0xaa, 0x49,
- 0x29, 0xce, 0xb9, 0x76, 0x53, 0x6d, 0xe0, 0x0a, 0xe2, 0x36, 0xc2, 0xb7, 0x4b, 0x82, 0x9f, 0xce,
- 0x81, 0xb5, 0xc4, 0xf1, 0xd4, 0x58, 0x42, 0x5f, 0xb4, 0xcc, 0x24, 0xcd, 0x18, 0x3c, 0x66, 0xf1,
- 0xab, 0x68, 0x6d, 0x36, 0xed, 0x32, 0x40, 0xa2, 0x07, 0x7a, 0x7e, 0x45, 0x53, 0x6c, 0xcb, 0x27,
- 0xd4, 0x81, 0x36, 0x1b, 0x4b, 0x00, 0x7d, 0x1f, 0xf3, 0xb0, 0x79, 0xc6, 0x48, 0xdd, 0x6c, 0x6a,
- 0xd3, 0x9f, 0xf4, 0xad, 0xc4, 0xcd, 0x45, 0xa7, 0xaf, 0xdc, 0x13, 0x66, 0xe2, 0xaf, 0xca, 0xa3,
- 0x42, 0x5c, 0xbf, 0x08, 0x79, 0x20, 0x07, 0xc5, 0xd6, 0x82, 0x34, 0x39, 0x2c, 0xe3, 0xd3, 0x8d,
- 0x12, 0x1d, 0x9f, 0x98, 0xe8, 0x1a, 0xcc, 0x0d, 0xbf, 0xc5, 0x2f, 0x62, 0xbb, 0x0e, 0x23, 0x50,
- 0x92, 0x92, 0xf0, 0xce, 0x70, 0x5d, 0x51, 0x38, 0x2c, 0x9c, 0xc8, 0xc0, 0xbb, 0xa4, 0x9b, 0x81,
- 0x83, 0xa9, 0x32, 0xe7, 0x3a, 0x47, 0x2a, 0xd3, 0xbc, 0x09, 0xd4, 0x5a, 0x1f, 0xf1, 0x72, 0xb8,
- 0xaf, 0xba, 0x24, 0x2f, 0x25, 0xd9, 0xc0, 0x76, 0xe1, 0xee, 0x7d, 0x7f, 0x60, 0x42, 0xfc, 0xec,
- 0xe3, 0x32, 0x13, 0x46, 0x7e, 0x5c, 0x8e, 0xa1, 0x46, 0xe8, 0x93, 0x14, 0xd7, 0x90, 0xf9, 0x80,
- 0xfa, 0x4f, 0xd7, 0x03, 0x0d, 0x97, 0x22, 0xc0, 0x6b, 0xbd, 0x97, 0xb3, 0x0e, 0xf4, 0xc5, 0x92,
- 0x42, 0x6b, 0x1b, 0xeb, 0xdc, 0x13, 0x13, 0x01, 0x42, 0x1c, 0xf0, 0x88, 0x31, 0x2c, 0x42, 0x59,
- 0x67, 0x7e, 0xff, 0x77, 0xab, 0xc1, 0x47, 0x50, 0x51, 0x64, 0x7d, 0x8f, 0xec, 0x68, 0xcc, 0x34,
- 0x76, 0xbf, 0x65, 0x89, 0x9c, 0x18, 0x7b, 0x21, 0x86, 0xbf, 0x3d, 0x79, 0xae, 0x6f, 0xc2, 0x12,
- 0x21, 0x3a, 0x95, 0x62, 0x65, 0xc9, 0xcc, 0xee, 0x08, 0x3a, 0xaf, 0xe9, 0x31, 0xe5, 0x6a, 0xa2,
- 0x27, 0x30, 0x34, 0x7b, 0x04, 0xf0, 0xe7, 0xd5, 0x14, 0x95, 0xd5, 0xbc, 0x05, 0x94, 0x4e, 0xb9,
- 0xa9, 0x1d, 0x10, 0x20, 0xe9, 0xbd, 0xf8, 0x44, 0xbe, 0x95, 0xb0, 0x2b, 0x9e, 0x3c, 0xd2, 0x5c,
- 0x47, 0x89, 0x0a, 0xee, 0xa9, 0xb8, 0xc9, 0xb5, 0x3f, 0x19, 0xf5, 0xf8, 0x33, 0x18, 0x9d, 0xa9,
- 0x01, 0xcf, 0xdc, 0xa2, 0x6c, 0x85, 0xde, 0x19, 0x24, 0xdd, 0x36, 0x19, 0x1a, 0x54, 0x9f, 0x52,
- 0xd3, 0xf8, 0xf5, 0x88, 0x73, 0x9f, 0xf7, 0x98, 0xa6, 0x41, 0x0d, 0xe0, 0xfe, 0xf8, 0x18, 0xb2,
- 0xe9, 0x2a, 0x60, 0x0e, 0xf3, 0xbe, 0x56, 0x8b, 0xee, 0x17, 0x8e, 0x56, 0x5e, 0x62, 0x7d, 0xb6,
- 0x18, 0x95, 0xba, 0xb5, 0xb3, 0x0e, 0x1c, 0x1b, 0x28, 0xb8, 0x8d, 0x0c, 0x63, 0x14, 0x37, 0x41,
- 0xa2, 0xe7, 0xf6, 0x63, 0x2e, 0xf8, 0x6c, 0x63, 0x45, 0xfc, 0x95, 0xb0, 0x90, 0xd3, 0x1e, 0x4f,
- 0x58, 0xfd, 0x40, 0xad, 0x6a, 0x1a, 0x82, 0x4c, 0x57, 0xae, 0x10, 0x69, 0x1f, 0xe0, 0xca, 0x67,
- 0x53, 0x6b, 0xb4, 0x8c, 0x5c, 0x67, 0x4b, 0x1d, 0x2f, 0x24, 0x50, 0xbd, 0xa8, 0xf3, 0x50, 0x23,
- 0xd2, 0xab, 0x48, 0x8f, 0x87, 0x01, 0xc0, 0x2d, 0x4d, 0x67, 0xee, 0x31, 0x87, 0x29, 0xd1, 0xd5,
- 0x49, 0x29, 0x86, 0x2b, 0x07, 0x05, 0xaa, 0x88, 0x15, 0xbc, 0xb0, 0x70, 0x0f, 0x75, 0x90, 0x35,
- 0xde, 0x09, 0x43, 0xe5, 0xa1, 0x11, 0x53, 0x60, 0x4f, 0x46, 0x1a, 0x58, 0xf1, 0x9f, 0x56, 0xef,
- 0x2e, 0xb8, 0x4a, 0xce, 0x4a, 0x86, 0x22, 0x59, 0x99, 0x4c, 0x81, 0xfd, 0x67, 0xf1, 0x19, 0xc4,
- 0xb3, 0x82, 0xd7, 0xd5, 0x6b, 0xc2, 0xe3, 0xbc, 0x1b, 0x84, 0x91, 0x09, 0x9f, 0x17, 0x85, 0x5c,
- 0xb4, 0x4d, 0x4f, 0x43, 0x0c, 0xae, 0x49, 0x98, 0xa4, 0x94, 0xf9, 0x63, 0x77, 0x16, 0x71, 0xc6,
- 0xc5, 0x74, 0xdc, 0xb9, 0xd2, 0x63, 0x64, 0x4c, 0xb4, 0x96, 0x44, 0x0b, 0x9a, 0x43, 0xb7, 0x74,
- 0xf6, 0xe3, 0x37, 0x2d, 0xc9, 0x93, 0xcd, 0x5a, 0x6e, 0x47, 0xd2, 0xed, 0x9b, 0x39, 0x06, 0xc7,
- 0xde, 0x49, 0xa8, 0x66, 0x0f, 0x54, 0xac, 0x57, 0xb6, 0xe5, 0x92, 0x81, 0xb1, 0xb0, 0x8c, 0xd5,
- 0xe5, 0x7b, 0x61, 0x1b, 0x2b, 0x63, 0xdd, 0x55, 0xe5, 0x6e, 0xa2, 0x60, 0xf5, 0x80, 0x15, 0x87,
- 0xd6, 0x78, 0x6c, 0x70, 0x69, 0x23, 0x6b, 0x34, 0x3f, 0x6c, 0x4a, 0x52, 0xe1, 0x59, 0xeb, 0x95,
- 0x2a, 0x75, 0x4f, 0x06, 0x15, 0x7f, 0xb6, 0x20, 0x81, 0xdf, 0x93, 0x7d, 0x37, 0x59, 0xd7, 0x9d,
- 0x6d, 0x1b, 0x00, 0x0b, 0x69, 0x92, 0x47, 0xe0, 0xde, 0xab, 0xaa, 0xa1, 0x54, 0x03, 0x50, 0xfa,
- 0x5c, 0xb3, 0xfb, 0xcf, 0xfb, 0xad, 0x5c, 0xfd, 0xd6, 0xfd, 0x73, 0x9b, 0x25, 0x77, 0xae, 0x5e,
- 0x75, 0x5a, 0xbd, 0xb4, 0x7c, 0xa9, 0xc4, 0xea, 0x22, 0xd9, 0xc3, 0x53, 0xd9, 0x3c, 0xb3, 0xc3,
- 0x45, 0x58, 0x02, 0x62, 0x3a, 0x79, 0x83, 0xbd, 0x91, 0x78, 0xa5, 0xd9, 0x0c, 0x08, 0x31, 0x55,
- 0x9c, 0x14, 0x89, 0x2f, 0xf4, 0x0d, 0x2c, 0x5c, 0x55, 0xe2, 0x82, 0xb9, 0x66, 0x22, 0xb3, 0xff,
- 0xfd, 0xf2, 0x5f, 0x71, 0xab, 0x47, 0x45, 0xc1, 0xf4, 0x84, 0x2d, 0x6d, 0xcd, 0xc2, 0xa9, 0x38,
- 0x29, 0xf5, 0x3c, 0xb2, 0xef, 0xa7, 0x44, 0x98, 0xb7, 0x84, 0xa0, 0xde, 0xda, 0xa9, 0x99, 0x25,
- 0x83, 0x11, 0x93, 0xcd, 0x2c, 0x5a, 0xa2, 0x9a, 0xff, 0xb0, 0x4a, 0x80, 0x3e, 0x2c, 0x52, 0xf3,
- 0x8f, 0xbd, 0xdd, 0xc5, 0x17, 0xea, 0x6b, 0xb4, 0x75, 0xa7, 0x22, 0xe9, 0xc1, 0xbd, 0x74, 0x80,
- 0x62, 0x6a, 0x55, 0x46, 0x4d, 0xf4, 0x47, 0x5a, 0x25, 0xc2, 0x67, 0x9b, 0xdc, 0xf8, 0x1b, 0xe7,
- 0xff, 0xd1, 0x44, 0xe6, 0xbe, 0x6c, 0xa4, 0x9d, 0xc3, 0x6e, 0x44, 0xfb, 0x54, 0xd5, 0x53, 0xec,
- 0xe4, 0x03, 0x9c, 0x22, 0xa0, 0xa1, 0xd1, 0x1a, 0x6e, 0xa3, 0x10, 0xf9, 0xd0, 0x14, 0xa6, 0x20,
- 0x8c, 0xe0, 0x35, 0x72, 0x92, 0x41, 0x43, 0x83, 0x93, 0x11, 0xec, 0x3d, 0x74, 0x43, 0x4a, 0x92,
- 0xe4, 0x91, 0xb7, 0xf2, 0xed, 0x9a, 0x6f, 0xd4, 0x23, 0x67, 0x07, 0xfb, 0x90, 0xb1, 0xb0, 0x23,
- 0x14, 0x7a, 0x50, 0x48, 0xdf, 0x89, 0x19, 0xa0, 0xdb, 0xf5, 0xff, 0x38, 0xfa, 0x97, 0x6b, 0x7b,
- 0xd3, 0x50, 0x77, 0xcf, 0xce, 0x4e, 0x6d, 0x79, 0x93, 0xc5, 0x49, 0xad, 0x17, 0x55, 0xa6, 0xd4,
- 0x82, 0x7d, 0x17, 0x2d, 0x0b, 0x76, 0x55, 0x90, 0x83, 0x56, 0x72, 0x76, 0xac, 0xe4, 0x24, 0x91,
- 0x4f, 0x85, 0xf7, 0xc7, 0x9d, 0x38, 0xd0, 0x92, 0x30, 0x91, 0x99, 0x25, 0x8a, 0x6c, 0xaa, 0x2d,
- 0xbb, 0x88, 0x30, 0x8c, 0xf2, 0xa6, 0x23, 0x60, 0x89, 0x44, 0x02, 0x1e, 0x18, 0xb4, 0xd9, 0xab,
- 0x4b, 0xa4, 0x57, 0xef, 0x49, 0x3c, 0x02, 0xe5, 0x7d, 0x38, 0x36, 0x49, 0x5b, 0xcd, 0x2d, 0x6f,
- 0x9d, 0x90, 0x63, 0xe0, 0x56, 0xa6, 0x9a, 0xf9, 0xf8, 0x65, 0xc1, 0x88, 0x8d, 0x43, 0x5b, 0xe0,
- 0xc2, 0x90, 0xaa, 0x22, 0xd2, 0x40, 0xe2, 0x94, 0x2d, 0x48, 0x75, 0xcb, 0x67, 0x84, 0xa5, 0xe1,
- 0xc3, 0x08, 0x30, 0xfa, 0xd7, 0xfd, 0x27, 0x9c, 0xb1, 0x03, 0x0f, 0x58, 0x15, 0x5a, 0x15, 0x4a,
- 0xa8, 0x48, 0x23, 0x74, 0xec, 0xc4, 0xe9, 0x83, 0xa6, 0xc3, 0x82, 0x7a, 0x0f, 0x2c, 0x17, 0x93,
- 0x14, 0x21, 0x03, 0xc2, 0xba, 0x4f, 0x47, 0xae, 0x53, 0xa7, 0x54, 0x53, 0xed, 0x79, 0xe0, 0x05,
- 0xa3, 0x27, 0xf8, 0xae, 0x99, 0xd5, 0x03, 0x01, 0x86, 0x92, 0xab, 0x03, 0xc2, 0x6a, 0xc3, 0xe8,
- 0x15, 0xc8, 0x40, 0x7b, 0x11, 0xc7, 0x89, 0xb5, 0x6d, 0x4d, 0x22, 0x61, 0x2d, 0x5a, 0x12, 0x5a,
- 0x48, 0x28, 0x0e, 0xeb, 0x5e, 0xde, 0x8b, 0x3f, 0x52, 0xb0, 0xeb, 0x8c, 0x0b, 0x83, 0x9e, 0x56,
- 0x6e, 0x66, 0xa4, 0xc7, 0xc1, 0x7c, 0x02, 0x85, 0x16, 0xe0, 0x64, 0x88, 0x04, 0x5a, 0xaa, 0xfb,
- 0xb3, 0xc1, 0xf7, 0x7d, 0x41, 0xc3, 0xf6, 0x00, 0x56, 0x61, 0xb8, 0xe7, 0xb5, 0x01, 0x05, 0x1d,
- 0x51, 0x99, 0x1d, 0xd9, 0x63, 0x24, 0x05, 0x4e, 0xfe, 0xe0, 0x26, 0xbb, 0xd6, 0xbb, 0x88, 0x33,
- 0x31, 0x20, 0x6d, 0x97, 0x69, 0x31, 0x5e, 0x03, 0xac, 0x13, 0x39, 0xa8, 0x5b, 0x18, 0x9b, 0x18,
- 0xbe, 0xf1, 0x54, 0x7d, 0xff, 0xa3, 0x61, 0xb3, 0x0c, 0x12, 0xf8, 0xde, 0xad, 0x3f, 0x50, 0xd1,
- 0xfc, 0x24, 0x94, 0x8a, 0x7e, 0xbd, 0xe5, 0xbe, 0x03, 0x74, 0xfb, 0xe5, 0xbb, 0x40, 0xcd, 0x09,
- 0xe2, 0x25, 0x30, 0xac, 0x2f, 0xc0, 0x73, 0x3a, 0x26, 0x5a, 0xbc, 0x3f, 0xc0, 0x90, 0xff, 0xc0,
- 0xe0, 0x14, 0xc5, 0x30, 0x1f, 0x21, 0x33, 0x77, 0xa6, 0xe5, 0xd3, 0x24, 0xca, 0xe4, 0x95, 0x01,
- 0x42, 0xa7, 0x7c, 0xe1, 0x8e, 0xd6, 0x6c, 0x00, 0xea, 0x5c, 0x83, 0x62, 0xb6, 0x19, 0xb6, 0xbf,
- 0x0a, 0xeb, 0x79, 0x15, 0x5a, 0x32, 0xa1, 0xa3, 0x76, 0xc2, 0x03, 0x28, 0xb7, 0x48, 0xc8, 0x25,
- 0xaa, 0xc5, 0x78, 0x93, 0x1f, 0x94, 0x6c, 0xdd, 0xca, 0x34, 0xf4, 0xee, 0xa4, 0xb1, 0x90, 0x66,
- 0xc9, 0x5f, 0xf0, 0x1c, 0x0e, 0x25, 0x72, 0x94, 0xa0, 0xa6, 0x66, 0x43, 0x01, 0xd4, 0x10, 0xe1,
- 0x07, 0x17, 0x9d, 0x51, 0xf0, 0xbd, 0xd8, 0x89, 0x33, 0xd5, 0xb3, 0x8c, 0xfd, 0x77, 0x8c, 0xc9,
- 0xa0, 0x8f, 0x7a, 0x07, 0x34, 0x3a, 0xfc, 0x86, 0x0f, 0x37, 0x03, 0x39, 0x2a, 0x5c, 0x0b, 0x69,
- 0x3c, 0xd6, 0xce, 0x88, 0x50, 0xe2, 0x20, 0x2e, 0x1e, 0xea, 0x66, 0x9d, 0xdf, 0x5a, 0xd2, 0x6a,
- 0xcb, 0x3d, 0xf9, 0xda, 0x58, 0x8e, 0xaf, 0x73, 0x3a, 0xd5, 0x6f, 0x7b, 0x9a, 0x44, 0x8b, 0xde,
- 0x92, 0xa4, 0x08, 0xf1, 0xae, 0xb1, 0x7c, 0xa9, 0x42, 0x2f, 0xc1, 0x83, 0x07, 0x9b, 0x0f, 0x65,
- 0xaf, 0x3e, 0x33, 0xbe, 0xf4, 0x21, 0x5d, 0xf8, 0x3c, 0x50, 0x1d, 0xe8, 0x9f, 0x43, 0xa1, 0x79,
- 0x11, 0x19, 0x8c, 0x48, 0xf7, 0xe2, 0x9d, 0x72, 0x73, 0xfc, 0x95, 0x12, 0x0f, 0x37, 0x5e, 0x7a,
- 0x71, 0xa0, 0xa0, 0x0e, 0x6a, 0x16, 0xfd, 0xbf, 0xa3, 0x63, 0x4a, 0x46, 0xa9, 0xe9, 0xb7, 0x8a,
- 0x00, 0xbd, 0x14, 0xe7, 0x39, 0x08, 0xe0, 0x24, 0xe5, 0x66, 0xd7, 0xa3, 0x95, 0xbf, 0x34, 0x08,
- 0x06, 0x57, 0x55, 0x9e, 0xd3, 0x21, 0x39, 0xe5, 0xe1, 0x0e, 0x6e, 0xa0, 0x83, 0x5e, 0xa7, 0x83,
- 0xf7, 0x38, 0x19, 0x15, 0xd3, 0xfe, 0x69, 0xb7, 0x8e, 0x52, 0x0b, 0x06, 0xf3, 0xf4, 0xa7, 0x21,
- 0x8a, 0x6c, 0x79, 0x4d, 0x56, 0x50, 0xed, 0xc0, 0xce, 0xda, 0xf0, 0xdf, 0xb7, 0x88, 0x53, 0x47,
- 0xda, 0x4b, 0x20, 0x2e, 0xf8, 0xc9, 0xb7, 0xf2, 0x38, 0x44, 0x7a, 0x52, 0x23, 0x80, 0x4f, 0x50,
- 0x83, 0x05, 0x63, 0xcd, 0xad, 0x0d, 0x1e, 0xa2, 0x22, 0xe4, 0xf3, 0x16, 0xfc, 0x6e, 0x85, 0x52,
- 0x46, 0x37, 0xd2, 0x52, 0xb3, 0x50, 0x4b, 0x27, 0x74, 0xe4, 0xb0, 0xac, 0x18, 0xdd, 0x4b, 0x30,
- 0x20, 0x0b, 0x20, 0x12, 0x2b, 0x45, 0xd7, 0xf8, 0xa8, 0xba, 0x65, 0x21, 0x81, 0x4e, 0x82, 0xc1,
- 0xa1, 0x6c, 0xad, 0x92, 0x2c, 0x5d, 0x10, 0xd6, 0x9d, 0xa3, 0x7d, 0x08, 0x7e, 0xd9, 0x14, 0xaa,
- 0x90, 0x5e, 0x8f, 0xd4, 0xcd, 0x51, 0xd9, 0xa6, 0x61, 0x58, 0x0c, 0x21, 0xd2, 0x5e, 0x17, 0x10,
- 0xe7, 0x2a, 0x1f, 0xa4, 0x63, 0x1d, 0x0f, 0xec, 0xc5, 0x76, 0x93, 0x36, 0x47, 0x31, 0x45, 0x3b,
- 0x87, 0x65, 0x9d, 0xee, 0x26, 0x4e, 0x42, 0x97, 0x74, 0x00, 0x9e, 0x26, 0x95, 0x64, 0x19, 0x2b,
- 0x3b, 0x14, 0x18, 0xeb, 0xd7, 0xfc, 0x20, 0x21, 0xcf, 0x1b, 0x25, 0xa7, 0x89, 0xfb, 0x7c, 0xeb,
- 0x91, 0xfd, 0xe7, 0x77, 0x6e, 0x4a, 0xa4, 0xb6, 0x4c, 0xe5, 0x9f, 0x3e, 0x46, 0x28, 0x41, 0x58,
- 0xab, 0x82, 0x12, 0x61, 0x75, 0x74, 0xb1, 0x6a, 0xbd, 0xeb, 0x3f, 0x56, 0x24, 0x83, 0xc9, 0x6c,
- 0x30, 0x1f, 0xd2, 0x78, 0x22, 0xb6, 0x16, 0xb6, 0x59, 0xaf, 0xee, 0xc3, 0x3a, 0x77, 0xfb, 0xe0,
- 0x40, 0x3d, 0x33, 0xcf, 0x39, 0x43, 0xa0, 0x6e, 0xb7, 0xa5, 0x85, 0xf7, 0xaa, 0xfa, 0x25, 0xea,
- 0x7c, 0x6c, 0xf7, 0xfd, 0x87, 0x11, 0xb1, 0x69, 0x1e, 0xa9, 0x92, 0x28, 0x73, 0x82, 0xf8, 0xa9,
- 0x26, 0x6f, 0x45, 0x31, 0x11, 0x49, 0x36, 0xb5, 0x35, 0x16, 0x40, 0x37, 0xb4, 0xe3, 0xf9, 0x8e,
- 0x8c, 0x32, 0x92, 0x2b, 0xef, 0x9c, 0xb0, 0xd1, 0x57, 0xea, 0xbe, 0xf0, 0xb1, 0x73, 0xb1, 0xad,
- 0xe6, 0x42, 0xb6, 0xed, 0xf2, 0x04, 0x07, 0xa2, 0x49, 0xf8, 0x73, 0x88, 0x2d, 0x99, 0x8c, 0x24,
- 0xb7, 0xd1, 0x10, 0xf8, 0xe4, 0xbf, 0xb6, 0x12, 0x07, 0xf9, 0xad, 0x2c, 0xb1, 0x82, 0xc5, 0xe6,
- 0x83, 0x22, 0xa6, 0xce, 0xbd, 0xb0, 0xb0, 0xf1, 0x79, 0x83, 0xc9, 0xaa, 0xa0, 0xc2, 0x69, 0x7f,
- 0x51, 0xfd, 0xc6, 0x17, 0xfe, 0x96, 0x9f, 0x1f, 0xce, 0x83, 0xfe, 0xd6, 0x68, 0x9e, 0x0c, 0xbb,
- 0x1c, 0x9f, 0x40, 0x97, 0x03, 0x88, 0x8c, 0x2c, 0xa7, 0x4a, 0xb6, 0xef, 0xb9, 0xe0, 0x59, 0xc6,
- 0x1e, 0x98, 0x31, 0x52, 0x22, 0x41, 0xf6, 0xb7, 0x5e, 0x5b, 0x2e, 0xa0, 0xbf, 0x3e, 0x99, 0xaa,
- 0x63, 0x97, 0xa7, 0x0a, 0xc5, 0x14, 0x33, 0x95, 0x01, 0xc1, 0x80, 0x75, 0xd3, 0xe8, 0x27, 0x3c,
- 0xf5, 0x7c, 0x00, 0x46, 0x14, 0x0c, 0xd8, 0x6d, 0x25, 0x20, 0x77, 0x0b, 0xaa, 0xb3, 0xa7, 0xe0,
- 0xe6, 0x88, 0x31, 0x7e, 0xcc, 0x1e, 0xee, 0xe4, 0xbe, 0x66, 0x2a, 0x8a, 0xa7, 0x68, 0x94, 0x4f,
- 0xa2, 0xb8, 0x3c, 0x3d, 0x75, 0x72, 0xf0, 0x8f, 0x94, 0xcf, 0x2c, 0x13, 0xbd, 0x6a, 0x53, 0x57,
- 0xac, 0x4f, 0x0b, 0x3d, 0x9c, 0x15, 0x32, 0x05, 0x7e, 0xfa, 0xf5, 0xb8, 0x53, 0xdb, 0x01, 0x8d,
- 0x35, 0x5a, 0x01, 0x98, 0xca, 0x47, 0x90, 0x51, 0xa8, 0x1a, 0x84, 0xcd, 0x86, 0x81, 0x8e, 0x53,
- 0x40, 0x4d, 0x76, 0xa8, 0xbd, 0x8b, 0x96, 0xd6, 0xb9, 0xc8, 0xd9, 0x71, 0x6f, 0x58, 0x2a, 0x70,
- 0xab, 0x11, 0x84, 0x70, 0x36, 0xc0, 0xc1, 0x5f, 0x2b, 0x2c, 0xa3, 0x5a, 0x32, 0x56, 0x1a, 0xb4,
- 0xdd, 0xaf, 0x4b, 0x6e, 0x4c, 0x4e, 0xa4, 0xdf, 0x2f, 0xdb, 0x0d, 0x01, 0xe0, 0xc7, 0x1c, 0x09,
- 0x78, 0x09, 0xaa, 0x51, 0xf0, 0x0f, 0x08, 0x6b, 0x61, 0x2a, 0x7b, 0x30, 0xa2, 0xf1, 0x26, 0xcc,
- 0xf0, 0x04, 0x38, 0xd1, 0xf5, 0x6c, 0x21, 0xf7, 0x8e, 0x6b, 0xc0, 0xb6, 0x9c, 0x8d, 0xb7, 0x7c,
- 0xff, 0x33, 0x28, 0x48, 0x06, 0x7b, 0x47, 0x05, 0xbb, 0xe2, 0x23, 0xb3, 0x00, 0x72, 0x43, 0xbe,
- 0xbe, 0xee, 0x8d, 0xb7, 0xa5, 0x26, 0x93, 0x61, 0x7a, 0x1f, 0x46, 0x1e, 0x13, 0x76, 0x35, 0x87,
- 0x75, 0x87, 0x7d, 0xe0, 0x71, 0xc1, 0x9b, 0xdc, 0x54, 0x56, 0x3f, 0xa1, 0x47, 0x63, 0xed, 0x08,
- 0x77, 0xe0, 0x6e, 0xbe, 0xe6, 0x83, 0xc0, 0xae, 0x96, 0x0e, 0xcf, 0x61, 0xb2, 0x6f, 0x8b, 0x04,
- 0x24, 0x9f, 0xa8, 0x0a, 0xf2, 0xb2, 0x77, 0x7b, 0x1c, 0xac, 0x97, 0x16, 0x4a, 0x28, 0xdf, 0x3e,
- 0xe9, 0xcb, 0x0d, 0x8a, 0x28, 0x86, 0xf0, 0x33, 0x17, 0x8e, 0x0b, 0xfa, 0x49, 0x4c, 0x84, 0x38,
- 0x3a, 0x05, 0xc2, 0xef, 0xba, 0xe0, 0xec, 0x83, 0xfd, 0x6f, 0x68, 0x60, 0xc8, 0xe6, 0x45, 0xca,
- 0x71, 0x82, 0x7b, 0xc2, 0xa6, 0x08, 0x2d, 0xa0, 0xc4, 0x20, 0x6c, 0x85, 0x74, 0x6f, 0x52, 0xa5,
- 0xcb, 0xaf, 0x01, 0x15, 0xab, 0x5d, 0x4f, 0x1f, 0x1b, 0xe5, 0xe9, 0x07, 0x9a, 0xb6, 0x41, 0xde,
- 0x68, 0xdc, 0x65, 0xaa, 0x7b, 0x93, 0xea, 0xba, 0x60, 0xc4, 0xb6, 0xef, 0x23, 0x6e, 0xb2, 0xa1,
- 0xce, 0xdc, 0xf5, 0xe8, 0xd4, 0x8c, 0x24, 0xdd, 0xda, 0xaa, 0x8c, 0x8c, 0x7b, 0xa9, 0x70, 0xeb,
- 0x8b, 0xb2, 0xe5, 0xc4, 0x66, 0x5f, 0xcf, 0x66, 0x39, 0x6d, 0xfd, 0x64, 0x59, 0x34, 0x5b, 0x6b,
- 0x56, 0xbe, 0x64, 0x89, 0x1e, 0x3c, 0x29, 0x55, 0xcf, 0x28, 0xce, 0x7f, 0xb6, 0xb8, 0xb7, 0x84,
- 0x82, 0x7e, 0xd4, 0xee, 0x67, 0x8f, 0x74, 0xf4, 0x0f, 0x30, 0x11, 0xc1, 0x21, 0xb5, 0x97, 0xcb,
- 0xb0, 0xa6, 0x4e, 0xb1, 0x39, 0x6b, 0xed, 0xb8, 0xb4, 0x1d, 0x9b, 0x88, 0xb4, 0x65, 0x9a, 0x5c,
- 0x55, 0x4e, 0x8d, 0xbd, 0x3e, 0x6a, 0xad, 0x79, 0xae, 0x56, 0x17, 0xfd, 0x6c, 0xdb, 0x95, 0x20,
- 0x90, 0xbc, 0xa0, 0x51, 0x8d, 0x82, 0x83, 0x70, 0x36, 0x94, 0x8f, 0x43, 0x5a, 0x9d, 0xc2, 0xa0,
- 0x08, 0x9a, 0xad, 0xb6, 0x0c, 0x8e, 0xa1, 0x7d, 0x69, 0xfb, 0x36, 0x36, 0xa6, 0x9c, 0x6f, 0xa1,
- 0x14, 0x37, 0xfe, 0xaa, 0xd7, 0xab, 0xd9, 0xeb, 0x8c, 0x2b, 0x86, 0xa8, 0x2f, 0x72, 0x32, 0x3c,
- 0x9a, 0x9b, 0x75, 0x19, 0x64, 0xe4, 0x21, 0xd9, 0xdc, 0xd8, 0x99, 0xf6, 0xdb, 0x1a, 0xe7, 0x7e,
- 0xdf, 0x5b, 0x38, 0x82, 0xe8, 0x6b, 0x3f, 0x3e, 0x56, 0x14, 0x5e, 0x85, 0xce, 0x20, 0xee, 0x05,
- 0x41, 0xa9, 0xb1, 0x09, 0xc0, 0xa9, 0xc2, 0x30, 0xa2, 0x54, 0xd5, 0x76, 0x14, 0xfb, 0x20, 0x8d,
- 0x66, 0xd6, 0x76, 0xa4, 0xa0, 0xe7, 0x92, 0x15, 0xd9, 0x25, 0x73, 0x00, 0x7b, 0x2f, 0xd6, 0x59,
- 0x5d, 0x3a, 0x94, 0xe0, 0x39, 0xe7, 0xe8, 0xbe, 0x2d, 0x3e, 0x30, 0x26, 0x18, 0xb5, 0x95, 0x7a,
- 0x92, 0x55, 0x31, 0x0b, 0x21, 0xc0, 0x92, 0xb3, 0x3e, 0x96, 0x3c, 0xe0, 0x53, 0xe3, 0x9d, 0xcc,
- 0x7b, 0xdc, 0x8e, 0xd1, 0x46, 0xf9, 0x7b, 0x1e, 0x3c, 0x00, 0x48, 0x97, 0x37, 0xef, 0x4d, 0x4a,
- 0x85, 0xdd, 0xab, 0x32, 0xec, 0xe2, 0x60, 0xd0, 0xee, 0x75, 0x02, 0xca, 0xf6, 0xb1, 0x0e, 0x1e,
- 0x9d, 0x6e, 0x20, 0x9f, 0xcd, 0x5e, 0x7f, 0xb1, 0x13, 0x3c, 0x07, 0xd4, 0x0a, 0x43, 0xff, 0x40,
- 0xd2, 0xc5, 0x9b, 0x5b, 0x5e, 0x89, 0x5e, 0x48, 0x28, 0x5b, 0xe0, 0x3a, 0x18, 0x6c, 0x83, 0xa7,
- 0x82, 0x7f, 0xb5, 0xd7, 0xbf, 0xcd, 0x09, 0x70, 0x36, 0xe5, 0xaf, 0x60, 0x0a, 0x98, 0x7c, 0x70,
- 0x7d, 0xac, 0x46, 0xb4, 0x30, 0x19, 0xf1, 0x3c, 0xc7, 0x55, 0xfd, 0x6f, 0x7a, 0x4b, 0xe5, 0x53,
- 0xcf, 0x06, 0x83, 0xca, 0x76, 0x30, 0x86, 0x27, 0x66, 0xf8, 0x3f, 0xea, 0x0e, 0x1d, 0xce, 0x01,
- 0xb3, 0x04, 0x62, 0xb3, 0xb3, 0x3f, 0xfe, 0x5f, 0x8a, 0x03, 0xc9, 0xfd, 0xb9, 0x8f, 0xc4, 0xa6,
- 0x60, 0x6e, 0xd9, 0x64, 0xe1, 0x51, 0x46, 0xb5, 0x09, 0xa3, 0x6a, 0x5c, 0x9e, 0xc2, 0xa4, 0xcc,
- 0xe6, 0xe1, 0x5f, 0xb4, 0x25, 0x1c, 0x19, 0x10, 0x25, 0xb7, 0x57, 0x6a, 0xbd, 0xd1, 0x6e, 0x32,
- 0xc7, 0xe4, 0xb1, 0x38, 0x93, 0x8c, 0x25, 0xfc, 0x13, 0x69, 0x44, 0xaf, 0x21, 0x0e, 0x66, 0xcc,
- 0x84, 0x62, 0xe3, 0x40, 0xd1, 0x6e, 0x7e, 0xc5, 0xd7, 0xcf, 0xdb, 0x37, 0x28, 0x74, 0xdb, 0x95,
- 0x3f, 0x72, 0xbd, 0x69, 0xe4, 0x48, 0xe4, 0xb7, 0xc5, 0xcc, 0xf5, 0x0a, 0x7a, 0xb5, 0x3f, 0x9f,
- 0x56, 0x4b, 0x6a, 0x13, 0xc6, 0x49, 0x54, 0x4a, 0x29, 0x85, 0xd4, 0x6f, 0x87, 0xa0, 0x8b, 0x48,
- 0x36, 0x28, 0xad, 0x9e, 0xa6, 0x54, 0x25, 0x54, 0x52, 0x22, 0xeb, 0x56, 0x26, 0x66, 0x2d, 0x70,
- 0x99, 0xa6, 0xfa, 0x14, 0x6f, 0x38, 0xc5, 0xe3, 0x87, 0xaf, 0x7d, 0x8d, 0x41, 0x63, 0x4b, 0x37,
- 0xe1, 0x18, 0xe9, 0xfa, 0x5f, 0x35, 0xdc, 0x14, 0x1f, 0x47, 0x4d, 0x23, 0x7c, 0x72, 0x29, 0xa3,
- 0x05, 0xbd, 0xbf, 0xd4, 0x5e, 0x12, 0x5e, 0x65, 0x63, 0x5f, 0xf9, 0xd9, 0xe3, 0x96, 0x0c, 0x7d,
- 0x56, 0xd1, 0x4b, 0xfc, 0xd2, 0x14, 0xec, 0x46, 0xd0, 0x1a, 0xbb, 0x76, 0xa9, 0x6f, 0xfe, 0xe7,
- 0x9d, 0xe9, 0x3f, 0x51, 0x5c, 0xaf, 0x51, 0x49, 0x2e, 0x1d, 0x2b, 0xbb, 0x63, 0xe7, 0x2d, 0xf4,
- 0x40, 0x92, 0x7b, 0xdf, 0x92, 0x78, 0xbd, 0xb3, 0x67, 0x73, 0x8e, 0xa1, 0xb8, 0x77, 0x95, 0x43,
- 0xb2, 0x2b, 0xa9, 0x64, 0xa3, 0xf0, 0xf6, 0xe9, 0xd9, 0x52, 0xef, 0x7a, 0xc5, 0x58, 0x07, 0xf5,
- 0x80, 0xfb, 0xd4, 0xc1, 0xe3, 0xad, 0xf7, 0x9c, 0xbd, 0x3b, 0xb9, 0xa0, 0xbd, 0xa9, 0xad, 0x6d,
- 0xac, 0x58, 0xe8, 0xec, 0x42, 0xee, 0xc0, 0x81, 0x03, 0x62, 0x2c, 0x20, 0xd2, 0x84, 0xff, 0x80,
- 0xbc, 0x02, 0x5f, 0x84, 0x7e, 0x76, 0x2f, 0xe6, 0x23, 0x4c, 0x26, 0x24, 0x11, 0xd8, 0x3b, 0xfb,
- 0x4d, 0xc4, 0x9a, 0x1d, 0x7f, 0x08, 0x80, 0xa4, 0xc2, 0x0e, 0x98, 0xd9, 0x09, 0x86, 0x74, 0xa2,
- 0xc5, 0x9a, 0xac, 0xe8, 0x5a, 0xe0, 0x82, 0xeb, 0x72, 0xec, 0xe6, 0x20, 0xc3, 0x79, 0xd6, 0xef,
- 0x70, 0x64, 0x47, 0x4f, 0xae, 0xbc, 0x1e, 0x88, 0x28, 0x0a, 0xdb, 0xcc, 0x99, 0xf6, 0x03, 0xe3,
- 0x61, 0x92, 0xbb, 0x8a, 0xff, 0x23, 0x3d, 0xef, 0x19, 0x4a, 0xa8, 0xe6, 0x8c, 0x27, 0x2e, 0x60,
- 0xe6, 0xdd, 0xc7, 0x08, 0x71, 0x61, 0xf7, 0x7e, 0x5e, 0x2c, 0xea, 0x00, 0x96, 0x61, 0x8e, 0xac,
- 0x14, 0xad, 0xec, 0x73, 0xe2, 0xba, 0xbf, 0xf0, 0xc5, 0x68, 0x14, 0x5b, 0x75, 0x4a, 0xba, 0x8a,
- 0xd6, 0x8b, 0xe2, 0xe4, 0x45, 0x9e, 0xcf, 0xef, 0x34, 0xa3, 0x55, 0xe3, 0x3d, 0x4b, 0x19, 0xd7,
- 0x8d, 0x7a, 0x9f, 0x51, 0xe4, 0xf6, 0x16, 0xf4, 0xaa, 0x7f, 0x65, 0x17, 0x32, 0x05, 0x05, 0x82,
- 0x73, 0x06, 0xc7, 0x87, 0x3d, 0xc4, 0x07, 0x54, 0xa5, 0x34, 0x0e, 0xd0, 0x3c, 0xbc, 0x92, 0x79,
- 0x4f, 0x50, 0xa4, 0xe0, 0xa5, 0xaf, 0xda, 0xfc, 0xb9, 0x1b, 0x12, 0x38, 0x0e, 0x9a, 0x6c, 0x4e,
- 0x6a, 0x3a, 0x67, 0x60, 0x3f, 0x54, 0x9a, 0x9a, 0xfe, 0x7e, 0xd0, 0x51, 0x71, 0x99, 0xa6, 0xd9,
- 0xe6, 0x0b, 0x4a, 0x1a, 0x03, 0xce, 0xcb, 0xf6, 0x48, 0x93, 0xd1, 0x22, 0x06, 0x53, 0x82, 0x47,
- 0x16, 0x6c, 0x67, 0xb1, 0xf4, 0x59, 0x15, 0x7e, 0xcc, 0x2f, 0x50, 0xbe, 0x0a, 0x46, 0x6b, 0x98,
- 0xd0, 0x2c, 0xa6, 0x96, 0x8c, 0x90, 0x69, 0xab, 0x03, 0x4a, 0x2a, 0xab, 0xea, 0x2c, 0x32, 0xfa,
- 0x53, 0x39, 0x82, 0x67, 0x72, 0xf4, 0x9a, 0xfc, 0x83, 0x07, 0xdd, 0xb6, 0xe3, 0xcb, 0x69, 0x27,
- 0x16, 0x54, 0xf4, 0x4f, 0x9f, 0x0f, 0x00, 0x9b, 0xd4, 0x50, 0xa3, 0xf6, 0x4d, 0x4f, 0x0f, 0x46,
- 0x29, 0x7c, 0x3e, 0x46, 0x8a, 0x86, 0x12, 0xab, 0xdc, 0x65, 0x4b, 0xa4, 0x2c, 0x79, 0x14, 0x63,
- 0x87, 0x94, 0x61, 0x15, 0x4e, 0x5d, 0xab, 0xc3, 0x74, 0x83, 0xf6, 0x1f, 0xaa, 0x95, 0x43, 0x55,
- 0xc2, 0x01, 0x86, 0x2f, 0x2a, 0xfd, 0x4a, 0x97, 0x15, 0x7b, 0x26, 0xb3, 0x78, 0xf3, 0x89, 0xd2,
- 0x12, 0xe5, 0x78, 0xa4, 0x56, 0x36, 0x1d, 0x3f, 0xce, 0x77, 0x66, 0xdf, 0xeb, 0x82, 0xb5, 0xf9,
- 0x1c, 0x1c, 0xec, 0x29, 0x85, 0xc3, 0xc0, 0xc8, 0xe3, 0xbf, 0x30, 0x84, 0x0a, 0x70, 0x74, 0x1b,
- 0xb6, 0x77, 0xdb, 0x8a, 0x2c, 0xbe, 0x42, 0x13, 0xb1, 0x02, 0x4f, 0xff, 0xe9, 0x92, 0xa3, 0xb3,
- 0x6c, 0xd3, 0x3f, 0xc0, 0xd0, 0x32, 0x57, 0x94, 0xb8, 0x7a, 0x8f, 0xa2, 0xef, 0xfc, 0x31, 0xe7,
- 0x50, 0x09, 0x49, 0xe1, 0x4d, 0xd0, 0x09, 0x1e, 0x52, 0xb4, 0x8b, 0x01, 0xf2, 0xf8, 0x38, 0xb7,
- 0xa9, 0xf3, 0xd9, 0xbe, 0x4a, 0x8e, 0x66, 0x2d, 0x2e, 0x3a, 0x7f, 0x36, 0x45, 0xef, 0xfa, 0x90,
- 0x02, 0xb0, 0xfa, 0x19, 0x04, 0xf2, 0x41, 0x74, 0xcf, 0x6c, 0x5b, 0x6a, 0x40, 0x33, 0x30, 0xb9,
- 0x0f, 0x3d, 0x62, 0xe9, 0x26, 0x69, 0xf1, 0x3e, 0x3c, 0x29, 0x84, 0xd7, 0xb1, 0xb1, 0x53, 0x0f,
- 0x99, 0x80, 0xfe, 0x77, 0x6d, 0xd1, 0xdd, 0xe9, 0x37, 0xb9, 0x54, 0x45, 0xe6, 0x44, 0x9c, 0x9f,
- 0x68, 0x5b, 0x45, 0x47, 0xdf, 0x5d, 0xa2, 0xe9, 0x67, 0x1c, 0x37, 0x10, 0xcb, 0xb7, 0x1a, 0xcc,
- 0x58, 0x0f, 0xe8, 0x92, 0x01, 0x43, 0x23, 0xc6, 0xce, 0x7c, 0xeb, 0x57, 0xb1, 0x12, 0xaa, 0xef,
- 0x82, 0x21, 0x9a, 0x28, 0x44, 0x1c, 0xf0, 0x75, 0xf6, 0xc0, 0x68, 0x69, 0x71, 0x2f, 0xb1, 0x17,
- 0x57, 0xee, 0x50, 0x32, 0x64, 0x73, 0x4a, 0xae, 0x91, 0xae, 0xb6, 0xa7, 0xc2, 0xcb, 0x33, 0xb3,
- 0x8b, 0x82, 0xea, 0x42, 0xdb, 0x9b, 0xbd, 0xd0, 0xc8, 0x27, 0xfc, 0xb9, 0x32, 0xc9, 0xe0, 0x06,
- 0x5d, 0xd3, 0xd1, 0x02, 0x5b, 0x7b, 0x29, 0x96, 0x19, 0x52, 0x0f, 0xd9, 0x4f, 0x6f, 0x0a, 0x61,
- 0xc6, 0x95, 0xe4, 0x85, 0x33, 0x42, 0xea, 0xa4, 0xba, 0x0e, 0x96, 0xc9, 0x1f, 0x49, 0xaf, 0x53,
- 0x6e, 0xe4, 0x2b, 0x95, 0x37, 0x11, 0xa3, 0x88, 0xb2, 0x98, 0xa5, 0x1f, 0xc0, 0xe5, 0xa4, 0x95,
- 0xa3, 0x0b, 0x80, 0x4c, 0x9d, 0x8a, 0x1e, 0x9f, 0x6e, 0x23, 0x61, 0x5d, 0x3a, 0x2d, 0x64, 0xe3,
- 0x76, 0x50, 0xf1, 0xe0, 0x4f, 0x54, 0x22, 0xb9, 0x1f, 0x9a, 0x80, 0xfc, 0xdf, 0xf4, 0x69, 0xb3,
- 0xa2, 0x11, 0xb1, 0x9e, 0x55, 0xd1, 0x3d, 0x0a, 0x4b, 0x98, 0x3e, 0x8e, 0x7e, 0x50, 0x48, 0x62,
- 0xf6, 0xcd, 0x14, 0x24, 0xf0, 0xe0, 0x36, 0x69, 0x95, 0xae, 0x34, 0x58, 0xeb, 0xd7, 0xaa, 0x93,
- 0xdd, 0xfd, 0x92, 0x03, 0xdb, 0xaf, 0xc4, 0x7f, 0xdd, 0x35, 0xe6, 0x13, 0xaa, 0x51, 0xb0, 0x05,
- 0xb1, 0xf8, 0x46, 0xf7, 0x66, 0x5c, 0xeb, 0x97, 0x7c, 0xb3, 0x33, 0xc0, 0x26, 0x58, 0x36, 0x4f,
- 0x93, 0x2c, 0xe1, 0x49, 0x02, 0xca, 0xa3, 0x97, 0x2e, 0x03, 0x8f, 0x61, 0xaa, 0x7d, 0xf3, 0xa1,
- 0xbc, 0xa3, 0xa0, 0x06, 0x18, 0x38, 0x75, 0x75, 0x6a, 0x96, 0xab, 0x39, 0x23, 0xad, 0x2b, 0x9e,
- 0xcd, 0x42, 0x74, 0xf8, 0xe6, 0x01, 0xfc, 0xf1, 0x51, 0x06, 0x23, 0xef, 0x8c, 0xab, 0xba, 0x67,
- 0x8c, 0xf2, 0x88, 0x29, 0x86, 0x3a, 0x5c, 0xc3, 0x0e, 0xcf, 0xf6, 0x56, 0xb9, 0xc3, 0xb2, 0xc5,
- 0xfb, 0x1b, 0x58, 0xfe, 0xaf, 0x8b, 0x67, 0x98, 0x77, 0x89, 0xaf, 0xda, 0xff, 0x64, 0x46, 0xaf,
- 0x6a, 0xbe, 0x52, 0x62, 0xc4, 0x98, 0x8e, 0x52, 0x2e, 0x38, 0xcc, 0x2e, 0x63, 0x82, 0x20, 0x93,
- 0x54, 0xb0, 0x03, 0x70, 0x46, 0xe5, 0x66, 0x7f, 0xf0, 0xf7, 0x0e, 0xe3, 0xf0, 0x37, 0x72, 0xfe,
- 0xfe, 0x18, 0x51, 0x93, 0xc4, 0x39, 0xbf, 0xa1, 0xaf, 0x13, 0xcf, 0xff, 0x84, 0xb4, 0x2c, 0x52,
- 0xaf, 0xc6, 0x53, 0x29, 0xe3, 0xd8, 0xe9, 0x64, 0x4e, 0xf5, 0x58, 0x90, 0xcd, 0xa9, 0x4f, 0x75,
- 0x30, 0x6d, 0xf2, 0x2a, 0xe4, 0xbc, 0x53, 0x13, 0xfd, 0xf4, 0xdb, 0xaa, 0x09, 0xe5, 0xcb, 0x7a,
- 0x97, 0xd0, 0x19, 0xcc, 0xe4, 0x8e, 0xc0, 0x28, 0xea, 0xef, 0xbd, 0xef, 0xc1, 0x4b, 0xd0, 0xd0,
- 0x95, 0xb7, 0x2a, 0x0f, 0x2c, 0x30, 0xe7, 0xac, 0x96, 0x22, 0x89, 0x7c, 0xfe, 0xa6, 0xf6, 0xd4,
- 0x46, 0xd2, 0xc3, 0x84, 0x68, 0x4e, 0x66, 0xfc, 0xba, 0x0a, 0x68, 0x43, 0xbc, 0xd7, 0xef, 0xcc,
- 0x3e, 0xc6, 0xb8, 0xa7, 0x77, 0x33, 0x0f, 0x91, 0x0d, 0xd0, 0xe3, 0xe9, 0xcb, 0xd2, 0x17, 0x61,
- 0xd7, 0x03, 0xee, 0xce, 0xce, 0xa4, 0xd8, 0x21, 0x14, 0xab, 0x0b, 0x8f, 0x8e, 0x89, 0x68, 0x23,
- 0x0d, 0x39, 0x5c, 0x95, 0x6b, 0xaf, 0xa8, 0x3c, 0x11, 0xfe, 0x66, 0xeb, 0xa4, 0xfd, 0xeb, 0x2b,
- 0x9c, 0xac, 0xa9, 0xc5, 0x29, 0x5b, 0x21, 0xd8, 0x50, 0x0c, 0x84, 0xc3, 0x3b, 0x0c, 0xbb, 0xbc,
- 0xca, 0x08, 0x79, 0xf6, 0x2b, 0xc0, 0x2d, 0xa0, 0x71, 0x8a, 0xed, 0x55, 0x4c, 0xd7, 0xb1, 0x3f,
- 0x29, 0xb1, 0xa7, 0x5b, 0xeb, 0xf4, 0x7b, 0xf7, 0xb9, 0x64, 0x8c, 0x8c, 0x04, 0x77, 0x78, 0x2c,
- 0xee, 0x99, 0x81, 0x95, 0xee, 0x55, 0x34, 0x0e, 0xc0, 0x7a, 0x67, 0xb1, 0x83, 0x46, 0x31, 0x58,
- 0xf6, 0x12, 0x8e, 0x6c, 0x24, 0x2a, 0xc1, 0xfc, 0xe7, 0x23, 0x0b, 0x21, 0x4a, 0x2a, 0xde, 0xf5,
- 0xa4, 0xe9, 0x78, 0xde, 0x10, 0xef, 0x74, 0x7a, 0xa9, 0x1f, 0x49, 0xe5, 0x3f, 0x6d, 0xb5, 0xa5,
- 0x5d, 0xaa, 0x11, 0x4f, 0x7d, 0x1e, 0x0e, 0xe1, 0xc3, 0x70, 0xb5, 0xb5, 0x9a, 0x62, 0x99, 0x91,
- 0xb0, 0x9e, 0x22, 0x4a, 0x17, 0x67, 0xdf, 0xad, 0x1f, 0xa7, 0x18, 0xeb, 0x3c, 0x99, 0xef, 0x1c,
- 0xbe, 0xed, 0xb2, 0x93, 0xd5, 0x93, 0xdf, 0xae, 0x61, 0x16, 0x6f, 0x42, 0x5b, 0x87, 0xb2, 0x33,
- 0x08, 0x30, 0xcf, 0x5a, 0xc1, 0xc5, 0x86, 0x4f, 0xe8, 0x81, 0x31, 0xf4, 0x50, 0xa8, 0xe7, 0x30,
- 0x24, 0x42, 0xf2, 0x4e, 0xa5, 0xa1, 0x03, 0x46, 0xb9, 0xd9, 0x50, 0xb9, 0xfa, 0xfb, 0xd4, 0x87,
- 0xd0, 0xcb, 0x22, 0xdc, 0xcc, 0x5b, 0xad, 0xa7, 0x50, 0xaa, 0xb1, 0xed, 0x8b, 0xbf, 0x8a, 0xda,
- 0x4b, 0x6a, 0xac, 0x34, 0xc4, 0xb5, 0xd1, 0x92, 0x17, 0xad, 0x4f, 0x2c, 0x43, 0x57, 0x2e, 0xf3,
- 0x44, 0x52, 0x10, 0x78, 0x50, 0x31, 0x4b, 0x4e, 0x0f, 0x21, 0x95, 0x84, 0x65, 0x63, 0x8d, 0x05,
- 0x68, 0x43, 0xe6, 0xf9, 0x01, 0xa6, 0xdb, 0xf1, 0xbe, 0xc4, 0x45, 0x66, 0x24, 0x15, 0xd3, 0x96,
- 0xf6, 0xa7, 0x40, 0xe9, 0x36, 0xa7, 0x2a, 0x18, 0x44, 0x1c, 0x27, 0x06, 0x6f, 0xf0, 0x6f, 0xbb,
- 0x2f, 0xf5, 0x47, 0x9f, 0xf9, 0xa4, 0x11, 0x22, 0xee, 0x14, 0x8d, 0xde, 0xe7, 0x4c, 0x9d, 0xad,
- 0x05, 0x5d, 0xf7, 0xf1, 0x58, 0xf8, 0x49, 0xac, 0x7a, 0xa1, 0x7b, 0x79, 0xfd, 0x0a, 0xbd, 0xf8,
- 0x86, 0x61, 0x14, 0x09, 0x4c, 0x14, 0x25, 0x57, 0x87, 0x4c, 0x85, 0x4b, 0x4e, 0x89, 0x52, 0xf9,
- 0x82, 0xfe, 0x70, 0x3f, 0x21, 0x73, 0x44, 0xf5, 0x5a, 0x77, 0xf6, 0xda, 0x57, 0xe0, 0xe3, 0xed,
- 0xb0, 0x3f, 0xb0, 0x34, 0x12, 0xdf, 0x24, 0x91, 0x2e, 0xe3, 0x2f, 0x75, 0xe7, 0x88, 0xfa, 0xb5,
- 0xd1, 0x67, 0xc4, 0x75, 0xf8, 0xa8, 0x67, 0x70, 0x91, 0x3b, 0x4c, 0xcb, 0x1b, 0x99, 0x90, 0x99,
- 0x0b, 0x45, 0x1c, 0xef, 0xeb, 0x90, 0x40, 0xb5, 0xc2, 0x63, 0xc6, 0x35, 0x8c, 0xdf, 0xd6, 0xfb,
- 0x3d, 0x12, 0x23, 0x39, 0x6a, 0x47, 0x6a, 0x1d, 0xf7, 0x5b, 0x84, 0x0b, 0x1d, 0x45, 0x53, 0xa3,
- 0x46, 0x33, 0x93, 0x73, 0x02, 0xb3, 0xef, 0xc3, 0x78, 0xfe, 0x28, 0xcc, 0x12, 0x60, 0x64, 0xb6,
- 0xf8, 0x57, 0xf3, 0x8a, 0xc3, 0x3b, 0xdc, 0xf6, 0xb8, 0x4b, 0x72, 0x78, 0x68, 0xcc, 0x72, 0xf6,
- 0xd9, 0x12, 0x9f, 0xe5, 0xdc, 0xb0, 0x9a, 0x5d, 0xb3, 0x2e, 0x47, 0x34, 0xdb, 0x86, 0x14, 0x64,
- 0x7a, 0x05, 0x78, 0xde, 0xb2, 0xd9, 0x15, 0xa7, 0xa2, 0x80, 0x83, 0x06, 0x40, 0x0f, 0x80, 0xef,
- 0xe9, 0xb8, 0xc0, 0x3e, 0x28, 0x1f, 0x87, 0x9a, 0x9a, 0xb1, 0x50, 0xc6, 0x08, 0x83, 0x59, 0xca,
- 0xe7, 0x1f, 0x90, 0xeb, 0x11, 0x4d, 0x10, 0x5e, 0x20, 0x80, 0xa1, 0xdf, 0xdd, 0x30, 0x80, 0xb1,
- 0xa2, 0x16, 0xcc, 0x2b, 0x7c, 0x13, 0x44, 0xbc, 0x36, 0xf6, 0x28, 0x31, 0xb8, 0xa1, 0xaf, 0x4c,
- 0xb7, 0x4d, 0x2a, 0xdc, 0xb5, 0x6e, 0x4c, 0x81, 0xe9, 0xe4, 0x83, 0xdb, 0xbb, 0x1c, 0x65, 0x8f,
- 0x8d, 0x4e, 0xfb, 0x02, 0xab, 0x81, 0x08, 0x56, 0x9f, 0x86, 0x0c, 0x16, 0xb9, 0xd1, 0xf6, 0x2c,
- 0xbe, 0xbb, 0xa0, 0x3e, 0x9a, 0x73, 0x19, 0xf7, 0xfc, 0xfc, 0xfd, 0x7e, 0xd3, 0x13, 0xad, 0x78,
- 0xdb, 0x3c, 0xac, 0xb2, 0xfb, 0xe9, 0xc8, 0xa5, 0xfc, 0x67, 0xd1, 0xa4, 0x3d, 0x67, 0x00, 0x52,
- 0x40, 0x58, 0xa5, 0x82, 0xe6, 0x7b, 0x57, 0x10, 0x57, 0x71, 0x06, 0x71, 0x88, 0xdd, 0xd0, 0xf5,
- 0x9f, 0x20, 0x2a, 0x7c, 0x73, 0xdf, 0x68, 0xda, 0xe5, 0x97, 0xe3, 0x35, 0x3b, 0xb8, 0x35, 0xed,
- 0x0b, 0xa4, 0x3a, 0x44, 0x0c, 0x18, 0x7d, 0x94, 0x98, 0x80, 0xdf, 0x41, 0xac, 0xd2, 0xc3, 0xd6,
- 0xa1, 0xfa, 0xce, 0x82, 0x95, 0x42, 0x59, 0x33, 0x3d, 0x81, 0x9f, 0xe9, 0x3c, 0xfa, 0xfe, 0x05,
- 0x61, 0x6f, 0xde, 0xa1, 0x0f, 0x86, 0x1a, 0xcb, 0x13, 0x3d, 0x94, 0x92, 0x27, 0x44, 0xa6, 0x55,
- 0xb3, 0x0e, 0x01, 0x26, 0x7e, 0x62, 0x82, 0xc2, 0x88, 0x05, 0x09, 0xac, 0xda, 0xa1, 0x09, 0x60,
- 0x25, 0xda, 0x86, 0x96, 0x54, 0xfa, 0xf8, 0x38, 0x05, 0x67, 0x1c, 0x52, 0x6a, 0x03, 0x1a, 0x54,
- 0x21, 0x50, 0x3f, 0x84, 0xbb, 0x2c, 0x3a, 0x40, 0x2b, 0x9b, 0xeb, 0x82, 0x25, 0x79, 0x4e, 0x37,
- 0x19, 0x07, 0x6b, 0x71, 0x8b, 0xaa, 0x6f, 0x32, 0x29, 0x31, 0x52, 0xc6, 0x7b, 0xec, 0xfe, 0xbe,
- 0xf8, 0x6e, 0x9b, 0x73, 0x13, 0xd7, 0xa9, 0xb8, 0x9f, 0x40, 0x38, 0x3e, 0x68, 0x7a, 0xd8, 0x82,
- 0xe2, 0xe0, 0x8a, 0xac, 0x69, 0x85, 0x90, 0x2c, 0xbd, 0x7a, 0x8e, 0xa1, 0xef, 0x47, 0x09, 0x8d,
- 0xb9, 0x1a, 0x90, 0xa5, 0x22, 0xc1, 0xa8, 0xe5, 0x92, 0x28, 0xd7, 0xf5, 0x8a, 0x95, 0x83, 0x0c,
- 0x97, 0x16, 0x1d, 0xc8, 0x1b, 0x40, 0x80, 0x2b, 0x7f, 0x4b, 0x76, 0xe7, 0x6c, 0x69, 0x99, 0xd3,
- 0x75, 0xee, 0xb0, 0x00, 0xb6, 0xa8, 0x87, 0x85, 0xf5, 0x63, 0x4e, 0xc4, 0xfc, 0x4c, 0x2e, 0x3c,
- 0x23, 0x8f, 0xa6, 0x79, 0x97, 0x07, 0xe4, 0x80, 0xf8, 0xde, 0xf5, 0x46, 0x60, 0x62, 0xd7, 0x5d,
- 0x23, 0x7b, 0xe4, 0xbd, 0x06, 0x66, 0x2a, 0x16, 0x31, 0x55, 0x04, 0xde, 0x5c, 0x14, 0x8b, 0x25,
- 0x0a, 0x0e, 0x14, 0xe6, 0xf3, 0xb8, 0x88, 0xf9, 0xc0, 0x5e, 0xeb, 0xef, 0x41, 0x69, 0x2a, 0x1c,
- 0x2e, 0x05, 0x1c, 0x88, 0x2d, 0xd5, 0x38, 0x48, 0xe6, 0x0c, 0x17, 0x58, 0xbb, 0xc9, 0xd8, 0xd7,
- 0xa3, 0xbc, 0x63, 0x5b, 0x9c, 0xa9, 0xf1, 0x99, 0x1e, 0xcb, 0x56, 0x9c, 0xfb, 0x17, 0xe0, 0x64,
- 0x78, 0x3d, 0xd5, 0x0b, 0x92, 0x29, 0x8a, 0xd7, 0x73, 0xbd, 0x16, 0xc6, 0x7d, 0x41, 0x52, 0xb2,
- 0x46, 0x04, 0xc7, 0xbc, 0x59, 0xe2, 0x33, 0xb8, 0x15, 0x06, 0x81, 0x85, 0x66, 0x38, 0x56, 0x33,
- 0xf6, 0x50, 0xc5, 0x11, 0xd6, 0xec, 0x4a, 0x45, 0x4f, 0x05, 0x21, 0x9a, 0x8b, 0xc2, 0xb9, 0x5f,
- 0x54, 0x7e, 0x2a, 0x44, 0xa6, 0xd4, 0x5a, 0xd9, 0x93, 0x20, 0x87, 0xbc, 0xc9, 0x80, 0x3a, 0x46,
- 0x99, 0x54, 0x57, 0x7a, 0x8a, 0xb5, 0x11, 0xbf, 0x9c, 0xa7, 0xc3, 0xac, 0xea, 0xb1, 0x54, 0xd3,
- 0xe7, 0x2e, 0x31, 0xc0, 0x0e, 0x48, 0x8e, 0xb9, 0x31, 0xd3, 0x2a, 0xf9, 0xdf, 0xa7, 0xcd, 0x99,
- 0x48, 0xc1, 0x29, 0x8d, 0xe1, 0x49, 0x58, 0xd7, 0xd4, 0x1d, 0x61, 0xf6, 0xc0, 0xca, 0x47, 0x6f,
- 0x6a, 0x55, 0x49, 0xf3, 0xe0, 0xe0, 0x4c, 0xf1, 0xe5, 0x32, 0xc0, 0x4c, 0xe2, 0xac, 0x1f, 0xea,
- 0x4f, 0xf3, 0x8d, 0xe1, 0x4d, 0xf6, 0xf0, 0xf4, 0x6c, 0x34, 0x17, 0x17, 0xdd, 0x0d, 0xa2, 0x02,
- 0xad, 0xcf, 0xc7, 0x15, 0x54, 0xdc, 0xeb, 0x04, 0x26, 0xf4, 0x01, 0xa9, 0x33, 0x8f, 0x8a, 0xe1,
- 0x66, 0xfe, 0xb6, 0x2b, 0x95, 0xcd, 0x1f, 0x62, 0x81, 0x54, 0x70, 0x68, 0x88, 0x53, 0x89, 0x69,
- 0x4a, 0x31, 0xcc, 0x48, 0x8d, 0xaf, 0x83, 0x7f, 0xf9, 0xa8, 0x7f, 0x63, 0x9f, 0x0c, 0x24, 0xc7,
- 0x9f, 0x21, 0x8a, 0x0d, 0xb4, 0xcd, 0xfe, 0xd4, 0x8a, 0xc5, 0x3d, 0xf5, 0x17, 0x73, 0x44, 0x40,
- 0xee, 0x08, 0x94, 0x0d, 0x56, 0x78, 0xae, 0x00, 0x61, 0xa4, 0x94, 0xc8, 0xd1, 0x4c, 0xbd, 0xdb,
- 0x27, 0xf8, 0x05, 0x84, 0x27, 0xaf, 0x88, 0xbd, 0x41, 0x97, 0x82, 0x4e, 0x07, 0x11, 0xc0, 0xf2,
- 0xff, 0xa4, 0x51, 0x7f, 0x86, 0x8e, 0xe8, 0x72, 0x93, 0xb2, 0x24, 0xbc, 0x60, 0xd0, 0xbf, 0xad,
- 0x6c, 0xaf, 0xa7, 0x8c, 0x04, 0x50, 0x1d, 0x83, 0xac, 0x7c, 0x25, 0xf6, 0x07, 0x70, 0xd8, 0xe2,
- 0x8e, 0x13, 0x5d, 0x22, 0x4e, 0x3e, 0xec, 0xf7, 0xf8, 0x93, 0x40, 0x1e, 0x8a, 0xed, 0x48, 0x05,
- 0x1c, 0xe4, 0x8f, 0xa5, 0x56, 0x82, 0x53, 0xf7, 0x18, 0x76, 0x4e, 0xa4, 0x2b, 0xde, 0x64, 0xcf,
- 0xc8, 0x39, 0x33, 0x52, 0x8a, 0x35, 0x78, 0xd9, 0x8e, 0x72, 0x1a, 0x86, 0x58, 0x8c, 0xba, 0x8d,
- 0xe2, 0x8e, 0xab, 0x8e, 0xbd, 0x9e, 0x33, 0x41, 0x40, 0x42, 0x76, 0x45, 0x91, 0x2c, 0x79, 0xfc,
- 0x32, 0xa9, 0x76, 0x2e, 0x42, 0x99, 0xa2, 0x7a, 0xbc, 0xe8, 0xcd, 0x64, 0xb9, 0x00, 0x87, 0xb1,
- 0xe3, 0x48, 0xa4, 0x25, 0x8d, 0x6a, 0x5b, 0xf0, 0x89, 0xf8, 0x24, 0x11, 0x1a, 0x2f, 0x2d, 0x99,
- 0xf8, 0x72, 0x38, 0xd8, 0xec, 0xef, 0xfe, 0x13, 0x9f, 0x5e, 0x3b, 0x0b, 0xd6, 0x83, 0xb7, 0x03,
- 0xb8, 0x7b, 0xe6, 0x34, 0xa7, 0x0b, 0xc3, 0x9d, 0x48, 0xdf, 0x8f, 0xe1, 0xc3, 0x62, 0x6b, 0xd4,
- 0xb1, 0x6c, 0xff, 0xf5, 0x45, 0xe4, 0xf5, 0x0d, 0xda, 0xc8, 0x96, 0x02, 0x30, 0x93, 0xcb, 0x76,
- 0x40, 0xfe, 0xea, 0x25, 0x66, 0xe8, 0xde, 0x30, 0x90, 0xed, 0x46, 0x56, 0x5c, 0xcf, 0x0d, 0x2a,
- 0xd3, 0x00, 0xa4, 0xfd, 0x84, 0x48, 0x5d, 0x5d, 0xe5, 0x8e, 0x45, 0x6f, 0x1d, 0xb4, 0x3d, 0x88,
- 0x92, 0x47, 0x3e, 0xfc, 0x97, 0x21, 0x3f, 0x03, 0x14, 0xef, 0x1e, 0xc4, 0xe5, 0x76, 0x87, 0x33,
- 0x35, 0x1b, 0x2d, 0xfe, 0x4f, 0xf0, 0x0f, 0xdf, 0x50, 0xcb, 0x4a, 0xb1, 0x1d, 0xed, 0x87, 0x14,
- 0x18, 0xa3, 0x6b, 0xc2, 0xd9, 0x2c, 0x3d, 0x69, 0xdf, 0xd5, 0x07, 0x10, 0x55, 0x8a, 0xab, 0xe5,
- 0xa7, 0x26, 0x27, 0xa2, 0xe6, 0xb3, 0xac, 0x75, 0x77, 0x37, 0xb8, 0xf3, 0xcb, 0x39, 0xa7, 0x98,
- 0xe3, 0x3a, 0x1d, 0x3b, 0xce, 0xcb, 0x51, 0x71, 0x5e, 0xfd, 0x98, 0x72, 0xa5, 0x6b, 0xec, 0x16,
- 0x7a, 0x8c, 0xec, 0xa4, 0xfa, 0x6e, 0xf3, 0x75, 0xac, 0x32, 0xb7, 0x37, 0x16, 0xba, 0xf3, 0x78,
- 0xf3, 0x4b, 0xb2, 0x0f, 0xec, 0x3a, 0xab, 0x52, 0x25, 0xc6, 0xcc, 0x6f, 0xc1, 0xb1, 0xc9, 0x82,
- 0xc2, 0x34, 0xd4, 0xd9, 0x11, 0x0b, 0x67, 0x7e, 0x72, 0x30, 0xd6, 0x40, 0xf4, 0xa4, 0xdc, 0xe7,
- 0x21, 0x5c, 0x3e, 0x25, 0xd4, 0xd4, 0x74, 0xea, 0x5a, 0xb8, 0x0a, 0x6a, 0x15, 0x1c, 0xa9, 0x96,
- 0xd8, 0x77, 0x23, 0x00, 0x73, 0xad, 0x26, 0x8a, 0x34, 0x2f, 0x5c, 0x08, 0x8b, 0x66, 0xa1, 0x47,
- 0x53, 0x1d, 0xd6, 0x31, 0x49, 0xca, 0x72, 0xd8, 0x9f, 0x41, 0x0a, 0x91, 0xe7, 0xad, 0x97, 0xc9,
- 0x58, 0xe2, 0x31, 0x15, 0x01, 0xbd, 0x53, 0xf4, 0x3a, 0xb1, 0x1f, 0xef, 0xce, 0x7d, 0xb0, 0x47,
- 0xb9, 0x66, 0xf3, 0x12, 0x80, 0xfb, 0x81, 0x7d, 0xba, 0x87, 0xca, 0x55, 0xcf, 0x60, 0x40, 0xdf,
- 0xad, 0xf9, 0x20, 0xbe, 0x04, 0x44, 0x32, 0x34, 0x71, 0xdc, 0x9b, 0x8f, 0xa0, 0x8b, 0xf8, 0x48,
- 0xbe, 0x35, 0xc9, 0xa9, 0x7b, 0x79, 0x81, 0x3e, 0xee, 0x14, 0x5b, 0x91, 0xa4, 0xa8, 0xbe, 0x27,
- 0x2b, 0x85, 0xdc, 0xf4, 0x7d, 0xf5, 0x09, 0xbe, 0x9e, 0x70, 0x18, 0xb1, 0x03, 0xde, 0x95, 0x92,
- 0x49, 0xd1, 0xc8, 0xd5, 0xbf, 0x88, 0xd3, 0xd8, 0x9c, 0x09, 0xfe, 0x2d, 0x91, 0x61, 0x37, 0xaa,
- 0x8c, 0x9c, 0x6a, 0x73, 0x48, 0xbc, 0x36, 0xd2, 0x58, 0x38, 0x9b, 0xdc, 0x51, 0x04, 0xdd, 0xe5,
- 0xce, 0x64, 0x77, 0x3c, 0x08, 0x40, 0x35, 0x92, 0xfa, 0x74, 0xb9, 0xd6, 0xeb, 0xcf, 0x85, 0xf9,
- 0x9a, 0xf5, 0x29, 0xa9, 0x22, 0xb7, 0xd7, 0x8b, 0xd8, 0xc6, 0x9f, 0xdb, 0xd1, 0x34, 0x38, 0x3f,
- 0xa8, 0xfd, 0xe5, 0x26, 0xb5, 0x3a, 0x5c, 0x30, 0xcc, 0xca, 0x33, 0x5d, 0xc5, 0x0f, 0x36, 0x0c,
- 0xe6, 0xa9, 0x2b, 0xe7, 0x7c, 0x9a, 0xcc, 0x3d, 0x87, 0xbd, 0x62, 0x81, 0x0d, 0xf7, 0x9c, 0xc2,
- 0x0e, 0xb9, 0xec, 0x39, 0xc0, 0xa4, 0xf2, 0x61, 0x67, 0x4f, 0x16, 0x2d, 0x2b, 0x8f, 0xdb, 0xb3,
- 0xea, 0x2d, 0x62, 0x84, 0x2c, 0xb3, 0x1f, 0xb7, 0x4b, 0x5b, 0xff, 0x83, 0x30, 0x50, 0x1f, 0xd8,
- 0xc5, 0x73, 0x65, 0x14, 0x84, 0x9a, 0xc3, 0xee, 0xda, 0xba, 0xc9, 0xc5, 0xe7, 0x6e, 0x7d, 0xb6,
- 0xaf, 0xb9, 0xba, 0x8b, 0x87, 0x71, 0x00, 0x84, 0x1a, 0xd8, 0x85, 0xa1, 0xb5, 0x78, 0xe5, 0xd7,
- 0x08, 0x70, 0xa3, 0xef, 0x2d, 0x81, 0xe1, 0x5e, 0xb1, 0xe4, 0x84, 0x70, 0x05, 0x6d, 0x2e, 0x3a,
- 0x7e, 0x8d, 0x08, 0x04, 0x81, 0x37, 0xd0, 0xf8, 0x24, 0x13, 0x66, 0xd7, 0xef, 0xe9, 0x7b, 0xc7,
- 0x01, 0xb1, 0x89, 0xcc, 0xf6, 0x09, 0x07, 0xdd, 0x7b, 0xf1, 0x29, 0x34, 0xd3, 0x3e, 0xbf, 0x44,
- 0x66, 0x52, 0xc8, 0x62, 0x65, 0xf9, 0x7f, 0x7d, 0x1b, 0x58, 0xdb, 0xcc, 0xea, 0x78, 0x85, 0x45,
- 0x30, 0x1b, 0xb7, 0x57, 0x46, 0xf6, 0x22, 0x4f, 0x59, 0x02, 0x2a, 0xbf, 0xa8, 0x8d, 0xa7, 0xa8,
- 0x9d, 0x20, 0x9d, 0x63, 0x3a, 0xdb, 0xe3, 0x74, 0xcd, 0x73, 0x43, 0x6f, 0xda, 0x1c, 0x94, 0xac,
- 0x24, 0x2f, 0xc8, 0xef, 0x0e, 0xff, 0xe4, 0xf2, 0xc6, 0x76, 0xd0, 0xe1, 0xbe, 0x09, 0xc2, 0xcb,
- 0xfb, 0x43, 0x9c, 0xa1, 0xf6, 0x66, 0x1d, 0x0a, 0xdc, 0xf7, 0x1d, 0xc3, 0x18, 0x36, 0xd5, 0x9f,
- 0x7b, 0xd0, 0xfa, 0xd2, 0xad, 0x55, 0x98, 0xe9, 0x8a, 0x7b, 0x80, 0xf4, 0xea, 0xba, 0xde, 0xf1,
- 0x08, 0xb2, 0xf2, 0xaf, 0x27, 0x1a, 0xf3, 0xe0, 0xef, 0x00, 0x10, 0x7f, 0xd1, 0xd5, 0x32, 0x10,
- 0x25, 0x95, 0x93, 0xf3, 0xd0, 0x9e, 0x31, 0xad, 0x26, 0x32, 0x53, 0xe2, 0x4e, 0x64, 0x69, 0xad,
- 0xa3, 0xf3, 0xd3, 0x92, 0x94, 0x72, 0xd4, 0xb3, 0xaf, 0x89, 0xf6, 0x02, 0x69, 0x8a, 0x4d, 0xf2,
- 0x91, 0x06, 0xbf, 0xf1, 0x66, 0x7f, 0xc3, 0x87, 0x9c, 0xec, 0x45, 0x42, 0x0c, 0x40, 0x79, 0x0e,
- 0xbe, 0x43, 0xe6, 0x11, 0xe9, 0x0b, 0x69, 0x0d, 0x89, 0x07, 0xef, 0xf7, 0x59, 0x43, 0x81, 0xe3,
- 0xfb, 0xee, 0x59, 0xb0, 0x48, 0x67, 0x64, 0x8e, 0x06, 0x24, 0xc1, 0x08, 0xe0, 0xb2, 0xb5, 0x1f,
- 0x48, 0xb9, 0x6e, 0x9d, 0x6b, 0x5c, 0xf8, 0x9c, 0xd6, 0x18, 0xbd, 0xc3, 0x21, 0x78, 0xda, 0x88,
- 0x0a, 0x59, 0xb1, 0xcb, 0x7d, 0xba, 0x7a, 0xe5, 0x1f, 0x8e, 0xb1, 0x2f, 0x20, 0x4b, 0xde, 0x5c,
- 0xfe, 0x0d, 0xfe, 0x4c, 0x5f, 0x12, 0x41, 0xd4, 0xc8, 0xb2, 0xdb, 0xa5, 0xa1, 0x3b, 0xc2, 0x05,
- 0xbc, 0x27, 0x55, 0x47, 0xef, 0x67, 0xd7, 0x2b, 0x94, 0x5b, 0x2d, 0x0c, 0xda, 0x92, 0xe1, 0x37,
- 0x80, 0xea, 0x3a, 0x5e, 0xb6, 0x45, 0xef, 0x5f, 0xb0, 0xec, 0xe5, 0x45, 0x06, 0x05, 0xc4, 0x83,
- 0x75, 0x3c, 0x58, 0xea, 0xfc, 0xe2, 0x53, 0xa6, 0x6b, 0xc9, 0x9e, 0x05, 0xbd, 0x85, 0x5d, 0x19,
- 0xb0, 0xd4, 0xa1, 0x00, 0xd3, 0xde, 0x5d, 0xfe, 0x0e, 0x57, 0x48, 0xd4, 0x87, 0xde, 0xd9, 0xf4,
- 0x40, 0x24, 0xeb, 0xe4, 0xec, 0x6d, 0xcb, 0xcc, 0xf1, 0xd8, 0xa3, 0xc8, 0x12, 0x9b, 0x0a, 0xc6,
- 0x85, 0xec, 0x63, 0x48, 0xcb, 0x0e, 0x91, 0x30, 0x1e, 0x45, 0xb3, 0x2a, 0xc7, 0xe0, 0xb5, 0x8f,
- 0x93, 0xf0, 0xbf, 0xd5, 0x9e, 0x83, 0xbd, 0x51, 0x9a, 0xda, 0x11, 0xe0, 0xb0, 0xfe, 0x19, 0xd9,
- 0xec, 0xed, 0xa7, 0x1d, 0xf2, 0x41, 0xc9, 0x27, 0xaa, 0xef, 0x41, 0x1c, 0x79, 0xb9, 0x65, 0x20,
- 0x64, 0x54, 0x9b, 0xd6, 0xdb, 0xee, 0x5e, 0x3e, 0xa1, 0x0f, 0x4a, 0x89, 0xac, 0x2c, 0xdf, 0x20,
- 0x35, 0x83, 0xf2, 0x15, 0x39, 0xf0, 0xb5, 0xc5, 0xc6, 0x27, 0x9c, 0x23, 0x57, 0xbe, 0x31, 0x5e,
- 0x7c, 0xfd, 0x25, 0x3a, 0xac, 0xca, 0x80, 0xed, 0x73, 0x27, 0x73, 0x3d, 0xe4, 0xec, 0xc1, 0xf4,
- 0x7c, 0x41, 0xcd, 0x92, 0xc4, 0x05, 0x09, 0xaf, 0x7c, 0x3c, 0x51, 0xd1, 0x01, 0x46, 0x26, 0x08,
- 0xfb, 0x44, 0xca, 0x8b, 0x19, 0xd8, 0x53, 0x46, 0x45, 0x3d, 0xca, 0x7a, 0x3d, 0x7a, 0xb6, 0x50,
- 0xfa, 0x3f, 0x1a, 0xd0, 0x3d, 0x53, 0xb5, 0x0f, 0xfc, 0xa5, 0x0f, 0x8a, 0xdd, 0x64, 0x80, 0x17,
- 0x73, 0xcf, 0xd4, 0x16, 0x41, 0x29, 0xee, 0xbb, 0x6d, 0x10, 0xd4, 0xd7, 0x90, 0xde, 0x78, 0x3b,
- 0xe2, 0x46, 0xdc, 0xe9, 0x37, 0xf9, 0x32, 0xc5, 0xf1, 0xe0, 0x9c, 0x9d, 0x45, 0x46, 0x47, 0xd7,
- 0xc7, 0x00, 0x04, 0xeb, 0xf5, 0xd7, 0x8a, 0x05, 0xc5, 0x6c, 0x8c, 0x9b, 0x03, 0x4d, 0x49, 0xca,
- 0xc7, 0x61, 0x9f, 0xdb, 0x56, 0xee, 0x6b, 0xf2, 0x9f, 0x98, 0xd4, 0xce, 0xb6, 0x59, 0x51, 0x1f,
- 0x3e, 0x41, 0xe1, 0xc0, 0x3e, 0x38, 0xd6, 0x86, 0x62, 0xe6, 0x58, 0xc6, 0x7a, 0xda, 0x7c, 0xe8,
- 0x7a, 0x8a, 0xdc, 0xdb, 0x58, 0x67, 0x49, 0x81, 0x0b, 0x9a, 0x97, 0x22, 0xba, 0xcd, 0xb6, 0xe3,
- 0x41, 0x80, 0x68, 0x5c, 0x0d, 0x8f, 0x0f, 0xb0, 0x0e, 0xab, 0xc6, 0xb7, 0x29, 0x0f, 0x07, 0x3c,
- 0x88, 0x1b, 0x41, 0x5d, 0x33, 0x2e, 0xa7, 0x2d, 0x1d, 0xae, 0x6b, 0x5d, 0x37, 0x48, 0x2e, 0xa3,
- 0x82, 0xd5, 0xc9, 0x28, 0xbc, 0x72, 0x7c, 0xad, 0x9a, 0x7d, 0xe0, 0x24, 0x31, 0x36, 0x8b, 0x49,
- 0x33, 0x44, 0x5a, 0xc8, 0x26, 0x82, 0x5f, 0x21, 0xf0, 0xdf, 0x2e, 0x97, 0x8d, 0x0a, 0x01, 0xa9,
- 0xec, 0x00, 0x8d, 0xbb, 0x9c, 0xff, 0x0b, 0x77, 0x99, 0xab, 0x1d, 0x29, 0xbe, 0x62, 0x6f, 0x1d,
- 0x68, 0xb4, 0x00, 0x61, 0xa9, 0x90, 0x55, 0x89, 0xd9, 0x31, 0x5d, 0x80, 0xd9, 0xb7, 0x53, 0xbe,
- 0xd3, 0x29, 0x1c, 0x75, 0x7f, 0x4c, 0x56, 0x73, 0x7f, 0xb5, 0x42, 0xfb, 0xb6, 0xc1, 0x2d, 0x86,
- 0xd6, 0x73, 0xa1, 0xa3, 0xe1, 0xe6, 0x8e, 0x47, 0x10, 0xbc, 0xce, 0xb2, 0x85, 0xef, 0xfd, 0x33,
- 0x1f, 0x18, 0xe9, 0x87, 0x36, 0xc2, 0x5e, 0x22, 0xb8, 0x62, 0x67, 0x33, 0xbc, 0xc8, 0x46, 0x53,
- 0x55, 0xd7, 0xef, 0x82, 0x98, 0xb7, 0x21, 0x12, 0x04, 0xd3, 0x0f, 0x80, 0x52, 0xe0, 0x35, 0xa7,
- 0x04, 0xc2, 0x47, 0x6a, 0xc8, 0xdc, 0xda, 0x9f, 0xe3, 0x18, 0x3c, 0x5d, 0x97, 0x31, 0x3b, 0x45,
- 0x56, 0xdc, 0xe3, 0x82, 0xb6, 0x7d, 0xcf, 0x60, 0x2b, 0xbe, 0x6a, 0x8b, 0xcc, 0x68, 0x55, 0xfb,
- 0x57, 0x7b, 0x80, 0x78, 0x07, 0xdd, 0xae, 0xf6, 0xb7, 0xac, 0x77, 0x9c, 0x71, 0x12, 0xbe, 0xf5,
- 0xf8, 0xda, 0xd2, 0xfd, 0x4f, 0x2d, 0xe3, 0xa0, 0xb2, 0xde, 0x67, 0x61, 0x4e, 0x79, 0xd0, 0xa1,
- 0x42, 0xc3, 0x0b, 0x27, 0x70, 0xd8, 0x2f, 0xaa, 0x28, 0x96, 0x65, 0x6e, 0x61, 0xe2, 0x2f, 0x52,
- 0xc7, 0x96, 0x4d, 0x96, 0x96, 0xeb, 0x37, 0xcb, 0xdd, 0x90, 0xab, 0xc7, 0x74, 0xd0, 0x09, 0xcc,
- 0x25, 0x52, 0x88, 0xee, 0x91, 0xd5, 0xdc, 0xcc, 0x20, 0x51, 0x24, 0x22, 0x1c, 0x8c, 0xad, 0xc2,
- 0x85, 0x36, 0x6b, 0xcc, 0x07, 0x7e, 0x17, 0x2b, 0xaf, 0x98, 0x30, 0x3c, 0xb2, 0xf4, 0x4b, 0x0b,
- 0x57, 0x10, 0x2e, 0x35, 0x64, 0x16, 0xf0, 0x3a, 0xf6, 0xab, 0x6f, 0x5f, 0x0a, 0x2b, 0xa7, 0x4b,
- 0xec, 0xf2, 0x02, 0x2b, 0x0a, 0xcf, 0x35, 0xd1, 0xf0, 0xc3, 0x4b, 0x0c, 0x8e, 0x1b, 0x08, 0xcf,
- 0x45, 0xf1, 0x98, 0x8c, 0xf7, 0x60, 0x60, 0xf6, 0x69, 0x22, 0x49, 0x70, 0x48, 0xbe, 0x2c, 0xb2,
- 0xba, 0xfd, 0x92, 0x1f, 0xfd, 0xfd, 0xdb, 0x93, 0x73, 0x6d, 0xb2, 0x7f, 0xe8, 0xe3, 0x4c, 0xa8,
- 0x7f, 0x12, 0x9a, 0xde, 0xe3, 0xee, 0x30, 0xc8, 0xcc, 0xcb, 0xa2, 0x99, 0xcf, 0x7e, 0xa2, 0x9f,
- 0xba, 0x1f, 0xd6, 0x38, 0x08, 0xc3, 0x45, 0xbd, 0x55, 0x47, 0x69, 0xbd, 0xd2, 0x42, 0x69, 0xf3,
- 0xb3, 0x68, 0xb7, 0xe5, 0x58, 0x4d, 0xb7, 0xd4, 0x47, 0x32, 0x45, 0xa1, 0x8c, 0x46, 0x76, 0xa2,
- 0x1d, 0x7a, 0x80, 0x1f, 0xde, 0xbd, 0x15, 0x96, 0x8a, 0xf9, 0xa6, 0xdb, 0x62, 0x98, 0x49, 0xef,
- 0xa7, 0x35, 0x4a, 0x19, 0x91, 0x23, 0x66, 0xa9, 0x3c, 0x64, 0x4c, 0x1f, 0xde, 0x93, 0x6e, 0x2b,
- 0x0e, 0xb1, 0xca, 0xa6, 0x2e, 0x3c, 0x24, 0x46, 0x88, 0x31, 0xe3, 0x11, 0x5b, 0x50, 0x63, 0xb2,
- 0x87, 0xca, 0x8c, 0x89, 0x09, 0x81, 0x52, 0x32, 0xc1, 0x5c, 0xa9, 0xbe, 0x1b, 0x77, 0xad, 0x67,
- 0x4d, 0xd2, 0x64, 0x24, 0x32, 0x9a, 0x00, 0xcf, 0xad, 0xd2, 0x04, 0x79, 0xde, 0x34, 0xb8, 0xdd,
- 0xef, 0x12, 0xaa, 0x35, 0x35, 0xa8, 0xca, 0x5e, 0xf3, 0x0b, 0xe3, 0x0f, 0xb4, 0x79, 0x67, 0xf2,
- 0x0f, 0x52, 0xa2, 0xe1, 0x12, 0x57, 0xa0, 0x33, 0xf3, 0xb8, 0x75, 0xcc, 0xd2, 0x29, 0xed, 0x21,
- 0x19, 0x41, 0xda, 0x67, 0x39, 0x60, 0x54, 0x2d, 0x51, 0x78, 0xc5, 0x34, 0x3b, 0x4b, 0xd5, 0x0a,
- 0x26, 0xa8, 0xde, 0x30, 0x3b, 0x60, 0xf1, 0x5b, 0x99, 0xff, 0xa3, 0x06, 0x71, 0x98, 0xca, 0xfa,
- 0x6f, 0x23, 0x74, 0x4d, 0x19, 0x49, 0xb2, 0x9b, 0x04, 0x68, 0x98, 0x03, 0xa8, 0x75, 0x5f, 0x44,
- 0x14, 0xe9, 0xa0, 0xa7, 0x23, 0x01, 0x3b, 0x77, 0x3e, 0xa1, 0x83, 0xc8, 0x44, 0xe6, 0x20, 0xab,
- 0x28, 0x48, 0xa1, 0xa0, 0xf0, 0x41, 0xc1, 0x83, 0x03, 0x62, 0x4e, 0x9f, 0x41, 0xfc, 0xb0, 0x93,
- 0x86, 0xc2, 0x12, 0x72, 0x42, 0xaf, 0xd3, 0x72, 0x6d, 0x89, 0xad, 0x54, 0xc9, 0xba, 0x29, 0xd7,
- 0x0e, 0x9d, 0x58, 0x3a, 0xb0, 0x85, 0x5d, 0x09, 0x1d, 0x1f, 0x03, 0xed, 0x9c, 0xce, 0xf3, 0x00,
- 0x42, 0xcb, 0xca, 0x06, 0x97, 0xff, 0xb6, 0xbc, 0x9b, 0xdc, 0xd5, 0x36, 0xf8, 0xd8, 0xd2, 0xc7,
- 0xfd, 0xf6, 0x07, 0x3c, 0x60, 0x12, 0x6c, 0x6d, 0xa3, 0x7d, 0xdd, 0x55, 0x7b, 0xf2, 0x31, 0xc3,
- 0x53, 0x8e, 0x30, 0xcc, 0x43, 0x08, 0xe6, 0x7a, 0x33, 0xca, 0xae, 0x24, 0x70, 0x80, 0x86, 0x59,
- 0xa2, 0x7c, 0x37, 0xc1, 0x2d, 0x54, 0x2b, 0x49, 0xc4, 0x5c, 0x7e, 0x47, 0xb7, 0xac, 0xac, 0x69,
- 0xa0, 0x22, 0x9b, 0xa0, 0xdc, 0xfa, 0x3f, 0xfe, 0xa4, 0x95, 0xca, 0x72, 0xa6, 0xdc, 0x84, 0x52,
- 0x51, 0xcb, 0x12, 0x72, 0xb8, 0xd5, 0x60, 0x95, 0x41, 0x91, 0x70, 0x6c, 0x68, 0x7c, 0xac, 0xa2,
- 0x0f, 0xe1, 0x3e, 0xc7, 0x22, 0x31, 0xba, 0x1b, 0x6d, 0x24, 0xa6, 0x2f, 0xf1, 0x75, 0xf3, 0x66,
- 0x13, 0x28, 0xb4, 0x1e, 0x86, 0x98, 0x47, 0x95, 0xc9, 0x0a, 0x40, 0x0b, 0xc4, 0x08, 0x80, 0x90,
- 0x7a, 0x9f, 0x66, 0x1b, 0x42, 0x8a, 0xa6, 0xb8, 0x7a, 0xc3, 0xab, 0x50, 0xc0, 0x83, 0x8b, 0xc8,
- 0x31, 0xc3, 0xee, 0x75, 0x91, 0x45, 0x80, 0xb8, 0x5d, 0x07, 0x08, 0xbc, 0x03, 0x22, 0x99, 0xac,
- 0x92, 0xab, 0x01, 0x87, 0x3e, 0xe5, 0xcc, 0x7d, 0xe4, 0x14, 0x28, 0x3b, 0xf5, 0x8e, 0x9f, 0x45,
- 0x24, 0xb0, 0x62, 0xd3, 0x02, 0x99, 0xb0, 0xe0, 0xeb, 0x03, 0xb8, 0x46, 0x8f, 0x47, 0x85, 0x6c,
- 0x65, 0x9d, 0x31, 0x80, 0xb8, 0x2f, 0x31, 0xff, 0xa8, 0x3a, 0x89, 0x47, 0xf9, 0x40, 0x06, 0xd3,
- 0xc3, 0x6b, 0x84, 0x01, 0x41, 0x1f, 0x4b, 0xee, 0x80, 0xed, 0xb2, 0xaa, 0xe9, 0x3d, 0x39, 0xa6,
- 0xe6, 0xf0, 0x70, 0x1f, 0xe6, 0x4e, 0xcf, 0xa1, 0x3d, 0xf3, 0x60, 0xd4, 0x39, 0xb8, 0x4b, 0x47,
- 0xb0, 0xc7, 0x7c, 0xae, 0x7b, 0x8d, 0x03, 0x23, 0xbb, 0xd8, 0x02, 0x85, 0x4e, 0x03, 0x5e, 0xf2,
- 0x0b, 0x0b, 0xc9, 0xec, 0x9a, 0x17, 0x23, 0x5f, 0x75, 0x1e, 0x64, 0x1d, 0x8a, 0x2e, 0xb4, 0x74,
- 0x6e, 0x4e, 0xff, 0x3a, 0xf2, 0x85, 0x5b, 0xe0, 0x43, 0xe9, 0x00, 0x99, 0xa3, 0x83, 0xe6, 0x2e,
- 0x3e, 0xa2, 0xd6, 0x00, 0x58, 0x6b, 0x9e, 0x4c, 0xe0, 0x03, 0xe3, 0x16, 0x15, 0x66, 0x64, 0x4a,
- 0x0d, 0xa8, 0xb9, 0x2c, 0x79, 0xdc, 0x55, 0xce, 0x4b, 0x5c, 0xc5, 0xf6, 0x5d, 0xf5, 0x5f, 0x36,
- 0x72, 0xe6, 0x26, 0x5e, 0xda, 0xe3, 0xef, 0xa8, 0xc5, 0x87, 0xce, 0x9f, 0x95, 0x5e, 0xc2, 0x9a,
- 0xf8, 0xd4, 0xf6, 0x56, 0x11, 0x98, 0x5a, 0xfb, 0x8f, 0x99, 0x4d, 0x54, 0x30, 0x94, 0xb4, 0x01,
- 0x0d, 0x58, 0x7a, 0xdb, 0x7d, 0x3b, 0x06, 0x2b, 0x76, 0x3a, 0xba, 0xf2, 0x87, 0x7d, 0x96, 0xf9,
- 0x9f, 0x4c, 0x10, 0x31, 0xec, 0xb0, 0x8f, 0x60, 0x9d, 0x06, 0x3a, 0x72, 0x2b, 0xa1, 0x95, 0x2d,
- 0x96, 0xf5, 0xe7, 0x1d, 0x82, 0x61, 0xc4, 0x5f, 0x60, 0xf2, 0x65, 0x2c, 0x4c, 0x79, 0xa5, 0x99,
- 0xdf, 0x24, 0x5f, 0x70, 0xed, 0x20, 0xca, 0x2b, 0x6d, 0xe0, 0x23, 0xc1, 0xfb, 0x4f, 0x65, 0xeb,
- 0xd3, 0xc2, 0xe3, 0x10, 0x5d, 0x85, 0xbe, 0xc1, 0xdc, 0x41, 0x92, 0xb6, 0xb6, 0x7e, 0xf1, 0x40,
- 0x0c, 0xfd, 0x8c, 0x3c, 0xad, 0x03, 0x57, 0x04, 0x35, 0xa2, 0x2f, 0x6c, 0x01, 0x81, 0x41, 0x99,
- 0xcc, 0xd7, 0xb6, 0x3b, 0x5d, 0xb7, 0xf9, 0x24, 0x47, 0x13, 0xe4, 0xc7, 0x30, 0xc0, 0xdb, 0x17,
- 0xfb, 0xa4, 0x5f, 0xae, 0x03, 0xf6, 0xe0, 0xed, 0x21, 0xec, 0x40, 0x39, 0xcd, 0xfa, 0x69, 0xde,
- 0x75, 0xa9, 0xe1, 0x42, 0x9c, 0xb0, 0xef, 0x8d, 0xa5, 0x17, 0x38, 0xe9, 0xca, 0x20, 0x62, 0xfb,
- 0x57, 0x15, 0x63, 0xbe, 0x3f, 0x72, 0x91, 0xc1, 0xd8, 0xe9, 0xab, 0x65, 0x1b, 0x64, 0x47, 0xb0,
- 0xad, 0x4c, 0xcc, 0xc5, 0x0c, 0x19, 0x9d, 0x96, 0xe6, 0x70, 0x9a, 0x00, 0x59, 0x1b, 0x3c, 0x5e,
- 0xc2, 0xcb, 0xb2, 0x18, 0xc7, 0xee, 0xe2, 0xe3, 0xd5, 0xa4, 0xb0, 0x96, 0x0f, 0x92, 0xea, 0x27,
- 0x29, 0xd2, 0x17, 0x7e, 0x2d, 0x58, 0x6e, 0x25, 0x62, 0x17, 0x84, 0x8c, 0x04, 0xc7, 0xc9, 0x04,
- 0x75, 0x96, 0x8f, 0xe0, 0xb6, 0x4f, 0xeb, 0x2f, 0xec, 0x8f, 0x09, 0x5a, 0xab, 0x7e, 0x61, 0xcd,
- 0xcf, 0xfc, 0xac, 0x92, 0x59, 0xb4, 0xfe, 0x31, 0xbb, 0x25, 0xd2, 0x0a, 0x68, 0xce, 0xb2, 0x4c,
- 0x61, 0x7e, 0xc5, 0x64, 0xa0, 0x9c, 0xa7, 0x3d, 0xbf, 0xfb, 0x63, 0x8a, 0xbc, 0x7f, 0x8c, 0x8d,
- 0x82, 0xfd, 0xd7, 0x7f, 0x6e, 0x20, 0x8a, 0x25, 0x36, 0x43, 0x25, 0x4c, 0x9f, 0x05, 0x57, 0xe0,
- 0x19, 0x25, 0xf4, 0x14, 0x5d, 0xe4, 0x3f, 0x3b, 0x76, 0x3e, 0xc8, 0xba, 0xc8, 0x8b, 0xca, 0x06,
- 0x3a, 0xa0, 0x06, 0x6e, 0x22, 0x47, 0xba, 0x97, 0x45, 0x06, 0x63, 0x23, 0x1b, 0x0f, 0xb3, 0x6f,
- 0x09, 0x77, 0x8f, 0x49, 0x01, 0x4d, 0x3f, 0x52, 0xa6, 0x3c, 0x4b, 0xdb, 0x95, 0x3d, 0x1b, 0xbe,
- 0xef, 0x50, 0x63, 0xaa, 0x3e, 0xca, 0xd6, 0x51, 0x43, 0xa9, 0x61, 0xe6, 0xec, 0xc2, 0x88, 0xca,
- 0x39, 0x68, 0x0d, 0xfc, 0xbe, 0xe4, 0xab, 0xaa, 0x78, 0x85, 0x77, 0xb1, 0x89, 0xbd, 0xf0, 0x4c,
- 0x1a, 0xaf, 0x41, 0x5f, 0xb3, 0xfe, 0x95, 0x96, 0x47, 0x76, 0x8c, 0xbe, 0x27, 0xd5, 0x5c, 0x1f,
- 0x48, 0x09, 0xc7, 0x23, 0x0c, 0x52, 0x82, 0x94, 0xd1, 0x60, 0x76, 0x67, 0x22, 0x84, 0x6c, 0x5b,
- 0x8a, 0xa3, 0x19, 0x92, 0xe4, 0xa4, 0x4f, 0xc8, 0x56, 0x47, 0xda, 0xfe, 0x95, 0xc9, 0x57, 0x08,
- 0xa6, 0x1f, 0x0a, 0x98, 0x0f, 0xcc, 0xc2, 0xff, 0x58, 0x1f, 0xb8, 0x5c, 0x0c, 0xd5, 0x68, 0xa4,
- 0x30, 0xc5, 0x66, 0x5c, 0x4d, 0x17, 0x78, 0xec, 0x8a, 0x6c, 0xe0, 0x9f, 0x4f, 0x74, 0xbf, 0xe3,
- 0x6c, 0xdb, 0x98, 0x27, 0x2c, 0xb8, 0x71, 0xe4, 0x72, 0x71, 0xf4, 0xa1, 0x33, 0x3a, 0xc9, 0x4d,
- 0xa5, 0x10, 0x03, 0xa7, 0xa6, 0x5e, 0xa3, 0x85, 0xed, 0xfa, 0x5b, 0x7d, 0x63, 0x43, 0x39, 0xe8,
- 0x29, 0x97, 0xc1, 0x83, 0xe2, 0x8d, 0x1d, 0xa2, 0x27, 0xbd, 0xa1, 0xe6, 0x68, 0xb9, 0x9b, 0xab,
- 0x9f, 0x46, 0x50, 0x1a, 0x0b, 0x25, 0x6f, 0x05, 0xc5, 0xc4, 0x1e, 0x29, 0x02, 0x6b, 0x2c, 0xb6,
- 0x74, 0x7c, 0xcb, 0x4c, 0x77, 0xab, 0xc3, 0xc6, 0xc8, 0xa2, 0x81, 0xaa, 0x6f, 0xe0, 0xba, 0x36,
- 0xa7, 0x05, 0xc7, 0xd0, 0x76, 0x6a, 0x55, 0x67, 0x59, 0x9d, 0xff, 0x75, 0xdb, 0x35, 0x2c, 0xe2,
- 0x51, 0x82, 0xce, 0x1f, 0x2c, 0x49, 0xdd, 0x04, 0x9e, 0xcf, 0xa2, 0xa1, 0x03, 0xf3, 0x3a, 0x79,
- 0xda, 0x59, 0xbc, 0x75, 0x76, 0xdd, 0xb0, 0xe3, 0x3e, 0xe3, 0xbc, 0x0b, 0xfe, 0x62, 0xed, 0xd5,
- 0x9a, 0x5f, 0x08, 0xb1, 0xab, 0xf3, 0xa9, 0x95, 0xa7, 0x5c, 0xe3, 0x7b, 0x58, 0xfb, 0xc1, 0x34,
- 0x09, 0x56, 0xb2, 0xab, 0x31, 0x46, 0xac, 0x3c, 0x56, 0x08, 0xcb, 0x0c, 0x08, 0xa0, 0x82, 0xf3,
- 0xc0, 0x91, 0xcd, 0xd0, 0x5d, 0x43, 0xa8, 0xbe, 0x46, 0x36, 0x8a, 0xfb, 0x25, 0x92, 0x18, 0x8d,
- 0xdd, 0x9d, 0xd6, 0xce, 0x99, 0xcc, 0x6d, 0x36, 0xa0, 0x8c, 0xab, 0x8f, 0xe0, 0x2f, 0x29, 0xbc,
- 0x02, 0xef, 0x25, 0xb6, 0xb2, 0xfc, 0x9f, 0x8f, 0xe8, 0xc1, 0x49, 0x0c, 0x5b, 0x77, 0x46, 0xf6,
- 0x60, 0xac, 0x9d, 0xd8, 0xd8, 0x6f, 0xee, 0xf0, 0x93, 0x9f, 0xe8, 0x38, 0x1f, 0x25, 0x3e, 0x9e,
- 0x5d, 0xef, 0x93, 0xef, 0xd4, 0x4d, 0x8a, 0xff, 0xa0, 0x78, 0xac, 0x91, 0x52, 0x02, 0x86, 0x60,
- 0x5a, 0xcb, 0x31, 0x6a, 0x29, 0xf8, 0xe9, 0xee, 0xec, 0x05, 0xf8, 0x4d, 0xdd, 0x70, 0xdc, 0x65,
- 0x84, 0x44, 0xac, 0x71, 0xdc, 0x74, 0x3a, 0xac, 0xa2, 0x09, 0xfd, 0x47, 0xb3, 0x0c, 0xef, 0x99,
- 0x43, 0x46, 0xc9, 0x2b, 0x95, 0x43, 0xc0, 0x59, 0xda, 0x3a, 0x43, 0x26, 0x99, 0x8a, 0x57, 0xf3,
- 0x5e, 0x41, 0x1f, 0x3e, 0x22, 0xf4, 0x57, 0x54, 0x98, 0x5a, 0xf5, 0x8c, 0x37, 0x0c, 0xca, 0xd4,
- 0x29, 0xb4, 0x9d, 0x1a, 0xf4, 0x45, 0x28, 0x2e, 0xe7, 0xfd, 0x52, 0xef, 0x3a, 0xee, 0xbe, 0x6e,
- 0xfc, 0xe1, 0x15, 0x3e, 0xfb, 0x89, 0x93, 0x81, 0xfe, 0x67, 0xa0, 0xaa, 0xe2, 0x11, 0x9e, 0xaa,
- 0xdf, 0x5a, 0x11, 0x6e, 0xae, 0x7c, 0xb5, 0xa6, 0x0f, 0xe8, 0x34, 0x00, 0x0d, 0x85, 0x8a, 0xfc,
- 0x2b, 0xa5, 0x7a, 0x3f, 0xf4, 0x17, 0x00, 0xde, 0x1c, 0x8b, 0x18, 0x2c, 0xc9, 0x8c, 0x02, 0x52,
- 0x77, 0x29, 0xd5, 0x92, 0x84, 0x70, 0xe7, 0xca, 0xfa, 0xe5, 0xc5, 0xe2, 0xaf, 0xdd, 0x73, 0x3c,
- 0xe8, 0x59, 0x2b, 0xf4, 0x2f, 0x3a, 0xe9, 0x40, 0x3d, 0xb4, 0x13, 0x12, 0x65, 0x36, 0xa5, 0x82,
- 0x2c, 0xd4, 0xa5, 0x0e, 0xcf, 0x8e, 0x63, 0x57, 0xff, 0xfc, 0x75, 0x87, 0x86, 0xda, 0xa8, 0x5e,
- 0x54, 0xde, 0xc2, 0x40, 0x9a, 0x4e, 0xfd, 0xd6, 0x41, 0xdf, 0x39, 0x03, 0x8a, 0x0a, 0xf1, 0x8a,
- 0x21, 0x74, 0x71, 0x83, 0x0e, 0x49, 0x64, 0x92, 0xce, 0x27, 0x3d, 0xed, 0x53, 0x48, 0x96, 0x13,
- 0x1d, 0xfb, 0x8b, 0x07, 0x56, 0x05, 0x13, 0x96, 0x47, 0x96, 0x5a, 0x92, 0x6b, 0x19, 0xef, 0x36,
- 0xaf, 0x6d, 0x98, 0x47, 0x85, 0x20, 0x0f, 0xed, 0xfe, 0xb6, 0xba, 0x45, 0xca, 0x42, 0x1f, 0xf5,
- 0x0d, 0x55, 0xe8, 0x24, 0x26, 0x6c, 0x30, 0xff, 0xe6, 0x55, 0xd7, 0xeb, 0xed, 0x12, 0x99, 0x14,
- 0x8e, 0xfb, 0x5b, 0x38, 0xb9, 0xfc, 0xdb, 0x9c, 0x70, 0x8d, 0x63, 0x1d, 0xc6, 0xef, 0x5b, 0x9b,
- 0xa4, 0x30, 0x4d, 0x23, 0x17, 0xb6, 0x0e, 0xf0, 0x8a, 0xd2, 0x50, 0x7e, 0x44, 0x34, 0x59, 0xe9,
- 0xc9, 0x34, 0x3e, 0xf6, 0x75, 0x6d, 0xfc, 0xc0, 0x8a, 0xfd, 0xf9, 0x73, 0xb4, 0x0c, 0xe1, 0x23,
- 0xcd, 0x45, 0x62, 0xec, 0x3e, 0xaa, 0x8e, 0xd3, 0x86, 0xcf, 0x53, 0xd7, 0x93, 0x62, 0x47, 0x23,
- 0xd9, 0x18, 0x06, 0xa2, 0x35, 0xef, 0x73, 0x57, 0x50, 0xc9, 0xdc, 0xbb, 0xb7, 0x05, 0xc6, 0x52,
- 0x44, 0xe8, 0x15, 0x6b, 0x5b, 0xd2, 0xf3, 0xf3, 0xd4, 0x1c, 0xa4, 0xaf, 0x73, 0x6a, 0x91, 0x81,
- 0x0b, 0xe8, 0x15, 0xed, 0x54, 0x60, 0xc2, 0x0e, 0xc8, 0xf9, 0x69, 0xbb, 0xac, 0x55, 0xcc, 0x36,
- 0xaf, 0x04, 0x3c, 0x2f, 0xc9, 0xbf, 0x1c, 0xc6, 0x99, 0x48, 0x0c, 0x5d, 0xd7, 0x16, 0xf0, 0x46,
- 0x8d, 0x59, 0x7b, 0x78, 0x49, 0xa4, 0xb5, 0x4c, 0x60, 0xa1, 0x24, 0x58, 0x61, 0x38, 0xa1, 0x46,
- 0x37, 0x02, 0xd0, 0x73, 0x52, 0xa5, 0x4b, 0xb3, 0xc9, 0xd9, 0x32, 0x43, 0xa6, 0x6a, 0xce, 0x14,
- 0xba, 0xe5, 0x71, 0xfc, 0x5e, 0xd6, 0xc3, 0x46, 0x4a, 0x4e, 0xfd, 0x6b, 0xa1, 0x75, 0xd0, 0x22,
- 0x6b, 0xe6, 0x1f, 0xc4, 0x1d, 0x1f, 0x22, 0x69, 0x09, 0x24, 0x1b, 0x92, 0x38, 0x42, 0xaa, 0x67,
- 0x52, 0x76, 0xba, 0xae, 0x9e, 0x3e, 0x68, 0x66, 0x96, 0xd4, 0x79, 0xb0, 0xeb, 0xe6, 0x86, 0x29,
- 0x2b, 0x74, 0x16, 0x22, 0x9f, 0xb6, 0xe6, 0xbd, 0xe3, 0xf9, 0xaa, 0x5f, 0xcf, 0xe1, 0xcb, 0xdb,
- 0xd4, 0x91, 0x13, 0xb2, 0x30, 0x52, 0xe1, 0xde, 0xbc, 0xef, 0x94, 0xe9, 0x2c, 0xfe, 0xd0, 0xdb,
- 0x44, 0x46, 0x24, 0xeb, 0x2f, 0xf7, 0x54, 0x7c, 0x49, 0x50, 0x1f, 0x64, 0xdb, 0xc1, 0xa6, 0x98,
- 0x5e, 0xd6, 0xce, 0xc2, 0xec, 0x76, 0x39, 0xa7, 0x27, 0xc3, 0x9c, 0x2f, 0xc9, 0xf8, 0xd0, 0xa3,
- 0xb4, 0x77, 0xea, 0xd6, 0xab, 0xbd, 0x64, 0xaf, 0x07, 0x77, 0x8f, 0x20, 0x59, 0x9e, 0x48, 0x02,
- 0x74, 0xb5, 0x45, 0x93, 0x74, 0x52, 0xba, 0x9c, 0x3b, 0xcd, 0x75, 0x7f, 0x4b, 0x4d, 0x15, 0x4a,
- 0x65, 0x90, 0x67, 0x3f, 0xdc, 0x55, 0x29, 0x69, 0xbb, 0x4d, 0x5a, 0xe9, 0x1d, 0xf4, 0x5d, 0xf5,
- 0x8a, 0x9f, 0x62, 0x2d, 0x12, 0xb3, 0x31, 0xdf, 0x52, 0x77, 0xfe, 0x34, 0xf5, 0xdf, 0xa3, 0xb7,
- 0x04, 0x94, 0x8e, 0xc2, 0xa7, 0xd4, 0xfa, 0x8f, 0xd9, 0x86, 0x56, 0x8b, 0x1b, 0xf0, 0x64, 0xea,
- 0x3b, 0x08, 0x59, 0x58, 0x23, 0xeb, 0x9a, 0x3d, 0xb7, 0xea, 0xb4, 0x28, 0xbe, 0x15, 0x6d, 0x0e,
- 0x0b, 0x25, 0x4d, 0x5e, 0x2d, 0xf7, 0x65, 0xdf, 0x21, 0x26, 0x89, 0x75, 0x1b, 0xbe, 0x94, 0x10,
- 0xb4, 0x77, 0xee, 0x03, 0xc6, 0x34, 0x98, 0xdb, 0x82, 0x02, 0xac, 0x50, 0x2e, 0xec, 0x94, 0x2e,
- 0xb3, 0x7b, 0x78, 0x82, 0xa9, 0x48, 0x82, 0xff, 0xa8, 0x7b, 0x82, 0x9f, 0xf1, 0xa8, 0x7e, 0x57,
- 0x82, 0xad, 0xab, 0x88, 0x8b, 0x8f, 0xc0, 0x9c, 0xa1, 0x26, 0xb5, 0xa4, 0xc0, 0x0c, 0xf0, 0x46,
- 0x4c, 0x9f, 0x04, 0x79, 0x80, 0x33, 0x3b, 0x9b, 0x91, 0x34, 0x67, 0x06, 0x2f, 0x89, 0x46, 0xf3,
- 0x90, 0x7a, 0xba, 0x7f, 0x03, 0x0d, 0xcb, 0xad, 0xa9, 0x4c, 0xd3, 0x50, 0x1d, 0x8a, 0x26, 0x16,
- 0x05, 0x30, 0x76, 0x8a, 0x77, 0x06, 0x86, 0x01, 0x43, 0x9d, 0xbf, 0xf8, 0xfe, 0xe8, 0xfc, 0xe3,
- 0xd2, 0x52, 0xf7, 0x71, 0xfa, 0x14, 0xb0, 0x62, 0xe4, 0x76, 0x4c, 0xba, 0x6f, 0x35, 0x55, 0xf1,
- 0x3b, 0x0a, 0xcb, 0x6c, 0x4e, 0x2d, 0x1d, 0x50, 0xb1, 0x99, 0xa4, 0x57, 0xd1, 0x26, 0x2f, 0x90,
- 0x66, 0x9c, 0xb2, 0x40, 0xb4, 0xb6, 0xa4, 0xb9, 0xa4, 0xff, 0x4b, 0x88, 0x1e, 0xbc, 0xe2, 0xd8,
- 0xba, 0xc9, 0x14, 0xbb, 0x79, 0x85, 0x27, 0xdc, 0xb1, 0xde, 0xd7, 0x0a, 0x0f, 0x92, 0xf7, 0x7c,
- 0xe9, 0xe9, 0x9a, 0x67, 0xeb, 0x6a, 0xf5, 0x67, 0xbc, 0x3b, 0xf3, 0x12, 0xd9, 0x4e, 0x26, 0x8c,
- 0x82, 0x17, 0x3f, 0x4d, 0x75, 0xdb, 0x6a, 0xb7, 0x4e, 0x4b, 0x78, 0x32, 0xbe, 0x22, 0x11, 0x99,
- 0x23, 0x5e, 0xfa, 0xda, 0xd8, 0x20, 0x25, 0x2f, 0x49, 0x0e, 0x04, 0xbe, 0xe2, 0x95, 0x7f, 0x5d,
- 0xc0, 0x05, 0x41, 0x55, 0xc2, 0x15, 0x43, 0x38, 0xb1, 0xf6, 0x38, 0xb2, 0x3a, 0x6f, 0x91, 0x05,
- 0x5a, 0xf9, 0xfa, 0xce, 0x79, 0x56, 0x16, 0xfd, 0x41, 0xe1, 0x42, 0x89, 0x77, 0x3e, 0x63, 0x69,
- 0xd4, 0x06, 0x43, 0x81, 0x25, 0x10, 0x4b, 0x5c, 0x3b, 0xbb, 0x5c, 0x19, 0x77, 0x01, 0x01, 0xad,
- 0x58, 0xa7, 0x88, 0x7e, 0x1c, 0x04, 0x00, 0x13, 0xa5, 0x65, 0x91, 0x3b, 0xb8, 0x4a, 0x4d, 0xe1,
- 0x9c, 0x7d, 0x91, 0x74, 0x64, 0x36, 0x15, 0xff, 0xe8, 0xf7, 0x0d, 0x86, 0x7d, 0xcb, 0x55, 0xbc,
- 0x09, 0x01, 0x71, 0xd5, 0x91, 0xd2, 0xd9, 0x83, 0xa1, 0x82, 0x69, 0xeb, 0x93, 0x99, 0x51, 0x40,
- 0xfe, 0xc4, 0xbe, 0x95, 0x16, 0x95, 0x42, 0x9c, 0xfa, 0x30, 0x87, 0x72, 0x92, 0x46, 0x42, 0x20,
- 0xa2, 0x9c, 0xae, 0xdb, 0x5a, 0x26, 0xc9, 0x1a, 0x9c, 0x0a, 0xed, 0xa9, 0x48, 0x61, 0x3c, 0xa3,
- 0x6a, 0xa9, 0xef, 0x2b, 0x67, 0x8f, 0xe4, 0x8f, 0xef, 0xd2, 0xd5, 0xf6, 0x9f, 0x63, 0x5d, 0x8c,
- 0x4f, 0x28, 0xc1, 0xc8, 0x3c, 0x20, 0x22, 0x58, 0x53, 0x3d, 0xab, 0xbd, 0x76, 0x54, 0x40, 0xe2,
- 0xdb, 0xc6, 0x79, 0xdf, 0x47, 0x61, 0xfe, 0x3c, 0xf6, 0x0e, 0xe2, 0x1f, 0xd4, 0x4a, 0x3d, 0x4a,
- 0x1a, 0xbe, 0x45, 0x27, 0x74, 0xd7, 0xe9, 0x74, 0x7d, 0xd1, 0x54, 0x56, 0xd6, 0xd7, 0xcf, 0xa0,
- 0x5c, 0x70, 0xbd, 0xa3, 0xbb, 0x91, 0x98, 0x23, 0x4c, 0x57, 0xc7, 0xcf, 0xc8, 0x0e, 0x91, 0x1f,
- 0x3c, 0x2f, 0x1e, 0x98, 0x2c, 0xf6, 0xe2, 0x13, 0x67, 0x95, 0xb4, 0xb4, 0xdc, 0x4e, 0x69, 0x9f,
- 0x99, 0x3d, 0x1c, 0xb6, 0x80, 0xe8, 0xc9, 0x38, 0xd2, 0x29, 0xca, 0x0a, 0x18, 0x53, 0xdc, 0x5b,
- 0x4b, 0x91, 0x8b, 0xde, 0x3f, 0xd1, 0x3b, 0x01, 0x83, 0xb5, 0xf5, 0xd3, 0x13, 0x7a, 0x0e, 0xcf,
- 0xa5, 0x3d, 0xba, 0x9f, 0x5d, 0xb4, 0x40, 0x21, 0x79, 0x22, 0x7d, 0xbd, 0xca, 0x0c, 0x1f, 0xb9,
- 0xcd, 0x7d, 0x44, 0x86, 0x23, 0xc3, 0xa8, 0x36, 0xda, 0xc4, 0xb1, 0xf5, 0x77, 0x96, 0xa4, 0x5e,
- 0x85, 0x55, 0x95, 0x05, 0x3b, 0x9c, 0x12, 0x95, 0x4a, 0x30, 0xed, 0x5e, 0xc0, 0xb4, 0x2d, 0xed,
- 0xda, 0x63, 0x49, 0xc7, 0xed, 0x96, 0xa3, 0xc0, 0xf4, 0x02, 0x5f, 0x41, 0x99, 0x79, 0xf2, 0x16,
- 0x42, 0x20, 0x14, 0x3a, 0x89, 0xa0, 0x4b, 0x52, 0x88, 0xdf, 0x1d, 0xf2, 0x5f, 0x5c, 0x8d, 0xb3,
- 0xf0, 0x58, 0x37, 0x3d, 0xfd, 0xb9, 0x23, 0xb5, 0xe0, 0xbb, 0xa9, 0x59, 0x60, 0x2a, 0xa9, 0xcc,
- 0xfd, 0xef, 0xc0, 0x08, 0xcf, 0x54, 0xc0, 0xed, 0xa9, 0xd3, 0x3c, 0xbe, 0x24, 0xe7, 0xb9, 0xd1,
- 0x7d, 0xd1, 0x08, 0xa1, 0xd0, 0xe2, 0x6f, 0x20, 0x8d, 0xa3, 0x87, 0x20, 0x83, 0x82, 0x24, 0x3f,
- 0x3b, 0x15, 0x48, 0x10, 0x89, 0x04, 0xc6, 0x1e, 0x46, 0xba, 0x49, 0x88, 0x05, 0x15, 0xcf, 0xd8,
- 0xc8, 0xa7, 0xdb, 0xca, 0x46, 0x07, 0x6a, 0x94, 0x60, 0xbc, 0x9b, 0x2b, 0xa6, 0xb0, 0x24, 0x31,
- 0xe9, 0x5a, 0x11, 0x96, 0x22, 0x48, 0x63, 0xb6, 0xb1, 0x43, 0x97, 0xf4, 0x98, 0x09, 0xd4, 0xf3,
- 0x99, 0xd1, 0xfd, 0xb6, 0xe1, 0x3e, 0x27, 0x4a, 0xc4, 0x96, 0x7f, 0x0d, 0x18, 0xd4, 0xd9, 0x31,
- 0x3a, 0x80, 0xfc, 0x64, 0x62, 0x86, 0x8c, 0xdd, 0xd8, 0x45, 0x2c, 0x43, 0x53, 0x03, 0x93, 0x46,
- 0xf9, 0x38, 0x08, 0x7d, 0xc0, 0xb1, 0x5d, 0xc9, 0xe3, 0xff, 0x06, 0x5e, 0x13, 0x3e, 0x9d, 0x7a,
- 0x7e, 0x58, 0x61, 0xb9, 0xc8, 0x9f, 0xf0, 0xaf, 0x9f, 0xe9, 0x6b, 0x3d, 0x66, 0xd2, 0xb0, 0x90,
- 0x8f, 0xd4, 0x79, 0xa9, 0xbd, 0x49, 0x2e, 0x9b, 0xd9, 0xe6, 0x87, 0x34, 0x13, 0x84, 0x70, 0xf8,
- 0xe1, 0x6a, 0x64, 0x18, 0x3f, 0xf2, 0xed, 0x77, 0xc1, 0xf7, 0xbc, 0xaf, 0xf3, 0xb3, 0x21, 0x26,
- 0x22, 0x72, 0x49, 0x26, 0x07, 0xd1, 0x99, 0x47, 0x54, 0x4d, 0x52, 0xa7, 0xe2, 0x60, 0xa3, 0x7a,
- 0xb2, 0x24, 0x94, 0xe0, 0xe4, 0xc2, 0xcc, 0x3e, 0x7c, 0x8f, 0x7f, 0x81, 0x61, 0xb4, 0xa4, 0x81,
- 0x54, 0xa0, 0xfa, 0xdf, 0xb5, 0x5f, 0xee, 0xe2, 0xc2, 0x3b, 0x29, 0x2a, 0x70, 0xc5, 0x77, 0x81,
- 0x40, 0x01, 0x67, 0x9f, 0x75, 0x2b, 0x05, 0xa2, 0x5a, 0x8d, 0x71, 0x60, 0x17, 0x53, 0xf8, 0x8c,
- 0xe8, 0x8b, 0x54, 0x85, 0xdd, 0x18, 0x23, 0x94, 0x75, 0x84, 0x89, 0x74, 0x67, 0xd1, 0xfd, 0xe3,
- 0xca, 0x07, 0xf9, 0x08, 0x95, 0xbc, 0xe3, 0xce, 0xf5, 0x58, 0xed, 0x0e, 0xc4, 0x46, 0xc2, 0x20,
- 0xcd, 0x10, 0xb9, 0x3b, 0x46, 0x87, 0xda, 0xa7, 0x7d, 0x64, 0x65, 0x06, 0x0a, 0xda, 0xf2, 0xa3,
- 0x3e, 0xc4, 0x84, 0xe0, 0x4d, 0x27, 0xc1, 0xde, 0x6d, 0x06, 0x51, 0x20, 0x9c, 0xc0, 0x17, 0x89,
- 0xbf, 0x24, 0x22, 0xdd, 0x71, 0x20, 0xfa, 0xc6, 0xc1, 0x09, 0x55, 0xce, 0xc7, 0x91, 0x64, 0xcc,
- 0x00, 0xa1, 0xd6, 0x62, 0xbf, 0x1b, 0x76, 0x16, 0x00, 0x4e, 0xa2, 0x20, 0xf7, 0x22, 0x6b, 0xa0,
- 0x63, 0xa8, 0x5d, 0x35, 0xd6, 0xbb, 0xfb, 0xb8, 0x08, 0xed, 0x89, 0x04, 0xc9, 0xb1, 0x91, 0xe5,
- 0x7e, 0xe1, 0xf1, 0x21, 0x30, 0xed, 0x01, 0x3a, 0x04, 0x01, 0x11, 0xc9, 0x6d, 0x67, 0xb2, 0x68,
- 0x09, 0x14, 0xa6, 0x10, 0x39, 0x9d, 0xcc, 0x87, 0x98, 0x0a, 0x6b, 0xd7, 0x7d, 0xd3, 0xce, 0x77,
- 0x56, 0x0b, 0x5f, 0xdf, 0x6a, 0x04, 0xf1, 0x13, 0x8b, 0x54, 0x11, 0x2b, 0x31, 0xc8, 0xff, 0xcf,
- 0x52, 0xab, 0xdb, 0x13, 0xfc, 0x06, 0xed, 0xcc, 0x31, 0x00, 0xbf, 0xd8, 0x7b, 0x9b, 0xea, 0xcf,
- 0x80, 0xc9, 0x3c, 0x95, 0xe2, 0x07, 0x39, 0x8c, 0x70, 0x54, 0x70, 0x3e, 0x4a, 0x8d, 0xa1, 0xfc,
- 0x82, 0x4b, 0xc2, 0x14, 0xb0, 0xc9, 0x86, 0x66, 0x0b, 0x9d, 0xce, 0xf0, 0x3b, 0x04, 0xd0, 0xc1,
- 0x83, 0x40, 0x4e, 0x7b, 0x6f, 0x1b, 0x55, 0x11, 0x76, 0x91, 0x16, 0x66, 0xaa, 0x24, 0x99, 0x95,
- 0xb4, 0x26, 0x1f, 0x29, 0xc3, 0x05, 0x7f, 0x0a, 0x72, 0x83, 0x6a, 0x4c, 0xa7, 0x1a, 0xd0, 0x6e,
- 0xab, 0xeb, 0xbf, 0x17, 0x1f, 0x15, 0x3e, 0xac, 0xdd, 0x1d, 0x30, 0xc2, 0x1c, 0x2c, 0xd3, 0xf3,
- 0x68, 0xd7, 0x8e, 0x11, 0x52, 0x45, 0x8f, 0xd9, 0xd6, 0x0f, 0x4c, 0x4f, 0x8d, 0x0a, 0x4c, 0x80,
- 0x0d, 0x4d, 0x1b, 0x14, 0x9f, 0x26, 0xa0, 0x5f, 0x7d, 0xd4, 0xbb, 0x83, 0x36, 0x5a, 0xd7, 0x4a,
- 0x61, 0xd5, 0x34, 0x8a, 0x89, 0xd5, 0x4c, 0x76, 0xda, 0x68, 0x79, 0xf4, 0x33, 0x05, 0x9a, 0x6e,
- 0xbb, 0x87, 0x65, 0xed, 0x62, 0x6c, 0xfa, 0x9d, 0xc9, 0xcc, 0x98, 0xe4, 0x38, 0xd4, 0xec, 0xbb,
- 0x8a, 0x28, 0x87, 0x23, 0x7a, 0x00, 0x8c, 0x15, 0x5d, 0x78, 0x61, 0xf3, 0xf7, 0x44, 0x64, 0xbb,
- 0x38, 0x65, 0xd9, 0x84, 0x0c, 0x56, 0xf7, 0x43, 0xc5, 0x96, 0x64, 0xcb, 0xef, 0x85, 0xa8, 0x2a,
- 0x9d, 0x1e, 0x47, 0x23, 0xf5, 0x14, 0x0f, 0xbf, 0x6f, 0x23, 0x12, 0x64, 0x38, 0xa8, 0x87, 0x96,
- 0xa2, 0x3d, 0xfd, 0x52, 0xb0, 0x49, 0x4c, 0xae, 0x09, 0xf0, 0x4e, 0x28, 0x5b, 0xb5, 0xe1, 0x7f,
- 0x10, 0xd1, 0x84, 0x43, 0xde, 0xb7, 0xd3, 0xdb, 0x9b, 0x1f, 0x78, 0x8e, 0xd9, 0x19, 0x11, 0x08,
- 0x7b, 0x3a, 0xd1, 0x97, 0xb4, 0xc7, 0x75, 0x4d, 0x79, 0xf5, 0xf0, 0x6b, 0xfe, 0xc7, 0x54, 0x17,
- 0x37, 0x70, 0x38, 0x92, 0xc3, 0x9c, 0xee, 0xca, 0xfe, 0xf5, 0xb3, 0x26, 0x45, 0xfa, 0x37, 0x80,
- 0x28, 0x5c, 0xda, 0x6e, 0x06, 0x98, 0x75, 0xd6, 0x2c, 0x79, 0xe0, 0xe3, 0x9a, 0x07, 0x3c, 0x57,
- 0xf6, 0xbd, 0x7b, 0xca, 0x91, 0x70, 0xfb, 0x00, 0xc9, 0x5b, 0x6d, 0x09, 0xf8, 0x4f, 0xd5, 0x4a,
- 0x9d, 0x3f, 0x00, 0xfe, 0x4f, 0x59, 0x9f, 0xa1, 0x5b, 0xe2, 0x40, 0x65, 0x8f, 0xba, 0x1a, 0xd6,
- 0x87, 0x68, 0x6d, 0xda, 0x87, 0x78, 0x08, 0xa8, 0x23, 0xdf, 0xdb, 0xa9, 0x85, 0x9d, 0x91, 0xe1,
- 0x77, 0x72, 0xc3, 0x74, 0x55, 0x6a, 0x56, 0xdf, 0x33, 0xf1, 0x15, 0x05, 0x7d, 0xd7, 0x69, 0x96,
- 0xf9, 0x08, 0xa4, 0x4b, 0xd0, 0x11, 0xa2, 0xe2, 0xf6, 0x0a, 0x94, 0x8c, 0x1a, 0x14, 0x52, 0xe8,
- 0xf2, 0xa9, 0x89, 0x23, 0x01, 0x0a, 0xa8, 0xf3, 0xaa, 0x7e, 0x9a, 0x1e, 0x70, 0xb3, 0xaf, 0xf6,
- 0x77, 0xf8, 0xc5, 0x81, 0x6e, 0x2c, 0xbd, 0x2a, 0x6c, 0x13, 0x9e, 0xd1, 0x30, 0xde, 0xe1, 0xd8,
- 0xc7, 0x43, 0xa6, 0x39, 0x6d, 0x80, 0xc1, 0x51, 0x30, 0x30, 0x7e, 0xe5, 0x2b, 0x04, 0x76, 0x5d,
- 0x41, 0x5c, 0x15, 0x11, 0xb9, 0x0d, 0xe9, 0x8b, 0xd3, 0x6e, 0x35, 0x79, 0xd1, 0x69, 0x75, 0xe6,
- 0x08, 0x0c, 0x8e, 0x90, 0x00, 0xa0, 0x4d, 0x78, 0x19, 0xa5, 0x5f, 0x41, 0x38, 0x16, 0xea, 0x1b,
- 0x19, 0xce, 0xba, 0xb8, 0x6e, 0x46, 0x31, 0x9a, 0x38, 0x91, 0xd2, 0xbe, 0x9b, 0x9d, 0xbc, 0x3b,
- 0x75, 0x37, 0x04, 0x95, 0x27, 0x50, 0x95, 0x9a, 0x79, 0x63, 0x36, 0x91, 0xc4, 0x6e, 0x0d, 0x77,
- 0xb7, 0x53, 0xe9, 0x16, 0x01, 0xc6, 0x03, 0x6b, 0x8f, 0xb7, 0xb6, 0x36, 0x01, 0x11, 0x20, 0x87,
- 0x5c, 0x5d, 0x62, 0xbf, 0x2f, 0x7b, 0x05, 0xdd, 0x3a, 0x09, 0x4b, 0xdc, 0x30, 0x8f, 0x38, 0x1e,
- 0xc1, 0xee, 0xd1, 0x0f, 0xe6, 0xe4, 0x95, 0x0a, 0x13, 0x0e, 0x45, 0xf9, 0xf3, 0xcd, 0xee, 0x52,
- 0x38, 0x0e, 0x86, 0x9b, 0xc4, 0x23, 0x2d, 0x49, 0xac, 0x77, 0x9b, 0x48, 0xf0, 0xde, 0x9b, 0x14,
- 0xd0, 0x3f, 0xba, 0x6a, 0x74, 0xb0, 0x9f, 0x52, 0xc9, 0xb0, 0x7e, 0xbe, 0xa5, 0xaf, 0xa9, 0x9b,
- 0x03, 0xc9, 0x30, 0x08, 0x66, 0x41, 0xf8, 0x22, 0x37, 0x69, 0x06, 0x34, 0xd5, 0xc2, 0xc6, 0x0a,
- 0x25, 0x6c, 0xaf, 0xed, 0x72, 0xb1, 0x71, 0xb3, 0xcb, 0xd9, 0x2d, 0xba, 0xb2, 0x13, 0x34, 0xf5,
- 0x09, 0xa3, 0xe5, 0x1a, 0x24, 0xcb, 0x47, 0x28, 0x1e, 0xcf, 0xf9, 0x29, 0x89, 0x22, 0xa9, 0xbf,
- 0x1d, 0x94, 0x03, 0x69, 0x7f, 0xeb, 0xa5, 0x4b, 0x39, 0x59, 0xfa, 0xbd, 0xec, 0x3e, 0xb7, 0x33,
- 0x62, 0x51, 0x65, 0xa9, 0x78, 0x6c, 0xdc, 0xb7, 0xca, 0x7f, 0xfa, 0x54, 0x25, 0x00, 0xe9, 0x9f,
- 0xa6, 0x4b, 0x0e, 0x24, 0x34, 0xee, 0x0f, 0x17, 0x9b, 0x6a, 0xe3, 0xe4, 0xee, 0x4d, 0x83, 0xa4,
- 0x79, 0x75, 0x8c, 0x46, 0x12, 0x6f, 0x28, 0x50, 0xef, 0x1f, 0x70, 0x9c, 0x49, 0x70, 0x7c, 0xd9,
- 0x19, 0x30, 0x43, 0x07, 0x49, 0x1f, 0xba, 0x7f, 0x1b, 0x17, 0xec, 0x01, 0x92, 0xcf, 0xd9, 0x32,
- 0xfa, 0xf2, 0xd9, 0x40, 0xf2, 0xb8, 0xaf, 0xa2, 0x42, 0xeb, 0x11, 0x36, 0xf9, 0x6b, 0x7c, 0x27,
- 0x68, 0x4c, 0xd6, 0x18, 0x76, 0x40, 0x31, 0xaf, 0x76, 0x38, 0x82, 0x97, 0x8b, 0xc5, 0x15, 0x41,
- 0x80, 0xdd, 0xab, 0xf1, 0x67, 0x00, 0x42, 0xfc, 0x37, 0x37, 0xe8, 0x29, 0x39, 0xea, 0x8c, 0x1c,
- 0x48, 0xe6, 0xb0, 0x5d, 0xa3, 0xae, 0x17, 0x6a, 0xe6, 0x5b, 0x5c, 0x71, 0x40, 0xc4, 0x5a, 0x8c,
- 0xee, 0x95, 0x0a, 0x0e, 0xcd, 0x4b, 0xbb, 0x4d, 0x66, 0x81, 0x9a, 0xc7, 0xf6, 0xe8, 0xf7, 0x99,
- 0x2e, 0x77, 0x3f, 0x3a, 0x4d, 0xa9, 0x12, 0xcc, 0x2a, 0x7d, 0xe3, 0xe8, 0x37, 0x6b, 0x9e, 0xd4,
- 0x38, 0x53, 0x30, 0x18, 0xbd, 0xf5, 0xb7, 0x61, 0x59, 0x64, 0xea, 0x9e, 0x55, 0x86, 0xe6, 0x1a,
- 0xce, 0x94, 0xe1, 0x34, 0x82, 0x6b, 0xcf, 0x3b, 0x5f, 0x86, 0x76, 0x74, 0xdf, 0x72, 0xf5, 0xa8,
- 0x08, 0x87, 0x50, 0x27, 0xc2, 0x9a, 0x98, 0x78, 0xe4, 0x09, 0x14, 0xc2, 0x65, 0x4b, 0x7a, 0xc9,
- 0xd9, 0x62, 0x1d, 0xb2, 0xa1, 0xc1, 0xab, 0x7e, 0xa0, 0x08, 0x9b, 0xd7, 0xb6, 0xcd, 0xe0, 0x40,
- 0xf7, 0xc6, 0xea, 0x41, 0xf1, 0xf4, 0x27, 0x93, 0x7e, 0xf6, 0x5f, 0x23, 0x76, 0x79, 0x48, 0x91,
- 0x45, 0x09, 0x08, 0xd8, 0xa2, 0x37, 0x49, 0x49, 0x85, 0x47, 0xa6, 0xdc, 0x21, 0x3d, 0xd0, 0x58,
- 0xac, 0x9e, 0xd2, 0x06, 0x02, 0x28, 0xbb, 0xb8, 0xd7, 0xb4, 0x35, 0x5d, 0x10, 0x95, 0xd6, 0xc8,
- 0x1c, 0xc5, 0x02, 0x8e, 0x57, 0x83, 0x51, 0x28, 0x25, 0xfd, 0x21, 0xd5, 0x3b, 0xe8, 0x22, 0x77,
- 0xe2, 0x99, 0x18, 0x61, 0x85, 0xce, 0x11, 0x70, 0x71, 0x2f, 0x99, 0x6e, 0x35, 0x43, 0xfa, 0x77,
- 0x24, 0xf8, 0x60, 0xb7, 0x06, 0x9c, 0x9a, 0xad, 0x55, 0xe6, 0x13, 0xa2, 0x28, 0x47, 0xb5, 0x17,
- 0x6c, 0xca, 0x9a, 0x97, 0x24, 0x52, 0x8a, 0xcb, 0x93, 0x85, 0x59, 0x52, 0x8a, 0x7a, 0xd6, 0xde,
- 0xc3, 0x10, 0x7e, 0x5d, 0x90, 0xe3, 0xb0, 0x8f, 0x51, 0x29, 0x36, 0xec, 0x9d, 0x7b, 0xd5, 0xed,
- 0x09, 0xd6, 0x23, 0x5b, 0xdc, 0x23, 0x4e, 0xeb, 0x28, 0x69, 0x66, 0xb5, 0x95, 0x05, 0x55, 0x2e,
- 0x5e, 0x2e, 0x90, 0x62, 0x1f, 0xdf, 0x7b, 0x71, 0xe7, 0x49, 0xb9, 0xda, 0x40, 0x59, 0x77, 0xc3,
- 0xde, 0x82, 0x16, 0xb2, 0x37, 0x1d, 0x37, 0x73, 0xae, 0xdd, 0xe0, 0x89, 0x44, 0x3e, 0x0f, 0x30,
- 0x73, 0xb4, 0x70, 0x18, 0xb2, 0x4f, 0xe1, 0x75, 0x97, 0x56, 0x16, 0x21, 0x77, 0x89, 0xb8, 0x13,
- 0x17, 0xf9, 0xdb, 0xee, 0xbe, 0x43, 0x1c, 0xd6, 0x62, 0x74, 0x4f, 0x0d, 0xb7, 0xb1, 0x35, 0x94,
- 0x44, 0x6b, 0x88, 0xf8, 0xd3, 0x00, 0x07, 0x5d, 0x17, 0x97, 0x68, 0x20, 0x22, 0x2d, 0xee, 0xd5,
- 0xf5, 0x55, 0x0d, 0xad, 0xfc, 0x7a, 0xbd, 0xd9, 0xa9, 0xa3, 0xb9, 0xda, 0x78, 0xa5, 0x06, 0x8a,
- 0x1e, 0x9a, 0x4b, 0xf1, 0x6c, 0x14, 0xca, 0x5b, 0x9d, 0x54, 0x46, 0x71, 0xa4, 0xf9, 0x29, 0xa9,
- 0xf6, 0x29, 0x7c, 0xec, 0x3d, 0xc9, 0x2d, 0x8d, 0xa0, 0xb6, 0x5e, 0xc5, 0x5a, 0x74, 0xde, 0xda,
- 0x0f, 0x7e, 0xe6, 0x73, 0x58, 0x2f, 0x5b, 0x51, 0x40, 0xbd, 0xfd, 0x91, 0x9e, 0xa3, 0x71, 0x09,
- 0xef, 0x77, 0xce, 0xc5, 0xd5, 0x6c, 0x87, 0xf2, 0xcd, 0xf0, 0x0b, 0xdc, 0x29, 0xe8, 0x95, 0x55,
- 0x4a, 0x23, 0x03, 0x86, 0x9d, 0x16, 0xfe, 0x97, 0x86, 0xc1, 0xc9, 0x28, 0xf1, 0x0b, 0x98, 0x31,
- 0xe4, 0xea, 0xee, 0xe3, 0xf0, 0xa2, 0x9e, 0x43, 0xbe, 0x2c, 0x46, 0xa1, 0x09, 0x08, 0x26, 0x08,
- 0x6f, 0x50, 0x94, 0x0e, 0x37, 0xb3, 0xce, 0xa3, 0xde, 0x5b, 0xee, 0x33, 0x86, 0x5a, 0x22, 0xa9,
- 0xe6, 0x64, 0x9a, 0xba, 0x8d, 0xf2, 0xb0, 0x9e, 0xc2, 0xc8, 0x04, 0x6d, 0xe8, 0x65, 0xa0, 0x16,
- 0xb0, 0x01, 0x93, 0x60, 0x6d, 0x1c, 0xcf, 0xff, 0x85, 0xde, 0xe4, 0xc1, 0x66, 0x43, 0x0e, 0x77,
- 0xaf, 0xe2, 0xd2, 0xae, 0x31, 0xa2, 0x9e, 0x9c, 0x01, 0x0a, 0x0e, 0xe6, 0x39, 0xa4, 0xe1, 0x8c,
- 0x88, 0xd5, 0x5e, 0x64, 0x7d, 0x0f, 0xed, 0x5e, 0x98, 0xc1, 0x49, 0xdc, 0x62, 0xe4, 0x61, 0xcf,
- 0x1b, 0x1e, 0xea, 0x83, 0x11, 0x42, 0x5d, 0x80, 0x06, 0xcc, 0x0b, 0xa1, 0x53, 0x45, 0xab, 0x6d,
- 0xe9, 0x00, 0x47, 0xf8, 0xda, 0xea, 0x27, 0xc1, 0x6c, 0x03, 0x2b, 0xaf, 0xcd, 0x54, 0xbc, 0x27,
- 0x5b, 0x07, 0xef, 0x6c, 0xfb, 0xce, 0x3a, 0xe0, 0x98, 0x5f, 0x99, 0xb8, 0xb2, 0x08, 0xdd, 0xc6,
- 0xbc, 0x94, 0xb5, 0x56, 0x25, 0x8d, 0x8d, 0x99, 0x24, 0x09, 0x37, 0x3f, 0x21, 0xae, 0x03, 0x69,
- 0x84, 0x73, 0xd9, 0xd9, 0xda, 0x8f, 0xc6, 0x23, 0x95, 0xfa, 0xff, 0xec, 0x91, 0x4b, 0x81, 0x3e,
- 0xbb, 0x2f, 0xc2, 0x7a, 0x3d, 0x65, 0xfc, 0x21, 0xc7, 0xcb, 0xec, 0x47, 0x63, 0x18, 0x33, 0xd1,
- 0x45, 0x5d, 0x72, 0xbe, 0x89, 0xbb, 0x08, 0x41, 0xf3, 0xcc, 0xd6, 0xc7, 0xfa, 0xa6, 0xe1, 0x91,
- 0x42, 0xf1, 0x96, 0xe6, 0x0e, 0x2b, 0x48, 0xfe, 0x5b, 0x09, 0x11, 0x44, 0xab, 0x24, 0x55, 0xef,
- 0x68, 0x8a, 0x3f, 0xc9, 0x9e, 0x13, 0x7a, 0x8b, 0x4b, 0x96, 0x20, 0x3b, 0xbf, 0xcc, 0x8c, 0x55,
- 0xe9, 0xe6, 0x6b, 0x28, 0xa0, 0x88, 0x68, 0x80, 0x66, 0x6e, 0x61, 0xb0, 0xdb, 0x2e, 0xf7, 0x93,
- 0x53, 0x33, 0xdc, 0xb2, 0xfb, 0x00, 0xbe, 0x65, 0x5b, 0x1a, 0x28, 0x9d, 0xcd, 0xb2, 0xb4, 0x25,
- 0xdf, 0x4f, 0x7c, 0xfc, 0x61, 0xd4, 0x2e, 0xcc, 0x50, 0x6a, 0x0c, 0xee, 0xd5, 0x0c, 0x9d, 0x7e,
- 0xbd, 0x4c, 0x03, 0x6b, 0xf4, 0x8d, 0xbf, 0xeb, 0xa3, 0x0e, 0x24, 0x13, 0x6c, 0xc6, 0x3b, 0x1c,
- 0xc2, 0x97, 0x04, 0x3d, 0xb2, 0x11, 0xbf, 0x29, 0x9a, 0x58, 0xd4, 0x56, 0xb4, 0x09, 0xa9, 0x81,
- 0x03, 0x05, 0x62, 0x87, 0x8e, 0x34, 0x5b, 0xd5, 0x06, 0x06, 0x39, 0x1a, 0x9f, 0x04, 0xe8, 0x4a,
- 0xf7, 0x0c, 0x91, 0xeb, 0x81, 0xb8, 0x95, 0x55, 0x2e, 0xa1, 0x69, 0xbb, 0x29, 0x5a, 0xd1, 0xb6,
- 0x39, 0x5c, 0x2a, 0xe9, 0x76, 0x2e, 0x08, 0x48, 0x55, 0x73, 0x60, 0x69, 0xf8, 0x43, 0x39, 0xee,
- 0xe8, 0xc6, 0xf6, 0xd7, 0xdb, 0xf9, 0x65, 0x84, 0x30, 0x1d, 0x75, 0x48, 0x29, 0xd1, 0xf4, 0xbb,
- 0x76, 0x5c, 0x5c, 0x40, 0xbb, 0x46, 0xcb, 0x45, 0xe6, 0x4b, 0x10, 0x37, 0xb9, 0xe9, 0xc7, 0x91,
- 0x3f, 0x0f, 0x9c, 0x02, 0x91, 0x9a, 0x27, 0x18, 0xbd, 0x26, 0xbf, 0x38, 0xc0, 0xf9, 0x14, 0xf5,
- 0xf3, 0xe9, 0xb1, 0x14, 0x56, 0xc0, 0x7b, 0xdd, 0xa1, 0x43, 0x4d, 0xca, 0x68, 0x24, 0xb2, 0x23,
- 0x47, 0xd5, 0x10, 0x7c, 0xb0, 0x51, 0x95, 0x7c, 0x54, 0xc2, 0x4d, 0xce, 0xc0, 0xa0, 0x62, 0xc2,
- 0xa0, 0x8d, 0x52, 0x26, 0xea, 0x8f, 0x36, 0xf5, 0x9f, 0x26, 0x2b, 0x68, 0x20, 0x93, 0xa3, 0x3c,
- 0xdf, 0xf9, 0xa5, 0xff, 0x35, 0x0f, 0x7e, 0xda, 0xc4, 0x5f, 0x5e, 0xca, 0xc6, 0xef, 0x49, 0x78,
- 0x1a, 0xec, 0x6b, 0x18, 0x83, 0x50, 0xa1, 0x88, 0x12, 0xff, 0x92, 0x6d, 0x60, 0xff, 0x21, 0x0e,
- 0x0c, 0xae, 0xbf, 0x3f, 0x82, 0x60, 0x64, 0x07, 0x1b, 0xd9, 0xbb, 0xb9, 0xea, 0x51, 0x87, 0xf4,
- 0x1e, 0xc3, 0x60, 0xba, 0xe1, 0x01, 0x20, 0x30, 0x2b, 0x13, 0xf2, 0x58, 0x9f, 0x3b, 0xde, 0x25,
- 0xb8, 0x7a, 0x9d, 0x47, 0xb6, 0x4c, 0x94, 0xb2, 0xb0, 0x7b, 0x28, 0x0b, 0xa5, 0x80, 0x22, 0x67,
- 0x14, 0x49, 0x9e, 0x86, 0x0b, 0x69, 0xad, 0x1e, 0x27, 0xac, 0x1e, 0x0e, 0x44, 0x85, 0x2a, 0xa9,
- 0x81, 0x9c, 0x35, 0xdf, 0x95, 0xec, 0x12, 0x7d, 0x32, 0x05, 0xfb, 0x72, 0x3f, 0x55, 0x24, 0xc8,
- 0xb4, 0x59, 0xaa, 0x39, 0x36, 0xe4, 0x2b, 0x38, 0x14, 0xdb, 0x37, 0x8c, 0xba, 0x69, 0xce, 0xf0,
- 0x76, 0x8e, 0x8f, 0x99, 0x4b, 0x3d, 0x07, 0x56, 0xaf, 0x96, 0xf2, 0xe1, 0xad, 0x41, 0x97, 0x09,
- 0x52, 0x7c, 0x84, 0xcc, 0xb9, 0x84, 0x61, 0x0c, 0xf6, 0xb8, 0x3f, 0x90, 0x0c, 0xef, 0x2e, 0x6c,
- 0xd9, 0x44, 0x9e, 0x17, 0x64, 0x7d, 0x7f, 0x78, 0xe1, 0x45, 0x63, 0xd3, 0x97, 0xfa, 0xd2, 0x3e,
- 0x70, 0x6b, 0x36, 0x1f, 0x74, 0x6f, 0x27, 0x97, 0x38, 0xb1, 0x20, 0xdc, 0xb3, 0x8a, 0x33, 0x1b,
- 0x62, 0xb1, 0x1a, 0x92, 0x42, 0x55, 0x0e, 0x18, 0xa1, 0xd2, 0xf1, 0xe9, 0xed, 0x03, 0xe9, 0xc9,
- 0xdc, 0xa0, 0x18, 0xd7, 0x7f, 0xcf, 0x8b, 0xef, 0x00, 0x1f, 0x50, 0xac, 0x04, 0x2a, 0x93, 0x4e,
- 0x00, 0xd2, 0x32, 0xe5, 0xb1, 0xc3, 0x6d, 0xe0, 0x57, 0xf5, 0x0e, 0x6d, 0x1c, 0x5f, 0xb7, 0xf6,
- 0xaa, 0xb6, 0xc3, 0x63, 0x7c, 0x34, 0xed, 0x22, 0x9e, 0x61, 0xd7, 0xe0, 0x1c, 0x6c, 0xa7, 0x77,
- 0xd2, 0x5e, 0x99, 0xee, 0xa3, 0x24, 0x00, 0xe3, 0x93, 0x2a, 0x62, 0x4b, 0x99, 0x56, 0xf9, 0xfe,
- 0x9c, 0x70, 0x91, 0x27, 0x6f, 0x62, 0x39, 0xf9, 0xe0, 0x6e, 0xc0, 0x17, 0xe2, 0x6e, 0xed, 0x67,
- 0x18, 0xb3, 0x7b, 0x5f, 0x8f, 0x18, 0x68, 0x8c, 0x29, 0x7b, 0x79, 0x97, 0x73, 0x0d, 0xcd, 0x1b,
- 0xfa, 0x08, 0xab, 0x1f, 0x24, 0x71, 0x37, 0x7f, 0x82, 0x6f, 0x29, 0x89, 0xe1, 0x5b, 0x2c, 0xeb,
- 0x73, 0xfe, 0x55, 0x91, 0x2c, 0x14, 0xac, 0x9a, 0x43, 0x6d, 0xd5, 0x06, 0x1b, 0xdc, 0x9f, 0x90,
- 0x02, 0x6b, 0xf5, 0x6d, 0x8c, 0x3c, 0x04, 0xf0, 0xa7, 0x2d, 0x6a, 0x3a, 0x6b, 0xc7, 0x8d, 0x16,
- 0x78, 0xa4, 0x06, 0x1b, 0x9f, 0x0d, 0x62, 0x6b, 0x81, 0x63, 0xb9, 0x22, 0xd4, 0x2c, 0xfb, 0x70,
- 0xdd, 0x78, 0x46, 0xf0, 0x7b, 0x37, 0x64, 0x5f, 0xf8, 0xfd, 0x9d, 0x3a, 0x4e, 0xb9, 0x56, 0x02,
- 0x0b, 0x3e, 0x19, 0x02, 0x5a, 0x12, 0x14, 0x95, 0x4e, 0x88, 0x58, 0xa1, 0x55, 0xd4, 0xde, 0xae,
- 0x1d, 0x4b, 0xd3, 0x5b, 0x8f, 0xb9, 0x63, 0xfa, 0x3a, 0xe3, 0x5e, 0x76, 0xd6, 0x4b, 0x7e, 0x30,
- 0xce, 0xf7, 0x37, 0xa9, 0x53, 0x3b, 0x61, 0x0c, 0x62, 0x73, 0x85, 0xfa, 0x7b, 0x93, 0x85, 0x75,
- 0x90, 0x9e, 0x15, 0x1d, 0x88, 0x9d, 0x3c, 0x76, 0xa8, 0x9c, 0xe0, 0x3e, 0xda, 0xf3, 0x2c, 0x99,
- 0x98, 0x6a, 0x41, 0x01, 0xd8, 0xb2, 0xdd, 0x43, 0x23, 0x64, 0xd8, 0xa7, 0x27, 0xdf, 0xbc, 0x3d,
- 0xb7, 0xa3, 0x5a, 0xda, 0x6f, 0xdc, 0x0f, 0x30, 0xd1, 0xaa, 0x72, 0x61, 0xde, 0xc6, 0xa2, 0xba,
- 0x9e, 0x01, 0x1b, 0x3f, 0x42, 0x82, 0xb3, 0x0b, 0xe1, 0xf1, 0x63, 0x96, 0xf5, 0x3b, 0x0b, 0xd9,
- 0x14, 0x1d, 0x79, 0x2f, 0x76, 0xf4, 0xaf, 0x0f, 0x4c, 0x3b, 0xe0, 0xe7, 0xb8, 0xe1, 0x9f, 0x9f,
- 0x80, 0x8a, 0xb3, 0x03, 0xe4, 0x90, 0x84, 0x9b, 0x7d, 0xa4, 0x2b, 0x61, 0x76, 0x85, 0x03, 0xd4,
- 0x31, 0xbb, 0xba, 0x94, 0x0e, 0xf5, 0x05, 0xda, 0x83, 0x99, 0x55, 0xfc, 0x1e, 0x86, 0x5e, 0xf9,
- 0x52, 0x66, 0x60, 0x78, 0x04, 0x70, 0xc5, 0x2d, 0x24, 0xd6, 0x1d, 0xcb, 0x05, 0xd6, 0xc1, 0x9d,
- 0xc4, 0xd0, 0x2e, 0xb9, 0x06, 0x9d, 0xb9, 0x11, 0x80, 0x09, 0x5f, 0x57, 0x0b, 0x58, 0xf7, 0x98,
- 0xfe, 0xcb, 0xaf, 0x5c, 0x59, 0xcb, 0xbc, 0x5c, 0x8e, 0xf7, 0x66, 0x2b, 0x69, 0xdf, 0xa3, 0x3d,
- 0xb7, 0xad, 0xd0, 0x1b, 0x2d, 0x77, 0x75, 0xd5, 0x30, 0xaf, 0xd3, 0x05, 0xc6, 0x97, 0xdf, 0x75,
- 0xcd, 0x2c, 0xfa, 0x4b, 0x6a, 0xe5, 0x3e, 0x11, 0xb3, 0xfc, 0x7d, 0xda, 0xd0, 0x2b, 0xa8, 0xd5,
- 0xf9, 0xf4, 0x1a, 0x6b, 0x32, 0xce, 0x94, 0x9d, 0xa2, 0xc0, 0xca, 0x7c, 0x47, 0x30, 0x38, 0x0d,
- 0xca, 0x46, 0xea, 0x8d, 0x3d, 0xe1, 0xf7, 0x29, 0xd5, 0x39, 0x02, 0x92, 0x83, 0x6f, 0xdb, 0x42,
- 0xdd, 0xab, 0xe7, 0x03, 0x5d, 0x34, 0x0f, 0x91, 0x38, 0x7d, 0x46, 0x1c, 0x28, 0xe5, 0x77, 0xc6,
- 0xb5, 0xd8, 0x1b, 0x5a, 0xca, 0xd8, 0x4c, 0xbd, 0xb8, 0x14, 0x5b, 0x1a, 0xdf, 0x17, 0x73, 0x90,
- 0x4b, 0x01, 0xf6, 0x7e, 0xd0, 0x7a, 0x0e, 0xcc, 0x4c, 0x58, 0xfa, 0x41, 0x51, 0xbe, 0x96, 0x2d,
- 0x38, 0xfd, 0x68, 0x3f, 0x4b, 0xad, 0x6f, 0xb4, 0x0e, 0x4f, 0x29, 0xc8, 0xf9, 0x2c, 0x7d, 0xca,
- 0x07, 0xb6, 0x29, 0xc5, 0x04, 0x72, 0xc1, 0x69, 0xc4, 0xee, 0xd4, 0x22, 0x96, 0xb5, 0x1b, 0x0b,
- 0xbe, 0x9e, 0x39, 0x2a, 0xf7, 0x5f, 0x36, 0x7f, 0xeb, 0x75, 0xd4, 0x4b, 0x8b, 0x58, 0xab, 0x61,
- 0x25, 0x4e, 0xc4, 0x56, 0x5e, 0x76, 0x16, 0x9f, 0xcb, 0xee, 0xc7, 0xd9, 0x36, 0xfa, 0x71, 0x14,
- 0x65, 0x2b, 0xe0, 0x34, 0xbb, 0x42, 0xcf, 0x9e, 0xac, 0xa4, 0x17, 0x52, 0x77, 0x5b, 0x92, 0x9b,
- 0xfa, 0xb6, 0x09, 0x53, 0x71, 0x28, 0x70, 0xa2, 0x6d, 0xb8, 0x79, 0x1a, 0x98, 0x82, 0xde, 0x94,
- 0xdb, 0xe6, 0x4d, 0x1c, 0x46, 0x26, 0x7e, 0x33, 0x61, 0x92, 0x24, 0xae, 0x66, 0xcf, 0xa8, 0x62,
- 0xac, 0xd9, 0x96, 0xce, 0xd6, 0xc7, 0xc2, 0x10, 0x16, 0x95, 0x82, 0xab, 0x12, 0x4c, 0x03, 0x14,
- 0x3b, 0x74, 0x0d, 0x01, 0x7a, 0x4a, 0x53, 0x24, 0xec, 0xf1, 0xdb, 0xd6, 0x5a, 0xf0, 0x2c, 0xb5,
- 0x80, 0x8c, 0x37, 0x39, 0x5f, 0x87, 0x65, 0x97, 0x60, 0x47, 0x73, 0x89, 0x4f, 0xb2, 0x35, 0x9c,
- 0xe5, 0x89, 0x47, 0x06, 0x09, 0xd5, 0x81, 0x7b, 0x3e, 0x64, 0xd2, 0xcd, 0xa3, 0xb9, 0x8e, 0x31,
- 0xde, 0x7e, 0xf8, 0xbf, 0x8a, 0x58, 0x5c, 0xf1, 0xd6, 0x3c, 0xd4, 0x0f, 0x6a, 0xbd, 0x95, 0xc2,
- 0x51, 0x7a, 0x8f, 0x57, 0x3a, 0x72, 0x2a, 0x00, 0xcd, 0x5e, 0xf3, 0x94, 0x99, 0x82, 0x82, 0x4b,
- 0x87, 0x8f, 0xee, 0xbe, 0xb7, 0xf2, 0xca, 0xff, 0x0a, 0xd6, 0x98, 0x12, 0xd6, 0xb4, 0x5f, 0x57,
- 0xb4, 0xd3, 0xc0, 0xa4, 0xc3, 0xd2, 0xfe, 0x74, 0x65, 0x82, 0xcc, 0x2e, 0xad, 0x66, 0x4c, 0x53,
- 0x3d, 0x17, 0xcd, 0xf7, 0xb1, 0x98, 0x9f, 0x9a, 0xd1, 0xa9, 0x01, 0x09, 0x9f, 0x3f, 0x9c, 0x97,
- 0x1e, 0xf6, 0xd8, 0x6b, 0xf8, 0x50, 0x82, 0x5d, 0xfe, 0x77, 0x05, 0x49, 0xaa, 0xa8, 0xcd, 0x93,
- 0xb1, 0x2b, 0xb5, 0xeb, 0xd0, 0x08, 0x11, 0x0c, 0x77, 0xcb, 0x8d, 0xc6, 0xfa, 0x16, 0x42, 0xbd,
- 0x00, 0xae, 0x16, 0x9b, 0xd8, 0x40, 0xc8, 0xca, 0xcb, 0x20, 0x7a, 0x37, 0xb4, 0x01, 0x09, 0x79,
- 0xc5, 0xb9, 0x73, 0xd8, 0xe1, 0x3b, 0x65, 0x7c, 0x8e, 0x30, 0xc3, 0xef, 0x25, 0x4e, 0xc4, 0x83,
- 0x95, 0x95, 0x73, 0x97, 0xd9, 0x4f, 0x63, 0xed, 0x2a, 0x9d, 0x2f, 0xbf, 0x42, 0x4f, 0xd5, 0xfe,
- 0x93, 0x18, 0xff, 0x42, 0xcd, 0x4f, 0x0d, 0x99, 0x33, 0x31, 0x0f, 0x19, 0x36, 0xfb, 0x50, 0x17,
- 0x1e, 0x1f, 0xb6, 0xe9, 0x6e, 0x51, 0x76, 0x41, 0x18, 0x5e, 0xea, 0x6c, 0x9a, 0x42, 0xfa, 0xbf,
- 0x68, 0x50, 0x07, 0xc7, 0xf9, 0xef, 0x3e, 0x4e, 0x34, 0xb4, 0x3e, 0xe5, 0x69, 0xc8, 0xbb, 0x98,
- 0xd8, 0xcc, 0x9a, 0x10, 0xc0, 0x4e, 0x62, 0x40, 0x8b, 0x03, 0xf4, 0xc1, 0x7b, 0x62, 0xdc, 0x53,
- 0xa6, 0xad, 0xe4, 0x91, 0xf5, 0xb3, 0xa3, 0xf8, 0x84, 0xa7, 0x25, 0x19, 0x44, 0x68, 0xbc, 0x7b,
- 0x4e, 0x05, 0x6b, 0x7e, 0x3e, 0xb4, 0x8b, 0xea, 0x4d, 0x3b, 0x71, 0xe2, 0x06, 0xf3, 0xcb, 0xda,
- 0x52, 0xae, 0xa5, 0x44, 0x8e, 0x7e, 0x78, 0xbe, 0x3c, 0xa9, 0x57, 0xaf, 0x47, 0x06, 0xf5, 0xf2,
- 0x8f, 0xe3, 0x5f, 0xbe, 0x9e, 0x1b, 0x6f, 0xfc, 0xbf, 0xc1, 0x82, 0x45, 0x85, 0xca, 0x08, 0xa6,
- 0xd1, 0xfe, 0x9f, 0xc2, 0x37, 0x31, 0x6a, 0x67, 0x2c, 0x4d, 0x45, 0x95, 0xba, 0xca, 0x0b, 0xdf,
- 0x81, 0xf0, 0x68, 0x32, 0xa0, 0x6c, 0xc0, 0x92, 0x87, 0x3d, 0x85, 0xe4, 0x81, 0xe2, 0xd3, 0x80,
- 0x0c, 0x3b, 0xb0, 0xb9, 0x45, 0x6e, 0x0e, 0xdb, 0xc0, 0xcf, 0x48, 0xf7, 0x04, 0xb3, 0x54, 0xb7,
- 0x71, 0xf9, 0x2d, 0xe2, 0xf2, 0xea, 0x5e, 0xa1, 0xe7, 0x05, 0x92, 0xe2, 0xfa, 0xe7, 0x9b, 0xea,
- 0x37, 0xb3, 0x55, 0xbf, 0xec, 0xd8, 0x61, 0xa8, 0x2a, 0x76, 0x54, 0x45, 0x0c, 0xf3, 0xc1, 0xb5,
- 0xf5, 0xc5, 0xf9, 0x00, 0x4b, 0xd3, 0x47, 0xf4, 0xa8, 0xe8, 0x0c, 0x77, 0x85, 0xe5, 0xc3, 0x69,
- 0xed, 0xc3, 0x30, 0xaf, 0xfd, 0x0b, 0x54, 0x46, 0x88, 0x1c, 0x83, 0x76, 0xc4, 0x57, 0xa8, 0x8e,
- 0x51, 0xc2, 0xb2, 0x76, 0x08, 0x23, 0x2d, 0x4e, 0x29, 0xae, 0x0f, 0xb4, 0x1f, 0x3a, 0x78, 0x3c,
- 0x8b, 0x73, 0x7d, 0x30, 0xb0, 0x75, 0x3e, 0xe0, 0x1a, 0x85, 0x65, 0xa3, 0x21, 0xb9, 0x53, 0x04,
- 0xbd, 0xfb, 0x20, 0x31, 0xfe, 0xbd, 0xf5, 0x55, 0x2c, 0xee, 0x1f, 0xab, 0xe6, 0x50, 0xdc, 0x3d,
- 0x6e, 0x31, 0x4f, 0xcb, 0xca, 0x3a, 0x4d, 0x19, 0x7b, 0x3b, 0xae, 0xd8, 0xf7, 0xfb, 0xa5, 0x6d,
- 0x92, 0x30, 0x26, 0x00, 0x02, 0xda, 0xd0, 0xd8, 0x61, 0x06, 0x81, 0x4e, 0xf9, 0x66, 0x60, 0x0d,
- 0x48, 0x6e, 0x58, 0x08, 0xdb, 0xfb, 0xc3, 0x39, 0x5f, 0x90, 0xbf, 0x51, 0xb5, 0x37, 0x9f, 0xc2,
- 0x87, 0x63, 0xb8, 0x39, 0x46, 0x6a, 0xdf, 0x3d, 0x48, 0x02, 0xff, 0x01, 0x24, 0x49, 0xf8, 0x5a,
- 0x52, 0xbb, 0xfd, 0x56, 0xfa, 0x00, 0x11, 0x97, 0xbb, 0x88, 0xba, 0x2b, 0x54, 0x00, 0xd9, 0xc6,
- 0x78, 0x93, 0x3f, 0xab, 0xfa, 0x56, 0x68, 0x5d, 0x73, 0x2b, 0xc7, 0x90, 0xad, 0x51, 0x19, 0x82,
- 0x02, 0x42, 0x66, 0x10, 0x40, 0x07, 0x99, 0x87, 0x2f, 0x9c, 0x1c, 0xe6, 0x39, 0x9d, 0x84, 0xab,
- 0x08, 0xbc, 0xbf, 0x44, 0x17, 0xbe, 0x41, 0x83, 0x9b, 0xb0, 0x36, 0x15, 0xe1, 0x9d, 0xfb, 0x8a,
- 0x87, 0x7a, 0x6f, 0xcc, 0x46, 0x0a, 0xb7, 0xbb, 0x1d, 0x8f, 0xdd, 0xa4, 0x8b, 0xb3, 0x0e, 0x78,
- 0x7f, 0x89, 0xd5, 0x49, 0x81, 0xe7, 0x5a, 0x09, 0x5b, 0x5b, 0x98, 0xf2, 0x65, 0xfc, 0x78, 0x09,
- 0xa0, 0xe3, 0xd7, 0x66, 0xa5, 0xaf, 0xd5, 0x8e, 0x1c, 0x80, 0x43, 0x56, 0x12, 0x9a, 0x03, 0x72,
- 0x5c, 0xcc, 0x82, 0x50, 0xf7, 0x53, 0x97, 0xda, 0xfc, 0xf0, 0x96, 0xda, 0xec, 0x10, 0x57, 0xc2,
- 0xc4, 0x02, 0x06, 0xdb, 0x2d, 0xe6, 0x96, 0x29, 0x0b, 0x04, 0x56, 0xf9, 0x39, 0x02, 0x37, 0x3c,
- 0x65, 0x9a, 0x76, 0xa1, 0x0b, 0x1c, 0xa3, 0xae, 0x7c, 0xae, 0xb3, 0x68, 0x5c, 0x1b, 0x2f, 0xaf,
- 0xfe, 0x9c, 0xb9, 0x64, 0x3d, 0x35, 0x84, 0x2d, 0x26, 0x48, 0xa8, 0x4d, 0x0a, 0x57, 0xec, 0x15,
- 0x2f, 0x7b, 0x8d, 0x1a, 0x6d, 0xb4, 0x72, 0xb1, 0xf3, 0xfa, 0x97, 0x9f, 0x3a, 0x8a, 0xe6, 0x5e,
- 0xf1, 0xc4, 0xcc, 0x6e, 0x75, 0x25, 0x5b, 0x4d, 0x6b, 0xac, 0x47, 0x30, 0xa5, 0x64, 0x51, 0xf1,
- 0x87, 0xf0, 0x85, 0x54, 0x82, 0x23, 0x3e, 0xf8, 0x32, 0xbd, 0x11, 0x17, 0x8a, 0xb3, 0x49, 0xac,
- 0xec, 0x6f, 0x59, 0x7e, 0x5f, 0xd0, 0xcd, 0x3f, 0xa8, 0x1e, 0xa8, 0xd6, 0xb8, 0xda, 0x92, 0x03,
- 0x4f, 0xc8, 0x12, 0x59, 0x93, 0x8c, 0xb3, 0x48, 0x8a, 0x80, 0xef, 0xbe, 0xb9, 0xd4, 0xfa, 0x90,
- 0xd9, 0xf2, 0x1c, 0x7a, 0x3e, 0x73, 0x99, 0x33, 0xaf, 0x6a, 0x79, 0x03, 0xf2, 0x02, 0x5b, 0x1a,
- 0x4f, 0xf7, 0x09, 0x9a, 0x7a, 0x07, 0xd4, 0xe8, 0x88, 0xc1, 0x5b, 0xf0, 0x05, 0xd0, 0x30, 0xab,
- 0x6c, 0x18, 0x6a, 0x3e, 0x8d, 0x1e, 0xdd, 0x2d, 0xdb, 0x23, 0xa8, 0xdb, 0x7c, 0xaa, 0xd1, 0xd6,
- 0xe3, 0xc6, 0xaa, 0xf7, 0x34, 0xad, 0x09, 0xba, 0xf2, 0xa7, 0x16, 0xed, 0x88, 0x7c, 0xe4, 0xe4,
- 0xcc, 0x99, 0x7e, 0xa1, 0xb4, 0x8f, 0xaf, 0x35, 0x11, 0x01, 0x42, 0xf2, 0x19, 0x37, 0x51, 0x18,
- 0x25, 0xc2, 0x35, 0x43, 0xde, 0x85, 0xd8, 0x43, 0x41, 0x16, 0x59, 0x28, 0x1e, 0xc8, 0x6f, 0xd2,
- 0xba, 0xbf, 0x18, 0x52, 0x9c, 0x13, 0x9c, 0x15, 0xe9, 0xbc, 0xd7, 0x21, 0xfa, 0x59, 0x9a, 0x60,
- 0x1e, 0xec, 0x64, 0xd9, 0x60, 0x8d, 0x31, 0x8c, 0xd6, 0x1e, 0x7d, 0xc4, 0xa8, 0x81, 0x76, 0x41,
- 0xa2, 0x41, 0x37, 0x04, 0xe4, 0x87, 0xc5, 0xe4, 0x58, 0x01, 0x37, 0x93, 0x9a, 0x76, 0xbd, 0x20,
- 0x86, 0xc9, 0xb7, 0x52, 0xb6, 0xd3, 0x59, 0x3f, 0x9f, 0xc8, 0xea, 0xbb, 0x9a, 0x71, 0x34, 0x36,
- 0x26, 0x83, 0xd2, 0xab, 0xb6, 0x6b, 0x45, 0x58, 0x0b, 0x73, 0xfd, 0x8d, 0x50, 0x0d, 0x81, 0x12,
- 0x10, 0x5a, 0xdf, 0x2c, 0x53, 0x6b, 0x48, 0x18, 0x60, 0x10, 0x69, 0xcd, 0x73, 0x52, 0x40, 0xd6,
- 0x14, 0x69, 0x68, 0x68, 0x8e, 0xe3, 0x01, 0x54, 0x3c, 0x8e, 0x8b, 0xe0, 0x77, 0x77, 0xdc, 0x5f,
- 0xca, 0x01, 0xc6, 0x08, 0x0b, 0xbf, 0x16, 0x5d, 0x71, 0x8f, 0x3e, 0xf7, 0x8e, 0x8f, 0x1f, 0x66,
- 0xcf, 0x49, 0xb3, 0xe8, 0x55, 0x00, 0x8d, 0x86, 0xcb, 0x3f, 0x2b, 0x03, 0x61, 0xde, 0x10, 0x4e,
- 0x7b, 0x24, 0xb2, 0x08, 0xec, 0x0f, 0xe6, 0xcd, 0x9c, 0xa1, 0xa4, 0x98, 0xe0, 0x0d, 0xcd, 0x20,
- 0xfa, 0x3a, 0x83, 0xb5, 0xec, 0x4c, 0x69, 0xa6, 0xfa, 0x2d, 0xe6, 0x76, 0xda, 0x8c, 0xc2, 0xe2,
- 0x04, 0x75, 0xfd, 0xb3, 0xdc, 0x8d, 0x93, 0x64, 0xd1, 0xa3, 0xcc, 0xb0, 0xf5, 0xbd, 0x0a, 0xaa,
- 0xbe, 0x0e, 0xe8, 0x19, 0x01, 0xb8, 0xc2, 0x4f, 0x5e, 0x78, 0x2f, 0x1a, 0x30, 0xf0, 0xb3, 0x8a,
- 0x5d, 0x9d, 0xc5, 0xac, 0xf4, 0x7b, 0x0d, 0xe4, 0xd4, 0x96, 0xea, 0xca, 0x4b, 0x85, 0x81, 0x3a,
- 0x0d, 0xe9, 0x0b, 0x37, 0x56, 0x9d, 0x0e, 0xd7, 0x02, 0x67, 0x87, 0x03, 0x09, 0xfd, 0x1b, 0x67,
- 0xd5, 0xe4, 0x69, 0xcc, 0xfc, 0xc3, 0xbf, 0x9a, 0x6d, 0x93, 0xc4, 0x45, 0x9c, 0xf8, 0xd9, 0x03,
- 0xad, 0x65, 0x70, 0x82, 0x49, 0xd3, 0xac, 0xa7, 0x8a, 0xf3, 0xda, 0x01, 0xbd, 0x26, 0xb3, 0xa4,
- 0xd7, 0x8a, 0x91, 0xbf, 0xea, 0x8b, 0x2b, 0xb0, 0x6c, 0xd8, 0x84, 0x7b, 0x4b, 0xf4, 0x2c, 0xbc,
- 0x45, 0x30, 0xe1, 0xf0, 0xbf, 0xfc, 0x4c, 0x81, 0xfc, 0x07, 0xa7, 0xea, 0x34, 0xcb, 0x15, 0x55,
- 0xa9, 0x9e, 0x70, 0x4f, 0xbb, 0xd8, 0x1b, 0xd6, 0x1b, 0x2d, 0x4e, 0x20, 0x72, 0x44, 0x00, 0x36,
- 0x1f, 0x23, 0x06, 0x40, 0x7e, 0xde, 0x3e, 0xd4, 0x61, 0x6f, 0x12, 0x56, 0x04, 0xd7, 0x58, 0x2f,
- 0x8d, 0x66, 0x0b, 0xff, 0xd2, 0x23, 0x5c, 0xf4, 0xd4, 0xa3, 0x58, 0xd0, 0x6d, 0xf6, 0x98, 0xab,
- 0xc5, 0x53, 0xea, 0xc4, 0x37, 0x47, 0xc3, 0x4a, 0x8d, 0xc6, 0x4c, 0x19, 0x5d, 0x17, 0xb4, 0x39,
- 0x71, 0xe9, 0x99, 0x82, 0xe6, 0x5b, 0xc5, 0x90, 0x33, 0xf7, 0x5b, 0x8d, 0x98, 0x4c, 0xcd, 0x7a,
- 0x6b, 0xd8, 0xb9, 0x8c, 0x11, 0x34, 0x8d, 0xc0, 0x9a, 0x57, 0x2a, 0x12, 0xd5, 0x7f, 0x3f, 0x94,
- 0x70, 0x93, 0x1a, 0x11, 0xe9, 0xf3, 0x99, 0x4f, 0x10, 0x38, 0xc7, 0xc2, 0xec, 0x62, 0xac, 0x59,
- 0x90, 0x3a, 0x85, 0x1d, 0xeb, 0xee, 0xa3, 0x90, 0x59, 0xfd, 0x0a, 0x07, 0x0a, 0xc7, 0x32, 0x2d,
- 0x11, 0x18, 0x53, 0x70, 0x80, 0x59, 0x59, 0x51, 0x33, 0xd8, 0x29, 0x85, 0xf4, 0x09, 0xf6, 0x76,
- 0x1e, 0x49, 0xa6, 0x79, 0xc1, 0x2c, 0xae, 0xa6, 0x54, 0xbe, 0xf6, 0x54, 0xb1, 0x95, 0x39, 0x97,
- 0xeb, 0xdc, 0xb2, 0xff, 0x99, 0x19, 0x9a, 0x9b, 0x0e, 0xad, 0x0e, 0x3f, 0xbf, 0xe0, 0x39, 0x8e,
- 0x27, 0x37, 0x1c, 0xdc, 0x86, 0x20, 0x1f, 0x21, 0xd5, 0x0e, 0xd6, 0xbc, 0x45, 0x3e, 0x1d, 0x33,
- 0x3b, 0x15, 0x35, 0xf9, 0x52, 0x98, 0x6f, 0x9a, 0x44, 0x25, 0x01, 0x6b, 0x3d, 0x47, 0x3b, 0x11,
- 0x35, 0x0e, 0x2a, 0xb5, 0x4e, 0xb3, 0xc9, 0x24, 0xe5, 0xae, 0x5b, 0x0e, 0x5f, 0x6a, 0x85, 0x89,
- 0xe5, 0x94, 0xd1, 0x74, 0x08, 0x70, 0x8b, 0xbe, 0x4d, 0xb8, 0x77, 0x4c, 0xa3, 0x14, 0x04, 0x09,
- 0xfe, 0x17, 0x0a, 0xca, 0xb0, 0x9a, 0x5d, 0x63, 0x01, 0xd0, 0xf3, 0xe9, 0x3d, 0xde, 0xaf, 0x0b,
- 0x31, 0x13, 0x61, 0x7a, 0x99, 0xf7, 0x00, 0x17, 0xb0, 0x3a, 0xfc, 0x27, 0x62, 0xfe, 0xd1, 0x36,
- 0x87, 0xb5, 0xfe, 0xd2, 0xad, 0xff, 0xfd, 0xfb, 0xb5, 0x38, 0x8b, 0xca, 0x64, 0xdc, 0x55, 0xb5,
- 0x4e, 0xed, 0x07, 0x07, 0x97, 0x13, 0x6b, 0xa1, 0x33, 0x42, 0x95, 0xb2, 0xaa, 0x0b, 0xf9, 0x1d,
- 0x94, 0x86, 0x37, 0x17, 0xe4, 0x7a, 0x63, 0xe8, 0x99, 0x5b, 0xe9, 0xfc, 0x30, 0x6e, 0x26, 0xed,
- 0x21, 0xd2, 0x0a, 0x28, 0xe5, 0xa0, 0xd7, 0x64, 0x02, 0x5e, 0xb1, 0x3a, 0x40, 0x4d, 0x2c, 0x2b,
- 0x4e, 0xc9, 0xbe, 0xf3, 0xe6, 0x91, 0x34, 0xe6, 0x71, 0xd5, 0xce, 0xdb, 0x47, 0x40, 0xbd, 0x80,
- 0x80, 0x48, 0x9b, 0xaf, 0x81, 0xf4, 0x83, 0x3f, 0x8e, 0x3c, 0x49, 0xf6, 0x29, 0x0c, 0x17, 0x91,
- 0xf2, 0x8f, 0x83, 0xfb, 0xb6, 0x04, 0x57, 0x13, 0x2f, 0x59, 0xa1, 0x7b, 0x72, 0xd4, 0x6c, 0x84,
- 0x41, 0x36, 0x86, 0x9e, 0x56, 0x7a, 0x73, 0x59, 0x54, 0x47, 0x8c, 0x85, 0x3f, 0x8d, 0x3a, 0xcc,
- 0x1b, 0x0b, 0x97, 0x26, 0x7a, 0x53, 0x09, 0x05, 0x37, 0xa1, 0x6d, 0x36, 0x62, 0xe9, 0x43, 0xb1,
- 0xf3, 0xe3, 0xb1, 0xc0, 0x80, 0xf7, 0x2e, 0xae, 0x49, 0x7a, 0xe6, 0xba, 0x1b, 0x42, 0x87, 0x5c,
- 0xc3, 0xae, 0x2c, 0xd0, 0xd2, 0x98, 0x77, 0x43, 0xd1, 0x81, 0x26, 0x9a, 0xe2, 0xbf, 0xf4, 0x6f,
- 0xee, 0x24, 0x52, 0xfb, 0x1f, 0x6a, 0x1f, 0x21, 0xef, 0xf0, 0xc6, 0x02, 0x85, 0xde, 0x1a, 0x4d,
- 0x13, 0xff, 0xa1, 0x58, 0x43, 0x79, 0xb7, 0xc9, 0x45, 0x51, 0x3f, 0x90, 0xb6, 0x76, 0xbb, 0xfb,
- 0x51, 0x8e, 0x37, 0xab, 0x13, 0x36, 0x84, 0x7b, 0xea, 0xea, 0x68, 0x49, 0xd7, 0x5b, 0x42, 0x64,
- 0x09, 0x76, 0x7b, 0x6e, 0xe6, 0x93, 0xd3, 0x27, 0x37, 0xce, 0x2f, 0xd7, 0x3b, 0x1e, 0xf0, 0xd2,
- 0x15, 0xb0, 0xc9, 0xb3, 0x09, 0xef, 0xfe, 0x60, 0xa5, 0x79, 0xb5, 0xb6, 0x30, 0x85, 0x0e, 0xcc,
- 0xbb, 0x23, 0x53, 0x58, 0x28, 0xf5, 0x66, 0xe7, 0xed, 0x2a, 0x0e, 0x8e, 0xdd, 0x23, 0x0d, 0x36,
- 0x84, 0xf3, 0xbe, 0x75, 0xe9, 0xf7, 0x47, 0x07, 0xf4, 0x39, 0x7b, 0x57, 0xe7, 0x1d, 0x94, 0xff,
- 0xe7, 0xe4, 0x9b, 0x91, 0x3d, 0x6e, 0xba, 0x28, 0xca, 0x07, 0xbb, 0xc9, 0xb1, 0x84, 0x7c, 0x6a,
- 0x50, 0x97, 0xf1, 0xf7, 0x22, 0xa7, 0xa3, 0x36, 0x28, 0xe9, 0x3a, 0x60, 0x30, 0x84, 0x73, 0xe8,
- 0x60, 0xbf, 0x26, 0xac, 0x57, 0xa9, 0xab, 0xd2, 0xb1, 0x3f, 0xff, 0xfc, 0x33, 0xe0, 0x8d
-};
-
-fastimage_t bfin_logo = {
-		DEF_BFIN_LOGO_DATA,
-		DEF_BFIN_LOGO_WIDTH,
-		DEF_BFIN_LOGO_HEIGHT,
-		DEF_BFIN_LOGO_BPP,
-		DEF_BFIN_LOGO_PIXEL_SIZE,
-		DEF_BFIN_LOGO_SIZE
-};
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
deleted file mode 100644
index a1462bd..0000000
--- a/arch/blackfin/include/asm/bitops.h
+++ /dev/null
@@ -1,358 +0,0 @@
-/*
- * U-Boot - bitops.h Routines for bit operations
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _BLACKFIN_BITOPS_H
-#define _BLACKFIN_BITOPS_H
-
-/*
- * Copyright 1992, Linus Torvalds.
- */
-
-#include <asm/byteorder.h>
-#include <asm/system.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/__ffs.h>
-
-#ifdef __KERNEL__
-/*
- * Function prototypes to keep gcc -Wall happy
- */
-
-/*
- * The __ functions are not atomic
- */
-
-/*
- * ffz = Find First Zero in word. Undefined if no zero exists,
- * so code should check against ~0UL first..
- */
-static __inline__ unsigned long ffz(unsigned long word)
-{
-	unsigned long result = 0;
-
-	while (word & 1) {
-		result++;
-		word >>= 1;
-	}
-	return result;
-}
-
-static __inline__ void set_bit(int nr, volatile void *addr)
-{
-	int *a = (int *)addr;
-	int mask;
-	unsigned long flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	local_irq_save(flags);
-	*a |= mask;
-	local_irq_restore(flags);
-}
-
-static __inline__ void __set_bit(int nr, volatile void *addr)
-{
-	int *a = (int *)addr;
-	int mask;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	*a |= mask;
-}
-#define PLATFORM__SET_BIT
-
-/*
- * clear_bit() doesn't provide any barrier for the compiler.
- */
-#define smp_mb__before_clear_bit()	barrier()
-#define smp_mb__after_clear_bit()	barrier()
-
-static __inline__ void clear_bit(int nr, volatile void *addr)
-{
-	int *a = (int *)addr;
-	int mask;
-	unsigned long flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	local_irq_save(flags);
-	*a &= ~mask;
-	local_irq_restore(flags);
-}
-
-static __inline__ void change_bit(int nr, volatile void *addr)
-{
-	int mask, flags;
-	unsigned long *ADDR = (unsigned long *)addr;
-
-	ADDR += nr >> 5;
-	mask = 1 << (nr & 31);
-	local_irq_save(flags);
-	*ADDR ^= mask;
-	local_irq_restore(flags);
-}
-
-static __inline__ void __change_bit(int nr, volatile void *addr)
-{
-	int mask;
-	unsigned long *ADDR = (unsigned long *)addr;
-
-	ADDR += nr >> 5;
-	mask = 1 << (nr & 31);
-	*ADDR ^= mask;
-}
-
-static __inline__ int test_and_set_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *)addr;
-	unsigned long flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	local_irq_save(flags);
-	retval = (mask & *a) != 0;
-	*a |= mask;
-	local_irq_restore(flags);
-
-	return retval;
-}
-
-static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *)addr;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	retval = (mask & *a) != 0;
-	*a |= mask;
-	return retval;
-}
-
-static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *)addr;
-	unsigned long flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	local_irq_save(flags);
-	retval = (mask & *a) != 0;
-	*a &= ~mask;
-	local_irq_restore(flags);
-
-	return retval;
-}
-
-static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *)addr;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	retval = (mask & *a) != 0;
-	*a &= ~mask;
-	return retval;
-}
-
-static __inline__ int test_and_change_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *)addr;
-	unsigned long flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	local_irq_save(flags);
-	retval = (mask & *a) != 0;
-	*a ^= mask;
-	local_irq_restore(flags);
-
-	return retval;
-}
-
-static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *)addr;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	retval = (mask & *a) != 0;
-	*a ^= mask;
-	return retval;
-}
-
-/*
- * This routine doesn't need to be atomic.
- */
-static __inline__ int __constant_test_bit(int nr, const volatile void *addr)
-{
-	return ((1UL << (nr & 31)) &
-		(((const volatile unsigned int *)addr)[nr >> 5])) != 0;
-}
-
-static __inline__ int __test_bit(int nr, volatile void *addr)
-{
-	int *a = (int *)addr;
-	int mask;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	return ((mask & *a) != 0);
-}
-
-#define	test_bit(nr,addr) \
-(__builtin_constant_p(nr) ? \
- __constant_test_bit((nr),(addr)) : \
- __test_bit((nr),(addr)))
-
-#define	find_first_zero_bit(addr, size) \
-	find_next_zero_bit((addr), (size), 0)
-
-static __inline__ int find_next_zero_bit(void *addr, int size, int offset)
-{
-	unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
-	unsigned long result = offset & ~31UL;
-	unsigned long tmp;
-
-	if (offset >= size)
-		return size;
-	size -= result;
-	offset &= 31UL;
-	if (offset) {
-		tmp = *(p++);
-		tmp |= ~0UL >> (32 - offset);
-		if (size < 32)
-			goto found_first;
-		if (~tmp)
-			goto found_middle;
-		size -= 32;
-		result += 32;
-	}
-	while (size & ~31UL) {
-		if (~(tmp = *(p++)))
-			goto found_middle;
-		result += 32;
-		size -= 32;
-	}
-	if (!size)
-		return result;
-	tmp = *p;
-
-      found_first:
-	tmp |= ~0UL >> size;
-      found_middle:
-	return result + ffz(tmp);
-}
-
-/*
- * hweightN: returns the hamming weight (i.e. the number
- * of bits set) of a N-bit word
- */
-
-#define hweight32(x)	generic_hweight32(x)
-#define hweight16(x)	generic_hweight16(x)
-#define hweight8(x)	generic_hweight8(x)
-
-static __inline__ int ext2_set_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	unsigned long flags;
-	volatile unsigned char *ADDR = (unsigned char *)addr;
-
-	ADDR += nr >> 3;
-	mask = 1 << (nr & 0x07);
-	local_irq_save(flags);
-	retval = (mask & *ADDR) != 0;
-	*ADDR |= mask;
-	local_irq_restore(flags);
-	return retval;
-}
-
-static __inline__ int ext2_clear_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	unsigned long flags;
-	volatile unsigned char *ADDR = (unsigned char *)addr;
-
-	ADDR += nr >> 3;
-	mask = 1 << (nr & 0x07);
-	local_irq_save(flags);
-	retval = (mask & *ADDR) != 0;
-	*ADDR &= ~mask;
-	local_irq_restore(flags);
-	return retval;
-}
-
-static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
-{
-	int mask;
-	const volatile unsigned char *ADDR = (const unsigned char *)addr;
-
-	ADDR += nr >> 3;
-	mask = 1 << (nr & 0x07);
-	return ((mask & *ADDR) != 0);
-}
-
-#define ext2_find_first_zero_bit(addr, size) \
-	ext2_find_next_zero_bit((addr), (size), 0)
-
-static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
-							unsigned long size,
-							unsigned long offset)
-{
-	unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
-	unsigned long result = offset & ~31UL;
-	unsigned long tmp;
-
-	if (offset >= size)
-		return size;
-	size -= result;
-	offset &= 31UL;
-	if (offset) {
-		tmp = *(p++);
-		tmp |= ~0UL >> (32 - offset);
-		if (size < 32)
-			goto found_first;
-		if (~tmp)
-			goto found_middle;
-		size -= 32;
-		result += 32;
-	}
-	while (size & ~31UL) {
-		if (~(tmp = *(p++)))
-			goto found_middle;
-		result += 32;
-		size -= 32;
-	}
-	if (!size)
-		return result;
-	tmp = *p;
-
-      found_first:
-	tmp |= ~0UL >> size;
-      found_middle:
-	return result + ffz(tmp);
-}
-
-/* Bitmap functions for the minix filesystem. */
-#define minix_test_and_set_bit(nr,addr)		test_and_set_bit(nr,addr)
-#define minix_set_bit(nr,addr)			set_bit(nr,addr)
-#define minix_test_and_clear_bit(nr,addr)	test_and_clear_bit(nr,addr)
-#define minix_test_bit(nr,addr)			test_bit(nr,addr)
-#define minix_find_first_zero_bit(addr,size)	find_first_zero_bit(addr,size)
-
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
deleted file mode 100644
index 204d02b..0000000
--- a/arch/blackfin/include/asm/blackfin.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __MACH_GLOB_BLACKFIN__
-#define __MACH_GLOB_BLACKFIN__
-
-#include "blackfin_def.h"
-#ifndef __ASSEMBLY__
-#include "blackfin_cdef.h"
-#endif
-#include "blackfin_local.h"
-
-#endif /* __MACH_GLOB_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_cdef.h b/arch/blackfin/include/asm/blackfin_cdef.h
deleted file mode 100644
index 8608711..0000000
--- a/arch/blackfin/include/asm/blackfin_cdef.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __MACH_CDEF_BLACKFIN__
-#define __MACH_CDEF_BLACKFIN__
-
-#ifdef __ADSPBF504__
-# include "mach-bf506/BF504_cdef.h"
-#endif
-#ifdef __ADSPBF506__
-# include "mach-bf506/BF506_cdef.h"
-#endif
-#ifdef __ADSPBF512__
-# include "mach-bf518/BF512_cdef.h"
-#endif
-#ifdef __ADSPBF514__
-# include "mach-bf518/BF514_cdef.h"
-#endif
-#ifdef __ADSPBF516__
-# include "mach-bf518/BF516_cdef.h"
-#endif
-#ifdef __ADSPBF518__
-# include "mach-bf518/BF518_cdef.h"
-#endif
-#ifdef __ADSPBF522__
-# include "mach-bf527/BF522_cdef.h"
-#endif
-#ifdef __ADSPBF523__
-# include "mach-bf527/BF523_cdef.h"
-#endif
-#ifdef __ADSPBF524__
-# include "mach-bf527/BF524_cdef.h"
-#endif
-#ifdef __ADSPBF525__
-# include "mach-bf527/BF525_cdef.h"
-#endif
-#ifdef __ADSPBF526__
-# include "mach-bf527/BF526_cdef.h"
-#endif
-#ifdef __ADSPBF527__
-# include "mach-bf527/BF527_cdef.h"
-#endif
-#ifdef __ADSPBF531__
-# include "mach-bf533/BF531_cdef.h"
-#endif
-#ifdef __ADSPBF532__
-# include "mach-bf533/BF532_cdef.h"
-#endif
-#ifdef __ADSPBF533__
-# include "mach-bf533/BF533_cdef.h"
-#endif
-#ifdef __ADSPBF534__
-# include "mach-bf537/BF534_cdef.h"
-#endif
-#ifdef __ADSPBF536__
-# include "mach-bf537/BF536_cdef.h"
-#endif
-#ifdef __ADSPBF537__
-# include "mach-bf537/BF537_cdef.h"
-#endif
-#ifdef __ADSPBF538__
-# include "mach-bf538/BF538_cdef.h"
-#endif
-#ifdef __ADSPBF539__
-# include "mach-bf538/BF539_cdef.h"
-#endif
-#ifdef __ADSPBF542__
-# include "mach-bf548/BF542_cdef.h"
-#endif
-#ifdef __ADSPBF544__
-# include "mach-bf548/BF544_cdef.h"
-#endif
-#ifdef __ADSPBF547__
-# include "mach-bf548/BF547_cdef.h"
-#endif
-#ifdef __ADSPBF548__
-# include "mach-bf548/BF548_cdef.h"
-#endif
-#ifdef __ADSPBF549__
-# include "mach-bf548/BF549_cdef.h"
-#endif
-#ifdef __ADSPBF561__
-# include "mach-bf561/BF561_cdef.h"
-#endif
-#ifdef __ADSPBF609__
-# include "mach-bf609/BF609_cdef.h"
-#endif
-
-#endif /* __MACH_CDEF_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_def.h b/arch/blackfin/include/asm/blackfin_def.h
deleted file mode 100644
index c96a3ec..0000000
--- a/arch/blackfin/include/asm/blackfin_def.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __MACH_DEF_BLACKFIN__
-#define __MACH_DEF_BLACKFIN__
-
-#ifdef __ADSPBF504__
-# include "mach-bf506/BF504_def.h"
-# include "mach-bf506/anomaly.h"
-# include "mach-bf506/def_local.h"
-#endif
-#ifdef __ADSPBF506__
-# include "mach-bf506/BF506_def.h"
-# include "mach-bf506/anomaly.h"
-# include "mach-bf506/def_local.h"
-#endif
-#ifdef __ADSPBF512__
-# include "mach-bf518/BF512_def.h"
-# include "mach-bf518/anomaly.h"
-# include "mach-bf518/def_local.h"
-#endif
-#ifdef __ADSPBF514__
-# include "mach-bf518/BF514_def.h"
-# include "mach-bf518/anomaly.h"
-# include "mach-bf518/def_local.h"
-#endif
-#ifdef __ADSPBF516__
-# include "mach-bf518/BF516_def.h"
-# include "mach-bf518/anomaly.h"
-# include "mach-bf518/def_local.h"
-#endif
-#ifdef __ADSPBF518__
-# include "mach-bf518/BF518_def.h"
-# include "mach-bf518/anomaly.h"
-# include "mach-bf518/def_local.h"
-#endif
-#ifdef __ADSPBF522__
-# include "mach-bf527/BF522_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF523__
-# include "mach-bf527/BF523_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF524__
-# include "mach-bf527/BF524_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF525__
-# include "mach-bf527/BF525_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF526__
-# include "mach-bf527/BF526_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF527__
-# include "mach-bf527/BF527_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF531__
-# include "mach-bf533/BF531_def.h"
-# include "mach-bf533/anomaly.h"
-# include "mach-bf533/def_local.h"
-#endif
-#ifdef __ADSPBF532__
-# include "mach-bf533/BF532_def.h"
-# include "mach-bf533/anomaly.h"
-# include "mach-bf533/def_local.h"
-#endif
-#ifdef __ADSPBF533__
-# include "mach-bf533/BF533_def.h"
-# include "mach-bf533/anomaly.h"
-# include "mach-bf533/def_local.h"
-#endif
-#ifdef __ADSPBF534__
-# include "mach-bf537/BF534_def.h"
-# include "mach-bf537/anomaly.h"
-# include "mach-bf537/def_local.h"
-#endif
-#ifdef __ADSPBF536__
-# include "mach-bf537/BF536_def.h"
-# include "mach-bf537/anomaly.h"
-# include "mach-bf537/def_local.h"
-#endif
-#ifdef __ADSPBF537__
-# include "mach-bf537/BF537_def.h"
-# include "mach-bf537/anomaly.h"
-# include "mach-bf537/def_local.h"
-#endif
-#ifdef __ADSPBF538__
-# include "mach-bf538/BF538_def.h"
-# include "mach-bf538/anomaly.h"
-# include "mach-bf538/def_local.h"
-#endif
-#ifdef __ADSPBF539__
-# include "mach-bf538/BF539_def.h"
-# include "mach-bf538/anomaly.h"
-# include "mach-bf538/def_local.h"
-#endif
-#ifdef __ADSPBF542__
-# include "mach-bf548/BF542_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF544__
-# include "mach-bf548/BF544_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF547__
-# include "mach-bf548/BF547_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF548__
-# include "mach-bf548/BF548_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF549__
-# include "mach-bf548/BF549_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF561__
-# include "mach-bf561/BF561_def.h"
-# include "mach-bf561/anomaly.h"
-# include "mach-bf561/def_local.h"
-#endif
-#ifdef __ADSPBF609__
-# include "mach-bf609/BF609_def.h"
-# include "mach-bf609/anomaly.h"
-# include "mach-bf609/def_local.h"
-#endif
-
-#endif /* __MACH_DEF_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
deleted file mode 100644
index 00556de..0000000
--- a/arch/blackfin/include/asm/blackfin_local.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * U-Boot - blackfin_local.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __BLACKFIN_LOCAL_H__
-#define __BLACKFIN_LOCAL_H__
-
-#include <asm/mem_map.h>
-
-#define LO(con32) ((con32) & 0xFFFF)
-#define lo(con32) ((con32) & 0xFFFF)
-#define HI(con32) (((con32) >> 16) & 0xFFFF)
-#define hi(con32) (((con32) >> 16) & 0xFFFF)
-
-#define OFFSET_(x) (x & 0x0000FFFF)
-#define MK_BMSK_(x) (1 << x)
-
-/* Ideally this should be USEC not MSEC, but the USEC multiplication
- * likes to overflow 32bit quantities which is all our assembler
- * currently supports ;(
- */
-#define USEC_PER_MSEC 1000
-#define MSEC_PER_SEC 1000
-#define BFIN_SCLK (100000000)
-#define SCLK_TO_MSEC(sclk) ((MSEC_PER_SEC * ((sclk) / USEC_PER_MSEC)) / (BFIN_SCLK / USEC_PER_MSEC))
-#define MSEC_TO_SCLK(msec) ((((BFIN_SCLK / USEC_PER_MSEC) * (msec)) / MSEC_PER_SEC) * USEC_PER_MSEC)
-
-#define L1_CACHE_SHIFT 5
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
-#include <linux/linkage.h>
-#include <asm/cache.h>
-
-#ifndef __ASSEMBLY__
-# ifdef SHARED_RESOURCES
-#  include <asm/shared_resources.h>
-# endif
-
-# include <linux/types.h>
-
-# define bfin_revid() (bfin_read_CHIPID() >> 28)
-
-extern int bfin_os_log_check(void);
-extern void bfin_os_log_dump(void);
-
-extern void blackfin_icache_flush_range(const void *, const void *);
-extern void blackfin_dcache_flush_range(const void *, const void *);
-extern void blackfin_icache_dcache_flush_range(const void *, const void *);
-extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
-
-/* Use DMA to move data from on chip to external memory.  The L1 instruction
- * regions can only be accessed via DMA, so if the address in question is in
- * that region, make sure we attempt to DMA indirectly.
- */
-# ifdef __ADSPBF561__
-  /* Core B regions all need dma from Core A */
-#  define addr_bfin_on_chip_mem(addr) \
-	((((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) || \
-	 (((unsigned long)(addr) & 0xFFC00000) == 0xFF400000))
-# else
-#  define addr_bfin_on_chip_mem(addr) \
-	(((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000)
-# endif
-
-# include <asm/system.h>
-
-#if ANOMALY_05000198
-# define NOP_PAD_ANOMALY_05000198 "nop;"
-#else
-# define NOP_PAD_ANOMALY_05000198
-#endif
-
-#define BFIN_BUG() while (1) asm volatile("emuexcpt;");
-
-#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
-	u32 __v; \
-	__asm__ __volatile__( \
-		NOP_PAD_ANOMALY_05000198 \
-		"%0 = " #asm_size "[%1]" #asm_ext ";" \
-		: "=d" (__v) \
-		: "a" (addr) \
-	); \
-	__v; })
-#define _bfin_writeX(addr, val, size, asm_size) \
-	__asm__ __volatile__( \
-		NOP_PAD_ANOMALY_05000198 \
-		#asm_size "[%0] = %1;" \
-		: \
-		: "a" (addr), "d" ((u##size)(val)) \
-		: "memory" \
-	)
-
-#define bfin_read8(addr)  _bfin_readX(addr,  8, b, (z))
-#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
-#define bfin_read32(addr) _bfin_readX(addr, 32,  ,    )
-#define bfin_write8(addr, val)  _bfin_writeX(addr, val,  8, b)
-#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
-#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32,  )
-
-#define bfin_read(addr) \
-({ \
-	sizeof(*(addr)) == 1 ? bfin_read8(addr)  : \
-	sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
-	sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
-	({ BFIN_BUG(); 0; }); \
-})
-#define bfin_write(addr, val) \
-do { \
-	switch (sizeof(*(addr))) { \
-	case 1: bfin_write8(addr, val);  break; \
-	case 2: bfin_write16(addr, val); break; \
-	case 4: bfin_write32(addr, val); break; \
-	default: \
-		BFIN_BUG(); \
-	} \
-} while (0)
-
-#define bfin_write_or(addr, bits) \
-do { \
-	typeof(addr) __addr = (addr); \
-	bfin_write(__addr, bfin_read(__addr) | (bits)); \
-} while (0)
-
-#define bfin_write_and(addr, bits) \
-do { \
-	typeof(addr) __addr = (addr); \
-	bfin_write(__addr, bfin_read(__addr) & (bits)); \
-} while (0)
-
-#define bfin_readPTR(addr) bfin_read32(addr)
-#define bfin_writePTR(addr, val) bfin_write32(addr, val)
-
-/* SSYNC implementation for C file */
-static inline void SSYNC(void)
-{
-	int _tmp;
-	if (ANOMALY_05000312)
-		__asm__ __volatile__(
-			"cli %0;"
-			"nop;"
-			"nop;"
-			"ssync;"
-			"sti %0;"
-			: "=d" (_tmp)
-		);
-	else if (ANOMALY_05000244)
-		__asm__ __volatile__(
-			"nop;"
-			"nop;"
-			"nop;"
-			"ssync;"
-		);
-	else
-		__asm__ __volatile__("ssync;");
-}
-
-/* CSYNC implementation for C file */
-static inline void CSYNC(void)
-{
-	int _tmp;
-	if (ANOMALY_05000312)
-		__asm__ __volatile__(
-			"cli %0;"
-			"nop;"
-			"nop;"
-			"csync;"
-			"sti %0;"
-			: "=d" (_tmp)
-		);
-	else if (ANOMALY_05000244)
-		__asm__ __volatile__(
-			"nop;"
-			"nop;"
-			"nop;"
-			"csync;"
-		);
-	else
-		__asm__ __volatile__("csync;");
-}
-
-#else  /* __ASSEMBLY__ */
-
-/* SSYNC & CSYNC implementations for assembly files */
-
-#define ssync(x) SSYNC(x)
-#define csync(x) CSYNC(x)
-
-#if ANOMALY_05000312
-#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
-#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
-
-#elif ANOMALY_05000244
-#define SSYNC(scratch) nop; nop; nop; SSYNC;
-#define CSYNC(scratch) nop; nop; nop; CSYNC;
-
-#else
-#define SSYNC(scratch) SSYNC;
-#define CSYNC(scratch) CSYNC;
-
-#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
-
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/blackfin/include/asm/byteorder.h b/arch/blackfin/include/asm/byteorder.h
deleted file mode 100644
index 593ba5a..0000000
--- a/arch/blackfin/include/asm/byteorder.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * U-Boot -  byteorder.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _BLACKFIN_BYTEORDER_H
-#define _BLACKFIN_BYTEORDER_H
-
-#include <asm/types.h>
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#include <linux/byteorder/little_endian.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
deleted file mode 100644
index 568885a..0000000
--- a/arch/blackfin/include/asm/cache.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_CACHE_H
-#define __ARCH_BLACKFIN_CACHE_H
-
-#include <linux/linkage.h>	/* for asmlinkage */
-
-/*
- * Bytes per L1 cache line
- * Blackfin loads 32 bytes for cache
- */
-#define L1_CACHE_SHIFT	5
-#define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)
-#define SMP_CACHE_BYTES	L1_CACHE_BYTES
-
-#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
-
-#ifdef CONFIG_SMP
-#define __cacheline_aligned
-#else
-#define ____cacheline_aligned
-
-/*
- * Put cacheline_aliged data to L1 data memory
- */
-#ifdef CONFIG_CACHELINE_ALIGNED_L1
-#define __cacheline_aligned				\
-	  __attribute__((__aligned__(L1_CACHE_BYTES),	\
-		__section__(".data_l1.cacheline_aligned")))
-#endif
-
-#endif
-
-/*
- * largest L1 which this arch supports
- */
-#define L1_CACHE_SHIFT_MAX	5
-
-#if defined(CONFIG_SMP) && \
-    !defined(CONFIG_BFIN_CACHE_COHERENT)
-# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
-# define __ARCH_SYNC_CORE_ICACHE
-# endif
-# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
-# define __ARCH_SYNC_CORE_DCACHE
-# endif
-#ifndef __ASSEMBLY__
-asmlinkage void __raw_smp_mark_barrier_asm(void);
-asmlinkage void __raw_smp_check_barrier_asm(void);
-
-static inline void smp_mark_barrier(void)
-{
-	__raw_smp_mark_barrier_asm();
-}
-static inline void smp_check_barrier(void)
-{
-	__raw_smp_check_barrier_asm();
-}
-
-void resync_core_dcache(void);
-void resync_core_icache(void);
-#endif
-#endif
-
-
-#endif
diff --git a/arch/blackfin/include/asm/clock.h b/arch/blackfin/include/asm/clock.h
deleted file mode 100644
index 05ae03c..0000000
--- a/arch/blackfin/include/asm/clock.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (C) 2012 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __CLOCK_H__
-#define __CLOCK_H__
-
-#include <asm/blackfin.h>
-#ifdef PLL_CTL
-#include <asm/mach-common/bits/pll.h>
-# define pll_is_bypassed() (bfin_read_PLL_CTL() & BYPASS)
-#else
-#include <asm/mach-common/bits/cgu.h>
-# define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP)
-# define bfin_read_PLL_CTL() bfin_read_CGU_CTL()
-# define bfin_read_PLL_DIV() bfin_read_CGU_DIV()
-# define SSEL SYSSEL
-# define SSEL_P SYSSEL_P
-#endif
-
-__attribute__((always_inline))
-static inline uint32_t early_division(uint32_t dividend, uint32_t divisor)
-{
-	uint32_t quotient;
-	uint32_t i, j;
-
-	for (quotient = 1, i = 1; dividend > divisor; ++i) {
-		j = divisor << i;
-		if (j > dividend || (j & 0x80000000)) {
-			--i;
-			quotient += (1 << i);
-			dividend -= (divisor << i);
-			i = 0;
-		}
-	}
-
-	return quotient;
-}
-
-__attribute__((always_inline))
-static inline uint32_t early_get_uart_clk(void)
-{
-	uint32_t msel, pll_ctl, vco;
-	uint32_t div, ssel, sclk, uclk;
-
-	pll_ctl = bfin_read_PLL_CTL();
-	msel = (pll_ctl & MSEL) >> MSEL_P;
-	if (msel == 0)
-		msel = (MSEL >> MSEL_P) + 1;
-
-	vco = (CONFIG_CLKIN_HZ >> (pll_ctl & DF)) * msel;
-	sclk = vco;
-	if (!pll_is_bypassed()) {
-		div = bfin_read_PLL_DIV();
-		ssel = (div & SSEL) >> SSEL_P;
-#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
-		sclk = vco/ssel;
-#else
-		sclk = early_division(vco, ssel);
-#endif
-	}
-	uclk = sclk;
-#ifdef CGU_DIV
-	ssel = (div & S0SEL) >> S0SEL_P;
-	uclk = early_division(sclk, ssel);
-#endif
-	return uclk;
-}
-
-extern u_long get_vco(void);
-extern u_long get_cclk(void);
-extern u_long get_sclk(void);
-
-#ifdef CGU_DIV
-extern u_long get_sclk0(void);
-extern u_long get_sclk1(void);
-extern u_long get_dclk(void);
-# define get_uart_clk get_sclk0
-# define get_i2c_clk get_sclk0
-# define get_spi_clk get_sclk1
-#else
-# define get_uart_clk get_sclk
-# define get_i2c_clk get_sclk
-# define get_spi_clk get_sclk
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config-pre.h
deleted file mode 100644
index 2d8b293..0000000
--- a/arch/blackfin/include/asm/config-pre.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * config-pre.h - common defines for Blackfin boards in config.h
- *
- * Copyright (c) 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_CONFIG_PRE_H__
-#define __ASM_BLACKFIN_CONFIG_PRE_H__
-
-/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
- * Depending on your cpu, some of these may not be valid, check your HRM.
- * The actual values here are meaningless as long as they're unique.
- */
-#define BFIN_BOOT_BYPASS      1       /* bypass bootrom */
-#define BFIN_BOOT_PARA        2       /* boot ldr out of parallel flash */
-#define BFIN_BOOT_SPI_MASTER  3       /* boot ldr out of serial flash */
-#define BFIN_BOOT_SPI_SLAVE   4       /* boot ldr as spi slave */
-#define BFIN_BOOT_TWI_MASTER  5       /* boot ldr over twi device */
-#define BFIN_BOOT_TWI_SLAVE   6       /* boot ldr over twi slave */
-#define BFIN_BOOT_UART        7       /* boot ldr over uart */
-#define BFIN_BOOT_IDLE        8       /* do nothing, just idle */
-#define BFIN_BOOT_FIFO        9       /* boot ldr out of FIFO */
-#define BFIN_BOOT_MEM         10      /* boot ldr out of memory (warmboot) */
-#define BFIN_BOOT_16HOST_DMA  11      /* boot ldr from 16-bit host dma */
-#define BFIN_BOOT_8HOST_DMA   12      /* boot ldr from 8-bit host dma */
-#define BFIN_BOOT_NAND        13      /* boot ldr from nand flash */
-#define BFIN_BOOT_RSI_MASTER  14      /* boot ldr from rsi */
-#define BFIN_BOOT_LP_SLAVE    15      /* boot ldr from link port */
-
-#ifndef __ASSEMBLY__
-static inline const char *get_bfin_boot_mode(int bfin_boot)
-{
-	switch (bfin_boot) {
-	case BFIN_BOOT_BYPASS:     return "bypass";
-	case BFIN_BOOT_PARA:       return "parallel flash";
-	case BFIN_BOOT_SPI_MASTER: return "spi flash";
-	case BFIN_BOOT_SPI_SLAVE:  return "spi slave";
-	case BFIN_BOOT_TWI_MASTER: return "i2c flash";
-	case BFIN_BOOT_TWI_SLAVE:  return "i2c slave";
-	case BFIN_BOOT_UART:       return "uart";
-	case BFIN_BOOT_IDLE:       return "idle";
-	case BFIN_BOOT_FIFO:       return "fifo";
-	case BFIN_BOOT_MEM:        return "memory";
-	case BFIN_BOOT_16HOST_DMA: return "16bit dma";
-	case BFIN_BOOT_8HOST_DMA:  return "8bit dma";
-	case BFIN_BOOT_NAND:       return "nand flash";
-	case BFIN_BOOT_RSI_MASTER: return "rsi master";
-	case BFIN_BOOT_LP_SLAVE:   return "link port slave";
-	default:                   return "INVALID";
-	}
-}
-#endif
-
-/* Most bootroms allow for EVT1 redirection */
-#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__)) \
-     && __SILICON_REVISION__ < 3) || defined(__ADSPBF561__)
-# undef CONFIG_BFIN_BOOTROM_USES_EVT1
-#else
-# define CONFIG_BFIN_BOOTROM_USES_EVT1
-#endif
-
-/* Define the default SPI CS used when booting out of SPI */
-#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
-    defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
-    defined(__ADSPBF51x__)
-# define BFIN_BOOT_SPI_SSEL 2
-#else
-# define BFIN_BOOT_SPI_SSEL 1
-#endif
-
-/* Define to get a GPIO CS with the Blackfin SPI controller */
-#define MAX_CTRL_CS 8
-
-/* There is no Blackfin/NetBSD port */
-#undef CONFIG_BOOTM_NETBSD
-
-/* We rarely use interrupts, so favor throughput over latency */
-#define CONFIG_BFIN_INS_LOWOVERHEAD
-
-#endif
diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
deleted file mode 100644
index 4e8313d..0000000
--- a/arch/blackfin/include/asm/config.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * config.h - setup common defines for Blackfin boards based on config.h
- *
- * Copyright (c) 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_CONFIG_POST_H__
-#define __ASM_BLACKFIN_CONFIG_POST_H__
-
-/* Some of our defines use this (like CONFIG_SYS_GBL_DATA_ADDR) */
-#include <asm-offsets.h>
-
-/* Sanity check CONFIG_BFIN_CPU */
-#ifndef CONFIG_BFIN_CPU
-# error CONFIG_BFIN_CPU: your board config needs to define this
-#endif
-
-#ifndef CONFIG_BFIN_SCRATCH_REG
-# define CONFIG_BFIN_SCRATCH_REG retn
-#endif
-
-/* U-Boot wants this config name */
-#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
-
-/* Make sure the structure is properly aligned */
-#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
-# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
-#endif
-
-/* Set default CONFIG_VCO_HZ if need be */
-#if !defined(CONFIG_VCO_HZ)
-# if (CONFIG_CLKIN_HALF == 0)
-#  define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
-# else
-#  define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2)
-# endif
-#endif
-
-/* Set default CONFIG_CCLK_HZ if need be */
-#if !defined(CONFIG_CCLK_HZ)
-# if (CONFIG_PLL_BYPASS == 0)
-#  define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV)
-# else
-#  define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-# endif
-#endif
-
-/* Set default CONFIG_SCLK_HZ if need be */
-#if !defined(CONFIG_SCLK_HZ)
-# if (CONFIG_PLL_BYPASS == 0)
-#  define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV)
-# else
-#  define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-# endif
-#endif
-
-/* Since we use these to program PLL registers directly,
- * make sure the values are sane and won't screw us up.
- */
-#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT
-# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63)
-#endif
-#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF
-# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1
-#endif
-#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS
-# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1
-#endif
-
-/* If we are using KGDB, make sure we defer exceptions */
-#ifdef CONFIG_CMD_KGDB
-# define CONFIG_EXCEPTION_DEFER	1
-#endif
-
-/* Using L1 scratch pad makes sense for everyone by default. */
-#ifndef CONFIG_LINUX_CMDLINE_ADDR
-# define CONFIG_LINUX_CMDLINE_ADDR L1_SRAM_SCRATCH
-#endif
-#ifndef CONFIG_LINUX_CMDLINE_SIZE
-# define CONFIG_LINUX_CMDLINE_SIZE L1_SRAM_SCRATCH_SIZE
-#endif
-
-/* Set default SPI flash CS to the one we boot from */
-#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_SPI_CS)
-# define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL
-#endif
-
-/* We need envcrc to embed the env into LDRs */
-#ifdef CONFIG_ENV_IS_EMBEDDED_IN_LDR
-# define CONFIG_BUILD_ENVCRC
-#endif
-
-/* Default/common Blackfin memory layout */
-#ifndef CONFIG_SYS_SDRAM_BASE
-# define CONFIG_SYS_SDRAM_BASE 0
-#endif
-#ifndef CONFIG_SYS_MAX_RAM_SIZE
-# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
-#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-# if CONFIG_SYS_MAX_RAM_SIZE
-#  define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
-# else
-#  define CONFIG_SYS_MONITOR_BASE 0
-# endif
-#endif
-#ifndef CONFIG_SYS_MALLOC_BASE
-# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#endif
-#ifndef CONFIG_STACKBASE
-# define CONFIG_STACKBASE (CONFIG_SYS_MALLOC_BASE - 4)
-#endif
-#ifndef CONFIG_SYS_MEMTEST_START
-# define CONFIG_SYS_MEMTEST_START 0
-#endif
-#ifndef CONFIG_SYS_MEMTEST_END
-# define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4)
-#endif
-#ifndef CONFIG_SYS_POST_WORD_ADDR
-# define CONFIG_SYS_POST_WORD_ADDR (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE - 4)
-#endif
-
-/* Check to make sure everything fits in external RAM */
-#if CONFIG_SYS_MAX_RAM_SIZE && \
-    ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
-# error Memory Map does not fit into configuration
-#endif
-
-/* Default/common Blackfin environment settings */
-#ifndef CONFIG_LOADADDR
-# define CONFIG_LOADADDR 0x1000000
-#endif
-#ifndef CONFIG_SYS_LOAD_ADDR
-# define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#endif
-#ifndef CONFIG_SYS_BOOTM_LEN
-# define CONFIG_SYS_BOOTM_LEN 0x4000000
-#endif
-#ifndef CONFIG_SYS_CBSIZE
-# define CONFIG_SYS_CBSIZE 1024
-#elif defined(CONFIG_CMD_KGDB) && CONFIG_SYS_CBSIZE < 1024
-# error "kgdb needs cbsize to be >= 1024"
-#endif
-#ifndef CONFIG_SYS_BARGSIZE
-# define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#endif
-#ifndef CONFIG_SYS_PBSIZE
-# define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#endif
-#ifndef CONFIG_SYS_MAXARGS
-# define CONFIG_SYS_MAXARGS 16
-#endif
-
-/* Blackfin POST tests */
-#ifdef CONFIG_POST_BSPEC1_GPIO_LEDS
-# define CONFIG_POST_BSPEC1 \
-	{ \
-		"LED test", "led", "This test verifies LEDs on the board.", \
-		POST_MEM | POST_ALWAYS, &led_post_test, NULL, NULL, \
-		CONFIG_SYS_POST_BSPEC1, \
-	}
-#endif
-#ifdef CONFIG_POST_BSPEC2_GPIO_BUTTONS
-# define CONFIG_POST_BSPEC2 \
-	{ \
-		"Button test", "button", "This test verifies buttons on the board.", \
-		POST_MEM | POST_ALWAYS, &button_post_test, NULL, NULL, \
-		CONFIG_SYS_POST_BSPEC2, \
-	}
-#endif
-
-#define CONFIG_CPU CONFIG_BFIN_CPU
-
-#endif
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
deleted file mode 100644
index 420380d..0000000
--- a/arch/blackfin/include/asm/cplb.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * cplb.h - defines for managing CPLB tables
- *
- * Copyright (c) 2002-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_CPLB_H__
-#define __ASM_BLACKFIN_CPLB_H__
-
-#include <asm/mach-common/bits/mpu.h>
-
-#define CPLB_ENABLE_ICACHE_P	0
-#define CPLB_ENABLE_DCACHE_P	1
-#define CPLB_ENABLE_DCACHE2_P	2
-#define CPLB_ENABLE_CPLBS_P	3	/* Deprecated! */
-#define CPLB_ENABLE_ICPLBS_P	4
-#define CPLB_ENABLE_DCPLBS_P	5
-
-#define CPLB_ENABLE_ICACHE	(1<<CPLB_ENABLE_ICACHE_P)
-#define CPLB_ENABLE_DCACHE	(1<<CPLB_ENABLE_DCACHE_P)
-#define CPLB_ENABLE_DCACHE2	(1<<CPLB_ENABLE_DCACHE2_P)
-#define CPLB_ENABLE_CPLBS	(1<<CPLB_ENABLE_CPLBS_P)
-#define CPLB_ENABLE_ICPLBS	(1<<CPLB_ENABLE_ICPLBS_P)
-#define CPLB_ENABLE_DCPLBS	(1<<CPLB_ENABLE_DCPLBS_P)
-#define CPLB_ENABLE_ANY_CPLBS	CPLB_ENABLE_CPLBS | \
-				CPLB_ENABLE_ICPLBS | \
-				CPLB_ENABLE_DCPLBS
-
-#define CPLB_RELOADED		0x0000
-#define CPLB_NO_UNLOCKED	0x0001
-#define CPLB_NO_ADDR_MATCH	0x0002
-#define CPLB_PROT_VIOL		0x0003
-
-#define CPLB_DEF_CACHE		CPLB_L1_CHBL | CPLB_WT
-#define CPLB_CACHE_ENABLED	CPLB_L1_CHBL | CPLB_DIRTY
-
-#define CPLB_ALL_ACCESS	CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
-
-#define CPLB_I_PAGE_MGMT	CPLB_LOCK | CPLB_VALID
-#define CPLB_D_PAGE_MGMT	CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DNOCACHE		CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DDOCACHE		CPLB_DNOCACHE | CPLB_DEF_CACHE
-#define CPLB_INOCACHE		CPLB_USER_RD | CPLB_VALID
-#define CPLB_IDOCACHE		CPLB_INOCACHE | CPLB_L1_CHBL
-
-/* Data Attibutes*/
-#if defined(__ADSPBF60x__)
-#define SDRAM_IGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | \
-				CPLB_USER_RD | CPLB_VALID)
-#else
-#define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | \
-				CPLB_USER_RD | CPLB_VALID)
-#endif
-#define SDRAM_IKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define L1_IMEMORY              (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL         (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
-
-#if ANOMALY_05000158
-# define ANOMALY_05000158_WORKAROUND 0x200
-#else
-# define ANOMALY_05000158_WORKAROUND 0
-#endif
-
-#ifdef CONFIG_DCACHE_WB		/*Write Back Policy */
-#if defined(__ADSPBF60x__)
-#define SDRAM_DGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | \
-				CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
-				CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#else
-#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | \
-				CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
-				CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#endif
-#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
-#define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-
-#else				/*Write Through */
-#if defined(__ADSPBF60x__)
-#define SDRAM_DGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_WT | \
-				CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
-				CPLB_USER_WR | CPLB_VALID | \
-				ANOMALY_05000158_WORKAROUND)
-#else
-#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | \
-				CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
-				CPLB_USER_WR | CPLB_VALID | \
-				ANOMALY_05000158_WORKAROUND)
-#endif
-#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
-#define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#endif
-
-#endif				/* _CPLB_H */
diff --git a/arch/blackfin/include/asm/deferred.h b/arch/blackfin/include/asm/deferred.h
deleted file mode 100644
index e75d7e8..0000000
--- a/arch/blackfin/include/asm/deferred.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * U-Boot - deferred register layout
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_DEFER_H
-#define _BLACKFIN_DEFER_H
-
-#define deferred_regs_DCPLB_FAULT_ADDR	0
-#define deferred_regs_ICPLB_FAULT_ADDR	1
-#define deferred_regs_retx		2
-#define deferred_regs_SEQSTAT		3
-#define deferred_regs_SYSCFG		4
-#define deferred_regs_IMASK		5
-#define deferred_regs_last		6
-
-#endif /* _BLACKFIN_DEFER_H */
diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h
deleted file mode 100644
index 06c3edd..0000000
--- a/arch/blackfin/include/asm/delay.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * U-Boot - delay.h Routines for introducing delays
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _BLACKFIN_DELAY_H
-#define _BLACKFIN_DELAY_H
-
-/*
- * Changes made by akbar.hussain@Lineo.com, for BLACKFIN
- * Copyright (C) 1994 Hamish Macdonald
- *
- * Delay routines, using a pre-computed "loops_per_second" value.
- */
-
-static __inline__ void __delay(unsigned long loops)
-{
-	__asm__ __volatile__("1:\t%0 += -1;\n\t"
-			     "cc = %0 == 0;\n\t"
-			     "if ! cc jump 1b;\n":"=d"(loops)
-			     :"0"(loops));
-}
-
-/*
- * Use only for very small delays ( < 1 msec).  Should probably use a
- * lookup table, really, as the multiplications take much too long with
- * short delays.  This is a "reasonable" implementation, though (and the
- * first constant multiplications gets optimized away if the delay is
- * a constant)
- */
-static __inline__ void __udelay(unsigned long usecs)
-{
-	__delay(usecs);
-}
-
-#endif
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
deleted file mode 100644
index 8a7c079..0000000
--- a/arch/blackfin/include/asm/dma.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * dma.h - Blackfin DMA defines/structures/etc...
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_DMA_H_
-#define _BLACKFIN_DMA_H_
-
-#include <linux/types.h>
-#ifdef __ADSPBF60x__
-#include <asm/mach-common/bits/dde.h>
-#else
-#include <asm/mach-common/bits/dma.h>
-#endif
-
-struct dmasg_large {
-	void *next_desc_addr;
-	u32 start_addr;
-	u16 cfg;
-	u16 x_count;
-	s16 x_modify;
-	u16 y_count;
-	s16 y_modify;
-} __attribute__((packed));
-
-struct dmasg {
-	u32 start_addr;
-	u16 cfg;
-	u16 x_count;
-	s16 x_modify;
-	u16 y_count;
-	s16 y_modify;
-} __attribute__((packed));
-
-struct dma_register {
-#ifdef __ADSPBF60x__
-	void *next_desc_ptr;	/* DMA Next Descriptor Pointer register */
-	u32 start_addr;		/* DMA Start address  register */
-	u32 config;		/* DMA Configuration register */
-
-	u32 x_count;		/* DMA x_count register */
-	s32 x_modify;		/* DMA x_modify register */
-	u32 y_count;		/* DMA y_count register */
-	s32 y_modify;		/* DMA y_modify register */
-	u32 __pad0[2];
-
-	void *curr_desc_ptr;	/* DMA Curr Descriptor Pointer register */
-	void *prev_desc_ptr;	/* DMA Prev Descriptor Pointer register */
-	void *curr_addr;	/* DMA Current Address Pointer register */
-	u32 status;		/* DMA irq status register */
-	u32 curr_x_count;	/* DMA Current x-count register */
-	u32 curr_y_count;	/* DMA Current y-count register */
-	u32 __pad1[2];
-
-	u32 bw_limit;		/* DMA Bandwidth Limit Count */
-	u32 curr_bw_limit;	/* DMA curr Bandwidth Limit Count */
-	u32 bw_monitor;		/* DMA Bandwidth Monitor Count */
-	u32 curr_bw_monitor;	/* DMA curr Bandwidth Monitor Count */
-#else
-	void *next_desc_ptr;	/* DMA Next Descriptor Pointer register */
-	u32 start_addr;		/* DMA Start address  register */
-
-	u16 config;		/* DMA Configuration register */
-	u16 dummy1;		/* DMA Configuration register */
-
-	u32 reserved;
-
-	u16 x_count;		/* DMA x_count register */
-	u16 dummy2;
-
-	s16 x_modify;		/* DMA x_modify register */
-	u16 dummy3;
-
-	u16 y_count;		/* DMA y_count register */
-	u16 dummy4;
-
-	s16 y_modify;		/* DMA y_modify register */
-	u16 dummy5;
-
-	void *curr_desc_ptr;	/* DMA Current Descriptor Pointer register */
-
-	u32 curr_addr_ptr;	/* DMA Current Address Pointer register */
-
-	u16 status;		/* DMA irq status register */
-	u16 dummy6;
-
-	u16 peripheral_map;	/* DMA peripheral map register */
-	u16 dummy7;
-
-	u16 curr_x_count;	/* DMA Current x-count register */
-	u16 dummy8;
-
-	u32 reserved2;
-
-	u16 curr_y_count;	/* DMA Current y-count register */
-	u16 dummy9;
-
-	u32 reserved3;
-#endif
-};
-
-#endif
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
deleted file mode 100644
index 98fe79c..0000000
--- a/arch/blackfin/include/asm/entry.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * entry.h - routines for context saving and restoring (for interrupts/exceptions)
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __BLACKFIN_ENTRY_H
-#define __BLACKFIN_ENTRY_H
-#ifdef __ASSEMBLY__
-
-#define SAVE_ALL_INT		save_context_no_interrupts
-#define SAVE_ALL_SYS		save_context_no_interrupts
-#define SAVE_CONTEXT		save_context_with_interrupts
-
-#define RESTORE_ALL		restore_context_no_interrupts
-#define RESTORE_ALL_SYS		restore_context_no_interrupts
-#define RESTORE_CONTEXT		restore_context_with_interrupts
-
-/*
- * Code to save processor context.
- * We even save the register which are preserved by a function call
- * - r4, r5, r6, r7, p3, p4, p5
- */
-.macro save_context_with_interrupts
-	[--sp] = R0;
-	[--sp] = ( R7:0, P5:0 );
-	[--sp] = fp;
-	[--sp] = usp;
-
-	[--sp] = i0;
-	[--sp] = i1;
-	[--sp] = i2;
-	[--sp] = i3;
-
-	[--sp] = m0;
-	[--sp] = m1;
-	[--sp] = m2;
-	[--sp] = m3;
-
-	[--sp] = l0;
-	[--sp] = l1;
-	[--sp] = l2;
-	[--sp] = l3;
-
-	[--sp] = b0;
-	[--sp] = b1;
-	[--sp] = b2;
-	[--sp] = b3;
-	[--sp] = a0.x;
-	[--sp] = a0.w;
-	[--sp] = a1.x;
-	[--sp] = a1.w;
-
-	[--sp] = LC0;
-	[--sp] = LC1;
-	[--sp] = LT0;
-	[--sp] = LT1;
-	[--sp] = LB0;
-	[--sp] = LB1;
-
-	[--sp] = ASTAT;
-
-	[--sp] = r0;	/* Skip reserved */
-	[--sp] = RETS;
-	[--sp] = RETI;
-	[--sp] = RETX;
-	[--sp] = RETN;
-	[--sp] = RETE;
-	[--sp] = SEQSTAT;
-	[--sp] = SYSCFG;
-#ifdef CONFIG_CMD_KGDB
-	p0.l = lo(IPEND)
-	p0.h = hi(IPEND)
-	r0 = [p0];
-#endif
-	[--sp] = r0;	/* Skip IPEND as well. */
-.endm
-
-.macro save_context_no_interrupts
-	[--sp] = R0;
-	[--sp] = ( R7:0, P5:0 );
-	[--sp] = fp;
-	[--sp] = usp;
-
-	[--sp] = i0;
-	[--sp] = i1;
-	[--sp] = i2;
-	[--sp] = i3;
-
-	[--sp] = m0;
-	[--sp] = m1;
-	[--sp] = m2;
-	[--sp] = m3;
-
-	[--sp] = l0;
-	[--sp] = l1;
-	[--sp] = l2;
-	[--sp] = l3;
-
-	[--sp] = b0;
-	[--sp] = b1;
-	[--sp] = b2;
-	[--sp] = b3;
-	[--sp] = a0.x;
-	[--sp] = a0.w;
-	[--sp] = a1.x;
-	[--sp] = a1.w;
-
-	[--sp] = LC0;
-	[--sp] = LC1;
-	[--sp] = LT0;
-	[--sp] = LT1;
-	[--sp] = LB0;
-	[--sp] = LB1;
-
-	[--sp] = ASTAT;
-
-	[--sp] = r0;	/* Skip reserved */
-	[--sp] = RETS;
-	r0 = RETI;
-	[--sp] = r0;
-	[--sp] = RETX;
-	[--sp] = RETN;
-	[--sp] = RETE;
-	[--sp] = SEQSTAT;
-	[--sp] = SYSCFG;
-#ifdef CONFIG_CMD_KGDB
-	p0.l = lo(IPEND)
-	p0.h = hi(IPEND)
-	r0 = [p0];
-#endif
-	[--sp] = r0;	/* Skip IPEND as well. */
-.endm
-
-.macro restore_context_no_interrupts
-	sp += 4;
-	SYSCFG = [sp++];
-	SEQSTAT = [sp++];
-	RETE = [sp++];
-	RETN = [sp++];
-	RETX = [sp++];
-	r0 = [sp++];
-	RETI = r0;
-	RETS = [sp++];
-
-	sp += 4;
-
-	ASTAT = [sp++];
-
-	LB1 = [sp++];
-	LB0 = [sp++];
-	LT1 = [sp++];
-	LT0 = [sp++];
-	LC1 = [sp++];
-	LC0 = [sp++];
-
-	a1.w = [sp++];
-	a1.x = [sp++];
-	a0.w = [sp++];
-	a0.x = [sp++];
-	b3 = [sp++];
-	b2 = [sp++];
-	b1 = [sp++];
-	b0 = [sp++];
-
-	l3 = [sp++];
-	l2 = [sp++];
-	l1 = [sp++];
-	l0 = [sp++];
-
-	m3 = [sp++];
-	m2 = [sp++];
-	m1 = [sp++];
-	m0 = [sp++];
-
-	i3 = [sp++];
-	i2 = [sp++];
-	i1 = [sp++];
-	i0 = [sp++];
-
-	sp += 4;
-	fp = [sp++];
-
-	( R7 : 0, P5 : 0) = [ SP ++ ];
-	sp += 4;
-.endm
-
-.macro restore_context_with_interrupts
-	sp += 4;
-	SYSCFG = [sp++];
-	SEQSTAT = [sp++];
-	RETE = [sp++];
-	RETN = [sp++];
-	RETX = [sp++];
-	RETI = [sp++];
-	RETS = [sp++];
-
-	sp += 4;
-
-	ASTAT = [sp++];
-
-	LB1 = [sp++];
-	LB0 = [sp++];
-	LT1 = [sp++];
-	LT0 = [sp++];
-	LC1 = [sp++];
-	LC0 = [sp++];
-
-	a1.w = [sp++];
-	a1.x = [sp++];
-	a0.w = [sp++];
-	a0.x = [sp++];
-	b3 = [sp++];
-	b2 = [sp++];
-	b1 = [sp++];
-	b0 = [sp++];
-
-	l3 = [sp++];
-	l2 = [sp++];
-	l1 = [sp++];
-	l0 = [sp++];
-
-	m3 = [sp++];
-	m2 = [sp++];
-	m1 = [sp++];
-	m0 = [sp++];
-
-	i3 = [sp++];
-	i2 = [sp++];
-	i1 = [sp++];
-	i0 = [sp++];
-
-	sp += 4;
-	fp = [sp++];
-
-	( R7 : 0, P5 : 0) = [ SP ++ ];
-	sp += 4;
-.endm
-
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h
deleted file mode 100644
index 69a6971..0000000
--- a/arch/blackfin/include/asm/global_data.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * U-Boot - global_data.h Declarations for global data of U-Boot
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef	__ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-
-#include <asm/u-boot.h>
-
-/* Architecture-specific global data */
-struct arch_global_data {
-	unsigned long board_type;
-};
-
-#include <asm-generic/global_data.h>
-
-#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("P3")
-
-#endif
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
deleted file mode 100644
index 1fa1a8e..0000000
--- a/arch/blackfin/include/asm/gpio.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_GPIO_H__
-#define __ARCH_BLACKFIN_GPIO_H__
-
-#include <asm-generic/gpio.h>
-#include <asm/portmux.h>
-
-#define gpio_bank(x)	((x) >> 4)
-#define gpio_bit(x)	(1<<((x) & 0xF))
-#define gpio_sub_n(x)	((x) & 0xF)
-
-#define GPIO_BANKSIZE	16
-#define GPIO_BANK_NUM	DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
-
-#define GPIO_0	0
-#define GPIO_1	1
-#define GPIO_2	2
-#define GPIO_3	3
-#define GPIO_4	4
-#define GPIO_5	5
-#define GPIO_6	6
-#define GPIO_7	7
-#define GPIO_8	8
-#define GPIO_9	9
-#define GPIO_10	10
-#define GPIO_11	11
-#define GPIO_12	12
-#define GPIO_13	13
-#define GPIO_14	14
-#define GPIO_15	15
-#define GPIO_16	16
-#define GPIO_17	17
-#define GPIO_18	18
-#define GPIO_19	19
-#define GPIO_20	20
-#define GPIO_21	21
-#define GPIO_22	22
-#define GPIO_23	23
-#define GPIO_24	24
-#define GPIO_25	25
-#define GPIO_26	26
-#define GPIO_27	27
-#define GPIO_28	28
-#define GPIO_29	29
-#define GPIO_30	30
-#define GPIO_31	31
-#define GPIO_32	32
-#define GPIO_33	33
-#define GPIO_34	34
-#define GPIO_35	35
-#define GPIO_36	36
-#define GPIO_37	37
-#define GPIO_38	38
-#define GPIO_39	39
-#define GPIO_40	40
-#define GPIO_41	41
-#define GPIO_42	42
-#define GPIO_43	43
-#define GPIO_44	44
-#define GPIO_45	45
-#define GPIO_46	46
-#define GPIO_47	47
-
-#define PERIPHERAL_USAGE 1
-#define GPIO_USAGE 0
-#define MAX_GPIOS MAX_BLACKFIN_GPIOS
-
-#ifndef __ASSEMBLY__
-
-#ifndef CONFIG_ADI_GPIO2
-void set_gpio_dir(unsigned, unsigned short);
-void set_gpio_inen(unsigned, unsigned short);
-void set_gpio_polar(unsigned, unsigned short);
-void set_gpio_edge(unsigned, unsigned short);
-void set_gpio_both(unsigned, unsigned short);
-void set_gpio_data(unsigned, unsigned short);
-void set_gpio_maska(unsigned, unsigned short);
-void set_gpio_maskb(unsigned, unsigned short);
-void set_gpio_toggle(unsigned);
-void set_gpiop_dir(unsigned, unsigned short);
-void set_gpiop_inen(unsigned, unsigned short);
-void set_gpiop_polar(unsigned, unsigned short);
-void set_gpiop_edge(unsigned, unsigned short);
-void set_gpiop_both(unsigned, unsigned short);
-void set_gpiop_data(unsigned, unsigned short);
-void set_gpiop_maska(unsigned, unsigned short);
-void set_gpiop_maskb(unsigned, unsigned short);
-unsigned short get_gpio_dir(unsigned);
-unsigned short get_gpio_inen(unsigned);
-unsigned short get_gpio_polar(unsigned);
-unsigned short get_gpio_edge(unsigned);
-unsigned short get_gpio_both(unsigned);
-unsigned short get_gpio_maska(unsigned);
-unsigned short get_gpio_maskb(unsigned);
-unsigned short get_gpio_data(unsigned);
-unsigned short get_gpiop_dir(unsigned);
-unsigned short get_gpiop_inen(unsigned);
-unsigned short get_gpiop_polar(unsigned);
-unsigned short get_gpiop_edge(unsigned);
-unsigned short get_gpiop_both(unsigned);
-unsigned short get_gpiop_maska(unsigned);
-unsigned short get_gpiop_maskb(unsigned);
-unsigned short get_gpiop_data(unsigned);
-
-struct gpio_port_t {
-	unsigned short data;
-	unsigned short dummy1;
-	unsigned short data_clear;
-	unsigned short dummy2;
-	unsigned short data_set;
-	unsigned short dummy3;
-	unsigned short toggle;
-	unsigned short dummy4;
-	unsigned short maska;
-	unsigned short dummy5;
-	unsigned short maska_clear;
-	unsigned short dummy6;
-	unsigned short maska_set;
-	unsigned short dummy7;
-	unsigned short maska_toggle;
-	unsigned short dummy8;
-	unsigned short maskb;
-	unsigned short dummy9;
-	unsigned short maskb_clear;
-	unsigned short dummy10;
-	unsigned short maskb_set;
-	unsigned short dummy11;
-	unsigned short maskb_toggle;
-	unsigned short dummy12;
-	unsigned short dir;
-	unsigned short dummy13;
-	unsigned short polar;
-	unsigned short dummy14;
-	unsigned short edge;
-	unsigned short dummy15;
-	unsigned short both;
-	unsigned short dummy16;
-	unsigned short inen;
-};
-#else
-extern struct gpio_port_t * const gpio_array[];
-#endif
-
-#ifdef ADI_SPECIAL_GPIO_BANKS
-void special_gpio_free(unsigned gpio);
-int special_gpio_request(unsigned gpio, const char *label);
-#endif
-
-void gpio_labels(void);
-
-static inline int gpio_is_valid(int number)
-{
-	return number >= 0 && number < MAX_GPIOS;
-}
-
-#include <linux/ctype.h>
-
-#define gpio_status() gpio_labels()
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
deleted file mode 100644
index d3337e4..0000000
--- a/arch/blackfin/include/asm/io.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * U-Boot - io.h IO routines
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_IO_H
-#define _BLACKFIN_IO_H
-
-#ifdef __KERNEL__
-
-#include <linux/compiler.h>
-#include <asm/blackfin.h>
-
-static inline void sync(void)
-{
-	SSYNC();
-}
-
-/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
- */
-#define MAP_NOCACHE	(0)
-#define MAP_WRCOMBINE	(0)
-#define MAP_WRBACK	(0)
-#define MAP_WRTHROUGH	(0)
-
-static inline void *
-map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
-{
-	return (void *)paddr;
-}
-
-/*
- * Take down a mapping set up by map_physmem().
- */
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-
-}
-
-static inline phys_addr_t virt_to_phys(void * vaddr)
-{
-	return (phys_addr_t)(vaddr);
-}
-
-/*
- * These are for ISA/PCI shared memory _only_ and should never be used
- * on any other type of memory, including Zorro memory. They are meant to
- * access the bus in the bus byte order which is little-endian!.
- *
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the bfin architecture, we just read/write the
- * memory location directly.
- */
-#ifndef __ASSEMBLY__
-
-static inline unsigned char readb(const volatile void __iomem *addr)
-{
-	unsigned int val;
-	int tmp;
-
-	__asm__ __volatile__ (
-		"cli %1;"
-		"NOP; NOP; SSYNC;"
-		"%0 = b [%2] (z);"
-		"sti %1;"
-		: "=d"(val), "=d"(tmp)
-		: "a"(addr)
-	);
-
-	return (unsigned char) val;
-}
-
-static inline unsigned short readw(const volatile void __iomem *addr)
-{
-	unsigned int val;
-	int tmp;
-
-	__asm__ __volatile__ (
-		"cli %1;"
-		"NOP; NOP; SSYNC;"
-		"%0 = w [%2] (z);"
-		"sti %1;"
-		: "=d"(val), "=d"(tmp)
-		: "a"(addr)
-	);
-
-	return (unsigned short) val;
-}
-
-static inline unsigned int readl(const volatile void __iomem *addr)
-{
-	unsigned int val;
-	int tmp;
-
-	__asm__ __volatile__ (
-		"cli %1;"
-		"NOP; NOP; SSYNC;"
-		"%0 = [%2];"
-		"sti %1;"
-		: "=d"(val), "=d"(tmp)
-		: "a"(addr)
-	);
-
-	return val;
-}
-
-#endif /*  __ASSEMBLY__ */
-
-#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-#define memset_io(a, b, c)	memset((void *)(a), (b), (c))
-#define memcpy_fromio(a, b, c)	memcpy((a), (void *)(b), (c))
-#define memcpy_toio(a, b, c)	memcpy((void *)(a), (b), (c))
-
-/* Convert "I/O port addresses" to actual addresses.  i.e. ugly casts. */
-#define __io(port) ((void *)(unsigned long)(port))
-
-#define inb(port)    readb(__io(port))
-#define inw(port)    readw(__io(port))
-#define inl(port)    readl(__io(port))
-#define in_le32(port) inl(port)
-#define outb(x, port) writeb(x, __io(port))
-#define outw(x, port) writew(x, __io(port))
-#define outl(x, port) writel(x, __io(port))
-#define out_le32(x, port) outl(x, port)
-
-#define inb_p(port)    inb(__io(port))
-#define inw_p(port)    inw(__io(port))
-#define inl_p(port)    inl(__io(port))
-#define outb_p(x, port) outb(x, __io(port))
-#define outw_p(x, port) outw(x, __io(port))
-#define outl_p(x, port) outl(x, __io(port))
-
-#define ioread8_rep(a, d, c)	readsb(a, d, c)
-#define ioread16_rep(a, d, c)	readsw(a, d, c)
-#define ioread32_rep(a, d, c)	readsl(a, d, c)
-#define iowrite8_rep(a, s, c)	writesb(a, s, c)
-#define iowrite16_rep(a, s, c)	writesw(a, s, c)
-#define iowrite32_rep(a, s, c)	writesl(a, s, c)
-
-#define ioread8(x)			readb(x)
-#define ioread16(x)			readw(x)
-#define ioread32(x)			readl(x)
-#define iowrite8(val, x)		writeb(val, x)
-#define iowrite16(val, x)		writew(val, x)
-#define iowrite32(val, x)		writel(val, x)
-
-#define mmiowb() wmb()
-
-#ifndef __ASSEMBLY__
-
-extern void outsb(unsigned long port, const void *addr, unsigned long count);
-extern void outsw(unsigned long port, const void *addr, unsigned long count);
-extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
-extern void outsl(unsigned long port, const void *addr, unsigned long count);
-
-extern void insb(unsigned long port, void *addr, unsigned long count);
-extern void insw(unsigned long port, void *addr, unsigned long count);
-extern void insw_8(unsigned long port, void *addr, unsigned long count);
-extern void insl(unsigned long port, void *addr, unsigned long count);
-extern void insl_16(unsigned long port, void *addr, unsigned long count);
-
-static inline void readsl(const void __iomem *addr, void *buf, int len)
-{
-	insl((unsigned long)addr, buf, len);
-}
-
-static inline void readsw(const void __iomem *addr, void *buf, int len)
-{
-	insw((unsigned long)addr, buf, len);
-}
-
-static inline void readsb(const void __iomem *addr, void *buf, int len)
-{
-	insb((unsigned long)addr, buf, len);
-}
-
-static inline void writesl(const void __iomem *addr, const void *buf, int len)
-{
-	outsl((unsigned long)addr, buf, len);
-}
-
-static inline void writesw(const void __iomem *addr, const void *buf, int len)
-{
-	outsw((unsigned long)addr, buf, len);
-}
-
-static inline void writesb(const void __iomem *addr, const void *buf, int len)
-{
-	outsb((unsigned long)addr, buf, len);
-}
-
-#if defined(CONFIG_STAMP_CF) || defined(CONFIG_BFIN_IDE)
-/* This hack for CF/IDE needs to be addressed at some point */
-extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
-extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
-extern unsigned char cf_inb(volatile unsigned char *addr);
-extern void cf_outb(unsigned char val, volatile unsigned char *addr);
-#undef inb
-#undef outb
-#undef insw
-#undef outsw
-#define inb(addr) cf_inb((void *)(addr))
-#define outb(x, addr) cf_outb((unsigned char)(x), (void *)(addr))
-#define insw(port, addr, cnt) cf_insw((void *)(addr), (void *)(port), cnt)
-#define outsw(port, addr, cnt) cf_outsw((void *)(port), (void *)(addr), cnt)
-#endif
-
-#endif
-
-#endif				/* __KERNEL__ */
-
-#endif
diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h
deleted file mode 100644
index 60d5317..0000000
--- a/arch/blackfin/include/asm/linkage.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * U-Boot - linkage.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf506/BF504_cdef.h b/arch/blackfin/include/asm/mach-bf506/BF504_cdef.h
deleted file mode 100644
index 27864e5..0000000
--- a/arch/blackfin/include/asm/mach-bf506/BF504_cdef.h
+++ /dev/null
@@ -1,1782 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF504_proc__
-#define __BFIN_CDEF_ADSP_BF504_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MODE() bfin_read16(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val) bfin_write16(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
-#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val)
-#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val)
-#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
-#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val)
-#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val)
-#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val)
-#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val)
-#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val)
-#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val)
-#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val)
-#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val)
-#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val)
-#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val)
-#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val)
-#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val)
-#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val)
-#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val)
-#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val)
-#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val)
-#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val)
-#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val)
-#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val)
-#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val)
-#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val)
-#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val)
-#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val)
-#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val)
-#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val)
-#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val)
-#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val)
-#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val)
-#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val)
-#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val)
-#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val)
-#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val)
-#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val)
-#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val)
-#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val)
-#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION)
-#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val)
-#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val)
-#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val)
-#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val)
-#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val)
-#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val)
-#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val)
-#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val)
-#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2)
-#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val)
-#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val)
-#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val)
-#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val)
-#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val)
-#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val)
-#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val)
-#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val)
-#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val)
-#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val)
-#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val)
-#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val)
-#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val)
-#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val)
-#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val)
-#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val)
-#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val)
-#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val)
-#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val)
-#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val)
-#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val)
-#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val)
-#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val)
-#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val)
-#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val)
-#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val)
-#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val)
-#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val)
-#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val)
-#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val)
-#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val)
-#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val)
-#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val)
-#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val)
-#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val)
-#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val)
-#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val)
-#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val)
-#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val)
-#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val)
-#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val)
-#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val)
-#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val)
-#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val)
-#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val)
-#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val)
-#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val)
-#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val)
-#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val)
-#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val)
-#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val)
-#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val)
-#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val)
-#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val)
-#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val)
-#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val)
-#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val)
-#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val)
-#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val)
-#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val)
-#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val)
-#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val)
-#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val)
-#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val)
-#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val)
-#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
-#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
-#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
-#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
-#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
-#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val)
-#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val)
-#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
-#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
-#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
-#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
-#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
-#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val)
-#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val)
-#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
-#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
-#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
-#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
-#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
-#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val)
-#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val)
-#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
-#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
-#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
-#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
-#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
-#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val)
-#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val)
-#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
-#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
-#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
-#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
-#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
-#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val)
-#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val)
-#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
-#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
-#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
-#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
-#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
-#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val)
-#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val)
-#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
-#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
-#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
-#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
-#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
-#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val)
-#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val)
-#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
-#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
-#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
-#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
-#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
-#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val)
-#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val)
-#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
-#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
-#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
-#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
-#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
-#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val)
-#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val)
-#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
-#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
-#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
-#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
-#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
-#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val)
-#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val)
-#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
-#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
-#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
-#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
-#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
-#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val)
-#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val)
-#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
-#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
-#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
-#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
-#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
-#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val)
-#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val)
-#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
-#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
-#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
-#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
-#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
-#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val)
-#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val)
-#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
-#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
-#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
-#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
-#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
-#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val)
-#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val)
-#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
-#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
-#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
-#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
-#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
-#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val)
-#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val)
-#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
-#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
-#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
-#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
-#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
-#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val)
-#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val)
-#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
-#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
-#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
-#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
-#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
-#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val)
-#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val)
-#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
-#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
-#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
-#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
-#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
-#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val)
-#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val)
-#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
-#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
-#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
-#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
-#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
-#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val)
-#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val)
-#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
-#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
-#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
-#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
-#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
-#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val)
-#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val)
-#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
-#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
-#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
-#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
-#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
-#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val)
-#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val)
-#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
-#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
-#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
-#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
-#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
-#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val)
-#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val)
-#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
-#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
-#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
-#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
-#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
-#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val)
-#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val)
-#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
-#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
-#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
-#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
-#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
-#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val)
-#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val)
-#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
-#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
-#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
-#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
-#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
-#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val)
-#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val)
-#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
-#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
-#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
-#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
-#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
-#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val)
-#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val)
-#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
-#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
-#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
-#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
-#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
-#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val)
-#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val)
-#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
-#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
-#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
-#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
-#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
-#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val)
-#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val)
-#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
-#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
-#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
-#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
-#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
-#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val)
-#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val)
-#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
-#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
-#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
-#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
-#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
-#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val)
-#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val)
-#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
-#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
-#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
-#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
-#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
-#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val)
-#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val)
-#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
-#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
-#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
-#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
-#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
-#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val)
-#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
-#define bfin_read_PWM1_CTRL() bfin_read16(PWM1_CTRL)
-#define bfin_write_PWM1_CTRL(val) bfin_write16(PWM1_CTRL, val)
-#define bfin_read_PWM1_STAT() bfin_read16(PWM1_STAT)
-#define bfin_write_PWM1_STAT(val) bfin_write16(PWM1_STAT, val)
-#define bfin_read_PWM1_TM() bfin_read16(PWM1_TM)
-#define bfin_write_PWM1_TM(val) bfin_write16(PWM1_TM, val)
-#define bfin_read_PWM1_DT() bfin_read16(PWM1_DT)
-#define bfin_write_PWM1_DT(val) bfin_write16(PWM1_DT, val)
-#define bfin_read_PWM1_GATE() bfin_read16(PWM1_GATE)
-#define bfin_write_PWM1_GATE(val) bfin_write16(PWM1_GATE, val)
-#define bfin_read_PWM1_CHA() bfin_read16(PWM1_CHA)
-#define bfin_write_PWM1_CHA(val) bfin_write16(PWM1_CHA, val)
-#define bfin_read_PWM1_CHB() bfin_read16(PWM1_CHB)
-#define bfin_write_PWM1_CHB(val) bfin_write16(PWM1_CHB, val)
-#define bfin_read_PWM1_CHC() bfin_read16(PWM1_CHC)
-#define bfin_write_PWM1_CHC(val) bfin_write16(PWM1_CHC, val)
-#define bfin_read_PWM1_SEG() bfin_read16(PWM1_SEG)
-#define bfin_write_PWM1_SEG(val) bfin_write16(PWM1_SEG, val)
-#define bfin_read_PWM1_SYNCWT() bfin_read16(PWM1_SYNCWT)
-#define bfin_write_PWM1_SYNCWT(val) bfin_write16(PWM1_SYNCWT, val)
-#define bfin_read_PWM1_CHAL() bfin_read16(PWM1_CHAL)
-#define bfin_write_PWM1_CHAL(val) bfin_write16(PWM1_CHAL, val)
-#define bfin_read_PWM1_CHBL() bfin_read16(PWM1_CHBL)
-#define bfin_write_PWM1_CHBL(val) bfin_write16(PWM1_CHBL, val)
-#define bfin_read_PWM1_CHCL() bfin_read16(PWM1_CHCL)
-#define bfin_write_PWM1_CHCL(val) bfin_write16(PWM1_CHCL, val)
-#define bfin_read_PWM1_LSI() bfin_read16(PWM1_LSI)
-#define bfin_write_PWM1_LSI(val) bfin_write16(PWM1_LSI, val)
-#define bfin_read_PWM1_STAT2() bfin_read16(PWM1_STAT2)
-#define bfin_write_PWM1_STAT2(val) bfin_write16(PWM1_STAT2, val)
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_NONGPIO_DRIVE() bfin_read16(NONGPIO_DRIVE)
-#define bfin_write_NONGPIO_DRIVE(val) bfin_write16(NONGPIO_DRIVE, val)
-#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
-#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
-#define bfin_read_FLASH_CONTROL() bfin_read16(FLASH_CONTROL)
-#define bfin_write_FLASH_CONTROL(val) bfin_write16(FLASH_CONTROL, val)
-#define bfin_read_FLASH_CONTROL_SET() bfin_read16(FLASH_CONTROL_SET)
-#define bfin_write_FLASH_CONTROL_SET(val) bfin_write16(FLASH_CONTROL_SET, val)
-#define bfin_read_FLASH_CONTROL_CLEAR() bfin_read16(FLASH_CONTROL_CLEAR)
-#define bfin_write_FLASH_CONTROL_CLEAR(val) bfin_write16(FLASH_CONTROL_CLEAR, val)
-#define bfin_read_CNT1_CONFIG() bfin_read16(CNT1_CONFIG)
-#define bfin_write_CNT1_CONFIG(val) bfin_write16(CNT1_CONFIG, val)
-#define bfin_read_CNT1_IMASK() bfin_read16(CNT1_IMASK)
-#define bfin_write_CNT1_IMASK(val) bfin_write16(CNT1_IMASK, val)
-#define bfin_read_CNT1_STATUS() bfin_read16(CNT1_STATUS)
-#define bfin_write_CNT1_STATUS(val) bfin_write16(CNT1_STATUS, val)
-#define bfin_read_CNT1_COMMAND() bfin_read16(CNT1_COMMAND)
-#define bfin_write_CNT1_COMMAND(val) bfin_write16(CNT1_COMMAND, val)
-#define bfin_read_CNT1_DEBOUNCE() bfin_read16(CNT1_DEBOUNCE)
-#define bfin_write_CNT1_DEBOUNCE(val) bfin_write16(CNT1_DEBOUNCE, val)
-#define bfin_read_CNT1_COUNTER() bfin_read32(CNT1_COUNTER)
-#define bfin_write_CNT1_COUNTER(val) bfin_write32(CNT1_COUNTER, val)
-#define bfin_read_CNT1_MAX() bfin_read32(CNT1_MAX)
-#define bfin_write_CNT1_MAX(val) bfin_write32(CNT1_MAX, val)
-#define bfin_read_CNT1_MIN() bfin_read32(CNT1_MIN)
-#define bfin_write_CNT1_MIN(val) bfin_write32(CNT1_MIN, val)
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_CNT0_CONFIG() bfin_read16(CNT0_CONFIG)
-#define bfin_write_CNT0_CONFIG(val) bfin_write16(CNT0_CONFIG, val)
-#define bfin_read_CNT0_IMASK() bfin_read16(CNT0_IMASK)
-#define bfin_write_CNT0_IMASK(val) bfin_write16(CNT0_IMASK, val)
-#define bfin_read_CNT0_STATUS() bfin_read16(CNT0_STATUS)
-#define bfin_write_CNT0_STATUS(val) bfin_write16(CNT0_STATUS, val)
-#define bfin_read_CNT0_COMMAND() bfin_read16(CNT0_COMMAND)
-#define bfin_write_CNT0_COMMAND(val) bfin_write16(CNT0_COMMAND, val)
-#define bfin_read_CNT0_DEBOUNCE() bfin_read16(CNT0_DEBOUNCE)
-#define bfin_write_CNT0_DEBOUNCE(val) bfin_write16(CNT0_DEBOUNCE, val)
-#define bfin_read_CNT0_COUNTER() bfin_read32(CNT0_COUNTER)
-#define bfin_write_CNT0_COUNTER(val) bfin_write32(CNT0_COUNTER, val)
-#define bfin_read_CNT0_MAX() bfin_read32(CNT0_MAX)
-#define bfin_write_CNT0_MAX(val) bfin_write32(CNT0_MAX, val)
-#define bfin_read_CNT0_MIN() bfin_read32(CNT0_MIN)
-#define bfin_write_CNT0_MIN(val) bfin_write32(CNT0_MIN, val)
-#define bfin_read_PWM0_CTRL() bfin_read16(PWM0_CTRL)
-#define bfin_write_PWM0_CTRL(val) bfin_write16(PWM0_CTRL, val)
-#define bfin_read_PWM0_STAT() bfin_read16(PWM0_STAT)
-#define bfin_write_PWM0_STAT(val) bfin_write16(PWM0_STAT, val)
-#define bfin_read_PWM0_TM() bfin_read16(PWM0_TM)
-#define bfin_write_PWM0_TM(val) bfin_write16(PWM0_TM, val)
-#define bfin_read_PWM0_DT() bfin_read16(PWM0_DT)
-#define bfin_write_PWM0_DT(val) bfin_write16(PWM0_DT, val)
-#define bfin_read_PWM0_GATE() bfin_read16(PWM0_GATE)
-#define bfin_write_PWM0_GATE(val) bfin_write16(PWM0_GATE, val)
-#define bfin_read_PWM0_CHA() bfin_read16(PWM0_CHA)
-#define bfin_write_PWM0_CHA(val) bfin_write16(PWM0_CHA, val)
-#define bfin_read_PWM0_CHB() bfin_read16(PWM0_CHB)
-#define bfin_write_PWM0_CHB(val) bfin_write16(PWM0_CHB, val)
-#define bfin_read_PWM0_CHC() bfin_read16(PWM0_CHC)
-#define bfin_write_PWM0_CHC(val) bfin_write16(PWM0_CHC, val)
-#define bfin_read_PWM0_SEG() bfin_read16(PWM0_SEG)
-#define bfin_write_PWM0_SEG(val) bfin_write16(PWM0_SEG, val)
-#define bfin_read_PWM0_SYNCWT() bfin_read16(PWM0_SYNCWT)
-#define bfin_write_PWM0_SYNCWT(val) bfin_write16(PWM0_SYNCWT, val)
-#define bfin_read_PWM0_CHAL() bfin_read16(PWM0_CHAL)
-#define bfin_write_PWM0_CHAL(val) bfin_write16(PWM0_CHAL, val)
-#define bfin_read_PWM0_CHBL() bfin_read16(PWM0_CHBL)
-#define bfin_write_PWM0_CHBL(val) bfin_write16(PWM0_CHBL, val)
-#define bfin_read_PWM0_CHCL() bfin_read16(PWM0_CHCL)
-#define bfin_write_PWM0_CHCL(val) bfin_write16(PWM0_CHCL, val)
-#define bfin_read_PWM0_LSI() bfin_read16(PWM0_LSI)
-#define bfin_write_PWM0_LSI(val) bfin_write16(PWM0_LSI, val)
-#define bfin_read_PWM0_STAT2() bfin_read16(PWM0_STAT2)
-#define bfin_write_PWM0_STAT2(val) bfin_write16(PWM0_STAT2, val)
-#define bfin_read_RSI_PWR_CONTROL() bfin_read16(RSI_PWR_CONTROL)
-#define bfin_write_RSI_PWR_CONTROL(val) bfin_write16(RSI_PWR_CONTROL, val)
-#define bfin_read_RSI_CLK_CONTROL() bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CONTROL() bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUSCL() bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUSCL(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_ESTAT() bfin_read16(RSI_ESTAT)
-#define bfin_write_RSI_ESTAT(val) bfin_write16(RSI_ESTAT, val)
-#define bfin_read_RSI_EMASK() bfin_read16(RSI_EMASK)
-#define bfin_write_RSI_EMASK(val) bfin_write16(RSI_EMASK, val)
-#define bfin_read_RSI_CONFIG() bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CONFIG(val) bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
-#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF504_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf506/BF504_def.h b/arch/blackfin/include/asm/mach-bf506/BF504_def.h
deleted file mode 100644
index 8b0345f..0000000
--- a/arch/blackfin/include/asm/mach-bf506/BF504_def.h
+++ /dev/null
@@ -1,944 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF504_proc__
-#define __BFIN_DEF_ADSP_BF504_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SIC_RVECT                      0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK0                     0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0                       0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0                       0xFFC00124 /* Interrupt Wakeup Register */
-#define SIC_IMASK1                     0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4                       0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5                       0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6                       0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7                       0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1                       0xFFC00160 /* Interrupt Status register */
-#define SIC_IWR1                       0xFFC00164 /* Interrupt Wakeup register */
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
-#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
-#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
-#define UART0_LCR                      0xFFC0040C /* Line Control Register */
-#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
-#define UART0_LSR                      0xFFC00414 /* Line Status Register */
-#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
-#define UART0_SCR                      0xFFC0041C /* Scratch Register */
-#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
-#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
-#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
-#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag register */
-#define SPI0_STAT                      0xFFC00508 /* SPI0 Status register */
-#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud rate Register */
-#define SPI0_SHADOW                    0xFFC00518 /* SPI0_RDBR Shadow Register */
-#define TIMER0_CONFIG                  0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                  0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH                   0xFFC0060C /* Timer 0 Width Register */
-#define TIMER1_CONFIG                  0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER                 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD                  0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH                   0xFFC0061C /* Timer 1 Width Register */
-#define TIMER2_CONFIG                  0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER                 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD                  0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH                   0xFFC0062C /* Timer 2 Width Register */
-#define TIMER3_CONFIG                  0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER                 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD                  0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH                   0xFFC0063C /* Timer 3 Width Register */
-#define TIMER4_CONFIG                  0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER                 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD                  0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH                   0xFFC0064C /* Timer 4 Width Register */
-#define TIMER5_CONFIG                  0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER                 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD                  0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH                   0xFFC0065C /* Timer 5 Width Register */
-#define TIMER6_CONFIG                  0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER                 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD                  0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH                   0xFFC0066C /* Timer 6 Width Register\n */
-#define TIMER7_CONFIG                  0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER                 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD                  0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH                   0xFFC0067C /* Timer 7 Width Register */
-#define TIMER_ENABLE                   0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE                  0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS                   0xFFC00688 /* Timer Status Register */
-#define PORTFIO                        0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR                  0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET                    0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE                 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA                  0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR            0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET              0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE           0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB                  0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR            0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET              0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE           0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR                    0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR                  0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE                   0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH                   0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN                   0xFFC00740 /* Port F I/O Input Enable Register  */
-#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                      0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX                      0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                      0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX                      0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_MODE                      0xFFC00A20 /* Asynchronous Memory Mode Control Register */
-#define EBIU_FCTL                      0xFFC00A24 /* Asynchronous Memory Parameter Control Register */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR             0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG                 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT                0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY               0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT                0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR             0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG                 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT                0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY               0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT                0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR             0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG                 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT                0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR             0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG                 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT                0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY               0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT                0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define PPI_CONTROL                    0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS                     0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT                      0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY                      0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME                      0xFFC01010 /* PPI Frame Length Register */
-#define TWI_CLKDIV                     0xFFC01400 /* Serial Clock Divider Register */
-#define TWI_CONTROL                    0xFFC01404 /* TWI Control Register */
-#define TWI_SLAVE_CTL                  0xFFC01408 /* Slave Mode Control Register */
-#define TWI_SLAVE_STAT                 0xFFC0140C /* Slave Mode Status Register */
-#define TWI_SLAVE_ADDR                 0xFFC01410 /* Slave Mode Address Register */
-#define TWI_MASTER_CTL                 0xFFC01414 /* Master Mode Control Register */
-#define TWI_MASTER_STAT                0xFFC01418 /* Master Mode Status Register */
-#define TWI_MASTER_ADDR                0xFFC0141C /* Master Mode Address Register */
-#define TWI_INT_STAT                   0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI_INT_MASK                   0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI_FIFO_CTL                   0xFFC01428 /* FIFO Control Register */
-#define TWI_FIFO_STAT                  0xFFC0142C /* FIFO Status Register */
-#define TWI_XMT_DATA8                  0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI_XMT_DATA16                 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI_RCV_DATA8                  0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI_RCV_DATA16                 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-#define PORTGIO                        0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR                  0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET                    0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE                 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA                  0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR            0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET              0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE           0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB                  0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR            0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET              0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE           0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR                    0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR                  0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE                   0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH                   0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN                   0xFFC01540 /* Port G I/O Input Enable Register */
-#define PORTHIO                        0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR                  0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET                    0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE                 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA                  0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR            0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET              0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE           0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB                  0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR            0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET              0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE           0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR                    0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR                  0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE                   0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH                   0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN                   0xFFC01740 /* Port H I/O Input Enable Register */
-#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
-#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
-#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
-#define UART1_LCR                      0xFFC0200C /* Line Control Register */
-#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
-#define UART1_LSR                      0xFFC02014 /* Line Status Register */
-#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
-#define UART1_SCR                      0xFFC0201C /* Scratch Register */
-#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
-#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
-#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
-#define CAN_MC1                        0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN_MD1                        0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN_TRS1                       0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN_TRR1                       0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN_TA1                        0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN_AA1                        0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN_RMP1                       0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN_RML1                       0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN_MBTIF1                     0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN_MBRIF1                     0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN_MBIM1                      0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN_RFH1                       0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN_OPSS1                      0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN_MC2                        0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN_MD2                        0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN_TRS2                       0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN_TRR2                       0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN_TA2                        0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN_AA2                        0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN_RMP2                       0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN_RML2                       0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN_MBTIF2                     0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN_MBRIF2                     0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN_MBIM2                      0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN_RFH2                       0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN_OPSS2                      0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN_CLOCK                      0xFFC02A80 /* CAN Controller 0 Clock Register */
-#define CAN_TIMING                     0xFFC02A84 /* CAN Controller 0 Timing Register */
-#define CAN_DEBUG                      0xFFC02A88 /* CAN Controller 0 Debug Register */
-#define CAN_STATUS                     0xFFC02A8C /* CAN Controller 0 Global Status Register */
-#define CAN_CEC                        0xFFC02A90 /* CAN Controller 0 Error Counter Register */
-#define CAN_GIS                        0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN_GIM                        0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN_GIF                        0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN_CONTROL                    0xFFC02AA0 /* CAN Controller 0 Master Control Register */
-#define CAN_INTR                       0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN_MBTD                       0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN_EWR                        0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN_ESR                        0xFFC02AB4 /* CAN Controller 0 Error Status Register */
-#define CAN_UCCNT                      0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
-#define CAN_UCRC                       0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN_UCCNF                      0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
-#define CAN_AM00L                      0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN_AM00H                      0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN_AM01L                      0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN_AM01H                      0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN_AM02L                      0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN_AM02H                      0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN_AM03L                      0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN_AM03H                      0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN_AM04L                      0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN_AM04H                      0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN_AM05L                      0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN_AM05H                      0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN_AM06L                      0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN_AM06H                      0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN_AM07L                      0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN_AM07H                      0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN_AM08L                      0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN_AM08H                      0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN_AM09L                      0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN_AM09H                      0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN_AM10L                      0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN_AM10H                      0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN_AM11L                      0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN_AM11H                      0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN_AM12L                      0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN_AM12H                      0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN_AM13L                      0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN_AM13H                      0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN_AM14L                      0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN_AM14H                      0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN_AM15L                      0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN_AM15H                      0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-#define CAN_AM16L                      0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN_AM16H                      0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN_AM17L                      0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN_AM17H                      0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN_AM18L                      0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN_AM18H                      0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN_AM19L                      0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN_AM19H                      0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN_AM20L                      0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN_AM20H                      0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN_AM21L                      0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN_AM21H                      0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN_AM22L                      0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN_AM22H                      0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN_AM23L                      0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN_AM23H                      0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN_AM24L                      0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN_AM24H                      0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN_AM25L                      0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN_AM25H                      0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN_AM26L                      0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN_AM26H                      0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN_AM27L                      0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN_AM27H                      0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN_AM28L                      0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN_AM28H                      0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN_AM29L                      0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN_AM29H                      0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN_AM30L                      0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN_AM30H                      0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN_AM31L                      0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN_AM31H                      0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-#define CAN_MB00_DATA0                 0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN_MB00_DATA1                 0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN_MB00_DATA2                 0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN_MB00_DATA3                 0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN_MB00_LENGTH                0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN_MB00_TIMESTAMP             0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN_MB00_ID0                   0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN_MB00_ID1                   0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN_MB01_DATA0                 0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN_MB01_DATA1                 0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN_MB01_DATA2                 0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN_MB01_DATA3                 0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN_MB01_LENGTH                0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN_MB01_TIMESTAMP             0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN_MB01_ID0                   0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN_MB01_ID1                   0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN_MB02_DATA0                 0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN_MB02_DATA1                 0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN_MB02_DATA2                 0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN_MB02_DATA3                 0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN_MB02_LENGTH                0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN_MB02_TIMESTAMP             0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN_MB02_ID0                   0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN_MB02_ID1                   0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN_MB03_DATA0                 0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN_MB03_DATA1                 0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN_MB03_DATA2                 0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN_MB03_DATA3                 0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN_MB03_LENGTH                0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN_MB03_TIMESTAMP             0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN_MB03_ID0                   0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN_MB03_ID1                   0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN_MB04_DATA0                 0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN_MB04_DATA1                 0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN_MB04_DATA2                 0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN_MB04_DATA3                 0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN_MB04_LENGTH                0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN_MB04_TIMESTAMP             0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN_MB04_ID0                   0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN_MB04_ID1                   0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN_MB05_DATA0                 0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN_MB05_DATA1                 0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN_MB05_DATA2                 0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN_MB05_DATA3                 0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN_MB05_LENGTH                0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN_MB05_TIMESTAMP             0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN_MB05_ID0                   0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN_MB05_ID1                   0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN_MB06_DATA0                 0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN_MB06_DATA1                 0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN_MB06_DATA2                 0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN_MB06_DATA3                 0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN_MB06_LENGTH                0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN_MB06_TIMESTAMP             0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN_MB06_ID0                   0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN_MB06_ID1                   0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN_MB07_DATA0                 0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN_MB07_DATA1                 0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN_MB07_DATA2                 0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN_MB07_DATA3                 0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN_MB07_LENGTH                0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN_MB07_TIMESTAMP             0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN_MB07_ID0                   0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN_MB07_ID1                   0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN_MB08_DATA0                 0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN_MB08_DATA1                 0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN_MB08_DATA2                 0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN_MB08_DATA3                 0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN_MB08_LENGTH                0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN_MB08_TIMESTAMP             0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN_MB08_ID0                   0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN_MB08_ID1                   0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN_MB09_DATA0                 0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN_MB09_DATA1                 0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN_MB09_DATA2                 0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN_MB09_DATA3                 0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN_MB09_LENGTH                0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN_MB09_TIMESTAMP             0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN_MB09_ID0                   0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN_MB09_ID1                   0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN_MB10_DATA0                 0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN_MB10_DATA1                 0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN_MB10_DATA2                 0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN_MB10_DATA3                 0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN_MB10_LENGTH                0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN_MB10_TIMESTAMP             0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN_MB10_ID0                   0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN_MB10_ID1                   0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN_MB11_DATA0                 0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN_MB11_DATA1                 0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN_MB11_DATA2                 0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN_MB11_DATA3                 0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN_MB11_LENGTH                0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN_MB11_TIMESTAMP             0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN_MB11_ID0                   0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN_MB11_ID1                   0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN_MB12_DATA0                 0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN_MB12_DATA1                 0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN_MB12_DATA2                 0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN_MB12_DATA3                 0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN_MB12_LENGTH                0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN_MB12_TIMESTAMP             0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN_MB12_ID0                   0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN_MB12_ID1                   0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN_MB13_DATA0                 0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN_MB13_DATA1                 0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN_MB13_DATA2                 0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN_MB13_DATA3                 0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN_MB13_LENGTH                0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN_MB13_TIMESTAMP             0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN_MB13_ID0                   0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN_MB13_ID1                   0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN_MB14_DATA0                 0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN_MB14_DATA1                 0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN_MB14_DATA2                 0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN_MB14_DATA3                 0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN_MB14_LENGTH                0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN_MB14_TIMESTAMP             0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN_MB14_ID0                   0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN_MB14_ID1                   0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN_MB15_DATA0                 0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN_MB15_DATA1                 0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN_MB15_DATA2                 0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN_MB15_DATA3                 0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN_MB15_LENGTH                0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN_MB15_TIMESTAMP             0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN_MB15_ID0                   0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN_MB15_ID1                   0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
-#define CAN_MB16_DATA0                 0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN_MB16_DATA1                 0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN_MB16_DATA2                 0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN_MB16_DATA3                 0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN_MB16_LENGTH                0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN_MB16_TIMESTAMP             0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN_MB16_ID0                   0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN_MB16_ID1                   0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN_MB17_DATA0                 0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN_MB17_DATA1                 0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN_MB17_DATA2                 0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN_MB17_DATA3                 0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN_MB17_LENGTH                0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN_MB17_TIMESTAMP             0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN_MB17_ID0                   0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN_MB17_ID1                   0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN_MB18_DATA0                 0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN_MB18_DATA1                 0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN_MB18_DATA2                 0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN_MB18_DATA3                 0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN_MB18_LENGTH                0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN_MB18_TIMESTAMP             0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN_MB18_ID0                   0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN_MB18_ID1                   0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN_MB19_DATA0                 0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN_MB19_DATA1                 0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN_MB19_DATA2                 0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN_MB19_DATA3                 0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN_MB19_LENGTH                0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN_MB19_TIMESTAMP             0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN_MB19_ID0                   0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN_MB19_ID1                   0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN_MB20_DATA0                 0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN_MB20_DATA1                 0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN_MB20_DATA2                 0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN_MB20_DATA3                 0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN_MB20_LENGTH                0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN_MB20_TIMESTAMP             0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN_MB20_ID0                   0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN_MB20_ID1                   0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN_MB21_DATA0                 0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN_MB21_DATA1                 0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN_MB21_DATA2                 0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN_MB21_DATA3                 0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN_MB21_LENGTH                0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN_MB21_TIMESTAMP             0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN_MB21_ID0                   0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN_MB21_ID1                   0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN_MB22_DATA0                 0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN_MB22_DATA1                 0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN_MB22_DATA2                 0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN_MB22_DATA3                 0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN_MB22_LENGTH                0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN_MB22_TIMESTAMP             0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN_MB22_ID0                   0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN_MB22_ID1                   0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN_MB23_DATA0                 0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN_MB23_DATA1                 0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN_MB23_DATA2                 0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN_MB23_DATA3                 0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN_MB23_LENGTH                0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN_MB23_TIMESTAMP             0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN_MB23_ID0                   0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN_MB23_ID1                   0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN_MB24_DATA0                 0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN_MB24_DATA1                 0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN_MB24_DATA2                 0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN_MB24_DATA3                 0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN_MB24_LENGTH                0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN_MB24_TIMESTAMP             0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN_MB24_ID0                   0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN_MB24_ID1                   0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN_MB25_DATA0                 0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN_MB25_DATA1                 0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN_MB25_DATA2                 0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN_MB25_DATA3                 0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN_MB25_LENGTH                0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN_MB25_TIMESTAMP             0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN_MB25_ID0                   0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN_MB25_ID1                   0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN_MB26_DATA0                 0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN_MB26_DATA1                 0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN_MB26_DATA2                 0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN_MB26_DATA3                 0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN_MB26_LENGTH                0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN_MB26_TIMESTAMP             0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN_MB26_ID0                   0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN_MB26_ID1                   0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN_MB27_DATA0                 0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN_MB27_DATA1                 0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN_MB27_DATA2                 0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN_MB27_DATA3                 0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN_MB27_LENGTH                0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN_MB27_TIMESTAMP             0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN_MB27_ID0                   0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN_MB27_ID1                   0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN_MB28_DATA0                 0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN_MB28_DATA1                 0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN_MB28_DATA2                 0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN_MB28_DATA3                 0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN_MB28_LENGTH                0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN_MB28_TIMESTAMP             0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN_MB28_ID0                   0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN_MB28_ID1                   0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN_MB29_DATA0                 0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN_MB29_DATA1                 0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN_MB29_DATA2                 0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN_MB29_DATA3                 0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN_MB29_LENGTH                0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN_MB29_TIMESTAMP             0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN_MB29_ID0                   0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN_MB29_ID1                   0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN_MB30_DATA0                 0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN_MB30_DATA1                 0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN_MB30_DATA2                 0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN_MB30_DATA3                 0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN_MB30_LENGTH                0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN_MB30_TIMESTAMP             0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN_MB30_ID0                   0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN_MB30_ID1                   0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN_MB31_DATA0                 0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN_MB31_DATA1                 0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN_MB31_DATA2                 0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN_MB31_DATA3                 0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN_MB31_LENGTH                0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN_MB31_TIMESTAMP             0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN_MB31_ID0                   0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN_MB31_ID1                   0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
-#define PWM1_CTRL                      0xFFC03000 /* PWM1 Control Register */
-#define PWM1_STAT                      0xFFC03004 /* PWM1 Status Register */
-#define PWM1_TM                        0xFFC03008 /* PWM1 Period Register */
-#define PWM1_DT                        0xFFC0300C /* PWM1 Dead Time Register */
-#define PWM1_GATE                      0xFFC03010 /* PWM1 Chopping Control */
-#define PWM1_CHA                       0xFFC03014 /* PWM1 Channel A Duty Control */
-#define PWM1_CHB                       0xFFC03018 /* PWM1 Channel B Duty Control */
-#define PWM1_CHC                       0xFFC0301C /* PWM1 Channel C Duty Control */
-#define PWM1_SEG                       0xFFC03020 /* PWM1 Crossover and Output Enable */
-#define PWM1_SYNCWT                    0xFFC03024 /* PWM1 Sync pulse width control */
-#define PWM1_CHAL                      0xFFC03028 /* PWM1 Channel AL Duty Control (SR mode only) */
-#define PWM1_CHBL                      0xFFC0302C /* PWM1 Channel BL Duty Control (SR mode only) */
-#define PWM1_CHCL                      0xFFC03030 /* PWM1 Channel CL Duty Control (SR mode only) */
-#define PWM1_LSI                       0xFFC03034 /* Low Side Invert (SR mode only) */
-#define PWM1_STAT2                     0xFFC03038 /* PWM1 Status Register */
-#define ACM_CTL                        0xFFC03100 /* ACM Control Register */
-#define ACM_TC0                        0xFFC03104 /* ACM Timing Configuration 0 Register */
-#define ACM_TC1                        0xFFC03108 /* ACM Timing Configuration 1 Register */
-#define ACM_STAT                       0xFFC0310C /* ACM Status Register */
-#define ACM_ES                         0xFFC03110 /* ACM Event Status Register */
-#define ACM_IMSK                       0xFFC03114 /* ACM Interrupt Mask Register */
-#define ACM_MS                         0xFFC03118 /* ACM Missed Event Status Register */
-#define ACM_EMSK                       0xFFC0311C /* ACM Missed Event Interrupt Mask Register */
-#define ACM_ER0                        0xFFC03120 /* ACM Event 0 Control Register */
-#define ACM_ER1                        0xFFC03124 /* ACM Event 1 Control Register */
-#define ACM_ER2                        0xFFC03128 /* ACM Event 2 Control Register */
-#define ACM_ER3                        0xFFC0312C /* ACM Event 3 Control Register */
-#define ACM_ER4                        0xFFC03130 /* ACM Event 4 Control Register */
-#define ACM_ER5                        0xFFC03134 /* ACM Event 5 Control Register */
-#define ACM_ER6                        0xFFC03138 /* ACM Event 6 Control Register */
-#define ACM_ER7                        0xFFC0313C /* ACM Event 7 Control Register */
-#define ACM_ER8                        0xFFC03140 /* ACM Event 8 Control Register */
-#define ACM_ER9                        0xFFC03144 /* ACM Event 9 Control Register */
-#define ACM_ER10                       0xFFC03148 /* ACM Event 10 Control Register */
-#define ACM_ER11                       0xFFC0314C /* ACM Event 11 Control Register */
-#define ACM_ER12                       0xFFC03150 /* ACM Event 12 Control Register */
-#define ACM_ER13                       0xFFC03154 /* ACM Event 13 Control Register */
-#define ACM_ER14                       0xFFC03158 /* ACM Event 14 Control Register */
-#define ACM_ER15                       0xFFC0315C /* ACM Event 15 Control Register */
-#define ACM_ET0                        0xFFC03180 /* ACM Event 0 Time Register */
-#define ACM_ET1                        0xFFC03184 /* ACM Event 1 Time Register */
-#define ACM_ET2                        0xFFC03188 /* ACM Event 2 Time Register */
-#define ACM_ET3                        0xFFC0318C /* ACM Event 3 Time Register */
-#define ACM_ET4                        0xFFC03190 /* ACM Event 4 Time Register */
-#define ACM_ET5                        0xFFC03194 /* ACM Event 5 Time Register */
-#define ACM_ET6                        0xFFC03198 /* ACM Event 6 Time Register */
-#define ACM_ET7                        0xFFC0319C /* ACM Event 7 Time Register */
-#define ACM_ET8                        0xFFC031A0 /* ACM Event 8 Time Register */
-#define ACM_ET9                        0xFFC031A4 /* ACM Event 9 Time Register */
-#define ACM_ET10                       0xFFC031A8 /* ACM Event 10 Time Register */
-#define ACM_ET11                       0xFFC031AC /* ACM Event 11 Time Register */
-#define ACM_ET12                       0xFFC031B0 /* ACM Event 12 Time Register */
-#define ACM_ET13                       0xFFC031B4 /* ACM Event 13 Time Register */
-#define ACM_ET14                       0xFFC031B8 /* ACM Event 14 Time Register */
-#define ACM_ET15                       0xFFC031BC /* ACM Event 15 Time Register */
-#define ACM_TMR0                       0xFFC031C0 /* ACM Timer 0 Registers */
-#define ACM_TMR1                       0xFFC031C4 /* ACM Timer 1 Registers */
-#define PORTF_FER                      0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER                      0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER                      0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define PORTF_MUX                      0xFFC03210 /* Port F mux control */
-#define PORTG_MUX                      0xFFC03214 /* Port G mux control */
-#define PORTH_MUX                      0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE                    0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE                    0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE                    0xFFC03228 /* Port H drive strength control */
-#define PORTF_HYSTERESIS               0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS               0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS               0xFFC03248 /* Port H Schmitt trigger control */
-#define NONGPIO_DRIVE                  0xFFC03280 /* Non-GPIO Port drive strength control */
-#define NONGPIO_HYSTERESIS             0xFFC03288 /* Non-GPIO Port Schmitt trigger control */
-#define FLASH_CONTROL                  0xFFC0328C /* Stacked flash control register */
-#define FLASH_CONTROL_SET              0xFFC03290 /* Stacked flash control set register */
-#define FLASH_CONTROL_CLEAR            0xFFC03294 /* Stacked flash control clear register */
-#define CNT1_CONFIG                    0xFFC03300 /* Counter 1 Configuration Register */
-#define CNT1_IMASK                     0xFFC03304 /* Counter 1 Interrupt Mask Register */
-#define CNT1_STATUS                    0xFFC03308 /* Counter 1 Status Register */
-#define CNT1_COMMAND                   0xFFC0330C /* Counter 1 Command Register */
-#define CNT1_DEBOUNCE                  0xFFC03310 /* Counter 1 Debounce Register */
-#define CNT1_COUNTER                   0xFFC03314 /* Counter 1 Counter Register */
-#define CNT1_MAX                       0xFFC03318 /* Counter 1 Boundry Value Register - max count */
-#define CNT1_MIN                       0xFFC0331C /* Counter 1 Boundry Value Register - min count */
-#define SPI1_CTL                       0xFFC03400 /* SPI1 Control */
-#define SPI1_FLG                       0xFFC03404 /* SPI1 Flag Register */
-#define SPI1_STAT                      0xFFC03408 /* SPI1 Status Register */
-#define SPI1_TDBR                      0xFFC0340C /* SPI1 Transmit Data Buffer */
-#define SPI1_RDBR                      0xFFC03410 /* SPI1 Receive Data Buffer */
-#define SPI1_BAUD                      0xFFC03414 /* SPI1 Baud Rate */
-#define SPI1_SHADOW                    0xFFC03418 /* SPI1_RDBR Shadow Register */
-#define CNT0_CONFIG                    0xFFC03500 /* Configuration/Control Register */
-#define CNT0_IMASK                     0xFFC03504 /* Interrupt Mask Register */
-#define CNT0_STATUS                    0xFFC03508 /* Status Register */
-#define CNT0_COMMAND                   0xFFC0350C /* Command Register */
-#define CNT0_DEBOUNCE                  0xFFC03510 /* Debounce Prescaler Register */
-#define CNT0_COUNTER                   0xFFC03514 /* Counter Register */
-#define CNT0_MAX                       0xFFC03518 /* Maximal Count Boundary Value Register */
-#define CNT0_MIN                       0xFFC0351C /* Minimal Count Boundary Value Register */
-#define PWM0_CTRL                      0xFFC03700 /* PWM Control Register */
-#define PWM0_STAT                      0xFFC03704 /* PWM Status Register */
-#define PWM0_TM                        0xFFC03708 /* PWM Period Register */
-#define PWM0_DT                        0xFFC0370C /* PWM Dead Time Register */
-#define PWM0_GATE                      0xFFC03710 /* PWM Chopping Control */
-#define PWM0_CHA                       0xFFC03714 /* PWM Channel A Duty Control */
-#define PWM0_CHB                       0xFFC03718 /* PWM Channel B Duty Control */
-#define PWM0_CHC                       0xFFC0371C /* PWM Channel C Duty Control */
-#define PWM0_SEG                       0xFFC03720 /* PWM Crossover and Output Enable */
-#define PWM0_SYNCWT                    0xFFC03724 /* PWM Sync pulse width control */
-#define PWM0_CHAL                      0xFFC03728 /* PWM Channel AL Duty Control (SR mode only) */
-#define PWM0_CHBL                      0xFFC0372C /* PWM Channel BL Duty Control (SR mode only) */
-#define PWM0_CHCL                      0xFFC03730 /* PWM Channel CL Duty Control (SR mode only) */
-#define PWM0_LSI                       0xFFC03734 /* Low Side Invert (SR mode only) */
-#define PWM0_STAT2                     0xFFC03738 /* PWM Status Register */
-#define RSI_PWR_CONTROL                0xFFC03800 /* RSI Power Control Register */
-#define RSI_CLK_CONTROL                0xFFC03804 /* RSI Clock Control Register */
-#define RSI_ARGUMENT                   0xFFC03808 /* RSI Argument Register */
-#define RSI_COMMAND                    0xFFC0380C /* RSI Command Register */
-#define RSI_RESP_CMD                   0xFFC03810 /* RSI Response Command Register */
-#define RSI_RESPONSE0                  0xFFC03814 /* RSI Response Register */
-#define RSI_RESPONSE1                  0xFFC03818 /* RSI Response Register */
-#define RSI_RESPONSE2                  0xFFC0381C /* RSI Response Register */
-#define RSI_RESPONSE3                  0xFFC03820 /* RSI Response Register */
-#define RSI_DATA_TIMER                 0xFFC03824 /* RSI Data Timer Register */
-#define RSI_DATA_LGTH                  0xFFC03828 /* RSI Data Length Register */
-#define RSI_DATA_CONTROL               0xFFC0382C /* RSI Data Control Register */
-#define RSI_DATA_CNT                   0xFFC03830 /* RSI Data Counter Register */
-#define RSI_STATUS                     0xFFC03834 /* RSI Status Register */
-#define RSI_STATUSCL                   0xFFC03838 /* RSI Status Clear Register */
-#define RSI_MASK0                      0xFFC0383C /* RSI Interrupt 0 Mask Register */
-#define RSI_MASK1                      0xFFC03840 /* RSI Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT                   0xFFC03848 /* RSI FIFO Counter Register */
-#define RSI_CEATA_CONTROL              0xFFC0384C /* RSI CEATA Register */
-#define RSI_FIFO                       0xFFC03880 /* RSI Data FIFO Register */
-#define RSI_ESTAT                      0xFFC038C0 /* RSI Exception Status Register */
-#define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
-#define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
-#define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
-#define RSI_PID0                       0xFFC038D0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID1                       0xFFC038D4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID2                       0xFFC038D8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID3                       0xFFC038DC /* RSI Peripheral ID Register 3 */
-#define DMA_TC_CNT                     0xFFC00B0C
-#define DMA_TC_PER                     0xFFC00B10
-
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE 0x8000
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE 0x8000
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif /* __BFIN_DEF_ADSP_BF504_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf506/BF506_cdef.h b/arch/blackfin/include/asm/mach-bf506/BF506_cdef.h
deleted file mode 100644
index 4c5baac..0000000
--- a/arch/blackfin/include/asm/mach-bf506/BF506_cdef.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF506_proc__
-#define __BFIN_CDEF_ADSP_BF506_proc__
-
-#include "BF504_cdef.h"
-
-#endif /* __BFIN_CDEF_ADSP_BF506_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf506/BF506_def.h b/arch/blackfin/include/asm/mach-bf506/BF506_def.h
deleted file mode 100644
index 1f91397..0000000
--- a/arch/blackfin/include/asm/mach-bf506/BF506_def.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF506_proc__
-#define __BFIN_DEF_ADSP_BF506_proc__
-
-#include "BF504_def.h"
-
-#endif /* __BFIN_DEF_ADSP_BF506_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf506/anomaly.h b/arch/blackfin/include/asm/mach-bf506/anomaly.h
deleted file mode 100644
index 5b3227a..0000000
--- a/arch/blackfin/include/asm/mach-bf506/anomaly.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- *  - Revision A, 02/18/2011; ADSP-BF504/BF504F/BF506F Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF506 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* UART IrDA Receiver Fails on Extended Bit Pulses */
-#define ANOMALY_05000447 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* SPORT0 Data Transmit Error in Multi-Channel Mode with Internal Clock */
-#define ANOMALY_05000476 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Disabling ACM During an Ongoing Transfer Can Lead to Undefined ACM Behavior */
-#define ANOMALY_05000478 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* TWI Vbus Minimum Specification Can Be Violated under Certain Conditions */
-#define ANOMALY_05000486 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* Maximum Idd-deepsleep Specifications Can Be Exceeded under Certain Conditions */
-#define ANOMALY_05000495 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (0)
-#define ANOMALY_05000357 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000371 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf506/def_local.h b/arch/blackfin/include/asm/mach-bf506/def_local.h
deleted file mode 100644
index e7a416d..0000000
--- a/arch/blackfin/include/asm/mach-bf506/def_local.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define CONFIG_BF50x 1	/* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf506/gpio.h b/arch/blackfin/include/asm/mach-bf506/gpio.h
deleted file mode 100644
index 08a82f4..0000000
--- a/arch/blackfin/include/asm/mach-bf506/gpio.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 35
-
-#define GPIO_PF0	0
-#define GPIO_PF1	1
-#define GPIO_PF2	2
-#define GPIO_PF3	3
-#define GPIO_PF4	4
-#define GPIO_PF5	5
-#define GPIO_PF6	6
-#define GPIO_PF7	7
-#define GPIO_PF8	8
-#define GPIO_PF9	9
-#define GPIO_PF10	10
-#define GPIO_PF11	11
-#define GPIO_PF12	12
-#define GPIO_PF13	13
-#define GPIO_PF14	14
-#define GPIO_PF15	15
-#define GPIO_PG0	16
-#define GPIO_PG1	17
-#define GPIO_PG2	18
-#define GPIO_PG3	19
-#define GPIO_PG4	20
-#define GPIO_PG5	21
-#define GPIO_PG6	22
-#define GPIO_PG7	23
-#define GPIO_PG8	24
-#define GPIO_PG9	25
-#define GPIO_PG10	26
-#define GPIO_PG11	27
-#define GPIO_PG12	28
-#define GPIO_PG13	29
-#define GPIO_PG14	30
-#define GPIO_PG15	31
-#define GPIO_PH0	32
-#define GPIO_PH1	33
-#define GPIO_PH2	34
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf506/portmux.h b/arch/blackfin/include/asm/mach-bf506/portmux.h
deleted file mode 100644
index 086186d..0000000
--- a/arch/blackfin/include/asm/mach-bf506/portmux.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
-
-/* PPI Port Mux */
-#define P_PPI0_D0	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#define P_PPI0_D1	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_PPI0_D2	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_PPI0_D3	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-
-#define P_PPI0_CLK	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
-#define P_PPI0_FS1	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_PPI0_FS2	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SCK	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_SPI0_MISO	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_SPI0_MOSI	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#define P_SPI1_SCK	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_SPI1_MISO	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPI1_MOSI	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-
-#define P_SPI1_SSEL1	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_SPI1_SSEL2	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPI1_SSEL3	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF13
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-/* SPORT Port Mux */
-#define P_SPORT0_DRPRI	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_SPORT0_RSCLK	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_SPORT0_RFS	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_SPORT0_TFS	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_SPORT0_DTPRI	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_SPORT0_DTSEC	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_SPORT0_DRSEC	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-
-#define P_SPORT1_DRPRI	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT1_RFS	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_SPORT1_RSCLK	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPORT1_DTPRI	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_SPORT1_TFS	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_SPORT1_TSCLK	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_SPORT1_DTSEC	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_SPORT1_DRSEC	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-
-/* UART Port Mux */
-#ifdef CONFIG_BF506_UART0_PORTF
-#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#else
-#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#endif
-#define P_UART0_RTS	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_UART0_CTS	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-
-#ifdef CONFIG_BF506_UART1_PORTG
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#else
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#endif
-#define P_UART1_RTS	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_UART1_CTS	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-
-/* Timer */
-#define P_TMRCLK	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
-#define P_TMR0		(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_TMR1		(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-#define P_TMR2		(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_TMR3		(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_TMR4		(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-#define P_TMR5		(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_TMR6		(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-
-/* CAN */
-#define P_CAN_TX	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_CAN_RX	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-
-/* PWM */
-#define P_PWM0_AH	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PWM0_AL	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define P_PWM0_BH	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PWM0_BL	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PWM0_CH	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PWM0_CL	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PWM0_SYNC	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PWM0_TRIP	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-
-#define P_PWM1_AH	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_PWM1_AL	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_PWM1_BH	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-#define P_PWM1_BL	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
-#define P_PWM1_CH	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
-#define P_PWM1_CL	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-#define P_PWM1_SYNC	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_PWM1_TRIP	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-
-/* RSI */
-#define P_RSI_DATA0	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_RSI_DATA1	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_RSI_DATA2	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_RSI_DATA3	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_RSI_DATA4	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_RSI_DATA5	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_RSI_DATA6	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_RSI_DATA7	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_RSI_CMD	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_RSI_CLK	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-
-/* ACM */
-#define P_ACM_SE_DIFF	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_ACM_RANGE	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_ACM_A0	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_ACM_A1	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_ACM_A2	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-
-#endif				/* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf506/ports.h b/arch/blackfin/include/asm/mach-bf506/ports.h
deleted file mode 100644
index f1e9cc0..0000000
--- a/arch/blackfin/include/asm/mach-bf506/ports.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORTx_MUX Masks */
-#define PORT_x_MUX_0_MASK	0x0003
-#define PORT_x_MUX_1_MASK	0x000C
-#define PORT_x_MUX_2_MASK	0x0030
-#define PORT_x_MUX_3_MASK	0x00C0
-#define PORT_x_MUX_4_MASK	0x0300
-#define PORT_x_MUX_5_MASK	0x0C00
-#define PORT_x_MUX_6_MASK	0x3000
-#define PORT_x_MUX_7_MASK	0xC000
-
-#define PORT_x_MUX_FUNC_1	(0x0)
-#define PORT_x_MUX_FUNC_2	(0x1)
-#define PORT_x_MUX_FUNC_3	(0x2)
-#define PORT_x_MUX_FUNC_4	(0x3)
-#define PORT_x_MUX_0_FUNC_1	(PORT_x_MUX_FUNC_1 << 0)
-#define PORT_x_MUX_0_FUNC_2	(PORT_x_MUX_FUNC_2 << 0)
-#define PORT_x_MUX_0_FUNC_3	(PORT_x_MUX_FUNC_3 << 0)
-#define PORT_x_MUX_0_FUNC_4	(PORT_x_MUX_FUNC_4 << 0)
-#define PORT_x_MUX_1_FUNC_1	(PORT_x_MUX_FUNC_1 << 2)
-#define PORT_x_MUX_1_FUNC_2	(PORT_x_MUX_FUNC_2 << 2)
-#define PORT_x_MUX_1_FUNC_3	(PORT_x_MUX_FUNC_3 << 2)
-#define PORT_x_MUX_1_FUNC_4	(PORT_x_MUX_FUNC_4 << 2)
-#define PORT_x_MUX_2_FUNC_1	(PORT_x_MUX_FUNC_1 << 4)
-#define PORT_x_MUX_2_FUNC_2	(PORT_x_MUX_FUNC_2 << 4)
-#define PORT_x_MUX_2_FUNC_3	(PORT_x_MUX_FUNC_3 << 4)
-#define PORT_x_MUX_2_FUNC_4	(PORT_x_MUX_FUNC_4 << 4)
-#define PORT_x_MUX_3_FUNC_1	(PORT_x_MUX_FUNC_1 << 6)
-#define PORT_x_MUX_3_FUNC_2	(PORT_x_MUX_FUNC_2 << 6)
-#define PORT_x_MUX_3_FUNC_3	(PORT_x_MUX_FUNC_3 << 6)
-#define PORT_x_MUX_3_FUNC_4	(PORT_x_MUX_FUNC_4 << 6)
-#define PORT_x_MUX_4_FUNC_1	(PORT_x_MUX_FUNC_1 << 8)
-#define PORT_x_MUX_4_FUNC_2	(PORT_x_MUX_FUNC_2 << 8)
-#define PORT_x_MUX_4_FUNC_3	(PORT_x_MUX_FUNC_3 << 8)
-#define PORT_x_MUX_4_FUNC_4	(PORT_x_MUX_FUNC_4 << 8)
-#define PORT_x_MUX_5_FUNC_1	(PORT_x_MUX_FUNC_1 << 10)
-#define PORT_x_MUX_5_FUNC_2	(PORT_x_MUX_FUNC_2 << 10)
-#define PORT_x_MUX_5_FUNC_3	(PORT_x_MUX_FUNC_3 << 10)
-#define PORT_x_MUX_5_FUNC_4	(PORT_x_MUX_FUNC_4 << 10)
-#define PORT_x_MUX_6_FUNC_1	(PORT_x_MUX_FUNC_1 << 12)
-#define PORT_x_MUX_6_FUNC_2	(PORT_x_MUX_FUNC_2 << 12)
-#define PORT_x_MUX_6_FUNC_3	(PORT_x_MUX_FUNC_3 << 12)
-#define PORT_x_MUX_6_FUNC_4	(PORT_x_MUX_FUNC_4 << 12)
-#define PORT_x_MUX_7_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-#include "../mach-common/bits/ports-h.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf518/BF512_cdef.h b/arch/blackfin/include/asm/mach-bf518/BF512_cdef.h
deleted file mode 100644
index db70e77..0000000
--- a/arch/blackfin/include/asm/mach-bf518/BF512_cdef.h
+++ /dev/null
@@ -1,1000 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF512_proc__
-#define __BFIN_CDEF_ADSP_BF512_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()       bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)   bfin_write32(TIMER_STATUS, val)
-#define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI_CLKDIV()         bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val)     bfin_write16(TWI_CLKDIV, val)
-#define bfin_read_TWI_CONTROL()        bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val)    bfin_write16(TWI_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTL()      bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val)  bfin_write16(TWI_SLAVE_CTL, val)
-#define bfin_read_TWI_SLAVE_STAT()     bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR()     bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL()     bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define bfin_read_TWI_MASTER_STAT()    bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR()    bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT()       bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val)   bfin_write16(TWI_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK()       bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val)   bfin_write16(TWI_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL()       bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val)   bfin_write16(TWI_FIFO_CTL, val)
-#define bfin_read_TWI_FIFO_STAT()      bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val)  bfin_write16(TWI_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8()      bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val)  bfin_write16(TWI_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16()     bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8()      bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val)  bfin_write16(TWI_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16()     bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define bfin_read_PORTGIO()            bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val)        bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR()      bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val)  bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET()        bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val)    bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE()     bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA()      bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val)  bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET()  bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB()      bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val)  bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET()  bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR()        bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val)    bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR()      bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val)  bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE()       bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val)   bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH()       bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val)   bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN()       bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val)   bfin_write16(PORTGIO_INEN, val)
-#define bfin_read_PORTHIO()            bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val)        bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR()      bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val)  bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET()        bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val)    bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE()     bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA()      bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val)  bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET()  bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB()      bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val)  bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET()  bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR()        bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val)    bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR()      bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val)  bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE()       bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val)   bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH()       bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val)   bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN()       bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val)   bfin_write16(PORTHIO_INEN, val)
-#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_PORTF_MUX()          bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)      bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX()          bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)      bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX()          bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)      bfin_write16(PORTH_MUX, val)
-#define bfin_read_PORTF_DRIVE()        bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val)    bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE()        bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val)    bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE()        bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val)    bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_HYSTERESIS()   bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS()   bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS()   bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_NONGPIO_DRIVE()      bfin_read16(NONGPIO_DRIVE)
-#define bfin_write_NONGPIO_DRIVE(val)  bfin_write16(NONGPIO_DRIVE, val)
-#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
-#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
-#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define bfin_read_PWM_CTRL()           bfin_read16(PWM_CTRL)
-#define bfin_write_PWM_CTRL(val)       bfin_write16(PWM_CTRL, val)
-#define bfin_read_PWM_STAT()           bfin_read16(PWM_STAT)
-#define bfin_write_PWM_STAT(val)       bfin_write16(PWM_STAT, val)
-#define bfin_read_PWM_TM()             bfin_read16(PWM_TM)
-#define bfin_write_PWM_TM(val)         bfin_write16(PWM_TM, val)
-#define bfin_read_PWM_DT()             bfin_read16(PWM_DT)
-#define bfin_write_PWM_DT(val)         bfin_write16(PWM_DT, val)
-#define bfin_read_PWM_GATE()           bfin_read16(PWM_GATE)
-#define bfin_write_PWM_GATE(val)       bfin_write16(PWM_GATE, val)
-#define bfin_read_PWM_CHA()            bfin_read16(PWM_CHA)
-#define bfin_write_PWM_CHA(val)        bfin_write16(PWM_CHA, val)
-#define bfin_read_PWM_CHB()            bfin_read16(PWM_CHB)
-#define bfin_write_PWM_CHB(val)        bfin_write16(PWM_CHB, val)
-#define bfin_read_PWM_CHC()            bfin_read16(PWM_CHC)
-#define bfin_write_PWM_CHC(val)        bfin_write16(PWM_CHC, val)
-#define bfin_read_PWM_SEG()            bfin_read16(PWM_SEG)
-#define bfin_write_PWM_SEG(val)        bfin_write16(PWM_SEG, val)
-#define bfin_read_PWM_SYNCWT()         bfin_read16(PWM_SYNCWT)
-#define bfin_write_PWM_SYNCWT(val)     bfin_write16(PWM_SYNCWT, val)
-#define bfin_read_PWM_CHAL()           bfin_read16(PWM_CHAL)
-#define bfin_write_PWM_CHAL(val)       bfin_write16(PWM_CHAL, val)
-#define bfin_read_PWM_CHBL()           bfin_read16(PWM_CHBL)
-#define bfin_write_PWM_CHBL(val)       bfin_write16(PWM_CHBL, val)
-#define bfin_read_PWM_CHCL()           bfin_read16(PWM_CHCL)
-#define bfin_write_PWM_CHCL(val)       bfin_write16(PWM_CHCL, val)
-#define bfin_read_PWM_LSI()            bfin_read16(PWM_LSI)
-#define bfin_write_PWM_LSI(val)        bfin_write16(PWM_LSI, val)
-#define bfin_read_PWM_STAT2()          bfin_read16(PWM_STAT2)
-#define bfin_write_PWM_STAT2(val)      bfin_write16(PWM_STAT2, val)
-#define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF512_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/BF512_def.h b/arch/blackfin/include/asm/mach-bf518/BF512_def.h
deleted file mode 100644
index bbaf22f..0000000
--- a/arch/blackfin/include/asm/mach-bf518/BF512_def.h
+++ /dev/null
@@ -1,517 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF512_proc__
-#define __BFIN_DEF_ADSP_BF512_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SIC_IMASK0                     0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0                       0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0                       0xFFC00124 /* Interrupt Wakeup Register */
-#define SIC_IMASK1                     0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4                       0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5                       0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6                       0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7                       0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1                       0xFFC00160 /* Interrupt Status register */
-#define SIC_IWR1                       0xFFC00164 /* Interrupt Wakeup register */
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
-#define UART0_THR                      0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR                      0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL                      0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER                      0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH                      0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR                      0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR                      0xFFC0040C /* Line Control Register */
-#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
-#define UART0_LSR                      0xFFC00414 /* Line Status Register */
-#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
-#define UART0_SCR                      0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL                     0xFFC00424 /* Global Control Register */
-#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag register */
-#define SPI0_STAT                      0xFFC00508 /* SPI0 Status register */
-#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud rate Register */
-#define SPI0_SHADOW                    0xFFC00518 /* SPI0_RDBR Shadow Register */
-#define SPI1_CTL                       0xFFC03400 /* SPI1 Control */
-#define SPI1_FLG                       0xFFC03404 /* SPI1 Flag Register */
-#define SPI1_STAT                      0xFFC03408 /* SPI1 Status Register */
-#define SPI1_TDBR                      0xFFC0340C /* SPI1 Transmit Data Buffer */
-#define SPI1_RDBR                      0xFFC03410 /* SPI1 Receive Data Buffer */
-#define SPI1_BAUD                      0xFFC03414 /* SPI1 Baud Rate */
-#define SPI1_SHADOW                    0xFFC03418 /* SPI1_RDBR Shadow Register */
-#define TIMER0_CONFIG                  0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                  0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH                   0xFFC0060C /* Timer 0 Width Register */
-#define TIMER1_CONFIG                  0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER                 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD                  0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH                   0xFFC0061C /* Timer 1 Width Register */
-#define TIMER2_CONFIG                  0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER                 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD                  0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH                   0xFFC0062C /* Timer 2 Width Register */
-#define TIMER3_CONFIG                  0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER                 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD                  0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH                   0xFFC0063C /* Timer 3 Width Register */
-#define TIMER4_CONFIG                  0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER                 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD                  0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH                   0xFFC0064C /* Timer 4 Width Register */
-#define TIMER5_CONFIG                  0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER                 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD                  0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH                   0xFFC0065C /* Timer 5 Width Register */
-#define TIMER6_CONFIG                  0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER                 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD                  0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH                   0xFFC0066C /* Timer 6 Width Register\n */
-#define TIMER7_CONFIG                  0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER                 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD                  0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH                   0xFFC0067C /* Timer 7 Width Register */
-#define TIMER_ENABLE                   0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE                  0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS                   0xFFC00688 /* Timer Status Register */
-#define PORTFIO                        0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR                  0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET                    0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE                 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA                  0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR            0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET              0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE           0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB                  0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR            0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET              0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE           0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR                    0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR                  0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE                   0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH                   0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN                   0xFFC00740 /* Port F I/O Input Enable Register  */
-#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                      0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX                      0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                      0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX                      0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL                    0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL                    0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDSTAT                    0xFFC00A1C /* SDRAM Status Register */
-#define EBIU_SDRRC                     0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR             0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG                 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT                0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY               0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT                0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR             0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG                 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT                0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY               0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT                0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR             0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG                 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT                0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR             0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG                 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT                0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY               0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT                0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define PPI_CONTROL                    0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS                     0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT                      0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY                      0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME                      0xFFC01010 /* PPI Frame Length Register */
-#define TWI_CLKDIV                     0xFFC01400 /* Serial Clock Divider Register */
-#define TWI_CONTROL                    0xFFC01404 /* TWI Control Register */
-#define TWI_SLAVE_CTL                  0xFFC01408 /* Slave Mode Control Register */
-#define TWI_SLAVE_STAT                 0xFFC0140C /* Slave Mode Status Register */
-#define TWI_SLAVE_ADDR                 0xFFC01410 /* Slave Mode Address Register */
-#define TWI_MASTER_CTL                 0xFFC01414 /* Master Mode Control Register */
-#define TWI_MASTER_STAT                0xFFC01418 /* Master Mode Status Register */
-#define TWI_MASTER_ADDR                0xFFC0141C /* Master Mode Address Register */
-#define TWI_INT_STAT                   0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI_INT_MASK                   0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI_FIFO_CTL                   0xFFC01428 /* FIFO Control Register */
-#define TWI_FIFO_STAT                  0xFFC0142C /* FIFO Status Register */
-#define TWI_XMT_DATA8                  0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI_XMT_DATA16                 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI_RCV_DATA8                  0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI_RCV_DATA16                 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-#define PORTGIO                        0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR                  0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET                    0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE                 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA                  0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR            0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET              0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE           0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB                  0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR            0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET              0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE           0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR                    0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR                  0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE                   0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH                   0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN                   0xFFC01540 /* Port G I/O Input Enable Register */
-#define PORTHIO                        0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR                  0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET                    0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE                 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA                  0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR            0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET              0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE           0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB                  0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR            0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET              0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE           0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR                    0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR                  0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE                   0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH                   0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN                   0xFFC01740 /* Port H I/O Input Enable Register */
-#define UART1_THR                      0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR                      0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL                      0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER                      0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH                      0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR                      0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR                      0xFFC0200C /* Line Control Register */
-#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
-#define UART1_LSR                      0xFFC02014 /* Line Status Register */
-#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
-#define UART1_SCR                      0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL                     0xFFC02024 /* Global Control Register */
-#define PORTF_FER                      0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER                      0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER                      0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define HMDMA0_CONTROL                 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT                  0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT                  0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT                0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW              0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT                  0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT                  0xFFC03318 /* HMDMA0 Current Block Count Register */
-#define HMDMA1_CONTROL                 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT                  0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT                  0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT                0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW              0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT                  0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT                  0xFFC03358 /* HMDMA1 Current Block Count Register */
-#define PORTF_MUX                      0xFFC03210 /* Port F mux control */
-#define PORTG_MUX                      0xFFC03214 /* Port G mux control */
-#define PORTH_MUX                      0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE                    0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE                    0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE                    0xFFC03228 /* Port H drive strength control */
-#define PORTF_HYSTERESIS               0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS               0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS               0xFFC03248 /* Port H Schmitt trigger control */
-#define NONGPIO_DRIVE                  0xFFC03280 /* Non-GPIO Port drive strength control */
-#define NONGPIO_HYSTERESIS             0xFFC03288 /* Non-GPIO Port Schmitt trigger control */
-#define CNT_CONFIG                     0xFFC03500 /* Configuration/Control Register */
-#define CNT_IMASK                      0xFFC03504 /* Interrupt Mask Register */
-#define CNT_STATUS                     0xFFC03508 /* Status Register */
-#define CNT_COMMAND                    0xFFC0350C /* Command Register */
-#define CNT_DEBOUNCE                   0xFFC03510 /* Debounce Prescaler Register */
-#define CNT_COUNTER                    0xFFC03514 /* Counter Register */
-#define CNT_MAX                        0xFFC03518 /* Maximal Count Boundary Value Register */
-#define CNT_MIN                        0xFFC0351C /* Minimal Count Boundary Value Register */
-#define SECURE_SYSSWT                  0xFFC03620 /* Secure System Switches */
-#define SECURE_CONTROL                 0xFFC03624 /* Secure Control */
-#define SECURE_STATUS                  0xFFC03628 /* Secure Status */
-#define OTP_DATA0                      0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1                      0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2                      0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3                      0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define PWM_CTRL                       0xFFC03700 /* PWM Control Register */
-#define PWM_STAT                       0xFFC03704 /* PWM Status Register */
-#define PWM_TM                         0xFFC03708 /* PWM Period Register */
-#define PWM_DT                         0xFFC0370C /* PWM Dead Time Register */
-#define PWM_GATE                       0xFFC03710 /* PWM Chopping Control */
-#define PWM_CHA                        0xFFC03714 /* PWM Channel A Duty Control */
-#define PWM_CHB                        0xFFC03718 /* PWM Channel B Duty Control */
-#define PWM_CHC                        0xFFC0371C /* PWM Channel C Duty Control */
-#define PWM_SEG                        0xFFC03720 /* PWM Crossover and Output Enable */
-#define PWM_SYNCWT                     0xFFC03724 /* PWM Sync pulse width control */
-#define PWM_CHAL                       0xFFC03728 /* PWM Channel AL Duty Control (SR mode only) */
-#define PWM_CHBL                       0xFFC0372C /* PWM Channel BL Duty Control (SR mode only) */
-#define PWM_CHCL                       0xFFC03730 /* PWM Channel CL Duty Control (SR mode only) */
-#define PWM_LSI                        0xFFC03734 /* Low Side Invert (SR mode only) */
-#define PWM_STAT2                      0xFFC03738 /* PWM Status Register */
-#define DMA_TC_CNT                     0xFFC00B0C
-#define DMA_TC_PER                     0xFFC00B10
-
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
-#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif /* __BFIN_DEF_ADSP_BF512_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/BF514_cdef.h b/arch/blackfin/include/asm/mach-bf518/BF514_cdef.h
deleted file mode 100644
index b13246f..0000000
--- a/arch/blackfin/include/asm/mach-bf518/BF514_cdef.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF514_proc__
-#define __BFIN_CDEF_ADSP_BF514_proc__
-
-#include "BF512_cdef.h"
-
-#define bfin_read_RSI_PWR_CONTROL()    bfin_read16(RSI_PWR_CONTROL)
-#define bfin_write_RSI_PWR_CONTROL(val) bfin_write16(RSI_PWR_CONTROL, val)
-#define bfin_read_RSI_CLK_CONTROL()    bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT()       bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val)   bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND()        bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val)    bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD()       bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val)   bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0()      bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val)  bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1()      bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val)  bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2()      bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val)  bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3()      bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val)  bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER()     bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH()      bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val)  bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CONTROL()   bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT()       bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val)   bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS()         bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val)     bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUSCL()       bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUSCL(val)   bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0()          bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val)      bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1()          bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val)      bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT()       bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val)   bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CONTROL()  bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_FIFO()           bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val)       bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_ESTAT()          bfin_read16(RSI_ESTAT)
-#define bfin_write_RSI_ESTAT(val)      bfin_write16(RSI_ESTAT, val)
-#define bfin_read_RSI_EMASK()          bfin_read16(RSI_EMASK)
-#define bfin_write_RSI_EMASK(val)      bfin_write16(RSI_EMASK, val)
-#define bfin_read_RSI_CONFIG()         bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CONFIG(val)     bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN()     bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0()           bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val)       bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1()           bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val)       bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2()           bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val)       bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3()           bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val)       bfin_write16(RSI_PID3, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF514_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/BF514_def.h b/arch/blackfin/include/asm/mach-bf518/BF514_def.h
deleted file mode 100644
index 708a4f7..0000000
--- a/arch/blackfin/include/asm/mach-bf518/BF514_def.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF514_proc__
-#define __BFIN_DEF_ADSP_BF514_proc__
-
-#include "BF512_def.h"
-
-#define RSI_PWR_CONTROL                0xFFC03800 /* RSI Power Control Register */
-#define RSI_CLK_CONTROL                0xFFC03804 /* RSI Clock Control Register */
-#define RSI_ARGUMENT                   0xFFC03808 /* RSI Argument Register */
-#define RSI_COMMAND                    0xFFC0380C /* RSI Command Register */
-#define RSI_RESP_CMD                   0xFFC03810 /* RSI Response Command Register */
-#define RSI_RESPONSE0                  0xFFC03814 /* RSI Response Register */
-#define RSI_RESPONSE1                  0xFFC03818 /* RSI Response Register */
-#define RSI_RESPONSE2                  0xFFC0381C /* RSI Response Register */
-#define RSI_RESPONSE3                  0xFFC03820 /* RSI Response Register */
-#define RSI_DATA_TIMER                 0xFFC03824 /* RSI Data Timer Register */
-#define RSI_DATA_LGTH                  0xFFC03828 /* RSI Data Length Register */
-#define RSI_DATA_CONTROL               0xFFC0382C /* RSI Data Control Register */
-#define RSI_DATA_CNT                   0xFFC03830 /* RSI Data Counter Register */
-#define RSI_STATUS                     0xFFC03834 /* RSI Status Register */
-#define RSI_STATUSCL                   0xFFC03838 /* RSI Status Clear Register */
-#define RSI_MASK0                      0xFFC0383C /* RSI Interrupt 0 Mask Register */
-#define RSI_MASK1                      0xFFC03840 /* RSI Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT                   0xFFC03848 /* RSI FIFO Counter Register */
-#define RSI_CEATA_CONTROL              0xFFC0384C /* RSI CEATA Register */
-#define RSI_FIFO                       0xFFC03880 /* RSI Data FIFO Register */
-#define RSI_ESTAT                      0xFFC038C0 /* RSI Exception Status Register */
-#define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
-#define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
-#define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
-#define RSI_PID0                       0xFFC038D0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID1                       0xFFC038D4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID2                       0xFFC038D8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID3                       0xFFC038DC /* RSI Peripheral ID Register 3 */
-
-#endif /* __BFIN_DEF_ADSP_BF514_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/BF516_cdef.h b/arch/blackfin/include/asm/mach-bf518/BF516_cdef.h
deleted file mode 100644
index 8722944..0000000
--- a/arch/blackfin/include/asm/mach-bf518/BF516_cdef.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF516_proc__
-#define __BFIN_CDEF_ADSP_BF516_proc__
-
-#include "BF514_cdef.h"
-
-#define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
-#define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF516_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/BF516_def.h b/arch/blackfin/include/asm/mach-bf518/BF516_def.h
deleted file mode 100644
index 8139c9b..0000000
--- a/arch/blackfin/include/asm/mach-bf518/BF516_def.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF516_proc__
-#define __BFIN_DEF_ADSP_BF516_proc__
-
-#include "BF514_def.h"
-
-#define EMAC_OPMODE                    0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO                    0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI                    0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO                    0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI                    0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD                    0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT                    0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC                       0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1                     0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2                     0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL                  0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0               0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1               0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2               0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3               0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD                0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF                0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0               0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1               0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-#define EMAC_SYSCTL                    0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT                    0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT                   0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY                   0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE                   0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT                   0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY                   0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE                   0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-#define EMAC_MMC_CTL                   0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS                 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE                 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS                 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE                 0xFFC03090 /* MMC TX Interrupt Enables Register */
-#define EMAC_RXC_OK                    0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS                   0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN                 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET                 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF                0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST                0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI                 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD                 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI                0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO                0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG                  0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL                0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE                0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE                 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM                0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT                0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED                 0xFFC03140 /* Type/Length Consistent RX Frame Count  */
-#define EMAC_RXC_SHORT                 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64                  0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128                 0xFFC0314C /* Good RX Frame Count - Byte Count  64 <= x < 128 */
-#define EMAC_RXC_LT256                 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512                 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024                0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024                0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_OK                    0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL                  0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL                0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET                 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER                 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL                0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL                0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND                0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR                0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST                0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI                 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD                 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR                0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL                0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM                0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT                0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64                  0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128                 0xFFC031C4 /* Good TX Frame Count - Byte Count  64 <= x < 128 */
-#define EMAC_TXC_LT256                 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512                 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024                0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024                0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT                 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-#endif /* __BFIN_DEF_ADSP_BF516_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/BF518_cdef.h b/arch/blackfin/include/asm/mach-bf518/BF518_cdef.h
deleted file mode 100644
index 0e582e1..0000000
--- a/arch/blackfin/include/asm/mach-bf518/BF518_cdef.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF518_proc__
-#define __BFIN_CDEF_ADSP_BF518_proc__
-
-#include "BF516_cdef.h"
-
-#define bfin_read_EMAC_PTP_CTL()       bfin_read16(EMAC_PTP_CTL)
-#define bfin_write_EMAC_PTP_CTL(val)   bfin_write16(EMAC_PTP_CTL, val)
-#define bfin_read_EMAC_PTP_IE()        bfin_read16(EMAC_PTP_IE)
-#define bfin_write_EMAC_PTP_IE(val)    bfin_write16(EMAC_PTP_IE, val)
-#define bfin_read_EMAC_PTP_ISTAT()     bfin_read16(EMAC_PTP_ISTAT)
-#define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val)
-#define bfin_read_EMAC_PTP_FOFF()      bfin_read32(EMAC_PTP_FOFF)
-#define bfin_write_EMAC_PTP_FOFF(val)  bfin_write32(EMAC_PTP_FOFF, val)
-#define bfin_read_EMAC_PTP_FV1()       bfin_read32(EMAC_PTP_FV1)
-#define bfin_write_EMAC_PTP_FV1(val)   bfin_write32(EMAC_PTP_FV1, val)
-#define bfin_read_EMAC_PTP_FV2()       bfin_read32(EMAC_PTP_FV2)
-#define bfin_write_EMAC_PTP_FV2(val)   bfin_write32(EMAC_PTP_FV2, val)
-#define bfin_read_EMAC_PTP_FV3()       bfin_read32(EMAC_PTP_FV3)
-#define bfin_write_EMAC_PTP_FV3(val)   bfin_write32(EMAC_PTP_FV3, val)
-#define bfin_read_EMAC_PTP_ADDEND()    bfin_read32(EMAC_PTP_ADDEND)
-#define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val)
-#define bfin_read_EMAC_PTP_ACCR()      bfin_read32(EMAC_PTP_ACCR)
-#define bfin_write_EMAC_PTP_ACCR(val)  bfin_write32(EMAC_PTP_ACCR, val)
-#define bfin_read_EMAC_PTP_OFFSET()    bfin_read32(EMAC_PTP_OFFSET)
-#define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val)
-#define bfin_read_EMAC_PTP_TIMELO()    bfin_read32(EMAC_PTP_TIMELO)
-#define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val)
-#define bfin_read_EMAC_PTP_TIMEHI()    bfin_read32(EMAC_PTP_TIMEHI)
-#define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val)
-#define bfin_read_EMAC_PTP_RXSNAPLO()  bfin_read32(EMAC_PTP_RXSNAPLO)
-#define bfin_write_EMAC_PTP_RXSNAPLO(val) bfin_write32(EMAC_PTP_RXSNAPLO, val)
-#define bfin_read_EMAC_PTP_RXSNAPHI()  bfin_read32(EMAC_PTP_RXSNAPHI)
-#define bfin_write_EMAC_PTP_RXSNAPHI(val) bfin_write32(EMAC_PTP_RXSNAPHI, val)
-#define bfin_read_EMAC_PTP_TXSNAPLO()  bfin_read32(EMAC_PTP_TXSNAPLO)
-#define bfin_write_EMAC_PTP_TXSNAPLO(val) bfin_write32(EMAC_PTP_TXSNAPLO, val)
-#define bfin_read_EMAC_PTP_TXSNAPHI()  bfin_read32(EMAC_PTP_TXSNAPHI)
-#define bfin_write_EMAC_PTP_TXSNAPHI(val) bfin_write32(EMAC_PTP_TXSNAPHI, val)
-#define bfin_read_EMAC_PTP_ALARMLO()   bfin_read32(EMAC_PTP_ALARMLO)
-#define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val)
-#define bfin_read_EMAC_PTP_ALARMHI()   bfin_read32(EMAC_PTP_ALARMHI)
-#define bfin_write_EMAC_PTP_ALARMHI(val) bfin_write32(EMAC_PTP_ALARMHI, val)
-#define bfin_read_EMAC_PTP_ID_OFF()    bfin_read16(EMAC_PTP_ID_OFF)
-#define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val)
-#define bfin_read_EMAC_PTP_ID_SNAP()   bfin_read32(EMAC_PTP_ID_SNAP)
-#define bfin_write_EMAC_PTP_ID_SNAP(val) bfin_write32(EMAC_PTP_ID_SNAP, val)
-#define bfin_read_EMAC_PTP_PPS_STARTLO() bfin_read32(EMAC_PTP_PPS_STARTLO)
-#define bfin_write_EMAC_PTP_PPS_STARTLO(val) bfin_write32(EMAC_PTP_PPS_STARTLO, val)
-#define bfin_read_EMAC_PTP_PPS_STARTHI() bfin_read32(EMAC_PTP_PPS_STARTHI)
-#define bfin_write_EMAC_PTP_PPS_STARTHI(val) bfin_write32(EMAC_PTP_PPS_STARTHI, val)
-#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD)
-#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF518_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/BF518_def.h b/arch/blackfin/include/asm/mach-bf518/BF518_def.h
deleted file mode 100644
index eec70d4..0000000
--- a/arch/blackfin/include/asm/mach-bf518/BF518_def.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF518_proc__
-#define __BFIN_DEF_ADSP_BF518_proc__
-
-#include "BF516_def.h"
-
-#define EMAC_PTP_CTL                   0xFFC030A0 /* PTP Block Control */
-#define EMAC_PTP_IE                    0xFFC030A4 /* PTP Block Interrupt Enable */
-#define EMAC_PTP_ISTAT                 0xFFC030A8 /* PTP Block Interrupt Status */
-#define EMAC_PTP_FOFF                  0xFFC030AC /* PTP Filter offset Register */
-#define EMAC_PTP_FV1                   0xFFC030B0 /* PTP Filter Value Register 1 */
-#define EMAC_PTP_FV2                   0xFFC030B4 /* PTP Filter Value Register 2 */
-#define EMAC_PTP_FV3                   0xFFC030B8 /* PTP Filter Value Register 3 */
-#define EMAC_PTP_ADDEND                0xFFC030BC /* PTP Addend for Frequency Compensation */
-#define EMAC_PTP_ACCR                  0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
-#define EMAC_PTP_OFFSET                0xFFC030C4 /* PTP Time Offset Register */
-#define EMAC_PTP_TIMELO                0xFFC030C8 /* PTP Precision Clock Time Low */
-#define EMAC_PTP_TIMEHI                0xFFC030CC /* PTP Precision Clock Time High */
-#define EMAC_PTP_RXSNAPLO              0xFFC030D0 /* PTP Receive Snapshot Register Low */
-#define EMAC_PTP_RXSNAPHI              0xFFC030D4 /* PTP Receive Snapshot Register High */
-#define EMAC_PTP_TXSNAPLO              0xFFC030D8 /* PTP Transmit Snapshot Register Low */
-#define EMAC_PTP_TXSNAPHI              0xFFC030DC /* PTP Transmit Snapshot Register High */
-#define EMAC_PTP_ALARMLO               0xFFC030E0 /* PTP Alarm time Low */
-#define EMAC_PTP_ALARMHI               0xFFC030E4 /* PTP Alarm time High */
-#define EMAC_PTP_ID_OFF                0xFFC030E8 /* PTP Capture ID offset register */
-#define EMAC_PTP_ID_SNAP               0xFFC030EC /* PTP Capture ID register */
-#define EMAC_PTP_PPS_STARTLO           0xFFC030F0 /* PPS Start Time Low */
-#define EMAC_PTP_PPS_STARTHI           0xFFC030F4 /* PPS Start Time High */
-#define EMAC_PTP_PPS_PERIOD            0xFFC030F8 /* PPS Count Register */
-
-#endif /* __BFIN_DEF_ADSP_BF518_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/anomaly.h b/arch/blackfin/include/asm/mach-bf518/anomaly.h
deleted file mode 100644
index 56383f7..0000000
--- a/arch/blackfin/include/asm/mach-bf518/anomaly.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- *  - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF518 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
-/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
-#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* Incorrect L1 Instruction Bank B Memory Map Location */
-#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
-/* PWM_TRIPB Signal Not Available on PG10 */
-#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
-/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
-#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (0)
-#define ANOMALY_05000357 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000371 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf518/def_local.h b/arch/blackfin/include/asm/mach-bf518/def_local.h
deleted file mode 100644
index 73f67d8..0000000
--- a/arch/blackfin/include/asm/mach-bf518/def_local.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define CONFIG_BF51x 1	/* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf518/gpio.h b/arch/blackfin/include/asm/mach-bf518/gpio.h
deleted file mode 100644
index 9af6ce0..0000000
--- a/arch/blackfin/include/asm/mach-bf518/gpio.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 41
-
-#define GPIO_PF0	0
-#define GPIO_PF1	1
-#define GPIO_PF2	2
-#define GPIO_PF3	3
-#define GPIO_PF4	4
-#define GPIO_PF5	5
-#define GPIO_PF6	6
-#define GPIO_PF7	7
-#define GPIO_PF8	8
-#define GPIO_PF9	9
-#define GPIO_PF10	10
-#define GPIO_PF11	11
-#define GPIO_PF12	12
-#define GPIO_PF13	13
-#define GPIO_PF14	14
-#define GPIO_PF15	15
-#define GPIO_PG0	16
-#define GPIO_PG1	17
-#define GPIO_PG2	18
-#define GPIO_PG3	19
-#define GPIO_PG4	20
-#define GPIO_PG5	21
-#define GPIO_PG6	22
-#define GPIO_PG7	23
-#define GPIO_PG8	24
-#define GPIO_PG9	25
-#define GPIO_PG10	26
-#define GPIO_PG11	27
-#define GPIO_PG12	28
-#define GPIO_PG13	29
-#define GPIO_PG14	30
-#define GPIO_PG15	31
-#define GPIO_PH0	32
-#define GPIO_PH1	33
-#define GPIO_PH2	34
-#define GPIO_PH3	35
-#define GPIO_PH4	36
-#define GPIO_PH5	37
-#define GPIO_PH6	38
-#define GPIO_PH7	39
-#define GPIO_PH8	40
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf518/portmux.h b/arch/blackfin/include/asm/mach-bf518/portmux.h
deleted file mode 100644
index cd84a56..0000000
--- a/arch/blackfin/include/asm/mach-bf518/portmux.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
-
-/* EMAC MII/RMII Port Mux */
-#define P_MII0_ETxD2	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_MII0_ERxD2	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_MII0_ETxD3	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_MII0_ERxD3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_MII0_ERxCLK	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_MII0_ERxDV	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_MII0_COL	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-
-#define P_MII0_MDC	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_MII0_MDIO	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_MII0_ETxD0	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_MII0_ERxD0	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_MII0_ETxD1	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_MII0_ERxD1	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_MII0_ETxEN	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_MII0_PHYINT	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_MII0_CRS	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_MII0_ERxER	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_MII0_TxCLK	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-
-#define P_MII0 {\
-	P_MII0_ETxD0, \
-	P_MII0_ETxD1, \
-	P_MII0_ETxD2, \
-	P_MII0_ETxD3, \
-	P_MII0_ETxEN, \
-	P_MII0_TxCLK, \
-	P_MII0_PHYINT, \
-	P_MII0_COL, \
-	P_MII0_ERxD0, \
-	P_MII0_ERxD1, \
-	P_MII0_ERxD2, \
-	P_MII0_ERxD3, \
-	P_MII0_ERxDV, \
-	P_MII0_ERxCLK, \
-	P_MII0_ERxER, \
-	P_MII0_CRS, \
-	P_MII0_MDC, \
-	P_MII0_MDIO, 0}
-
-#define P_RMII0 {\
-	P_MII0_ETxD0, \
-	P_MII0_ETxD1, \
-	P_MII0_ETxEN, \
-	P_MII0_ERxD0, \
-	P_MII0_ERxD1, \
-	P_MII0_ERxER, \
-	P_MII0_TxCLK, \
-	P_MII0_PHYINT, \
-	P_MII0_CRS, \
-	P_MII0_MDC, \
-	P_MII0_MDIO, 0}
-
-/* PPI Port Mux */
-#define P_PPI0_D0	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_PPI0_D1	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_PPI0_D2	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PPI0_D3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_PPI0_CLK	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_PPI0_FS1	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_PPI0_FS2	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPI0_SCK	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_SPI0_MISO	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_SPI0_MOSI	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_SPI0_SSEL4	(P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_SPI0_SSEL5	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-
-#define P_SPI1_SS	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_SPI1_SCK	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_SPI1_MISO	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_SPI1_MOSI	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-
-#define P_SPI1_SSEL1	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_SPI1_SSEL2	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_SPI1_SSEL3	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
-#define P_SPI1_SSEL4	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_SPI1_SSEL5	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-/* SPORT Port Mux */
-#define P_SPORT0_DRPRI	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_SPORT0_RSCLK	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPORT0_RFS	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPORT0_TFS	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DTPRI	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPORT0_DTSEC	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT0_DRSEC	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-
-#define P_SPORT1_DRPRI	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_SPORT1_RFS	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_SPORT1_RSCLK	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_SPORT1_DTPRI	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_SPORT1_TFS	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_SPORT1_TSCLK	(P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_SPORT1_DTSEC	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_SPORT1_DRSEC	(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-
-/* UART Port Mux */
-#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-
-/* Timer */
-#define P_TMRCLK	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_TMR0		(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_TMR1		(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_TMR2		(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_TMR3		(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_TMR4		(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
-#define P_TMR5		(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR6		(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-#define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-
-/* DMA */
-#define P_DMAR1		(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-#define P_DMAR0		(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-
-/* TWI */
-#define P_TWI0_SCL	(P_DONTCARE)
-#define P_TWI0_SDA	(P_DONTCARE)
-
-/* PWM */
-#define P_PWM0_AH		(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_PWM0_AL		(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_PWM0_BH		(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_PWM0_BL		(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_PWM0_CH		(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_PWM0_CL		(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_PWM0_SYNC		(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-
-#define P_PWM1_AH		(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_PWM1_AL		(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_PWM1_BH		(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_PWM1_BL		(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_PWM1_CH		(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_PWM1_CL		(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_PWM1_SYNC		(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-
-#define P_PWM_TRIPB		(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-
-/* RSI */
-#define P_RSI_DATA0		(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_RSI_DATA1		(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_RSI_DATA2		(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_RSI_DATA3		(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_RSI_DATA4		(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_RSI_DATA5		(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_RSI_DATA6		(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_RSI_DATA7		(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_RSI_CMD		(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_RSI_CLK		(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-
-/* PTP */
-#define P_PTP_PPS		(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_PTP_CLKOUT		(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-
-/* AMS */
-#define P_AMS2			(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_AMS3			(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#define P_HWAIT			(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
-
-#endif				/* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf518/ports.h b/arch/blackfin/include/asm/mach-bf518/ports.h
deleted file mode 100644
index f1e9cc0..0000000
--- a/arch/blackfin/include/asm/mach-bf518/ports.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORTx_MUX Masks */
-#define PORT_x_MUX_0_MASK	0x0003
-#define PORT_x_MUX_1_MASK	0x000C
-#define PORT_x_MUX_2_MASK	0x0030
-#define PORT_x_MUX_3_MASK	0x00C0
-#define PORT_x_MUX_4_MASK	0x0300
-#define PORT_x_MUX_5_MASK	0x0C00
-#define PORT_x_MUX_6_MASK	0x3000
-#define PORT_x_MUX_7_MASK	0xC000
-
-#define PORT_x_MUX_FUNC_1	(0x0)
-#define PORT_x_MUX_FUNC_2	(0x1)
-#define PORT_x_MUX_FUNC_3	(0x2)
-#define PORT_x_MUX_FUNC_4	(0x3)
-#define PORT_x_MUX_0_FUNC_1	(PORT_x_MUX_FUNC_1 << 0)
-#define PORT_x_MUX_0_FUNC_2	(PORT_x_MUX_FUNC_2 << 0)
-#define PORT_x_MUX_0_FUNC_3	(PORT_x_MUX_FUNC_3 << 0)
-#define PORT_x_MUX_0_FUNC_4	(PORT_x_MUX_FUNC_4 << 0)
-#define PORT_x_MUX_1_FUNC_1	(PORT_x_MUX_FUNC_1 << 2)
-#define PORT_x_MUX_1_FUNC_2	(PORT_x_MUX_FUNC_2 << 2)
-#define PORT_x_MUX_1_FUNC_3	(PORT_x_MUX_FUNC_3 << 2)
-#define PORT_x_MUX_1_FUNC_4	(PORT_x_MUX_FUNC_4 << 2)
-#define PORT_x_MUX_2_FUNC_1	(PORT_x_MUX_FUNC_1 << 4)
-#define PORT_x_MUX_2_FUNC_2	(PORT_x_MUX_FUNC_2 << 4)
-#define PORT_x_MUX_2_FUNC_3	(PORT_x_MUX_FUNC_3 << 4)
-#define PORT_x_MUX_2_FUNC_4	(PORT_x_MUX_FUNC_4 << 4)
-#define PORT_x_MUX_3_FUNC_1	(PORT_x_MUX_FUNC_1 << 6)
-#define PORT_x_MUX_3_FUNC_2	(PORT_x_MUX_FUNC_2 << 6)
-#define PORT_x_MUX_3_FUNC_3	(PORT_x_MUX_FUNC_3 << 6)
-#define PORT_x_MUX_3_FUNC_4	(PORT_x_MUX_FUNC_4 << 6)
-#define PORT_x_MUX_4_FUNC_1	(PORT_x_MUX_FUNC_1 << 8)
-#define PORT_x_MUX_4_FUNC_2	(PORT_x_MUX_FUNC_2 << 8)
-#define PORT_x_MUX_4_FUNC_3	(PORT_x_MUX_FUNC_3 << 8)
-#define PORT_x_MUX_4_FUNC_4	(PORT_x_MUX_FUNC_4 << 8)
-#define PORT_x_MUX_5_FUNC_1	(PORT_x_MUX_FUNC_1 << 10)
-#define PORT_x_MUX_5_FUNC_2	(PORT_x_MUX_FUNC_2 << 10)
-#define PORT_x_MUX_5_FUNC_3	(PORT_x_MUX_FUNC_3 << 10)
-#define PORT_x_MUX_5_FUNC_4	(PORT_x_MUX_FUNC_4 << 10)
-#define PORT_x_MUX_6_FUNC_1	(PORT_x_MUX_FUNC_1 << 12)
-#define PORT_x_MUX_6_FUNC_2	(PORT_x_MUX_FUNC_2 << 12)
-#define PORT_x_MUX_6_FUNC_3	(PORT_x_MUX_FUNC_3 << 12)
-#define PORT_x_MUX_6_FUNC_4	(PORT_x_MUX_FUNC_4 << 12)
-#define PORT_x_MUX_7_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-#include "../mach-common/bits/ports-h.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
deleted file mode 100644
index 49a60af..0000000
--- a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
+++ /dev/null
@@ -1,1012 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF522_proc__
-#define __BFIN_CDEF_ADSP_BF522_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()       bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)   bfin_write32(TIMER_STATUS, val)
-#define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI_CLKDIV()         bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val)     bfin_write16(TWI_CLKDIV, val)
-#define bfin_read_TWI_CONTROL()        bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val)    bfin_write16(TWI_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTL()      bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val)  bfin_write16(TWI_SLAVE_CTL, val)
-#define bfin_read_TWI_SLAVE_STAT()     bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR()     bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL()     bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define bfin_read_TWI_MASTER_STAT()    bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR()    bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT()       bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val)   bfin_write16(TWI_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK()       bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val)   bfin_write16(TWI_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL()       bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val)   bfin_write16(TWI_FIFO_CTL, val)
-#define bfin_read_TWI_FIFO_STAT()      bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val)  bfin_write16(TWI_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8()      bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val)  bfin_write16(TWI_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16()     bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8()      bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val)  bfin_write16(TWI_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16()     bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define bfin_read_PORTGIO()            bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val)        bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR()      bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val)  bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET()        bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val)    bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE()     bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA()      bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val)  bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET()  bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB()      bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val)  bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET()  bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR()        bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val)    bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR()      bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val)  bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE()       bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val)   bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH()       bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val)   bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN()       bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val)   bfin_write16(PORTGIO_INEN, val)
-#define bfin_read_PORTHIO()            bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val)        bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR()      bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val)  bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET()        bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val)    bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE()     bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA()      bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val)  bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET()  bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB()      bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val)  bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET()  bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR()        bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val)    bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR()      bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val)  bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE()       bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val)   bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH()       bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val)   bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN()       bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val)   bfin_write16(PORTHIO_INEN, val)
-#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_PORTF_MUX()          bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)      bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX()          bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)      bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX()          bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)      bfin_write16(PORTH_MUX, val)
-#define bfin_read_PORTF_DRIVE()        bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val)    bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE()        bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val)    bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE()        bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val)    bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW()         bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val)     bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW()         bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val)     bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW()         bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val)     bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERESIS()   bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS()   bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS()   bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_NONGPIO_DRIVE()      bfin_read16(NONGPIO_DRIVE)
-#define bfin_write_NONGPIO_DRIVE(val)  bfin_write16(NONGPIO_DRIVE, val)
-#define bfin_read_NONGPIO_SLEW()       bfin_read16(NONGPIO_SLEW)
-#define bfin_write_NONGPIO_SLEW(val)   bfin_write16(NONGPIO_SLEW, val)
-#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
-#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
-#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
-#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
-#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF522_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_def.h b/arch/blackfin/include/asm/mach-bf527/BF522_def.h
deleted file mode 100644
index 075c697..0000000
--- a/arch/blackfin/include/asm/mach-bf527/BF522_def.h
+++ /dev/null
@@ -1,513 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF522_proc__
-#define __BFIN_DEF_ADSP_BF522_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SIC_RVECT                      0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK0                     0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0                       0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0                       0xFFC00124 /* Interrupt Wakeup Register */
-#define SIC_IMASK1                     0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4                       0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5                       0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6                       0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7                       0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1                       0xFFC00160 /* Interrupt Status register */
-#define SIC_IWR1                       0xFFC00164 /* Interrupt Wakeup register */
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
-#define UART0_THR                      0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR                      0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL                      0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER                      0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH                      0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR                      0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR                      0xFFC0040C /* Line Control Register */
-#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
-#define UART0_LSR                      0xFFC00414 /* Line Status Register */
-#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
-#define UART0_SCR                      0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL                     0xFFC00424 /* Global Control Register */
-#define SPI_CTL                        0xFFC00500 /* SPI Control Register */
-#define SPI_FLG                        0xFFC00504 /* SPI Flag register */
-#define SPI_STAT                       0xFFC00508 /* SPI Status register */
-#define SPI_TDBR                       0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR                       0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD                       0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW                     0xFFC00518 /* SPI_RDBR Shadow Register */
-#define TIMER0_CONFIG                  0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                  0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH                   0xFFC0060C /* Timer 0 Width Register */
-#define TIMER1_CONFIG                  0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER                 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD                  0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH                   0xFFC0061C /* Timer 1 Width Register */
-#define TIMER2_CONFIG                  0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER                 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD                  0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH                   0xFFC0062C /* Timer 2 Width Register */
-#define TIMER3_CONFIG                  0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER                 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD                  0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH                   0xFFC0063C /* Timer 3 Width Register */
-#define TIMER4_CONFIG                  0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER                 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD                  0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH                   0xFFC0064C /* Timer 4 Width Register */
-#define TIMER5_CONFIG                  0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER                 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD                  0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH                   0xFFC0065C /* Timer 5 Width Register */
-#define TIMER6_CONFIG                  0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER                 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD                  0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH                   0xFFC0066C /* Timer 6 Width Register\n */
-#define TIMER7_CONFIG                  0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER                 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD                  0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH                   0xFFC0067C /* Timer 7 Width Register */
-#define TIMER_ENABLE                   0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE                  0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS                   0xFFC00688 /* Timer Status Register */
-#define PORTFIO                        0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR                  0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET                    0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE                 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA                  0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR            0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET              0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE           0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB                  0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR            0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET              0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE           0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR                    0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR                  0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE                   0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH                   0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN                   0xFFC00740 /* Port F I/O Input Enable Register  */
-#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                      0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX                      0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                      0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX                      0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL                    0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL                    0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC                     0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT                    0xFFC00A1C /* SDRAM Status Register */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR             0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG                 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT                0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY               0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT                0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR             0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG                 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT                0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY               0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT                0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR             0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG                 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT                0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR             0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG                 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT                0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY               0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT                0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define PPI_CONTROL                    0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS                     0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT                      0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY                      0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME                      0xFFC01010 /* PPI Frame Length Register */
-#define TWI_CLKDIV                     0xFFC01400 /* Serial Clock Divider Register */
-#define TWI_CONTROL                    0xFFC01404 /* TWI Control Register */
-#define TWI_SLAVE_CTL                  0xFFC01408 /* Slave Mode Control Register */
-#define TWI_SLAVE_STAT                 0xFFC0140C /* Slave Mode Status Register */
-#define TWI_SLAVE_ADDR                 0xFFC01410 /* Slave Mode Address Register */
-#define TWI_MASTER_CTL                 0xFFC01414 /* Master Mode Control Register */
-#define TWI_MASTER_STAT                0xFFC01418 /* Master Mode Status Register */
-#define TWI_MASTER_ADDR                0xFFC0141C /* Master Mode Address Register */
-#define TWI_INT_STAT                   0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI_INT_MASK                   0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI_FIFO_CTL                   0xFFC01428 /* FIFO Control Register */
-#define TWI_FIFO_STAT                  0xFFC0142C /* FIFO Status Register */
-#define TWI_XMT_DATA8                  0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI_XMT_DATA16                 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI_RCV_DATA8                  0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI_RCV_DATA16                 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-#define PORTGIO                        0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR                  0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET                    0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE                 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA                  0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR            0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET              0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE           0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB                  0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR            0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET              0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE           0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR                    0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR                  0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE                   0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH                   0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN                   0xFFC01540 /* Port G I/O Input Enable Register */
-#define PORTHIO                        0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR                  0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET                    0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE                 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA                  0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR            0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET              0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE           0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB                  0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR            0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET              0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE           0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR                    0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR                  0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE                   0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH                   0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN                   0xFFC01740 /* Port H I/O Input Enable Register */
-#define UART1_THR                      0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR                      0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL                      0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER                      0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH                      0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR                      0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR                      0xFFC0200C /* Line Control Register */
-#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
-#define UART1_LSR                      0xFFC02014 /* Line Status Register */
-#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
-#define UART1_SCR                      0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL                     0xFFC02024 /* Global Control Register */
-#define PORTF_FER                      0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER                      0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER                      0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define HMDMA0_CONTROL                 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT                  0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT                  0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT                0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW              0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT                  0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT                  0xFFC03318 /* HMDMA0 Current Block Count Register */
-#define HMDMA1_CONTROL                 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT                  0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT                  0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT                0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW              0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT                  0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT                  0xFFC03358 /* HMDMA1 Current Block Count Register */
-#define PORTF_MUX                      0xFFC03210 /* Port F mux control */
-#define PORTG_MUX                      0xFFC03214 /* Port G mux control */
-#define PORTH_MUX                      0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE                    0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE                    0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE                    0xFFC03228 /* Port H drive strength control */
-#define PORTF_SLEW                     0xFFC03230 /* Port F slew control */
-#define PORTG_SLEW                     0xFFC03234 /* Port G slew control */
-#define PORTH_SLEW                     0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERESIS               0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS               0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS               0xFFC03248 /* Port H Schmitt trigger control */
-#define NONGPIO_DRIVE                  0xFFC03280 /* Non-GPIO Port drive strength control */
-#define NONGPIO_SLEW                   0xFFC03284 /* Non-GPIO Port slew control */
-#define NONGPIO_HYSTERESIS             0xFFC03288 /* Non-GPIO Port Schmitt trigger control */
-#define HOST_CONTROL                   0xFFC03400 /* HOST Control Register */
-#define HOST_STATUS                    0xFFC03404 /* HOST Status Register */
-#define HOST_TIMEOUT                   0xFFC03408 /* HOST Acknowledge Mode Timeout Register */
-#define CNT_CONFIG                     0xFFC03500 /* Configuration/Control Register */
-#define CNT_IMASK                      0xFFC03504 /* Interrupt Mask Register */
-#define CNT_STATUS                     0xFFC03508 /* Status Register */
-#define CNT_COMMAND                    0xFFC0350C /* Command Register */
-#define CNT_DEBOUNCE                   0xFFC03510 /* Debounce Prescaler Register */
-#define CNT_COUNTER                    0xFFC03514 /* Counter Register */
-#define CNT_MAX                        0xFFC03518 /* Maximal Count Boundary Value Register */
-#define CNT_MIN                        0xFFC0351C /* Minimal Count Boundary Value Register */
-#define OTP_CONTROL                    0xFFC03600 /* OTP/Fuse Control Register */
-#define OTP_BEN                        0xFFC03604 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS                     0xFFC03608 /* OTP/Fuse Status */
-#define OTP_TIMING                     0xFFC0360C /* OTP/Fuse Access Timing */
-#define SECURE_SYSSWT                  0xFFC03620 /* Secure System Switches */
-#define SECURE_CONTROL                 0xFFC03624 /* Secure Control */
-#define SECURE_STATUS                  0xFFC03628 /* Secure Status */
-#define OTP_DATA0                      0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1                      0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2                      0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3                      0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define NFC_CTL                        0xFFC03700 /* NAND Control Register */
-#define NFC_STAT                       0xFFC03704 /* NAND Status Register */
-#define NFC_IRQSTAT                    0xFFC03708 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK                    0xFFC0370C /* NAND Interrupt Mask Register */
-#define NFC_ECC0                       0xFFC03710 /* NAND ECC Register 0 */
-#define NFC_ECC1                       0xFFC03714 /* NAND ECC Register 1 */
-#define NFC_ECC2                       0xFFC03718 /* NAND ECC Register 2 */
-#define NFC_ECC3                       0xFFC0371C /* NAND ECC Register 3 */
-#define NFC_COUNT                      0xFFC03720 /* NAND ECC Count Register */
-#define NFC_RST                        0xFFC03724 /* NAND ECC Reset Register */
-#define NFC_PGCTL                      0xFFC03728 /* NAND Page Control Register */
-#define NFC_READ                       0xFFC0372C /* NAND Read Data Register */
-#define NFC_ADDR                       0xFFC03740 /* NAND Address Register */
-#define NFC_CMD                        0xFFC03744 /* NAND Command Register */
-#define NFC_DATA_WR                    0xFFC03748 /* NAND Data Write Register */
-#define NFC_DATA_RD                    0xFFC0374C /* NAND Data Read Register */
-#define DMA_TC_CNT                     0xFFC00B0C
-#define DMA_TC_PER                     0xFFC00B10
-
-#endif /* __BFIN_DEF_ADSP_BF522_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
deleted file mode 100644
index 593330e..0000000
--- a/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF522_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF523_def.h b/arch/blackfin/include/asm/mach-bf527/BF523_def.h
deleted file mode 100644
index e88a450..0000000
--- a/arch/blackfin/include/asm/mach-bf527/BF523_def.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF522_def.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
deleted file mode 100644
index 060dce3..0000000
--- a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF524_proc__
-#define __BFIN_CDEF_ADSP_BF524_proc__
-
-#include "BF522_cdef.h"
-
-#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF524_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_def.h b/arch/blackfin/include/asm/mach-bf527/BF524_def.h
deleted file mode 100644
index f0e7716..0000000
--- a/arch/blackfin/include/asm/mach-bf527/BF524_def.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF524_proc__
-#define __BFIN_DEF_ADSP_BF524_proc__
-
-#include "BF522_def.h"
-
-#define USB_FADDR                      0xFFC03800 /* Function address register */
-#define USB_POWER                      0xFFC03804 /* Power management register */
-#define USB_INTRTX                     0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX                     0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE                    0xFFC03810 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE                    0xFFC03814 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB                    0xFFC03818 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE                   0xFFC0381C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME                      0xFFC03820 /* USB frame number */
-#define USB_INDEX                      0xFFC03824 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE                   0xFFC03828 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR                   0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL                 0xFFC03830 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET              0xFFC03840 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0                       0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR                      0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET              0xFFC03848 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR                      0xFFC0384C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0                     0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT                    0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE                     0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0                  0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL                 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE                     0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL                 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT                    0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO                   0xFFC03880 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO                   0xFFC03888 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO                   0xFFC03890 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO                   0xFFC03898 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO                   0xFFC038A0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO                   0xFFC038A8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO                   0xFFC038B0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO                   0xFFC038B8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL                0xFFC03900 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ               0xFFC03904 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK              0xFFC03908 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO                   0xFFC03948 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN                      0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1                    0xFFC03950 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1                    0xFFC03954 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1                    0xFFC03958 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL                 0xFFC039E0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB                 0xFFC039E4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2                0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST                   0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL                0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV                 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP              0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR               0xFFC03A04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP              0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR               0xFFC03A0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT             0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE              0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL          0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE              0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL          0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT             0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP              0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR               0xFFC03A44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP              0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR               0xFFC03A4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT             0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE              0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL          0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE              0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL          0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT             0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP              0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR               0xFFC03A84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP              0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR               0xFFC03A8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT             0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE              0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL          0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE              0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL          0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT             0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP              0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR               0xFFC03AC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP              0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR               0xFFC03ACC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT             0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE              0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL          0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE              0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL          0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT             0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP              0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR               0xFFC03B04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP              0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR               0xFFC03B0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT             0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE              0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL          0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE              0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL          0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT             0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP              0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR               0xFFC03B44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP              0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR               0xFFC03B4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT             0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE              0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL          0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE              0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL          0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT             0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP              0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR               0xFFC03B84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP              0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR               0xFFC03B8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT             0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE              0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL          0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE              0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL          0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT             0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP              0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR               0xFFC03BC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP              0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR               0xFFC03BCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT             0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE              0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL          0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE              0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL          0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT             0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT              0xFFC03C00 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL               0xFFC03C04 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW               0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH              0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW              0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH             0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL               0xFFC03C24 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW               0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH              0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW              0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH             0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL               0xFFC03C44 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW               0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH              0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW              0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH             0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL               0xFFC03C64 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW               0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH              0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW              0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH             0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL               0xFFC03C84 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW               0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH              0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW              0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH             0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL               0xFFC03CA4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW               0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH              0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW              0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH             0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL               0xFFC03CC4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW               0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH              0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW              0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH             0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL               0xFFC03CE4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW               0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH              0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW              0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH             0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_BF524_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h
deleted file mode 100644
index 415eb07..0000000
--- a/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF524_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF525_def.h b/arch/blackfin/include/asm/mach-bf527/BF525_def.h
deleted file mode 100644
index 930cb59..0000000
--- a/arch/blackfin/include/asm/mach-bf527/BF525_def.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF524_def.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
deleted file mode 100644
index 515acd3..0000000
--- a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF526_proc__
-#define __BFIN_CDEF_ADSP_BF526_proc__
-
-#include "BF524_cdef.h"
-
-#define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
-#define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF526_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_def.h b/arch/blackfin/include/asm/mach-bf527/BF526_def.h
deleted file mode 100644
index 40b5b01..0000000
--- a/arch/blackfin/include/asm/mach-bf527/BF526_def.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF526_proc__
-#define __BFIN_DEF_ADSP_BF526_proc__
-
-#include "BF524_def.h"
-
-#define EMAC_OPMODE                    0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO                    0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI                    0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO                    0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI                    0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD                    0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT                    0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC                       0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1                     0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2                     0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL                  0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0               0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1               0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2               0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3               0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD                0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF                0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0               0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1               0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-#define EMAC_SYSCTL                    0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT                    0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT                   0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY                   0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE                   0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT                   0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY                   0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE                   0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-#define EMAC_MMC_CTL                   0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS                 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE                 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS                 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE                 0xFFC03090 /* MMC TX Interrupt Enables Register */
-#define EMAC_RXC_OK                    0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS                   0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN                 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET                 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF                0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST                0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI                 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD                 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI                0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO                0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG                  0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL                0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE                0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE                 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM                0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT                0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED                 0xFFC03140 /* Type/Length Consistent RX Frame Count  */
-#define EMAC_RXC_SHORT                 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64                  0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128                 0xFFC0314C /* Good RX Frame Count - Byte Count  64 <= x < 128 */
-#define EMAC_RXC_LT256                 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512                 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024                0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024                0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_OK                    0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL                  0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL                0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET                 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER                 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL                0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL                0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND                0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR                0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST                0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI                 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD                 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR                0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL                0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM                0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT                0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64                  0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128                 0xFFC031C4 /* Good TX Frame Count - Byte Count  64 <= x < 128 */
-#define EMAC_TXC_LT256                 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512                 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024                0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024                0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT                 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-#endif /* __BFIN_DEF_ADSP_BF526_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h
deleted file mode 100644
index c5abe62..0000000
--- a/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF526_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF527_def.h b/arch/blackfin/include/asm/mach-bf527/BF527_def.h
deleted file mode 100644
index 9541674..0000000
--- a/arch/blackfin/include/asm/mach-bf527/BF527_def.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF526_def.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/anomaly.h b/arch/blackfin/include/asm/mach-bf527/anomaly.h
deleted file mode 100644
index 6884706..0000000
--- a/arch/blackfin/include/asm/mach-bf527/anomaly.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- *  - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
- *  - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support old silicon - sorry */
-#if __SILICON_REVISION__ < 0
-# error will not work on BF526/BF527 silicon version
-#endif
-
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-# define ANOMALY_BF526 1
-#else
-# define ANOMALY_BF526 0
-#endif
-#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
-# define ANOMALY_BF527 1
-#else
-# define ANOMALY_BF527 0
-#endif
-
-#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
-#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
-#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
-/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0xE510
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
-/* Security Features Are Not Functional */
-#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
-/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Incorrect Default CSEL Value in PLL_DIV */
-#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
-/* Authentication Fails To Initiate */
-#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
-/* Data Read From L3 Memory by USB DMA May be Corrupted */
-#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
-/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
-#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
-/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
-#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
-/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
-#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Default Internal Voltage Regulator Setting */
-#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
-/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* DEB2_URGENT Bit Not Functional */
-#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
-#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
-/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
-#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
-#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
-/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
-#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Internal Voltage Regulator Not Trimmed */
-#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
-#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* The WURESET Bit in the SYSCR Register is not Functional */
-#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
-/* USB DMA Short Packet Data Corruption */
-#define ANOMALY_05000450 (1)
-/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
-#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (1)
-/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
-#define ANOMALY_05000457 (1)
-/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* USB Rx DMA Hang */
-#define ANOMALY_05000465 (1)
-/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (1)
-/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
-#define ANOMALY_05000483 (1)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
-/* The CODEC Zero-Cross Detect Feature is not Functional */
-#define ANOMALY_05000487 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf527/def_local.h b/arch/blackfin/include/asm/mach-bf527/def_local.h
deleted file mode 100644
index 1ffa239..0000000
--- a/arch/blackfin/include/asm/mach-bf527/def_local.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#include "gpio.h"
-#include "mem_map.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define CONFIG_BF52x 1	/* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf527/gpio.h b/arch/blackfin/include/asm/mach-bf527/gpio.h
deleted file mode 100644
index f80c299..0000000
--- a/arch/blackfin/include/asm/mach-bf527/gpio.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0	0
-#define GPIO_PF1	1
-#define GPIO_PF2	2
-#define GPIO_PF3	3
-#define GPIO_PF4	4
-#define GPIO_PF5	5
-#define GPIO_PF6	6
-#define GPIO_PF7	7
-#define GPIO_PF8	8
-#define GPIO_PF9	9
-#define GPIO_PF10	10
-#define GPIO_PF11	11
-#define GPIO_PF12	12
-#define GPIO_PF13	13
-#define GPIO_PF14	14
-#define GPIO_PF15	15
-#define GPIO_PG0	16
-#define GPIO_PG1	17
-#define GPIO_PG2	18
-#define GPIO_PG3	19
-#define GPIO_PG4	20
-#define GPIO_PG5	21
-#define GPIO_PG6	22
-#define GPIO_PG7	23
-#define GPIO_PG8	24
-#define GPIO_PG9	25
-#define GPIO_PG10	26
-#define GPIO_PG11	27
-#define GPIO_PG12	28
-#define GPIO_PG13	29
-#define GPIO_PG14	30
-#define GPIO_PG15	31
-#define GPIO_PH0	32
-#define GPIO_PH1	33
-#define GPIO_PH2	34
-#define GPIO_PH3	35
-#define GPIO_PH4	36
-#define GPIO_PH5	37
-#define GPIO_PH6	38
-#define GPIO_PH7	39
-#define GPIO_PH8	40
-#define GPIO_PH9	41
-#define GPIO_PH10	42
-#define GPIO_PH11	43
-#define GPIO_PH12	44
-#define GPIO_PH13	45
-#define GPIO_PH14	46
-#define GPIO_PH15	47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf527/mem_map.h b/arch/blackfin/include/asm/mach-bf527/mem_map.h
deleted file mode 100644
index 8386b4b..0000000
--- a/arch/blackfin/include/asm/mach-bf527/mem_map.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Common Blackfin memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BF52X_MEM_MAP_H__
-#define __BF52X_MEM_MAP_H__
-
-#define L1_DATA_A_SRAM      (0xFF800000)
-#define L1_DATA_A_SRAM_SIZE (0x4000)
-#define L1_DATA_A_SRAM_END  (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM      (0xFF900000)
-#define L1_DATA_B_SRAM_SIZE (0x4000)
-#define L1_DATA_B_SRAM_END  (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#define L1_INST_SRAM        (0xFFA00000)
-#define L1_INST_SRAM_SIZE   (0xC000)
-#define L1_INST_SRAM_END    (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf527/portmux.h b/arch/blackfin/include/asm/mach-bf527/portmux.h
deleted file mode 100644
index aa16558..0000000
--- a/arch/blackfin/include/asm/mach-bf527/portmux.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_D0	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#if !defined(CONFIG_BF527_SPORT0_PORTG)
-#define P_SPORT0_DRPRI	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_SPORT0_RFS	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_SPORT0_RSCLK	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_SPORT0_DTPRI	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPORT0_TFS	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPORT0_DTSEC	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_SPORT0_DRSEC	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#else
-#define P_SPORT0_DTPRI	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DRSEC	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_SPORT0_DTSEC	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_SPORT0_DRPRI	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_SPORT0_RFS	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT0_RSCLK	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#if !defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
-#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#else
-#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#endif
-#define P_SPORT0_TFS	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#endif
-
-#define P_SPORT1_DRPRI	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_SPORT1_RSCLK	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_SPORT1_RFS	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_SPORT1_TFS	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_SPORT1_DTPRI	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_SPORT1_DTSEC	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_SPORT1_DRSEC	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_SPI0_SSEL6	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_SPI0_SSEL7	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-
-#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-
-#if !defined(CONFIG_BF527_UART1_PORTG)
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#else
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#endif
-
-#define P_CNT_CZM	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3))
-#define P_CNT_CDG	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3))
-#define P_CNT_CUD	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3))
-
-#define P_HWAIT		(P_DONTCARE)
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_SPI0_SCK	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_SPI0_MISO	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_SPI0_MOSI	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR1		(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_FS2	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_TMR3		(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_TMR4		(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_TMR5		(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_TMR6		(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-/* #define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
-#define P_DMAR1		(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_DMAR0		(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_TMR2		(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_MDC		(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_RMII0_MDINT	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_MII0_PHYINT	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-
-#define P_HOST_WR	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-#define P_HOST_ACK	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_HOST_ADDR	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_HOST_RD	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_HOST_CE	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define P_NAND_D0	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_NAND_D1	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_NAND_D2	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_NAND_D3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_NAND_D4	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_NAND_D5	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_NAND_D6	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_NAND_D7	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#else /*if defined(CONFIG_BF527_NAND_D_PORTH)*/
-#define P_NAND_D0	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_NAND_D1	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_NAND_D2	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_NAND_D3	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_NAND_D4	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_NAND_D5	(P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_NAND_D6	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_NAND_D7	(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#endif
-
-#define P_SPI0_SSEL4	(P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_SPI0_SSEL5	(P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_NAND_CE	(P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_NAND_WE	(P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_NAND_RE	(P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_NAND_RB	(P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_NAND_CLE	(P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_NAND_ALE	(P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-
-#define P_HOST_D0	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_HOST_D1	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_HOST_D2	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_HOST_D3	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_HOST_D4	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_HOST_D5	(P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
-#define P_HOST_D6	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_HOST_D7	(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-#define P_HOST_D8	(P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_HOST_D9	(P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
-#define P_HOST_D10	(P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
-#define P_HOST_D11	(P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
-#define P_HOST_D12	(P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
-#define P_HOST_D13	(P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
-#define P_HOST_D14	(P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
-#define P_HOST_D15	(P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
-
-#define P_MII0_ETxD0	(P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_MII0_ETxD1	(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-#define P_MII0_ETxD2	(P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
-#define P_MII0_ETxD3	(P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
-#define P_MII0_ETxEN	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_MII0_TxCLK	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_MII0_COL	(P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-#define P_MII0_ERxD0	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_MII0_ERxD1	(P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
-#define P_MII0_ERxD2	(P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
-#define P_MII0_ERxD3	(P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
-#define P_MII0_ERxDV	(P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
-#define P_MII0_ERxCLK	(P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
-#define P_MII0_ERxER	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_MII0_CRS	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_RMII0_REF_CLK	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_RMII0_CRS_DV	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_MDIO		(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-
-#define P_TWI0_SCL	(P_DONTCARE)
-#define P_TWI0_SDA	(P_DONTCARE)
-#define P_PPI0_FS1	(P_DONTCARE)
-#define P_TMR0		(P_DONTCARE)
-#define P_TMRCLK	(P_DONTCARE)
-#define P_PPI0_CLK	(P_DONTCARE)
-
-#define P_MII0 {\
-	P_MII0_ETxD0, \
-	P_MII0_ETxD1, \
-	P_MII0_ETxD2, \
-	P_MII0_ETxD3, \
-	P_MII0_ETxEN, \
-	P_MII0_TxCLK, \
-	P_MII0_PHYINT, \
-	P_MII0_COL, \
-	P_MII0_ERxD0, \
-	P_MII0_ERxD1, \
-	P_MII0_ERxD2, \
-	P_MII0_ERxD3, \
-	P_MII0_ERxDV, \
-	P_MII0_ERxCLK, \
-	P_MII0_ERxER, \
-	P_MII0_CRS, \
-	P_MDC, \
-	P_MDIO, 0}
-
-#define P_RMII0 {\
-	P_MII0_ETxD0, \
-	P_MII0_ETxD1, \
-	P_MII0_ETxEN, \
-	P_MII0_ERxD0, \
-	P_MII0_ERxD1, \
-	P_MII0_ERxER, \
-	P_RMII0_REF_CLK, \
-	P_RMII0_MDINT, \
-	P_RMII0_CRS_DV, \
-	P_MDC, \
-	P_MDIO, 0}
-
-#endif				/* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf527/ports.h b/arch/blackfin/include/asm/mach-bf527/ports.h
deleted file mode 100644
index e6b1df8..0000000
--- a/arch/blackfin/include/asm/mach-bf527/ports.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORTx_MUX Masks */
-#define PORT_x_MUX_0_MASK	0x0003
-#define PORT_x_MUX_1_MASK	0x000C
-#define PORT_x_MUX_2_MASK	0x0030
-#define PORT_x_MUX_3_MASK	0x00C0
-#define PORT_x_MUX_4_MASK	0x0300
-#define PORT_x_MUX_5_MASK	0x0C00
-#define PORT_x_MUX_6_MASK	0x3000
-#define PORT_x_MUX_7_MASK	0xC000
-
-#define PORT_x_MUX_FUNC_1	(0x0)
-#define PORT_x_MUX_FUNC_2	(0x1)
-#define PORT_x_MUX_FUNC_3	(0x2)
-#define PORT_x_MUX_FUNC_4	(0x3)
-#define PORT_x_MUX_0_FUNC_1	(PORT_x_MUX_FUNC_1 << 0)
-#define PORT_x_MUX_0_FUNC_2	(PORT_x_MUX_FUNC_2 << 0)
-#define PORT_x_MUX_0_FUNC_3	(PORT_x_MUX_FUNC_3 << 0)
-#define PORT_x_MUX_0_FUNC_4	(PORT_x_MUX_FUNC_4 << 0)
-#define PORT_x_MUX_1_FUNC_1	(PORT_x_MUX_FUNC_1 << 2)
-#define PORT_x_MUX_1_FUNC_2	(PORT_x_MUX_FUNC_2 << 2)
-#define PORT_x_MUX_1_FUNC_3	(PORT_x_MUX_FUNC_3 << 2)
-#define PORT_x_MUX_1_FUNC_4	(PORT_x_MUX_FUNC_4 << 2)
-#define PORT_x_MUX_2_FUNC_1	(PORT_x_MUX_FUNC_1 << 4)
-#define PORT_x_MUX_2_FUNC_2	(PORT_x_MUX_FUNC_2 << 4)
-#define PORT_x_MUX_2_FUNC_3	(PORT_x_MUX_FUNC_3 << 4)
-#define PORT_x_MUX_2_FUNC_4	(PORT_x_MUX_FUNC_4 << 4)
-#define PORT_x_MUX_3_FUNC_1	(PORT_x_MUX_FUNC_1 << 6)
-#define PORT_x_MUX_3_FUNC_2	(PORT_x_MUX_FUNC_2 << 6)
-#define PORT_x_MUX_3_FUNC_3	(PORT_x_MUX_FUNC_3 << 6)
-#define PORT_x_MUX_3_FUNC_4	(PORT_x_MUX_FUNC_4 << 6)
-#define PORT_x_MUX_4_FUNC_1	(PORT_x_MUX_FUNC_1 << 8)
-#define PORT_x_MUX_4_FUNC_2	(PORT_x_MUX_FUNC_2 << 8)
-#define PORT_x_MUX_4_FUNC_3	(PORT_x_MUX_FUNC_3 << 8)
-#define PORT_x_MUX_4_FUNC_4	(PORT_x_MUX_FUNC_4 << 8)
-#define PORT_x_MUX_5_FUNC_1	(PORT_x_MUX_FUNC_1 << 10)
-#define PORT_x_MUX_5_FUNC_2	(PORT_x_MUX_FUNC_2 << 10)
-#define PORT_x_MUX_5_FUNC_3	(PORT_x_MUX_FUNC_3 << 10)
-#define PORT_x_MUX_5_FUNC_4	(PORT_x_MUX_FUNC_4 << 10)
-#define PORT_x_MUX_6_FUNC_1	(PORT_x_MUX_FUNC_1 << 12)
-#define PORT_x_MUX_6_FUNC_2	(PORT_x_MUX_FUNC_2 << 12)
-#define PORT_x_MUX_6_FUNC_3	(PORT_x_MUX_FUNC_3 << 12)
-#define PORT_x_MUX_6_FUNC_4	(PORT_x_MUX_FUNC_4 << 12)
-#define PORT_x_MUX_7_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-#include "../mach-common/bits/ports-h.h"
-#include "../mach-common/bits/ports-j.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h
deleted file mode 100644
index 2572bfa..0000000
--- a/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h
+++ /dev/null
@@ -1,872 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF531_proc__
-#define __BFIN_CDEF_ADSP_BF531_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_MDMAFLX0_DMACNFG_D() bfin_read16(MDMAFLX0_DMACNFG_D)
-#define bfin_write_MDMAFLX0_DMACNFG_D(val) bfin_write16(MDMAFLX0_DMACNFG_D, val)
-#define bfin_read_MDMAFLX0_XCOUNT_D()  bfin_read16(MDMAFLX0_XCOUNT_D)
-#define bfin_write_MDMAFLX0_XCOUNT_D(val) bfin_write16(MDMAFLX0_XCOUNT_D, val)
-#define bfin_read_MDMAFLX0_XMODIFY_D() bfin_read16(MDMAFLX0_XMODIFY_D)
-#define bfin_write_MDMAFLX0_XMODIFY_D(val) bfin_write16(MDMAFLX0_XMODIFY_D, val)
-#define bfin_read_MDMAFLX0_YCOUNT_D()  bfin_read16(MDMAFLX0_YCOUNT_D)
-#define bfin_write_MDMAFLX0_YCOUNT_D(val) bfin_write16(MDMAFLX0_YCOUNT_D, val)
-#define bfin_read_MDMAFLX0_YMODIFY_D() bfin_read16(MDMAFLX0_YMODIFY_D)
-#define bfin_write_MDMAFLX0_YMODIFY_D(val) bfin_write16(MDMAFLX0_YMODIFY_D, val)
-#define bfin_read_MDMAFLX0_IRQSTAT_D() bfin_read16(MDMAFLX0_IRQSTAT_D)
-#define bfin_write_MDMAFLX0_IRQSTAT_D(val) bfin_write16(MDMAFLX0_IRQSTAT_D, val)
-#define bfin_read_MDMAFLX0_PMAP_D()    bfin_read16(MDMAFLX0_PMAP_D)
-#define bfin_write_MDMAFLX0_PMAP_D(val) bfin_write16(MDMAFLX0_PMAP_D, val)
-#define bfin_read_MDMAFLX0_CURXCOUNT_D() bfin_read16(MDMAFLX0_CURXCOUNT_D)
-#define bfin_write_MDMAFLX0_CURXCOUNT_D(val) bfin_write16(MDMAFLX0_CURXCOUNT_D, val)
-#define bfin_read_MDMAFLX0_CURYCOUNT_D() bfin_read16(MDMAFLX0_CURYCOUNT_D)
-#define bfin_write_MDMAFLX0_CURYCOUNT_D(val) bfin_write16(MDMAFLX0_CURYCOUNT_D, val)
-#define bfin_read_MDMAFLX0_DMACNFG_S() bfin_read16(MDMAFLX0_DMACNFG_S)
-#define bfin_write_MDMAFLX0_DMACNFG_S(val) bfin_write16(MDMAFLX0_DMACNFG_S, val)
-#define bfin_read_MDMAFLX0_XCOUNT_S()  bfin_read16(MDMAFLX0_XCOUNT_S)
-#define bfin_write_MDMAFLX0_XCOUNT_S(val) bfin_write16(MDMAFLX0_XCOUNT_S, val)
-#define bfin_read_MDMAFLX0_XMODIFY_S() bfin_read16(MDMAFLX0_XMODIFY_S)
-#define bfin_write_MDMAFLX0_XMODIFY_S(val) bfin_write16(MDMAFLX0_XMODIFY_S, val)
-#define bfin_read_MDMAFLX0_YCOUNT_S()  bfin_read16(MDMAFLX0_YCOUNT_S)
-#define bfin_write_MDMAFLX0_YCOUNT_S(val) bfin_write16(MDMAFLX0_YCOUNT_S, val)
-#define bfin_read_MDMAFLX0_YMODIFY_S() bfin_read16(MDMAFLX0_YMODIFY_S)
-#define bfin_write_MDMAFLX0_YMODIFY_S(val) bfin_write16(MDMAFLX0_YMODIFY_S, val)
-#define bfin_read_MDMAFLX0_IRQSTAT_S() bfin_read16(MDMAFLX0_IRQSTAT_S)
-#define bfin_write_MDMAFLX0_IRQSTAT_S(val) bfin_write16(MDMAFLX0_IRQSTAT_S, val)
-#define bfin_read_MDMAFLX0_PMAP_S()    bfin_read16(MDMAFLX0_PMAP_S)
-#define bfin_write_MDMAFLX0_PMAP_S(val) bfin_write16(MDMAFLX0_PMAP_S, val)
-#define bfin_read_MDMAFLX0_CURXCOUNT_S() bfin_read16(MDMAFLX0_CURXCOUNT_S)
-#define bfin_write_MDMAFLX0_CURXCOUNT_S(val) bfin_write16(MDMAFLX0_CURXCOUNT_S, val)
-#define bfin_read_MDMAFLX0_CURYCOUNT_S() bfin_read16(MDMAFLX0_CURYCOUNT_S)
-#define bfin_write_MDMAFLX0_CURYCOUNT_S(val) bfin_write16(MDMAFLX0_CURYCOUNT_S, val)
-#define bfin_read_MDMAFLX1_DMACNFG_D() bfin_read16(MDMAFLX1_DMACNFG_D)
-#define bfin_write_MDMAFLX1_DMACNFG_D(val) bfin_write16(MDMAFLX1_DMACNFG_D, val)
-#define bfin_read_MDMAFLX1_XCOUNT_D()  bfin_read16(MDMAFLX1_XCOUNT_D)
-#define bfin_write_MDMAFLX1_XCOUNT_D(val) bfin_write16(MDMAFLX1_XCOUNT_D, val)
-#define bfin_read_MDMAFLX1_XMODIFY_D() bfin_read16(MDMAFLX1_XMODIFY_D)
-#define bfin_write_MDMAFLX1_XMODIFY_D(val) bfin_write16(MDMAFLX1_XMODIFY_D, val)
-#define bfin_read_MDMAFLX1_YCOUNT_D()  bfin_read16(MDMAFLX1_YCOUNT_D)
-#define bfin_write_MDMAFLX1_YCOUNT_D(val) bfin_write16(MDMAFLX1_YCOUNT_D, val)
-#define bfin_read_MDMAFLX1_YMODIFY_D() bfin_read16(MDMAFLX1_YMODIFY_D)
-#define bfin_write_MDMAFLX1_YMODIFY_D(val) bfin_write16(MDMAFLX1_YMODIFY_D, val)
-#define bfin_read_MDMAFLX1_IRQSTAT_D() bfin_read16(MDMAFLX1_IRQSTAT_D)
-#define bfin_write_MDMAFLX1_IRQSTAT_D(val) bfin_write16(MDMAFLX1_IRQSTAT_D, val)
-#define bfin_read_MDMAFLX1_PMAP_D()    bfin_read16(MDMAFLX1_PMAP_D)
-#define bfin_write_MDMAFLX1_PMAP_D(val) bfin_write16(MDMAFLX1_PMAP_D, val)
-#define bfin_read_MDMAFLX1_CURXCOUNT_D() bfin_read16(MDMAFLX1_CURXCOUNT_D)
-#define bfin_write_MDMAFLX1_CURXCOUNT_D(val) bfin_write16(MDMAFLX1_CURXCOUNT_D, val)
-#define bfin_read_MDMAFLX1_CURYCOUNT_D() bfin_read16(MDMAFLX1_CURYCOUNT_D)
-#define bfin_write_MDMAFLX1_CURYCOUNT_D(val) bfin_write16(MDMAFLX1_CURYCOUNT_D, val)
-#define bfin_read_MDMAFLX1_DMACNFG_S() bfin_read16(MDMAFLX1_DMACNFG_S)
-#define bfin_write_MDMAFLX1_DMACNFG_S(val) bfin_write16(MDMAFLX1_DMACNFG_S, val)
-#define bfin_read_MDMAFLX1_XCOUNT_S()  bfin_read16(MDMAFLX1_XCOUNT_S)
-#define bfin_write_MDMAFLX1_XCOUNT_S(val) bfin_write16(MDMAFLX1_XCOUNT_S, val)
-#define bfin_read_MDMAFLX1_XMODIFY_S() bfin_read16(MDMAFLX1_XMODIFY_S)
-#define bfin_write_MDMAFLX1_XMODIFY_S(val) bfin_write16(MDMAFLX1_XMODIFY_S, val)
-#define bfin_read_MDMAFLX1_YCOUNT_S()  bfin_read16(MDMAFLX1_YCOUNT_S)
-#define bfin_write_MDMAFLX1_YCOUNT_S(val) bfin_write16(MDMAFLX1_YCOUNT_S, val)
-#define bfin_read_MDMAFLX1_YMODIFY_S() bfin_read16(MDMAFLX1_YMODIFY_S)
-#define bfin_write_MDMAFLX1_YMODIFY_S(val) bfin_write16(MDMAFLX1_YMODIFY_S, val)
-#define bfin_read_MDMAFLX1_IRQSTAT_S() bfin_read16(MDMAFLX1_IRQSTAT_S)
-#define bfin_write_MDMAFLX1_IRQSTAT_S(val) bfin_write16(MDMAFLX1_IRQSTAT_S, val)
-#define bfin_read_MDMAFLX1_PMAP_S()    bfin_read16(MDMAFLX1_PMAP_S)
-#define bfin_write_MDMAFLX1_PMAP_S(val) bfin_write16(MDMAFLX1_PMAP_S, val)
-#define bfin_read_MDMAFLX1_CURXCOUNT_S() bfin_read16(MDMAFLX1_CURXCOUNT_S)
-#define bfin_write_MDMAFLX1_CURXCOUNT_S(val) bfin_write16(MDMAFLX1_CURXCOUNT_S, val)
-#define bfin_read_MDMAFLX1_CURYCOUNT_S() bfin_read16(MDMAFLX1_CURYCOUNT_S)
-#define bfin_write_MDMAFLX1_CURYCOUNT_S(val) bfin_write16(MDMAFLX1_CURYCOUNT_S, val)
-#define bfin_read_DMAFLX0_DMACNFG()    bfin_read16(DMAFLX0_DMACNFG)
-#define bfin_write_DMAFLX0_DMACNFG(val) bfin_write16(DMAFLX0_DMACNFG, val)
-#define bfin_read_DMAFLX0_XCOUNT()     bfin_read16(DMAFLX0_XCOUNT)
-#define bfin_write_DMAFLX0_XCOUNT(val) bfin_write16(DMAFLX0_XCOUNT, val)
-#define bfin_read_DMAFLX0_XMODIFY()    bfin_read16(DMAFLX0_XMODIFY)
-#define bfin_write_DMAFLX0_XMODIFY(val) bfin_write16(DMAFLX0_XMODIFY, val)
-#define bfin_read_DMAFLX0_YCOUNT()     bfin_read16(DMAFLX0_YCOUNT)
-#define bfin_write_DMAFLX0_YCOUNT(val) bfin_write16(DMAFLX0_YCOUNT, val)
-#define bfin_read_DMAFLX0_YMODIFY()    bfin_read16(DMAFLX0_YMODIFY)
-#define bfin_write_DMAFLX0_YMODIFY(val) bfin_write16(DMAFLX0_YMODIFY, val)
-#define bfin_read_DMAFLX0_IRQSTAT()    bfin_read16(DMAFLX0_IRQSTAT)
-#define bfin_write_DMAFLX0_IRQSTAT(val) bfin_write16(DMAFLX0_IRQSTAT, val)
-#define bfin_read_DMAFLX0_PMAP()       bfin_read16(DMAFLX0_PMAP)
-#define bfin_write_DMAFLX0_PMAP(val)   bfin_write16(DMAFLX0_PMAP, val)
-#define bfin_read_DMAFLX0_CURXCOUNT()  bfin_read16(DMAFLX0_CURXCOUNT)
-#define bfin_write_DMAFLX0_CURXCOUNT(val) bfin_write16(DMAFLX0_CURXCOUNT, val)
-#define bfin_read_DMAFLX0_CURYCOUNT()  bfin_read16(DMAFLX0_CURYCOUNT)
-#define bfin_write_DMAFLX0_CURYCOUNT(val) bfin_write16(DMAFLX0_CURYCOUNT, val)
-#define bfin_read_DMAFLX1_DMACNFG()    bfin_read16(DMAFLX1_DMACNFG)
-#define bfin_write_DMAFLX1_DMACNFG(val) bfin_write16(DMAFLX1_DMACNFG, val)
-#define bfin_read_DMAFLX1_XCOUNT()     bfin_read16(DMAFLX1_XCOUNT)
-#define bfin_write_DMAFLX1_XCOUNT(val) bfin_write16(DMAFLX1_XCOUNT, val)
-#define bfin_read_DMAFLX1_XMODIFY()    bfin_read16(DMAFLX1_XMODIFY)
-#define bfin_write_DMAFLX1_XMODIFY(val) bfin_write16(DMAFLX1_XMODIFY, val)
-#define bfin_read_DMAFLX1_YCOUNT()     bfin_read16(DMAFLX1_YCOUNT)
-#define bfin_write_DMAFLX1_YCOUNT(val) bfin_write16(DMAFLX1_YCOUNT, val)
-#define bfin_read_DMAFLX1_YMODIFY()    bfin_read16(DMAFLX1_YMODIFY)
-#define bfin_write_DMAFLX1_YMODIFY(val) bfin_write16(DMAFLX1_YMODIFY, val)
-#define bfin_read_DMAFLX1_IRQSTAT()    bfin_read16(DMAFLX1_IRQSTAT)
-#define bfin_write_DMAFLX1_IRQSTAT(val) bfin_write16(DMAFLX1_IRQSTAT, val)
-#define bfin_read_DMAFLX1_PMAP()       bfin_read16(DMAFLX1_PMAP)
-#define bfin_write_DMAFLX1_PMAP(val)   bfin_write16(DMAFLX1_PMAP, val)
-#define bfin_read_DMAFLX1_CURXCOUNT()  bfin_read16(DMAFLX1_CURXCOUNT)
-#define bfin_write_DMAFLX1_CURXCOUNT(val) bfin_write16(DMAFLX1_CURXCOUNT, val)
-#define bfin_read_DMAFLX1_CURYCOUNT()  bfin_read16(DMAFLX1_CURYCOUNT)
-#define bfin_write_DMAFLX1_CURYCOUNT(val) bfin_write16(DMAFLX1_CURYCOUNT, val)
-#define bfin_read_DMAFLX2_DMACNFG()    bfin_read16(DMAFLX2_DMACNFG)
-#define bfin_write_DMAFLX2_DMACNFG(val) bfin_write16(DMAFLX2_DMACNFG, val)
-#define bfin_read_DMAFLX2_XCOUNT()     bfin_read16(DMAFLX2_XCOUNT)
-#define bfin_write_DMAFLX2_XCOUNT(val) bfin_write16(DMAFLX2_XCOUNT, val)
-#define bfin_read_DMAFLX2_XMODIFY()    bfin_read16(DMAFLX2_XMODIFY)
-#define bfin_write_DMAFLX2_XMODIFY(val) bfin_write16(DMAFLX2_XMODIFY, val)
-#define bfin_read_DMAFLX2_YCOUNT()     bfin_read16(DMAFLX2_YCOUNT)
-#define bfin_write_DMAFLX2_YCOUNT(val) bfin_write16(DMAFLX2_YCOUNT, val)
-#define bfin_read_DMAFLX2_YMODIFY()    bfin_read16(DMAFLX2_YMODIFY)
-#define bfin_write_DMAFLX2_YMODIFY(val) bfin_write16(DMAFLX2_YMODIFY, val)
-#define bfin_read_DMAFLX2_IRQSTAT()    bfin_read16(DMAFLX2_IRQSTAT)
-#define bfin_write_DMAFLX2_IRQSTAT(val) bfin_write16(DMAFLX2_IRQSTAT, val)
-#define bfin_read_DMAFLX2_PMAP()       bfin_read16(DMAFLX2_PMAP)
-#define bfin_write_DMAFLX2_PMAP(val)   bfin_write16(DMAFLX2_PMAP, val)
-#define bfin_read_DMAFLX2_CURXCOUNT()  bfin_read16(DMAFLX2_CURXCOUNT)
-#define bfin_write_DMAFLX2_CURXCOUNT(val) bfin_write16(DMAFLX2_CURXCOUNT, val)
-#define bfin_read_DMAFLX2_CURYCOUNT()  bfin_read16(DMAFLX2_CURYCOUNT)
-#define bfin_write_DMAFLX2_CURYCOUNT(val) bfin_write16(DMAFLX2_CURYCOUNT, val)
-#define bfin_read_DMAFLX3_DMACNFG()    bfin_read16(DMAFLX3_DMACNFG)
-#define bfin_write_DMAFLX3_DMACNFG(val) bfin_write16(DMAFLX3_DMACNFG, val)
-#define bfin_read_DMAFLX3_XCOUNT()     bfin_read16(DMAFLX3_XCOUNT)
-#define bfin_write_DMAFLX3_XCOUNT(val) bfin_write16(DMAFLX3_XCOUNT, val)
-#define bfin_read_DMAFLX3_XMODIFY()    bfin_read16(DMAFLX3_XMODIFY)
-#define bfin_write_DMAFLX3_XMODIFY(val) bfin_write16(DMAFLX3_XMODIFY, val)
-#define bfin_read_DMAFLX3_YCOUNT()     bfin_read16(DMAFLX3_YCOUNT)
-#define bfin_write_DMAFLX3_YCOUNT(val) bfin_write16(DMAFLX3_YCOUNT, val)
-#define bfin_read_DMAFLX3_YMODIFY()    bfin_read16(DMAFLX3_YMODIFY)
-#define bfin_write_DMAFLX3_YMODIFY(val) bfin_write16(DMAFLX3_YMODIFY, val)
-#define bfin_read_DMAFLX3_IRQSTAT()    bfin_read16(DMAFLX3_IRQSTAT)
-#define bfin_write_DMAFLX3_IRQSTAT(val) bfin_write16(DMAFLX3_IRQSTAT, val)
-#define bfin_read_DMAFLX3_PMAP()       bfin_read16(DMAFLX3_PMAP)
-#define bfin_write_DMAFLX3_PMAP(val)   bfin_write16(DMAFLX3_PMAP, val)
-#define bfin_read_DMAFLX3_CURXCOUNT()  bfin_read16(DMAFLX3_CURXCOUNT)
-#define bfin_write_DMAFLX3_CURXCOUNT(val) bfin_write16(DMAFLX3_CURXCOUNT, val)
-#define bfin_read_DMAFLX3_CURYCOUNT()  bfin_read16(DMAFLX3_CURYCOUNT)
-#define bfin_write_DMAFLX3_CURYCOUNT(val) bfin_write16(DMAFLX3_CURYCOUNT, val)
-#define bfin_read_DMAFLX4_DMACNFG()    bfin_read16(DMAFLX4_DMACNFG)
-#define bfin_write_DMAFLX4_DMACNFG(val) bfin_write16(DMAFLX4_DMACNFG, val)
-#define bfin_read_DMAFLX4_XCOUNT()     bfin_read16(DMAFLX4_XCOUNT)
-#define bfin_write_DMAFLX4_XCOUNT(val) bfin_write16(DMAFLX4_XCOUNT, val)
-#define bfin_read_DMAFLX4_XMODIFY()    bfin_read16(DMAFLX4_XMODIFY)
-#define bfin_write_DMAFLX4_XMODIFY(val) bfin_write16(DMAFLX4_XMODIFY, val)
-#define bfin_read_DMAFLX4_YCOUNT()     bfin_read16(DMAFLX4_YCOUNT)
-#define bfin_write_DMAFLX4_YCOUNT(val) bfin_write16(DMAFLX4_YCOUNT, val)
-#define bfin_read_DMAFLX4_YMODIFY()    bfin_read16(DMAFLX4_YMODIFY)
-#define bfin_write_DMAFLX4_YMODIFY(val) bfin_write16(DMAFLX4_YMODIFY, val)
-#define bfin_read_DMAFLX4_IRQSTAT()    bfin_read16(DMAFLX4_IRQSTAT)
-#define bfin_write_DMAFLX4_IRQSTAT(val) bfin_write16(DMAFLX4_IRQSTAT, val)
-#define bfin_read_DMAFLX4_PMAP()       bfin_read16(DMAFLX4_PMAP)
-#define bfin_write_DMAFLX4_PMAP(val)   bfin_write16(DMAFLX4_PMAP, val)
-#define bfin_read_DMAFLX4_CURXCOUNT()  bfin_read16(DMAFLX4_CURXCOUNT)
-#define bfin_write_DMAFLX4_CURXCOUNT(val) bfin_write16(DMAFLX4_CURXCOUNT, val)
-#define bfin_read_DMAFLX4_CURYCOUNT()  bfin_read16(DMAFLX4_CURYCOUNT)
-#define bfin_write_DMAFLX4_CURYCOUNT(val) bfin_write16(DMAFLX4_CURYCOUNT, val)
-#define bfin_read_DMAFLX5_DMACNFG()    bfin_read16(DMAFLX5_DMACNFG)
-#define bfin_write_DMAFLX5_DMACNFG(val) bfin_write16(DMAFLX5_DMACNFG, val)
-#define bfin_read_DMAFLX5_XCOUNT()     bfin_read16(DMAFLX5_XCOUNT)
-#define bfin_write_DMAFLX5_XCOUNT(val) bfin_write16(DMAFLX5_XCOUNT, val)
-#define bfin_read_DMAFLX5_XMODIFY()    bfin_read16(DMAFLX5_XMODIFY)
-#define bfin_write_DMAFLX5_XMODIFY(val) bfin_write16(DMAFLX5_XMODIFY, val)
-#define bfin_read_DMAFLX5_YCOUNT()     bfin_read16(DMAFLX5_YCOUNT)
-#define bfin_write_DMAFLX5_YCOUNT(val) bfin_write16(DMAFLX5_YCOUNT, val)
-#define bfin_read_DMAFLX5_YMODIFY()    bfin_read16(DMAFLX5_YMODIFY)
-#define bfin_write_DMAFLX5_YMODIFY(val) bfin_write16(DMAFLX5_YMODIFY, val)
-#define bfin_read_DMAFLX5_IRQSTAT()    bfin_read16(DMAFLX5_IRQSTAT)
-#define bfin_write_DMAFLX5_IRQSTAT(val) bfin_write16(DMAFLX5_IRQSTAT, val)
-#define bfin_read_DMAFLX5_PMAP()       bfin_read16(DMAFLX5_PMAP)
-#define bfin_write_DMAFLX5_PMAP(val)   bfin_write16(DMAFLX5_PMAP, val)
-#define bfin_read_DMAFLX5_CURXCOUNT()  bfin_read16(DMAFLX5_CURXCOUNT)
-#define bfin_write_DMAFLX5_CURXCOUNT(val) bfin_write16(DMAFLX5_CURXCOUNT, val)
-#define bfin_read_DMAFLX5_CURYCOUNT()  bfin_read16(DMAFLX5_CURYCOUNT)
-#define bfin_write_DMAFLX5_CURYCOUNT(val) bfin_write16(DMAFLX5_CURYCOUNT, val)
-#define bfin_read_DMAFLX6_DMACNFG()    bfin_read16(DMAFLX6_DMACNFG)
-#define bfin_write_DMAFLX6_DMACNFG(val) bfin_write16(DMAFLX6_DMACNFG, val)
-#define bfin_read_DMAFLX6_XCOUNT()     bfin_read16(DMAFLX6_XCOUNT)
-#define bfin_write_DMAFLX6_XCOUNT(val) bfin_write16(DMAFLX6_XCOUNT, val)
-#define bfin_read_DMAFLX6_XMODIFY()    bfin_read16(DMAFLX6_XMODIFY)
-#define bfin_write_DMAFLX6_XMODIFY(val) bfin_write16(DMAFLX6_XMODIFY, val)
-#define bfin_read_DMAFLX6_YCOUNT()     bfin_read16(DMAFLX6_YCOUNT)
-#define bfin_write_DMAFLX6_YCOUNT(val) bfin_write16(DMAFLX6_YCOUNT, val)
-#define bfin_read_DMAFLX6_YMODIFY()    bfin_read16(DMAFLX6_YMODIFY)
-#define bfin_write_DMAFLX6_YMODIFY(val) bfin_write16(DMAFLX6_YMODIFY, val)
-#define bfin_read_DMAFLX6_IRQSTAT()    bfin_read16(DMAFLX6_IRQSTAT)
-#define bfin_write_DMAFLX6_IRQSTAT(val) bfin_write16(DMAFLX6_IRQSTAT, val)
-#define bfin_read_DMAFLX6_PMAP()       bfin_read16(DMAFLX6_PMAP)
-#define bfin_write_DMAFLX6_PMAP(val)   bfin_write16(DMAFLX6_PMAP, val)
-#define bfin_read_DMAFLX6_CURXCOUNT()  bfin_read16(DMAFLX6_CURXCOUNT)
-#define bfin_write_DMAFLX6_CURXCOUNT(val) bfin_write16(DMAFLX6_CURXCOUNT, val)
-#define bfin_read_DMAFLX6_CURYCOUNT()  bfin_read16(DMAFLX6_CURYCOUNT)
-#define bfin_write_DMAFLX6_CURYCOUNT(val) bfin_write16(DMAFLX6_CURYCOUNT, val)
-#define bfin_read_DMAFLX7_DMACNFG()    bfin_read16(DMAFLX7_DMACNFG)
-#define bfin_write_DMAFLX7_DMACNFG(val) bfin_write16(DMAFLX7_DMACNFG, val)
-#define bfin_read_DMAFLX7_XCOUNT()     bfin_read16(DMAFLX7_XCOUNT)
-#define bfin_write_DMAFLX7_XCOUNT(val) bfin_write16(DMAFLX7_XCOUNT, val)
-#define bfin_read_DMAFLX7_XMODIFY()    bfin_read16(DMAFLX7_XMODIFY)
-#define bfin_write_DMAFLX7_XMODIFY(val) bfin_write16(DMAFLX7_XMODIFY, val)
-#define bfin_read_DMAFLX7_YCOUNT()     bfin_read16(DMAFLX7_YCOUNT)
-#define bfin_write_DMAFLX7_YCOUNT(val) bfin_write16(DMAFLX7_YCOUNT, val)
-#define bfin_read_DMAFLX7_YMODIFY()    bfin_read16(DMAFLX7_YMODIFY)
-#define bfin_write_DMAFLX7_YMODIFY(val) bfin_write16(DMAFLX7_YMODIFY, val)
-#define bfin_read_DMAFLX7_IRQSTAT()    bfin_read16(DMAFLX7_IRQSTAT)
-#define bfin_write_DMAFLX7_IRQSTAT(val) bfin_write16(DMAFLX7_IRQSTAT, val)
-#define bfin_read_DMAFLX7_PMAP()       bfin_read16(DMAFLX7_PMAP)
-#define bfin_write_DMAFLX7_PMAP(val)   bfin_write16(DMAFLX7_PMAP, val)
-#define bfin_read_DMAFLX7_CURXCOUNT()  bfin_read16(DMAFLX7_CURXCOUNT)
-#define bfin_write_DMAFLX7_CURXCOUNT(val) bfin_write16(DMAFLX7_CURXCOUNT, val)
-#define bfin_read_DMAFLX7_CURYCOUNT()  bfin_read16(DMAFLX7_CURYCOUNT)
-#define bfin_write_DMAFLX7_CURYCOUNT(val) bfin_write16(DMAFLX7_CURYCOUNT, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()       bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)   bfin_write16(TIMER_STATUS, val)
-#define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK()          bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val)      bfin_write32(SIC_IMASK, val)
-#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR()            bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val)        bfin_write32(SIC_ISR, val)
-#define bfin_read_SIC_IWR()            bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val)        bfin_write32(SIC_IWR, val)
-#define bfin_read_UART_THR()           bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val)       bfin_write16(UART_THR, val)
-#define bfin_read_UART_DLL()           bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val)       bfin_write16(UART_DLL, val)
-#define bfin_read_UART_DLH()           bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val)       bfin_write16(UART_DLH, val)
-#define bfin_read_UART_IER()           bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val)       bfin_write16(UART_IER, val)
-#define bfin_read_UART_IIR()           bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val)       bfin_write16(UART_IIR, val)
-#define bfin_read_UART_LCR()           bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val)       bfin_write16(UART_LCR, val)
-#define bfin_read_UART_MCR()           bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val)       bfin_write16(UART_MCR, val)
-#define bfin_read_UART_LSR()           bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val)       bfin_write16(UART_LSR, val)
-#define bfin_read_UART_SCR()           bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val)       bfin_write16(UART_SCR, val)
-#define bfin_read_UART_RBR()           bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val)       bfin_write16(UART_RBR, val)
-#define bfin_read_UART_GCTL()          bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val)      bfin_write16(UART_GCTL, val)
-#define bfin_read_SPT0_TX_CONFIG0()    bfin_read16(SPT0_TX_CONFIG0)
-#define bfin_write_SPT0_TX_CONFIG0(val) bfin_write16(SPT0_TX_CONFIG0, val)
-#define bfin_read_SPT0_TX_CONFIG1()    bfin_read16(SPT0_TX_CONFIG1)
-#define bfin_write_SPT0_TX_CONFIG1(val) bfin_write16(SPT0_TX_CONFIG1, val)
-#define bfin_read_SPT0_RX_CONFIG0()    bfin_read16(SPT0_RX_CONFIG0)
-#define bfin_write_SPT0_RX_CONFIG0(val) bfin_write16(SPT0_RX_CONFIG0, val)
-#define bfin_read_SPT0_RX_CONFIG1()    bfin_read16(SPT0_RX_CONFIG1)
-#define bfin_write_SPT0_RX_CONFIG1(val) bfin_write16(SPT0_RX_CONFIG1, val)
-#define bfin_read_SPT0_TX()            bfin_read32(SPT0_TX)
-#define bfin_write_SPT0_TX(val)        bfin_write32(SPT0_TX, val)
-#define bfin_read_SPT0_RX()            bfin_read32(SPT0_RX)
-#define bfin_write_SPT0_RX(val)        bfin_write32(SPT0_RX, val)
-#define bfin_read_SPT0_TSCLKDIV()      bfin_read16(SPT0_TSCLKDIV)
-#define bfin_write_SPT0_TSCLKDIV(val)  bfin_write16(SPT0_TSCLKDIV, val)
-#define bfin_read_SPT0_RSCLKDIV()      bfin_read16(SPT0_RSCLKDIV)
-#define bfin_write_SPT0_RSCLKDIV(val)  bfin_write16(SPT0_RSCLKDIV, val)
-#define bfin_read_SPT0_TFSDIV()        bfin_read16(SPT0_TFSDIV)
-#define bfin_write_SPT0_TFSDIV(val)    bfin_write16(SPT0_TFSDIV, val)
-#define bfin_read_SPT0_RFSDIV()        bfin_read16(SPT0_RFSDIV)
-#define bfin_write_SPT0_RFSDIV(val)    bfin_write16(SPT0_RFSDIV, val)
-#define bfin_read_SPT0_STAT()          bfin_read16(SPT0_STAT)
-#define bfin_write_SPT0_STAT(val)      bfin_write16(SPT0_STAT, val)
-#define bfin_read_SPT0_MTCS0()         bfin_read32(SPT0_MTCS0)
-#define bfin_write_SPT0_MTCS0(val)     bfin_write32(SPT0_MTCS0, val)
-#define bfin_read_SPT0_MTCS1()         bfin_read32(SPT0_MTCS1)
-#define bfin_write_SPT0_MTCS1(val)     bfin_write32(SPT0_MTCS1, val)
-#define bfin_read_SPT0_MTCS2()         bfin_read32(SPT0_MTCS2)
-#define bfin_write_SPT0_MTCS2(val)     bfin_write32(SPT0_MTCS2, val)
-#define bfin_read_SPT0_MTCS3()         bfin_read32(SPT0_MTCS3)
-#define bfin_write_SPT0_MTCS3(val)     bfin_write32(SPT0_MTCS3, val)
-#define bfin_read_SPT0_MRCS0()         bfin_read32(SPT0_MRCS0)
-#define bfin_write_SPT0_MRCS0(val)     bfin_write32(SPT0_MRCS0, val)
-#define bfin_read_SPT0_MRCS1()         bfin_read32(SPT0_MRCS1)
-#define bfin_write_SPT0_MRCS1(val)     bfin_write32(SPT0_MRCS1, val)
-#define bfin_read_SPT0_MRCS2()         bfin_read32(SPT0_MRCS2)
-#define bfin_write_SPT0_MRCS2(val)     bfin_write32(SPT0_MRCS2, val)
-#define bfin_read_SPT0_MRCS3()         bfin_read32(SPT0_MRCS3)
-#define bfin_write_SPT0_MRCS3(val)     bfin_write32(SPT0_MRCS3, val)
-#define bfin_read_SPT0_MCMC1()         bfin_read16(SPT0_MCMC1)
-#define bfin_write_SPT0_MCMC1(val)     bfin_write16(SPT0_MCMC1, val)
-#define bfin_read_SPT0_MCMC2()         bfin_read16(SPT0_MCMC2)
-#define bfin_write_SPT0_MCMC2(val)     bfin_write16(SPT0_MCMC2, val)
-#define bfin_read_SPT0_CHNL()          bfin_read16(SPT0_CHNL)
-#define bfin_write_SPT0_CHNL(val)      bfin_write16(SPT0_CHNL, val)
-#define bfin_read_SPT1_TX_CONFIG0()    bfin_read16(SPT1_TX_CONFIG0)
-#define bfin_write_SPT1_TX_CONFIG0(val) bfin_write16(SPT1_TX_CONFIG0, val)
-#define bfin_read_SPT1_TX_CONFIG1()    bfin_read16(SPT1_TX_CONFIG1)
-#define bfin_write_SPT1_TX_CONFIG1(val) bfin_write16(SPT1_TX_CONFIG1, val)
-#define bfin_read_SPT1_RX_CONFIG0()    bfin_read16(SPT1_RX_CONFIG0)
-#define bfin_write_SPT1_RX_CONFIG0(val) bfin_write16(SPT1_RX_CONFIG0, val)
-#define bfin_read_SPT1_RX_CONFIG1()    bfin_read16(SPT1_RX_CONFIG1)
-#define bfin_write_SPT1_RX_CONFIG1(val) bfin_write16(SPT1_RX_CONFIG1, val)
-#define bfin_read_SPT1_TX()            bfin_read16(SPT1_TX)
-#define bfin_write_SPT1_TX(val)        bfin_write16(SPT1_TX, val)
-#define bfin_read_SPT1_RX()            bfin_read16(SPT1_RX)
-#define bfin_write_SPT1_RX(val)        bfin_write16(SPT1_RX, val)
-#define bfin_read_SPT1_TSCLKDIV()      bfin_read16(SPT1_TSCLKDIV)
-#define bfin_write_SPT1_TSCLKDIV(val)  bfin_write16(SPT1_TSCLKDIV, val)
-#define bfin_read_SPT1_RSCLKDIV()      bfin_read16(SPT1_RSCLKDIV)
-#define bfin_write_SPT1_RSCLKDIV(val)  bfin_write16(SPT1_RSCLKDIV, val)
-#define bfin_read_SPT1_TFSDIV()        bfin_read16(SPT1_TFSDIV)
-#define bfin_write_SPT1_TFSDIV(val)    bfin_write16(SPT1_TFSDIV, val)
-#define bfin_read_SPT1_RFSDIV()        bfin_read16(SPT1_RFSDIV)
-#define bfin_write_SPT1_RFSDIV(val)    bfin_write16(SPT1_RFSDIV, val)
-#define bfin_read_SPT1_STAT()          bfin_read16(SPT1_STAT)
-#define bfin_write_SPT1_STAT(val)      bfin_write16(SPT1_STAT, val)
-#define bfin_read_SPT1_MTCS0()         bfin_read32(SPT1_MTCS0)
-#define bfin_write_SPT1_MTCS0(val)     bfin_write32(SPT1_MTCS0, val)
-#define bfin_read_SPT1_MTCS1()         bfin_read32(SPT1_MTCS1)
-#define bfin_write_SPT1_MTCS1(val)     bfin_write32(SPT1_MTCS1, val)
-#define bfin_read_SPT1_MTCS2()         bfin_read32(SPT1_MTCS2)
-#define bfin_write_SPT1_MTCS2(val)     bfin_write32(SPT1_MTCS2, val)
-#define bfin_read_SPT1_MTCS3()         bfin_read32(SPT1_MTCS3)
-#define bfin_write_SPT1_MTCS3(val)     bfin_write32(SPT1_MTCS3, val)
-#define bfin_read_SPT1_MRCS0()         bfin_read32(SPT1_MRCS0)
-#define bfin_write_SPT1_MRCS0(val)     bfin_write32(SPT1_MRCS0, val)
-#define bfin_read_SPT1_MRCS1()         bfin_read32(SPT1_MRCS1)
-#define bfin_write_SPT1_MRCS1(val)     bfin_write32(SPT1_MRCS1, val)
-#define bfin_read_SPT1_MRCS2()         bfin_read32(SPT1_MRCS2)
-#define bfin_write_SPT1_MRCS2(val)     bfin_write32(SPT1_MRCS2, val)
-#define bfin_read_SPT1_MRCS3()         bfin_read32(SPT1_MRCS3)
-#define bfin_write_SPT1_MRCS3(val)     bfin_write32(SPT1_MRCS3, val)
-#define bfin_read_SPT1_MCMC1()         bfin_read16(SPT1_MCMC1)
-#define bfin_write_SPT1_MCMC1(val)     bfin_write16(SPT1_MCMC1, val)
-#define bfin_read_SPT1_MCMC2()         bfin_read16(SPT1_MCMC2)
-#define bfin_write_SPT1_MCMC2(val)     bfin_write16(SPT1_MCMC2, val)
-#define bfin_read_SPT1_CHNL()          bfin_read16(SPT1_CHNL)
-#define bfin_write_SPT1_CHNL(val)      bfin_write16(SPT1_CHNL, val)
-#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define bfin_read_TBUF()               bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
-#define bfin_read_PFCTL()              bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
-#define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
-#define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
-#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
-#define bfin_read_FIO_FLAG_D()         bfin_read16(FIO_FLAG_D)
-#define bfin_write_FIO_FLAG_D(val)     bfin_write16(FIO_FLAG_D, val)
-#define bfin_read_FIO_FLAG_C()         bfin_read16(FIO_FLAG_C)
-#define bfin_write_FIO_FLAG_C(val)     bfin_write16(FIO_FLAG_C, val)
-#define bfin_read_FIO_FLAG_S()         bfin_read16(FIO_FLAG_S)
-#define bfin_write_FIO_FLAG_S(val)     bfin_write16(FIO_FLAG_S, val)
-#define bfin_read_FIO_FLAG_T()         bfin_read16(FIO_FLAG_T)
-#define bfin_write_FIO_FLAG_T(val)     bfin_write16(FIO_FLAG_T, val)
-#define bfin_read_FIO_MASKA_D()        bfin_read16(FIO_MASKA_D)
-#define bfin_write_FIO_MASKA_D(val)    bfin_write16(FIO_MASKA_D, val)
-#define bfin_read_FIO_MASKA_C()        bfin_read16(FIO_MASKA_C)
-#define bfin_write_FIO_MASKA_C(val)    bfin_write16(FIO_MASKA_C, val)
-#define bfin_read_FIO_MASKA_S()        bfin_read16(FIO_MASKA_S)
-#define bfin_write_FIO_MASKA_S(val)    bfin_write16(FIO_MASKA_S, val)
-#define bfin_read_FIO_MASKA_T()        bfin_read16(FIO_MASKA_T)
-#define bfin_write_FIO_MASKA_T(val)    bfin_write16(FIO_MASKA_T, val)
-#define bfin_read_FIO_MASKB_D()        bfin_read16(FIO_MASKB_D)
-#define bfin_write_FIO_MASKB_D(val)    bfin_write16(FIO_MASKB_D, val)
-#define bfin_read_FIO_MASKB_C()        bfin_read16(FIO_MASKB_C)
-#define bfin_write_FIO_MASKB_C(val)    bfin_write16(FIO_MASKB_C, val)
-#define bfin_read_FIO_MASKB_S()        bfin_read16(FIO_MASKB_S)
-#define bfin_write_FIO_MASKB_S(val)    bfin_write16(FIO_MASKB_S, val)
-#define bfin_read_FIO_MASKB_T()        bfin_read16(FIO_MASKB_T)
-#define bfin_write_FIO_MASKB_T(val)    bfin_write16(FIO_MASKB_T, val)
-#define bfin_read_FIO_DIR()            bfin_read16(FIO_DIR)
-#define bfin_write_FIO_DIR(val)        bfin_write16(FIO_DIR, val)
-#define bfin_read_FIO_POLAR()          bfin_read16(FIO_POLAR)
-#define bfin_write_FIO_POLAR(val)      bfin_write16(FIO_POLAR, val)
-#define bfin_read_FIO_EDGE()           bfin_read16(FIO_EDGE)
-#define bfin_write_FIO_EDGE(val)       bfin_write16(FIO_EDGE, val)
-#define bfin_read_FIO_BOTH()           bfin_read16(FIO_BOTH)
-#define bfin_write_FIO_BOTH(val)       bfin_write16(FIO_BOTH, val)
-#define bfin_read_FIO_INEN()           bfin_read16(FIO_INEN)
-#define bfin_write_FIO_INEN(val)       bfin_write16(FIO_INEN, val)
-#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()    bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()     bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()    bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()     bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()    bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()     bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()    bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()     bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()    bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()     bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()    bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()     bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()    bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()     bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()    bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()     bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF531_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf533/BF531_def.h b/arch/blackfin/include/asm/mach-bf533/BF531_def.h
deleted file mode 100644
index 2bcd2d8..0000000
--- a/arch/blackfin/include/asm/mach-bf533/BF531_def.h
+++ /dev/null
@@ -1,444 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF531_proc__
-#define __BFIN_DEF_ADSP_BF531_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define MDMAFLX0_DMACNFG_D             0xFFC00E08
-#define MDMAFLX0_XCOUNT_D              0xFFC00E10
-#define MDMAFLX0_XMODIFY_D             0xFFC00E14
-#define MDMAFLX0_YCOUNT_D              0xFFC00E18
-#define MDMAFLX0_YMODIFY_D             0xFFC00E1C
-#define MDMAFLX0_IRQSTAT_D             0xFFC00E28
-#define MDMAFLX0_PMAP_D                0xFFC00E2C
-#define MDMAFLX0_CURXCOUNT_D           0xFFC00E30
-#define MDMAFLX0_CURYCOUNT_D           0xFFC00E38
-#define MDMAFLX0_DMACNFG_S             0xFFC00E48
-#define MDMAFLX0_XCOUNT_S              0xFFC00E50
-#define MDMAFLX0_XMODIFY_S             0xFFC00E54
-#define MDMAFLX0_YCOUNT_S              0xFFC00E58
-#define MDMAFLX0_YMODIFY_S             0xFFC00E5C
-#define MDMAFLX0_IRQSTAT_S             0xFFC00E68
-#define MDMAFLX0_PMAP_S                0xFFC00E6C
-#define MDMAFLX0_CURXCOUNT_S           0xFFC00E70
-#define MDMAFLX0_CURYCOUNT_S           0xFFC00E78
-#define MDMAFLX1_DMACNFG_D             0xFFC00E88
-#define MDMAFLX1_XCOUNT_D              0xFFC00E90
-#define MDMAFLX1_XMODIFY_D             0xFFC00E94
-#define MDMAFLX1_YCOUNT_D              0xFFC00E98
-#define MDMAFLX1_YMODIFY_D             0xFFC00E9C
-#define MDMAFLX1_IRQSTAT_D             0xFFC00EA8
-#define MDMAFLX1_PMAP_D                0xFFC00EAC
-#define MDMAFLX1_CURXCOUNT_D           0xFFC00EB0
-#define MDMAFLX1_CURYCOUNT_D           0xFFC00EB8
-#define MDMAFLX1_DMACNFG_S             0xFFC00EC8
-#define MDMAFLX1_XCOUNT_S              0xFFC00ED0
-#define MDMAFLX1_XMODIFY_S             0xFFC00ED4
-#define MDMAFLX1_YCOUNT_S              0xFFC00ED8
-#define MDMAFLX1_YMODIFY_S             0xFFC00EDC
-#define MDMAFLX1_IRQSTAT_S             0xFFC00EE8
-#define MDMAFLX1_PMAP_S                0xFFC00EEC
-#define MDMAFLX1_CURXCOUNT_S           0xFFC00EF0
-#define MDMAFLX1_CURYCOUNT_S           0xFFC00EF8
-#define DMAFLX0_DMACNFG                0xFFC00C08
-#define DMAFLX0_XCOUNT                 0xFFC00C10
-#define DMAFLX0_XMODIFY                0xFFC00C14
-#define DMAFLX0_YCOUNT                 0xFFC00C18
-#define DMAFLX0_YMODIFY                0xFFC00C1C
-#define DMAFLX0_IRQSTAT                0xFFC00C28
-#define DMAFLX0_PMAP                   0xFFC00C2C
-#define DMAFLX0_CURXCOUNT              0xFFC00C30
-#define DMAFLX0_CURYCOUNT              0xFFC00C38
-#define DMAFLX1_DMACNFG                0xFFC00C48
-#define DMAFLX1_XCOUNT                 0xFFC00C50
-#define DMAFLX1_XMODIFY                0xFFC00C54
-#define DMAFLX1_YCOUNT                 0xFFC00C58
-#define DMAFLX1_YMODIFY                0xFFC00C5C
-#define DMAFLX1_IRQSTAT                0xFFC00C68
-#define DMAFLX1_PMAP                   0xFFC00C6C
-#define DMAFLX1_CURXCOUNT              0xFFC00C70
-#define DMAFLX1_CURYCOUNT              0xFFC00C78
-#define DMAFLX2_DMACNFG                0xFFC00C88
-#define DMAFLX2_XCOUNT                 0xFFC00C90
-#define DMAFLX2_XMODIFY                0xFFC00C94
-#define DMAFLX2_YCOUNT                 0xFFC00C98
-#define DMAFLX2_YMODIFY                0xFFC00C9C
-#define DMAFLX2_IRQSTAT                0xFFC00CA8
-#define DMAFLX2_PMAP                   0xFFC00CAC
-#define DMAFLX2_CURXCOUNT              0xFFC00CB0
-#define DMAFLX2_CURYCOUNT              0xFFC00CB8
-#define DMAFLX3_DMACNFG                0xFFC00CC8
-#define DMAFLX3_XCOUNT                 0xFFC00CD0
-#define DMAFLX3_XMODIFY                0xFFC00CD4
-#define DMAFLX3_YCOUNT                 0xFFC00CD8
-#define DMAFLX3_YMODIFY                0xFFC00CDC
-#define DMAFLX3_IRQSTAT                0xFFC00CE8
-#define DMAFLX3_PMAP                   0xFFC00CEC
-#define DMAFLX3_CURXCOUNT              0xFFC00CF0
-#define DMAFLX3_CURYCOUNT              0xFFC00CF8
-#define DMAFLX4_DMACNFG                0xFFC00D08
-#define DMAFLX4_XCOUNT                 0xFFC00D10
-#define DMAFLX4_XMODIFY                0xFFC00D14
-#define DMAFLX4_YCOUNT                 0xFFC00D18
-#define DMAFLX4_YMODIFY                0xFFC00D1C
-#define DMAFLX4_IRQSTAT                0xFFC00D28
-#define DMAFLX4_PMAP                   0xFFC00D2C
-#define DMAFLX4_CURXCOUNT              0xFFC00D30
-#define DMAFLX4_CURYCOUNT              0xFFC00D38
-#define DMAFLX5_DMACNFG                0xFFC00D48
-#define DMAFLX5_XCOUNT                 0xFFC00D50
-#define DMAFLX5_XMODIFY                0xFFC00D54
-#define DMAFLX5_YCOUNT                 0xFFC00D58
-#define DMAFLX5_YMODIFY                0xFFC00D5C
-#define DMAFLX5_IRQSTAT                0xFFC00D68
-#define DMAFLX5_PMAP                   0xFFC00D6C
-#define DMAFLX5_CURXCOUNT              0xFFC00D70
-#define DMAFLX5_CURYCOUNT              0xFFC00D78
-#define DMAFLX6_DMACNFG                0xFFC00D88
-#define DMAFLX6_XCOUNT                 0xFFC00D90
-#define DMAFLX6_XMODIFY                0xFFC00D94
-#define DMAFLX6_YCOUNT                 0xFFC00D98
-#define DMAFLX6_YMODIFY                0xFFC00D9C
-#define DMAFLX6_IRQSTAT                0xFFC00DA8
-#define DMAFLX6_PMAP                   0xFFC00DAC
-#define DMAFLX6_CURXCOUNT              0xFFC00DB0
-#define DMAFLX6_CURYCOUNT              0xFFC00DB8
-#define DMAFLX7_DMACNFG                0xFFC00DC8
-#define DMAFLX7_XCOUNT                 0xFFC00DD0
-#define DMAFLX7_XMODIFY                0xFFC00DD4
-#define DMAFLX7_YCOUNT                 0xFFC00DD8
-#define DMAFLX7_YMODIFY                0xFFC00DDC
-#define DMAFLX7_IRQSTAT                0xFFC00DE8
-#define DMAFLX7_PMAP                   0xFFC00DEC
-#define DMAFLX7_CURXCOUNT              0xFFC00DF0
-#define DMAFLX7_CURYCOUNT              0xFFC00DF8
-#define TIMER0_CONFIG                  0xFFC00600
-#define TIMER0_COUNTER                 0xFFC00604
-#define TIMER0_PERIOD                  0xFFC00608
-#define TIMER0_WIDTH                   0xFFC0060C
-#define TIMER1_CONFIG                  0xFFC00610
-#define TIMER1_COUNTER                 0xFFC00614
-#define TIMER1_PERIOD                  0xFFC00618
-#define TIMER1_WIDTH                   0xFFC0061C
-#define TIMER2_CONFIG                  0xFFC00620
-#define TIMER2_COUNTER                 0xFFC00624
-#define TIMER2_PERIOD                  0xFFC00628
-#define TIMER2_WIDTH                   0xFFC0062C
-#define TIMER_ENABLE                   0xFFC00640
-#define TIMER_DISABLE                  0xFFC00644
-#define TIMER_STATUS                   0xFFC00648
-#define SIC_RVECT                      0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK                      0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR                        0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR                        0xFFC00124 /* Interrupt Wakeup Register */
-#define UART_THR                       0xFFC00400 /* Transmit Holding */
-#define UART_DLL                       0xFFC00400 /* Divisor Latch Low Byte */
-#define UART_DLH                       0xFFC00404 /* Divisor Latch High Byte */
-#define UART_IER                       0xFFC00404
-#define UART_IIR                       0xFFC00408
-#define UART_LCR                       0xFFC0040C
-#define UART_MCR                       0xFFC00410
-#define UART_LSR                       0xFFC00414
-#define UART_SCR                       0xFFC0041C
-#define UART_RBR                       0xFFC00400 /* Receive Buffer */
-#define UART0_RBR                      UART_RBR
-#define UART_GCTL                      0xFFC00424
-#define SPT0_TX_CONFIG0                0xFFC00800
-#define SPT0_TX_CONFIG1                0xFFC00804
-#define SPT0_RX_CONFIG0                0xFFC00820
-#define SPT0_RX_CONFIG1                0xFFC00824
-#define SPT0_TX                        0xFFC00810
-#define SPT0_RX                        0xFFC00818
-#define SPT0_TSCLKDIV                  0xFFC00808
-#define SPT0_RSCLKDIV                  0xFFC00828
-#define SPT0_TFSDIV                    0xFFC0080C
-#define SPT0_RFSDIV                    0xFFC0082C
-#define SPT0_STAT                      0xFFC00830
-#define SPT0_MTCS0                     0xFFC00840
-#define SPT0_MTCS1                     0xFFC00844
-#define SPT0_MTCS2                     0xFFC00848
-#define SPT0_MTCS3                     0xFFC0084C
-#define SPT0_MRCS0                     0xFFC00850
-#define SPT0_MRCS1                     0xFFC00854
-#define SPT0_MRCS2                     0xFFC00858
-#define SPT0_MRCS3                     0xFFC0085C
-#define SPT0_MCMC1                     0xFFC00838
-#define SPT0_MCMC2                     0xFFC0083C
-#define SPT0_CHNL                      0xFFC00834
-#define SPT1_TX_CONFIG0                0xFFC00900
-#define SPT1_TX_CONFIG1                0xFFC00904
-#define SPT1_RX_CONFIG0                0xFFC00920
-#define SPT1_RX_CONFIG1                0xFFC00924
-#define SPT1_TX                        0xFFC00910
-#define SPT1_RX                        0xFFC00918
-#define SPT1_TSCLKDIV                  0xFFC00908
-#define SPT1_RSCLKDIV                  0xFFC00928
-#define SPT1_TFSDIV                    0xFFC0090C
-#define SPT1_RFSDIV                    0xFFC0092C
-#define SPT1_STAT                      0xFFC00930
-#define SPT1_MTCS0                     0xFFC00940
-#define SPT1_MTCS1                     0xFFC00944
-#define SPT1_MTCS2                     0xFFC00948
-#define SPT1_MTCS3                     0xFFC0094C
-#define SPT1_MRCS0                     0xFFC00950
-#define SPT1_MRCS1                     0xFFC00954
-#define SPT1_MRCS2                     0xFFC00958
-#define SPT1_MRCS3                     0xFFC0095C
-#define SPT1_MCMC1                     0xFFC00938
-#define SPT1_MCMC2                     0xFFC0093C
-#define SPT1_CHNL                      0xFFC00934
-#define PPI_CONTROL                    0xFFC01000
-#define PPI_STATUS                     0xFFC01004
-#define PPI_DELAY                      0xFFC0100C
-#define PPI_COUNT                      0xFFC01008
-#define PPI_FRAME                      0xFFC01010
-#define PLL_CTL                        0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV                        0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT                       0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define SWRST                          0xFFC00100 /* Software Reset Register (16-bit) */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-#define CHIPID                         0xFFC00014
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define RTC_STAT                       0xFFC00300
-#define RTC_ICTL                       0xFFC00304
-#define RTC_ISTAT                      0xFFC00308
-#define RTC_SWCNT                      0xFFC0030C
-#define RTC_ALARM                      0xFFC00310
-#define RTC_PREN                       0xFFC00314
-#define SPI_CTL                        0xFFC00500
-#define SPI_FLG                        0xFFC00504
-#define SPI_STAT                       0xFFC00508
-#define SPI_TDBR                       0xFFC0050C
-#define SPI_RDBR                       0xFFC00510
-#define SPI_BAUD                       0xFFC00514
-#define SPI_SHADOW                     0xFFC00518
-#define FIO_FLAG_D                     0xFFC00700
-#define FIO_FLAG_C                     0xFFC00704
-#define FIO_FLAG_S                     0xFFC00708
-#define FIO_FLAG_T                     0xFFC0070C
-#define FIO_MASKA_D                    0xFFC00710
-#define FIO_MASKA_C                    0xFFC00714
-#define FIO_MASKA_S                    0xFFC00718
-#define FIO_MASKA_T                    0xFFC0071C
-#define FIO_MASKB_D                    0xFFC00720
-#define FIO_MASKB_C                    0xFFC00724
-#define FIO_MASKB_S                    0xFFC00728
-#define FIO_MASKB_T                    0xFFC0072C
-#define FIO_DIR                        0xFFC00730
-#define FIO_POLAR                      0xFFC00734
-#define FIO_EDGE                       0xFFC00738
-#define FIO_BOTH                       0xFFC0073C
-#define FIO_INEN                       0xFFC00740
-#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                      0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX                      0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                      0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX                      0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00
-#define DMA0_START_ADDR                0xFFC00C04
-#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                   0xFFC00C10
-#define DMA0_X_MODIFY                  0xFFC00C14
-#define DMA0_Y_COUNT                   0xFFC00C18
-#define DMA0_Y_MODIFY                  0xFFC00C1C
-#define DMA0_CURR_DESC_PTR             0xFFC00C20
-#define DMA0_CURR_ADDR                 0xFFC00C24
-#define DMA0_IRQ_STATUS                0xFFC00C28
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C
-#define DMA0_CURR_X_COUNT              0xFFC00C30
-#define DMA0_CURR_Y_COUNT              0xFFC00C38
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40
-#define DMA1_START_ADDR                0xFFC00C44
-#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC00C50
-#define DMA1_X_MODIFY                  0xFFC00C54
-#define DMA1_Y_COUNT                   0xFFC00C58
-#define DMA1_Y_MODIFY                  0xFFC00C5C
-#define DMA1_CURR_DESC_PTR             0xFFC00C60
-#define DMA1_CURR_ADDR                 0xFFC00C64
-#define DMA1_IRQ_STATUS                0xFFC00C68
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C
-#define DMA1_CURR_X_COUNT              0xFFC00C70
-#define DMA1_CURR_Y_COUNT              0xFFC00C78
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80
-#define DMA2_START_ADDR                0xFFC00C84
-#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC00C90
-#define DMA2_X_MODIFY                  0xFFC00C94
-#define DMA2_Y_COUNT                   0xFFC00C98
-#define DMA2_Y_MODIFY                  0xFFC00C9C
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0
-#define DMA2_CURR_ADDR                 0xFFC00CA4
-#define DMA2_IRQ_STATUS                0xFFC00CA8
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC
-#define DMA2_CURR_X_COUNT              0xFFC00CB0
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0
-#define DMA3_START_ADDR                0xFFC00CC4
-#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC00CD0
-#define DMA3_X_MODIFY                  0xFFC00CD4
-#define DMA3_Y_COUNT                   0xFFC00CD8
-#define DMA3_Y_MODIFY                  0xFFC00CDC
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0
-#define DMA3_CURR_ADDR                 0xFFC00CE4
-#define DMA3_IRQ_STATUS                0xFFC00CE8
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC
-#define DMA3_CURR_X_COUNT              0xFFC00CF0
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00
-#define DMA4_START_ADDR                0xFFC00D04
-#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC00D10
-#define DMA4_X_MODIFY                  0xFFC00D14
-#define DMA4_Y_COUNT                   0xFFC00D18
-#define DMA4_Y_MODIFY                  0xFFC00D1C
-#define DMA4_CURR_DESC_PTR             0xFFC00D20
-#define DMA4_CURR_ADDR                 0xFFC00D24
-#define DMA4_IRQ_STATUS                0xFFC00D28
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C
-#define DMA4_CURR_X_COUNT              0xFFC00D30
-#define DMA4_CURR_Y_COUNT              0xFFC00D38
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40
-#define DMA5_START_ADDR                0xFFC00D44
-#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC00D50
-#define DMA5_X_MODIFY                  0xFFC00D54
-#define DMA5_Y_COUNT                   0xFFC00D58
-#define DMA5_Y_MODIFY                  0xFFC00D5C
-#define DMA5_CURR_DESC_PTR             0xFFC00D60
-#define DMA5_CURR_ADDR                 0xFFC00D64
-#define DMA5_IRQ_STATUS                0xFFC00D68
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C
-#define DMA5_CURR_X_COUNT              0xFFC00D70
-#define DMA5_CURR_Y_COUNT              0xFFC00D78
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80
-#define DMA6_START_ADDR                0xFFC00D84
-#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC00D90
-#define DMA6_X_MODIFY                  0xFFC00D94
-#define DMA6_Y_COUNT                   0xFFC00D98
-#define DMA6_Y_MODIFY                  0xFFC00D9C
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0
-#define DMA6_CURR_ADDR                 0xFFC00DA4
-#define DMA6_IRQ_STATUS                0xFFC00DA8
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC
-#define DMA6_CURR_X_COUNT              0xFFC00DB0
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0
-#define DMA7_START_ADDR                0xFFC00DC4
-#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC00DD0
-#define DMA7_X_MODIFY                  0xFFC00DD4
-#define DMA7_Y_COUNT                   0xFFC00DD8
-#define DMA7_Y_MODIFY                  0xFFC00DDC
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0
-#define DMA7_CURR_ADDR                 0xFFC00DE4
-#define DMA7_IRQ_STATUS                0xFFC00DE8
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC
-#define DMA7_CURR_X_COUNT              0xFFC00DF0
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8
-#define MDMA_D0_NEXT_DESC_PTR          0xFFC00E00
-#define MDMA_D0_START_ADDR             0xFFC00E04
-#define MDMA_D0_CONFIG                 0xFFC00E08
-#define MDMA_D0_X_COUNT                0xFFC00E10
-#define MDMA_D0_X_MODIFY               0xFFC00E14
-#define MDMA_D0_Y_COUNT                0xFFC00E18
-#define MDMA_D0_Y_MODIFY               0xFFC00E1C
-#define MDMA_D0_CURR_DESC_PTR          0xFFC00E20
-#define MDMA_D0_CURR_ADDR              0xFFC00E24
-#define MDMA_D0_IRQ_STATUS             0xFFC00E28
-#define MDMA_D0_PERIPHERAL_MAP         0xFFC00E2C
-#define MDMA_D0_CURR_X_COUNT           0xFFC00E30
-#define MDMA_D0_CURR_Y_COUNT           0xFFC00E38
-#define MDMA_S0_NEXT_DESC_PTR          0xFFC00E40
-#define MDMA_S0_START_ADDR             0xFFC00E44
-#define MDMA_S0_CONFIG                 0xFFC00E48
-#define MDMA_S0_X_COUNT                0xFFC00E50
-#define MDMA_S0_X_MODIFY               0xFFC00E54
-#define MDMA_S0_Y_COUNT                0xFFC00E58
-#define MDMA_S0_Y_MODIFY               0xFFC00E5C
-#define MDMA_S0_CURR_DESC_PTR          0xFFC00E60
-#define MDMA_S0_CURR_ADDR              0xFFC00E64
-#define MDMA_S0_IRQ_STATUS             0xFFC00E68
-#define MDMA_S0_PERIPHERAL_MAP         0xFFC00E6C
-#define MDMA_S0_CURR_X_COUNT           0xFFC00E70
-#define MDMA_S0_CURR_Y_COUNT           0xFFC00E78
-#define MDMA_D1_NEXT_DESC_PTR          0xFFC00E80
-#define MDMA_D1_START_ADDR             0xFFC00E84
-#define MDMA_D1_CONFIG                 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT                0xFFC00E90
-#define MDMA_D1_X_MODIFY               0xFFC00E94
-#define MDMA_D1_Y_COUNT                0xFFC00E98
-#define MDMA_D1_Y_MODIFY               0xFFC00E9C
-#define MDMA_D1_CURR_DESC_PTR          0xFFC00EA0
-#define MDMA_D1_CURR_ADDR              0xFFC00EA4
-#define MDMA_D1_IRQ_STATUS             0xFFC00EA8
-#define MDMA_D1_PERIPHERAL_MAP         0xFFC00EAC
-#define MDMA_D1_CURR_X_COUNT           0xFFC00EB0
-#define MDMA_D1_CURR_Y_COUNT           0xFFC00EB8
-#define MDMA_S1_NEXT_DESC_PTR          0xFFC00EC0
-#define MDMA_S1_START_ADDR             0xFFC00EC4
-#define MDMA_S1_CONFIG                 0xFFC00EC8
-#define MDMA_S1_X_COUNT                0xFFC00ED0
-#define MDMA_S1_X_MODIFY               0xFFC00ED4
-#define MDMA_S1_Y_COUNT                0xFFC00ED8
-#define MDMA_S1_Y_MODIFY               0xFFC00EDC
-#define MDMA_S1_CURR_DESC_PTR          0xFFC00EE0
-#define MDMA_S1_CURR_ADDR              0xFFC00EE4
-#define MDMA_S1_IRQ_STATUS             0xFFC00EE8
-#define MDMA_S1_PERIPHERAL_MAP         0xFFC00EEC
-#define MDMA_S1_CURR_X_COUNT           0xFFC00EF0
-#define MDMA_S1_CURR_Y_COUNT           0xFFC00EF8
-#define EBIU_AMGCTL                    0xFFC00A00
-#define EBIU_AMBCTL0                   0xFFC00A04
-#define EBIU_AMBCTL1                   0xFFC00A08
-#define EBIU_SDGCTL                    0xFFC00A10
-#define EBIU_SDBCTL                    0xFFC00A14
-#define EBIU_SDRRC                     0xFFC00A18
-#define EBIU_SDSTAT                    0xFFC00A1C
-#define DMA_TC_CNT                     0xFFC00B0C
-#define DMA_TC_PER                     0xFFC00B10
-
-#ifndef __BFIN_DEF_ADSP_BF533_proc__
-#define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-#endif
-
-#endif /* __BFIN_DEF_ADSP_BF531_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h
deleted file mode 100644
index 09f2521..0000000
--- a/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF531_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf533/BF532_def.h b/arch/blackfin/include/asm/mach-bf533/BF532_def.h
deleted file mode 100644
index 64f55f5..0000000
--- a/arch/blackfin/include/asm/mach-bf533/BF532_def.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF532_proc__
-#define __BFIN_DEF_ADSP_BF532_proc__
-
-#include "BF531_def.h"
-
-#ifndef __BFIN_DEF_ADSP_BF533_proc__
-#define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-#endif
-
-#endif /* __BFIN_DEF_ADSP_BF532_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h
deleted file mode 100644
index 3044327..0000000
--- a/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF532_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf533/BF533_def.h b/arch/blackfin/include/asm/mach-bf533/BF533_def.h
deleted file mode 100644
index 3c0595f..0000000
--- a/arch/blackfin/include/asm/mach-bf533/BF533_def.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF533_proc__
-#define __BFIN_DEF_ADSP_BF533_proc__
-
-#include "BF532_def.h"
-
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
-#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif /* __BFIN_DEF_ADSP_BF533_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf533/anomaly.h b/arch/blackfin/include/asm/mach-bf533/anomaly.h
deleted file mode 100644
index 03f2b40..0000000
--- a/arch/blackfin/include/asm/mach-bf533/anomaly.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- *  - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 or 0.2 silicon - sorry */
-#if __SILICON_REVISION__ < 3
-# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
-#endif
-
-#if defined(__ADSPBF531__)
-# define ANOMALY_BF531 1
-#else
-# define ANOMALY_BF531 0
-#endif
-#if defined(__ADSPBF532__)
-# define ANOMALY_BF532 1
-#else
-# define ANOMALY_BF532 0
-#endif
-#if defined(__ADSPBF533__)
-# define ANOMALY_BF533 1
-#else
-# define ANOMALY_BF533 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
-#define ANOMALY_05000105 (__SILICON_REVISION__ > 2)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
-#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
-/* False Protection Exceptions when Speculative Fetch Is Cancelled */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
-/* Failing MMR Accesses when Preceding Memory Read Stalls */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4)
-/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
-#define ANOMALY_05000201 (__SILICON_REVISION__ == 3)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
-/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Data CPLBs Should Prevent False Hardware Errors */
-#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
-/* Spontaneous Reset of Internal Voltage Regulator */
-#define ANOMALY_05000271 (__SILICON_REVISION__ == 3)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (1)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
-/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */
-#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (1)	/* note: brokenness is noted in documentation, not anomaly sheet */
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
-#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
-/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
-#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
-/* PPI Does Not Start Properly In Specific Mode */
-#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
-#define ANOMALY_05000471 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Internal voltage regulator can't be modified via register writes */
-#define ANOMALY_05000066 (__SILICON_REVISION__ < 2)
-/* Watchpoints (Hardware Breakpoints) are not supported */
-#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
-/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */
-#define ANOMALY_05000070 (__SILICON_REVISION__ < 2)
-/* Writing FIO_DIR can corrupt a programmable flag's data */
-#define ANOMALY_05000079 (__SILICON_REVISION__ < 2)
-/* Timer Auto-Baud Mode requires the UART clock to be enabled. */
-#define ANOMALY_05000086 (__SILICON_REVISION__ < 2)
-/* Internal Clocking Modes on SPORT0 not supported */
-#define ANOMALY_05000088 (__SILICON_REVISION__ < 2)
-/* Internal voltage regulator does not wake up from an RTC wakeup */
-#define ANOMALY_05000092 (__SILICON_REVISION__ < 2)
-/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */
-#define ANOMALY_05000093 (__SILICON_REVISION__ < 2)
-/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */
-#define ANOMALY_05000095 (__SILICON_REVISION__ < 2)
-/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */
-#define ANOMALY_05000096 (__SILICON_REVISION__ < 2)
-/* Performance Monitor 0 and 1 are swapped when monitoring memory events */
-#define ANOMALY_05000097 (__SILICON_REVISION__ < 2)
-/* 32-bit SPORT DMA will be word reversed */
-#define ANOMALY_05000098 (__SILICON_REVISION__ < 2)
-/* Incorrect status in the UART_IIR register */
-#define ANOMALY_05000100 (__SILICON_REVISION__ < 2)
-/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */
-#define ANOMALY_05000101 (__SILICON_REVISION__ < 2)
-/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
-#define ANOMALY_05000102 (__SILICON_REVISION__ < 2)
-/* Incorrect Value Written to the Cycle Counters */
-#define ANOMALY_05000103 (__SILICON_REVISION__ < 2)
-/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */
-#define ANOMALY_05000104 (__SILICON_REVISION__ < 2)
-/* Programmable Flag (PF3) functionality not supported in all PPI modes */
-#define ANOMALY_05000106 (__SILICON_REVISION__ < 2)
-/* Data store can be lost when targeting a cache line fill */
-#define ANOMALY_05000107 (__SILICON_REVISION__ < 2)
-/* Reserved Bits in SYSCFG Register Not Set at Power-On */
-#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
-/* Infinite Core Stall */
-#define ANOMALY_05000114 (__SILICON_REVISION__ < 2)
-/* PPI_FSx may glitch when generated by the on chip Timers. */
-#define ANOMALY_05000115 (__SILICON_REVISION__ < 2)
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */
-#define ANOMALY_05000117 (__SILICON_REVISION__ < 2)
-/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */
-#define ANOMALY_05000118 (__SILICON_REVISION__ < 2)
-/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */
-#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* SPI clock polarity and phase bits incorrect during booting */
-#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> Is Not Set on Reset */
-#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
-/* SPI boot will not complete if there is a zero fill block in the loader file */
-#define ANOMALY_05000138 (__SILICON_REVISION__ == 2)
-/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */
-#define ANOMALY_05000139 (__SILICON_REVISION__ < 2)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */
-#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
-#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
-/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
-/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
-/* Disabling the PPI Resets the PPI Configuration Registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
-/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */
-#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
-/* Internal Voltage Regulator may not start up */
-#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf533/def_local.h b/arch/blackfin/include/asm/mach-bf533/def_local.h
deleted file mode 100644
index c545b54..0000000
--- a/arch/blackfin/include/asm/mach-bf533/def_local.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define BF533_FAMILY 1	/* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf533/gpio.h b/arch/blackfin/include/asm/mach-bf533/gpio.h
deleted file mode 100644
index e02416d..0000000
--- a/arch/blackfin/include/asm/mach-bf533/gpio.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 16
-
-#define GPIO_PF0	0
-#define GPIO_PF1	1
-#define GPIO_PF2	2
-#define GPIO_PF3	3
-#define GPIO_PF4	4
-#define GPIO_PF5	5
-#define GPIO_PF6	6
-#define GPIO_PF7	7
-#define GPIO_PF8	8
-#define GPIO_PF9	9
-#define GPIO_PF10	10
-#define GPIO_PF11	11
-#define GPIO_PF12	12
-#define GPIO_PF13	13
-#define GPIO_PF14	14
-#define GPIO_PF15	15
-
-#define PORT_F GPIO_PF0
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf533/portmux.h b/arch/blackfin/include/asm/mach-bf533/portmux.h
deleted file mode 100644
index 96f5d91..0000000
--- a/arch/blackfin/include/asm/mach-bf533/portmux.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK	(P_DONTCARE)
-#define P_PPI0_FS1	(P_DONTCARE)
-#define P_PPI0_FS2	(P_DONTCARE)
-#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF11))
-#define P_PPI0_D0	(P_DONTCARE)
-#define P_PPI0_D1	(P_DONTCARE)
-#define P_PPI0_D2	(P_DONTCARE)
-#define P_PPI0_D3	(P_DONTCARE)
-#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF12))
-
-#define P_SPORT1_TSCLK	(P_DONTCARE)
-#define P_SPORT1_RSCLK	(P_DONTCARE)
-#define P_SPORT0_TSCLK	(P_DONTCARE)
-#define P_SPORT0_RSCLK	(P_DONTCARE)
-#define P_UART0_RX	(P_DONTCARE)
-#define P_UART0_TX	(P_DONTCARE)
-#define P_SPORT1_DRSEC	(P_DONTCARE)
-#define P_SPORT1_RFS	(P_DONTCARE)
-#define P_SPORT1_DTPRI	(P_DONTCARE)
-#define P_SPORT1_DTSEC	(P_DONTCARE)
-#define P_SPORT1_TFS	(P_DONTCARE)
-#define P_SPORT1_DRPRI	(P_DONTCARE)
-#define P_SPORT0_DRSEC	(P_DONTCARE)
-#define P_SPORT0_RFS	(P_DONTCARE)
-#define P_SPORT0_DTPRI	(P_DONTCARE)
-#define P_SPORT0_DTSEC	(P_DONTCARE)
-#define P_SPORT0_TFS	(P_DONTCARE)
-#define P_SPORT0_DRPRI	(P_DONTCARE)
-
-#define P_SPI0_MOSI	(P_DONTCARE)
-#define P_SPI0_MISO	(P_DONTCARE)
-#define P_SPI0_SCK	(P_DONTCARE)
-#define P_SPI0_SSEL7	(P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6	(P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5	(P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4	(P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PF0))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#define P_TMR2		(P_DONTCARE)
-#define P_TMR1		(P_DONTCARE)
-#define P_TMR0		(P_DONTCARE)
-#define P_TMRCLK	(P_DEFINED | P_IDENT(GPIO_PF1))
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf533/ports.h b/arch/blackfin/include/asm/mach-bf533/ports.h
deleted file mode 100644
index 512d6df..0000000
--- a/arch/blackfin/include/asm/mach-bf533/ports.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-#include "../mach-common/bits/ports-f.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h
deleted file mode 100644
index 3d9412d..0000000
--- a/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h
+++ /dev/null
@@ -1,1624 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF534_proc__
-#define __BFIN_CDEF_ADSP_BF534_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK()          bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val)      bfin_write32(SIC_IMASK, val)
-#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR()            bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val)        bfin_write32(SIC_ISR, val)
-#define bfin_read_SIC_IWR()            bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val)        bfin_write32(SIC_IWR, val)
-#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()       bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)   bfin_write32(TIMER_STATUS, val)
-#define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI_CLKDIV()         bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val)     bfin_write16(TWI_CLKDIV, val)
-#define bfin_read_TWI_CONTROL()        bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val)    bfin_write16(TWI_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTL()      bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val)  bfin_write16(TWI_SLAVE_CTL, val)
-#define bfin_read_TWI_SLAVE_STAT()     bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR()     bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL()     bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define bfin_read_TWI_MASTER_STAT()    bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR()    bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT()       bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val)   bfin_write16(TWI_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK()       bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val)   bfin_write16(TWI_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL()       bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val)   bfin_write16(TWI_FIFO_CTL, val)
-#define bfin_read_TWI_FIFO_STAT()      bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val)  bfin_write16(TWI_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8()      bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val)  bfin_write16(TWI_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16()     bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8()      bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val)  bfin_write16(TWI_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16()     bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define bfin_read_PORTGIO()            bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val)        bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR()      bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val)  bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET()        bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val)    bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE()     bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA()      bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val)  bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET()  bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB()      bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val)  bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET()  bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR()        bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val)    bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR()      bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val)  bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE()       bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val)   bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH()       bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val)   bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN()       bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val)   bfin_write16(PORTGIO_INEN, val)
-#define bfin_read_PORTHIO()            bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val)        bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR()      bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val)  bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET()        bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val)    bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE()     bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA()      bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val)  bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET()  bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB()      bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val)  bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET()  bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR()        bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val)    bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR()      bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val)  bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE()       bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val)   bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH()       bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val)   bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN()       bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val)   bfin_write16(PORTHIO_INEN, val)
-#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define bfin_read_CAN_MC1()            bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val)        bfin_write16(CAN_MC1, val)
-#define bfin_read_CAN_MD1()            bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val)        bfin_write16(CAN_MD1, val)
-#define bfin_read_CAN_TRS1()           bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val)       bfin_write16(CAN_TRS1, val)
-#define bfin_read_CAN_TRR1()           bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val)       bfin_write16(CAN_TRR1, val)
-#define bfin_read_CAN_TA1()            bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val)        bfin_write16(CAN_TA1, val)
-#define bfin_read_CAN_AA1()            bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val)        bfin_write16(CAN_AA1, val)
-#define bfin_read_CAN_RMP1()           bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val)       bfin_write16(CAN_RMP1, val)
-#define bfin_read_CAN_RML1()           bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val)       bfin_write16(CAN_RML1, val)
-#define bfin_read_CAN_MBTIF1()         bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val)     bfin_write16(CAN_MBTIF1, val)
-#define bfin_read_CAN_MBRIF1()         bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val)     bfin_write16(CAN_MBRIF1, val)
-#define bfin_read_CAN_MBIM1()          bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val)      bfin_write16(CAN_MBIM1, val)
-#define bfin_read_CAN_RFH1()           bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val)       bfin_write16(CAN_RFH1, val)
-#define bfin_read_CAN_OPSS1()          bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val)      bfin_write16(CAN_OPSS1, val)
-#define bfin_read_CAN_MC2()            bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val)        bfin_write16(CAN_MC2, val)
-#define bfin_read_CAN_MD2()            bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val)        bfin_write16(CAN_MD2, val)
-#define bfin_read_CAN_TRS2()           bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val)       bfin_write16(CAN_TRS2, val)
-#define bfin_read_CAN_TRR2()           bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val)       bfin_write16(CAN_TRR2, val)
-#define bfin_read_CAN_TA2()            bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val)        bfin_write16(CAN_TA2, val)
-#define bfin_read_CAN_AA2()            bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val)        bfin_write16(CAN_AA2, val)
-#define bfin_read_CAN_RMP2()           bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val)       bfin_write16(CAN_RMP2, val)
-#define bfin_read_CAN_RML2()           bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val)       bfin_write16(CAN_RML2, val)
-#define bfin_read_CAN_MBTIF2()         bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val)     bfin_write16(CAN_MBTIF2, val)
-#define bfin_read_CAN_MBRIF2()         bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val)     bfin_write16(CAN_MBRIF2, val)
-#define bfin_read_CAN_MBIM2()          bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val)      bfin_write16(CAN_MBIM2, val)
-#define bfin_read_CAN_RFH2()           bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val)       bfin_write16(CAN_RFH2, val)
-#define bfin_read_CAN_OPSS2()          bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val)      bfin_write16(CAN_OPSS2, val)
-#define bfin_read_CAN_CLOCK()          bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val)      bfin_write16(CAN_CLOCK, val)
-#define bfin_read_CAN_TIMING()         bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val)     bfin_write16(CAN_TIMING, val)
-#define bfin_read_CAN_DEBUG()          bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val)      bfin_write16(CAN_DEBUG, val)
-#define bfin_read_CAN_STATUS()         bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val)     bfin_write16(CAN_STATUS, val)
-#define bfin_read_CAN_CEC()            bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val)        bfin_write16(CAN_CEC, val)
-#define bfin_read_CAN_GIS()            bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val)        bfin_write16(CAN_GIS, val)
-#define bfin_read_CAN_GIM()            bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val)        bfin_write16(CAN_GIM, val)
-#define bfin_read_CAN_GIF()            bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val)        bfin_write16(CAN_GIF, val)
-#define bfin_read_CAN_CONTROL()        bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val)    bfin_write16(CAN_CONTROL, val)
-#define bfin_read_CAN_INTR()           bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val)       bfin_write16(CAN_INTR, val)
-#define bfin_read_CAN_VERSION()        bfin_read16(CAN_VERSION)
-#define bfin_write_CAN_VERSION(val)    bfin_write16(CAN_VERSION, val)
-#define bfin_read_CAN_MBTD()           bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val)       bfin_write16(CAN_MBTD, val)
-#define bfin_read_CAN_EWR()            bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val)        bfin_write16(CAN_EWR, val)
-#define bfin_read_CAN_ESR()            bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val)        bfin_write16(CAN_ESR, val)
-#define bfin_read_CAN_UCREG()          bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val)      bfin_write16(CAN_UCREG, val)
-#define bfin_read_CAN_UCCNT()          bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val)      bfin_write16(CAN_UCCNT, val)
-#define bfin_read_CAN_UCRC()           bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val)       bfin_write16(CAN_UCRC, val)
-#define bfin_read_CAN_UCCNF()          bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val)      bfin_write16(CAN_UCCNF, val)
-#define bfin_read_CAN_VERSION2()       bfin_read16(CAN_VERSION2)
-#define bfin_write_CAN_VERSION2(val)   bfin_write16(CAN_VERSION2, val)
-#define bfin_read_CAN_AM00L()          bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val)      bfin_write16(CAN_AM00L, val)
-#define bfin_read_CAN_AM00H()          bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val)      bfin_write16(CAN_AM00H, val)
-#define bfin_read_CAN_AM01L()          bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val)      bfin_write16(CAN_AM01L, val)
-#define bfin_read_CAN_AM01H()          bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val)      bfin_write16(CAN_AM01H, val)
-#define bfin_read_CAN_AM02L()          bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val)      bfin_write16(CAN_AM02L, val)
-#define bfin_read_CAN_AM02H()          bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val)      bfin_write16(CAN_AM02H, val)
-#define bfin_read_CAN_AM03L()          bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val)      bfin_write16(CAN_AM03L, val)
-#define bfin_read_CAN_AM03H()          bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val)      bfin_write16(CAN_AM03H, val)
-#define bfin_read_CAN_AM04L()          bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val)      bfin_write16(CAN_AM04L, val)
-#define bfin_read_CAN_AM04H()          bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val)      bfin_write16(CAN_AM04H, val)
-#define bfin_read_CAN_AM05L()          bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val)      bfin_write16(CAN_AM05L, val)
-#define bfin_read_CAN_AM05H()          bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val)      bfin_write16(CAN_AM05H, val)
-#define bfin_read_CAN_AM06L()          bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val)      bfin_write16(CAN_AM06L, val)
-#define bfin_read_CAN_AM06H()          bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val)      bfin_write16(CAN_AM06H, val)
-#define bfin_read_CAN_AM07L()          bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val)      bfin_write16(CAN_AM07L, val)
-#define bfin_read_CAN_AM07H()          bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val)      bfin_write16(CAN_AM07H, val)
-#define bfin_read_CAN_AM08L()          bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val)      bfin_write16(CAN_AM08L, val)
-#define bfin_read_CAN_AM08H()          bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val)      bfin_write16(CAN_AM08H, val)
-#define bfin_read_CAN_AM09L()          bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val)      bfin_write16(CAN_AM09L, val)
-#define bfin_read_CAN_AM09H()          bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val)      bfin_write16(CAN_AM09H, val)
-#define bfin_read_CAN_AM10L()          bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val)      bfin_write16(CAN_AM10L, val)
-#define bfin_read_CAN_AM10H()          bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val)      bfin_write16(CAN_AM10H, val)
-#define bfin_read_CAN_AM11L()          bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val)      bfin_write16(CAN_AM11L, val)
-#define bfin_read_CAN_AM11H()          bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val)      bfin_write16(CAN_AM11H, val)
-#define bfin_read_CAN_AM12L()          bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val)      bfin_write16(CAN_AM12L, val)
-#define bfin_read_CAN_AM12H()          bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val)      bfin_write16(CAN_AM12H, val)
-#define bfin_read_CAN_AM13L()          bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val)      bfin_write16(CAN_AM13L, val)
-#define bfin_read_CAN_AM13H()          bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val)      bfin_write16(CAN_AM13H, val)
-#define bfin_read_CAN_AM14L()          bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val)      bfin_write16(CAN_AM14L, val)
-#define bfin_read_CAN_AM14H()          bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val)      bfin_write16(CAN_AM14H, val)
-#define bfin_read_CAN_AM15L()          bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val)      bfin_write16(CAN_AM15L, val)
-#define bfin_read_CAN_AM15H()          bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val)      bfin_write16(CAN_AM15H, val)
-#define bfin_read_CAN_AM16L()          bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val)      bfin_write16(CAN_AM16L, val)
-#define bfin_read_CAN_AM16H()          bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val)      bfin_write16(CAN_AM16H, val)
-#define bfin_read_CAN_AM17L()          bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val)      bfin_write16(CAN_AM17L, val)
-#define bfin_read_CAN_AM17H()          bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val)      bfin_write16(CAN_AM17H, val)
-#define bfin_read_CAN_AM18L()          bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val)      bfin_write16(CAN_AM18L, val)
-#define bfin_read_CAN_AM18H()          bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val)      bfin_write16(CAN_AM18H, val)
-#define bfin_read_CAN_AM19L()          bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val)      bfin_write16(CAN_AM19L, val)
-#define bfin_read_CAN_AM19H()          bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val)      bfin_write16(CAN_AM19H, val)
-#define bfin_read_CAN_AM20L()          bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val)      bfin_write16(CAN_AM20L, val)
-#define bfin_read_CAN_AM20H()          bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val)      bfin_write16(CAN_AM20H, val)
-#define bfin_read_CAN_AM21L()          bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val)      bfin_write16(CAN_AM21L, val)
-#define bfin_read_CAN_AM21H()          bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val)      bfin_write16(CAN_AM21H, val)
-#define bfin_read_CAN_AM22L()          bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val)      bfin_write16(CAN_AM22L, val)
-#define bfin_read_CAN_AM22H()          bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val)      bfin_write16(CAN_AM22H, val)
-#define bfin_read_CAN_AM23L()          bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val)      bfin_write16(CAN_AM23L, val)
-#define bfin_read_CAN_AM23H()          bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val)      bfin_write16(CAN_AM23H, val)
-#define bfin_read_CAN_AM24L()          bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val)      bfin_write16(CAN_AM24L, val)
-#define bfin_read_CAN_AM24H()          bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val)      bfin_write16(CAN_AM24H, val)
-#define bfin_read_CAN_AM25L()          bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val)      bfin_write16(CAN_AM25L, val)
-#define bfin_read_CAN_AM25H()          bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val)      bfin_write16(CAN_AM25H, val)
-#define bfin_read_CAN_AM26L()          bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val)      bfin_write16(CAN_AM26L, val)
-#define bfin_read_CAN_AM26H()          bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val)      bfin_write16(CAN_AM26H, val)
-#define bfin_read_CAN_AM27L()          bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val)      bfin_write16(CAN_AM27L, val)
-#define bfin_read_CAN_AM27H()          bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val)      bfin_write16(CAN_AM27H, val)
-#define bfin_read_CAN_AM28L()          bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val)      bfin_write16(CAN_AM28L, val)
-#define bfin_read_CAN_AM28H()          bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val)      bfin_write16(CAN_AM28H, val)
-#define bfin_read_CAN_AM29L()          bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val)      bfin_write16(CAN_AM29L, val)
-#define bfin_read_CAN_AM29H()          bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val)      bfin_write16(CAN_AM29H, val)
-#define bfin_read_CAN_AM30L()          bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val)      bfin_write16(CAN_AM30L, val)
-#define bfin_read_CAN_AM30H()          bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val)      bfin_write16(CAN_AM30H, val)
-#define bfin_read_CAN_AM31L()          bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val)      bfin_write16(CAN_AM31L, val)
-#define bfin_read_CAN_AM31H()          bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val)      bfin_write16(CAN_AM31H, val)
-#define bfin_read_CAN_MB00_DATA0()     bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
-#define bfin_read_CAN_MB00_DATA1()     bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
-#define bfin_read_CAN_MB00_DATA2()     bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
-#define bfin_read_CAN_MB00_DATA3()     bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
-#define bfin_read_CAN_MB00_LENGTH()    bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
-#define bfin_read_CAN_MB00_ID0()       bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val)   bfin_write16(CAN_MB00_ID0, val)
-#define bfin_read_CAN_MB00_ID1()       bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val)   bfin_write16(CAN_MB00_ID1, val)
-#define bfin_read_CAN_MB01_DATA0()     bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
-#define bfin_read_CAN_MB01_DATA1()     bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
-#define bfin_read_CAN_MB01_DATA2()     bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
-#define bfin_read_CAN_MB01_DATA3()     bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
-#define bfin_read_CAN_MB01_LENGTH()    bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
-#define bfin_read_CAN_MB01_ID0()       bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val)   bfin_write16(CAN_MB01_ID0, val)
-#define bfin_read_CAN_MB01_ID1()       bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val)   bfin_write16(CAN_MB01_ID1, val)
-#define bfin_read_CAN_MB02_DATA0()     bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
-#define bfin_read_CAN_MB02_DATA1()     bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
-#define bfin_read_CAN_MB02_DATA2()     bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
-#define bfin_read_CAN_MB02_DATA3()     bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
-#define bfin_read_CAN_MB02_LENGTH()    bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
-#define bfin_read_CAN_MB02_ID0()       bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val)   bfin_write16(CAN_MB02_ID0, val)
-#define bfin_read_CAN_MB02_ID1()       bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val)   bfin_write16(CAN_MB02_ID1, val)
-#define bfin_read_CAN_MB03_DATA0()     bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
-#define bfin_read_CAN_MB03_DATA1()     bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
-#define bfin_read_CAN_MB03_DATA2()     bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
-#define bfin_read_CAN_MB03_DATA3()     bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
-#define bfin_read_CAN_MB03_LENGTH()    bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
-#define bfin_read_CAN_MB03_ID0()       bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val)   bfin_write16(CAN_MB03_ID0, val)
-#define bfin_read_CAN_MB03_ID1()       bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val)   bfin_write16(CAN_MB03_ID1, val)
-#define bfin_read_CAN_MB04_DATA0()     bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
-#define bfin_read_CAN_MB04_DATA1()     bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
-#define bfin_read_CAN_MB04_DATA2()     bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
-#define bfin_read_CAN_MB04_DATA3()     bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
-#define bfin_read_CAN_MB04_LENGTH()    bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
-#define bfin_read_CAN_MB04_ID0()       bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val)   bfin_write16(CAN_MB04_ID0, val)
-#define bfin_read_CAN_MB04_ID1()       bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val)   bfin_write16(CAN_MB04_ID1, val)
-#define bfin_read_CAN_MB05_DATA0()     bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
-#define bfin_read_CAN_MB05_DATA1()     bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
-#define bfin_read_CAN_MB05_DATA2()     bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
-#define bfin_read_CAN_MB05_DATA3()     bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
-#define bfin_read_CAN_MB05_LENGTH()    bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
-#define bfin_read_CAN_MB05_ID0()       bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val)   bfin_write16(CAN_MB05_ID0, val)
-#define bfin_read_CAN_MB05_ID1()       bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val)   bfin_write16(CAN_MB05_ID1, val)
-#define bfin_read_CAN_MB06_DATA0()     bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
-#define bfin_read_CAN_MB06_DATA1()     bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
-#define bfin_read_CAN_MB06_DATA2()     bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
-#define bfin_read_CAN_MB06_DATA3()     bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
-#define bfin_read_CAN_MB06_LENGTH()    bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
-#define bfin_read_CAN_MB06_ID0()       bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val)   bfin_write16(CAN_MB06_ID0, val)
-#define bfin_read_CAN_MB06_ID1()       bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val)   bfin_write16(CAN_MB06_ID1, val)
-#define bfin_read_CAN_MB07_DATA0()     bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
-#define bfin_read_CAN_MB07_DATA1()     bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
-#define bfin_read_CAN_MB07_DATA2()     bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
-#define bfin_read_CAN_MB07_DATA3()     bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
-#define bfin_read_CAN_MB07_LENGTH()    bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
-#define bfin_read_CAN_MB07_ID0()       bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val)   bfin_write16(CAN_MB07_ID0, val)
-#define bfin_read_CAN_MB07_ID1()       bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val)   bfin_write16(CAN_MB07_ID1, val)
-#define bfin_read_CAN_MB08_DATA0()     bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
-#define bfin_read_CAN_MB08_DATA1()     bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
-#define bfin_read_CAN_MB08_DATA2()     bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
-#define bfin_read_CAN_MB08_DATA3()     bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
-#define bfin_read_CAN_MB08_LENGTH()    bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
-#define bfin_read_CAN_MB08_ID0()       bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val)   bfin_write16(CAN_MB08_ID0, val)
-#define bfin_read_CAN_MB08_ID1()       bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val)   bfin_write16(CAN_MB08_ID1, val)
-#define bfin_read_CAN_MB09_DATA0()     bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
-#define bfin_read_CAN_MB09_DATA1()     bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
-#define bfin_read_CAN_MB09_DATA2()     bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
-#define bfin_read_CAN_MB09_DATA3()     bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
-#define bfin_read_CAN_MB09_LENGTH()    bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
-#define bfin_read_CAN_MB09_ID0()       bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val)   bfin_write16(CAN_MB09_ID0, val)
-#define bfin_read_CAN_MB09_ID1()       bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val)   bfin_write16(CAN_MB09_ID1, val)
-#define bfin_read_CAN_MB10_DATA0()     bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
-#define bfin_read_CAN_MB10_DATA1()     bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
-#define bfin_read_CAN_MB10_DATA2()     bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
-#define bfin_read_CAN_MB10_DATA3()     bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
-#define bfin_read_CAN_MB10_LENGTH()    bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
-#define bfin_read_CAN_MB10_ID0()       bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val)   bfin_write16(CAN_MB10_ID0, val)
-#define bfin_read_CAN_MB10_ID1()       bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val)   bfin_write16(CAN_MB10_ID1, val)
-#define bfin_read_CAN_MB11_DATA0()     bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
-#define bfin_read_CAN_MB11_DATA1()     bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
-#define bfin_read_CAN_MB11_DATA2()     bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
-#define bfin_read_CAN_MB11_DATA3()     bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
-#define bfin_read_CAN_MB11_LENGTH()    bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
-#define bfin_read_CAN_MB11_ID0()       bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val)   bfin_write16(CAN_MB11_ID0, val)
-#define bfin_read_CAN_MB11_ID1()       bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val)   bfin_write16(CAN_MB11_ID1, val)
-#define bfin_read_CAN_MB12_DATA0()     bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
-#define bfin_read_CAN_MB12_DATA1()     bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
-#define bfin_read_CAN_MB12_DATA2()     bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
-#define bfin_read_CAN_MB12_DATA3()     bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
-#define bfin_read_CAN_MB12_LENGTH()    bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
-#define bfin_read_CAN_MB12_ID0()       bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val)   bfin_write16(CAN_MB12_ID0, val)
-#define bfin_read_CAN_MB12_ID1()       bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val)   bfin_write16(CAN_MB12_ID1, val)
-#define bfin_read_CAN_MB13_DATA0()     bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
-#define bfin_read_CAN_MB13_DATA1()     bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
-#define bfin_read_CAN_MB13_DATA2()     bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
-#define bfin_read_CAN_MB13_DATA3()     bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
-#define bfin_read_CAN_MB13_LENGTH()    bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
-#define bfin_read_CAN_MB13_ID0()       bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val)   bfin_write16(CAN_MB13_ID0, val)
-#define bfin_read_CAN_MB13_ID1()       bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val)   bfin_write16(CAN_MB13_ID1, val)
-#define bfin_read_CAN_MB14_DATA0()     bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
-#define bfin_read_CAN_MB14_DATA1()     bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
-#define bfin_read_CAN_MB14_DATA2()     bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
-#define bfin_read_CAN_MB14_DATA3()     bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
-#define bfin_read_CAN_MB14_LENGTH()    bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
-#define bfin_read_CAN_MB14_ID0()       bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val)   bfin_write16(CAN_MB14_ID0, val)
-#define bfin_read_CAN_MB14_ID1()       bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val)   bfin_write16(CAN_MB14_ID1, val)
-#define bfin_read_CAN_MB15_DATA0()     bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
-#define bfin_read_CAN_MB15_DATA1()     bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
-#define bfin_read_CAN_MB15_DATA2()     bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
-#define bfin_read_CAN_MB15_DATA3()     bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
-#define bfin_read_CAN_MB15_LENGTH()    bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
-#define bfin_read_CAN_MB15_ID0()       bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val)   bfin_write16(CAN_MB15_ID0, val)
-#define bfin_read_CAN_MB15_ID1()       bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val)   bfin_write16(CAN_MB15_ID1, val)
-#define bfin_read_CAN_MB16_DATA0()     bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
-#define bfin_read_CAN_MB16_DATA1()     bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
-#define bfin_read_CAN_MB16_DATA2()     bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
-#define bfin_read_CAN_MB16_DATA3()     bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
-#define bfin_read_CAN_MB16_LENGTH()    bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
-#define bfin_read_CAN_MB16_ID0()       bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val)   bfin_write16(CAN_MB16_ID0, val)
-#define bfin_read_CAN_MB16_ID1()       bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val)   bfin_write16(CAN_MB16_ID1, val)
-#define bfin_read_CAN_MB17_DATA0()     bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
-#define bfin_read_CAN_MB17_DATA1()     bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
-#define bfin_read_CAN_MB17_DATA2()     bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
-#define bfin_read_CAN_MB17_DATA3()     bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
-#define bfin_read_CAN_MB17_LENGTH()    bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
-#define bfin_read_CAN_MB17_ID0()       bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val)   bfin_write16(CAN_MB17_ID0, val)
-#define bfin_read_CAN_MB17_ID1()       bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val)   bfin_write16(CAN_MB17_ID1, val)
-#define bfin_read_CAN_MB18_DATA0()     bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
-#define bfin_read_CAN_MB18_DATA1()     bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
-#define bfin_read_CAN_MB18_DATA2()     bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
-#define bfin_read_CAN_MB18_DATA3()     bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
-#define bfin_read_CAN_MB18_LENGTH()    bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
-#define bfin_read_CAN_MB18_ID0()       bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val)   bfin_write16(CAN_MB18_ID0, val)
-#define bfin_read_CAN_MB18_ID1()       bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val)   bfin_write16(CAN_MB18_ID1, val)
-#define bfin_read_CAN_MB19_DATA0()     bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
-#define bfin_read_CAN_MB19_DATA1()     bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
-#define bfin_read_CAN_MB19_DATA2()     bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
-#define bfin_read_CAN_MB19_DATA3()     bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
-#define bfin_read_CAN_MB19_LENGTH()    bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
-#define bfin_read_CAN_MB19_ID0()       bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val)   bfin_write16(CAN_MB19_ID0, val)
-#define bfin_read_CAN_MB19_ID1()       bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val)   bfin_write16(CAN_MB19_ID1, val)
-#define bfin_read_CAN_MB20_DATA0()     bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
-#define bfin_read_CAN_MB20_DATA1()     bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
-#define bfin_read_CAN_MB20_DATA2()     bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
-#define bfin_read_CAN_MB20_DATA3()     bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
-#define bfin_read_CAN_MB20_LENGTH()    bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
-#define bfin_read_CAN_MB20_ID0()       bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val)   bfin_write16(CAN_MB20_ID0, val)
-#define bfin_read_CAN_MB20_ID1()       bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val)   bfin_write16(CAN_MB20_ID1, val)
-#define bfin_read_CAN_MB21_DATA0()     bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
-#define bfin_read_CAN_MB21_DATA1()     bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
-#define bfin_read_CAN_MB21_DATA2()     bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
-#define bfin_read_CAN_MB21_DATA3()     bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
-#define bfin_read_CAN_MB21_LENGTH()    bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
-#define bfin_read_CAN_MB21_ID0()       bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val)   bfin_write16(CAN_MB21_ID0, val)
-#define bfin_read_CAN_MB21_ID1()       bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val)   bfin_write16(CAN_MB21_ID1, val)
-#define bfin_read_CAN_MB22_DATA0()     bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
-#define bfin_read_CAN_MB22_DATA1()     bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
-#define bfin_read_CAN_MB22_DATA2()     bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
-#define bfin_read_CAN_MB22_DATA3()     bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
-#define bfin_read_CAN_MB22_LENGTH()    bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
-#define bfin_read_CAN_MB22_ID0()       bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val)   bfin_write16(CAN_MB22_ID0, val)
-#define bfin_read_CAN_MB22_ID1()       bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val)   bfin_write16(CAN_MB22_ID1, val)
-#define bfin_read_CAN_MB23_DATA0()     bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
-#define bfin_read_CAN_MB23_DATA1()     bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
-#define bfin_read_CAN_MB23_DATA2()     bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
-#define bfin_read_CAN_MB23_DATA3()     bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
-#define bfin_read_CAN_MB23_LENGTH()    bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
-#define bfin_read_CAN_MB23_ID0()       bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val)   bfin_write16(CAN_MB23_ID0, val)
-#define bfin_read_CAN_MB23_ID1()       bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val)   bfin_write16(CAN_MB23_ID1, val)
-#define bfin_read_CAN_MB24_DATA0()     bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
-#define bfin_read_CAN_MB24_DATA1()     bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
-#define bfin_read_CAN_MB24_DATA2()     bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
-#define bfin_read_CAN_MB24_DATA3()     bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
-#define bfin_read_CAN_MB24_LENGTH()    bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
-#define bfin_read_CAN_MB24_ID0()       bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val)   bfin_write16(CAN_MB24_ID0, val)
-#define bfin_read_CAN_MB24_ID1()       bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val)   bfin_write16(CAN_MB24_ID1, val)
-#define bfin_read_CAN_MB25_DATA0()     bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
-#define bfin_read_CAN_MB25_DATA1()     bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
-#define bfin_read_CAN_MB25_DATA2()     bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
-#define bfin_read_CAN_MB25_DATA3()     bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
-#define bfin_read_CAN_MB25_LENGTH()    bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
-#define bfin_read_CAN_MB25_ID0()       bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val)   bfin_write16(CAN_MB25_ID0, val)
-#define bfin_read_CAN_MB25_ID1()       bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val)   bfin_write16(CAN_MB25_ID1, val)
-#define bfin_read_CAN_MB26_DATA0()     bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
-#define bfin_read_CAN_MB26_DATA1()     bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
-#define bfin_read_CAN_MB26_DATA2()     bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
-#define bfin_read_CAN_MB26_DATA3()     bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
-#define bfin_read_CAN_MB26_LENGTH()    bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
-#define bfin_read_CAN_MB26_ID0()       bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val)   bfin_write16(CAN_MB26_ID0, val)
-#define bfin_read_CAN_MB26_ID1()       bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val)   bfin_write16(CAN_MB26_ID1, val)
-#define bfin_read_CAN_MB27_DATA0()     bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
-#define bfin_read_CAN_MB27_DATA1()     bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
-#define bfin_read_CAN_MB27_DATA2()     bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
-#define bfin_read_CAN_MB27_DATA3()     bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
-#define bfin_read_CAN_MB27_LENGTH()    bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
-#define bfin_read_CAN_MB27_ID0()       bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val)   bfin_write16(CAN_MB27_ID0, val)
-#define bfin_read_CAN_MB27_ID1()       bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val)   bfin_write16(CAN_MB27_ID1, val)
-#define bfin_read_CAN_MB28_DATA0()     bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
-#define bfin_read_CAN_MB28_DATA1()     bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
-#define bfin_read_CAN_MB28_DATA2()     bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
-#define bfin_read_CAN_MB28_DATA3()     bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
-#define bfin_read_CAN_MB28_LENGTH()    bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
-#define bfin_read_CAN_MB28_ID0()       bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val)   bfin_write16(CAN_MB28_ID0, val)
-#define bfin_read_CAN_MB28_ID1()       bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val)   bfin_write16(CAN_MB28_ID1, val)
-#define bfin_read_CAN_MB29_DATA0()     bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
-#define bfin_read_CAN_MB29_DATA1()     bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
-#define bfin_read_CAN_MB29_DATA2()     bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
-#define bfin_read_CAN_MB29_DATA3()     bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
-#define bfin_read_CAN_MB29_LENGTH()    bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
-#define bfin_read_CAN_MB29_ID0()       bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val)   bfin_write16(CAN_MB29_ID0, val)
-#define bfin_read_CAN_MB29_ID1()       bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val)   bfin_write16(CAN_MB29_ID1, val)
-#define bfin_read_CAN_MB30_DATA0()     bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
-#define bfin_read_CAN_MB30_DATA1()     bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
-#define bfin_read_CAN_MB30_DATA2()     bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
-#define bfin_read_CAN_MB30_DATA3()     bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
-#define bfin_read_CAN_MB30_LENGTH()    bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
-#define bfin_read_CAN_MB30_ID0()       bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val)   bfin_write16(CAN_MB30_ID0, val)
-#define bfin_read_CAN_MB30_ID1()       bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val)   bfin_write16(CAN_MB30_ID1, val)
-#define bfin_read_CAN_MB31_DATA0()     bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
-#define bfin_read_CAN_MB31_DATA1()     bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
-#define bfin_read_CAN_MB31_DATA2()     bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
-#define bfin_read_CAN_MB31_DATA3()     bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
-#define bfin_read_CAN_MB31_LENGTH()    bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
-#define bfin_read_CAN_MB31_ID0()       bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val)   bfin_write16(CAN_MB31_ID0, val)
-#define bfin_read_CAN_MB31_ID1()       bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val)   bfin_write16(CAN_MB31_ID1, val)
-#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX()           bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val)       bfin_write16(PORT_MUX, val)
-#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF534_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/BF534_def.h b/arch/blackfin/include/asm/mach-bf537/BF534_def.h
deleted file mode 100644
index cb6a543..0000000
--- a/arch/blackfin/include/asm/mach-bf537/BF534_def.h
+++ /dev/null
@@ -1,831 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF534_proc__
-#define __BFIN_DEF_ADSP_BF534_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT                      0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK                      0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR                        0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR                        0xFFC00124 /* Interrupt Wakeup Register */
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
-#define UART0_THR                      0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR                      0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL                      0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER                      0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH                      0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR                      0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR                      0xFFC0040C /* Line Control Register */
-#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
-#define UART0_LSR                      0xFFC00414 /* Line Status Register */
-#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
-#define UART0_SCR                      0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL                     0xFFC00424 /* Global Control Register */
-#define SPI_CTL                        0xFFC00500 /* SPI Control Register */
-#define SPI_FLG                        0xFFC00504 /* SPI Flag register */
-#define SPI_STAT                       0xFFC00508 /* SPI Status register */
-#define SPI_TDBR                       0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR                       0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD                       0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW                     0xFFC00518 /* SPI_RDBR Shadow Register */
-#define TIMER0_CONFIG                  0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                  0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH                   0xFFC0060C /* Timer 0 Width Register */
-#define TIMER1_CONFIG                  0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER                 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD                  0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH                   0xFFC0061C /* Timer 1 Width Register */
-#define TIMER2_CONFIG                  0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER                 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD                  0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH                   0xFFC0062C /* Timer 2 Width Register */
-#define TIMER3_CONFIG                  0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER                 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD                  0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH                   0xFFC0063C /* Timer 3 Width Register */
-#define TIMER4_CONFIG                  0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER                 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD                  0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH                   0xFFC0064C /* Timer 4 Width Register */
-#define TIMER5_CONFIG                  0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER                 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD                  0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH                   0xFFC0065C /* Timer 5 Width Register */
-#define TIMER6_CONFIG                  0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER                 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD                  0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH                   0xFFC0066C /* Timer 6 Width Register\n */
-#define TIMER7_CONFIG                  0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER                 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD                  0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH                   0xFFC0067C /* Timer 7 Width Register */
-#define TIMER_ENABLE                   0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE                  0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS                   0xFFC00688 /* Timer Status Register */
-#define PORTFIO                        0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR                  0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET                    0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE                 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA                  0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR            0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET              0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE           0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB                  0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR            0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET              0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE           0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR                    0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR                  0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE                   0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH                   0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN                   0xFFC00740 /* Port F I/O Input Enable Register  */
-#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                      0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX                      0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                      0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX                      0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL                    0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL                    0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC                     0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT                    0xFFC00A1C /* SDRAM Status Register */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR             0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG                 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT                0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY               0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT                0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR             0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG                 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT                0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY               0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT                0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR             0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG                 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT                0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR             0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG                 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT                0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY               0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT                0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define PPI_CONTROL                    0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS                     0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT                      0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY                      0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME                      0xFFC01010 /* PPI Frame Length Register */
-#define TWI_CLKDIV                     0xFFC01400 /* Serial Clock Divider Register */
-#define TWI_CONTROL                    0xFFC01404 /* TWI Control Register */
-#define TWI_SLAVE_CTL                  0xFFC01408 /* Slave Mode Control Register */
-#define TWI_SLAVE_STAT                 0xFFC0140C /* Slave Mode Status Register */
-#define TWI_SLAVE_ADDR                 0xFFC01410 /* Slave Mode Address Register */
-#define TWI_MASTER_CTL                 0xFFC01414 /* Master Mode Control Register */
-#define TWI_MASTER_STAT                0xFFC01418 /* Master Mode Status Register */
-#define TWI_MASTER_ADDR                0xFFC0141C /* Master Mode Address Register */
-#define TWI_INT_STAT                   0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI_INT_MASK                   0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI_FIFO_CTL                   0xFFC01428 /* FIFO Control Register */
-#define TWI_FIFO_STAT                  0xFFC0142C /* FIFO Status Register */
-#define TWI_XMT_DATA8                  0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI_XMT_DATA16                 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI_RCV_DATA8                  0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI_RCV_DATA16                 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-#define PORTGIO                        0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR                  0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET                    0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE                 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA                  0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR            0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET              0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE           0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB                  0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR            0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET              0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE           0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR                    0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR                  0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE                   0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH                   0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN                   0xFFC01540 /* Port G I/O Input Enable Register */
-#define PORTHIO                        0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR                  0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET                    0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE                 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA                  0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR            0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET              0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE           0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB                  0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR            0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET              0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE           0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR                    0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR                  0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE                   0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH                   0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN                   0xFFC01740 /* Port H I/O Input Enable Register */
-#define UART1_THR                      0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR                      0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL                      0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER                      0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH                      0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR                      0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR                      0xFFC0200C /* Line Control Register */
-#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
-#define UART1_LSR                      0xFFC02014 /* Line Status Register */
-#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
-#define UART1_SCR                      0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL                     0xFFC02024 /* Global Control Register */
-#define CAN_MC1                        0xFFC02A00 /* Mailbox config reg 1 */
-#define CAN_MD1                        0xFFC02A04 /* Mailbox direction reg 1 */
-#define CAN_TRS1                       0xFFC02A08 /* Transmit Request Set reg 1 */
-#define CAN_TRR1                       0xFFC02A0C /* Transmit Request Reset reg 1 */
-#define CAN_TA1                        0xFFC02A10 /* Transmit Acknowledge reg 1 */
-#define CAN_AA1                        0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
-#define CAN_RMP1                       0xFFC02A18 /* Receive Message Pending reg 1 */
-#define CAN_RML1                       0xFFC02A1C /* Receive Message Lost reg 1 */
-#define CAN_MBTIF1                     0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
-#define CAN_MBRIF1                     0xFFC02A24 /* Mailbox Receive  Interrupt Flag reg 1 */
-#define CAN_MBIM1                      0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
-#define CAN_RFH1                       0xFFC02A2C /* Remote Frame Handling reg 1 */
-#define CAN_OPSS1                      0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
-#define CAN_MC2                        0xFFC02A40 /* Mailbox config reg 2 */
-#define CAN_MD2                        0xFFC02A44 /* Mailbox direction reg 2 */
-#define CAN_TRS2                       0xFFC02A48 /* Transmit Request Set reg 2 */
-#define CAN_TRR2                       0xFFC02A4C /* Transmit Request Reset reg 2 */
-#define CAN_TA2                        0xFFC02A50 /* Transmit Acknowledge reg 2 */
-#define CAN_AA2                        0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
-#define CAN_RMP2                       0xFFC02A58 /* Receive Message Pending reg 2 */
-#define CAN_RML2                       0xFFC02A5C /* Receive Message Lost reg 2 */
-#define CAN_MBTIF2                     0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
-#define CAN_MBRIF2                     0xFFC02A64 /* Mailbox Receive  Interrupt Flag reg 2 */
-#define CAN_MBIM2                      0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
-#define CAN_RFH2                       0xFFC02A6C /* Remote Frame Handling reg 2 */
-#define CAN_OPSS2                      0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
-#define CAN_CLOCK                      0xFFC02A80 /* Bit Timing Configuration register 0 */
-#define CAN_TIMING                     0xFFC02A84 /* Bit Timing Configuration register 1 */
-#define CAN_DEBUG                      0xFFC02A88 /* Config register */
-#define CAN_STATUS                     0xFFC02A8C /* Global Status Register */
-#define CAN_CEC                        0xFFC02A90 /* Error Counter Register */
-#define CAN_GIS                        0xFFC02A94 /* Global Interrupt Status Register */
-#define CAN_GIM                        0xFFC02A98 /* Global Interrupt Mask Register */
-#define CAN_GIF                        0xFFC02A9C /* Global Interrupt Flag Register */
-#define CAN_CONTROL                    0xFFC02AA0 /* Master Control Register */
-#define CAN_INTR                       0xFFC02AA4 /* Interrupt Pending Register */
-#define CAN_VERSION                    0xFFC02AA8 /* Version Code Register */
-#define CAN_MBTD                       0xFFC02AAC /* Mailbox Temporary Disable Feature */
-#define CAN_EWR                        0xFFC02AB0 /* Programmable Warning Level */
-#define CAN_ESR                        0xFFC02AB4 /* Error Status Register */
-#define CAN_UCREG                      0xFFC02AC0 /* Universal Counter Register/Capture Register */
-#define CAN_UCCNT                      0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC                       0xFFC02AC8 /* Universal Counter Force Reload Register */
-#define CAN_UCCNF                      0xFFC02ACC /* Universal Counter Configuration Register */
-#define CAN_VERSION2                   0xFFC02AD4 /* Version Code Register 2 */
-#define CAN_AM00L                      0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
-#define CAN_AM00H                      0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
-#define CAN_AM01L                      0xFFC02B08 /* Mailbox 1 Low Acceptance Mask  */
-#define CAN_AM01H                      0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
-#define CAN_AM02L                      0xFFC02B10 /* Mailbox 2 Low Acceptance Mask  */
-#define CAN_AM02H                      0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
-#define CAN_AM03L                      0xFFC02B18 /* Mailbox 3 Low Acceptance Mask  */
-#define CAN_AM03H                      0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
-#define CAN_AM04L                      0xFFC02B20 /* Mailbox 4 Low Acceptance Mask  */
-#define CAN_AM04H                      0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
-#define CAN_AM05L                      0xFFC02B28 /* Mailbox 5 Low Acceptance Mask  */
-#define CAN_AM05H                      0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
-#define CAN_AM06L                      0xFFC02B30 /* Mailbox 6 Low Acceptance Mask  */
-#define CAN_AM06H                      0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
-#define CAN_AM07L                      0xFFC02B38 /* Mailbox 7 Low Acceptance Mask  */
-#define CAN_AM07H                      0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
-#define CAN_AM08L                      0xFFC02B40 /* Mailbox 8 Low Acceptance Mask  */
-#define CAN_AM08H                      0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
-#define CAN_AM09L                      0xFFC02B48 /* Mailbox 9 Low Acceptance Mask  */
-#define CAN_AM09H                      0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
-#define CAN_AM10L                      0xFFC02B50 /* Mailbox 10 Low Acceptance Mask  */
-#define CAN_AM10H                      0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
-#define CAN_AM11L                      0xFFC02B58 /* Mailbox 11 Low Acceptance Mask  */
-#define CAN_AM11H                      0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
-#define CAN_AM12L                      0xFFC02B60 /* Mailbox 12 Low Acceptance Mask  */
-#define CAN_AM12H                      0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
-#define CAN_AM13L                      0xFFC02B68 /* Mailbox 13 Low Acceptance Mask  */
-#define CAN_AM13H                      0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
-#define CAN_AM14L                      0xFFC02B70 /* Mailbox 14 Low Acceptance Mask  */
-#define CAN_AM14H                      0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
-#define CAN_AM15L                      0xFFC02B78 /* Mailbox 15 Low Acceptance Mask  */
-#define CAN_AM15H                      0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
-#define CAN_AM16L                      0xFFC02B80 /* Mailbox 16 Low Acceptance Mask  */
-#define CAN_AM16H                      0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
-#define CAN_AM17L                      0xFFC02B88 /* Mailbox 17 Low Acceptance Mask  */
-#define CAN_AM17H                      0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
-#define CAN_AM18L                      0xFFC02B90 /* Mailbox 18 Low Acceptance Mask  */
-#define CAN_AM18H                      0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
-#define CAN_AM19L                      0xFFC02B98 /* Mailbox 19 Low Acceptance Mask  */
-#define CAN_AM19H                      0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
-#define CAN_AM20L                      0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask  */
-#define CAN_AM20H                      0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
-#define CAN_AM21L                      0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask  */
-#define CAN_AM21H                      0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
-#define CAN_AM22L                      0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask  */
-#define CAN_AM22H                      0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
-#define CAN_AM23L                      0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask  */
-#define CAN_AM23H                      0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
-#define CAN_AM24L                      0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask  */
-#define CAN_AM24H                      0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
-#define CAN_AM25L                      0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask  */
-#define CAN_AM25H                      0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
-#define CAN_AM26L                      0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask  */
-#define CAN_AM26H                      0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
-#define CAN_AM27L                      0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask  */
-#define CAN_AM27H                      0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
-#define CAN_AM28L                      0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask  */
-#define CAN_AM28H                      0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
-#define CAN_AM29L                      0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask  */
-#define CAN_AM29H                      0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
-#define CAN_AM30L                      0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask  */
-#define CAN_AM30H                      0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
-#define CAN_AM31L                      0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask  */
-#define CAN_AM31H                      0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
-#define CAN_MB00_DATA0                 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
-#define CAN_MB00_DATA1                 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
-#define CAN_MB00_DATA2                 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
-#define CAN_MB00_DATA3                 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
-#define CAN_MB00_LENGTH                0xFFC02C10 /* Mailbox 0 Data Length Code Register */
-#define CAN_MB00_TIMESTAMP             0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
-#define CAN_MB00_ID0                   0xFFC02C18 /* Mailbox 0 Identifier Low Register */
-#define CAN_MB00_ID1                   0xFFC02C1C /* Mailbox 0 Identifier High Register */
-#define CAN_MB01_DATA0                 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register  */
-#define CAN_MB01_DATA1                 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
-#define CAN_MB01_DATA2                 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
-#define CAN_MB01_DATA3                 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
-#define CAN_MB01_LENGTH                0xFFC02C30 /* Mailbox 1 Data Length Code Register */
-#define CAN_MB01_TIMESTAMP             0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
-#define CAN_MB01_ID0                   0xFFC02C38 /* Mailbox 1 Identifier Low Register */
-#define CAN_MB01_ID1                   0xFFC02C3C /* Mailbox 1 Identifier High Register */
-#define CAN_MB02_DATA0                 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register  */
-#define CAN_MB02_DATA1                 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
-#define CAN_MB02_DATA2                 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
-#define CAN_MB02_DATA3                 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
-#define CAN_MB02_LENGTH                0xFFC02C50 /* Mailbox 2 Data Length Code Register    */
-#define CAN_MB02_TIMESTAMP             0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
-#define CAN_MB02_ID0                   0xFFC02C58 /* Mailbox 2 Identifier Low Register */
-#define CAN_MB02_ID1                   0xFFC02C5C /* Mailbox 2 Identifier High Register */
-#define CAN_MB03_DATA0                 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register  */
-#define CAN_MB03_DATA1                 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
-#define CAN_MB03_DATA2                 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
-#define CAN_MB03_DATA3                 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
-#define CAN_MB03_LENGTH                0xFFC02C70 /* Mailbox 3 Data Length Code Register */
-#define CAN_MB03_TIMESTAMP             0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
-#define CAN_MB03_ID0                   0xFFC02C78 /* Mailbox 3 Identifier Low Register */
-#define CAN_MB03_ID1                   0xFFC02C7C /* Mailbox 3 Identifier High Register */
-#define CAN_MB04_DATA0                 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
-#define CAN_MB04_DATA1                 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
-#define CAN_MB04_DATA2                 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
-#define CAN_MB04_DATA3                 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
-#define CAN_MB04_LENGTH                0xFFC02C90 /* Mailbox 4 Data Length Code Register */
-#define CAN_MB04_TIMESTAMP             0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
-#define CAN_MB04_ID0                   0xFFC02C98 /* Mailbox 4 Identifier Low Register */
-#define CAN_MB04_ID1                   0xFFC02C9C /* Mailbox 4 Identifier High Register */
-#define CAN_MB05_DATA0                 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register  */
-#define CAN_MB05_DATA1                 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
-#define CAN_MB05_DATA2                 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
-#define CAN_MB05_DATA3                 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
-#define CAN_MB05_LENGTH                0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
-#define CAN_MB05_TIMESTAMP             0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
-#define CAN_MB05_ID0                   0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
-#define CAN_MB05_ID1                   0xFFC02CBC /* Mailbox 5 Identifier High Register */
-#define CAN_MB06_DATA0                 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register  */
-#define CAN_MB06_DATA1                 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
-#define CAN_MB06_DATA2                 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
-#define CAN_MB06_DATA3                 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
-#define CAN_MB06_LENGTH                0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
-#define CAN_MB06_TIMESTAMP             0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
-#define CAN_MB06_ID0                   0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
-#define CAN_MB06_ID1                   0xFFC02CDC /* Mailbox 6 Identifier High Register */
-#define CAN_MB07_DATA0                 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
-#define CAN_MB07_DATA1                 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
-#define CAN_MB07_DATA2                 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
-#define CAN_MB07_DATA3                 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
-#define CAN_MB07_LENGTH                0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
-#define CAN_MB07_TIMESTAMP             0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
-#define CAN_MB07_ID0                   0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
-#define CAN_MB07_ID1                   0xFFC02CFC /* Mailbox 7 Identifier High Register */
-#define CAN_MB08_DATA0                 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
-#define CAN_MB08_DATA1                 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
-#define CAN_MB08_DATA2                 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
-#define CAN_MB08_DATA3                 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
-#define CAN_MB08_LENGTH                0xFFC02D10 /* Mailbox 8 Data Length Code Register */
-#define CAN_MB08_TIMESTAMP             0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
-#define CAN_MB08_ID0                   0xFFC02D18 /* Mailbox 8 Identifier Low Register */
-#define CAN_MB08_ID1                   0xFFC02D1C /* Mailbox 8 Identifier High Register */
-#define CAN_MB09_DATA0                 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
-#define CAN_MB09_DATA1                 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
-#define CAN_MB09_DATA2                 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
-#define CAN_MB09_DATA3                 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
-#define CAN_MB09_LENGTH                0xFFC02D30 /* Mailbox 9 Data Length Code Register */
-#define CAN_MB09_TIMESTAMP             0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
-#define CAN_MB09_ID0                   0xFFC02D38 /* Mailbox 9 Identifier Low Register */
-#define CAN_MB09_ID1                   0xFFC02D3C /* Mailbox 9 Identifier High Register */
-#define CAN_MB10_DATA0                 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
-#define CAN_MB10_DATA1                 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
-#define CAN_MB10_DATA2                 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
-#define CAN_MB10_DATA3                 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
-#define CAN_MB10_LENGTH                0xFFC02D50 /* Mailbox 10 Data Length Code Register */
-#define CAN_MB10_TIMESTAMP             0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
-#define CAN_MB10_ID0                   0xFFC02D58 /* Mailbox 10 Identifier Low Register */
-#define CAN_MB10_ID1                   0xFFC02D5C /* Mailbox 10 Identifier High Register */
-#define CAN_MB11_DATA0                 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
-#define CAN_MB11_DATA1                 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
-#define CAN_MB11_DATA2                 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
-#define CAN_MB11_DATA3                 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
-#define CAN_MB11_LENGTH                0xFFC02D70 /* Mailbox 11 Data Length Code Register */
-#define CAN_MB11_TIMESTAMP             0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
-#define CAN_MB11_ID0                   0xFFC02D78 /* Mailbox 11 Identifier Low Register */
-#define CAN_MB11_ID1                   0xFFC02D7C /* Mailbox 11 Identifier High Register */
-#define CAN_MB12_DATA0                 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
-#define CAN_MB12_DATA1                 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
-#define CAN_MB12_DATA2                 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
-#define CAN_MB12_DATA3                 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
-#define CAN_MB12_LENGTH                0xFFC02D90 /* Mailbox 12 Data Length Code Register */
-#define CAN_MB12_TIMESTAMP             0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
-#define CAN_MB12_ID0                   0xFFC02D98 /* Mailbox 12 Identifier Low Register */
-#define CAN_MB12_ID1                   0xFFC02D9C /* Mailbox 12 Identifier High Register */
-#define CAN_MB13_DATA0                 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
-#define CAN_MB13_DATA1                 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
-#define CAN_MB13_DATA2                 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
-#define CAN_MB13_DATA3                 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
-#define CAN_MB13_LENGTH                0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
-#define CAN_MB13_TIMESTAMP             0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
-#define CAN_MB13_ID0                   0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
-#define CAN_MB13_ID1                   0xFFC02DBC /* Mailbox 13 Identifier High Register */
-#define CAN_MB14_DATA0                 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
-#define CAN_MB14_DATA1                 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
-#define CAN_MB14_DATA2                 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
-#define CAN_MB14_DATA3                 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
-#define CAN_MB14_LENGTH                0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
-#define CAN_MB14_TIMESTAMP             0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
-#define CAN_MB14_ID0                   0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
-#define CAN_MB14_ID1                   0xFFC02DDC /* Mailbox 14 Identifier High Register */
-#define CAN_MB15_DATA0                 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
-#define CAN_MB15_DATA1                 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
-#define CAN_MB15_DATA2                 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
-#define CAN_MB15_DATA3                 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
-#define CAN_MB15_LENGTH                0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
-#define CAN_MB15_TIMESTAMP             0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
-#define CAN_MB15_ID0                   0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
-#define CAN_MB15_ID1                   0xFFC02DFC /* Mailbox 15 Identifier High Register */
-#define CAN_MB16_DATA0                 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
-#define CAN_MB16_DATA1                 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
-#define CAN_MB16_DATA2                 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
-#define CAN_MB16_DATA3                 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
-#define CAN_MB16_LENGTH                0xFFC02E10 /* Mailbox 16 Data Length Code Register */
-#define CAN_MB16_TIMESTAMP             0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
-#define CAN_MB16_ID0                   0xFFC02E18 /* Mailbox 16 Identifier Low Register */
-#define CAN_MB16_ID1                   0xFFC02E1C /* Mailbox 16 Identifier High Register */
-#define CAN_MB17_DATA0                 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
-#define CAN_MB17_DATA1                 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
-#define CAN_MB17_DATA2                 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
-#define CAN_MB17_DATA3                 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
-#define CAN_MB17_LENGTH                0xFFC02E30 /* Mailbox 17 Data Length Code Register */
-#define CAN_MB17_TIMESTAMP             0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
-#define CAN_MB17_ID0                   0xFFC02E38 /* Mailbox 17 Identifier Low Register */
-#define CAN_MB17_ID1                   0xFFC02E3C /* Mailbox 17 Identifier High Register */
-#define CAN_MB18_DATA0                 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
-#define CAN_MB18_DATA1                 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
-#define CAN_MB18_DATA2                 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
-#define CAN_MB18_DATA3                 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
-#define CAN_MB18_LENGTH                0xFFC02E50 /* Mailbox 18 Data Length Code Register */
-#define CAN_MB18_TIMESTAMP             0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
-#define CAN_MB18_ID0                   0xFFC02E58 /* Mailbox 18 Identifier Low Register */
-#define CAN_MB18_ID1                   0xFFC02E5C /* Mailbox 18 Identifier High Register */
-#define CAN_MB19_DATA0                 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
-#define CAN_MB19_DATA1                 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
-#define CAN_MB19_DATA2                 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
-#define CAN_MB19_DATA3                 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
-#define CAN_MB19_LENGTH                0xFFC02E70 /* Mailbox 19 Data Length Code Register */
-#define CAN_MB19_TIMESTAMP             0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
-#define CAN_MB19_ID0                   0xFFC02E78 /* Mailbox 19 Identifier Low Register */
-#define CAN_MB19_ID1                   0xFFC02E7C /* Mailbox 19 Identifier High Register */
-#define CAN_MB20_DATA0                 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
-#define CAN_MB20_DATA1                 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
-#define CAN_MB20_DATA2                 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
-#define CAN_MB20_DATA3                 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
-#define CAN_MB20_LENGTH                0xFFC02E90 /* Mailbox 20 Data Length Code Register */
-#define CAN_MB20_TIMESTAMP             0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
-#define CAN_MB20_ID0                   0xFFC02E98 /* Mailbox 20 Identifier Low Register */
-#define CAN_MB20_ID1                   0xFFC02E9C /* Mailbox 20 Identifier High Register */
-#define CAN_MB21_DATA0                 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
-#define CAN_MB21_DATA1                 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
-#define CAN_MB21_DATA2                 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
-#define CAN_MB21_DATA3                 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
-#define CAN_MB21_LENGTH                0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
-#define CAN_MB21_TIMESTAMP             0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
-#define CAN_MB21_ID0                   0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
-#define CAN_MB21_ID1                   0xFFC02EBC /* Mailbox 21 Identifier High Register */
-#define CAN_MB22_DATA0                 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
-#define CAN_MB22_DATA1                 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
-#define CAN_MB22_DATA2                 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
-#define CAN_MB22_DATA3                 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
-#define CAN_MB22_LENGTH                0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
-#define CAN_MB22_TIMESTAMP             0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
-#define CAN_MB22_ID0                   0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
-#define CAN_MB22_ID1                   0xFFC02EDC /* Mailbox 22 Identifier High Register */
-#define CAN_MB23_DATA0                 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
-#define CAN_MB23_DATA1                 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
-#define CAN_MB23_DATA2                 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
-#define CAN_MB23_DATA3                 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
-#define CAN_MB23_LENGTH                0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
-#define CAN_MB23_TIMESTAMP             0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
-#define CAN_MB23_ID0                   0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
-#define CAN_MB23_ID1                   0xFFC02EFC /* Mailbox 23 Identifier High Register */
-#define CAN_MB24_DATA0                 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
-#define CAN_MB24_DATA1                 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
-#define CAN_MB24_DATA2                 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
-#define CAN_MB24_DATA3                 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
-#define CAN_MB24_LENGTH                0xFFC02F10 /* Mailbox 24 Data Length Code Register */
-#define CAN_MB24_TIMESTAMP             0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
-#define CAN_MB24_ID0                   0xFFC02F18 /* Mailbox 24 Identifier Low Register */
-#define CAN_MB24_ID1                   0xFFC02F1C /* Mailbox 24 Identifier High Register */
-#define CAN_MB25_DATA0                 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
-#define CAN_MB25_DATA1                 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
-#define CAN_MB25_DATA2                 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
-#define CAN_MB25_DATA3                 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
-#define CAN_MB25_LENGTH                0xFFC02F30 /* Mailbox 25 Data Length Code Register */
-#define CAN_MB25_TIMESTAMP             0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
-#define CAN_MB25_ID0                   0xFFC02F38 /* Mailbox 25 Identifier Low Register */
-#define CAN_MB25_ID1                   0xFFC02F3C /* Mailbox 25 Identifier High Register */
-#define CAN_MB26_DATA0                 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
-#define CAN_MB26_DATA1                 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
-#define CAN_MB26_DATA2                 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
-#define CAN_MB26_DATA3                 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
-#define CAN_MB26_LENGTH                0xFFC02F50 /* Mailbox 26 Data Length Code Register */
-#define CAN_MB26_TIMESTAMP             0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
-#define CAN_MB26_ID0                   0xFFC02F58 /* Mailbox 26 Identifier Low Register */
-#define CAN_MB26_ID1                   0xFFC02F5C /* Mailbox 26 Identifier High Register */
-#define CAN_MB27_DATA0                 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
-#define CAN_MB27_DATA1                 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
-#define CAN_MB27_DATA2                 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
-#define CAN_MB27_DATA3                 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
-#define CAN_MB27_LENGTH                0xFFC02F70 /* Mailbox 27 Data Length Code Register */
-#define CAN_MB27_TIMESTAMP             0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
-#define CAN_MB27_ID0                   0xFFC02F78 /* Mailbox 27 Identifier Low Register */
-#define CAN_MB27_ID1                   0xFFC02F7C /* Mailbox 27 Identifier High Register */
-#define CAN_MB28_DATA0                 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
-#define CAN_MB28_DATA1                 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
-#define CAN_MB28_DATA2                 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
-#define CAN_MB28_DATA3                 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
-#define CAN_MB28_LENGTH                0xFFC02F90 /* Mailbox 28 Data Length Code Register */
-#define CAN_MB28_TIMESTAMP             0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
-#define CAN_MB28_ID0                   0xFFC02F98 /* Mailbox 28 Identifier Low Register */
-#define CAN_MB28_ID1                   0xFFC02F9C /* Mailbox 28 Identifier High Register */
-#define CAN_MB29_DATA0                 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
-#define CAN_MB29_DATA1                 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
-#define CAN_MB29_DATA2                 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
-#define CAN_MB29_DATA3                 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
-#define CAN_MB29_LENGTH                0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
-#define CAN_MB29_TIMESTAMP             0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
-#define CAN_MB29_ID0                   0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
-#define CAN_MB29_ID1                   0xFFC02FBC /* Mailbox 29 Identifier High Register */
-#define CAN_MB30_DATA0                 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
-#define CAN_MB30_DATA1                 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
-#define CAN_MB30_DATA2                 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
-#define CAN_MB30_DATA3                 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
-#define CAN_MB30_LENGTH                0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
-#define CAN_MB30_TIMESTAMP             0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
-#define CAN_MB30_ID0                   0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
-#define CAN_MB30_ID1                   0xFFC02FDC /* Mailbox 30 Identifier High Register */
-#define CAN_MB31_DATA0                 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
-#define CAN_MB31_DATA1                 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
-#define CAN_MB31_DATA2                 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
-#define CAN_MB31_DATA3                 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
-#define CAN_MB31_LENGTH                0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
-#define CAN_MB31_TIMESTAMP             0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
-#define CAN_MB31_ID0                   0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
-#define CAN_MB31_ID1                   0xFFC02FFC /* Mailbox 31 Identifier High Register */
-#define PORTF_FER                      0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER                      0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER                      0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define PORT_MUX                       0xFFC0320C /* Port Multiplexer Control Register */
-#define HMDMA0_CONTROL                 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT                  0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT                  0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT                0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW              0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT                  0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT                  0xFFC03318 /* HMDMA0 Current Block Count Register */
-#define HMDMA1_CONTROL                 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT                  0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT                  0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT                0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW              0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT                  0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT                  0xFFC03358 /* HMDMA1 Current Block Count Register */
-#define CHIPID                         0xFFC00014
-#define DMA_TC_CNT                     0xFFC00B0C
-#define DMA_TC_PER                     0xFFC00B10
-
-#if !defined(__ADSPBF536__)
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
-#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#endif
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif /* __BFIN_DEF_ADSP_BF534_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h
deleted file mode 100644
index ccf57c8..0000000
--- a/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF536_proc__
-#define __BFIN_CDEF_ADSP_BF536_proc__
-
-#include "BF534_cdef.h"
-
-#define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
-#define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF536_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/BF536_def.h b/arch/blackfin/include/asm/mach-bf537/BF536_def.h
deleted file mode 100644
index 9d8d00a..0000000
--- a/arch/blackfin/include/asm/mach-bf537/BF536_def.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF536_proc__
-#define __BFIN_DEF_ADSP_BF536_proc__
-
-#include "BF534_def.h"
-
-#define EMAC_OPMODE                    0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO                    0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI                    0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO                    0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI                    0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD                    0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT                    0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC                       0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1                     0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2                     0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL                  0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0               0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1               0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2               0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3               0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD                0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF                0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0               0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1               0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-#define EMAC_SYSCTL                    0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT                    0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT                   0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY                   0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE                   0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT                   0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY                   0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE                   0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-#define EMAC_MMC_CTL                   0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS                 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE                 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS                 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE                 0xFFC03090 /* MMC TX Interrupt Enables Register */
-#define EMAC_RXC_OK                    0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS                   0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN                 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET                 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF                0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST                0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI                 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD                 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI                0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO                0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG                  0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL                0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE                0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE                 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM                0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT                0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED                 0xFFC03140 /* Type/Length Consistent RX Frame Count  */
-#define EMAC_RXC_SHORT                 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64                  0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128                 0xFFC0314C /* Good RX Frame Count - Byte Count  64 <= x < 128 */
-#define EMAC_RXC_LT256                 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512                 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024                0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024                0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_OK                    0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL                  0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL                0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET                 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER                 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL                0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL                0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND                0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR                0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST                0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI                 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD                 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR                0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL                0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM                0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT                0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64                  0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128                 0xFFC031C4 /* Good TX Frame Count - Byte Count  64 <= x < 128 */
-#define EMAC_TXC_LT256                 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512                 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024                0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024                0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT                 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-#endif /* __BFIN_DEF_ADSP_BF536_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h
deleted file mode 100644
index 958363b..0000000
--- a/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF536_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf537/BF537_def.h b/arch/blackfin/include/asm/mach-bf537/BF537_def.h
deleted file mode 100644
index 383d7a7..0000000
--- a/arch/blackfin/include/asm/mach-bf537/BF537_def.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF536_def.h"
diff --git a/arch/blackfin/include/asm/mach-bf537/anomaly.h b/arch/blackfin/include/asm/mach-bf537/anomaly.h
deleted file mode 100644
index 543cd3f..0000000
--- a/arch/blackfin/include/asm/mach-bf537/anomaly.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- *  - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 silicon - sorry */
-#if __SILICON_REVISION__ < 2
-# error will not work on BF537 silicon version 0.0 or 0.1
-#endif
-
-#if defined(__ADSPBF534__)
-# define ANOMALY_BF534 1
-#else
-# define ANOMALY_BF534 0
-#endif
-#if defined(__ADSPBF536__)
-# define ANOMALY_BF536 1
-#else
-# define ANOMALY_BF536 0
-#endif
-#if defined(__ADSPBF537__)
-# define ANOMALY_BF537 1
-#else
-# define ANOMALY_BF537 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
-/* EMAC TX DMA Error After an Early Frame Abort */
-#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
-/* EMAC MDIO Input Latched on Wrong MDC Edge */
-#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
-#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
-/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
-#define ANOMALY_05000280 (1)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
-/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
-#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
-/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
-#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
-#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
-#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
-#define ANOMALY_05000322 (1)
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
-/* UART Gets Disabled after UART Boot */
-#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000359 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
-#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
-/* Instruction Cache Is Not Functional */
-#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
-/* Buffered CLKIN Output Is Disabled by Default */
-#define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000485 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf537/def_local.h b/arch/blackfin/include/asm/mach-bf537/def_local.h
deleted file mode 100644
index e210db9..0000000
--- a/arch/blackfin/include/asm/mach-bf537/def_local.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define BF537_FAMILY 1	/* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf537/gpio.h b/arch/blackfin/include/asm/mach-bf537/gpio.h
deleted file mode 100644
index f80c299..0000000
--- a/arch/blackfin/include/asm/mach-bf537/gpio.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0	0
-#define GPIO_PF1	1
-#define GPIO_PF2	2
-#define GPIO_PF3	3
-#define GPIO_PF4	4
-#define GPIO_PF5	5
-#define GPIO_PF6	6
-#define GPIO_PF7	7
-#define GPIO_PF8	8
-#define GPIO_PF9	9
-#define GPIO_PF10	10
-#define GPIO_PF11	11
-#define GPIO_PF12	12
-#define GPIO_PF13	13
-#define GPIO_PF14	14
-#define GPIO_PF15	15
-#define GPIO_PG0	16
-#define GPIO_PG1	17
-#define GPIO_PG2	18
-#define GPIO_PG3	19
-#define GPIO_PG4	20
-#define GPIO_PG5	21
-#define GPIO_PG6	22
-#define GPIO_PG7	23
-#define GPIO_PG8	24
-#define GPIO_PG9	25
-#define GPIO_PG10	26
-#define GPIO_PG11	27
-#define GPIO_PG12	28
-#define GPIO_PG13	29
-#define GPIO_PG14	30
-#define GPIO_PG15	31
-#define GPIO_PH0	32
-#define GPIO_PH1	33
-#define GPIO_PH2	34
-#define GPIO_PH3	35
-#define GPIO_PH4	36
-#define GPIO_PH5	37
-#define GPIO_PH6	38
-#define GPIO_PH7	39
-#define GPIO_PH8	40
-#define GPIO_PH9	41
-#define GPIO_PH10	42
-#define GPIO_PH11	43
-#define GPIO_PH12	44
-#define GPIO_PH13	45
-#define GPIO_PH14	46
-#define GPIO_PH15	47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf537/portmux.h b/arch/blackfin/include/asm/mach-bf537/portmux.h
deleted file mode 100644
index 71d9eae..0000000
--- a/arch/blackfin/include/asm/mach-bf537/portmux.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES	(MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE)	/* We additionally handle PORTJ */
-
-#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_TMR5		(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_TMR4		(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_TMR3		(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_TMR2		(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_TMR1		(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_TMR0		(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_SPI0_MOSI	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_SPI0_MISO	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_SPI0_SCK	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_CLK	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_DMAR0		(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_DMAR1		(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_TMR6		(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPI0_SSEL6	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPI0_SSEL5	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPI0_SSEL4	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_FS2	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_FS1	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_TACLK0	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_TMRCLK	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-#define P_PPI0_D0	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_D1	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_D2	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D3	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPORT1_DRSEC	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT1_DTSEC	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_SPORT1_RSCLK	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_SPORT1_RFS	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_SPORT1_DRPRI	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_SPORT1_TFS	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_SPORT1_DTPRI	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_MII0_ETxD0	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_MII0_ETxD1	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_MII0_ETxD2	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_MII0_ETxD3	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_MII0_ETxEN	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MII0_TxCLK	(P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MII0_PHYINT	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MII0_COL	(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_MII0_ERxD0	(P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_MII0_ERxD1	(P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_MII0_ERxD2	(P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_MII0_ERxD3	(P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_MII0_ERxDV	(P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_MII0_ERxCLK	(P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_MII0_ERxER	(P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_MII0_CRS	(P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-#define P_RMII0_REF_CLK	(P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_RMII0_MDINT	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_RMII0_CRS_DV	(P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-
-#define PORT_PJ0	(GPIO_PH15 + 1)
-#define PORT_PJ1	(GPIO_PH15 + 2)
-#define PORT_PJ2	(GPIO_PH15 + 3)
-#define PORT_PJ3	(GPIO_PH15 + 4)
-#define PORT_PJ4	(GPIO_PH15 + 5)
-#define PORT_PJ5	(GPIO_PH15 + 6)
-#define PORT_PJ6	(GPIO_PH15 + 7)
-#define PORT_PJ7	(GPIO_PH15 + 8)
-#define PORT_PJ8	(GPIO_PH15 + 9)
-#define PORT_PJ9	(GPIO_PH15 + 10)
-#define PORT_PJ10	(GPIO_PH15 + 11)
-#define PORT_PJ11	(GPIO_PH15 + 12)
-
-#define P_MDC		(P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
-#define P_MDIO		(P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
-#define P_TWI0_SCL	(P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
-#define P_TWI0_SDA	(P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
-#define P_SPORT0_DRSEC	(P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
-#define P_SPORT0_DTSEC	(P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
-#define P_SPORT0_RSCLK	(P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
-#define P_SPORT0_RFS	(P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
-#define P_SPORT0_DRPRI	(P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
-#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
-#define P_SPORT0_TFS	(P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
-#define P_SPORT0_DTPRI	(P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
-#define P_CAN0_RX	(P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
-#define P_CAN0_TX	(P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
-#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
-#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
-#define P_SPI0_SSEL7	(P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
-
-#define P_MII0 {\
-	P_MII0_ETxD0, \
-	P_MII0_ETxD1, \
-	P_MII0_ETxD2, \
-	P_MII0_ETxD3, \
-	P_MII0_ETxEN, \
-	P_MII0_TxCLK, \
-	P_MII0_PHYINT, \
-	P_MII0_COL, \
-	P_MII0_ERxD0, \
-	P_MII0_ERxD1, \
-	P_MII0_ERxD2, \
-	P_MII0_ERxD3, \
-	P_MII0_ERxDV, \
-	P_MII0_ERxCLK, \
-	P_MII0_ERxER, \
-	P_MII0_CRS, \
-	P_MDC, \
-	P_MDIO, 0}
-
-#define P_RMII0 {\
-	P_MII0_ETxD0, \
-	P_MII0_ETxD1, \
-	P_MII0_ETxEN, \
-	P_MII0_ERxD0, \
-	P_MII0_ERxD1, \
-	P_MII0_ERxER, \
-	P_RMII0_REF_CLK, \
-	P_RMII0_MDINT, \
-	P_RMII0_CRS_DV, \
-	P_MDC, \
-	P_MDIO, 0}
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf537/ports.h b/arch/blackfin/include/asm/mach-bf537/ports.h
deleted file mode 100644
index 2f62934..0000000
--- a/arch/blackfin/include/asm/mach-bf537/ports.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORT_MUX Masks */
-#define PJSE			0x0001
-#define PJCE_MASK		0x0006
-#define PJCE_SPORT		0x0000
-#define PJCE_CAN		0x0001
-#define PJCE_SPI		0x0002
-#define PFDE			0x0008
-#define PFTE			0x0010
-#define PFS6E			0x0020
-#define PFS5E			0x0040
-#define PFS4E			0x0080
-#define PFFE			0x0100
-#define PGSE			0x0200
-#define PGRE			0x0400
-#define PGTE			0x0800
-
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-#include "../mach-common/bits/ports-h.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf538/BF538_cdef.h b/arch/blackfin/include/asm/mach-bf538/BF538_cdef.h
deleted file mode 100644
index 42acdcc..0000000
--- a/arch/blackfin/include/asm/mach-bf538/BF538_cdef.h
+++ /dev/null
@@ -1,2014 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF538_proc__
-#define __BFIN_CDEF_ADSP_BF538_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT()          bfin_readPTR(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)      bfin_writePTR(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART2_THR()          bfin_read16(UART2_THR)
-#define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
-#define bfin_read_UART2_RBR()          bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val)      bfin_write16(UART2_RBR, val)
-#define bfin_read_UART2_DLL()          bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val)      bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH()          bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val)      bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_IER()          bfin_read16(UART2_IER)
-#define bfin_write_UART2_IER(val)      bfin_write16(UART2_IER, val)
-#define bfin_read_UART2_IIR()          bfin_read16(UART2_IIR)
-#define bfin_write_UART2_IIR(val)      bfin_write16(UART2_IIR, val)
-#define bfin_read_UART2_LCR()          bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val)      bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR()          bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val)      bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR()          bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val)      bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_SCR()          bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val)      bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_GCTL()         bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val)     bfin_write16(UART2_GCTL, val)
-#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_SPI2_CTL()           bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val)       bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG()           bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val)       bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT()          bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val)      bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR()          bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val)      bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR()          bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val)      bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD()          bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val)      bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW()        bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val)    bfin_write16(SPI2_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()       bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)   bfin_write16(TIMER_STATUS, val)
-#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_PORTCIO_FER()        bfin_read16(PORTCIO_FER)
-#define bfin_write_PORTCIO_FER(val)    bfin_write16(PORTCIO_FER, val)
-#define bfin_read_PORTCIO()            bfin_read16(PORTCIO)
-#define bfin_write_PORTCIO(val)        bfin_write16(PORTCIO, val)
-#define bfin_read_PORTCIO_CLEAR()      bfin_read16(PORTCIO_CLEAR)
-#define bfin_write_PORTCIO_CLEAR(val)  bfin_write16(PORTCIO_CLEAR, val)
-#define bfin_read_PORTCIO_SET()        bfin_read16(PORTCIO_SET)
-#define bfin_write_PORTCIO_SET(val)    bfin_write16(PORTCIO_SET, val)
-#define bfin_read_PORTCIO_TOGGLE()     bfin_read16(PORTCIO_TOGGLE)
-#define bfin_write_PORTCIO_TOGGLE(val) bfin_write16(PORTCIO_TOGGLE, val)
-#define bfin_read_PORTCIO_DIR()        bfin_read16(PORTCIO_DIR)
-#define bfin_write_PORTCIO_DIR(val)    bfin_write16(PORTCIO_DIR, val)
-#define bfin_read_PORTCIO_INEN()       bfin_read16(PORTCIO_INEN)
-#define bfin_write_PORTCIO_INEN(val)   bfin_write16(PORTCIO_INEN, val)
-#define bfin_read_PORTDIO_FER()        bfin_read16(PORTDIO_FER)
-#define bfin_write_PORTDIO_FER(val)    bfin_write16(PORTDIO_FER, val)
-#define bfin_read_PORTDIO()            bfin_read16(PORTDIO)
-#define bfin_write_PORTDIO(val)        bfin_write16(PORTDIO, val)
-#define bfin_read_PORTDIO_CLEAR()      bfin_read16(PORTDIO_CLEAR)
-#define bfin_write_PORTDIO_CLEAR(val)  bfin_write16(PORTDIO_CLEAR, val)
-#define bfin_read_PORTDIO_SET()        bfin_read16(PORTDIO_SET)
-#define bfin_write_PORTDIO_SET(val)    bfin_write16(PORTDIO_SET, val)
-#define bfin_read_PORTDIO_TOGGLE()     bfin_read16(PORTDIO_TOGGLE)
-#define bfin_write_PORTDIO_TOGGLE(val) bfin_write16(PORTDIO_TOGGLE, val)
-#define bfin_read_PORTDIO_DIR()        bfin_read16(PORTDIO_DIR)
-#define bfin_write_PORTDIO_DIR(val)    bfin_write16(PORTDIO_DIR, val)
-#define bfin_read_PORTDIO_INEN()       bfin_read16(PORTDIO_INEN)
-#define bfin_write_PORTDIO_INEN(val)   bfin_write16(PORTDIO_INEN, val)
-#define bfin_read_PORTEIO_FER()        bfin_read16(PORTEIO_FER)
-#define bfin_write_PORTEIO_FER(val)    bfin_write16(PORTEIO_FER, val)
-#define bfin_read_PORTEIO()            bfin_read16(PORTEIO)
-#define bfin_write_PORTEIO(val)        bfin_write16(PORTEIO, val)
-#define bfin_read_PORTEIO_CLEAR()      bfin_read16(PORTEIO_CLEAR)
-#define bfin_write_PORTEIO_CLEAR(val)  bfin_write16(PORTEIO_CLEAR, val)
-#define bfin_read_PORTEIO_SET()        bfin_read16(PORTEIO_SET)
-#define bfin_write_PORTEIO_SET(val)    bfin_write16(PORTEIO_SET, val)
-#define bfin_read_PORTEIO_TOGGLE()     bfin_read16(PORTEIO_TOGGLE)
-#define bfin_write_PORTEIO_TOGGLE(val) bfin_write16(PORTEIO_TOGGLE, val)
-#define bfin_read_PORTEIO_DIR()        bfin_read16(PORTEIO_DIR)
-#define bfin_write_PORTEIO_DIR(val)    bfin_write16(PORTEIO_DIR, val)
-#define bfin_read_PORTEIO_INEN()       bfin_read16(PORTEIO_INEN)
-#define bfin_write_PORTEIO_INEN(val)   bfin_write16(PORTEIO_INEN, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMA0_TC_PER()        bfin_read16(DMA0_TC_PER)
-#define bfin_write_DMA0_TC_PER(val)    bfin_write16(DMA0_TC_PER, val)
-#define bfin_read_DMA0_TC_CNT()        bfin_read16(DMA0_TC_CNT)
-#define bfin_write_DMA0_TC_CNT(val)    bfin_write16(DMA0_TC_CNT, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_TC_PER()        bfin_read16(DMA1_TC_PER)
-#define bfin_write_DMA1_TC_PER(val)    bfin_write16(DMA1_TC_PER, val)
-#define bfin_read_DMA1_TC_CNT()        bfin_read16(DMA1_TC_CNT)
-#define bfin_write_DMA1_TC_CNT(val)    bfin_write16(DMA1_TC_CNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_D0_START_ADDR() bfin_readPTR(MDMA0_D0_START_ADDR)
-#define bfin_write_MDMA0_D0_START_ADDR(val) bfin_writePTR(MDMA0_D0_START_ADDR, val)
-#define bfin_read_MDMA0_D0_CONFIG()    bfin_read16(MDMA0_D0_CONFIG)
-#define bfin_write_MDMA0_D0_CONFIG(val) bfin_write16(MDMA0_D0_CONFIG, val)
-#define bfin_read_MDMA0_D0_X_COUNT()   bfin_read16(MDMA0_D0_X_COUNT)
-#define bfin_write_MDMA0_D0_X_COUNT(val) bfin_write16(MDMA0_D0_X_COUNT, val)
-#define bfin_read_MDMA0_D0_X_MODIFY()  bfin_read16(MDMA0_D0_X_MODIFY)
-#define bfin_write_MDMA0_D0_X_MODIFY(val) bfin_write16(MDMA0_D0_X_MODIFY, val)
-#define bfin_read_MDMA0_D0_Y_COUNT()   bfin_read16(MDMA0_D0_Y_COUNT)
-#define bfin_write_MDMA0_D0_Y_COUNT(val) bfin_write16(MDMA0_D0_Y_COUNT, val)
-#define bfin_read_MDMA0_D0_Y_MODIFY()  bfin_read16(MDMA0_D0_Y_MODIFY)
-#define bfin_write_MDMA0_D0_Y_MODIFY(val) bfin_write16(MDMA0_D0_Y_MODIFY, val)
-#define bfin_read_MDMA0_D0_CURR_DESC_PTR() bfin_readPTR(MDMA0_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_D0_CURR_ADDR() bfin_readPTR(MDMA0_D0_CURR_ADDR)
-#define bfin_write_MDMA0_D0_CURR_ADDR(val) bfin_writePTR(MDMA0_D0_CURR_ADDR, val)
-#define bfin_read_MDMA0_D0_IRQ_STATUS() bfin_read16(MDMA0_D0_IRQ_STATUS)
-#define bfin_write_MDMA0_D0_IRQ_STATUS(val) bfin_write16(MDMA0_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_D0_PERIPHERAL_MAP() bfin_read16(MDMA0_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_D0_CURR_X_COUNT() bfin_read16(MDMA0_D0_CURR_X_COUNT)
-#define bfin_write_MDMA0_D0_CURR_X_COUNT(val) bfin_write16(MDMA0_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_D0_CURR_Y_COUNT() bfin_read16(MDMA0_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_D0_CURR_Y_COUNT(val) bfin_write16(MDMA0_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_S0_START_ADDR() bfin_readPTR(MDMA0_S0_START_ADDR)
-#define bfin_write_MDMA0_S0_START_ADDR(val) bfin_writePTR(MDMA0_S0_START_ADDR, val)
-#define bfin_read_MDMA0_S0_CONFIG()    bfin_read16(MDMA0_S0_CONFIG)
-#define bfin_write_MDMA0_S0_CONFIG(val) bfin_write16(MDMA0_S0_CONFIG, val)
-#define bfin_read_MDMA0_S0_X_COUNT()   bfin_read16(MDMA0_S0_X_COUNT)
-#define bfin_write_MDMA0_S0_X_COUNT(val) bfin_write16(MDMA0_S0_X_COUNT, val)
-#define bfin_read_MDMA0_S0_X_MODIFY()  bfin_read16(MDMA0_S0_X_MODIFY)
-#define bfin_write_MDMA0_S0_X_MODIFY(val) bfin_write16(MDMA0_S0_X_MODIFY, val)
-#define bfin_read_MDMA0_S0_Y_COUNT()   bfin_read16(MDMA0_S0_Y_COUNT)
-#define bfin_write_MDMA0_S0_Y_COUNT(val) bfin_write16(MDMA0_S0_Y_COUNT, val)
-#define bfin_read_MDMA0_S0_Y_MODIFY()  bfin_read16(MDMA0_S0_Y_MODIFY)
-#define bfin_write_MDMA0_S0_Y_MODIFY(val) bfin_write16(MDMA0_S0_Y_MODIFY, val)
-#define bfin_read_MDMA0_S0_CURR_DESC_PTR() bfin_readPTR(MDMA0_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_S0_CURR_ADDR() bfin_readPTR(MDMA0_S0_CURR_ADDR)
-#define bfin_write_MDMA0_S0_CURR_ADDR(val) bfin_writePTR(MDMA0_S0_CURR_ADDR, val)
-#define bfin_read_MDMA0_S0_IRQ_STATUS() bfin_read16(MDMA0_S0_IRQ_STATUS)
-#define bfin_write_MDMA0_S0_IRQ_STATUS(val) bfin_write16(MDMA0_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_S0_PERIPHERAL_MAP() bfin_read16(MDMA0_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_S0_CURR_X_COUNT() bfin_read16(MDMA0_S0_CURR_X_COUNT)
-#define bfin_write_MDMA0_S0_CURR_X_COUNT(val) bfin_write16(MDMA0_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_S0_CURR_Y_COUNT() bfin_read16(MDMA0_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_S0_CURR_Y_COUNT(val) bfin_write16(MDMA0_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_D1_START_ADDR() bfin_readPTR(MDMA0_D1_START_ADDR)
-#define bfin_write_MDMA0_D1_START_ADDR(val) bfin_writePTR(MDMA0_D1_START_ADDR, val)
-#define bfin_read_MDMA0_D1_CONFIG()    bfin_read16(MDMA0_D1_CONFIG)
-#define bfin_write_MDMA0_D1_CONFIG(val) bfin_write16(MDMA0_D1_CONFIG, val)
-#define bfin_read_MDMA0_D1_X_COUNT()   bfin_read16(MDMA0_D1_X_COUNT)
-#define bfin_write_MDMA0_D1_X_COUNT(val) bfin_write16(MDMA0_D1_X_COUNT, val)
-#define bfin_read_MDMA0_D1_X_MODIFY()  bfin_read16(MDMA0_D1_X_MODIFY)
-#define bfin_write_MDMA0_D1_X_MODIFY(val) bfin_write16(MDMA0_D1_X_MODIFY, val)
-#define bfin_read_MDMA0_D1_Y_COUNT()   bfin_read16(MDMA0_D1_Y_COUNT)
-#define bfin_write_MDMA0_D1_Y_COUNT(val) bfin_write16(MDMA0_D1_Y_COUNT, val)
-#define bfin_read_MDMA0_D1_Y_MODIFY()  bfin_read16(MDMA0_D1_Y_MODIFY)
-#define bfin_write_MDMA0_D1_Y_MODIFY(val) bfin_write16(MDMA0_D1_Y_MODIFY, val)
-#define bfin_read_MDMA0_D1_CURR_DESC_PTR() bfin_readPTR(MDMA0_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA0_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_D1_CURR_ADDR() bfin_readPTR(MDMA0_D1_CURR_ADDR)
-#define bfin_write_MDMA0_D1_CURR_ADDR(val) bfin_writePTR(MDMA0_D1_CURR_ADDR, val)
-#define bfin_read_MDMA0_D1_IRQ_STATUS() bfin_read16(MDMA0_D1_IRQ_STATUS)
-#define bfin_write_MDMA0_D1_IRQ_STATUS(val) bfin_write16(MDMA0_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA0_D1_PERIPHERAL_MAP() bfin_read16(MDMA0_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_D1_CURR_X_COUNT() bfin_read16(MDMA0_D1_CURR_X_COUNT)
-#define bfin_write_MDMA0_D1_CURR_X_COUNT(val) bfin_write16(MDMA0_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_D1_CURR_Y_COUNT() bfin_read16(MDMA0_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA0_D1_CURR_Y_COUNT(val) bfin_write16(MDMA0_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_S1_START_ADDR() bfin_readPTR(MDMA0_S1_START_ADDR)
-#define bfin_write_MDMA0_S1_START_ADDR(val) bfin_writePTR(MDMA0_S1_START_ADDR, val)
-#define bfin_read_MDMA0_S1_CONFIG()    bfin_read16(MDMA0_S1_CONFIG)
-#define bfin_write_MDMA0_S1_CONFIG(val) bfin_write16(MDMA0_S1_CONFIG, val)
-#define bfin_read_MDMA0_S1_X_COUNT()   bfin_read16(MDMA0_S1_X_COUNT)
-#define bfin_write_MDMA0_S1_X_COUNT(val) bfin_write16(MDMA0_S1_X_COUNT, val)
-#define bfin_read_MDMA0_S1_X_MODIFY()  bfin_read16(MDMA0_S1_X_MODIFY)
-#define bfin_write_MDMA0_S1_X_MODIFY(val) bfin_write16(MDMA0_S1_X_MODIFY, val)
-#define bfin_read_MDMA0_S1_Y_COUNT()   bfin_read16(MDMA0_S1_Y_COUNT)
-#define bfin_write_MDMA0_S1_Y_COUNT(val) bfin_write16(MDMA0_S1_Y_COUNT, val)
-#define bfin_read_MDMA0_S1_Y_MODIFY()  bfin_read16(MDMA0_S1_Y_MODIFY)
-#define bfin_write_MDMA0_S1_Y_MODIFY(val) bfin_write16(MDMA0_S1_Y_MODIFY, val)
-#define bfin_read_MDMA0_S1_CURR_DESC_PTR() bfin_readPTR(MDMA0_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA0_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_S1_CURR_ADDR() bfin_readPTR(MDMA0_S1_CURR_ADDR)
-#define bfin_write_MDMA0_S1_CURR_ADDR(val) bfin_writePTR(MDMA0_S1_CURR_ADDR, val)
-#define bfin_read_MDMA0_S1_IRQ_STATUS() bfin_read16(MDMA0_S1_IRQ_STATUS)
-#define bfin_write_MDMA0_S1_IRQ_STATUS(val) bfin_write16(MDMA0_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA0_S1_PERIPHERAL_MAP() bfin_read16(MDMA0_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_S1_CURR_X_COUNT() bfin_read16(MDMA0_S1_CURR_X_COUNT)
-#define bfin_write_MDMA0_S1_CURR_X_COUNT(val) bfin_write16(MDMA0_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_S1_CURR_Y_COUNT() bfin_read16(MDMA0_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA0_S1_CURR_Y_COUNT(val) bfin_write16(MDMA0_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR)
-#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val)
-#define bfin_read_MDMA1_D0_CONFIG()    bfin_read16(MDMA1_D0_CONFIG)
-#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val)
-#define bfin_read_MDMA1_D0_X_COUNT()   bfin_read16(MDMA1_D0_X_COUNT)
-#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val)
-#define bfin_read_MDMA1_D0_X_MODIFY()  bfin_read16(MDMA1_D0_X_MODIFY)
-#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val)
-#define bfin_read_MDMA1_D0_Y_COUNT()   bfin_read16(MDMA1_D0_Y_COUNT)
-#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val)
-#define bfin_read_MDMA1_D0_Y_MODIFY()  bfin_read16(MDMA1_D0_Y_MODIFY)
-#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val)
-#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR)
-#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
-#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
-#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
-#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR)
-#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val)
-#define bfin_read_MDMA1_S0_CONFIG()    bfin_read16(MDMA1_S0_CONFIG)
-#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val)
-#define bfin_read_MDMA1_S0_X_COUNT()   bfin_read16(MDMA1_S0_X_COUNT)
-#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val)
-#define bfin_read_MDMA1_S0_X_MODIFY()  bfin_read16(MDMA1_S0_X_MODIFY)
-#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val)
-#define bfin_read_MDMA1_S0_Y_COUNT()   bfin_read16(MDMA1_S0_Y_COUNT)
-#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val)
-#define bfin_read_MDMA1_S0_Y_MODIFY()  bfin_read16(MDMA1_S0_Y_MODIFY)
-#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val)
-#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR)
-#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
-#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
-#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
-#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR)
-#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val)
-#define bfin_read_MDMA1_D1_CONFIG()    bfin_read16(MDMA1_D1_CONFIG)
-#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val)
-#define bfin_read_MDMA1_D1_X_COUNT()   bfin_read16(MDMA1_D1_X_COUNT)
-#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val)
-#define bfin_read_MDMA1_D1_X_MODIFY()  bfin_read16(MDMA1_D1_X_MODIFY)
-#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val)
-#define bfin_read_MDMA1_D1_Y_COUNT()   bfin_read16(MDMA1_D1_Y_COUNT)
-#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val)
-#define bfin_read_MDMA1_D1_Y_MODIFY()  bfin_read16(MDMA1_D1_Y_MODIFY)
-#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val)
-#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR)
-#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
-#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
-#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
-#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR)
-#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val)
-#define bfin_read_MDMA1_S1_CONFIG()    bfin_read16(MDMA1_S1_CONFIG)
-#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val)
-#define bfin_read_MDMA1_S1_X_COUNT()   bfin_read16(MDMA1_S1_X_COUNT)
-#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val)
-#define bfin_read_MDMA1_S1_X_MODIFY()  bfin_read16(MDMA1_S1_X_MODIFY)
-#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val)
-#define bfin_read_MDMA1_S1_Y_COUNT()   bfin_read16(MDMA1_S1_Y_COUNT)
-#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val)
-#define bfin_read_MDMA1_S1_Y_MODIFY()  bfin_read16(MDMA1_S1_Y_MODIFY)
-#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val)
-#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR)
-#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
-#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
-#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
-#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI0_SLAVE_CTRL()    bfin_read16(TWI0_SLAVE_CTRL)
-#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
-#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
-#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
-#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
-#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTRL()    bfin_read16(TWI1_SLAVE_CTRL)
-#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
-#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
-#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
-#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
-#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define bfin_read_CAN_MC1()            bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val)        bfin_write16(CAN_MC1, val)
-#define bfin_read_CAN_MD1()            bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val)        bfin_write16(CAN_MD1, val)
-#define bfin_read_CAN_TRS1()           bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val)       bfin_write16(CAN_TRS1, val)
-#define bfin_read_CAN_TRR1()           bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val)       bfin_write16(CAN_TRR1, val)
-#define bfin_read_CAN_TA1()            bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val)        bfin_write16(CAN_TA1, val)
-#define bfin_read_CAN_AA1()            bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val)        bfin_write16(CAN_AA1, val)
-#define bfin_read_CAN_RMP1()           bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val)       bfin_write16(CAN_RMP1, val)
-#define bfin_read_CAN_RML1()           bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val)       bfin_write16(CAN_RML1, val)
-#define bfin_read_CAN_MBTIF1()         bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val)     bfin_write16(CAN_MBTIF1, val)
-#define bfin_read_CAN_MBRIF1()         bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val)     bfin_write16(CAN_MBRIF1, val)
-#define bfin_read_CAN_MBIM1()          bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val)      bfin_write16(CAN_MBIM1, val)
-#define bfin_read_CAN_RFH1()           bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val)       bfin_write16(CAN_RFH1, val)
-#define bfin_read_CAN_OPSS1()          bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val)      bfin_write16(CAN_OPSS1, val)
-#define bfin_read_CAN_MC2()            bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val)        bfin_write16(CAN_MC2, val)
-#define bfin_read_CAN_MD2()            bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val)        bfin_write16(CAN_MD2, val)
-#define bfin_read_CAN_TRS2()           bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val)       bfin_write16(CAN_TRS2, val)
-#define bfin_read_CAN_TRR2()           bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val)       bfin_write16(CAN_TRR2, val)
-#define bfin_read_CAN_TA2()            bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val)        bfin_write16(CAN_TA2, val)
-#define bfin_read_CAN_AA2()            bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val)        bfin_write16(CAN_AA2, val)
-#define bfin_read_CAN_RMP2()           bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val)       bfin_write16(CAN_RMP2, val)
-#define bfin_read_CAN_RML2()           bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val)       bfin_write16(CAN_RML2, val)
-#define bfin_read_CAN_MBTIF2()         bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val)     bfin_write16(CAN_MBTIF2, val)
-#define bfin_read_CAN_MBRIF2()         bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val)     bfin_write16(CAN_MBRIF2, val)
-#define bfin_read_CAN_MBIM2()          bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val)      bfin_write16(CAN_MBIM2, val)
-#define bfin_read_CAN_RFH2()           bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val)       bfin_write16(CAN_RFH2, val)
-#define bfin_read_CAN_OPSS2()          bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val)      bfin_write16(CAN_OPSS2, val)
-#define bfin_read_CAN_CLOCK()          bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val)      bfin_write16(CAN_CLOCK, val)
-#define bfin_read_CAN_TIMING()         bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val)     bfin_write16(CAN_TIMING, val)
-#define bfin_read_CAN_DEBUG()          bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val)      bfin_write16(CAN_DEBUG, val)
-#define bfin_read_CAN_STATUS()         bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val)     bfin_write16(CAN_STATUS, val)
-#define bfin_read_CAN_CEC()            bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val)        bfin_write16(CAN_CEC, val)
-#define bfin_read_CAN_GIS()            bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val)        bfin_write16(CAN_GIS, val)
-#define bfin_read_CAN_GIM()            bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val)        bfin_write16(CAN_GIM, val)
-#define bfin_read_CAN_GIF()            bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val)        bfin_write16(CAN_GIF, val)
-#define bfin_read_CAN_CONTROL()        bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val)    bfin_write16(CAN_CONTROL, val)
-#define bfin_read_CAN_INTR()           bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val)       bfin_write16(CAN_INTR, val)
-#define bfin_read_CAN_VERSION()        bfin_read16(CAN_VERSION)
-#define bfin_write_CAN_VERSION(val)    bfin_write16(CAN_VERSION, val)
-#define bfin_read_CAN_MBTD()           bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val)       bfin_write16(CAN_MBTD, val)
-#define bfin_read_CAN_EWR()            bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val)        bfin_write16(CAN_EWR, val)
-#define bfin_read_CAN_ESR()            bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val)        bfin_write16(CAN_ESR, val)
-#define bfin_read_CAN_UCREG()          bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val)      bfin_write16(CAN_UCREG, val)
-#define bfin_read_CAN_UCCNT()          bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val)      bfin_write16(CAN_UCCNT, val)
-#define bfin_read_CAN_UCRC()           bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val)       bfin_write16(CAN_UCRC, val)
-#define bfin_read_CAN_UCCNF()          bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val)      bfin_write16(CAN_UCCNF, val)
-#define bfin_read_CAN_VERSION2()       bfin_read16(CAN_VERSION2)
-#define bfin_write_CAN_VERSION2(val)   bfin_write16(CAN_VERSION2, val)
-#define bfin_read_CAN_AM00L()          bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val)      bfin_write16(CAN_AM00L, val)
-#define bfin_read_CAN_AM00H()          bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val)      bfin_write16(CAN_AM00H, val)
-#define bfin_read_CAN_AM01L()          bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val)      bfin_write16(CAN_AM01L, val)
-#define bfin_read_CAN_AM01H()          bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val)      bfin_write16(CAN_AM01H, val)
-#define bfin_read_CAN_AM02L()          bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val)      bfin_write16(CAN_AM02L, val)
-#define bfin_read_CAN_AM02H()          bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val)      bfin_write16(CAN_AM02H, val)
-#define bfin_read_CAN_AM03L()          bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val)      bfin_write16(CAN_AM03L, val)
-#define bfin_read_CAN_AM03H()          bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val)      bfin_write16(CAN_AM03H, val)
-#define bfin_read_CAN_AM04L()          bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val)      bfin_write16(CAN_AM04L, val)
-#define bfin_read_CAN_AM04H()          bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val)      bfin_write16(CAN_AM04H, val)
-#define bfin_read_CAN_AM05L()          bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val)      bfin_write16(CAN_AM05L, val)
-#define bfin_read_CAN_AM05H()          bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val)      bfin_write16(CAN_AM05H, val)
-#define bfin_read_CAN_AM06L()          bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val)      bfin_write16(CAN_AM06L, val)
-#define bfin_read_CAN_AM06H()          bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val)      bfin_write16(CAN_AM06H, val)
-#define bfin_read_CAN_AM07L()          bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val)      bfin_write16(CAN_AM07L, val)
-#define bfin_read_CAN_AM07H()          bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val)      bfin_write16(CAN_AM07H, val)
-#define bfin_read_CAN_AM08L()          bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val)      bfin_write16(CAN_AM08L, val)
-#define bfin_read_CAN_AM08H()          bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val)      bfin_write16(CAN_AM08H, val)
-#define bfin_read_CAN_AM09L()          bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val)      bfin_write16(CAN_AM09L, val)
-#define bfin_read_CAN_AM09H()          bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val)      bfin_write16(CAN_AM09H, val)
-#define bfin_read_CAN_AM10L()          bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val)      bfin_write16(CAN_AM10L, val)
-#define bfin_read_CAN_AM10H()          bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val)      bfin_write16(CAN_AM10H, val)
-#define bfin_read_CAN_AM11L()          bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val)      bfin_write16(CAN_AM11L, val)
-#define bfin_read_CAN_AM11H()          bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val)      bfin_write16(CAN_AM11H, val)
-#define bfin_read_CAN_AM12L()          bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val)      bfin_write16(CAN_AM12L, val)
-#define bfin_read_CAN_AM12H()          bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val)      bfin_write16(CAN_AM12H, val)
-#define bfin_read_CAN_AM13L()          bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val)      bfin_write16(CAN_AM13L, val)
-#define bfin_read_CAN_AM13H()          bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val)      bfin_write16(CAN_AM13H, val)
-#define bfin_read_CAN_AM14L()          bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val)      bfin_write16(CAN_AM14L, val)
-#define bfin_read_CAN_AM14H()          bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val)      bfin_write16(CAN_AM14H, val)
-#define bfin_read_CAN_AM15L()          bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val)      bfin_write16(CAN_AM15L, val)
-#define bfin_read_CAN_AM15H()          bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val)      bfin_write16(CAN_AM15H, val)
-#define bfin_read_CAN_AM16L()          bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val)      bfin_write16(CAN_AM16L, val)
-#define bfin_read_CAN_AM16H()          bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val)      bfin_write16(CAN_AM16H, val)
-#define bfin_read_CAN_AM17L()          bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val)      bfin_write16(CAN_AM17L, val)
-#define bfin_read_CAN_AM17H()          bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val)      bfin_write16(CAN_AM17H, val)
-#define bfin_read_CAN_AM18L()          bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val)      bfin_write16(CAN_AM18L, val)
-#define bfin_read_CAN_AM18H()          bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val)      bfin_write16(CAN_AM18H, val)
-#define bfin_read_CAN_AM19L()          bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val)      bfin_write16(CAN_AM19L, val)
-#define bfin_read_CAN_AM19H()          bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val)      bfin_write16(CAN_AM19H, val)
-#define bfin_read_CAN_AM20L()          bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val)      bfin_write16(CAN_AM20L, val)
-#define bfin_read_CAN_AM20H()          bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val)      bfin_write16(CAN_AM20H, val)
-#define bfin_read_CAN_AM21L()          bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val)      bfin_write16(CAN_AM21L, val)
-#define bfin_read_CAN_AM21H()          bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val)      bfin_write16(CAN_AM21H, val)
-#define bfin_read_CAN_AM22L()          bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val)      bfin_write16(CAN_AM22L, val)
-#define bfin_read_CAN_AM22H()          bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val)      bfin_write16(CAN_AM22H, val)
-#define bfin_read_CAN_AM23L()          bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val)      bfin_write16(CAN_AM23L, val)
-#define bfin_read_CAN_AM23H()          bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val)      bfin_write16(CAN_AM23H, val)
-#define bfin_read_CAN_AM24L()          bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val)      bfin_write16(CAN_AM24L, val)
-#define bfin_read_CAN_AM24H()          bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val)      bfin_write16(CAN_AM24H, val)
-#define bfin_read_CAN_AM25L()          bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val)      bfin_write16(CAN_AM25L, val)
-#define bfin_read_CAN_AM25H()          bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val)      bfin_write16(CAN_AM25H, val)
-#define bfin_read_CAN_AM26L()          bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val)      bfin_write16(CAN_AM26L, val)
-#define bfin_read_CAN_AM26H()          bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val)      bfin_write16(CAN_AM26H, val)
-#define bfin_read_CAN_AM27L()          bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val)      bfin_write16(CAN_AM27L, val)
-#define bfin_read_CAN_AM27H()          bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val)      bfin_write16(CAN_AM27H, val)
-#define bfin_read_CAN_AM28L()          bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val)      bfin_write16(CAN_AM28L, val)
-#define bfin_read_CAN_AM28H()          bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val)      bfin_write16(CAN_AM28H, val)
-#define bfin_read_CAN_AM29L()          bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val)      bfin_write16(CAN_AM29L, val)
-#define bfin_read_CAN_AM29H()          bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val)      bfin_write16(CAN_AM29H, val)
-#define bfin_read_CAN_AM30L()          bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val)      bfin_write16(CAN_AM30L, val)
-#define bfin_read_CAN_AM30H()          bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val)      bfin_write16(CAN_AM30H, val)
-#define bfin_read_CAN_AM31L()          bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val)      bfin_write16(CAN_AM31L, val)
-#define bfin_read_CAN_AM31H()          bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val)      bfin_write16(CAN_AM31H, val)
-#define bfin_read_CAN_MB00_DATA0()     bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
-#define bfin_read_CAN_MB00_DATA1()     bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
-#define bfin_read_CAN_MB00_DATA2()     bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
-#define bfin_read_CAN_MB00_DATA3()     bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
-#define bfin_read_CAN_MB00_LENGTH()    bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
-#define bfin_read_CAN_MB00_ID0()       bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val)   bfin_write16(CAN_MB00_ID0, val)
-#define bfin_read_CAN_MB00_ID1()       bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val)   bfin_write16(CAN_MB00_ID1, val)
-#define bfin_read_CAN_MB01_DATA0()     bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
-#define bfin_read_CAN_MB01_DATA1()     bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
-#define bfin_read_CAN_MB01_DATA2()     bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
-#define bfin_read_CAN_MB01_DATA3()     bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
-#define bfin_read_CAN_MB01_LENGTH()    bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
-#define bfin_read_CAN_MB01_ID0()       bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val)   bfin_write16(CAN_MB01_ID0, val)
-#define bfin_read_CAN_MB01_ID1()       bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val)   bfin_write16(CAN_MB01_ID1, val)
-#define bfin_read_CAN_MB02_DATA0()     bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
-#define bfin_read_CAN_MB02_DATA1()     bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
-#define bfin_read_CAN_MB02_DATA2()     bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
-#define bfin_read_CAN_MB02_DATA3()     bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
-#define bfin_read_CAN_MB02_LENGTH()    bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
-#define bfin_read_CAN_MB02_ID0()       bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val)   bfin_write16(CAN_MB02_ID0, val)
-#define bfin_read_CAN_MB02_ID1()       bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val)   bfin_write16(CAN_MB02_ID1, val)
-#define bfin_read_CAN_MB03_DATA0()     bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
-#define bfin_read_CAN_MB03_DATA1()     bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
-#define bfin_read_CAN_MB03_DATA2()     bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
-#define bfin_read_CAN_MB03_DATA3()     bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
-#define bfin_read_CAN_MB03_LENGTH()    bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
-#define bfin_read_CAN_MB03_ID0()       bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val)   bfin_write16(CAN_MB03_ID0, val)
-#define bfin_read_CAN_MB03_ID1()       bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val)   bfin_write16(CAN_MB03_ID1, val)
-#define bfin_read_CAN_MB04_DATA0()     bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
-#define bfin_read_CAN_MB04_DATA1()     bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
-#define bfin_read_CAN_MB04_DATA2()     bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
-#define bfin_read_CAN_MB04_DATA3()     bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
-#define bfin_read_CAN_MB04_LENGTH()    bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
-#define bfin_read_CAN_MB04_ID0()       bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val)   bfin_write16(CAN_MB04_ID0, val)
-#define bfin_read_CAN_MB04_ID1()       bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val)   bfin_write16(CAN_MB04_ID1, val)
-#define bfin_read_CAN_MB05_DATA0()     bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
-#define bfin_read_CAN_MB05_DATA1()     bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
-#define bfin_read_CAN_MB05_DATA2()     bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
-#define bfin_read_CAN_MB05_DATA3()     bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
-#define bfin_read_CAN_MB05_LENGTH()    bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
-#define bfin_read_CAN_MB05_ID0()       bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val)   bfin_write16(CAN_MB05_ID0, val)
-#define bfin_read_CAN_MB05_ID1()       bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val)   bfin_write16(CAN_MB05_ID1, val)
-#define bfin_read_CAN_MB06_DATA0()     bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
-#define bfin_read_CAN_MB06_DATA1()     bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
-#define bfin_read_CAN_MB06_DATA2()     bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
-#define bfin_read_CAN_MB06_DATA3()     bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
-#define bfin_read_CAN_MB06_LENGTH()    bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
-#define bfin_read_CAN_MB06_ID0()       bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val)   bfin_write16(CAN_MB06_ID0, val)
-#define bfin_read_CAN_MB06_ID1()       bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val)   bfin_write16(CAN_MB06_ID1, val)
-#define bfin_read_CAN_MB07_DATA0()     bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
-#define bfin_read_CAN_MB07_DATA1()     bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
-#define bfin_read_CAN_MB07_DATA2()     bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
-#define bfin_read_CAN_MB07_DATA3()     bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
-#define bfin_read_CAN_MB07_LENGTH()    bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
-#define bfin_read_CAN_MB07_ID0()       bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val)   bfin_write16(CAN_MB07_ID0, val)
-#define bfin_read_CAN_MB07_ID1()       bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val)   bfin_write16(CAN_MB07_ID1, val)
-#define bfin_read_CAN_MB08_DATA0()     bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
-#define bfin_read_CAN_MB08_DATA1()     bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
-#define bfin_read_CAN_MB08_DATA2()     bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
-#define bfin_read_CAN_MB08_DATA3()     bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
-#define bfin_read_CAN_MB08_LENGTH()    bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
-#define bfin_read_CAN_MB08_ID0()       bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val)   bfin_write16(CAN_MB08_ID0, val)
-#define bfin_read_CAN_MB08_ID1()       bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val)   bfin_write16(CAN_MB08_ID1, val)
-#define bfin_read_CAN_MB09_DATA0()     bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
-#define bfin_read_CAN_MB09_DATA1()     bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
-#define bfin_read_CAN_MB09_DATA2()     bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
-#define bfin_read_CAN_MB09_DATA3()     bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
-#define bfin_read_CAN_MB09_LENGTH()    bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
-#define bfin_read_CAN_MB09_ID0()       bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val)   bfin_write16(CAN_MB09_ID0, val)
-#define bfin_read_CAN_MB09_ID1()       bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val)   bfin_write16(CAN_MB09_ID1, val)
-#define bfin_read_CAN_MB10_DATA0()     bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
-#define bfin_read_CAN_MB10_DATA1()     bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
-#define bfin_read_CAN_MB10_DATA2()     bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
-#define bfin_read_CAN_MB10_DATA3()     bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
-#define bfin_read_CAN_MB10_LENGTH()    bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
-#define bfin_read_CAN_MB10_ID0()       bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val)   bfin_write16(CAN_MB10_ID0, val)
-#define bfin_read_CAN_MB10_ID1()       bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val)   bfin_write16(CAN_MB10_ID1, val)
-#define bfin_read_CAN_MB11_DATA0()     bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
-#define bfin_read_CAN_MB11_DATA1()     bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
-#define bfin_read_CAN_MB11_DATA2()     bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
-#define bfin_read_CAN_MB11_DATA3()     bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
-#define bfin_read_CAN_MB11_LENGTH()    bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
-#define bfin_read_CAN_MB11_ID0()       bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val)   bfin_write16(CAN_MB11_ID0, val)
-#define bfin_read_CAN_MB11_ID1()       bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val)   bfin_write16(CAN_MB11_ID1, val)
-#define bfin_read_CAN_MB12_DATA0()     bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
-#define bfin_read_CAN_MB12_DATA1()     bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
-#define bfin_read_CAN_MB12_DATA2()     bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
-#define bfin_read_CAN_MB12_DATA3()     bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
-#define bfin_read_CAN_MB12_LENGTH()    bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
-#define bfin_read_CAN_MB12_ID0()       bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val)   bfin_write16(CAN_MB12_ID0, val)
-#define bfin_read_CAN_MB12_ID1()       bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val)   bfin_write16(CAN_MB12_ID1, val)
-#define bfin_read_CAN_MB13_DATA0()     bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
-#define bfin_read_CAN_MB13_DATA1()     bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
-#define bfin_read_CAN_MB13_DATA2()     bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
-#define bfin_read_CAN_MB13_DATA3()     bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
-#define bfin_read_CAN_MB13_LENGTH()    bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
-#define bfin_read_CAN_MB13_ID0()       bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val)   bfin_write16(CAN_MB13_ID0, val)
-#define bfin_read_CAN_MB13_ID1()       bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val)   bfin_write16(CAN_MB13_ID1, val)
-#define bfin_read_CAN_MB14_DATA0()     bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
-#define bfin_read_CAN_MB14_DATA1()     bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
-#define bfin_read_CAN_MB14_DATA2()     bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
-#define bfin_read_CAN_MB14_DATA3()     bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
-#define bfin_read_CAN_MB14_LENGTH()    bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
-#define bfin_read_CAN_MB14_ID0()       bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val)   bfin_write16(CAN_MB14_ID0, val)
-#define bfin_read_CAN_MB14_ID1()       bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val)   bfin_write16(CAN_MB14_ID1, val)
-#define bfin_read_CAN_MB15_DATA0()     bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
-#define bfin_read_CAN_MB15_DATA1()     bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
-#define bfin_read_CAN_MB15_DATA2()     bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
-#define bfin_read_CAN_MB15_DATA3()     bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
-#define bfin_read_CAN_MB15_LENGTH()    bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
-#define bfin_read_CAN_MB15_ID0()       bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val)   bfin_write16(CAN_MB15_ID0, val)
-#define bfin_read_CAN_MB15_ID1()       bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val)   bfin_write16(CAN_MB15_ID1, val)
-#define bfin_read_CAN_MB16_DATA0()     bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
-#define bfin_read_CAN_MB16_DATA1()     bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
-#define bfin_read_CAN_MB16_DATA2()     bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
-#define bfin_read_CAN_MB16_DATA3()     bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
-#define bfin_read_CAN_MB16_LENGTH()    bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
-#define bfin_read_CAN_MB16_ID0()       bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val)   bfin_write16(CAN_MB16_ID0, val)
-#define bfin_read_CAN_MB16_ID1()       bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val)   bfin_write16(CAN_MB16_ID1, val)
-#define bfin_read_CAN_MB17_DATA0()     bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
-#define bfin_read_CAN_MB17_DATA1()     bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
-#define bfin_read_CAN_MB17_DATA2()     bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
-#define bfin_read_CAN_MB17_DATA3()     bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
-#define bfin_read_CAN_MB17_LENGTH()    bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
-#define bfin_read_CAN_MB17_ID0()       bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val)   bfin_write16(CAN_MB17_ID0, val)
-#define bfin_read_CAN_MB17_ID1()       bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val)   bfin_write16(CAN_MB17_ID1, val)
-#define bfin_read_CAN_MB18_DATA0()     bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
-#define bfin_read_CAN_MB18_DATA1()     bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
-#define bfin_read_CAN_MB18_DATA2()     bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
-#define bfin_read_CAN_MB18_DATA3()     bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
-#define bfin_read_CAN_MB18_LENGTH()    bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
-#define bfin_read_CAN_MB18_ID0()       bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val)   bfin_write16(CAN_MB18_ID0, val)
-#define bfin_read_CAN_MB18_ID1()       bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val)   bfin_write16(CAN_MB18_ID1, val)
-#define bfin_read_CAN_MB19_DATA0()     bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
-#define bfin_read_CAN_MB19_DATA1()     bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
-#define bfin_read_CAN_MB19_DATA2()     bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
-#define bfin_read_CAN_MB19_DATA3()     bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
-#define bfin_read_CAN_MB19_LENGTH()    bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
-#define bfin_read_CAN_MB19_ID0()       bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val)   bfin_write16(CAN_MB19_ID0, val)
-#define bfin_read_CAN_MB19_ID1()       bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val)   bfin_write16(CAN_MB19_ID1, val)
-#define bfin_read_CAN_MB20_DATA0()     bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
-#define bfin_read_CAN_MB20_DATA1()     bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
-#define bfin_read_CAN_MB20_DATA2()     bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
-#define bfin_read_CAN_MB20_DATA3()     bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
-#define bfin_read_CAN_MB20_LENGTH()    bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
-#define bfin_read_CAN_MB20_ID0()       bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val)   bfin_write16(CAN_MB20_ID0, val)
-#define bfin_read_CAN_MB20_ID1()       bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val)   bfin_write16(CAN_MB20_ID1, val)
-#define bfin_read_CAN_MB21_DATA0()     bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
-#define bfin_read_CAN_MB21_DATA1()     bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
-#define bfin_read_CAN_MB21_DATA2()     bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
-#define bfin_read_CAN_MB21_DATA3()     bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
-#define bfin_read_CAN_MB21_LENGTH()    bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
-#define bfin_read_CAN_MB21_ID0()       bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val)   bfin_write16(CAN_MB21_ID0, val)
-#define bfin_read_CAN_MB21_ID1()       bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val)   bfin_write16(CAN_MB21_ID1, val)
-#define bfin_read_CAN_MB22_DATA0()     bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
-#define bfin_read_CAN_MB22_DATA1()     bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
-#define bfin_read_CAN_MB22_DATA2()     bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
-#define bfin_read_CAN_MB22_DATA3()     bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
-#define bfin_read_CAN_MB22_LENGTH()    bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
-#define bfin_read_CAN_MB22_ID0()       bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val)   bfin_write16(CAN_MB22_ID0, val)
-#define bfin_read_CAN_MB22_ID1()       bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val)   bfin_write16(CAN_MB22_ID1, val)
-#define bfin_read_CAN_MB23_DATA0()     bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
-#define bfin_read_CAN_MB23_DATA1()     bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
-#define bfin_read_CAN_MB23_DATA2()     bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
-#define bfin_read_CAN_MB23_DATA3()     bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
-#define bfin_read_CAN_MB23_LENGTH()    bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
-#define bfin_read_CAN_MB23_ID0()       bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val)   bfin_write16(CAN_MB23_ID0, val)
-#define bfin_read_CAN_MB23_ID1()       bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val)   bfin_write16(CAN_MB23_ID1, val)
-#define bfin_read_CAN_MB24_DATA0()     bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
-#define bfin_read_CAN_MB24_DATA1()     bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
-#define bfin_read_CAN_MB24_DATA2()     bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
-#define bfin_read_CAN_MB24_DATA3()     bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
-#define bfin_read_CAN_MB24_LENGTH()    bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
-#define bfin_read_CAN_MB24_ID0()       bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val)   bfin_write16(CAN_MB24_ID0, val)
-#define bfin_read_CAN_MB24_ID1()       bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val)   bfin_write16(CAN_MB24_ID1, val)
-#define bfin_read_CAN_MB25_DATA0()     bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
-#define bfin_read_CAN_MB25_DATA1()     bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
-#define bfin_read_CAN_MB25_DATA2()     bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
-#define bfin_read_CAN_MB25_DATA3()     bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
-#define bfin_read_CAN_MB25_LENGTH()    bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
-#define bfin_read_CAN_MB25_ID0()       bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val)   bfin_write16(CAN_MB25_ID0, val)
-#define bfin_read_CAN_MB25_ID1()       bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val)   bfin_write16(CAN_MB25_ID1, val)
-#define bfin_read_CAN_MB26_DATA0()     bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
-#define bfin_read_CAN_MB26_DATA1()     bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
-#define bfin_read_CAN_MB26_DATA2()     bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
-#define bfin_read_CAN_MB26_DATA3()     bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
-#define bfin_read_CAN_MB26_LENGTH()    bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
-#define bfin_read_CAN_MB26_ID0()       bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val)   bfin_write16(CAN_MB26_ID0, val)
-#define bfin_read_CAN_MB26_ID1()       bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val)   bfin_write16(CAN_MB26_ID1, val)
-#define bfin_read_CAN_MB27_DATA0()     bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
-#define bfin_read_CAN_MB27_DATA1()     bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
-#define bfin_read_CAN_MB27_DATA2()     bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
-#define bfin_read_CAN_MB27_DATA3()     bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
-#define bfin_read_CAN_MB27_LENGTH()    bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
-#define bfin_read_CAN_MB27_ID0()       bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val)   bfin_write16(CAN_MB27_ID0, val)
-#define bfin_read_CAN_MB27_ID1()       bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val)   bfin_write16(CAN_MB27_ID1, val)
-#define bfin_read_CAN_MB28_DATA0()     bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
-#define bfin_read_CAN_MB28_DATA1()     bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
-#define bfin_read_CAN_MB28_DATA2()     bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
-#define bfin_read_CAN_MB28_DATA3()     bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
-#define bfin_read_CAN_MB28_LENGTH()    bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
-#define bfin_read_CAN_MB28_ID0()       bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val)   bfin_write16(CAN_MB28_ID0, val)
-#define bfin_read_CAN_MB28_ID1()       bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val)   bfin_write16(CAN_MB28_ID1, val)
-#define bfin_read_CAN_MB29_DATA0()     bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
-#define bfin_read_CAN_MB29_DATA1()     bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
-#define bfin_read_CAN_MB29_DATA2()     bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
-#define bfin_read_CAN_MB29_DATA3()     bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
-#define bfin_read_CAN_MB29_LENGTH()    bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
-#define bfin_read_CAN_MB29_ID0()       bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val)   bfin_write16(CAN_MB29_ID0, val)
-#define bfin_read_CAN_MB29_ID1()       bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val)   bfin_write16(CAN_MB29_ID1, val)
-#define bfin_read_CAN_MB30_DATA0()     bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
-#define bfin_read_CAN_MB30_DATA1()     bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
-#define bfin_read_CAN_MB30_DATA2()     bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
-#define bfin_read_CAN_MB30_DATA3()     bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
-#define bfin_read_CAN_MB30_LENGTH()    bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
-#define bfin_read_CAN_MB30_ID0()       bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val)   bfin_write16(CAN_MB30_ID0, val)
-#define bfin_read_CAN_MB30_ID1()       bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val)   bfin_write16(CAN_MB30_ID1, val)
-#define bfin_read_CAN_MB31_DATA0()     bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
-#define bfin_read_CAN_MB31_DATA1()     bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
-#define bfin_read_CAN_MB31_DATA2()     bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
-#define bfin_read_CAN_MB31_DATA3()     bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
-#define bfin_read_CAN_MB31_LENGTH()    bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
-#define bfin_read_CAN_MB31_ID0()       bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val)   bfin_write16(CAN_MB31_ID0, val)
-#define bfin_read_CAN_MB31_ID1()       bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val)   bfin_write16(CAN_MB31_ID1, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF538_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf538/BF538_def.h b/arch/blackfin/include/asm/mach-bf538/BF538_def.h
deleted file mode 100644
index 1736dab..0000000
--- a/arch/blackfin/include/asm/mach-bf538/BF538_def.h
+++ /dev/null
@@ -1,1025 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF538_proc__
-#define __BFIN_DEF_ADSP_BF538_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL                        0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV                        0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT                       0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SIC_RVECT                      0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK0                     0xFFC0010C /* Interrupt Mask Register 0 */
-#define SIC_IMASK1                     0xFFC00128 /* Interrupt Mask Register 1 */
-#define SIC_ISR0                       0xFFC00120 /* Interrupt Status Register 0 */
-#define SIC_ISR1                       0xFFC0012C /* Interrupt Status Register 1 */
-#define SIC_IWR0                       0xFFC00124 /* Interrupt Wakeup Register 0 */
-#define SIC_IWR1                       0xFFC00130 /* Interrupt Wakeup Register 1 */
-#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_IAR4                       0xFFC00134 /* Interrupt Assignment Register 4 */
-#define SIC_IAR5                       0xFFC00138 /* Interrupt Assignment Register 5 */
-#define SIC_IAR6                       0xFFC0013C /* Interrupt Assignment Register 6 */
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define RTC_STAT                       0xFFC00300
-#define RTC_ICTL                       0xFFC00304
-#define RTC_ISTAT                      0xFFC00308
-#define RTC_SWCNT                      0xFFC0030C
-#define RTC_ALARM                      0xFFC00310
-#define RTC_PREN                       0xFFC00314
-#define UART0_THR                      0xFFC00400
-#define UART0_RBR                      0xFFC00400
-#define UART0_DLL                      0xFFC00400
-#define UART0_DLH                      0xFFC00404
-#define UART0_IER                      0xFFC00404
-#define UART0_IIR                      0xFFC00408
-#define UART0_LCR                      0xFFC0040C
-#define UART0_MCR                      0xFFC00410
-#define UART0_LSR                      0xFFC00414
-#define UART0_SCR                      0xFFC0041C
-#define UART0_GCTL                     0xFFC00424
-#define UART1_THR                      0xFFC02000
-#define UART1_RBR                      0xFFC02000
-#define UART1_DLL                      0xFFC02000
-#define UART1_DLH                      0xFFC02004
-#define UART1_IER                      0xFFC02004
-#define UART1_IIR                      0xFFC02008
-#define UART1_LCR                      0xFFC0200C
-#define UART1_MCR                      0xFFC02010
-#define UART1_LSR                      0xFFC02014
-#define UART1_SCR                      0xFFC0201C
-#define UART1_GCTL                     0xFFC02024
-#define UART2_THR                      0xFFC02100
-#define UART2_RBR                      0xFFC02100
-#define UART2_DLL                      0xFFC02100
-#define UART2_DLH                      0xFFC02104
-#define UART2_IER                      0xFFC02104
-#define UART2_IIR                      0xFFC02108
-#define UART2_LCR                      0xFFC0210C
-#define UART2_MCR                      0xFFC02110
-#define UART2_LSR                      0xFFC02114
-#define UART2_SCR                      0xFFC0211C
-#define UART2_GCTL                     0xFFC02124
-#define SPI0_CTL                       0xFFC00500
-#define SPI0_FLG                       0xFFC00504
-#define SPI0_STAT                      0xFFC00508
-#define SPI0_TDBR                      0xFFC0050C
-#define SPI0_RDBR                      0xFFC00510
-#define SPI0_BAUD                      0xFFC00514
-#define SPI0_SHADOW                    0xFFC00518
-#define SPI1_CTL                       0xFFC02300
-#define SPI1_FLG                       0xFFC02304
-#define SPI1_STAT                      0xFFC02308
-#define SPI1_TDBR                      0xFFC0230C
-#define SPI1_RDBR                      0xFFC02310
-#define SPI1_BAUD                      0xFFC02314
-#define SPI1_SHADOW                    0xFFC02318
-#define SPI2_CTL                       0xFFC02400
-#define SPI2_FLG                       0xFFC02404
-#define SPI2_STAT                      0xFFC02408
-#define SPI2_TDBR                      0xFFC0240C
-#define SPI2_RDBR                      0xFFC02410
-#define SPI2_BAUD                      0xFFC02414
-#define SPI2_SHADOW                    0xFFC02418
-#define TIMER0_CONFIG                  0xFFC00600
-#define TIMER0_COUNTER                 0xFFC00604
-#define TIMER0_PERIOD                  0xFFC00608
-#define TIMER0_WIDTH                   0xFFC0060C
-#define TIMER1_CONFIG                  0xFFC00610
-#define TIMER1_COUNTER                 0xFFC00614
-#define TIMER1_PERIOD                  0xFFC00618
-#define TIMER1_WIDTH                   0xFFC0061C
-#define TIMER2_CONFIG                  0xFFC00620
-#define TIMER2_COUNTER                 0xFFC00624
-#define TIMER2_PERIOD                  0xFFC00628
-#define TIMER2_WIDTH                   0xFFC0062C
-#define TIMER_ENABLE                   0xFFC00640
-#define TIMER_DISABLE                  0xFFC00644
-#define TIMER_STATUS                   0xFFC00648
-#define SPORT0_TCR1                    0xFFC00800
-#define SPORT0_TCR2                    0xFFC00804
-#define SPORT0_TCLKDIV                 0xFFC00808
-#define SPORT0_TFSDIV                  0xFFC0080C
-#define SPORT0_TX                      0xFFC00810
-#define SPORT0_RX                      0xFFC00818
-#define SPORT0_RCR1                    0xFFC00820
-#define SPORT0_RCR2                    0xFFC00824
-#define SPORT0_RCLKDIV                 0xFFC00828
-#define SPORT0_RFSDIV                  0xFFC0082C
-#define SPORT0_STAT                    0xFFC00830
-#define SPORT0_CHNL                    0xFFC00834
-#define SPORT0_MCMC1                   0xFFC00838
-#define SPORT0_MCMC2                   0xFFC0083C
-#define SPORT0_MTCS0                   0xFFC00840
-#define SPORT0_MTCS1                   0xFFC00844
-#define SPORT0_MTCS2                   0xFFC00848
-#define SPORT0_MTCS3                   0xFFC0084C
-#define SPORT0_MRCS0                   0xFFC00850
-#define SPORT0_MRCS1                   0xFFC00854
-#define SPORT0_MRCS2                   0xFFC00858
-#define SPORT0_MRCS3                   0xFFC0085C
-#define SPORT1_TCR1                    0xFFC00900
-#define SPORT1_TCR2                    0xFFC00904
-#define SPORT1_TCLKDIV                 0xFFC00908
-#define SPORT1_TFSDIV                  0xFFC0090C
-#define SPORT1_TX                      0xFFC00910
-#define SPORT1_RX                      0xFFC00918
-#define SPORT1_RCR1                    0xFFC00920
-#define SPORT1_RCR2                    0xFFC00924
-#define SPORT1_RCLKDIV                 0xFFC00928
-#define SPORT1_RFSDIV                  0xFFC0092C
-#define SPORT1_STAT                    0xFFC00930
-#define SPORT1_CHNL                    0xFFC00934
-#define SPORT1_MCMC1                   0xFFC00938
-#define SPORT1_MCMC2                   0xFFC0093C
-#define SPORT1_MTCS0                   0xFFC00940
-#define SPORT1_MTCS1                   0xFFC00944
-#define SPORT1_MTCS2                   0xFFC00948
-#define SPORT1_MTCS3                   0xFFC0094C
-#define SPORT1_MRCS0                   0xFFC00950
-#define SPORT1_MRCS1                   0xFFC00954
-#define SPORT1_MRCS2                   0xFFC00958
-#define SPORT1_MRCS3                   0xFFC0095C
-#define SPORT2_TCR1                    0xFFC02500
-#define SPORT2_TCR2                    0xFFC02504
-#define SPORT2_TCLKDIV                 0xFFC02508
-#define SPORT2_TFSDIV                  0xFFC0250C
-#define SPORT2_TX                      0xFFC02510
-#define SPORT2_RX                      0xFFC02518
-#define SPORT2_RCR1                    0xFFC02520
-#define SPORT2_RCR2                    0xFFC02524
-#define SPORT2_RCLKDIV                 0xFFC02528
-#define SPORT2_RFSDIV                  0xFFC0252C
-#define SPORT2_STAT                    0xFFC02530
-#define SPORT2_CHNL                    0xFFC02534
-#define SPORT2_MCMC1                   0xFFC02538
-#define SPORT2_MCMC2                   0xFFC0253C
-#define SPORT2_MTCS0                   0xFFC02540
-#define SPORT2_MTCS1                   0xFFC02544
-#define SPORT2_MTCS2                   0xFFC02548
-#define SPORT2_MTCS3                   0xFFC0254C
-#define SPORT2_MRCS0                   0xFFC02550
-#define SPORT2_MRCS1                   0xFFC02554
-#define SPORT2_MRCS2                   0xFFC02558
-#define SPORT2_MRCS3                   0xFFC0255C
-#define SPORT3_TCR1                    0xFFC02600
-#define SPORT3_TCR2                    0xFFC02604
-#define SPORT3_TCLKDIV                 0xFFC02608
-#define SPORT3_TFSDIV                  0xFFC0260C
-#define SPORT3_TX                      0xFFC02610
-#define SPORT3_RX                      0xFFC02618
-#define SPORT3_RCR1                    0xFFC02620
-#define SPORT3_RCR2                    0xFFC02624
-#define SPORT3_RCLKDIV                 0xFFC02628
-#define SPORT3_RFSDIV                  0xFFC0262C
-#define SPORT3_STAT                    0xFFC02630
-#define SPORT3_CHNL                    0xFFC02634
-#define SPORT3_MCMC1                   0xFFC02638
-#define SPORT3_MCMC2                   0xFFC0263C
-#define SPORT3_MTCS0                   0xFFC02640
-#define SPORT3_MTCS1                   0xFFC02644
-#define SPORT3_MTCS2                   0xFFC02648
-#define SPORT3_MTCS3                   0xFFC0264C
-#define SPORT3_MRCS0                   0xFFC02650
-#define SPORT3_MRCS1                   0xFFC02654
-#define SPORT3_MRCS2                   0xFFC02658
-#define SPORT3_MRCS3                   0xFFC0265C
-#define PORTFIO                        0xFFC00700
-#define PORTFIO_CLEAR                  0xFFC00704
-#define PORTFIO_SET                    0xFFC00708
-#define PORTFIO_TOGGLE                 0xFFC0070C
-#define PORTFIO_MASKA                  0xFFC00710
-#define PORTFIO_MASKA_CLEAR            0xFFC00714
-#define PORTFIO_MASKA_SET              0xFFC00718
-#define PORTFIO_MASKA_TOGGLE           0xFFC0071C
-#define PORTFIO_MASKB                  0xFFC00720
-#define PORTFIO_MASKB_CLEAR            0xFFC00724
-#define PORTFIO_MASKB_SET              0xFFC00728
-#define PORTFIO_MASKB_TOGGLE           0xFFC0072C
-#define PORTFIO_DIR                    0xFFC00730
-#define PORTFIO_POLAR                  0xFFC00734
-#define PORTFIO_EDGE                   0xFFC00738
-#define PORTFIO_BOTH                   0xFFC0073C
-#define PORTFIO_INEN                   0xFFC00740
-#define PORTCIO_FER                    0xFFC01500
-#define PORTCIO                        0xFFC01510
-#define PORTCIO_CLEAR                  0xFFC01520
-#define PORTCIO_SET                    0xFFC01530
-#define PORTCIO_TOGGLE                 0xFFC01540
-#define PORTCIO_DIR                    0xFFC01550
-#define PORTCIO_INEN                   0xFFC01560
-#define PORTDIO_FER                    0xFFC01504
-#define PORTDIO                        0xFFC01514
-#define PORTDIO_CLEAR                  0xFFC01524
-#define PORTDIO_SET                    0xFFC01534
-#define PORTDIO_TOGGLE                 0xFFC01544
-#define PORTDIO_DIR                    0xFFC01554
-#define PORTDIO_INEN                   0xFFC01564
-#define PORTEIO_FER                    0xFFC01508
-#define PORTEIO                        0xFFC01518
-#define PORTEIO_CLEAR                  0xFFC01528
-#define PORTEIO_SET                    0xFFC01538
-#define PORTEIO_TOGGLE                 0xFFC01548
-#define PORTEIO_DIR                    0xFFC01558
-#define PORTEIO_INEN                   0xFFC01568
-#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL                    0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL                    0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC                     0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT                    0xFFC00A1C /* SDRAM Status Register */
-#define DMA0_TC_PER                    0xFFC00B0C /* Traffic Control Periods */
-#define DMA0_TC_CNT                    0xFFC00B10 /* Traffic Control Current Counts */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00
-#define DMA0_START_ADDR                0xFFC00C04
-#define DMA0_CONFIG                    0xFFC00C08
-#define DMA0_X_COUNT                   0xFFC00C10
-#define DMA0_X_MODIFY                  0xFFC00C14
-#define DMA0_Y_COUNT                   0xFFC00C18
-#define DMA0_Y_MODIFY                  0xFFC00C1C
-#define DMA0_CURR_DESC_PTR             0xFFC00C20
-#define DMA0_CURR_ADDR                 0xFFC00C24
-#define DMA0_IRQ_STATUS                0xFFC00C28
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C
-#define DMA0_CURR_X_COUNT              0xFFC00C30
-#define DMA0_CURR_Y_COUNT              0xFFC00C38
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40
-#define DMA1_START_ADDR                0xFFC00C44
-#define DMA1_CONFIG                    0xFFC00C48
-#define DMA1_X_COUNT                   0xFFC00C50
-#define DMA1_X_MODIFY                  0xFFC00C54
-#define DMA1_Y_COUNT                   0xFFC00C58
-#define DMA1_Y_MODIFY                  0xFFC00C5C
-#define DMA1_CURR_DESC_PTR             0xFFC00C60
-#define DMA1_CURR_ADDR                 0xFFC00C64
-#define DMA1_IRQ_STATUS                0xFFC00C68
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C
-#define DMA1_CURR_X_COUNT              0xFFC00C70
-#define DMA1_CURR_Y_COUNT              0xFFC00C78
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80
-#define DMA2_START_ADDR                0xFFC00C84
-#define DMA2_CONFIG                    0xFFC00C88
-#define DMA2_X_COUNT                   0xFFC00C90
-#define DMA2_X_MODIFY                  0xFFC00C94
-#define DMA2_Y_COUNT                   0xFFC00C98
-#define DMA2_Y_MODIFY                  0xFFC00C9C
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0
-#define DMA2_CURR_ADDR                 0xFFC00CA4
-#define DMA2_IRQ_STATUS                0xFFC00CA8
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC
-#define DMA2_CURR_X_COUNT              0xFFC00CB0
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0
-#define DMA3_START_ADDR                0xFFC00CC4
-#define DMA3_CONFIG                    0xFFC00CC8
-#define DMA3_X_COUNT                   0xFFC00CD0
-#define DMA3_X_MODIFY                  0xFFC00CD4
-#define DMA3_Y_COUNT                   0xFFC00CD8
-#define DMA3_Y_MODIFY                  0xFFC00CDC
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0
-#define DMA3_CURR_ADDR                 0xFFC00CE4
-#define DMA3_IRQ_STATUS                0xFFC00CE8
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC
-#define DMA3_CURR_X_COUNT              0xFFC00CF0
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00
-#define DMA4_START_ADDR                0xFFC00D04
-#define DMA4_CONFIG                    0xFFC00D08
-#define DMA4_X_COUNT                   0xFFC00D10
-#define DMA4_X_MODIFY                  0xFFC00D14
-#define DMA4_Y_COUNT                   0xFFC00D18
-#define DMA4_Y_MODIFY                  0xFFC00D1C
-#define DMA4_CURR_DESC_PTR             0xFFC00D20
-#define DMA4_CURR_ADDR                 0xFFC00D24
-#define DMA4_IRQ_STATUS                0xFFC00D28
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C
-#define DMA4_CURR_X_COUNT              0xFFC00D30
-#define DMA4_CURR_Y_COUNT              0xFFC00D38
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40
-#define DMA5_START_ADDR                0xFFC00D44
-#define DMA5_CONFIG                    0xFFC00D48
-#define DMA5_X_COUNT                   0xFFC00D50
-#define DMA5_X_MODIFY                  0xFFC00D54
-#define DMA5_Y_COUNT                   0xFFC00D58
-#define DMA5_Y_MODIFY                  0xFFC00D5C
-#define DMA5_CURR_DESC_PTR             0xFFC00D60
-#define DMA5_CURR_ADDR                 0xFFC00D64
-#define DMA5_IRQ_STATUS                0xFFC00D68
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C
-#define DMA5_CURR_X_COUNT              0xFFC00D70
-#define DMA5_CURR_Y_COUNT              0xFFC00D78
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80
-#define DMA6_START_ADDR                0xFFC00D84
-#define DMA6_CONFIG                    0xFFC00D88
-#define DMA6_X_COUNT                   0xFFC00D90
-#define DMA6_X_MODIFY                  0xFFC00D94
-#define DMA6_Y_COUNT                   0xFFC00D98
-#define DMA6_Y_MODIFY                  0xFFC00D9C
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0
-#define DMA6_CURR_ADDR                 0xFFC00DA4
-#define DMA6_IRQ_STATUS                0xFFC00DA8
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC
-#define DMA6_CURR_X_COUNT              0xFFC00DB0
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0
-#define DMA7_START_ADDR                0xFFC00DC4
-#define DMA7_CONFIG                    0xFFC00DC8
-#define DMA7_X_COUNT                   0xFFC00DD0
-#define DMA7_X_MODIFY                  0xFFC00DD4
-#define DMA7_Y_COUNT                   0xFFC00DD8
-#define DMA7_Y_MODIFY                  0xFFC00DDC
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0
-#define DMA7_CURR_ADDR                 0xFFC00DE4
-#define DMA7_IRQ_STATUS                0xFFC00DE8
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC
-#define DMA7_CURR_X_COUNT              0xFFC00DF0
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8
-#define DMA1_TC_PER                    0xFFC01B0C /* Traffic Control Periods */
-#define DMA1_TC_CNT                    0xFFC01B10 /* Traffic Control Current Counts */
-#define DMA8_NEXT_DESC_PTR             0xFFC01C00
-#define DMA8_START_ADDR                0xFFC01C04
-#define DMA8_CONFIG                    0xFFC01C08
-#define DMA8_X_COUNT                   0xFFC01C10
-#define DMA8_X_MODIFY                  0xFFC01C14
-#define DMA8_Y_COUNT                   0xFFC01C18
-#define DMA8_Y_MODIFY                  0xFFC01C1C
-#define DMA8_CURR_DESC_PTR             0xFFC01C20
-#define DMA8_CURR_ADDR                 0xFFC01C24
-#define DMA8_IRQ_STATUS                0xFFC01C28
-#define DMA8_PERIPHERAL_MAP            0xFFC01C2C
-#define DMA8_CURR_X_COUNT              0xFFC01C30
-#define DMA8_CURR_Y_COUNT              0xFFC01C38
-#define DMA9_NEXT_DESC_PTR             0xFFC01C40
-#define DMA9_START_ADDR                0xFFC01C44
-#define DMA9_CONFIG                    0xFFC01C48
-#define DMA9_X_COUNT                   0xFFC01C50
-#define DMA9_X_MODIFY                  0xFFC01C54
-#define DMA9_Y_COUNT                   0xFFC01C58
-#define DMA9_Y_MODIFY                  0xFFC01C5C
-#define DMA9_CURR_DESC_PTR             0xFFC01C60
-#define DMA9_CURR_ADDR                 0xFFC01C64
-#define DMA9_IRQ_STATUS                0xFFC01C68
-#define DMA9_PERIPHERAL_MAP            0xFFC01C6C
-#define DMA9_CURR_X_COUNT              0xFFC01C70
-#define DMA9_CURR_Y_COUNT              0xFFC01C78
-#define DMA10_NEXT_DESC_PTR            0xFFC01C80
-#define DMA10_START_ADDR               0xFFC01C84
-#define DMA10_CONFIG                   0xFFC01C88
-#define DMA10_X_COUNT                  0xFFC01C90
-#define DMA10_X_MODIFY                 0xFFC01C94
-#define DMA10_Y_COUNT                  0xFFC01C98
-#define DMA10_Y_MODIFY                 0xFFC01C9C
-#define DMA10_CURR_DESC_PTR            0xFFC01CA0
-#define DMA10_CURR_ADDR                0xFFC01CA4
-#define DMA10_IRQ_STATUS               0xFFC01CA8
-#define DMA10_PERIPHERAL_MAP           0xFFC01CAC
-#define DMA10_CURR_X_COUNT             0xFFC01CB0
-#define DMA10_CURR_Y_COUNT             0xFFC01CB8
-#define DMA11_NEXT_DESC_PTR            0xFFC01CC0
-#define DMA11_START_ADDR               0xFFC01CC4
-#define DMA11_CONFIG                   0xFFC01CC8
-#define DMA11_X_COUNT                  0xFFC01CD0
-#define DMA11_X_MODIFY                 0xFFC01CD4
-#define DMA11_Y_COUNT                  0xFFC01CD8
-#define DMA11_Y_MODIFY                 0xFFC01CDC
-#define DMA11_CURR_DESC_PTR            0xFFC01CE0
-#define DMA11_CURR_ADDR                0xFFC01CE4
-#define DMA11_IRQ_STATUS               0xFFC01CE8
-#define DMA11_PERIPHERAL_MAP           0xFFC01CEC
-#define DMA11_CURR_X_COUNT             0xFFC01CF0
-#define DMA11_CURR_Y_COUNT             0xFFC01CF8
-#define DMA12_NEXT_DESC_PTR            0xFFC01D00
-#define DMA12_START_ADDR               0xFFC01D04
-#define DMA12_CONFIG                   0xFFC01D08
-#define DMA12_X_COUNT                  0xFFC01D10
-#define DMA12_X_MODIFY                 0xFFC01D14
-#define DMA12_Y_COUNT                  0xFFC01D18
-#define DMA12_Y_MODIFY                 0xFFC01D1C
-#define DMA12_CURR_DESC_PTR            0xFFC01D20
-#define DMA12_CURR_ADDR                0xFFC01D24
-#define DMA12_IRQ_STATUS               0xFFC01D28
-#define DMA12_PERIPHERAL_MAP           0xFFC01D2C
-#define DMA12_CURR_X_COUNT             0xFFC01D30
-#define DMA12_CURR_Y_COUNT             0xFFC01D38
-#define DMA13_NEXT_DESC_PTR            0xFFC01D40
-#define DMA13_START_ADDR               0xFFC01D44
-#define DMA13_CONFIG                   0xFFC01D48
-#define DMA13_X_COUNT                  0xFFC01D50
-#define DMA13_X_MODIFY                 0xFFC01D54
-#define DMA13_Y_COUNT                  0xFFC01D58
-#define DMA13_Y_MODIFY                 0xFFC01D5C
-#define DMA13_CURR_DESC_PTR            0xFFC01D60
-#define DMA13_CURR_ADDR                0xFFC01D64
-#define DMA13_IRQ_STATUS               0xFFC01D68
-#define DMA13_PERIPHERAL_MAP           0xFFC01D6C
-#define DMA13_CURR_X_COUNT             0xFFC01D70
-#define DMA13_CURR_Y_COUNT             0xFFC01D78
-#define DMA14_NEXT_DESC_PTR            0xFFC01D80
-#define DMA14_START_ADDR               0xFFC01D84
-#define DMA14_CONFIG                   0xFFC01D88
-#define DMA14_X_COUNT                  0xFFC01D90
-#define DMA14_X_MODIFY                 0xFFC01D94
-#define DMA14_Y_COUNT                  0xFFC01D98
-#define DMA14_Y_MODIFY                 0xFFC01D9C
-#define DMA14_CURR_DESC_PTR            0xFFC01DA0
-#define DMA14_CURR_ADDR                0xFFC01DA4
-#define DMA14_IRQ_STATUS               0xFFC01DA8
-#define DMA14_PERIPHERAL_MAP           0xFFC01DAC
-#define DMA14_CURR_X_COUNT             0xFFC01DB0
-#define DMA14_CURR_Y_COUNT             0xFFC01DB8
-#define DMA15_NEXT_DESC_PTR            0xFFC01DC0
-#define DMA15_START_ADDR               0xFFC01DC4
-#define DMA15_CONFIG                   0xFFC01DC8
-#define DMA15_X_COUNT                  0xFFC01DD0
-#define DMA15_X_MODIFY                 0xFFC01DD4
-#define DMA15_Y_COUNT                  0xFFC01DD8
-#define DMA15_Y_MODIFY                 0xFFC01DDC
-#define DMA15_CURR_DESC_PTR            0xFFC01DE0
-#define DMA15_CURR_ADDR                0xFFC01DE4
-#define DMA15_IRQ_STATUS               0xFFC01DE8
-#define DMA15_PERIPHERAL_MAP           0xFFC01DEC
-#define DMA15_CURR_X_COUNT             0xFFC01DF0
-#define DMA15_CURR_Y_COUNT             0xFFC01DF8
-#define DMA16_NEXT_DESC_PTR            0xFFC01E00
-#define DMA16_START_ADDR               0xFFC01E04
-#define DMA16_CONFIG                   0xFFC01E08
-#define DMA16_X_COUNT                  0xFFC01E10
-#define DMA16_X_MODIFY                 0xFFC01E14
-#define DMA16_Y_COUNT                  0xFFC01E18
-#define DMA16_Y_MODIFY                 0xFFC01E1C
-#define DMA16_CURR_DESC_PTR            0xFFC01E20
-#define DMA16_CURR_ADDR                0xFFC01E24
-#define DMA16_IRQ_STATUS               0xFFC01E28
-#define DMA16_PERIPHERAL_MAP           0xFFC01E2C
-#define DMA16_CURR_X_COUNT             0xFFC01E30
-#define DMA16_CURR_Y_COUNT             0xFFC01E38
-#define DMA17_NEXT_DESC_PTR            0xFFC01E40
-#define DMA17_START_ADDR               0xFFC01E44
-#define DMA17_CONFIG                   0xFFC01E48
-#define DMA17_X_COUNT                  0xFFC01E50
-#define DMA17_X_MODIFY                 0xFFC01E54
-#define DMA17_Y_COUNT                  0xFFC01E58
-#define DMA17_Y_MODIFY                 0xFFC01E5C
-#define DMA17_CURR_DESC_PTR            0xFFC01E60
-#define DMA17_CURR_ADDR                0xFFC01E64
-#define DMA17_IRQ_STATUS               0xFFC01E68
-#define DMA17_PERIPHERAL_MAP           0xFFC01E6C
-#define DMA17_CURR_X_COUNT             0xFFC01E70
-#define DMA17_CURR_Y_COUNT             0xFFC01E78
-#define DMA18_NEXT_DESC_PTR            0xFFC01E80
-#define DMA18_START_ADDR               0xFFC01E84
-#define DMA18_CONFIG                   0xFFC01E88
-#define DMA18_X_COUNT                  0xFFC01E90
-#define DMA18_X_MODIFY                 0xFFC01E94
-#define DMA18_Y_COUNT                  0xFFC01E98
-#define DMA18_Y_MODIFY                 0xFFC01E9C
-#define DMA18_CURR_DESC_PTR            0xFFC01EA0
-#define DMA18_CURR_ADDR                0xFFC01EA4
-#define DMA18_IRQ_STATUS               0xFFC01EA8
-#define DMA18_PERIPHERAL_MAP           0xFFC01EAC
-#define DMA18_CURR_X_COUNT             0xFFC01EB0
-#define DMA18_CURR_Y_COUNT             0xFFC01EB8
-#define DMA19_NEXT_DESC_PTR            0xFFC01EC0
-#define DMA19_START_ADDR               0xFFC01EC4
-#define DMA19_CONFIG                   0xFFC01EC8
-#define DMA19_X_COUNT                  0xFFC01ED0
-#define DMA19_X_MODIFY                 0xFFC01ED4
-#define DMA19_Y_COUNT                  0xFFC01ED8
-#define DMA19_Y_MODIFY                 0xFFC01EDC
-#define DMA19_CURR_DESC_PTR            0xFFC01EE0
-#define DMA19_CURR_ADDR                0xFFC01EE4
-#define DMA19_IRQ_STATUS               0xFFC01EE8
-#define DMA19_PERIPHERAL_MAP           0xFFC01EEC
-#define DMA19_CURR_X_COUNT             0xFFC01EF0
-#define DMA19_CURR_Y_COUNT             0xFFC01EF8
-#define MDMA0_D0_NEXT_DESC_PTR         0xFFC00E00
-#define MDMA0_D0_START_ADDR            0xFFC00E04
-#define MDMA0_D0_CONFIG                0xFFC00E08
-#define MDMA0_D0_X_COUNT               0xFFC00E10
-#define MDMA0_D0_X_MODIFY              0xFFC00E14
-#define MDMA0_D0_Y_COUNT               0xFFC00E18
-#define MDMA0_D0_Y_MODIFY              0xFFC00E1C
-#define MDMA0_D0_CURR_DESC_PTR         0xFFC00E20
-#define MDMA0_D0_CURR_ADDR             0xFFC00E24
-#define MDMA0_D0_IRQ_STATUS            0xFFC00E28
-#define MDMA0_D0_PERIPHERAL_MAP        0xFFC00E2C
-#define MDMA0_D0_CURR_X_COUNT          0xFFC00E30
-#define MDMA0_D0_CURR_Y_COUNT          0xFFC00E38
-#define MDMA0_S0_NEXT_DESC_PTR         0xFFC00E40
-#define MDMA0_S0_START_ADDR            0xFFC00E44
-#define MDMA0_S0_CONFIG                0xFFC00E48
-#define MDMA0_S0_X_COUNT               0xFFC00E50
-#define MDMA0_S0_X_MODIFY              0xFFC00E54
-#define MDMA0_S0_Y_COUNT               0xFFC00E58
-#define MDMA0_S0_Y_MODIFY              0xFFC00E5C
-#define MDMA0_S0_CURR_DESC_PTR         0xFFC00E60
-#define MDMA0_S0_CURR_ADDR             0xFFC00E64
-#define MDMA0_S0_IRQ_STATUS            0xFFC00E68
-#define MDMA0_S0_PERIPHERAL_MAP        0xFFC00E6C
-#define MDMA0_S0_CURR_X_COUNT          0xFFC00E70
-#define MDMA0_S0_CURR_Y_COUNT          0xFFC00E78
-#define MDMA0_D1_NEXT_DESC_PTR         0xFFC00E80
-#define MDMA0_D1_START_ADDR            0xFFC00E84
-#define MDMA0_D1_CONFIG                0xFFC00E88
-#define MDMA0_D1_X_COUNT               0xFFC00E90
-#define MDMA0_D1_X_MODIFY              0xFFC00E94
-#define MDMA0_D1_Y_COUNT               0xFFC00E98
-#define MDMA0_D1_Y_MODIFY              0xFFC00E9C
-#define MDMA0_D1_CURR_DESC_PTR         0xFFC00EA0
-#define MDMA0_D1_CURR_ADDR             0xFFC00EA4
-#define MDMA0_D1_IRQ_STATUS            0xFFC00EA8
-#define MDMA0_D1_PERIPHERAL_MAP        0xFFC00EAC
-#define MDMA0_D1_CURR_X_COUNT          0xFFC00EB0
-#define MDMA0_D1_CURR_Y_COUNT          0xFFC00EB8
-#define MDMA0_S1_NEXT_DESC_PTR         0xFFC00EC0
-#define MDMA0_S1_START_ADDR            0xFFC00EC4
-#define MDMA0_S1_CONFIG                0xFFC00EC8
-#define MDMA0_S1_X_COUNT               0xFFC00ED0
-#define MDMA0_S1_X_MODIFY              0xFFC00ED4
-#define MDMA0_S1_Y_COUNT               0xFFC00ED8
-#define MDMA0_S1_Y_MODIFY              0xFFC00EDC
-#define MDMA0_S1_CURR_DESC_PTR         0xFFC00EE0
-#define MDMA0_S1_CURR_ADDR             0xFFC00EE4
-#define MDMA0_S1_IRQ_STATUS            0xFFC00EE8
-#define MDMA0_S1_PERIPHERAL_MAP        0xFFC00EEC
-#define MDMA0_S1_CURR_X_COUNT          0xFFC00EF0
-#define MDMA0_S1_CURR_Y_COUNT          0xFFC00EF8
-#define MDMA1_D0_NEXT_DESC_PTR         0xFFC01F00
-#define MDMA1_D0_START_ADDR            0xFFC01F04
-#define MDMA1_D0_CONFIG                0xFFC01F08
-#define MDMA1_D0_X_COUNT               0xFFC01F10
-#define MDMA1_D0_X_MODIFY              0xFFC01F14
-#define MDMA1_D0_Y_COUNT               0xFFC01F18
-#define MDMA1_D0_Y_MODIFY              0xFFC01F1C
-#define MDMA1_D0_CURR_DESC_PTR         0xFFC01F20
-#define MDMA1_D0_CURR_ADDR             0xFFC01F24
-#define MDMA1_D0_IRQ_STATUS            0xFFC01F28
-#define MDMA1_D0_PERIPHERAL_MAP        0xFFC01F2C
-#define MDMA1_D0_CURR_X_COUNT          0xFFC01F30
-#define MDMA1_D0_CURR_Y_COUNT          0xFFC01F38
-#define MDMA1_S0_NEXT_DESC_PTR         0xFFC01F40
-#define MDMA1_S0_START_ADDR            0xFFC01F44
-#define MDMA1_S0_CONFIG                0xFFC01F48
-#define MDMA1_S0_X_COUNT               0xFFC01F50
-#define MDMA1_S0_X_MODIFY              0xFFC01F54
-#define MDMA1_S0_Y_COUNT               0xFFC01F58
-#define MDMA1_S0_Y_MODIFY              0xFFC01F5C
-#define MDMA1_S0_CURR_DESC_PTR         0xFFC01F60
-#define MDMA1_S0_CURR_ADDR             0xFFC01F64
-#define MDMA1_S0_IRQ_STATUS            0xFFC01F68
-#define MDMA1_S0_PERIPHERAL_MAP        0xFFC01F6C
-#define MDMA1_S0_CURR_X_COUNT          0xFFC01F70
-#define MDMA1_S0_CURR_Y_COUNT          0xFFC01F78
-#define MDMA1_D1_NEXT_DESC_PTR         0xFFC01F80
-#define MDMA1_D1_START_ADDR            0xFFC01F84
-#define MDMA1_D1_CONFIG                0xFFC01F88
-#define MDMA1_D1_X_COUNT               0xFFC01F90
-#define MDMA1_D1_X_MODIFY              0xFFC01F94
-#define MDMA1_D1_Y_COUNT               0xFFC01F98
-#define MDMA1_D1_Y_MODIFY              0xFFC01F9C
-#define MDMA1_D1_CURR_DESC_PTR         0xFFC01FA0
-#define MDMA1_D1_CURR_ADDR             0xFFC01FA4
-#define MDMA1_D1_IRQ_STATUS            0xFFC01FA8
-#define MDMA1_D1_PERIPHERAL_MAP        0xFFC01FAC
-#define MDMA1_D1_CURR_X_COUNT          0xFFC01FB0
-#define MDMA1_D1_CURR_Y_COUNT          0xFFC01FB8
-#define MDMA1_S1_NEXT_DESC_PTR         0xFFC01FC0
-#define MDMA1_S1_START_ADDR            0xFFC01FC4
-#define MDMA1_S1_CONFIG                0xFFC01FC8
-#define MDMA1_S1_X_COUNT               0xFFC01FD0
-#define MDMA1_S1_X_MODIFY              0xFFC01FD4
-#define MDMA1_S1_Y_COUNT               0xFFC01FD8
-#define MDMA1_S1_Y_MODIFY              0xFFC01FDC
-#define MDMA1_S1_CURR_DESC_PTR         0xFFC01FE0
-#define MDMA1_S1_CURR_ADDR             0xFFC01FE4
-#define MDMA1_S1_IRQ_STATUS            0xFFC01FE8
-#define MDMA1_S1_PERIPHERAL_MAP        0xFFC01FEC
-#define MDMA1_S1_CURR_X_COUNT          0xFFC01FF0
-#define MDMA1_S1_CURR_Y_COUNT          0xFFC01FF8
-#define PPI_CONTROL                    0xFFC01000
-#define PPI_STATUS                     0xFFC01004
-#define PPI_DELAY                      0xFFC0100C
-#define PPI_COUNT                      0xFFC01008
-#define PPI_FRAME                      0xFFC01010
-#define TWI0_CLKDIV                    0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL                   0xFFC01404 /* TWIO Master Internal Time Reference Register */
-#define TWI0_SLAVE_CTRL                0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT                0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR                0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL                0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT               0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR               0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT                  0xFFC01420 /* TWIO Master Interrupt Register */
-#define TWI0_INT_MASK                  0xFFC01424 /* TWIO Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL                  0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT                 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8                 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16                0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8                 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16                0xFFC0148C /* FIFO Receive Data Double Byte Register */
-#define TWI1_CLKDIV                    0xFFC02200 /* Serial Clock Divider Register */
-#define TWI1_CONTROL                   0xFFC02204 /* TWI1 Master Internal Time Reference Register */
-#define TWI1_SLAVE_CTRL                0xFFC02208 /* Slave Mode Control Register */
-#define TWI1_SLAVE_STAT                0xFFC0220C /* Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR                0xFFC02210 /* Slave Mode Address Register */
-#define TWI1_MASTER_CTL                0xFFC02214 /* Master Mode Control Register */
-#define TWI1_MASTER_STAT               0xFFC02218 /* Master Mode Status Register */
-#define TWI1_MASTER_ADDR               0xFFC0221C /* Master Mode Address Register */
-#define TWI1_INT_STAT                  0xFFC02220 /* TWI1 Master Interrupt Register */
-#define TWI1_INT_MASK                  0xFFC02224 /* TWI1 Master Interrupt Mask Register */
-#define TWI1_FIFO_CTL                  0xFFC02228 /* FIFO Control Register */
-#define TWI1_FIFO_STAT                 0xFFC0222C /* FIFO Status Register */
-#define TWI1_XMT_DATA8                 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16                0xFFC02284 /* FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8                 0xFFC02288 /* FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16                0xFFC0228C /* FIFO Receive Data Double Byte Register */
-#define CAN_MC1                        0xFFC02A00 /* Mailbox config reg 1 */
-#define CAN_MD1                        0xFFC02A04 /* Mailbox direction reg 1 */
-#define CAN_TRS1                       0xFFC02A08 /* Transmit Request Set reg 1 */
-#define CAN_TRR1                       0xFFC02A0C /* Transmit Request Reset reg 1 */
-#define CAN_TA1                        0xFFC02A10 /* Transmit Acknowledge reg 1 */
-#define CAN_AA1                        0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
-#define CAN_RMP1                       0xFFC02A18 /* Receive Message Pending reg 1 */
-#define CAN_RML1                       0xFFC02A1C /* Receive Message Lost reg 1 */
-#define CAN_MBTIF1                     0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
-#define CAN_MBRIF1                     0xFFC02A24 /* Mailbox Receive  Interrupt Flag reg 1 */
-#define CAN_MBIM1                      0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
-#define CAN_RFH1                       0xFFC02A2C /* Remote Frame Handling reg 1 */
-#define CAN_OPSS1                      0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
-#define CAN_MC2                        0xFFC02A40 /* Mailbox config reg 2 */
-#define CAN_MD2                        0xFFC02A44 /* Mailbox direction reg 2 */
-#define CAN_TRS2                       0xFFC02A48 /* Transmit Request Set reg 2 */
-#define CAN_TRR2                       0xFFC02A4C /* Transmit Request Reset reg 2 */
-#define CAN_TA2                        0xFFC02A50 /* Transmit Acknowledge reg 2 */
-#define CAN_AA2                        0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
-#define CAN_RMP2                       0xFFC02A58 /* Receive Message Pending reg 2 */
-#define CAN_RML2                       0xFFC02A5C /* Receive Message Lost reg 2 */
-#define CAN_MBTIF2                     0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
-#define CAN_MBRIF2                     0xFFC02A64 /* Mailbox Receive  Interrupt Flag reg 2 */
-#define CAN_MBIM2                      0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
-#define CAN_RFH2                       0xFFC02A6C /* Remote Frame Handling reg 2 */
-#define CAN_OPSS2                      0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
-#define CAN_CLOCK                      0xFFC02A80 /* Bit Timing Configuration register 0 */
-#define CAN_TIMING                     0xFFC02A84 /* Bit Timing Configuration register 1 */
-#define CAN_DEBUG                      0xFFC02A88 /* Config register */
-#define CAN_STATUS                     0xFFC02A8C /* Global Status Register */
-#define CAN_CEC                        0xFFC02A90 /* Error Counter Register */
-#define CAN_GIS                        0xFFC02A94 /* Global Interrupt Status Register */
-#define CAN_GIM                        0xFFC02A98 /* Global Interrupt Mask Register */
-#define CAN_GIF                        0xFFC02A9C /* Global Interrupt Flag Register */
-#define CAN_CONTROL                    0xFFC02AA0 /* Master Control Register */
-#define CAN_INTR                       0xFFC02AA4 /* Interrupt Pending Register */
-#define CAN_VERSION                    0xFFC02AA8 /* Version Code Register */
-#define CAN_MBTD                       0xFFC02AAC /* Mailbox Temporary Disable Feature */
-#define CAN_EWR                        0xFFC02AB0 /* Programmable Warning Level */
-#define CAN_ESR                        0xFFC02AB4 /* Error Status Register */
-#define CAN_UCREG                      0xFFC02AC0 /* Universal Counter Register/Capture Register */
-#define CAN_UCCNT                      0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC                       0xFFC02AC8 /* Universal Counter Force Reload Register */
-#define CAN_UCCNF                      0xFFC02ACC /* Universal Counter Configuration Register */
-#define CAN_VERSION2                   0xFFC02AD4 /* Version Code Register 2 */
-#define CAN_AM00L                      0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
-#define CAN_AM00H                      0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
-#define CAN_AM01L                      0xFFC02B08 /* Mailbox 1 Low Acceptance Mask  */
-#define CAN_AM01H                      0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
-#define CAN_AM02L                      0xFFC02B10 /* Mailbox 2 Low Acceptance Mask  */
-#define CAN_AM02H                      0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
-#define CAN_AM03L                      0xFFC02B18 /* Mailbox 3 Low Acceptance Mask  */
-#define CAN_AM03H                      0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
-#define CAN_AM04L                      0xFFC02B20 /* Mailbox 4 Low Acceptance Mask  */
-#define CAN_AM04H                      0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
-#define CAN_AM05L                      0xFFC02B28 /* Mailbox 5 Low Acceptance Mask  */
-#define CAN_AM05H                      0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
-#define CAN_AM06L                      0xFFC02B30 /* Mailbox 6 Low Acceptance Mask  */
-#define CAN_AM06H                      0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
-#define CAN_AM07L                      0xFFC02B38 /* Mailbox 7 Low Acceptance Mask  */
-#define CAN_AM07H                      0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
-#define CAN_AM08L                      0xFFC02B40 /* Mailbox 8 Low Acceptance Mask  */
-#define CAN_AM08H                      0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
-#define CAN_AM09L                      0xFFC02B48 /* Mailbox 9 Low Acceptance Mask  */
-#define CAN_AM09H                      0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
-#define CAN_AM10L                      0xFFC02B50 /* Mailbox 10 Low Acceptance Mask  */
-#define CAN_AM10H                      0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
-#define CAN_AM11L                      0xFFC02B58 /* Mailbox 11 Low Acceptance Mask  */
-#define CAN_AM11H                      0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
-#define CAN_AM12L                      0xFFC02B60 /* Mailbox 12 Low Acceptance Mask  */
-#define CAN_AM12H                      0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
-#define CAN_AM13L                      0xFFC02B68 /* Mailbox 13 Low Acceptance Mask  */
-#define CAN_AM13H                      0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
-#define CAN_AM14L                      0xFFC02B70 /* Mailbox 14 Low Acceptance Mask  */
-#define CAN_AM14H                      0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
-#define CAN_AM15L                      0xFFC02B78 /* Mailbox 15 Low Acceptance Mask  */
-#define CAN_AM15H                      0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
-#define CAN_AM16L                      0xFFC02B80 /* Mailbox 16 Low Acceptance Mask  */
-#define CAN_AM16H                      0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
-#define CAN_AM17L                      0xFFC02B88 /* Mailbox 17 Low Acceptance Mask  */
-#define CAN_AM17H                      0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
-#define CAN_AM18L                      0xFFC02B90 /* Mailbox 18 Low Acceptance Mask  */
-#define CAN_AM18H                      0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
-#define CAN_AM19L                      0xFFC02B98 /* Mailbox 19 Low Acceptance Mask  */
-#define CAN_AM19H                      0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
-#define CAN_AM20L                      0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask  */
-#define CAN_AM20H                      0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
-#define CAN_AM21L                      0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask  */
-#define CAN_AM21H                      0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
-#define CAN_AM22L                      0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask  */
-#define CAN_AM22H                      0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
-#define CAN_AM23L                      0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask  */
-#define CAN_AM23H                      0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
-#define CAN_AM24L                      0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask  */
-#define CAN_AM24H                      0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
-#define CAN_AM25L                      0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask  */
-#define CAN_AM25H                      0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
-#define CAN_AM26L                      0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask  */
-#define CAN_AM26H                      0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
-#define CAN_AM27L                      0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask  */
-#define CAN_AM27H                      0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
-#define CAN_AM28L                      0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask  */
-#define CAN_AM28H                      0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
-#define CAN_AM29L                      0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask  */
-#define CAN_AM29H                      0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
-#define CAN_AM30L                      0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask  */
-#define CAN_AM30H                      0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
-#define CAN_AM31L                      0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask  */
-#define CAN_AM31H                      0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
-#define CAN_MB00_DATA0                 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
-#define CAN_MB00_DATA1                 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
-#define CAN_MB00_DATA2                 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
-#define CAN_MB00_DATA3                 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
-#define CAN_MB00_LENGTH                0xFFC02C10 /* Mailbox 0 Data Length Code Register */
-#define CAN_MB00_TIMESTAMP             0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
-#define CAN_MB00_ID0                   0xFFC02C18 /* Mailbox 0 Identifier Low Register */
-#define CAN_MB00_ID1                   0xFFC02C1C /* Mailbox 0 Identifier High Register */
-#define CAN_MB01_DATA0                 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register  */
-#define CAN_MB01_DATA1                 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
-#define CAN_MB01_DATA2                 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
-#define CAN_MB01_DATA3                 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
-#define CAN_MB01_LENGTH                0xFFC02C30 /* Mailbox 1 Data Length Code Register */
-#define CAN_MB01_TIMESTAMP             0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
-#define CAN_MB01_ID0                   0xFFC02C38 /* Mailbox 1 Identifier Low Register */
-#define CAN_MB01_ID1                   0xFFC02C3C /* Mailbox 1 Identifier High Register */
-#define CAN_MB02_DATA0                 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register  */
-#define CAN_MB02_DATA1                 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
-#define CAN_MB02_DATA2                 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
-#define CAN_MB02_DATA3                 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
-#define CAN_MB02_LENGTH                0xFFC02C50 /* Mailbox 2 Data Length Code Register    */
-#define CAN_MB02_TIMESTAMP             0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
-#define CAN_MB02_ID0                   0xFFC02C58 /* Mailbox 2 Identifier Low Register */
-#define CAN_MB02_ID1                   0xFFC02C5C /* Mailbox 2 Identifier High Register */
-#define CAN_MB03_DATA0                 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register  */
-#define CAN_MB03_DATA1                 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
-#define CAN_MB03_DATA2                 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
-#define CAN_MB03_DATA3                 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
-#define CAN_MB03_LENGTH                0xFFC02C70 /* Mailbox 3 Data Length Code Register */
-#define CAN_MB03_TIMESTAMP             0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
-#define CAN_MB03_ID0                   0xFFC02C78 /* Mailbox 3 Identifier Low Register */
-#define CAN_MB03_ID1                   0xFFC02C7C /* Mailbox 3 Identifier High Register */
-#define CAN_MB04_DATA0                 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
-#define CAN_MB04_DATA1                 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
-#define CAN_MB04_DATA2                 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
-#define CAN_MB04_DATA3                 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
-#define CAN_MB04_LENGTH                0xFFC02C90 /* Mailbox 4 Data Length Code Register */
-#define CAN_MB04_TIMESTAMP             0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
-#define CAN_MB04_ID0                   0xFFC02C98 /* Mailbox 4 Identifier Low Register */
-#define CAN_MB04_ID1                   0xFFC02C9C /* Mailbox 4 Identifier High Register */
-#define CAN_MB05_DATA0                 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register  */
-#define CAN_MB05_DATA1                 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
-#define CAN_MB05_DATA2                 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
-#define CAN_MB05_DATA3                 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
-#define CAN_MB05_LENGTH                0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
-#define CAN_MB05_TIMESTAMP             0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
-#define CAN_MB05_ID0                   0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
-#define CAN_MB05_ID1                   0xFFC02CBC /* Mailbox 5 Identifier High Register */
-#define CAN_MB06_DATA0                 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register  */
-#define CAN_MB06_DATA1                 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
-#define CAN_MB06_DATA2                 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
-#define CAN_MB06_DATA3                 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
-#define CAN_MB06_LENGTH                0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
-#define CAN_MB06_TIMESTAMP             0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
-#define CAN_MB06_ID0                   0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
-#define CAN_MB06_ID1                   0xFFC02CDC /* Mailbox 6 Identifier High Register */
-#define CAN_MB07_DATA0                 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
-#define CAN_MB07_DATA1                 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
-#define CAN_MB07_DATA2                 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
-#define CAN_MB07_DATA3                 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
-#define CAN_MB07_LENGTH                0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
-#define CAN_MB07_TIMESTAMP             0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
-#define CAN_MB07_ID0                   0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
-#define CAN_MB07_ID1                   0xFFC02CFC /* Mailbox 7 Identifier High Register */
-#define CAN_MB08_DATA0                 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
-#define CAN_MB08_DATA1                 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
-#define CAN_MB08_DATA2                 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
-#define CAN_MB08_DATA3                 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
-#define CAN_MB08_LENGTH                0xFFC02D10 /* Mailbox 8 Data Length Code Register */
-#define CAN_MB08_TIMESTAMP             0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
-#define CAN_MB08_ID0                   0xFFC02D18 /* Mailbox 8 Identifier Low Register */
-#define CAN_MB08_ID1                   0xFFC02D1C /* Mailbox 8 Identifier High Register */
-#define CAN_MB09_DATA0                 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
-#define CAN_MB09_DATA1                 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
-#define CAN_MB09_DATA2                 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
-#define CAN_MB09_DATA3                 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
-#define CAN_MB09_LENGTH                0xFFC02D30 /* Mailbox 9 Data Length Code Register */
-#define CAN_MB09_TIMESTAMP             0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
-#define CAN_MB09_ID0                   0xFFC02D38 /* Mailbox 9 Identifier Low Register */
-#define CAN_MB09_ID1                   0xFFC02D3C /* Mailbox 9 Identifier High Register */
-#define CAN_MB10_DATA0                 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
-#define CAN_MB10_DATA1                 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
-#define CAN_MB10_DATA2                 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
-#define CAN_MB10_DATA3                 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
-#define CAN_MB10_LENGTH                0xFFC02D50 /* Mailbox 10 Data Length Code Register */
-#define CAN_MB10_TIMESTAMP             0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
-#define CAN_MB10_ID0                   0xFFC02D58 /* Mailbox 10 Identifier Low Register */
-#define CAN_MB10_ID1                   0xFFC02D5C /* Mailbox 10 Identifier High Register */
-#define CAN_MB11_DATA0                 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
-#define CAN_MB11_DATA1                 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
-#define CAN_MB11_DATA2                 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
-#define CAN_MB11_DATA3                 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
-#define CAN_MB11_LENGTH                0xFFC02D70 /* Mailbox 11 Data Length Code Register */
-#define CAN_MB11_TIMESTAMP             0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
-#define CAN_MB11_ID0                   0xFFC02D78 /* Mailbox 11 Identifier Low Register */
-#define CAN_MB11_ID1                   0xFFC02D7C /* Mailbox 11 Identifier High Register */
-#define CAN_MB12_DATA0                 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
-#define CAN_MB12_DATA1                 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
-#define CAN_MB12_DATA2                 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
-#define CAN_MB12_DATA3                 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
-#define CAN_MB12_LENGTH                0xFFC02D90 /* Mailbox 12 Data Length Code Register */
-#define CAN_MB12_TIMESTAMP             0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
-#define CAN_MB12_ID0                   0xFFC02D98 /* Mailbox 12 Identifier Low Register */
-#define CAN_MB12_ID1                   0xFFC02D9C /* Mailbox 12 Identifier High Register */
-#define CAN_MB13_DATA0                 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
-#define CAN_MB13_DATA1                 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
-#define CAN_MB13_DATA2                 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
-#define CAN_MB13_DATA3                 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
-#define CAN_MB13_LENGTH                0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
-#define CAN_MB13_TIMESTAMP             0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
-#define CAN_MB13_ID0                   0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
-#define CAN_MB13_ID1                   0xFFC02DBC /* Mailbox 13 Identifier High Register */
-#define CAN_MB14_DATA0                 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
-#define CAN_MB14_DATA1                 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
-#define CAN_MB14_DATA2                 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
-#define CAN_MB14_DATA3                 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
-#define CAN_MB14_LENGTH                0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
-#define CAN_MB14_TIMESTAMP             0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
-#define CAN_MB14_ID0                   0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
-#define CAN_MB14_ID1                   0xFFC02DDC /* Mailbox 14 Identifier High Register */
-#define CAN_MB15_DATA0                 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
-#define CAN_MB15_DATA1                 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
-#define CAN_MB15_DATA2                 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
-#define CAN_MB15_DATA3                 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
-#define CAN_MB15_LENGTH                0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
-#define CAN_MB15_TIMESTAMP             0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
-#define CAN_MB15_ID0                   0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
-#define CAN_MB15_ID1                   0xFFC02DFC /* Mailbox 15 Identifier High Register */
-#define CAN_MB16_DATA0                 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
-#define CAN_MB16_DATA1                 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
-#define CAN_MB16_DATA2                 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
-#define CAN_MB16_DATA3                 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
-#define CAN_MB16_LENGTH                0xFFC02E10 /* Mailbox 16 Data Length Code Register */
-#define CAN_MB16_TIMESTAMP             0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
-#define CAN_MB16_ID0                   0xFFC02E18 /* Mailbox 16 Identifier Low Register */
-#define CAN_MB16_ID1                   0xFFC02E1C /* Mailbox 16 Identifier High Register */
-#define CAN_MB17_DATA0                 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
-#define CAN_MB17_DATA1                 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
-#define CAN_MB17_DATA2                 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
-#define CAN_MB17_DATA3                 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
-#define CAN_MB17_LENGTH                0xFFC02E30 /* Mailbox 17 Data Length Code Register */
-#define CAN_MB17_TIMESTAMP             0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
-#define CAN_MB17_ID0                   0xFFC02E38 /* Mailbox 17 Identifier Low Register */
-#define CAN_MB17_ID1                   0xFFC02E3C /* Mailbox 17 Identifier High Register */
-#define CAN_MB18_DATA0                 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
-#define CAN_MB18_DATA1                 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
-#define CAN_MB18_DATA2                 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
-#define CAN_MB18_DATA3                 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
-#define CAN_MB18_LENGTH                0xFFC02E50 /* Mailbox 18 Data Length Code Register */
-#define CAN_MB18_TIMESTAMP             0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
-#define CAN_MB18_ID0                   0xFFC02E58 /* Mailbox 18 Identifier Low Register */
-#define CAN_MB18_ID1                   0xFFC02E5C /* Mailbox 18 Identifier High Register */
-#define CAN_MB19_DATA0                 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
-#define CAN_MB19_DATA1                 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
-#define CAN_MB19_DATA2                 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
-#define CAN_MB19_DATA3                 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
-#define CAN_MB19_LENGTH                0xFFC02E70 /* Mailbox 19 Data Length Code Register */
-#define CAN_MB19_TIMESTAMP             0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
-#define CAN_MB19_ID0                   0xFFC02E78 /* Mailbox 19 Identifier Low Register */
-#define CAN_MB19_ID1                   0xFFC02E7C /* Mailbox 19 Identifier High Register */
-#define CAN_MB20_DATA0                 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
-#define CAN_MB20_DATA1                 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
-#define CAN_MB20_DATA2                 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
-#define CAN_MB20_DATA3                 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
-#define CAN_MB20_LENGTH                0xFFC02E90 /* Mailbox 20 Data Length Code Register */
-#define CAN_MB20_TIMESTAMP             0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
-#define CAN_MB20_ID0                   0xFFC02E98 /* Mailbox 20 Identifier Low Register */
-#define CAN_MB20_ID1                   0xFFC02E9C /* Mailbox 20 Identifier High Register */
-#define CAN_MB21_DATA0                 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
-#define CAN_MB21_DATA1                 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
-#define CAN_MB21_DATA2                 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
-#define CAN_MB21_DATA3                 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
-#define CAN_MB21_LENGTH                0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
-#define CAN_MB21_TIMESTAMP             0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
-#define CAN_MB21_ID0                   0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
-#define CAN_MB21_ID1                   0xFFC02EBC /* Mailbox 21 Identifier High Register */
-#define CAN_MB22_DATA0                 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
-#define CAN_MB22_DATA1                 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
-#define CAN_MB22_DATA2                 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
-#define CAN_MB22_DATA3                 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
-#define CAN_MB22_LENGTH                0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
-#define CAN_MB22_TIMESTAMP             0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
-#define CAN_MB22_ID0                   0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
-#define CAN_MB22_ID1                   0xFFC02EDC /* Mailbox 22 Identifier High Register */
-#define CAN_MB23_DATA0                 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
-#define CAN_MB23_DATA1                 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
-#define CAN_MB23_DATA2                 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
-#define CAN_MB23_DATA3                 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
-#define CAN_MB23_LENGTH                0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
-#define CAN_MB23_TIMESTAMP             0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
-#define CAN_MB23_ID0                   0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
-#define CAN_MB23_ID1                   0xFFC02EFC /* Mailbox 23 Identifier High Register */
-#define CAN_MB24_DATA0                 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
-#define CAN_MB24_DATA1                 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
-#define CAN_MB24_DATA2                 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
-#define CAN_MB24_DATA3                 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
-#define CAN_MB24_LENGTH                0xFFC02F10 /* Mailbox 24 Data Length Code Register */
-#define CAN_MB24_TIMESTAMP             0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
-#define CAN_MB24_ID0                   0xFFC02F18 /* Mailbox 24 Identifier Low Register */
-#define CAN_MB24_ID1                   0xFFC02F1C /* Mailbox 24 Identifier High Register */
-#define CAN_MB25_DATA0                 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
-#define CAN_MB25_DATA1                 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
-#define CAN_MB25_DATA2                 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
-#define CAN_MB25_DATA3                 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
-#define CAN_MB25_LENGTH                0xFFC02F30 /* Mailbox 25 Data Length Code Register */
-#define CAN_MB25_TIMESTAMP             0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
-#define CAN_MB25_ID0                   0xFFC02F38 /* Mailbox 25 Identifier Low Register */
-#define CAN_MB25_ID1                   0xFFC02F3C /* Mailbox 25 Identifier High Register */
-#define CAN_MB26_DATA0                 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
-#define CAN_MB26_DATA1                 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
-#define CAN_MB26_DATA2                 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
-#define CAN_MB26_DATA3                 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
-#define CAN_MB26_LENGTH                0xFFC02F50 /* Mailbox 26 Data Length Code Register */
-#define CAN_MB26_TIMESTAMP             0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
-#define CAN_MB26_ID0                   0xFFC02F58 /* Mailbox 26 Identifier Low Register */
-#define CAN_MB26_ID1                   0xFFC02F5C /* Mailbox 26 Identifier High Register */
-#define CAN_MB27_DATA0                 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
-#define CAN_MB27_DATA1                 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
-#define CAN_MB27_DATA2                 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
-#define CAN_MB27_DATA3                 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
-#define CAN_MB27_LENGTH                0xFFC02F70 /* Mailbox 27 Data Length Code Register */
-#define CAN_MB27_TIMESTAMP             0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
-#define CAN_MB27_ID0                   0xFFC02F78 /* Mailbox 27 Identifier Low Register */
-#define CAN_MB27_ID1                   0xFFC02F7C /* Mailbox 27 Identifier High Register */
-#define CAN_MB28_DATA0                 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
-#define CAN_MB28_DATA1                 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
-#define CAN_MB28_DATA2                 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
-#define CAN_MB28_DATA3                 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
-#define CAN_MB28_LENGTH                0xFFC02F90 /* Mailbox 28 Data Length Code Register */
-#define CAN_MB28_TIMESTAMP             0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
-#define CAN_MB28_ID0                   0xFFC02F98 /* Mailbox 28 Identifier Low Register */
-#define CAN_MB28_ID1                   0xFFC02F9C /* Mailbox 28 Identifier High Register */
-#define CAN_MB29_DATA0                 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
-#define CAN_MB29_DATA1                 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
-#define CAN_MB29_DATA2                 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
-#define CAN_MB29_DATA3                 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
-#define CAN_MB29_LENGTH                0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
-#define CAN_MB29_TIMESTAMP             0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
-#define CAN_MB29_ID0                   0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
-#define CAN_MB29_ID1                   0xFFC02FBC /* Mailbox 29 Identifier High Register */
-#define CAN_MB30_DATA0                 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
-#define CAN_MB30_DATA1                 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
-#define CAN_MB30_DATA2                 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
-#define CAN_MB30_DATA3                 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
-#define CAN_MB30_LENGTH                0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
-#define CAN_MB30_TIMESTAMP             0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
-#define CAN_MB30_ID0                   0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
-#define CAN_MB30_ID1                   0xFFC02FDC /* Mailbox 30 Identifier High Register */
-#define CAN_MB31_DATA0                 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
-#define CAN_MB31_DATA1                 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
-#define CAN_MB31_DATA2                 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
-#define CAN_MB31_DATA3                 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
-#define CAN_MB31_LENGTH                0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
-#define CAN_MB31_TIMESTAMP             0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
-#define CAN_MB31_ID0                   0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
-#define CAN_MB31_ID1                   0xFFC02FFC /* Mailbox 31 Identifier High Register */
-
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
-#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif /* __BFIN_DEF_ADSP_BF538_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf538/BF539_cdef.h b/arch/blackfin/include/asm/mach-bf538/BF539_cdef.h
deleted file mode 100644
index 7e785b4..0000000
--- a/arch/blackfin/include/asm/mach-bf538/BF539_cdef.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF538_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf538/BF539_def.h b/arch/blackfin/include/asm/mach-bf538/BF539_def.h
deleted file mode 100644
index 5a2ed8d..0000000
--- a/arch/blackfin/include/asm/mach-bf538/BF539_def.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF538_def.h"
diff --git a/arch/blackfin/include/asm/mach-bf538/anomaly.h b/arch/blackfin/include/asm/mach-bf538/anomaly.h
deleted file mode 100644
index b6ca997..0000000
--- a/arch/blackfin/include/asm/mach-bf538/anomaly.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- *  - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
- *  - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support old silicon - sorry */
-#if __SILICON_REVISION__ < 4
-# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
-#endif
-
-#if defined(__ADSPBF538__)
-# define ANOMALY_BF538 1
-#else
-# define ANOMALY_BF538 0
-#endif
-#if defined(__ADSPBF539__)
-# define ANOMALY_BF539 1
-#else
-# define ANOMALY_BF539 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (1)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (1)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (ANOMALY_BF538)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
-/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
-#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
-/* Hibernate Leakage Current Is Higher Than Specified */
-#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000294 (1)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
-/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
-#define ANOMALY_05000317 (__SILICON_REVISION__ < 4)	/* XXX: Same as 05000318 */
-/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
-#define ANOMALY_05000318 (__SILICON_REVISION__ < 4)	/* XXX: Same as 05000317 */
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
-/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
-#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
-/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
-#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Specific GPIO Pins May Change State when Entering Hibernate */
-#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000254 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf538/def_local.h b/arch/blackfin/include/asm/mach-bf538/def_local.h
deleted file mode 100644
index 54d8e76..0000000
--- a/arch/blackfin/include/asm/mach-bf538/def_local.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define BF538_FAMILY 1	/* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf538/gpio.h b/arch/blackfin/include/asm/mach-bf538/gpio.h
deleted file mode 100644
index bd9adb7..0000000
--- a/arch/blackfin/include/asm/mach-bf538/gpio.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (C) 2008-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 16
-#define BFIN_SPECIAL_GPIO_BANKS 3
-
-#define GPIO_PF0	0	/* PF */
-#define GPIO_PF1	1
-#define GPIO_PF2	2
-#define GPIO_PF3	3
-#define GPIO_PF4	4
-#define GPIO_PF5	5
-#define GPIO_PF6	6
-#define GPIO_PF7	7
-#define GPIO_PF8	8
-#define GPIO_PF9	9
-#define GPIO_PF10	10
-#define GPIO_PF11	11
-#define GPIO_PF12	12
-#define GPIO_PF13	13
-#define GPIO_PF14	14
-#define GPIO_PF15	15
-#define GPIO_PC0	16	/* PC */
-#define GPIO_PC1	17
-#define GPIO_PC4	20
-#define GPIO_PC5	21
-#define GPIO_PC6	22
-#define GPIO_PC7	23
-#define GPIO_PC8	24
-#define GPIO_PC9	25
-#define GPIO_PD0	32	/* PD */
-#define GPIO_PD1	33
-#define GPIO_PD2	34
-#define GPIO_PD3	35
-#define GPIO_PD4	36
-#define GPIO_PD5	37
-#define GPIO_PD6	38
-#define GPIO_PD7	39
-#define GPIO_PD8	40
-#define GPIO_PD9	41
-#define GPIO_PD10	42
-#define GPIO_PD11	43
-#define GPIO_PD12	44
-#define GPIO_PD13	45
-#define GPIO_PE0	48	/* PE */
-#define GPIO_PE1	49
-#define GPIO_PE2	50
-#define GPIO_PE3	51
-#define GPIO_PE4	52
-#define GPIO_PE5	53
-#define GPIO_PE6	54
-#define GPIO_PE7	55
-#define GPIO_PE8	56
-#define GPIO_PE9	57
-#define GPIO_PE10	58
-#define GPIO_PE11	59
-#define GPIO_PE12	60
-#define GPIO_PE13	61
-#define GPIO_PE14	62
-#define GPIO_PE15	63
-
-#define PORT_F GPIO_PF0
-#define PORT_C GPIO_PC0
-#define PORT_D GPIO_PD0
-#define PORT_E GPIO_PE0
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf538/portmux.h b/arch/blackfin/include/asm/mach-bf538/portmux.h
deleted file mode 100644
index b773c5f..0000000
--- a/arch/blackfin/include/asm/mach-bf538/portmux.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES	64
-
-#define P_TMR2		(P_DONTCARE)
-#define P_TMR1		(P_DONTCARE)
-#define P_TMR0		(P_DONTCARE)
-#define P_TMRCLK	(P_DONTCARE)
-#define P_PPI0_CLK	(P_DONTCARE)
-#define P_PPI0_FS1	(P_DONTCARE)
-#define P_PPI0_FS2	(P_DONTCARE)
-
-#define P_TWI0_SCL	(P_DONTCARE)
-#define P_TWI0_SDA	(P_DONTCARE)
-#define P_TWI1_SCL	(P_DONTCARE)
-#define P_TWI1_SDA	(P_DONTCARE)
-
-#define P_SPORT1_TSCLK	(P_DONTCARE)
-#define P_SPORT1_RSCLK	(P_DONTCARE)
-#define P_SPORT0_TSCLK	(P_DONTCARE)
-#define P_SPORT0_RSCLK	(P_DONTCARE)
-#define P_SPORT1_DRSEC	(P_DONTCARE)
-#define P_SPORT1_RFS	(P_DONTCARE)
-#define P_SPORT1_DTPRI	(P_DONTCARE)
-#define P_SPORT1_DTSEC	(P_DONTCARE)
-#define P_SPORT1_TFS	(P_DONTCARE)
-#define P_SPORT1_DRPRI	(P_DONTCARE)
-#define P_SPORT0_DRSEC	(P_DONTCARE)
-#define P_SPORT0_RFS	(P_DONTCARE)
-#define P_SPORT0_DTPRI	(P_DONTCARE)
-#define P_SPORT0_DTSEC	(P_DONTCARE)
-#define P_SPORT0_TFS	(P_DONTCARE)
-#define P_SPORT0_DRPRI	(P_DONTCARE)
-
-#define P_UART0_RX	(P_DONTCARE)
-#define P_UART0_TX	(P_DONTCARE)
-
-#define P_SPI0_MOSI	(P_DONTCARE)
-#define P_SPI0_MISO	(P_DONTCARE)
-#define P_SPI0_SCK	(P_DONTCARE)
-
-#define P_PPI0_D0	(P_DONTCARE)
-#define P_PPI0_D1	(P_DONTCARE)
-#define P_PPI0_D2	(P_DONTCARE)
-#define P_PPI0_D3	(P_DONTCARE)
-
-#define P_CAN0_TX	(P_DEFINED | P_IDENT(GPIO_PC0))
-#define P_CAN0_RX	(P_DEFINED | P_IDENT(GPIO_PC1))
-
-#define P_SPI1_MOSI	(P_DEFINED | P_IDENT(GPIO_PD0))
-#define P_SPI1_MISO	(P_DEFINED | P_IDENT(GPIO_PD1))
-#define P_SPI1_SCK	(P_DEFINED | P_IDENT(GPIO_PD2))
-#define P_SPI1_SS	(P_DEFINED | P_IDENT(GPIO_PD3))
-#define P_SPI1_SSEL1	(P_DEFINED | P_IDENT(GPIO_PD4))
-#define P_SPI2_MOSI	(P_DEFINED | P_IDENT(GPIO_PD5))
-#define P_SPI2_MISO	(P_DEFINED | P_IDENT(GPIO_PD6))
-#define P_SPI2_SCK	(P_DEFINED | P_IDENT(GPIO_PD7))
-#define P_SPI2_SS	(P_DEFINED | P_IDENT(GPIO_PD8))
-#define P_SPI2_SSEL1	(P_DEFINED | P_IDENT(GPIO_PD9))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PD10))
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PD11))
-#define P_UART2_RX	(P_DEFINED | P_IDENT(GPIO_PD12))
-#define P_UART2_TX	(P_DEFINED | P_IDENT(GPIO_PD13))
-
-#define P_SPORT2_RSCLK	(P_DEFINED | P_IDENT(GPIO_PE0))
-#define P_SPORT2_RFS	(P_DEFINED | P_IDENT(GPIO_PE1))
-#define P_SPORT2_DRPRI	(P_DEFINED | P_IDENT(GPIO_PE2))
-#define P_SPORT2_DRSEC	(P_DEFINED | P_IDENT(GPIO_PE3))
-#define P_SPORT2_TSCLK	(P_DEFINED | P_IDENT(GPIO_PE4))
-#define P_SPORT2_TFS	(P_DEFINED | P_IDENT(GPIO_PE5))
-#define P_SPORT2_DTPRI	(P_DEFINED | P_IDENT(GPIO_PE6))
-#define P_SPORT2_DTSEC	(P_DEFINED | P_IDENT(GPIO_PE7))
-#define P_SPORT3_RSCLK	(P_DEFINED | P_IDENT(GPIO_PE8))
-#define P_SPORT3_RFS	(P_DEFINED | P_IDENT(GPIO_PE9))
-#define P_SPORT3_DRPRI	(P_DEFINED | P_IDENT(GPIO_PE10))
-#define P_SPORT3_DRSEC	(P_DEFINED | P_IDENT(GPIO_PE11))
-#define P_SPORT3_TSCLK	(P_DEFINED | P_IDENT(GPIO_PE12))
-#define P_SPORT3_TFS	(P_DEFINED | P_IDENT(GPIO_PE13))
-#define P_SPORT3_DTPRI	(P_DEFINED | P_IDENT(GPIO_PE14))
-#define P_SPORT3_DTSEC	(P_DEFINED | P_IDENT(GPIO_PE15))
-
-#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF11))
-
-#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF12))
-#define P_SPI0_SSEL7	(P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6	(P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5	(P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4	(P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PF0))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf538/ports.h b/arch/blackfin/include/asm/mach-bf538/ports.h
deleted file mode 100644
index 4ae09f0..0000000
--- a/arch/blackfin/include/asm/mach-bf538/ports.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-#include "../mach-common/bits/ports-c.h"
-#include "../mach-common/bits/ports-d.h"
-#include "../mach-common/bits/ports-e.h"
-#include "../mach-common/bits/ports-f.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
deleted file mode 100644
index 84fa5d2..0000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
+++ /dev/null
@@ -1,2913 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_EDN_BF542_extended__
-#define __BFIN_CDEF_ADSP_EDN_BF542_extended__
-
-#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
-#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
-#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
-#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
-#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
-#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
-#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
-#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
-#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
-#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
-#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
-#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
-#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA()              bfin_read16(PORTA)
-#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB()              bfin_read16(PORTB)
-#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC()              bfin_read16(PORTC)
-#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD()              bfin_read16(PORTD)
-#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE()              bfin_read16(PORTE)
-#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF()              bfin_read16(PORTF)
-#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG()              bfin_read16(PORTG)
-#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH()              bfin_read16(PORTH)
-#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
-#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI()              bfin_read16(PORTI)
-#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
-#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ()              bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
-#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
-#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
-#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
-#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
-#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
-#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
-#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
-#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
-#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
-#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
-#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
-#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
-#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
-#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
-#define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
-#define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
-#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
-#define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
-#define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
-#define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
-#define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
-#define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
-#define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
-#define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
-#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
-#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
-#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
-#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
-#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
-#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_EDN_BF542_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h
deleted file mode 100644
index d94744d..0000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h
+++ /dev/null
@@ -1,1463 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_EDN_BF542_extended__
-#define __BFIN_DEF_ADSP_EDN_BF542_extended__
-
-#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
-#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
-#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
-#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
-#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
-#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
-#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
-#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
-#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
-#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
-#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
-#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
-#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
-#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
-#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
-#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
-#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
-#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
-#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
-#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
-#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
-#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
-#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
-#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
-#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
-#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
-#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
-#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
-#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
-#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
-#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
-#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
-#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
-#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
-#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
-#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
-#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
-#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
-#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
-#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
-#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
-#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
-#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
-#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
-#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
-#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
-#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
-#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
-#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
-#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
-#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
-#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
-#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
-#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
-#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
-#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
-#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
-#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
-#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
-#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
-#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
-#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
-#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
-#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
-#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
-#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
-#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
-#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
-#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
-#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
-#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
-#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
-#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
-#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
-#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
-#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
-#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
-#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
-#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
-#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
-#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
-#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
-#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
-#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
-#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
-#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
-#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
-#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
-#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
-#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
-#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
-#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
-#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
-#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
-#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
-#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
-#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
-#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
-#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
-#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
-#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
-#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
-#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
-#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
-#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
-#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
-#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
-#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
-#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
-#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
-#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
-#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
-#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
-#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
-#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
-#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
-#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
-#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
-#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
-#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
-#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
-#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
-#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
-#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
-#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
-#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
-#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
-#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
-#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
-#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
-#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
-#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
-#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
-#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
-#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
-#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
-#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
-#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
-#define PORTA                          0xFFC014C4 /* GPIO Data Register */
-#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
-#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
-#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
-#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
-#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
-#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
-#define PORTB                          0xFFC014E4 /* GPIO Data Register */
-#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
-#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
-#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
-#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
-#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
-#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
-#define PORTC                          0xFFC01504 /* GPIO Data Register */
-#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
-#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
-#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
-#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
-#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
-#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
-#define PORTD                          0xFFC01524 /* GPIO Data Register */
-#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
-#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
-#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
-#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
-#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
-#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
-#define PORTE                          0xFFC01544 /* GPIO Data Register */
-#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
-#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
-#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
-#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
-#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
-#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
-#define PORTF                          0xFFC01564 /* GPIO Data Register */
-#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
-#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
-#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
-#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
-#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
-#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
-#define PORTG                          0xFFC01584 /* GPIO Data Register */
-#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
-#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
-#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
-#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
-#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
-#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
-#define PORTH                          0xFFC015A4 /* GPIO Data Register */
-#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
-#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
-#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
-#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
-#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
-#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
-#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
-#define PORTI                          0xFFC015C4 /* GPIO Data Register */
-#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
-#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
-#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
-#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
-#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
-#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
-#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
-#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
-#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
-#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
-#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
-#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
-#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
-#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
-#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
-#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
-#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
-#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
-#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
-#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
-#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
-#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
-#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
-#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
-#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
-#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
-#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
-#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
-#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
-#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
-#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
-#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
-#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
-#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
-#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
-#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
-#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
-#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
-#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
-#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
-#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
-#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
-#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
-#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
-#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
-#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
-#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
-#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
-#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
-#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
-#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
-#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
-#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
-#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
-#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
-#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
-#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
-#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
-#define CNT_STATUS                     0xFFC04208 /* Status Register  */
-#define CNT_COMMAND                    0xFFC0420C /* Command Register */
-#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
-#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
-#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
-#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
-#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
-#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
-#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
-#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
-#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
-#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
-#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
-#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
-#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define KPAD_CTL                       0xFFC04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE                  0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL                      0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL                    0xFFC0410C /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT                      0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL                  0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
-#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
-#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
-#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
-#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
-#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
-#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
-#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
-#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
-#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
-#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
-#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
-#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
-#define SDH_STATUS                     0xFFC03934 /* SDH Status */
-#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
-#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
-#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
-#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
-#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
-#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
-#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
-#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
-#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
-#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
-#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
-#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
-#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
-#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
-#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
-#define ATAPI_CONTROL                  0xFFC03800 /* ATAPI Control Register */
-#define ATAPI_STATUS                   0xFFC03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR                 0xFFC03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF                0xFFC0380C /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF                0xFFC03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK                 0xFFC03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS               0xFFC03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN                 0xFFC0381C /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS              0xFFC03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE                 0xFFC03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE                0xFFC03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT               0xFFC0382C /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT               0xFFC03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT             0xFFC03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT           0xFFC03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0                0xFFC03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0                0xFFC03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1                0xFFC03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0              0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1              0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2              0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0              0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1              0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2              0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3              0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
-#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
-#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
-#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
-#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
-#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
-#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
-#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
-#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
-#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
-#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
-#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
-#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
-#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
-#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
-#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
-#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
-#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
-#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
-#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
-#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
-#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
-#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
-#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
-#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
-#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
-#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
-#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
-#define CAN0_MC1                       0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN0_MD1                       0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN0_TRS1                      0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN0_TRR1                      0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN0_TA1                       0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN0_AA1                       0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1                      0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN0_RML1                      0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1                    0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1                    0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1                     0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1                      0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN0_OPSS1                     0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN0_MC2                       0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN0_MD2                       0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN0_TRS2                      0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN0_TRR2                      0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN0_TA2                       0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN0_AA2                       0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2                      0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN0_RML2                      0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2                    0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2                    0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2                     0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2                      0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN0_OPSS2                     0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN0_CLOCK                     0xFFC02A80 /* CAN Controller 0 Clock Register */
-#define CAN0_TIMING                    0xFFC02A84 /* CAN Controller 0 Timing Register */
-#define CAN0_DEBUG                     0xFFC02A88 /* CAN Controller 0 Debug Register */
-#define CAN0_STATUS                    0xFFC02A8C /* CAN Controller 0 Global Status Register */
-#define CAN0_CEC                       0xFFC02A90 /* CAN Controller 0 Error Counter Register */
-#define CAN0_GIS                       0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN0_GIM                       0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN0_GIF                       0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN0_CONTROL                   0xFFC02AA0 /* CAN Controller 0 Master Control Register */
-#define CAN0_INTR                      0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN0_MBTD                      0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN0_EWR                       0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN0_ESR                       0xFFC02AB4 /* CAN Controller 0 Error Status Register */
-#define CAN0_UCCNT                     0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
-#define CAN0_UCRC                      0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN0_UCCNF                     0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
-#define CAN0_AM00L                     0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN0_AM00H                     0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN0_AM01L                     0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN0_AM01H                     0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN0_AM02L                     0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN0_AM02H                     0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN0_AM03L                     0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN0_AM03H                     0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN0_AM04L                     0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN0_AM04H                     0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN0_AM05L                     0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN0_AM05H                     0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN0_AM06L                     0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN0_AM06H                     0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN0_AM07L                     0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN0_AM07H                     0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN0_AM08L                     0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN0_AM08H                     0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN0_AM09L                     0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN0_AM09H                     0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN0_AM10L                     0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN0_AM10H                     0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN0_AM11L                     0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN0_AM11H                     0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN0_AM12L                     0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN0_AM12H                     0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN0_AM13L                     0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN0_AM13H                     0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN0_AM14L                     0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN0_AM14H                     0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN0_AM15L                     0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN0_AM15H                     0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-#define CAN0_AM16L                     0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN0_AM16H                     0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN0_AM17L                     0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN0_AM17H                     0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN0_AM18L                     0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN0_AM18H                     0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN0_AM19L                     0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN0_AM19H                     0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN0_AM20L                     0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN0_AM20H                     0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN0_AM21L                     0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN0_AM21H                     0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN0_AM22L                     0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN0_AM22H                     0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN0_AM23L                     0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN0_AM23H                     0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN0_AM24L                     0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN0_AM24H                     0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN0_AM25L                     0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN0_AM25H                     0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN0_AM26L                     0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN0_AM26H                     0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN0_AM27L                     0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN0_AM27H                     0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN0_AM28L                     0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN0_AM28H                     0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN0_AM29L                     0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN0_AM29H                     0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN0_AM30L                     0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN0_AM30H                     0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN0_AM31L                     0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN0_AM31H                     0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-#define CAN0_MB00_DATA0                0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN0_MB00_DATA1                0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN0_MB00_DATA2                0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN0_MB00_DATA3                0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN0_MB00_LENGTH               0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN0_MB00_TIMESTAMP            0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN0_MB00_ID0                  0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN0_MB00_ID1                  0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN0_MB01_DATA0                0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN0_MB01_DATA1                0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN0_MB01_DATA2                0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN0_MB01_DATA3                0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN0_MB01_LENGTH               0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN0_MB01_TIMESTAMP            0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN0_MB01_ID0                  0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN0_MB01_ID1                  0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN0_MB02_DATA0                0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN0_MB02_DATA1                0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN0_MB02_DATA2                0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN0_MB02_DATA3                0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN0_MB02_LENGTH               0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN0_MB02_TIMESTAMP            0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN0_MB02_ID0                  0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN0_MB02_ID1                  0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN0_MB03_DATA0                0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN0_MB03_DATA1                0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN0_MB03_DATA2                0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN0_MB03_DATA3                0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN0_MB03_LENGTH               0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN0_MB03_TIMESTAMP            0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN0_MB03_ID0                  0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN0_MB03_ID1                  0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN0_MB04_DATA0                0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN0_MB04_DATA1                0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN0_MB04_DATA2                0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN0_MB04_DATA3                0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN0_MB04_LENGTH               0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN0_MB04_TIMESTAMP            0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN0_MB04_ID0                  0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN0_MB04_ID1                  0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN0_MB05_DATA0                0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN0_MB05_DATA1                0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN0_MB05_DATA2                0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN0_MB05_DATA3                0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN0_MB05_LENGTH               0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN0_MB05_TIMESTAMP            0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN0_MB05_ID0                  0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN0_MB05_ID1                  0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN0_MB06_DATA0                0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN0_MB06_DATA1                0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN0_MB06_DATA2                0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN0_MB06_DATA3                0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN0_MB06_LENGTH               0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN0_MB06_TIMESTAMP            0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN0_MB06_ID0                  0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN0_MB06_ID1                  0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN0_MB07_DATA0                0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN0_MB07_DATA1                0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN0_MB07_DATA2                0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN0_MB07_DATA3                0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN0_MB07_LENGTH               0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN0_MB07_TIMESTAMP            0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN0_MB07_ID0                  0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN0_MB07_ID1                  0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN0_MB08_DATA0                0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN0_MB08_DATA1                0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN0_MB08_DATA2                0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN0_MB08_DATA3                0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN0_MB08_LENGTH               0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN0_MB08_TIMESTAMP            0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN0_MB08_ID0                  0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN0_MB08_ID1                  0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN0_MB09_DATA0                0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN0_MB09_DATA1                0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN0_MB09_DATA2                0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN0_MB09_DATA3                0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN0_MB09_LENGTH               0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN0_MB09_TIMESTAMP            0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN0_MB09_ID0                  0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN0_MB09_ID1                  0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN0_MB10_DATA0                0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN0_MB10_DATA1                0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN0_MB10_DATA2                0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN0_MB10_DATA3                0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN0_MB10_LENGTH               0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN0_MB10_TIMESTAMP            0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN0_MB10_ID0                  0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN0_MB10_ID1                  0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN0_MB11_DATA0                0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN0_MB11_DATA1                0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN0_MB11_DATA2                0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN0_MB11_DATA3                0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN0_MB11_LENGTH               0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN0_MB11_TIMESTAMP            0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN0_MB11_ID0                  0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN0_MB11_ID1                  0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN0_MB12_DATA0                0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN0_MB12_DATA1                0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN0_MB12_DATA2                0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN0_MB12_DATA3                0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN0_MB12_LENGTH               0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN0_MB12_TIMESTAMP            0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN0_MB12_ID0                  0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN0_MB12_ID1                  0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN0_MB13_DATA0                0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN0_MB13_DATA1                0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN0_MB13_DATA2                0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN0_MB13_DATA3                0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN0_MB13_LENGTH               0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN0_MB13_TIMESTAMP            0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN0_MB13_ID0                  0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN0_MB13_ID1                  0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN0_MB14_DATA0                0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN0_MB14_DATA1                0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN0_MB14_DATA2                0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN0_MB14_DATA3                0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN0_MB14_LENGTH               0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN0_MB14_TIMESTAMP            0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN0_MB14_ID0                  0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN0_MB14_ID1                  0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN0_MB15_DATA0                0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN0_MB15_DATA1                0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN0_MB15_DATA2                0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN0_MB15_DATA3                0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN0_MB15_LENGTH               0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN0_MB15_TIMESTAMP            0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN0_MB15_ID0                  0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN0_MB15_ID1                  0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
-#define CAN0_MB16_DATA0                0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN0_MB16_DATA1                0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN0_MB16_DATA2                0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN0_MB16_DATA3                0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN0_MB16_LENGTH               0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN0_MB16_TIMESTAMP            0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN0_MB16_ID0                  0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN0_MB16_ID1                  0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN0_MB17_DATA0                0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN0_MB17_DATA1                0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN0_MB17_DATA2                0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN0_MB17_DATA3                0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN0_MB17_LENGTH               0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN0_MB17_TIMESTAMP            0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN0_MB17_ID0                  0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN0_MB17_ID1                  0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN0_MB18_DATA0                0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN0_MB18_DATA1                0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN0_MB18_DATA2                0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN0_MB18_DATA3                0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN0_MB18_LENGTH               0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN0_MB18_TIMESTAMP            0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN0_MB18_ID0                  0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN0_MB18_ID1                  0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN0_MB19_DATA0                0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN0_MB19_DATA1                0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN0_MB19_DATA2                0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN0_MB19_DATA3                0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN0_MB19_LENGTH               0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN0_MB19_TIMESTAMP            0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN0_MB19_ID0                  0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN0_MB19_ID1                  0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN0_MB20_DATA0                0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN0_MB20_DATA1                0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN0_MB20_DATA2                0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN0_MB20_DATA3                0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN0_MB20_LENGTH               0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN0_MB20_TIMESTAMP            0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN0_MB20_ID0                  0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN0_MB20_ID1                  0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN0_MB21_DATA0                0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN0_MB21_DATA1                0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN0_MB21_DATA2                0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN0_MB21_DATA3                0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN0_MB21_LENGTH               0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN0_MB21_TIMESTAMP            0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN0_MB21_ID0                  0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN0_MB21_ID1                  0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN0_MB22_DATA0                0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN0_MB22_DATA1                0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN0_MB22_DATA2                0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN0_MB22_DATA3                0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN0_MB22_LENGTH               0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN0_MB22_TIMESTAMP            0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN0_MB22_ID0                  0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN0_MB22_ID1                  0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN0_MB23_DATA0                0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN0_MB23_DATA1                0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN0_MB23_DATA2                0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN0_MB23_DATA3                0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN0_MB23_LENGTH               0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN0_MB23_TIMESTAMP            0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN0_MB23_ID0                  0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN0_MB23_ID1                  0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN0_MB24_DATA0                0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN0_MB24_DATA1                0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN0_MB24_DATA2                0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN0_MB24_DATA3                0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN0_MB24_LENGTH               0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN0_MB24_TIMESTAMP            0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN0_MB24_ID0                  0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN0_MB24_ID1                  0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN0_MB25_DATA0                0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN0_MB25_DATA1                0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN0_MB25_DATA2                0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN0_MB25_DATA3                0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN0_MB25_LENGTH               0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN0_MB25_TIMESTAMP            0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN0_MB25_ID0                  0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN0_MB25_ID1                  0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN0_MB26_DATA0                0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN0_MB26_DATA1                0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN0_MB26_DATA2                0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN0_MB26_DATA3                0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN0_MB26_LENGTH               0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN0_MB26_TIMESTAMP            0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN0_MB26_ID0                  0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN0_MB26_ID1                  0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN0_MB27_DATA0                0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN0_MB27_DATA1                0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN0_MB27_DATA2                0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN0_MB27_DATA3                0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN0_MB27_LENGTH               0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN0_MB27_TIMESTAMP            0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN0_MB27_ID0                  0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN0_MB27_ID1                  0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN0_MB28_DATA0                0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN0_MB28_DATA1                0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN0_MB28_DATA2                0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN0_MB28_DATA3                0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN0_MB28_LENGTH               0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN0_MB28_TIMESTAMP            0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN0_MB28_ID0                  0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN0_MB28_ID1                  0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN0_MB29_DATA0                0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN0_MB29_DATA1                0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN0_MB29_DATA2                0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN0_MB29_DATA3                0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN0_MB29_LENGTH               0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN0_MB29_TIMESTAMP            0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN0_MB29_ID0                  0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN0_MB29_ID1                  0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN0_MB30_DATA0                0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN0_MB30_DATA1                0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN0_MB30_DATA2                0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN0_MB30_DATA3                0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN0_MB30_LENGTH               0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN0_MB30_TIMESTAMP            0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN0_MB30_ID0                  0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN0_MB30_ID1                  0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN0_MB31_DATA0                0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN0_MB31_DATA1                0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN0_MB31_DATA2                0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN0_MB31_DATA3                0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN0_MB31_LENGTH               0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN0_MB31_TIMESTAMP            0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN0_MB31_ID0                  0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN0_MB31_ID1                  0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
-#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
-#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
-#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
-#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
-#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
-#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
-#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
-#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
-#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
-#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
-#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
-#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
-#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
-#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
-#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
-#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
-#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
-#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
-#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
-#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
-#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
-#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
-#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
-#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
-#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
-#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
-#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
-#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
-#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
-#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
-#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
-#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
-#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
-#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
-#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
-#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
-#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
-#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
-#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
-#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
-#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
-#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
-#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
-#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
-#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
-#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
-#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
-#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
-#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
-#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
-#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
-#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
-#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
-#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
-#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
-#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
-#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
-#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
-#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
-#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
-#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
-#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
-#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
-#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
-#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
-#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
-#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
-#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
-#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
-#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
-#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
-#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
-#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
-#define UART0_LCR                      0xFFC0040C /* Line Control Register */
-#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
-#define UART0_LSR                      0xFFC00414 /* Line Status Register */
-#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
-#define UART0_SCR                      0xFFC0041C /* Scratch Register */
-#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
-#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
-#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
-#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
-#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
-#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
-#define UART1_LCR                      0xFFC0200C /* Line Control Register */
-#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
-#define UART1_LSR                      0xFFC02014 /* Line Status Register */
-#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
-#define UART1_SCR                      0xFFC0201C /* Scratch Register */
-#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
-#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
-#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
-#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
-#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
-#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
-#define UART3_LCR                      0xFFC0310C /* Line Control Register */
-#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
-#define UART3_LSR                      0xFFC03114 /* Line Status Register */
-#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
-#define UART3_SCR                      0xFFC0311C /* Scratch Register */
-#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
-#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
-#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
-#define USB_FADDR                      0xFFC03C00 /* Function address register */
-#define USB_POWER                      0xFFC03C04 /* Power management register */
-#define USB_INTRTX                     0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX                     0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE                    0xFFC03C10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE                    0xFFC03C14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB                    0xFFC03C18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE                   0xFFC03C1C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME                      0xFFC03C20 /* USB frame number */
-#define USB_INDEX                      0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE                   0xFFC03C28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR                   0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL                 0xFFC03C30 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET              0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0                       0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR                      0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET              0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR                      0xFFC03C4C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0                     0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT                    0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE                     0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0                  0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL                 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE                     0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL                 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT                    0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO                   0xFFC03C80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO                   0xFFC03C88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO                   0xFFC03C90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO                   0xFFC03C98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO                   0xFFC03CA0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO                   0xFFC03CA8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO                   0xFFC03CB0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO                   0xFFC03CB8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL                0xFFC03D00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ               0xFFC03D04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK              0xFFC03D08 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO                   0xFFC03D48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN                      0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1                    0xFFC03D50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1                    0xFFC03D54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1                    0xFFC03D58 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL                 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB                 0xFFC03DE4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2                0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST                   0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL                0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV                 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP              0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR               0xFFC03E04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP              0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR               0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT             0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE              0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL          0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE              0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL          0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT             0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP              0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR               0xFFC03E44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP              0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR               0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT             0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE              0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL          0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE              0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL          0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT             0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP              0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR               0xFFC03E84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP              0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR               0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT             0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE              0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL          0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE              0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL          0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT             0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP              0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR               0xFFC03EC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP              0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR               0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT             0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE              0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL          0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE              0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL          0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT             0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP              0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR               0xFFC03F04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP              0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR               0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT             0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE              0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL          0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE              0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL          0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT             0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP              0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR               0xFFC03F44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP              0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR               0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT             0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE              0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL          0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE              0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL          0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT             0xFFC03F68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP              0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR               0xFFC03F84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP              0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR               0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT             0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE              0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL          0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE              0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL          0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT             0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP              0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR               0xFFC03FC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP              0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR               0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT             0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE              0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL          0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE              0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL          0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT             0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT              0xFFC04000 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL               0xFFC04004 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW               0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH              0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW              0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH             0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL               0xFFC04024 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW               0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH              0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW              0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH             0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL               0xFFC04044 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW               0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH              0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW              0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH             0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL               0xFFC04064 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW               0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH              0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW              0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH             0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL               0xFFC04084 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW               0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH              0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW              0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH             0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL               0xFFC040A4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW               0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH              0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW              0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH             0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL               0xFFC040C4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW               0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH              0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW              0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH             0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL               0xFFC040E4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW               0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH              0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW              0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH             0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_EDN_BF542_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
deleted file mode 100644
index 517e143..0000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
+++ /dev/null
@@ -1,3309 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_EDN_BF544_extended__
-#define __BFIN_CDEF_ADSP_EDN_BF544_extended__
-
-#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
-#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
-#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
-#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
-#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
-#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
-#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
-#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
-#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
-#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
-#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
-#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
-#define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
-#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
-#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA()              bfin_read16(PORTA)
-#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB()              bfin_read16(PORTB)
-#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC()              bfin_read16(PORTC)
-#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD()              bfin_read16(PORTD)
-#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE()              bfin_read16(PORTE)
-#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF()              bfin_read16(PORTF)
-#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG()              bfin_read16(PORTG)
-#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH()              bfin_read16(PORTH)
-#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
-#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI()              bfin_read16(PORTI)
-#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
-#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ()              bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
-#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
-#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
-#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
-#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
-#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
-#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
-#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
-#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
-#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
-#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
-#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
-#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
-#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
-#define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
-#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
-#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
-#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
-#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
-#define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
-#define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
-#define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
-#define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
-#define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
-#define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
-#define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
-#define bfin_read_CAN1_MC1()           bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val)       bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1()           bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val)       bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1()          bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val)      bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1()          bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val)      bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1()           bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val)       bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1()           bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val)       bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1()          bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val)      bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1()          bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val)      bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1()        bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val)    bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1()        bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val)    bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1()         bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val)     bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1()          bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val)      bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1()         bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val)     bfin_write16(CAN1_OPSS1, val)
-#define bfin_read_CAN1_MC2()           bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val)       bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2()           bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val)       bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2()          bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val)      bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2()          bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val)      bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2()           bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val)       bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2()           bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val)       bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2()          bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val)      bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2()          bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val)      bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2()        bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val)    bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2()        bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val)    bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2()         bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val)     bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2()          bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val)      bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2()         bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val)     bfin_write16(CAN1_OPSS2, val)
-#define bfin_read_CAN1_CLOCK()         bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val)     bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING()        bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val)    bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG()         bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val)     bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS()        bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val)    bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC()           bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val)       bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS()           bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val)       bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM()           bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val)       bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF()           bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val)       bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL()       bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val)   bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR()          bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val)      bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD()          bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val)      bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR()           bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val)       bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR()           bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val)       bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT()         bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val)     bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC()          bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val)      bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF()         bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val)     bfin_write16(CAN1_UCCNF, val)
-#define bfin_read_CAN1_AM00L()         bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val)     bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H()         bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val)     bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L()         bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val)     bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H()         bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val)     bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L()         bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val)     bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H()         bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val)     bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L()         bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val)     bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H()         bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val)     bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L()         bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val)     bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H()         bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val)     bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L()         bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val)     bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H()         bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val)     bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L()         bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val)     bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H()         bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val)     bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L()         bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val)     bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H()         bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val)     bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L()         bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val)     bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H()         bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val)     bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L()         bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val)     bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H()         bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val)     bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L()         bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val)     bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H()         bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val)     bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L()         bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val)     bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H()         bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val)     bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L()         bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val)     bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H()         bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val)     bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L()         bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val)     bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H()         bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val)     bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L()         bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val)     bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H()         bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val)     bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L()         bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val)     bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H()         bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val)     bfin_write16(CAN1_AM15H, val)
-#define bfin_read_CAN1_AM16L()         bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val)     bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H()         bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val)     bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L()         bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val)     bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H()         bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val)     bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L()         bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val)     bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H()         bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val)     bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L()         bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val)     bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H()         bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val)     bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L()         bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val)     bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H()         bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val)     bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L()         bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val)     bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H()         bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val)     bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L()         bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val)     bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H()         bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val)     bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L()         bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val)     bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H()         bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val)     bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L()         bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val)     bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H()         bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val)     bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L()         bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val)     bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H()         bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val)     bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L()         bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val)     bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H()         bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val)     bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L()         bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val)     bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H()         bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val)     bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L()         bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val)     bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H()         bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val)     bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L()         bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val)     bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H()         bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val)     bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L()         bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val)     bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H()         bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val)     bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L()         bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val)     bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H()         bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val)     bfin_write16(CAN1_AM31H, val)
-#define bfin_read_CAN1_MB00_DATA0()    bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1()    bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2()    bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3()    bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH()   bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0()      bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val)  bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1()      bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val)  bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0()    bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1()    bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2()    bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3()    bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH()   bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0()      bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val)  bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1()      bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val)  bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0()    bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1()    bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2()    bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3()    bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH()   bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0()      bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val)  bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1()      bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val)  bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0()    bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1()    bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2()    bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3()    bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH()   bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0()      bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val)  bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1()      bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val)  bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0()    bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1()    bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2()    bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3()    bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH()   bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0()      bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val)  bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1()      bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val)  bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0()    bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1()    bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2()    bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3()    bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH()   bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0()      bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val)  bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1()      bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val)  bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0()    bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1()    bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2()    bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3()    bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH()   bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0()      bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val)  bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1()      bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val)  bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0()    bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1()    bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2()    bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3()    bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH()   bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0()      bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val)  bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1()      bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val)  bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0()    bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1()    bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2()    bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3()    bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH()   bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0()      bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val)  bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1()      bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val)  bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0()    bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1()    bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2()    bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3()    bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH()   bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0()      bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val)  bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1()      bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val)  bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0()    bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1()    bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2()    bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3()    bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH()   bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0()      bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val)  bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1()      bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val)  bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0()    bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1()    bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2()    bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3()    bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH()   bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0()      bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val)  bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1()      bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val)  bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0()    bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1()    bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2()    bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3()    bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH()   bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0()      bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val)  bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1()      bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val)  bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0()    bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1()    bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2()    bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3()    bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH()   bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0()      bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val)  bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1()      bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val)  bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0()    bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1()    bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2()    bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3()    bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH()   bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0()      bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val)  bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1()      bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val)  bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0()    bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1()    bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2()    bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3()    bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH()   bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0()      bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val)  bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1()      bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val)  bfin_write16(CAN1_MB15_ID1, val)
-#define bfin_read_CAN1_MB16_DATA0()    bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1()    bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2()    bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3()    bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH()   bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0()      bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val)  bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1()      bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val)  bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0()    bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1()    bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2()    bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3()    bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH()   bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0()      bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val)  bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1()      bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val)  bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0()    bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1()    bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2()    bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3()    bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH()   bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0()      bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val)  bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1()      bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val)  bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0()    bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1()    bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2()    bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3()    bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH()   bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0()      bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val)  bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1()      bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val)  bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0()    bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1()    bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2()    bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3()    bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH()   bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0()      bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val)  bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1()      bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val)  bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0()    bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1()    bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2()    bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3()    bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH()   bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0()      bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val)  bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1()      bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val)  bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0()    bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1()    bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2()    bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3()    bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH()   bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0()      bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val)  bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1()      bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val)  bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0()    bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1()    bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2()    bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3()    bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH()   bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0()      bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val)  bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1()      bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val)  bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0()    bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1()    bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2()    bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3()    bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH()   bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0()      bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val)  bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1()      bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val)  bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0()    bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1()    bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2()    bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3()    bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH()   bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0()      bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val)  bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1()      bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val)  bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0()    bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1()    bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2()    bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3()    bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH()   bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0()      bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val)  bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1()      bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val)  bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0()    bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1()    bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2()    bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3()    bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH()   bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0()      bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val)  bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1()      bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val)  bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0()    bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1()    bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2()    bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3()    bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH()   bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0()      bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val)  bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1()      bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val)  bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0()    bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1()    bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2()    bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3()    bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH()   bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0()      bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val)  bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1()      bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val)  bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0()    bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1()    bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2()    bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3()    bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH()   bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0()      bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val)  bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1()      bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val)  bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0()    bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1()    bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2()    bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3()    bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH()   bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0()      bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val)  bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1()      bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val)  bfin_write16(CAN1_MB31_ID1, val)
-#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
-#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
-#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
-#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
-#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
-#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
-#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
-#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
-#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
-
-#endif /* __BFIN_CDEF_ADSP_EDN_BF544_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h
deleted file mode 100644
index 4b4f67d..0000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h
+++ /dev/null
@@ -1,1661 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_EDN_BF544_extended__
-#define __BFIN_DEF_ADSP_EDN_BF544_extended__
-
-#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
-#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
-#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
-#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
-#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
-#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
-#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
-#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
-#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
-#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
-#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
-#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
-#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
-#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
-#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
-#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
-#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
-#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
-#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
-#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
-#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
-#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
-#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
-#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
-#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
-#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
-#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
-#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
-#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
-#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
-#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
-#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
-#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
-#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
-#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
-#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
-#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
-#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
-#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
-#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
-#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
-#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
-#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
-#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
-#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
-#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
-#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
-#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
-#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
-#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
-#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
-#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
-#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
-#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
-#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
-#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
-#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
-#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
-#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
-#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
-#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
-#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
-#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
-#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
-#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
-#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
-#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
-#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
-#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
-#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
-#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
-#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
-#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
-#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
-#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
-#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
-#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
-#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
-#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
-#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
-#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
-#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
-#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
-#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
-#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
-#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
-#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
-#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
-#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
-#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
-#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
-#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
-#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
-#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
-#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
-#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
-#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
-#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
-#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
-#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
-#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
-#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
-#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
-#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
-#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
-#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
-#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
-#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
-#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
-#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
-#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
-#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
-#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
-#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
-#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
-#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
-#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
-#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
-#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
-#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
-#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
-#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
-#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
-#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
-#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
-#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
-#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
-#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
-#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
-#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
-#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
-#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
-#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
-#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
-#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
-#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
-#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
-#define PIXC_CTL                       0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL                       0xFFC04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF                       0xFFC04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART                   0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND                     0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART                   0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND                     0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP                   0xFFC0441C /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART                   0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND                     0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART                   0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND                     0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP                   0xFFC04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT                  0xFFC0443C /* Overlay interrupt configuration/status */
-#define PIXC_RYCON                     0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON                     0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON                     0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS                    0xFFC0444C /* Bias values for the color space conversion matrix */
-#define PIXC_TC                        0xFFC04450 /* Holds the transparent color value */
-#define HOST_CONTROL                   0xFFC03A00 /* HOSTDP Control Register */
-#define HOST_STATUS                    0xFFC03A04 /* HOSTDP Status Register */
-#define HOST_TIMEOUT                   0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
-#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
-#define PORTA                          0xFFC014C4 /* GPIO Data Register */
-#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
-#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
-#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
-#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
-#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
-#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
-#define PORTB                          0xFFC014E4 /* GPIO Data Register */
-#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
-#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
-#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
-#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
-#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
-#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
-#define PORTC                          0xFFC01504 /* GPIO Data Register */
-#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
-#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
-#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
-#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
-#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
-#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
-#define PORTD                          0xFFC01524 /* GPIO Data Register */
-#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
-#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
-#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
-#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
-#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
-#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
-#define PORTE                          0xFFC01544 /* GPIO Data Register */
-#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
-#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
-#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
-#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
-#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
-#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
-#define PORTF                          0xFFC01564 /* GPIO Data Register */
-#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
-#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
-#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
-#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
-#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
-#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
-#define PORTG                          0xFFC01584 /* GPIO Data Register */
-#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
-#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
-#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
-#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
-#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
-#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
-#define PORTH                          0xFFC015A4 /* GPIO Data Register */
-#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
-#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
-#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
-#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
-#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
-#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
-#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
-#define PORTI                          0xFFC015C4 /* GPIO Data Register */
-#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
-#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
-#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
-#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
-#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
-#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
-#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
-#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
-#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
-#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
-#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
-#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
-#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
-#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
-#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
-#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
-#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
-#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
-#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
-#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
-#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
-#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
-#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
-#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
-#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
-#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
-#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
-#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
-#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
-#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
-#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
-#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
-#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
-#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
-#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
-#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
-#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
-#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
-#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
-#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
-#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
-#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
-#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
-#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
-#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
-#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
-#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
-#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
-#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
-#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
-#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
-#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
-#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
-#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
-#define TIMER8_CONFIG                  0xFFC00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER                 0xFFC00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD                  0xFFC00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH                   0xFFC0060C /* Timer 8 Width Register */
-#define TIMER9_CONFIG                  0xFFC00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER                 0xFFC00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD                  0xFFC00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH                   0xFFC0061C /* Timer 9 Width Register */
-#define TIMER10_CONFIG                 0xFFC00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER                0xFFC00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD                 0xFFC00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH                  0xFFC0062C /* Timer 10 Width Register */
-#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
-#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
-#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
-#define TIMER_ENABLE1                  0xFFC00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1                 0xFFC00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1                  0xFFC00648 /* Timer Group of 3 Status Register */
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
-#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
-#define CNT_STATUS                     0xFFC04208 /* Status Register  */
-#define CNT_COMMAND                    0xFFC0420C /* Command Register */
-#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
-#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
-#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
-#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
-#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
-#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
-#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
-#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
-#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
-#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
-#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
-#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
-#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
-#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
-#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
-#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
-#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
-#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
-#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
-#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
-#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
-#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
-#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
-#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
-#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
-#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
-#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
-#define EPPI0_STATUS                   0xFFC01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT                   0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY                   0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT                   0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY                   0xFFC01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME                    0xFFC01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE                     0xFFC01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV                   0xFFC0101C /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL                  0xFFC01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL                 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL                0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB                 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF                0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP                     0xFFC01034 /* EPPI0 Clipping Register */
-#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
-#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
-#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
-#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
-#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
-#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
-#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
-#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
-#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
-#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
-#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
-#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
-#define CAN0_MC1                       0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN0_MD1                       0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN0_TRS1                      0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN0_TRR1                      0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN0_TA1                       0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN0_AA1                       0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1                      0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN0_RML1                      0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1                    0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1                    0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1                     0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1                      0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN0_OPSS1                     0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN0_MC2                       0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN0_MD2                       0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN0_TRS2                      0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN0_TRR2                      0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN0_TA2                       0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN0_AA2                       0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2                      0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN0_RML2                      0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2                    0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2                    0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2                     0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2                      0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN0_OPSS2                     0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN0_CLOCK                     0xFFC02A80 /* CAN Controller 0 Clock Register */
-#define CAN0_TIMING                    0xFFC02A84 /* CAN Controller 0 Timing Register */
-#define CAN0_DEBUG                     0xFFC02A88 /* CAN Controller 0 Debug Register */
-#define CAN0_STATUS                    0xFFC02A8C /* CAN Controller 0 Global Status Register */
-#define CAN0_CEC                       0xFFC02A90 /* CAN Controller 0 Error Counter Register */
-#define CAN0_GIS                       0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN0_GIM                       0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN0_GIF                       0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN0_CONTROL                   0xFFC02AA0 /* CAN Controller 0 Master Control Register */
-#define CAN0_INTR                      0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN0_MBTD                      0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN0_EWR                       0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN0_ESR                       0xFFC02AB4 /* CAN Controller 0 Error Status Register */
-#define CAN0_UCCNT                     0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
-#define CAN0_UCRC                      0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN0_UCCNF                     0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
-#define CAN0_AM00L                     0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN0_AM00H                     0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN0_AM01L                     0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN0_AM01H                     0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN0_AM02L                     0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN0_AM02H                     0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN0_AM03L                     0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN0_AM03H                     0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN0_AM04L                     0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN0_AM04H                     0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN0_AM05L                     0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN0_AM05H                     0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN0_AM06L                     0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN0_AM06H                     0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN0_AM07L                     0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN0_AM07H                     0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN0_AM08L                     0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN0_AM08H                     0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN0_AM09L                     0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN0_AM09H                     0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN0_AM10L                     0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN0_AM10H                     0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN0_AM11L                     0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN0_AM11H                     0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN0_AM12L                     0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN0_AM12H                     0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN0_AM13L                     0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN0_AM13H                     0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN0_AM14L                     0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN0_AM14H                     0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN0_AM15L                     0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN0_AM15H                     0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-#define CAN0_AM16L                     0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN0_AM16H                     0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN0_AM17L                     0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN0_AM17H                     0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN0_AM18L                     0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN0_AM18H                     0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN0_AM19L                     0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN0_AM19H                     0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN0_AM20L                     0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN0_AM20H                     0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN0_AM21L                     0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN0_AM21H                     0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN0_AM22L                     0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN0_AM22H                     0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN0_AM23L                     0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN0_AM23H                     0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN0_AM24L                     0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN0_AM24H                     0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN0_AM25L                     0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN0_AM25H                     0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN0_AM26L                     0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN0_AM26H                     0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN0_AM27L                     0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN0_AM27H                     0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN0_AM28L                     0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN0_AM28H                     0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN0_AM29L                     0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN0_AM29H                     0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN0_AM30L                     0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN0_AM30H                     0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN0_AM31L                     0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN0_AM31H                     0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-#define CAN0_MB00_DATA0                0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN0_MB00_DATA1                0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN0_MB00_DATA2                0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN0_MB00_DATA3                0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN0_MB00_LENGTH               0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN0_MB00_TIMESTAMP            0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN0_MB00_ID0                  0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN0_MB00_ID1                  0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN0_MB01_DATA0                0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN0_MB01_DATA1                0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN0_MB01_DATA2                0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN0_MB01_DATA3                0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN0_MB01_LENGTH               0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN0_MB01_TIMESTAMP            0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN0_MB01_ID0                  0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN0_MB01_ID1                  0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN0_MB02_DATA0                0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN0_MB02_DATA1                0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN0_MB02_DATA2                0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN0_MB02_DATA3                0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN0_MB02_LENGTH               0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN0_MB02_TIMESTAMP            0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN0_MB02_ID0                  0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN0_MB02_ID1                  0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN0_MB03_DATA0                0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN0_MB03_DATA1                0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN0_MB03_DATA2                0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN0_MB03_DATA3                0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN0_MB03_LENGTH               0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN0_MB03_TIMESTAMP            0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN0_MB03_ID0                  0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN0_MB03_ID1                  0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN0_MB04_DATA0                0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN0_MB04_DATA1                0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN0_MB04_DATA2                0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN0_MB04_DATA3                0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN0_MB04_LENGTH               0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN0_MB04_TIMESTAMP            0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN0_MB04_ID0                  0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN0_MB04_ID1                  0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN0_MB05_DATA0                0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN0_MB05_DATA1                0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN0_MB05_DATA2                0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN0_MB05_DATA3                0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN0_MB05_LENGTH               0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN0_MB05_TIMESTAMP            0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN0_MB05_ID0                  0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN0_MB05_ID1                  0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN0_MB06_DATA0                0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN0_MB06_DATA1                0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN0_MB06_DATA2                0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN0_MB06_DATA3                0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN0_MB06_LENGTH               0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN0_MB06_TIMESTAMP            0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN0_MB06_ID0                  0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN0_MB06_ID1                  0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN0_MB07_DATA0                0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN0_MB07_DATA1                0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN0_MB07_DATA2                0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN0_MB07_DATA3                0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN0_MB07_LENGTH               0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN0_MB07_TIMESTAMP            0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN0_MB07_ID0                  0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN0_MB07_ID1                  0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN0_MB08_DATA0                0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN0_MB08_DATA1                0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN0_MB08_DATA2                0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN0_MB08_DATA3                0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN0_MB08_LENGTH               0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN0_MB08_TIMESTAMP            0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN0_MB08_ID0                  0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN0_MB08_ID1                  0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN0_MB09_DATA0                0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN0_MB09_DATA1                0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN0_MB09_DATA2                0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN0_MB09_DATA3                0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN0_MB09_LENGTH               0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN0_MB09_TIMESTAMP            0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN0_MB09_ID0                  0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN0_MB09_ID1                  0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN0_MB10_DATA0                0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN0_MB10_DATA1                0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN0_MB10_DATA2                0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN0_MB10_DATA3                0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN0_MB10_LENGTH               0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN0_MB10_TIMESTAMP            0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN0_MB10_ID0                  0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN0_MB10_ID1                  0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN0_MB11_DATA0                0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN0_MB11_DATA1                0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN0_MB11_DATA2                0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN0_MB11_DATA3                0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN0_MB11_LENGTH               0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN0_MB11_TIMESTAMP            0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN0_MB11_ID0                  0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN0_MB11_ID1                  0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN0_MB12_DATA0                0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN0_MB12_DATA1                0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN0_MB12_DATA2                0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN0_MB12_DATA3                0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN0_MB12_LENGTH               0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN0_MB12_TIMESTAMP            0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN0_MB12_ID0                  0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN0_MB12_ID1                  0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN0_MB13_DATA0                0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN0_MB13_DATA1                0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN0_MB13_DATA2                0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN0_MB13_DATA3                0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN0_MB13_LENGTH               0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN0_MB13_TIMESTAMP            0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN0_MB13_ID0                  0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN0_MB13_ID1                  0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN0_MB14_DATA0                0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN0_MB14_DATA1                0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN0_MB14_DATA2                0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN0_MB14_DATA3                0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN0_MB14_LENGTH               0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN0_MB14_TIMESTAMP            0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN0_MB14_ID0                  0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN0_MB14_ID1                  0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN0_MB15_DATA0                0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN0_MB15_DATA1                0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN0_MB15_DATA2                0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN0_MB15_DATA3                0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN0_MB15_LENGTH               0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN0_MB15_TIMESTAMP            0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN0_MB15_ID0                  0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN0_MB15_ID1                  0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
-#define CAN0_MB16_DATA0                0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN0_MB16_DATA1                0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN0_MB16_DATA2                0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN0_MB16_DATA3                0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN0_MB16_LENGTH               0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN0_MB16_TIMESTAMP            0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN0_MB16_ID0                  0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN0_MB16_ID1                  0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN0_MB17_DATA0                0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN0_MB17_DATA1                0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN0_MB17_DATA2                0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN0_MB17_DATA3                0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN0_MB17_LENGTH               0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN0_MB17_TIMESTAMP            0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN0_MB17_ID0                  0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN0_MB17_ID1                  0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN0_MB18_DATA0                0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN0_MB18_DATA1                0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN0_MB18_DATA2                0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN0_MB18_DATA3                0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN0_MB18_LENGTH               0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN0_MB18_TIMESTAMP            0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN0_MB18_ID0                  0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN0_MB18_ID1                  0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN0_MB19_DATA0                0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN0_MB19_DATA1                0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN0_MB19_DATA2                0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN0_MB19_DATA3                0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN0_MB19_LENGTH               0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN0_MB19_TIMESTAMP            0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN0_MB19_ID0                  0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN0_MB19_ID1                  0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN0_MB20_DATA0                0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN0_MB20_DATA1                0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN0_MB20_DATA2                0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN0_MB20_DATA3                0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN0_MB20_LENGTH               0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN0_MB20_TIMESTAMP            0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN0_MB20_ID0                  0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN0_MB20_ID1                  0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN0_MB21_DATA0                0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN0_MB21_DATA1                0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN0_MB21_DATA2                0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN0_MB21_DATA3                0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN0_MB21_LENGTH               0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN0_MB21_TIMESTAMP            0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN0_MB21_ID0                  0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN0_MB21_ID1                  0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN0_MB22_DATA0                0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN0_MB22_DATA1                0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN0_MB22_DATA2                0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN0_MB22_DATA3                0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN0_MB22_LENGTH               0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN0_MB22_TIMESTAMP            0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN0_MB22_ID0                  0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN0_MB22_ID1                  0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN0_MB23_DATA0                0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN0_MB23_DATA1                0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN0_MB23_DATA2                0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN0_MB23_DATA3                0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN0_MB23_LENGTH               0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN0_MB23_TIMESTAMP            0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN0_MB23_ID0                  0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN0_MB23_ID1                  0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN0_MB24_DATA0                0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN0_MB24_DATA1                0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN0_MB24_DATA2                0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN0_MB24_DATA3                0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN0_MB24_LENGTH               0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN0_MB24_TIMESTAMP            0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN0_MB24_ID0                  0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN0_MB24_ID1                  0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN0_MB25_DATA0                0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN0_MB25_DATA1                0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN0_MB25_DATA2                0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN0_MB25_DATA3                0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN0_MB25_LENGTH               0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN0_MB25_TIMESTAMP            0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN0_MB25_ID0                  0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN0_MB25_ID1                  0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN0_MB26_DATA0                0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN0_MB26_DATA1                0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN0_MB26_DATA2                0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN0_MB26_DATA3                0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN0_MB26_LENGTH               0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN0_MB26_TIMESTAMP            0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN0_MB26_ID0                  0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN0_MB26_ID1                  0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN0_MB27_DATA0                0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN0_MB27_DATA1                0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN0_MB27_DATA2                0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN0_MB27_DATA3                0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN0_MB27_LENGTH               0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN0_MB27_TIMESTAMP            0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN0_MB27_ID0                  0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN0_MB27_ID1                  0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN0_MB28_DATA0                0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN0_MB28_DATA1                0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN0_MB28_DATA2                0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN0_MB28_DATA3                0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN0_MB28_LENGTH               0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN0_MB28_TIMESTAMP            0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN0_MB28_ID0                  0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN0_MB28_ID1                  0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN0_MB29_DATA0                0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN0_MB29_DATA1                0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN0_MB29_DATA2                0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN0_MB29_DATA3                0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN0_MB29_LENGTH               0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN0_MB29_TIMESTAMP            0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN0_MB29_ID0                  0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN0_MB29_ID1                  0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN0_MB30_DATA0                0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN0_MB30_DATA1                0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN0_MB30_DATA2                0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN0_MB30_DATA3                0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN0_MB30_LENGTH               0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN0_MB30_TIMESTAMP            0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN0_MB30_ID0                  0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN0_MB30_ID1                  0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN0_MB31_DATA0                0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN0_MB31_DATA1                0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN0_MB31_DATA2                0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN0_MB31_DATA3                0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN0_MB31_LENGTH               0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN0_MB31_TIMESTAMP            0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN0_MB31_ID0                  0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN0_MB31_ID1                  0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
-#define CAN1_MC1                       0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define CAN1_MD1                       0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */
-#define CAN1_TRS1                      0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */
-#define CAN1_TRR1                      0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define CAN1_TA1                       0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define CAN1_AA1                       0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define CAN1_RMP1                      0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */
-#define CAN1_RML1                      0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */
-#define CAN1_MBTIF1                    0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN1_MBRIF1                    0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN1_MBIM1                     0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define CAN1_RFH1                      0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define CAN1_OPSS1                     0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN1_MC2                       0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define CAN1_MD2                       0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */
-#define CAN1_TRS2                      0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */
-#define CAN1_TRR2                      0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define CAN1_TA2                       0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define CAN1_AA2                       0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define CAN1_RMP2                      0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */
-#define CAN1_RML2                      0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */
-#define CAN1_MBTIF2                    0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN1_MBRIF2                    0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN1_MBIM2                     0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define CAN1_RFH2                      0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define CAN1_OPSS2                     0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN1_CLOCK                     0xFFC03280 /* CAN Controller 1 Clock Register */
-#define CAN1_TIMING                    0xFFC03284 /* CAN Controller 1 Timing Register */
-#define CAN1_DEBUG                     0xFFC03288 /* CAN Controller 1 Debug Register */
-#define CAN1_STATUS                    0xFFC0328C /* CAN Controller 1 Global Status Register */
-#define CAN1_CEC                       0xFFC03290 /* CAN Controller 1 Error Counter Register */
-#define CAN1_GIS                       0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */
-#define CAN1_GIM                       0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */
-#define CAN1_GIF                       0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */
-#define CAN1_CONTROL                   0xFFC032A0 /* CAN Controller 1 Master Control Register */
-#define CAN1_INTR                      0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */
-#define CAN1_MBTD                      0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define CAN1_EWR                       0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */
-#define CAN1_ESR                       0xFFC032B4 /* CAN Controller 1 Error Status Register */
-#define CAN1_UCCNT                     0xFFC032C4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC                      0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */
-#define CAN1_UCCNF                     0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */
-#define CAN1_AM00L                     0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define CAN1_AM00H                     0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define CAN1_AM01L                     0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define CAN1_AM01H                     0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define CAN1_AM02L                     0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define CAN1_AM02H                     0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define CAN1_AM03L                     0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define CAN1_AM03H                     0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define CAN1_AM04L                     0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define CAN1_AM04H                     0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define CAN1_AM05L                     0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define CAN1_AM05H                     0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define CAN1_AM06L                     0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define CAN1_AM06H                     0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define CAN1_AM07L                     0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define CAN1_AM07H                     0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define CAN1_AM08L                     0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define CAN1_AM08H                     0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define CAN1_AM09L                     0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define CAN1_AM09H                     0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define CAN1_AM10L                     0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define CAN1_AM10H                     0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define CAN1_AM11L                     0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define CAN1_AM11H                     0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define CAN1_AM12L                     0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define CAN1_AM12H                     0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define CAN1_AM13L                     0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define CAN1_AM13H                     0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define CAN1_AM14L                     0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define CAN1_AM14H                     0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define CAN1_AM15L                     0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define CAN1_AM15H                     0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-#define CAN1_AM16L                     0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define CAN1_AM16H                     0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define CAN1_AM17L                     0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define CAN1_AM17H                     0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define CAN1_AM18L                     0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define CAN1_AM18H                     0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define CAN1_AM19L                     0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define CAN1_AM19H                     0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define CAN1_AM20L                     0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define CAN1_AM20H                     0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define CAN1_AM21L                     0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define CAN1_AM21H                     0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define CAN1_AM22L                     0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define CAN1_AM22H                     0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define CAN1_AM23L                     0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define CAN1_AM23H                     0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define CAN1_AM24L                     0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define CAN1_AM24H                     0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define CAN1_AM25L                     0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define CAN1_AM25H                     0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define CAN1_AM26L                     0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define CAN1_AM26H                     0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define CAN1_AM27L                     0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define CAN1_AM27H                     0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define CAN1_AM28L                     0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define CAN1_AM28H                     0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define CAN1_AM29L                     0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define CAN1_AM29H                     0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define CAN1_AM30L                     0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define CAN1_AM30H                     0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define CAN1_AM31L                     0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define CAN1_AM31H                     0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-#define CAN1_MB00_DATA0                0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define CAN1_MB00_DATA1                0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define CAN1_MB00_DATA2                0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define CAN1_MB00_DATA3                0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define CAN1_MB00_LENGTH               0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */
-#define CAN1_MB00_TIMESTAMP            0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define CAN1_MB00_ID0                  0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define CAN1_MB00_ID1                  0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define CAN1_MB01_DATA0                0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define CAN1_MB01_DATA1                0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define CAN1_MB01_DATA2                0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define CAN1_MB01_DATA3                0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define CAN1_MB01_LENGTH               0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */
-#define CAN1_MB01_TIMESTAMP            0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define CAN1_MB01_ID0                  0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define CAN1_MB01_ID1                  0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define CAN1_MB02_DATA0                0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define CAN1_MB02_DATA1                0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define CAN1_MB02_DATA2                0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define CAN1_MB02_DATA3                0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define CAN1_MB02_LENGTH               0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */
-#define CAN1_MB02_TIMESTAMP            0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define CAN1_MB02_ID0                  0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define CAN1_MB02_ID1                  0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define CAN1_MB03_DATA0                0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define CAN1_MB03_DATA1                0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define CAN1_MB03_DATA2                0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define CAN1_MB03_DATA3                0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define CAN1_MB03_LENGTH               0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */
-#define CAN1_MB03_TIMESTAMP            0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define CAN1_MB03_ID0                  0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define CAN1_MB03_ID1                  0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define CAN1_MB04_DATA0                0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define CAN1_MB04_DATA1                0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define CAN1_MB04_DATA2                0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define CAN1_MB04_DATA3                0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define CAN1_MB04_LENGTH               0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */
-#define CAN1_MB04_TIMESTAMP            0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define CAN1_MB04_ID0                  0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define CAN1_MB04_ID1                  0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define CAN1_MB05_DATA0                0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define CAN1_MB05_DATA1                0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define CAN1_MB05_DATA2                0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define CAN1_MB05_DATA3                0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define CAN1_MB05_LENGTH               0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */
-#define CAN1_MB05_TIMESTAMP            0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define CAN1_MB05_ID0                  0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define CAN1_MB05_ID1                  0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define CAN1_MB06_DATA0                0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define CAN1_MB06_DATA1                0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define CAN1_MB06_DATA2                0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define CAN1_MB06_DATA3                0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define CAN1_MB06_LENGTH               0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */
-#define CAN1_MB06_TIMESTAMP            0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define CAN1_MB06_ID0                  0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define CAN1_MB06_ID1                  0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define CAN1_MB07_DATA0                0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define CAN1_MB07_DATA1                0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define CAN1_MB07_DATA2                0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define CAN1_MB07_DATA3                0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define CAN1_MB07_LENGTH               0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */
-#define CAN1_MB07_TIMESTAMP            0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define CAN1_MB07_ID0                  0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define CAN1_MB07_ID1                  0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define CAN1_MB08_DATA0                0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define CAN1_MB08_DATA1                0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define CAN1_MB08_DATA2                0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define CAN1_MB08_DATA3                0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define CAN1_MB08_LENGTH               0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */
-#define CAN1_MB08_TIMESTAMP            0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define CAN1_MB08_ID0                  0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define CAN1_MB08_ID1                  0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define CAN1_MB09_DATA0                0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define CAN1_MB09_DATA1                0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define CAN1_MB09_DATA2                0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define CAN1_MB09_DATA3                0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define CAN1_MB09_LENGTH               0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */
-#define CAN1_MB09_TIMESTAMP            0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define CAN1_MB09_ID0                  0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define CAN1_MB09_ID1                  0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define CAN1_MB10_DATA0                0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define CAN1_MB10_DATA1                0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define CAN1_MB10_DATA2                0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define CAN1_MB10_DATA3                0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define CAN1_MB10_LENGTH               0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */
-#define CAN1_MB10_TIMESTAMP            0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define CAN1_MB10_ID0                  0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define CAN1_MB10_ID1                  0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define CAN1_MB11_DATA0                0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define CAN1_MB11_DATA1                0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define CAN1_MB11_DATA2                0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define CAN1_MB11_DATA3                0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define CAN1_MB11_LENGTH               0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */
-#define CAN1_MB11_TIMESTAMP            0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define CAN1_MB11_ID0                  0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define CAN1_MB11_ID1                  0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define CAN1_MB12_DATA0                0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define CAN1_MB12_DATA1                0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define CAN1_MB12_DATA2                0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define CAN1_MB12_DATA3                0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define CAN1_MB12_LENGTH               0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */
-#define CAN1_MB12_TIMESTAMP            0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define CAN1_MB12_ID0                  0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define CAN1_MB12_ID1                  0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define CAN1_MB13_DATA0                0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define CAN1_MB13_DATA1                0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define CAN1_MB13_DATA2                0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define CAN1_MB13_DATA3                0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define CAN1_MB13_LENGTH               0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */
-#define CAN1_MB13_TIMESTAMP            0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define CAN1_MB13_ID0                  0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define CAN1_MB13_ID1                  0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define CAN1_MB14_DATA0                0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define CAN1_MB14_DATA1                0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define CAN1_MB14_DATA2                0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define CAN1_MB14_DATA3                0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define CAN1_MB14_LENGTH               0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */
-#define CAN1_MB14_TIMESTAMP            0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define CAN1_MB14_ID0                  0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define CAN1_MB14_ID1                  0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define CAN1_MB15_DATA0                0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define CAN1_MB15_DATA1                0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define CAN1_MB15_DATA2                0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define CAN1_MB15_DATA3                0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define CAN1_MB15_LENGTH               0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */
-#define CAN1_MB15_TIMESTAMP            0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define CAN1_MB15_ID0                  0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define CAN1_MB15_ID1                  0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */
-#define CAN1_MB16_DATA0                0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define CAN1_MB16_DATA1                0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define CAN1_MB16_DATA2                0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define CAN1_MB16_DATA3                0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define CAN1_MB16_LENGTH               0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */
-#define CAN1_MB16_TIMESTAMP            0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define CAN1_MB16_ID0                  0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define CAN1_MB16_ID1                  0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define CAN1_MB17_DATA0                0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define CAN1_MB17_DATA1                0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define CAN1_MB17_DATA2                0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define CAN1_MB17_DATA3                0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define CAN1_MB17_LENGTH               0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */
-#define CAN1_MB17_TIMESTAMP            0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define CAN1_MB17_ID0                  0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define CAN1_MB17_ID1                  0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define CAN1_MB18_DATA0                0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define CAN1_MB18_DATA1                0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define CAN1_MB18_DATA2                0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define CAN1_MB18_DATA3                0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define CAN1_MB18_LENGTH               0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */
-#define CAN1_MB18_TIMESTAMP            0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define CAN1_MB18_ID0                  0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define CAN1_MB18_ID1                  0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define CAN1_MB19_DATA0                0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define CAN1_MB19_DATA1                0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define CAN1_MB19_DATA2                0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define CAN1_MB19_DATA3                0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define CAN1_MB19_LENGTH               0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */
-#define CAN1_MB19_TIMESTAMP            0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define CAN1_MB19_ID0                  0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define CAN1_MB19_ID1                  0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define CAN1_MB20_DATA0                0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define CAN1_MB20_DATA1                0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define CAN1_MB20_DATA2                0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define CAN1_MB20_DATA3                0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define CAN1_MB20_LENGTH               0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */
-#define CAN1_MB20_TIMESTAMP            0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define CAN1_MB20_ID0                  0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define CAN1_MB20_ID1                  0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define CAN1_MB21_DATA0                0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define CAN1_MB21_DATA1                0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define CAN1_MB21_DATA2                0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define CAN1_MB21_DATA3                0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define CAN1_MB21_LENGTH               0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */
-#define CAN1_MB21_TIMESTAMP            0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define CAN1_MB21_ID0                  0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define CAN1_MB21_ID1                  0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define CAN1_MB22_DATA0                0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define CAN1_MB22_DATA1                0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define CAN1_MB22_DATA2                0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define CAN1_MB22_DATA3                0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define CAN1_MB22_LENGTH               0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */
-#define CAN1_MB22_TIMESTAMP            0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define CAN1_MB22_ID0                  0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define CAN1_MB22_ID1                  0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define CAN1_MB23_DATA0                0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define CAN1_MB23_DATA1                0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define CAN1_MB23_DATA2                0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define CAN1_MB23_DATA3                0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define CAN1_MB23_LENGTH               0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */
-#define CAN1_MB23_TIMESTAMP            0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define CAN1_MB23_ID0                  0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define CAN1_MB23_ID1                  0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define CAN1_MB24_DATA0                0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define CAN1_MB24_DATA1                0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define CAN1_MB24_DATA2                0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define CAN1_MB24_DATA3                0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define CAN1_MB24_LENGTH               0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */
-#define CAN1_MB24_TIMESTAMP            0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define CAN1_MB24_ID0                  0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define CAN1_MB24_ID1                  0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define CAN1_MB25_DATA0                0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define CAN1_MB25_DATA1                0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define CAN1_MB25_DATA2                0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define CAN1_MB25_DATA3                0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define CAN1_MB25_LENGTH               0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */
-#define CAN1_MB25_TIMESTAMP            0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define CAN1_MB25_ID0                  0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define CAN1_MB25_ID1                  0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define CAN1_MB26_DATA0                0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define CAN1_MB26_DATA1                0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define CAN1_MB26_DATA2                0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define CAN1_MB26_DATA3                0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define CAN1_MB26_LENGTH               0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */
-#define CAN1_MB26_TIMESTAMP            0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define CAN1_MB26_ID0                  0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define CAN1_MB26_ID1                  0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define CAN1_MB27_DATA0                0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define CAN1_MB27_DATA1                0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define CAN1_MB27_DATA2                0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define CAN1_MB27_DATA3                0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define CAN1_MB27_LENGTH               0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */
-#define CAN1_MB27_TIMESTAMP            0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define CAN1_MB27_ID0                  0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define CAN1_MB27_ID1                  0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define CAN1_MB28_DATA0                0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define CAN1_MB28_DATA1                0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define CAN1_MB28_DATA2                0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define CAN1_MB28_DATA3                0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define CAN1_MB28_LENGTH               0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */
-#define CAN1_MB28_TIMESTAMP            0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define CAN1_MB28_ID0                  0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define CAN1_MB28_ID1                  0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define CAN1_MB29_DATA0                0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define CAN1_MB29_DATA1                0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define CAN1_MB29_DATA2                0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define CAN1_MB29_DATA3                0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define CAN1_MB29_LENGTH               0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */
-#define CAN1_MB29_TIMESTAMP            0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define CAN1_MB29_ID0                  0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define CAN1_MB29_ID1                  0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define CAN1_MB30_DATA0                0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define CAN1_MB30_DATA1                0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define CAN1_MB30_DATA2                0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define CAN1_MB30_DATA3                0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define CAN1_MB30_LENGTH               0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */
-#define CAN1_MB30_TIMESTAMP            0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define CAN1_MB30_ID0                  0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define CAN1_MB30_ID1                  0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define CAN1_MB31_DATA0                0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define CAN1_MB31_DATA1                0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define CAN1_MB31_DATA2                0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define CAN1_MB31_DATA3                0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define CAN1_MB31_LENGTH               0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */
-#define CAN1_MB31_TIMESTAMP            0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define CAN1_MB31_ID0                  0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define CAN1_MB31_ID1                  0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */
-#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
-#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
-#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
-#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
-#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
-#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
-#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
-#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
-#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
-#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
-#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
-#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
-#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
-#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
-#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
-#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
-#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
-#define TWI1_CLKDIV                    0xFFC02200 /* Clock Divider Register */
-#define TWI1_CONTROL                   0xFFC02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL                 0xFFC02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT                0xFFC0220C /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR                0xFFC02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL                0xFFC02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT               0xFFC02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR               0xFFC0221C /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT                  0xFFC02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK                  0xFFC02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL                  0xFFC02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT                 0xFFC0222C /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8                 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16                0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8                 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16                0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
-#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
-#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
-#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
-#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
-#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
-#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
-#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
-#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
-#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
-#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
-#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
-#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
-#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
-#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
-#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
-#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
-#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
-#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
-#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
-#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
-#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
-#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
-#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
-#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
-#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
-#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
-#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
-#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
-#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
-#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
-#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
-#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
-#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
-#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
-#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
-#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
-#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
-#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
-#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
-#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
-#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
-#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
-#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
-#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
-#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
-#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
-#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
-#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
-#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
-#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
-#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
-#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
-#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
-#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
-#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
-#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
-#define UART0_LCR                      0xFFC0040C /* Line Control Register */
-#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
-#define UART0_LSR                      0xFFC00414 /* Line Status Register */
-#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
-#define UART0_SCR                      0xFFC0041C /* Scratch Register */
-#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
-#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
-#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
-#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
-#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
-#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
-#define UART1_LCR                      0xFFC0200C /* Line Control Register */
-#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
-#define UART1_LSR                      0xFFC02014 /* Line Status Register */
-#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
-#define UART1_SCR                      0xFFC0201C /* Scratch Register */
-#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
-#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
-#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
-#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
-#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
-#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
-#define UART3_LCR                      0xFFC0310C /* Line Control Register */
-#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
-#define UART3_LSR                      0xFFC03114 /* Line Status Register */
-#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
-#define UART3_SCR                      0xFFC0311C /* Scratch Register */
-#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
-#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
-#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
-
-#endif /* __BFIN_DEF_ADSP_EDN_BF544_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
deleted file mode 100644
index 7e0c043..0000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
+++ /dev/null
@@ -1,2404 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_EDN_BF547_extended__
-#define __BFIN_CDEF_ADSP_EDN_BF547_extended__
-
-#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
-#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
-#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
-#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
-#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
-#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
-#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
-#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
-#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
-#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
-#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
-#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
-#define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
-#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
-#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA()              bfin_read16(PORTA)
-#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB()              bfin_read16(PORTB)
-#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC()              bfin_read16(PORTC)
-#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD()              bfin_read16(PORTD)
-#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE()              bfin_read16(PORTE)
-#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF()              bfin_read16(PORTF)
-#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG()              bfin_read16(PORTG)
-#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH()              bfin_read16(PORTH)
-#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
-#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI()              bfin_read16(PORTI)
-#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
-#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ()              bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
-#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
-#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
-#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
-#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
-#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
-#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
-#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
-#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
-#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
-#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
-#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
-#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
-#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
-#define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
-#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
-#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
-#define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
-#define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
-#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
-#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
-#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_SPI2_CTL()           bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val)       bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG()           bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val)       bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT()          bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val)      bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR()          bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val)      bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR()          bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val)      bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD()          bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val)      bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW()        bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val)    bfin_write16(SPI2_SHADOW, val)
-#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
-#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
-#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
-#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
-#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
-#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
-#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
-#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
-#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define bfin_read_UART2_DLL()          bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val)      bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH()          bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val)      bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL()         bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val)     bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR()          bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val)      bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR()          bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val)      bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR()          bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val)      bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR()          bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val)      bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR()          bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val)      bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET()      bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val)  bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR()    bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_THR()          bfin_read16(UART2_THR)
-#define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
-#define bfin_read_UART2_RBR()          bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val)      bfin_write16(UART2_RBR, val)
-#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
-#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_EDN_BF547_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h
deleted file mode 100644
index ef9111f..0000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h
+++ /dev/null
@@ -1,1209 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_EDN_BF547_extended__
-#define __BFIN_DEF_ADSP_EDN_BF547_extended__
-
-#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
-#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
-#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
-#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
-#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
-#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
-#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
-#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
-#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
-#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
-#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
-#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
-#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
-#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
-#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
-#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
-#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
-#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
-#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
-#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
-#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
-#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
-#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
-#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
-#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
-#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
-#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
-#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
-#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
-#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
-#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
-#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
-#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
-#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
-#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
-#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
-#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
-#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
-#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
-#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
-#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
-#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
-#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
-#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
-#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
-#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
-#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
-#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
-#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
-#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
-#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
-#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
-#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
-#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
-#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
-#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
-#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
-#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
-#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
-#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
-#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
-#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
-#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
-#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
-#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
-#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
-#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
-#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
-#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
-#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
-#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
-#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
-#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
-#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
-#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
-#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
-#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
-#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
-#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
-#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
-#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
-#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
-#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
-#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
-#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
-#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
-#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
-#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
-#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
-#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
-#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
-#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
-#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
-#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
-#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
-#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
-#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
-#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
-#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
-#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
-#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
-#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
-#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
-#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
-#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
-#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
-#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
-#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
-#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
-#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
-#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
-#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
-#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
-#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
-#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
-#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
-#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
-#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
-#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
-#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
-#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
-#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
-#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
-#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
-#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
-#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
-#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
-#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
-#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
-#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
-#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
-#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
-#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
-#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
-#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
-#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
-#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
-#define PIXC_CTL                       0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL                       0xFFC04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF                       0xFFC04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART                   0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND                     0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART                   0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND                     0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP                   0xFFC0441C /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART                   0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND                     0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART                   0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND                     0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP                   0xFFC04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT                  0xFFC0443C /* Overlay interrupt configuration/status */
-#define PIXC_RYCON                     0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON                     0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON                     0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS                    0xFFC0444C /* Bias values for the color space conversion matrix */
-#define PIXC_TC                        0xFFC04450 /* Holds the transparent color value */
-#define HOST_CONTROL                   0xFFC03A00 /* HOSTDP Control Register */
-#define HOST_STATUS                    0xFFC03A04 /* HOSTDP Status Register */
-#define HOST_TIMEOUT                   0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
-#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
-#define PORTA                          0xFFC014C4 /* GPIO Data Register */
-#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
-#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
-#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
-#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
-#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
-#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
-#define PORTB                          0xFFC014E4 /* GPIO Data Register */
-#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
-#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
-#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
-#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
-#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
-#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
-#define PORTC                          0xFFC01504 /* GPIO Data Register */
-#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
-#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
-#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
-#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
-#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
-#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
-#define PORTD                          0xFFC01524 /* GPIO Data Register */
-#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
-#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
-#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
-#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
-#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
-#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
-#define PORTE                          0xFFC01544 /* GPIO Data Register */
-#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
-#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
-#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
-#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
-#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
-#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
-#define PORTF                          0xFFC01564 /* GPIO Data Register */
-#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
-#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
-#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
-#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
-#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
-#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
-#define PORTG                          0xFFC01584 /* GPIO Data Register */
-#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
-#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
-#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
-#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
-#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
-#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
-#define PORTH                          0xFFC015A4 /* GPIO Data Register */
-#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
-#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
-#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
-#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
-#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
-#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
-#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
-#define PORTI                          0xFFC015C4 /* GPIO Data Register */
-#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
-#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
-#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
-#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
-#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
-#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
-#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
-#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
-#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
-#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
-#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
-#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
-#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
-#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
-#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
-#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
-#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
-#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
-#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
-#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
-#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
-#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
-#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
-#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
-#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
-#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
-#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
-#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
-#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
-#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
-#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
-#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
-#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
-#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
-#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
-#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
-#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
-#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
-#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
-#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
-#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
-#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
-#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
-#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
-#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
-#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
-#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
-#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
-#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
-#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
-#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
-#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
-#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
-#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
-#define TIMER8_CONFIG                  0xFFC00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER                 0xFFC00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD                  0xFFC00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH                   0xFFC0060C /* Timer 8 Width Register */
-#define TIMER9_CONFIG                  0xFFC00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER                 0xFFC00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD                  0xFFC00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH                   0xFFC0061C /* Timer 9 Width Register */
-#define TIMER10_CONFIG                 0xFFC00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER                0xFFC00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD                 0xFFC00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH                  0xFFC0062C /* Timer 10 Width Register */
-#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
-#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
-#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
-#define TIMER_ENABLE1                  0xFFC00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1                 0xFFC00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1                  0xFFC00648 /* Timer Group of 3 Status Register */
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
-#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
-#define CNT_STATUS                     0xFFC04208 /* Status Register  */
-#define CNT_COMMAND                    0xFFC0420C /* Command Register */
-#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
-#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
-#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
-#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
-#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
-#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
-#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
-#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
-#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
-#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
-#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
-#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
-#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define KPAD_CTL                       0xFFC04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE                  0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL                      0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL                    0xFFC0410C /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT                      0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL                  0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
-#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
-#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
-#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
-#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
-#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
-#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
-#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
-#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
-#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
-#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
-#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
-#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
-#define SDH_STATUS                     0xFFC03934 /* SDH Status */
-#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
-#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
-#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
-#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
-#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
-#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
-#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
-#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
-#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
-#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
-#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
-#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
-#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
-#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
-#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
-#define ATAPI_CONTROL                  0xFFC03800 /* ATAPI Control Register */
-#define ATAPI_STATUS                   0xFFC03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR                 0xFFC03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF                0xFFC0380C /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF                0xFFC03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK                 0xFFC03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS               0xFFC03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN                 0xFFC0381C /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS              0xFFC03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE                 0xFFC03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE                0xFFC03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT               0xFFC0382C /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT               0xFFC03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT             0xFFC03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT           0xFFC03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0                0xFFC03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0                0xFFC03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1                0xFFC03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0              0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1              0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2              0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0              0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1              0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2              0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3              0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
-#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
-#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
-#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
-#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
-#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
-#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
-#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
-#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
-#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
-#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
-#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
-#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
-#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
-#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
-#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
-#define EPPI0_STATUS                   0xFFC01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT                   0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY                   0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT                   0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY                   0xFFC01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME                    0xFFC01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE                     0xFFC01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV                   0xFFC0101C /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL                  0xFFC01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL                 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL                0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB                 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF                0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP                     0xFFC01034 /* EPPI0 Clipping Register */
-#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
-#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
-#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
-#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
-#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
-#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
-#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
-#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
-#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
-#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
-#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
-#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
-#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
-#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
-#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
-#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
-#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
-#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
-#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
-#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
-#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
-#define SPI2_CTL                       0xFFC02400 /* SPI2 Control Register */
-#define SPI2_FLG                       0xFFC02404 /* SPI2 Flag Register */
-#define SPI2_STAT                      0xFFC02408 /* SPI2 Status Register */
-#define SPI2_TDBR                      0xFFC0240C /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR                      0xFFC02410 /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD                      0xFFC02414 /* SPI2 Baud Rate Register */
-#define SPI2_SHADOW                    0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */
-#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
-#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
-#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
-#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
-#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
-#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
-#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
-#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
-#define TWI1_CLKDIV                    0xFFC02200 /* Clock Divider Register */
-#define TWI1_CONTROL                   0xFFC02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL                 0xFFC02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT                0xFFC0220C /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR                0xFFC02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL                0xFFC02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT               0xFFC02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR               0xFFC0221C /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT                  0xFFC02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK                  0xFFC02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL                  0xFFC02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT                 0xFFC0222C /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8                 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16                0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8                 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16                0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
-#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */
-#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */
-#define SPORT0_TX                      0xFFC00810 /* SPORT0 Transmit Data Register */
-#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Receive Configuration 1 Register */
-#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Receive Configuration 2 Register */
-#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */
-#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */
-#define SPORT0_RX                      0xFFC00818 /* SPORT0 Receive Data Register */
-#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */
-#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */
-#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */
-#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */
-#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */
-#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */
-#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */
-#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
-#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
-#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
-#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
-#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
-#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
-#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
-#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
-#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
-#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
-#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
-#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
-#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
-#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
-#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
-#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
-#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
-#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
-#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
-#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
-#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
-#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
-#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
-#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
-#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
-#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
-#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
-#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
-#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
-#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
-#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
-#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
-#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
-#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
-#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
-#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
-#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
-#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
-#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
-#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
-#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
-#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
-#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
-#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
-#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
-#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
-#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
-#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
-#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
-#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
-#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
-#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
-#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
-#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
-#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
-#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
-#define UART0_LCR                      0xFFC0040C /* Line Control Register */
-#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
-#define UART0_LSR                      0xFFC00414 /* Line Status Register */
-#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
-#define UART0_SCR                      0xFFC0041C /* Scratch Register */
-#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
-#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
-#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
-#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
-#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
-#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
-#define UART1_LCR                      0xFFC0200C /* Line Control Register */
-#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
-#define UART1_LSR                      0xFFC02014 /* Line Status Register */
-#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
-#define UART1_SCR                      0xFFC0201C /* Scratch Register */
-#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
-#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
-#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
-#define UART2_DLL                      0xFFC02100 /* Divisor Latch Low Byte */
-#define UART2_DLH                      0xFFC02104 /* Divisor Latch High Byte */
-#define UART2_GCTL                     0xFFC02108 /* Global Control Register */
-#define UART2_LCR                      0xFFC0210C /* Line Control Register */
-#define UART2_MCR                      0xFFC02110 /* Modem Control Register */
-#define UART2_LSR                      0xFFC02114 /* Line Status Register */
-#define UART2_MSR                      0xFFC02118 /* Modem Status Register */
-#define UART2_SCR                      0xFFC0211C /* Scratch Register */
-#define UART2_IER_SET                  0xFFC02120 /* Interrupt Enable Register Set */
-#define UART2_IER_CLEAR                0xFFC02124 /* Interrupt Enable Register Clear */
-#define UART2_THR                      0xFFC02128 /* Transmit Hold Register */
-#define UART2_RBR                      0xFFC0212C /* Receive Buffer Register */
-#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
-#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
-#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
-#define UART3_LCR                      0xFFC0310C /* Line Control Register */
-#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
-#define UART3_LSR                      0xFFC03114 /* Line Status Register */
-#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
-#define UART3_SCR                      0xFFC0311C /* Scratch Register */
-#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
-#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
-#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
-#define USB_FADDR                      0xFFC03C00 /* Function address register */
-#define USB_POWER                      0xFFC03C04 /* Power management register */
-#define USB_INTRTX                     0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX                     0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE                    0xFFC03C10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE                    0xFFC03C14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB                    0xFFC03C18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE                   0xFFC03C1C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME                      0xFFC03C20 /* USB frame number */
-#define USB_INDEX                      0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE                   0xFFC03C28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR                   0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL                 0xFFC03C30 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET              0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0                       0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR                      0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET              0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR                      0xFFC03C4C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0                     0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT                    0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE                     0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0                  0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL                 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE                     0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL                 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT                    0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO                   0xFFC03C80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO                   0xFFC03C88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO                   0xFFC03C90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO                   0xFFC03C98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO                   0xFFC03CA0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO                   0xFFC03CA8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO                   0xFFC03CB0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO                   0xFFC03CB8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL                0xFFC03D00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ               0xFFC03D04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK              0xFFC03D08 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO                   0xFFC03D48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN                      0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1                    0xFFC03D50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1                    0xFFC03D54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1                    0xFFC03D58 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL                 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB                 0xFFC03DE4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2                0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST                   0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL                0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV                 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP              0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR               0xFFC03E04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP              0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR               0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT             0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE              0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL          0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE              0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL          0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT             0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP              0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR               0xFFC03E44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP              0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR               0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT             0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE              0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL          0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE              0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL          0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT             0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP              0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR               0xFFC03E84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP              0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR               0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT             0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE              0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL          0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE              0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL          0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT             0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP              0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR               0xFFC03EC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP              0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR               0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT             0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE              0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL          0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE              0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL          0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT             0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP              0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR               0xFFC03F04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP              0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR               0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT             0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE              0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL          0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE              0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL          0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT             0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP              0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR               0xFFC03F44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP              0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR               0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT             0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE              0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL          0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE              0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL          0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT             0xFFC03F68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP              0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR               0xFFC03F84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP              0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR               0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT             0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE              0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL          0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE              0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL          0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT             0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP              0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR               0xFFC03FC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP              0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR               0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT             0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE              0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL          0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE              0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL          0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT             0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT              0xFFC04000 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL               0xFFC04004 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW               0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH              0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW              0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH             0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL               0xFFC04024 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW               0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH              0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW              0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH             0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL               0xFFC04044 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW               0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH              0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW              0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH             0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL               0xFFC04064 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW               0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH              0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW              0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH             0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL               0xFFC04084 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW               0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH              0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW              0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH             0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL               0xFFC040A4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW               0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH              0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW              0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH             0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL               0xFFC040C4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW               0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH              0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW              0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH             0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL               0xFFC040E4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW               0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH              0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW              0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH             0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_EDN_BF547_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
deleted file mode 100644
index dfb3276..0000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
+++ /dev/null
@@ -1,3852 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_EDN_BF548_extended__
-#define __BFIN_CDEF_ADSP_EDN_BF548_extended__
-
-#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
-#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
-#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
-#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
-#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
-#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
-#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
-#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
-#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
-#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
-#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
-#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
-#define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
-#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
-#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA()              bfin_read16(PORTA)
-#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB()              bfin_read16(PORTB)
-#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC()              bfin_read16(PORTC)
-#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD()              bfin_read16(PORTD)
-#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE()              bfin_read16(PORTE)
-#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF()              bfin_read16(PORTF)
-#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG()              bfin_read16(PORTG)
-#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH()              bfin_read16(PORTH)
-#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
-#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI()              bfin_read16(PORTI)
-#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
-#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ()              bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
-#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
-#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
-#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
-#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
-#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
-#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
-#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
-#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
-#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
-#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
-#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
-#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
-#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
-#define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
-#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
-#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
-#define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
-#define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
-#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
-#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
-#define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
-#define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
-#define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
-#define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
-#define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
-#define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
-#define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
-#define bfin_read_CAN1_MC1()           bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val)       bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1()           bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val)       bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1()          bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val)      bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1()          bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val)      bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1()           bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val)       bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1()           bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val)       bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1()          bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val)      bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1()          bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val)      bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1()        bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val)    bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1()        bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val)    bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1()         bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val)     bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1()          bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val)      bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1()         bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val)     bfin_write16(CAN1_OPSS1, val)
-#define bfin_read_CAN1_MC2()           bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val)       bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2()           bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val)       bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2()          bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val)      bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2()          bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val)      bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2()           bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val)       bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2()           bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val)       bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2()          bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val)      bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2()          bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val)      bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2()        bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val)    bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2()        bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val)    bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2()         bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val)     bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2()          bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val)      bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2()         bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val)     bfin_write16(CAN1_OPSS2, val)
-#define bfin_read_CAN1_CLOCK()         bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val)     bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING()        bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val)    bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG()         bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val)     bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS()        bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val)    bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC()           bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val)       bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS()           bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val)       bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM()           bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val)       bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF()           bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val)       bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL()       bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val)   bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR()          bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val)      bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD()          bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val)      bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR()           bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val)       bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR()           bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val)       bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT()         bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val)     bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC()          bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val)      bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF()         bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val)     bfin_write16(CAN1_UCCNF, val)
-#define bfin_read_CAN1_AM00L()         bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val)     bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H()         bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val)     bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L()         bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val)     bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H()         bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val)     bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L()         bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val)     bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H()         bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val)     bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L()         bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val)     bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H()         bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val)     bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L()         bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val)     bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H()         bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val)     bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L()         bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val)     bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H()         bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val)     bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L()         bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val)     bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H()         bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val)     bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L()         bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val)     bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H()         bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val)     bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L()         bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val)     bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H()         bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val)     bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L()         bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val)     bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H()         bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val)     bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L()         bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val)     bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H()         bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val)     bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L()         bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val)     bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H()         bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val)     bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L()         bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val)     bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H()         bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val)     bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L()         bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val)     bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H()         bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val)     bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L()         bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val)     bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H()         bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val)     bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L()         bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val)     bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H()         bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val)     bfin_write16(CAN1_AM15H, val)
-#define bfin_read_CAN1_AM16L()         bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val)     bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H()         bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val)     bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L()         bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val)     bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H()         bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val)     bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L()         bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val)     bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H()         bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val)     bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L()         bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val)     bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H()         bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val)     bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L()         bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val)     bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H()         bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val)     bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L()         bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val)     bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H()         bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val)     bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L()         bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val)     bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H()         bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val)     bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L()         bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val)     bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H()         bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val)     bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L()         bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val)     bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H()         bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val)     bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L()         bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val)     bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H()         bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val)     bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L()         bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val)     bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H()         bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val)     bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L()         bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val)     bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H()         bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val)     bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L()         bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val)     bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H()         bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val)     bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L()         bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val)     bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H()         bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val)     bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L()         bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val)     bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H()         bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val)     bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L()         bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val)     bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H()         bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val)     bfin_write16(CAN1_AM31H, val)
-#define bfin_read_CAN1_MB00_DATA0()    bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1()    bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2()    bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3()    bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH()   bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0()      bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val)  bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1()      bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val)  bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0()    bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1()    bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2()    bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3()    bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH()   bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0()      bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val)  bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1()      bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val)  bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0()    bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1()    bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2()    bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3()    bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH()   bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0()      bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val)  bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1()      bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val)  bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0()    bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1()    bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2()    bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3()    bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH()   bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0()      bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val)  bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1()      bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val)  bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0()    bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1()    bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2()    bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3()    bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH()   bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0()      bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val)  bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1()      bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val)  bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0()    bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1()    bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2()    bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3()    bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH()   bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0()      bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val)  bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1()      bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val)  bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0()    bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1()    bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2()    bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3()    bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH()   bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0()      bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val)  bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1()      bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val)  bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0()    bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1()    bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2()    bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3()    bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH()   bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0()      bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val)  bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1()      bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val)  bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0()    bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1()    bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2()    bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3()    bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH()   bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0()      bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val)  bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1()      bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val)  bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0()    bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1()    bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2()    bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3()    bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH()   bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0()      bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val)  bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1()      bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val)  bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0()    bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1()    bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2()    bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3()    bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH()   bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0()      bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val)  bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1()      bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val)  bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0()    bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1()    bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2()    bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3()    bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH()   bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0()      bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val)  bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1()      bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val)  bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0()    bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1()    bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2()    bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3()    bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH()   bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0()      bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val)  bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1()      bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val)  bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0()    bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1()    bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2()    bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3()    bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH()   bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0()      bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val)  bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1()      bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val)  bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0()    bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1()    bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2()    bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3()    bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH()   bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0()      bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val)  bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1()      bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val)  bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0()    bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1()    bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2()    bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3()    bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH()   bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0()      bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val)  bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1()      bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val)  bfin_write16(CAN1_MB15_ID1, val)
-#define bfin_read_CAN1_MB16_DATA0()    bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1()    bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2()    bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3()    bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH()   bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0()      bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val)  bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1()      bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val)  bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0()    bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1()    bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2()    bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3()    bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH()   bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0()      bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val)  bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1()      bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val)  bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0()    bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1()    bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2()    bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3()    bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH()   bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0()      bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val)  bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1()      bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val)  bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0()    bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1()    bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2()    bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3()    bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH()   bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0()      bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val)  bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1()      bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val)  bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0()    bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1()    bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2()    bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3()    bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH()   bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0()      bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val)  bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1()      bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val)  bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0()    bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1()    bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2()    bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3()    bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH()   bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0()      bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val)  bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1()      bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val)  bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0()    bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1()    bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2()    bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3()    bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH()   bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0()      bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val)  bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1()      bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val)  bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0()    bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1()    bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2()    bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3()    bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH()   bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0()      bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val)  bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1()      bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val)  bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0()    bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1()    bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2()    bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3()    bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH()   bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0()      bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val)  bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1()      bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val)  bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0()    bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1()    bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2()    bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3()    bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH()   bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0()      bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val)  bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1()      bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val)  bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0()    bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1()    bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2()    bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3()    bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH()   bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0()      bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val)  bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1()      bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val)  bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0()    bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1()    bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2()    bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3()    bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH()   bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0()      bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val)  bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1()      bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val)  bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0()    bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1()    bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2()    bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3()    bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH()   bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0()      bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val)  bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1()      bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val)  bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0()    bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1()    bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2()    bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3()    bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH()   bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0()      bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val)  bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1()      bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val)  bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0()    bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1()    bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2()    bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3()    bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH()   bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0()      bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val)  bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1()      bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val)  bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0()    bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1()    bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2()    bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3()    bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH()   bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0()      bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val)  bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1()      bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val)  bfin_write16(CAN1_MB31_ID1, val)
-#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_SPI2_CTL()           bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val)       bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG()           bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val)       bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT()          bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val)      bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR()          bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val)      bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR()          bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val)      bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD()          bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val)      bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW()        bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val)    bfin_write16(SPI2_SHADOW, val)
-#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
-#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
-#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
-#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
-#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
-#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
-#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
-#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
-#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define bfin_read_UART2_DLL()          bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val)      bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH()          bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val)      bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL()         bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val)     bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR()          bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val)      bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR()          bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val)      bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR()          bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val)      bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR()          bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val)      bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR()          bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val)      bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET()      bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val)  bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR()    bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_THR()          bfin_read16(UART2_THR)
-#define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
-#define bfin_read_UART2_RBR()          bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val)      bfin_write16(UART2_RBR, val)
-#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
-#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_EDN_BF548_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h
deleted file mode 100644
index 1be6688..0000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h
+++ /dev/null
@@ -1,1933 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_EDN_BF548_extended__
-#define __BFIN_DEF_ADSP_EDN_BF548_extended__
-
-#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
-#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
-#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
-#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
-#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
-#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
-#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
-#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
-#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
-#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
-#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
-#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
-#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
-#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
-#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
-#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
-#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
-#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
-#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
-#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
-#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
-#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
-#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
-#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
-#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
-#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
-#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
-#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
-#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
-#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
-#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
-#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
-#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
-#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
-#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
-#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
-#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
-#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
-#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
-#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
-#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
-#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
-#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
-#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
-#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
-#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
-#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
-#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
-#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
-#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
-#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
-#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
-#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
-#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
-#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
-#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
-#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
-#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
-#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
-#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
-#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
-#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
-#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
-#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
-#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
-#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
-#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
-#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
-#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
-#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
-#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
-#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
-#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
-#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
-#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
-#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
-#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
-#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
-#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
-#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
-#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
-#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
-#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
-#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
-#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
-#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
-#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
-#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
-#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
-#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
-#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
-#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
-#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
-#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
-#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
-#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
-#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
-#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
-#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
-#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
-#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
-#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
-#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
-#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
-#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
-#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
-#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
-#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
-#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
-#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
-#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
-#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
-#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
-#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
-#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
-#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
-#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
-#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
-#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
-#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
-#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
-#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
-#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
-#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
-#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
-#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
-#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
-#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
-#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
-#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
-#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
-#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
-#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
-#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
-#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
-#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
-#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
-#define PIXC_CTL                       0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL                       0xFFC04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF                       0xFFC04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART                   0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND                     0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART                   0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND                     0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP                   0xFFC0441C /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART                   0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND                     0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART                   0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND                     0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP                   0xFFC04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT                  0xFFC0443C /* Overlay interrupt configuration/status */
-#define PIXC_RYCON                     0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON                     0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON                     0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS                    0xFFC0444C /* Bias values for the color space conversion matrix */
-#define PIXC_TC                        0xFFC04450 /* Holds the transparent color value */
-#define HOST_CONTROL                   0xFFC03A00 /* HOSTDP Control Register */
-#define HOST_STATUS                    0xFFC03A04 /* HOSTDP Status Register */
-#define HOST_TIMEOUT                   0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
-#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
-#define PORTA                          0xFFC014C4 /* GPIO Data Register */
-#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
-#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
-#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
-#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
-#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
-#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
-#define PORTB                          0xFFC014E4 /* GPIO Data Register */
-#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
-#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
-#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
-#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
-#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
-#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
-#define PORTC                          0xFFC01504 /* GPIO Data Register */
-#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
-#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
-#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
-#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
-#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
-#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
-#define PORTD                          0xFFC01524 /* GPIO Data Register */
-#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
-#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
-#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
-#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
-#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
-#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
-#define PORTE                          0xFFC01544 /* GPIO Data Register */
-#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
-#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
-#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
-#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
-#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
-#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
-#define PORTF                          0xFFC01564 /* GPIO Data Register */
-#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
-#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
-#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
-#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
-#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
-#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
-#define PORTG                          0xFFC01584 /* GPIO Data Register */
-#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
-#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
-#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
-#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
-#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
-#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
-#define PORTH                          0xFFC015A4 /* GPIO Data Register */
-#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
-#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
-#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
-#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
-#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
-#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
-#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
-#define PORTI                          0xFFC015C4 /* GPIO Data Register */
-#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
-#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
-#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
-#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
-#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
-#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
-#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
-#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
-#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
-#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
-#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
-#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
-#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
-#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
-#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
-#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
-#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
-#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
-#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
-#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
-#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
-#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
-#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
-#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
-#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
-#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
-#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
-#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
-#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
-#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
-#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
-#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
-#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
-#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
-#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
-#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
-#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
-#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
-#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
-#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
-#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
-#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
-#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
-#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
-#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
-#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
-#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
-#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
-#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
-#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
-#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
-#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
-#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
-#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
-#define TIMER8_CONFIG                  0xFFC00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER                 0xFFC00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD                  0xFFC00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH                   0xFFC0060C /* Timer 8 Width Register */
-#define TIMER9_CONFIG                  0xFFC00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER                 0xFFC00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD                  0xFFC00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH                   0xFFC0061C /* Timer 9 Width Register */
-#define TIMER10_CONFIG                 0xFFC00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER                0xFFC00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD                 0xFFC00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH                  0xFFC0062C /* Timer 10 Width Register */
-#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
-#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
-#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
-#define TIMER_ENABLE1                  0xFFC00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1                 0xFFC00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1                  0xFFC00648 /* Timer Group of 3 Status Register */
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
-#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
-#define CNT_STATUS                     0xFFC04208 /* Status Register  */
-#define CNT_COMMAND                    0xFFC0420C /* Command Register */
-#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
-#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
-#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
-#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
-#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
-#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
-#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
-#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
-#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
-#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
-#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
-#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
-#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define KPAD_CTL                       0xFFC04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE                  0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL                      0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL                    0xFFC0410C /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT                      0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL                  0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
-#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
-#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
-#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
-#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
-#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
-#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
-#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
-#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
-#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
-#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
-#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
-#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
-#define SDH_STATUS                     0xFFC03934 /* SDH Status */
-#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
-#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
-#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
-#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
-#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
-#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
-#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
-#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
-#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
-#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
-#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
-#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
-#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
-#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
-#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
-#define ATAPI_CONTROL                  0xFFC03800 /* ATAPI Control Register */
-#define ATAPI_STATUS                   0xFFC03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR                 0xFFC03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF                0xFFC0380C /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF                0xFFC03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK                 0xFFC03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS               0xFFC03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN                 0xFFC0381C /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS              0xFFC03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE                 0xFFC03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE                0xFFC03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT               0xFFC0382C /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT               0xFFC03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT             0xFFC03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT           0xFFC03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0                0xFFC03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0                0xFFC03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1                0xFFC03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0              0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1              0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2              0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0              0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1              0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2              0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3              0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
-#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
-#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
-#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
-#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
-#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
-#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
-#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
-#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
-#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
-#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
-#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
-#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
-#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
-#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
-#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
-#define EPPI0_STATUS                   0xFFC01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT                   0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY                   0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT                   0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY                   0xFFC01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME                    0xFFC01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE                     0xFFC01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV                   0xFFC0101C /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL                  0xFFC01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL                 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL                0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB                 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF                0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP                     0xFFC01034 /* EPPI0 Clipping Register */
-#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
-#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
-#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
-#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
-#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
-#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
-#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
-#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
-#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
-#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
-#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
-#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
-#define CAN0_MC1                       0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN0_MD1                       0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN0_TRS1                      0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN0_TRR1                      0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN0_TA1                       0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN0_AA1                       0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1                      0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN0_RML1                      0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1                    0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1                    0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1                     0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1                      0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN0_OPSS1                     0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN0_MC2                       0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN0_MD2                       0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN0_TRS2                      0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN0_TRR2                      0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN0_TA2                       0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN0_AA2                       0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2                      0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN0_RML2                      0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2                    0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2                    0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2                     0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2                      0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN0_OPSS2                     0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN0_CLOCK                     0xFFC02A80 /* CAN Controller 0 Clock Register */
-#define CAN0_TIMING                    0xFFC02A84 /* CAN Controller 0 Timing Register */
-#define CAN0_DEBUG                     0xFFC02A88 /* CAN Controller 0 Debug Register */
-#define CAN0_STATUS                    0xFFC02A8C /* CAN Controller 0 Global Status Register */
-#define CAN0_CEC                       0xFFC02A90 /* CAN Controller 0 Error Counter Register */
-#define CAN0_GIS                       0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN0_GIM                       0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN0_GIF                       0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN0_CONTROL                   0xFFC02AA0 /* CAN Controller 0 Master Control Register */
-#define CAN0_INTR                      0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN0_MBTD                      0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN0_EWR                       0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN0_ESR                       0xFFC02AB4 /* CAN Controller 0 Error Status Register */
-#define CAN0_UCCNT                     0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
-#define CAN0_UCRC                      0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN0_UCCNF                     0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
-#define CAN0_AM00L                     0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN0_AM00H                     0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN0_AM01L                     0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN0_AM01H                     0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN0_AM02L                     0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN0_AM02H                     0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN0_AM03L                     0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN0_AM03H                     0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN0_AM04L                     0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN0_AM04H                     0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN0_AM05L                     0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN0_AM05H                     0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN0_AM06L                     0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN0_AM06H                     0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN0_AM07L                     0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN0_AM07H                     0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN0_AM08L                     0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN0_AM08H                     0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN0_AM09L                     0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN0_AM09H                     0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN0_AM10L                     0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN0_AM10H                     0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN0_AM11L                     0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN0_AM11H                     0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN0_AM12L                     0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN0_AM12H                     0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN0_AM13L                     0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN0_AM13H                     0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN0_AM14L                     0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN0_AM14H                     0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN0_AM15L                     0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN0_AM15H                     0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-#define CAN0_AM16L                     0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN0_AM16H                     0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN0_AM17L                     0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN0_AM17H                     0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN0_AM18L                     0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN0_AM18H                     0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN0_AM19L                     0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN0_AM19H                     0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN0_AM20L                     0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN0_AM20H                     0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN0_AM21L                     0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN0_AM21H                     0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN0_AM22L                     0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN0_AM22H                     0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN0_AM23L                     0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN0_AM23H                     0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN0_AM24L                     0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN0_AM24H                     0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN0_AM25L                     0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN0_AM25H                     0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN0_AM26L                     0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN0_AM26H                     0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN0_AM27L                     0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN0_AM27H                     0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN0_AM28L                     0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN0_AM28H                     0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN0_AM29L                     0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN0_AM29H                     0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN0_AM30L                     0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN0_AM30H                     0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN0_AM31L                     0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN0_AM31H                     0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-#define CAN0_MB00_DATA0                0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN0_MB00_DATA1                0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN0_MB00_DATA2                0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN0_MB00_DATA3                0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN0_MB00_LENGTH               0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN0_MB00_TIMESTAMP            0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN0_MB00_ID0                  0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN0_MB00_ID1                  0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN0_MB01_DATA0                0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN0_MB01_DATA1                0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN0_MB01_DATA2                0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN0_MB01_DATA3                0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN0_MB01_LENGTH               0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN0_MB01_TIMESTAMP            0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN0_MB01_ID0                  0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN0_MB01_ID1                  0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN0_MB02_DATA0                0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN0_MB02_DATA1                0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN0_MB02_DATA2                0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN0_MB02_DATA3                0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN0_MB02_LENGTH               0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN0_MB02_TIMESTAMP            0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN0_MB02_ID0                  0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN0_MB02_ID1                  0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN0_MB03_DATA0                0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN0_MB03_DATA1                0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN0_MB03_DATA2                0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN0_MB03_DATA3                0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN0_MB03_LENGTH               0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN0_MB03_TIMESTAMP            0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN0_MB03_ID0                  0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN0_MB03_ID1                  0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN0_MB04_DATA0                0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN0_MB04_DATA1                0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN0_MB04_DATA2                0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN0_MB04_DATA3                0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN0_MB04_LENGTH               0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN0_MB04_TIMESTAMP            0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN0_MB04_ID0                  0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN0_MB04_ID1                  0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN0_MB05_DATA0                0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN0_MB05_DATA1                0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN0_MB05_DATA2                0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN0_MB05_DATA3                0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN0_MB05_LENGTH               0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN0_MB05_TIMESTAMP            0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN0_MB05_ID0                  0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN0_MB05_ID1                  0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN0_MB06_DATA0                0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN0_MB06_DATA1                0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN0_MB06_DATA2                0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN0_MB06_DATA3                0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN0_MB06_LENGTH               0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN0_MB06_TIMESTAMP            0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN0_MB06_ID0                  0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN0_MB06_ID1                  0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN0_MB07_DATA0                0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN0_MB07_DATA1                0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN0_MB07_DATA2                0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN0_MB07_DATA3                0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN0_MB07_LENGTH               0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN0_MB07_TIMESTAMP            0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN0_MB07_ID0                  0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN0_MB07_ID1                  0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN0_MB08_DATA0                0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN0_MB08_DATA1                0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN0_MB08_DATA2                0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN0_MB08_DATA3                0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN0_MB08_LENGTH               0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN0_MB08_TIMESTAMP            0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN0_MB08_ID0                  0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN0_MB08_ID1                  0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN0_MB09_DATA0                0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN0_MB09_DATA1                0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN0_MB09_DATA2                0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN0_MB09_DATA3                0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN0_MB09_LENGTH               0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN0_MB09_TIMESTAMP            0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN0_MB09_ID0                  0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN0_MB09_ID1                  0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN0_MB10_DATA0                0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN0_MB10_DATA1                0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN0_MB10_DATA2                0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN0_MB10_DATA3                0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN0_MB10_LENGTH               0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN0_MB10_TIMESTAMP            0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN0_MB10_ID0                  0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN0_MB10_ID1                  0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN0_MB11_DATA0                0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN0_MB11_DATA1                0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN0_MB11_DATA2                0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN0_MB11_DATA3                0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN0_MB11_LENGTH               0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN0_MB11_TIMESTAMP            0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN0_MB11_ID0                  0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN0_MB11_ID1                  0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN0_MB12_DATA0                0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN0_MB12_DATA1                0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN0_MB12_DATA2                0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN0_MB12_DATA3                0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN0_MB12_LENGTH               0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN0_MB12_TIMESTAMP            0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN0_MB12_ID0                  0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN0_MB12_ID1                  0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN0_MB13_DATA0                0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN0_MB13_DATA1                0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN0_MB13_DATA2                0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN0_MB13_DATA3                0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN0_MB13_LENGTH               0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN0_MB13_TIMESTAMP            0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN0_MB13_ID0                  0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN0_MB13_ID1                  0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN0_MB14_DATA0                0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN0_MB14_DATA1                0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN0_MB14_DATA2                0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN0_MB14_DATA3                0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN0_MB14_LENGTH               0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN0_MB14_TIMESTAMP            0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN0_MB14_ID0                  0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN0_MB14_ID1                  0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN0_MB15_DATA0                0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN0_MB15_DATA1                0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN0_MB15_DATA2                0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN0_MB15_DATA3                0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN0_MB15_LENGTH               0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN0_MB15_TIMESTAMP            0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN0_MB15_ID0                  0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN0_MB15_ID1                  0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
-#define CAN0_MB16_DATA0                0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN0_MB16_DATA1                0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN0_MB16_DATA2                0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN0_MB16_DATA3                0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN0_MB16_LENGTH               0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN0_MB16_TIMESTAMP            0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN0_MB16_ID0                  0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN0_MB16_ID1                  0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN0_MB17_DATA0                0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN0_MB17_DATA1                0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN0_MB17_DATA2                0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN0_MB17_DATA3                0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN0_MB17_LENGTH               0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN0_MB17_TIMESTAMP            0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN0_MB17_ID0                  0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN0_MB17_ID1                  0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN0_MB18_DATA0                0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN0_MB18_DATA1                0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN0_MB18_DATA2                0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN0_MB18_DATA3                0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN0_MB18_LENGTH               0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN0_MB18_TIMESTAMP            0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN0_MB18_ID0                  0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN0_MB18_ID1                  0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN0_MB19_DATA0                0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN0_MB19_DATA1                0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN0_MB19_DATA2                0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN0_MB19_DATA3                0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN0_MB19_LENGTH               0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN0_MB19_TIMESTAMP            0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN0_MB19_ID0                  0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN0_MB19_ID1                  0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN0_MB20_DATA0                0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN0_MB20_DATA1                0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN0_MB20_DATA2                0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN0_MB20_DATA3                0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN0_MB20_LENGTH               0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN0_MB20_TIMESTAMP            0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN0_MB20_ID0                  0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN0_MB20_ID1                  0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN0_MB21_DATA0                0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN0_MB21_DATA1                0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN0_MB21_DATA2                0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN0_MB21_DATA3                0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN0_MB21_LENGTH               0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN0_MB21_TIMESTAMP            0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN0_MB21_ID0                  0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN0_MB21_ID1                  0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN0_MB22_DATA0                0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN0_MB22_DATA1                0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN0_MB22_DATA2                0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN0_MB22_DATA3                0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN0_MB22_LENGTH               0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN0_MB22_TIMESTAMP            0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN0_MB22_ID0                  0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN0_MB22_ID1                  0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN0_MB23_DATA0                0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN0_MB23_DATA1                0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN0_MB23_DATA2                0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN0_MB23_DATA3                0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN0_MB23_LENGTH               0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN0_MB23_TIMESTAMP            0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN0_MB23_ID0                  0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN0_MB23_ID1                  0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN0_MB24_DATA0                0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN0_MB24_DATA1                0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN0_MB24_DATA2                0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN0_MB24_DATA3                0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN0_MB24_LENGTH               0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN0_MB24_TIMESTAMP            0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN0_MB24_ID0                  0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN0_MB24_ID1                  0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN0_MB25_DATA0                0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN0_MB25_DATA1                0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN0_MB25_DATA2                0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN0_MB25_DATA3                0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN0_MB25_LENGTH               0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN0_MB25_TIMESTAMP            0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN0_MB25_ID0                  0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN0_MB25_ID1                  0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN0_MB26_DATA0                0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN0_MB26_DATA1                0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN0_MB26_DATA2                0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN0_MB26_DATA3                0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN0_MB26_LENGTH               0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN0_MB26_TIMESTAMP            0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN0_MB26_ID0                  0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN0_MB26_ID1                  0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN0_MB27_DATA0                0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN0_MB27_DATA1                0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN0_MB27_DATA2                0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN0_MB27_DATA3                0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN0_MB27_LENGTH               0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN0_MB27_TIMESTAMP            0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN0_MB27_ID0                  0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN0_MB27_ID1                  0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN0_MB28_DATA0                0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN0_MB28_DATA1                0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN0_MB28_DATA2                0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN0_MB28_DATA3                0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN0_MB28_LENGTH               0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN0_MB28_TIMESTAMP            0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN0_MB28_ID0                  0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN0_MB28_ID1                  0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN0_MB29_DATA0                0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN0_MB29_DATA1                0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN0_MB29_DATA2                0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN0_MB29_DATA3                0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN0_MB29_LENGTH               0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN0_MB29_TIMESTAMP            0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN0_MB29_ID0                  0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN0_MB29_ID1                  0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN0_MB30_DATA0                0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN0_MB30_DATA1                0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN0_MB30_DATA2                0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN0_MB30_DATA3                0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN0_MB30_LENGTH               0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN0_MB30_TIMESTAMP            0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN0_MB30_ID0                  0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN0_MB30_ID1                  0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN0_MB31_DATA0                0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN0_MB31_DATA1                0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN0_MB31_DATA2                0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN0_MB31_DATA3                0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN0_MB31_LENGTH               0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN0_MB31_TIMESTAMP            0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN0_MB31_ID0                  0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN0_MB31_ID1                  0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
-#define CAN1_MC1                       0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define CAN1_MD1                       0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */
-#define CAN1_TRS1                      0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */
-#define CAN1_TRR1                      0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define CAN1_TA1                       0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define CAN1_AA1                       0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define CAN1_RMP1                      0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */
-#define CAN1_RML1                      0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */
-#define CAN1_MBTIF1                    0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN1_MBRIF1                    0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN1_MBIM1                     0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define CAN1_RFH1                      0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define CAN1_OPSS1                     0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN1_MC2                       0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define CAN1_MD2                       0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */
-#define CAN1_TRS2                      0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */
-#define CAN1_TRR2                      0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define CAN1_TA2                       0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define CAN1_AA2                       0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define CAN1_RMP2                      0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */
-#define CAN1_RML2                      0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */
-#define CAN1_MBTIF2                    0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN1_MBRIF2                    0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN1_MBIM2                     0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define CAN1_RFH2                      0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define CAN1_OPSS2                     0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN1_CLOCK                     0xFFC03280 /* CAN Controller 1 Clock Register */
-#define CAN1_TIMING                    0xFFC03284 /* CAN Controller 1 Timing Register */
-#define CAN1_DEBUG                     0xFFC03288 /* CAN Controller 1 Debug Register */
-#define CAN1_STATUS                    0xFFC0328C /* CAN Controller 1 Global Status Register */
-#define CAN1_CEC                       0xFFC03290 /* CAN Controller 1 Error Counter Register */
-#define CAN1_GIS                       0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */
-#define CAN1_GIM                       0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */
-#define CAN1_GIF                       0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */
-#define CAN1_CONTROL                   0xFFC032A0 /* CAN Controller 1 Master Control Register */
-#define CAN1_INTR                      0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */
-#define CAN1_MBTD                      0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define CAN1_EWR                       0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */
-#define CAN1_ESR                       0xFFC032B4 /* CAN Controller 1 Error Status Register */
-#define CAN1_UCCNT                     0xFFC032C4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC                      0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */
-#define CAN1_UCCNF                     0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */
-#define CAN1_AM00L                     0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define CAN1_AM00H                     0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define CAN1_AM01L                     0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define CAN1_AM01H                     0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define CAN1_AM02L                     0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define CAN1_AM02H                     0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define CAN1_AM03L                     0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define CAN1_AM03H                     0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define CAN1_AM04L                     0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define CAN1_AM04H                     0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define CAN1_AM05L                     0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define CAN1_AM05H                     0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define CAN1_AM06L                     0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define CAN1_AM06H                     0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define CAN1_AM07L                     0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define CAN1_AM07H                     0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define CAN1_AM08L                     0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define CAN1_AM08H                     0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define CAN1_AM09L                     0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define CAN1_AM09H                     0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define CAN1_AM10L                     0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define CAN1_AM10H                     0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define CAN1_AM11L                     0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define CAN1_AM11H                     0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define CAN1_AM12L                     0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define CAN1_AM12H                     0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define CAN1_AM13L                     0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define CAN1_AM13H                     0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define CAN1_AM14L                     0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define CAN1_AM14H                     0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define CAN1_AM15L                     0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define CAN1_AM15H                     0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-#define CAN1_AM16L                     0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define CAN1_AM16H                     0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define CAN1_AM17L                     0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define CAN1_AM17H                     0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define CAN1_AM18L                     0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define CAN1_AM18H                     0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define CAN1_AM19L                     0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define CAN1_AM19H                     0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define CAN1_AM20L                     0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define CAN1_AM20H                     0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define CAN1_AM21L                     0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define CAN1_AM21H                     0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define CAN1_AM22L                     0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define CAN1_AM22H                     0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define CAN1_AM23L                     0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define CAN1_AM23H                     0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define CAN1_AM24L                     0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define CAN1_AM24H                     0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define CAN1_AM25L                     0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define CAN1_AM25H                     0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define CAN1_AM26L                     0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define CAN1_AM26H                     0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define CAN1_AM27L                     0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define CAN1_AM27H                     0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define CAN1_AM28L                     0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define CAN1_AM28H                     0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define CAN1_AM29L                     0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define CAN1_AM29H                     0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define CAN1_AM30L                     0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define CAN1_AM30H                     0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define CAN1_AM31L                     0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define CAN1_AM31H                     0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-#define CAN1_MB00_DATA0                0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define CAN1_MB00_DATA1                0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define CAN1_MB00_DATA2                0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define CAN1_MB00_DATA3                0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define CAN1_MB00_LENGTH               0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */
-#define CAN1_MB00_TIMESTAMP            0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define CAN1_MB00_ID0                  0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define CAN1_MB00_ID1                  0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define CAN1_MB01_DATA0                0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define CAN1_MB01_DATA1                0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define CAN1_MB01_DATA2                0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define CAN1_MB01_DATA3                0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define CAN1_MB01_LENGTH               0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */
-#define CAN1_MB01_TIMESTAMP            0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define CAN1_MB01_ID0                  0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define CAN1_MB01_ID1                  0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define CAN1_MB02_DATA0                0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define CAN1_MB02_DATA1                0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define CAN1_MB02_DATA2                0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define CAN1_MB02_DATA3                0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define CAN1_MB02_LENGTH               0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */
-#define CAN1_MB02_TIMESTAMP            0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define CAN1_MB02_ID0                  0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define CAN1_MB02_ID1                  0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define CAN1_MB03_DATA0                0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define CAN1_MB03_DATA1                0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define CAN1_MB03_DATA2                0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define CAN1_MB03_DATA3                0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define CAN1_MB03_LENGTH               0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */
-#define CAN1_MB03_TIMESTAMP            0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define CAN1_MB03_ID0                  0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define CAN1_MB03_ID1                  0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define CAN1_MB04_DATA0                0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define CAN1_MB04_DATA1                0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define CAN1_MB04_DATA2                0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define CAN1_MB04_DATA3                0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define CAN1_MB04_LENGTH               0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */
-#define CAN1_MB04_TIMESTAMP            0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define CAN1_MB04_ID0                  0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define CAN1_MB04_ID1                  0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define CAN1_MB05_DATA0                0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define CAN1_MB05_DATA1                0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define CAN1_MB05_DATA2                0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define CAN1_MB05_DATA3                0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define CAN1_MB05_LENGTH               0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */
-#define CAN1_MB05_TIMESTAMP            0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define CAN1_MB05_ID0                  0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define CAN1_MB05_ID1                  0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define CAN1_MB06_DATA0                0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define CAN1_MB06_DATA1                0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define CAN1_MB06_DATA2                0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define CAN1_MB06_DATA3                0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define CAN1_MB06_LENGTH               0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */
-#define CAN1_MB06_TIMESTAMP            0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define CAN1_MB06_ID0                  0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define CAN1_MB06_ID1                  0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define CAN1_MB07_DATA0                0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define CAN1_MB07_DATA1                0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define CAN1_MB07_DATA2                0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define CAN1_MB07_DATA3                0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define CAN1_MB07_LENGTH               0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */
-#define CAN1_MB07_TIMESTAMP            0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define CAN1_MB07_ID0                  0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define CAN1_MB07_ID1                  0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define CAN1_MB08_DATA0                0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define CAN1_MB08_DATA1                0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define CAN1_MB08_DATA2                0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define CAN1_MB08_DATA3                0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define CAN1_MB08_LENGTH               0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */
-#define CAN1_MB08_TIMESTAMP            0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define CAN1_MB08_ID0                  0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define CAN1_MB08_ID1                  0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define CAN1_MB09_DATA0                0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define CAN1_MB09_DATA1                0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define CAN1_MB09_DATA2                0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define CAN1_MB09_DATA3                0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define CAN1_MB09_LENGTH               0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */
-#define CAN1_MB09_TIMESTAMP            0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define CAN1_MB09_ID0                  0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define CAN1_MB09_ID1                  0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define CAN1_MB10_DATA0                0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define CAN1_MB10_DATA1                0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define CAN1_MB10_DATA2                0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define CAN1_MB10_DATA3                0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define CAN1_MB10_LENGTH               0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */
-#define CAN1_MB10_TIMESTAMP            0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define CAN1_MB10_ID0                  0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define CAN1_MB10_ID1                  0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define CAN1_MB11_DATA0                0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define CAN1_MB11_DATA1                0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define CAN1_MB11_DATA2                0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define CAN1_MB11_DATA3                0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define CAN1_MB11_LENGTH               0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */
-#define CAN1_MB11_TIMESTAMP            0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define CAN1_MB11_ID0                  0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define CAN1_MB11_ID1                  0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define CAN1_MB12_DATA0                0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define CAN1_MB12_DATA1                0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define CAN1_MB12_DATA2                0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define CAN1_MB12_DATA3                0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define CAN1_MB12_LENGTH               0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */
-#define CAN1_MB12_TIMESTAMP            0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define CAN1_MB12_ID0                  0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define CAN1_MB12_ID1                  0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define CAN1_MB13_DATA0                0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define CAN1_MB13_DATA1                0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define CAN1_MB13_DATA2                0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define CAN1_MB13_DATA3                0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define CAN1_MB13_LENGTH               0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */
-#define CAN1_MB13_TIMESTAMP            0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define CAN1_MB13_ID0                  0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define CAN1_MB13_ID1                  0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define CAN1_MB14_DATA0                0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define CAN1_MB14_DATA1                0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define CAN1_MB14_DATA2                0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define CAN1_MB14_DATA3                0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define CAN1_MB14_LENGTH               0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */
-#define CAN1_MB14_TIMESTAMP            0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define CAN1_MB14_ID0                  0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define CAN1_MB14_ID1                  0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define CAN1_MB15_DATA0                0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define CAN1_MB15_DATA1                0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define CAN1_MB15_DATA2                0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define CAN1_MB15_DATA3                0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define CAN1_MB15_LENGTH               0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */
-#define CAN1_MB15_TIMESTAMP            0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define CAN1_MB15_ID0                  0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define CAN1_MB15_ID1                  0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */
-#define CAN1_MB16_DATA0                0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define CAN1_MB16_DATA1                0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define CAN1_MB16_DATA2                0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define CAN1_MB16_DATA3                0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define CAN1_MB16_LENGTH               0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */
-#define CAN1_MB16_TIMESTAMP            0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define CAN1_MB16_ID0                  0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define CAN1_MB16_ID1                  0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define CAN1_MB17_DATA0                0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define CAN1_MB17_DATA1                0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define CAN1_MB17_DATA2                0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define CAN1_MB17_DATA3                0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define CAN1_MB17_LENGTH               0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */
-#define CAN1_MB17_TIMESTAMP            0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define CAN1_MB17_ID0                  0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define CAN1_MB17_ID1                  0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define CAN1_MB18_DATA0                0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define CAN1_MB18_DATA1                0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define CAN1_MB18_DATA2                0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define CAN1_MB18_DATA3                0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define CAN1_MB18_LENGTH               0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */
-#define CAN1_MB18_TIMESTAMP            0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define CAN1_MB18_ID0                  0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define CAN1_MB18_ID1                  0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define CAN1_MB19_DATA0                0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define CAN1_MB19_DATA1                0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define CAN1_MB19_DATA2                0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define CAN1_MB19_DATA3                0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define CAN1_MB19_LENGTH               0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */
-#define CAN1_MB19_TIMESTAMP            0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define CAN1_MB19_ID0                  0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define CAN1_MB19_ID1                  0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define CAN1_MB20_DATA0                0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define CAN1_MB20_DATA1                0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define CAN1_MB20_DATA2                0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define CAN1_MB20_DATA3                0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define CAN1_MB20_LENGTH               0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */
-#define CAN1_MB20_TIMESTAMP            0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define CAN1_MB20_ID0                  0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define CAN1_MB20_ID1                  0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define CAN1_MB21_DATA0                0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define CAN1_MB21_DATA1                0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define CAN1_MB21_DATA2                0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define CAN1_MB21_DATA3                0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define CAN1_MB21_LENGTH               0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */
-#define CAN1_MB21_TIMESTAMP            0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define CAN1_MB21_ID0                  0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define CAN1_MB21_ID1                  0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define CAN1_MB22_DATA0                0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define CAN1_MB22_DATA1                0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define CAN1_MB22_DATA2                0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define CAN1_MB22_DATA3                0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define CAN1_MB22_LENGTH               0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */
-#define CAN1_MB22_TIMESTAMP            0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define CAN1_MB22_ID0                  0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define CAN1_MB22_ID1                  0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define CAN1_MB23_DATA0                0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define CAN1_MB23_DATA1                0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define CAN1_MB23_DATA2                0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define CAN1_MB23_DATA3                0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define CAN1_MB23_LENGTH               0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */
-#define CAN1_MB23_TIMESTAMP            0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define CAN1_MB23_ID0                  0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define CAN1_MB23_ID1                  0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define CAN1_MB24_DATA0                0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define CAN1_MB24_DATA1                0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define CAN1_MB24_DATA2                0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define CAN1_MB24_DATA3                0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define CAN1_MB24_LENGTH               0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */
-#define CAN1_MB24_TIMESTAMP            0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define CAN1_MB24_ID0                  0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define CAN1_MB24_ID1                  0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define CAN1_MB25_DATA0                0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define CAN1_MB25_DATA1                0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define CAN1_MB25_DATA2                0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define CAN1_MB25_DATA3                0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define CAN1_MB25_LENGTH               0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */
-#define CAN1_MB25_TIMESTAMP            0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define CAN1_MB25_ID0                  0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define CAN1_MB25_ID1                  0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define CAN1_MB26_DATA0                0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define CAN1_MB26_DATA1                0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define CAN1_MB26_DATA2                0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define CAN1_MB26_DATA3                0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define CAN1_MB26_LENGTH               0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */
-#define CAN1_MB26_TIMESTAMP            0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define CAN1_MB26_ID0                  0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define CAN1_MB26_ID1                  0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define CAN1_MB27_DATA0                0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define CAN1_MB27_DATA1                0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define CAN1_MB27_DATA2                0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define CAN1_MB27_DATA3                0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define CAN1_MB27_LENGTH               0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */
-#define CAN1_MB27_TIMESTAMP            0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define CAN1_MB27_ID0                  0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define CAN1_MB27_ID1                  0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define CAN1_MB28_DATA0                0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define CAN1_MB28_DATA1                0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define CAN1_MB28_DATA2                0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define CAN1_MB28_DATA3                0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define CAN1_MB28_LENGTH               0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */
-#define CAN1_MB28_TIMESTAMP            0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define CAN1_MB28_ID0                  0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define CAN1_MB28_ID1                  0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define CAN1_MB29_DATA0                0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define CAN1_MB29_DATA1                0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define CAN1_MB29_DATA2                0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define CAN1_MB29_DATA3                0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define CAN1_MB29_LENGTH               0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */
-#define CAN1_MB29_TIMESTAMP            0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define CAN1_MB29_ID0                  0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define CAN1_MB29_ID1                  0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define CAN1_MB30_DATA0                0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define CAN1_MB30_DATA1                0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define CAN1_MB30_DATA2                0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define CAN1_MB30_DATA3                0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define CAN1_MB30_LENGTH               0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */
-#define CAN1_MB30_TIMESTAMP            0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define CAN1_MB30_ID0                  0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define CAN1_MB30_ID1                  0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define CAN1_MB31_DATA0                0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define CAN1_MB31_DATA1                0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define CAN1_MB31_DATA2                0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define CAN1_MB31_DATA3                0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define CAN1_MB31_LENGTH               0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */
-#define CAN1_MB31_TIMESTAMP            0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define CAN1_MB31_ID0                  0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define CAN1_MB31_ID1                  0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */
-#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
-#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
-#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
-#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
-#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
-#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
-#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
-#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
-#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
-#define SPI2_CTL                       0xFFC02400 /* SPI2 Control Register */
-#define SPI2_FLG                       0xFFC02404 /* SPI2 Flag Register */
-#define SPI2_STAT                      0xFFC02408 /* SPI2 Status Register */
-#define SPI2_TDBR                      0xFFC0240C /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR                      0xFFC02410 /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD                      0xFFC02414 /* SPI2 Baud Rate Register */
-#define SPI2_SHADOW                    0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */
-#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
-#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
-#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
-#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
-#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
-#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
-#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
-#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
-#define TWI1_CLKDIV                    0xFFC02200 /* Clock Divider Register */
-#define TWI1_CONTROL                   0xFFC02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL                 0xFFC02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT                0xFFC0220C /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR                0xFFC02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL                0xFFC02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT               0xFFC02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR               0xFFC0221C /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT                  0xFFC02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK                  0xFFC02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL                  0xFFC02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT                 0xFFC0222C /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8                 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16                0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8                 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16                0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
-#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */
-#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */
-#define SPORT0_TX                      0xFFC00810 /* SPORT0 Transmit Data Register */
-#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Receive Configuration 1 Register */
-#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Receive Configuration 2 Register */
-#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */
-#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */
-#define SPORT0_RX                      0xFFC00818 /* SPORT0 Receive Data Register */
-#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */
-#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */
-#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */
-#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */
-#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */
-#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */
-#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */
-#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
-#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
-#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
-#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
-#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
-#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
-#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
-#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
-#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
-#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
-#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
-#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
-#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
-#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
-#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
-#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
-#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
-#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
-#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
-#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
-#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
-#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
-#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
-#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
-#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
-#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
-#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
-#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
-#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
-#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
-#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
-#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
-#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
-#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
-#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
-#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
-#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
-#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
-#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
-#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
-#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
-#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
-#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
-#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
-#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
-#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
-#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
-#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
-#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
-#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
-#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
-#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
-#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
-#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
-#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
-#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
-#define UART0_LCR                      0xFFC0040C /* Line Control Register */
-#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
-#define UART0_LSR                      0xFFC00414 /* Line Status Register */
-#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
-#define UART0_SCR                      0xFFC0041C /* Scratch Register */
-#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
-#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
-#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
-#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
-#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
-#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
-#define UART1_LCR                      0xFFC0200C /* Line Control Register */
-#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
-#define UART1_LSR                      0xFFC02014 /* Line Status Register */
-#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
-#define UART1_SCR                      0xFFC0201C /* Scratch Register */
-#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
-#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
-#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
-#define UART2_DLL                      0xFFC02100 /* Divisor Latch Low Byte */
-#define UART2_DLH                      0xFFC02104 /* Divisor Latch High Byte */
-#define UART2_GCTL                     0xFFC02108 /* Global Control Register */
-#define UART2_LCR                      0xFFC0210C /* Line Control Register */
-#define UART2_MCR                      0xFFC02110 /* Modem Control Register */
-#define UART2_LSR                      0xFFC02114 /* Line Status Register */
-#define UART2_MSR                      0xFFC02118 /* Modem Status Register */
-#define UART2_SCR                      0xFFC0211C /* Scratch Register */
-#define UART2_IER_SET                  0xFFC02120 /* Interrupt Enable Register Set */
-#define UART2_IER_CLEAR                0xFFC02124 /* Interrupt Enable Register Clear */
-#define UART2_THR                      0xFFC02128 /* Transmit Hold Register */
-#define UART2_RBR                      0xFFC0212C /* Receive Buffer Register */
-#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
-#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
-#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
-#define UART3_LCR                      0xFFC0310C /* Line Control Register */
-#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
-#define UART3_LSR                      0xFFC03114 /* Line Status Register */
-#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
-#define UART3_SCR                      0xFFC0311C /* Scratch Register */
-#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
-#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
-#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
-#define USB_FADDR                      0xFFC03C00 /* Function address register */
-#define USB_POWER                      0xFFC03C04 /* Power management register */
-#define USB_INTRTX                     0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX                     0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE                    0xFFC03C10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE                    0xFFC03C14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB                    0xFFC03C18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE                   0xFFC03C1C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME                      0xFFC03C20 /* USB frame number */
-#define USB_INDEX                      0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE                   0xFFC03C28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR                   0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL                 0xFFC03C30 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET              0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0                       0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR                      0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET              0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR                      0xFFC03C4C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0                     0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT                    0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE                     0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0                  0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL                 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE                     0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL                 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT                    0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO                   0xFFC03C80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO                   0xFFC03C88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO                   0xFFC03C90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO                   0xFFC03C98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO                   0xFFC03CA0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO                   0xFFC03CA8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO                   0xFFC03CB0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO                   0xFFC03CB8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL                0xFFC03D00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ               0xFFC03D04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK              0xFFC03D08 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO                   0xFFC03D48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN                      0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1                    0xFFC03D50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1                    0xFFC03D54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1                    0xFFC03D58 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL                 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB                 0xFFC03DE4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2                0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST                   0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL                0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV                 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP              0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR               0xFFC03E04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP              0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR               0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT             0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE              0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL          0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE              0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL          0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT             0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP              0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR               0xFFC03E44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP              0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR               0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT             0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE              0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL          0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE              0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL          0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT             0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP              0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR               0xFFC03E84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP              0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR               0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT             0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE              0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL          0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE              0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL          0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT             0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP              0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR               0xFFC03EC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP              0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR               0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT             0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE              0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL          0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE              0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL          0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT             0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP              0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR               0xFFC03F04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP              0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR               0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT             0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE              0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL          0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE              0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL          0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT             0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP              0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR               0xFFC03F44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP              0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR               0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT             0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE              0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL          0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE              0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL          0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT             0xFFC03F68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP              0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR               0xFFC03F84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP              0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR               0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT             0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE              0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL          0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE              0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL          0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT             0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP              0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR               0xFFC03FC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP              0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR               0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT             0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE              0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL          0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE              0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL          0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT             0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT              0xFFC04000 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL               0xFFC04004 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW               0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH              0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW              0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH             0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL               0xFFC04024 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW               0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH              0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW              0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH             0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL               0xFFC04044 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW               0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH              0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW              0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH             0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL               0xFFC04064 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW               0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH              0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW              0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH             0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL               0xFFC04084 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW               0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH              0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW              0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH             0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL               0xFFC040A4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW               0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH              0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW              0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH             0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL               0xFFC040C4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW               0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH              0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW              0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH             0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL               0xFFC040E4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW               0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH              0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW              0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH             0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_EDN_BF548_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
deleted file mode 100644
index 970f13f..0000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
+++ /dev/null
@@ -1,4084 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_EDN_BF549_extended__
-#define __BFIN_CDEF_ADSP_EDN_BF549_extended__
-
-#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
-#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
-#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
-#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
-#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
-#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
-#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
-#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
-#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
-#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
-#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
-#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
-#define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
-#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
-#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA()              bfin_read16(PORTA)
-#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB()              bfin_read16(PORTB)
-#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC()              bfin_read16(PORTC)
-#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD()              bfin_read16(PORTD)
-#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE()              bfin_read16(PORTE)
-#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF()              bfin_read16(PORTF)
-#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG()              bfin_read16(PORTG)
-#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH()              bfin_read16(PORTH)
-#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
-#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI()              bfin_read16(PORTI)
-#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
-#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ()              bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
-#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
-#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
-#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
-#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
-#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
-#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
-#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
-#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
-#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
-#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
-#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
-#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
-#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
-#define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
-#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
-#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_MXVR_CONFIG()        bfin_read16(MXVR_CONFIG)
-#define bfin_write_MXVR_CONFIG(val)    bfin_write16(MXVR_CONFIG, val)
-#define bfin_read_MXVR_STATE_0()       bfin_read32(MXVR_STATE_0)
-#define bfin_write_MXVR_STATE_0(val)   bfin_write32(MXVR_STATE_0, val)
-#define bfin_read_MXVR_STATE_1()       bfin_read32(MXVR_STATE_1)
-#define bfin_write_MXVR_STATE_1(val)   bfin_write32(MXVR_STATE_1, val)
-#define bfin_read_MXVR_INT_STAT_0()    bfin_read32(MXVR_INT_STAT_0)
-#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
-#define bfin_read_MXVR_INT_STAT_1()    bfin_read32(MXVR_INT_STAT_1)
-#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
-#define bfin_read_MXVR_INT_EN_0()      bfin_read32(MXVR_INT_EN_0)
-#define bfin_write_MXVR_INT_EN_0(val)  bfin_write32(MXVR_INT_EN_0, val)
-#define bfin_read_MXVR_INT_EN_1()      bfin_read32(MXVR_INT_EN_1)
-#define bfin_write_MXVR_INT_EN_1(val)  bfin_write32(MXVR_INT_EN_1, val)
-#define bfin_read_MXVR_POSITION()      bfin_read16(MXVR_POSITION)
-#define bfin_write_MXVR_POSITION(val)  bfin_write16(MXVR_POSITION, val)
-#define bfin_read_MXVR_MAX_POSITION()  bfin_read16(MXVR_MAX_POSITION)
-#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
-#define bfin_read_MXVR_DELAY()         bfin_read16(MXVR_DELAY)
-#define bfin_write_MXVR_DELAY(val)     bfin_write16(MXVR_DELAY, val)
-#define bfin_read_MXVR_MAX_DELAY()     bfin_read16(MXVR_MAX_DELAY)
-#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
-#define bfin_read_MXVR_LADDR()         bfin_read32(MXVR_LADDR)
-#define bfin_write_MXVR_LADDR(val)     bfin_write32(MXVR_LADDR, val)
-#define bfin_read_MXVR_GADDR()         bfin_read16(MXVR_GADDR)
-#define bfin_write_MXVR_GADDR(val)     bfin_write16(MXVR_GADDR, val)
-#define bfin_read_MXVR_AADDR()         bfin_read32(MXVR_AADDR)
-#define bfin_write_MXVR_AADDR(val)     bfin_write32(MXVR_AADDR, val)
-#define bfin_read_MXVR_ALLOC_0()       bfin_read32(MXVR_ALLOC_0)
-#define bfin_write_MXVR_ALLOC_0(val)   bfin_write32(MXVR_ALLOC_0, val)
-#define bfin_read_MXVR_ALLOC_1()       bfin_read32(MXVR_ALLOC_1)
-#define bfin_write_MXVR_ALLOC_1(val)   bfin_write32(MXVR_ALLOC_1, val)
-#define bfin_read_MXVR_ALLOC_2()       bfin_read32(MXVR_ALLOC_2)
-#define bfin_write_MXVR_ALLOC_2(val)   bfin_write32(MXVR_ALLOC_2, val)
-#define bfin_read_MXVR_ALLOC_3()       bfin_read32(MXVR_ALLOC_3)
-#define bfin_write_MXVR_ALLOC_3(val)   bfin_write32(MXVR_ALLOC_3, val)
-#define bfin_read_MXVR_ALLOC_4()       bfin_read32(MXVR_ALLOC_4)
-#define bfin_write_MXVR_ALLOC_4(val)   bfin_write32(MXVR_ALLOC_4, val)
-#define bfin_read_MXVR_ALLOC_5()       bfin_read32(MXVR_ALLOC_5)
-#define bfin_write_MXVR_ALLOC_5(val)   bfin_write32(MXVR_ALLOC_5, val)
-#define bfin_read_MXVR_ALLOC_6()       bfin_read32(MXVR_ALLOC_6)
-#define bfin_write_MXVR_ALLOC_6(val)   bfin_write32(MXVR_ALLOC_6, val)
-#define bfin_read_MXVR_ALLOC_7()       bfin_read32(MXVR_ALLOC_7)
-#define bfin_write_MXVR_ALLOC_7(val)   bfin_write32(MXVR_ALLOC_7, val)
-#define bfin_read_MXVR_ALLOC_8()       bfin_read32(MXVR_ALLOC_8)
-#define bfin_write_MXVR_ALLOC_8(val)   bfin_write32(MXVR_ALLOC_8, val)
-#define bfin_read_MXVR_ALLOC_9()       bfin_read32(MXVR_ALLOC_9)
-#define bfin_write_MXVR_ALLOC_9(val)   bfin_write32(MXVR_ALLOC_9, val)
-#define bfin_read_MXVR_ALLOC_10()      bfin_read32(MXVR_ALLOC_10)
-#define bfin_write_MXVR_ALLOC_10(val)  bfin_write32(MXVR_ALLOC_10, val)
-#define bfin_read_MXVR_ALLOC_11()      bfin_read32(MXVR_ALLOC_11)
-#define bfin_write_MXVR_ALLOC_11(val)  bfin_write32(MXVR_ALLOC_11, val)
-#define bfin_read_MXVR_ALLOC_12()      bfin_read32(MXVR_ALLOC_12)
-#define bfin_write_MXVR_ALLOC_12(val)  bfin_write32(MXVR_ALLOC_12, val)
-#define bfin_read_MXVR_ALLOC_13()      bfin_read32(MXVR_ALLOC_13)
-#define bfin_write_MXVR_ALLOC_13(val)  bfin_write32(MXVR_ALLOC_13, val)
-#define bfin_read_MXVR_ALLOC_14()      bfin_read32(MXVR_ALLOC_14)
-#define bfin_write_MXVR_ALLOC_14(val)  bfin_write32(MXVR_ALLOC_14, val)
-#define bfin_read_MXVR_SYNC_LCHAN_0()  bfin_read32(MXVR_SYNC_LCHAN_0)
-#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
-#define bfin_read_MXVR_SYNC_LCHAN_1()  bfin_read32(MXVR_SYNC_LCHAN_1)
-#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
-#define bfin_read_MXVR_SYNC_LCHAN_2()  bfin_read32(MXVR_SYNC_LCHAN_2)
-#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
-#define bfin_read_MXVR_SYNC_LCHAN_3()  bfin_read32(MXVR_SYNC_LCHAN_3)
-#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
-#define bfin_read_MXVR_SYNC_LCHAN_4()  bfin_read32(MXVR_SYNC_LCHAN_4)
-#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
-#define bfin_read_MXVR_SYNC_LCHAN_5()  bfin_read32(MXVR_SYNC_LCHAN_5)
-#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
-#define bfin_read_MXVR_SYNC_LCHAN_6()  bfin_read32(MXVR_SYNC_LCHAN_6)
-#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
-#define bfin_read_MXVR_SYNC_LCHAN_7()  bfin_read32(MXVR_SYNC_LCHAN_7)
-#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
-#define bfin_read_MXVR_DMA0_CONFIG()   bfin_read32(MXVR_DMA0_CONFIG)
-#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
-#define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR)
-#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val)
-#define bfin_read_MXVR_DMA0_COUNT()    bfin_read16(MXVR_DMA0_COUNT)
-#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
-#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR)
-#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
-#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA1_CONFIG()   bfin_read32(MXVR_DMA1_CONFIG)
-#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
-#define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR)
-#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val)
-#define bfin_read_MXVR_DMA1_COUNT()    bfin_read16(MXVR_DMA1_COUNT)
-#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
-#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR)
-#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
-#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA2_CONFIG()   bfin_read32(MXVR_DMA2_CONFIG)
-#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
-#define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR)
-#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val)
-#define bfin_read_MXVR_DMA2_COUNT()    bfin_read16(MXVR_DMA2_COUNT)
-#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
-#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR)
-#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
-#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA3_CONFIG()   bfin_read32(MXVR_DMA3_CONFIG)
-#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
-#define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR)
-#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val)
-#define bfin_read_MXVR_DMA3_COUNT()    bfin_read16(MXVR_DMA3_COUNT)
-#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
-#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR)
-#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
-#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA4_CONFIG()   bfin_read32(MXVR_DMA4_CONFIG)
-#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
-#define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR)
-#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val)
-#define bfin_read_MXVR_DMA4_COUNT()    bfin_read16(MXVR_DMA4_COUNT)
-#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
-#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR)
-#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
-#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA5_CONFIG()   bfin_read32(MXVR_DMA5_CONFIG)
-#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
-#define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR)
-#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val)
-#define bfin_read_MXVR_DMA5_COUNT()    bfin_read16(MXVR_DMA5_COUNT)
-#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
-#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR)
-#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
-#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA6_CONFIG()   bfin_read32(MXVR_DMA6_CONFIG)
-#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
-#define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR)
-#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val)
-#define bfin_read_MXVR_DMA6_COUNT()    bfin_read16(MXVR_DMA6_COUNT)
-#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
-#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR)
-#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
-#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA7_CONFIG()   bfin_read32(MXVR_DMA7_CONFIG)
-#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
-#define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR)
-#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val)
-#define bfin_read_MXVR_DMA7_COUNT()    bfin_read16(MXVR_DMA7_COUNT)
-#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
-#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR)
-#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
-#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
-#define bfin_read_MXVR_AP_CTL()        bfin_read16(MXVR_AP_CTL)
-#define bfin_write_MXVR_AP_CTL(val)    bfin_write16(MXVR_AP_CTL, val)
-#define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR)
-#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val)
-#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR)
-#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val)
-#define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR)
-#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val)
-#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR)
-#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val)
-#define bfin_read_MXVR_CM_CTL()        bfin_read32(MXVR_CM_CTL)
-#define bfin_write_MXVR_CM_CTL(val)    bfin_write32(MXVR_CM_CTL, val)
-#define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR)
-#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val)
-#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR)
-#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val)
-#define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR)
-#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val)
-#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR)
-#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val)
-#define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR)
-#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val)
-#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR)
-#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val)
-#define bfin_read_MXVR_PAT_DATA_0()    bfin_read32(MXVR_PAT_DATA_0)
-#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
-#define bfin_read_MXVR_PAT_EN_0()      bfin_read32(MXVR_PAT_EN_0)
-#define bfin_write_MXVR_PAT_EN_0(val)  bfin_write32(MXVR_PAT_EN_0, val)
-#define bfin_read_MXVR_PAT_DATA_1()    bfin_read32(MXVR_PAT_DATA_1)
-#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
-#define bfin_read_MXVR_PAT_EN_1()      bfin_read32(MXVR_PAT_EN_1)
-#define bfin_write_MXVR_PAT_EN_1(val)  bfin_write32(MXVR_PAT_EN_1, val)
-#define bfin_read_MXVR_FRAME_CNT_0()   bfin_read16(MXVR_FRAME_CNT_0)
-#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
-#define bfin_read_MXVR_FRAME_CNT_1()   bfin_read16(MXVR_FRAME_CNT_1)
-#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
-#define bfin_read_MXVR_ROUTING_0()     bfin_read32(MXVR_ROUTING_0)
-#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
-#define bfin_read_MXVR_ROUTING_1()     bfin_read32(MXVR_ROUTING_1)
-#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
-#define bfin_read_MXVR_ROUTING_2()     bfin_read32(MXVR_ROUTING_2)
-#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
-#define bfin_read_MXVR_ROUTING_3()     bfin_read32(MXVR_ROUTING_3)
-#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
-#define bfin_read_MXVR_ROUTING_4()     bfin_read32(MXVR_ROUTING_4)
-#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
-#define bfin_read_MXVR_ROUTING_5()     bfin_read32(MXVR_ROUTING_5)
-#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
-#define bfin_read_MXVR_ROUTING_6()     bfin_read32(MXVR_ROUTING_6)
-#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
-#define bfin_read_MXVR_ROUTING_7()     bfin_read32(MXVR_ROUTING_7)
-#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
-#define bfin_read_MXVR_ROUTING_8()     bfin_read32(MXVR_ROUTING_8)
-#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
-#define bfin_read_MXVR_ROUTING_9()     bfin_read32(MXVR_ROUTING_9)
-#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
-#define bfin_read_MXVR_ROUTING_10()    bfin_read32(MXVR_ROUTING_10)
-#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
-#define bfin_read_MXVR_ROUTING_11()    bfin_read32(MXVR_ROUTING_11)
-#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
-#define bfin_read_MXVR_ROUTING_12()    bfin_read32(MXVR_ROUTING_12)
-#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
-#define bfin_read_MXVR_ROUTING_13()    bfin_read32(MXVR_ROUTING_13)
-#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
-#define bfin_read_MXVR_ROUTING_14()    bfin_read32(MXVR_ROUTING_14)
-#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
-#define bfin_read_MXVR_BLOCK_CNT()     bfin_read16(MXVR_BLOCK_CNT)
-#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
-#define bfin_read_MXVR_CLK_CTL()       bfin_read32(MXVR_CLK_CTL)
-#define bfin_write_MXVR_CLK_CTL(val)   bfin_write32(MXVR_CLK_CTL, val)
-#define bfin_read_MXVR_CDRPLL_CTL()    bfin_read32(MXVR_CDRPLL_CTL)
-#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
-#define bfin_read_MXVR_FMPLL_CTL()     bfin_read32(MXVR_FMPLL_CTL)
-#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
-#define bfin_read_MXVR_PIN_CTL()       bfin_read16(MXVR_PIN_CTL)
-#define bfin_write_MXVR_PIN_CTL(val)   bfin_write16(MXVR_PIN_CTL, val)
-#define bfin_read_MXVR_SCLK_CNT()      bfin_read16(MXVR_SCLK_CNT)
-#define bfin_write_MXVR_SCLK_CNT(val)  bfin_write16(MXVR_SCLK_CNT, val)
-#define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
-#define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
-#define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
-#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
-#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
-#define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
-#define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
-#define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
-#define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
-#define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
-#define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
-#define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
-#define bfin_read_CAN1_MC1()           bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val)       bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1()           bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val)       bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1()          bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val)      bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1()          bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val)      bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1()           bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val)       bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1()           bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val)       bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1()          bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val)      bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1()          bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val)      bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1()        bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val)    bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1()        bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val)    bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1()         bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val)     bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1()          bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val)      bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1()         bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val)     bfin_write16(CAN1_OPSS1, val)
-#define bfin_read_CAN1_MC2()           bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val)       bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2()           bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val)       bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2()          bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val)      bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2()          bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val)      bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2()           bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val)       bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2()           bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val)       bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2()          bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val)      bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2()          bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val)      bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2()        bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val)    bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2()        bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val)    bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2()         bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val)     bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2()          bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val)      bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2()         bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val)     bfin_write16(CAN1_OPSS2, val)
-#define bfin_read_CAN1_CLOCK()         bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val)     bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING()        bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val)    bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG()         bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val)     bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS()        bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val)    bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC()           bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val)       bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS()           bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val)       bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM()           bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val)       bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF()           bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val)       bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL()       bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val)   bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR()          bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val)      bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD()          bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val)      bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR()           bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val)       bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR()           bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val)       bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT()         bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val)     bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC()          bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val)      bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF()         bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val)     bfin_write16(CAN1_UCCNF, val)
-#define bfin_read_CAN1_AM00L()         bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val)     bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H()         bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val)     bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L()         bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val)     bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H()         bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val)     bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L()         bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val)     bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H()         bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val)     bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L()         bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val)     bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H()         bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val)     bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L()         bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val)     bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H()         bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val)     bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L()         bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val)     bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H()         bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val)     bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L()         bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val)     bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H()         bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val)     bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L()         bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val)     bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H()         bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val)     bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L()         bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val)     bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H()         bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val)     bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L()         bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val)     bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H()         bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val)     bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L()         bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val)     bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H()         bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val)     bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L()         bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val)     bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H()         bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val)     bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L()         bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val)     bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H()         bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val)     bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L()         bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val)     bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H()         bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val)     bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L()         bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val)     bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H()         bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val)     bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L()         bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val)     bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H()         bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val)     bfin_write16(CAN1_AM15H, val)
-#define bfin_read_CAN1_AM16L()         bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val)     bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H()         bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val)     bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L()         bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val)     bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H()         bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val)     bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L()         bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val)     bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H()         bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val)     bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L()         bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val)     bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H()         bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val)     bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L()         bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val)     bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H()         bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val)     bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L()         bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val)     bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H()         bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val)     bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L()         bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val)     bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H()         bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val)     bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L()         bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val)     bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H()         bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val)     bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L()         bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val)     bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H()         bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val)     bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L()         bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val)     bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H()         bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val)     bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L()         bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val)     bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H()         bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val)     bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L()         bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val)     bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H()         bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val)     bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L()         bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val)     bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H()         bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val)     bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L()         bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val)     bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H()         bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val)     bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L()         bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val)     bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H()         bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val)     bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L()         bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val)     bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H()         bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val)     bfin_write16(CAN1_AM31H, val)
-#define bfin_read_CAN1_MB00_DATA0()    bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1()    bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2()    bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3()    bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH()   bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0()      bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val)  bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1()      bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val)  bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0()    bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1()    bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2()    bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3()    bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH()   bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0()      bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val)  bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1()      bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val)  bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0()    bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1()    bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2()    bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3()    bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH()   bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0()      bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val)  bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1()      bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val)  bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0()    bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1()    bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2()    bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3()    bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH()   bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0()      bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val)  bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1()      bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val)  bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0()    bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1()    bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2()    bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3()    bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH()   bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0()      bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val)  bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1()      bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val)  bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0()    bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1()    bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2()    bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3()    bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH()   bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0()      bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val)  bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1()      bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val)  bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0()    bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1()    bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2()    bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3()    bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH()   bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0()      bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val)  bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1()      bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val)  bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0()    bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1()    bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2()    bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3()    bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH()   bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0()      bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val)  bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1()      bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val)  bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0()    bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1()    bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2()    bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3()    bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH()   bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0()      bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val)  bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1()      bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val)  bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0()    bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1()    bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2()    bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3()    bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH()   bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0()      bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val)  bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1()      bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val)  bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0()    bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1()    bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2()    bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3()    bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH()   bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0()      bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val)  bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1()      bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val)  bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0()    bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1()    bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2()    bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3()    bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH()   bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0()      bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val)  bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1()      bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val)  bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0()    bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1()    bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2()    bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3()    bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH()   bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0()      bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val)  bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1()      bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val)  bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0()    bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1()    bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2()    bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3()    bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH()   bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0()      bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val)  bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1()      bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val)  bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0()    bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1()    bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2()    bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3()    bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH()   bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0()      bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val)  bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1()      bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val)  bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0()    bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1()    bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2()    bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3()    bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH()   bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0()      bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val)  bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1()      bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val)  bfin_write16(CAN1_MB15_ID1, val)
-#define bfin_read_CAN1_MB16_DATA0()    bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1()    bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2()    bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3()    bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH()   bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0()      bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val)  bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1()      bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val)  bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0()    bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1()    bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2()    bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3()    bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH()   bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0()      bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val)  bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1()      bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val)  bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0()    bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1()    bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2()    bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3()    bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH()   bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0()      bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val)  bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1()      bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val)  bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0()    bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1()    bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2()    bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3()    bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH()   bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0()      bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val)  bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1()      bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val)  bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0()    bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1()    bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2()    bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3()    bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH()   bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0()      bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val)  bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1()      bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val)  bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0()    bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1()    bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2()    bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3()    bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH()   bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0()      bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val)  bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1()      bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val)  bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0()    bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1()    bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2()    bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3()    bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH()   bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0()      bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val)  bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1()      bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val)  bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0()    bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1()    bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2()    bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3()    bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH()   bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0()      bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val)  bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1()      bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val)  bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0()    bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1()    bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2()    bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3()    bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH()   bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0()      bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val)  bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1()      bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val)  bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0()    bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1()    bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2()    bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3()    bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH()   bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0()      bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val)  bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1()      bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val)  bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0()    bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1()    bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2()    bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3()    bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH()   bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0()      bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val)  bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1()      bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val)  bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0()    bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1()    bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2()    bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3()    bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH()   bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0()      bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val)  bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1()      bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val)  bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0()    bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1()    bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2()    bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3()    bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH()   bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0()      bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val)  bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1()      bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val)  bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0()    bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1()    bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2()    bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3()    bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH()   bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0()      bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val)  bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1()      bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val)  bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0()    bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1()    bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2()    bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3()    bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH()   bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0()      bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val)  bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1()      bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val)  bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0()    bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1()    bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2()    bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3()    bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH()   bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0()      bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val)  bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1()      bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val)  bfin_write16(CAN1_MB31_ID1, val)
-#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_SPI2_CTL()           bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val)       bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG()           bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val)       bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT()          bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val)      bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR()          bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val)      bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR()          bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val)      bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD()          bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val)      bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW()        bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val)    bfin_write16(SPI2_SHADOW, val)
-#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
-#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
-#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
-#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
-#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
-#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
-#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
-#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
-#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define bfin_read_UART2_DLL()          bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val)      bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH()          bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val)      bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL()         bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val)     bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR()          bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val)      bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR()          bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val)      bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR()          bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val)      bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR()          bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val)      bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR()          bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val)      bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET()      bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val)  bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR()    bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_THR()          bfin_read16(UART2_THR)
-#define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
-#define bfin_read_UART2_RBR()          bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val)      bfin_write16(UART2_RBR, val)
-#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
-#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_EDN_BF549_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h
deleted file mode 100644
index 33c82b4..0000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h
+++ /dev/null
@@ -1,2049 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_EDN_BF549_extended__
-#define __BFIN_DEF_ADSP_EDN_BF549_extended__
-
-#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
-#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
-#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
-#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
-#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
-#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
-#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
-#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
-#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
-#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
-#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
-#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
-#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
-#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
-#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
-#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
-#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
-#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
-#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
-#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
-#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
-#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
-#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
-#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
-#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
-#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
-#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
-#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
-#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
-#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
-#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
-#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
-#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
-#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
-#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
-#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
-#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
-#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
-#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
-#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
-#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
-#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
-#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
-#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
-#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
-#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
-#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
-#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
-#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
-#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
-#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
-#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
-#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
-#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
-#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
-#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
-#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
-#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
-#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
-#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
-#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
-#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
-#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
-#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
-#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
-#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
-#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
-#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
-#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
-#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
-#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
-#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
-#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
-#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
-#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
-#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
-#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
-#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
-#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
-#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
-#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
-#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
-#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
-#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
-#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
-#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
-#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
-#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
-#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
-#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
-#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
-#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
-#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
-#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
-#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
-#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
-#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
-#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
-#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
-#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
-#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
-#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
-#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
-#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
-#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
-#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
-#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
-#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
-#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
-#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
-#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
-#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
-#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
-#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
-#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
-#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
-#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
-#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
-#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
-#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
-#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
-#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
-#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
-#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
-#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
-#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
-#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
-#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
-#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
-#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
-#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
-#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
-#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
-#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
-#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
-#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
-#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
-#define PIXC_CTL                       0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL                       0xFFC04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF                       0xFFC04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART                   0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND                     0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART                   0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND                     0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP                   0xFFC0441C /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART                   0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND                     0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART                   0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND                     0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP                   0xFFC04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT                  0xFFC0443C /* Overlay interrupt configuration/status */
-#define PIXC_RYCON                     0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON                     0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON                     0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS                    0xFFC0444C /* Bias values for the color space conversion matrix */
-#define PIXC_TC                        0xFFC04450 /* Holds the transparent color value */
-#define HOST_CONTROL                   0xFFC03A00 /* HOSTDP Control Register */
-#define HOST_STATUS                    0xFFC03A04 /* HOSTDP Status Register */
-#define HOST_TIMEOUT                   0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
-#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
-#define PORTA                          0xFFC014C4 /* GPIO Data Register */
-#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
-#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
-#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
-#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
-#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
-#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
-#define PORTB                          0xFFC014E4 /* GPIO Data Register */
-#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
-#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
-#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
-#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
-#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
-#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
-#define PORTC                          0xFFC01504 /* GPIO Data Register */
-#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
-#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
-#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
-#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
-#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
-#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
-#define PORTD                          0xFFC01524 /* GPIO Data Register */
-#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
-#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
-#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
-#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
-#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
-#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
-#define PORTE                          0xFFC01544 /* GPIO Data Register */
-#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
-#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
-#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
-#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
-#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
-#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
-#define PORTF                          0xFFC01564 /* GPIO Data Register */
-#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
-#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
-#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
-#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
-#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
-#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
-#define PORTG                          0xFFC01584 /* GPIO Data Register */
-#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
-#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
-#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
-#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
-#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
-#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
-#define PORTH                          0xFFC015A4 /* GPIO Data Register */
-#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
-#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
-#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
-#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
-#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
-#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
-#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
-#define PORTI                          0xFFC015C4 /* GPIO Data Register */
-#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
-#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
-#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
-#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
-#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
-#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
-#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
-#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
-#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
-#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
-#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
-#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
-#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
-#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
-#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
-#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
-#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
-#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
-#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
-#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
-#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
-#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
-#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
-#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
-#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
-#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
-#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
-#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
-#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
-#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
-#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
-#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
-#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
-#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
-#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
-#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
-#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
-#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
-#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
-#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
-#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
-#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
-#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
-#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
-#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
-#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
-#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
-#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
-#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
-#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
-#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
-#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
-#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
-#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
-#define TIMER8_CONFIG                  0xFFC00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER                 0xFFC00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD                  0xFFC00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH                   0xFFC0060C /* Timer 8 Width Register */
-#define TIMER9_CONFIG                  0xFFC00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER                 0xFFC00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD                  0xFFC00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH                   0xFFC0061C /* Timer 9 Width Register */
-#define TIMER10_CONFIG                 0xFFC00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER                0xFFC00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD                 0xFFC00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH                  0xFFC0062C /* Timer 10 Width Register */
-#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
-#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
-#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
-#define TIMER_ENABLE1                  0xFFC00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1                 0xFFC00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1                  0xFFC00648 /* Timer Group of 3 Status Register */
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
-#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
-#define CNT_STATUS                     0xFFC04208 /* Status Register  */
-#define CNT_COMMAND                    0xFFC0420C /* Command Register */
-#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
-#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
-#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
-#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
-#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
-#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
-#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
-#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
-#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
-#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
-#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
-#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
-#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define MXVR_CONFIG                    0xFFC02700 /* MXVR Configuration Register */
-#define MXVR_STATE_0                   0xFFC02708 /* MXVR State Register 0 */
-#define MXVR_STATE_1                   0xFFC0270C /* MXVR State Register 1 */
-#define MXVR_INT_STAT_0                0xFFC02710 /* MXVR Interrupt Status Register 0 */
-#define MXVR_INT_STAT_1                0xFFC02714 /* MXVR Interrupt Status Register 1 */
-#define MXVR_INT_EN_0                  0xFFC02718 /* MXVR Interrupt Enable Register 0 */
-#define MXVR_INT_EN_1                  0xFFC0271C /* MXVR Interrupt Enable Register 1 */
-#define MXVR_POSITION                  0xFFC02720 /* MXVR Node Position Register */
-#define MXVR_MAX_POSITION              0xFFC02724 /* MXVR Maximum Node Position Register */
-#define MXVR_DELAY                     0xFFC02728 /* MXVR Node Frame Delay Register */
-#define MXVR_MAX_DELAY                 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */
-#define MXVR_LADDR                     0xFFC02730 /* MXVR Logical Address Register */
-#define MXVR_GADDR                     0xFFC02734 /* MXVR Group Address Register */
-#define MXVR_AADDR                     0xFFC02738 /* MXVR Alternate Address Register */
-#define MXVR_ALLOC_0                   0xFFC0273C /* MXVR Allocation Table Register 0 */
-#define MXVR_ALLOC_1                   0xFFC02740 /* MXVR Allocation Table Register 1 */
-#define MXVR_ALLOC_2                   0xFFC02744 /* MXVR Allocation Table Register 2 */
-#define MXVR_ALLOC_3                   0xFFC02748 /* MXVR Allocation Table Register 3 */
-#define MXVR_ALLOC_4                   0xFFC0274C /* MXVR Allocation Table Register 4 */
-#define MXVR_ALLOC_5                   0xFFC02750 /* MXVR Allocation Table Register 5 */
-#define MXVR_ALLOC_6                   0xFFC02754 /* MXVR Allocation Table Register 6 */
-#define MXVR_ALLOC_7                   0xFFC02758 /* MXVR Allocation Table Register 7 */
-#define MXVR_ALLOC_8                   0xFFC0275C /* MXVR Allocation Table Register 8 */
-#define MXVR_ALLOC_9                   0xFFC02760 /* MXVR Allocation Table Register 9 */
-#define MXVR_ALLOC_10                  0xFFC02764 /* MXVR Allocation Table Register 10 */
-#define MXVR_ALLOC_11                  0xFFC02768 /* MXVR Allocation Table Register 11 */
-#define MXVR_ALLOC_12                  0xFFC0276C /* MXVR Allocation Table Register 12 */
-#define MXVR_ALLOC_13                  0xFFC02770 /* MXVR Allocation Table Register 13 */
-#define MXVR_ALLOC_14                  0xFFC02774 /* MXVR Allocation Table Register 14 */
-#define MXVR_SYNC_LCHAN_0              0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define MXVR_SYNC_LCHAN_1              0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define MXVR_SYNC_LCHAN_2              0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define MXVR_SYNC_LCHAN_3              0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define MXVR_SYNC_LCHAN_4              0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define MXVR_SYNC_LCHAN_5              0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define MXVR_SYNC_LCHAN_6              0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define MXVR_SYNC_LCHAN_7              0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
-#define MXVR_DMA0_CONFIG               0xFFC02798 /* MXVR Sync Data DMA0 Config Register */
-#define MXVR_DMA0_START_ADDR           0xFFC0279C /* MXVR Sync Data DMA0 Start Address */
-#define MXVR_DMA0_COUNT                0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */
-#define MXVR_DMA0_CURR_ADDR            0xFFC027A4 /* MXVR Sync Data DMA0 Current Address */
-#define MXVR_DMA0_CURR_COUNT           0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count */
-#define MXVR_DMA1_CONFIG               0xFFC027AC /* MXVR Sync Data DMA1 Config Register */
-#define MXVR_DMA1_START_ADDR           0xFFC027B0 /* MXVR Sync Data DMA1 Start Address */
-#define MXVR_DMA1_COUNT                0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */
-#define MXVR_DMA1_CURR_ADDR            0xFFC027B8 /* MXVR Sync Data DMA1 Current Address */
-#define MXVR_DMA1_CURR_COUNT           0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count */
-#define MXVR_DMA2_CONFIG               0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */
-#define MXVR_DMA2_START_ADDR           0xFFC027C4 /* MXVR Sync Data DMA2 Start Address */
-#define MXVR_DMA2_COUNT                0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */
-#define MXVR_DMA2_CURR_ADDR            0xFFC027CC /* MXVR Sync Data DMA2 Current Address */
-#define MXVR_DMA2_CURR_COUNT           0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count */
-#define MXVR_DMA3_CONFIG               0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */
-#define MXVR_DMA3_START_ADDR           0xFFC027D8 /* MXVR Sync Data DMA3 Start Address */
-#define MXVR_DMA3_COUNT                0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */
-#define MXVR_DMA3_CURR_ADDR            0xFFC027E0 /* MXVR Sync Data DMA3 Current Address */
-#define MXVR_DMA3_CURR_COUNT           0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count */
-#define MXVR_DMA4_CONFIG               0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */
-#define MXVR_DMA4_START_ADDR           0xFFC027EC /* MXVR Sync Data DMA4 Start Address */
-#define MXVR_DMA4_COUNT                0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */
-#define MXVR_DMA4_CURR_ADDR            0xFFC027F4 /* MXVR Sync Data DMA4 Current Address */
-#define MXVR_DMA4_CURR_COUNT           0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count */
-#define MXVR_DMA5_CONFIG               0xFFC027FC /* MXVR Sync Data DMA5 Config Register */
-#define MXVR_DMA5_START_ADDR           0xFFC02800 /* MXVR Sync Data DMA5 Start Address */
-#define MXVR_DMA5_COUNT                0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */
-#define MXVR_DMA5_CURR_ADDR            0xFFC02808 /* MXVR Sync Data DMA5 Current Address */
-#define MXVR_DMA5_CURR_COUNT           0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count */
-#define MXVR_DMA6_CONFIG               0xFFC02810 /* MXVR Sync Data DMA6 Config Register */
-#define MXVR_DMA6_START_ADDR           0xFFC02814 /* MXVR Sync Data DMA6 Start Address */
-#define MXVR_DMA6_COUNT                0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */
-#define MXVR_DMA6_CURR_ADDR            0xFFC0281C /* MXVR Sync Data DMA6 Current Address */
-#define MXVR_DMA6_CURR_COUNT           0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count */
-#define MXVR_DMA7_CONFIG               0xFFC02824 /* MXVR Sync Data DMA7 Config Register */
-#define MXVR_DMA7_START_ADDR           0xFFC02828 /* MXVR Sync Data DMA7 Start Address */
-#define MXVR_DMA7_COUNT                0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */
-#define MXVR_DMA7_CURR_ADDR            0xFFC02830 /* MXVR Sync Data DMA7 Current Address */
-#define MXVR_DMA7_CURR_COUNT           0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count */
-#define MXVR_AP_CTL                    0xFFC02838 /* MXVR Async Packet Control Register */
-#define MXVR_APRB_START_ADDR           0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */
-#define MXVR_APRB_CURR_ADDR            0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */
-#define MXVR_APTB_START_ADDR           0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */
-#define MXVR_APTB_CURR_ADDR            0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */
-#define MXVR_CM_CTL                    0xFFC0284C /* MXVR Control Message Control Register */
-#define MXVR_CMRB_START_ADDR           0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */
-#define MXVR_CMRB_CURR_ADDR            0xFFC02854 /* MXVR Control Message RX Buffer Current Address */
-#define MXVR_CMTB_START_ADDR           0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */
-#define MXVR_CMTB_CURR_ADDR            0xFFC0285C /* MXVR Control Message TX Buffer Current Address */
-#define MXVR_RRDB_START_ADDR           0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */
-#define MXVR_RRDB_CURR_ADDR            0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */
-#define MXVR_PAT_DATA_0                0xFFC02868 /* MXVR Pattern Data Register 0 */
-#define MXVR_PAT_EN_0                  0xFFC0286C /* MXVR Pattern Enable Register 0 */
-#define MXVR_PAT_DATA_1                0xFFC02870 /* MXVR Pattern Data Register 1 */
-#define MXVR_PAT_EN_1                  0xFFC02874 /* MXVR Pattern Enable Register 1 */
-#define MXVR_FRAME_CNT_0               0xFFC02878 /* MXVR Frame Counter 0 */
-#define MXVR_FRAME_CNT_1               0xFFC0287C /* MXVR Frame Counter 1 */
-#define MXVR_ROUTING_0                 0xFFC02880 /* MXVR Routing Table Register 0 */
-#define MXVR_ROUTING_1                 0xFFC02884 /* MXVR Routing Table Register 1 */
-#define MXVR_ROUTING_2                 0xFFC02888 /* MXVR Routing Table Register 2 */
-#define MXVR_ROUTING_3                 0xFFC0288C /* MXVR Routing Table Register 3 */
-#define MXVR_ROUTING_4                 0xFFC02890 /* MXVR Routing Table Register 4 */
-#define MXVR_ROUTING_5                 0xFFC02894 /* MXVR Routing Table Register 5 */
-#define MXVR_ROUTING_6                 0xFFC02898 /* MXVR Routing Table Register 6 */
-#define MXVR_ROUTING_7                 0xFFC0289C /* MXVR Routing Table Register 7 */
-#define MXVR_ROUTING_8                 0xFFC028A0 /* MXVR Routing Table Register 8 */
-#define MXVR_ROUTING_9                 0xFFC028A4 /* MXVR Routing Table Register 9 */
-#define MXVR_ROUTING_10                0xFFC028A8 /* MXVR Routing Table Register 10 */
-#define MXVR_ROUTING_11                0xFFC028AC /* MXVR Routing Table Register 11 */
-#define MXVR_ROUTING_12                0xFFC028B0 /* MXVR Routing Table Register 12 */
-#define MXVR_ROUTING_13                0xFFC028B4 /* MXVR Routing Table Register 13 */
-#define MXVR_ROUTING_14                0xFFC028B8 /* MXVR Routing Table Register 14 */
-#define MXVR_BLOCK_CNT                 0xFFC028C0 /* MXVR Block Counter */
-#define MXVR_CLK_CTL                   0xFFC028D0 /* MXVR Clock Control Register */
-#define MXVR_CDRPLL_CTL                0xFFC028D4 /* MXVR Clock/Data Recovery PLL Control Register */
-#define MXVR_FMPLL_CTL                 0xFFC028D8 /* MXVR Frequency Multiply PLL Control Register */
-#define MXVR_PIN_CTL                   0xFFC028DC /* MXVR Pin Control Register */
-#define MXVR_SCLK_CNT                  0xFFC028E0 /* MXVR System Clock Counter Register */
-#define KPAD_CTL                       0xFFC04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE                  0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL                      0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL                    0xFFC0410C /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT                      0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL                  0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
-#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
-#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
-#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
-#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
-#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
-#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
-#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
-#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
-#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
-#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
-#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
-#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
-#define SDH_STATUS                     0xFFC03934 /* SDH Status */
-#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
-#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
-#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
-#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
-#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
-#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
-#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
-#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
-#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
-#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
-#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
-#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
-#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
-#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
-#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
-#define ATAPI_CONTROL                  0xFFC03800 /* ATAPI Control Register */
-#define ATAPI_STATUS                   0xFFC03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR                 0xFFC03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF                0xFFC0380C /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF                0xFFC03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK                 0xFFC03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS               0xFFC03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN                 0xFFC0381C /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS              0xFFC03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE                 0xFFC03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE                0xFFC03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT               0xFFC0382C /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT               0xFFC03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT             0xFFC03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT           0xFFC03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0                0xFFC03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0                0xFFC03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1                0xFFC03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0              0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1              0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2              0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0              0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1              0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2              0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3              0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
-#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
-#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
-#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
-#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
-#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
-#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
-#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
-#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
-#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
-#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
-#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
-#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
-#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
-#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
-#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
-#define EPPI0_STATUS                   0xFFC01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT                   0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY                   0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT                   0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY                   0xFFC01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME                    0xFFC01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE                     0xFFC01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV                   0xFFC0101C /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL                  0xFFC01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL                 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL                0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB                 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF                0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP                     0xFFC01034 /* EPPI0 Clipping Register */
-#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
-#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
-#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
-#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
-#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
-#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
-#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
-#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
-#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
-#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
-#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
-#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
-#define CAN0_MC1                       0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN0_MD1                       0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN0_TRS1                      0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN0_TRR1                      0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN0_TA1                       0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN0_AA1                       0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1                      0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN0_RML1                      0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1                    0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1                    0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1                     0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1                      0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN0_OPSS1                     0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN0_MC2                       0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN0_MD2                       0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN0_TRS2                      0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN0_TRR2                      0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN0_TA2                       0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN0_AA2                       0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2                      0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN0_RML2                      0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2                    0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2                    0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2                     0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2                      0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN0_OPSS2                     0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN0_CLOCK                     0xFFC02A80 /* CAN Controller 0 Clock Register */
-#define CAN0_TIMING                    0xFFC02A84 /* CAN Controller 0 Timing Register */
-#define CAN0_DEBUG                     0xFFC02A88 /* CAN Controller 0 Debug Register */
-#define CAN0_STATUS                    0xFFC02A8C /* CAN Controller 0 Global Status Register */
-#define CAN0_CEC                       0xFFC02A90 /* CAN Controller 0 Error Counter Register */
-#define CAN0_GIS                       0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN0_GIM                       0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN0_GIF                       0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN0_CONTROL                   0xFFC02AA0 /* CAN Controller 0 Master Control Register */
-#define CAN0_INTR                      0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN0_MBTD                      0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN0_EWR                       0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN0_ESR                       0xFFC02AB4 /* CAN Controller 0 Error Status Register */
-#define CAN0_UCCNT                     0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
-#define CAN0_UCRC                      0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN0_UCCNF                     0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
-#define CAN0_AM00L                     0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN0_AM00H                     0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN0_AM01L                     0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN0_AM01H                     0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN0_AM02L                     0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN0_AM02H                     0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN0_AM03L                     0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN0_AM03H                     0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN0_AM04L                     0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN0_AM04H                     0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN0_AM05L                     0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN0_AM05H                     0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN0_AM06L                     0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN0_AM06H                     0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN0_AM07L                     0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN0_AM07H                     0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN0_AM08L                     0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN0_AM08H                     0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN0_AM09L                     0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN0_AM09H                     0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN0_AM10L                     0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN0_AM10H                     0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN0_AM11L                     0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN0_AM11H                     0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN0_AM12L                     0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN0_AM12H                     0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN0_AM13L                     0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN0_AM13H                     0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN0_AM14L                     0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN0_AM14H                     0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN0_AM15L                     0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN0_AM15H                     0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-#define CAN0_AM16L                     0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN0_AM16H                     0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN0_AM17L                     0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN0_AM17H                     0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN0_AM18L                     0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN0_AM18H                     0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN0_AM19L                     0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN0_AM19H                     0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN0_AM20L                     0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN0_AM20H                     0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN0_AM21L                     0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN0_AM21H                     0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN0_AM22L                     0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN0_AM22H                     0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN0_AM23L                     0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN0_AM23H                     0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN0_AM24L                     0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN0_AM24H                     0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN0_AM25L                     0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN0_AM25H                     0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN0_AM26L                     0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN0_AM26H                     0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN0_AM27L                     0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN0_AM27H                     0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN0_AM28L                     0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN0_AM28H                     0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN0_AM29L                     0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN0_AM29H                     0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN0_AM30L                     0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN0_AM30H                     0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN0_AM31L                     0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN0_AM31H                     0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-#define CAN0_MB00_DATA0                0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN0_MB00_DATA1                0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN0_MB00_DATA2                0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN0_MB00_DATA3                0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN0_MB00_LENGTH               0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN0_MB00_TIMESTAMP            0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN0_MB00_ID0                  0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN0_MB00_ID1                  0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN0_MB01_DATA0                0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN0_MB01_DATA1                0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN0_MB01_DATA2                0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN0_MB01_DATA3                0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN0_MB01_LENGTH               0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN0_MB01_TIMESTAMP            0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN0_MB01_ID0                  0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN0_MB01_ID1                  0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN0_MB02_DATA0                0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN0_MB02_DATA1                0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN0_MB02_DATA2                0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN0_MB02_DATA3                0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN0_MB02_LENGTH               0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN0_MB02_TIMESTAMP            0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN0_MB02_ID0                  0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN0_MB02_ID1                  0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN0_MB03_DATA0                0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN0_MB03_DATA1                0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN0_MB03_DATA2                0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN0_MB03_DATA3                0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN0_MB03_LENGTH               0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN0_MB03_TIMESTAMP            0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN0_MB03_ID0                  0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN0_MB03_ID1                  0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN0_MB04_DATA0                0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN0_MB04_DATA1                0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN0_MB04_DATA2                0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN0_MB04_DATA3                0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN0_MB04_LENGTH               0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN0_MB04_TIMESTAMP            0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN0_MB04_ID0                  0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN0_MB04_ID1                  0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN0_MB05_DATA0                0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN0_MB05_DATA1                0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN0_MB05_DATA2                0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN0_MB05_DATA3                0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN0_MB05_LENGTH               0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN0_MB05_TIMESTAMP            0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN0_MB05_ID0                  0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN0_MB05_ID1                  0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN0_MB06_DATA0                0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN0_MB06_DATA1                0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN0_MB06_DATA2                0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN0_MB06_DATA3                0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN0_MB06_LENGTH               0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN0_MB06_TIMESTAMP            0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN0_MB06_ID0                  0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN0_MB06_ID1                  0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN0_MB07_DATA0                0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN0_MB07_DATA1                0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN0_MB07_DATA2                0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN0_MB07_DATA3                0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN0_MB07_LENGTH               0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN0_MB07_TIMESTAMP            0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN0_MB07_ID0                  0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN0_MB07_ID1                  0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN0_MB08_DATA0                0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN0_MB08_DATA1                0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN0_MB08_DATA2                0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN0_MB08_DATA3                0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN0_MB08_LENGTH               0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN0_MB08_TIMESTAMP            0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN0_MB08_ID0                  0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN0_MB08_ID1                  0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN0_MB09_DATA0                0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN0_MB09_DATA1                0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN0_MB09_DATA2                0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN0_MB09_DATA3                0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN0_MB09_LENGTH               0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN0_MB09_TIMESTAMP            0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN0_MB09_ID0                  0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN0_MB09_ID1                  0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN0_MB10_DATA0                0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN0_MB10_DATA1                0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN0_MB10_DATA2                0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN0_MB10_DATA3                0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN0_MB10_LENGTH               0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN0_MB10_TIMESTAMP            0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN0_MB10_ID0                  0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN0_MB10_ID1                  0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN0_MB11_DATA0                0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN0_MB11_DATA1                0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN0_MB11_DATA2                0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN0_MB11_DATA3                0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN0_MB11_LENGTH               0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN0_MB11_TIMESTAMP            0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN0_MB11_ID0                  0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN0_MB11_ID1                  0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN0_MB12_DATA0                0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN0_MB12_DATA1                0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN0_MB12_DATA2                0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN0_MB12_DATA3                0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN0_MB12_LENGTH               0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN0_MB12_TIMESTAMP            0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN0_MB12_ID0                  0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN0_MB12_ID1                  0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN0_MB13_DATA0                0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN0_MB13_DATA1                0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN0_MB13_DATA2                0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN0_MB13_DATA3                0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN0_MB13_LENGTH               0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN0_MB13_TIMESTAMP            0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN0_MB13_ID0                  0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN0_MB13_ID1                  0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN0_MB14_DATA0                0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN0_MB14_DATA1                0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN0_MB14_DATA2                0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN0_MB14_DATA3                0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN0_MB14_LENGTH               0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN0_MB14_TIMESTAMP            0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN0_MB14_ID0                  0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN0_MB14_ID1                  0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN0_MB15_DATA0                0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN0_MB15_DATA1                0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN0_MB15_DATA2                0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN0_MB15_DATA3                0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN0_MB15_LENGTH               0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN0_MB15_TIMESTAMP            0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN0_MB15_ID0                  0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN0_MB15_ID1                  0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
-#define CAN0_MB16_DATA0                0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN0_MB16_DATA1                0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN0_MB16_DATA2                0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN0_MB16_DATA3                0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN0_MB16_LENGTH               0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN0_MB16_TIMESTAMP            0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN0_MB16_ID0                  0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN0_MB16_ID1                  0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN0_MB17_DATA0                0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN0_MB17_DATA1                0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN0_MB17_DATA2                0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN0_MB17_DATA3                0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN0_MB17_LENGTH               0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN0_MB17_TIMESTAMP            0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN0_MB17_ID0                  0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN0_MB17_ID1                  0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN0_MB18_DATA0                0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN0_MB18_DATA1                0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN0_MB18_DATA2                0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN0_MB18_DATA3                0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN0_MB18_LENGTH               0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN0_MB18_TIMESTAMP            0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN0_MB18_ID0                  0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN0_MB18_ID1                  0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN0_MB19_DATA0                0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN0_MB19_DATA1                0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN0_MB19_DATA2                0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN0_MB19_DATA3                0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN0_MB19_LENGTH               0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN0_MB19_TIMESTAMP            0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN0_MB19_ID0                  0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN0_MB19_ID1                  0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN0_MB20_DATA0                0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN0_MB20_DATA1                0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN0_MB20_DATA2                0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN0_MB20_DATA3                0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN0_MB20_LENGTH               0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN0_MB20_TIMESTAMP            0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN0_MB20_ID0                  0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN0_MB20_ID1                  0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN0_MB21_DATA0                0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN0_MB21_DATA1                0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN0_MB21_DATA2                0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN0_MB21_DATA3                0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN0_MB21_LENGTH               0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN0_MB21_TIMESTAMP            0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN0_MB21_ID0                  0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN0_MB21_ID1                  0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN0_MB22_DATA0                0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN0_MB22_DATA1                0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN0_MB22_DATA2                0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN0_MB22_DATA3                0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN0_MB22_LENGTH               0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN0_MB22_TIMESTAMP            0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN0_MB22_ID0                  0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN0_MB22_ID1                  0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN0_MB23_DATA0                0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN0_MB23_DATA1                0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN0_MB23_DATA2                0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN0_MB23_DATA3                0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN0_MB23_LENGTH               0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN0_MB23_TIMESTAMP            0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN0_MB23_ID0                  0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN0_MB23_ID1                  0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN0_MB24_DATA0                0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN0_MB24_DATA1                0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN0_MB24_DATA2                0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN0_MB24_DATA3                0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN0_MB24_LENGTH               0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN0_MB24_TIMESTAMP            0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN0_MB24_ID0                  0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN0_MB24_ID1                  0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN0_MB25_DATA0                0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN0_MB25_DATA1                0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN0_MB25_DATA2                0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN0_MB25_DATA3                0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN0_MB25_LENGTH               0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN0_MB25_TIMESTAMP            0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN0_MB25_ID0                  0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN0_MB25_ID1                  0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN0_MB26_DATA0                0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN0_MB26_DATA1                0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN0_MB26_DATA2                0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN0_MB26_DATA3                0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN0_MB26_LENGTH               0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN0_MB26_TIMESTAMP            0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN0_MB26_ID0                  0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN0_MB26_ID1                  0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN0_MB27_DATA0                0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN0_MB27_DATA1                0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN0_MB27_DATA2                0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN0_MB27_DATA3                0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN0_MB27_LENGTH               0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN0_MB27_TIMESTAMP            0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN0_MB27_ID0                  0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN0_MB27_ID1                  0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN0_MB28_DATA0                0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN0_MB28_DATA1                0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN0_MB28_DATA2                0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN0_MB28_DATA3                0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN0_MB28_LENGTH               0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN0_MB28_TIMESTAMP            0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN0_MB28_ID0                  0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN0_MB28_ID1                  0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN0_MB29_DATA0                0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN0_MB29_DATA1                0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN0_MB29_DATA2                0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN0_MB29_DATA3                0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN0_MB29_LENGTH               0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN0_MB29_TIMESTAMP            0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN0_MB29_ID0                  0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN0_MB29_ID1                  0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN0_MB30_DATA0                0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN0_MB30_DATA1                0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN0_MB30_DATA2                0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN0_MB30_DATA3                0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN0_MB30_LENGTH               0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN0_MB30_TIMESTAMP            0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN0_MB30_ID0                  0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN0_MB30_ID1                  0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN0_MB31_DATA0                0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN0_MB31_DATA1                0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN0_MB31_DATA2                0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN0_MB31_DATA3                0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN0_MB31_LENGTH               0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN0_MB31_TIMESTAMP            0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN0_MB31_ID0                  0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN0_MB31_ID1                  0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
-#define CAN1_MC1                       0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define CAN1_MD1                       0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */
-#define CAN1_TRS1                      0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */
-#define CAN1_TRR1                      0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define CAN1_TA1                       0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define CAN1_AA1                       0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define CAN1_RMP1                      0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */
-#define CAN1_RML1                      0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */
-#define CAN1_MBTIF1                    0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN1_MBRIF1                    0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN1_MBIM1                     0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define CAN1_RFH1                      0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define CAN1_OPSS1                     0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN1_MC2                       0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define CAN1_MD2                       0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */
-#define CAN1_TRS2                      0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */
-#define CAN1_TRR2                      0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define CAN1_TA2                       0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define CAN1_AA2                       0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define CAN1_RMP2                      0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */
-#define CAN1_RML2                      0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */
-#define CAN1_MBTIF2                    0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN1_MBRIF2                    0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN1_MBIM2                     0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define CAN1_RFH2                      0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define CAN1_OPSS2                     0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN1_CLOCK                     0xFFC03280 /* CAN Controller 1 Clock Register */
-#define CAN1_TIMING                    0xFFC03284 /* CAN Controller 1 Timing Register */
-#define CAN1_DEBUG                     0xFFC03288 /* CAN Controller 1 Debug Register */
-#define CAN1_STATUS                    0xFFC0328C /* CAN Controller 1 Global Status Register */
-#define CAN1_CEC                       0xFFC03290 /* CAN Controller 1 Error Counter Register */
-#define CAN1_GIS                       0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */
-#define CAN1_GIM                       0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */
-#define CAN1_GIF                       0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */
-#define CAN1_CONTROL                   0xFFC032A0 /* CAN Controller 1 Master Control Register */
-#define CAN1_INTR                      0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */
-#define CAN1_MBTD                      0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define CAN1_EWR                       0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */
-#define CAN1_ESR                       0xFFC032B4 /* CAN Controller 1 Error Status Register */
-#define CAN1_UCCNT                     0xFFC032C4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC                      0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */
-#define CAN1_UCCNF                     0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */
-#define CAN1_AM00L                     0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define CAN1_AM00H                     0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define CAN1_AM01L                     0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define CAN1_AM01H                     0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define CAN1_AM02L                     0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define CAN1_AM02H                     0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define CAN1_AM03L                     0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define CAN1_AM03H                     0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define CAN1_AM04L                     0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define CAN1_AM04H                     0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define CAN1_AM05L                     0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define CAN1_AM05H                     0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define CAN1_AM06L                     0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define CAN1_AM06H                     0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define CAN1_AM07L                     0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define CAN1_AM07H                     0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define CAN1_AM08L                     0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define CAN1_AM08H                     0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define CAN1_AM09L                     0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define CAN1_AM09H                     0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define CAN1_AM10L                     0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define CAN1_AM10H                     0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define CAN1_AM11L                     0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define CAN1_AM11H                     0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define CAN1_AM12L                     0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define CAN1_AM12H                     0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define CAN1_AM13L                     0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define CAN1_AM13H                     0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define CAN1_AM14L                     0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define CAN1_AM14H                     0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define CAN1_AM15L                     0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define CAN1_AM15H                     0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-#define CAN1_AM16L                     0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define CAN1_AM16H                     0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define CAN1_AM17L                     0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define CAN1_AM17H                     0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define CAN1_AM18L                     0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define CAN1_AM18H                     0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define CAN1_AM19L                     0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define CAN1_AM19H                     0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define CAN1_AM20L                     0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define CAN1_AM20H                     0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define CAN1_AM21L                     0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define CAN1_AM21H                     0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define CAN1_AM22L                     0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define CAN1_AM22H                     0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define CAN1_AM23L                     0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define CAN1_AM23H                     0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define CAN1_AM24L                     0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define CAN1_AM24H                     0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define CAN1_AM25L                     0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define CAN1_AM25H                     0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define CAN1_AM26L                     0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define CAN1_AM26H                     0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define CAN1_AM27L                     0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define CAN1_AM27H                     0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define CAN1_AM28L                     0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define CAN1_AM28H                     0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define CAN1_AM29L                     0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define CAN1_AM29H                     0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define CAN1_AM30L                     0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define CAN1_AM30H                     0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define CAN1_AM31L                     0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define CAN1_AM31H                     0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-#define CAN1_MB00_DATA0                0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define CAN1_MB00_DATA1                0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define CAN1_MB00_DATA2                0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define CAN1_MB00_DATA3                0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define CAN1_MB00_LENGTH               0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */
-#define CAN1_MB00_TIMESTAMP            0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define CAN1_MB00_ID0                  0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define CAN1_MB00_ID1                  0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define CAN1_MB01_DATA0                0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define CAN1_MB01_DATA1                0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define CAN1_MB01_DATA2                0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define CAN1_MB01_DATA3                0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define CAN1_MB01_LENGTH               0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */
-#define CAN1_MB01_TIMESTAMP            0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define CAN1_MB01_ID0                  0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define CAN1_MB01_ID1                  0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define CAN1_MB02_DATA0                0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define CAN1_MB02_DATA1                0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define CAN1_MB02_DATA2                0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define CAN1_MB02_DATA3                0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define CAN1_MB02_LENGTH               0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */
-#define CAN1_MB02_TIMESTAMP            0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define CAN1_MB02_ID0                  0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define CAN1_MB02_ID1                  0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define CAN1_MB03_DATA0                0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define CAN1_MB03_DATA1                0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define CAN1_MB03_DATA2                0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define CAN1_MB03_DATA3                0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define CAN1_MB03_LENGTH               0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */
-#define CAN1_MB03_TIMESTAMP            0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define CAN1_MB03_ID0                  0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define CAN1_MB03_ID1                  0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define CAN1_MB04_DATA0                0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define CAN1_MB04_DATA1                0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define CAN1_MB04_DATA2                0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define CAN1_MB04_DATA3                0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define CAN1_MB04_LENGTH               0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */
-#define CAN1_MB04_TIMESTAMP            0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define CAN1_MB04_ID0                  0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define CAN1_MB04_ID1                  0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define CAN1_MB05_DATA0                0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define CAN1_MB05_DATA1                0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define CAN1_MB05_DATA2                0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define CAN1_MB05_DATA3                0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define CAN1_MB05_LENGTH               0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */
-#define CAN1_MB05_TIMESTAMP            0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define CAN1_MB05_ID0                  0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define CAN1_MB05_ID1                  0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define CAN1_MB06_DATA0                0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define CAN1_MB06_DATA1                0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define CAN1_MB06_DATA2                0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define CAN1_MB06_DATA3                0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define CAN1_MB06_LENGTH               0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */
-#define CAN1_MB06_TIMESTAMP            0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define CAN1_MB06_ID0                  0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define CAN1_MB06_ID1                  0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define CAN1_MB07_DATA0                0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define CAN1_MB07_DATA1                0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define CAN1_MB07_DATA2                0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define CAN1_MB07_DATA3                0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define CAN1_MB07_LENGTH               0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */
-#define CAN1_MB07_TIMESTAMP            0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define CAN1_MB07_ID0                  0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define CAN1_MB07_ID1                  0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define CAN1_MB08_DATA0                0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define CAN1_MB08_DATA1                0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define CAN1_MB08_DATA2                0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define CAN1_MB08_DATA3                0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define CAN1_MB08_LENGTH               0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */
-#define CAN1_MB08_TIMESTAMP            0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define CAN1_MB08_ID0                  0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define CAN1_MB08_ID1                  0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define CAN1_MB09_DATA0                0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define CAN1_MB09_DATA1                0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define CAN1_MB09_DATA2                0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define CAN1_MB09_DATA3                0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define CAN1_MB09_LENGTH               0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */
-#define CAN1_MB09_TIMESTAMP            0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define CAN1_MB09_ID0                  0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define CAN1_MB09_ID1                  0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define CAN1_MB10_DATA0                0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define CAN1_MB10_DATA1                0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define CAN1_MB10_DATA2                0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define CAN1_MB10_DATA3                0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define CAN1_MB10_LENGTH               0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */
-#define CAN1_MB10_TIMESTAMP            0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define CAN1_MB10_ID0                  0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define CAN1_MB10_ID1                  0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define CAN1_MB11_DATA0                0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define CAN1_MB11_DATA1                0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define CAN1_MB11_DATA2                0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define CAN1_MB11_DATA3                0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define CAN1_MB11_LENGTH               0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */
-#define CAN1_MB11_TIMESTAMP            0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define CAN1_MB11_ID0                  0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define CAN1_MB11_ID1                  0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define CAN1_MB12_DATA0                0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define CAN1_MB12_DATA1                0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define CAN1_MB12_DATA2                0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define CAN1_MB12_DATA3                0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define CAN1_MB12_LENGTH               0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */
-#define CAN1_MB12_TIMESTAMP            0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define CAN1_MB12_ID0                  0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define CAN1_MB12_ID1                  0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define CAN1_MB13_DATA0                0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define CAN1_MB13_DATA1                0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define CAN1_MB13_DATA2                0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define CAN1_MB13_DATA3                0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define CAN1_MB13_LENGTH               0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */
-#define CAN1_MB13_TIMESTAMP            0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define CAN1_MB13_ID0                  0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define CAN1_MB13_ID1                  0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define CAN1_MB14_DATA0                0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define CAN1_MB14_DATA1                0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define CAN1_MB14_DATA2                0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define CAN1_MB14_DATA3                0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define CAN1_MB14_LENGTH               0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */
-#define CAN1_MB14_TIMESTAMP            0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define CAN1_MB14_ID0                  0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define CAN1_MB14_ID1                  0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define CAN1_MB15_DATA0                0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define CAN1_MB15_DATA1                0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define CAN1_MB15_DATA2                0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define CAN1_MB15_DATA3                0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define CAN1_MB15_LENGTH               0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */
-#define CAN1_MB15_TIMESTAMP            0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define CAN1_MB15_ID0                  0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define CAN1_MB15_ID1                  0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */
-#define CAN1_MB16_DATA0                0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define CAN1_MB16_DATA1                0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define CAN1_MB16_DATA2                0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define CAN1_MB16_DATA3                0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define CAN1_MB16_LENGTH               0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */
-#define CAN1_MB16_TIMESTAMP            0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define CAN1_MB16_ID0                  0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define CAN1_MB16_ID1                  0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define CAN1_MB17_DATA0                0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define CAN1_MB17_DATA1                0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define CAN1_MB17_DATA2                0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define CAN1_MB17_DATA3                0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define CAN1_MB17_LENGTH               0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */
-#define CAN1_MB17_TIMESTAMP            0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define CAN1_MB17_ID0                  0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define CAN1_MB17_ID1                  0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define CAN1_MB18_DATA0                0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define CAN1_MB18_DATA1                0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define CAN1_MB18_DATA2                0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define CAN1_MB18_DATA3                0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define CAN1_MB18_LENGTH               0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */
-#define CAN1_MB18_TIMESTAMP            0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define CAN1_MB18_ID0                  0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define CAN1_MB18_ID1                  0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define CAN1_MB19_DATA0                0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define CAN1_MB19_DATA1                0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define CAN1_MB19_DATA2                0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define CAN1_MB19_DATA3                0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define CAN1_MB19_LENGTH               0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */
-#define CAN1_MB19_TIMESTAMP            0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define CAN1_MB19_ID0                  0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define CAN1_MB19_ID1                  0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define CAN1_MB20_DATA0                0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define CAN1_MB20_DATA1                0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define CAN1_MB20_DATA2                0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define CAN1_MB20_DATA3                0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define CAN1_MB20_LENGTH               0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */
-#define CAN1_MB20_TIMESTAMP            0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define CAN1_MB20_ID0                  0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define CAN1_MB20_ID1                  0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define CAN1_MB21_DATA0                0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define CAN1_MB21_DATA1                0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define CAN1_MB21_DATA2                0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define CAN1_MB21_DATA3                0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define CAN1_MB21_LENGTH               0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */
-#define CAN1_MB21_TIMESTAMP            0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define CAN1_MB21_ID0                  0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define CAN1_MB21_ID1                  0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define CAN1_MB22_DATA0                0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define CAN1_MB22_DATA1                0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define CAN1_MB22_DATA2                0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define CAN1_MB22_DATA3                0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define CAN1_MB22_LENGTH               0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */
-#define CAN1_MB22_TIMESTAMP            0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define CAN1_MB22_ID0                  0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define CAN1_MB22_ID1                  0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define CAN1_MB23_DATA0                0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define CAN1_MB23_DATA1                0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define CAN1_MB23_DATA2                0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define CAN1_MB23_DATA3                0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define CAN1_MB23_LENGTH               0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */
-#define CAN1_MB23_TIMESTAMP            0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define CAN1_MB23_ID0                  0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define CAN1_MB23_ID1                  0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define CAN1_MB24_DATA0                0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define CAN1_MB24_DATA1                0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define CAN1_MB24_DATA2                0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define CAN1_MB24_DATA3                0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define CAN1_MB24_LENGTH               0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */
-#define CAN1_MB24_TIMESTAMP            0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define CAN1_MB24_ID0                  0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define CAN1_MB24_ID1                  0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define CAN1_MB25_DATA0                0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define CAN1_MB25_DATA1                0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define CAN1_MB25_DATA2                0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define CAN1_MB25_DATA3                0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define CAN1_MB25_LENGTH               0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */
-#define CAN1_MB25_TIMESTAMP            0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define CAN1_MB25_ID0                  0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define CAN1_MB25_ID1                  0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define CAN1_MB26_DATA0                0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define CAN1_MB26_DATA1                0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define CAN1_MB26_DATA2                0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define CAN1_MB26_DATA3                0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define CAN1_MB26_LENGTH               0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */
-#define CAN1_MB26_TIMESTAMP            0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define CAN1_MB26_ID0                  0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define CAN1_MB26_ID1                  0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define CAN1_MB27_DATA0                0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define CAN1_MB27_DATA1                0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define CAN1_MB27_DATA2                0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define CAN1_MB27_DATA3                0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define CAN1_MB27_LENGTH               0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */
-#define CAN1_MB27_TIMESTAMP            0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define CAN1_MB27_ID0                  0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define CAN1_MB27_ID1                  0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define CAN1_MB28_DATA0                0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define CAN1_MB28_DATA1                0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define CAN1_MB28_DATA2                0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define CAN1_MB28_DATA3                0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define CAN1_MB28_LENGTH               0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */
-#define CAN1_MB28_TIMESTAMP            0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define CAN1_MB28_ID0                  0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define CAN1_MB28_ID1                  0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define CAN1_MB29_DATA0                0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define CAN1_MB29_DATA1                0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define CAN1_MB29_DATA2                0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define CAN1_MB29_DATA3                0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define CAN1_MB29_LENGTH               0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */
-#define CAN1_MB29_TIMESTAMP            0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define CAN1_MB29_ID0                  0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define CAN1_MB29_ID1                  0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define CAN1_MB30_DATA0                0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define CAN1_MB30_DATA1                0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define CAN1_MB30_DATA2                0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define CAN1_MB30_DATA3                0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define CAN1_MB30_LENGTH               0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */
-#define CAN1_MB30_TIMESTAMP            0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define CAN1_MB30_ID0                  0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define CAN1_MB30_ID1                  0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define CAN1_MB31_DATA0                0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define CAN1_MB31_DATA1                0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define CAN1_MB31_DATA2                0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define CAN1_MB31_DATA3                0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define CAN1_MB31_LENGTH               0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */
-#define CAN1_MB31_TIMESTAMP            0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define CAN1_MB31_ID0                  0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define CAN1_MB31_ID1                  0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */
-#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
-#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
-#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
-#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
-#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
-#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
-#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
-#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
-#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
-#define SPI2_CTL                       0xFFC02400 /* SPI2 Control Register */
-#define SPI2_FLG                       0xFFC02404 /* SPI2 Flag Register */
-#define SPI2_STAT                      0xFFC02408 /* SPI2 Status Register */
-#define SPI2_TDBR                      0xFFC0240C /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR                      0xFFC02410 /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD                      0xFFC02414 /* SPI2 Baud Rate Register */
-#define SPI2_SHADOW                    0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */
-#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
-#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
-#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
-#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
-#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
-#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
-#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
-#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
-#define TWI1_CLKDIV                    0xFFC02200 /* Clock Divider Register */
-#define TWI1_CONTROL                   0xFFC02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL                 0xFFC02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT                0xFFC0220C /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR                0xFFC02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL                0xFFC02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT               0xFFC02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR               0xFFC0221C /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT                  0xFFC02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK                  0xFFC02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL                  0xFFC02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT                 0xFFC0222C /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8                 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16                0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8                 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16                0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
-#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */
-#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */
-#define SPORT0_TX                      0xFFC00810 /* SPORT0 Transmit Data Register */
-#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Receive Configuration 1 Register */
-#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Receive Configuration 2 Register */
-#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */
-#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */
-#define SPORT0_RX                      0xFFC00818 /* SPORT0 Receive Data Register */
-#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */
-#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */
-#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */
-#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */
-#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */
-#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */
-#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */
-#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
-#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
-#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
-#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
-#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
-#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
-#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
-#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
-#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
-#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
-#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
-#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
-#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
-#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
-#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
-#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
-#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
-#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
-#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
-#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
-#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
-#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
-#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
-#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
-#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
-#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
-#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
-#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
-#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
-#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
-#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
-#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
-#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
-#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
-#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
-#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
-#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
-#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
-#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
-#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
-#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
-#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
-#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
-#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
-#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
-#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
-#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
-#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
-#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
-#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
-#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
-#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
-#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
-#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
-#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
-#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
-#define UART0_LCR                      0xFFC0040C /* Line Control Register */
-#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
-#define UART0_LSR                      0xFFC00414 /* Line Status Register */
-#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
-#define UART0_SCR                      0xFFC0041C /* Scratch Register */
-#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
-#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
-#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
-#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
-#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
-#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
-#define UART1_LCR                      0xFFC0200C /* Line Control Register */
-#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
-#define UART1_LSR                      0xFFC02014 /* Line Status Register */
-#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
-#define UART1_SCR                      0xFFC0201C /* Scratch Register */
-#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
-#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
-#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
-#define UART2_DLL                      0xFFC02100 /* Divisor Latch Low Byte */
-#define UART2_DLH                      0xFFC02104 /* Divisor Latch High Byte */
-#define UART2_GCTL                     0xFFC02108 /* Global Control Register */
-#define UART2_LCR                      0xFFC0210C /* Line Control Register */
-#define UART2_MCR                      0xFFC02110 /* Modem Control Register */
-#define UART2_LSR                      0xFFC02114 /* Line Status Register */
-#define UART2_MSR                      0xFFC02118 /* Modem Status Register */
-#define UART2_SCR                      0xFFC0211C /* Scratch Register */
-#define UART2_IER_SET                  0xFFC02120 /* Interrupt Enable Register Set */
-#define UART2_IER_CLEAR                0xFFC02124 /* Interrupt Enable Register Clear */
-#define UART2_THR                      0xFFC02128 /* Transmit Hold Register */
-#define UART2_RBR                      0xFFC0212C /* Receive Buffer Register */
-#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
-#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
-#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
-#define UART3_LCR                      0xFFC0310C /* Line Control Register */
-#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
-#define UART3_LSR                      0xFFC03114 /* Line Status Register */
-#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
-#define UART3_SCR                      0xFFC0311C /* Scratch Register */
-#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
-#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
-#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
-#define USB_FADDR                      0xFFC03C00 /* Function address register */
-#define USB_POWER                      0xFFC03C04 /* Power management register */
-#define USB_INTRTX                     0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX                     0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE                    0xFFC03C10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE                    0xFFC03C14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB                    0xFFC03C18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE                   0xFFC03C1C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME                      0xFFC03C20 /* USB frame number */
-#define USB_INDEX                      0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE                   0xFFC03C28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR                   0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL                 0xFFC03C30 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET              0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0                       0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR                      0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET              0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR                      0xFFC03C4C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0                     0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT                    0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE                     0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0                  0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL                 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE                     0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL                 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT                    0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO                   0xFFC03C80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO                   0xFFC03C88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO                   0xFFC03C90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO                   0xFFC03C98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO                   0xFFC03CA0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO                   0xFFC03CA8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO                   0xFFC03CB0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO                   0xFFC03CB8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL                0xFFC03D00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ               0xFFC03D04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK              0xFFC03D08 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO                   0xFFC03D48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN                      0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1                    0xFFC03D50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1                    0xFFC03D54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1                    0xFFC03D58 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL                 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB                 0xFFC03DE4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2                0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST                   0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL                0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV                 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP              0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR               0xFFC03E04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP              0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR               0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT             0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE              0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL          0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE              0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL          0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT             0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP              0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR               0xFFC03E44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP              0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR               0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT             0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE              0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL          0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE              0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL          0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT             0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP              0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR               0xFFC03E84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP              0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR               0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT             0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE              0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL          0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE              0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL          0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT             0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP              0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR               0xFFC03EC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP              0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR               0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT             0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE              0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL          0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE              0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL          0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT             0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP              0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR               0xFFC03F04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP              0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR               0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT             0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE              0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL          0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE              0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL          0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT             0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP              0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR               0xFFC03F44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP              0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR               0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT             0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE              0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL          0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE              0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL          0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT             0xFFC03F68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP              0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR               0xFFC03F84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP              0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR               0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT             0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE              0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL          0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE              0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL          0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT             0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP              0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR               0xFFC03FC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP              0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR               0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT             0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE              0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL          0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE              0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL          0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT             0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT              0xFFC04000 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL               0xFFC04004 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW               0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH              0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW              0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH             0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL               0xFFC04024 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW               0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH              0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW              0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH             0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL               0xFFC04044 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW               0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH              0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW              0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH             0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL               0xFFC04064 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW               0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH              0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW              0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH             0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL               0xFFC04084 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW               0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH              0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW              0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH             0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL               0xFFC040A4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW               0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH              0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW              0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH             0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL               0xFFC040C4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW               0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH              0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW              0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH             0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL               0xFFC040E4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW               0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH              0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW              0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH             0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_EDN_BF549_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h
deleted file mode 100644
index fbd3092..0000000
--- a/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF542_proc__
-#define __BFIN_CDEF_ADSP_BF542_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF542-extended_cdef.h"
-
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF542_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF542_def.h b/arch/blackfin/include/asm/mach-bf548/BF542_def.h
deleted file mode 100644
index 38452ff..0000000
--- a/arch/blackfin/include/asm/mach-bf548/BF542_def.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF542_proc__
-#define __BFIN_DEF_ADSP_BF542_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF542-extended_def.h"
-
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-
-#endif /* __BFIN_DEF_ADSP_BF542_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h
deleted file mode 100644
index ef26af3..0000000
--- a/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF544_proc__
-#define __BFIN_CDEF_ADSP_BF544_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF544-extended_cdef.h"
-
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF544_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF544_def.h b/arch/blackfin/include/asm/mach-bf548/BF544_def.h
deleted file mode 100644
index c12e9be..0000000
--- a/arch/blackfin/include/asm/mach-bf548/BF544_def.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF544_proc__
-#define __BFIN_DEF_ADSP_BF544_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF544-extended_def.h"
-
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-
-#endif /* __BFIN_DEF_ADSP_BF544_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h
deleted file mode 100644
index 3f1ff8b..0000000
--- a/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF547_proc__
-#define __BFIN_CDEF_ADSP_BF547_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF547-extended_cdef.h"
-
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF547_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF547_def.h b/arch/blackfin/include/asm/mach-bf548/BF547_def.h
deleted file mode 100644
index e1f666b1..0000000
--- a/arch/blackfin/include/asm/mach-bf548/BF547_def.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF547_proc__
-#define __BFIN_DEF_ADSP_BF547_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF547-extended_def.h"
-
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-
-#endif /* __BFIN_DEF_ADSP_BF547_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h
deleted file mode 100644
index c8be3af..0000000
--- a/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF548_proc__
-#define __BFIN_CDEF_ADSP_BF548_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF548-extended_cdef.h"
-
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF548_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF548_def.h b/arch/blackfin/include/asm/mach-bf548/BF548_def.h
deleted file mode 100644
index 48b257c..0000000
--- a/arch/blackfin/include/asm/mach-bf548/BF548_def.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF548_proc__
-#define __BFIN_DEF_ADSP_BF548_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF548-extended_def.h"
-
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-
-#endif /* __BFIN_DEF_ADSP_BF548_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h
deleted file mode 100644
index 212d54e..0000000
--- a/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF549_proc__
-#define __BFIN_CDEF_ADSP_BF549_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF549-extended_cdef.h"
-
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF549_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF549_def.h b/arch/blackfin/include/asm/mach-bf548/BF549_def.h
deleted file mode 100644
index 22f4a88..0000000
--- a/arch/blackfin/include/asm/mach-bf548/BF549_def.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF549_proc__
-#define __BFIN_DEF_ADSP_BF549_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF549-extended_def.h"
-
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-
-#endif /* __BFIN_DEF_ADSP_BF549_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/anomaly.h b/arch/blackfin/include/asm/mach-bf548/anomaly.h
deleted file mode 100644
index 021fb19..0000000
--- a/arch/blackfin/include/asm/mach-bf548/anomaly.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- *  - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.0 or 0.1 silicon - sorry */
-/* XXX: let u-boot slide
-#if __SILICON_REVISION__ < 2
-# error will not work on BF548 silicon version 0.0, or 0.1
-#endif
-*/
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* FIFO Boot Mode Not Functional */
-#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
-/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-/*
- * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
- *       shows that the fix itself does not cover all cases.
- */
-#define ANOMALY_05000353 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* External Memory Read Access Hangs Core With PLL Bypass */
-#define ANOMALY_05000360 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000365 (1)
-/* Addressing Conflict between Boot ROM and Asynchronous Memory */
-#define ANOMALY_05000369 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
-/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
-#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
-/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
-#define ANOMALY_05000379 (1)
-/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
-#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
-/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
-/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
-/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
-#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
-/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
-#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
-#define ANOMALY_05000446 (1)
-/* UART IrDA Receiver Fails on Extended Bit Pulses */
-#define ANOMALY_05000447 (1)
-/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
-#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
-/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
-#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
-/* USB DMA Short Packet Data Corruption */
-#define ANOMALY_05000450 (1)
-/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (1)
-/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
-#define ANOMALY_05000457 (1)
-/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
-/* USB DMA RX Data Corruption */
-#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
-/* USB TX DMA Hang */
-#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
-/* USB Rx DMA Hang */
-#define ANOMALY_05000465 (1)
-/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
-/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
-#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
-#define ANOMALY_05000483 (1)
-/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
-#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
-#define ANOMALY_05000500 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
-#define ANOMALY_05000502 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
-/* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
-/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
-#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
-/* Synchronous Burst Flash Boot Mode Is Not Functional */
-#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
-/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
-#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
-/* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
-/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
-#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
-/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
-/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
-#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
-/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
-#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0x5411
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
-/* Data Lost when Core Reads SDH Data FIFO */
-#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
-/* PLL Status Register Is Inaccurate */
-#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
-/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
-#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
-/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
-#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
-/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
-#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
-/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
-#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
-/* Changed Meaning of BCODE Field in SYSCR Register */
-#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
-/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
-#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000254 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf548/def_local.h b/arch/blackfin/include/asm/mach-bf548/def_local.h
deleted file mode 100644
index f1e69a7..0000000
--- a/arch/blackfin/include/asm/mach-bf548/def_local.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#include "gpio.h"
-#include "mem_map.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define CONFIG_BF54x 1	/* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf548/gpio.h b/arch/blackfin/include/asm/mach-bf548/gpio.h
deleted file mode 100644
index 28037e3..0000000
--- a/arch/blackfin/include/asm/mach-bf548/gpio.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define GPIO_PA0	0
-#define GPIO_PA1	1
-#define GPIO_PA2	2
-#define GPIO_PA3	3
-#define GPIO_PA4	4
-#define GPIO_PA5	5
-#define GPIO_PA6	6
-#define GPIO_PA7	7
-#define GPIO_PA8	8
-#define GPIO_PA9	9
-#define GPIO_PA10	10
-#define GPIO_PA11	11
-#define GPIO_PA12	12
-#define GPIO_PA13	13
-#define GPIO_PA14	14
-#define GPIO_PA15	15
-#define GPIO_PB0	16
-#define GPIO_PB1	17
-#define GPIO_PB2	18
-#define GPIO_PB3	19
-#define GPIO_PB4	20
-#define GPIO_PB5	21
-#define GPIO_PB6	22
-#define GPIO_PB7	23
-#define GPIO_PB8	24
-#define GPIO_PB9	25
-#define GPIO_PB10	26
-#define GPIO_PB11	27
-#define GPIO_PB12	28
-#define GPIO_PB13	29
-#define GPIO_PB14	30
-#define GPIO_PB15	31	/* N/A */
-#define GPIO_PC0	32
-#define GPIO_PC1	33
-#define GPIO_PC2	34
-#define GPIO_PC3	35
-#define GPIO_PC4	36
-#define GPIO_PC5	37
-#define GPIO_PC6	38
-#define GPIO_PC7	39
-#define GPIO_PC8	40
-#define GPIO_PC9	41
-#define GPIO_PC10	42
-#define GPIO_PC11	43
-#define GPIO_PC12	44
-#define GPIO_PC13	45
-#define GPIO_PC14	46	/* N/A */
-#define GPIO_PC15	47	/* N/A */
-#define GPIO_PD0	48
-#define GPIO_PD1	49
-#define GPIO_PD2	50
-#define GPIO_PD3	51
-#define GPIO_PD4	52
-#define GPIO_PD5	53
-#define GPIO_PD6	54
-#define GPIO_PD7	55
-#define GPIO_PD8	56
-#define GPIO_PD9	57
-#define GPIO_PD10	58
-#define GPIO_PD11	59
-#define GPIO_PD12	60
-#define GPIO_PD13	61
-#define GPIO_PD14	62
-#define GPIO_PD15	63
-#define GPIO_PE0	64
-#define GPIO_PE1	65
-#define GPIO_PE2	66
-#define GPIO_PE3	67
-#define GPIO_PE4	68
-#define GPIO_PE5	69
-#define GPIO_PE6	70
-#define GPIO_PE7	71
-#define GPIO_PE8	72
-#define GPIO_PE9	73
-#define GPIO_PE10	74
-#define GPIO_PE11	75
-#define GPIO_PE12	76
-#define GPIO_PE13	77
-#define GPIO_PE14	78
-#define GPIO_PE15	79
-#define GPIO_PF0	80
-#define GPIO_PF1	81
-#define GPIO_PF2	82
-#define GPIO_PF3	83
-#define GPIO_PF4	84
-#define GPIO_PF5	85
-#define GPIO_PF6	86
-#define GPIO_PF7	87
-#define GPIO_PF8	88
-#define GPIO_PF9	89
-#define GPIO_PF10	90
-#define GPIO_PF11	91
-#define GPIO_PF12	92
-#define GPIO_PF13	93
-#define GPIO_PF14	94
-#define GPIO_PF15	95
-#define GPIO_PG0	96
-#define GPIO_PG1	97
-#define GPIO_PG2	98
-#define GPIO_PG3	99
-#define GPIO_PG4	100
-#define GPIO_PG5	101
-#define GPIO_PG6	102
-#define GPIO_PG7	103
-#define GPIO_PG8	104
-#define GPIO_PG9	105
-#define GPIO_PG10	106
-#define GPIO_PG11	107
-#define GPIO_PG12	108
-#define GPIO_PG13	109
-#define GPIO_PG14	110
-#define GPIO_PG15	111
-#define GPIO_PH0	112
-#define GPIO_PH1	113
-#define GPIO_PH2	114
-#define GPIO_PH3	115
-#define GPIO_PH4	116
-#define GPIO_PH5	117
-#define GPIO_PH6	118
-#define GPIO_PH7	119
-#define GPIO_PH8	120
-#define GPIO_PH9	121
-#define GPIO_PH10	122
-#define GPIO_PH11	123
-#define GPIO_PH12	124
-#define GPIO_PH13	125
-#define GPIO_PH14	126	/* N/A */
-#define GPIO_PH15	127	/* N/A */
-#define GPIO_PI0	128
-#define GPIO_PI1	129
-#define GPIO_PI2	130
-#define GPIO_PI3	131
-#define GPIO_PI4	132
-#define GPIO_PI5	133
-#define GPIO_PI6	134
-#define GPIO_PI7	135
-#define GPIO_PI8	136
-#define GPIO_PI9	137
-#define GPIO_PI10	138
-#define GPIO_PI11	139
-#define GPIO_PI12	140
-#define GPIO_PI13	141
-#define GPIO_PI14	142
-#define GPIO_PI15	143
-#define GPIO_PJ0	144
-#define GPIO_PJ1	145
-#define GPIO_PJ2	146
-#define GPIO_PJ3	147
-#define GPIO_PJ4	148
-#define GPIO_PJ5	149
-#define GPIO_PJ6	150
-#define GPIO_PJ7	151
-#define GPIO_PJ8	152
-#define GPIO_PJ9	153
-#define GPIO_PJ10	154
-#define GPIO_PJ11	155
-#define GPIO_PJ12	156
-#define GPIO_PJ13	157
-#define GPIO_PJ14	158	/* N/A */
-#define GPIO_PJ15	159	/* N/A */
-
-#define MAX_BLACKFIN_GPIOS 160
-
-#ifndef __ASSEMBLY__
-
-struct gpio_port_t {
-	unsigned short port_fer;
-	unsigned short dummy1;
-	unsigned short data;
-	unsigned short dummy2;
-	unsigned short data_set;
-	unsigned short dummy3;
-	unsigned short data_clear;
-	unsigned short dummy4;
-	unsigned short dir_set;
-	unsigned short dummy5;
-	unsigned short dir_clear;
-	unsigned short dummy6;
-	unsigned short inen;
-	unsigned short dummy7;
-	unsigned int port_mux;
-};
-
-struct gpio_port_s {
-	unsigned short fer;
-	unsigned short data;
-	unsigned short dir;
-	unsigned short inen;
-	unsigned int mux;
-};
-
-#endif
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf548/mem_map.h b/arch/blackfin/include/asm/mach-bf548/mem_map.h
deleted file mode 100644
index 4f94397..0000000
--- a/arch/blackfin/include/asm/mach-bf548/mem_map.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Common Blackfin memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BF54X_MEM_MAP_H__
-#define __BF54X_MEM_MAP_H__
-
-#define L1_DATA_A_SRAM      (0xFF800000)
-#define L1_DATA_A_SRAM_SIZE (0x4000)
-#define L1_DATA_A_SRAM_END  (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM      (0xFF900000)
-#define L1_DATA_B_SRAM_SIZE (0x4000)
-#define L1_DATA_B_SRAM_END  (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#define L1_INST_SRAM        (0xFFA00000)
-#define L1_INST_SRAM_SIZE   (0xC000)
-#define L1_INST_SRAM_END    (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf548/portmux.h b/arch/blackfin/include/asm/mach-bf548/portmux.h
deleted file mode 100644
index e222462..0000000
--- a/arch/blackfin/include/asm/mach-bf548/portmux.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
-
-#define P_SPORT2_TFS	(P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_SPORT2_DTSEC	(P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_SPORT2_DTPRI	(P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_SPORT2_TSCLK	(P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_SPORT2_RFS	(P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_SPORT2_DRSEC	(P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_SPORT2_DRPRI	(P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_SPORT2_RSCLK	(P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_SPORT3_TFS	(P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_SPORT3_DTSEC	(P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_SPORT3_DTPRI	(P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_SPORT3_TSCLK	(P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_SPORT3_RFS	(P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_SPORT3_DRSEC	(P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_SPORT3_DRPRI	(P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_SPORT3_RSCLK	(P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_TMR4	(P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_TMR5	(P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_TMR6	(P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_TMR7	(P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-
-#define P_TWI1_SCL	(P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-#define P_TWI1_SDA	(P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_UART3_RTS	(P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_UART3_CTS	(P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_UART2_TX	(P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_UART2_RX	(P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-#define P_UART3_TX	(P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_UART3_RX	(P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_SPI2_SS	(P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_SPI2_SSEL1	(P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
-#define P_SPI2_SSEL2	(P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_SPI2_SSEL3	(P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_SPI2_SCK	(P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
-#define P_SPI2_MOSI	(P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_SPI2_MISO	(P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-#define P_TMR0	(P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_TMR1	(P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
-#define P_TMR2	(P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
-#define P_TMR3	(P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
-
-#define P_SPORT0_TFS	(P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_SPORT0_DTSEC	(P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_SPORT0_DTPRI	(P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_SPORT0_RFS	(P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_SPORT0_DRSEC	(P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_SPORT0_DRPRI	(P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_SPORT0_RSCLK	(P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_SD_D0	(P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
-#define P_SD_D1	(P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_SD_D2	(P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
-#define P_SD_D3	(P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
-#define P_SD_CLK	(P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-#define P_SD_CMD	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_MMCLK	(P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_MBCLK	(P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-
-#define P_PPI1_D0	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_PPI1_D1	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-#define P_PPI1_D2	(P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_PPI1_D3	(P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_PPI1_D4	(P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_PPI1_D5	(P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_PPI1_D6	(P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_PPI1_D7	(P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
-#define P_PPI1_D8	(P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
-#define P_PPI1_D9	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_PPI1_D10	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_PPI1_D11	(P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_PPI1_D12	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_PPI1_D13	(P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_PPI1_D14	(P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_PPI1_D15	(P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
-
-#define P_HOST_D8	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_HOST_D9	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_HOST_D10	(P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
-#define P_HOST_D11	(P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
-#define P_HOST_D12	(P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
-#define P_HOST_D13	(P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
-#define P_HOST_D14	(P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_HOST_D15	(P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_HOST_D0	(P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_HOST_D1	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_HOST_D2	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-#define P_HOST_D3	(P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
-#define P_HOST_D4	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_HOST_D5	(P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
-#define P_HOST_D6	(P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
-#define P_HOST_D7	(P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_SPORT1_TFS	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPORT1_DTSEC	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPORT1_DTPRI	(P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
-#define P_SPORT1_TSCLK	(P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
-#define P_SPORT1_RFS	(P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
-#define P_SPORT1_DRSEC	(P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
-#define P_SPORT1_DRPRI	(P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
-#define P_SPORT1_RSCLK	(P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
-#define P_PPI2_D0	(P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
-#define P_PPI2_D1	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_PPI2_D2	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_PPI2_D3	(P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
-#define P_PPI2_D4	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
-#define P_PPI2_D5	(P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
-#define P_PPI2_D6	(P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
-#define P_PPI2_D7	(P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_PPI0_D18	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
-#define P_PPI0_D19	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
-#define P_PPI0_D20	(P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
-#define P_PPI0_D21	(P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
-#define P_PPI0_D22	(P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
-#define P_PPI0_D23	(P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
-#define P_KEY_ROW0	(P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
-#define P_KEY_ROW1	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
-#define P_KEY_ROW2	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
-#define P_KEY_ROW3	(P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_KEY_COL0	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_KEY_COL1	(P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
-#define P_KEY_COL2	(P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
-#define P_KEY_COL3	(P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-#define P_SPI0_SCK	(P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-#define P_SPI0_MISO	(P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI0_MOSI	(P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
-#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
-#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
-#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
-#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
-#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
-#define P_UART1_RTS	(P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
-#define P_UART1_CTS	(P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_PPI1_CLK	(P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_PPI1_FS1	(P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_PPI1_FS2	(P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_TWI0_SCL	(P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_TWI0_SDA	(P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_KEY_COL7	(P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_KEY_ROW6	(P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_KEY_COL6	(P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_KEY_ROW5	(P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_KEY_COL5	(P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_KEY_ROW4	(P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_KEY_COL4	(P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-#define P_KEY_ROW7	(P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-
-#define P_PPI0_D0	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
-# define P_ATAPI_D0A	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-# define P_ATAPI_D1A	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-# define P_ATAPI_D2A	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-# define P_ATAPI_D3A	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-# define P_ATAPI_D4A	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-# define P_ATAPI_D5A	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-# define P_ATAPI_D6A	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-# define P_ATAPI_D7A	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-# define P_ATAPI_D8A	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-# define P_ATAPI_D9A	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-# define P_ATAPI_D10A	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-# define P_ATAPI_D11A	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-# define P_ATAPI_D12A	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-# define P_ATAPI_D13A	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-# define P_ATAPI_D14A	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-# define P_ATAPI_D15A	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#else
-# define P_ATAPI_D0A	(P_DONTCARE)
-# define P_ATAPI_D1A	(P_DONTCARE)
-# define P_ATAPI_D2A	(P_DONTCARE)
-# define P_ATAPI_D3A	(P_DONTCARE)
-# define P_ATAPI_D4A	(P_DONTCARE)
-# define P_ATAPI_D5A	(P_DONTCARE)
-# define P_ATAPI_D6A	(P_DONTCARE)
-# define P_ATAPI_D7A	(P_DONTCARE)
-# define P_ATAPI_D8A	(P_DONTCARE)
-# define P_ATAPI_D9A	(P_DONTCARE)
-# define P_ATAPI_D10A	(P_DONTCARE)
-# define P_ATAPI_D11A	(P_DONTCARE)
-# define P_ATAPI_D12A	(P_DONTCARE)
-# define P_ATAPI_D13A	(P_DONTCARE)
-# define P_ATAPI_D14A	(P_DONTCARE)
-# define P_ATAPI_D15A	(P_DONTCARE)
-#endif
-
-#define P_PPI0_CLK	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_FS1	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_FS2	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D16	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D17	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPI1_SSEL1	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPI1_SSEL2	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPI1_SSEL3	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPI1_SCK	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPI1_MISO	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPI1_MOSI	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_SPI1_SS	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_CAN0_TX	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_CAN0_RX	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_CAN1_TX	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_CAN1_RX	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
-# define P_ATAPI_A0A	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-# define P_ATAPI_A1A	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-# define P_ATAPI_A2A	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#else
-# define P_ATAPI_A0A	(P_DONTCARE)
-# define P_ATAPI_A1A	(P_DONTCARE)
-# define P_ATAPI_A2A	(P_DONTCARE)
-#endif
-#define P_HOST_CE	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_HOST_RD	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_HOST_WR	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_MTXONB	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_PPI2_FS2	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_PPI2_FS1	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_PPI2_CLK	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_CNT_CZM	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
-
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_ATAPI_RESET	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_HOST_ADDR	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_HOST_ACK	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MTX	(P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MRX	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MRXONB	(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_A4	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_A5	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_A6	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_A7	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_A8	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_A9	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_PPI1_FS3	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_PPI2_FS3	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_TMR8	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_TMR9	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_TMR10	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_DMAR0	(P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_DMAR1	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_CNT_CDG	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_CNT_CUD	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-
-#define P_A10	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
-#define P_A11	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
-#define P_A12	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
-#define P_A13	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
-#define P_A14	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
-#define P_A15	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
-#define P_A16	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
-#define P_A17	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
-#define P_A18	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
-#define P_A19	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
-#define P_A20	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
-#define P_A21	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
-#define P_A22	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
-#define P_A23	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
-#define P_A24	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
-#define P_A25	(P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
-#define P_NOR_CLK	(P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
-
-#define P_AMC_ARDY_NOR_WAIT	(P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
-#define P_NAND_CE	(P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
-#define P_NAND_RB	(P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
-#define P_ATAPI_DIOR	(P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
-#define P_ATAPI_DIOW	(P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
-#define P_ATAPI_CS0	(P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
-#define P_ATAPI_CS1	(P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
-#define P_ATAPI_DMACK	(P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
-#define P_ATAPI_DMARQ	(P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
-#define P_ATAPI_INTRQ	(P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
-#define P_ATAPI_IORDY	(P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
-#define P_AMC_BR	(P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
-#define P_AMC_BG	(P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
-#define P_AMC_BGH	(P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
-
-
-#define P_NAND_D0	(P_DONTCARE)
-#define P_NAND_D1	(P_DONTCARE)
-#define P_NAND_D2	(P_DONTCARE)
-#define P_NAND_D3	(P_DONTCARE)
-#define P_NAND_D4	(P_DONTCARE)
-#define P_NAND_D5	(P_DONTCARE)
-#define P_NAND_D6	(P_DONTCARE)
-#define P_NAND_D7	(P_DONTCARE)
-#define P_NAND_WE	(P_DONTCARE)
-#define P_NAND_RE	(P_DONTCARE)
-#define P_NAND_CLE	(P_DONTCARE)
-#define P_NAND_ALE	(P_DONTCARE)
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ports.h b/arch/blackfin/include/asm/mach-bf548/ports.h
deleted file mode 100644
index 50054f3..0000000
--- a/arch/blackfin/include/asm/mach-bf548/ports.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORTx_MUX Masks */
-#define PORT_x_MUX_0_MASK	0x00000003
-#define PORT_x_MUX_1_MASK	0x0000000C
-#define PORT_x_MUX_2_MASK	0x00000030
-#define PORT_x_MUX_3_MASK	0x000000C0
-#define PORT_x_MUX_4_MASK	0x00000300
-#define PORT_x_MUX_5_MASK	0x00000C00
-#define PORT_x_MUX_6_MASK	0x00003000
-#define PORT_x_MUX_7_MASK	0x0000C000
-#define PORT_x_MUX_8_MASK	0x00030000
-#define PORT_x_MUX_9_MASK	0x000C0000
-#define PORT_x_MUX_10_MASK	0x00300000
-#define PORT_x_MUX_11_MASK	0x00C00000
-#define PORT_x_MUX_12_MASK	0x03000000
-#define PORT_x_MUX_13_MASK	0x0C000000
-#define PORT_x_MUX_14_MASK	0x30000000
-#define PORT_x_MUX_15_MASK	0xC0000000
-
-#define PORT_x_MUX_FUNC_1	(0x0)
-#define PORT_x_MUX_FUNC_2	(0x1)
-#define PORT_x_MUX_FUNC_3	(0x2)
-#define PORT_x_MUX_FUNC_4	(0x3)
-#define PORT_x_MUX_0_FUNC_1	(PORT_x_MUX_FUNC_1 << 0)
-#define PORT_x_MUX_0_FUNC_2	(PORT_x_MUX_FUNC_2 << 0)
-#define PORT_x_MUX_0_FUNC_3	(PORT_x_MUX_FUNC_3 << 0)
-#define PORT_x_MUX_0_FUNC_4	(PORT_x_MUX_FUNC_4 << 0)
-#define PORT_x_MUX_1_FUNC_1	(PORT_x_MUX_FUNC_1 << 2)
-#define PORT_x_MUX_1_FUNC_2	(PORT_x_MUX_FUNC_2 << 2)
-#define PORT_x_MUX_1_FUNC_3	(PORT_x_MUX_FUNC_3 << 2)
-#define PORT_x_MUX_1_FUNC_4	(PORT_x_MUX_FUNC_4 << 2)
-#define PORT_x_MUX_2_FUNC_1	(PORT_x_MUX_FUNC_1 << 4)
-#define PORT_x_MUX_2_FUNC_2	(PORT_x_MUX_FUNC_2 << 4)
-#define PORT_x_MUX_2_FUNC_3	(PORT_x_MUX_FUNC_3 << 4)
-#define PORT_x_MUX_2_FUNC_4	(PORT_x_MUX_FUNC_4 << 4)
-#define PORT_x_MUX_3_FUNC_1	(PORT_x_MUX_FUNC_1 << 6)
-#define PORT_x_MUX_3_FUNC_2	(PORT_x_MUX_FUNC_2 << 6)
-#define PORT_x_MUX_3_FUNC_3	(PORT_x_MUX_FUNC_3 << 6)
-#define PORT_x_MUX_3_FUNC_4	(PORT_x_MUX_FUNC_4 << 6)
-#define PORT_x_MUX_4_FUNC_1	(PORT_x_MUX_FUNC_1 << 8)
-#define PORT_x_MUX_4_FUNC_2	(PORT_x_MUX_FUNC_2 << 8)
-#define PORT_x_MUX_4_FUNC_3	(PORT_x_MUX_FUNC_3 << 8)
-#define PORT_x_MUX_4_FUNC_4	(PORT_x_MUX_FUNC_4 << 8)
-#define PORT_x_MUX_5_FUNC_1	(PORT_x_MUX_FUNC_1 << 10)
-#define PORT_x_MUX_5_FUNC_2	(PORT_x_MUX_FUNC_2 << 10)
-#define PORT_x_MUX_5_FUNC_3	(PORT_x_MUX_FUNC_3 << 10)
-#define PORT_x_MUX_5_FUNC_4	(PORT_x_MUX_FUNC_4 << 10)
-#define PORT_x_MUX_6_FUNC_1	(PORT_x_MUX_FUNC_1 << 12)
-#define PORT_x_MUX_6_FUNC_2	(PORT_x_MUX_FUNC_2 << 12)
-#define PORT_x_MUX_6_FUNC_3	(PORT_x_MUX_FUNC_3 << 12)
-#define PORT_x_MUX_6_FUNC_4	(PORT_x_MUX_FUNC_4 << 12)
-#define PORT_x_MUX_7_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_8_FUNC_1	(PORT_x_MUX_FUNC_1 << 16)
-#define PORT_x_MUX_8_FUNC_2	(PORT_x_MUX_FUNC_2 << 16)
-#define PORT_x_MUX_8_FUNC_3	(PORT_x_MUX_FUNC_3 << 16)
-#define PORT_x_MUX_8_FUNC_4	(PORT_x_MUX_FUNC_4 << 16)
-#define PORT_x_MUX_9_FUNC_1	(PORT_x_MUX_FUNC_1 << 18)
-#define PORT_x_MUX_9_FUNC_2	(PORT_x_MUX_FUNC_2 << 18)
-#define PORT_x_MUX_9_FUNC_3	(PORT_x_MUX_FUNC_3 << 18)
-#define PORT_x_MUX_9_FUNC_4	(PORT_x_MUX_FUNC_4 << 18)
-#define PORT_x_MUX_10_FUNC_1	(PORT_x_MUX_FUNC_1 << 20)
-#define PORT_x_MUX_10_FUNC_2	(PORT_x_MUX_FUNC_2 << 20)
-#define PORT_x_MUX_10_FUNC_3	(PORT_x_MUX_FUNC_3 << 20)
-#define PORT_x_MUX_10_FUNC_4	(PORT_x_MUX_FUNC_4 << 20)
-#define PORT_x_MUX_11_FUNC_1	(PORT_x_MUX_FUNC_1 << 22)
-#define PORT_x_MUX_11_FUNC_2	(PORT_x_MUX_FUNC_2 << 22)
-#define PORT_x_MUX_11_FUNC_3	(PORT_x_MUX_FUNC_3 << 22)
-#define PORT_x_MUX_11_FUNC_4	(PORT_x_MUX_FUNC_4 << 22)
-#define PORT_x_MUX_12_FUNC_1	(PORT_x_MUX_FUNC_1 << 24)
-#define PORT_x_MUX_12_FUNC_2	(PORT_x_MUX_FUNC_2 << 24)
-#define PORT_x_MUX_12_FUNC_3	(PORT_x_MUX_FUNC_3 << 24)
-#define PORT_x_MUX_12_FUNC_4	(PORT_x_MUX_FUNC_4 << 24)
-#define PORT_x_MUX_13_FUNC_1	(PORT_x_MUX_FUNC_1 << 26)
-#define PORT_x_MUX_13_FUNC_2	(PORT_x_MUX_FUNC_2 << 26)
-#define PORT_x_MUX_13_FUNC_3	(PORT_x_MUX_FUNC_3 << 26)
-#define PORT_x_MUX_13_FUNC_4	(PORT_x_MUX_FUNC_4 << 26)
-#define PORT_x_MUX_14_FUNC_1	(PORT_x_MUX_FUNC_1 << 28)
-#define PORT_x_MUX_14_FUNC_2	(PORT_x_MUX_FUNC_2 << 28)
-#define PORT_x_MUX_14_FUNC_3	(PORT_x_MUX_FUNC_3 << 28)
-#define PORT_x_MUX_14_FUNC_4	(PORT_x_MUX_FUNC_4 << 28)
-#define PORT_x_MUX_15_FUNC_1	(PORT_x_MUX_FUNC_1 << 30)
-#define PORT_x_MUX_15_FUNC_2	(PORT_x_MUX_FUNC_2 << 30)
-#define PORT_x_MUX_15_FUNC_3	(PORT_x_MUX_FUNC_3 << 30)
-#define PORT_x_MUX_15_FUNC_4	(PORT_x_MUX_FUNC_4 << 30)
-
-#include "../mach-common/bits/ports-a.h"
-#include "../mach-common/bits/ports-b.h"
-#include "../mach-common/bits/ports-c.h"
-#include "../mach-common/bits/ports-d.h"
-#include "../mach-common/bits/ports-e.h"
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-#include "../mach-common/bits/ports-h.h"
-#include "../mach-common/bits/ports-i.h"
-#include "../mach-common/bits/ports-j.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h b/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h
deleted file mode 100644
index 211ba88..0000000
--- a/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h
+++ /dev/null
@@ -1,1410 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF561_proc__
-#define __BFIN_CDEF_ADSP_BF561_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
-#define bfin_read_WDOGA_CTL()          bfin_read16(WDOGA_CTL)
-#define bfin_write_WDOGA_CTL(val)      bfin_write16(WDOGA_CTL, val)
-#define bfin_read_WDOGA_CNT()          bfin_read32(WDOGA_CNT)
-#define bfin_write_WDOGA_CNT(val)      bfin_write32(WDOGA_CNT, val)
-#define bfin_read_WDOGA_STAT()         bfin_read32(WDOGA_STAT)
-#define bfin_write_WDOGA_STAT(val)     bfin_write32(WDOGA_STAT, val)
-#define bfin_read_WDOGB_CTL()          bfin_read16(WDOGB_CTL)
-#define bfin_write_WDOGB_CTL(val)      bfin_write16(WDOGB_CTL, val)
-#define bfin_read_WDOGB_CNT()          bfin_read32(WDOGB_CNT)
-#define bfin_write_WDOGB_CNT(val)      bfin_write32(WDOGB_CNT, val)
-#define bfin_read_WDOGB_STAT()         bfin_read32(WDOGB_STAT)
-#define bfin_write_WDOGB_STAT(val)     bfin_write32(WDOGB_STAT, val)
-#define bfin_read_DMA1_TC_PER()        bfin_read16(DMA1_TC_PER)
-#define bfin_write_DMA1_TC_PER(val)    bfin_write16(DMA1_TC_PER, val)
-#define bfin_read_DMA1_TC_CNT()        bfin_read16(DMA1_TC_CNT)
-#define bfin_write_DMA1_TC_CNT(val)    bfin_write16(DMA1_TC_CNT, val)
-#define bfin_read_DMA1_0_CONFIG()      bfin_read16(DMA1_0_CONFIG)
-#define bfin_write_DMA1_0_CONFIG(val)  bfin_write16(DMA1_0_CONFIG, val)
-#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_readPTR(DMA1_0_NEXT_DESC_PTR)
-#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_0_START_ADDR()  bfin_readPTR(DMA1_0_START_ADDR)
-#define bfin_write_DMA1_0_START_ADDR(val) bfin_writePTR(DMA1_0_START_ADDR, val)
-#define bfin_read_DMA1_0_X_COUNT()     bfin_read16(DMA1_0_X_COUNT)
-#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT, val)
-#define bfin_read_DMA1_0_Y_COUNT()     bfin_read16(DMA1_0_Y_COUNT)
-#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT, val)
-#define bfin_read_DMA1_0_X_MODIFY()    bfin_read16(DMA1_0_X_MODIFY)
-#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY, val)
-#define bfin_read_DMA1_0_Y_MODIFY()    bfin_read16(DMA1_0_Y_MODIFY)
-#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY, val)
-#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_readPTR(DMA1_0_CURR_DESC_PTR)
-#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_writePTR(DMA1_0_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_0_CURR_ADDR()   bfin_readPTR(DMA1_0_CURR_ADDR)
-#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_writePTR(DMA1_0_CURR_ADDR, val)
-#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
-#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT, val)
-#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
-#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_0_IRQ_STATUS()  bfin_read16(DMA1_0_IRQ_STATUS)
-#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS, val)
-#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
-#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_1_CONFIG()      bfin_read16(DMA1_1_CONFIG)
-#define bfin_write_DMA1_1_CONFIG(val)  bfin_write16(DMA1_1_CONFIG, val)
-#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_readPTR(DMA1_1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_1_START_ADDR()  bfin_readPTR(DMA1_1_START_ADDR)
-#define bfin_write_DMA1_1_START_ADDR(val) bfin_writePTR(DMA1_1_START_ADDR, val)
-#define bfin_read_DMA1_1_X_COUNT()     bfin_read16(DMA1_1_X_COUNT)
-#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT, val)
-#define bfin_read_DMA1_1_Y_COUNT()     bfin_read16(DMA1_1_Y_COUNT)
-#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT, val)
-#define bfin_read_DMA1_1_X_MODIFY()    bfin_read16(DMA1_1_X_MODIFY)
-#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY, val)
-#define bfin_read_DMA1_1_Y_MODIFY()    bfin_read16(DMA1_1_Y_MODIFY)
-#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY, val)
-#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_readPTR(DMA1_1_CURR_DESC_PTR)
-#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_1_CURR_ADDR()   bfin_readPTR(DMA1_1_CURR_ADDR)
-#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_writePTR(DMA1_1_CURR_ADDR, val)
-#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
-#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
-#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_1_IRQ_STATUS()  bfin_read16(DMA1_1_IRQ_STATUS)
-#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS, val)
-#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_2_CONFIG()      bfin_read16(DMA1_2_CONFIG)
-#define bfin_write_DMA1_2_CONFIG(val)  bfin_write16(DMA1_2_CONFIG, val)
-#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_readPTR(DMA1_2_NEXT_DESC_PTR)
-#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_2_START_ADDR()  bfin_readPTR(DMA1_2_START_ADDR)
-#define bfin_write_DMA1_2_START_ADDR(val) bfin_writePTR(DMA1_2_START_ADDR, val)
-#define bfin_read_DMA1_2_X_COUNT()     bfin_read16(DMA1_2_X_COUNT)
-#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT, val)
-#define bfin_read_DMA1_2_Y_COUNT()     bfin_read16(DMA1_2_Y_COUNT)
-#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT, val)
-#define bfin_read_DMA1_2_X_MODIFY()    bfin_read16(DMA1_2_X_MODIFY)
-#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY, val)
-#define bfin_read_DMA1_2_Y_MODIFY()    bfin_read16(DMA1_2_Y_MODIFY)
-#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY, val)
-#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_readPTR(DMA1_2_CURR_DESC_PTR)
-#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_writePTR(DMA1_2_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_2_CURR_ADDR()   bfin_readPTR(DMA1_2_CURR_ADDR)
-#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_writePTR(DMA1_2_CURR_ADDR, val)
-#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
-#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT, val)
-#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
-#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_2_IRQ_STATUS()  bfin_read16(DMA1_2_IRQ_STATUS)
-#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS, val)
-#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
-#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_3_CONFIG()      bfin_read16(DMA1_3_CONFIG)
-#define bfin_write_DMA1_3_CONFIG(val)  bfin_write16(DMA1_3_CONFIG, val)
-#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_readPTR(DMA1_3_NEXT_DESC_PTR)
-#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_3_START_ADDR()  bfin_readPTR(DMA1_3_START_ADDR)
-#define bfin_write_DMA1_3_START_ADDR(val) bfin_writePTR(DMA1_3_START_ADDR, val)
-#define bfin_read_DMA1_3_X_COUNT()     bfin_read16(DMA1_3_X_COUNT)
-#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT, val)
-#define bfin_read_DMA1_3_Y_COUNT()     bfin_read16(DMA1_3_Y_COUNT)
-#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT, val)
-#define bfin_read_DMA1_3_X_MODIFY()    bfin_read16(DMA1_3_X_MODIFY)
-#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY, val)
-#define bfin_read_DMA1_3_Y_MODIFY()    bfin_read16(DMA1_3_Y_MODIFY)
-#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY, val)
-#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_readPTR(DMA1_3_CURR_DESC_PTR)
-#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_writePTR(DMA1_3_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_3_CURR_ADDR()   bfin_readPTR(DMA1_3_CURR_ADDR)
-#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_writePTR(DMA1_3_CURR_ADDR, val)
-#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
-#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT, val)
-#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
-#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_3_IRQ_STATUS()  bfin_read16(DMA1_3_IRQ_STATUS)
-#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS, val)
-#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
-#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_4_CONFIG()      bfin_read16(DMA1_4_CONFIG)
-#define bfin_write_DMA1_4_CONFIG(val)  bfin_write16(DMA1_4_CONFIG, val)
-#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_readPTR(DMA1_4_NEXT_DESC_PTR)
-#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_4_START_ADDR()  bfin_readPTR(DMA1_4_START_ADDR)
-#define bfin_write_DMA1_4_START_ADDR(val) bfin_writePTR(DMA1_4_START_ADDR, val)
-#define bfin_read_DMA1_4_X_COUNT()     bfin_read16(DMA1_4_X_COUNT)
-#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT, val)
-#define bfin_read_DMA1_4_Y_COUNT()     bfin_read16(DMA1_4_Y_COUNT)
-#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT, val)
-#define bfin_read_DMA1_4_X_MODIFY()    bfin_read16(DMA1_4_X_MODIFY)
-#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY, val)
-#define bfin_read_DMA1_4_Y_MODIFY()    bfin_read16(DMA1_4_Y_MODIFY)
-#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY, val)
-#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_readPTR(DMA1_4_CURR_DESC_PTR)
-#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_writePTR(DMA1_4_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_4_CURR_ADDR()   bfin_readPTR(DMA1_4_CURR_ADDR)
-#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_writePTR(DMA1_4_CURR_ADDR, val)
-#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
-#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT, val)
-#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
-#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_4_IRQ_STATUS()  bfin_read16(DMA1_4_IRQ_STATUS)
-#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS, val)
-#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
-#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_5_CONFIG()      bfin_read16(DMA1_5_CONFIG)
-#define bfin_write_DMA1_5_CONFIG(val)  bfin_write16(DMA1_5_CONFIG, val)
-#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_readPTR(DMA1_5_NEXT_DESC_PTR)
-#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_5_START_ADDR()  bfin_readPTR(DMA1_5_START_ADDR)
-#define bfin_write_DMA1_5_START_ADDR(val) bfin_writePTR(DMA1_5_START_ADDR, val)
-#define bfin_read_DMA1_5_X_COUNT()     bfin_read16(DMA1_5_X_COUNT)
-#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT, val)
-#define bfin_read_DMA1_5_Y_COUNT()     bfin_read16(DMA1_5_Y_COUNT)
-#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT, val)
-#define bfin_read_DMA1_5_X_MODIFY()    bfin_read16(DMA1_5_X_MODIFY)
-#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY, val)
-#define bfin_read_DMA1_5_Y_MODIFY()    bfin_read16(DMA1_5_Y_MODIFY)
-#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY, val)
-#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_readPTR(DMA1_5_CURR_DESC_PTR)
-#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_writePTR(DMA1_5_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_5_CURR_ADDR()   bfin_readPTR(DMA1_5_CURR_ADDR)
-#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_writePTR(DMA1_5_CURR_ADDR, val)
-#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
-#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT, val)
-#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
-#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_5_IRQ_STATUS()  bfin_read16(DMA1_5_IRQ_STATUS)
-#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS, val)
-#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
-#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_6_CONFIG()      bfin_read16(DMA1_6_CONFIG)
-#define bfin_write_DMA1_6_CONFIG(val)  bfin_write16(DMA1_6_CONFIG, val)
-#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_readPTR(DMA1_6_NEXT_DESC_PTR)
-#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_6_START_ADDR()  bfin_readPTR(DMA1_6_START_ADDR)
-#define bfin_write_DMA1_6_START_ADDR(val) bfin_writePTR(DMA1_6_START_ADDR, val)
-#define bfin_read_DMA1_6_X_COUNT()     bfin_read16(DMA1_6_X_COUNT)
-#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT, val)
-#define bfin_read_DMA1_6_Y_COUNT()     bfin_read16(DMA1_6_Y_COUNT)
-#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT, val)
-#define bfin_read_DMA1_6_X_MODIFY()    bfin_read16(DMA1_6_X_MODIFY)
-#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY, val)
-#define bfin_read_DMA1_6_Y_MODIFY()    bfin_read16(DMA1_6_Y_MODIFY)
-#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY, val)
-#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_readPTR(DMA1_6_CURR_DESC_PTR)
-#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_writePTR(DMA1_6_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_6_CURR_ADDR()   bfin_readPTR(DMA1_6_CURR_ADDR)
-#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_writePTR(DMA1_6_CURR_ADDR, val)
-#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
-#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT, val)
-#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
-#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_6_IRQ_STATUS()  bfin_read16(DMA1_6_IRQ_STATUS)
-#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS, val)
-#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
-#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_7_CONFIG()      bfin_read16(DMA1_7_CONFIG)
-#define bfin_write_DMA1_7_CONFIG(val)  bfin_write16(DMA1_7_CONFIG, val)
-#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_readPTR(DMA1_7_NEXT_DESC_PTR)
-#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_7_START_ADDR()  bfin_readPTR(DMA1_7_START_ADDR)
-#define bfin_write_DMA1_7_START_ADDR(val) bfin_writePTR(DMA1_7_START_ADDR, val)
-#define bfin_read_DMA1_7_X_COUNT()     bfin_read16(DMA1_7_X_COUNT)
-#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT, val)
-#define bfin_read_DMA1_7_Y_COUNT()     bfin_read16(DMA1_7_Y_COUNT)
-#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT, val)
-#define bfin_read_DMA1_7_X_MODIFY()    bfin_read16(DMA1_7_X_MODIFY)
-#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY, val)
-#define bfin_read_DMA1_7_Y_MODIFY()    bfin_read16(DMA1_7_Y_MODIFY)
-#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY, val)
-#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_readPTR(DMA1_7_CURR_DESC_PTR)
-#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_writePTR(DMA1_7_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_7_CURR_ADDR()   bfin_readPTR(DMA1_7_CURR_ADDR)
-#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_writePTR(DMA1_7_CURR_ADDR, val)
-#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
-#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT, val)
-#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
-#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_7_IRQ_STATUS()  bfin_read16(DMA1_7_IRQ_STATUS)
-#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS, val)
-#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
-#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_8_CONFIG()      bfin_read16(DMA1_8_CONFIG)
-#define bfin_write_DMA1_8_CONFIG(val)  bfin_write16(DMA1_8_CONFIG, val)
-#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_readPTR(DMA1_8_NEXT_DESC_PTR)
-#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_8_START_ADDR()  bfin_readPTR(DMA1_8_START_ADDR)
-#define bfin_write_DMA1_8_START_ADDR(val) bfin_writePTR(DMA1_8_START_ADDR, val)
-#define bfin_read_DMA1_8_X_COUNT()     bfin_read16(DMA1_8_X_COUNT)
-#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT, val)
-#define bfin_read_DMA1_8_Y_COUNT()     bfin_read16(DMA1_8_Y_COUNT)
-#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT, val)
-#define bfin_read_DMA1_8_X_MODIFY()    bfin_read16(DMA1_8_X_MODIFY)
-#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY, val)
-#define bfin_read_DMA1_8_Y_MODIFY()    bfin_read16(DMA1_8_Y_MODIFY)
-#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY, val)
-#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_readPTR(DMA1_8_CURR_DESC_PTR)
-#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_writePTR(DMA1_8_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_8_CURR_ADDR()   bfin_readPTR(DMA1_8_CURR_ADDR)
-#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_writePTR(DMA1_8_CURR_ADDR, val)
-#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
-#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT, val)
-#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
-#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_8_IRQ_STATUS()  bfin_read16(DMA1_8_IRQ_STATUS)
-#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS, val)
-#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
-#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_9_CONFIG()      bfin_read16(DMA1_9_CONFIG)
-#define bfin_write_DMA1_9_CONFIG(val)  bfin_write16(DMA1_9_CONFIG, val)
-#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_readPTR(DMA1_9_NEXT_DESC_PTR)
-#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_9_START_ADDR()  bfin_readPTR(DMA1_9_START_ADDR)
-#define bfin_write_DMA1_9_START_ADDR(val) bfin_writePTR(DMA1_9_START_ADDR, val)
-#define bfin_read_DMA1_9_X_COUNT()     bfin_read16(DMA1_9_X_COUNT)
-#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT, val)
-#define bfin_read_DMA1_9_Y_COUNT()     bfin_read16(DMA1_9_Y_COUNT)
-#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT, val)
-#define bfin_read_DMA1_9_X_MODIFY()    bfin_read16(DMA1_9_X_MODIFY)
-#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY, val)
-#define bfin_read_DMA1_9_Y_MODIFY()    bfin_read16(DMA1_9_Y_MODIFY)
-#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY, val)
-#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_readPTR(DMA1_9_CURR_DESC_PTR)
-#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_writePTR(DMA1_9_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_9_CURR_ADDR()   bfin_readPTR(DMA1_9_CURR_ADDR)
-#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_writePTR(DMA1_9_CURR_ADDR, val)
-#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
-#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT, val)
-#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
-#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_9_IRQ_STATUS()  bfin_read16(DMA1_9_IRQ_STATUS)
-#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS, val)
-#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
-#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_10_CONFIG()     bfin_read16(DMA1_10_CONFIG)
-#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG, val)
-#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_readPTR(DMA1_10_NEXT_DESC_PTR)
-#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_10_START_ADDR() bfin_readPTR(DMA1_10_START_ADDR)
-#define bfin_write_DMA1_10_START_ADDR(val) bfin_writePTR(DMA1_10_START_ADDR, val)
-#define bfin_read_DMA1_10_X_COUNT()    bfin_read16(DMA1_10_X_COUNT)
-#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT, val)
-#define bfin_read_DMA1_10_Y_COUNT()    bfin_read16(DMA1_10_Y_COUNT)
-#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT, val)
-#define bfin_read_DMA1_10_X_MODIFY()   bfin_read16(DMA1_10_X_MODIFY)
-#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY, val)
-#define bfin_read_DMA1_10_Y_MODIFY()   bfin_read16(DMA1_10_Y_MODIFY)
-#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY, val)
-#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_readPTR(DMA1_10_CURR_DESC_PTR)
-#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_writePTR(DMA1_10_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_10_CURR_ADDR()  bfin_readPTR(DMA1_10_CURR_ADDR)
-#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_writePTR(DMA1_10_CURR_ADDR, val)
-#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
-#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT, val)
-#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
-#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
-#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS, val)
-#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
-#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_11_CONFIG()     bfin_read16(DMA1_11_CONFIG)
-#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG, val)
-#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_readPTR(DMA1_11_NEXT_DESC_PTR)
-#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_11_START_ADDR() bfin_readPTR(DMA1_11_START_ADDR)
-#define bfin_write_DMA1_11_START_ADDR(val) bfin_writePTR(DMA1_11_START_ADDR, val)
-#define bfin_read_DMA1_11_X_COUNT()    bfin_read16(DMA1_11_X_COUNT)
-#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT, val)
-#define bfin_read_DMA1_11_Y_COUNT()    bfin_read16(DMA1_11_Y_COUNT)
-#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT, val)
-#define bfin_read_DMA1_11_X_MODIFY()   bfin_read16(DMA1_11_X_MODIFY)
-#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY, val)
-#define bfin_read_DMA1_11_Y_MODIFY()   bfin_read16(DMA1_11_Y_MODIFY)
-#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY, val)
-#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_readPTR(DMA1_11_CURR_DESC_PTR)
-#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_writePTR(DMA1_11_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_11_CURR_ADDR()  bfin_readPTR(DMA1_11_CURR_ADDR)
-#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_writePTR(DMA1_11_CURR_ADDR, val)
-#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
-#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT, val)
-#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
-#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
-#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS, val)
-#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
-#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_TC_PER()        bfin_read16(DMA2_TC_PER)
-#define bfin_write_DMA2_TC_PER(val)    bfin_write16(DMA2_TC_PER, val)
-#define bfin_read_DMA2_TC_CNT()        bfin_read16(DMA2_TC_CNT)
-#define bfin_write_DMA2_TC_CNT(val)    bfin_write16(DMA2_TC_CNT, val)
-#define bfin_read_DMA2_0_CONFIG()      bfin_read16(DMA2_0_CONFIG)
-#define bfin_write_DMA2_0_CONFIG(val)  bfin_write16(DMA2_0_CONFIG, val)
-#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_readPTR(DMA2_0_NEXT_DESC_PTR)
-#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_0_START_ADDR()  bfin_readPTR(DMA2_0_START_ADDR)
-#define bfin_write_DMA2_0_START_ADDR(val) bfin_writePTR(DMA2_0_START_ADDR, val)
-#define bfin_read_DMA2_0_X_COUNT()     bfin_read16(DMA2_0_X_COUNT)
-#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT, val)
-#define bfin_read_DMA2_0_Y_COUNT()     bfin_read16(DMA2_0_Y_COUNT)
-#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT, val)
-#define bfin_read_DMA2_0_X_MODIFY()    bfin_read16(DMA2_0_X_MODIFY)
-#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY, val)
-#define bfin_read_DMA2_0_Y_MODIFY()    bfin_read16(DMA2_0_Y_MODIFY)
-#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY, val)
-#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_readPTR(DMA2_0_CURR_DESC_PTR)
-#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_writePTR(DMA2_0_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_0_CURR_ADDR()   bfin_readPTR(DMA2_0_CURR_ADDR)
-#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_writePTR(DMA2_0_CURR_ADDR, val)
-#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
-#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT, val)
-#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
-#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_0_IRQ_STATUS()  bfin_read16(DMA2_0_IRQ_STATUS)
-#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS, val)
-#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
-#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_1_CONFIG()      bfin_read16(DMA2_1_CONFIG)
-#define bfin_write_DMA2_1_CONFIG(val)  bfin_write16(DMA2_1_CONFIG, val)
-#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_readPTR(DMA2_1_NEXT_DESC_PTR)
-#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_1_START_ADDR()  bfin_readPTR(DMA2_1_START_ADDR)
-#define bfin_write_DMA2_1_START_ADDR(val) bfin_writePTR(DMA2_1_START_ADDR, val)
-#define bfin_read_DMA2_1_X_COUNT()     bfin_read16(DMA2_1_X_COUNT)
-#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT, val)
-#define bfin_read_DMA2_1_Y_COUNT()     bfin_read16(DMA2_1_Y_COUNT)
-#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT, val)
-#define bfin_read_DMA2_1_X_MODIFY()    bfin_read16(DMA2_1_X_MODIFY)
-#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY, val)
-#define bfin_read_DMA2_1_Y_MODIFY()    bfin_read16(DMA2_1_Y_MODIFY)
-#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY, val)
-#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_readPTR(DMA2_1_CURR_DESC_PTR)
-#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_writePTR(DMA2_1_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_1_CURR_ADDR()   bfin_readPTR(DMA2_1_CURR_ADDR)
-#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_writePTR(DMA2_1_CURR_ADDR, val)
-#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
-#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT, val)
-#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
-#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_1_IRQ_STATUS()  bfin_read16(DMA2_1_IRQ_STATUS)
-#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS, val)
-#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
-#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_2_CONFIG()      bfin_read16(DMA2_2_CONFIG)
-#define bfin_write_DMA2_2_CONFIG(val)  bfin_write16(DMA2_2_CONFIG, val)
-#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_readPTR(DMA2_2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_2_START_ADDR()  bfin_readPTR(DMA2_2_START_ADDR)
-#define bfin_write_DMA2_2_START_ADDR(val) bfin_writePTR(DMA2_2_START_ADDR, val)
-#define bfin_read_DMA2_2_X_COUNT()     bfin_read16(DMA2_2_X_COUNT)
-#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT, val)
-#define bfin_read_DMA2_2_Y_COUNT()     bfin_read16(DMA2_2_Y_COUNT)
-#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT, val)
-#define bfin_read_DMA2_2_X_MODIFY()    bfin_read16(DMA2_2_X_MODIFY)
-#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY, val)
-#define bfin_read_DMA2_2_Y_MODIFY()    bfin_read16(DMA2_2_Y_MODIFY)
-#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY, val)
-#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_readPTR(DMA2_2_CURR_DESC_PTR)
-#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_2_CURR_ADDR()   bfin_readPTR(DMA2_2_CURR_ADDR)
-#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_writePTR(DMA2_2_CURR_ADDR, val)
-#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
-#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
-#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_2_IRQ_STATUS()  bfin_read16(DMA2_2_IRQ_STATUS)
-#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS, val)
-#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_3_CONFIG()      bfin_read16(DMA2_3_CONFIG)
-#define bfin_write_DMA2_3_CONFIG(val)  bfin_write16(DMA2_3_CONFIG, val)
-#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_readPTR(DMA2_3_NEXT_DESC_PTR)
-#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_3_START_ADDR()  bfin_readPTR(DMA2_3_START_ADDR)
-#define bfin_write_DMA2_3_START_ADDR(val) bfin_writePTR(DMA2_3_START_ADDR, val)
-#define bfin_read_DMA2_3_X_COUNT()     bfin_read16(DMA2_3_X_COUNT)
-#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT, val)
-#define bfin_read_DMA2_3_Y_COUNT()     bfin_read16(DMA2_3_Y_COUNT)
-#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT, val)
-#define bfin_read_DMA2_3_X_MODIFY()    bfin_read16(DMA2_3_X_MODIFY)
-#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY, val)
-#define bfin_read_DMA2_3_Y_MODIFY()    bfin_read16(DMA2_3_Y_MODIFY)
-#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY, val)
-#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_readPTR(DMA2_3_CURR_DESC_PTR)
-#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_writePTR(DMA2_3_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_3_CURR_ADDR()   bfin_readPTR(DMA2_3_CURR_ADDR)
-#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_writePTR(DMA2_3_CURR_ADDR, val)
-#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
-#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT, val)
-#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
-#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_3_IRQ_STATUS()  bfin_read16(DMA2_3_IRQ_STATUS)
-#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS, val)
-#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
-#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_4_CONFIG()      bfin_read16(DMA2_4_CONFIG)
-#define bfin_write_DMA2_4_CONFIG(val)  bfin_write16(DMA2_4_CONFIG, val)
-#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_readPTR(DMA2_4_NEXT_DESC_PTR)
-#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_4_START_ADDR()  bfin_readPTR(DMA2_4_START_ADDR)
-#define bfin_write_DMA2_4_START_ADDR(val) bfin_writePTR(DMA2_4_START_ADDR, val)
-#define bfin_read_DMA2_4_X_COUNT()     bfin_read16(DMA2_4_X_COUNT)
-#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT, val)
-#define bfin_read_DMA2_4_Y_COUNT()     bfin_read16(DMA2_4_Y_COUNT)
-#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT, val)
-#define bfin_read_DMA2_4_X_MODIFY()    bfin_read16(DMA2_4_X_MODIFY)
-#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY, val)
-#define bfin_read_DMA2_4_Y_MODIFY()    bfin_read16(DMA2_4_Y_MODIFY)
-#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY, val)
-#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_readPTR(DMA2_4_CURR_DESC_PTR)
-#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_writePTR(DMA2_4_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_4_CURR_ADDR()   bfin_readPTR(DMA2_4_CURR_ADDR)
-#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_writePTR(DMA2_4_CURR_ADDR, val)
-#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
-#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT, val)
-#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
-#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_4_IRQ_STATUS()  bfin_read16(DMA2_4_IRQ_STATUS)
-#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS, val)
-#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
-#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_5_CONFIG()      bfin_read16(DMA2_5_CONFIG)
-#define bfin_write_DMA2_5_CONFIG(val)  bfin_write16(DMA2_5_CONFIG, val)
-#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_readPTR(DMA2_5_NEXT_DESC_PTR)
-#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_5_START_ADDR()  bfin_readPTR(DMA2_5_START_ADDR)
-#define bfin_write_DMA2_5_START_ADDR(val) bfin_writePTR(DMA2_5_START_ADDR, val)
-#define bfin_read_DMA2_5_X_COUNT()     bfin_read16(DMA2_5_X_COUNT)
-#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT, val)
-#define bfin_read_DMA2_5_Y_COUNT()     bfin_read16(DMA2_5_Y_COUNT)
-#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT, val)
-#define bfin_read_DMA2_5_X_MODIFY()    bfin_read16(DMA2_5_X_MODIFY)
-#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY, val)
-#define bfin_read_DMA2_5_Y_MODIFY()    bfin_read16(DMA2_5_Y_MODIFY)
-#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY, val)
-#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_readPTR(DMA2_5_CURR_DESC_PTR)
-#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_writePTR(DMA2_5_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_5_CURR_ADDR()   bfin_readPTR(DMA2_5_CURR_ADDR)
-#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_writePTR(DMA2_5_CURR_ADDR, val)
-#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
-#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT, val)
-#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
-#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_5_IRQ_STATUS()  bfin_read16(DMA2_5_IRQ_STATUS)
-#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS, val)
-#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
-#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_6_CONFIG()      bfin_read16(DMA2_6_CONFIG)
-#define bfin_write_DMA2_6_CONFIG(val)  bfin_write16(DMA2_6_CONFIG, val)
-#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_readPTR(DMA2_6_NEXT_DESC_PTR)
-#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_6_START_ADDR()  bfin_readPTR(DMA2_6_START_ADDR)
-#define bfin_write_DMA2_6_START_ADDR(val) bfin_writePTR(DMA2_6_START_ADDR, val)
-#define bfin_read_DMA2_6_X_COUNT()     bfin_read16(DMA2_6_X_COUNT)
-#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT, val)
-#define bfin_read_DMA2_6_Y_COUNT()     bfin_read16(DMA2_6_Y_COUNT)
-#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT, val)
-#define bfin_read_DMA2_6_X_MODIFY()    bfin_read16(DMA2_6_X_MODIFY)
-#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY, val)
-#define bfin_read_DMA2_6_Y_MODIFY()    bfin_read16(DMA2_6_Y_MODIFY)
-#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY, val)
-#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_readPTR(DMA2_6_CURR_DESC_PTR)
-#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_writePTR(DMA2_6_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_6_CURR_ADDR()   bfin_readPTR(DMA2_6_CURR_ADDR)
-#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_writePTR(DMA2_6_CURR_ADDR, val)
-#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
-#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT, val)
-#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
-#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_6_IRQ_STATUS()  bfin_read16(DMA2_6_IRQ_STATUS)
-#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS, val)
-#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
-#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_7_CONFIG()      bfin_read16(DMA2_7_CONFIG)
-#define bfin_write_DMA2_7_CONFIG(val)  bfin_write16(DMA2_7_CONFIG, val)
-#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_readPTR(DMA2_7_NEXT_DESC_PTR)
-#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_7_START_ADDR()  bfin_readPTR(DMA2_7_START_ADDR)
-#define bfin_write_DMA2_7_START_ADDR(val) bfin_writePTR(DMA2_7_START_ADDR, val)
-#define bfin_read_DMA2_7_X_COUNT()     bfin_read16(DMA2_7_X_COUNT)
-#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT, val)
-#define bfin_read_DMA2_7_Y_COUNT()     bfin_read16(DMA2_7_Y_COUNT)
-#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT, val)
-#define bfin_read_DMA2_7_X_MODIFY()    bfin_read16(DMA2_7_X_MODIFY)
-#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY, val)
-#define bfin_read_DMA2_7_Y_MODIFY()    bfin_read16(DMA2_7_Y_MODIFY)
-#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY, val)
-#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_readPTR(DMA2_7_CURR_DESC_PTR)
-#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_writePTR(DMA2_7_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_7_CURR_ADDR()   bfin_readPTR(DMA2_7_CURR_ADDR)
-#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_writePTR(DMA2_7_CURR_ADDR, val)
-#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
-#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT, val)
-#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
-#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_7_IRQ_STATUS()  bfin_read16(DMA2_7_IRQ_STATUS)
-#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS, val)
-#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
-#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_8_CONFIG()      bfin_read16(DMA2_8_CONFIG)
-#define bfin_write_DMA2_8_CONFIG(val)  bfin_write16(DMA2_8_CONFIG, val)
-#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_readPTR(DMA2_8_NEXT_DESC_PTR)
-#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_8_START_ADDR()  bfin_readPTR(DMA2_8_START_ADDR)
-#define bfin_write_DMA2_8_START_ADDR(val) bfin_writePTR(DMA2_8_START_ADDR, val)
-#define bfin_read_DMA2_8_X_COUNT()     bfin_read16(DMA2_8_X_COUNT)
-#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT, val)
-#define bfin_read_DMA2_8_Y_COUNT()     bfin_read16(DMA2_8_Y_COUNT)
-#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT, val)
-#define bfin_read_DMA2_8_X_MODIFY()    bfin_read16(DMA2_8_X_MODIFY)
-#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY, val)
-#define bfin_read_DMA2_8_Y_MODIFY()    bfin_read16(DMA2_8_Y_MODIFY)
-#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY, val)
-#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_readPTR(DMA2_8_CURR_DESC_PTR)
-#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_writePTR(DMA2_8_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_8_CURR_ADDR()   bfin_readPTR(DMA2_8_CURR_ADDR)
-#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_writePTR(DMA2_8_CURR_ADDR, val)
-#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
-#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT, val)
-#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
-#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_8_IRQ_STATUS()  bfin_read16(DMA2_8_IRQ_STATUS)
-#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS, val)
-#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
-#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_9_CONFIG()      bfin_read16(DMA2_9_CONFIG)
-#define bfin_write_DMA2_9_CONFIG(val)  bfin_write16(DMA2_9_CONFIG, val)
-#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_readPTR(DMA2_9_NEXT_DESC_PTR)
-#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_9_START_ADDR()  bfin_readPTR(DMA2_9_START_ADDR)
-#define bfin_write_DMA2_9_START_ADDR(val) bfin_writePTR(DMA2_9_START_ADDR, val)
-#define bfin_read_DMA2_9_X_COUNT()     bfin_read16(DMA2_9_X_COUNT)
-#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT, val)
-#define bfin_read_DMA2_9_Y_COUNT()     bfin_read16(DMA2_9_Y_COUNT)
-#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT, val)
-#define bfin_read_DMA2_9_X_MODIFY()    bfin_read16(DMA2_9_X_MODIFY)
-#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY, val)
-#define bfin_read_DMA2_9_Y_MODIFY()    bfin_read16(DMA2_9_Y_MODIFY)
-#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY, val)
-#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_readPTR(DMA2_9_CURR_DESC_PTR)
-#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_writePTR(DMA2_9_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_9_CURR_ADDR()   bfin_readPTR(DMA2_9_CURR_ADDR)
-#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_writePTR(DMA2_9_CURR_ADDR, val)
-#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
-#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT, val)
-#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
-#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_9_IRQ_STATUS()  bfin_read16(DMA2_9_IRQ_STATUS)
-#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS, val)
-#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
-#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_10_CONFIG()     bfin_read16(DMA2_10_CONFIG)
-#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG, val)
-#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_readPTR(DMA2_10_NEXT_DESC_PTR)
-#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_10_START_ADDR() bfin_readPTR(DMA2_10_START_ADDR)
-#define bfin_write_DMA2_10_START_ADDR(val) bfin_writePTR(DMA2_10_START_ADDR, val)
-#define bfin_read_DMA2_10_X_COUNT()    bfin_read16(DMA2_10_X_COUNT)
-#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT, val)
-#define bfin_read_DMA2_10_Y_COUNT()    bfin_read16(DMA2_10_Y_COUNT)
-#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT, val)
-#define bfin_read_DMA2_10_X_MODIFY()   bfin_read16(DMA2_10_X_MODIFY)
-#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY, val)
-#define bfin_read_DMA2_10_Y_MODIFY()   bfin_read16(DMA2_10_Y_MODIFY)
-#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY, val)
-#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_readPTR(DMA2_10_CURR_DESC_PTR)
-#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_writePTR(DMA2_10_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_10_CURR_ADDR()  bfin_readPTR(DMA2_10_CURR_ADDR)
-#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_writePTR(DMA2_10_CURR_ADDR, val)
-#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
-#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT, val)
-#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
-#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
-#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS, val)
-#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
-#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_11_CONFIG()     bfin_read16(DMA2_11_CONFIG)
-#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG, val)
-#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_readPTR(DMA2_11_NEXT_DESC_PTR)
-#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_11_START_ADDR() bfin_readPTR(DMA2_11_START_ADDR)
-#define bfin_write_DMA2_11_START_ADDR(val) bfin_writePTR(DMA2_11_START_ADDR, val)
-#define bfin_read_DMA2_11_X_COUNT()    bfin_read16(DMA2_11_X_COUNT)
-#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT, val)
-#define bfin_read_DMA2_11_Y_COUNT()    bfin_read16(DMA2_11_Y_COUNT)
-#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT, val)
-#define bfin_read_DMA2_11_X_MODIFY()   bfin_read16(DMA2_11_X_MODIFY)
-#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY, val)
-#define bfin_read_DMA2_11_Y_MODIFY()   bfin_read16(DMA2_11_Y_MODIFY)
-#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY, val)
-#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_readPTR(DMA2_11_CURR_DESC_PTR)
-#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_writePTR(DMA2_11_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_11_CURR_ADDR()  bfin_readPTR(DMA2_11_CURR_ADDR)
-#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_writePTR(DMA2_11_CURR_ADDR, val)
-#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
-#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT, val)
-#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
-#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
-#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS, val)
-#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
-#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP, val)
-#define bfin_read_IMDMA_S0_CONFIG()    bfin_read16(IMDMA_S0_CONFIG)
-#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG, val)
-#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_IMDMA_S0_START_ADDR() bfin_readPTR(IMDMA_S0_START_ADDR)
-#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_writePTR(IMDMA_S0_START_ADDR, val)
-#define bfin_read_IMDMA_S0_X_COUNT()   bfin_read16(IMDMA_S0_X_COUNT)
-#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT, val)
-#define bfin_read_IMDMA_S0_Y_COUNT()   bfin_read16(IMDMA_S0_Y_COUNT)
-#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT, val)
-#define bfin_read_IMDMA_S0_X_MODIFY()  bfin_read16(IMDMA_S0_X_MODIFY)
-#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY, val)
-#define bfin_read_IMDMA_S0_Y_MODIFY()  bfin_read16(IMDMA_S0_Y_MODIFY)
-#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY, val)
-#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_readPTR(IMDMA_S0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_readPTR(IMDMA_S0_CURR_ADDR)
-#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_writePTR(IMDMA_S0_CURR_ADDR, val)
-#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
-#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
-#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS, val)
-#define bfin_read_IMDMA_D0_CONFIG()    bfin_read16(IMDMA_D0_CONFIG)
-#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG, val)
-#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_IMDMA_D0_START_ADDR() bfin_readPTR(IMDMA_D0_START_ADDR)
-#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_writePTR(IMDMA_D0_START_ADDR, val)
-#define bfin_read_IMDMA_D0_X_COUNT()   bfin_read16(IMDMA_D0_X_COUNT)
-#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT, val)
-#define bfin_read_IMDMA_D0_Y_COUNT()   bfin_read16(IMDMA_D0_Y_COUNT)
-#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT, val)
-#define bfin_read_IMDMA_D0_X_MODIFY()  bfin_read16(IMDMA_D0_X_MODIFY)
-#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY, val)
-#define bfin_read_IMDMA_D0_Y_MODIFY()  bfin_read16(IMDMA_D0_Y_MODIFY)
-#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY, val)
-#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_readPTR(IMDMA_D0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_readPTR(IMDMA_D0_CURR_ADDR)
-#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_writePTR(IMDMA_D0_CURR_ADDR, val)
-#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
-#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
-#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS, val)
-#define bfin_read_IMDMA_S1_CONFIG()    bfin_read16(IMDMA_S1_CONFIG)
-#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG, val)
-#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_IMDMA_S1_START_ADDR() bfin_readPTR(IMDMA_S1_START_ADDR)
-#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_writePTR(IMDMA_S1_START_ADDR, val)
-#define bfin_read_IMDMA_S1_X_COUNT()   bfin_read16(IMDMA_S1_X_COUNT)
-#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT, val)
-#define bfin_read_IMDMA_S1_Y_COUNT()   bfin_read16(IMDMA_S1_Y_COUNT)
-#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT, val)
-#define bfin_read_IMDMA_S1_X_MODIFY()  bfin_read16(IMDMA_S1_X_MODIFY)
-#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY, val)
-#define bfin_read_IMDMA_S1_Y_MODIFY()  bfin_read16(IMDMA_S1_Y_MODIFY)
-#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY, val)
-#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_readPTR(IMDMA_S1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_readPTR(IMDMA_S1_CURR_ADDR)
-#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_writePTR(IMDMA_S1_CURR_ADDR, val)
-#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
-#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
-#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS, val)
-#define bfin_read_IMDMA_D1_CONFIG()    bfin_read16(IMDMA_D1_CONFIG)
-#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG, val)
-#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_IMDMA_D1_START_ADDR() bfin_readPTR(IMDMA_D1_START_ADDR)
-#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_writePTR(IMDMA_D1_START_ADDR, val)
-#define bfin_read_IMDMA_D1_X_COUNT()   bfin_read16(IMDMA_D1_X_COUNT)
-#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT, val)
-#define bfin_read_IMDMA_D1_Y_COUNT()   bfin_read16(IMDMA_D1_Y_COUNT)
-#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT, val)
-#define bfin_read_IMDMA_D1_X_MODIFY()  bfin_read16(IMDMA_D1_X_MODIFY)
-#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY, val)
-#define bfin_read_IMDMA_D1_Y_MODIFY()  bfin_read16(IMDMA_D1_Y_MODIFY)
-#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY, val)
-#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_readPTR(IMDMA_D1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_readPTR(IMDMA_D1_CURR_ADDR)
-#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_writePTR(IMDMA_D1_CURR_ADDR, val)
-#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
-#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
-#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_S0_CONFIG()    bfin_read16(MDMA1_S0_CONFIG)
-#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val)
-#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR)
-#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val)
-#define bfin_read_MDMA1_S0_X_COUNT()   bfin_read16(MDMA1_S0_X_COUNT)
-#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val)
-#define bfin_read_MDMA1_S0_Y_COUNT()   bfin_read16(MDMA1_S0_Y_COUNT)
-#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val)
-#define bfin_read_MDMA1_S0_X_MODIFY()  bfin_read16(MDMA1_S0_X_MODIFY)
-#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val)
-#define bfin_read_MDMA1_S0_Y_MODIFY()  bfin_read16(MDMA1_S0_Y_MODIFY)
-#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val)
-#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR)
-#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
-#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
-#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
-#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_D0_CONFIG()    bfin_read16(MDMA1_D0_CONFIG)
-#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val)
-#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR)
-#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val)
-#define bfin_read_MDMA1_D0_X_COUNT()   bfin_read16(MDMA1_D0_X_COUNT)
-#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val)
-#define bfin_read_MDMA1_D0_Y_COUNT()   bfin_read16(MDMA1_D0_Y_COUNT)
-#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val)
-#define bfin_read_MDMA1_D0_X_MODIFY()  bfin_read16(MDMA1_D0_X_MODIFY)
-#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val)
-#define bfin_read_MDMA1_D0_Y_MODIFY()  bfin_read16(MDMA1_D0_Y_MODIFY)
-#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val)
-#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR)
-#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
-#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
-#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
-#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_S1_CONFIG()    bfin_read16(MDMA1_S1_CONFIG)
-#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val)
-#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR)
-#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val)
-#define bfin_read_MDMA1_S1_X_COUNT()   bfin_read16(MDMA1_S1_X_COUNT)
-#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val)
-#define bfin_read_MDMA1_S1_Y_COUNT()   bfin_read16(MDMA1_S1_Y_COUNT)
-#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val)
-#define bfin_read_MDMA1_S1_X_MODIFY()  bfin_read16(MDMA1_S1_X_MODIFY)
-#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val)
-#define bfin_read_MDMA1_S1_Y_MODIFY()  bfin_read16(MDMA1_S1_Y_MODIFY)
-#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val)
-#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR)
-#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
-#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
-#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
-#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_D1_CONFIG()    bfin_read16(MDMA1_D1_CONFIG)
-#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val)
-#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR)
-#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val)
-#define bfin_read_MDMA1_D1_X_COUNT()   bfin_read16(MDMA1_D1_X_COUNT)
-#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val)
-#define bfin_read_MDMA1_D1_Y_COUNT()   bfin_read16(MDMA1_D1_Y_COUNT)
-#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val)
-#define bfin_read_MDMA1_D1_X_MODIFY()  bfin_read16(MDMA1_D1_X_MODIFY)
-#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val)
-#define bfin_read_MDMA1_D1_Y_MODIFY()  bfin_read16(MDMA1_D1_Y_MODIFY)
-#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val)
-#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR)
-#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
-#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
-#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
-#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA2_S0_CONFIG()    bfin_read16(MDMA2_S0_CONFIG)
-#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG, val)
-#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_S0_START_ADDR() bfin_readPTR(MDMA2_S0_START_ADDR)
-#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_writePTR(MDMA2_S0_START_ADDR, val)
-#define bfin_read_MDMA2_S0_X_COUNT()   bfin_read16(MDMA2_S0_X_COUNT)
-#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT, val)
-#define bfin_read_MDMA2_S0_Y_COUNT()   bfin_read16(MDMA2_S0_Y_COUNT)
-#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT, val)
-#define bfin_read_MDMA2_S0_X_MODIFY()  bfin_read16(MDMA2_S0_X_MODIFY)
-#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY, val)
-#define bfin_read_MDMA2_S0_Y_MODIFY()  bfin_read16(MDMA2_S0_Y_MODIFY)
-#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY, val)
-#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_readPTR(MDMA2_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_readPTR(MDMA2_S0_CURR_ADDR)
-#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_writePTR(MDMA2_S0_CURR_ADDR, val)
-#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT)
-#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS)
-#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA2_D0_CONFIG()    bfin_read16(MDMA2_D0_CONFIG)
-#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG, val)
-#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_D0_START_ADDR() bfin_readPTR(MDMA2_D0_START_ADDR)
-#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_writePTR(MDMA2_D0_START_ADDR, val)
-#define bfin_read_MDMA2_D0_X_COUNT()   bfin_read16(MDMA2_D0_X_COUNT)
-#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT, val)
-#define bfin_read_MDMA2_D0_Y_COUNT()   bfin_read16(MDMA2_D0_Y_COUNT)
-#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT, val)
-#define bfin_read_MDMA2_D0_X_MODIFY()  bfin_read16(MDMA2_D0_X_MODIFY)
-#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY, val)
-#define bfin_read_MDMA2_D0_Y_MODIFY()  bfin_read16(MDMA2_D0_Y_MODIFY)
-#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY, val)
-#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_readPTR(MDMA2_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_readPTR(MDMA2_D0_CURR_ADDR)
-#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_writePTR(MDMA2_D0_CURR_ADDR, val)
-#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT)
-#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS)
-#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA2_S1_CONFIG()    bfin_read16(MDMA2_S1_CONFIG)
-#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG, val)
-#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_S1_START_ADDR() bfin_readPTR(MDMA2_S1_START_ADDR)
-#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_writePTR(MDMA2_S1_START_ADDR, val)
-#define bfin_read_MDMA2_S1_X_COUNT()   bfin_read16(MDMA2_S1_X_COUNT)
-#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT, val)
-#define bfin_read_MDMA2_S1_Y_COUNT()   bfin_read16(MDMA2_S1_Y_COUNT)
-#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT, val)
-#define bfin_read_MDMA2_S1_X_MODIFY()  bfin_read16(MDMA2_S1_X_MODIFY)
-#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY, val)
-#define bfin_read_MDMA2_S1_Y_MODIFY()  bfin_read16(MDMA2_S1_Y_MODIFY)
-#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY, val)
-#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_readPTR(MDMA2_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_readPTR(MDMA2_S1_CURR_ADDR)
-#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_writePTR(MDMA2_S1_CURR_ADDR, val)
-#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT)
-#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS)
-#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA2_D1_CONFIG()    bfin_read16(MDMA2_D1_CONFIG)
-#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG, val)
-#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_D1_START_ADDR() bfin_readPTR(MDMA2_D1_START_ADDR)
-#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_writePTR(MDMA2_D1_START_ADDR, val)
-#define bfin_read_MDMA2_D1_X_COUNT()   bfin_read16(MDMA2_D1_X_COUNT)
-#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT, val)
-#define bfin_read_MDMA2_D1_Y_COUNT()   bfin_read16(MDMA2_D1_Y_COUNT)
-#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT, val)
-#define bfin_read_MDMA2_D1_X_MODIFY()  bfin_read16(MDMA2_D1_X_MODIFY)
-#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY, val)
-#define bfin_read_MDMA2_D1_Y_MODIFY()  bfin_read16(MDMA2_D1_Y_MODIFY)
-#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY, val)
-#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_readPTR(MDMA2_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_readPTR(MDMA2_D1_CURR_ADDR)
-#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_writePTR(MDMA2_D1_CURR_ADDR, val)
-#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT)
-#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS)
-#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
-#define bfin_read_TIMER11_CONFIG()     bfin_read16(TIMER11_CONFIG)
-#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG, val)
-#define bfin_read_TIMER11_COUNTER()    bfin_read32(TIMER11_COUNTER)
-#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER, val)
-#define bfin_read_TIMER11_PERIOD()     bfin_read32(TIMER11_PERIOD)
-#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD, val)
-#define bfin_read_TIMER11_WIDTH()      bfin_read32(TIMER11_WIDTH)
-#define bfin_write_TIMER11_WIDTH(val)  bfin_write32(TIMER11_WIDTH, val)
-#define bfin_read_TMRS4_ENABLE()       bfin_read32(TMRS4_ENABLE)
-#define bfin_write_TMRS4_ENABLE(val)   bfin_write32(TMRS4_ENABLE, val)
-#define bfin_read_TMRS4_DISABLE()      bfin_read32(TMRS4_DISABLE)
-#define bfin_write_TMRS4_DISABLE(val)  bfin_write32(TMRS4_DISABLE, val)
-#define bfin_read_TMRS4_STATUS()       bfin_read32(TMRS4_STATUS)
-#define bfin_write_TMRS4_STATUS(val)   bfin_write32(TMRS4_STATUS, val)
-#define bfin_read_TMRS8_ENABLE()       bfin_read32(TMRS8_ENABLE)
-#define bfin_write_TMRS8_ENABLE(val)   bfin_write32(TMRS8_ENABLE, val)
-#define bfin_read_TMRS8_DISABLE()      bfin_read32(TMRS8_DISABLE)
-#define bfin_write_TMRS8_DISABLE(val)  bfin_write32(TMRS8_DISABLE, val)
-#define bfin_read_TMRS8_STATUS()       bfin_read32(TMRS8_STATUS)
-#define bfin_write_TMRS8_STATUS(val)   bfin_write32(TMRS8_STATUS, val)
-#define bfin_read_FIO0_FLAG_D()        bfin_read16(FIO0_FLAG_D)
-#define bfin_write_FIO0_FLAG_D(val)    bfin_write16(FIO0_FLAG_D, val)
-#define bfin_read_FIO0_FLAG_C()        bfin_read16(FIO0_FLAG_C)
-#define bfin_write_FIO0_FLAG_C(val)    bfin_write16(FIO0_FLAG_C, val)
-#define bfin_read_FIO0_FLAG_S()        bfin_read16(FIO0_FLAG_S)
-#define bfin_write_FIO0_FLAG_S(val)    bfin_write16(FIO0_FLAG_S, val)
-#define bfin_read_FIO0_FLAG_T()        bfin_read16(FIO0_FLAG_T)
-#define bfin_write_FIO0_FLAG_T(val)    bfin_write16(FIO0_FLAG_T, val)
-#define bfin_read_FIO0_MASKA_D()       bfin_read16(FIO0_MASKA_D)
-#define bfin_write_FIO0_MASKA_D(val)   bfin_write16(FIO0_MASKA_D, val)
-#define bfin_read_FIO0_MASKA_C()       bfin_read16(FIO0_MASKA_C)
-#define bfin_write_FIO0_MASKA_C(val)   bfin_write16(FIO0_MASKA_C, val)
-#define bfin_read_FIO0_MASKA_S()       bfin_read16(FIO0_MASKA_S)
-#define bfin_write_FIO0_MASKA_S(val)   bfin_write16(FIO0_MASKA_S, val)
-#define bfin_read_FIO0_MASKA_T()       bfin_read16(FIO0_MASKA_T)
-#define bfin_write_FIO0_MASKA_T(val)   bfin_write16(FIO0_MASKA_T, val)
-#define bfin_read_FIO0_MASKB_D()       bfin_read16(FIO0_MASKB_D)
-#define bfin_write_FIO0_MASKB_D(val)   bfin_write16(FIO0_MASKB_D, val)
-#define bfin_read_FIO0_MASKB_C()       bfin_read16(FIO0_MASKB_C)
-#define bfin_write_FIO0_MASKB_C(val)   bfin_write16(FIO0_MASKB_C, val)
-#define bfin_read_FIO0_MASKB_S()       bfin_read16(FIO0_MASKB_S)
-#define bfin_write_FIO0_MASKB_S(val)   bfin_write16(FIO0_MASKB_S, val)
-#define bfin_read_FIO0_MASKB_T()       bfin_read16(FIO0_MASKB_T)
-#define bfin_write_FIO0_MASKB_T(val)   bfin_write16(FIO0_MASKB_T, val)
-#define bfin_read_FIO0_DIR()           bfin_read16(FIO0_DIR)
-#define bfin_write_FIO0_DIR(val)       bfin_write16(FIO0_DIR, val)
-#define bfin_read_FIO0_POLAR()         bfin_read16(FIO0_POLAR)
-#define bfin_write_FIO0_POLAR(val)     bfin_write16(FIO0_POLAR, val)
-#define bfin_read_FIO0_EDGE()          bfin_read16(FIO0_EDGE)
-#define bfin_write_FIO0_EDGE(val)      bfin_write16(FIO0_EDGE, val)
-#define bfin_read_FIO0_BOTH()          bfin_read16(FIO0_BOTH)
-#define bfin_write_FIO0_BOTH(val)      bfin_write16(FIO0_BOTH, val)
-#define bfin_read_FIO0_INEN()          bfin_read16(FIO0_INEN)
-#define bfin_write_FIO0_INEN(val)      bfin_write16(FIO0_INEN, val)
-#define bfin_read_FIO1_FLAG_D()        bfin_read16(FIO1_FLAG_D)
-#define bfin_write_FIO1_FLAG_D(val)    bfin_write16(FIO1_FLAG_D, val)
-#define bfin_read_FIO1_FLAG_C()        bfin_read16(FIO1_FLAG_C)
-#define bfin_write_FIO1_FLAG_C(val)    bfin_write16(FIO1_FLAG_C, val)
-#define bfin_read_FIO1_FLAG_S()        bfin_read16(FIO1_FLAG_S)
-#define bfin_write_FIO1_FLAG_S(val)    bfin_write16(FIO1_FLAG_S, val)
-#define bfin_read_FIO1_FLAG_T()        bfin_read16(FIO1_FLAG_T)
-#define bfin_write_FIO1_FLAG_T(val)    bfin_write16(FIO1_FLAG_T, val)
-#define bfin_read_FIO1_MASKA_D()       bfin_read16(FIO1_MASKA_D)
-#define bfin_write_FIO1_MASKA_D(val)   bfin_write16(FIO1_MASKA_D, val)
-#define bfin_read_FIO1_MASKA_C()       bfin_read16(FIO1_MASKA_C)
-#define bfin_write_FIO1_MASKA_C(val)   bfin_write16(FIO1_MASKA_C, val)
-#define bfin_read_FIO1_MASKA_S()       bfin_read16(FIO1_MASKA_S)
-#define bfin_write_FIO1_MASKA_S(val)   bfin_write16(FIO1_MASKA_S, val)
-#define bfin_read_FIO1_MASKA_T()       bfin_read16(FIO1_MASKA_T)
-#define bfin_write_FIO1_MASKA_T(val)   bfin_write16(FIO1_MASKA_T, val)
-#define bfin_read_FIO1_MASKB_D()       bfin_read16(FIO1_MASKB_D)
-#define bfin_write_FIO1_MASKB_D(val)   bfin_write16(FIO1_MASKB_D, val)
-#define bfin_read_FIO1_MASKB_C()       bfin_read16(FIO1_MASKB_C)
-#define bfin_write_FIO1_MASKB_C(val)   bfin_write16(FIO1_MASKB_C, val)
-#define bfin_read_FIO1_MASKB_S()       bfin_read16(FIO1_MASKB_S)
-#define bfin_write_FIO1_MASKB_S(val)   bfin_write16(FIO1_MASKB_S, val)
-#define bfin_read_FIO1_MASKB_T()       bfin_read16(FIO1_MASKB_T)
-#define bfin_write_FIO1_MASKB_T(val)   bfin_write16(FIO1_MASKB_T, val)
-#define bfin_read_FIO1_DIR()           bfin_read16(FIO1_DIR)
-#define bfin_write_FIO1_DIR(val)       bfin_write16(FIO1_DIR, val)
-#define bfin_read_FIO1_POLAR()         bfin_read16(FIO1_POLAR)
-#define bfin_write_FIO1_POLAR(val)     bfin_write16(FIO1_POLAR, val)
-#define bfin_read_FIO1_EDGE()          bfin_read16(FIO1_EDGE)
-#define bfin_write_FIO1_EDGE(val)      bfin_write16(FIO1_EDGE, val)
-#define bfin_read_FIO1_BOTH()          bfin_read16(FIO1_BOTH)
-#define bfin_write_FIO1_BOTH(val)      bfin_write16(FIO1_BOTH, val)
-#define bfin_read_FIO1_INEN()          bfin_read16(FIO1_INEN)
-#define bfin_write_FIO1_INEN(val)      bfin_write16(FIO1_INEN, val)
-#define bfin_read_FIO2_FLAG_D()        bfin_read16(FIO2_FLAG_D)
-#define bfin_write_FIO2_FLAG_D(val)    bfin_write16(FIO2_FLAG_D, val)
-#define bfin_read_FIO2_FLAG_C()        bfin_read16(FIO2_FLAG_C)
-#define bfin_write_FIO2_FLAG_C(val)    bfin_write16(FIO2_FLAG_C, val)
-#define bfin_read_FIO2_FLAG_S()        bfin_read16(FIO2_FLAG_S)
-#define bfin_write_FIO2_FLAG_S(val)    bfin_write16(FIO2_FLAG_S, val)
-#define bfin_read_FIO2_FLAG_T()        bfin_read16(FIO2_FLAG_T)
-#define bfin_write_FIO2_FLAG_T(val)    bfin_write16(FIO2_FLAG_T, val)
-#define bfin_read_FIO2_MASKA_D()       bfin_read16(FIO2_MASKA_D)
-#define bfin_write_FIO2_MASKA_D(val)   bfin_write16(FIO2_MASKA_D, val)
-#define bfin_read_FIO2_MASKA_C()       bfin_read16(FIO2_MASKA_C)
-#define bfin_write_FIO2_MASKA_C(val)   bfin_write16(FIO2_MASKA_C, val)
-#define bfin_read_FIO2_MASKA_S()       bfin_read16(FIO2_MASKA_S)
-#define bfin_write_FIO2_MASKA_S(val)   bfin_write16(FIO2_MASKA_S, val)
-#define bfin_read_FIO2_MASKA_T()       bfin_read16(FIO2_MASKA_T)
-#define bfin_write_FIO2_MASKA_T(val)   bfin_write16(FIO2_MASKA_T, val)
-#define bfin_read_FIO2_MASKB_D()       bfin_read16(FIO2_MASKB_D)
-#define bfin_write_FIO2_MASKB_D(val)   bfin_write16(FIO2_MASKB_D, val)
-#define bfin_read_FIO2_MASKB_C()       bfin_read16(FIO2_MASKB_C)
-#define bfin_write_FIO2_MASKB_C(val)   bfin_write16(FIO2_MASKB_C, val)
-#define bfin_read_FIO2_MASKB_S()       bfin_read16(FIO2_MASKB_S)
-#define bfin_write_FIO2_MASKB_S(val)   bfin_write16(FIO2_MASKB_S, val)
-#define bfin_read_FIO2_MASKB_T()       bfin_read16(FIO2_MASKB_T)
-#define bfin_write_FIO2_MASKB_T(val)   bfin_write16(FIO2_MASKB_T, val)
-#define bfin_read_FIO2_DIR()           bfin_read16(FIO2_DIR)
-#define bfin_write_FIO2_DIR(val)       bfin_write16(FIO2_DIR, val)
-#define bfin_read_FIO2_POLAR()         bfin_read16(FIO2_POLAR)
-#define bfin_write_FIO2_POLAR(val)     bfin_write16(FIO2_POLAR, val)
-#define bfin_read_FIO2_EDGE()          bfin_read16(FIO2_EDGE)
-#define bfin_write_FIO2_EDGE(val)      bfin_write16(FIO2_EDGE, val)
-#define bfin_read_FIO2_BOTH()          bfin_read16(FIO2_BOTH)
-#define bfin_write_FIO2_BOTH(val)      bfin_write16(FIO2_BOTH, val)
-#define bfin_read_FIO2_INEN()          bfin_read16(FIO2_INEN)
-#define bfin_write_FIO2_INEN(val)      bfin_write16(FIO2_INEN, val)
-#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()          bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SICA_SWRST()         bfin_read16(SICA_SWRST)
-#define bfin_write_SICA_SWRST(val)     bfin_write16(SICA_SWRST, val)
-#define bfin_read_SICA_SYSCR()         bfin_read16(SICA_SYSCR)
-#define bfin_write_SICA_SYSCR(val)     bfin_write16(SICA_SYSCR, val)
-#define bfin_read_SICA_RVECT()         bfin_read16(SICA_RVECT)
-#define bfin_write_SICA_RVECT(val)     bfin_write16(SICA_RVECT, val)
-#define bfin_read_SICA_IMASK0()        bfin_read32(SICA_IMASK0)
-#define bfin_write_SICA_IMASK0(val)    bfin_write32(SICA_IMASK0, val)
-#define bfin_read_SICA_IMASK1()        bfin_read32(SICA_IMASK1)
-#define bfin_write_SICA_IMASK1(val)    bfin_write32(SICA_IMASK1, val)
-#define bfin_read_SICA_ISR0()          bfin_read32(SICA_ISR0)
-#define bfin_write_SICA_ISR0(val)      bfin_write32(SICA_ISR0, val)
-#define bfin_read_SICA_ISR1()          bfin_read32(SICA_ISR1)
-#define bfin_write_SICA_ISR1(val)      bfin_write32(SICA_ISR1, val)
-#define bfin_read_SICA_IWR0()          bfin_read32(SICA_IWR0)
-#define bfin_write_SICA_IWR0(val)      bfin_write32(SICA_IWR0, val)
-#define bfin_read_SICA_IWR1()          bfin_read32(SICA_IWR1)
-#define bfin_write_SICA_IWR1(val)      bfin_write32(SICA_IWR1, val)
-#define bfin_read_SICA_IAR0()          bfin_read32(SICA_IAR0)
-#define bfin_write_SICA_IAR0(val)      bfin_write32(SICA_IAR0, val)
-#define bfin_read_SICA_IAR1()          bfin_read32(SICA_IAR1)
-#define bfin_write_SICA_IAR1(val)      bfin_write32(SICA_IAR1, val)
-#define bfin_read_SICA_IAR2()          bfin_read32(SICA_IAR2)
-#define bfin_write_SICA_IAR2(val)      bfin_write32(SICA_IAR2, val)
-#define bfin_read_SICA_IAR3()          bfin_read32(SICA_IAR3)
-#define bfin_write_SICA_IAR3(val)      bfin_write32(SICA_IAR3, val)
-#define bfin_read_SICA_IAR4()          bfin_read32(SICA_IAR4)
-#define bfin_write_SICA_IAR4(val)      bfin_write32(SICA_IAR4, val)
-#define bfin_read_SICA_IAR5()          bfin_read32(SICA_IAR5)
-#define bfin_write_SICA_IAR5(val)      bfin_write32(SICA_IAR5, val)
-#define bfin_read_SICA_IAR6()          bfin_read32(SICA_IAR6)
-#define bfin_write_SICA_IAR6(val)      bfin_write32(SICA_IAR6, val)
-#define bfin_read_SICA_IAR7()          bfin_read32(SICA_IAR7)
-#define bfin_write_SICA_IAR7(val)      bfin_write32(SICA_IAR7, val)
-#define bfin_read_SICB_SWRST()         bfin_read16(SICB_SWRST)
-#define bfin_write_SICB_SWRST(val)     bfin_write16(SICB_SWRST, val)
-#define bfin_read_SICB_SYSCR()         bfin_read16(SICB_SYSCR)
-#define bfin_write_SICB_SYSCR(val)     bfin_write16(SICB_SYSCR, val)
-#define bfin_read_SICB_RVECT()         bfin_read16(SICB_RVECT)
-#define bfin_write_SICB_RVECT(val)     bfin_write16(SICB_RVECT, val)
-#define bfin_read_SICB_IMASK0()        bfin_read32(SICB_IMASK0)
-#define bfin_write_SICB_IMASK0(val)    bfin_write32(SICB_IMASK0, val)
-#define bfin_read_SICB_IMASK1()        bfin_read32(SICB_IMASK1)
-#define bfin_write_SICB_IMASK1(val)    bfin_write32(SICB_IMASK1, val)
-#define bfin_read_SICB_ISR0()          bfin_read32(SICB_ISR0)
-#define bfin_write_SICB_ISR0(val)      bfin_write32(SICB_ISR0, val)
-#define bfin_read_SICB_ISR1()          bfin_read32(SICB_ISR1)
-#define bfin_write_SICB_ISR1(val)      bfin_write32(SICB_ISR1, val)
-#define bfin_read_SICB_IWR0()          bfin_read32(SICB_IWR0)
-#define bfin_write_SICB_IWR0(val)      bfin_write32(SICB_IWR0, val)
-#define bfin_read_SICB_IWR1()          bfin_read32(SICB_IWR1)
-#define bfin_write_SICB_IWR1(val)      bfin_write32(SICB_IWR1, val)
-#define bfin_read_SICB_IAR0()          bfin_read32(SICB_IAR0)
-#define bfin_write_SICB_IAR0(val)      bfin_write32(SICB_IAR0, val)
-#define bfin_read_SICB_IAR1()          bfin_read32(SICB_IAR1)
-#define bfin_write_SICB_IAR1(val)      bfin_write32(SICB_IAR1, val)
-#define bfin_read_SICB_IAR2()          bfin_read32(SICB_IAR2)
-#define bfin_write_SICB_IAR2(val)      bfin_write32(SICB_IAR2, val)
-#define bfin_read_SICB_IAR3()          bfin_read32(SICB_IAR3)
-#define bfin_write_SICB_IAR3(val)      bfin_write32(SICB_IAR3, val)
-#define bfin_read_SICB_IAR4()          bfin_read32(SICB_IAR4)
-#define bfin_write_SICB_IAR4(val)      bfin_write32(SICB_IAR4, val)
-#define bfin_read_SICB_IAR5()          bfin_read32(SICB_IAR5)
-#define bfin_write_SICB_IAR5(val)      bfin_write32(SICB_IAR5, val)
-#define bfin_read_SICB_IAR6()          bfin_read32(SICB_IAR6)
-#define bfin_write_SICB_IAR6(val)      bfin_write32(SICB_IAR6, val)
-#define bfin_read_SICB_IAR7()          bfin_read32(SICB_IAR7)
-#define bfin_write_SICB_IAR7(val)      bfin_write32(SICB_IAR7, val)
-#define bfin_read_PPI0_CONTROL()       bfin_read16(PPI0_CONTROL)
-#define bfin_write_PPI0_CONTROL(val)   bfin_write16(PPI0_CONTROL, val)
-#define bfin_read_PPI0_STATUS()        bfin_read16(PPI0_STATUS)
-#define bfin_write_PPI0_STATUS(val)    bfin_write16(PPI0_STATUS, val)
-#define bfin_read_PPI0_DELAY()         bfin_read16(PPI0_DELAY)
-#define bfin_write_PPI0_DELAY(val)     bfin_write16(PPI0_DELAY, val)
-#define bfin_read_PPI0_COUNT()         bfin_read16(PPI0_COUNT)
-#define bfin_write_PPI0_COUNT(val)     bfin_write16(PPI0_COUNT, val)
-#define bfin_read_PPI0_FRAME()         bfin_read16(PPI0_FRAME)
-#define bfin_write_PPI0_FRAME(val)     bfin_write16(PPI0_FRAME, val)
-#define bfin_read_PPI1_CONTROL()       bfin_read16(PPI1_CONTROL)
-#define bfin_write_PPI1_CONTROL(val)   bfin_write16(PPI1_CONTROL, val)
-#define bfin_read_PPI1_STATUS()        bfin_read16(PPI1_STATUS)
-#define bfin_write_PPI1_STATUS(val)    bfin_write16(PPI1_STATUS, val)
-#define bfin_read_PPI1_DELAY()         bfin_read16(PPI1_DELAY)
-#define bfin_write_PPI1_DELAY(val)     bfin_write16(PPI1_DELAY, val)
-#define bfin_read_PPI1_COUNT()         bfin_read16(PPI1_COUNT)
-#define bfin_write_PPI1_COUNT(val)     bfin_write16(PPI1_COUNT, val)
-#define bfin_read_PPI1_FRAME()         bfin_read16(PPI1_FRAME)
-#define bfin_write_PPI1_FRAME(val)     bfin_write16(PPI1_FRAME, val)
-#define bfin_read_UART_THR()           bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val)       bfin_write16(UART_THR, val)
-#define bfin_read_UART_RBR()           bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val)       bfin_write16(UART_RBR, val)
-#define bfin_read_UART_DLL()           bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val)       bfin_write16(UART_DLL, val)
-#define bfin_read_UART_DLH()           bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val)       bfin_write16(UART_DLH, val)
-#define bfin_read_UART_IER()           bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val)       bfin_write16(UART_IER, val)
-#define bfin_read_UART_IIR()           bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val)       bfin_write16(UART_IIR, val)
-#define bfin_read_UART_LCR()           bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val)       bfin_write16(UART_LCR, val)
-#define bfin_read_UART_MCR()           bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val)       bfin_write16(UART_MCR, val)
-#define bfin_read_UART_LSR()           bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val)       bfin_write16(UART_LSR, val)
-#define bfin_read_UART_MSR()           bfin_read16(UART_MSR)
-#define bfin_write_UART_MSR(val)       bfin_write16(UART_MSR, val)
-#define bfin_read_UART_SCR()           bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val)       bfin_write16(UART_SCR, val)
-#define bfin_read_UART_GCTL()          bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val)      bfin_write16(UART_GCTL, val)
-#define bfin_read_UART_GBL()           bfin_read16(UART_GBL)
-#define bfin_write_UART_GBL(val)       bfin_write16(UART_GBL, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()        bfin_read32(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)    bfin_write32(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF561_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_def.h b/arch/blackfin/include/asm/mach-bf561/BF561_def.h
deleted file mode 100644
index 8fd552f..0000000
--- a/arch/blackfin/include/asm/mach-bf561/BF561_def.h
+++ /dev/null
@@ -1,719 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF561_proc__
-#define __BFIN_DEF_ADSP_BF561_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL                        0xFFC00000
-#define PLL_DIV                        0xFFC00004
-#define VR_CTL                         0xFFC00008
-#define PLL_STAT                       0xFFC0000C
-#define PLL_LOCKCNT                    0xFFC00010
-#define CHIPID                         0xFFC00014
-#define SPI_CTL                        0xFFC00500
-#define SPI_FLG                        0xFFC00504
-#define SPI_STAT                       0xFFC00508
-#define SPI_TDBR                       0xFFC0050C
-#define SPI_RDBR                       0xFFC00510
-#define SPI_BAUD                       0xFFC00514
-#define SPI_SHADOW                     0xFFC00518
-#define WDOGA_CTL                      0xFFC00200
-#define WDOGA_CNT                      0xFFC00204
-#define WDOGA_STAT                     0xFFC00208
-#define WDOGB_CTL                      0xFFC01200
-#define WDOGB_CNT                      0xFFC01204
-#define WDOGB_STAT                     0xFFC01208
-#define DMA1_TC_PER                    0xFFC01B0C /* Traffic Control Periods */
-#define DMA1_TC_CNT                    0xFFC01B10 /* Traffic Control Current Counts */
-#define DMA1_0_CONFIG                  0xFFC01C08
-#define DMA1_0_NEXT_DESC_PTR           0xFFC01C00
-#define DMA1_0_START_ADDR              0xFFC01C04
-#define DMA1_0_X_COUNT                 0xFFC01C10
-#define DMA1_0_Y_COUNT                 0xFFC01C18
-#define DMA1_0_X_MODIFY                0xFFC01C14
-#define DMA1_0_Y_MODIFY                0xFFC01C1C
-#define DMA1_0_CURR_DESC_PTR           0xFFC01C20
-#define DMA1_0_CURR_ADDR               0xFFC01C24
-#define DMA1_0_CURR_X_COUNT            0xFFC01C30
-#define DMA1_0_CURR_Y_COUNT            0xFFC01C38
-#define DMA1_0_IRQ_STATUS              0xFFC01C28
-#define DMA1_0_PERIPHERAL_MAP          0xFFC01C2C
-#define DMA1_1_CONFIG                  0xFFC01C48
-#define DMA1_1_NEXT_DESC_PTR           0xFFC01C40
-#define DMA1_1_START_ADDR              0xFFC01C44
-#define DMA1_1_X_COUNT                 0xFFC01C50
-#define DMA1_1_Y_COUNT                 0xFFC01C58
-#define DMA1_1_X_MODIFY                0xFFC01C54
-#define DMA1_1_Y_MODIFY                0xFFC01C5C
-#define DMA1_1_CURR_DESC_PTR           0xFFC01C60
-#define DMA1_1_CURR_ADDR               0xFFC01C64
-#define DMA1_1_CURR_X_COUNT            0xFFC01C70
-#define DMA1_1_CURR_Y_COUNT            0xFFC01C78
-#define DMA1_1_IRQ_STATUS              0xFFC01C68
-#define DMA1_1_PERIPHERAL_MAP          0xFFC01C6C
-#define DMA1_2_CONFIG                  0xFFC01C88
-#define DMA1_2_NEXT_DESC_PTR           0xFFC01C80
-#define DMA1_2_START_ADDR              0xFFC01C84
-#define DMA1_2_X_COUNT                 0xFFC01C90
-#define DMA1_2_Y_COUNT                 0xFFC01C98
-#define DMA1_2_X_MODIFY                0xFFC01C94
-#define DMA1_2_Y_MODIFY                0xFFC01C9C
-#define DMA1_2_CURR_DESC_PTR           0xFFC01CA0
-#define DMA1_2_CURR_ADDR               0xFFC01CA4
-#define DMA1_2_CURR_X_COUNT            0xFFC01CB0
-#define DMA1_2_CURR_Y_COUNT            0xFFC01CB8
-#define DMA1_2_IRQ_STATUS              0xFFC01CA8
-#define DMA1_2_PERIPHERAL_MAP          0xFFC01CAC
-#define DMA1_3_CONFIG                  0xFFC01CC8
-#define DMA1_3_NEXT_DESC_PTR           0xFFC01CC0
-#define DMA1_3_START_ADDR              0xFFC01CC4
-#define DMA1_3_X_COUNT                 0xFFC01CD0
-#define DMA1_3_Y_COUNT                 0xFFC01CD8
-#define DMA1_3_X_MODIFY                0xFFC01CD4
-#define DMA1_3_Y_MODIFY                0xFFC01CDC
-#define DMA1_3_CURR_DESC_PTR           0xFFC01CE0
-#define DMA1_3_CURR_ADDR               0xFFC01CE4
-#define DMA1_3_CURR_X_COUNT            0xFFC01CF0
-#define DMA1_3_CURR_Y_COUNT            0xFFC01CF8
-#define DMA1_3_IRQ_STATUS              0xFFC01CE8
-#define DMA1_3_PERIPHERAL_MAP          0xFFC01CEC
-#define DMA1_4_CONFIG                  0xFFC01D08
-#define DMA1_4_NEXT_DESC_PTR           0xFFC01D00
-#define DMA1_4_START_ADDR              0xFFC01D04
-#define DMA1_4_X_COUNT                 0xFFC01D10
-#define DMA1_4_Y_COUNT                 0xFFC01D18
-#define DMA1_4_X_MODIFY                0xFFC01D14
-#define DMA1_4_Y_MODIFY                0xFFC01D1C
-#define DMA1_4_CURR_DESC_PTR           0xFFC01D20
-#define DMA1_4_CURR_ADDR               0xFFC01D24
-#define DMA1_4_CURR_X_COUNT            0xFFC01D30
-#define DMA1_4_CURR_Y_COUNT            0xFFC01D38
-#define DMA1_4_IRQ_STATUS              0xFFC01D28
-#define DMA1_4_PERIPHERAL_MAP          0xFFC01D2C
-#define DMA1_5_CONFIG                  0xFFC01D48
-#define DMA1_5_NEXT_DESC_PTR           0xFFC01D40
-#define DMA1_5_START_ADDR              0xFFC01D44
-#define DMA1_5_X_COUNT                 0xFFC01D50
-#define DMA1_5_Y_COUNT                 0xFFC01D58
-#define DMA1_5_X_MODIFY                0xFFC01D54
-#define DMA1_5_Y_MODIFY                0xFFC01D5C
-#define DMA1_5_CURR_DESC_PTR           0xFFC01D60
-#define DMA1_5_CURR_ADDR               0xFFC01D64
-#define DMA1_5_CURR_X_COUNT            0xFFC01D70
-#define DMA1_5_CURR_Y_COUNT            0xFFC01D78
-#define DMA1_5_IRQ_STATUS              0xFFC01D68
-#define DMA1_5_PERIPHERAL_MAP          0xFFC01D6C
-#define DMA1_6_CONFIG                  0xFFC01D88
-#define DMA1_6_NEXT_DESC_PTR           0xFFC01D80
-#define DMA1_6_START_ADDR              0xFFC01D84
-#define DMA1_6_X_COUNT                 0xFFC01D90
-#define DMA1_6_Y_COUNT                 0xFFC01D98
-#define DMA1_6_X_MODIFY                0xFFC01D94
-#define DMA1_6_Y_MODIFY                0xFFC01D9C
-#define DMA1_6_CURR_DESC_PTR           0xFFC01DA0
-#define DMA1_6_CURR_ADDR               0xFFC01DA4
-#define DMA1_6_CURR_X_COUNT            0xFFC01DB0
-#define DMA1_6_CURR_Y_COUNT            0xFFC01DB8
-#define DMA1_6_IRQ_STATUS              0xFFC01DA8
-#define DMA1_6_PERIPHERAL_MAP          0xFFC01DAC
-#define DMA1_7_CONFIG                  0xFFC01DC8
-#define DMA1_7_NEXT_DESC_PTR           0xFFC01DC0
-#define DMA1_7_START_ADDR              0xFFC01DC4
-#define DMA1_7_X_COUNT                 0xFFC01DD0
-#define DMA1_7_Y_COUNT                 0xFFC01DD8
-#define DMA1_7_X_MODIFY                0xFFC01DD4
-#define DMA1_7_Y_MODIFY                0xFFC01DDC
-#define DMA1_7_CURR_DESC_PTR           0xFFC01DE0
-#define DMA1_7_CURR_ADDR               0xFFC01DE4
-#define DMA1_7_CURR_X_COUNT            0xFFC01DF0
-#define DMA1_7_CURR_Y_COUNT            0xFFC01DF8
-#define DMA1_7_IRQ_STATUS              0xFFC01DE8
-#define DMA1_7_PERIPHERAL_MAP          0xFFC01DEC
-#define DMA1_8_CONFIG                  0xFFC01E08
-#define DMA1_8_NEXT_DESC_PTR           0xFFC01E00
-#define DMA1_8_START_ADDR              0xFFC01E04
-#define DMA1_8_X_COUNT                 0xFFC01E10
-#define DMA1_8_Y_COUNT                 0xFFC01E18
-#define DMA1_8_X_MODIFY                0xFFC01E14
-#define DMA1_8_Y_MODIFY                0xFFC01E1C
-#define DMA1_8_CURR_DESC_PTR           0xFFC01E20
-#define DMA1_8_CURR_ADDR               0xFFC01E24
-#define DMA1_8_CURR_X_COUNT            0xFFC01E30
-#define DMA1_8_CURR_Y_COUNT            0xFFC01E38
-#define DMA1_8_IRQ_STATUS              0xFFC01E28
-#define DMA1_8_PERIPHERAL_MAP          0xFFC01E2C
-#define DMA1_9_CONFIG                  0xFFC01E48
-#define DMA1_9_NEXT_DESC_PTR           0xFFC01E40
-#define DMA1_9_START_ADDR              0xFFC01E44
-#define DMA1_9_X_COUNT                 0xFFC01E50
-#define DMA1_9_Y_COUNT                 0xFFC01E58
-#define DMA1_9_X_MODIFY                0xFFC01E54
-#define DMA1_9_Y_MODIFY                0xFFC01E5C
-#define DMA1_9_CURR_DESC_PTR           0xFFC01E60
-#define DMA1_9_CURR_ADDR               0xFFC01E64
-#define DMA1_9_CURR_X_COUNT            0xFFC01E70
-#define DMA1_9_CURR_Y_COUNT            0xFFC01E78
-#define DMA1_9_IRQ_STATUS              0xFFC01E68
-#define DMA1_9_PERIPHERAL_MAP          0xFFC01E6C
-#define DMA1_10_CONFIG                 0xFFC01E88
-#define DMA1_10_NEXT_DESC_PTR          0xFFC01E80
-#define DMA1_10_START_ADDR             0xFFC01E84
-#define DMA1_10_X_COUNT                0xFFC01E90
-#define DMA1_10_Y_COUNT                0xFFC01E98
-#define DMA1_10_X_MODIFY               0xFFC01E94
-#define DMA1_10_Y_MODIFY               0xFFC01E9C
-#define DMA1_10_CURR_DESC_PTR          0xFFC01EA0
-#define DMA1_10_CURR_ADDR              0xFFC01EA4
-#define DMA1_10_CURR_X_COUNT           0xFFC01EB0
-#define DMA1_10_CURR_Y_COUNT           0xFFC01EB8
-#define DMA1_10_IRQ_STATUS             0xFFC01EA8
-#define DMA1_10_PERIPHERAL_MAP         0xFFC01EAC
-#define DMA1_11_CONFIG                 0xFFC01EC8
-#define DMA1_11_NEXT_DESC_PTR          0xFFC01EC0
-#define DMA1_11_START_ADDR             0xFFC01EC4
-#define DMA1_11_X_COUNT                0xFFC01ED0
-#define DMA1_11_Y_COUNT                0xFFC01ED8
-#define DMA1_11_X_MODIFY               0xFFC01ED4
-#define DMA1_11_Y_MODIFY               0xFFC01EDC
-#define DMA1_11_CURR_DESC_PTR          0xFFC01EE0
-#define DMA1_11_CURR_ADDR              0xFFC01EE4
-#define DMA1_11_CURR_X_COUNT           0xFFC01EF0
-#define DMA1_11_CURR_Y_COUNT           0xFFC01EF8
-#define DMA1_11_IRQ_STATUS             0xFFC01EE8
-#define DMA1_11_PERIPHERAL_MAP         0xFFC01EEC
-#define DMA2_TC_PER                    0xFFC00B0C
-#define DMA2_TC_CNT                    0xFFC01B10 /* Traffic Control Current Counts */
-#define DMA2_0_CONFIG                  0xFFC00C08
-#define DMA2_0_NEXT_DESC_PTR           0xFFC00C00
-#define DMA2_0_START_ADDR              0xFFC00C04
-#define DMA2_0_X_COUNT                 0xFFC00C10
-#define DMA2_0_Y_COUNT                 0xFFC00C18
-#define DMA2_0_X_MODIFY                0xFFC00C14
-#define DMA2_0_Y_MODIFY                0xFFC00C1C
-#define DMA2_0_CURR_DESC_PTR           0xFFC00C20
-#define DMA2_0_CURR_ADDR               0xFFC00C24
-#define DMA2_0_CURR_X_COUNT            0xFFC00C30
-#define DMA2_0_CURR_Y_COUNT            0xFFC00C38
-#define DMA2_0_IRQ_STATUS              0xFFC00C28
-#define DMA2_0_PERIPHERAL_MAP          0xFFC00C2C
-#define DMA2_1_CONFIG                  0xFFC00C48
-#define DMA2_1_NEXT_DESC_PTR           0xFFC00C40
-#define DMA2_1_START_ADDR              0xFFC00C44
-#define DMA2_1_X_COUNT                 0xFFC00C50
-#define DMA2_1_Y_COUNT                 0xFFC00C58
-#define DMA2_1_X_MODIFY                0xFFC00C54
-#define DMA2_1_Y_MODIFY                0xFFC00C5C
-#define DMA2_1_CURR_DESC_PTR           0xFFC00C60
-#define DMA2_1_CURR_ADDR               0xFFC00C64
-#define DMA2_1_CURR_X_COUNT            0xFFC00C70
-#define DMA2_1_CURR_Y_COUNT            0xFFC00C78
-#define DMA2_1_IRQ_STATUS              0xFFC00C68
-#define DMA2_1_PERIPHERAL_MAP          0xFFC00C6C
-#define DMA2_2_CONFIG                  0xFFC00C88
-#define DMA2_2_NEXT_DESC_PTR           0xFFC00C80
-#define DMA2_2_START_ADDR              0xFFC00C84
-#define DMA2_2_X_COUNT                 0xFFC00C90
-#define DMA2_2_Y_COUNT                 0xFFC00C98
-#define DMA2_2_X_MODIFY                0xFFC00C94
-#define DMA2_2_Y_MODIFY                0xFFC00C9C
-#define DMA2_2_CURR_DESC_PTR           0xFFC00CA0
-#define DMA2_2_CURR_ADDR               0xFFC00CA4
-#define DMA2_2_CURR_X_COUNT            0xFFC00CB0
-#define DMA2_2_CURR_Y_COUNT            0xFFC00CB8
-#define DMA2_2_IRQ_STATUS              0xFFC00CA8
-#define DMA2_2_PERIPHERAL_MAP          0xFFC00CAC
-#define DMA2_3_CONFIG                  0xFFC00CC8
-#define DMA2_3_NEXT_DESC_PTR           0xFFC00CC0
-#define DMA2_3_START_ADDR              0xFFC00CC4
-#define DMA2_3_X_COUNT                 0xFFC00CD0
-#define DMA2_3_Y_COUNT                 0xFFC00CD8
-#define DMA2_3_X_MODIFY                0xFFC00CD4
-#define DMA2_3_Y_MODIFY                0xFFC00CDC
-#define DMA2_3_CURR_DESC_PTR           0xFFC00CE0
-#define DMA2_3_CURR_ADDR               0xFFC00CE4
-#define DMA2_3_CURR_X_COUNT            0xFFC00CF0
-#define DMA2_3_CURR_Y_COUNT            0xFFC00CF8
-#define DMA2_3_IRQ_STATUS              0xFFC00CE8
-#define DMA2_3_PERIPHERAL_MAP          0xFFC00CEC
-#define DMA2_4_CONFIG                  0xFFC00D08
-#define DMA2_4_NEXT_DESC_PTR           0xFFC00D00
-#define DMA2_4_START_ADDR              0xFFC00D04
-#define DMA2_4_X_COUNT                 0xFFC00D10
-#define DMA2_4_Y_COUNT                 0xFFC00D18
-#define DMA2_4_X_MODIFY                0xFFC00D14
-#define DMA2_4_Y_MODIFY                0xFFC00D1C
-#define DMA2_4_CURR_DESC_PTR           0xFFC00D20
-#define DMA2_4_CURR_ADDR               0xFFC00D24
-#define DMA2_4_CURR_X_COUNT            0xFFC00D30
-#define DMA2_4_CURR_Y_COUNT            0xFFC00D38
-#define DMA2_4_IRQ_STATUS              0xFFC00D28
-#define DMA2_4_PERIPHERAL_MAP          0xFFC00D2C
-#define DMA2_5_CONFIG                  0xFFC00D48
-#define DMA2_5_NEXT_DESC_PTR           0xFFC00D40
-#define DMA2_5_START_ADDR              0xFFC00D44
-#define DMA2_5_X_COUNT                 0xFFC00D50
-#define DMA2_5_Y_COUNT                 0xFFC00D58
-#define DMA2_5_X_MODIFY                0xFFC00D54
-#define DMA2_5_Y_MODIFY                0xFFC00D5C
-#define DMA2_5_CURR_DESC_PTR           0xFFC00D60
-#define DMA2_5_CURR_ADDR               0xFFC00D64
-#define DMA2_5_CURR_X_COUNT            0xFFC00D70
-#define DMA2_5_CURR_Y_COUNT            0xFFC00D78
-#define DMA2_5_IRQ_STATUS              0xFFC00D68
-#define DMA2_5_PERIPHERAL_MAP          0xFFC00D6C
-#define DMA2_6_CONFIG                  0xFFC00D88
-#define DMA2_6_NEXT_DESC_PTR           0xFFC00D80
-#define DMA2_6_START_ADDR              0xFFC00D84
-#define DMA2_6_X_COUNT                 0xFFC00D90
-#define DMA2_6_Y_COUNT                 0xFFC00D98
-#define DMA2_6_X_MODIFY                0xFFC00D94
-#define DMA2_6_Y_MODIFY                0xFFC00D9C
-#define DMA2_6_CURR_DESC_PTR           0xFFC00DA0
-#define DMA2_6_CURR_ADDR               0xFFC00DA4
-#define DMA2_6_CURR_X_COUNT            0xFFC00DB0
-#define DMA2_6_CURR_Y_COUNT            0xFFC00DB8
-#define DMA2_6_IRQ_STATUS              0xFFC00DA8
-#define DMA2_6_PERIPHERAL_MAP          0xFFC00DAC
-#define DMA2_7_CONFIG                  0xFFC00DC8
-#define DMA2_7_NEXT_DESC_PTR           0xFFC00DC0
-#define DMA2_7_START_ADDR              0xFFC00DC4
-#define DMA2_7_X_COUNT                 0xFFC00DD0
-#define DMA2_7_Y_COUNT                 0xFFC00DD8
-#define DMA2_7_X_MODIFY                0xFFC00DD4
-#define DMA2_7_Y_MODIFY                0xFFC00DDC
-#define DMA2_7_CURR_DESC_PTR           0xFFC00DE0
-#define DMA2_7_CURR_ADDR               0xFFC00DE4
-#define DMA2_7_CURR_X_COUNT            0xFFC00DF0
-#define DMA2_7_CURR_Y_COUNT            0xFFC00DF8
-#define DMA2_7_IRQ_STATUS              0xFFC00DE8
-#define DMA2_7_PERIPHERAL_MAP          0xFFC00DEC
-#define DMA2_8_CONFIG                  0xFFC00E08
-#define DMA2_8_NEXT_DESC_PTR           0xFFC00E00
-#define DMA2_8_START_ADDR              0xFFC00E04
-#define DMA2_8_X_COUNT                 0xFFC00E10
-#define DMA2_8_Y_COUNT                 0xFFC00E18
-#define DMA2_8_X_MODIFY                0xFFC00E14
-#define DMA2_8_Y_MODIFY                0xFFC00E1C
-#define DMA2_8_CURR_DESC_PTR           0xFFC00E20
-#define DMA2_8_CURR_ADDR               0xFFC00E24
-#define DMA2_8_CURR_X_COUNT            0xFFC00E30
-#define DMA2_8_CURR_Y_COUNT            0xFFC00E38
-#define DMA2_8_IRQ_STATUS              0xFFC00E28
-#define DMA2_8_PERIPHERAL_MAP          0xFFC00E2C
-#define DMA2_9_CONFIG                  0xFFC00E48
-#define DMA2_9_NEXT_DESC_PTR           0xFFC00E40
-#define DMA2_9_START_ADDR              0xFFC00E44
-#define DMA2_9_X_COUNT                 0xFFC00E50
-#define DMA2_9_Y_COUNT                 0xFFC00E58
-#define DMA2_9_X_MODIFY                0xFFC00E54
-#define DMA2_9_Y_MODIFY                0xFFC00E5C
-#define DMA2_9_CURR_DESC_PTR           0xFFC00E60
-#define DMA2_9_CURR_ADDR               0xFFC00E64
-#define DMA2_9_CURR_X_COUNT            0xFFC00E70
-#define DMA2_9_CURR_Y_COUNT            0xFFC00E78
-#define DMA2_9_IRQ_STATUS              0xFFC00E68
-#define DMA2_9_PERIPHERAL_MAP          0xFFC00E6C
-#define DMA2_10_CONFIG                 0xFFC00E88
-#define DMA2_10_NEXT_DESC_PTR          0xFFC00E80
-#define DMA2_10_START_ADDR             0xFFC00E84
-#define DMA2_10_X_COUNT                0xFFC00E90
-#define DMA2_10_Y_COUNT                0xFFC00E98
-#define DMA2_10_X_MODIFY               0xFFC00E94
-#define DMA2_10_Y_MODIFY               0xFFC00E9C
-#define DMA2_10_CURR_DESC_PTR          0xFFC00EA0
-#define DMA2_10_CURR_ADDR              0xFFC00EA4
-#define DMA2_10_CURR_X_COUNT           0xFFC00EB0
-#define DMA2_10_CURR_Y_COUNT           0xFFC00EB8
-#define DMA2_10_IRQ_STATUS             0xFFC00EA8
-#define DMA2_10_PERIPHERAL_MAP         0xFFC00EAC
-#define DMA2_11_CONFIG                 0xFFC00EC8
-#define DMA2_11_NEXT_DESC_PTR          0xFFC00EC0
-#define DMA2_11_START_ADDR             0xFFC00EC4
-#define DMA2_11_X_COUNT                0xFFC00ED0
-#define DMA2_11_Y_COUNT                0xFFC00ED8
-#define DMA2_11_X_MODIFY               0xFFC00ED4
-#define DMA2_11_Y_MODIFY               0xFFC00EDC
-#define DMA2_11_CURR_DESC_PTR          0xFFC00EE0
-#define DMA2_11_CURR_ADDR              0xFFC00EE4
-#define DMA2_11_CURR_X_COUNT           0xFFC00EF0
-#define DMA2_11_CURR_Y_COUNT           0xFFC00EF8
-#define DMA2_11_IRQ_STATUS             0xFFC00EE8
-#define DMA2_11_PERIPHERAL_MAP         0xFFC00EEC
-#define IMDMA_S0_CONFIG                0xFFC01848
-#define IMDMA_S0_NEXT_DESC_PTR         0xFFC01840
-#define IMDMA_S0_START_ADDR            0xFFC01844
-#define IMDMA_S0_X_COUNT               0xFFC01850
-#define IMDMA_S0_Y_COUNT               0xFFC01858
-#define IMDMA_S0_X_MODIFY              0xFFC01854
-#define IMDMA_S0_Y_MODIFY              0xFFC0185C
-#define IMDMA_S0_CURR_DESC_PTR         0xFFC01860
-#define IMDMA_S0_CURR_ADDR             0xFFC01864
-#define IMDMA_S0_CURR_X_COUNT          0xFFC01870
-#define IMDMA_S0_CURR_Y_COUNT          0xFFC01878
-#define IMDMA_S0_IRQ_STATUS            0xFFC01868
-#define IMDMA_D0_CONFIG                0xFFC01808
-#define IMDMA_D0_NEXT_DESC_PTR         0xFFC01800
-#define IMDMA_D0_START_ADDR            0xFFC01804
-#define IMDMA_D0_X_COUNT               0xFFC01810
-#define IMDMA_D0_Y_COUNT               0xFFC01818
-#define IMDMA_D0_X_MODIFY              0xFFC01814
-#define IMDMA_D0_Y_MODIFY              0xFFC0181C
-#define IMDMA_D0_CURR_DESC_PTR         0xFFC01820
-#define IMDMA_D0_CURR_ADDR             0xFFC01824
-#define IMDMA_D0_CURR_X_COUNT          0xFFC01830
-#define IMDMA_D0_CURR_Y_COUNT          0xFFC01838
-#define IMDMA_D0_IRQ_STATUS            0xFFC01828
-#define IMDMA_S1_CONFIG                0xFFC018C8
-#define IMDMA_S1_NEXT_DESC_PTR         0xFFC018C0
-#define IMDMA_S1_START_ADDR            0xFFC018C4
-#define IMDMA_S1_X_COUNT               0xFFC018D0
-#define IMDMA_S1_Y_COUNT               0xFFC018D8
-#define IMDMA_S1_X_MODIFY              0xFFC018D4
-#define IMDMA_S1_Y_MODIFY              0xFFC018DC
-#define IMDMA_S1_CURR_DESC_PTR         0xFFC018E0
-#define IMDMA_S1_CURR_ADDR             0xFFC018E4
-#define IMDMA_S1_CURR_X_COUNT          0xFFC018F0
-#define IMDMA_S1_CURR_Y_COUNT          0xFFC018F8
-#define IMDMA_S1_IRQ_STATUS            0xFFC018E8
-#define IMDMA_D1_CONFIG                0xFFC01888
-#define IMDMA_D1_NEXT_DESC_PTR         0xFFC01880
-#define IMDMA_D1_START_ADDR            0xFFC01884
-#define IMDMA_D1_X_COUNT               0xFFC01890
-#define IMDMA_D1_Y_COUNT               0xFFC01898
-#define IMDMA_D1_X_MODIFY              0xFFC01894
-#define IMDMA_D1_Y_MODIFY              0xFFC0189C
-#define IMDMA_D1_CURR_DESC_PTR         0xFFC018A0
-#define IMDMA_D1_CURR_ADDR             0xFFC018A4
-#define IMDMA_D1_CURR_X_COUNT          0xFFC018B0
-#define IMDMA_D1_CURR_Y_COUNT          0xFFC018B8
-#define IMDMA_D1_IRQ_STATUS            0xFFC018A8
-#define MDMA1_S0_CONFIG                0xFFC01F48
-#define MDMA1_S0_NEXT_DESC_PTR         0xFFC01F40
-#define MDMA1_S0_START_ADDR            0xFFC01F44
-#define MDMA1_S0_X_COUNT               0xFFC01F50
-#define MDMA1_S0_Y_COUNT               0xFFC01F58
-#define MDMA1_S0_X_MODIFY              0xFFC01F54
-#define MDMA1_S0_Y_MODIFY              0xFFC01F5C
-#define MDMA1_S0_CURR_DESC_PTR         0xFFC01F60
-#define MDMA1_S0_CURR_ADDR             0xFFC01F64
-#define MDMA1_S0_CURR_X_COUNT          0xFFC01F70
-#define MDMA1_S0_CURR_Y_COUNT          0xFFC01F78
-#define MDMA1_S0_IRQ_STATUS            0xFFC01F68
-#define MDMA1_S0_PERIPHERAL_MAP        0xFFC01F6C
-#define MDMA1_D0_CONFIG                0xFFC01F08
-#define MDMA1_D0_NEXT_DESC_PTR         0xFFC01F00
-#define MDMA1_D0_START_ADDR            0xFFC01F04
-#define MDMA1_D0_X_COUNT               0xFFC01F10
-#define MDMA1_D0_Y_COUNT               0xFFC01F18
-#define MDMA1_D0_X_MODIFY              0xFFC01F14
-#define MDMA1_D0_Y_MODIFY              0xFFC01F1C
-#define MDMA1_D0_CURR_DESC_PTR         0xFFC01F20
-#define MDMA1_D0_CURR_ADDR             0xFFC01F24
-#define MDMA1_D0_CURR_X_COUNT          0xFFC01F30
-#define MDMA1_D0_CURR_Y_COUNT          0xFFC01F38
-#define MDMA1_D0_IRQ_STATUS            0xFFC01F28
-#define MDMA1_D0_PERIPHERAL_MAP        0xFFC01F2C
-#define MDMA1_S1_CONFIG                0xFFC01FC8
-#define MDMA1_S1_NEXT_DESC_PTR         0xFFC01FC0
-#define MDMA1_S1_START_ADDR            0xFFC01FC4
-#define MDMA1_S1_X_COUNT               0xFFC01FD0
-#define MDMA1_S1_Y_COUNT               0xFFC01FD8
-#define MDMA1_S1_X_MODIFY              0xFFC01FD4
-#define MDMA1_S1_Y_MODIFY              0xFFC01FDC
-#define MDMA1_S1_CURR_DESC_PTR         0xFFC01FE0
-#define MDMA1_S1_CURR_ADDR             0xFFC01FE4
-#define MDMA1_S1_CURR_X_COUNT          0xFFC01FF0
-#define MDMA1_S1_CURR_Y_COUNT          0xFFC01FF8
-#define MDMA1_S1_IRQ_STATUS            0xFFC01FE8
-#define MDMA1_S1_PERIPHERAL_MAP        0xFFC01FEC
-#define MDMA1_D1_CONFIG                0xFFC01F88
-#define MDMA1_D1_NEXT_DESC_PTR         0xFFC01F80
-#define MDMA1_D1_START_ADDR            0xFFC01F84
-#define MDMA1_D1_X_COUNT               0xFFC01F90
-#define MDMA1_D1_Y_COUNT               0xFFC01F98
-#define MDMA1_D1_X_MODIFY              0xFFC01F94
-#define MDMA1_D1_Y_MODIFY              0xFFC01F9C
-#define MDMA1_D1_CURR_DESC_PTR         0xFFC01FA0
-#define MDMA1_D1_CURR_ADDR             0xFFC01FA4
-#define MDMA1_D1_CURR_X_COUNT          0xFFC01FB0
-#define MDMA1_D1_CURR_Y_COUNT          0xFFC01FB8
-#define MDMA1_D1_IRQ_STATUS            0xFFC01FA8
-#define MDMA1_D1_PERIPHERAL_MAP        0xFFC01FAC
-#define MDMA2_S0_CONFIG                0xFFC00F48
-#define MDMA2_S0_NEXT_DESC_PTR         0xFFC00F40
-#define MDMA2_S0_START_ADDR            0xFFC00F44
-#define MDMA2_S0_X_COUNT               0xFFC00F50
-#define MDMA2_S0_Y_COUNT               0xFFC00F58
-#define MDMA2_S0_X_MODIFY              0xFFC00F54
-#define MDMA2_S0_Y_MODIFY              0xFFC00F5C
-#define MDMA2_S0_CURR_DESC_PTR         0xFFC00F60
-#define MDMA2_S0_CURR_ADDR             0xFFC00F64
-#define MDMA2_S0_CURR_X_COUNT          0xFFC00F70
-#define MDMA2_S0_CURR_Y_COUNT          0xFFC00F78
-#define MDMA2_S0_IRQ_STATUS            0xFFC00F68
-#define MDMA2_S0_PERIPHERAL_MAP        0xFFC00F6C
-#define MDMA2_D0_CONFIG                0xFFC00F08
-#define MDMA2_D0_NEXT_DESC_PTR         0xFFC00F00
-#define MDMA2_D0_START_ADDR            0xFFC00F04
-#define MDMA2_D0_X_COUNT               0xFFC00F10
-#define MDMA2_D0_Y_COUNT               0xFFC00F18
-#define MDMA2_D0_X_MODIFY              0xFFC00F14
-#define MDMA2_D0_Y_MODIFY              0xFFC00F1C
-#define MDMA2_D0_CURR_DESC_PTR         0xFFC00F20
-#define MDMA2_D0_CURR_ADDR             0xFFC00F24
-#define MDMA2_D0_CURR_X_COUNT          0xFFC00F30
-#define MDMA2_D0_CURR_Y_COUNT          0xFFC00F38
-#define MDMA2_D0_IRQ_STATUS            0xFFC00F28
-#define MDMA2_D0_PERIPHERAL_MAP        0xFFC00F2C
-#define MDMA2_S1_CONFIG                0xFFC00FC8
-#define MDMA2_S1_NEXT_DESC_PTR         0xFFC00FC0
-#define MDMA2_S1_START_ADDR            0xFFC00FC4
-#define MDMA2_S1_X_COUNT               0xFFC00FD0
-#define MDMA2_S1_Y_COUNT               0xFFC00FD8
-#define MDMA2_S1_X_MODIFY              0xFFC00FD4
-#define MDMA2_S1_Y_MODIFY              0xFFC00FDC
-#define MDMA2_S1_CURR_DESC_PTR         0xFFC00FE0
-#define MDMA2_S1_CURR_ADDR             0xFFC00FE4
-#define MDMA2_S1_CURR_X_COUNT          0xFFC00FF0
-#define MDMA2_S1_CURR_Y_COUNT          0xFFC00FF8
-#define MDMA2_S1_IRQ_STATUS            0xFFC00FE8
-#define MDMA2_S1_PERIPHERAL_MAP        0xFFC00FEC
-#define MDMA2_D1_CONFIG                0xFFC00F88
-#define MDMA2_D1_NEXT_DESC_PTR         0xFFC00F80
-#define MDMA2_D1_START_ADDR            0xFFC00F84
-#define MDMA2_D1_X_COUNT               0xFFC00F90
-#define MDMA2_D1_Y_COUNT               0xFFC00F98
-#define MDMA2_D1_X_MODIFY              0xFFC00F94
-#define MDMA2_D1_Y_MODIFY              0xFFC00F9C
-#define MDMA2_D1_CURR_DESC_PTR         0xFFC00FA0
-#define MDMA2_D1_CURR_ADDR             0xFFC00FA4
-#define MDMA2_D1_CURR_X_COUNT          0xFFC00FB0
-#define MDMA2_D1_CURR_Y_COUNT          0xFFC00FB8
-#define MDMA2_D1_IRQ_STATUS            0xFFC00FA8
-#define MDMA2_D1_PERIPHERAL_MAP        0xFFC00FAC
-#define TIMER0_CONFIG                  0xFFC00600
-#define TIMER0_COUNTER                 0xFFC00604
-#define TIMER0_PERIOD                  0xFFC00608
-#define TIMER0_WIDTH                   0xFFC0060C
-#define TIMER1_CONFIG                  0xFFC00610
-#define TIMER1_COUNTER                 0xFFC00614
-#define TIMER1_PERIOD                  0xFFC00618
-#define TIMER1_WIDTH                   0xFFC0061C
-#define TIMER2_CONFIG                  0xFFC00620
-#define TIMER2_COUNTER                 0xFFC00624
-#define TIMER2_PERIOD                  0xFFC00628
-#define TIMER2_WIDTH                   0xFFC0062C
-#define TIMER3_CONFIG                  0xFFC00630
-#define TIMER3_COUNTER                 0xFFC00634
-#define TIMER3_PERIOD                  0xFFC00638
-#define TIMER3_WIDTH                   0xFFC0063C
-#define TIMER4_CONFIG                  0xFFC00640
-#define TIMER4_COUNTER                 0xFFC00644
-#define TIMER4_PERIOD                  0xFFC00648
-#define TIMER4_WIDTH                   0xFFC0064C
-#define TIMER5_CONFIG                  0xFFC00650
-#define TIMER5_COUNTER                 0xFFC00654
-#define TIMER5_PERIOD                  0xFFC00658
-#define TIMER5_WIDTH                   0xFFC0065C
-#define TIMER6_CONFIG                  0xFFC00660
-#define TIMER6_COUNTER                 0xFFC00664
-#define TIMER6_PERIOD                  0xFFC00668
-#define TIMER6_WIDTH                   0xFFC0066C
-#define TIMER7_CONFIG                  0xFFC00670
-#define TIMER7_COUNTER                 0xFFC00674
-#define TIMER7_PERIOD                  0xFFC00678
-#define TIMER7_WIDTH                   0xFFC0067C
-#define TIMER8_CONFIG                  0xFFC01600
-#define TIMER8_COUNTER                 0xFFC01604
-#define TIMER8_PERIOD                  0xFFC01608
-#define TIMER8_WIDTH                   0xFFC0160C
-#define TIMER9_CONFIG                  0xFFC01610
-#define TIMER9_COUNTER                 0xFFC01614
-#define TIMER9_PERIOD                  0xFFC01618
-#define TIMER9_WIDTH                   0xFFC0161C
-#define TIMER10_CONFIG                 0xFFC01620
-#define TIMER10_COUNTER                0xFFC01624
-#define TIMER10_PERIOD                 0xFFC01628
-#define TIMER10_WIDTH                  0xFFC0162C
-#define TIMER11_CONFIG                 0xFFC01630
-#define TIMER11_COUNTER                0xFFC01634
-#define TIMER11_PERIOD                 0xFFC01638
-#define TIMER11_WIDTH                  0xFFC0163C
-#define TMRS4_ENABLE                   0xFFC01640
-#define TMRS4_DISABLE                  0xFFC01644
-#define TMRS4_STATUS                   0xFFC01648
-#define TMRS8_ENABLE                   0xFFC00680
-#define TMRS8_DISABLE                  0xFFC00684
-#define TMRS8_STATUS                   0xFFC00688
-#define FIO0_FLAG_D                    0xFFC00700
-#define FIO0_FLAG_C                    0xFFC00704
-#define FIO0_FLAG_S                    0xFFC00708
-#define FIO0_FLAG_T                    0xFFC0070C
-#define FIO0_MASKA_D                   0xFFC00710
-#define FIO0_MASKA_C                   0xFFC00714
-#define FIO0_MASKA_S                   0xFFC00718
-#define FIO0_MASKA_T                   0xFFC0071C
-#define FIO0_MASKB_D                   0xFFC00720
-#define FIO0_MASKB_C                   0xFFC00724
-#define FIO0_MASKB_S                   0xFFC00728
-#define FIO0_MASKB_T                   0xFFC0072C
-#define FIO0_DIR                       0xFFC00730
-#define FIO0_POLAR                     0xFFC00734
-#define FIO0_EDGE                      0xFFC00738
-#define FIO0_BOTH                      0xFFC0073C
-#define FIO0_INEN                      0xFFC00740
-#define FIO1_FLAG_D                    0xFFC01500
-#define FIO1_FLAG_C                    0xFFC01504
-#define FIO1_FLAG_S                    0xFFC01508
-#define FIO1_FLAG_T                    0xFFC0150C
-#define FIO1_MASKA_D                   0xFFC01510
-#define FIO1_MASKA_C                   0xFFC01514
-#define FIO1_MASKA_S                   0xFFC01518
-#define FIO1_MASKA_T                   0xFFC0151C
-#define FIO1_MASKB_D                   0xFFC01520
-#define FIO1_MASKB_C                   0xFFC01524
-#define FIO1_MASKB_S                   0xFFC01528
-#define FIO1_MASKB_T                   0xFFC0152C
-#define FIO1_DIR                       0xFFC01530
-#define FIO1_POLAR                     0xFFC01534
-#define FIO1_EDGE                      0xFFC01538
-#define FIO1_BOTH                      0xFFC0153C
-#define FIO1_INEN                      0xFFC01540
-#define FIO2_FLAG_D                    0xFFC01700
-#define FIO2_FLAG_C                    0xFFC01704
-#define FIO2_FLAG_S                    0xFFC01708
-#define FIO2_FLAG_T                    0xFFC0170C
-#define FIO2_MASKA_D                   0xFFC01710
-#define FIO2_MASKA_C                   0xFFC01714
-#define FIO2_MASKA_S                   0xFFC01718
-#define FIO2_MASKA_T                   0xFFC0171C
-#define FIO2_MASKB_D                   0xFFC01720
-#define FIO2_MASKB_C                   0xFFC01724
-#define FIO2_MASKB_S                   0xFFC01728
-#define FIO2_MASKB_T                   0xFFC0172C
-#define FIO2_DIR                       0xFFC01730
-#define FIO2_POLAR                     0xFFC01734
-#define FIO2_EDGE                      0xFFC01738
-#define FIO2_BOTH                      0xFFC0173C
-#define FIO2_INEN                      0xFFC01740
-#define SPORT0_TCR1                    0xFFC00800
-#define SPORT0_TCR2                    0xFFC00804
-#define SPORT0_TCLKDIV                 0xFFC00808
-#define SPORT0_TFSDIV                  0xFFC0080C
-#define SPORT0_TX                      0xFFC00810
-#define SPORT0_RX                      0xFFC00818
-#define SPORT0_RCR1                    0xFFC00820
-#define SPORT0_RCR2                    0xFFC00824
-#define SPORT0_RCLKDIV                 0xFFC00828
-#define SPORT0_RFSDIV                  0xFFC0082C
-#define SPORT0_STAT                    0xFFC00830
-#define SPORT0_CHNL                    0xFFC00834
-#define SPORT0_MCMC1                   0xFFC00838
-#define SPORT0_MCMC2                   0xFFC0083C
-#define SPORT0_MTCS0                   0xFFC00840
-#define SPORT0_MTCS1                   0xFFC00844
-#define SPORT0_MTCS2                   0xFFC00848
-#define SPORT0_MTCS3                   0xFFC0084C
-#define SPORT0_MRCS0                   0xFFC00850
-#define SPORT0_MRCS1                   0xFFC00854
-#define SPORT0_MRCS2                   0xFFC00858
-#define SPORT0_MRCS3                   0xFFC0085C
-#define SPORT1_TCR1                    0xFFC00900
-#define SPORT1_TCR2                    0xFFC00904
-#define SPORT1_TCLKDIV                 0xFFC00908
-#define SPORT1_TFSDIV                  0xFFC0090C
-#define SPORT1_TX                      0xFFC00910
-#define SPORT1_RX                      0xFFC00918
-#define SPORT1_RCR1                    0xFFC00920
-#define SPORT1_RCR2                    0xFFC00924
-#define SPORT1_RCLKDIV                 0xFFC00928
-#define SPORT1_RFSDIV                  0xFFC0092C
-#define SPORT1_STAT                    0xFFC00930
-#define SPORT1_CHNL                    0xFFC00934
-#define SPORT1_MCMC1                   0xFFC00938
-#define SPORT1_MCMC2                   0xFFC0093C
-#define SPORT1_MTCS0                   0xFFC00940
-#define SPORT1_MTCS1                   0xFFC00944
-#define SPORT1_MTCS2                   0xFFC00948
-#define SPORT1_MTCS3                   0xFFC0094C
-#define SPORT1_MRCS0                   0xFFC00950
-#define SPORT1_MRCS1                   0xFFC00954
-#define SPORT1_MRCS2                   0xFFC00958
-#define SPORT1_MRCS3                   0xFFC0095C
-#define SICA_SWRST                     0xFFC00100
-#define SICA_SYSCR                     0xFFC00104
-#define SICA_RVECT                     0xFFC00108
-#define SICA_IMASK0                    0xFFC0010C
-#define SICA_IMASK1                    0xFFC00110
-#define SICA_ISR0                      0xFFC00114
-#define SICA_ISR1                      0xFFC00118
-#define SICA_IWR0                      0xFFC0011C
-#define SICA_IWR1                      0xFFC00120
-#define SICA_IAR0                      0xFFC00124
-#define SICA_IAR1                      0xFFC00128
-#define SICA_IAR2                      0xFFC0012C
-#define SICA_IAR3                      0xFFC00130
-#define SICA_IAR4                      0xFFC00134
-#define SICA_IAR5                      0xFFC00138
-#define SICA_IAR6                      0xFFC0013C
-#define SICA_IAR7                      0xFFC00140
-#define SICB_SWRST                     0xFFC01100
-#define SICB_SYSCR                     0xFFC01104
-#define SICB_RVECT                     0xFFC01108
-#define SICB_IMASK0                    0xFFC0110C
-#define SICB_IMASK1                    0xFFC01110
-#define SICB_ISR0                      0xFFC01114
-#define SICB_ISR1                      0xFFC01118
-#define SICB_IWR0                      0xFFC0111C
-#define SICB_IWR1                      0xFFC01120
-#define SICB_IAR0                      0xFFC01124
-#define SICB_IAR1                      0xFFC01128
-#define SICB_IAR2                      0xFFC0112C
-#define SICB_IAR3                      0xFFC01130
-#define SICB_IAR4                      0xFFC01134
-#define SICB_IAR5                      0xFFC01138
-#define SICB_IAR6                      0xFFC0113C
-#define SICB_IAR7                      0xFFC01140
-#define PPI0_CONTROL                   0xFFC01000
-#define PPI0_STATUS                    0xFFC01004
-#define PPI0_DELAY                     0xFFC0100C
-#define PPI0_COUNT                     0xFFC01008
-#define PPI0_FRAME                     0xFFC01010
-#define PPI1_CONTROL                   0xFFC01300
-#define PPI1_STATUS                    0xFFC01304
-#define PPI1_DELAY                     0xFFC0130C
-#define PPI1_COUNT                     0xFFC01308
-#define PPI1_FRAME                     0xFFC01310
-#define UART_THR                       0xFFC00400
-#define UART_RBR                       0xFFC00400
-#define UART0_RBR                      UART_RBR
-#define UART_DLL                       0xFFC00400
-#define UART_DLH                       0xFFC00404
-#define UART_IER                       0xFFC00404
-#define UART_IIR                       0xFFC00408
-#define UART_LCR                       0xFFC0040C
-#define UART_MCR                       0xFFC00410
-#define UART_LSR                       0xFFC00414
-#define UART_MSR                       0xFFC00418
-#define UART_SCR                       0xFFC0041C
-#define UART_GCTL                      0xFFC00424
-#define UART_GBL                       0xFFC00424
-#define EBIU_AMGCTL                    0xFFC00A00
-#define EBIU_AMBCTL0                   0xFFC00A04
-#define EBIU_AMBCTL1                   0xFFC00A08
-#define EBIU_SDGCTL                    0xFFC00A10
-#define EBIU_SDBCTL                    0xFFC00A14
-#define EBIU_SDRRC                     0xFFC00A18
-#define EBIU_SDSTAT                    0xFFC00A1C
-
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA03FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#define COREB_L1_CODE_START       0xFF600000
-
-#endif /* __BFIN_DEF_ADSP_BF561_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf561/anomaly.h b/arch/blackfin/include/asm/mach-bf561/anomaly.h
deleted file mode 100644
index b27173c..0000000
--- a/arch/blackfin/include/asm/mach-bf561/anomaly.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- *  - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
-#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
-# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
-#define ANOMALY_05000120 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* SIGNBITS Instruction Not Functional under Certain Conditions */
-#define ANOMALY_05000127 (1)
-/* IMDMA S1/D1 Channel May Stall */
-#define ANOMALY_05000149 (1)
-/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
-#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
-/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
-/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
-#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
-/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Disabling the PPI Resets the PPI Configuration Registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
-/* Internal Memory DMA Does Not Operate at Full Speed */
-#define ANOMALY_05000182 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
-/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
-/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
-#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
-/* IMDMA Corrupted Data after a Halt */
-#define ANOMALY_05000187 (1)
-/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
-#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
-/* False Protection Exceptions when Speculative Fetch Is Cancelled */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
-/* PPI Not Functional at Core Voltage < 1Volt */
-#define ANOMALY_05000190 (1)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
-/* Failing MMR Accesses when Preceding Memory Read Stalls */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
-/* Specific Sequence that Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
-/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
-#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
-/* TESTSET Operation Forces Stall on the Other Core */
-#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
-/* Exception Not Generated for MMR Accesses in Reserved Region */
-#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
-/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
-#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
-/* IMDMA May Corrupt Data under Certain Conditions */
-#define ANOMALY_05000267 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Data Cache Write Back to External Synchronous Memory May Be Lost */
-#define ANOMALY_05000274 (1)
-/* PPI Timing and Sampling Information Updates */
-#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
-/* False Hardware Error when ISR Context Is Not Restored */
-/* Temporarily walk around for bug 5423 till this issue is confirmed by
- * official anomaly document. It looks 05000281 still exists on bf561
- * v0.5.
- */
-#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (1)
-/* Reads Will Receive Incorrect Data under Certain Conditions */
-#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (1)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (1)
-/* PF2 Output Remains Asserted after SPI Master Boot */
-#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
-/* Erroneous GPIO Flag Pin Operations under Specific Sequences */
-#define ANOMALY_05000323 (1)
-/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
-#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
-/* 24-Bit SPI Boot Mode Is Not Functional */
-#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
-/* Slave SPI Boot Mode Is Not Functional */
-#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
-/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
-#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
-/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
-/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
-#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* Conflicting Column Address Widths Causes SDRAM Errors */
-#define ANOMALY_05000362 (1)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
-#define ANOMALY_05000412 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
-#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* SCKELOW Feature Is Not Functional */
-#define ANOMALY_05000458 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
-#define ANOMALY_05000471 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
-#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
-/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
-#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
-/* Stall in multi-unit DMA operations */
-#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* DMA engine may lose data due to incorrect handshaking */
-#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
-/* DMA stalls when all three controllers read data from the same source */
-#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
-/* Execution stall when executing in L2 and doing external accesses */
-#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
-/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
-#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> is not set on Reset */
-#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* DSPID register values incorrect */
-#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000119 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf561/def_local.h b/arch/blackfin/include/asm/mach-bf561/def_local.h
deleted file mode 100644
index 08e37e5..0000000
--- a/arch/blackfin/include/asm/mach-bf561/def_local.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#define SWRST SICA_SWRST
-#define SYSCR SICA_SYSCR
-#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
-#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
-
-#define WDOG_CNT WDOGA_CNT
-#define WDOG_CTL WDOGA_CTL
-#define bfin_write_WDOG_CNT(val) bfin_write_WDOGA_CNT(val)
-#define bfin_write_WDOG_CTL(val) bfin_write_WDOGA_CTL(val)
-#define bfin_write_WDOG_STAT(val) bfin_write_WDOGA_STAT(val)
-
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define BF561_FAMILY 1	/* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf561/gpio.h b/arch/blackfin/include/asm/mach-bf561/gpio.h
deleted file mode 100644
index 4f8aa5d..0000000
--- a/arch/blackfin/include/asm/mach-bf561/gpio.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0	0
-#define GPIO_PF1	1
-#define GPIO_PF2	2
-#define GPIO_PF3	3
-#define GPIO_PF4	4
-#define GPIO_PF5	5
-#define GPIO_PF6	6
-#define GPIO_PF7	7
-#define GPIO_PF8	8
-#define GPIO_PF9	9
-#define GPIO_PF10	10
-#define GPIO_PF11	11
-#define GPIO_PF12	12
-#define GPIO_PF13	13
-#define GPIO_PF14	14
-#define GPIO_PF15	15
-#define GPIO_PF16	16
-#define GPIO_PF17	17
-#define GPIO_PF18	18
-#define GPIO_PF19	19
-#define GPIO_PF20	20
-#define GPIO_PF21	21
-#define GPIO_PF22	22
-#define GPIO_PF23	23
-#define GPIO_PF24	24
-#define GPIO_PF25	25
-#define GPIO_PF26	26
-#define GPIO_PF27	27
-#define GPIO_PF28	28
-#define GPIO_PF29	29
-#define GPIO_PF30	30
-#define GPIO_PF31	31
-#define GPIO_PF32	32
-#define GPIO_PF33	33
-#define GPIO_PF34	34
-#define GPIO_PF35	35
-#define GPIO_PF36	36
-#define GPIO_PF37	37
-#define GPIO_PF38	38
-#define GPIO_PF39	39
-#define GPIO_PF40	40
-#define GPIO_PF41	41
-#define GPIO_PF42	42
-#define GPIO_PF43	43
-#define GPIO_PF44	44
-#define GPIO_PF45	45
-#define GPIO_PF46	46
-#define GPIO_PF47	47
-
-#define PORT_FIO0 GPIO_0
-#define PORT_FIO1 GPIO_16
-#define PORT_FIO2 GPIO_32
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf561/portmux.h b/arch/blackfin/include/asm/mach-bf561/portmux.h
deleted file mode 100644
index 2339ffd..0000000
--- a/arch/blackfin/include/asm/mach-bf561/portmux.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK	(P_DONTCARE)
-#define P_PPI0_FS1	(P_DONTCARE)
-#define P_PPI0_FS2	(P_DONTCARE)
-#define P_PPI0_FS3	(P_DONTCARE)
-#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PF47))
-#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PF46))
-#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF45))
-#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF44))
-#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF43))
-#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF42))
-#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF41))
-#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF40))
-#define P_PPI0_D0	(P_DONTCARE)
-#define P_PPI0_D1	(P_DONTCARE)
-#define P_PPI0_D2	(P_DONTCARE)
-#define P_PPI0_D3	(P_DONTCARE)
-#define P_PPI0_D4	(P_DONTCARE)
-#define P_PPI0_D5	(P_DONTCARE)
-#define P_PPI0_D6	(P_DONTCARE)
-#define P_PPI0_D7	(P_DONTCARE)
-#define P_PPI1_CLK	(P_DONTCARE)
-#define P_PPI1_FS1	(P_DONTCARE)
-#define P_PPI1_FS2	(P_DONTCARE)
-#define P_PPI1_FS3	(P_DONTCARE)
-#define P_PPI1_D15	(P_DEFINED | P_IDENT(GPIO_PF39))
-#define P_PPI1_D14	(P_DEFINED | P_IDENT(GPIO_PF38))
-#define P_PPI1_D13	(P_DEFINED | P_IDENT(GPIO_PF37))
-#define P_PPI1_D12	(P_DEFINED | P_IDENT(GPIO_PF36))
-#define P_PPI1_D11	(P_DEFINED | P_IDENT(GPIO_PF35))
-#define P_PPI1_D10	(P_DEFINED | P_IDENT(GPIO_PF34))
-#define P_PPI1_D9	(P_DEFINED | P_IDENT(GPIO_PF33))
-#define P_PPI1_D8	(P_DEFINED | P_IDENT(GPIO_PF32))
-#define P_PPI1_D0	(P_DONTCARE)
-#define P_PPI1_D1	(P_DONTCARE)
-#define P_PPI1_D2	(P_DONTCARE)
-#define P_PPI1_D3	(P_DONTCARE)
-#define P_PPI1_D4	(P_DONTCARE)
-#define P_PPI1_D5	(P_DONTCARE)
-#define P_PPI1_D6	(P_DONTCARE)
-#define P_PPI1_D7	(P_DONTCARE)
-#define P_SPORT1_TSCLK	(P_DEFINED | P_IDENT(GPIO_PF31))
-#define P_SPORT1_RSCLK	(P_DEFINED | P_IDENT(GPIO_PF30))
-#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(GPIO_PF29))
-#define P_SPORT0_RSCLK	(P_DEFINED | P_IDENT(GPIO_PF28))
-#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PF27))
-#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PF26))
-#define P_SPORT1_DRSEC	(P_DEFINED | P_IDENT(GPIO_PF25))
-#define P_SPORT1_RFS	(P_DEFINED | P_IDENT(GPIO_PF24))
-#define P_SPORT1_DTPRI	(P_DEFINED | P_IDENT(GPIO_PF23))
-#define P_SPORT1_DTSEC	(P_DEFINED | P_IDENT(GPIO_PF22))
-#define P_SPORT1_TFS	(P_DEFINED | P_IDENT(GPIO_PF21))
-#define P_SPORT1_DRPRI	(P_DONTCARE)
-#define P_SPORT0_DRSEC	(P_DEFINED | P_IDENT(GPIO_PF20))
-#define P_SPORT0_RFS	(P_DEFINED | P_IDENT(GPIO_PF19))
-#define P_SPORT0_DTPRI	(P_DEFINED | P_IDENT(GPIO_PF18))
-#define P_SPORT0_DTSEC	(P_DEFINED | P_IDENT(GPIO_PF17))
-#define P_SPORT0_TFS	(P_DEFINED | P_IDENT(GPIO_PF16))
-#define P_SPORT0_DRPRI	(P_DONTCARE)
-#define P_TMRCLK	(P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_SPI0_SSEL7	(P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6	(P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5	(P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4	(P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_TMR11		(P_DONTCARE)
-#define P_TMR10		(P_DONTCARE)
-#define P_TMR9		(P_DONTCARE)
-#define P_TMR8		(P_DONTCARE)
-#define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_TMR6		(P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_TMR5		(P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_TMR4		(P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_TMR3		(P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_TMR2		(P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_TMR1		(P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_TMR0		(P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_SPI0_MOSI	(P_DONTCARE)
-#define P_SPI0_MISO	(P_DONTCARE)
-#define P_SPI0_SCK	(P_DONTCARE)
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf561/ports.h b/arch/blackfin/include/asm/mach-bf561/ports.h
deleted file mode 100644
index 194d4a3..0000000
--- a/arch/blackfin/include/asm/mach-bf561/ports.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-#include "../mach-common/bits/ports-f.h"
-
-/* The non-standard PF16+ */
-#define PF16		(1 << 0)
-#define PF17		(1 << 1)
-#define PF18		(1 << 2)
-#define PF19		(1 << 3)
-#define PF20		(1 << 4)
-#define PF21		(1 << 5)
-#define PF22		(1 << 6)
-#define PF23		(1 << 7)
-#define PF24		(1 << 8)
-#define PF25		(1 << 9)
-#define PF26		(1 << 10)
-#define PF27		(1 << 11)
-#define PF28		(1 << 12)
-#define PF29		(1 << 13)
-#define PF30		(1 << 14)
-#define PF31		(1 << 15)
-#define PF32		(1 << 0)
-#define PF33		(1 << 1)
-#define PF34		(1 << 2)
-#define PF35		(1 << 3)
-#define PF36		(1 << 4)
-#define PF37		(1 << 5)
-#define PF38		(1 << 6)
-#define PF39		(1 << 7)
-#define PF40		(1 << 8)
-#define PF41		(1 << 9)
-#define PF42		(1 << 10)
-#define PF43		(1 << 11)
-#define PF44		(1 << 12)
-#define PF45		(1 << 13)
-#define PF46		(1 << 14)
-#define PF47		(1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h b/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h
deleted file mode 100644
index c590031..0000000
--- a/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF609_proc__
-#define __BFIN_CDEF_ADSP_BF609_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_CGU_STAT() bfin_read32(CGU_STAT)
-#define bfin_read_CGU_CLKOUTSEL() bfin_read32(CGU_CLKOUTSEL)
-#define bfin_read_CGU_CTL() bfin_read32(CGU_CTL)
-#define bfin_write_CGU_CTL(val) bfin_write32(CGU_CTL, val)
-#define bfin_read_CGU_DIV() bfin_read32(CGU_DIV)
-#define bfin_write_CGU_DIV(val) bfin_write32(CGU_DIV, val)
-
-#define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL)
-#define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val)
-
-#define bfin_read_CHIPID()		bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)		bfin_write32(CHIPID, val)
-
-#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
-#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
-#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
-#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
-#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
-#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
-#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
-#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
-#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
-#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
-#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
-#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
-#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
-#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
-#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
-#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
-#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
-#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
-
-#define bfin_read_SEC_CCTL()		bfin_read32(SEC0_CCTL0)
-#define bfin_write_SEC_CCTL(val)	bfin_write32(SEC0_CCTL0, val)
-#define bfin_read_SEC_GCTL()		bfin_read32(SEC0_GCTL)
-#define bfin_write_SEC_GCTL(val)	bfin_write32(SEC0_GCTL, val)
-
-#define bfin_read_SEC_FCTL()		bfin_read32(SEC0_FCTL)
-#define bfin_write_SEC_FCTL(val)	bfin_write32(SEC0_FCTL, val)
-#define bfin_read_SEC_SCTL(sid)		bfin_read32((SEC0_SCTL0 + (sid) * 8))
-#define bfin_write_SEC_SCTL(sid, val)	bfin_write32((SEC0_SCTL0 \
-	+ (sid) * 8), val)
-
-#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
-#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
-#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
-#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
-#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
-#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
-#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
-#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
-#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
-#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
-#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
-#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
-#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
-#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
-#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
-#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
-#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
-#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
-#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
-#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
-#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
-#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
-#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
-#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
-#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
-#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
-#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
-
-#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLL_OSC)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val)
-#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val)
-#define bfin_read_USB_DMA_INTERRUPT()  bfin_read8(USB_DMA_IRQ)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write8(USB_DMA_IRQ, val)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val)
-#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL)
-
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_DSCPTR_NXT)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_DSCPTR_NXT, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_ADDRSTART)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_ADDRSTART, val)
-#define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CFG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CFG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_XCNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_XCNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_XMOD)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_XMOD, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_YCNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_YCNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_YMOD)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_YMOD, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_DSCPTR_CUR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_DSCPTR_CUR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_ADDR_CUR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_ADDR_CUR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_STAT)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_STAT, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_XCNT_CUR)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_XCNT_CUR, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_YCNT_CUR)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_YCNT_CUR, val)
-
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_CTL() bfin_read32(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write32(WDOG_CTL, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_SPI_BAUD() bfin_read32(SPI0_CLK)
-#define bfin_write_SPI_BAUD(val) bfin_write32(SPI0_CLK, val)
-
-#define bfin_read_PORTD_FER() bfin_read32(PORTD_FER)
-#define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val)
-#define bfin_write_PORTD_FER_CLR(val) bfin_write32(PORTD_FER_CLR, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTG_FER() bfin_read32(PORTG_FER)
-#define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val)
-#define bfin_write_PORTG_FER_CLR(val) bfin_write32(PORTG_FER_CLR, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-
-#define bfin_read_RSI_CLK_CONTROL()    bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT()       bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val)   bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND()        bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val)    bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD()       bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val)   bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0()      bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val)  bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1()      bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val)  bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2()      bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val)  bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3()      bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val)  bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER()     bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH()      bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val)  bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CONTROL()   bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT()       bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val)   bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS()         bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val)     bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUSCL()       bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUSCL(val)   bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0()          bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val)      bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1()          bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val)      bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT()       bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val)   bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CONTROL()  bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_BLKSZ()          bfin_read16(RSI_BLKSZ)
-#define bfin_write_RSI_BLKSZ(val)      bfin_write16(RSI_BLKSZ, val)
-#define bfin_read_RSI_FIFO()           bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val)       bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_ESTAT()          bfin_read32(RSI_ESTAT)
-#define bfin_write_RSI_ESTAT(val)      bfin_write32(RSI_ESTAT, val)
-#define bfin_read_RSI_EMASK()          bfin_read32(RSI_EMASK)
-#define bfin_write_RSI_EMASK(val)      bfin_write32(RSI_EMASK, val)
-#define bfin_read_RSI_CONFIG()         bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CONFIG(val)     bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN()     bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0()           bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val)       bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1()           bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val)       bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2()           bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val)       bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3()           bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val)       bfin_write16(RSI_PID3, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF609_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h
deleted file mode 100644
index fd0d86d..0000000
--- a/arch/blackfin/include/asm/mach-bf609/BF609_def.h
+++ /dev/null
@@ -1,254 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF609_proc__
-#define __BFIN_DEF_ADSP_BF609_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define RSI_CLK_CONTROL   0xFFC00604 /* RSI0 Clock Control Register */
-#define RSI_ARGUMENT      0xFFC00608 /* RSI0 Argument Register */
-#define RSI_COMMAND       0xFFC0060C /* RSI0 Command Register */
-#define RSI_RESP_CMD      0xFFC00610 /* RSI0 Response Command Register */
-#define RSI_RESPONSE0     0xFFC00614 /* RSI0 Response 0 Register */
-#define RSI_RESPONSE1     0xFFC00618 /* RSI0 Response 1 Register */
-#define RSI_RESPONSE2     0xFFC0061C /* RSI0 Response 2 Register */
-#define RSI_RESPONSE3     0xFFC00620 /* RSI0 Response 3 Register */
-#define RSI_DATA_TIMER    0xFFC00624 /* RSI0 Data Timer Register */
-#define RSI_DATA_LGTH     0xFFC00628 /* RSI0 Data Length Register */
-#define RSI_DATA_CONTROL  0xFFC0062C /* RSI0 Data Control Register */
-#define RSI_DATA_CNT      0xFFC00630 /* RSI0 Data Count Register */
-#define RSI_STATUS        0xFFC00634 /* RSI0 Status Register */
-#define RSI_STATUSCL      0xFFC00638 /* RSI0 Status Clear Register */
-#define RSI_IMSK0         0xFFC0063C /* RSI0 Interrupt 0 Mask Register */
-#define RSI_IMSK1         0xFFC00640 /* RSI0 Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT      0xFFC00648 /* RSI0 FIFO Counter Register */
-#define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 contains bit to dis CCS gen */
-#define RSI_BOOT_TCNTR    0xFFC00650 /* RSI0 Boot Timing Counter Register */
-#define RSI_BACK_TOUT     0xFFC00654 /* RSI0 Boot Ack Timeout Register */
-#define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */
-#define RSI_BLKSZ         0xFFC0065C /* RSI0 Block Size Register */
-#define RSI_FIFO          0xFFC00680 /* RSI0 Data FIFO Register */
-#define RSI_ESTAT         0xFFC006C0 /* RSI0 Exception Status Register */
-#define RSI_EMASK         0xFFC006C4 /* RSI0 Exception Mask Register */
-#define RSI_CONFIG        0xFFC006C8 /* RSI0 Configuration Register */
-#define RSI_RD_WAIT_EN    0xFFC006CC /* RSI0 Read Wait Enable Register */
-#define RSI_PID0          0xFFC006D0 /* RSI0 Peripheral Id Register */
-#define RSI_PID1          0xFFC006D4 /* RSI0 Peripheral Id Register */
-#define RSI_PID2          0xFFC006D8 /* RSI0 Peripheral Id Register */
-#define RSI_PID3          0xFFC006DC /* RSI0 Peripheral Id Register */
-
-#define TWI0_CLKDIV       0xFFC01E00 /* TWI0 SCL Clock Divider */
-#define TWI1_CLKDIV       0xFFC01F00 /* TWI1 SCL Clock Divider */
-
-#define UART0_REVID       0xFFC02000 /* UART0 Revision ID Register */
-#define UART0_CTL         0xFFC02004 /* UART0 Control Register */
-#define UART0_STAT        0xFFC02008 /* UART0 Status Register */
-#define UART0_SCR         0xFFC0200C /* UART0 Scratch Register */
-#define UART0_CLK         0xFFC02010 /* UART0 Clock Rate Register */
-#define UART0_IMSK        0xFFC02014 /* UART0 Interrupt Mask Register */
-#define UART0_IMSK_SET    0xFFC02018 /* UART0 Interrupt Mask Set Register */
-#define UART0_IMSK_CLR    0xFFC0201C /* UART0 Interrupt Mask Clear Register */
-#define UART0_RBR         0xFFC02020 /* UART0 Receive Buffer Register */
-#define UART0_THR         0xFFC02024 /* UART0 Transmit Hold Register */
-#define UART0_TAIP        0xFFC02028 /* UART0 TX Address/Insert Pulse Reg */
-#define UART0_TSR         0xFFC0202C /* UART0 Transmit Shift Register */
-#define UART0_RSR         0xFFC02030 /* UART0 Receive Shift Register */
-#define UART0_TXCNT       0xFFC02034 /* UART0 Transmit Counter Register */
-#define UART0_RXCNT       0xFFC02038 /* UART0 Receive Counter Register */
-#define UART1_REVID       0xFFC02400 /* UART1 Revision ID Register */
-#define UART1_CTL         0xFFC02404 /* UART1 Control Register */
-#define UART1_STAT        0xFFC02408 /* UART1 Status Register */
-#define UART1_SCR         0xFFC0240C /* UART1 Scratch Register */
-#define UART1_CLK         0xFFC02410 /* UART1 Clock Rate Register */
-#define UART1_IMSK        0xFFC02414 /* UART1 Interrupt Mask Register */
-#define UART1_IMSK_SET    0xFFC02418 /* UART1 Interrupt Mask Set Register */
-#define UART1_IMSK_CLR    0xFFC0241C /* UART1 Interrupt Mask Clear Register */
-#define UART1_RBR         0xFFC02420 /* UART1 Receive Buffer Register */
-#define UART1_THR         0xFFC02424 /* UART1 Transmit Hold Register */
-#define UART1_TAIP        0xFFC02428 /* UART1 TX Address/Insert Pulse Reg */
-#define UART1_TSR         0xFFC0242C /* UART1 Transmit Shift Register */
-#define UART1_RSR         0xFFC02430 /* UART1 Receive Shift Register */
-#define UART1_TXCNT       0xFFC02434 /* UART1 Transmit Counter Register */
-#define UART1_RXCNT       0xFFC02438 /* UART1 Receive Counter Register */
-
-#define PORTA_FER         0xFFC03000 /* PORTA Port x Function Enable */
-#define PORTA_FER_SET     0xFFC03004 /* PORTA Port x Function Enable Set */
-#define PORTA_FER_CLR     0xFFC03008 /* PORTA Port x Function Enable Clear */
-#define PORTA_MUX         0xFFC03030 /* PORTA Port x Multiplexer Control */
-#define PORTB_FER         0xFFC03080 /* PORTB Port x Function Enable */
-#define PORTB_FER_SET     0xFFC03084 /* PORTB Port x Function Enable Set */
-#define PORTB_FER_CLR     0xFFC03088 /* PORTB Port x Function Enable Clear */
-#define PORTB_MUX         0xFFC030B0 /* PORTB Port x Multiplexer Control */
-#define PORTC_FER         0xFFC03100 /* PORTC Port x Function Enable */
-#define PORTC_FER_SET     0xFFC03104 /* PORTC Port x Function Enable Set */
-#define PORTC_FER_CLR     0xFFC03108 /* PORTC Port x Function Enable Clear */
-#define PORTC_MUX         0xFFC03130 /* PORTC Port x Multiplexer Control */
-#define PORTD_FER         0xFFC03180 /* PORTD Port x Function Enable */
-#define PORTD_FER_SET     0xFFC03184 /* PORTD Port x Function Enable Set */
-#define PORTD_FER_CLR     0xFFC03188 /* PORTD Port x Function Enable Clear */
-#define PORTD_MUX         0xFFC031B0 /* PORTD Port x Multiplexer Control */
-#define PORTE_FER         0xFFC03200 /* PORTE Port x Function Enable */
-#define PORTE_FER_SET     0xFFC03204 /* PORTE Port x Function Enable Set */
-#define PORTE_FER_CLR     0xFFC03208 /* PORTE Port x Function Enable Clear */
-#define PORTE_MUX         0xFFC03230 /* PORTE Port x Multiplexer Control */
-#define PORTF_FER         0xFFC03280 /* PORTF Port x Function Enable */
-#define PORTF_FER_SET     0xFFC03284 /* PORTF Port x Function Enable Set */
-#define PORTF_FER_CLR     0xFFC03288 /* PORTF Port x Function Enable Clear */
-#define PORTF_MUX         0xFFC032B0 /* PORTF Port x Multiplexer Control */
-#define PORTG_FER         0xFFC03300 /* PORTG Port x Function Enable */
-#define PORTG_FER_SET     0xFFC03304 /* PORTG Port x Function Enable Set */
-#define PORTG_FER_CLR     0xFFC03308 /* PORTG Port x Function Enable Clear */
-#define PORTG_MUX         0xFFC03330 /* PORTG Port x Multiplexer Control */
-
-#define SMC_GCTL          0xFFC16004 /* SMC Control Register */
-#define SMC_GSTAT         0xFFC16008 /* SMC Status Register */
-#define SMC_B0CTL         0xFFC1600C /* SMC Bank0 Control Register */
-#define SMC_B0TIM         0xFFC16010 /* SMC Bank0 Timing Register */
-#define SMC_B0ETIM        0xFFC16014 /* SMC Bank0 Extended Timing Register */
-#define SMC_B1CTL         0xFFC1601C /* SMC BANK1 Control Register */
-#define SMC_B1TIM         0xFFC16020 /* SMC BANK1 Timing Register */
-#define SMC_B1ETIM        0xFFC16024 /* SMC BANK1 Extended Timing Register */
-#define SMC_B2CTL         0xFFC1602C /* SMC BANK2 Control Register */
-#define SMC_B2TIM         0xFFC16030 /* SMC BANK2 Timing Register */
-#define SMC_B2ETIM        0xFFC16034 /* SMC BANK2 Extended Timing Register */
-#define SMC_B3CTL         0xFFC1603C /* SMC BANK3 Control Register */
-#define SMC_B3TIM         0xFFC16040 /* SMC BANK3 Timing Register */
-#define SMC_B3ETIM        0xFFC16044 /* SMC BANK3 Extended Timing Register */
-
-#define WDOG_CTL          0xFFC17000 /* WDOG0 Control Register */
-#define WDOG_CNT          0xFFC17004 /* WDOG0 Count Register */
-#define WDOG_STAT         0xFFC17008 /* WDOG0 Watchdog Timer Status Register */
-#define WDOG1_CTL         0xFFC17800 /* WDOG1 Control Register */
-#define WDOG1_CNT         0xFFC17804 /* WDOG1 Count Register */
-#define WDOG1_STAT        0xFFC17808 /* WDOG1 Watchdog Timer Status Register */
-
-#define SDU0_MSG_SET      0xFFC1F084 /* SDU0 Message Set Register */
-
-#define EMAC0_MACCFG      0xFFC20000 /* EMAC0 MAC Configuration Register */
-#define EMAC1_MACCFG      0xFFC22000 /* EMAC1 MAC Configuration Register */
-
-#define SPI0_REGBASE      0xFFC40400 /* SPI0 Base Address */
-#define SPI1_REGBASE      0xFFC40500 /* SPI1 Base Address */
-
-#define DMA10_DSCPTR_NXT  0xFFC05000 /* DMA10 Pointer to Next Initial Desc */
-#define DMA10_ADDRSTART   0xFFC05004 /* DMA10 Start Address of Current Buf */
-#define DMA10_CFG         0xFFC05008 /* DMA10 Configuration Register */
-#define DMA10_XCNT        0xFFC0500C /* DMA10 Inner Loop Count Start Value */
-#define DMA10_XMOD        0xFFC05010 /* DMA10 Inner Loop Address Increment */
-#define DMA10_YCNT        0xFFC05014 /* DMA10 Outer Loop Count Start Value */
-#define DMA10_YMOD        0xFFC05018 /* DMA10 Outer Loop Address Increment */
-#define DMA10_DSCPTR_CUR  0xFFC05024 /* DMA10 Current Descriptor Pointer */
-#define DMA10_DSCPTR_PRV  0xFFC05028 /* DMA10 Previous Initial Desc Pointer */
-#define DMA10_ADDR_CUR    0xFFC0502C /* DMA10 Current Address */
-#define DMA10_STAT        0xFFC05030 /* DMA10 Status Register */
-#define DMA10_XCNT_CUR    0xFFC05034 /* DMA10 Curr Count(1D) or intra-row(2D)*/
-#define DMA10_YCNT_CUR    0xFFC05038 /* DMA10 Curr Row Count (2D only) */
-#define DMA10_BWLCNT      0xFFC05040 /* DMA10 Bandwidth Limit Count */
-#define DMA10_BWLCNT_CUR  0xFFC05044 /* DMA10 Bandwidth Limit Count Current */
-#define DMA10_BWMCNT      0xFFC05048 /* DMA10 Bandwidth Monitor Count */
-#define DMA10_BWMCNT_CUR  0xFFC0504C /* DMA10 Bandwidth Monitor Count Current*/
-
-#define MDMA_S0_NEXT_DESC_PTR DMA21_DSCPTR_NXT
-#define DMA21_DSCPTR_NXT  0xFFC09000 /* DMA21 Pointer to Next Initial Desc */
-#define MDMA_D0_NEXT_DESC_PTR DMA22_DSCPTR_NXT
-#define DMA22_DSCPTR_NXT  0xFFC09080 /* DMA22 Pointer to Next Initial Desc */
-
-#define DMC0_ID           0xFFC80000 /* DMC0 Identification Register */
-#define DMC0_CTL          0xFFC80004 /* DMC0 Control Register */
-#define DMC0_STAT         0xFFC80008 /* DMC0 Status Register */
-#define DMC0_EFFCTL       0xFFC8000C /* DMC0 Efficiency Controller */
-#define DMC0_PRIO         0xFFC80010 /* DMC0 Priority ID Register */
-#define DMC0_PRIOMSK      0xFFC80014 /* DMC0 Priority ID Mask */
-#define DMC0_CFG          0xFFC80040 /* DMC0 SDRAM Configuration */
-#define DMC0_TR0          0xFFC80044 /* DMC0 Timing Register 0 */
-#define DMC0_TR1          0xFFC80048 /* DMC0 Timing Register 1 */
-#define DMC0_TR2          0xFFC8004C /* DMC0 Timing Register 2 */
-#define DMC0_MSK          0xFFC8005C /* DMC0 Mode Register Mask */
-#define DMC0_MR           0xFFC80060 /* DMC0 Mode Shadow register */
-#define DMC0_EMR1         0xFFC80064 /* DMC0 EMR1 Shadow Register */
-#define DMC0_EMR2         0xFFC80068 /* DMC0 EMR2 Shadow Register */
-#define DMC0_EMR3         0xFFC8006C /* DMC0 EMR3 Shadow Register */
-#define DMC0_DLLCTL       0xFFC80080 /* DMC0 DLL Control Register */
-#define DMC0_PADCTL       0xFFC800C0 /* DMC0 PAD Control Register 0 */
-
-#define SEC0_CCTL0        0xFFCA4400 /* SEC0 Core Control Register n */
-#define SEC0_CCTL1        0xFFCA4440 /* SEC0 Core Control Register n */
-#define SEC0_FCTL         0xFFCA4010 /* SEC0 Fault Control Register */
-#define SEC0_GCTL         0xFFCA4000 /* SEC0 Global Control Register */
-#define SEC0_SCTL0        0xFFCA4800 /* SEC0 IRQ Source Control Register n */
-
-#define RCU0_CTL          0xFFCA6000 /* RCU0 Control Register */
-#define RCU0_STAT         0xFFCA6004 /* RCU0 Status Register */
-#define RCU0_CRCTL        0xFFCA6008 /* RCU0 Core Reset Control Register */
-#define RCU0_CRSTAT       0xFFCA600C /* RCU0 Core Reset Status Register */
-#define RCU0_SIDIS        0xFFCA6010 /* RCU0 Sys Interface Disable Register */
-#define RCU0_SISTAT       0xFFCA6014 /* RCU0 Sys Interface Status Register */
-#define RCU0_SVECT_LCK    0xFFCA6018 /* RCU0 SVECT Lock Register */
-#define RCU0_BCODE        0xFFCA601C /* RCU0 Boot Code Register */
-#define RCU0_SVECT0       0xFFCA6020 /* RCU0 Software Vector Register n */
-#define RCU0_SVECT1       0xFFCA6024 /* RCU0 Software Vector Register n */
-
-#define CGU_CTL           0xFFCA8000 /* CGU0 Control Register */
-#define CGU_STAT          0xFFCA8004 /* CGU0 Status Register */
-#define CGU_DIV           0xFFCA8008 /* CGU0 Divisor Register */
-#define CGU_CLKOUTSEL     0xFFCA800C /* CGU0 CLKOUT Select Register */
-
-#define DPM0_CTL          0xFFCA9000 /* DPM0 Control Register */
-#define DPM0_STAT         0xFFCA9004 /* DPM0 Status Register */
-#define DPM0_CCBF_DIS     0xFFCA9008 /* DPM0 Core Clock Buffer Disable */
-#define DPM0_CCBF_EN      0xFFCA900C /* DPM0 Core Clock Buffer Enable */
-#define DPM0_CCBF_STAT    0xFFCA9010 /* DPM0 Core Clock Buffer Status */
-#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Stat Sticky */
-#define DPM0_SCBF_DIS     0xFFCA9018 /* DPM0 System Clock Buffer Disable */
-#define DPM0_WAKE_EN      0xFFCA901C /* DPM0 Wakeup Enable Register */
-#define DPM0_WAKE_POL     0xFFCA9020 /* DPM0 Wakeup Polarity Register */
-#define DPM0_WAKE_STAT    0xFFCA9024 /* DPM0 Wakeup Status Register */
-#define DPM0_HIB_DIS      0xFFCA9028 /* DPM0 Hibernate Disable Register */
-#define DPM0_PGCNTR       0xFFCA902C /* DPM0 Power Good Counter Register */
-#define DPM0_RESTORE0     0xFFCA9030 /* DPM0 Restore Register */
-#define DPM0_RESTORE1     0xFFCA9034 /* DPM0 Restore Register */
-#define DPM0_RESTORE2     0xFFCA9038 /* DPM0 Restore Register */
-#define DPM0_RESTORE3     0xFFCA903C /* DPM0 Restore Register */
-#define DPM0_RESTORE4     0xFFCA9040 /* DPM0 Restore Register */
-#define DPM0_RESTORE5     0xFFCA9044 /* DPM0 Restore Register */
-#define DPM0_RESTORE6     0xFFCA9048 /* DPM0 Restore Register */
-#define DPM0_RESTORE7     0xFFCA904C /* DPM0 Restore Register */
-#define DPM0_RESTORE8     0xFFCA9050 /* DPM0 Restore Register */
-#define DPM0_RESTORE9     0xFFCA9054 /* DPM0 Restore Register */
-#define DPM0_RESTORE10    0xFFCA9058 /* DPM0 Restore Register */
-#define DPM0_RESTORE11    0xFFCA905C /* DPM0 Restore Register */
-#define DPM0_RESTORE12    0xFFCA9060 /* DPM0 Restore Register */
-#define DPM0_RESTORE13    0xFFCA9064 /* DPM0 Restore Register */
-#define DPM0_RESTORE14    0xFFCA9068 /* DPM0 Restore Register */
-#define DPM0_RESTORE15    0xFFCA906C /* DPM0 Restore Register */
-
-#define USB_FADDR         0xFFCC1000 /* USB Device Address in Peripheral Mode*/
-#define USB_DMA_IRQ       0xFFCC1200 /* USB Interrupt Register */
-#define USB_VBUS_CTL      0xFFCC1380 /* USB VBus Control */
-#define USB_PHY_CTL       0xFFCC1394 /* USB PHY Control */
-#define USB_PLL_OSC       0xFFCC1398 /* USB PLL and Oscillator Control */
-
-
-#define                           CHIPID  0xffc00014
-/* CHIPID Masks */
-#define                   CHIPID_VERSION  0xF0000000
-#define                    CHIPID_FAMILY  0x0FFFF000
-#define               CHIPID_MANUFACTURE  0x00000FFE
-
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000->0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE 0x8000
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000->0xFF903FFF Data Bank B SRAM */
-#define L1_DATA_B_SRAM_SIZE 0x4000
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000->0xFFA07FFF Inst Bank A SRAM */
-#define L1_INST_SRAM_SIZE 0x8000
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#define COREB_L1_CODE_START       0xFF600000
-
-#endif /* __BFIN_DEF_ADSP_BF609_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf609/anomaly.h b/arch/blackfin/include/asm/mach-bf609/anomaly.h
deleted file mode 100644
index 0a70f08..0000000
--- a/arch/blackfin/include/asm/mach-bf609/anomaly.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright 2004-2012 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- *  - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF609 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
-#define ANOMALY_16000003 (1)
-/* The EPPI Data Enable (DEN) Signal is Not Functional */
-#define ANOMALY_16000004 (1)
-/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
-#define ANOMALY_16000005 (1)
-/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
-#define ANOMALY_16000006 (1)
-/* DDR2 Memory Reads May Fail Intermittently */
-#define ANOMALY_16000007 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_16000008 (1)
-/* TestSET Instruction Cannot Be Interrupted */
-#define ANOMALY_16000009 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_16000010 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_16000011 (1)
-/* Speculative Fetches of Indirect-Pointer Inst Can Cause False Hw Errors */
-#define ANOMALY_16000012 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_16000013 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_16000014 (1)
-/* Multi-Issue Inst with dsp32shiftimm in slot1 and P in slot2 Not Supported */
-#define ANOMALY_16000015 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_16000017 (1)
-/* RSI Boot Cleanup Routine Does Not Clear Registers */
-#define ANOMALY_16000018 (1)
-/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
-#define ANOMALY_16000019 (1)
-/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
-#define ANOMALY_16000020 (1)
-/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hb/Wk Sequence */
-#define ANOMALY_16000021 (1)
-/* Boot Code Fails to Enable Parity Fault Detection */
-#define ANOMALY_16000022 (1)
-/* USB DMA interrupt status do not show the DMA channel intr in the DMA ISR */
-#define ANOMALY_16000027 (1)
-/* Interrupted Core Reads of MMRs May Cause Data Loss */
-#define ANOMALY_16000030 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000481 (1)
-
-/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
-#define ANOMALY_05000491 ANOMALY_16000008
-#define ANOMALY_05000477 ANOMALY_16000009
-#define ANOMALY_05000443 ANOMALY_16000010
-#define ANOMALY_05000461 ANOMALY_16000011
-#define ANOMALY_05000426 ANOMALY_16000012
-#define ANOMALY_05000310 ANOMALY_16000013
-#define ANOMALY_05000245 ANOMALY_16000014
-#define ANOMALY_05000074 ANOMALY_16000015
-#define ANOMALY_05000416 ANOMALY_16000017
-
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf609/def_local.h b/arch/blackfin/include/asm/mach-bf609/def_local.h
deleted file mode 100644
index d4250e6..0000000
--- a/arch/blackfin/include/asm/mach-bf609/def_local.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define CONFIG_BF60x 1	/* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf609/gpio.h b/arch/blackfin/include/asm/mach-bf609/gpio.h
deleted file mode 100644
index e297bcc..0000000
--- a/arch/blackfin/include/asm/mach-bf609/gpio.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 112
-
-#define GPIO_PA0	0
-#define GPIO_PA1	1
-#define GPIO_PA2	2
-#define GPIO_PA3	3
-#define GPIO_PA4	4
-#define GPIO_PA5	5
-#define GPIO_PA6	6
-#define GPIO_PA7	7
-#define GPIO_PA8	8
-#define GPIO_PA9	9
-#define GPIO_PA10	10
-#define GPIO_PA11	11
-#define GPIO_PA12	12
-#define GPIO_PA13	13
-#define GPIO_PA14	14
-#define GPIO_PA15	15
-#define GPIO_PB0	16
-#define GPIO_PB1	17
-#define GPIO_PB2	18
-#define GPIO_PB3	19
-#define GPIO_PB4	20
-#define GPIO_PB5	21
-#define GPIO_PB6	22
-#define GPIO_PB7	23
-#define GPIO_PB8	24
-#define GPIO_PB9	25
-#define GPIO_PB10	26
-#define GPIO_PB11	27
-#define GPIO_PB12	28
-#define GPIO_PB13	29
-#define GPIO_PB14	30
-#define GPIO_PB15	31
-#define GPIO_PC0	32
-#define GPIO_PC1	33
-#define GPIO_PC2	34
-#define GPIO_PC3	35
-#define GPIO_PC4	36
-#define GPIO_PC5	37
-#define GPIO_PC6	38
-#define GPIO_PC7	39
-#define GPIO_PC8	40
-#define GPIO_PC9	41
-#define GPIO_PC10	42
-#define GPIO_PC11	43
-#define GPIO_PC12	44
-#define GPIO_PC13	45
-#define GPIO_PC14	46
-#define GPIO_PC15	47
-#define GPIO_PD0	48
-#define GPIO_PD1	49
-#define GPIO_PD2	50
-#define GPIO_PD3	51
-#define GPIO_PD4	52
-#define GPIO_PD5	53
-#define GPIO_PD6	54
-#define GPIO_PD7	55
-#define GPIO_PD8	56
-#define GPIO_PD9	57
-#define GPIO_PD10	58
-#define GPIO_PD11	59
-#define GPIO_PD12	60
-#define GPIO_PD13	61
-#define GPIO_PD14	62
-#define GPIO_PD15	63
-#define GPIO_PE0	64
-#define GPIO_PE1	65
-#define GPIO_PE2	66
-#define GPIO_PE3	67
-#define GPIO_PE4	68
-#define GPIO_PE5	69
-#define GPIO_PE6	70
-#define GPIO_PE7	71
-#define GPIO_PE8	72
-#define GPIO_PE9	73
-#define GPIO_PE10	74
-#define GPIO_PE11	75
-#define GPIO_PE12	76
-#define GPIO_PE13	77
-#define GPIO_PE14	78
-#define GPIO_PE15	79
-#define GPIO_PF0	80
-#define GPIO_PF1	81
-#define GPIO_PF2	82
-#define GPIO_PF3	83
-#define GPIO_PF4	84
-#define GPIO_PF5	85
-#define GPIO_PF6	86
-#define GPIO_PF7	87
-#define GPIO_PF8	88
-#define GPIO_PF9	89
-#define GPIO_PF10	90
-#define GPIO_PF11	91
-#define GPIO_PF12	92
-#define GPIO_PF13	93
-#define GPIO_PF14	94
-#define GPIO_PF15	95
-#define GPIO_PG0	96
-#define GPIO_PG1	97
-#define GPIO_PG2	98
-#define GPIO_PG3	99
-#define GPIO_PG4	100
-#define GPIO_PG5	101
-#define GPIO_PG6	102
-#define GPIO_PG7	103
-#define GPIO_PG8	104
-#define GPIO_PG9	105
-#define GPIO_PG10	106
-#define GPIO_PG11	107
-#define GPIO_PG12	108
-#define GPIO_PG13	109
-#define GPIO_PG14	110
-#define GPIO_PG15	111
-
-#ifndef __ASSEMBLY__
-
-struct gpio_port_t {
-	unsigned long port_fer;
-	unsigned long port_fer_set;
-	unsigned long port_fer_clear;
-	unsigned long data;
-	unsigned long data_set;
-	unsigned long data_clear;
-	unsigned long dir;
-	unsigned long dir_set;
-	unsigned long dir_clear;
-	unsigned long inen;
-	unsigned long inen_set;
-	unsigned long inen_clear;
-	unsigned long port_mux;
-	unsigned long toggle;
-	unsigned long polar;
-	unsigned long polar_set;
-	unsigned long polar_clear;
-	unsigned long lock;
-	unsigned long spare;
-	unsigned long revid;
-};
-
-#endif
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf609/portmux.h b/arch/blackfin/include/asm/mach-bf609/portmux.h
deleted file mode 100644
index 757570f..0000000
--- a/arch/blackfin/include/asm/mach-bf609/portmux.h
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * Copyright 2008-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
-
-/* EMAC RMII Port Mux */
-#define P_MII0_MDC	(P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_MII0_MDIO	(P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_MII0_ETxD0	(P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_MII0_ERxD0	(P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_MII0_ETxD1	(P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_MII0_ERxD1	(P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_MII0_ETxEN	(P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_MII0_PHYINT	(P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_MII0_CRS	(P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_MII0_ERxER	(P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_MII0_TxCLK	(P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-
-#define P_RMII0 {\
-	P_MII0_ETxD0, \
-	P_MII0_ETxD1, \
-	P_MII0_ETxEN, \
-	P_MII0_ERxD0, \
-	P_MII0_ERxD1, \
-	P_MII0_ERxER, \
-	P_MII0_TxCLK, \
-	P_MII0_PHYINT, \
-	P_MII0_CRS, \
-	P_MII0_MDC, \
-	P_PTP0_PPS, \
-	P_PTP1_PPS, \
-	P_MII0_MDIO, 0}
-
-#define P_MII1_MDC	(P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_MII1_MDIO	(P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_MII1_ETxD0	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_MII1_ERxD0	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_MII1_ETxD1	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_MII1_ERxD1	(P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_MII1_ETxEN	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_MII1_PHYINT	(P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_MII1_CRS	(P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_MII1_ERxER	(P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_MII1_TxCLK	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-
-#define P_RMII1 {\
-	P_MII1_ETxD0, \
-	P_MII1_ETxD1, \
-	P_MII1_ETxEN, \
-	P_MII1_ERxD0, \
-	P_MII1_ERxD1, \
-	P_MII1_ERxER, \
-	P_MII1_TxCLK, \
-	P_MII1_PHYINT, \
-	P_MII1_CRS, \
-	P_MII1_MDC, \
-	P_MII1_MDIO, 0}
-
-/* PPI Port Mux */
-#define P_PPI0_D0	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_PPI0_D1	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_PPI0_D2	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PPI0_D3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define P_PPI0_D16	(P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_PPI0_D17	(P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_PPI0_D18	(P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_PPI0_D19	(P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_PPI0_D20	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_PPI0_D21	(P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_PPI0_D22	(P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_PPI0_D23	(P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_PPI0_CLK	(P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1))
-#define P_PPI0_FS1	(P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1))
-#define P_PPI0_FS2	(P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-
-#define P_PPI1_D0	(P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1))
-#define P_PPI1_D1	(P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_PPI1_D2	(P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1))
-#define P_PPI1_D3	(P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1))
-#define P_PPI1_D4	(P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1))
-#define P_PPI1_D5	(P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-#define P_PPI1_D6	(P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1))
-#define P_PPI1_D7	(P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1))
-#define P_PPI1_D8	(P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1))
-#define P_PPI1_D9	(P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1))
-#define P_PPI1_D10	(P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1))
-#define P_PPI1_D11	(P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1))
-#define P_PPI1_D12	(P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1))
-#define P_PPI1_D13	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1))
-#define P_PPI1_D14	(P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1))
-#define P_PPI1_D15	(P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1))
-#define P_PPI1_D16	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_PPI1_D17	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_PPI1_CLK	(P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1))
-#define P_PPI1_FS1	(P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1))
-#define P_PPI1_FS2	(P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_PPI1_FS3	(P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1))
-
-#define P_PPI2_D0	(P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1))
-#define P_PPI2_D1	(P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_PPI2_D2	(P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1))
-#define P_PPI2_D3	(P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1))
-#define P_PPI2_D4	(P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1))
-#define P_PPI2_D5	(P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_PPI2_D6	(P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1))
-#define P_PPI2_D7	(P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1))
-#define P_PPI2_D8	(P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1))
-#define P_PPI2_D9	(P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_PPI2_D10	(P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1))
-#define P_PPI2_D11	(P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1))
-#define P_PPI2_D12	(P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1))
-#define P_PPI2_D13	(P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-#define P_PPI2_D14	(P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1))
-#define P_PPI2_D15	(P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1))
-#define P_PPI2_D16	(P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1))
-#define P_PPI2_D17	(P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_PPI2_CLK	(P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1))
-#define P_PPI2_FS1	(P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1))
-#define P_PPI2_FS2	(P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1))
-#define P_PPI2_FS3	(P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_SPI0_SCK	(P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_SPI0_MISO	(P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_SPI0_MOSI	(P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_SPI0_RDY	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_SPI0_D2	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_SPI0_D3	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPI0_SSEL4	(P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0))
-#define P_SPI0_SSEL5	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_SPI0_SSEL6	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_SPI0_SSEL7	(P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-
-#define P_SPI1_SS	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_SPI1_SCK	(P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_SPI1_MISO	(P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_SPI1_MOSI	(P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_SPI1_RDY	(P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI1_D2	(P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI1_D3	(P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-
-#define P_SPI1_SSEL1	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_SPI1_SSEL2	(P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_SPI1_SSEL3	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_SPI1_SSEL4	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_SPI1_SSEL5	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_SPI1_SSEL6	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI1_SSEL7	(P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS
-#define P_DEFAULT_BOOT_SPI_CS
-
-/* UART Port Mux */
-#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_UART0_RTS	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_UART0_CTS	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_UART1_RTS	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_UART1_CTS	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-
-/* Timer */
-#define P_TMRCLK	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3))
-#define P_TMR0		(P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2))
-#define P_TMR1		(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_TMR2		(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-#define P_TMR3		(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_TMR4		(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_TMR5		(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_TMR6		(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-
-/* RSI */
-#define P_RSI_DATA0	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_RSI_DATA1	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_RSI_DATA2	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
-#define P_RSI_DATA3	(P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2))
-#define P_RSI_DATA4	(P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2))
-#define P_RSI_DATA5	(P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2))
-#define P_RSI_DATA6	(P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2))
-#define P_RSI_DATA7	(P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2))
-#define P_RSI_CMD	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_RSI_CLK	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-
-/* PTP */
-#define P_PTP0_PPS	(P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
-#define P_PTP0_CLKIN	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
-#define P_PTP0_AUXIN	(P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
-
-#define P_PTP1_PPS	(P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_PTP1_CLKIN	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
-#define P_PTP1_AUXIN	(P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
-
-/* SMC Port Mux */
-#define P_A3		(P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_A4		(P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_A5		(P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_A6		(P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_A7		(P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_A8		(P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_A9		(P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_A10		(P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_A11		(P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_A12		(P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_A13		(P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_A14		(P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_A15		(P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_A16		(P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_A17		(P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_A18		(P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_A19		(P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_A20		(P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_A21		(P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_A22		(P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_A23		(P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_A24		(P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_A25		(P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_NORCK         (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-
-#define P_AMS1		(P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_AMS2		(P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_AMS3		(P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-
-#define P_ABE0		(P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(1))
-#define P_ABE1		(P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(1))
-
-/* CAN */
-#define P_CAN0_TX	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_CAN0_RX	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-
-#endif				/* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf609/ports.h b/arch/blackfin/include/asm/mach-bf609/ports.h
deleted file mode 100644
index b361c7b..0000000
--- a/arch/blackfin/include/asm/mach-bf609/ports.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORTx_MUX Masks */
-#define PORT_x_MUX_0_MASK	0x00000003
-#define PORT_x_MUX_1_MASK	0x0000000C
-#define PORT_x_MUX_2_MASK	0x00000030
-#define PORT_x_MUX_3_MASK	0x000000C0
-#define PORT_x_MUX_4_MASK	0x00000300
-#define PORT_x_MUX_5_MASK	0x00000C00
-#define PORT_x_MUX_6_MASK	0x00003000
-#define PORT_x_MUX_7_MASK	0x0000C000
-#define PORT_x_MUX_8_MASK	0x00030000
-#define PORT_x_MUX_9_MASK	0x000C0000
-#define PORT_x_MUX_10_MASK	0x00300000
-#define PORT_x_MUX_11_MASK	0x00C00000
-#define PORT_x_MUX_12_MASK	0x03000000
-#define PORT_x_MUX_13_MASK	0x0C000000
-#define PORT_x_MUX_14_MASK	0x30000000
-#define PORT_x_MUX_15_MASK	0xC0000000
-
-#define PORT_x_MUX_FUNC_1	(0x0)
-#define PORT_x_MUX_FUNC_2	(0x1)
-#define PORT_x_MUX_FUNC_3	(0x2)
-#define PORT_x_MUX_FUNC_4	(0x3)
-#define PORT_x_MUX_0_FUNC_1	(PORT_x_MUX_FUNC_1 << 0)
-#define PORT_x_MUX_0_FUNC_2	(PORT_x_MUX_FUNC_2 << 0)
-#define PORT_x_MUX_0_FUNC_3	(PORT_x_MUX_FUNC_3 << 0)
-#define PORT_x_MUX_0_FUNC_4	(PORT_x_MUX_FUNC_4 << 0)
-#define PORT_x_MUX_1_FUNC_1	(PORT_x_MUX_FUNC_1 << 2)
-#define PORT_x_MUX_1_FUNC_2	(PORT_x_MUX_FUNC_2 << 2)
-#define PORT_x_MUX_1_FUNC_3	(PORT_x_MUX_FUNC_3 << 2)
-#define PORT_x_MUX_1_FUNC_4	(PORT_x_MUX_FUNC_4 << 2)
-#define PORT_x_MUX_2_FUNC_1	(PORT_x_MUX_FUNC_1 << 4)
-#define PORT_x_MUX_2_FUNC_2	(PORT_x_MUX_FUNC_2 << 4)
-#define PORT_x_MUX_2_FUNC_3	(PORT_x_MUX_FUNC_3 << 4)
-#define PORT_x_MUX_2_FUNC_4	(PORT_x_MUX_FUNC_4 << 4)
-#define PORT_x_MUX_3_FUNC_1	(PORT_x_MUX_FUNC_1 << 6)
-#define PORT_x_MUX_3_FUNC_2	(PORT_x_MUX_FUNC_2 << 6)
-#define PORT_x_MUX_3_FUNC_3	(PORT_x_MUX_FUNC_3 << 6)
-#define PORT_x_MUX_3_FUNC_4	(PORT_x_MUX_FUNC_4 << 6)
-#define PORT_x_MUX_4_FUNC_1	(PORT_x_MUX_FUNC_1 << 8)
-#define PORT_x_MUX_4_FUNC_2	(PORT_x_MUX_FUNC_2 << 8)
-#define PORT_x_MUX_4_FUNC_3	(PORT_x_MUX_FUNC_3 << 8)
-#define PORT_x_MUX_4_FUNC_4	(PORT_x_MUX_FUNC_4 << 8)
-#define PORT_x_MUX_5_FUNC_1	(PORT_x_MUX_FUNC_1 << 10)
-#define PORT_x_MUX_5_FUNC_2	(PORT_x_MUX_FUNC_2 << 10)
-#define PORT_x_MUX_5_FUNC_3	(PORT_x_MUX_FUNC_3 << 10)
-#define PORT_x_MUX_5_FUNC_4	(PORT_x_MUX_FUNC_4 << 10)
-#define PORT_x_MUX_6_FUNC_1	(PORT_x_MUX_FUNC_1 << 12)
-#define PORT_x_MUX_6_FUNC_2	(PORT_x_MUX_FUNC_2 << 12)
-#define PORT_x_MUX_6_FUNC_3	(PORT_x_MUX_FUNC_3 << 12)
-#define PORT_x_MUX_6_FUNC_4	(PORT_x_MUX_FUNC_4 << 12)
-#define PORT_x_MUX_7_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_8_FUNC_1	(PORT_x_MUX_FUNC_1 << 16)
-#define PORT_x_MUX_8_FUNC_2	(PORT_x_MUX_FUNC_2 << 16)
-#define PORT_x_MUX_8_FUNC_3	(PORT_x_MUX_FUNC_3 << 16)
-#define PORT_x_MUX_8_FUNC_4	(PORT_x_MUX_FUNC_4 << 16)
-#define PORT_x_MUX_9_FUNC_1	(PORT_x_MUX_FUNC_1 << 18)
-#define PORT_x_MUX_9_FUNC_2	(PORT_x_MUX_FUNC_2 << 18)
-#define PORT_x_MUX_9_FUNC_3	(PORT_x_MUX_FUNC_3 << 18)
-#define PORT_x_MUX_9_FUNC_4	(PORT_x_MUX_FUNC_4 << 18)
-#define PORT_x_MUX_10_FUNC_1	(PORT_x_MUX_FUNC_1 << 20)
-#define PORT_x_MUX_10_FUNC_2	(PORT_x_MUX_FUNC_2 << 20)
-#define PORT_x_MUX_10_FUNC_3	(PORT_x_MUX_FUNC_3 << 20)
-#define PORT_x_MUX_10_FUNC_4	(PORT_x_MUX_FUNC_4 << 20)
-#define PORT_x_MUX_11_FUNC_1	(PORT_x_MUX_FUNC_1 << 22)
-#define PORT_x_MUX_11_FUNC_2	(PORT_x_MUX_FUNC_2 << 22)
-#define PORT_x_MUX_11_FUNC_3	(PORT_x_MUX_FUNC_3 << 22)
-#define PORT_x_MUX_11_FUNC_4	(PORT_x_MUX_FUNC_4 << 22)
-#define PORT_x_MUX_12_FUNC_1	(PORT_x_MUX_FUNC_1 << 24)
-#define PORT_x_MUX_12_FUNC_2	(PORT_x_MUX_FUNC_2 << 24)
-#define PORT_x_MUX_12_FUNC_3	(PORT_x_MUX_FUNC_3 << 24)
-#define PORT_x_MUX_12_FUNC_4	(PORT_x_MUX_FUNC_4 << 24)
-#define PORT_x_MUX_13_FUNC_1	(PORT_x_MUX_FUNC_1 << 26)
-#define PORT_x_MUX_13_FUNC_2	(PORT_x_MUX_FUNC_2 << 26)
-#define PORT_x_MUX_13_FUNC_3	(PORT_x_MUX_FUNC_3 << 26)
-#define PORT_x_MUX_13_FUNC_4	(PORT_x_MUX_FUNC_4 << 26)
-#define PORT_x_MUX_14_FUNC_1	(PORT_x_MUX_FUNC_1 << 28)
-#define PORT_x_MUX_14_FUNC_2	(PORT_x_MUX_FUNC_2 << 28)
-#define PORT_x_MUX_14_FUNC_3	(PORT_x_MUX_FUNC_3 << 28)
-#define PORT_x_MUX_14_FUNC_4	(PORT_x_MUX_FUNC_4 << 28)
-#define PORT_x_MUX_15_FUNC_1	(PORT_x_MUX_FUNC_1 << 30)
-#define PORT_x_MUX_15_FUNC_2	(PORT_x_MUX_FUNC_2 << 30)
-#define PORT_x_MUX_15_FUNC_3	(PORT_x_MUX_FUNC_3 << 30)
-#define PORT_x_MUX_15_FUNC_4	(PORT_x_MUX_FUNC_4 << 30)
-
-#include "../mach-common/bits/ports-a.h"
-#include "../mach-common/bits/ports-b.h"
-#include "../mach-common/bits/ports-c.h"
-#include "../mach-common/bits/ports-d.h"
-#include "../mach-common/bits/ports-e.h"
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h
deleted file mode 100644
index 3acf94b..0000000
--- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h
+++ /dev/null
@@ -1,276 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_EDN_core__
-#define __BFIN_CDEF_ADSP_EDN_core__
-
-#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define bfin_read_DCPLB_FAULT_STATUS() bfin_read32(DCPLB_FAULT_STATUS)
-#define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val)
-#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-
-#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-
-#define bfin_read_EVT0()               bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define bfin_read_EVT1()               bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define bfin_read_EVT2()               bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define bfin_read_EVT3()               bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define bfin_read_EVT4()               bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define bfin_read_EVT5()               bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define bfin_read_EVT6()               bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define bfin_read_EVT7()               bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define bfin_read_EVT8()               bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define bfin_read_EVT9()               bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define bfin_read_EVT10()              bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define bfin_read_EVT11()              bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define bfin_read_EVT12()              bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define bfin_read_EVT13()              bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define bfin_read_EVT14()              bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define bfin_read_EVT15()              bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-
-#define bfin_read_EVT_OVERRIDE()       bfin_read32(EVT_OVERRIDE)
-#define bfin_write_EVT_OVERRIDE(val)   bfin_write32(EVT_OVERRIDE, val)
-#define bfin_read_ILAT()               bfin_read32(ILAT)
-#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define bfin_read_IMASK()              bfin_read32(IMASK)
-#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define bfin_read_IPEND()              bfin_read32(IPEND)
-#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define bfin_read_IPRIO()              bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-
-#define bfin_read_TCNTL()              bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define bfin_read_TSCALE()             bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
-#define bfin_read_DBGSTAT()            bfin_read32(DBGSTAT)
-#define bfin_write_DBGSTAT(val)        bfin_write32(DBGSTAT, val)
-
-#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define bfin_read_TBUF()               bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
-
-#define bfin_read_WPIACTL()            bfin_read32(WPIACTL)
-#define bfin_write_WPIACTL(val)        bfin_write32(WPIACTL, val)
-#define bfin_read_WPIA0()              bfin_readPTR(WPIA0)
-#define bfin_write_WPIA0(val)          bfin_writePTR(WPIA0, val)
-#define bfin_read_WPIA1()              bfin_readPTR(WPIA1)
-#define bfin_write_WPIA1(val)          bfin_writePTR(WPIA1, val)
-#define bfin_read_WPIA2()              bfin_readPTR(WPIA2)
-#define bfin_write_WPIA2(val)          bfin_writePTR(WPIA2, val)
-#define bfin_read_WPIA3()              bfin_readPTR(WPIA3)
-#define bfin_write_WPIA3(val)          bfin_writePTR(WPIA3, val)
-#define bfin_read_WPIA4()              bfin_readPTR(WPIA4)
-#define bfin_write_WPIA4(val)          bfin_writePTR(WPIA4, val)
-#define bfin_read_WPIA5()              bfin_readPTR(WPIA5)
-#define bfin_write_WPIA5(val)          bfin_writePTR(WPIA5, val)
-#define bfin_read_WPIACNT0()           bfin_read32(WPIACNT0)
-#define bfin_write_WPIACNT0(val)       bfin_write32(WPIACNT0, val)
-#define bfin_read_WPIACNT1()           bfin_read32(WPIACNT1)
-#define bfin_write_WPIACNT1(val)       bfin_write32(WPIACNT1, val)
-#define bfin_read_WPIACNT2()           bfin_read32(WPIACNT2)
-#define bfin_write_WPIACNT2(val)       bfin_write32(WPIACNT2, val)
-#define bfin_read_WPIACNT3()           bfin_read32(WPIACNT3)
-#define bfin_write_WPIACNT3(val)       bfin_write32(WPIACNT3, val)
-#define bfin_read_WPIACNT4()           bfin_read32(WPIACNT4)
-#define bfin_write_WPIACNT4(val)       bfin_write32(WPIACNT4, val)
-#define bfin_read_WPIACNT5()           bfin_read32(WPIACNT5)
-#define bfin_write_WPIACNT5(val)       bfin_write32(WPIACNT5, val)
-#define bfin_read_WPDACTL()            bfin_read32(WPDACTL)
-#define bfin_write_WPDACTL(val)        bfin_write32(WPDACTL, val)
-#define bfin_read_WPDA0()              bfin_readPTR(WPDA0)
-#define bfin_write_WPDA0(val)          bfin_writePTR(WPDA0, val)
-#define bfin_read_WPDA1()              bfin_readPTR(WPDA1)
-#define bfin_write_WPDA1(val)          bfin_writePTR(WPDA1, val)
-#define bfin_read_WPDACNT0()           bfin_read32(WPDACNT0)
-#define bfin_write_WPDACNT0(val)       bfin_write32(WPDACNT0, val)
-#define bfin_read_WPDACNT1()           bfin_read32(WPDACNT1)
-#define bfin_write_WPDACNT1(val)       bfin_write32(WPDACNT1, val)
-#define bfin_read_WPSTAT()             bfin_read32(WPSTAT)
-#define bfin_write_WPSTAT(val)         bfin_write32(WPSTAT, val)
-
-#define bfin_read_PFCTL()              bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
-#define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
-#define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
-
-#endif /* __BFIN_CDEF_ADSP_EDN_core__ */
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h
deleted file mode 100644
index cf28b8e..0000000
--- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_EDN_core__
-#define __BFIN_DEF_ADSP_EDN_core__
-
-#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
-#define DCPLB_FAULT_STATUS             0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
-
-#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_FAULT_STATUS             0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
-
-#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
-
-#define EVT_OVERRIDE                   0xFFE02100
-#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
-#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
-#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-
-#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
-#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
-
-#define DSPID                          0xFFE05000
-#define DBGSTAT                        0xFFE05008
-
-#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF                           0xFFE06100 /* Trace Buffer */
-
-#define WPIACTL                        0xFFE07000
-#define WPIA0                          0xFFE07040
-#define WPIA1                          0xFFE07044
-#define WPIA2                          0xFFE07048
-#define WPIA3                          0xFFE0704C
-#define WPIA4                          0xFFE07050
-#define WPIA5                          0xFFE07054
-#define WPIACNT0                       0xFFE07080
-#define WPIACNT1                       0xFFE07084
-#define WPIACNT2                       0xFFE07088
-#define WPIACNT3                       0xFFE0708C
-#define WPIACNT4                       0xFFE07090
-#define WPIACNT5                       0xFFE07094
-#define WPDACTL                        0xFFE07100
-#define WPDA0                          0xFFE07140
-#define WPDA1                          0xFFE07144
-#define WPDACNT0                       0xFFE07180
-#define WPDACNT1                       0xFFE07184
-#define WPSTAT                         0xFFE07200
-
-#define PFCTL                          0xFFE08000
-#define PFCNTR0                        0xFFE08100
-#define PFCNTR1                        0xFFE08104
-
-#endif /* __BFIN_DEF_ADSP_EDN_core__ */
diff --git a/arch/blackfin/include/asm/mach-common/bits/bootrom.h b/arch/blackfin/include/asm/mach-common/bits/bootrom.h
deleted file mode 100644
index 0e2cacb..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/bootrom.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * Boot ROM Entry Points and such
- */
-
-/* These Blackfins all have a Boot ROM that is not reusable (at all):
- *  BF531 / BF532 / BF533
- *  BF538 / BF539
- *  BF561
- * So there is nothing for us to export ;(
- *
- * These Blackfins started to roll with the idea that the Boot ROM can
- * provide useful functions, but still only a few (and not really useful):
- *  BF534 / BF536 / BF537
- *
- * Looking forward, Boot ROM's on newer Blackfins have quite a few
- * nice entry points that are usable at runtime and beyond.  We'll
- * only define known legacy parts (listed above) and otherwise just
- * assume it's a newer part.
- *
- * These entry points are accomplished by placing a small jump table at
- * the start of the Boot ROM.  This way the addresses are fixed forever.
- */
-
-#ifndef __BFIN_PERIPHERAL_BOOTROM__
-#define __BFIN_PERIPHERAL_BOOTROM__
-
-/* All Blackfin's have the Boot ROM entry point at the same address */
-#define _BOOTROM_RESET 0xEF000000
-
-#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
-    defined(__ADSPBF538__) || defined(__ADSPBF539__) || \
-    defined(__ADSPBF561__)
-
-	/* Nothing to export */
-
-#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
-
-	/* The BF537 family */
-
-#define _BOOTROM_FINAL_INIT            0xEF000002
-/*       reserved                      0xEF000004 */
-#define _BOOTROM_DO_MEMORY_DMA         0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH        0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI          0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI          0xEF00000C
-/*       reserved                      0xEF00000E */
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI   0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI   0xEF000014
-/*       reserved                      0xEF000016 */
-/*       reserved                      0xEF000018 */
-
-	/* Glue to newer Boot ROMs */
-#define _BOOTROM_MDMA                  _BOOTROM_DO_MEMORY_DMA
-#define _BOOTROM_MEMBOOT               _BOOTROM_BOOT_DXE_FLASH
-#define _BOOTROM_SPIBOOT               _BOOTROM_BOOT_DXE_FLASH
-#define _BOOTROM_TWIBOOT               _BOOTROM_BOOT_DXE_TWI
-
-#else
-
-	/* All the newer Boot ROMs */
-
-#define _BOOTROM_FINAL_INIT            0xEF000002
-#define _BOOTROM_PDMA                  0xEF000004
-#define _BOOTROM_MDMA                  0xEF000006
-#define _BOOTROM_MEMBOOT               0xEF000008
-#define _BOOTROM_SPIBOOT               0xEF00000A
-#define _BOOTROM_TWIBOOT               0xEF00000C
-/*       reserved                      0xEF00000E */
-/*       reserved                      0xEF000010 */
-/*       reserved                      0xEF000012 */
-/*       reserved                      0xEF000014 */
-/*       reserved                      0xEF000016 */
-#define _BOOTROM_OTP_COMMAND           0xEF000018
-#define _BOOTROM_OTP_READ              0xEF00001A
-#define _BOOTROM_OTP_WRITE             0xEF00001C
-#define _BOOTROM_ECC_TABLE             0xEF00001E
-#define _BOOTROM_BOOTKERNEL            0xEF000020
-#define _BOOTROM_GETPORT               0xEF000022
-#define _BOOTROM_NMI                   0xEF000024
-#define _BOOTROM_HWERROR               0xEF000026
-#define _BOOTROM_EXCEPTION             0xEF000028
-#define _BOOTROM_CRC32                 0xEF000030
-#define _BOOTROM_CRC32POLY             0xEF000032
-#define _BOOTROM_CRC32CALLBACK         0xEF000034
-#define _BOOTROM_CRC32INITCODE         0xEF000036
-#define _BOOTROM_SYSCONTROL            0xEF000038
-#define _BOOTROM_REV                   0xEF000040
-#define _BOOTROM_SESR                  0xEF001000
-
-#define BOOTROM_FOLLOWS_C_ABI 1
-
-#define BOOTROM_CAPS_ADI_BOOT_STRUCTS 1
-
-#endif
-
-#ifndef BOOTROM_FOLLOWS_C_ABI
-#define BOOTROM_FOLLOWS_C_ABI 0
-#endif
-#ifndef BOOTROM_CAPS_ADI_BOOT_STRUCTS
-#define BOOTROM_CAPS_ADI_BOOT_STRUCTS 0
-#endif
-
-/* Possible syscontrol action flags */
-#define SYSCTRL_READ        0x00000000    /* read registers */
-#define SYSCTRL_WRITE       0x00000001    /* write registers */
-#define SYSCTRL_SYSRESET    0x00000002    /* perform system reset */
-#define SYSCTRL_CORERESET   0x00000004    /* perform core reset */
-#define SYSCTRL_SOFTRESET   0x00000006    /* perform core and system reset */
-#define SYSCTRL_VRCTL       0x00000010    /* read/write VR_CTL register */
-#define SYSCTRL_EXTVOLTAGE  0x00000020    /* VDDINT supplied externally */
-#define SYSCTRL_INTVOLTAGE  0x00000000    /* VDDINT generated by on-chip regulator */
-#define SYSCTRL_OTPVOLTAGE  0x00000040    /* For Factory Purposes Only */
-#define SYSCTRL_PLLCTL      0x00000100    /* read/write PLL_CTL register */
-#define SYSCTRL_PLLDIV      0x00000200    /* read/write PLL_DIV register */
-#define SYSCTRL_LOCKCNT     0x00000400    /* read/write PLL_LOCKCNT register */
-#define SYSCTRL_PLLSTAT     0x00000800    /* read/write PLL_STAT register */
-
-#ifndef __ASSEMBLY__
-
-#if BOOTROM_FOLLOWS_C_ABI
-# define BOOTROM_CALLED_FUNC_ATTR
-#else
-# define BOOTROM_CALLED_FUNC_ATTR __attribute__((saveall))
-#endif
-
-/* Structures for the syscontrol() function */
-typedef struct ADI_SYSCTRL_VALUES {
-	uint16_t uwVrCtl;
-	uint16_t uwPllCtl;
-	uint16_t uwPllDiv;
-	uint16_t uwPllLockCnt;
-	uint16_t uwPllStat;
-} ADI_SYSCTRL_VALUES;
-
-#ifndef _BOOTROM_SYSCONTROL
-#define _BOOTROM_SYSCONTROL 0
-#endif
-static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)_BOOTROM_SYSCONTROL;
-
-/* We need a dedicated function since we need to screw with the stack pointer
- * when resetting.  The on-chip ROM will save/restore registers on the stack
- * when doing a system reset, so the stack cannot be outside of the chip.
- */
-__attribute__((__noreturn__))
-static inline void bfrom_SoftReset(void *new_stack)
-{
-	while (1)
-		__asm__ __volatile__(
-			"sp = %[stack];"
-			"jump (%[bfrom_syscontrol]);"
-			: : [bfrom_syscontrol] "p"(bfrom_SysControl),
-				"q0"(SYSCTRL_SOFTRESET),
-				"q1"(0),
-				"q2"(NULL),
-				[stack] "p"(new_stack)
-		);
-}
-
-/* Structures for working with LDRs and boot rom callbacks */
-typedef struct ADI_BOOT_HEADER {
-	int32_t dBlockCode;
-	void    *pTargetAddress;
-	int32_t dByteCount;
-	int32_t dArgument;
-} ADI_BOOT_HEADER;
-
-typedef struct ADI_BOOT_BUFFER {
-	void    *pSource;
-	int32_t dByteCount;
-} ADI_BOOT_BUFFER;
-
-typedef struct ADI_BOOT_DATA {
-	void    *pSource;
-	void    *pDestination;
-	int16_t *pControlRegister;
-	int16_t *pDmaControlRegister;
-	int32_t dControlValue;
-	int32_t dByteCount;
-	int32_t dFlags;
-	int16_t uwDataWidth;
-	int16_t uwSrcModifyMult;
-	int16_t uwDstModifyMult;
-	int16_t uwHwait;
-	int16_t uwSsel;
-	int16_t uwUserShort;
-	int32_t dUserLong;
-	int32_t dReserved2;
-	void    *pErrorFunction;
-	void    *pLoadFunction;
-	void    *pCallBackFunction;
-	ADI_BOOT_HEADER *pHeader;
-	void    *pTempBuffer;
-	void    *pTempCurrent;
-	int32_t dTempByteCount;
-	int32_t dBlockCount;
-	int32_t dClock;
-	void    *pLogBuffer;
-	void    *pLogCurrent;
-	int32_t dLogByteCount;
-} ADI_BOOT_DATA;
-
-typedef void ADI_BOOT_HOOK_FUNC (ADI_BOOT_DATA *);
-
-#ifndef _BOOTROM_MEMBOOT
-#define _BOOTROM_MEMBOOT 0
-#endif
-static uint32_t (* const bfrom_MemBoot)(void *pBootStream, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_MEMBOOT;
-
-#ifndef _BOOTROM_TWIBOOT
-#define _BOOTROM_TWIBOOT 0
-#endif
-static uint32_t (* const bfrom_TwiBoot)(int32_t dTwiAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_TWIBOOT;
-
-#ifndef _BOOTROM_SPIBOOT
-#define _BOOTROM_SPIBOOT 0
-#endif
-static uint32_t (* const bfrom_SpiBoot)(int32_t dSpiAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_SPIBOOT;
-
-#ifndef _BOOTROM_OTPBOOT
-#define _BOOTROM_OTPBOOT 0
-#endif
-static uint32_t (* const bfrom_OtpBoot)(int32_t dOtpAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_OTPBOOT;
-
-#ifndef _BOOTROM_NANDBOOT
-#define _BOOTROM_NANDBOOT 0
-#endif
-static uint32_t (* const bfrom_NandBoot)(int32_t dNandAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_NANDBOOT;
-
-#endif /* __ASSEMBLY__ */
-
-/* Bit defines for BF53x block flags */
-#define BFLAG_53X_ZEROFILL     0x0001
-#define BFLAG_53X_RESVECT      0x0002
-#define BFLAG_53X_INIT         0x0008
-#define BFLAG_53X_IGNORE       0x0010
-#define BFLAG_53X_PFLAG_MASK   0x01E0
-#define BFLAG_53X_PFLAG_SHIFT  5
-#define BFLAG_53X_PPORT_MASK   0x0600
-#define BFLAG_53X_PPORT_SHIFT  9
-#define BFLAG_53X_COMPRESSED   0x2000
-#define BFLAG_53X_FINAL        0x8000
-
-/* Bit defines for BF56x global header */
-#define GFLAG_56X_16BIT_FLASH  0x00000001
-#define GFLAG_56X_WAIT_MASK    0x0000001E
-#define GFLAG_56X_WAIT_SHIFT   1
-#define GFLAG_56X_HOLD_MASK    0x000000C0
-#define GFLAG_56X_HOLD_SHIFT   6
-#define GFLAG_56X_SPI_MASK     0x00000700
-#define GFLAG_56X_SPI_SHIFT    8
-#define GFLAG_56X_SPI_500K     0x0
-#define GFLAG_56X_SPI_1M       0x1
-#define GFLAG_56X_SPI_2M       0x2
-#define GFLAG_56X_SIGN_MASK    0xFF000000
-#define GFLAG_56X_SIGN_SHIFT   28
-#define GFLAG_56X_SIGN_MAGIC   0xA
-
-/* Bit defines for ADI_BOOT_DATA->dFlags */
-#define BFLAG_DMACODE_MASK     0x0000000F
-#define BFLAG_SAFE             0x00000010
-#define BFLAG_AUX              0x00000020
-#define BFLAG_FILL             0x00000100
-#define BFLAG_QUICKBOOT        0x00000200
-#define BFLAG_CALLBACK         0x00000400
-#define BFLAG_INIT             0x00000800
-#define BFLAG_IGNORE           0x00001000
-#define BFLAG_INDIRECT         0x00002000
-#define BFLAG_FIRST            0x00004000
-#define BFLAG_FINAL            0x00008000
-#define BFLAG_HDRSIGN_MASK     0xFF000000
-#define BFLAG_HDRSIGN_SHIFT    24
-#define BFLAG_HDRSIGN_MAGIC    0xAD
-#define BFLAG_HDRCHK_MASK      0x00FF0000
-#define BFLAG_HDRCHK_SHIFT     16
-#define BFLAG_HOOK             0x00400000
-#define BFLAG_HDRINDIRECT      0x00800000
-#define BFLAG_TYPE_MASK        0x00300000
-#define BFLAG_TYPE_1           0x00000000
-#define BFLAG_TYPE_2           0x00100000
-#define BFLAG_TYPE_3           0x00200000
-#define BFLAG_TYPE_4           0x00300000
-#define BFLAG_FASTREAD         0x00400000
-#define BFLAG_NOAUTO           0x01000000
-#define BFLAG_PERIPHERAL       0x02000000
-#define BFLAG_SLAVE            0x04000000
-#define BFLAG_WAKEUP           0x08000000
-#define BFLAG_NEXTDXE          0x10000000
-#define BFLAG_RETURN           0x20000000
-#define BFLAG_RESET            0x40000000
-#define BFLAG_NONRESTORE       0x80000000
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/cgu.h b/arch/blackfin/include/asm/mach-common/bits/cgu.h
deleted file mode 100644
index cdf7349..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/cgu.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * CGU Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_CGU__
-#define __BFIN_PERIPHERAL_CGU__
-
-/* CGU_CTL Masks */
-#define DF			(1 << 0)
-#define MSEL			(0x7f << MSEL_P)
-#define WIDLE			(1 << WIDLE_P)
-#define LOCK			(1 << LOCK_P)
-
-#define DF_P			0
-#define MSEL_P			8
-#define WIDLE_P			30
-#define LOCK_P			31
-#define MSEL_MASK               0x7F00
-#define DF_MASK                 0x1
-
-/* CGU_STAT Masks */
-#define PLLEN			(1 << 0)
-#define PLLBP			(1 << 1)
-#define PLLLK			(1 << 2)
-#define CLKSALGN		(1 << 3)
-#define CCBF0EN			(1 << 4)
-#define CCBF1EN			(1 << 5)
-#define SCBF0EN			(1 << 6)
-#define SCBF1EN			(1 << 7)
-#define DCBFEN			(1 << 8)
-#define OCBFEN			(1 << 9)
-#define ADRERR			(1 << 16)
-#define LWERR			(1 << 17)
-#define DIVERR			(1 << 18)
-#define WDFMSERR		(1 << 19)
-#define WDIVERR			(1 << 20)
-#define PLLLKERR		(1 << 21)
-
-/* CGU_DIV Masks */
-#define CSEL			(0x1f << CSEL_P)
-#define S0SEL			(3 << S0SEL_P)
-#define SYSSEL			(0x1f << SYSSEL_P)
-#define S1SEL			(3 << S1SEL_P)
-#define DSEL			(0x1f << DSEL_P)
-#define OSEL			(0x7f << OSEL_P)
-#define ALGN			(1 << ALGN_P)
-#define UPDT			(1 << UPDT_P)
-#define LOCK			(1 << LOCK_P)
-
-#define CSEL_P			0
-#define S0SEL_P			5
-#define SYSSEL_P		8
-#define S1SEL_P			13
-#define DSEL_P			16
-#define OSEL_P			22
-#define ALGN_P			29
-#define UPDT_P			30
-#define LOCK_P			31
-
-/* CGU_CLKOUTSEL Masks */
-#define CLKOUTSEL		(0xf << 0)
-#define USBCLKSEL		(0x3f << 16)
-#define LOCK			(1 << LOCK_P)
-
-#define LOCK_P			31
-
-#define CLKOUTSEL_CLKIN		0x0
-#define CLKOUTSEL_CCLK		0x1
-#define CLKOUTSEL_SYSCLK	0x2
-#define CLKOUTSEL_SCLK0		0x3
-#define CLKOUTSEL_SCLK1		0x4
-#define CLKOUTSEL_DCLK		0x5
-#define CLKOUTSEL_USB_PLL	0x6
-#define CLKOUTSEL_OUTCLK	0x7
-#define CLKOUTSEL_USB_CLKIN	0x8
-#define CLKOUTSEL_WDOG		0x9
-#define CLKOUTSEL_PMON		0xA
-#define CLKOUTSEL_GND		0xB
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/core.h b/arch/blackfin/include/asm/mach-common/bits/core.h
deleted file mode 100644
index 6db4f81..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/core.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Misc Core Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_CORE__
-#define __BFIN_PERIPHERAL_CORE__
-
-/*
- * EVT registers (ILAT, IMASK, and IPEND).
- */
-
-#define EVT_EMU_P		0	/* Emulator interrupt bit position */
-#define EVT_RST_P		1	/* Reset interrupt bit position */
-#define EVT_NMI_P		2	/* Non Maskable interrupt bit position */
-#define EVT_EVX_P		3	/* Exception bit position */
-#define EVT_IRPTEN_P		4	/* Global interrupt enable bit position */
-#define EVT_IVHW_P		5	/* Hardware Error interrupt bit position */
-#define EVT_IVTMR_P		6	/* Timer interrupt bit position */
-#define EVT_IVG7_P		7	/* IVG7 interrupt bit position */
-#define EVT_IVG8_P		8	/* IVG8 interrupt bit position */
-#define EVT_IVG9_P		9	/* IVG9 interrupt bit position */
-#define EVT_IVG10_P		10	/* IVG10 interrupt bit position */
-#define EVT_IVG11_P		11	/* IVG11 interrupt bit position */
-#define EVT_IVG12_P		12	/* IVG12 interrupt bit position */
-#define EVT_IVG13_P		13	/* IVG13 interrupt bit position */
-#define EVT_IVG14_P		14	/* IVG14 interrupt bit position */
-#define EVT_IVG15_P		15	/* IVG15 interrupt bit position */
-
-#define EVT_EMU			MK_BMSK_(EVT_EMU_P   )	/* Emulator interrupt mask */
-#define EVT_RST			MK_BMSK_(EVT_RST_P   )	/* Reset interrupt mask */
-#define EVT_NMI			MK_BMSK_(EVT_NMI_P   )	/* Non Maskable interrupt mask */
-#define EVT_EVX			MK_BMSK_(EVT_EVX_P   )	/* Exception mask */
-#define EVT_IRPTEN		MK_BMSK_(EVT_IRPTEN_P)	/* Global interrupt enable mask */
-#define EVT_IVHW		MK_BMSK_(EVT_IVHW_P  )	/* Hardware Error interrupt mask */
-#define EVT_IVTMR		MK_BMSK_(EVT_IVTMR_P )	/* Timer interrupt mask */
-#define EVT_IVG7		MK_BMSK_(EVT_IVG7_P  )	/* IVG7 interrupt mask */
-#define EVT_IVG8		MK_BMSK_(EVT_IVG8_P  )	/* IVG8 interrupt mask */
-#define EVT_IVG9		MK_BMSK_(EVT_IVG9_P  )	/* IVG9 interrupt mask */
-#define EVT_IVG10		MK_BMSK_(EVT_IVG10_P )	/* IVG10 interrupt mask */
-#define EVT_IVG11		MK_BMSK_(EVT_IVG11_P )	/* IVG11 interrupt mask */
-#define EVT_IVG12		MK_BMSK_(EVT_IVG12_P )	/* IVG12 interrupt mask */
-#define EVT_IVG13		MK_BMSK_(EVT_IVG13_P )	/* IVG13 interrupt mask */
-#define EVT_IVG14		MK_BMSK_(EVT_IVG14_P )	/* IVG14 interrupt mask */
-#define EVT_IVG15		MK_BMSK_(EVT_IVG15_P )	/* IVG15 interrupt mask */
-
-/*
- * SEQSTAT register
- */
-
-#define EXCAUSE_P	0	/* Last exception cause bit positions */
-#define EXCAUSE0_P	0	/* Last exception cause bit 0 */
-#define EXCAUSE1_P	1	/* Last exception cause bit 1 */
-#define EXCAUSE2_P	2	/* Last exception cause bit 2 */
-#define EXCAUSE3_P	3	/* Last exception cause bit 3 */
-#define EXCAUSE4_P	4	/* Last exception cause bit 4 */
-#define EXCAUSE5_P	5	/* Last exception cause bit 5 */
-#define IDLE_REQ_P	12	/* Pending idle mode request, set by IDLE instruction */
-#define SFTRESET_P	13	/* Indicates whether the last reset was a software reset (=1) */
-#define HWERRCAUSE_P	14	/* Last hw error cause bit positions */
-#define HWERRCAUSE0_P	14	/* Last hw error cause bit 0 */
-#define HWERRCAUSE1_P	15	/* Last hw error cause bit 1 */
-#define HWERRCAUSE2_P	16	/* Last hw error cause bit 2 */
-#define HWERRCAUSE3_P	17	/* Last hw error cause bit 3 */
-#define HWERRCAUSE4_P	18	/* Last hw error cause bit 4 */
-#define HWERRCAUSE5_P	19	/* Last hw error cause bit 5 */
-#define HWERRCAUSE6_P	20	/* Last hw error cause bit 6 */
-#define HWERRCAUSE7_P	21	/* Last hw error cause bit 7 */
-
-#define EXCAUSE \
-	( MK_BMSK_(EXCAUSE0_P) | \
-	  MK_BMSK_(EXCAUSE1_P) | \
-	  MK_BMSK_(EXCAUSE2_P) | \
-	  MK_BMSK_(EXCAUSE3_P) | \
-	  MK_BMSK_(EXCAUSE4_P) | \
-	  MK_BMSK_(EXCAUSE5_P) )
-#define SFTRESET \
-	( MK_BMSK_(SFTRESET_P) )
-#define HWERRCAUSE \
-	( MK_BMSK_(HWERRCAUSE0_P) | \
-	  MK_BMSK_(HWERRCAUSE1_P) | \
-	  MK_BMSK_(HWERRCAUSE2_P) | \
-	  MK_BMSK_(HWERRCAUSE3_P) | \
-	  MK_BMSK_(HWERRCAUSE4_P) )
-
-/* SWRST Masks */
-#define SYSTEM_RESET		0x0007		/* Initiates A System Software Reset */
-#ifdef __ADSPBF561__
-# define DOUBLE_FAULT_A		0x0008
-# define DOUBLE_FAULT_B		0x0010
-# define DOUBLE_FAULT		0x0018		/* Core [A|B] Double Fault Causes Reset */
-# define RESET_DOUBLE_A		0x0800
-# define RESET_DOUBLE_B		0x1000
-# define RESET_DOUBLE		0x1800		/* SW Reset Generated By Core [A|B] Double-Fault */
-# define RESET_WDOG_B		0x2000
-# define RESET_WDOG_A		0x4000
-# define RESET_WDOG		0x6000		/* SW Reset Generated By Watchdog [A|B] Timer */
-#else
-# define DOUBLE_FAULT		0x0008		/* Core Double Fault Causes Reset */
-# define RESET_DOUBLE		0x2000		/* SW Reset Generated By Core Double-Fault */
-# define RESET_WDOG		0x4000		/* SW Reset Generated By Watchdog Timer */
-#endif
-#define RESET_SOFTWARE		0x8000		/* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCFG Masks */
-#define SSSTEP			0x00000001	/* Supervisor Single Step */
-#define CCEN			0x00000002	/* Cycle Counter Enable */
-#define SNEN			0x00000004	/* Self-Nesting Interrupt Enable */
-#define SYSCFG_SSSTEP_P	0
-#define SYSCFG_CCEN_P	1
-#define SYSCFG_SCEN_P	2
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/dde.h b/arch/blackfin/include/asm/mach-common/bits/dde.h
deleted file mode 100644
index f7b0bb9..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/dde.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Distributed DMA Engine (DDE) Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_DDE__
-#define __BFIN_PERIPHERAL_DDE__
-
-/* DMA_CONFIG Masks */
-#define DMAEN			(1 << DMAEN_P)	/* DMA Channel Enable */
-#define WNR			(1 << WNR_P)	/* Channel Direction (W/R*) */
-#define SYNC			(1 << SYNC_P)	/* Sync Work Unit Transitions */
-#define CADDR			(1 << CADDR_P)	/* Use Current Address */
-#define PSIZE			(7 << PSIZE_P)	/* Peripheral Word Size */
-#define PSIZE_1			(0 << PSIZE_P)
-#define PSIZE_2			(1 << PSIZE_P)
-#define PSIZE_4			(2 << PSIZE_P)
-#define PSIZE_8			(3 << PSIZE_P)
-#define MSIZE			(7 << MSIZE_P)	/* Memory Transfer Size */
-#define MSIZE_1			(0 << MSIZE_P)
-#define MSIZE_2			(1 << MSIZE_P)
-#define MSIZE_4			(2 << MSIZE_P)
-#define MSIZE_8			(3 << MSIZE_P)
-#define MSIZE_16		(4 << MSIZE_P)
-#define MSIZE_32		(5 << MSIZE_P)
-#define FLOW			(7 << FLOW_P)	/* Next Operation */
-#define FLOW_STOP		(0 << FLOW_P)	/* Stop Mode */
-#define FLOW_AUTO		(1 << FLOW_P)	/* Autobuffer Mode */
-#define FLOW_DSCL		(4 << FLOW_P)	/* Descriptor List */
-#define FLOW_DSCA		(5 << FLOW_P)	/* Descriptor Array */
-#define FLOW_DSDL		(6 << FLOW_P)	/* Descriptor On Demand List */
-#define FLOW_DSDA		(7 << FLOW_P)	/* Descriptor On Demand Array */
-#define NDSIZE			(7 << NDSIZE_P)	/* Next Descriptor Set Size */
-#define NDSIZE_1		(0 << NDSIZE_P)
-#define NDSIZE_2		(1 << NDSIZE_P)
-#define NDSIZE_3		(2 << NDSIZE_P)
-#define NDSIZE_4		(3 << NDSIZE_P)
-#define NDSIZE_5		(4 << NDSIZE_P)
-#define NDSIZE_6		(5 << NDSIZE_P)
-#define NDSIZE_7		(6 << NDSIZE_P)
-#define DI_EN_X                 (1 << INT_P)
-#define DI_EN_Y                 (2 << INT_P)
-#define DI_EN_P			(3 << INT_P)
-#define DI_EN			(DI_EN_X)
-#define DI_XCOUNT_EN            (1 << INT_P)    /* xcount expires interrupt */
-#define TRIG			(3 << TRIG_P)	/* Generate Trigger */
-#define TOVEN			(1 << TOVEN_P)
-#define DESCIDCPY		(1 << DESCIDCPY_P)
-#define TWOD			(1 << TWOD_P)
-#define PDRF			(1 << PDRF_P)
-
-#define DMAEN_P			0
-#define WNR_P			1
-#define SYNC_P			2
-#define CADDR_P			3
-#define PSIZE_P			4
-#define MSIZE_P			8
-#define FLOW_P			12
-#define TWAIT_P			15
-#define NDSIZE_P		16
-#define INT_P			20
-#define TRIG_P			22
-#define TOVEN_P			24
-#define DESCIDCPY_P		25
-#define TWOD_P			26
-#define PDRF_P			28
-
-/* DMA_STATUS Masks */
-#define DMA_DONE		(1 << DMA_DONE_P)	/* Work Unit/Row Done */
-#define DMA_ERR			(1 << DMA_ERR_P)	/* Error Interrupt */
-#define DMA_PIRQ		(1 << DMA_PIRQ_P)	/* Peri Intr Request */
-#define DMA_ERRC		(7 << DMA_ERRC_P)	/* Error Cause */
-#define DMA_RUN			(7 << DMA_RUN_P)	/* Run Status */
-#define DMA_PBWIDTH		(3 << DMA_PBWIDTH_P)	/* Peri Bus Width */
-#define DMA_MBWIDTH		(3 << DMA_MBWIDTH_P)	/* Memory Bus Width */
-#define DMA_FIFOFILL		(7 << DMA_FIFOFILL_P)	/* FIFO Fill Status */
-#define DMA_TWAIT		(1 << DMA_TWAIT_P)	/* Trigger Wait Stat */
-
-#define DMA_DONE_P		0
-#define DMA_ERR_P		1
-#define DMA_PIRQ_P		2
-#define DMA_ERRC_P		4
-#define DMA_RUN_P		8
-#define DMA_PBWIDTH_P		12
-#define DMA_MBWIDTH_P		14
-#define DMA_FIFOFILL_P		16
-#define DMA_TWAIT_P		20
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/dma.h b/arch/blackfin/include/asm/mach-common/bits/dma.h
deleted file mode 100644
index ac426ad..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/dma.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * DMA Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_DMA__
-#define __BFIN_PERIPHERAL_DMA__
-
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
-#define DMAEN			0x0001	/* DMA Channel Enable */
-#define WNR			0x0002	/* Channel Direction (W/R*) */
-#define WDSIZE_8		0x0000	/* Transfer Word Size = 8 */
-
-#ifdef CONFIG_BF60x
-
-#define PSIZE_8			0x00000000	/* Transfer Word Size = 16 */
-#define PSIZE_16		0x00000010	/* Transfer Word Size = 16 */
-#define PSIZE_32		0x00000020	/* Transfer Word Size = 32 */
-#define PSIZE_64		0x00000030	/* Transfer Word Size = 32 */
-#define WDSIZE_16		0x00000100	/* Transfer Word Size = 16 */
-#define WDSIZE_32		0x00000200	/* Transfer Word Size = 32 */
-#define WDSIZE_64		0x00000300	/* Transfer Word Size = 32 */
-#define WDSIZE_128		0x00000400	/* Transfer Word Size = 32 */
-#define WDSIZE_256		0x00000500	/* Transfer Word Size = 32 */
-#define DMA2D			0x04000000	/* DMA Mode (2D/1D*) */
-#define RESTART			0x00000004	/* DMA Buffer Clear SYNC */
-#define DI_EN_X			0x00100000	/* Data Int Enable in X count */
-#define DI_EN_Y			0x00200000	/* Data Int Enable in Y count */
-#define DI_EN_P			0x00300000	/* Data Int Enable in Peri */
-#define DI_EN			DI_EN_X		/* Data Int Enable */
-#define NDSIZE_0		0x00000000	/* Next Desc Size = 0 */
-#define NDSIZE_1		0x00010000	/* Next Desc Size = 1 */
-#define NDSIZE_2		0x00020000	/* Next Desc Size = 2 */
-#define NDSIZE_3		0x00030000	/* Next Desc Size = 3 */
-#define NDSIZE_4		0x00040000	/* Next Desc Size = 4 */
-#define NDSIZE_5		0x00050000	/* Next Desc Size = 5 */
-#define NDSIZE_6		0x00060000	/* Next Desc Size = 6 */
-#define NDSIZE			0x00070000	/* Next Desc Size */
-#define NDSIZE_OFFSET		16		/* Next Desc Size Offset */
-#define DMAFLOW_LIST		0x00004000	/* Desc List Mode */
-#define DMAFLOW_ARRAY		0x00005000	/* Desc Array Mode */
-#define DMAFLOW_LIST_DEMAND	0x00006000	/* Desc Demand List Mode */
-#define DMAFLOW_ARRAY_DEMAND	0x00007000	/* Desc Demand Array Mode */
-#define DMA_RUN_DFETCH		0x00000100	/* DMA Channel Run (DFETCH) */
-#define DMA_RUN			0x00000200	/* DMA Channel Run */
-#define DMA_RUN_WAIT_TRIG	0x00000300	/* DMA Channel Run (WAIT TRIG)*/
-#define DMA_RUN_WAIT_ACK	0x00000400	/* DMA Channel Run (WAIT ACK) */
-
-#else
-
-#define WDSIZE_16		0x0004	/* Transfer Word Size = 16 */
-#define WDSIZE_32		0x0008	/* Transfer Word Size = 32 */
-#define PSIZE_16		WDSIZE_16
-#define PSIZE_32		WDSIZE_32
-#define DMA2D			0x0010	/* DMA Mode (2D/1D*) */
-#define RESTART			0x0020	/* DMA Buffer Clear */
-#define DI_SEL			0x0040	/* Data Interrupt Timing Select */
-#define DI_EN			0x0080	/* Data Interrupt Enable */
-#define NDSIZE			0x0F00	/* Next Descriptor bitmask */
-#define NDSIZE_0		0x0000	/* Next Descriptor Size = 0 */
-#define NDSIZE_1		0x0100	/* Next Descriptor Size = 1 */
-#define NDSIZE_2		0x0200	/* Next Descriptor Size = 2 */
-#define NDSIZE_3		0x0300	/* Next Descriptor Size = 3 */
-#define NDSIZE_4		0x0400	/* Next Descriptor Size = 4 */
-#define NDSIZE_5		0x0500	/* Next Descriptor Size = 5 */
-#define NDSIZE_6		0x0600	/* Next Descriptor Size = 6 */
-#define NDSIZE_7		0x0700	/* Next Descriptor Size = 7 */
-#define NDSIZE_8		0x0800	/* Next Descriptor Size = 8 */
-#define NDSIZE_9		0x0900	/* Next Descriptor Size = 9 */
-#define FLOW_ARRAY		0x4000	/* Descriptor Array Mode */
-#define FLOW_SMALL		0x6000	/* Small Model Descriptor List Mode */
-#define FLOW_LARGE		0x7000	/* Large Model Descriptor List Mode */
-
-#define DMAEN_P			0	/* Channel Enable */
-#define WNR_P			1	/* Channel Direction (W/R*) */
-#define WDSIZE_P		2	/* Transfer Word Size */
-#define DMA2D_P			4	/* 2D/1D* Mode */
-#define RESTART_P		5	/* Restart */
-#define DI_SEL_P		6	/* Data Interrupt Select */
-#define DI_EN_P			7	/* Data Interrupt Enable */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
-#define DMA_DONE		0x0001	/* DMA Completion Interrupt Status */
-#define DMA_ERR			0x0002	/* DMA Error Interrupt Status */
-#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator */
-#define DMA_RUN			0x0008	/* DMA Channel Running Indicator */
-
-#endif
-#define DMAFLOW			0x7000	/* Flow Control */
-#define FLOW_STOP		0x0000	/* Stop Mode */
-#define FLOW_AUTO		0x1000	/* Autobuffer Mode */
-
-#define DMA_DONE_P		0	/* DMA Done Indicator */
-#define DMA_ERR_P		1	/* DMA Error Indicator */
-#define DFETCH_P		2	/* Descriptor Fetch Indicator */
-#define DMA_RUN_P		3	/* DMA Running Indicator */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE			0x0040	/* DMA Channel Type (Mem/Peri) */
-#define CTYPE_P			6	/* DMA Channel Type BIT POSITION */
-#define PMAP			0xF000	/* Peripheral Mapped To This Channel */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ebiu.h b/arch/blackfin/include/asm/mach-common/bits/ebiu.h
deleted file mode 100644
index 7c0c569..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/ebiu.h
+++ /dev/null
@@ -1,440 +0,0 @@
-/*
- * EBIU Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_EBIU__
-#define __BFIN_PERIPHERAL_EBIU__
-
-/* EBIU_AMGCTL Masks */
-#define AMCKEN		0x0001		/* Enable CLKOUT */
-#define AMBEN_NONE	0x0000		/* All Banks Disabled */
-#define AMBEN_B0	0x0002		/* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1	0x0004		/* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2	0x0006		/* Enable Asynchronous Memory Banks 0,/ 1, and 2 */
-#define AMBEN_ALL	0x0008		/* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define B0_PEN		0x0010		/* Enable 16-bit packing Bank 0 */
-#define B1_PEN		0x0020		/* Enable 16-bit packing Bank 1 */
-#define B2_PEN		0x0040		/* Enable 16-bit packing Bank 2 */
-#define B3_PEN		0x0080		/* Enable 16-bit packing Bank 3 */
-#define CDPRIO		0x0100		/* Core has priority over DMA for external accesses */
-
-/* EBIU_AMGCTL Bit Positions */
-#define AMCKEN_P	0x00000000	/* Enable CLKOUT */
-#define AMBEN_P0	0x00000001	/* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1	0x00000002	/* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
-#define AMBEN_P2	0x00000003	/* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-#define B0_PEN_P	0x00000004	/* Enable 16-bit packing Bank 0 */
-#define B1_PEN_P	0x00000005	/* Enable 16-bit packing Bank 1 */
-#define B2_PEN_P	0x00000006	/* Enable 16-bit packing Bank 2 */
-#define B3_PEN_P	0x00000007	/* Enable 16-bit packing Bank 3 */
-#define CDPRIO_P	0x00000008	/* Core has priority over DMA for external accesses */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN		0x00000001	/* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL	0x00000002	/* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1		0x00000004	/* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2		0x00000008	/* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3		0x0000000C	/* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4		0x00000000	/* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1		0x00000010	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2		0x00000020	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3		0x00000030	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4		0x00000000	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1		0x00000040	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2		0x00000080	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3		0x000000C0	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0		0x00000000	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1		0x00000100	/* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2		0x00000200	/* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3		0x00000300	/* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4		0x00000400	/* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5		0x00000500	/* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6		0x00000600	/* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7		0x00000700	/* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8		0x00000800	/* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9		0x00000900	/* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10	0x00000A00	/* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11	0x00000B00	/* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12	0x00000C00	/* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13	0x00000D00	/* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14	0x00000E00	/* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15	0x00000F00	/* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1		0x00001000	/* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2		0x00002000	/* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3		0x00003000	/* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4		0x00004000	/* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5		0x00005000	/* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6		0x00006000	/* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7		0x00007000	/* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8		0x00008000	/* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9		0x00009000	/* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10	0x0000A000	/* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11	0x0000B000	/* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12	0x0000C000	/* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13	0x0000D000	/* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14	0x0000E000	/* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15	0x0000F000	/* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN		0x00010000	/* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL	0x00020000	/* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1		0x00040000	/* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2		0x00080000	/* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3		0x000C0000	/* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4		0x00000000	/* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1		0x00100000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2		0x00200000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3		0x00300000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4		0x00000000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1		0x00400000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2		0x00800000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3		0x00C00000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0		0x00000000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1		0x01000000	/* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2		0x02000000	/* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3		0x03000000	/* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4		0x04000000	/* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5		0x05000000	/* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6		0x06000000	/* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7		0x07000000	/* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8		0x08000000	/* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9		0x09000000	/* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10	0x0A000000	/* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11	0x0B000000	/* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12	0x0C000000	/* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13	0x0D000000	/* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14	0x0E000000	/* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15	0x0F000000	/* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1		0x10000000	/* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2		0x20000000	/* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3		0x30000000	/* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4		0x40000000	/* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5		0x50000000	/* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6		0x60000000	/* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7		0x70000000	/* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8		0x80000000	/* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9		0x90000000	/* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10	0xA0000000	/* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11	0xB0000000	/* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12	0xC0000000	/* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13	0xD0000000	/* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14	0xE0000000	/* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15	0xF0000000	/* Bank 1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN		0x00000001	/* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL	0x00000002	/* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1		0x00000004	/* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2		0x00000008	/* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3		0x0000000C	/* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4		0x00000000	/* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1		0x00000010	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2		0x00000020	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3		0x00000030	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4		0x00000000	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1		0x00000040	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2		0x00000080	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3		0x000000C0	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0		0x00000000	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1		0x00000100	/* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2		0x00000200	/* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3		0x00000300	/* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4		0x00000400	/* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5		0x00000500	/* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6		0x00000600	/* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7		0x00000700	/* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8		0x00000800	/* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9		0x00000900	/* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10	0x00000A00	/* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11	0x00000B00	/* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12	0x00000C00	/* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13	0x00000D00	/* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14	0x00000E00	/* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15	0x00000F00	/* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1		0x00001000	/* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2		0x00002000	/* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3		0x00003000	/* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4		0x00004000	/* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5		0x00005000	/* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6		0x00006000	/* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7		0x00007000	/* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8		0x00008000	/* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9		0x00009000	/* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10	0x0000A000	/* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11	0x0000B000	/* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12	0x0000C000	/* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13	0x0000D000	/* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14	0x0000E000	/* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15	0x0000F000	/* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN		0x00010000	/* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL	0x00020000	/* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1		0x00040000	/* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2		0x00080000	/* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3		0x000C0000	/* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4		0x00000000	/* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1		0x00100000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2		0x00200000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3		0x00300000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4		0x00000000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1		0x00400000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2		0x00800000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3		0x00C00000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0		0x00000000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1		0x01000000	/* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2		0x02000000	/* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3		0x03000000	/* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4		0x04000000	/* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5		0x05000000	/* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6		0x06000000	/* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7		0x07000000	/* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8		0x08000000	/* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9		0x09000000	/* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10	0x0A000000	/* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11	0x0B000000	/* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12	0x0C000000	/* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13	0x0D000000	/* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14	0x0E000000	/* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15	0x0F000000	/* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1		0x10000000	/* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2		0x20000000	/* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3		0x30000000	/* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4		0x40000000	/* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5		0x50000000	/* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6		0x60000000	/* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7		0x70000000	/* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8		0x80000000	/* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9		0x90000000	/* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10	0xA0000000	/* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11	0xB0000000	/* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12	0xC0000000	/* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13	0xD0000000	/* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14	0xE0000000	/* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15	0xF0000000	/* Bank 3 Write Access Time = 15 cycles */
-
-/* Only available on newer parts */
-#ifdef EBIU_MODE
-
-/* EBIU_MBSCTL Bit Positions */
-#define AMSB0CTL_P	0
-#define AMSB1CTL_P	2
-#define AMSB2CTL_P	4
-#define AMSB3CTL_P	6
-
-/* EBIU_MBSCTL Masks */
-#define AMSB0CTL_MASK	(0x3 << AMSB0CTL_P)	/* Async Memory Bank 0 Control Modes */
-#define AMSB0CTL_NONE	(0x0 << AMSB0CTL_P)	/* Control Mode - 00 - No logic */
-#define AMSB0CTL_ARE	(0x1 << AMSB0CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */
-#define AMSB0CTL_AOE	(0x2 << AMSB0CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */
-#define AMSB0CTL_AWE	(0x3 << AMSB0CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */
-#define AMSB1CTL_MASK	(0x3 << AMSB1CTL_P)	/* Async Memory Bank 1 Control Modes */
-#define AMSB1CTL_NONE	(0x0 << AMSB1CTL_P)	/* Control Mode - 00 - No logic */
-#define AMSB1CTL_ARE	(0x1 << AMSB1CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */
-#define AMSB1CTL_AOE	(0x2 << AMSB1CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */
-#define AMSB1CTL_AWE	(0x3 << AMSB1CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */
-#define AMSB2CTL_MASK	(0x3 << AMSB2CTL_P)	/* Async Memory Bank 2 Control Modes */
-#define AMSB2CTL_NONE	(0x0 << AMSB2CTL_P)	/* Control Mode - 00 - No logic */
-#define AMSB2CTL_ARE	(0x1 << AMSB2CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */
-#define AMSB2CTL_AOE	(0x2 << AMSB2CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */
-#define AMSB2CTL_AWE	(0x3 << AMSB2CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */
-#define AMSB3CTL_MASK	(0x3 << AMSB3CTL_P)	/* Async Memory Bank 3 Control Modes */
-#define AMSB3CTL_NONE	(0x0 << AMSB3CTL_P)	/* Control Mode - 00 - No logic */
-#define AMSB3CTL_ARE	(0x1 << AMSB3CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */
-#define AMSB3CTL_AOE	(0x2 << AMSB3CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */
-#define AMSB3CTL_AWE	(0x3 << AMSB3CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */
-
-/* EBIU_MODE Bit Positions */
-#define B0MODE_P	0
-#define B1MODE_P	2
-#define B2MODE_P	4
-#define B3MODE_P	6
-
-/* EBIU_MODE Masks */
-#define B0MODE_MASK	(0x3 << B0MODE_P)	/* Async Memory Bank 0 Access Mode */
-#define B0MODE_ASYNC	(0x0 << B0MODE_P)	/* Access Mode - 00 - Asynchronous Mode */
-#define B0MODE_FLASH	(0x1 << B0MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */
-#define B0MODE_PAGE	(0x2 << B0MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */
-#define B0MODE_BURST	(0x3 << B0MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */
-#define B1MODE_MASK	(0x3 << B1MODE_P)	/* Async Memory Bank 1 Access Mode */
-#define B1MODE_ASYNC	(0x0 << B1MODE_P)	/* Access Mode - 00 - Asynchronous Mode */
-#define B1MODE_FLASH	(0x1 << B1MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */
-#define B1MODE_PAGE	(0x2 << B1MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */
-#define B1MODE_BURST	(0x3 << B1MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */
-#define B2MODE_MASK	(0x3 << B2MODE_P)	/* Async Memory Bank 2 Access Mode */
-#define B2MODE_ASYNC	(0x0 << B2MODE_P)	/* Access Mode - 00 - Asynchronous Mode */
-#define B2MODE_FLASH	(0x1 << B2MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */
-#define B2MODE_PAGE	(0x2 << B2MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */
-#define B2MODE_BURST	(0x3 << B2MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */
-#define B3MODE_MASK	(0x3 << B3MODE_P)	/* Async Memory Bank 3 Access Mode */
-#define B3MODE_ASYNC	(0x0 << B3MODE_P)	/* Access Mode - 00 - Asynchronous Mode */
-#define B3MODE_FLASH	(0x1 << B3MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */
-#define B3MODE_PAGE	(0x2 << B3MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */
-#define B3MODE_BURST	(0x3 << B3MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */
-
-/* EBIU_FCTL Bit Positions */
-#define TESTSETLOCK_P	0
-#define BCLK_P		1
-#define PGWS_P		3
-#define PGSZ_P		6
-#define RDDL_P		7
-
-/* EBIU_FCTL Masks */
-#define TESTSETLOCK	(0x1 << TESTSETLOCK_P)	/* Test set lock */
-#define BCLK_MASK	(0x3 << BCLK_P)		/* Burst clock frequency */
-#define BCLK_2		(0x1 << BCLK_P)		/* Burst clock frequency - SCLK/2 */
-#define BCLK_3		(0x2 << BCLK_P)		/* Burst clock frequency - SCLK/3 */
-#define BCLK_4		(0x3 << BCLK_P)		/* Burst clock frequency - SCLK/4 */
-#define PGWS_MASK	(0x7 << PGWS_P)		/* Page wait states */
-#define PGWS_0		(0x0 << PGWS_P)		/* Page wait states - 0 cycles */
-#define PGWS_1		(0x1 << PGWS_P)		/* Page wait states - 1 cycles */
-#define PGWS_2		(0x2 << PGWS_P)		/* Page wait states - 2 cycles */
-#define PGWS_3		(0x3 << PGWS_P)		/* Page wait states - 3 cycles */
-#define PGWS_4		(0x4 << PGWS_P)		/* Page wait states - 4 cycles */
-#define PGSZ		(0x1 << PGSZ_P)		/* Page size */
-#define PGSZ_4		(0x0 << PGSZ_P)		/* Page size - 4 words */
-#define PGSZ_8		(0x1 << PGSZ_P)		/* Page size - 8 words */
-#define RDDL		(0x38 << RDDL_P)	/* Read data delay */
-
-/* EBIU_ARBSTAT Masks */
-#define ARBSTAT		0x00000001	/* Arbitration status */
-#define BGSTAT		0x00000002	/* External Bus grant status */
-
-#endif /* EBIU_MODE */
-
-/* Only available on SDRAM based-parts */
-#ifdef EBIU_SDGCTL
-
-/* EBIU_SDGCTL Masks */
-#define SCTLE		0x00000001	/* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define SCK1E		0x00000002	/* Enable CLKOUT, /SCLK1 */
-#define CL_2		0x00000008	/* SDRAM CAS latency = 2 cycles */
-#define CL_3		0x0000000C	/* SDRAM CAS latency = 3 cycles */
-#define PASR_ALL	0x00000000	/* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1	0x00000010	/* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0		0x00000020	/* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1		0x00000040	/* SDRAM tRAS = 1 cycle */
-#define TRAS_2		0x00000080	/* SDRAM tRAS = 2 cycles */
-#define TRAS_3		0x000000C0	/* SDRAM tRAS = 3 cycles */
-#define TRAS_4		0x00000100	/* SDRAM tRAS = 4 cycles */
-#define TRAS_5		0x00000140	/* SDRAM tRAS = 5 cycles */
-#define TRAS_6		0x00000180	/* SDRAM tRAS = 6 cycles */
-#define TRAS_7		0x000001C0	/* SDRAM tRAS = 7 cycles */
-#define TRAS_8		0x00000200	/* SDRAM tRAS = 8 cycles */
-#define TRAS_9		0x00000240	/* SDRAM tRAS = 9 cycles */
-#define TRAS_10		0x00000280	/* SDRAM tRAS = 10 cycles */
-#define TRAS_11		0x000002C0	/* SDRAM tRAS = 11 cycles */
-#define TRAS_12		0x00000300	/* SDRAM tRAS = 12 cycles */
-#define TRAS_13		0x00000340	/* SDRAM tRAS = 13 cycles */
-#define TRAS_14		0x00000380	/* SDRAM tRAS = 14 cycles */
-#define TRAS_15		0x000003C0	/* SDRAM tRAS = 15 cycles */
-#define TRP_1		0x00000800	/* SDRAM tRP = 1 cycle */
-#define TRP_2		0x00001000	/* SDRAM tRP = 2 cycles */
-#define TRP_3		0x00001800	/* SDRAM tRP = 3 cycles */
-#define TRP_4		0x00002000	/* SDRAM tRP = 4 cycles */
-#define TRP_5		0x00002800	/* SDRAM tRP = 5 cycles */
-#define TRP_6		0x00003000	/* SDRAM tRP = 6 cycles */
-#define TRP_7		0x00003800	/* SDRAM tRP = 7 cycles */
-#define TRCD_1		0x00008000	/* SDRAM tRCD = 1 cycle */
-#define TRCD_2		0x00010000	/* SDRAM tRCD = 2 cycles */
-#define TRCD_3		0x00018000	/* SDRAM tRCD = 3 cycles */
-#define TRCD_4		0x00020000	/* SDRAM tRCD = 4 cycles */
-#define TRCD_5		0x00028000	/* SDRAM tRCD = 5 cycles */
-#define TRCD_6		0x00030000	/* SDRAM tRCD = 6 cycles */
-#define TRCD_7		0x00038000	/* SDRAM tRCD = 7 cycles */
-#define TWR_1		0x00080000	/* SDRAM tWR = 1 cycle */
-#define TWR_2		0x00100000	/* SDRAM tWR = 2 cycles */
-#define TWR_3		0x00180000	/* SDRAM tWR = 3 cycles */
-#define PUPSD		0x00200000	/* Power-up start delay */
-#define PSM		0x00400000	/* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS		0x00800000	/* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS		0x01000000	/* Start SDRAM self-refresh mode */
-#define EBUFE		0x02000000	/* Enable external buffering timing */
-#define FBBRW		0x04000000	/* Fast back-to-back read write enable */
-#define EMREN		0x10000000	/* Extended mode register enable */
-#define TCSR		0x20000000	/* Temp compensated self refresh value 85 deg C */
-#define CDDBG		0x40000000	/* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE		0x0001		/* Enable SDRAM External Bank */
-#define EBSZ_16		0x0000		/* SDRAM External Bank Size = 16MB */
-#define EBSZ_32		0x0002		/* SDRAM External Bank Size = 32MB */
-#define EBSZ_64		0x0004		/* SDRAM External Bank Size = 64MB */
-#define EBSZ_128	0x0006		/* SDRAM External Bank Size = 128MB */
-#define EBSZ_256	0x0008		/* SDRAM External Bank Size = 256MB */
-#define EBSZ_512	0x000A		/* SDRAM External Bank Size = 512MB */
-#define EBCAW_8		0x0000		/* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9		0x0010		/* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10	0x0020		/* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11	0x0030		/* SDRAM External Bank Column Address Width = 11 Bits */
-
-#ifdef __ADSPBF561__
-
-#define EB0E		(EBE<<0)	/* Enable SDRAM external bank 0 */
-#define EB0SZ_16	(EBSZ_16<<0)	/* SDRAM external bank size = 16MB */
-#define EB0SZ_32	(EBSZ_32<<0)	/* SDRAM external bank size = 32MB */
-#define EB0SZ_64	(EBSZ_64<<0)	/* SDRAM external bank size = 64MB */
-#define EB0SZ_128	(EBSZ_128<<0)	/* SDRAM external bank size = 128MB */
-#define EB0CAW_8	(EBCAW_8<<0)	/* SDRAM external bank column address width = 8 bits */
-#define EB0CAW_9	(EBCAW_9<<0)	/* SDRAM external bank column address width = 9 bits */
-#define EB0CAW_10	(EBCAW_10<<0)	/* SDRAM external bank column address width = 9 bits */
-#define EB0CAW_11	(EBCAW_11<<0)	/* SDRAM external bank column address width = 9 bits */
-
-#define EB1E		(EBE<<8)	/* Enable SDRAM external bank 0 */
-#define EB1SZ_16	(EBSZ_16<<8)	/* SDRAM external bank size = 16MB */
-#define EB1SZ_32	(EBSZ_32<<8)	/* SDRAM external bank size = 32MB */
-#define EB1SZ_64	(EBSZ_64<<8)	/* SDRAM external bank size = 64MB */
-#define EB1SZ_128	(EBSZ_128<<8)	/* SDRAM external bank size = 128MB */
-#define EB1CAW_8	(EBCAW_8<<8)	/* SDRAM external bank column address width = 8 bits */
-#define EB1CAW_9	(EBCAW_9<<8)	/* SDRAM external bank column address width = 9 bits */
-#define EB1CAW_10	(EBCAW_10<<8)	/* SDRAM external bank column address width = 9 bits */
-#define EB1CAW_11	(EBCAW_11<<8)	/* SDRAM external bank column address width = 9 bits */
-
-#define EB2E		(EBE<<16)	/* Enable SDRAM external bank 0 */
-#define EB2SZ_16	(EBSZ_16<<16)	/* SDRAM external bank size = 16MB */
-#define EB2SZ_32	(EBSZ_32<<16)	/* SDRAM external bank size = 32MB */
-#define EB2SZ_64	(EBSZ_64<<16)	/* SDRAM external bank size = 64MB */
-#define EB2SZ_128	(EBSZ_128<<16)	/* SDRAM external bank size = 128MB */
-#define EB2CAW_8	(EBCAW_8<<16)	/* SDRAM external bank column address width = 8 bits */
-#define EB2CAW_9	(EBCAW_9<<16)	/* SDRAM external bank column address width = 9 bits */
-#define EB2CAW_10	(EBCAW_10<<16)	/* SDRAM external bank column address width = 9 bits */
-#define EB2CAW_11	(EBCAW_11<<16)	/* SDRAM external bank column address width = 9 bits */
-
-#define EB3E		(EBE<<24)	/* Enable SDRAM external bank 0 */
-#define EB3SZ_16	(EBSZ_16<<24)	/* SDRAM external bank size = 16MB */
-#define EB3SZ_32	(EBSZ_32<<24)	/* SDRAM external bank size = 32MB */
-#define EB3SZ_64	(EBSZ_64<<24)	/* SDRAM external bank size = 64MB */
-#define EB3SZ_128	(EBSZ_128<<24)	/* SDRAM external bank size = 128MB */
-#define EB3CAW_8	(EBCAW_8<<24)	/* SDRAM external bank column address width = 8 bits */
-#define EB3CAW_9	(EBCAW_9<<24)	/* SDRAM external bank column address width = 9 bits */
-#define EB3CAW_10	(EBCAW_10<<24)	/* SDRAM external bank column address width = 9 bits */
-#define EB3CAW_11	(EBCAW_11<<24)	/* SDRAM external bank column address width = 9 bits */
-
-#endif /* BF561 */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI		0x0001		/* SDRAM controller is idle */
-#define SDSRA		0x0002		/* SDRAM self refresh is active */
-#define SDPUA		0x0004		/* SDRAM power up active */
-#define SDRS		0x0008		/* SDRAM is in reset state */
-#define SDEASE		0x0010		/* SDRAM EAB sticky error status - W1C */
-#define BGSTAT		0x0020		/* Bus granted */
-
-/* Only available on DDR based-parts */
-#else
-
-/* EBIU_ERRMST Masks */
-#define DEB0_ERROR	0x0001		/* DEB0 access on reserved memory */
-#define DEB1_ERROR	0x0002		/* DEB1 access on reserved memory */
-#define DEB2_ERROR	0x0004		/* DEB2 (USB) access on reserved memory */
-#define CORE_ERROR	0x0008		/* Core access on reserved memory */
-#define DEB0_MERROR	0x0010		/* DEB0 access on reserved memory and DEB0_ERROR is set */
-#define DEB1_MERROR	0x0020		/* DEB1 access on reserved memory and DEB1_ERROR is set */
-#define DEB2_MERROR	0x0040		/* DEB2 access on reserved memory and DEB2_ERROR is set */
-#define CORE_MERROR	0x0080		/* Core access on reserved memory and CORE_ERROR is set */
-
-/* EBIU_RSTCTL Masks */
-#define DDR_SRESET	0x0001		/* Reset Control to DDR Controller */
-#define SRREQ		0x0008		/* Self Refresh Request */
-#define SRACK		0x0010		/* Self Refresh Request Acknowledgement */
-#define MDDRENABLE	0x0020		/* Mobile DDR Enable */
-
-#endif /* EBIU_SDGCTL */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/emac.h b/arch/blackfin/include/asm/mach-common/bits/emac.h
deleted file mode 100644
index 4c9bc9d..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/emac.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Ethernet MAC Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_EMAC__
-#define __BFIN_PERIPHERAL_EMAC__
-
-/* EMAC_OPMODE Masks */
-#define	RE		0x00000001	/* Receiver Enable */
-#define	ASTP		0x00000002	/* Enable Automatic Pad Stripping On RX Frames */
-#define	HU		0x00000010	/* Hash Filter Unicast Address */
-#define	HM		0x00000020	/* Hash Filter Multicast Address */
-#define	PAM		0x00000040	/* Pass-All-Multicast Mode Enable */
-#define	PR		0x00000080	/* Promiscuous Mode Enable */
-#define	IFE		0x00000100	/* Inverse Filtering Enable */
-#define	DBF		0x00000200	/* Disable Broadcast Frame Reception */
-#define	PBF		0x00000400	/* Pass Bad Frames Enable */
-#define	PSF		0x00000800	/* Pass Short Frames Enable */
-#define	RAF		0x00001000	/* Receive-All Mode */
-#define	TE		0x00010000	/* Transmitter Enable */
-#define	DTXPAD		0x00020000	/* Disable Automatic TX Padding */
-#define	DTXCRC		0x00040000	/* Disable Automatic TX CRC Generation */
-#define	DC		0x00080000	/* Deferral Check */
-#define	BOLMT		0x00300000	/* Back-Off Limit */
-#define	BOLMT_10	0x00000000	/* 10-bit range */
-#define	BOLMT_8		0x00100000	/* 8-bit range */
-#define	BOLMT_4		0x00200000	/* 4-bit range */
-#define	BOLMT_1		0x00300000	/* 1-bit range */
-#define	DRTY		0x00400000	/* Disable TX Retry On Collision */
-#define	LCTRE		0x00800000	/* Enable TX Retry On Late Collision */
-#define	RMII		0x01000000	/* RMII/MII* Mode */
-#define	RMII_10		0x02000000	/* Speed Select for RMII Port (10MBit/100MBit*) */
-#define	FDMODE		0x04000000	/* Duplex Mode Enable (Full/Half*) */
-#define	LB		0x08000000	/* Internal Loopback Enable */
-#define	DRO		0x10000000	/* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-#define	STABUSY		0x00000001	/* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define	STAOP		0x00000002	/* Station Management Operation Code (Write/Read*) */
-#define	STADISPRE	0x00000004	/* Disable Preamble Generation */
-#define	STAIE		0x00000008	/* Station Mgt. Transfer Done Interrupt Enable */
-#define	REGAD		0x000007C0	/* STA Register Address */
-#define	PHYAD		0x0000F800	/* PHY Device Address */
-
-#define	SET_REGAD(x)	(((x) & 0x1F) <<  6)	/* Set STA Register Address */
-#define	SET_PHYAD(x)	(((x) & 0x1F) << 11)	/* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-#define	STADATA		0x0000FFFF	/* Station Management Data */
-
-/* EMAC_FLC Masks */
-#define	FLCBUSY		0x00000001	/* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define	FLCE		0x00000002	/* Flow Control Enable */
-#define	PCF		0x00000004	/* Pass Control Frames */
-#define	BKPRSEN		0x00000008	/* Enable Backpressure */
-#define	FLCPAUSE	0xFFFF0000	/* Pause Time */
-
-#define	SET_FLCPAUSE(x)	(((x) & 0xFFFF) << 16)	/* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-#define	CAPWKFRM	0x00000001	/* Capture Wake-Up Frames */
-#define	MPKE		0x00000002	/* Magic Packet Enable */
-#define	RWKE		0x00000004	/* Remote Wake-Up Frame Enable */
-#define	GUWKE		0x00000008	/* Global Unicast Wake Enable */
-#define	MPKS		0x00000020	/* Magic Packet Received Status */
-#define	RWKS		0x00000F00	/* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-#define	WF0_E		0x00000001	/* Enable Wake-Up Filter 0 */
-#define	WF0_T		0x00000008	/* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define	WF1_E		0x00000100	/* Enable Wake-Up Filter 1 */
-#define	WF1_T		0x00000800	/* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define	WF2_E		0x00010000	/* Enable Wake-Up Filter 2 */
-#define	WF2_T		0x00080000	/* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define	WF3_E		0x01000000	/* Enable Wake-Up Filter 3 */
-#define	WF3_T		0x08000000	/* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-#define	WF0_OFF		0x000000FF	/* Wake-Up Filter 0 Pattern Offset */
-#define	WF1_OFF		0x0000FF00	/* Wake-Up Filter 1 Pattern Offset */
-#define	WF2_OFF		0x00FF0000	/* Wake-Up Filter 2 Pattern Offset */
-#define	WF3_OFF		0xFF000000	/* Wake-Up Filter 3 Pattern Offset */
-
-#define	SET_WF0_OFF(x)	(((x) & 0xFF) <<  0)	/* Set Wake-Up Filter 0 Byte Offset */
-#define	SET_WF1_OFF(x)	(((x) & 0xFF) <<  8)	/* Set Wake-Up Filter 1 Byte Offset */
-#define	SET_WF2_OFF(x)	(((x) & 0xFF) << 16)	/* Set Wake-Up Filter 2 Byte Offset */
-#define	SET_WF3_OFF(x)	(((x) & 0xFF) << 24)	/* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define	SET_WF_OFFS(x0,x1,x2,x3)	(SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-#define	WF0_CRC		0x0000FFFF	/* Wake-Up Filter 0 Pattern CRC */
-#define	WF1_CRC		0xFFFF0000	/* Wake-Up Filter 1 Pattern CRC */
-
-#define	SET_WF0_CRC(x)	(((x) & 0xFFFF) << 0)	/* Set Wake-Up Filter 0 Target CRC */
-#define	SET_WF1_CRC(x)	(((x) & 0xFFFF) << 16)	/* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-#define	WF2_CRC		0x0000FFFF	/* Wake-Up Filter 2 Pattern CRC */
-#define	WF3_CRC		0xFFFF0000	/* Wake-Up Filter 3 Pattern CRC */
-
-#define	SET_WF2_CRC(x)	(((x) & 0xFFFF) << 0)	/* Set Wake-Up Filter 2 Target CRC */
-#define	SET_WF3_CRC(x)	(((x) & 0xFFFF) << 16)	/* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-#define	PHYIE		0x00000001	/* PHY_INT Interrupt Enable */
-#define	RXDWA		0x00000002	/* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define	RXCKS		0x00000004	/* Enable RX Frame TCP/UDP Checksum Computation */
-#define	MDCDIV		0x00003F00	/* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define	SET_MDCDIV(x)	(((x) & 0x3F) << 8)	/* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-#define	PHYINT		0x00000001	/* PHY_INT Interrupt Status */
-#define	MMCINT		0x00000002	/* MMC Counter Interrupt Status */
-#define	RXFSINT		0x00000004	/* RX Frame-Status Interrupt Status */
-#define	TXFSINT		0x00000008	/* TX Frame-Status Interrupt Status */
-#define	WAKEDET		0x00000010	/* Wake-Up Detected Status */
-#define	RXDMAERR	0x00000020	/* RX DMA Direction Error Status */
-#define	TXDMAERR	0x00000040	/* TX DMA Direction Error Status */
-#define	STMDONE		0x00000080	/* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-#define	RX_FRLEN	0x000007FF	/* Frame Length In Bytes */
-#define	RX_COMP		0x00001000	/* RX Frame Complete */
-#define	RX_OK		0x00002000	/* RX Frame Received With No Errors */
-#define	RX_LONG		0x00004000	/* RX Frame Too Long Error */
-#define	RX_ALIGN	0x00008000	/* RX Frame Alignment Error */
-#define	RX_CRC		0x00010000	/* RX Frame CRC Error */
-#define	RX_LEN		0x00020000	/* RX Frame Length Error */
-#define	RX_FRAG		0x00040000	/* RX Frame Fragment Error */
-#define	RX_ADDR		0x00080000	/* RX Frame Address Filter Failed Error */
-#define	RX_DMAO		0x00100000	/* RX Frame DMA Overrun Error */
-#define	RX_PHY		0x00200000	/* RX Frame PHY Error */
-#define	RX_LATE		0x00400000	/* RX Frame Late Collision Error */
-#define	RX_RANGE	0x00800000	/* RX Frame Length Field Out of Range Error */
-#define	RX_MULTI	0x01000000	/* RX Multicast Frame Indicator */
-#define	RX_BROAD	0x02000000	/* RX Broadcast Frame Indicator */
-#define	RX_CTL		0x04000000	/* RX Control Frame Indicator */
-#define	RX_UCTL		0x08000000	/* Unsupported RX Control Frame Indicator */
-#define	RX_TYPE		0x10000000	/* RX Typed Frame Indicator */
-#define	RX_VLAN1	0x20000000	/* RX VLAN1 Frame Indicator */
-#define	RX_VLAN2	0x40000000	/* RX VLAN2 Frame Indicator */
-#define	RX_ACCEPT	0x80000000	/* RX Frame Accepted Indicator */
-
-/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-#define	TX_COMP		0x00000001	/* TX Frame Complete */
-#define	TX_OK		0x00000002	/* TX Frame Sent With No Errors */
-#define	TX_ECOLL	0x00000004	/* TX Frame Excessive Collision Error */
-#define	TX_LATE		0x00000008	/* TX Frame Late Collision Error */
-#define	TX_DMAU		0x00000010	/* TX Frame DMA Underrun Error (STAT) */
-#define	TX_MACE		0x00000010	/* Internal MAC Error Detected (STKY and IRQE) */
-#define	TX_EDEFER	0x00000020	/* TX Frame Excessive Deferral Error */
-#define	TX_BROAD	0x00000040	/* TX Broadcast Frame Indicator */
-#define	TX_MULTI	0x00000080	/* TX Multicast Frame Indicator */
-#define	TX_CCNT		0x00000F00	/* TX Frame Collision Count */
-#define	TX_DEFER	0x00001000	/* TX Frame Deferred Indicator */
-#define	TX_CRS		0x00002000	/* TX Frame Carrier Sense Not Asserted Error */
-#define	TX_LOSS		0x00004000	/* TX Frame Carrier Lost During TX Error */
-#define	TX_RETRY	0x00008000	/* TX Frame Successful After Retry */
-#define	TX_FRLEN	0x07FF0000	/* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define	RSTC		0x00000001	/* Reset All Counters */
-#define	CROLL		0x00000002	/* Counter Roll-Over Enable */
-#define	CCOR		0x00000004	/* Counter Clear-On-Read Mode Enable */
-#define	MMCE		0x00000008	/* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define	RX_OK_CNT	0x00000001	/* RX Frames Received With No Errors */
-#define	RX_FCS_CNT	0x00000002	/* RX Frames W/Frame Check Sequence Errors */
-#define	RX_ALIGN_CNT	0x00000004	/* RX Frames With Alignment Errors */
-#define	RX_OCTET_CNT	0x00000008	/* RX Octets Received OK */
-#define	RX_LOST_CNT	0x00000010	/* RX Frames Lost Due To Internal MAC RX Error */
-#define	RX_UNI_CNT	0x00000020	/* Unicast RX Frames Received OK */
-#define	RX_MULTI_CNT	0x00000040	/* Multicast RX Frames Received OK */
-#define	RX_BROAD_CNT	0x00000080	/* Broadcast RX Frames Received OK */
-#define	RX_IRL_CNT	0x00000100	/* RX Frames With In-Range Length Errors */
-#define	RX_ORL_CNT	0x00000200	/* RX Frames With Out-Of-Range Length Errors */
-#define	RX_LONG_CNT	0x00000400	/* RX Frames With Frame Too Long Errors */
-#define	RX_MACCTL_CNT	0x00000800	/* MAC Control RX Frames Received */
-#define	RX_OPCODE_CTL	0x00001000	/* Unsupported Op-Code RX Frames Received */
-#define	RX_PAUSE_CNT	0x00002000	/* PAUSEMAC Control RX Frames Received */
-#define	RX_ALLF_CNT	0x00004000	/* All RX Frames Received */
-#define	RX_ALLO_CNT	0x00008000	/* All RX Octets Received */
-#define	RX_TYPED_CNT	0x00010000	/* Typed RX Frames Received */
-#define	RX_SHORT_CNT	0x00020000	/* RX Frame Fragments (< 64 Bytes) Received */
-#define	RX_EQ64_CNT	0x00040000	/* 64-Byte RX Frames Received */
-#define	RX_LT128_CNT	0x00080000	/* 65-127-Byte RX Frames Received */
-#define	RX_LT256_CNT	0x00100000	/* 128-255-Byte RX Frames Received */
-#define	RX_LT512_CNT	0x00200000	/* 256-511-Byte RX Frames Received */
-#define	RX_LT1024_CNT	0x00400000	/* 512-1023-Byte RX Frames Received */
-#define	RX_GE1024_CNT	0x00800000	/* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-#define	TX_OK_CNT	0x00000001	/* TX Frames Sent OK */
-#define	TX_SCOLL_CNT	0x00000002	/* TX Frames With Single Collisions */
-#define	TX_MCOLL_CNT	0x00000004	/* TX Frames With Multiple Collisions */
-#define	TX_OCTET_CNT	0x00000008	/* TX Octets Sent OK */
-#define	TX_DEFER_CNT	0x00000010	/* TX Frames With Deferred Transmission */
-#define	TX_LATE_CNT	0x00000020	/* TX Frames With Late Collisions */
-#define	TX_ABORTC_CNT	0x00000040	/* TX Frames Aborted Due To Excess Collisions */
-#define	TX_LOST_CNT	0x00000080	/* TX Frames Lost Due To Internal MAC TX Error */
-#define	TX_CRS_CNT	0x00000100	/* TX Frames With Carrier Sense Errors */
-#define	TX_UNI_CNT	0x00000200	/* Unicast TX Frames Sent */
-#define	TX_MULTI_CNT	0x00000400	/* Multicast TX Frames Sent */
-#define	TX_BROAD_CNT	0x00000800	/* Broadcast TX Frames Sent */
-#define	TX_EXDEF_CTL	0x00001000	/* TX Frames With Excessive Deferral */
-#define	TX_MACCTL_CNT	0x00002000	/* MAC Control TX Frames Sent */
-#define	TX_ALLF_CNT	0x00004000	/* All TX Frames Sent */
-#define	TX_ALLO_CNT	0x00008000	/* All TX Octets Sent */
-#define	TX_EQ64_CNT	0x00010000	/* 64-Byte TX Frames Sent */
-#define	TX_LT128_CNT	0x00020000	/* 65-127-Byte TX Frames Sent */
-#define	TX_LT256_CNT	0x00040000	/* 128-255-Byte TX Frames Sent */
-#define	TX_LT512_CNT	0x00080000	/* 256-511-Byte TX Frames Sent */
-#define	TX_LT1024_CNT	0x00100000	/* 512-1023-Byte TX Frames Sent */
-#define	TX_GE1024_CNT	0x00200000	/* 1024-Max-Byte TX Frames Sent */
-#define	TX_ABORT_CNT	0x00400000	/* TX Frames Aborted */
-
-/*default value for EMAC_VLANx reg*/
-#define EMAC_VLANX_DEF_VAL 0xFFFF
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/eppi.h b/arch/blackfin/include/asm/mach-common/bits/eppi.h
deleted file mode 100644
index fb1456f..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/eppi.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Enhanced PPI (EPPI)
- */
-
-#ifndef __BFIN_PERIPHERAL_EPPI__
-#define __BFIN_PERIPHERAL_EPPI__
-
-/* Bit masks for EPPIx_STATUS */
-#define CFIFO_ERR              0x0001        /* Chroma FIFO Error */
-#define YFIFO_ERR              0x0002        /* Luma FIFO Error */
-#define LTERR_OVR              0x0004        /* Line Track Overflow */
-#define LTERR_UNDR             0x0008        /* Line Track Underflow */
-#define FTERR_OVR              0x0010        /* Frame Track Overflow */
-#define FTERR_UNDR             0x0020        /* Frame Track Underflow */
-#define ERR_NCOR               0x0040        /* Preamble Error Not Corrected */
-#define DMA1URQ                0x0080        /* DMA1 Urgent Request */
-#define DMA0URQ                0x0100        /* DMA0 Urgent Request */
-#define ERR_DET                0x4000        /* Preamble Error Detected */
-#define FLD                    0x8000        /* Field */
-
-/* Bit masks for EPPIx_CONTROL */
-#define EPPI_EN                0x00000001    /* Enable */
-#define EPPI_DIR               0x00000002    /* Direction */
-#define XFR_TYPE               0x0000000c    /* Operating Mode */
-#define FS_CFG                 0x00000030    /* Frame Sync Configuration */
-#define FLD_SEL                0x00000040    /* Field Select/Trigger */
-#define ITU_TYPE               0x00000080    /* ITU Interlaced or Progressive */
-#define BLANKGEN               0x00000100    /* ITU Output Mode with Internal Blanking Generation */
-#define ICLKGEN                0x00000200    /* Internal Clock Generation */
-#define IFSGEN                 0x00000400    /* Internal Frame Sync Generation */
-#define POLC                   0x00001800    /* Frame Sync and Data Driving/Sampling Edges */
-#define POLS                   0x00006000    /* Frame Sync Polarity */
-#define DLENGTH                0x00038000    /* Data Length */
-#define SKIP_EN                0x00040000    /* Skip Enable */
-#define SKIP_EO                0x00080000    /* Skip Even or Odd */
-#define PACKEN                 0x00100000    /* Packing/Unpacking Enable */
-#define SWAPEN                 0x00200000    /* Swap Enable */
-#define SIGN_EXT               0x00400000    /* Sign Extension or Zero-filled / Data Split Format */
-#define SPLT_EVEN_ODD          0x00800000    /* Split Even and Odd Data Samples */
-#define SUBSPLT_ODD            0x01000000    /* Sub-split Odd Samples */
-#define DMACFG                 0x02000000    /* One or Two DMA Channels Mode */
-#define RGB_FMT_EN             0x04000000    /* RGB Formatting Enable */
-#define FIFO_RWM               0x18000000    /* FIFO Regular Watermarks */
-#define FIFO_UWM               0x60000000    /* FIFO Urgent Watermarks */
-
-#define DLEN_8                 (0 << 15)     /* 000 - 8 bits */
-#define DLEN_10                (1 << 15)     /* 001 - 10 bits */
-#define DLEN_12                (2 << 15)     /* 010 - 12 bits */
-#define DLEN_14                (3 << 15)     /* 011 - 14 bits */
-#define DLEN_16                (4 << 15)     /* 100 - 16 bits */
-#define DLEN_18                (5 << 15)     /* 101 - 18 bits */
-#define DLEN_24                (6 << 15)     /* 110 - 24 bits */
-
-/* Bit masks for EPPIx_FS2W_LVB */
-#define F1VB_BD                0x000000ff    /* Vertical Blanking before Field 1 Active Data */
-#define F1VB_AD                0x0000ff00    /* Vertical Blanking after Field 1 Active Data */
-#define F2VB_BD                0x00ff0000    /* Vertical Blanking before Field 2 Active Data */
-#define F2VB_AD                0xff000000    /* Vertical Blanking after Field 2 Active Data */
-
-/* Bit masks for EPPIx_FS2W_LAVF */
-#define F1_ACT                 0x0000ffff    /* Number of Lines of Active Data in Field 1 */
-#define F2_ACT                 0xffff0000    /* Number of Lines of Active Data in Field 2 */
-
-/* Bit masks for EPPIx_CLIP */
-#define LOW_ODD                0x000000ff    /* Lower Limit for Odd Bytes (Chroma) */
-#define HIGH_ODD               0x0000ff00    /* Upper Limit for Odd Bytes (Chroma) */
-#define LOW_EVEN               0x00ff0000    /* Lower Limit for Even Bytes (Luma) */
-#define HIGH_EVEN              0xff000000    /* Upper Limit for Even Bytes (Luma) */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/mpu.h b/arch/blackfin/include/asm/mach-common/bits/mpu.h
deleted file mode 100644
index cfde236..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/mpu.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * MPU Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_MPU__
-#define __BFIN_PERIPHERAL_MPU__
-
-/*
- * DMEM_CONTROL Register
- */
-
-/* ** Bit Positions */
-#define ENDM_P			0x00	/* (doesn't really exist) Enable Data Memory L1 */
-#define DMCTL_ENDM_P		ENDM_P	/* "" (older define) */
-#define ENDCPLB_P		0x01	/* Enable DCPLBS */
-#define DMCTL_ENDCPLB_P		ENDCPLB_P	/* "" (older define) */
-#define DMC0_P			0x02	/* L1 Data Memory Configure bit 0 */
-#define DMCTL_DMC0_P		DMC0_P	/* "" (older define) */
-#define DMC1_P			0x03	/* L1 Data Memory Configure bit 1 */
-#define DMCTL_DMC1_P		DMC1_P	/* "" (older define) */
-#define DCBS_P			0x04	/* L1 Data Cache Bank Select */
-#define PORT_PREF0_P		0x12	/* DAG0 Port Preference */
-#define PORT_PREF1_P		0x13	/* DAG1 Port Preference */
-
-/* ** Masks */
-#define ENDM			0x00000001	/* (doesn't really exist) Enable Data Memory L1 */
-#define ENDCPLB			0x00000002	/* Enable DCPLB */
-#define ASRAM_BSRAM		0x00000000
-#define ACACHE_BSRAM		0x00000008
-#define ACACHE_BCACHE		0x0000000C
-#define DCBS			0x00000010	/*  L1 Data Cache Bank Select */
-#define PORT_PREF0		0x00001000	/* DAG0 Port Preference */
-#define PORT_PREF1		0x00002000	/* DAG1 Port Preference */
-
-/* IMEM_CONTROL Register */
-/* ** Bit Positions */
-#define ENIM_P			0x00	/* Enable L1 Code Memory */
-#define IMCTL_ENIM_P		0x00	/* "" (older define) */
-#define ENICPLB_P		0x01	/* Enable ICPLB */
-#define IMCTL_ENICPLB_P		0x01	/* "" (older define) */
-#define IMC_P			0x02	/* Enable */
-#define IMCTL_IMC_P		0x02	/* Configure L1 code memory as cache (0=SRAM) */
-#define ILOC0_P			0x03	/* Lock Way 0 */
-#define ILOC1_P			0x04	/* Lock Way 1 */
-#define ILOC2_P			0x05	/* Lock Way 2 */
-#define ILOC3_P			0x06	/* Lock Way 3 */
-#define LRUPRIORST_P		0x0D	/* Least Recently Used Replacement Priority */
-
-/* ** Masks */
-#define ENIM			0x00000001	/* Enable L1 Code Memory */
-#define ENICPLB			0x00000002	/* Enable ICPLB */
-#define IMC			0x00000004	/* Configure L1 code memory as cache (0=SRAM) */
-#define ILOC0			0x00000008	/* Lock Way 0 */
-#define ILOC1			0x00000010	/* Lock Way 1 */
-#define ILOC2			0x00000020	/* Lock Way 2 */
-#define ILOC3			0x00000040	/* Lock Way 3 */
-#define LRUPRIORST		0x00002000	/* Least Recently Used Replacement Priority */
-
-/* DCPLB_DATA and ICPLB_DATA Registers */
-/* ** Bit Positions */
-#define CPLB_VALID_P		0x00000000	/* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK_P		0x00000001	/* 0=entry may be replaced, 1=entry locked */
-#define CPLB_USER_RD_P		0x00000002	/* 0=no read access, 1=read access allowed (user mode) */
-
-/* ** Masks */
-#define CPLB_VALID		0x00000001	/* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK		0x00000002	/* 0=entry may be replaced, 1=entry locked */
-#define CPLB_USER_RD		0x00000004	/* 0=no read access, 1=read access allowed (user mode) */
-#define PAGE_SIZE_1KB		0x00000000	/* 1 KB page size */
-#define PAGE_SIZE_4KB		0x00010000	/* 4 KB page size */
-#define PAGE_SIZE_1MB		0x00020000	/* 1 MB page size */
-#define PAGE_SIZE_4MB		0x00030000	/* 4 MB page size */
-#define PAGE_SIZE_16KB		0x00040000	/* 16 KB page size */
-#define PAGE_SIZE_64KB		0x00050000	/* 64 KB page size */
-#define PAGE_SIZE_16MB		0x00060000	/* 16 MB page size */
-#define PAGE_SIZE_64MB		0x00070000	/* 64 MB page size */
-#define PAGE_SIZE_MASK		0x00070000	/* page_size field mask */
-#define PAGE_SIZE_SHIFT		16
-#define CPLB_L1SRAM		0x00000020	/* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
-#define CPLB_PORTPRIO		0x00000200	/* 0=low priority port, 1= high priority port */
-#define CPLB_L1_CHBL		0x00001000	/* 0=non-cacheable in L1, 1=cacheable in L1 */
-
-/* ICPLB_DATA only */
-#define CPLB_LRUPRIO		0x00000100	/* 0=can be replaced by any line, 1=priority for non-replacement */
-
-/* DCPLB_DATA only */
-#define CPLB_USER_WR		0x00000008	/* 0=no write access, 0=write access allowed (user mode) */
-#define CPLB_SUPV_WR		0x00000010	/* 0=no write access, 0=write access allowed (supervisor mode) */
-#define CPLB_DIRTY		0x00000080	/* 1=dirty, 0=clean */
-#define CPLB_L1_AOW		0x00008000	/* 0=do not allocate cache lines on write-through writes, */
-						/* 1= allocate cache lines on write-through writes. */
-#define CPLB_WT			0x00004000	/* 0=write-back, 1=write-through */
-
-/* ITEST_COMMAND and DTEST_COMMAND Registers */
-/* ** Masks */
-#define TEST_READ		0x00000000	/* Read Access */
-#define TEST_WRITE		0x00000002	/* Write Access */
-#define TEST_TAG		0x00000000	/* Access TAG */
-#define TEST_DATA		0x00000004	/* Access DATA */
-#define TEST_DW0		0x00000000	/* Select Double Word 0 */
-#define TEST_DW1		0x00000008	/* Select Double Word 1 */
-#define TEST_DW2		0x00000010	/* Select Double Word 2 */
-#define TEST_DW3		0x00000018	/* Select Double Word 3 */
-#define TEST_MB0		0x00000000	/* Select Mini-Bank 0 */
-#define TEST_MB1		0x00010000	/* Select Mini-Bank 1 */
-#define TEST_MB2		0x00020000	/* Select Mini-Bank 2 */
-#define TEST_MB3		0x00030000	/* Select Mini-Bank 3 */
-#define TEST_SET(x)		((x << 5) & 0x03E0)	/* Set Index 0->31 */
-#define TEST_WAY0		0x00000000	/* Access Way0 */
-#define TEST_WAY1		0x04000000	/* Access Way1 */
-
-/* ** ITEST_COMMAND only */
-#define TEST_WAY2		0x08000000	/* Access Way2 */
-#define TEST_WAY3		0x0C000000	/* Access Way3 */
-
-/* ** DTEST_COMMAND only */
-#define TEST_BNKSELA		0x00000000	/* Access SuperBank A */
-#define TEST_BNKSELB		0x00800000	/* Access SuperBank B */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/otp.h b/arch/blackfin/include/asm/mach-common/bits/otp.h
deleted file mode 100644
index 4e3f1af..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/otp.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * OTP Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_OTP__
-#define __BFIN_PERIPHERAL_OTP__
-
-#ifndef __ASSEMBLY__
-
-#include "bootrom.h"
-
-static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)_BOOTROM_OTP_COMMAND;
-static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_READ;
-static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_WRITE;
-
-#endif
-
-/* otp_command(): defines for "command" */
-#define OTP_INIT                 0x00000001
-#define OTP_CLOSE                0x00000002
-
-/* otp_{read,write}(): defines for "flags" */
-#define OTP_LOWER_HALF           0x00000000 /* select upper/lower 64-bit half (bit 0) */
-#define OTP_UPPER_HALF           0x00000001
-#define OTP_NO_ECC               0x00000010 /* do not use ECC */
-#define OTP_LOCK                 0x00000020 /* sets page protection bit for page */
-#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
-
-/* Return values for all functions */
-#define OTP_SUCCESS          0x00000000
-#define OTP_MASTER_ERROR     0x001
-#define OTP_WRITE_ERROR      0x003
-#define OTP_READ_ERROR       0x005
-#define OTP_ACC_VIO_ERROR    0x009
-#define OTP_DATA_MULT_ERROR  0x011
-#define OTP_ECC_MULT_ERROR   0x021
-#define OTP_PREV_WR_ERROR    0x041
-#define OTP_DATA_SB_WARN     0x100
-#define OTP_ECC_SB_WARN      0x200
-
-/* Predefined otp pages: Factory Programmed Settings */
-#define FPS00                0x0004
-#define FPS01                0x0005
-#define FPS02                0x0006
-#define FPS03                0x0007
-#define FPS04                0x0008
-#define FPS05                0x0009
-#define FPS06                0x000A
-#define FPS07                0x000B
-#define FPS08                0x000C
-#define FPS09                0x000D
-#define FPS10                0x000E
-#define FPS11                0x000F
-
-/* Predefined otp pages: Customer Programmed Settings */
-#define CPS00                0x0010
-#define CPS01                0x0011
-#define CPS02                0x0012
-#define CPS03                0x0013
-#define CPS04                0x0014
-#define CPS05                0x0015
-#define CPS06                0x0016
-#define CPS07                0x0017
-
-/* Predefined otp pages: Pre-Boot Settings */
-#define PBS00                0x0018
-#define PBS01                0x0019
-#define PBS02                0x001A
-#define PBS03                0x001B
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/pata.h b/arch/blackfin/include/asm/mach-common/bits/pata.h
deleted file mode 100644
index 9b61824..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/pata.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * ATAPI Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PATA__
-#define __BFIN_PERIPHERAL_PATA__
-
-/* Bit masks for ATAPI_CONTROL */
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for ATAPI_CONTROL */
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-#endif /* __BFIN_PERIPHERAL_PATA__ */
diff --git a/arch/blackfin/include/asm/mach-common/bits/pll.h b/arch/blackfin/include/asm/mach-common/bits/pll.h
deleted file mode 100644
index fe0ba0f..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/pll.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * PLL Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PLL__
-#define __BFIN_PERIPHERAL_PLL__
-
-/* PLL_CTL Masks */
-#define DF			0x0001		/* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
-#define PLL_OFF			0x0002		/* PLL Not Powered */
-#define STOPCK			0x0008		/* Core Clock Off */
-#define PDWN			0x0020		/* Enter Deep Sleep Mode */
-#define IN_DELAY		0x0040		/* Add 200ps Delay To EBIU Input Latches */
-#define OUT_DELAY		0x0080		/* Add 200ps Delay To EBIU Output Signals */
-#define BYPASS			0x0100		/* Bypass the PLL */
-#define MSEL			0x7E00		/* Multiplier Select For CCLK/VCO Factors */
-#define SPORT_HYST		0x8000		/* Enable Additional Hysteresis on SPORT Input Pins */
-
-#define MSEL_P			9
-
-/* PLL_DIV Masks */
-#define SSEL			0x000F		/* System Select */
-#define CSEL			0x0030		/* Core Select */
-#define CSEL_DIV1		0x0000		/* CCLK = VCO / 1 */
-#define CSEL_DIV2		0x0010		/* CCLK = VCO / 2 */
-#define CSEL_DIV4		0x0020		/* CCLK = VCO / 4 */
-#define CSEL_DIV8		0x0030		/* CCLK = VCO / 8 */
-
-#define CCLK_DIV1		CSEL_DIV1
-#define CCLK_DIV2		CSEL_DIV2
-#define CCLK_DIV4		CSEL_DIV4
-#define CCLK_DIV8		CSEL_DIV8
-
-#define SSEL_P			0
-#define CSEL_P			4
-
-/* PLL_STAT Masks */
-#define ACTIVE_PLLENABLED	0x0001		/* Processor In Active Mode With PLL Enabled */
-#define FULL_ON			0x0002		/* Processor In Full On Mode */
-#define ACTIVE_PLLDISABLED	0x0004		/* Processor In Active Mode With PLL Disabled */
-#define DEEP_SLEEP		0x0008		/* Processor In Deep Sleep Mode */
-#define SLEEP			0x0010		/* Processor In Sleep Mode */
-#define PLL_LOCKED		0x0020		/* PLL_LOCKCNT Has Been Reached */
-#define CORE_IDLE		0x0040		/* Processor In IDLE Mode */
-#define VSTAT			0x0080		/* Voltage Regulator Has Reached Programmed Voltage */
-
-/* VR_CTL Masks */
-#ifdef __ADSPBF52x__
-#define FREQ_MASK		0x3000		/* Switching Oscillator Frequency For Regulator */
-#define FREQ_HIBERNATE		0x0000		/* Powerdown/Bypass On-Board Regulation */
-#define FREQ_1000		0x3000		/* Switching Frequency Is 1 MHz */
-#else
-#define FREQ_MASK		0x0003		/* Switching Oscillator Frequency For Regulator */
-#define FREQ_HIBERNATE		0x0000		/* Powerdown/Bypass On-Board Regulation */
-#define FREQ_333		0x0001		/* Switching Frequency Is 333 kHz */
-#define FREQ_667		0x0002		/* Switching Frequency Is 667 kHz */
-#define FREQ_1000		0x0003		/* Switching Frequency Is 1 MHz */
-#endif
-
-#define GAIN_MASK		0x000C		/* Voltage Level Gain */
-#define GAIN_5			0x0000		/* GAIN = 5 */
-#define GAIN_10			0x0004		/* GAIN = 10 */
-#define GAIN_20			0x0008		/* GAIN = 20 */
-#define GAIN_50			0x000C		/* GAIN = 50 */
-
-#ifdef __ADSPBF52x__
-#define VLEV_MASK		0x00F0		/* Internal Voltage Level */
-#define VLEV_085		0x0040		/* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090		0x0050		/* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095		0x0060		/* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100		0x0070		/* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105		0x0080		/* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110		0x0090		/* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115		0x00A0		/* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120		0x00B0		/* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#else
-#define VLEV_MASK		0x00F0		/* Internal Voltage Level */
-#define VLEV_085		0x0060		/* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090		0x0070		/* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095		0x0080		/* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100		0x0090		/* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105		0x00A0		/* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110		0x00B0		/* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115		0x00C0		/* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120		0x00D0		/* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#define VLEV_125		0x00E0		/* VLEV = 1.25 V (-5% - +10% Accuracy) */
-#define VLEV_130		0x00F0		/* VLEV = 1.30 V (-5% - +10% Accuracy) */
-#endif
-
-#define WAKE			0x0100		/* Enable RTC/Reset Wakeup From Hibernate */
-#define CANWE			0x0200		/* Enable CAN Wakeup From Hibernate */
-#define PHYWE			0x0400		/* Enable PHY Wakeup From Hibernate */
-#define GPWE			0x0400		/* General-purpose Wakeup From Hibernate */
-#define MXVRWE			0x0400		/* MXVR Wakeup From Hibernate */
-#define USBWE			0x0800		/* USB Wakeup From Hibernate */
-#define KPADWE			0x1000		/* Keypad Wakeup From Hibernate */
-#define ROTWE			0x2000		/* Rotary Counter Wakeup From Hibernate */
-#define CLKBUFOE		0x4000		/* CLKIN Buffer Output Enable */
-#define CKELOW			0x8000		/* Enable Drive CKE Low During Reset */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-a.h b/arch/blackfin/include/asm/mach-common/bits/ports-a.h
deleted file mode 100644
index 9f78a76..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-a.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port A Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_A__
-#define __BFIN_PERIPHERAL_PORT_A__
-
-#define PA0		(1 << 0)
-#define PA1		(1 << 1)
-#define PA2		(1 << 2)
-#define PA3		(1 << 3)
-#define PA4		(1 << 4)
-#define PA5		(1 << 5)
-#define PA6		(1 << 6)
-#define PA7		(1 << 7)
-#define PA8		(1 << 8)
-#define PA9		(1 << 9)
-#define PA10		(1 << 10)
-#define PA11		(1 << 11)
-#define PA12		(1 << 12)
-#define PA13		(1 << 13)
-#define PA14		(1 << 14)
-#define PA15		(1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-b.h b/arch/blackfin/include/asm/mach-common/bits/ports-b.h
deleted file mode 100644
index b81702f..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-b.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port B Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_B__
-#define __BFIN_PERIPHERAL_PORT_B__
-
-#define PB0		(1 << 0)
-#define PB1		(1 << 1)
-#define PB2		(1 << 2)
-#define PB3		(1 << 3)
-#define PB4		(1 << 4)
-#define PB5		(1 << 5)
-#define PB6		(1 << 6)
-#define PB7		(1 << 7)
-#define PB8		(1 << 8)
-#define PB9		(1 << 9)
-#define PB10		(1 << 10)
-#define PB11		(1 << 11)
-#define PB12		(1 << 12)
-#define PB13		(1 << 13)
-#define PB14		(1 << 14)
-#define PB15		(1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-c.h b/arch/blackfin/include/asm/mach-common/bits/ports-c.h
deleted file mode 100644
index 3cc665e..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-c.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port C Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_C__
-#define __BFIN_PERIPHERAL_PORT_C__
-
-#define PC0		(1 << 0)
-#define PC1		(1 << 1)
-#define PC2		(1 << 2)
-#define PC3		(1 << 3)
-#define PC4		(1 << 4)
-#define PC5		(1 << 5)
-#define PC6		(1 << 6)
-#define PC7		(1 << 7)
-#define PC8		(1 << 8)
-#define PC9		(1 << 9)
-#define PC10		(1 << 10)
-#define PC11		(1 << 11)
-#define PC12		(1 << 12)
-#define PC13		(1 << 13)
-#define PC14		(1 << 14)
-#define PC15		(1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-d.h b/arch/blackfin/include/asm/mach-common/bits/ports-d.h
deleted file mode 100644
index 868c6a0..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-d.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port D Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_D__
-#define __BFIN_PERIPHERAL_PORT_D__
-
-#define PD0		(1 << 0)
-#define PD1		(1 << 1)
-#define PD2		(1 << 2)
-#define PD3		(1 << 3)
-#define PD4		(1 << 4)
-#define PD5		(1 << 5)
-#define PD6		(1 << 6)
-#define PD7		(1 << 7)
-#define PD8		(1 << 8)
-#define PD9		(1 << 9)
-#define PD10		(1 << 10)
-#define PD11		(1 << 11)
-#define PD12		(1 << 12)
-#define PD13		(1 << 13)
-#define PD14		(1 << 14)
-#define PD15		(1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-e.h b/arch/blackfin/include/asm/mach-common/bits/ports-e.h
deleted file mode 100644
index c88b0d0..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-e.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port E Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_E__
-#define __BFIN_PERIPHERAL_PORT_E__
-
-#define PE0		(1 << 0)
-#define PE1		(1 << 1)
-#define PE2		(1 << 2)
-#define PE3		(1 << 3)
-#define PE4		(1 << 4)
-#define PE5		(1 << 5)
-#define PE6		(1 << 6)
-#define PE7		(1 << 7)
-#define PE8		(1 << 8)
-#define PE9		(1 << 9)
-#define PE10		(1 << 10)
-#define PE11		(1 << 11)
-#define PE12		(1 << 12)
-#define PE13		(1 << 13)
-#define PE14		(1 << 14)
-#define PE15		(1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-f.h b/arch/blackfin/include/asm/mach-common/bits/ports-f.h
deleted file mode 100644
index d6af206..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-f.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port F Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_F__
-#define __BFIN_PERIPHERAL_PORT_F__
-
-#define PF0		(1 << 0)
-#define PF1		(1 << 1)
-#define PF2		(1 << 2)
-#define PF3		(1 << 3)
-#define PF4		(1 << 4)
-#define PF5		(1 << 5)
-#define PF6		(1 << 6)
-#define PF7		(1 << 7)
-#define PF8		(1 << 8)
-#define PF9		(1 << 9)
-#define PF10		(1 << 10)
-#define PF11		(1 << 11)
-#define PF12		(1 << 12)
-#define PF13		(1 << 13)
-#define PF14		(1 << 14)
-#define PF15		(1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-g.h b/arch/blackfin/include/asm/mach-common/bits/ports-g.h
deleted file mode 100644
index 09355d3..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-g.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port G Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_G__
-#define __BFIN_PERIPHERAL_PORT_G__
-
-#define PG0		(1 << 0)
-#define PG1		(1 << 1)
-#define PG2		(1 << 2)
-#define PG3		(1 << 3)
-#define PG4		(1 << 4)
-#define PG5		(1 << 5)
-#define PG6		(1 << 6)
-#define PG7		(1 << 7)
-#define PG8		(1 << 8)
-#define PG9		(1 << 9)
-#define PG10		(1 << 10)
-#define PG11		(1 << 11)
-#define PG12		(1 << 12)
-#define PG13		(1 << 13)
-#define PG14		(1 << 14)
-#define PG15		(1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-h.h b/arch/blackfin/include/asm/mach-common/bits/ports-h.h
deleted file mode 100644
index fa3910c..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-h.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port H Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_H__
-#define __BFIN_PERIPHERAL_PORT_H__
-
-#define PH0		(1 << 0)
-#define PH1		(1 << 1)
-#define PH2		(1 << 2)
-#define PH3		(1 << 3)
-#define PH4		(1 << 4)
-#define PH5		(1 << 5)
-#define PH6		(1 << 6)
-#define PH7		(1 << 7)
-#define PH8		(1 << 8)
-#define PH9		(1 << 9)
-#define PH10		(1 << 10)
-#define PH11		(1 << 11)
-#define PH12		(1 << 12)
-#define PH13		(1 << 13)
-#define PH14		(1 << 14)
-#define PH15		(1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-i.h b/arch/blackfin/include/asm/mach-common/bits/ports-i.h
deleted file mode 100644
index f176f08..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-i.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port I Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_I__
-#define __BFIN_PERIPHERAL_PORT_I__
-
-#define PI0		(1 << 0)
-#define PI1		(1 << 1)
-#define PI2		(1 << 2)
-#define PI3		(1 << 3)
-#define PI4		(1 << 4)
-#define PI5		(1 << 5)
-#define PI6		(1 << 6)
-#define PI7		(1 << 7)
-#define PI8		(1 << 8)
-#define PI9		(1 << 9)
-#define PI10		(1 << 10)
-#define PI11		(1 << 11)
-#define PI12		(1 << 12)
-#define PI13		(1 << 13)
-#define PI14		(1 << 14)
-#define PI15		(1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-j.h b/arch/blackfin/include/asm/mach-common/bits/ports-j.h
deleted file mode 100644
index 924123e..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-j.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port J Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_J__
-#define __BFIN_PERIPHERAL_PORT_J__
-
-#define PJ0		(1 << 0)
-#define PJ1		(1 << 1)
-#define PJ2		(1 << 2)
-#define PJ3		(1 << 3)
-#define PJ4		(1 << 4)
-#define PJ5		(1 << 5)
-#define PJ6		(1 << 6)
-#define PJ7		(1 << 7)
-#define PJ8		(1 << 8)
-#define PJ9		(1 << 9)
-#define PJ10		(1 << 10)
-#define PJ11		(1 << 11)
-#define PJ12		(1 << 12)
-#define PJ13		(1 << 13)
-#define PJ14		(1 << 14)
-#define PJ15		(1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ppi.h b/arch/blackfin/include/asm/mach-common/bits/ppi.h
deleted file mode 100644
index 523f238..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/ppi.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * PPI Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PPI__
-#define __BFIN_PERIPHERAL_PPI__
-
-/* PPI_CONTROL Masks */
-#define PORT_EN			0x0001	/* PPI Port Enable */
-#define PORT_DIR		0x0002	/* PPI Port Direction */
-#define XFR_TYPE		0x000C	/* PPI Transfer Type */
-#define PORT_CFG		0x0030	/* PPI Port Configuration */
-#define FLD_SEL			0x0040	/* PPI Active Field Select */
-#define PACK_EN			0x0080	/* PPI Packing Mode */
-#define DMA32			0x0100	/* PPI 32-bit DMA Enable */
-#define SKIP_EN			0x0200	/* PPI Skip Element Enable */
-#define SKIP_EO			0x0400	/* PPI Skip Even/Odd Elements */
-#define DLENGTH			0x3800	/* PPI Data Length */
-#define DLEN_8			0x0000	/* Data Length = 8 Bits */
-#define DLEN_10			0x0800	/* Data Length = 10 Bits */
-#define DLEN_11			0x1000	/* Data Length = 11 Bits */
-#define DLEN_12			0x1800	/* Data Length = 12 Bits */
-#define DLEN_13			0x2000	/* Data Length = 13 Bits */
-#define DLEN_14			0x2800	/* Data Length = 14 Bits */
-#define DLEN_15			0x3000	/* Data Length = 15 Bits */
-#define DLEN_16			0x3800	/* Data Length = 16 Bits */
-#define POLC			0x4000	/* PPI Clock Polarity */
-#define POLS			0x8000	/* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD			0x0400	/* Field Indicator */
-#define FT_ERR			0x0800	/* Frame Track Error */
-#define OVR			0x1000	/* FIFO Overflow Error */
-#define UNDR			0x2000	/* FIFO Underrun Error */
-#define ERR_DET			0x4000	/* Error Detected Indicator */
-#define ERR_NCOR		0x8000	/* Error Not Corrected Indicator */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/rtc.h b/arch/blackfin/include/asm/mach-common/bits/rtc.h
deleted file mode 100644
index f5a0cdb..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/rtc.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * RTC Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_RTC__
-#define __BFIN_PERIPHERAL_RTC__
-
-/* RTC_STAT and RTC_ALARM Masks */
-#define	RTC_SEC			0x0000003F	/* Real-Time Clock Seconds */
-#define	RTC_MIN			0x00000FC0	/* Real-Time Clock Minutes */
-#define	RTC_HR			0x0001F000	/* Real-Time Clock Hours */
-#define	RTC_DAY			0xFFFE0000	/* Real-Time Clock Days */
-
-#define RTC_SEC_P		0
-#define RTC_MIN_P		6
-#define RTC_HR_P		12
-#define RTC_DAY_P		17
-
-/*
- * RTC_ALARM Macro
- */
-#define SET_ALARM(day, hr, min, sec) \
-	( (((day) << RTC_DAY_P) & RTC_DAY) | \
-	  (((hr)  << RTC_HR_P ) & RTC_HR ) | \
-	  (((min) << RTC_MIN_P) & RTC_MIN) | \
-	  (((sec) << RTC_SEC_P) & RTC_SEC) )
-
-/* RTC_ICTL and RTC_ISTAT Masks */
-#define	STOPWATCH		0x0001	/* Stopwatch Interrupt Enable */
-#define	ALARM			0x0002	/* Alarm Interrupt Enable */
-#define	SECOND			0x0004	/* Seconds (1 Hz) Interrupt Enable */
-#define	MINUTE			0x0008	/* Minutes Interrupt Enable */
-#define	HOUR			0x0010	/* Hours Interrupt Enable */
-#define	DAY			0x0020	/* 24 Hours (Days) Interrupt Enable */
-#define	DAY_ALARM		0x0040	/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
-#define	WRITE_PENDING		0x4000	/* Write Pending Status */
-#define	WRITE_COMPLETE		0x8000	/* Write Complete Interrupt Enable */
-
-/* RTC_FAST / RTC_PREN Mask */
-#define PREN			0x0001	/* Enable Prescaler, RTC Runs @1 Hz */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/sdh.h b/arch/blackfin/include/asm/mach-common/bits/sdh.h
deleted file mode 100644
index 1c60d4b..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/sdh.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * SDH Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_SDH__
-#define __BFIN_PERIPHERAL_SDH__
-
-/* Bit masks for SDH_COMMAND */
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define                     CMD_E  0x400      /* Command Enable */
-#ifdef RSI_BLKSZ
-#define           CMD_CRC_CHECK_D  0x800      /* CRC Check is disabled */
-#define            CMD_DATA0_BUSY  0x1000     /* Check Busy State on DATA0 */
-#endif
-
-/* Bit masks for SDH_PWR_CTL */
-#ifndef RSI_BLKSZ
-#define                    PWR_ON  0x3        /* Power On */
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                   ROD_CTL  0x80       /* Rod Control */
-#endif
-
-/* Bit masks for SDH_CLK_CTL */
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define             BUS_MODE_MASK  0x1800     /* Bus Mode Mask */
-#define                 STD_BUS_1  0x000      /* Standard Bus 1 bit mode */
-#define                WIDE_BUS_4  0x800      /* Wide Bus 4 bit mode */
-#define                BYTE_BUS_8  0x1000     /* Byte Bus 8 bit mode */
-#ifdef RSI_BLKSZ
-#define            CARD_TYPE_MASK  0xe000     /* Card type mask */
-#define          CARD_TYPE_OFFSET  13         /* Card type offset */
-#define            CARD_TYPE_SDIO  0
-#define            CARD_TYPE_eMMC  1
-#define              CARD_TYPE_SD  2
-#define           CARD_TYPE_CEATA  3
-#endif
-
-/* Bit masks for SDH_RESP_CMD */
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#ifndef RSI_BLKSZ
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-#else
-
-/* Bit masks for SDH_BLK_SIZE */
-#define              DTX_BLK_LGTH  0x1fff     /* Data Transfer Block Length */
-#endif
-
-/* Bit masks for SDH_STATUS */
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define              CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define              DAT_TIME_OUT  0x8        /* Data Time Out */
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                   DAT_END  0x100      /* Data End */
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-
-/* Bit masks for SDH_STATUS_CLR */
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-
-/* Bit masks for SDH_MASK0 */
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-
-/* Bit masks for SDH_FIFO_CNT */
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-#define          SD_CARD_BUSYMODE  0x80000000 /* Card is in Busy mode */
-#define           SD_CARD_SLPMODE  0x40000000 /* Card in Sleep Mode */
-#define             SD_CARD_READY  0x00020000 /* Card Ready */
-
-/* Bit masks for SDH_E_MASK */
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                   SCD_MSK  0x10       /* Mask Card Detect */
-
-/* Bit masks for SDH_CFG */
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#ifndef RSI_BLKSZ
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-#else
-#define                    PWR_ON  0x600      /* Power On */
-#define                 SD_CMD_OD  0x800      /* Open Drain Output */
-#define                   BOOT_EN  0x1000     /* Boot Enable */
-#define                 BOOT_MODE  0x2000     /* Alternate Boot Mode */
-#define               BOOT_ACK_EN  0x4000     /* Boot ACK is expected */
-#endif
-
-/* Bit masks for SDH_RD_WAIT_EN */
-#define                       RWR  0x1        /* Read Wait Request */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/spi.h b/arch/blackfin/include/asm/mach-common/bits/spi.h
deleted file mode 100644
index 869dcb0..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/spi.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * SPI Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_SPI__
-#define __BFIN_PERIPHERAL_SPI__
-
-/* SPI_CTL Masks */
-#define	TIMOD			0x0003	/* Transfer Initiate Mode */
-#define RDBR_CORE		0x0000	/* RDBR Read Initiates, IRQ When RDBR Full */
-#define	TDBR_CORE		0x0001	/* TDBR Write Initiates, IRQ When TDBR Empty */
-#define RDBR_DMA		0x0002	/* DMA Read, DMA Until FIFO Empty */
-#define TDBR_DMA		0x0003	/* DMA Write, DMA Until FIFO Full */
-#define SZ			0x0004	/* Send Zero (When TDBR Empty, Send Zero/Last*) */
-#define GM			0x0008	/* Get More (When RDBR Full, Overwrite/Discard*) */
-#define PSSE			0x0010	/* Slave-Select Input Enable */
-#define EMISO			0x0020	/* Enable MISO As Output */
-#define SIZE			0x0100	/* Size of Words (16/8* Bits) */
-#define LSBF			0x0200	/* LSB First */
-#define CPHA			0x0400	/* Clock Phase */
-#define CPOL			0x0800	/* Clock Polarity */
-#define MSTR			0x1000	/* Master/Slave* */
-#define WOM			0x2000	/* Write Open Drain Master */
-#define SPE			0x4000	/* SPI Enable */
-
-/* SPI_FLG Masks */
-#define FLS1			0x0002	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2			0x0004	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3			0x0008	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4			0x0010	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5			0x0020	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6			0x0040	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7			0x0080	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1			0x0200	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLG2			0x0400	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3			0x0800	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLG4			0x1000	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLG5			0x2000	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLG6			0x4000	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLG7			0x8000	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_FLG Bit Positions */
-#define FLS1_P			0x0001	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2_P			0x0002	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3_P			0x0003	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4_P			0x0004	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5_P			0x0005	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6_P			0x0006	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7_P			0x0007	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1_P			0x0009	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLG2_P			0x000A	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3_P			0x000B	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLG4_P			0x000C	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLG5_P			0x000D	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLG6_P			0x000E	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLG7_P			0x000F	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_STAT Masks */
-#define SPIF			0x0001	/* SPI Finished (Single-Word Transfer Complete) */
-#define MODF			0x0002	/* Mode Fault Error (Another Device Tried To Become Master) */
-#define TXE			0x0004	/* Transmission Error (Data Sent With No New Data In TDBR) */
-#define TXS			0x0008	/* SPI_TDBR Data Buffer Status (Full/Empty*) */
-#define RBSY			0x0010	/* Receive Error (Data Received With RDBR Full) */
-#define RXS			0x0020	/* SPI_RDBR Data Buffer Status (Full/Empty*) */
-#define TXCOL			0x0040	/* Transmit Collision Error (Corrupt Data May Have Been Sent) */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/spi6xx.h b/arch/blackfin/include/asm/mach-common/bits/spi6xx.h
deleted file mode 100644
index 3368712..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/spi6xx.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * Analog Devices bfin_spi3 controller driver
- *
- * Copyright (c) 2011 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _SPI_CHANNEL_H_
-#define _SPI_CHANNEL_H_
-
-#include <linux/types.h>
-
-/* SPI_CONTROL */
-#define SPI_CTL_EN          0x00000001 /* Enable */
-#define SPI_CTL_MSTR        0x00000002 /* Master/Slave */
-#define SPI_CTL_PSSE        0x00000004 /* controls modf error in master mode */
-#define SPI_CTL_ODM         0x00000008 /* Open Drain Mode */
-#define SPI_CTL_CPHA        0x00000010 /* Clock Phase */
-#define SPI_CTL_CPOL        0x00000020 /* Clock Polarity */
-#define SPI_CTL_ASSEL       0x00000040 /* Slave Select Pin Control */
-#define SPI_CTL_SELST       0x00000080 /* Slave Select Polarity in transfers */
-#define SPI_CTL_EMISO       0x00000100 /*Enable MISO */
-#define SPI_CTL_SIZE        0x00000600 /*Word Transfer Size */
-#define SPI_CTL_SIZE08      0x00000000 /*SIZE: 8 bits */
-#define SPI_CTL_SIZE16      0x00000200 /*SIZE: 16 bits */
-#define SPI_CTL_SIZE32      0x00000400 /*SIZE: 32 bits */
-#define SPI_CTL_LSBF        0x00001000 /*LSB First */
-#define SPI_CTL_FCEN        0x00002000 /*Flow-Control Enable */
-#define SPI_CTL_FCCH        0x00004000 /*Flow-Control Channel Selection */
-#define SPI_CTL_FCPL        0x00008000 /*Flow-Control Polarity */
-#define SPI_CTL_FCWM        0x00030000 /*Flow-Control Water-Mark */
-#define SPI_CTL_FIFO0       0x00000000 /*FCWM: Tx empty or Rx Full */
-#define SPI_CTL_FIFO1       0x00010000 /*FCWM: Tx empty or Rx full (>=75%) */
-#define SPI_CTL_FIFO2       0x00020000 /*FCWM: Tx empty or Rx full (>=50%) */
-#define SPI_CTL_FMODE       0x00040000 /*Fast-mode Enable */
-#define SPI_CTL_MIOM        0x00300000 /*Multiple I/O Mode */
-#define SPI_CTL_MIO_DIS     0x00000000 /*MIOM: Disable */
-#define SPI_CTL_MIO_DUAL    0x00100000 /*MIOM: Enable DIOM (Dual I/O Mode) */
-#define SPI_CTL_MIO_QUAD    0x00200000 /*MIOM: Enable QUAD (Quad SPI Mode) */
-#define SPI_CTL_SOSI        0x00400000 /*Start on MOSI */
-/* SPI_RX_CONTROL */
-#define SPI_RXCTL_REN       0x00000001 /*Receive Channel Enable */
-#define SPI_RXCTL_RTI       0x00000004 /*Receive Transfer Initiate */
-#define SPI_RXCTL_RWCEN     0x00000008 /*Receive Word Counter Enable */
-#define SPI_RXCTL_RDR       0x00000070 /*Receive Data Request */
-#define SPI_RXCTL_RDR_DIS   0x00000000 /*RDR: Disabled */
-#define SPI_RXCTL_RDR_NE    0x00000010 /*RDR: RFIFO not empty */
-#define SPI_RXCTL_RDR_25    0x00000020 /*RDR: RFIFO 25% full */
-#define SPI_RXCTL_RDR_50    0x00000030 /*RDR: RFIFO 50% full */
-#define SPI_RXCTL_RDR_75    0x00000040 /*RDR: RFIFO 75% full */
-#define SPI_RXCTL_RDR_FULL  0x00000050 /*RDR: RFIFO full */
-#define SPI_RXCTL_RDO       0x00000100 /*Receive Data Over-Run */
-#define SPI_RXCTL_RRWM      0x00003000 /*FIFO Regular Water-Mark */
-#define SPI_RXCTL_RWM_0     0x00000000 /*RRWM: RFIFO Empty */
-#define SPI_RXCTL_RWM_25    0x00001000 /*RRWM: RFIFO 25% full */
-#define SPI_RXCTL_RWM_50    0x00002000 /*RRWM: RFIFO 50% full */
-#define SPI_RXCTL_RWM_75    0x00003000 /*RRWM: RFIFO 75% full */
-#define SPI_RXCTL_RUWM      0x00070000 /*FIFO Urgent Water-Mark */
-#define SPI_RXCTL_UWM_DIS   0x00000000 /*RUWM: Disabled */
-#define SPI_RXCTL_UWM_25    0x00010000 /*RUWM: RFIFO 25% full */
-#define SPI_RXCTL_UWM_50    0x00020000 /*RUWM: RFIFO 50% full */
-#define SPI_RXCTL_UWM_75    0x00030000 /*RUWM: RFIFO 75% full */
-#define SPI_RXCTL_UWM_FULL  0x00040000 /*RUWM: RFIFO full */
-/* SPI_TX_CONTROL */
-#define SPI_TXCTL_TEN       0x00000001 /*Transmit Channel Enable */
-#define SPI_TXCTL_TTI       0x00000004 /*Transmit Transfer Initiate */
-#define SPI_TXCTL_TWCEN     0x00000008 /*Transmit Word Counter Enable */
-#define SPI_TXCTL_TDR       0x00000070 /*Transmit Data Request */
-#define SPI_TXCTL_TDR_DIS   0x00000000 /*TDR: Disabled */
-#define SPI_TXCTL_TDR_NF    0x00000010 /*TDR: TFIFO not full */
-#define SPI_TXCTL_TDR_25    0x00000020 /*TDR: TFIFO 25% empty */
-#define SPI_TXCTL_TDR_50    0x00000030 /*TDR: TFIFO 50% empty */
-#define SPI_TXCTL_TDR_75    0x00000040 /*TDR: TFIFO 75% empty */
-#define SPI_TXCTL_TDR_EMPTY 0x00000050 /*TDR: TFIFO empty */
-#define SPI_TXCTL_TDU       0x00000100 /*Transmit Data Under-Run */
-#define SPI_TXCTL_TRWM      0x00003000 /*FIFO Regular Water-Mark */
-#define SPI_TXCTL_RWM_FULL  0x00000000 /*TRWM: TFIFO full */
-#define SPI_TXCTL_RWM_25    0x00001000 /*TRWM: TFIFO 25% empty */
-#define SPI_TXCTL_RWM_50    0x00002000 /*TRWM: TFIFO 50% empty */
-#define SPI_TXCTL_RWM_75    0x00003000 /*TRWM: TFIFO 75% empty */
-#define SPI_TXCTL_TUWM      0x00070000 /*FIFO Urgent Water-Mark */
-#define SPI_TXCTL_UWM_DIS   0x00000000 /*TUWM: Disabled */
-#define SPI_TXCTL_UWM_25    0x00010000 /*TUWM: TFIFO 25% empty */
-#define SPI_TXCTL_UWM_50    0x00020000 /*TUWM: TFIFO 50% empty */
-#define SPI_TXCTL_UWM_75    0x00030000 /*TUWM: TFIFO 75% empty */
-#define SPI_TXCTL_UWM_EMPTY 0x00040000 /*TUWM: TFIFO empty */
-/* SPI_CLOCK */
-#define SPI_CLK_BAUD        0x0000FFFF /*Baud Rate */
-/* SPI_DELAY */
-#define SPI_DLY_STOP        0x000000FF /*Transfer delay time */
-#define SPI_DLY_LEADX       0x00000100 /*Extended (1 SCK) LEAD Control */
-#define SPI_DLY_LAGX        0x00000200 /*Extended (1 SCK) LAG control */
-/* SPI_SSEL */
-#define SPI_SLVSEL_SSE1     0x00000002 /*SPISSEL1 Enable */
-#define SPI_SLVSEL_SSE2     0x00000004 /*SPISSEL2 Enable */
-#define SPI_SLVSEL_SSE3     0x00000008 /*SPISSEL3 Enable */
-#define SPI_SLVSEL_SSE4     0x00000010 /*SPISSEL4 Enable */
-#define SPI_SLVSEL_SSE5     0x00000020 /*SPISSEL5 Enable */
-#define SPI_SLVSEL_SSE6     0x00000040 /*SPISSEL6 Enable */
-#define SPI_SLVSEL_SSE7     0x00000080 /*SPISSEL7 Enable */
-#define SPI_SLVSEL_SSEL1    0x00000200 /*SPISSEL1 Value */
-#define SPI_SLVSEL_SSEL2    0x00000400 /*SPISSEL2 Value */
-#define SPI_SLVSEL_SSEL3    0x00000800 /*SPISSEL3 Value */
-#define SPI_SLVSEL_SSEL4    0x00001000 /*SPISSEL4 Value */
-#define SPI_SLVSEL_SSEL5    0x00002000 /*SPISSEL5 Value */
-#define SPI_SLVSEL_SSEL6    0x00004000 /*SPISSEL6 Value */
-#define SPI_SLVSEL_SSEL7    0x00008000 /*SPISSEL7 Value */
-/* SPI_RWC */
-#define SPI_RWC_VALUE       0x0000FFFF /*Received Word-Count */
-/* SPI_RWCR */
-#define SPI_RWCR_VALUE      0x0000FFFF /*Received Word-Count Reload */
-/* SPI_TWC */
-#define SPI_TWC_VALUE       0x0000FFFF /*Transmitted Word-Count */
-/* SPI_TWCR */
-#define SPI_TWCR_VALUE      0x0000FFFF /*Transmitted Word-Count Reload */
-/* SPI_IMASK */
-#define SPI_IMSK_RUWM       0x00000002 /*Receive Water-Mark Interrupt Mask */
-#define SPI_IMSK_TUWM       0x00000004 /*Transmit Water-Mark Interrupt Mask */
-#define SPI_IMSK_ROM        0x00000010 /*Receive Over-Run Interrupt Mask */
-#define SPI_IMSK_TUM        0x00000020 /*Transmit Under-Run Interrupt Mask */
-#define SPI_IMSK_TCM        0x00000040 /*Transmit Collision Interrupt Mask */
-#define SPI_IMSK_MFM        0x00000080 /*Mode Fault Interrupt Mask */
-#define SPI_IMSK_RSM        0x00000100 /*Receive Start Interrupt Mask */
-#define SPI_IMSK_TSM        0x00000200 /*Transmit Start Interrupt Mask */
-#define SPI_IMSK_RFM        0x00000400 /*Receive Finish Interrupt Mask */
-#define SPI_IMSK_TFM        0x00000800 /*Transmit Finish Interrupt Mask */
-/* SPI_IMASKCL */
-#define SPI_IMSK_CLR_RUW    0x00000002 /*Receive Water-Mark Interrupt Mask */
-#define SPI_IMSK_CLR_TUWM   0x00000004 /*Transmit Water-Mark Interrupt Mask */
-#define SPI_IMSK_CLR_ROM    0x00000010 /*Receive Over-Run Interrupt Mask */
-#define SPI_IMSK_CLR_TUM    0x00000020 /*Transmit Under-Run Interrupt Mask */
-#define SPI_IMSK_CLR_TCM    0x00000040 /*Transmit Collision Interrupt Mask */
-#define SPI_IMSK_CLR_MFM    0x00000080 /*Mode Fault Interrupt Mask */
-#define SPI_IMSK_CLR_RSM    0x00000100 /*Receive Start Interrupt Mask */
-#define SPI_IMSK_CLR_TSM    0x00000200 /*Transmit Start Interrupt Mask */
-#define SPI_IMSK_CLR_RFM    0x00000400 /*Receive Finish Interrupt Mask */
-#define SPI_IMSK_CLR_TFM    0x00000800 /*Transmit Finish Interrupt Mask */
-/* SPI_IMASKST */
-#define SPI_IMSK_SET_RUWM   0x00000002 /*Receive Water-Mark Interrupt Mask */
-#define SPI_IMSK_SET_TUWM   0x00000004 /*Transmit Water-Mark Interrupt Mask */
-#define SPI_IMSK_SET_ROM    0x00000010 /*Receive Over-Run Interrupt Mask */
-#define SPI_IMSK_SET_TUM    0x00000020 /*Transmit Under-Run Interrupt Mask */
-#define SPI_IMSK_SET_TCM    0x00000040 /*Transmit Collision Interrupt Mask */
-#define SPI_IMSK_SET_MFM    0x00000080 /*Mode Fault Interrupt Mask */
-#define SPI_IMSK_SET_RSM    0x00000100 /*Receive Start Interrupt Mask */
-#define SPI_IMSK_SET_TSM    0x00000200 /*Transmit Start Interrupt Mask */
-#define SPI_IMSK_SET_RFM    0x00000400 /*Receive Finish Interrupt Mask */
-#define SPI_IMSK_SET_TFM    0x00000800 /*Transmit Finish Interrupt Mask */
-/* SPI_STATUS */
-#define SPI_STAT_SPIF       0x00000001 /*SPI Finished */
-#define SPI_STAT_RUWM       0x00000002 /*Receive Water-Mark Breached */
-#define SPI_STAT_TUWM       0x00000004 /*Transmit Water-Mark Breached */
-#define SPI_STAT_ROE        0x00000010 /*Receive Over-Run Indication */
-#define SPI_STAT_TUE        0x00000020 /*Transmit Under-Run Indication */
-#define SPI_STAT_TCE        0x00000040 /*Transmit Collision Indication */
-#define SPI_STAT_MODF       0x00000080 /*Mode Fault Indication */
-#define SPI_STAT_RS         0x00000100 /*Receive Start Indication */
-#define SPI_STAT_TS         0x00000200 /*Transmit Start Indication */
-#define SPI_STAT_RF         0x00000400 /*Receive Finish Indication */
-#define SPI_STAT_TF         0x00000800 /*Transmit Finish Indication */
-#define SPI_STAT_RFS        0x00007000 /*SPI_RFIFO status */
-#define SPI_STAT_RFIFO_EMPTY 0x00000000 /*RFS: RFIFO Empty */
-#define SPI_STAT_RFIFO_25   0x00001000 /*RFS: RFIFO 25% Full */
-#define SPI_STAT_RFIFO_50   0x00002000 /*RFS: RFIFO 50% Full */
-#define SPI_STAT_RFIFO_75   0x00003000 /*RFS: RFIFO 75% Full */
-#define SPI_STAT_RFIFO_FULL 0x00004000 /*RFS: RFIFO Full */
-#define SPI_STAT_TFS        0x00070000 /*SPI_TFIFO status */
-#define SPI_STAT_TFIFO_FULL 0x00000000 /*TFS: TFIFO full */
-#define SPI_STAT_TFIFO_25   0x00010000 /*TFS: TFIFO 25% empty */
-#define SPI_STAT_TFIFO_50   0x00020000 /*TFS: TFIFO 50% empty */
-#define SPI_STAT_TFIFO_75   0x00030000 /*TFS: TFIFO 75% empty */
-#define SPI_STAT_TFIFO_EMPTY 0x00040000 /*TFS: TFIFO empty */
-#define SPI_STAT_FCS        0x00100000 /*Flow-Control Stall Indication */
-#define SPI_STAT_RFE        0x00400000 /*SPI_RFIFO Empty */
-#define SPI_STAT_TFF        0x00800000 /*SPI_TFIFO Full */
-/* SPI_ILAT */
-#define SPI_ILAT_RUWMI      0x00000002 /*Receive Water Mark Interrupt */
-#define SPI_ILAT_TUWMI      0x00000004 /*Transmit Water Mark Interrupt */
-#define SPI_ILAT_ROI        0x00000010 /*Receive Over-Run Indication */
-#define SPI_ILAT_TUI        0x00000020 /*Transmit Under-Run Indication */
-#define SPI_ILAT_TCI        0x00000040 /*Transmit Collision Indication */
-#define SPI_ILAT_MFI        0x00000080 /*Mode Fault Indication */
-#define SPI_ILAT_RSI        0x00000100 /*Receive Start Indication */
-#define SPI_ILAT_TSI        0x00000200 /*Transmit Start Indication */
-#define SPI_ILAT_RFI        0x00000400 /*Receive Finish Indication */
-#define SPI_ILAT_TFI        0x00000800 /*Transmit Finish Indication */
-/* SPI_ILATCL */
-#define SPI_ILAT_CLR_RUWMI  0x00000002 /*Receive Water Mark Interrupt */
-#define SPI_ILAT_CLR_TUWMI  0x00000004 /*Transmit Water Mark Interrupt */
-#define SPI_ILAT_CLR_ROI    0x00000010 /*Receive Over-Run Indication */
-#define SPI_ILAT_CLR_TUI    0x00000020 /*Transmit Under-Run Indication */
-#define SPI_ILAT_CLR_TCI    0x00000040 /*Transmit Collision Indication */
-#define SPI_ILAT_CLR_MFI    0x00000080 /*Mode Fault Indication */
-#define SPI_ILAT_CLR_RSI    0x00000100 /*Receive Start Indication */
-#define SPI_ILAT_CLR_TSI    0x00000200 /*Transmit Start Indication */
-#define SPI_ILAT_CLR_RFI    0x00000400 /*Receive Finish Indication */
-#define SPI_ILAT_CLR_TFI    0x00000800 /*Transmit Finish Indication */
-
-/*
- * bfin spi3 registers layout
- */
-struct bfin_spi_regs {
-	u32 revid;
-	u32 control;
-	u32 rx_control;
-	u32 tx_control;
-	u32 clock;
-	u32 delay;
-	u32 ssel;
-	u32 rwc;
-	u32 rwcr;
-	u32 twc;
-	u32 twcr;
-	u32 reserved0;
-	u32 emask;
-	u32 emaskcl;
-	u32 emaskst;
-	u32 reserved1;
-	u32 status;
-	u32 elat;
-	u32 elatcl;
-	u32 reserved2;
-	u32 rfifo;
-	u32 reserved3;
-	u32 tfifo;
-};
-
-#endif /* _SPI_CHANNEL_H_ */
diff --git a/arch/blackfin/include/asm/mach-common/bits/timer.h b/arch/blackfin/include/asm/mach-common/bits/timer.h
deleted file mode 100644
index 9513f80..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/timer.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * General Purpose Timer Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_TIMER__
-#define __BFIN_PERIPHERAL_TIMER__
-
-/* TIMER_ENABLE Masks */
-#define TIMEN0			0x0001		/* Enable Timer 0					*/
-#define TIMEN1			0x0002		/* Enable Timer 1					*/
-#define TIMEN2			0x0004		/* Enable Timer 2					*/
-#define TIMEN3			0x0008		/* Enable Timer 3					*/
-#define TIMEN4			0x0010		/* Enable Timer 4					*/
-#define TIMEN5			0x0020		/* Enable Timer 5					*/
-#define TIMEN6			0x0040		/* Enable Timer 6					*/
-#define TIMEN7			0x0080		/* Enable Timer 7					*/
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0			TIMEN0		/* Disable Timer 0					*/
-#define TIMDIS1			TIMEN1		/* Disable Timer 1					*/
-#define TIMDIS2			TIMEN2		/* Disable Timer 2					*/
-#define TIMDIS3			TIMEN3		/* Disable Timer 3					*/
-#define TIMDIS4			TIMEN4		/* Disable Timer 4					*/
-#define TIMDIS5			TIMEN5		/* Disable Timer 5					*/
-#define TIMDIS6			TIMEN6		/* Disable Timer 6					*/
-#define TIMDIS7			TIMEN7		/* Disable Timer 7					*/
-
-/* TIMER_STATUS Masks */
-#define TIMIL0			0x00000001	/* Timer 0 Interrupt				*/
-#define TIMIL1			0x00000002	/* Timer 1 Interrupt				*/
-#define TIMIL2			0x00000004	/* Timer 2 Interrupt				*/
-#define TIMIL3			0x00000008	/* Timer 3 Interrupt				*/
-#define TOVF_ERR0		0x00000010	/* Timer 0 Counter Overflow			*/
-#define TOVF_ERR1		0x00000020	/* Timer 1 Counter Overflow			*/
-#define TOVF_ERR2		0x00000040	/* Timer 2 Counter Overflow			*/
-#define TOVF_ERR3		0x00000080	/* Timer 3 Counter Overflow			*/
-#define TRUN0			0x00001000	/* Timer 0 Slave Enable Status		*/
-#define TRUN1			0x00002000	/* Timer 1 Slave Enable Status		*/
-#define TRUN2			0x00004000	/* Timer 2 Slave Enable Status		*/
-#define TRUN3			0x00008000	/* Timer 3 Slave Enable Status		*/
-#define TIMIL4			0x00010000	/* Timer 4 Interrupt				*/
-#define TIMIL5			0x00020000	/* Timer 5 Interrupt				*/
-#define TIMIL6			0x00040000	/* Timer 6 Interrupt				*/
-#define TIMIL7			0x00080000	/* Timer 7 Interrupt				*/
-#define TOVF_ERR4		0x00100000	/* Timer 4 Counter Overflow			*/
-#define TOVF_ERR5		0x00200000	/* Timer 5 Counter Overflow			*/
-#define TOVF_ERR6		0x00400000	/* Timer 6 Counter Overflow			*/
-#define TOVF_ERR7		0x00800000	/* Timer 7 Counter Overflow			*/
-#define TRUN4			0x10000000	/* Timer 4 Slave Enable Status		*/
-#define TRUN5			0x20000000	/* Timer 5 Slave Enable Status		*/
-#define TRUN6			0x40000000	/* Timer 6 Slave Enable Status		*/
-#define TRUN7			0x80000000	/* Timer 7 Slave Enable Status		*/
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT			0x0001	/* Pulse-Width Modulation Output Mode	*/
-#define WDTH_CAP		0x0002	/* Width Capture Input Mode				*/
-#define EXT_CLK			0x0003	/* External Clock Mode					*/
-#define PULSE_HI		0x0004	/* Action Pulse (Positive/Negative*)	*/
-#define PERIOD_CNT		0x0008	/* Period Count							*/
-#define IRQ_ENA			0x0010	/* Interrupt Request Enable				*/
-#define TIN_SEL			0x0020	/* Timer Input Select					*/
-#define OUT_DIS			0x0040	/* Output Pad Disable					*/
-#define CLK_SEL			0x0080	/* Timer Clock Select					*/
-#define TOGGLE_HI		0x0100	/* PWM_OUT PULSE_HI Toggle Mode			*/
-#define EMU_RUN			0x0200	/* Emulation Behavior Select			*/
-#define ERR_TYP			0xC000	/* Error Type							*/
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/trace.h b/arch/blackfin/include/asm/mach-common/bits/trace.h
deleted file mode 100644
index 13e2134..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/trace.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Trace Unit Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_TRACE__
-#define __BFIN_PERIPHERAL_TRACE__
-
-/* Trace Buffer Control (TBUFCTL) Register Masks */
-#define TBUFPWR       0x00000001
-#define TBUFEN        0x00000002
-#define TBUFOVF       0x00000004
-#define CMPLB_SINGLE  0x00000008
-#define CMPLP_DOUBLE  0x00000010
-#define CMPLB         (CMPLB_SINGLE | CMPLP_DOUBLE)
-
-/* Trace Buffer Status (TBUFSTAT) Register Masks */
-#define TBUFCNT       0x0000001F
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/twi.h b/arch/blackfin/include/asm/mach-common/bits/twi.h
deleted file mode 100644
index 8fa7d9f..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/twi.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * TWI Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_TWI__
-#define __BFIN_PERIPHERAL_TWI__
-
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
-#define	CLKLOW(x)		((x) & 0xFF)		/* Periods Clock Is Held Low */
-#define CLKHI(y)		(((y)&0xFF)<<0x8)	/* Periods Before New Clock Low */
-
-/* TWI_PRESCALE Masks */
-#define	PRESCALE		0x007F	/* SCLKs Per Internal Time Reference (10MHz) */
-#define	TWI_ENA			0x0080	/* TWI Enable */
-#define	SCCB			0x0200	/* SCCB Compatibility Enable */
-
-/* TWI_SLAVE_CTL Masks */
-#define	SEN			0x0001	/* Slave Enable */
-#define	SADD_LEN		0x0002	/* Slave Address Length */
-#define	STDVAL			0x0004	/* Slave Transmit Data Valid */
-#define	TSC_NAK			0x0008	/* NAK/ACK* Generated At Conclusion Of Transfer */
-#define	GEN			0x0010	/* General Call Adrress Matching Enabled */
-
-/* TWI_SLAVE_STAT Masks */
-#define	SDIR			0x0001	/* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL			0x0002	/* General Call Indicator */
-
-/* TWI_MASTER_CTRL Masks */
-#define	MEN			0x0001	/* Master Mode Enable */
-#define	MADD_LEN		0x0002	/* Master Address Length */
-#define	MDIR			0x0004	/* Master Transmit Direction (RX/TX*) */
-#define	FAST			0x0008	/* Use Fast Mode Timing Specs */
-#define	STOP			0x0010	/* Issue Stop Condition */
-#define	RSTART			0x0020	/* Repeat Start or Stop* At End Of Transfer */
-#define	DCNT			0x3FC0	/* Data Bytes To Transfer */
-#define	SDAOVR			0x4000	/* Serial Data Override */
-#define	SCLOVR			0x8000	/* Serial Clock Override */
-
-/* TWI_MASTER_STAT Masks */
-#define	MPROG			0x0001	/* Master Transfer In Progress */
-#define	LOSTARB			0x0002	/* Lost Arbitration Indicator (Xfer Aborted) */
-#define	ANAK			0x0004	/* Address Not Acknowledged */
-#define	DNAK			0x0008	/* Data Not Acknowledged */
-#define	BUFRDERR		0x0010	/* Buffer Read Error */
-#define	BUFWRERR		0x0020	/* Buffer Write Error */
-#define	SDASEN			0x0040	/* Serial Data Sense */
-#define	SCLSEN			0x0080	/* Serial Clock Sense */
-#define	BUSBUSY			0x0100	/* Bus Busy Indicator */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
-#define	SINIT			0x0001	/* Slave Transfer Initiated */
-#define	SCOMP			0x0002	/* Slave Transfer Complete */
-#define	SERR			0x0004	/* Slave Transfer Error */
-#define	SOVF			0x0008	/* Slave Overflow */
-#define	MCOMP			0x0010	/* Master Transfer Complete */
-#define	MERR			0x0020	/* Master Transfer Error */
-#define	XMTSERV			0x0040	/* Transmit FIFO Service */
-#define	RCVSERV			0x0080	/* Receive FIFO Service */
-
-/* TWI_FIFO_CTRL Masks */
-#define	XMTFLUSH		0x0001	/* Transmit Buffer Flush */
-#define	RCVFLUSH		0x0002	/* Receive Buffer Flush */
-#define	XMTINTLEN		0x0004	/* Transmit Buffer Interrupt Length */
-#define	RCVINTLEN		0x0008	/* Receive Buffer Interrupt Length */
-
-/* TWI_FIFO_STAT Masks */
-#define	XMTSTAT			0x0003	/* Transmit FIFO Status */
-#define	XMT_EMPTY		0x0000	/* Transmit FIFO Empty */
-#define	XMT_HALF		0x0001	/* Transmit FIFO Has 1 Byte To Write */
-#define	XMT_FULL		0x0003	/* Transmit FIFO Full (2 Bytes To Write) */
-
-#define	RCVSTAT			0x000C	/* Receive FIFO Status */
-#define	RCV_EMPTY		0x0000	/* Receive FIFO Empty */
-#define	RCV_HALF		0x0004	/* Receive FIFO Has 1 Byte To Read */
-#define	RCV_FULL		0x000C	/* Receive FIFO Full (2 Bytes To Read) */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/uart.h b/arch/blackfin/include/asm/mach-common/bits/uart.h
deleted file mode 100644
index ac1ba11..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/uart.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * UART Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_UART__
-#define __BFIN_PERIPHERAL_UART__
-
-/* UARTx_LCR Masks */
-#define WLS			0x03	/* Word Length Select */
-#define WLS_5			0x00	/* 5 bit word */
-#define WLS_6			0x01	/* 6 bit word */
-#define WLS_7			0x02	/* 7 bit word */
-#define WLS_8			0x03	/* 8 bit word */
-#define STB			0x04	/* Stop Bits */
-#define PEN			0x08	/* Parity Enable */
-#define EPS			0x10	/* Even Parity Select */
-#define STP			0x20	/* Stick Parity */
-#define SB			0x40	/* Set Break */
-#define DLAB			0x80	/* Divisor Latch Access */
-
-#define DLAB_P			0x07
-#define SB_P			0x06
-#define STP_P			0x05
-#define EPS_P			0x04
-#define PEN_P			0x03
-#define STB_P			0x02
-#define WLS_P1			0x01
-#define WLS_P0			0x00
-
-/* UARTx_MCR Mask */
-#define XOFF			0x01	/* Transmitter off */
-#define MRTS			0x02	/* Manual Request to Send */
-#define RFIT			0x04	/* Receive FIFO IRQ Threshold */
-#define RFRT			0x08	/* Receive FIFO RTS Threshold */
-#define LOOP_ENA		0x10	/* Loopback Mode Enable */
-#define FCPOL			0x20	/* Flow Control Pin Polarity */
-#define ARTS			0x40	/* Auto RTS generation for RX handshake */
-#define ACTS			0x80	/* Auto CTS operation for TX handshake */
-
-#define XOFF_P			0
-#define MRTS_P			1
-#define RFIT_P			2
-#define RFRT_P			3
-#define LOOP_ENA_P		4
-#define FCPOL_P			5
-#define ARTS_P			6
-#define ACTS_P			7
-
-/* UARTx_LSR Masks */
-#define DR			0x01	/* Data Ready */
-#define OE			0x02	/* Overrun Error */
-#define PE			0x04	/* Parity Error */
-#define FE			0x08	/* Framing Error */
-#define BI			0x10	/* Break Interrupt */
-#define THRE			0x20	/* THR Empty */
-#define TEMT			0x40	/* TSR and UART_THR Empty */
-
-#define DR_P			0x00
-#define OE_P			0x01
-#define PE_P			0x02
-#define FE_P			0x03
-#define BI_P			0x04
-#define THRE_P			0x05
-#define TEMT_P			0x06
-
-/* UARTx_IER Masks */
-#define ERBFI			0x01	/* Enable Receive Buffer Full Interrupt */
-#define ETBEI			0x02	/* Enable Transmit Buffer Empty Interrupt */
-#define ELSI			0x04	/* Enable RX Status Interrupt */
-
-#define ERBFI_P			0x00
-#define ETBEI_P			0x01
-#define ELSI_P			0x02
-
-/* UARTx_IIR Masks */
-#define NINT			0x01	/* Pending Interrupt */
-#define STATUS			0x06	/* Highest Priority Pending Interrupt */
-
-#define NINT_P			0x00
-#define STATUS_P0		0x01
-#define STATUS_P1		0x02
-
-/* UARTx_GCTL Masks */
-#define UCEN			0x01	/* Enable UARTx Clocks */
-#define IREN			0x02	/* Enable IrDA Mode */
-#define TPOLC			0x04	/* IrDA TX Polarity Change */
-#define RPOLC			0x08	/* IrDA RX Polarity Change */
-#define FPE			0x10	/* Force Parity Error On Transmit */
-#define FFE			0x20	/* Force Framing Error On Transmit */
-
-#define UCEN_P			0x00
-#define IREN_P			0x01
-#define TPOLC_P			0x02
-#define RPOLC_P			0x03
-#define FPE_P			0x04
-#define FFE_P			0x05
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/uart4.h b/arch/blackfin/include/asm/mach-common/bits/uart4.h
deleted file mode 100644
index 37808de..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/uart4.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * UART4 Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_UART4__
-#define __BFIN_PERIPHERAL_UART4__
-
-/* UART_CONTROL */
-#define UEN			(1 << 0)
-#define LOOP_ENA		(1 << 1)
-#define UMOD			(3 << 4)
-#define UMOD_UART		(0 << 4)
-#define UMOD_MDB		(1 << 4)
-#define UMOD_IRDA		(1 << 4)
-#define WLS			(3 << 8)
-#define WLS_5			(0 << 8)
-#define WLS_6			(1 << 8)
-#define WLS_7			(2 << 8)
-#define WLS_8			(3 << 8)
-#define STB			(1 << 12)
-#define STBH			(1 << 13)
-#define PEN			(1 << 14)
-#define EPS			(1 << 15)
-#define STP			(1 << 16)
-#define FPE			(1 << 17)
-#define FFE			(1 << 18)
-#define SB			(1 << 19)
-#define FCPOL			(1 << 22)
-#define RPOLC			(1 << 23)
-#define TPOLC			(1 << 24)
-#define MRTS			(1 << 25)
-#define XOFF			(1 << 26)
-#define ARTS			(1 << 27)
-#define ACTS			(1 << 28)
-#define RFIT			(1 << 29)
-#define RFRT			(1 << 30)
-
-/* UART_STATUS */
-#define DR			(1 << 0)
-#define OE			(1 << 1)
-#define PE			(1 << 2)
-#define FE			(1 << 3)
-#define BI			(1 << 4)
-#define THRE			(1 << 5)
-#define TEMT			(1 << 7)
-#define TFI			(1 << 8)
-#define ASTKY			(1 << 9)
-#define ADDR			(1 << 10)
-#define RO			(1 << 11)
-#define SCTS			(1 << 12)
-#define CTS			(1 << 16)
-#define RFCS			(1 << 17)
-
-/* UART_EMASK */
-#define ERBFI			(1 << 0)
-#define ETBEI			(1 << 1)
-#define ELSI			(1 << 2)
-#define EDSSI			(1 << 3)
-#define EDTPTI			(1 << 4)
-#define ETFI			(1 << 5)
-#define ERFCI			(1 << 6)
-#define EAWI			(1 << 7)
-#define ERXS			(1 << 8)
-#define ETXS			(1 << 9)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/usb.h b/arch/blackfin/include/asm/mach-common/bits/usb.h
deleted file mode 100644
index c639058..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/usb.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * USB Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_USB__
-#define __BFIN_PERIPHERAL_USB__
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS	0x7f	/* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM		0x1	/* enable SuspendM output */
-#define SUSPEND_MODE		0x2	/* Suspend Mode indicator */
-#define RESUME_MODE		0x4	/* DMA Mode */
-#define RESET			0x8	/* Reset indicator */
-#define HS_MODE			0x10	/* High Speed mode indicator */
-#define HS_ENABLE		0x20	/* high Speed Enable */
-#define SOFT_CONN		0x40	/* Soft connect */
-#define ISO_UPDATE		0x80	/* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX			0x1	/* Tx Endpoint 0 interrupt */
-#define EP1_TX			0x2	/* Tx Endpoint 1 interrupt */
-#define EP2_TX			0x4	/* Tx Endpoint 2 interrupt */
-#define EP3_TX			0x8	/* Tx Endpoint 3 interrupt */
-#define EP4_TX			0x10	/* Tx Endpoint 4 interrupt */
-#define EP5_TX			0x20	/* Tx Endpoint 5 interrupt */
-#define EP6_TX			0x40	/* Tx Endpoint 6 interrupt */
-#define EP7_TX			0x80	/* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX			0x2	/* Rx Endpoint 1 interrupt */
-#define EP2_RX			0x4	/* Rx Endpoint 2 interrupt */
-#define EP3_RX			0x8	/* Rx Endpoint 3 interrupt */
-#define EP4_RX			0x10	/* Rx Endpoint 4 interrupt */
-#define EP5_RX			0x20	/* Rx Endpoint 5 interrupt */
-#define EP6_RX			0x40	/* Rx Endpoint 6 interrupt */
-#define EP7_RX			0x80	/* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E		0x1	/* Endpoint 0 interrupt Enable */
-#define EP1_TX_E		0x2	/* Tx Endpoint 1 interrupt enable */
-#define EP2_TX_E		0x4	/* Tx Endpoint 2 interrupt enable */
-#define EP3_TX_E		0x8	/* Tx Endpoint 3 interrupt enable */
-#define EP4_TX_E		0x10	/* Tx Endpoint 4 interrupt enable */
-#define EP5_TX_E		0x20	/* Tx Endpoint 5 interrupt enable */
-#define EP6_TX_E		0x40	/* Tx Endpoint 6 interrupt enable */
-#define EP7_TX_E		0x80	/* Tx Endpoint 7 interrupt enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E		0x02	/* Rx Endpoint 1 interrupt enable */
-#define EP2_RX_E		0x04	/* Rx Endpoint 2 interrupt enable */
-#define EP3_RX_E		0x08	/* Rx Endpoint 3 interrupt enable */
-#define EP4_RX_E		0x10	/* Rx Endpoint 4 interrupt enable */
-#define EP5_RX_E		0x20	/* Rx Endpoint 5 interrupt enable */
-#define EP6_RX_E		0x40	/* Rx Endpoint 6 interrupt enable */
-#define EP7_RX_E		0x80	/* Rx Endpoint 7 interrupt enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B		0x01	/* Suspend indicator */
-#define RESUME_B		0x02	/* Resume indicator */
-#define RESET_OR_BABLE_B	0x04	/* Reset/babble indicator */
-#define SOF_B			0x08	/* Start of frame */
-#define CONN_B			0x10	/* Connection indicator */
-#define DISCON_B		0x20	/* Disconnect indicator */
-#define SESSION_REQ_B		0x40	/* Session Request */
-#define VBUS_ERROR_B		0x80	/* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE		0x01	/* Suspend indicator int enable */
-#define RESUME_BE		0x02	/* Resume indicator int enable */
-#define RESET_OR_BABLE_BE	0x04	/* Reset/babble indicator int enable */
-#define SOF_BE			0x08	/* Start of frame int enable */
-#define CONN_BE			0x10	/* Connection indicator int enable */
-#define DISCON_BE		0x20	/* Disconnect indicator int enable */
-#define SESSION_REQ_BE		0x40	/* Session Request int enable */
-#define VBUS_ERROR_BE		0x80	/* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER		0x7ff	/* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT	0xf	/* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA		0x0001	/* enables USB module */
-#define EP1_TX_ENA		0x0002	/* Transmit endpoint 1 enable */
-#define EP2_TX_ENA		0x0004	/* Transmit endpoint 2 enable */
-#define EP3_TX_ENA		0x0008	/* Transmit endpoint 3 enable */
-#define EP4_TX_ENA		0x0010	/* Transmit endpoint 4 enable */
-#define EP5_TX_ENA		0x0020	/* Transmit endpoint 5 enable */
-#define EP6_TX_ENA		0x0040	/* Transmit endpoint 6 enable */
-#define EP7_TX_ENA		0x0080	/* Transmit endpoint 7 enable */
-#define EP1_RX_ENA		0x0100	/* Receive endpoint 1 enable */
-#define EP2_RX_ENA		0x0200	/* Receive endpoint 2 enable */
-#define EP3_RX_ENA		0x0400	/* Receive endpoint 3 enable */
-#define EP4_RX_ENA		0x0800	/* Receive endpoint 4 enable */
-#define EP5_RX_ENA		0x1000	/* Receive endpoint 5 enable */
-#define EP6_RX_ENA		0x2000	/* Receive endpoint 6 enable */
-#define EP7_RX_ENA		0x4000	/* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION			0x1	/* session indicator */
-#define HOST_REQ		0x2	/* Host negotiation request */
-#define HOST_MODE		0x4	/* indicates USBDRC is a host */
-#define VBUS0			0x8	/* Vbus level indicator[0] */
-#define VBUS1			0x10	/* Vbus level indicator[1] */
-#define LSDEV			0x20	/* Low-speed indicator */
-#define FSDEV			0x40	/* Full or High-speed indicator */
-#define B_DEVICE		0x80	/* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON		0x1	/* indicator to drive VBUS control circuit */
-#define DRIVE_VBUS_OFF		0x2	/* indicator to shut off charge pump */
-#define CHRG_VBUS_START		0x4	/* indicator for external circuit to start charging VBUS */
-#define CHRG_VBUS_END		0x8	/* indicator for external circuit to end charging VBUS */
-#define DISCHRG_VBUS_START	0x10	/* indicator to start discharging VBUS */
-#define DISCHRG_VBUS_END	0x20	/* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA	0x01	/* enable DRIVE_VBUS_ON interrupt */
-#define DRIVE_VBUS_OFF_ENA	0x02	/* enable DRIVE_VBUS_OFF interrupt */
-#define CHRG_VBUS_START_ENA	0x04	/* enable CHRG_VBUS_START interrupt */
-#define CHRG_VBUS_END_ENA	0x08	/* enable CHRG_VBUS_END interrupt */
-#define DISCHRG_VBUS_START_ENA	0x10	/* enable DISCHRG_VBUS_START interrupt */
-#define DISCHRG_VBUS_END_ENA	0x20	/* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY		0x1	/* data packet receive indicator */
-#define TXPKTRDY		0x2	/* data packet in FIFO indicator */
-#define STALL_SENT		0x4	/* STALL handshake sent */
-#define DATAEND			0x8	/* Data end indicator */
-#define SETUPEND		0x10	/* Setup end */
-#define SENDSTALL		0x20	/* Send STALL handshake */
-#define SERVICED_RXPKTRDY	0x40	/* used to clear the RxPktRdy bit */
-#define SERVICED_SETUPEND	0x80	/* used to clear the SetupEnd bit */
-#define FLUSHFIFO		0x100	/* flush endpoint FIFO */
-#define STALL_RECEIVED_H	0x4	/* STALL handshake received host mode */
-#define SETUPPKT_H		0x8	/* send Setup token host mode */
-#define ERROR_H			0x10	/* timeout error indicator host mode */
-#define REQPKT_H		0x20	/* Request an IN transaction host mode */
-#define STATUSPKT_H		0x40	/* Status stage transaction host mode */
-#define NAK_TIMEOUT_H		0x80	/* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT		0x7f	/* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT		0x1f	/* frames/micro frames count after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T	0x7ff	/* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R	0x7ff	/* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T		0x1	/* data packet in FIFO indicator */
-#define FIFO_NOT_EMPTY_T	0x2	/* FIFO not empty */
-#define UNDERRUN_T		0x4	/* TxPktRdy not set for an IN token */
-#define FLUSHFIFO_T		0x8	/* flush endpoint FIFO */
-#define STALL_SEND_T		0x10	/* issue a Stall handshake */
-#define STALL_SENT_T		0x20	/* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_T	0x40	/* clear endpoint data toggle */
-#define INCOMPTX_T		0x80	/* indicates that a large packet is split */
-#define DMAREQMODE_T		0x400	/* DMA mode (0 or 1) selection */
-#define FORCE_DATATOGGLE_T	0x800	/* Force data toggle */
-#define DMAREQ_ENA_T		0x1000	/* Enable DMA request for Tx EP */
-#define ISO_T			0x4000	/* enable Isochronous transfers */
-#define AUTOSET_T		0x8000	/* allows TxPktRdy to be set automatically */
-#define ERROR_TH		0x4	/* error condition host mode */
-#define STALL_RECEIVED_TH	0x20	/* Stall handshake received host mode */
-#define NAK_TIMEOUT_TH		0x80	/* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT		0x1fff	/* Byte len for the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R		0x1	/* data packet in FIFO indicator */
-#define FIFO_FULL_R		0x2	/* FIFO not empty */
-#define OVERRUN_R		0x4	/* TxPktRdy not set for an IN token */
-#define DATAERROR_R		0x8	/* Out packet cannot be loaded into Rx FIFO */
-#define FLUSHFIFO_R		0x10	/* flush endpoint FIFO */
-#define STALL_SEND_R		0x20	/* issue a Stall handshake */
-#define STALL_SENT_R		0x40	/* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_R	0x80	/* clear endpoint data toggle */
-#define INCOMPRX_R		0x100	/* indicates that a large packet is split */
-#define DMAREQMODE_R		0x800	/* DMA mode (0 or 1) selection */
-#define DISNYET_R		0x1000	/* disable Nyet handshakes */
-#define DMAREQ_ENA_R		0x2000	/* Enable DMA request for Tx EP */
-#define ISO_R			0x4000	/* enable Isochronous transfers */
-#define AUTOCLEAR_R		0x8000	/* allows TxPktRdy to be set automatically */
-#define ERROR_RH		0x4	/* TxPktRdy not set for an IN token host mode */
-#define REQPKT_RH		0x20	/* request an IN transaction host mode */
-#define STALL_RECEIVED_RH	0x40	/* Stall handshake received host mode */
-#define INCOMPRX_RH		0x100	/* large packet is split host mode */
-#define DMAREQMODE_RH		0x800	/* DMA mode (0 or 1) selection host mode */
-#define AUTOREQ_RH		0x4000	/* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT		0x1fff	/* Packet byte len in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T		0xf	/* EP number */
-#define PROTOCOL_T		0xc	/* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL	0xff	/* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R		0xf	/* EP number */
-#define PROTOCOL_R		0xc	/* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL	0xff	/* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT		0x1	/* DMA0 pending interrupt */
-#define DMA1_INT		0x2	/* DMA1 pending interrupt */
-#define DMA2_INT		0x4	/* DMA2 pending interrupt */
-#define DMA3_INT		0x8	/* DMA3 pending interrupt */
-#define DMA4_INT		0x10	/* DMA4 pending interrupt */
-#define DMA5_INT		0x20	/* DMA5 pending interrupt */
-#define DMA6_INT		0x40	/* DMA6 pending interrupt */
-#define DMA7_INT		0x80	/* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA			0x1	/* DMA enable */
-#define DIRECTION		0x2	/* direction of DMA transfer */
-#define MODE			0x4	/* DMA Bus error */
-#define INT_ENA			0x8	/* Interrupt enable */
-#define EPNUM			0xf0	/* EP number */
-#define BUSERROR		0x100	/* DMA Bus error */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/watchdog.h b/arch/blackfin/include/asm/mach-common/bits/watchdog.h
deleted file mode 100644
index 75924f9..0000000
--- a/arch/blackfin/include/asm/mach-common/bits/watchdog.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Watchdog Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_WATCHDOG__
-#define __BFIN_PERIPHERAL_WATCHDOG__
-
-/* Watchdog Timer WDOG_CTL Register Masks */
-
-#define WDEV			0x0006	/* event generated on roll over */
-#define WDEV_RESET		0x0000	/* generate reset event on roll over */
-#define WDEV_NMI		0x0002	/* generate NMI event on roll over */
-#define WDEV_GPI		0x0004	/* generate GP IRQ on roll over */
-#define WDEV_NONE		0x0006	/* no event on roll over */
-#define WDEN			0x0FF0	/* enable watchdog */
-#define WDDIS			0x0AD0	/* disable watchdog */
-#define WDRO			0x8000	/* watchdog rolled over latch */
-
-#endif
diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h
deleted file mode 100644
index 3e361d6..0000000
--- a/arch/blackfin/include/asm/mem_map.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Common Blackfin memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MEM_MAP_H__
-#define __BFIN_MEM_MAP_H__
-
-/* Every Blackfin so far has MMRs like this */
-#ifndef COREMMR_BASE
-# define COREMMR_BASE 0xFFE00000
-#endif
-#ifndef SYSMMR_BASE
-# define SYSMMR_BASE  0xFFC00000
-#endif
-
-/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */
-#ifndef L1_SRAM_SCRATCH
-# define L1_SRAM_SCRATCH      0xFFB00000
-# define L1_SRAM_SCRATCH_SIZE 0x1000
-# define L1_SRAM_SCRATCH_END  (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
deleted file mode 100644
index 003694b..0000000
--- a/arch/blackfin/include/asm/portmux.h
+++ /dev/null
@@ -1,1193 +0,0 @@
-/*
- * Common header file for Blackfin family of processors
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _PORTMUX_H_
-#define _PORTMUX_H_
-
-#define P_IDENT(x)	((x) & 0x1FF)
-#define P_FUNCT(x)	(((x) & 0x3) << 9)
-#define P_FUNCT2MUX(x)	(((x) >> 9) & 0x3)
-#define P_DEFINED	0x8000
-#define P_UNDEF		0x4000
-#define P_MAYSHARE	0x2000
-#define P_DONTCARE	0x1000
-
-#ifndef __ASSEMBLY__
-
-int peripheral_request(unsigned short per, const char *label);
-void peripheral_free(unsigned short per);
-int peripheral_request_list(const unsigned short per[], const char *label);
-void peripheral_free_list(const unsigned short per[]);
-
-#endif
-
-#include <asm/blackfin.h>
-
-#ifndef P_SPORT2_TFS
-#define P_SPORT2_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTSEC
-#define P_SPORT2_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTPRI
-#define P_SPORT2_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_TSCLK
-#define P_SPORT2_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RFS
-#define P_SPORT2_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRSEC
-#define P_SPORT2_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRPRI
-#define P_SPORT2_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RSCLK
-#define P_SPORT2_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TFS
-#define P_SPORT3_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTSEC
-#define P_SPORT3_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTPRI
-#define P_SPORT3_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TSCLK
-#define P_SPORT3_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RFS
-#define P_SPORT3_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRSEC
-#define P_SPORT3_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRPRI
-#define P_SPORT3_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RSCLK
-#define P_SPORT3_RSCLK P_UNDEF
-#endif
-
-#ifndef P_TMR4
-#define P_TMR4 P_UNDEF
-#endif
-
-#ifndef P_TMR5
-#define P_TMR5 P_UNDEF
-#endif
-
-#ifndef P_TMR6
-#define P_TMR6 P_UNDEF
-#endif
-
-#ifndef P_TMR7
-#define P_TMR7 P_UNDEF
-#endif
-
-#ifndef P_TWI1_SCL
-#define P_TWI1_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI1_SDA
-#define P_TWI1_SDA P_UNDEF
-#endif
-
-#ifndef P_UART3_RTS
-#define P_UART3_RTS P_UNDEF
-#endif
-
-#ifndef P_UART3_CTS
-#define P_UART3_CTS P_UNDEF
-#endif
-
-#ifndef P_UART2_TX
-#define P_UART2_TX P_UNDEF
-#endif
-
-#ifndef P_UART2_RX
-#define P_UART2_RX P_UNDEF
-#endif
-
-#ifndef P_UART3_TX
-#define P_UART3_TX P_UNDEF
-#endif
-
-#ifndef P_UART3_RX
-#define P_UART3_RX P_UNDEF
-#endif
-
-#ifndef P_SPI2_SS
-#define P_SPI2_SS P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL1
-#define P_SPI2_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL2
-#define P_SPI2_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL3
-#define P_SPI2_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL4
-#define P_SPI2_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL5
-#define P_SPI2_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL6
-#define P_SPI2_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL7
-#define P_SPI2_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SCK
-#define P_SPI2_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI2_MOSI
-#define P_SPI2_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI2_MISO
-#define P_SPI2_MISO P_UNDEF
-#endif
-
-#ifndef P_TMR0
-#define P_TMR0 P_UNDEF
-#endif
-
-#ifndef P_TMR1
-#define P_TMR1 P_UNDEF
-#endif
-
-#ifndef P_TMR2
-#define P_TMR2 P_UNDEF
-#endif
-
-#ifndef P_TMR3
-#define P_TMR3 P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TFS
-#define P_SPORT0_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTSEC
-#define P_SPORT0_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTPRI
-#define P_SPORT0_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TSCLK
-#define P_SPORT0_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RFS
-#define P_SPORT0_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRSEC
-#define P_SPORT0_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRPRI
-#define P_SPORT0_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RSCLK
-#define P_SPORT0_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SD_D0
-#define P_SD_D0 P_UNDEF
-#endif
-
-#ifndef P_SD_D1
-#define P_SD_D1 P_UNDEF
-#endif
-
-#ifndef P_SD_D2
-#define P_SD_D2 P_UNDEF
-#endif
-
-#ifndef P_SD_D3
-#define P_SD_D3 P_UNDEF
-#endif
-
-#ifndef P_SD_CLK
-#define P_SD_CLK P_UNDEF
-#endif
-
-#ifndef P_SD_CMD
-#define P_SD_CMD P_UNDEF
-#endif
-
-#ifndef P_MMCLK
-#define P_MMCLK P_UNDEF
-#endif
-
-#ifndef P_MBCLK
-#define P_MBCLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_D0
-#define P_PPI1_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D1
-#define P_PPI1_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D2
-#define P_PPI1_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D3
-#define P_PPI1_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D4
-#define P_PPI1_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D5
-#define P_PPI1_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D6
-#define P_PPI1_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D7
-#define P_PPI1_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D8
-#define P_PPI1_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D9
-#define P_PPI1_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D10
-#define P_PPI1_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D11
-#define P_PPI1_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D12
-#define P_PPI1_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D13
-#define P_PPI1_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D14
-#define P_PPI1_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D15
-#define P_PPI1_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D8
-#define P_HOST_D8 P_UNDEF
-#endif
-
-#ifndef P_HOST_D9
-#define P_HOST_D9 P_UNDEF
-#endif
-
-#ifndef P_HOST_D10
-#define P_HOST_D10 P_UNDEF
-#endif
-
-#ifndef P_HOST_D11
-#define P_HOST_D11 P_UNDEF
-#endif
-
-#ifndef P_HOST_D12
-#define P_HOST_D12 P_UNDEF
-#endif
-
-#ifndef P_HOST_D13
-#define P_HOST_D13 P_UNDEF
-#endif
-
-#ifndef P_HOST_D14
-#define P_HOST_D14 P_UNDEF
-#endif
-
-#ifndef P_HOST_D15
-#define P_HOST_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D0
-#define P_HOST_D0 P_UNDEF
-#endif
-
-#ifndef P_HOST_D1
-#define P_HOST_D1 P_UNDEF
-#endif
-
-#ifndef P_HOST_D2
-#define P_HOST_D2 P_UNDEF
-#endif
-
-#ifndef P_HOST_D3
-#define P_HOST_D3 P_UNDEF
-#endif
-
-#ifndef P_HOST_D4
-#define P_HOST_D4 P_UNDEF
-#endif
-
-#ifndef P_HOST_D5
-#define P_HOST_D5 P_UNDEF
-#endif
-
-#ifndef P_HOST_D6
-#define P_HOST_D6 P_UNDEF
-#endif
-
-#ifndef P_HOST_D7
-#define P_HOST_D7 P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TFS
-#define P_SPORT1_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTSEC
-#define P_SPORT1_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTPRI
-#define P_SPORT1_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TSCLK
-#define P_SPORT1_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RFS
-#define P_SPORT1_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRSEC
-#define P_SPORT1_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRPRI
-#define P_SPORT1_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RSCLK
-#define P_SPORT1_RSCLK P_UNDEF
-#endif
-
-#ifndef P_PPI2_D0
-#define P_PPI2_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D1
-#define P_PPI2_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D2
-#define P_PPI2_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D3
-#define P_PPI2_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D4
-#define P_PPI2_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D5
-#define P_PPI2_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D6
-#define P_PPI2_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D7
-#define P_PPI2_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D18
-#define P_PPI0_D18 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D19
-#define P_PPI0_D19 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D20
-#define P_PPI0_D20 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D21
-#define P_PPI0_D21 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D22
-#define P_PPI0_D22 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D23
-#define P_PPI0_D23 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW0
-#define P_KEY_ROW0 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW1
-#define P_KEY_ROW1 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW2
-#define P_KEY_ROW2 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW3
-#define P_KEY_ROW3 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL0
-#define P_KEY_COL0 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL1
-#define P_KEY_COL1 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL2
-#define P_KEY_COL2 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL3
-#define P_KEY_COL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SCK
-#define P_SPI0_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI0_MISO
-#define P_SPI0_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI0_MOSI
-#define P_SPI0_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI0_SS
-#define P_SPI0_SS P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL1
-#define P_SPI0_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL2
-#define P_SPI0_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL3
-#define P_SPI0_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL4
-#define P_SPI0_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL5
-#define P_SPI0_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL6
-#define P_SPI0_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL7
-#define P_SPI0_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_UART0_TX
-#define P_UART0_TX P_UNDEF
-#endif
-
-#ifndef P_UART0_RX
-#define P_UART0_RX P_UNDEF
-#endif
-
-#ifndef P_UART1_RTS
-#define P_UART1_RTS P_UNDEF
-#endif
-
-#ifndef P_UART1_CTS
-#define P_UART1_CTS P_UNDEF
-#endif
-
-#ifndef P_PPI1_CLK
-#define P_PPI1_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS1
-#define P_PPI1_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS2
-#define P_PPI1_FS2 P_UNDEF
-#endif
-
-#ifndef P_TWI0_SCL
-#define P_TWI0_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI0_SDA
-#define P_TWI0_SDA P_UNDEF
-#endif
-
-#ifndef P_KEY_COL7
-#define P_KEY_COL7 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW6
-#define P_KEY_ROW6 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL6
-#define P_KEY_COL6 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW5
-#define P_KEY_ROW5 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL5
-#define P_KEY_COL5 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW4
-#define P_KEY_ROW4 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL4
-#define P_KEY_COL4 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW7
-#define P_KEY_ROW7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D0
-#define P_PPI0_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D1
-#define P_PPI0_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D2
-#define P_PPI0_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D3
-#define P_PPI0_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D4
-#define P_PPI0_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D5
-#define P_PPI0_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D6
-#define P_PPI0_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D7
-#define P_PPI0_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D8
-#define P_PPI0_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D9
-#define P_PPI0_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D10
-#define P_PPI0_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D11
-#define P_PPI0_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D12
-#define P_PPI0_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D13
-#define P_PPI0_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D14
-#define P_PPI0_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D15
-#define P_PPI0_D15 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D0A
-#define P_ATAPI_D0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D1A
-#define P_ATAPI_D1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D2A
-#define P_ATAPI_D2A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D3A
-#define P_ATAPI_D3A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D4A
-#define P_ATAPI_D4A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D5A
-#define P_ATAPI_D5A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D6A
-#define P_ATAPI_D6A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D7A
-#define P_ATAPI_D7A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D8A
-#define P_ATAPI_D8A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D9A
-#define P_ATAPI_D9A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D10A
-#define P_ATAPI_D10A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D11A
-#define P_ATAPI_D11A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D12A
-#define P_ATAPI_D12A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D13A
-#define P_ATAPI_D13A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D14A
-#define P_ATAPI_D14A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D15A
-#define P_ATAPI_D15A P_UNDEF
-#endif
-
-#ifndef P_PPI0_CLK
-#define P_PPI0_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS1
-#define P_PPI0_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS2
-#define P_PPI0_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D16
-#define P_PPI0_D16 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D17
-#define P_PPI0_D17 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL1
-#define P_SPI1_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL2
-#define P_SPI1_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL3
-#define P_SPI1_SSEL3 P_UNDEF
-#endif
-
-
-#ifndef P_SPI1_SSEL4
-#define P_SPI1_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL5
-#define P_SPI1_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL6
-#define P_SPI1_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL7
-#define P_SPI1_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SCK
-#define P_SPI1_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI1_MISO
-#define P_SPI1_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI1_MOSI
-#define P_SPI1_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI1_SS
-#define P_SPI1_SS P_UNDEF
-#endif
-
-#ifndef P_CAN0_TX
-#define P_CAN0_TX P_UNDEF
-#endif
-
-#ifndef P_CAN0_RX
-#define P_CAN0_RX P_UNDEF
-#endif
-
-#ifndef P_CAN1_TX
-#define P_CAN1_TX P_UNDEF
-#endif
-
-#ifndef P_CAN1_RX
-#define P_CAN1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A0A
-#define P_ATAPI_A0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A1A
-#define P_ATAPI_A1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A2A
-#define P_ATAPI_A2A P_UNDEF
-#endif
-
-#ifndef P_HOST_CE
-#define P_HOST_CE P_UNDEF
-#endif
-
-#ifndef P_HOST_RD
-#define P_HOST_RD P_UNDEF
-#endif
-
-#ifndef P_HOST_WR
-#define P_HOST_WR P_UNDEF
-#endif
-
-#ifndef P_MTXONB
-#define P_MTXONB P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS2
-#define P_PPI2_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS1
-#define P_PPI2_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_CLK
-#define P_PPI2_CLK P_UNDEF
-#endif
-
-#ifndef P_CNT_CZM
-#define P_CNT_CZM P_UNDEF
-#endif
-
-#ifndef P_UART1_TX
-#define P_UART1_TX P_UNDEF
-#endif
-
-#ifndef P_UART1_RX
-#define P_UART1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_RESET
-#define P_ATAPI_RESET P_UNDEF
-#endif
-
-#ifndef P_HOST_ADDR
-#define P_HOST_ADDR P_UNDEF
-#endif
-
-#ifndef P_HOST_ACK
-#define P_HOST_ACK P_UNDEF
-#endif
-
-#ifndef P_MTX
-#define P_MTX P_UNDEF
-#endif
-
-#ifndef P_MRX
-#define P_MRX P_UNDEF
-#endif
-
-#ifndef P_MRXONB
-#define P_MRXONB P_UNDEF
-#endif
-
-#ifndef P_A4
-#define P_A4 P_UNDEF
-#endif
-
-#ifndef P_A5
-#define P_A5 P_UNDEF
-#endif
-
-#ifndef P_A6
-#define P_A6 P_UNDEF
-#endif
-
-#ifndef P_A7
-#define P_A7 P_UNDEF
-#endif
-
-#ifndef P_A8
-#define P_A8 P_UNDEF
-#endif
-
-#ifndef P_A9
-#define P_A9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS3
-#define P_PPI1_FS3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS3
-#define P_PPI2_FS3 P_UNDEF
-#endif
-
-#ifndef P_TMR8
-#define P_TMR8 P_UNDEF
-#endif
-
-#ifndef P_TMR9
-#define P_TMR9 P_UNDEF
-#endif
-
-#ifndef P_TMR10
-#define P_TMR10 P_UNDEF
-#endif
-#ifndef P_TMR11
-#define P_TMR11 P_UNDEF
-#endif
-
-#ifndef P_DMAR0
-#define P_DMAR0 P_UNDEF
-#endif
-
-#ifndef P_DMAR1
-#define P_DMAR1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS3
-#define P_PPI0_FS3 P_UNDEF
-#endif
-
-#ifndef P_CNT_CDG
-#define P_CNT_CDG P_UNDEF
-#endif
-
-#ifndef P_CNT_CUD
-#define P_CNT_CUD P_UNDEF
-#endif
-
-#ifndef P_A10
-#define P_A10 P_UNDEF
-#endif
-
-#ifndef P_A11
-#define P_A11 P_UNDEF
-#endif
-
-#ifndef P_A12
-#define P_A12 P_UNDEF
-#endif
-
-#ifndef P_A13
-#define P_A13 P_UNDEF
-#endif
-
-#ifndef P_A14
-#define P_A14 P_UNDEF
-#endif
-
-#ifndef P_A15
-#define P_A15 P_UNDEF
-#endif
-
-#ifndef P_A16
-#define P_A16 P_UNDEF
-#endif
-
-#ifndef P_A17
-#define P_A17 P_UNDEF
-#endif
-
-#ifndef P_A18
-#define P_A18 P_UNDEF
-#endif
-
-#ifndef P_A19
-#define P_A19 P_UNDEF
-#endif
-
-#ifndef P_A20
-#define P_A20 P_UNDEF
-#endif
-
-#ifndef P_A21
-#define P_A21 P_UNDEF
-#endif
-
-#ifndef P_A22
-#define P_A22 P_UNDEF
-#endif
-
-#ifndef P_A23
-#define P_A23 P_UNDEF
-#endif
-
-#ifndef P_A24
-#define P_A24 P_UNDEF
-#endif
-
-#ifndef P_A25
-#define P_A25 P_UNDEF
-#endif
-
-#ifndef P_NOR_CLK
-#define P_NOR_CLK P_UNDEF
-#endif
-
-#ifndef P_TMRCLK
-#define P_TMRCLK P_UNDEF
-#endif
-
-#ifndef P_AMC_ARDY_NOR_WAIT
-#define P_AMC_ARDY_NOR_WAIT P_UNDEF
-#endif
-
-#ifndef P_NAND_CE
-#define P_NAND_CE P_UNDEF
-#endif
-
-#ifndef P_NAND_RB
-#define P_NAND_RB P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOR
-#define P_ATAPI_DIOR P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOW
-#define P_ATAPI_DIOW P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS0
-#define P_ATAPI_CS0 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS1
-#define P_ATAPI_CS1 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMACK
-#define P_ATAPI_DMACK P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMARQ
-#define P_ATAPI_DMARQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_INTRQ
-#define P_ATAPI_INTRQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_IORDY
-#define P_ATAPI_IORDY P_UNDEF
-#endif
-
-#ifndef P_AMC_BR
-#define P_AMC_BR P_UNDEF
-#endif
-
-#ifndef P_AMC_BG
-#define P_AMC_BG P_UNDEF
-#endif
-
-#ifndef P_AMC_BGH
-#define P_AMC_BGH P_UNDEF
-#endif
-
-/* EMAC */
-
-#ifndef P_MII0_ETxD0
-#define P_MII0_ETxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD1
-#define P_MII0_ETxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD2
-#define P_MII0_ETxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD3
-#define P_MII0_ETxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxEN
-#define P_MII0_ETxEN P_UNDEF
-#endif
-
-#ifndef P_MII0_TxCLK
-#define P_MII0_TxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_PHYINT
-#define P_MII0_PHYINT P_UNDEF
-#endif
-
-#ifndef P_MII0_COL
-#define P_MII0_COL P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD0
-#define P_MII0_ERxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD1
-#define P_MII0_ERxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD2
-#define P_MII0_ERxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD3
-#define P_MII0_ERxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxDV
-#define P_MII0_ERxDV P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxCLK
-#define P_MII0_ERxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxER
-#define P_MII0_ERxER P_UNDEF
-#endif
-
-#ifndef P_MII0_CRS
-#define P_MII0_CRS P_UNDEF
-#endif
-
-#ifndef P_RMII0_REF_CLK
-#define P_RMII0_REF_CLK P_UNDEF
-#endif
-
-#ifndef P_RMII0_MDINT
-#define P_RMII0_MDINT P_UNDEF
-#endif
-
-#ifndef P_RMII0_CRS_DV
-#define P_RMII0_CRS_DV P_UNDEF
-#endif
-
-#ifndef P_MDC
-#define P_MDC P_UNDEF
-#endif
-
-#ifndef P_MDIO
-#define P_MDIO P_UNDEF
-#endif
-
-#endif				/* _PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/posix_types.h b/arch/blackfin/include/asm/posix_types.h
deleted file mode 100644
index 8535235..0000000
--- a/arch/blackfin/include/asm/posix_types.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * U-Boot - posix_types.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ARCH_BLACKFIN_POSIX_TYPES_H
-#define __ARCH_BLACKFIN_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned short __kernel_dev_t;
-typedef unsigned long __kernel_ino_t;
-typedef unsigned short __kernel_mode_t;
-typedef unsigned short __kernel_nlink_t;
-typedef long __kernel_off_t;
-typedef int __kernel_pid_t;
-typedef unsigned int __kernel_ipc_pid_t;
-typedef unsigned int __kernel_uid_t;
-typedef unsigned int __kernel_gid_t;
-typedef unsigned long __kernel_size_t;
-typedef long __kernel_ssize_t;
-typedef int __kernel_ptrdiff_t;
-typedef long __kernel_time_t;
-typedef long __kernel_suseconds_t;
-typedef long __kernel_clock_t;
-typedef int __kernel_timer_t;
-typedef int __kernel_clockid_t;
-typedef int __kernel_daddr_t;
-typedef char *__kernel_caddr_t;
-typedef unsigned short __kernel_uid16_t;
-typedef unsigned short __kernel_gid16_t;
-typedef unsigned int __kernel_uid32_t;
-typedef unsigned int __kernel_gid32_t;
-
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-
-#ifdef __GNUC__
-typedef long long __kernel_loff_t;
-#endif
-
-typedef struct {
-	int val[2];
-} __kernel_fsid_t;
-
-#if defined(__KERNEL__)
-
-#undef	__FD_SET
-#define	__FD_SET(d, set)	((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
-
-#undef	__FD_CLR
-#define	__FD_CLR(d, set)	((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
-
-#undef	__FD_ISSET
-#define	__FD_ISSET(d, set)	((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
-
-#undef	__FD_ZERO
-#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
-
-#endif				/* defined(__KERNEL__) */
-
-#endif
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
deleted file mode 100644
index 1daf59b..0000000
--- a/arch/blackfin/include/asm/processor.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * U-Boot - processor.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * include/asm-m68k/processor.h
- * Changes made by Akbar Hussain Lineo, Inc, May 2001 for BLACKFIN
- * Copyright (C) 1995 Hamish Macdonald
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_BLACKFIN_PROCESSOR_H
-#define __ASM_BLACKFIN_PROCESSOR_H
-
-/* Stub to make stupid common code happy */
-
-#endif
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
deleted file mode 100644
index 251d5e6..0000000
--- a/arch/blackfin/include/asm/ptrace.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_PTRACE_H
-#define _BFIN_PTRACE_H
-
-/*
- * GCC defines register number like this:
- * -----------------------------
- *       0 - 7 are data registers R0-R7
- *       8 - 15 are address registers P0-P7
- *      16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
- *      32 - 33 A registers A0 & A1
- *      34 -    status register
- * -----------------------------
- *
- * We follows above, except:
- *      32-33 --- Low 32-bit of A0&1
- *      34-35 --- High 8-bit of A0&1
- */
-
-#ifndef __ASSEMBLY__
-
-struct task_struct;
-
-/* this struct defines the way the registers are stored on the
-   stack during a system call. */
-
-struct pt_regs {
-	long orig_pc;
-	long ipend;
-	long seqstat;
-	long rete;
-	long retn;
-	long retx;
-	long pc;		/* PC == RETI */
-	long rets;
-	long reserved;		/* Used as scratch during system calls */
-	long astat;
-	long lb1;
-	long lb0;
-	long lt1;
-	long lt0;
-	long lc1;
-	long lc0;
-	long a1w;
-	long a1x;
-	long a0w;
-	long a0x;
-	long b3;
-	long b2;
-	long b1;
-	long b0;
-	long l3;
-	long l2;
-	long l1;
-	long l0;
-	long m3;
-	long m2;
-	long m1;
-	long m0;
-	long i3;
-	long i2;
-	long i1;
-	long i0;
-	long usp;
-	long fp;
-	long p5;
-	long p4;
-	long p3;
-	long p2;
-	long p1;
-	long p0;
-	long r7;
-	long r6;
-	long r5;
-	long r4;
-	long r3;
-	long r2;
-	long r1;
-	long r0;
-	long orig_r0;
-	long orig_p0;
-	long syscfg;
-};
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS            12
-#define PTRACE_SETREGS            13	/* ptrace signal  */
-
-#define PTRACE_GETFDPIC           31	/* get the ELF fdpic loadmap address */
-#define PTRACE_GETFDPIC_EXEC       0	/* [addr] request the executable loadmap */
-#define PTRACE_GETFDPIC_INTERP     1	/* [addr] request the interpreter loadmap */
-
-#define PS_S  (0x0002)
-
-#ifdef __KERNEL__
-
-/* user_mode returns true if only one bit is set in IPEND, other than the
-   master interrupt enable.  */
-#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
-#define instruction_pointer(regs) ((regs)->pc)
-#define user_stack_pointer(regs)  ((regs)->usp)
-#define profile_pc(regs) instruction_pointer(regs)
-extern void show_regs(struct pt_regs *);
-
-#define arch_has_single_step()	(1)
-extern void user_enable_single_step(struct task_struct *);
-/* see arch/blackfin/kernel/ptrace.c about this redirect */
-#define user_disable_single_step(child) ptrace_disable(child)
-
-/*
- * Get the address of the live pt_regs for the specified task.
- * These are saved onto the top kernel stack when the process
- * is not running.
- *
- * Note: if a user thread is execve'd from kernel space, the
- * kernel stack will not be empty on entry to the kernel, so
- * ptracing these tasks will fail.
- */
-#define task_pt_regs(task) \
-	(struct pt_regs *) \
-	    ((unsigned long)task_stack_page(task) + \
-	     (THREAD_SIZE - sizeof(struct pt_regs)))
-
-#endif  /*  __KERNEL__  */
-
-#endif				/* __ASSEMBLY__ */
-
-/*
- * Offsets used by 'ptrace' system call interface.
- */
-
-#define PT_R0 204
-#define PT_R1 200
-#define PT_R2 196
-#define PT_R3 192
-#define PT_R4 188
-#define PT_R5 184
-#define PT_R6 180
-#define PT_R7 176
-#define PT_P0 172
-#define PT_P1 168
-#define PT_P2 164
-#define PT_P3 160
-#define PT_P4 156
-#define PT_P5 152
-#define PT_FP 148
-#define PT_USP 144
-#define PT_I0 140
-#define PT_I1 136
-#define PT_I2 132
-#define PT_I3 128
-#define PT_M0 124
-#define PT_M1 120
-#define PT_M2 116
-#define PT_M3 112
-#define PT_L0 108
-#define PT_L1 104
-#define PT_L2 100
-#define PT_L3 96
-#define PT_B0 92
-#define PT_B1 88
-#define PT_B2 84
-#define PT_B3 80
-#define PT_A0X 76
-#define PT_A0W 72
-#define PT_A1X 68
-#define PT_A1W 64
-#define PT_LC0 60
-#define PT_LC1 56
-#define PT_LT0 52
-#define PT_LT1 48
-#define PT_LB0 44
-#define PT_LB1 40
-#define PT_ASTAT 36
-#define PT_RESERVED 32
-#define PT_RETS 28
-#define PT_PC 24
-#define PT_RETX 20
-#define PT_RETN 16
-#define PT_RETE 12
-#define PT_SEQSTAT 8
-#define PT_IPEND 4
-
-#define PT_ORIG_R0 208
-#define PT_ORIG_P0 212
-#define PT_SYSCFG 216
-#define PT_TEXT_ADDR 220
-#define PT_TEXT_END_ADDR 224
-#define PT_DATA_ADDR 228
-#define PT_FDPIC_EXEC 232
-#define PT_FDPIC_INTERP 236
-
-#endif				/* _BFIN_PTRACE_H */
diff --git a/arch/blackfin/include/asm/sdh.h b/arch/blackfin/include/asm/sdh.h
deleted file mode 100644
index 2c2f63e..0000000
--- a/arch/blackfin/include/asm/sdh.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * sdh.h, export bfin_mmc_init
- *
- * Copyright (c) 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_SDH_H__
-#define __ASM_SDH_H__
-
-#include <mmc.h>
-#include <asm/u-boot.h>
-
-int bfin_mmc_init(bd_t *bis);
-
-#endif
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
deleted file mode 100644
index 1ea1c41..0000000
--- a/arch/blackfin/include/asm/sections.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2012 The Chromium OS Authors.
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_BLACKFIN_SECTIONS_H
-#define __ASM_BLACKFIN_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h
deleted file mode 100644
index 87a337d..0000000
--- a/arch/blackfin/include/asm/serial.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * serial.h - common serial defines for early debug and serial driver.
- *            any functions defined here must be always_inline since
- *            initcode cannot have function calls.
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_CPU_SERIAL_H__
-#define __BFIN_CPU_SERIAL_H__
-
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-
-#ifndef CONFIG_UART_CONSOLE
-# define CONFIG_UART_CONSOLE 0
-#endif
-
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-# define BFIN_DEBUG_EARLY_SERIAL 1
-#else
-# define BFIN_DEBUG_EARLY_SERIAL 0
-#endif
-
-#if defined(__ADSPBF60x__)
-# define BFIN_UART_HW_VER 4
-#elif defined(__ADSPBF50x__) || defined(__ADSPBF54x__)
-# define BFIN_UART_HW_VER 2
-#else
-# define BFIN_UART_HW_VER 1
-#endif
-
-#define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx
-#define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx)
-#define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin)
-#define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin)
-
-#define pUART ((volatile struct bfin_mmr_serial *)uart_base)
-
-#ifndef __ASSEMBLY__
-__attribute__((always_inline))
-static inline void serial_do_portmux(void);
-#endif
-
-#if BFIN_UART_HW_VER < 4
-# include "serial1.h"
-#else
-# include "serial4.h"
-#endif
-
-#ifndef __ASSEMBLY__
-
-__attribute__((always_inline))
-static inline void serial_do_portmux(void)
-{
-	if (!BFIN_DEBUG_EARLY_SERIAL) {
-		const unsigned short pins[] = { P_UART(RX), P_UART(TX), 0, };
-		peripheral_request_list(pins, "bfin-uart");
-		return;
-	}
-
-	serial_early_do_portmux();
-}
-
-#ifndef BFIN_IN_INITCODE
-__attribute__((always_inline))
-static inline void serial_early_puts(const char *s)
-{
-	if (BFIN_DEBUG_EARLY_SERIAL) {
-		serial_puts("Early: ");
-		serial_puts(s);
-	}
-}
-#endif
-
-#else
-
-.macro serial_early_init
-#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM)
-	call __serial_early_init;
-#endif
-.endm
-
-.macro serial_early_set_baud
-#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM)
-	R0.L = LO(CONFIG_BAUDRATE);
-	R0.H = HI(CONFIG_BAUDRATE);
-	call __serial_early_set_baud;
-#endif
-.endm
-
-#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
-#define update_serial_early_string_addr \
-	R1.L = _start; \
-	R1.H = _start; \
-	R0 = R0 - R1; \
-	R1.L = 0; \
-	R1.H = 0x2000; \
-	R0 = R0 + R1;
-#else
-#define update_serial_early_string_addr
-#endif
-
-/* Since we embed the string right into our .text section, we need
- * to find its address.  We do this by getting our PC and adding 2
- * bytes (which is the length of the jump instruction).  Then we
- * pass this address to serial_puts().
- */
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-# define serial_early_puts(str) \
-	.section .rodata; \
-	7: \
-	.ascii "Early:"; \
-	.ascii __FILE__; \
-	.ascii ": "; \
-	.ascii str; \
-	.asciz "\n"; \
-	.previous; \
-	R0.L = 7b; \
-	R0.H = 7b; \
-	update_serial_early_string_addr \
-	call _uart_early_puts;
-#else
-# define serial_early_puts(str)
-#endif
-
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/serial1.h b/arch/blackfin/include/asm/serial1.h
deleted file mode 100644
index 467d381..0000000
--- a/arch/blackfin/include/asm/serial1.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * serial.h - common serial defines for early debug and serial driver.
- *            any functions defined here must be always_inline since
- *            initcode cannot have function calls.
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_CPU_SERIAL1_H__
-#define __BFIN_CPU_SERIAL1_H__
-
-#include <asm/mach-common/bits/uart.h>
-
-#ifndef __ASSEMBLY__
-
-#include <asm/clock.h>
-
-#define MMR_UART(n) _PASTE_UART(n, UART, DLL)
-#ifdef UART_DLL
-# define UART0_DLL UART_DLL
-# if CONFIG_UART_CONSOLE != 0
-#  error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
-# endif
-#endif
-#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
-
-#define LOB(x) ((x) & 0xFF)
-#define HIB(x) (((x) >> 8) & 0xFF)
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits.  So use a helper macro to streamline this.
- */
-struct bfin_mmr_serial {
-#if BFIN_UART_HW_VER == 2
-	u16 dll;
-	u16 __pad_0;
-	u16 dlh;
-	u16 __pad_1;
-	u16 gctl;
-	u16 __pad_2;
-	u16 lcr;
-	u16 __pad_3;
-	u16 mcr;
-	u16 __pad_4;
-	u16 lsr;
-	u16 __pad_5;
-	u16 msr;
-	u16 __pad_6;
-	u16 scr;
-	u16 __pad_7;
-	u16 ier_set;
-	u16 __pad_8;
-	u16 ier_clear;
-	u16 __pad_9;
-	u16 thr;
-	u16 __pad_10;
-	u16 rbr;
-	u16 __pad_11;
-#else
-	union {
-		u16 dll;
-		u16 thr;
-		const u16 rbr;
-	};
-	const u16 __spad0;
-	union {
-		u16 dlh;
-		u16 ier;
-	};
-	const u16 __spad1;
-	const u16 iir;
-	u16 __pad_0;
-	u16 lcr;
-	u16 __pad_1;
-	u16 mcr;
-	u16 __pad_2;
-	u16 lsr;
-	u16 __pad_3;
-	u16 msr;
-	u16 __pad_4;
-	u16 scr;
-	u16 __pad_5;
-	const u32 __spad2;
-	u16 gctl;
-	u16 __pad_6;
-#endif
-};
-
-#define uart_lsr_t uint32_t
-#define _lsr_read(p)     bfin_read(&p->lsr)
-#define _lsr_write(p, v) bfin_write(&p->lsr, v)
-
-#if BFIN_UART_HW_VER == 2
-# define ACCESS_LATCH()
-# define ACCESS_PORT_IER()
-#else
-# define ACCESS_LATCH()    bfin_write_or(&pUART->lcr, DLAB)
-# define ACCESS_PORT_IER() bfin_write_and(&pUART->lcr, ~DLAB)
-#endif
-
-__attribute__((always_inline))
-static inline void serial_early_do_mach_portmux(char port, int mux_mask,
-	int mux_func, int port_pin)
-{
-	switch (port) {
-#if defined(__ADSPBF54x__)
-	case 'B':
-		bfin_write_PORTB_MUX((bfin_read_PORTB_MUX() &
-			~mux_mask) | mux_func);
-		bfin_write_PORTB_FER(bfin_read_PORTB_FER() | port_pin);
-		break;
-	case 'E':
-		bfin_write_PORTE_MUX((bfin_read_PORTE_MUX() &
-			~mux_mask) | mux_func);
-		bfin_write_PORTE_FER(bfin_read_PORTE_FER() | port_pin);
-		break;
-#endif
-#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF52x__)
-	case 'F':
-		bfin_write_PORTF_MUX((bfin_read_PORTF_MUX() &
-			~mux_mask) | mux_func);
-		bfin_write_PORTF_FER(bfin_read_PORTF_FER() | port_pin);
-		break;
-	case 'G':
-		bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
-			~mux_mask) | mux_func);
-		bfin_write_PORTG_FER(bfin_read_PORTG_FER() | port_pin);
-		break;
-	case 'H':
-		bfin_write_PORTH_MUX((bfin_read_PORTH_MUX() &
-			~mux_mask) | mux_func);
-		bfin_write_PORTH_FER(bfin_read_PORTH_FER() | port_pin);
-		break;
-#endif
-	default:
-		break;
-	}
-}
-
-__attribute__((always_inline))
-static inline void serial_early_do_portmux(void)
-{
-#if defined(__ADSPBF50x__)
-	switch (CONFIG_UART_CONSOLE) {
-	case 0:
-		serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
-		PORT_x_MUX_7_FUNC_1, PG12); /* TX: G; mux 7; func 1; PG12 */
-		serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
-		PORT_x_MUX_7_FUNC_1, PG13); /* RX: G; mux 7; func 1; PG13 */
-		break;
-	case 1:
-		serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
-		PORT_x_MUX_3_FUNC_1, PF7); /* TX: F; mux 3; func 1; PF6 */
-		serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
-		PORT_x_MUX_3_FUNC_1, PF6); /* RX: F; mux 3; func 1; PF7 */
-		break;
-	}
-#elif defined(__ADSPBF51x__)
-	switch (CONFIG_UART_CONSOLE) {
-	case 0:
-		serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
-		PORT_x_MUX_5_FUNC_2, PG9); /* TX: G; mux 5; func 2; PG9 */
-		serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
-		PORT_x_MUX_5_FUNC_2, PG10); /* RX: G; mux 5; func 2; PG10 */
-		break;
-	case 1:
-		serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
-		PORT_x_MUX_3_FUNC_2, PH7); /* TX: H; mux 3; func 2; PH6 */
-		serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
-		PORT_x_MUX_3_FUNC_2, PH6); /* RX: H; mux 3; func 2; PH7 */
-		break;
-	}
-#elif defined(__ADSPBF52x__)
-	switch (CONFIG_UART_CONSOLE) {
-	case 0:
-		serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
-		PORT_x_MUX_2_FUNC_3, PG7); /* TX: G; mux 2; func 3; PG7 */
-		serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
-		PORT_x_MUX_2_FUNC_3, PG8); /* RX: G; mux 2; func 3; PG8 */
-		break;
-	case 1:
-		serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
-		PORT_x_MUX_5_FUNC_3, PF14); /* TX: F; mux 5; func 3; PF14 */
-		serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
-		PORT_x_MUX_5_FUNC_3, PF15); /* RX: F; mux 5; func 3; PF15 */
-		break;
-	}
-#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
-	const uint16_t func[] = { PFDE, PFTE, };
-	bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]);
-	bfin_write_PORTF_FER(bfin_read_PORTF_FER() |
-			(1 << P_IDENT(P_UART(RX))) |
-			(1 << P_IDENT(P_UART(TX))));
-#elif defined(__ADSPBF54x__)
-	switch (CONFIG_UART_CONSOLE) {
-	case 0:
-		serial_early_do_mach_portmux('E', PORT_x_MUX_7_MASK,
-		PORT_x_MUX_7_FUNC_1, PE7); /* TX: E; mux 7; func 1; PE7 */
-		serial_early_do_mach_portmux('E', PORT_x_MUX_8_MASK,
-		PORT_x_MUX_8_FUNC_1, PE8); /* RX: E; mux 8; func 1; PE8 */
-		break;
-	case 1:
-		serial_early_do_mach_portmux('H', PORT_x_MUX_0_MASK,
-		PORT_x_MUX_0_FUNC_1, PH0); /* TX: H; mux 0; func 1; PH0 */
-		serial_early_do_mach_portmux('H', PORT_x_MUX_1_MASK,
-		PORT_x_MUX_1_FUNC_1, PH1); /* RX: H; mux 1; func 1; PH1 */
-		break;
-	case 2:
-		serial_early_do_mach_portmux('B', PORT_x_MUX_4_MASK,
-		PORT_x_MUX_4_FUNC_1, PB4); /* TX: B; mux 4; func 1; PB4 */
-		serial_early_do_mach_portmux('B', PORT_x_MUX_5_MASK,
-		PORT_x_MUX_5_FUNC_1, PB5); /* RX: B; mux 5; func 1; PB5 */
-		break;
-	case 3:
-		serial_early_do_mach_portmux('B', PORT_x_MUX_6_MASK,
-		PORT_x_MUX_6_FUNC_1, PB6); /* TX: B; mux 6; func 1; PB6 */
-		serial_early_do_mach_portmux('B', PORT_x_MUX_7_MASK,
-		PORT_x_MUX_7_FUNC_1, PB7); /* RX: B; mux 7; func 1; PB7 */
-		break;
-	}
-#elif defined(__ADSPBF561__)
-	/* UART pins could be GPIO, but they aren't pin muxed.  */
-#else
-# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
-#  error "missing portmux logic for UART"
-# endif
-#endif
-	SSYNC();
-}
-
-__attribute__((always_inline))
-static inline int uart_init(uint32_t uart_base)
-{
-	/* always enable UART -- avoids anomalies 05000309 and 05000350 */
-	bfin_write(&pUART->gctl, UCEN);
-
-	/* Set LCR to Word Lengh 8-bit word select */
-	bfin_write(&pUART->lcr, WLS_8);
-
-	SSYNC();
-
-	return 0;
-}
-
-__attribute__((always_inline))
-static inline int serial_early_init(uint32_t uart_base)
-{
-	/* handle portmux crap on different Blackfins */
-	serial_do_portmux();
-
-	return uart_init(uart_base);
-}
-
-__attribute__((always_inline))
-static inline int serial_early_uninit(uint32_t uart_base)
-{
-	/* disable the UART by clearing UCEN */
-	bfin_write(&pUART->gctl, 0);
-
-	return 0;
-}
-
-__attribute__((always_inline))
-static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor)
-{
-	/* Set DLAB in LCR to Access DLL and DLH */
-	ACCESS_LATCH();
-	SSYNC();
-
-	/* Program the divisor to get the baud rate we want */
-	bfin_write(&pUART->dll, LOB(divisor));
-	bfin_write(&pUART->dlh, HIB(divisor));
-	SSYNC();
-
-	/* Clear DLAB in LCR to Access THR RBR IER */
-	ACCESS_PORT_IER();
-	SSYNC();
-}
-
-__attribute__((always_inline))
-static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
-{
-	/* Translate from baud into divisor in terms of SCLK.  The
-	 * weird multiplication is to make sure we over sample just
-	 * a little rather than under sample the incoming signals.
-	 */
-#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
-	uint16_t divisor = (early_get_uart_clk() + baud * 8) / (baud * 16)
-			- ANOMALY_05000230;
-#else
-	uint16_t divisor = early_division(early_get_uart_clk() + (baud * 8),
-			baud * 16) - ANOMALY_05000230;
-#endif
-
-	serial_set_divisor(uart_base, divisor);
-}
-
-__attribute__((always_inline))
-static inline void serial_early_put_div(uint16_t divisor)
-{
-	uint32_t uart_base = UART_BASE;
-
-	/* Set DLAB in LCR to Access DLL and DLH */
-	ACCESS_LATCH();
-	SSYNC();
-
-	/* Program the divisor to get the baud rate we want */
-	bfin_write(&pUART->dll, LOB(divisor));
-	bfin_write(&pUART->dlh, HIB(divisor));
-	SSYNC();
-
-	/* Clear DLAB in LCR to Access THR RBR IER */
-	ACCESS_PORT_IER();
-	SSYNC();
-}
-
-__attribute__((always_inline))
-static inline uint16_t serial_early_get_div(void)
-{
-	uint32_t uart_base = UART_BASE;
-
-	/* Set DLAB in LCR to Access DLL and DLH */
-	ACCESS_LATCH();
-	SSYNC();
-
-	uint8_t dll = bfin_read(&pUART->dll);
-	uint8_t dlh = bfin_read(&pUART->dlh);
-	uint16_t divisor = (dlh << 8) | dll;
-
-	/* Clear DLAB in LCR to Access THR RBR IER */
-	ACCESS_PORT_IER();
-	SSYNC();
-
-	return divisor;
-}
-
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/serial4.h b/arch/blackfin/include/asm/serial4.h
deleted file mode 100644
index 6548396..0000000
--- a/arch/blackfin/include/asm/serial4.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * serial.h - common serial defines for early debug and serial driver.
- *            any functions defined here must be always_inline since
- *            initcode cannot have function calls.
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_CPU_SERIAL4_H__
-#define __BFIN_CPU_SERIAL4_H__
-
-#include <asm/mach-common/bits/uart4.h>
-
-#ifndef __ASSEMBLY__
-
-#include <asm/clock.h>
-
-#define MMR_UART(n) _PASTE_UART(n, UART, REVID)
-#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
-
-struct bfin_mmr_serial {
-	u32 revid;
-	u32 control;
-	u32 status;
-	u32 scr;
-	u32 clock;
-	u32 emask;
-	u32 emaskst;
-	u32 emaskcl;
-	u32 rbr;
-	u32 thr;
-	u32 taip;
-	u32 tsr;
-	u32 rsr;
-	u32 txdiv_cnt;
-	u32 rxdiv_cnt;
-};
-#define uart_lsr_t uint32_t
-#define _lsr_read(p)     bfin_read(&p->status)
-#define _lsr_write(p, v) bfin_write(&p->status, v)
-
-__attribute__((always_inline))
-static inline void serial_early_do_mach_portmux(char port, int mux_mask,
-	int mux_func, int port_pin)
-{
-	switch (port) {
-	case 'D':
-		bfin_write_PORTD_MUX((bfin_read_PORTD_MUX() &
-			~mux_mask) | mux_func);
-		bfin_write_PORTD_FER_SET(port_pin);
-		break;
-	case 'G':
-		bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
-			~mux_mask) | mux_func);
-		bfin_write_PORTG_FER_SET(port_pin);
-		break;
-	}
-}
-
-__attribute__((always_inline))
-static inline void serial_early_do_portmux(void)
-{
-#if defined(__ADSPBF60x__)
-	switch (CONFIG_UART_CONSOLE) {
-	case 0:
-		serial_early_do_mach_portmux('D', PORT_x_MUX_7_MASK,
-		PORT_x_MUX_7_FUNC_2, PD7); /* TX: D; mux 7; func 2; PD7 */
-		serial_early_do_mach_portmux('D', PORT_x_MUX_8_MASK,
-		PORT_x_MUX_8_FUNC_2, PD8); /* RX: D; mux 8; func 2; PD8 */
-		break;
-	case 1:
-		serial_early_do_mach_portmux('G', PORT_x_MUX_15_MASK,
-		PORT_x_MUX_15_FUNC_1, PG15); /* TX: G; mux 15; func 1; PG15 */
-		serial_early_do_mach_portmux('G', PORT_x_MUX_14_MASK,
-		PORT_x_MUX_14_FUNC_1, PG14); /* RX: G; mux 14; func 1; PG14 */
-		break;
-	}
-#else
-# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
-#  error "missing portmux logic for UART"
-# endif
-#endif
-	SSYNC();
-}
-
-__attribute__((always_inline))
-static inline int uart_init(uint32_t uart_base)
-{
-	/* always enable UART to 8-bit mode */
-	bfin_write(&pUART->control, UEN | UMOD_UART | WLS_8);
-
-	SSYNC();
-
-	return 0;
-}
-
-__attribute__((always_inline))
-static inline int serial_early_init(uint32_t uart_base)
-{
-	/* handle portmux crap on different Blackfins */
-	serial_do_portmux();
-
-	return uart_init(uart_base);
-}
-
-__attribute__((always_inline))
-static inline int serial_early_uninit(uint32_t uart_base)
-{
-	/* disable the UART by clearing UEN */
-	bfin_write(&pUART->control, 0);
-
-	return 0;
-}
-
-__attribute__((always_inline))
-static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor)
-{
-	/* Program the divisor to get the baud rate we want */
-	bfin_write(&pUART->clock, divisor);
-	SSYNC();
-}
-
-__attribute__((always_inline))
-static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
-{
-	uint16_t divisor = early_division(early_get_uart_clk(), baud * 16);
-
-	/* Program the divisor to get the baud rate we want */
-	serial_set_divisor(uart_base, divisor);
-}
-
-__attribute__((always_inline))
-static inline void serial_early_put_div(uint32_t divisor)
-{
-	uint32_t uart_base = UART_BASE;
-	bfin_write(&pUART->clock, divisor);
-}
-
-__attribute__((always_inline))
-static inline uint32_t serial_early_get_div(void)
-{
-	uint32_t uart_base = UART_BASE;
-	return bfin_read(&pUART->clock);
-}
-
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/shared_resources.h b/arch/blackfin/include/asm/shared_resources.h
deleted file mode 100644
index 42dab9f..0000000
--- a/arch/blackfin/include/asm/shared_resources.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * U-Boot - setup.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SHARED_RESOURCES_H_
-#define _SHARED_RESOURCES_H_
-
-void swap_to(int device_id);
-
-#define FLASH	 0
-#define ETHERNET 1
-
-#endif /* _SHARED_RESOURCES_H_ */
diff --git a/arch/blackfin/include/asm/signal.h b/arch/blackfin/include/asm/signal.h
deleted file mode 100644
index 7b1573c..0000000
--- a/arch/blackfin/include/asm/signal.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/signal.h>
diff --git a/arch/blackfin/include/asm/soft_switch.h b/arch/blackfin/include/asm/soft_switch.h
deleted file mode 100644
index 321b070..0000000
--- a/arch/blackfin/include/asm/soft_switch.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __SOFT_SWITCH_H__
-#define __SOFT_SWITCH_H__
-
-#define IO_PORT_A              0
-#define IO_PORT_B              1
-#define IO_PORT_INPUT          0
-#define IO_PORT_OUTPUT         1
-
-int config_switch_bit(int num, int port, int bit, int dir, uchar value);
-#endif
diff --git a/arch/blackfin/include/asm/string.h b/arch/blackfin/include/asm/string.h
deleted file mode 100644
index 15f50f2..0000000
--- a/arch/blackfin/include/asm/string.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * U-Boot - string.h String functions
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* Changed by Lineo Inc. May 2001 */
-
-#ifndef _BLACKFINNOMMU_STRING_H_
-#define _BLACKFINNOMMU_STRING_H_
-
-#ifdef __KERNEL__		/* only set these up for kernel code */
-
-#define __HAVE_ARCH_STRCPY
-#define __HAVE_ARCH_STRNCPY
-#define __HAVE_ARCH_STRCMP
-#define __HAVE_ARCH_STRNCMP
-#define __HAVE_ARCH_MEMCPY
-#define __HAVE_ARCH_MEMCMP
-#define __HAVE_ARCH_MEMSET
-#define __HAVE_ARCH_MEMMOVE
-
-extern char *strcpy(char *dest, const char *src);
-extern char *strncpy(char *dest, const char *src, size_t n);
-extern int strcmp(const char *cs, const char *ct);
-extern int strncmp(const char *cs, const char *ct, size_t count);
-extern void *memcpy(void *dest, const void *src, size_t count);
-extern void *memset(void *s, int c, size_t count);
-extern int memcmp(const void *, const void *, size_t);
-extern void *memmove(void *dest, const void *src, size_t count);
-
-#else				/* KERNEL */
-
-/*
- * let user libraries deal with these,
- * IMHO the kernel has no place defining these functions for user apps
- */
-
-#define __HAVE_ARCH_STRCPY	1
-#define __HAVE_ARCH_STRNCPY	1
-#define __HAVE_ARCH_STRCAT	1
-#define __HAVE_ARCH_STRNCAT	1
-#define __HAVE_ARCH_STRCMP	1
-#define __HAVE_ARCH_STRNCMP	1
-#define __HAVE_ARCH_STRNICMP	1
-#define __HAVE_ARCH_STRCHR	1
-#define __HAVE_ARCH_STRRCHR	1
-#define __HAVE_ARCH_STRSTR	1
-#define __HAVE_ARCH_STRLEN	1
-#define __HAVE_ARCH_STRNLEN	1
-#define __HAVE_ARCH_MEMSET	1
-#define __HAVE_ARCH_MEMCPY	1
-#define __HAVE_ARCH_MEMMOVE	1
-#define __HAVE_ARCH_MEMSCAN	1
-#define __HAVE_ARCH_MEMCMP	1
-#define __HAVE_ARCH_MEMCHR	1
-#define __HAVE_ARCH_STRTOK	1
-
-#endif				/* KERNEL */
-
-#endif				/* _BLACKFIN_STRING_H_ */
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
deleted file mode 100644
index f0c4ae2..0000000
--- a/arch/blackfin/include/asm/system.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * U-Boot - system.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _BLACKFIN_SYSTEM_H
-#define _BLACKFIN_SYSTEM_H
-
-/*
- * Interrupt configuring macros.
- */
-
-extern int irq_flags;
-
-#define local_irq_enable() \
-	__asm__ __volatile__ ( \
-		"sti %0;" \
-		: \
-		: "d" (irq_flags) \
-	)
-
-#define local_irq_disable() \
-	do { \
-		int __tmp_dummy; \
-		__asm__ __volatile__ ( \
-			"cli %0;" \
-			: "=d" (__tmp_dummy) \
-		); \
-	} while (0)
-
-# define local_irq_save(x) \
-	__asm__ __volatile__ ( \
-		"cli %0;" \
-		: "=&d" (x) \
-	)
-
-#define local_save_flags(x) \
-	__asm__ __volatile__ ( \
-		"cli %0;" \
-		"sti %0;" \
-		: "=d" (x) \
-	)
-
-#define irqs_enabled_from_flags(x) ((x) != 0x1f)
-
-#define local_irq_restore(x) \
-	do { \
-		if (irqs_enabled_from_flags(x)) \
-			local_irq_enable(); \
-	} while (0)
-
-/*
- * Force strict CPU ordering.
- */
-#define nop()			asm volatile ("nop;\n\t"::)
-#define mb()			asm volatile (""   : : :"memory")
-#define rmb()			asm volatile (""   : : :"memory")
-#define wmb()			asm volatile (""   : : :"memory")
-#define set_rmb(var, value)	do { xchg(&var, value); } while (0)
-#define set_mb(var, value)	set_rmb(var, value)
-#define set_wmb(var, value)	do { var = value; wmb(); } while (0)
-
-#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-
-struct __xchg_dummy {
-	unsigned long a[100];
-};
-#define __xg(x) ((volatile struct __xchg_dummy *)(x))
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
-				   int size)
-{
-	unsigned long tmp = 0;
-	unsigned long flags = 0;
-
-	local_irq_save(flags);
-
-	switch (size) {
-	case 1:
-		__asm__ __volatile__
-			("%0 = b%2 (z);\n\t"
-			 "b%2 = %1;\n\t"
-			 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-		break;
-	case 2:
-		__asm__ __volatile__
-			("%0 = w%2 (z);\n\t"
-			 "w%2 = %1;\n\t"
-			 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-		break;
-	case 4:
-		__asm__ __volatile__
-			("%0 = %2;\n\t"
-			 "%2 = %1;\n\t"
-			 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-		break;
-	}
-	local_irq_restore(flags);
-	return tmp;
-}
-
-void bfin_reset_boot_spi_cs(unsigned short pin);
-
-#endif	/* _BLACKFIN_SYSTEM_H */
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
deleted file mode 100644
index 7422d3d..0000000
--- a/arch/blackfin/include/asm/traps.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- *  Copyright 2004-2009 Analog Devices Inc.
- *                 2001 Lineo, Inc
- *                        Tony Kou
- *                 1993 Hamish Macdonald
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BFIN_TRAPS_H
-#define _BFIN_TRAPS_H
-
-#define VEC_SYS		(0)
-#define VEC_EXCPT01	(1)
-#define VEC_EXCPT02	(2)
-#define VEC_EXCPT03	(3)
-#define VEC_EXCPT04	(4)
-#define VEC_EXCPT05	(5)
-#define VEC_EXCPT06	(6)
-#define VEC_EXCPT07	(7)
-#define VEC_EXCPT08	(8)
-#define VEC_EXCPT09	(9)
-#define VEC_EXCPT10	(10)
-#define VEC_EXCPT11	(11)
-#define VEC_EXCPT12	(12)
-#define VEC_EXCPT13	(13)
-#define VEC_EXCPT14	(14)
-#define VEC_EXCPT15	(15)
-#define VEC_STEP	(16)
-#define VEC_OVFLOW	(17)
-#define VEC_UNDEF_I	(33)
-#define VEC_ILGAL_I	(34)
-#define VEC_CPLB_VL	(35)
-#define VEC_MISALI_D	(36)
-#define VEC_UNCOV	(37)
-#define VEC_CPLB_M	(38)
-#define VEC_CPLB_MHIT	(39)
-#define VEC_WATCH	(40)
-#define VEC_ISTRU_VL	(41)	/*ADSP-BF535 only (MH) */
-#define VEC_MISALI_I	(42)
-#define VEC_CPLB_I_VL	(43)
-#define VEC_CPLB_I_M	(44)
-#define VEC_CPLB_I_MHIT	(45)
-#define VEC_ILL_RES	(46)	/* including unvalid supervisor mode insn */
-/* The hardware reserves (63) for future use - we use it to tell our
- * normal exception handling code we have a hardware error
- */
-#define VEC_HWERR	(63)
-
-#endif				/* _BFIN_TRAPS_H */
diff --git a/arch/blackfin/include/asm/twi.h b/arch/blackfin/include/asm/twi.h
deleted file mode 100644
index 922cdbd..0000000
--- a/arch/blackfin/include/asm/twi.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * i2c.c - driver for Blackfin on-chip TWI/I2C
- *
- * Copyright (c) 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_TWI_H
-#define __ARCH_TWI_H
-
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/twi.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/types.h b/arch/blackfin/include/asm/types.h
deleted file mode 100644
index 4da64c4..0000000
--- a/arch/blackfin/include/asm/types.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * U-Boot - types.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _BLACKFIN_TYPES_H
-#define _BLACKFIN_TYPES_H
-
-/*
- * This file is never included by application software unless
- * explicitly requested (e.g., via linux/types.h) in which case the
- * application is Linux specific so (user-) name space pollution is
- * not a major issue.  However, for interoperability, libraries still
- * need to be careful to avoid a name clashes.
- */
-
-typedef unsigned short umode_t;
-
-/*
- * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
- * header files exported to user space
- */
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-/* HK0617   -- Changes to unsigned long temporarily */
-#if defined(__GNUC__)
-__extension__ typedef __signed__ long long __s64;
-__extension__ typedef unsigned long long __u64;
-#endif
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long long s64;
-typedef unsigned long long u64;
-
-#define BITS_PER_LONG 32
-
-/* Dma addresses are 32-bits wide. */
-
-typedef u32 dma_addr_t;
-
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
-
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/u-boot.h b/arch/blackfin/include/asm/u-boot.h
deleted file mode 100644
index 1ada44e..0000000
--- a/arch/blackfin/include/asm/u-boot.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * U-Boot - u-boot.h Structure declarations for board specific data
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _U_BOOT_H_
-#define _U_BOOT_H_	1
-
-typedef struct bd_info {
-	unsigned long bi_boot_params;	/* where this board expects params */
-	unsigned long bi_memstart;	/* start of DRAM memory */
-	phys_size_t bi_memsize;		/* size  of DRAM memory in bytes */
-	unsigned long bi_flashstart;	/* start of FLASH memory */
-	unsigned long bi_flashsize;	/* size  of FLASH memory */
-	unsigned long bi_flashoffset;	/* reserved area for startup monitor */
-	const char *bi_r_version;
-	const char *bi_cpu;
-	const char *bi_board_name;
-	unsigned long bi_vco;
-	unsigned long bi_cclk;
-	unsigned long bi_sclk;
-	unsigned char bi_enetaddr[6];
-} bd_t;
-
-/* For image.h:image_check_target_arch() */
-#define IH_ARCH_DEFAULT IH_ARCH_BLACKFIN
-
-int	arch_misc_init(void);
-
-#endif	/* _U_BOOT_H_ */
diff --git a/arch/blackfin/include/asm/unaligned.h b/arch/blackfin/include/asm/unaligned.h
deleted file mode 100644
index 6cecbbb..0000000
--- a/arch/blackfin/include/asm/unaligned.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/unaligned.h>
diff --git a/arch/blackfin/lib/.gitignore b/arch/blackfin/lib/.gitignore
deleted file mode 100644
index 09f1be0..0000000
--- a/arch/blackfin/lib/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-u-boot.lds
diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile
deleted file mode 100644
index de02c69..0000000
--- a/arch/blackfin/lib/Makefile
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# U-Boot Makefile
-#
-# Copyright (c) 2005-2008 Analog Devices Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= ins.o
-obj-y	+= memcmp.o
-obj-y	+= memcpy.o
-obj-y	+= memmove.o
-obj-y	+= memset.o
-obj-y	+= outs.o
-obj-$(CONFIG_CMD_KGDB) += __kgdb.o
-obj-y	+= boot.o
-obj-y	+= cache.o
-obj-y	+= clocks.o
-obj-$(CONFIG_CMD_CACHE_DUMP) += cmd_cache_dump.o
-obj-$(CONFIG_CMD_KGDB) += kgdb.o
-obj-y	+= muldi3.o
-obj-$(CONFIG_HAS_POST) += post.o
-obj-y	+= string.o
-obj-y	+= sections.o
diff --git a/arch/blackfin/lib/__kgdb.S b/arch/blackfin/lib/__kgdb.S
deleted file mode 100644
index 4e7b6a4..0000000
--- a/arch/blackfin/lib/__kgdb.S
+++ /dev/null
@@ -1,154 +0,0 @@
-#include <linux/linkage.h>
-
-/* save stack context for non-local goto
- * int kgdb_setjmp(long *buf)
- */
-
-ENTRY(_kgdb_setjmp)
-	[--SP] = p0; 	/* Save P0 */
-	p0 = r0;
-	r0 = [SP++];	/* Load P0 into R0 */
-
-	[p0 + 0x00] = r0;       /* GP address registers */
-	[p0 + 0x04] = p1;
-	[p0 + 0x08] = p2;
-	[p0 + 0x0C] = p3;
-	[p0 + 0x10] = p4;
-	[p0 + 0x14] = p5;
-	[p0 + 0x18] = FP;       /* frame pointer */
-	[p0 + 0x1C] = SP;       /* stack pointer */
-
-	[p0 + 0x20] = p0;       /* data regs */
-	[p0 + 0x24] = r1;
-	[p0 + 0x28] = r2;
-	[p0 + 0x2C] = r3;
-	[p0 + 0x30] = r4;
-	[p0 + 0x34] = r5;
-	[p0 + 0x38] = r6;
-	[p0 + 0x3C] = r7;
-
-	r0 = ASTAT;	[p0 + 0x40] = r0;
-
-	/* loop counters */
-	r0 = LC0;	[p0 + 0x44] = r0;
-	r0 = LC1;	[p0 + 0x48] = r0;
-
-	/* Accumulator */
-	r0 = A0.w;	[p0 + 0x4C] = r0;
-	r0.l = A0.x;	[p0 + 0x50] = r0;
-	r0 = A1.w;	[p0 + 0x54] = r0;
-	r0.l = A1.x;	[p0 + 0x58] = r0;
-
-	/* index registers */
-	r0 = i0;	[p0 + 0x5C] = r0;
-	r0 = i1;	[p0 + 0x60] = r0;
-	r0 = i2;	[p0 + 0x64] = r0;
-	r0 = i3;	[p0 + 0x68] = r0;
-
-	/* modifier registers */
-	r0 = m0;	[p0 + 0x6C] = r0;
-	r0 = m1;	[p0 + 0x70] = r0;
-	r0 = m2;	[p0 + 0x74] = r0;
-	r0 = m3;	[p0 + 0x78] = r0;
-
-	/* length registers */
-	r0 = l0;	[p0 + 0x7C] = r0;
-	r0 = l1;	[p0 + 0x80] = r0;
-	r0 = l2;	[p0 + 0x84] = r0;
-	r0 = l3;	[p0 + 0x88] = r0;
-
-	/* base registers */
-	r0 = b0;	[p0 + 0x8C] = r0;
-	r0 = b1;	[p0 + 0x90] = r0;
-	r0 = b2;	[p0 + 0x94] = r0;
-	r0 = b3;	[p0 + 0x98] = r0;
-
-	/* store return address */
-	r0 = RETS;	[p0 + 0x9C] = r0;
-
-	R0 = 0;
-	RTS;
-ENDPROC(_kgdb_setjmp)
-
-/*
- * non-local jump to a saved stack context
- * longjmp(long *buf, int val)
- */
-
-ENTRY(_kgdb_longjmp)
-	p0 = r0;
-	r0 = [p0 + 0x00];
-	[--sp] = r0;
-
-	/* GP address registers - skip p0 for now*/
-	p1 = [p0 + 0x04];
-	p2 = [p0 + 0x08];
-	p3 = [p0 + 0x0C];
-	p4 = [p0 + 0x10];
-	p5 = [p0 + 0x14];
-	/* frame pointer */
-	fp = [p0 + 0x18];
-	/* stack pointer */
-	r0 = [sp++];
-	sp = [p0 + 0x1C];
-	[--sp] = r0;
-	[--sp] = r1;
-
-	/* data regs */
-	r0 = [p0 + 0x20];
-	r1 = [p0 + 0x24];
-	r2 = [p0 + 0x28];
-	r3 = [p0 + 0x2C];
-	r4 = [p0 + 0x30];
-	r5 = [p0 + 0x34];
-	r6 = [p0 + 0x38];
-	r7 = [p0 + 0x3C];
-
-	r0 = [p0 + 0x40];	ASTAT = r0;
-
-	/* loop counters */
-	r0 = [p0 + 0x44];	LC0 = r0;
-	r0 = [p0 + 0x48];	LC1 = r0;
-
-	/* Accumulator */
-	r0 = [p0 + 0x4C];	A0.w = r0;
-	r0 = [p0 + 0x50];	A0.x = r0;
-	r0 = [p0 + 0x54];	A1.w = r0;
-	r0 = [p0 + 0x58];	A1.x = r0;
-
-	/* index registers */
-	r0 = [p0 + 0x5C];	i0 = r0;
-	r0 = [p0 + 0x60];	i1 = r0;
-	r0 = [p0 + 0x64];	i2 = r0;
-	r0 = [p0 + 0x68];	i3 = r0;
-
-	/* modifier registers */
-	r0 = [p0 + 0x6C];	m0 = r0;
-	r0 = [p0 + 0x70];	m1 = r0;
-	r0 = [p0 + 0x74];	m2 = r0;
-	r0 = [p0 + 0x78];	m3 = r0;
-
-	/* length registers */
-	r0 = [p0 + 0x7C];	l0 = r0;
-	r0 = [p0 + 0x80];	l1 = r0;
-	r0 = [p0 + 0x84];	l2 = r0;
-	r0 = [p0 + 0x88];	l3 = r0;
-
-	/* base registers */
-	r0 = [p0 + 0x8C];	b0 = r0;
-	r0 = [p0 + 0x90];	b1 = r0;
-	r0 = [p0 + 0x94];	b2 = r0;
-	r0 = [p0 + 0x98];	b3 = r0;
-
-	/* store return address */
-	r0 = [p0 + 0x9C];	RETS = r0;
-
-	/* fixup R0 & P0 */
-	r0 = [sp++];
-	p0 = [sp++];
-	CC = R0 == 0;
-	IF !CC JUMP .Lfinished;
-	R0 = 1;
-.Lfinished:
-	RTS;
-ENDPROC(_kgdb_longjmp)
diff --git a/arch/blackfin/lib/boot.c b/arch/blackfin/lib/boot.c
deleted file mode 100644
index fd4c82e..0000000
--- a/arch/blackfin/lib/boot.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * U-Boot - boot.c - misc boot helper functions
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <image.h>
-#include <asm/blackfin.h>
-
-#ifdef SHARED_RESOURCES
-extern void swap_to(int device_id);
-#endif
-
-#ifdef CONFIG_VIDEO
-extern void video_stop(void);
-#endif
-
-static char *make_command_line(void)
-{
-	char *dest = (char *)CONFIG_LINUX_CMDLINE_ADDR;
-	char *bootargs = getenv("bootargs");
-
-	if (bootargs == NULL)
-		return NULL;
-
-	strncpy(dest, bootargs, CONFIG_LINUX_CMDLINE_SIZE);
-	dest[CONFIG_LINUX_CMDLINE_SIZE - 1] = 0;
-	return dest;
-}
-
-extern ulong bfin_poweron_retx;
-
-int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
-{
-	int	(*appl) (char *cmdline);
-	char	*cmdline;
-
-	if (flag & BOOTM_STATE_OS_PREP)
-		return 0;
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
-
-#ifdef SHARED_RESOURCES
-	swap_to(FLASH);
-#endif
-
-#ifdef CONFIG_VIDEO
-	/* maybe this should be standardized and moved to bootm ... */
-	video_stop();
-#endif
-
-	appl = (int (*)(char *))images->ep;
-
-	printf("Starting Kernel at = %p\n", appl);
-	cmdline = make_command_line();
-	icache_disable();
-	dcache_disable();
-	asm __volatile__(
-		"RETX = %[retx];"
-		"CALL (%0);"
-		:
-		: "p"(appl), "q0"(cmdline), [retx] "d"(bfin_poweron_retx)
-	);
-	/* does not return */
-
-	return 1;
-}
diff --git a/arch/blackfin/lib/cache.c b/arch/blackfin/lib/cache.c
deleted file mode 100644
index 8d93339..0000000
--- a/arch/blackfin/lib/cache.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * U-Boot - cache.c
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/mpu.h>
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
-	void *start_addr, *end_addr;
-	int istatus, dstatus;
-
-	/* no need to flush stuff in on chip memory (L1/L2/etc...) */
-	if (addr >= 0xE0000000)
-		return;
-
-	start_addr = (void *)addr;
-	end_addr = (void *)(addr + size);
-	istatus = icache_status();
-	dstatus = dcache_status();
-
-	if (istatus) {
-		if (dstatus)
-			blackfin_icache_dcache_flush_range(start_addr, end_addr);
-		else
-			blackfin_icache_flush_range(start_addr, end_addr);
-	} else if (dstatus)
-		blackfin_dcache_flush_range(start_addr, end_addr);
-}
-
-#ifdef CONFIG_DCACHE_WB
-static void flushinv_all_dcache(void)
-{
-	u32 way, bank, subbank, set;
-	u32 status, addr;
-	u32 dmem_ctl = bfin_read_DMEM_CONTROL();
-
-	for (bank = 0; bank < 2; ++bank) {
-		if (!(dmem_ctl & (1 << (DMC1_P - bank))))
-			continue;
-
-		for (way = 0; way < 2; ++way)
-			for (subbank = 0; subbank < 4; ++subbank)
-				for (set = 0; set < 64; ++set) {
-
-					bfin_write_DTEST_COMMAND(
-						way << 26 |
-						bank << 23 |
-						subbank << 16 |
-						set << 5
-					);
-					CSYNC();
-					status = bfin_read_DTEST_DATA0();
-
-					/* only worry about valid/dirty entries */
-					if ((status & 0x3) != 0x3)
-						continue;
-
-					/* construct the address using the tag */
-					addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
-
-					/* flush it */
-					__asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
-				}
-	}
-}
-#endif
-
-void icache_enable(void)
-{
-	bfin_write_IMEM_CONTROL(IMC | ENICPLB);
-	SSYNC();
-}
-
-void icache_disable(void)
-{
-	bfin_write_IMEM_CONTROL(0);
-	SSYNC();
-}
-
-int icache_status(void)
-{
-	return bfin_read_IMEM_CONTROL() & IMC;
-}
-
-void dcache_enable(void)
-{
-	bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
-	SSYNC();
-}
-
-void dcache_disable(void)
-{
-#ifdef CONFIG_DCACHE_WB
-	bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ENDCPLB));
-	flushinv_all_dcache();
-#endif
-	bfin_write_DMEM_CONTROL(0);
-	SSYNC();
-}
-
-int dcache_status(void)
-{
-	return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE;
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-	blackfin_dcache_flush_invalidate_range((const void *)start, (const void *)stop);
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-	blackfin_dcache_flush_range((const void *)start, (const void *)stop);
-}
diff --git a/arch/blackfin/lib/clocks.c b/arch/blackfin/lib/clocks.c
deleted file mode 100644
index 7ed56a7..0000000
--- a/arch/blackfin/lib/clocks.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * clocks.c - figure out sclk/cclk/vco and such
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/clock.h>
-
-/* Get the voltage input multiplier */
-u_long get_vco(void)
-{
-	static u_long cached_vco_pll_ctl, cached_vco;
-
-	u_long msel, pll_ctl;
-
-	pll_ctl = bfin_read_PLL_CTL();
-	if (pll_ctl == cached_vco_pll_ctl)
-		return cached_vco;
-	else
-		cached_vco_pll_ctl = pll_ctl;
-
-	msel = (pll_ctl & MSEL) >> MSEL_P;
-	if (0 == msel)
-		msel = (MSEL >> MSEL_P) + 1;
-
-	cached_vco = CONFIG_CLKIN_HZ;
-	cached_vco >>= (pll_ctl & DF);
-	cached_vco *= msel;
-	return cached_vco;
-}
-
-/* Get the Core clock */
-u_long get_cclk(void)
-{
-	static u_long cached_cclk_pll_div, cached_cclk;
-	u_long div, csel;
-#ifndef CGU_DIV
-	u_long ssel;
-#endif
-
-	if (pll_is_bypassed())
-		return CONFIG_CLKIN_HZ;
-
-	div = bfin_read_PLL_DIV();
-	if (div == cached_cclk_pll_div)
-		return cached_cclk;
-	else
-		cached_cclk_pll_div = div;
-
-	csel = (div & CSEL) >> CSEL_P;
-#ifndef CGU_DIV
-	ssel = (div & SSEL) >> SSEL_P;
-	if (ssel && ssel < (1 << csel))	/* SCLK > CCLK */
-		cached_cclk = get_vco() / ssel;
-	else
-		cached_cclk = get_vco() >> csel;
-#else
-	cached_cclk = get_vco() / csel;
-#endif
-	return cached_cclk;
-}
-
-/* Get the System clock */
-#ifdef CGU_DIV
-
-static u_long cached_sclk_pll_div, cached_sclk;
-static u_long cached_sclk0, cached_sclk1, cached_dclk;
-static u_long _get_sclk(u_long *cache)
-{
-	u_long div, ssel;
-
-	if (pll_is_bypassed())
-		return CONFIG_CLKIN_HZ;
-
-	div = bfin_read_PLL_DIV();
-	if (div == cached_sclk_pll_div)
-		return *cache;
-	else
-		cached_sclk_pll_div = div;
-
-	ssel = (div & SYSSEL) >> SYSSEL_P;
-	cached_sclk = get_vco() / ssel;
-
-	ssel = (div & S0SEL) >> S0SEL_P;
-	cached_sclk0 = cached_sclk / ssel;
-
-	ssel = (div & S1SEL) >> S1SEL_P;
-	cached_sclk1 = cached_sclk / ssel;
-
-	ssel = (div & DSEL) >> DSEL_P;
-	cached_dclk = get_vco() / ssel;
-
-	return *cache;
-}
-
-u_long get_sclk(void)
-{
-	return _get_sclk(&cached_sclk);
-}
-
-u_long get_sclk0(void)
-{
-	return _get_sclk(&cached_sclk0);
-}
-
-u_long get_sclk1(void)
-{
-	return _get_sclk(&cached_sclk1);
-}
-
-u_long get_dclk(void)
-{
-	return _get_sclk(&cached_dclk);
-}
-#else
-
-u_long get_sclk(void)
-{
-	static u_long cached_sclk_pll_div, cached_sclk;
-	u_long div, ssel;
-
-	if (pll_is_bypassed())
-		return CONFIG_CLKIN_HZ;
-
-	div = bfin_read_PLL_DIV();
-	if (div == cached_sclk_pll_div)
-		return cached_sclk;
-	else
-		cached_sclk_pll_div = div;
-
-	ssel = (div & SSEL) >> SSEL_P;
-	cached_sclk = get_vco() / ssel;
-
-	return cached_sclk;
-}
-
-#endif
diff --git a/arch/blackfin/lib/cmd_cache_dump.c b/arch/blackfin/lib/cmd_cache_dump.c
deleted file mode 100644
index a4c799a..0000000
--- a/arch/blackfin/lib/cmd_cache_dump.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * U-Boot - cmd_cache_dump.c
- *
- * Copyright (c) 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-#include <common.h>
-#include <command.h>
-#include <console.h>
-
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/mpu.h>
-
-static int check_limit(const char *type, size_t start_limit, size_t end_limit, size_t start, size_t end)
-{
-	if (start >= start_limit && start <= end_limit && \
-	    end <= end_limit && end >= start_limit && \
-	    start <= end)
-		return 0;
-
-	printf("%s limit violation: %zu <= (user:%zu) <= (user:%zu) <= %zu\n",
-		type, start_limit, start, end, end_limit);
-	return 1;
-}
-
-int do_icache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int cache_status = icache_status();
-
-	if (cache_status)
-		icache_disable();
-
-	uint32_t cmd_base, tag, cache_upper, cache_lower;
-
-	size_t way, way_start = 0, way_end = 3;
-	size_t sbnk, sbnk_start = 0, sbnk_end = 3;
-	size_t set, set_start = 0, set_end = 31;
-	size_t dw;
-
-	if (argc > 1) {
-		way_start = way_end = simple_strtoul(argv[1], NULL, 10);
-		if (argc > 2) {
-			sbnk_start = sbnk_end = simple_strtoul(argv[2], NULL, 10);
-			if (argc > 3)
-				set_start = set_end = simple_strtoul(argv[3], NULL, 10);
-		}
-	}
-
-	if (check_limit("way", 0, 3, way_start, way_end) || \
-	    check_limit("subbank", 0, 3, sbnk_start, sbnk_end) || \
-	    check_limit("set", 0, 31, set_start, set_end))
-		return 1;
-
-	puts("Way:Subbank:Set: [valid-tag lower upper] {invalid-tag lower upper}...\n");
-
-	for (way = way_start; way <= way_end; ++way) {
-		for (sbnk = sbnk_start; sbnk <= sbnk_end; ++sbnk) {
-			for (set = set_start; set <= set_end; ++set) {
-				printf("%zu:%zu:%2zu: ", way, sbnk, set);
-				for (dw = 0; dw < 4; ++dw) {
-					if (ctrlc())
-						return 1;
-
-					cmd_base = \
-						(way  << 26) | \
-						(sbnk << 16) | \
-						(set  <<  5) | \
-						(dw   <<  3);
-
-					/* first read the tag */
-					bfin_write_ITEST_COMMAND(cmd_base | 0x0);
-					SSYNC();
-					tag = bfin_read_ITEST_DATA0();
-					printf("%c%08x ", (tag & 0x1 ? ' ' : '{'), tag);
-
-					/* grab the data at this loc */
-					bfin_write_ITEST_COMMAND(cmd_base | 0x4);
-					SSYNC();
-					cache_lower = bfin_read_ITEST_DATA0();
-					cache_upper = bfin_read_ITEST_DATA1();
-					printf("%08x %08x%c ", cache_lower, cache_upper, (tag & 0x1 ? ' ' : '}'));
-				}
-				puts("\n");
-			}
-		}
-	}
-
-	if (cache_status)
-		icache_enable();
-
-	return 0;
-}
-
-U_BOOT_CMD(icache_dump, 4, 0, do_icache_dump,
-	"icache_dump - dump current instruction cache\n",
-	"[way] [subbank] [set]");
-
-int do_dcache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	u32 way, bank, subbank, set;
-	u32 status, addr;
-	u32 dmem_ctl = bfin_read_DMEM_CONTROL();
-
-	for (bank = 0; bank < 2; ++bank) {
-		if (!(dmem_ctl & (1 << (DMC1_P - bank))))
-			continue;
-
-		for (way = 0; way < 2; ++way)
-			for (subbank = 0; subbank < 4; ++subbank) {
-				printf("%i:%i:%i:\t", bank, way, subbank);
-				for (set = 0; set < 64; ++set) {
-
-					if (ctrlc())
-						return 1;
-
-					/* retrieve a cache tag */
-					bfin_write_DTEST_COMMAND(
-						way << 26 |
-						bank << 23 |
-						subbank << 16 |
-						set << 5
-					);
-					CSYNC();
-					status = bfin_read_DTEST_DATA0();
-
-					/* construct the address using the tag */
-					addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
-
-					/* show it */
-					if (set && !(set % 4))
-						puts("\n\t");
-					printf("%c%08x%c%08x%c ", (status & 0x1 ? '[' : '{'), status, (status & 0x2 ? 'd' : ' '), addr, (status & 0x1 ? ']' : '}'));
-				}
-				puts("\n");
-			}
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(dcache_dump, 4, 0, do_dcache_dump,
-	"dcache_dump - dump current data cache\n",
-	"[bank] [way] [subbank] [set]");
diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S
deleted file mode 100644
index 3ac6d84..0000000
--- a/arch/blackfin/lib/ins.S
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * arch/blackfin/lib/ins.S - ins{bwl} using hardware loops
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-
-.align 2
-
-#ifdef CONFIG_IPIPE
-# define DO_CLI \
-	[--sp] = rets; \
-	[--sp] = (P5:0); \
-	sp += -12; \
-	call ___ipipe_disable_root_irqs_hw; \
-	sp += 12; \
-	(P5:0) = [sp++];
-# define CLI_INNER_NOP
-#else
-# define DO_CLI cli R3;
-# define CLI_INNER_NOP nop; nop; nop;
-#endif
-
-#ifdef CONFIG_IPIPE
-# define DO_STI \
-	sp += -12; \
-	call ___ipipe_enable_root_irqs_hw; \
-	sp += 12; \
-2:	rets = [sp++];
-#else
-# define DO_STI 2: sti R3;
-#endif
-
-#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
-# define CLI_OUTER DO_CLI;
-# define STI_OUTER DO_STI;
-# define CLI_INNER 1:
-# if ANOMALY_05000416
-#  define STI_INNER nop; 2: nop;
-# else
-#  define STI_INNER 2:
-# endif
-#else
-# define CLI_OUTER
-# define STI_OUTER
-# define CLI_INNER 1: DO_CLI; CLI_INNER_NOP;
-# define STI_INNER DO_STI;
-#endif
-
-/*
- * Reads on the Blackfin are speculative. In Blackfin terms, this means they
- * can be interrupted at any time (even after they have been issued on to the
- * external bus), and re-issued after the interrupt occurs.
- *
- * If a FIFO is sitting on the end of the read, it will see two reads,
- * when the core only sees one. The FIFO receives the read which is cancelled,
- * and not delivered to the core.
- *
- * To solve this, interrupts are turned off before reads occur to I/O space.
- * There are 3 versions of all these functions
- *  - turns interrupts off every read (higher overhead, but lower latency)
- *  - turns interrupts off every loop (low overhead, but longer latency)
- *  - DMA version, which do not suffer from this issue. DMA versions have
- *      different name (prefixed by dma_ ), and are located in
- *      ../kernel/bfin_dma_5xx.c
- * Using the dma related functions are recommended for transfering large
- * buffers in/out of FIFOs.
- */
-
-#define COMMON_INS(func, ops) \
-.section .text._ins##func; \
-ENTRY(_ins##func) \
-	P0 = R0;	/* P0 = port */ \
-	CLI_OUTER;	/* 3 instructions before first read access */ \
-	P1 = R1;	/* P1 = address */ \
-	P2 = R2;	/* P2 = count */ \
-	SSYNC; \
- \
-	LSETUP(1f, 2f) LC0 = P2; \
-	CLI_INNER; \
-	ops; \
-	STI_INNER; \
- \
-	STI_OUTER; \
-	RTS; \
-ENDPROC(_ins##func)
-
-COMMON_INS(l, \
-	R0 = [P0]; \
-	[P1++] = R0; \
-)
-
-COMMON_INS(w, \
-	R0 = W[P0]; \
-	W[P1++] = R0; \
-)
-
-COMMON_INS(w_8, \
-	R0 = W[P0]; \
-	B[P1++] = R0; \
-	R0 = R0 >> 8; \
-	B[P1++] = R0; \
-)
-
-COMMON_INS(b, \
-	R0 = B[P0]; \
-	B[P1++] = R0; \
-)
-
-COMMON_INS(l_16, \
-	R0 = [P0]; \
-	W[P1++] = R0; \
-	R0 = R0 >> 16; \
-	W[P1++] = R0; \
-)
diff --git a/arch/blackfin/lib/kgdb.c b/arch/blackfin/lib/kgdb.c
deleted file mode 100644
index 2a7c072..0000000
--- a/arch/blackfin/lib/kgdb.c
+++ /dev/null
@@ -1,423 +0,0 @@
-/*
- * U-Boot - architecture specific kgdb code
- *
- * Copyright 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-
-#include <kgdb.h>
-#include <asm/processor.h>
-#include <asm/mach-common/bits/core.h>
-#include "kgdb.h"
-#include <asm/deferred.h>
-#include <asm/traps.h>
-#include <asm/signal.h>
-
-void kgdb_enter(struct pt_regs *regs, kgdb_data *kdp)
-{
-	/* disable interrupts */
-	disable_interrupts();
-
-	/* reply to host that an exception has occurred */
-	kdp->sigval = kgdb_trap(regs);
-
-	/* send the PC and the Stack Pointer */
-	kdp->nregs = 2;
-	kdp->regs[0].num = BFIN_PC;
-	kdp->regs[0].val = regs->pc;
-
-	kdp->regs[1].num = BFIN_SP;
-	kdp->regs[1].val = (unsigned long)regs;
-
-}
-
-void kgdb_exit(struct pt_regs *regs, kgdb_data *kdp)
-{
-	if (kdp->extype & KGDBEXIT_WITHADDR)
-		printf("KGDBEXIT_WITHADDR\n");
-
-	switch (kdp->extype & KGDBEXIT_TYPEMASK) {
-	case KGDBEXIT_KILL:
-		printf("KGDBEXIT_KILL:\n");
-		break;
-	case KGDBEXIT_CONTINUE:
-		/* Make sure the supervisor single step bit is clear */
-		regs->syscfg &= ~1;
-		break;
-	case KGDBEXIT_SINGLE:
-		/* set the supervisor single step bit */
-		regs->syscfg |= 1;
-		break;
-	default:
-		printf("KGDBEXIT : %d\n", kdp->extype);
-	}
-
-	/* enable interrupts */
-	enable_interrupts();
-}
-
-int kgdb_trap(struct pt_regs *regs)
-{
-	/* ipend doesn't get filled in properly */
-	switch (regs->seqstat & EXCAUSE) {
-	case VEC_EXCPT01:
-		return SIGTRAP;
-	case VEC_EXCPT03:
-		return SIGSEGV;
-	case VEC_EXCPT02:
-		return SIGTRAP;
-	case VEC_EXCPT04 ... VEC_EXCPT15:
-		return SIGILL;
-	case VEC_STEP:
-		return SIGTRAP;
-	case VEC_OVFLOW:
-		return SIGTRAP;
-	case VEC_UNDEF_I:
-		return SIGILL;
-	case VEC_ILGAL_I:
-		return SIGILL;
-	case VEC_CPLB_VL:
-		return SIGSEGV;
-	case VEC_MISALI_D:
-		return SIGBUS;
-	case VEC_UNCOV:
-		return SIGILL;
-	case VEC_CPLB_MHIT:
-		return SIGSEGV;
-	case VEC_MISALI_I:
-		return SIGBUS;
-	case VEC_CPLB_I_VL:
-		return SIGBUS;
-	case VEC_CPLB_I_MHIT:
-		return SIGSEGV;
-	default:
-		return SIGBUS;
-	}
-}
-
-/*
- * getregs - gets the pt_regs, and gives them to kgdb's buffer
- */
-int kgdb_getregs(struct pt_regs *regs, char *buf, int max)
-{
-	unsigned long *gdb_regs = (unsigned long *)buf;
-
-	if (max < NUMREGBYTES)
-		kgdb_error(KGDBERR_NOSPACE);
-
-	if ((unsigned long)gdb_regs & 3)
-		kgdb_error(KGDBERR_ALIGNFAULT);
-
-	gdb_regs[BFIN_R0] = regs->r0;
-	gdb_regs[BFIN_R1] = regs->r1;
-	gdb_regs[BFIN_R2] = regs->r2;
-	gdb_regs[BFIN_R3] = regs->r3;
-	gdb_regs[BFIN_R4] = regs->r4;
-	gdb_regs[BFIN_R5] = regs->r5;
-	gdb_regs[BFIN_R6] = regs->r6;
-	gdb_regs[BFIN_R7] = regs->r7;
-	gdb_regs[BFIN_P0] = regs->p0;
-	gdb_regs[BFIN_P1] = regs->p1;
-	gdb_regs[BFIN_P2] = regs->p2;
-	gdb_regs[BFIN_P3] = regs->p3;
-	gdb_regs[BFIN_P4] = regs->p4;
-	gdb_regs[BFIN_P5] = regs->p5;
-	gdb_regs[BFIN_SP] = (unsigned long)regs;
-	gdb_regs[BFIN_FP] = regs->fp;
-	gdb_regs[BFIN_I0] = regs->i0;
-	gdb_regs[BFIN_I1] = regs->i1;
-	gdb_regs[BFIN_I2] = regs->i2;
-	gdb_regs[BFIN_I3] = regs->i3;
-	gdb_regs[BFIN_M0] = regs->m0;
-	gdb_regs[BFIN_M1] = regs->m1;
-	gdb_regs[BFIN_M2] = regs->m2;
-	gdb_regs[BFIN_M3] = regs->m3;
-	gdb_regs[BFIN_B0] = regs->b0;
-	gdb_regs[BFIN_B1] = regs->b1;
-	gdb_regs[BFIN_B2] = regs->b2;
-	gdb_regs[BFIN_B3] = regs->b3;
-	gdb_regs[BFIN_L0] = regs->l0;
-	gdb_regs[BFIN_L1] = regs->l1;
-	gdb_regs[BFIN_L2] = regs->l2;
-	gdb_regs[BFIN_L3] = regs->l3;
-	gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
-	gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
-	gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
-	gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
-	gdb_regs[BFIN_ASTAT] = regs->astat;
-	gdb_regs[BFIN_RETS] = regs->rets;
-	gdb_regs[BFIN_LC0] = regs->lc0;
-	gdb_regs[BFIN_LT0] = regs->lt0;
-	gdb_regs[BFIN_LB0] = regs->lb0;
-	gdb_regs[BFIN_LC1] = regs->lc1;
-	gdb_regs[BFIN_LT1] = regs->lt1;
-	gdb_regs[BFIN_LB1] = regs->lb1;
-	gdb_regs[BFIN_CYCLES] = 0;
-	gdb_regs[BFIN_CYCLES2] = 0;
-	gdb_regs[BFIN_USP] = regs->usp;
-	gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
-	gdb_regs[BFIN_SYSCFG] = regs->syscfg;
-	gdb_regs[BFIN_RETI] = regs->pc;
-	gdb_regs[BFIN_RETX] = regs->retx;
-	gdb_regs[BFIN_RETN] = regs->retn;
-	gdb_regs[BFIN_RETE] = regs->rete;
-	gdb_regs[BFIN_PC] = regs->pc;
-	gdb_regs[BFIN_CC] = 0;
-	gdb_regs[BFIN_EXTRA1] = 0;
-	gdb_regs[BFIN_EXTRA2] = 0;
-	gdb_regs[BFIN_EXTRA3] = 0;
-	gdb_regs[BFIN_IPEND] = regs->ipend;
-
-	return NUMREGBYTES;
-}
-
-/*
- * putreg - put kgdb's reg (regno) into the pt_regs
- */
-void kgdb_putreg(struct pt_regs *regs, int regno, char *buf, int length)
-{
-	unsigned long *ptr = (unsigned long *)buf;
-
-	if (regno < 0 || regno > BFIN_NUM_REGS)
-		kgdb_error(KGDBERR_BADPARAMS);
-
-	if (length < 4)
-		kgdb_error(KGDBERR_NOSPACE);
-
-	if ((unsigned long)ptr & 3)
-		kgdb_error(KGDBERR_ALIGNFAULT);
-
-	switch (regno) {
-	case BFIN_R0:
-		regs->r0 = *ptr;
-		break;
-	case BFIN_R1:
-		regs->r1 = *ptr;
-		break;
-	case BFIN_R2:
-		regs->r2 = *ptr;
-		break;
-	case BFIN_R3:
-		regs->r3 = *ptr;
-		break;
-	case BFIN_R4:
-		regs->r4 = *ptr;
-		break;
-	case BFIN_R5:
-		regs->r5 = *ptr;
-		break;
-	case BFIN_R6:
-		regs->r6 = *ptr;
-		break;
-	case BFIN_R7:
-		regs->r7 = *ptr;
-		break;
-	case BFIN_P0:
-		regs->p0 = *ptr;
-		break;
-	case BFIN_P1:
-		regs->p1 = *ptr;
-		break;
-	case BFIN_P2:
-		regs->p2 = *ptr;
-		break;
-	case BFIN_P3:
-		regs->p3 = *ptr;
-		break;
-	case BFIN_P4:
-		regs->p4 = *ptr;
-		break;
-	case BFIN_P5:
-		regs->p5 = *ptr;
-		break;
-	case BFIN_SP:
-		regs->reserved = *ptr;
-		break;
-	case BFIN_FP:
-		regs->fp = *ptr;
-		break;
-	case BFIN_I0:
-		regs->i0 = *ptr;
-		break;
-	case BFIN_I1:
-		regs->i1 = *ptr;
-		break;
-	case BFIN_I2:
-		regs->i2 = *ptr;
-		break;
-	case BFIN_I3:
-		regs->i3 = *ptr;
-		break;
-	case BFIN_M0:
-		regs->m0 = *ptr;
-		break;
-	case BFIN_M1:
-		regs->m1 = *ptr;
-		break;
-	case BFIN_M2:
-		regs->m2 = *ptr;
-		break;
-	case BFIN_M3:
-		regs->m3 = *ptr;
-		break;
-	case BFIN_B0:
-		regs->b0 = *ptr;
-		break;
-	case BFIN_B1:
-		regs->b1 = *ptr;
-		break;
-	case BFIN_B2:
-		regs->b2 = *ptr;
-		break;
-	case BFIN_B3:
-		regs->b3 = *ptr;
-		break;
-	case BFIN_L0:
-		regs->l0 = *ptr;
-		break;
-	case BFIN_L1:
-		regs->l1 = *ptr;
-		break;
-	case BFIN_L2:
-		regs->l2 = *ptr;
-		break;
-	case BFIN_L3:
-		regs->l3 = *ptr;
-		break;
-	case BFIN_A0_DOT_X:
-		regs->a0x = *ptr;
-		break;
-	case BFIN_A0_DOT_W:
-		regs->a0w = *ptr;
-		break;
-	case BFIN_A1_DOT_X:
-		regs->a1x = *ptr;
-		break;
-	case BFIN_A1_DOT_W:
-		regs->a1w = *ptr;
-		break;
-	case BFIN_ASTAT:
-		regs->astat = *ptr;
-		break;
-	case BFIN_RETS:
-		regs->rets = *ptr;
-		break;
-	case BFIN_LC0:
-		regs->lc0 = *ptr;
-		break;
-	case BFIN_LT0:
-		regs->lt0 = *ptr;
-		break;
-	case BFIN_LB0:
-		regs->lb0 = *ptr;
-		break;
-	case BFIN_LC1:
-		regs->lc1 = *ptr;
-		break;
-	case BFIN_LT1:
-		regs->lt1 = *ptr;
-		break;
-	case BFIN_LB1:
-		regs->lb1 = *ptr;
-		break;
-/*
-  BFIN_CYCLES,
-  BFIN_CYCLES2,
-  BFIN_USP,
-  BFIN_SEQSTAT,
-  BFIN_SYSCFG,
-*/
-	case BFIN_RETX:
-		regs->retx = *ptr;
-		break;
-	case BFIN_RETN:
-		regs->retn = *ptr;
-		break;
-	case BFIN_RETE:
-		regs->rete = *ptr;
-		break;
-	case BFIN_PC:
-		regs->pc = *ptr;
-		break;
-
-	default:
-		kgdb_error(KGDBERR_BADPARAMS);
-	}
-}
-
-void kgdb_putregs(struct pt_regs *regs, char *buf, int length)
-{
-	unsigned long *gdb_regs = (unsigned long *)buf;
-
-	if (length != BFIN_NUM_REGS)
-		kgdb_error(KGDBERR_NOSPACE);
-
-	if ((unsigned long)gdb_regs & 3)
-		kgdb_error(KGDBERR_ALIGNFAULT);
-
-	regs->r0 = gdb_regs[BFIN_R0];
-	regs->r1 = gdb_regs[BFIN_R1];
-	regs->r2 = gdb_regs[BFIN_R2];
-	regs->r3 = gdb_regs[BFIN_R3];
-	regs->r4 = gdb_regs[BFIN_R4];
-	regs->r5 = gdb_regs[BFIN_R5];
-	regs->r6 = gdb_regs[BFIN_R6];
-	regs->r7 = gdb_regs[BFIN_R7];
-	regs->p0 = gdb_regs[BFIN_P0];
-	regs->p1 = gdb_regs[BFIN_P1];
-	regs->p2 = gdb_regs[BFIN_P2];
-	regs->p3 = gdb_regs[BFIN_P3];
-	regs->p4 = gdb_regs[BFIN_P4];
-	regs->p5 = gdb_regs[BFIN_P5];
-	regs->fp = gdb_regs[BFIN_FP];
-/*	regs->sp = gdb_regs[BFIN_ ]; */
-	regs->i0 = gdb_regs[BFIN_I0];
-	regs->i1 = gdb_regs[BFIN_I1];
-	regs->i2 = gdb_regs[BFIN_I2];
-	regs->i3 = gdb_regs[BFIN_I3];
-	regs->m0 = gdb_regs[BFIN_M0];
-	regs->m1 = gdb_regs[BFIN_M1];
-	regs->m2 = gdb_regs[BFIN_M2];
-	regs->m3 = gdb_regs[BFIN_M3];
-	regs->b0 = gdb_regs[BFIN_B0];
-	regs->b1 = gdb_regs[BFIN_B1];
-	regs->b2 = gdb_regs[BFIN_B2];
-	regs->b3 = gdb_regs[BFIN_B3];
-	regs->l0 = gdb_regs[BFIN_L0];
-	regs->l1 = gdb_regs[BFIN_L1];
-	regs->l2 = gdb_regs[BFIN_L2];
-	regs->l3 = gdb_regs[BFIN_L3];
-	regs->a0x = gdb_regs[BFIN_A0_DOT_X];
-	regs->a0w = gdb_regs[BFIN_A0_DOT_W];
-	regs->a1x = gdb_regs[BFIN_A1_DOT_X];
-	regs->a1w = gdb_regs[BFIN_A1_DOT_W];
-	regs->rets = gdb_regs[BFIN_RETS];
-	regs->lc0 = gdb_regs[BFIN_LC0];
-	regs->lt0 = gdb_regs[BFIN_LT0];
-	regs->lb0 = gdb_regs[BFIN_LB0];
-	regs->lc1 = gdb_regs[BFIN_LC1];
-	regs->lt1 = gdb_regs[BFIN_LT1];
-	regs->lb1 = gdb_regs[BFIN_LB1];
-	regs->usp = gdb_regs[BFIN_USP];
-	regs->syscfg = gdb_regs[BFIN_SYSCFG];
-	regs->retx = gdb_regs[BFIN_PC];
-	regs->retn = gdb_regs[BFIN_RETN];
-	regs->rete = gdb_regs[BFIN_RETE];
-	regs->pc = gdb_regs[BFIN_PC];
-
-#if 0	/* can't change these */
-	regs->astat = gdb_regs[BFIN_ASTAT];
-	regs->seqstat = gdb_regs[BFIN_SEQSTAT];
-	regs->ipend = gdb_regs[BFIN_IPEND];
-#endif
-
-}
-
-void kgdb_breakpoint(int argc, char * const argv[])
-{
-	asm volatile ("excpt 0x1\n");
-}
diff --git a/arch/blackfin/lib/kgdb.h b/arch/blackfin/lib/kgdb.h
deleted file mode 100644
index 18f1f49..0000000
--- a/arch/blackfin/lib/kgdb.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/* Blackfin KGDB header
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_KGDB_H__
-#define __ASM_BLACKFIN_KGDB_H__
-
-/* gdb locks */
-#define KGDB_MAX_NO_CPUS 8
-
-/*
- * BUFMAX defines the maximum number of characters in inbound/outbound buffers.
- * At least NUMREGBYTES*2 are needed for register packets.
- * Longer buffer is needed to list all threads.
- */
-#define BUFMAX 2048
-
-enum regnames {
-  /* Core Registers */
-  BFIN_R0 = 0,
-  BFIN_R1,
-  BFIN_R2,
-  BFIN_R3,
-  BFIN_R4,
-  BFIN_R5,
-  BFIN_R6,
-  BFIN_R7,
-  BFIN_P0,
-  BFIN_P1,
-  BFIN_P2,
-  BFIN_P3,
-  BFIN_P4,
-  BFIN_P5,
-  BFIN_SP,
-  BFIN_FP,
-  BFIN_I0,
-  BFIN_I1,
-  BFIN_I2,
-  BFIN_I3,
-  BFIN_M0,
-  BFIN_M1,
-  BFIN_M2,
-  BFIN_M3,
-  BFIN_B0,
-  BFIN_B1,
-  BFIN_B2,
-  BFIN_B3,
-  BFIN_L0,
-  BFIN_L1,
-  BFIN_L2,
-  BFIN_L3,
-  BFIN_A0_DOT_X,
-  BFIN_A0_DOT_W,
-  BFIN_A1_DOT_X,
-  BFIN_A1_DOT_W,
-  BFIN_ASTAT,
-  BFIN_RETS,
-  BFIN_LC0,
-  BFIN_LT0,
-  BFIN_LB0,
-  BFIN_LC1,
-  BFIN_LT1,
-  BFIN_LB1,
-  BFIN_CYCLES,
-  BFIN_CYCLES2,
-  BFIN_USP,
-  BFIN_SEQSTAT,
-  BFIN_SYSCFG,
-  BFIN_RETI,
-  BFIN_RETX,
-  BFIN_RETN,
-  BFIN_RETE,
-
-  /* Pseudo Registers */
-  BFIN_PC,
-  BFIN_CC,
-  BFIN_EXTRA1,		/* Address of .text section.  */
-  BFIN_EXTRA2,		/* Address of .data section.  */
-  BFIN_EXTRA3,		/* Address of .bss section.  */
-  BFIN_FDPIC_EXEC,
-  BFIN_FDPIC_INTERP,
-
-  /* MMRs */
-  BFIN_IPEND,
-
-  /* LAST ENTRY SHOULD NOT BE CHANGED.  */
-  BFIN_NUM_REGS		/* The number of all registers.  */
-};
-
-/* Number of bytes of registers.  */
-#define NUMREGBYTES (BFIN_NUM_REGS * 4)
-
-static inline void arch_kgdb_breakpoint(void)
-{
-	asm volatile ("EXCPT 2;");
-}
-#define BREAK_INSTR_SIZE	2
-#define CACHE_FLUSH_IS_SAFE	1
-#define GDB_ADJUSTS_BREAK_OFFSET
-#define GDB_SKIP_HW_WATCH_TEST
-#define HW_INST_WATCHPOINT_NUM	6
-#define HW_WATCHPOINT_NUM	8
-#define TYPE_INST_WATCHPOINT	0
-#define TYPE_DATA_WATCHPOINT	1
-
-/* Instruction watchpoint address control register bits mask */
-#define WPPWR		0x1
-#define WPIREN01	0x2
-#define WPIRINV01	0x4
-#define WPIAEN0		0x8
-#define WPIAEN1		0x10
-#define WPICNTEN0	0x20
-#define WPICNTEN1	0x40
-#define EMUSW0		0x80
-#define EMUSW1		0x100
-#define WPIREN23	0x200
-#define WPIRINV23	0x400
-#define WPIAEN2		0x800
-#define WPIAEN3		0x1000
-#define WPICNTEN2	0x2000
-#define WPICNTEN3	0x4000
-#define EMUSW2		0x8000
-#define EMUSW3		0x10000
-#define WPIREN45	0x20000
-#define WPIRINV45	0x40000
-#define WPIAEN4		0x80000
-#define WPIAEN5		0x100000
-#define WPICNTEN4	0x200000
-#define WPICNTEN5	0x400000
-#define EMUSW4		0x800000
-#define EMUSW5		0x1000000
-#define WPAND		0x2000000
-
-/* Data watchpoint address control register bits mask */
-#define WPDREN01	0x1
-#define WPDRINV01	0x2
-#define WPDAEN0		0x4
-#define WPDAEN1		0x8
-#define WPDCNTEN0	0x10
-#define WPDCNTEN1	0x20
-
-#define WPDSRC0		0xc0
-#define WPDACC0_OFFSET	8
-#define WPDSRC1		0xc00
-#define WPDACC1_OFFSET	12
-
-/* Watchpoint status register bits mask */
-#define STATIA0		0x1
-#define STATIA1		0x2
-#define STATIA2		0x4
-#define STATIA3		0x8
-#define STATIA4		0x10
-#define STATIA5		0x20
-#define STATDA0		0x40
-#define STATDA1		0x80
-
-#endif
diff --git a/arch/blackfin/lib/memcmp.S b/arch/blackfin/lib/memcmp.S
deleted file mode 100644
index c8a5bed..0000000
--- a/arch/blackfin/lib/memcmp.S
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * File: memcmp.S
- *
- * Copyright 2004-2007 Analog Devices Inc.
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-.align 2
-
-/*
- * C Library function MEMCMP
- * R0 = First Address
- * R1 = Second Address
- * R2 = count
- * Favours word aligned data.
- */
-
-.globl _memcmp;
-.type _memcmp, STT_FUNC;
-_memcmp:
-	I1 = P3;
-	P0 = R0;			/* P0 = s1 address */
-	P3 = R1;			/* P3 = s2 Address  */
-	P2 = R2 ;			/* P2 = count */
-	CC = R2 <= 7(IU);
-	IF CC JUMP  .Ltoo_small;
-	I0 = R1;			/* s2 */
-	R1 = R1 | R0;		/* OR addresses together */
-	R1 <<= 30;		/* check bottom two bits */
-	CC =  AZ;			/* AZ set if zero. */
-	IF !CC JUMP  .Lbytes ;	/* Jump if addrs not aligned. */
-
-	P1 = P2 >> 2;		/* count = n/4 */
-	R3 =  3;
-	R2 = R2 & R3;		/* remainder */
-	P2 = R2;			/* set remainder */
-
-	LSETUP (.Lquad_loop_s , .Lquad_loop_e) LC0=P1;
-.Lquad_loop_s:
-	NOP;
-	R0 = [P0++];
-	R1 = [I0++];
-	CC = R0 == R1;
-	IF !CC JUMP .Lquad_different;
-.Lquad_loop_e:
-	NOP;
-
-	P3 = I0;			/* s2 */
-.Ltoo_small:
-	CC = P2 == 0;		/* Check zero count*/
-	IF CC JUMP .Lfinished;	/* very unlikely*/
-
-.Lbytes:
-	LSETUP (.Lbyte_loop_s , .Lbyte_loop_e) LC0=P2;
-.Lbyte_loop_s:
-	R1 = B[P3++](Z);	/* *s2 */
-	R0 = B[P0++](Z);	/* *s1 */
-	CC = R0 == R1;
-	IF !CC JUMP .Ldifferent;
-.Lbyte_loop_e:
-	NOP;
-
-.Ldifferent:
-	R0 = R0 - R1;
-	P3 = I1;
-	RTS;
-
-.Lquad_different:
-/* We've read two quads which don't match.
- * Can't just compare them, because we're
- * a little-endian machine, so the MSBs of
- * the regs occur at later addresses in the
- * string.
- * Arrange to re-read those two quads again,
- * byte-by-byte.
- */
-	P0 += -4;		/* back up to the start of the */
-	P3 = I0;		/* quads, and increase the*/
-	P2 += 4;		/* remainder count*/
-	P3 += -4;
-	JUMP .Lbytes;
-
-.Lfinished:
-	R0 = 0;
-	P3 = I1;
-	RTS;
-
-.size _memcmp, .-_memcmp
diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S
deleted file mode 100644
index 596ff1c..0000000
--- a/arch/blackfin/lib/memcpy.S
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * File: memcpy.S
- *
- * Copyright 2004-2007 Analog Devices Inc.
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-.align 2
-
-.globl _memcpy_ASM;
-.type _memcpy_ASM, STT_FUNC;
-_memcpy_ASM:
-	CC = R2 <=  0;	/* length not positive?*/
-	IF CC JUMP  .L_P1L2147483647;	/* Nothing to do */
-
-	P0 = R0 ;	/* dst*/
-	P1 = R1 ;	/* src*/
-	P2 = R2 ;	/* length */
-
-	/* check for overlapping data */
-	CC = R1 < R0;	/* src < dst */
-	IF !CC JUMP .Lno_overlap;
-	R3 = R1 + R2;
-	CC = R0 < R3;	/* and dst < src+len */
-	IF CC JUMP .Lhas_overlap;
-
-.Lno_overlap:
-	/* Check for aligned data.*/
-
-	R3 = R1 | R0;
-	R0 = 0x3;
-	R3 = R3 & R0;
-	CC = R3;	/* low bits set on either address? */
-	IF CC JUMP .Lnot_aligned;
-
-	/* Both addresses are word-aligned, so we can copy
-	at least part of the data using word copies.*/
-	P2 = P2 >> 2;
-	CC = P2 <= 2;
-	IF !CC JUMP .Lmore_than_seven;
-	/* less than eight bytes... */
-	P2 = R2;
-	LSETUP(.Lthree_start, .Lthree_end) LC0=P2;
-	R0 = R1;	/* setup src address for return */
-.Lthree_start:
-	R3 = B[P1++] (X);
-.Lthree_end:
-	B[P0++] = R3;
-
-	RTS;
-
-.Lmore_than_seven:
-	/* There's at least eight bytes to copy. */
-	P2 += -1;	/* because we unroll one iteration */
-	LSETUP(.Lword_loop, .Lword_loop) LC0=P2;
-	R0 = R1;
-	I1 = P1;
-	R3 = [I1++];
-.Lword_loop:
-	MNOP || [P0++] = R3 || R3 = [I1++];
-
-	[P0++] = R3;
-	/* Any remaining bytes to copy? */
-	R3 = 0x3;
-	R3 = R2 & R3;
-	CC = R3 == 0;
-	P1 = I1;	/* in case there's something left, */
-	IF !CC JUMP .Lbytes_left;
-	RTS;
-.Lbytes_left:	P2 = R3;
-.Lnot_aligned:
-	/* From here, we're copying byte-by-byte. */
-	LSETUP (.Lbyte_start , .Lbyte_end) LC0=P2;
-	R0 = R1;	/* Save src address for return */
-.Lbyte_start:
-	R1 = B[P1++] (X);
-.Lbyte_end:
-	B[P0++] = R1;
-
-.L_P1L2147483647:
-	RTS;
-
-.Lhas_overlap:
-/* Need to reverse the copying, because the
- * dst would clobber the src.
- * Don't bother to work out alignment for
- * the reverse case.
- */
-	R0 = R1;	/* save src for later. */
-	P0 = P0 + P2;
-	P0 += -1;
-	P1 = P1 + P2;
-	P1 += -1;
-	LSETUP(.Lover_start, .Lover_end) LC0=P2;
-.Lover_start:
-	R1 = B[P1--] (X);
-.Lover_end:
-	B[P0--] = R1;
-
-	RTS;
-
-.size _memcpy_ASM, .-_memcpy_ASM
diff --git a/arch/blackfin/lib/memmove.S b/arch/blackfin/lib/memmove.S
deleted file mode 100644
index 9ab2077..0000000
--- a/arch/blackfin/lib/memmove.S
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * File: memmove.S
- *
- * Copyright 2004-2007 Analog Devices Inc.
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-.align 2
-
-/*
- * C Library function MEMMOVE
- * R0 = To Address (leave unchanged to form result)
- * R1 = From Address
- * R2 = count
- * Data may overlap
- */
-
-.globl _memmove;
-.type _memmove, STT_FUNC;
-_memmove:
-	I1 = P3;
-	P0 = R0;                  /* P0 = To address */
-	P3 = R1;                  /* P3 = From Address */
-	P2 = R2 ;                 /* P2 = count */
-	CC = P2 == 0;             /* Check zero count*/
-	IF CC JUMP .Lfinished;    /* very unlikely */
-
-	CC = R1 < R0 (IU);        /* From < To */
-	IF !CC JUMP .Lno_overlap;
-	R3 = R1 + R2;
-	CC = R0 <= R3 (IU);       /* (From+len) >= To */
-	IF CC JUMP .Loverlap;
-.Lno_overlap:
-	R3 = 11;
-	CC = R2 <= R3;
-	IF CC JUMP  .Lbytes;
-	R3 = R1 | R0;             /* OR addresses together */
-	R3 <<= 30;                /* check bottom two bits */
-	CC =  AZ;                 /* AZ set if zero.*/
-	IF !CC JUMP  .Lbytes ;    /* Jump if addrs not aligned.*/
-
-	I0 = P3;
-	P1 = P2 >> 2;             /* count = n/4 */
-	P1 += -1;
-	R3 =  3;
-	R2 = R2 & R3;             /* remainder */
-	P2 = R2;                  /* set remainder */
-	R1 = [I0++];
-
-	LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
-.Lquad_loop: MNOP || [P0++] = R1 || R1 = [I0++];
-	[P0++] = R1;
-
-	CC = P2 == 0;             /* any remaining bytes? */
-	P3 = I0;                  /* Ammend P3 to updated ptr. */
-	IF !CC JUMP .Lbytes;
-	P3 = I1;
-	RTS;
-
-.Lbytes:     LSETUP (.Lbyte2_s , .Lbyte2_e) LC0=P2;
-.Lbyte2_s:   R1 = B[P3++](Z);
-.Lbyte2_e:   B[P0++] = R1;
-
-.Lfinished:  P3 = I1;
-	RTS;
-
-.Loverlap:
-	P2 += -1;
-	P0 = P0 + P2;
-	P3 = P3 + P2;
-	R1 = B[P3--] (Z);
-	CC = P2 == 0;
-	IF CC JUMP .Lno_loop;
-	LSETUP (.Lol_s, .Lol_e) LC0 = P2;
-.Lol_s:    B[P0--] = R1;
-.Lol_e:    R1 = B[P3--] (Z);
-.Lno_loop: B[P0] = R1;
-	P3 = I1;
-	RTS;
-
-.size _memmove, .-_memmove
diff --git a/arch/blackfin/lib/memset.S b/arch/blackfin/lib/memset.S
deleted file mode 100644
index 21cbabd..0000000
--- a/arch/blackfin/lib/memset.S
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * File: memset.S
- *
- * Copyright 2004-2007 Analog Devices Inc.
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-.align 2
-
-/*
- * C Library function MEMSET
- * R0 = address (leave unchanged to form result)
- * R1 = filler byte
- * R2 = count
- * Favours word aligned data.
- */
-
-.globl _memset;
-.type _memset, STT_FUNC;
-_memset:
-	P0 = R0 ;              /* P0 = address */
-	P2 = R2 ;              /* P2 = count   */
-	R3 = R0 + R2;          /* end          */
-	CC = R2 <= 7(IU);
-	IF CC JUMP  .Ltoo_small;
-	R1 = R1.B (Z);         /* R1 = fill char */
-	R2 =  3;
-	R2 = R0 & R2;          /* addr bottom two bits */
-	CC =  R2 == 0;             /* AZ set if zero.	*/
-	IF !CC JUMP  .Lforce_align ;  /* Jump if addr not aligned. */
-
-.Laligned:
-	P1 = P2 >> 2;          /* count = n/4        */
-	R2 = R1 <<  8;         /* create quad filler */
-	R2.L = R2.L + R1.L(NS);
-	R2.H = R2.L + R1.H(NS);
-	P2 = R3;
-
-	LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
-.Lquad_loop:
-	[P0++] = R2;
-
-	CC = P0 == P2;
-	IF !CC JUMP .Lbytes_left;
-	RTS;
-
-.Lbytes_left:
-	R2 = R3;                /* end point */
-	R3 = P0;                /* current position */
-	R2 = R2 - R3;           /* bytes left */
-	P2 = R2;
-
-.Ltoo_small:
-	CC = P2 == 0;           /* Check zero count */
-	IF CC JUMP .Lfinished;    /* Unusual */
-
-.Lbytes:
-	LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2;
-.Lbyte_loop:
-	B[P0++] = R1;
-
-.Lfinished:
-	RTS;
-
-.Lforce_align:
-	CC = BITTST (R0, 0);  /* odd byte */
-	R0 = 4;
-	R0 = R0 - R2;
-	P1 = R0;
-	R0 = P0;		    /* Recover return address */
-	IF !CC JUMP .Lskip1;
-	B[P0++] = R1;
-.Lskip1:
-	CC = R2 <= 2;          /* 2 bytes */
-	P2 -= P1;              /* reduce count */
-	IF !CC JUMP .Laligned;
-	B[P0++] = R1;
-	B[P0++] = R1;
-	JUMP .Laligned;
-
-.size _memset, .-_memset
diff --git a/arch/blackfin/lib/muldi3.c b/arch/blackfin/lib/muldi3.c
deleted file mode 100644
index 9f6f60d..0000000
--- a/arch/blackfin/lib/muldi3.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * U-Boot - muldi3.c contains routines for mult and div
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* Generic function got from GNU gcc package, libgcc2.c */
-#ifndef SI_TYPE_SIZE
-#define SI_TYPE_SIZE 32
-#endif
-#define __ll_B (1L << (SI_TYPE_SIZE / 2))
-#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
-#define __ll_highpart(t) ((USItype) (t) / __ll_B)
-#define BITS_PER_UNIT 8
-
-#if !defined (umul_ppmm)
-#define umul_ppmm(w1, w0, u, v)						\
-do {									\
-	USItype __x0, __x1, __x2, __x3;					\
-	USItype __ul, __vl, __uh, __vh;					\
-									\
-	__ul = __ll_lowpart (u);					\
-	__uh = __ll_highpart (u);					\
-	__vl = __ll_lowpart (v);					\
-	__vh = __ll_highpart (v);					\
-									\
-	__x0 = (USItype) __ul * __vl;					\
-	__x1 = (USItype) __ul * __vh;					\
-	__x2 = (USItype) __uh * __vl;					\
-	__x3 = (USItype) __uh * __vh;					\
-									\
-	__x1 += __ll_highpart (__x0);/* this can't give carry */	\
-	__x1 += __x2;	/* but this indeed can */			\
-	if (__x1 < __x2)	/* did we get it? */			\
-		__x3 += __ll_B;	/* yes, add it in the proper pos. */	\
-									\
-	(w1) = __x3 + __ll_highpart (__x1);				\
-	(w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);	\
-} while (0)
-#endif
-
-#if !defined (__umulsidi3)
-#define __umulsidi3(u, v)						\
-	({DIunion __w;							\
-	umul_ppmm (__w.s.high, __w.s.low, u, v);			\
-	__w.ll; })
-#endif
-
-typedef unsigned int USItype __attribute__ ((mode(SI)));
-typedef int SItype __attribute__ ((mode(SI)));
-typedef int DItype __attribute__ ((mode(DI)));
-typedef int word_type __attribute__ ((mode(__word__)));
-
-struct DIstruct {
-	SItype low, high;
-};
-typedef union {
-	struct DIstruct s;
-	DItype ll;
-} DIunion;
-
-DItype __muldi3(DItype u, DItype v)
-{
-	DIunion w;
-	DIunion uu, vv;
-
-	uu.ll = u, vv.ll = v;
-	/*  panic("kernel panic for __muldi3"); */
-	w.ll = __umulsidi3(uu.s.low, vv.s.low);
-	w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
-		     + (USItype) uu.s.high * (USItype) vv.s.low);
-
-	return w.ll;
-}
diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S
deleted file mode 100644
index 39d5332..0000000
--- a/arch/blackfin/lib/outs.S
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *                2005 BuyWays BV
- *                      Bas Vermeulen <bas@buyways.nl>
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-.section .text._outsl
-ENTRY(_outsl)
-	P0 = R0;	/* P0 = port */
-	P1 = R1;	/* P1 = address */
-	P2 = R2;	/* P2 = count */
-
-	LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
-.Llong_loop_s: R0 = [P1++];
-.Llong_loop_e: [P0] = R0;
-	RTS;
-ENDPROC(_outsl)
-
-.section .text._outsw
-ENTRY(_outsw)
-	P0 = R0;	/* P0 = port */
-	P1 = R1;	/* P1 = address */
-	P2 = R2;	/* P2 = count */
-
-	LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
-.Lword_loop_s: R0 = W[P1++];
-.Lword_loop_e: W[P0] = R0;
-	RTS;
-ENDPROC(_outsw)
-
-.section .text._outsb
-ENTRY(_outsb)
-	P0 = R0;	/* P0 = port */
-	P1 = R1;	/* P1 = address */
-	P2 = R2;	/* P2 = count */
-
-	LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
-.Lbyte_loop_s: R0 = B[P1++];
-.Lbyte_loop_e: B[P0] = R0;
-	RTS;
-ENDPROC(_outsb)
-
-.section .text._outsw_8
-ENTRY(_outsw_8)
-	P0 = R0;	/* P0 = port */
-	P1 = R1;	/* P1 = address */
-	P2 = R2;	/* P2 = count */
-
-	LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
-.Lword8_loop_s: R1 = B[P1++];
-		R0 = B[P1++];
-		R0 = R0 << 8;
-		R0 = R0 + R1;
-.Lword8_loop_e: W[P0] = R0;
-	RTS;
-ENDPROC(_outsw_8)
diff --git a/arch/blackfin/lib/post.c b/arch/blackfin/lib/post.c
deleted file mode 100644
index b3c5fab..0000000
--- a/arch/blackfin/lib/post.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Blackfin POST code
- *
- * Copyright (c) 2005-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <post.h>
-
-#include <asm/gpio.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
-int led_post_test(int flags)
-{
-	unsigned leds[] = { CONFIG_POST_BSPEC1_GPIO_LEDS };
-	int i;
-
-	/* First turn them all off */
-	for (i = 0; i < ARRAY_SIZE(leds); ++i) {
-		if (gpio_request(leds[i], "post")) {
-			printf("could not request gpio %u\n", leds[i]);
-			continue;
-		}
-		gpio_direction_output(leds[i], 0);
-	}
-
-	/* Now turn them on one by one */
-	for (i = 0; i < ARRAY_SIZE(leds); ++i) {
-		printf("LED%i on", i + 1);
-		gpio_set_value(leds[i], 1);
-		udelay(1000000);
-		printf("\b\b\b\b\b\b\b");
-		gpio_free(leds[i]);
-	}
-
-	return 0;
-}
-#endif
-
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC2
-int button_post_test(int flags)
-{
-	unsigned buttons[] = { CONFIG_POST_BSPEC2_GPIO_BUTTONS };
-	unsigned int sws[] = { CONFIG_POST_BSPEC2_GPIO_NAMES };
-	int i, delay = 5;
-	unsigned short value = 0;
-	int result = 0;
-
-	for (i = 0; i < ARRAY_SIZE(buttons); ++i) {
-		if (gpio_request(buttons[i], "post")) {
-			printf("could not request gpio %u\n", buttons[i]);
-			continue;
-		}
-		gpio_direction_input(buttons[i]);
-
-		delay = 5;
-		printf("\n--------Press SW%i: %2d ", sws[i], delay);
-		while (delay--) {
-			int j;
-			for (j = 0; j < 100; j++) {
-				value = gpio_get_value(buttons[i]);
-				if (value != 0)
-					break;
-				udelay(10000);
-			}
-			printf("\b\b\b%2d ", delay);
-		}
-		if (value != 0)
-			puts("\b\bOK");
-		else {
-			result = -1;
-			puts("\b\bfailed");
-		}
-
-		gpio_free(buttons[i]);
-	}
-
-	puts("\n");
-
-	return result;
-}
-#endif
diff --git a/arch/blackfin/lib/sections.c b/arch/blackfin/lib/sections.c
deleted file mode 100644
index 86fc4df..0000000
--- a/arch/blackfin/lib/sections.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * U-Boot - section.c
- *
- * Copyright (c) 2014 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-char __bss_start[0] __attribute__((section(".__bss_start")));
-char __bss_end[0] __attribute__((section(".__bss_end")));
-char __init_end[0] __attribute__((section(".__init_end")));
diff --git a/arch/blackfin/lib/string.c b/arch/blackfin/lib/string.c
deleted file mode 100644
index c904a88..0000000
--- a/arch/blackfin/lib/string.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * U-Boot - string.c Contains library routines.
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/io.h>
-#include <asm/dma.h>
-
-char *strcpy(char *dest, const char *src)
-{
-	char *xdest = dest;
-	char temp = 0;
-
-	__asm__ __volatile__ (
-		"1:\t%2 = B [%1++] (Z);\n\t"
-		"B [%0++] = %2;\n\t"
-		"CC = %2;\n\t"
-		"if cc jump 1b (bp);\n"
-		: "=a"(dest), "=a"(src), "=d"(temp)
-		: "0"(dest), "1"(src), "2"(temp)
-		: "memory");
-
-	return xdest;
-}
-
-char *strncpy(char *dest, const char *src, size_t n)
-{
-	char *xdest = dest;
-	char temp = 0;
-
-	if (n == 0)
-		return xdest;
-
-	__asm__ __volatile__ (
-		"1:\t%3 = B [%1++] (Z);\n\t"
-		"B [%0++] = %3;\n\t"
-		"CC = %3;\n\t"
-		"if ! cc jump 2f;\n\t"
-		"%2 += -1;\n\t"
-		"CC = %2 == 0;\n\t"
-		"if ! cc jump 1b (bp);\n"
-		"2:\n"
-		: "=a"(dest), "=a"(src), "=da"(n), "=d"(temp)
-		: "0"(dest), "1"(src), "2"(n), "3"(temp)
-		: "memory");
-
-	return xdest;
-}
-
-int strcmp(const char *cs, const char *ct)
-{
-	char __res1, __res2;
-
-	__asm__ (
-		"1:\t%2 = B[%0++] (Z);\n\t"	/* get *cs */
-		"%3 = B[%1++] (Z);\n\t"	/* get *ct */
-		"CC = %2 == %3;\n\t"	/* compare a byte */
-		"if ! cc jump 2f;\n\t"	/* not equal, break out */
-		"CC = %2;\n\t"	/* at end of cs? */
-		"if cc jump 1b (bp);\n\t"	/* no, keep going */
-		"jump.s 3f;\n"	/* strings are equal */
-		"2:\t%2 = %2 - %3;\n"	/* *cs - *ct */
-		"3:\n"
-		: "=a"(cs), "=a"(ct), "=d"(__res1), "=d"(__res2)
-		: "0"(cs), "1"(ct));
-
-	return __res1;
-}
-
-int strncmp(const char *cs, const char *ct, size_t count)
-{
-	char __res1, __res2;
-
-	if (!count)
-		return 0;
-
-	__asm__(
-		"1:\t%3 = B[%0++] (Z);\n\t"	/* get *cs */
-		"%4 = B[%1++] (Z);\n\t"	/* get *ct */
-		"CC = %3 == %4;\n\t"	/* compare a byte */
-		"if ! cc jump 3f;\n\t"	/* not equal, break out */
-		"CC = %3;\n\t"	/* at end of cs? */
-		"if ! cc jump 4f;\n\t"	/* yes, all done */
-		"%2 += -1;\n\t"	/* no, adjust count */
-		"CC = %2 == 0;\n\t" "if ! cc jump 1b;\n"	/* more to do, keep going */
-		"2:\t%3 = 0;\n\t"	/* strings are equal */
-		"jump.s    4f;\n" "3:\t%3 = %3 - %4;\n"	/* *cs - *ct */
-		"4:"
-		: "=a"(cs), "=a"(ct), "=da"(count), "=d"(__res1), "=d"(__res2)
-		: "0"(cs), "1"(ct), "2"(count));
-
-	return __res1;
-}
-
-#ifdef MDMA1_D0_NEXT_DESC_PTR
-# define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR
-# define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR
-#endif
-
-static void dma_calc_size(unsigned long ldst, unsigned long lsrc, size_t count,
-			unsigned long *dshift, unsigned long *bpos)
-{
-	unsigned long limit;
-
-#ifdef MSIZE
-	/* The max memory DMA memory transfer size is 32 bytes. */
-	limit = 5;
-	*dshift = MSIZE_P;
-#else
-	/* The max memory DMA memory transfer size is 4 bytes. */
-	limit = 2;
-	*dshift = WDSIZE_P;
-#endif
-
-	*bpos = min(limit, (unsigned long)ffs(ldst | lsrc | count)) - 1;
-}
-
-/* This version misbehaves for count values of 0 and 2^16+.
- * Perhaps we should detect that ?  Nowhere do we actually
- * use dma memcpy for those types of lengths though ...
- */
-void dma_memcpy_nocache(void *dst, const void *src, size_t count)
-{
-	struct dma_register *mdma_d0 = (void *)MDMA_D0_NEXT_DESC_PTR;
-	struct dma_register *mdma_s0 = (void *)MDMA_S0_NEXT_DESC_PTR;
-	unsigned long ldst = (unsigned long)dst;
-	unsigned long lsrc = (unsigned long)src;
-	unsigned long dshift, bpos;
-	uint32_t dsize, mod;
-
-	/* Disable DMA in case it's still running (older u-boot's did not
-	 * always turn them off).  Do it before the if statement below so
-	 * we can be cheap and not do a SSYNC() due to the forced abort.
-	 */
-	bfin_write(&mdma_d0->config, 0);
-	bfin_write(&mdma_s0->config, 0);
-	bfin_write(&mdma_d0->status, DMA_RUN | DMA_DONE | DMA_ERR);
-
-	/* Scratchpad cannot be a DMA source or destination */
-	if ((lsrc >= L1_SRAM_SCRATCH && lsrc < L1_SRAM_SCRATCH_END) ||
-	    (ldst >= L1_SRAM_SCRATCH && ldst < L1_SRAM_SCRATCH_END))
-		hang();
-
-	dma_calc_size(ldst, lsrc, count, &dshift, &bpos);
-	dsize = bpos << dshift;
-	count >>= bpos;
-	mod = 1 << bpos;
-
-#ifdef PSIZE
-	/* The max memory DMA peripheral transfer size is 4 bytes. */
-	dsize |= min(2UL, bpos) << PSIZE_P;
-#endif
-
-	/* Copy sram functions from sdram to sram */
-	/* Setup destination start address */
-	bfin_write(&mdma_d0->start_addr, ldst);
-	/* Setup destination xcount */
-	bfin_write(&mdma_d0->x_count, count);
-	/* Setup destination xmodify */
-	bfin_write(&mdma_d0->x_modify, mod);
-
-	/* Setup Source start address */
-	bfin_write(&mdma_s0->start_addr, lsrc);
-	/* Setup Source xcount */
-	bfin_write(&mdma_s0->x_count, count);
-	/* Setup Source xmodify */
-	bfin_write(&mdma_s0->x_modify, mod);
-
-	/* Enable source DMA */
-	bfin_write(&mdma_s0->config, dsize | DMAEN);
-	bfin_write(&mdma_d0->config, dsize | DMAEN | WNR | DI_EN);
-	SSYNC();
-
-	while (!(bfin_read(&mdma_d0->status) & DMA_DONE))
-		continue;
-
-	bfin_write(&mdma_d0->status, DMA_RUN | DMA_DONE | DMA_ERR);
-	bfin_write(&mdma_d0->config, 0);
-	bfin_write(&mdma_s0->config, 0);
-}
-/* We should do a dcache invalidate on the destination after the dma, but since
- * we lack such hardware capability, we'll flush/invalidate the destination
- * before the dma and bank on the idea that u-boot is single threaded.
- */
-void *dma_memcpy(void *dst, const void *src, size_t count)
-{
-	if (dcache_status()) {
-		blackfin_dcache_flush_range(src, src + count);
-		blackfin_dcache_flush_invalidate_range(dst, dst + count);
-	}
-
-	dma_memcpy_nocache(dst, src, count);
-
-	if (icache_status())
-		blackfin_icache_flush_range(dst, dst + count);
-
-	return dst;
-}
-
-/*
- * memcpy - Copy one area of memory to another
- * @dest: Where to copy to
- * @src: Where to copy from
- * @count: The size of the area.
- *
- * We need to have this wrapper in memcpy() as common code may call memcpy()
- * to load up L1 regions.  Consider loading an ELF which has sections with
- * LMA's pointing to L1.  The common code ELF loader will simply use memcpy()
- * to move the ELF's sections into the right place.  We need to catch that
- * here and redirect to dma_memcpy().
- */
-extern void *memcpy_ASM(void *dst, const void *src, size_t count);
-void *memcpy(void *dst, const void *src, size_t count)
-{
-	if (!count)
-		return dst;
-
-#ifdef CONFIG_CMD_KGDB
-	if (src >= (void *)SYSMMR_BASE) {
-		if (count == 2 && (unsigned long)src % 2 == 0) {
-			u16 mmr = bfin_read16(src);
-			memcpy(dst, &mmr, sizeof(mmr));
-			return dst;
-		}
-		if (count == 4 && (unsigned long)src % 4 == 0) {
-			u32 mmr = bfin_read32(src);
-			memcpy(dst, &mmr, sizeof(mmr));
-			return dst;
-		}
-		/* Failed for some reason */
-		memset(dst, 0xad, count);
-		return dst;
-	}
-	if (dst >= (void *)SYSMMR_BASE) {
-		if (count == 2 && (unsigned long)dst % 2 == 0) {
-			u16 mmr;
-			memcpy(&mmr, src, sizeof(mmr));
-			bfin_write16(dst, mmr);
-			return dst;
-		}
-		if (count == 4 && (unsigned long)dst % 4 == 0) {
-			u32 mmr;
-			memcpy(&mmr, src, sizeof(mmr));
-			bfin_write32(dst, mmr);
-			return dst;
-		}
-		/* Failed for some reason */
-		memset(dst, 0xad, count);
-		return dst;
-	}
-#endif
-
-	/* if L1 is the source or dst, use DMA */
-	if (addr_bfin_on_chip_mem(dst) || addr_bfin_on_chip_mem(src))
-		return dma_memcpy(dst, src, count);
-	else
-		/* No L1 is involved, so just call regular memcpy */
-		return memcpy_ASM(dst, src, count);
-}
diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c
index c29e98c..2706812 100644
--- a/arch/mips/mach-ath79/dram.c
+++ b/arch/mips/mach-ath79/dram.c
@@ -9,8 +9,12 @@
 #include <asm/addrspace.h>
 #include <mach/ddr.h>
 
-phys_size_t initdram(int board_type)
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
 {
 	ddr_tap_tuning();
-	return get_ram_size((void *)KSEG1, SZ_256M);
+	gd->ram_size = get_ram_size((void *)KSEG1, SZ_256M);
+
+	return 0;
 }
diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
index ac33391..c3194f0 100644
--- a/arch/mips/mach-pic32/cpu.c
+++ b/arch/mips/mach-pic32/cpu.c
@@ -110,12 +110,14 @@ static void ddr2_pmd_ungate(void)
 }
 
 /* initialize the DDR2 Controller and DDR2 PHY */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	ddr2_pmd_ungate();
 	ddr2_phy_init();
 	ddr2_ctrl_init();
-	return ddr2_calculate_size();
+	gd->ram_size = ddr2_calculate_size();
+
+	return 0;
 }
 
 int misc_init_r(void)
diff --git a/arch/mips/mach-pic32/include/mach/ddr.h b/arch/mips/mach-pic32/include/mach/ddr.h
index 00abfa3..e7da807 100644
--- a/arch/mips/mach-pic32/include/mach/ddr.h
+++ b/arch/mips/mach-pic32/include/mach/ddr.h
@@ -8,7 +8,7 @@
 #ifndef __MICROCHIP_PIC32_DDR_H
 #define __MICROCHIP_PIC32_DDR_H
 
-/* called by initdram() function */
+/* called by dram_init() function */
 void ddr2_phy_init(void);
 void ddr2_ctrl_init(void);
 phys_size_t ddr2_calculate_size(void);
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
index 7b2b637..99971fd 100644
--- a/arch/nds32/cpu/n1213/start.S
+++ b/arch/nds32/cpu/n1213/start.S
@@ -90,24 +90,6 @@ _start:	j	reset
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index c1caa65..6c4ec2c 100644
--- a/arch/nios2/cpu/cpu.c
+++ b/arch/nios2/cpu/cpu.c
@@ -150,3 +150,9 @@ U_BOOT_DRIVER(altera_nios2) = {
 	.ops		= &altera_nios2_ops,
 	.flags		= DM_FLAG_PRE_RELOC,
 };
+
+/* This is a dummy function on nios2 */
+int dram_init(void)
+{
+	return 0;
+}
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
deleted file mode 100644
index 11014d1..0000000
--- a/arch/openrisc/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-menu "OpenRISC architecture"
-	depends on OPENRISC
-
-config SYS_ARCH
-	default "openrisc"
-
-choice
-	prompt "Target select"
-	optional
-
-config TARGET_OPENRISC_GENERIC
-	bool "Support openrisc-generic"
-
-endchoice
-
-source "board/openrisc/openrisc-generic/Kconfig"
-
-endmenu
diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile
deleted file mode 100644
index c4da3ce..0000000
--- a/arch/openrisc/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-head-y := arch/openrisc/cpu/start.o
-
-libs-y += arch/openrisc/cpu/
-libs-y += arch/openrisc/lib/
diff --git a/arch/openrisc/config.mk b/arch/openrisc/config.mk
deleted file mode 100644
index bfdb71f..0000000
--- a/arch/openrisc/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2011
-# Julius Baxter <julius@opencores.org>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := or1k-elf-
-endif
-
-# r10 used for global object pointer, already set in OR32 GCC but just to be
-# clear
-PLATFORM_CPPFLAGS += -D__OR1K__ -ffixed-r10
-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
diff --git a/arch/openrisc/cpu/Makefile b/arch/openrisc/cpu/Makefile
deleted file mode 100644
index fc47d66..0000000
--- a/arch/openrisc/cpu/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2011
-# Julius Baxter <julius@opencores.org>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-extra-y	= start.o
-obj-y	= cache.o cpu.o exceptions.o interrupts.o
diff --git a/arch/openrisc/cpu/cache.c b/arch/openrisc/cpu/cache.c
deleted file mode 100644
index fe5b704..0000000
--- a/arch/openrisc/cpu/cache.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/system.h>
-
-void flush_dcache_range(unsigned long addr, unsigned long stop)
-{
-	ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
-
-	while (addr < stop) {
-		mtspr(SPR_DCBFR, addr);
-		addr += block_size;
-	}
-}
-
-void invalidate_dcache_range(unsigned long addr, unsigned long stop)
-{
-	ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
-
-	while (addr < stop) {
-		mtspr(SPR_DCBIR, addr);
-		addr += block_size;
-	}
-}
-
-static void invalidate_icache_range(unsigned long addr, unsigned long stop)
-{
-	ulong block_size = (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16;
-
-	while (addr < stop) {
-		mtspr(SPR_ICBIR, addr);
-		addr += block_size;
-	}
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
-	flush_dcache_range(addr, addr + size);
-	invalidate_icache_range(addr, addr + size);
-}
-
-int icache_status(void)
-{
-	return mfspr(SPR_SR) & SPR_SR_ICE;
-}
-
-int checkicache(void)
-{
-	unsigned long iccfgr;
-	unsigned long cache_set_size;
-	unsigned long cache_ways;
-	unsigned long cache_block_size;
-
-	iccfgr = mfspr(SPR_ICCFGR);
-	cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
-	cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
-	cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
-
-	return cache_set_size * cache_ways * cache_block_size;
-}
-
-int dcache_status(void)
-{
-	return mfspr(SPR_SR) & SPR_SR_DCE;
-}
-
-int checkdcache(void)
-{
-	unsigned long dccfgr;
-	unsigned long cache_set_size;
-	unsigned long cache_ways;
-	unsigned long cache_block_size;
-
-	dccfgr = mfspr(SPR_DCCFGR);
-	cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
-	cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
-	cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
-
-	return cache_set_size * cache_ways * cache_block_size;
-}
-
-void dcache_enable(void)
-{
-	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
-	asm volatile("l.nop");
-	asm volatile("l.nop");
-	asm volatile("l.nop");
-	asm volatile("l.nop");
-	asm volatile("l.nop");
-	asm volatile("l.nop");
-	asm volatile("l.nop");
-	asm volatile("l.nop");
-}
-
-void dcache_disable(void)
-{
-	mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE);
-}
-
-void icache_enable(void)
-{
-	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_ICE);
-	asm volatile("l.nop");
-	asm volatile("l.nop");
-	asm volatile("l.nop");
-	asm volatile("l.nop");
-	asm volatile("l.nop");
-	asm volatile("l.nop");
-	asm volatile("l.nop");
-	asm volatile("l.nop");
-}
-
-void icache_disable(void)
-{
-	mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE);
-}
-
-int cache_init(void)
-{
-	if (mfspr(SPR_UPR) & SPR_UPR_ICP) {
-		icache_disable();
-		invalidate_icache_range(0, checkicache());
-		icache_enable();
-	}
-
-	if (mfspr(SPR_UPR) & SPR_UPR_DCP) {
-		dcache_disable();
-		invalidate_dcache_range(0, checkdcache());
-		dcache_enable();
-	}
-
-	return 0;
-}
diff --git a/arch/openrisc/cpu/cpu.c b/arch/openrisc/cpu/cpu.c
deleted file mode 100644
index 272656a..0000000
--- a/arch/openrisc/cpu/cpu.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/system.h>
-#include <asm/openrisc_exc.h>
-
-static volatile int illegal_instruction;
-
-static void illegal_instruction_handler(void)
-{
-	ulong *epcr = (ulong *)mfspr(SPR_EPCR_BASE);
-
-	/* skip over the illegal instruction */
-	mtspr(SPR_EPCR_BASE, (ulong)(++epcr));
-	illegal_instruction = 1;
-}
-
-static void checkinstructions(void)
-{
-	ulong ra = 1, rb = 1, rc;
-
-	exception_install_handler(EXC_ILLEGAL_INSTR,
-				illegal_instruction_handler);
-
-	illegal_instruction = 0;
-	asm volatile("l.mul %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb));
-	printf("           Hardware multiplier: %s\n",
-		illegal_instruction ? "no" : "yes");
-
-	illegal_instruction = 0;
-	asm volatile("l.div %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb));
-	printf("           Hardware divider: %s\n",
-		illegal_instruction ? "no" : "yes");
-
-	exception_free_handler(EXC_ILLEGAL_INSTR);
-}
-
-int checkcpu(void)
-{
-	ulong upr = mfspr(SPR_UPR);
-	ulong vr = mfspr(SPR_VR);
-	ulong iccfgr = mfspr(SPR_ICCFGR);
-	ulong dccfgr = mfspr(SPR_DCCFGR);
-	ulong immucfgr = mfspr(SPR_IMMUCFGR);
-	ulong dmmucfgr = mfspr(SPR_DMMUCFGR);
-	ulong cpucfgr = mfspr(SPR_CPUCFGR);
-	uint ver = (vr & SPR_VR_VER) >> 24;
-	uint rev = vr & SPR_VR_REV;
-	uint block_size;
-	uint ways;
-	uint sets;
-
-	printf("CPU:   OpenRISC-%x00 (rev %d) @ %d MHz\n",
-		ver, rev, (CONFIG_SYS_CLK_FREQ / 1000000));
-
-	if (upr & SPR_UPR_DCP) {
-		block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
-		ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
-		printf("       D-Cache: %d bytes, %d bytes/line, %d way(s)\n",
-		       checkdcache(), block_size, ways);
-	} else {
-		printf("       D-Cache: no\n");
-	}
-
-	if (upr & SPR_UPR_ICP) {
-		block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
-		ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
-		printf("       I-Cache: %d bytes, %d bytes/line, %d way(s)\n",
-		       checkicache(), block_size, ways);
-	} else {
-		printf("       I-Cache: no\n");
-	}
-
-	if (upr & SPR_UPR_DMP) {
-		sets = 1 << ((dmmucfgr & SPR_DMMUCFGR_NTS) >> 2);
-		ways = (dmmucfgr & SPR_DMMUCFGR_NTW) + 1;
-		printf("       DMMU: %d sets, %d way(s)\n",
-		       sets, ways);
-	} else {
-		printf("       DMMU: no\n");
-	}
-
-	if (upr & SPR_UPR_IMP) {
-		sets = 1 << ((immucfgr & SPR_IMMUCFGR_NTS) >> 2);
-		ways = (immucfgr & SPR_IMMUCFGR_NTW) + 1;
-		printf("       IMMU: %d sets, %d way(s)\n",
-		       sets, ways);
-	} else {
-		printf("       IMMU: no\n");
-	}
-
-	printf("       MAC unit: %s\n",
-		(upr & SPR_UPR_MP) ? "yes" : "no");
-	printf("       Debug unit: %s\n",
-		(upr & SPR_UPR_DUP) ? "yes" : "no");
-	printf("       Performance counters: %s\n",
-		(upr & SPR_UPR_PCUP) ? "yes" : "no");
-	printf("       Power management: %s\n",
-		(upr & SPR_UPR_PMP) ? "yes" : "no");
-	printf("       Interrupt controller: %s\n",
-		(upr & SPR_UPR_PICP) ? "yes" : "no");
-	printf("       Timer: %s\n",
-		(upr & SPR_UPR_TTP) ? "yes" : "no");
-	printf("       Custom unit(s): %s\n",
-		(upr & SPR_UPR_CUP) ? "yes" : "no");
-
-	printf("       Supported instructions:\n");
-	printf("           ORBIS32: %s\n",
-		(cpucfgr & SPR_CPUCFGR_OB32S) ? "yes" : "no");
-	printf("           ORBIS64: %s\n",
-		(cpucfgr & SPR_CPUCFGR_OB64S) ? "yes" : "no");
-	printf("           ORFPX32: %s\n",
-		(cpucfgr & SPR_CPUCFGR_OF32S) ? "yes" : "no");
-	printf("           ORFPX64: %s\n",
-		(cpucfgr & SPR_CPUCFGR_OF64S) ? "yes" : "no");
-
-	checkinstructions();
-
-	return 0;
-}
-
-int cleanup_before_linux(void)
-{
-	disable_interrupts();
-	return 0;
-}
-
-extern void __reset(void);
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	disable_interrupts();
-	/* Code the jump to __reset here as the compiler is prone to
-	   emitting a bad jump instruction if the function is in flash */
-	__asm__("l.movhi r1,hi(__reset);  \
-		 l.ori r1,r1,lo(__reset); \
-		 l.jr r1");
-	/* not reached, __reset does not return */
-	return 0;
-}
diff --git a/arch/openrisc/cpu/exceptions.c b/arch/openrisc/cpu/exceptions.c
deleted file mode 100644
index b339997..0000000
--- a/arch/openrisc/cpu/exceptions.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <stdio_dev.h>
-#include <asm/system.h>
-
-static const char * const excp_table[] = {
-	"Unknown exception",
-	"Reset",
-	"Bus Error",
-	"Data Page Fault",
-	"Instruction Page Fault",
-	"Tick Timer",
-	"Alignment",
-	"Illegal Instruction",
-	"External Interrupt",
-	"D-TLB Miss",
-	"I-TLB Miss",
-	"Range",
-	"System Call",
-	"Floating Point",
-	"Trap",
-};
-
-static void (*handlers[32])(void);
-
-void exception_install_handler(int exception, void (*handler)(void))
-{
-	if (exception < 0 || exception > 31)
-		return;
-
-	handlers[exception] = handler;
-}
-
-void exception_free_handler(int exception)
-{
-	if (exception < 0 || exception > 31)
-		return;
-
-	handlers[exception] = 0;
-}
-
-static void exception_hang(int vect)
-{
-	printf("Unhandled exception at 0x%x ", vect & 0xff00);
-
-	vect = ((vect >> 8) & 0xff);
-	if (vect < ARRAY_SIZE(excp_table))
-		printf("(%s)\n", excp_table[vect]);
-	else
-		printf("(%s)\n", excp_table[0]);
-
-	printf("EPCR: 0x%08lx\n", mfspr(SPR_EPCR_BASE));
-	printf("EEAR: 0x%08lx\n", mfspr(SPR_EEAR_BASE));
-	printf("ESR:  0x%08lx\n", mfspr(SPR_ESR_BASE));
-	hang();
-}
-
-void exception_handler(int vect)
-{
-	int exception = vect >> 8;
-
-	if (handlers[exception])
-		handlers[exception]();
-	else
-		exception_hang(vect);
-}
diff --git a/arch/openrisc/cpu/interrupts.c b/arch/openrisc/cpu/interrupts.c
deleted file mode 100644
index 1ecfbf0..0000000
--- a/arch/openrisc/cpu/interrupts.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/types.h>
-#include <asm/ptrace.h>
-#include <asm/system.h>
-#include <asm/openrisc_exc.h>
-
-struct irq_action {
-	interrupt_handler_t *handler;
-	void *arg;
-	int count;
-};
-
-static struct irq_action handlers[32];
-
-void interrupt_handler(void)
-{
-	int irq;
-
-	while ((irq = ffs(mfspr(SPR_PICSR)))) {
-		if (handlers[--irq].handler) {
-			handlers[irq].handler(handlers[irq].arg);
-			handlers[irq].count++;
-		} else {
-			/* disable the interrupt */
-			mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1 << irq));
-			printf("Unhandled interrupt: %d\n", irq);
-		}
-		/* clear the interrupt */
-		mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1 << irq));
-	}
-}
-
-int interrupt_init(void)
-{
-	/* install handler for external interrupt exception */
-	exception_install_handler(EXC_EXT_IRQ, interrupt_handler);
-	/* Enable interrupts in supervisor register */
-	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
-
-	return 0;
-}
-
-void enable_interrupts(void)
-{
-	/* Set interrupt enable bit in supervisor register */
-	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
-	/* Enable timer exception */
-	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE);
-}
-
-int disable_interrupts(void)
-{
-	/* Clear interrupt enable bit in supervisor register */
-	mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE);
-	/* Disable timer exception */
-	mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_TEE);
-
-	return 0;
-}
-
-void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg)
-{
-	if (irq < 0 || irq > 31)
-		return;
-
-	handlers[irq].handler = handler;
-	handlers[irq].arg = arg;
-}
-
-void irq_free_handler(int irq)
-{
-	if (irq < 0 || irq > 31)
-		return;
-
-	handlers[irq].handler = 0;
-	handlers[irq].arg = 0;
-}
-
-#if defined(CONFIG_CMD_IRQ)
-int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int i;
-
-	printf("\nInterrupt-Information:\n\n");
-	printf("Nr  Routine   Arg       Count\n");
-	printf("-----------------------------\n");
-
-	for (i = 0; i < 32; i++) {
-		if (handlers[i].handler) {
-			printf("%02d  %08lx  %08lx  %d\n",
-				i,
-				(ulong)handlers[i].handler,
-				(ulong)handlers[i].arg,
-				handlers[i].count);
-		}
-	}
-	printf("\n");
-
-	return 0;
-}
-#endif
diff --git a/arch/openrisc/cpu/start.S b/arch/openrisc/cpu/start.S
deleted file mode 100644
index 1ae3b75..0000000
--- a/arch/openrisc/cpu/start.S
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- * (C) Copyright 2014, Franck Jullien <franck.jullien@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <asm-offsets.h>
-#include <asm/spr-defs.h>
-
-#define EXCEPTION_STACK_SIZE (128+128)
-
-#define HANDLE_EXCEPTION			\
-	l.addi	r1, r1, -EXCEPTION_STACK_SIZE	;\
-	l.sw	0x00(r1), r2			;\
-	l.sw	0x1c(r1), r9			;\
-	l.movhi r2,hi(_exception_handler)       ;\
-	l.ori   r2,r2,lo(_exception_handler)    ;\
-	l.jalr	r2              		;\
-	 l.nop					;\
-	l.lwz 	r9, 0x1c(r1)			;\
-	l.addi	r1, r1, EXCEPTION_STACK_SIZE	;\
-	l.rfe					;\
-	 l.nop
-
-	.section .vectors, "ax"
-	.global __reset
-
-	/* reset */
-	.org	0x100
-__reset:
-	/* there is no guarantee r0 is hardwired to zero, clear it here */
-	l.andi	r0, r0, 0
-	/* reset stack and frame pointers */
-	l.andi	r1, r0, 0
-	l.andi	r2, r0, 0
-
-	/* set supervisor mode */
-	l.ori	r3,r0,SPR_SR_SM
-	l.mtspr	r0,r3,SPR_SR
-
-	l.jal	_cur
-	l.nop
-_cur:
-	l.ori	r8, r9, 0		/* Get _cur current address */
-
-	l.movhi	r3, hi(_cur)
-	l.ori	r3, r3, lo(_cur)
-	l.sfeq	r8, r3			/* If we are running at the linked address */
-	l.bf	_no_vector_reloc	/* there is not need for relocation */
-	 l.sub	r8, r8, r3
-
-	l.mfspr	r4, r0, SPR_CPUCFGR
-	l.andi	r4, r4, SPR_CPUCFGR_EVBARP	/* Exception Vector Base Address Register present ? */
-	l.sfnei	r4,0
-	l.bnf	_reloc_vectors
-	l.movhi	r5, 0			/* Destination */
-
-	l.mfspr	r4, r0, SPR_EVBAR
-	l.add	r5, r5, r4
-
-_reloc_vectors:
-	/* Relocate vectors*/
-	l.movhi	r5, 0			/* Destination */
-	l.movhi	r6, hi(__start)		/* Length */
-	l.ori	r6, r6, lo(__start)
-	l.ori	r3, r8, 0
-
-.L_relocvectors:
-	l.lwz	r7, 0(r3)
-	l.sw	0(r5), r7
-	l.addi	r5, r5, 4
-	l.sfeq	r5, r6
-	l.bnf	.L_relocvectors
-	 l.addi	r3, r3, 4
-
-_no_vector_reloc:
-
-	/* Relocate u-boot */
-	l.movhi	r3,hi(__start)		/* source start offset */
-	l.ori	r3,r3,lo(__start)
-	l.add	r3,r8,r3
-
-	l.movhi	r4,hi(_stext)		/* dest start address */
-	l.ori	r4,r4,lo(_stext)
-	l.movhi	r5,hi(__end)		/* dest end address */
-	l.ori	r5,r5,lo(__end)
-
-.L_reloc:
-	l.lwz	r6,0(r3)
-	l.sw	0(r4),r6
-	l.addi	r3,r3,4
-	l.sfltu	r4,r5
-	l.bf	.L_reloc
-	 l.addi	r4,r4,4			/* delay slot */
-
-	l.movhi	r4,hi(_start)
-	l.ori	r4,r4,lo(_start)
-	l.jr	r4
-	 l.nop
-
-	/* bus error */
-	.org	0x200
-	HANDLE_EXCEPTION
-
-	/* data page fault */
-	.org	0x300
-	HANDLE_EXCEPTION
-
-	/* instruction page fault */
-	.org	0x400
-	HANDLE_EXCEPTION
-
-	/* tick timer */
-	.org	0x500
-	HANDLE_EXCEPTION
-
-	/* alignment */
-	.org	0x600
-	HANDLE_EXCEPTION
-
-	/* illegal instruction */
-	.org	0x700
-	HANDLE_EXCEPTION
-
-	/* external interrupt */
-	.org	0x800
-	HANDLE_EXCEPTION
-
-	/* D-TLB miss */
-	.org	0x900
-	HANDLE_EXCEPTION
-
-	/* I-TLB miss */
-	.org	0xa00
-	HANDLE_EXCEPTION
-
-	/* range */
-	.org	0xb00
-	HANDLE_EXCEPTION
-
-	/* system call */
-	.org	0xc00
-	HANDLE_EXCEPTION
-
-	/* floating point */
-	.org	0xd00
-	HANDLE_EXCEPTION
-
-	/* trap */
-	.org	0xe00
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0xf00
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1100
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1200
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1300
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1400
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1500
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1600
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1700
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1800
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1900
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1a00
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1b00
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1c00
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1d00
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1e00
-	HANDLE_EXCEPTION
-
-	/* reserved */
-	.org	0x1f00
-	HANDLE_EXCEPTION
-
-	/* Startup routine */
-	.text
-	.global _start
-_start:
-	/* Init stack and frame pointers */
-	l.movhi	r1, hi(CONFIG_SYS_INIT_SP_ADDR)
-	l.ori	r1, r1, lo(CONFIG_SYS_INIT_SP_ADDR)
-	l.or	r2, r0, r1
-
-	/* clear BSS segments */
-	l.movhi	r4, hi(_bss_start)
-	l.ori	r4, r4, lo(_bss_start)
-	l.movhi	r5, hi(_bss_end)
-	l.ori	r5, r5, lo(_bss_end)
-.L_clear_bss:
-	l.sw	0(r4), r0
-	l.sfltu	r4,r5
-	l.bf	.L_clear_bss
-	 l.addi	r4,r4,4
-
-	/* Reset registers before jumping to board_init */
-	l.andi	r3, r0, 0
-	l.andi	r4, r0, 0
-	l.andi	r5, r0, 0
-	l.andi	r6, r0, 0
-	l.andi	r7, r0, 0
-	l.andi	r8, r0, 0
-	l.andi	r9, r0, 0
-	l.andi	r10, r0, 0
-	l.andi	r11, r0, 0
-	l.andi	r12, r0, 0
-	l.andi	r13, r0, 0
-	l.andi	r14, r0, 0
-	l.andi	r15, r0, 0
-	l.andi	r17, r0, 0
-	l.andi	r18, r0, 0
-	l.andi	r19, r0, 0
-	l.andi	r20, r0, 0
-	l.andi	r21, r0, 0
-	l.andi	r22, r0, 0
-	l.andi	r23, r0, 0
-	l.andi	r24, r0, 0
-	l.andi	r25, r0, 0
-	l.andi	r26, r0, 0
-	l.andi	r27, r0, 0
-	l.andi	r28, r0, 0
-	l.andi	r29, r0, 0
-	l.andi	r30, r0, 0
-	l.andi	r31, r0, 0
-
-	l.j	board_init
-	 l.nop
-
-	.size	_start, .-_start
-
-/*
- * Store state onto stack and call the real exception handler
- */
-	.section .text
-	.extern	exception_handler
-	.type	_exception_handler,@function
-
-_exception_handler:
-	/* Store state (r2 and r9 already saved)*/
-	l.sw	0x04(r1), r3
-	l.sw	0x08(r1), r4
-	l.sw	0x0c(r1), r5
-	l.sw	0x10(r1), r6
-	l.sw	0x14(r1), r7
-	l.sw	0x18(r1), r8
-	l.sw	0x20(r1), r10
-	l.sw	0x24(r1), r11
-	l.sw	0x28(r1), r12
-	l.sw	0x2c(r1), r13
-	l.sw	0x30(r1), r14
-	l.sw	0x34(r1), r15
-	l.sw	0x38(r1), r16
-	l.sw	0x3c(r1), r17
-	l.sw	0x40(r1), r18
-	l.sw	0x44(r1), r19
-	l.sw	0x48(r1), r20
-	l.sw	0x4c(r1), r21
-	l.sw	0x50(r1), r22
-	l.sw	0x54(r1), r23
-	l.sw	0x58(r1), r24
-	l.sw	0x5c(r1), r25
-	l.sw	0x60(r1), r26
-	l.sw	0x64(r1), r27
-	l.sw	0x68(r1), r28
-	l.sw	0x6c(r1), r29
-	l.sw	0x70(r1), r30
-	l.sw	0x74(r1), r31
-
-	/* Save return address */
-	l.or	r14, r0, r9
-	/* Call exception handler with the link address as argument */
-	l.jal	exception_handler
-	 l.or	r3, r0, r14
-	/* Load return address */
-	l.or	r9, r0, r14
-
-	/* Restore state */
-	l.lwz	r2, 0x00(r1)
-	l.lwz	r3, 0x04(r1)
-	l.lwz	r4, 0x08(r1)
-	l.lwz	r5, 0x0c(r1)
-	l.lwz	r6, 0x10(r1)
-	l.lwz	r7, 0x14(r1)
-	l.lwz	r8, 0x18(r1)
-	l.lwz	r10, 0x20(r1)
-	l.lwz	r11, 0x24(r1)
-	l.lwz	r12, 0x28(r1)
-	l.lwz	r13, 0x2c(r1)
-	l.lwz	r14, 0x30(r1)
-	l.lwz	r15, 0x34(r1)
-	l.lwz	r16, 0x38(r1)
-	l.lwz	r17, 0x3c(r1)
-	l.lwz	r18, 0x40(r1)
-	l.lwz	r19, 0x44(r1)
-	l.lwz	r20, 0x48(r1)
-	l.lwz	r21, 0x4c(r1)
-	l.lwz	r22, 0x50(r1)
-	l.lwz	r23, 0x54(r1)
-	l.lwz	r24, 0x58(r1)
-	l.lwz	r25, 0x5c(r1)
-	l.lwz	r26, 0x60(r1)
-	l.lwz	r27, 0x64(r1)
-	l.lwz	r28, 0x68(r1)
-	l.lwz	r29, 0x6c(r1)
-	l.lwz	r30, 0x70(r1)
-	l.lwz	r31, 0x74(r1)
-	l.jr	r9
-	 l.nop
diff --git a/arch/openrisc/cpu/u-boot.lds b/arch/openrisc/cpu/u-boot.lds
deleted file mode 100644
index 854088b..0000000
--- a/arch/openrisc/cpu/u-boot.lds
+++ /dev/null
@@ -1,77 +0,0 @@
-#include <config.h>
-OUTPUT_ARCH(or1k)
-__DYNAMIC  =  0;
-
-MEMORY
-{
-	vectors	: ORIGIN = 0, LENGTH = 0x2000
-	ram	: ORIGIN = CONFIG_SYS_MONITOR_BASE,
-		  LENGTH = CONFIG_SYS_MONITOR_LEN
-}
-
-SECTIONS
-{
-	.vectors :
-	{
-		*(.vectors)
-	} > vectors
-
-	__start = .;
-	.text : AT (__start) {
-		_stext = .;
-		*(.text)
-		_etext = .;
-		*(.lit)
-		*(.shdata)
-		_endtext = .;
-	}  > ram
-
-
-	 . = ALIGN(4);
-	 .u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	 } > ram
-
-	.rodata : {
-		*(.rodata);
-		*(.rodata.*)
-	} > ram
-
-	.shbss :
-	{
-		*(.shbss)
-	} > ram
-
-	.talias :
-	{
-	}  > ram
-
-	.data : {
-		sdata = .;
-		_sdata = .;
-		*(.data)
-		edata = .;
-		_edata = .;
-	} > ram
-
-	.bss :
-	{
-		_bss_start = .;
-		*(.bss)
-		*(COMMON)
-		_bss_end = .;
-	} > ram
-	__end = .;
-
-	/* No stack specification - done manually */
-
-	.stab  0 (NOLOAD) :
-	{
-		[ .stab ]
-	}
-
-	.stabstr  0 (NOLOAD) :
-	{
-		[ .stabstr ]
-	}
-}
diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h
deleted file mode 100644
index 28c4658..0000000
--- a/arch/openrisc/include/asm/bitops.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_BITOPS_H
-#define __ASM_OPENRISC_BITOPS_H
-
-#define PLATFORM_FLS
-#include <asm/bitops/fls.h>
-#define PLATFORM_FFS
-#include <asm/bitops/ffs.h>
-
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/__ffs.h>
-
-#define hweight32(x) generic_hweight32(x)
-#define hweight16(x) generic_hweight16(x)
-#define hweight8(x) generic_hweight8(x)
-
-#endif /* __ASM_GENERIC_BITOPS_H */
diff --git a/arch/openrisc/include/asm/bitops/ffs.h b/arch/openrisc/include/asm/bitops/ffs.h
deleted file mode 100644
index 50746cf..0000000
--- a/arch/openrisc/include/asm/bitops/ffs.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * OpenRISC Linux
- *
- * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_FFS_H
-#define __ASM_OPENRISC_FFS_H
-
-static inline int ffs(int x)
-{
-	int ret;
-
-	__asm__ ("l.ff1 %0,%1"
-		 : "=r" (ret)
-		 : "r" (x));
-
-	return ret;
-}
-
-#endif /* __ASM_OPENRISC_FFS_H */
diff --git a/arch/openrisc/include/asm/bitops/fls.h b/arch/openrisc/include/asm/bitops/fls.h
deleted file mode 100644
index 7447229..0000000
--- a/arch/openrisc/include/asm/bitops/fls.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * OpenRISC Linux
- *
- * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_FLS_H
-#define __ASM_OPENRISC_FLS_H
-
-static inline int fls(int x)
-{
-	int ret;
-
-	__asm__ ("l.fl1 %0,%1"
-		 : "=r" (ret)
-		 : "r" (x));
-
-	return ret;
-}
-
-#endif /* __ASM_OPENRISC_FLS_H */
diff --git a/arch/openrisc/include/asm/byteorder.h b/arch/openrisc/include/asm/byteorder.h
deleted file mode 100644
index 60d14f7..0000000
--- a/arch/openrisc/include/asm/byteorder.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <linux/byteorder/big_endian.h>
diff --git a/arch/openrisc/include/asm/cache.h b/arch/openrisc/include/asm/cache.h
deleted file mode 100644
index 22d4370..0000000
--- a/arch/openrisc/include/asm/cache.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_CACHE_H_
-#define __ASM_OPENRISC_CACHE_H_
-
-/*
- * Valid L1 data cache line sizes for the OpenRISC architecture are
- * 16 and 32 bytes.
- * If the board configuration has not specified one we default to the
- * largest of these values for alignment of DMA buffers.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN       CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN       32
-#endif
-
-#endif /* __ASM_OPENRISC_CACHE_H_ */
diff --git a/arch/openrisc/include/asm/config.h b/arch/openrisc/include/asm/config.h
deleted file mode 100644
index cd29734..0000000
--- a/arch/openrisc/include/asm/config.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_CONFIG_H_
-#define _ASM_CONFIG_H_
-
-#endif
diff --git a/arch/openrisc/include/asm/global_data.h b/arch/openrisc/include/asm/global_data.h
deleted file mode 100644
index 428ce1b..0000000
--- a/arch/openrisc/include/asm/global_data.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2004 Atmark Techno, Inc.
- *
- * Yasushi SHOJI <yashi@atmark-techno.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-
-/* Architecture-specific global data */
-struct arch_global_data {
-};
-
-#include <asm-generic/global_data.h>
-
-/* OR32 GCC already has r10 set as fixed-use */
-#define DECLARE_GLOBAL_DATA_PTR	register volatile gd_t *gd asm ("r10")
-
-#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/openrisc/include/asm/gpio.h b/arch/openrisc/include/asm/gpio.h
deleted file mode 100644
index c57a430..0000000
--- a/arch/openrisc/include/asm/gpio.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * OpenRISC gpio driver
- *
- * Copyright (C) 2011 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * based on nios2 gpio driver
- * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
- *
- * when CONFIG_SYS_GPIO_BASE is not defined, board may provide
- * its own driver.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifdef CONFIG_SYS_GPIO_BASE
-#include <asm/io.h>
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-	return 0;
-}
-
-static inline int gpio_free(unsigned gpio)
-{
-	return 0;
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
-	return (readb(CONFIG_SYS_GPIO_BASE + gpio/8) >> gpio%8) & 0x1;
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-	u8 tmp = readb(CONFIG_SYS_GPIO_BASE + gpio/8);
-
-	if (value)
-		tmp |= (1 << gpio%8);
-	else
-		tmp &= ~(1 << gpio%8);
-	writeb(tmp, CONFIG_SYS_GPIO_BASE + gpio/8);
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
-	gpio_set_value(gpio + CONFIG_SYS_GPIO_WIDTH, 0);
-
-	return 0;
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-	gpio_set_value(gpio + CONFIG_SYS_GPIO_WIDTH, 1);
-	gpio_set_value(gpio, value);
-
-	return 0;
-}
-
-static inline int gpio_is_valid(int number)
-{
-	return ((unsigned)number) < CONFIG_SYS_GPIO_WIDTH;
-}
-#else
-extern int gpio_request(unsigned gpio, const char *label);
-extern int gpio_free(unsigned gpio);
-extern int gpio_direction_input(unsigned gpio);
-extern int gpio_direction_output(unsigned gpio, int value);
-extern int gpio_get_value(unsigned gpio);
-extern void gpio_set_value(unsigned gpio, int value);
-extern int gpio_is_valid(int number);
-#endif /* CONFIG_SYS_GPIO_BASE */
diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h
deleted file mode 100644
index 86fbbc4..0000000
--- a/arch/openrisc/include/asm/io.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_IO_H
-#define __ASM_OPENRISC_IO_H
-
-/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
- */
-#define MAP_NOCACHE	(0)
-#define MAP_WRCOMBINE	(0)
-#define MAP_WRBACK	(0)
-#define MAP_WRTHROUGH	(0)
-
-static inline void *
-map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
-{
-	return (void *)paddr;
-}
-
-/*
- * Take down a mapping set up by map_physmem().
- */
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-
-}
-
-/*
- * Change virtual addresses to physical addresses
- */
-static inline phys_addr_t virt_to_phys(void *vaddr)
-{
-	return (phys_addr_t)(vaddr);
-}
-
-
-/*
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the openrisc architecture, we just read/write the
- * memory location directly.
- */
-#define readb(addr) (*(volatile unsigned char *) (addr))
-#define readw(addr) (*(volatile unsigned short *) (addr))
-#define readl(addr) (*(volatile unsigned int *) (addr))
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-
-#define writeb(b, addr) ((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b, addr) ((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b, addr) ((*(volatile unsigned int *) (addr)) = (b))
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-
-#define memset_io(a, b, c)	memset((void *)(a), (b), (c))
-#define memcpy_fromio(a, b, c)	memcpy((a), (void *)(b), (c))
-#define memcpy_toio(a, b, c)	memcpy((void *)(a), (b), (c))
-
-/*
- * Again, OpenRISC does not require mem IO specific function.
- */
-
-
-#define IO_BASE			0x0
-#define IO_SPACE_LIMIT		0xffffffff
-
-#define inb(port)		readb((port + IO_BASE))
-#define outb(value, port)	writeb((value), (port + IO_BASE))
-#define inb_p(port)		inb((port))
-#define outb_p(value, port)	outb((value), (port))
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)	__va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)	p
-
-#define ioread8(addr)		readb(addr)
-#define ioread16(addr)		readw(addr)
-#define ioread32(addr)		readl(addr)
-
-#define iowrite8(v, addr)	writeb((v), (addr))
-#define iowrite16(v, addr)	writew((v), (addr))
-#define iowrite32(v, addr)	writel((v), (addr))
-
-#endif
diff --git a/arch/openrisc/include/asm/linkage.h b/arch/openrisc/include/asm/linkage.h
deleted file mode 100644
index e69de29..0000000
--- a/arch/openrisc/include/asm/linkage.h
+++ /dev/null
diff --git a/arch/openrisc/include/asm/openrisc_exc.h b/arch/openrisc/include/asm/openrisc_exc.h
deleted file mode 100644
index a53ed82..0000000
--- a/arch/openrisc/include/asm/openrisc_exc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _OPENRISC_EXC_H_
-#define _OPENRISC_EXC_H_
-
-#define EXC_RESET		0x01
-#define EXC_BUS_ERROR		0x02
-#define EXC_DATA_PAGE_FAULT	0x03
-#define EXC_INSTR_PAGE_FAULT	0x04
-#define EXC_TIMER		0x05
-#define EXC_ALIGNMENT		0x06
-#define EXC_ILLEGAL_INSTR	0x07
-#define EXC_EXT_IRQ		0x08
-#define EXC_DTLB_MISS		0x09
-#define EXC_ITLB_MISS		0x0a
-#define EXC_RANGE		0x0b
-#define EXC_SYSCALL		0x0c
-#define EXC_FLOAT_POINT		0x0d
-#define EXC_TRAP		0x0e
-
-void exception_install_handler(int exception, void (*handler)(void));
-void exception_free_handler(int exception);
-
-#endif
diff --git a/arch/openrisc/include/asm/posix_types.h b/arch/openrisc/include/asm/posix_types.h
deleted file mode 100644
index d1fffe0..0000000
--- a/arch/openrisc/include/asm/posix_types.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Based on microblaze implementation:
- *  Copyright (C) 2003       John Williams <jwilliams@itee.uq.edu.au>
- *  Copyright (C) 2001,2002  NEC Corporation
- *  Copyright (C) 2001,2002  Miles Bader <miles@gnu.org>
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License.  See the file COPYING in the main directory of this
- * archive for more details.
- *
- * Written by Miles Bader <miles@gnu.org>
- * Microblaze port by John Williams
- */
-
-#ifndef __ASM_OPENRISC_POSIX_TYPES_H
-#define __ASM_OPENRISC_POSIX_TYPES_H
-
-typedef unsigned int	__kernel_dev_t;
-typedef unsigned long	__kernel_ino_t;
-typedef unsigned long long __kernel_ino64_t;
-typedef unsigned int	__kernel_mode_t;
-typedef unsigned int	__kernel_nlink_t;
-typedef long		__kernel_off_t;
-typedef long long	__kernel_loff_t;
-typedef int		__kernel_pid_t;
-typedef unsigned short	__kernel_ipc_pid_t;
-typedef unsigned int	__kernel_uid_t;
-typedef unsigned int	__kernel_gid_t;
-typedef unsigned int	__kernel_size_t;
-typedef int		__kernel_ssize_t;
-typedef int		__kernel_ptrdiff_t;
-typedef long		__kernel_time_t;
-typedef long		__kernel_suseconds_t;
-typedef long		__kernel_clock_t;
-typedef int		__kernel_daddr_t;
-typedef char		*__kernel_caddr_t;
-typedef unsigned short	__kernel_uid16_t;
-typedef unsigned short	__kernel_gid16_t;
-typedef unsigned int	__kernel_uid32_t;
-typedef unsigned int	__kernel_gid32_t;
-
-typedef unsigned short	__kernel_old_uid_t;
-typedef unsigned short	__kernel_old_gid_t;
-
-
-typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
-	int	val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
-	int	__val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
-} __kernel_fsid_t;
-
-
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
-
-#undef __FD_SET
-#define __FD_SET(fd, fd_set) \
-	__set_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
-#undef __FD_CLR
-#define __FD_CLR(fd, fd_set) \
-	__clear_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
-#undef __FD_ISSET
-#define __FD_ISSET(fd, fd_set) \
-	__test_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
-#undef __FD_ZERO
-#define __FD_ZERO(fd_set) \
-	memset(fd_set, 0, sizeof(*(fd_set *)fd_set))
-
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
-
-#endif /* __ASM_OPENRISC_POSIX_TYPES_H */
diff --git a/arch/openrisc/include/asm/processor.h b/arch/openrisc/include/asm/processor.h
deleted file mode 100644
index 304c95f..0000000
--- a/arch/openrisc/include/asm/processor.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASM_OPENRISC_PROCESSOR_H
-#define __ASM_OPENRISC_PROCESSOR_H
-
-#endif
diff --git a/arch/openrisc/include/asm/ptrace.h b/arch/openrisc/include/asm/ptrace.h
deleted file mode 100644
index 6608d8a..0000000
--- a/arch/openrisc/include/asm/ptrace.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * OpenRISC Linux
- *
- * Linux architectural port borrowing liberally from similar works of
- * others.  All original copyrights apply as per the original source
- * declaration.
- *
- * OpenRISC implementation:
- * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
- * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
- * et al.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_PTRACE_H
-#define __ASM_OPENRISC_PTRACE_H
-
-#include <asm/spr-defs.h>
-
-#ifndef __ASSEMBLY__
-/*
- * This is the layout of the regset returned by the GETREGSET ptrace call
- */
-struct user_regs_struct {
-	/* GPR R0-R31... */
-	unsigned long gpr[32];
-	unsigned long pc;
-	unsigned long sr;
-	unsigned long pad1;
-	unsigned long pad2;
-};
-#endif
-
-#ifdef __KERNEL__
-
-/*
- * Make kernel PTrace/register structures opaque to userspace... userspace can
- * access thread state via the regset mechanism.  This allows us a bit of
- * flexibility in how we order the registers on the stack, permitting some
- * optimizations like packing call-clobbered registers together so that
- * they share a cacheline (not done yet, though... future optimization).
- */
-
-#ifndef __ASSEMBLY__
-/*
- * This struct describes how the registers are laid out on the kernel stack
- * during a syscall or other kernel entry.
- *
- * This structure should always be cacheline aligned on the stack.
- * FIXME: I don't think that's the case right now.  The alignment is
- * taken care of elsewhere... head.S, process.c, etc.
- */
-
-struct pt_regs {
-	union {
-		struct {
-			/* Named registers */
-			long  sr;	/* Stored in place of r0 */
-			long  sp;	/* r1 */
-		};
-		struct {
-			/* Old style */
-			long offset[2];
-			long gprs[30];
-		};
-		struct {
-			/* New style */
-			long gpr[32];
-		};
-	};
-	long  pc;
-	long  orig_gpr11;	/* For restarting system calls */
-	long  syscallno;	/* Syscall number (used by strace) */
-	long dummy;		/* Cheap alignment fix */
-};
-#endif /* __ASSEMBLY__ */
-
-/* TODO: Rename this to REDZONE because that's what it is */
-#define STACK_FRAME_OVERHEAD  128  /* size of minimum stack frame */
-
-#define instruction_pointer(regs)	((regs)->pc)
-#define user_mode(regs)			(((regs)->sr & SPR_SR_SM) == 0)
-#define user_stack_pointer(regs)	((unsigned long)(regs)->sp)
-#define profile_pc(regs)		instruction_pointer(regs)
-
-/*
- * Offsets used by 'ptrace' system call interface.
- */
-#define PT_SR         0
-#define PT_SP         4
-#define PT_GPR2       8
-#define PT_GPR3       12
-#define PT_GPR4       16
-#define PT_GPR5       20
-#define PT_GPR6       24
-#define PT_GPR7       28
-#define PT_GPR8       32
-#define PT_GPR9       36
-#define PT_GPR10      40
-#define PT_GPR11      44
-#define PT_GPR12      48
-#define PT_GPR13      52
-#define PT_GPR14      56
-#define PT_GPR15      60
-#define PT_GPR16      64
-#define PT_GPR17      68
-#define PT_GPR18      72
-#define PT_GPR19      76
-#define PT_GPR20      80
-#define PT_GPR21      84
-#define PT_GPR22      88
-#define PT_GPR23      92
-#define PT_GPR24      96
-#define PT_GPR25      100
-#define PT_GPR26      104
-#define PT_GPR27      108
-#define PT_GPR28      112
-#define PT_GPR29      116
-#define PT_GPR30      120
-#define PT_GPR31      124
-#define PT_PC	      128
-#define PT_ORIG_GPR11 132
-#define PT_SYSCALLNO  136
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASM_OPENRISC_PTRACE_H */
diff --git a/arch/openrisc/include/asm/sections.h b/arch/openrisc/include/asm/sections.h
deleted file mode 100644
index bbe20f7..0000000
--- a/arch/openrisc/include/asm/sections.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2012 The Chromium OS Authors.
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_SECTIONS_H
-#define __ASM_OPENRISC_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/arch/openrisc/include/asm/spr-defs.h b/arch/openrisc/include/asm/spr-defs.h
deleted file mode 100644
index e30d210..0000000
--- a/arch/openrisc/include/asm/spr-defs.h
+++ /dev/null
@@ -1,575 +0,0 @@
-/*
- * SPR Definitions
- *
- * Copyright (C) 2000 Damjan Lampret
- * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
- * Copyright (C) 2008, 2010 Embecosm Limited
- * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
- * et al.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * This file is part of OpenRISC 1000 Architectural Simulator.
- */
-
-#ifndef SPR_DEFS__H
-#define SPR_DEFS__H
-
-/* Definition of special-purpose registers (SPRs) */
-
-#define MAX_GRPS (32)
-#define MAX_SPRS_PER_GRP_BITS (11)
-#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
-#define MAX_SPRS (0x10000)
-
-/* Base addresses for the groups */
-#define SPRGROUP_SYS	(0 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_DMMU	(1 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_IMMU	(2 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_DC	(3 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_IC	(4 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_MAC	(5 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_D	(6 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_PC	(7 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_PM	(8 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_PIC	(9 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_TT	(10 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_FP	(11 << MAX_SPRS_PER_GRP_BITS)
-
-/* System control and status group */
-#define SPR_VR		(SPRGROUP_SYS + 0)
-#define SPR_UPR		(SPRGROUP_SYS + 1)
-#define SPR_CPUCFGR	(SPRGROUP_SYS + 2)
-#define SPR_DMMUCFGR	(SPRGROUP_SYS + 3)
-#define SPR_IMMUCFGR	(SPRGROUP_SYS + 4)
-#define SPR_DCCFGR	(SPRGROUP_SYS + 5)
-#define SPR_ICCFGR	(SPRGROUP_SYS + 6)
-#define SPR_DCFGR	(SPRGROUP_SYS + 7)
-#define SPR_PCCFGR	(SPRGROUP_SYS + 8)
-#define SPR_VR2		(SPRGROUP_SYS + 9)
-#define SPR_AVR		(SPRGROUP_SYS + 10)
-#define SPR_EVBAR	(SPRGROUP_SYS + 11)
-#define SPR_AECR	(SPRGROUP_SYS + 12)
-#define SPR_AESR	(SPRGROUP_SYS + 13)
-#define SPR_NPC		(SPRGROUP_SYS + 16)
-#define SPR_SR		(SPRGROUP_SYS + 17)
-#define SPR_PPC		(SPRGROUP_SYS + 18)
-#define SPR_FPCSR	(SPRGROUP_SYS + 20)
-#define SPR_EPCR_BASE	(SPRGROUP_SYS + 32)
-#define SPR_EPCR_LAST	(SPRGROUP_SYS + 47)
-#define SPR_EEAR_BASE	(SPRGROUP_SYS + 48)
-#define SPR_EEAR_LAST	(SPRGROUP_SYS + 63)
-#define SPR_ESR_BASE	(SPRGROUP_SYS + 64)
-#define SPR_ESR_LAST	(SPRGROUP_SYS + 79)
-#define SPR_GPR_BASE	(SPRGROUP_SYS + 1024)
-
-/* Data MMU group */
-#define SPR_DMMUCR	(SPRGROUP_DMMU + 0)
-#define SPR_DTLBEIR	(SPRGROUP_DMMU + 2)
-#define SPR_DTLBMR_BASE(WAY)	(SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
-#define SPR_DTLBMR_LAST(WAY)	(SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
-#define SPR_DTLBTR_BASE(WAY)	(SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
-#define SPR_DTLBTR_LAST(WAY)	(SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
-
-/* Instruction MMU group */
-#define SPR_IMMUCR	(SPRGROUP_IMMU + 0)
-#define SPR_ITLBEIR	(SPRGROUP_IMMU + 2)
-#define SPR_ITLBMR_BASE(WAY)	(SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
-#define SPR_ITLBMR_LAST(WAY)	(SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
-#define SPR_ITLBTR_BASE(WAY)	(SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
-#define SPR_ITLBTR_LAST(WAY)	(SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
-
-/* Data cache group */
-#define SPR_DCCR	(SPRGROUP_DC + 0)
-#define SPR_DCBPR	(SPRGROUP_DC + 1)
-#define SPR_DCBFR	(SPRGROUP_DC + 2)
-#define SPR_DCBIR	(SPRGROUP_DC + 3)
-#define SPR_DCBWR	(SPRGROUP_DC + 4)
-#define SPR_DCBLR	(SPRGROUP_DC + 5)
-#define SPR_DCR_BASE(WAY)	(SPRGROUP_DC + 0x200 + (WAY) * 0x200)
-#define SPR_DCR_LAST(WAY)	(SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
-
-/* Instruction cache group */
-#define SPR_ICCR	(SPRGROUP_IC + 0)
-#define SPR_ICBPR	(SPRGROUP_IC + 1)
-#define SPR_ICBIR	(SPRGROUP_IC + 2)
-#define SPR_ICBLR	(SPRGROUP_IC + 3)
-#define SPR_ICR_BASE(WAY)	(SPRGROUP_IC + 0x200 + (WAY) * 0x200)
-#define SPR_ICR_LAST(WAY)	(SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
-
-/* MAC group */
-#define SPR_MACLO	(SPRGROUP_MAC + 1)
-#define SPR_MACHI	(SPRGROUP_MAC + 2)
-
-/* Debug group */
-#define SPR_DVR(N)	(SPRGROUP_D + (N))
-#define SPR_DCR(N)	(SPRGROUP_D + 8 + (N))
-#define SPR_DMR1	(SPRGROUP_D + 16)
-#define SPR_DMR2	(SPRGROUP_D + 17)
-#define SPR_DWCR0	(SPRGROUP_D + 18)
-#define SPR_DWCR1	(SPRGROUP_D + 19)
-#define SPR_DSR		(SPRGROUP_D + 20)
-#define SPR_DRR		(SPRGROUP_D + 21)
-
-/* Performance counters group */
-#define SPR_PCCR(N)	(SPRGROUP_PC + (N))
-#define SPR_PCMR(N)	(SPRGROUP_PC + 8 + (N))
-
-/* Power management group */
-#define SPR_PMR		(SPRGROUP_PM + 0)
-
-/* PIC group */
-#define SPR_PICMR	(SPRGROUP_PIC + 0)
-#define SPR_PICPR	(SPRGROUP_PIC + 1)
-#define SPR_PICSR	(SPRGROUP_PIC + 2)
-
-/* Tick Timer group */
-#define SPR_TTMR	(SPRGROUP_TT + 0)
-#define SPR_TTCR	(SPRGROUP_TT + 1)
-
-/*
- * Bit definitions for the Version Register
- */
-#define SPR_VR_VER	0xff000000 /* Processor version */
-#define SPR_VR_CFG	0x00ff0000 /* Processor configuration */
-#define SPR_VR_RES	0x0000ffc0 /* Reserved */
-#define SPR_VR_REV	0x0000003f /* Processor revision */
-
-#define SPR_VR_VER_OFF	24
-#define SPR_VR_CFG_OFF	16
-#define SPR_VR_REV_OFF	0
-
-/*
- * Bit definitions for the Unit Present Register
- */
-#define SPR_UPR_UP	0x00000001 /* UPR present */
-#define SPR_UPR_DCP	0x00000002 /* Data cache present */
-#define SPR_UPR_ICP	0x00000004 /* Instruction cache present */
-#define SPR_UPR_DMP	0x00000008 /* Data MMU present */
-#define SPR_UPR_IMP	0x00000010 /* Instruction MMU present */
-#define SPR_UPR_MP	0x00000020 /* MAC present */
-#define SPR_UPR_DUP	0x00000040 /* Debug unit present */
-#define SPR_UPR_PCUP	0x00000080 /* Performance counters unit present */
-#define SPR_UPR_PMP	0x00000100 /* Power management present */
-#define SPR_UPR_PICP	0x00000200 /* PIC present */
-#define SPR_UPR_TTP	0x00000400 /* Tick timer present */
-#define SPR_UPR_RES	0x00fe0000 /* Reserved */
-#define SPR_UPR_CUP	0xff000000 /* Context units present */
-
-/*
- * Bit definitions for the CPU configuration register
- */
-#define SPR_CPUCFGR_NSGF	0x0000000f /* Number of shadow GPR files */
-#define SPR_CPUCFGR_CGF		0x00000010 /* Custom GPR file */
-#define SPR_CPUCFGR_OB32S	0x00000020 /* ORBIS32 supported */
-#define SPR_CPUCFGR_OB64S	0x00000040 /* ORBIS64 supported */
-#define SPR_CPUCFGR_OF32S	0x00000080 /* ORFPX32 supported */
-#define SPR_CPUCFGR_OF64S	0x00000100 /* ORFPX64 supported */
-#define SPR_CPUCFGR_OV64S	0x00000200 /* ORVDX64 supported */
-#define SPR_CPUCFGR_ND		0x00000400 /* No delay slot */
-#define SPR_CPUCFGR_AVRP	0x00000800 /* Arch. Version Register present */
-#define SPR_CPUCFGR_EVBARP	0x00001000 /* Exception Vector Base Address Register (EVBAR) present */
-#define SPR_CPUCFGR_ISRP	0x00002000 /* Implementation-Specific Registers (ISR0-7) present */
-#define SPR_CPUCFGR_AECSRP	0x00004000 /* Arithmetic Exception Control Register (AECR) and */
-					   /* Arithmetic Exception Status Register (AESR) presents */
-#define SPR_CPUCFGR_RES		0xffffc000 /* Reserved */
-
-/*
- * Bit definitions for the Debug configuration register and other
- * constants.
- */
-
-#define SPR_DCFGR_NDP	0x00000007  /* Number of matchpoints mask */
-#define SPR_DCFGR_NDP1	0x00000000  /* One matchpoint supported */
-#define SPR_DCFGR_NDP2	0x00000001  /* Two matchpoints supported */
-#define SPR_DCFGR_NDP3	0x00000002  /* Three matchpoints supported */
-#define SPR_DCFGR_NDP4	0x00000003  /* Four matchpoints supported */
-#define SPR_DCFGR_NDP5	0x00000004  /* Five matchpoints supported */
-#define SPR_DCFGR_NDP6	0x00000005  /* Six matchpoints supported */
-#define SPR_DCFGR_NDP7	0x00000006  /* Seven matchpoints supported */
-#define SPR_DCFGR_NDP8	0x00000007  /* Eight matchpoints supported */
-#define SPR_DCFGR_WPCI	0x00000008  /* Watchpoint counters implemented */
-
-#define MATCHPOINTS_TO_NDP(n)	(1 == n ? SPR_DCFGR_NDP1 : \
-				2 == n ? SPR_DCFGR_NDP2 : \
-				3 == n ? SPR_DCFGR_NDP3 : \
-				4 == n ? SPR_DCFGR_NDP4 : \
-				5 == n ? SPR_DCFGR_NDP5 : \
-				6 == n ? SPR_DCFGR_NDP6 : \
-				7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
-#define MAX_MATCHPOINTS	8
-#define MAX_WATCHPOINTS	(MAX_MATCHPOINTS + 2)
-
-/*
- * Bit definitions for the Supervision Register
- */
-#define SPR_SR_SM	0x00000001 /* Supervisor Mode */
-#define SPR_SR_TEE	0x00000002 /* Tick timer Exception Enable */
-#define SPR_SR_IEE	0x00000004 /* Interrupt Exception Enable */
-#define SPR_SR_DCE	0x00000008 /* Data Cache Enable */
-#define SPR_SR_ICE	0x00000010 /* Instruction Cache Enable */
-#define SPR_SR_DME	0x00000020 /* Data MMU Enable */
-#define SPR_SR_IME	0x00000040 /* Instruction MMU Enable */
-#define SPR_SR_LEE	0x00000080 /* Little Endian Enable */
-#define SPR_SR_CE	0x00000100 /* CID Enable */
-#define SPR_SR_F	0x00000200 /* Condition Flag */
-#define SPR_SR_CY	0x00000400 /* Carry flag */
-#define SPR_SR_OV	0x00000800 /* Overflow flag */
-#define SPR_SR_OVE	0x00001000 /* Overflow flag Exception */
-#define SPR_SR_DSX	0x00002000 /* Delay Slot Exception */
-#define SPR_SR_EPH	0x00004000 /* Exception Prefix High */
-#define SPR_SR_FO	0x00008000 /* Fixed one */
-#define SPR_SR_SUMRA	0x00010000 /* Supervisor SPR read access */
-#define SPR_SR_RES	0x0ffe0000 /* Reserved */
-#define SPR_SR_CID	0xf0000000 /* Context ID */
-
-/*
- * Bit definitions for the Data MMU Control Register
- */
-#define SPR_DMMUCR_P2S		0x0000003e /* Level 2 Page Size */
-#define SPR_DMMUCR_P1S		0x000007c0 /* Level 1 Page Size */
-#define SPR_DMMUCR_VADDR_WIDTH	0x0000f800 /* Virtual ADDR Width */
-#define SPR_DMMUCR_PADDR_WIDTH	0x000f0000 /* Physical ADDR Width */
-
-/*
- * Bit definitions for the Instruction MMU Control Register
- */
-#define SPR_IMMUCR_P2S		0x0000003e /* Level 2 Page Size */
-#define SPR_IMMUCR_P1S		0x000007c0 /* Level 1 Page Size */
-#define SPR_IMMUCR_VADDR_WIDTH	0x0000f800 /* Virtual ADDR Width */
-#define SPR_IMMUCR_PADDR_WIDTH	0x000f0000 /* Physical ADDR Width */
-
-/*
- * Bit definitions for the Data TLB Match Register
- */
-#define SPR_DTLBMR_V	0x00000001 /* Valid */
-#define SPR_DTLBMR_PL1	0x00000002 /* Page Level 1 (if 0 then PL2) */
-#define SPR_DTLBMR_CID	0x0000003c /* Context ID */
-#define SPR_DTLBMR_LRU	0x000000c0 /* Least Recently Used */
-#define SPR_DTLBMR_VPN	0xfffff000 /* Virtual Page Number */
-
-/*
- * Bit definitions for the Data TLB Translate Register
- */
-#define SPR_DTLBTR_CC	0x00000001 /* Cache Coherency */
-#define SPR_DTLBTR_CI	0x00000002 /* Cache Inhibit */
-#define SPR_DTLBTR_WBC	0x00000004 /* Write-Back Cache */
-#define SPR_DTLBTR_WOM	0x00000008 /* Weakly-Ordered Memory */
-#define SPR_DTLBTR_A	0x00000010 /* Accessed */
-#define SPR_DTLBTR_D	0x00000020 /* Dirty */
-#define SPR_DTLBTR_URE	0x00000040 /* User Read Enable */
-#define SPR_DTLBTR_UWE	0x00000080 /* User Write Enable */
-#define SPR_DTLBTR_SRE	0x00000100 /* Supervisor Read Enable */
-#define SPR_DTLBTR_SWE	0x00000200 /* Supervisor Write Enable */
-#define SPR_DTLBTR_PPN	0xfffff000 /* Physical Page Number */
-
-/*
- * Bit definitions for the Instruction TLB Match Register
- */
-#define SPR_ITLBMR_V	0x00000001 /* Valid */
-#define SPR_ITLBMR_PL1	0x00000002 /* Page Level 1 (if 0 then PL2) */
-#define SPR_ITLBMR_CID	0x0000003c /* Context ID */
-#define SPR_ITLBMR_LRU	0x000000c0 /* Least Recently Used */
-#define SPR_ITLBMR_VPN	0xfffff000 /* Virtual Page Number */
-
-/*
- * Bit definitions for the Instruction TLB Translate Register
- */
-#define SPR_ITLBTR_CC	0x00000001 /* Cache Coherency */
-#define SPR_ITLBTR_CI	0x00000002 /* Cache Inhibit */
-#define SPR_ITLBTR_WBC	0x00000004 /* Write-Back Cache */
-#define SPR_ITLBTR_WOM	0x00000008 /* Weakly-Ordered Memory */
-#define SPR_ITLBTR_A	0x00000010 /* Accessed */
-#define SPR_ITLBTR_D	0x00000020 /* Dirty */
-#define SPR_ITLBTR_SXE	0x00000040 /* User Read Enable */
-#define SPR_ITLBTR_UXE	0x00000080 /* User Write Enable */
-#define SPR_ITLBTR_PPN	0xfffff000 /* Physical Page Number */
-
-/*
- * Bit definitions for Data Cache Control register
- */
-#define SPR_DCCR_EW	0x000000ff /* Enable ways */
-
-/*
- * Bit definitions for Insn Cache Control register
- */
-#define SPR_ICCR_EW	0x000000ff /* Enable ways */
-
-/*
- * Bit definitions for Data Cache Configuration Register
- */
-
-#define SPR_DCCFGR_NCW		0x00000007
-#define SPR_DCCFGR_NCS		0x00000078
-#define SPR_DCCFGR_CBS		0x00000080
-#define SPR_DCCFGR_CWS		0x00000100
-#define SPR_DCCFGR_CCRI		0x00000200
-#define SPR_DCCFGR_CBIRI	0x00000400
-#define SPR_DCCFGR_CBPRI	0x00000800
-#define SPR_DCCFGR_CBLRI	0x00001000
-#define SPR_DCCFGR_CBFRI	0x00002000
-#define SPR_DCCFGR_CBWBRI	0x00004000
-
-#define SPR_DCCFGR_NCW_OFF	0
-#define SPR_DCCFGR_NCS_OFF	3
-#define SPR_DCCFGR_CBS_OFF	7
-
-/*
- * Bit definitions for Instruction Cache Configuration Register
- */
-#define SPR_ICCFGR_NCW		0x00000007
-#define SPR_ICCFGR_NCS		0x00000078
-#define SPR_ICCFGR_CBS		0x00000080
-#define SPR_ICCFGR_CCRI		0x00000200
-#define SPR_ICCFGR_CBIRI	0x00000400
-#define SPR_ICCFGR_CBPRI	0x00000800
-#define SPR_ICCFGR_CBLRI	0x00001000
-
-#define SPR_ICCFGR_NCW_OFF	0
-#define SPR_ICCFGR_NCS_OFF	3
-#define SPR_ICCFGR_CBS_OFF	7
-
-/*
- * Bit definitions for Data MMU Configuration Register
- */
-#define SPR_DMMUCFGR_NTW	0x00000003
-#define SPR_DMMUCFGR_NTS	0x0000001C
-#define SPR_DMMUCFGR_NAE	0x000000E0
-#define SPR_DMMUCFGR_CRI	0x00000100
-#define SPR_DMMUCFGR_PRI	0x00000200
-#define SPR_DMMUCFGR_TEIRI	0x00000400
-#define SPR_DMMUCFGR_HTR	0x00000800
-
-#define SPR_DMMUCFGR_NTW_OFF	0
-#define SPR_DMMUCFGR_NTS_OFF	2
-
-/*
- * Bit definitions for Instruction MMU Configuration Register
- */
-#define SPR_IMMUCFGR_NTW	0x00000003
-#define SPR_IMMUCFGR_NTS	0x0000001C
-#define SPR_IMMUCFGR_NAE	0x000000E0
-#define SPR_IMMUCFGR_CRI	0x00000100
-#define SPR_IMMUCFGR_PRI	0x00000200
-#define SPR_IMMUCFGR_TEIRI	0x00000400
-#define SPR_IMMUCFGR_HTR	0x00000800
-
-#define SPR_IMMUCFGR_NTW_OFF	0
-#define SPR_IMMUCFGR_NTS_OFF	2
-
-/*
- * Bit definitions for Debug Control registers
- */
-#define SPR_DCR_DP	0x00000001 /* DVR/DCR present */
-#define SPR_DCR_CC	0x0000000e /* Compare condition */
-#define SPR_DCR_SC	0x00000010 /* Signed compare */
-#define SPR_DCR_CT	0x000000e0 /* Compare to */
-
-/* Bit results with SPR_DCR_CC mask */
-#define SPR_DCR_CC_MASKED	0x00000000
-#define SPR_DCR_CC_EQUAL	0x00000002
-#define SPR_DCR_CC_LESS		0x00000004
-#define SPR_DCR_CC_LESSE	0x00000006
-#define SPR_DCR_CC_GREAT	0x00000008
-#define SPR_DCR_CC_GREATE	0x0000000a
-#define SPR_DCR_CC_NEQUAL	0x0000000c
-
-/* Bit results with SPR_DCR_CT mask */
-#define SPR_DCR_CT_DISABLED	0x00000000
-#define SPR_DCR_CT_IFEA		0x00000020
-#define SPR_DCR_CT_LEA		0x00000040
-#define SPR_DCR_CT_SEA		0x00000060
-#define SPR_DCR_CT_LD		0x00000080
-#define SPR_DCR_CT_SD		0x000000a0
-#define SPR_DCR_CT_LSEA		0x000000c0
-#define SPR_DCR_CT_LSD		0x000000e0
-
-/*
- * Bit definitions for Debug Mode 1 register
- */
-#define SPR_DMR1_CW		0x000fffff /* Chain register pair data */
-#define SPR_DMR1_CW0_AND	0x00000001
-#define SPR_DMR1_CW0_OR		0x00000002
-#define SPR_DMR1_CW0		(SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
-#define SPR_DMR1_CW1_AND	0x00000004
-#define SPR_DMR1_CW1_OR		0x00000008
-#define SPR_DMR1_CW1		(SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
-#define SPR_DMR1_CW2_AND	0x00000010
-#define SPR_DMR1_CW2_OR		0x00000020
-#define SPR_DMR1_CW2		(SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
-#define SPR_DMR1_CW3_AND	0x00000040
-#define SPR_DMR1_CW3_OR		0x00000080
-#define SPR_DMR1_CW3		(SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
-#define SPR_DMR1_CW4_AND	0x00000100
-#define SPR_DMR1_CW4_OR		0x00000200
-#define SPR_DMR1_CW4		(SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
-#define SPR_DMR1_CW5_AND	0x00000400
-#define SPR_DMR1_CW5_OR		0x00000800
-#define SPR_DMR1_CW5		(SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
-#define SPR_DMR1_CW6_AND	0x00001000
-#define SPR_DMR1_CW6_OR		0x00002000
-#define SPR_DMR1_CW6		(SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
-#define SPR_DMR1_CW7_AND	0x00004000
-#define SPR_DMR1_CW7_OR		0x00008000
-#define SPR_DMR1_CW7		(SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
-#define SPR_DMR1_CW8_AND	0x00010000
-#define SPR_DMR1_CW8_OR		0x00020000
-#define SPR_DMR1_CW8		(SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
-#define SPR_DMR1_CW9_AND	0x00040000
-#define SPR_DMR1_CW9_OR		0x00080000
-#define SPR_DMR1_CW9		(SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
-#define SPR_DMR1_RES1		0x00300000 /* Reserved */
-#define SPR_DMR1_ST		0x00400000 /* Single-step trace*/
-#define SPR_DMR1_BT		0x00800000 /* Branch trace */
-#define SPR_DMR1_RES2		0xff000000 /* Reserved */
-
-/*
- * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
- */
-#define SPR_DMR2_WCE0		0x00000001 /* Watchpoint counter 0 enable */
-#define SPR_DMR2_WCE1		0x00000002 /* Watchpoint counter 0 enable */
-#define SPR_DMR2_AWTC		0x00000ffc /* Assign watchpoints to counters */
-#define SPR_DMR2_AWTC_OFF	2 /* Bit offset to AWTC field */
-#define SPR_DMR2_WGB		0x003ff000 /* Watch generating breakpoint */
-#define SPR_DMR2_WGB_OFF	12 /* Bit offset to WGB field */
-#define SPR_DMR2_WBS		0xffc00000 /* Watchpoint status */
-#define SPR_DMR2_WBS_OFF	22 /* Bit offset to WBS field */
-
-/*
- * Bit definitions for Debug watchpoint counter registers
- */
-#define SPR_DWCR_COUNT		0x0000ffff /* Count */
-#define SPR_DWCR_MATCH		0xffff0000 /* Match */
-#define SPR_DWCR_MATCH_OFF	16 /* Match bit offset */
-
-/*
- * Bit definitions for Debug stop register
- *
- */
-#define SPR_DSR_RSTE	0x00000001 /* Reset exception */
-#define SPR_DSR_BUSEE	0x00000002 /* Bus error exception */
-#define SPR_DSR_DPFE	0x00000004 /* Data Page Fault exception */
-#define SPR_DSR_IPFE	0x00000008 /* Insn Page Fault exception */
-#define SPR_DSR_TTE	0x00000010 /* Tick Timer exception */
-#define SPR_DSR_AE	0x00000020 /* Alignment exception */
-#define SPR_DSR_IIE	0x00000040 /* Illegal Instruction exception */
-#define SPR_DSR_IE	0x00000080 /* Interrupt exception */
-#define SPR_DSR_DME	0x00000100 /* DTLB miss exception */
-#define SPR_DSR_IME	0x00000200 /* ITLB miss exception */
-#define SPR_DSR_RE	0x00000400 /* Range exception */
-#define SPR_DSR_SCE	0x00000800 /* System call exception */
-#define SPR_DSR_FPE	0x00001000 /* Floating Point Exception */
-#define SPR_DSR_TE	0x00002000 /* Trap exception */
-
-/*
- * Bit definitions for Debug reason register
- */
-#define SPR_DRR_RSTE	0x00000001 /* Reset exception */
-#define SPR_DRR_BUSEE	0x00000002 /* Bus error exception */
-#define SPR_DRR_DPFE	0x00000004 /* Data Page Fault exception */
-#define SPR_DRR_IPFE	0x00000008 /* Insn Page Fault exception */
-#define SPR_DRR_TTE	0x00000010 /* Tick Timer exception */
-#define SPR_DRR_AE	0x00000020 /* Alignment exception */
-#define SPR_DRR_IIE	0x00000040 /* Illegal Instruction exception */
-#define SPR_DRR_IE	0x00000080 /* Interrupt exception */
-#define SPR_DRR_DME	0x00000100 /* DTLB miss exception */
-#define SPR_DRR_IME	0x00000200 /* ITLB miss exception */
-#define SPR_DRR_RE	0x00000400 /* Range exception */
-#define SPR_DRR_SCE	0x00000800 /* System call exception */
-#define SPR_DRR_FPE	0x00001000 /* Floating Point Exception */
-#define SPR_DRR_TE	0x00002000 /* Trap exception */
-
-/*
- * Bit definitions for Performance counters mode registers
- */
-#define SPR_PCMR_CP	0x00000001 /* Counter present */
-#define SPR_PCMR_UMRA	0x00000002 /* User mode read access */
-#define SPR_PCMR_CISM	0x00000004 /* Count in supervisor mode */
-#define SPR_PCMR_CIUM	0x00000008 /* Count in user mode */
-#define SPR_PCMR_LA	0x00000010 /* Load access event */
-#define SPR_PCMR_SA	0x00000020 /* Store access event */
-#define SPR_PCMR_IF	0x00000040 /* Instruction fetch event*/
-#define SPR_PCMR_DCM	0x00000080 /* Data cache miss event */
-#define SPR_PCMR_ICM	0x00000100 /* Insn cache miss event */
-#define SPR_PCMR_IFS	0x00000200 /* Insn fetch stall event */
-#define SPR_PCMR_LSUS	0x00000400 /* LSU stall event */
-#define SPR_PCMR_BS	0x00000800 /* Branch stall event */
-#define SPR_PCMR_DTLBM	0x00001000 /* DTLB miss event */
-#define SPR_PCMR_ITLBM	0x00002000 /* ITLB miss event */
-#define SPR_PCMR_DDS	0x00004000 /* Data dependency stall event */
-#define SPR_PCMR_WPE	0x03ff8000 /* Watchpoint events */
-
-/*
- * Bit definitions for the Power management register
- */
-#define SPR_PMR_SDF	0x0000000f /* Slow down factor */
-#define SPR_PMR_DME	0x00000010 /* Doze mode enable */
-#define SPR_PMR_SME	0x00000020 /* Sleep mode enable */
-#define SPR_PMR_DCGE	0x00000040 /* Dynamic clock gating enable */
-#define SPR_PMR_SUME	0x00000080 /* Suspend mode enable */
-
-/*
- * Bit definitions for PICMR
- */
-#define SPR_PICMR_IUM	0xfffffffc /* Interrupt unmask */
-
-/*
- * Bit definitions for PICPR
- */
-#define SPR_PICPR_IPRIO	0xfffffffc /* Interrupt priority */
-
-/*
- * Bit definitions for PICSR
- */
-#define SPR_PICSR_IS	0xffffffff /* Interrupt status */
-
-/*
- * Bit definitions for Tick Timer Control Register
- */
-#define SPR_TTCR_CNT	0xffffffff /* Count, time period */
-#define SPR_TTMR_TP	0x0fffffff /* Time period */
-#define SPR_TTMR_IP	0x10000000 /* Interrupt Pending */
-#define SPR_TTMR_IE	0x20000000 /* Interrupt Enable */
-#define SPR_TTMR_DI	0x00000000 /* Disabled */
-#define SPR_TTMR_RT	0x40000000 /* Restart tick */
-#define SPR_TTMR_SR	0x80000000 /* Single run */
-#define SPR_TTMR_CR	0xc0000000 /* Continuous run */
-#define SPR_TTMR_M	0xc0000000 /* Tick mode */
-
-/*
- * Bit definitions for the FP Control Status Register
- */
-#define SPR_FPCSR_FPEE	0x00000001 /* Floating Point Exception Enable */
-#define SPR_FPCSR_RM	0x00000006 /* Rounding Mode */
-#define SPR_FPCSR_OVF	0x00000008 /* Overflow Flag */
-#define SPR_FPCSR_UNF	0x00000010 /* Underflow Flag */
-#define SPR_FPCSR_SNF	0x00000020 /* SNAN Flag */
-#define SPR_FPCSR_QNF	0x00000040 /* QNAN Flag */
-#define SPR_FPCSR_ZF	0x00000080 /* Zero Flag */
-#define SPR_FPCSR_IXF	0x00000100 /* Inexact Flag */
-#define SPR_FPCSR_IVF	0x00000200 /* Invalid Flag */
-#define SPR_FPCSR_INF	0x00000400 /* Infinity Flag */
-#define SPR_FPCSR_DZF	0x00000800 /* Divide By Zero Flag */
-#define SPR_FPCSR_ALLF	(SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
-			SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \
-			SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
-
-#define FPCSR_RM_RN	(0<<1)
-#define FPCSR_RM_RZ	(1<<1)
-#define FPCSR_RM_RIP	(2<<1)
-#define FPCSR_RM_RIN	(3<<1)
-
-/*
- * l.nop constants
- */
-#define NOP_NOP			0x0000 /* Normal nop instruction */
-#define NOP_EXIT		0x0001 /* End of simulation */
-#define NOP_REPORT		0x0002 /* Simple report */
-#define NOP_PUTC		0x0004 /* Simputc instruction */
-#define NOP_CNT_RESET		0x0005 /* Reset statistics counters */
-#define NOP_GET_TICKS		0x0006 /* Get # ticks running */
-#define NOP_GET_PS		0x0007 /* Get picosecs/cycle */
-#define NOP_REPORT_FIRST	0x0400 /* Report with number */
-#define NOP_REPORT_LAST		0x03ff /* Report with number */
-
-#endif /* SPR_DEFS__H */
diff --git a/arch/openrisc/include/asm/string.h b/arch/openrisc/include/asm/string.h
deleted file mode 100644
index 73e2655..0000000
--- a/arch/openrisc/include/asm/string.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASM_OPENRISC_STRING_H
-#define __ASM_OPENRISC_STRING_H
-
-#endif
diff --git a/arch/openrisc/include/asm/system.h b/arch/openrisc/include/asm/system.h
deleted file mode 100644
index 7adfd88..0000000
--- a/arch/openrisc/include/asm/system.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_SYSTEM_H
-#define __ASM_OPENRISC_SYSTEM_H
-
-#include <asm/spr-defs.h>
-
-static inline unsigned long mfspr(unsigned long add)
-{
-	unsigned long ret;
-
-	__asm__ __volatile__ ("l.mfspr %0,r0,%1" : "=r" (ret) : "K" (add));
-
-	return ret;
-}
-
-static inline void mtspr(unsigned long add, unsigned long val)
-{
-	__asm__ __volatile__ ("l.mtspr r0,%1,%0" : : "K" (add), "r" (val));
-}
-
-#endif /* __ASM_OPENRISC_SYSTEM_H */
diff --git a/arch/openrisc/include/asm/types.h b/arch/openrisc/include/asm/types.h
deleted file mode 100644
index 1fe00bf..0000000
--- a/arch/openrisc/include/asm/types.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_TYPES_H
-#define _ASM_TYPES_H
-
-/*
- * This file is never included by application software unless
- * explicitly requested (e.g., via linux/types.h) in which case the
- * application is Linux specific so (user-) name space pollution is
- * not a major issue.  However, for interoperability, libraries still
- * need to be careful to avoid a name clashes.
- */
-
-typedef unsigned short umode_t;
-
-/*
- * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
- * header files exported to user space
- */
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-#if defined(__GNUC__)
-__extension__ typedef __signed__ long long __s64;
-__extension__ typedef unsigned long long __u64;
-#endif
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long long s64;
-typedef unsigned long long u64;
-
-#define BITS_PER_LONG 32
-
-/* Dma addresses are 32-bits wide.  */
-
-typedef u32 dma_addr_t;
-
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_TYPES_H */
diff --git a/arch/openrisc/include/asm/u-boot.h b/arch/openrisc/include/asm/u-boot.h
deleted file mode 100644
index cdb8ff9..0000000
--- a/arch/openrisc/include/asm/u-boot.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- ********************************************************************
- * NOTE: This header file defines an interface to U-Boot. Including
- * this (unmodified) header file in another file is considered normal
- * use of U-Boot, and does *not* fall under the heading of "derived
- * work".
- ********************************************************************
- */
-
-#ifndef _U_BOOT_H_
-#define _U_BOOT_H_
-
-typedef struct bd_info {
-	unsigned long	bi_arch_number;	/* unique id for this board */
-	unsigned long	bi_boot_params;	/* where this board expects params */
-	unsigned long	bi_memstart;	/* start of DRAM memory */
-	phys_size_t	bi_memsize;	/* size of DRAM memory in bytes */
-	unsigned long	bi_flashstart;	/* start of FLASH memory */
-	unsigned long	bi_flashsize;	/* size  of FLASH memory */
-	unsigned long	bi_flashoffset;	/* reserved area for startup monitor */
-} bd_t;
-
-#define IH_ARCH_DEFAULT IH_ARCH_OPENRISC
-
-#endif	/* _U_BOOT_H_ */
diff --git a/arch/openrisc/include/asm/unaligned.h b/arch/openrisc/include/asm/unaligned.h
deleted file mode 100644
index 6cecbbb..0000000
--- a/arch/openrisc/include/asm/unaligned.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/unaligned.h>
diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile
deleted file mode 100644
index 3a2f6ec..0000000
--- a/arch/openrisc/lib/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
-obj-y	+= timer.o
diff --git a/arch/openrisc/lib/bootm.c b/arch/openrisc/lib/bootm.c
deleted file mode 100644
index a18748f..0000000
--- a/arch/openrisc/lib/bootm.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2011 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * Based on microblaze implementation by:
- * (C) Copyright 2007 Michal Simek
- * (C) Copyright 2004 Atmark Techno, Inc.
- *
- * Michal  SIMEK <monstr@monstr.eu>
- * Yasushi SHOJI <yashi@atmark-techno.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <image.h>
-#include <u-boot/zlib.h>
-#include <asm/byteorder.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int do_bootm_linux(int flag, int argc, char * const argv[],
-			bootm_headers_t *images)
-{
-	void	(*kernel) (unsigned int);
-	ulong	rd_data_start, rd_data_end;
-
-	/*
-	 * allow the PREP bootm subcommand, it is required for bootm to work
-	 */
-	if (flag & BOOTM_STATE_OS_PREP)
-		return 0;
-
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
-
-	int	ret;
-
-	char	*of_flat_tree = NULL;
-#if defined(CONFIG_OF_LIBFDT)
-	/* did generic code already find a device tree? */
-	if (images->ft_len)
-		of_flat_tree = images->ft_addr;
-#endif
-
-	kernel = (void (*)(unsigned int))images->ep;
-
-	/* find ramdisk */
-	ret = boot_get_ramdisk(argc, argv, images, IH_ARCH_OPENRISC,
-			&rd_data_start, &rd_data_end);
-	if (ret)
-		return 1;
-
-	show_boot_progress(15);
-
-	if (!of_flat_tree && argc > 1)
-		of_flat_tree = (char *)simple_strtoul(argv[1], NULL, 16);
-#ifdef DEBUG
-	printf("## Transferring control to Linux (at address 0x%08lx) " \
-				"ramdisk 0x%08lx, FDT 0x%08lx...\n",
-		(ulong) kernel, rd_data_start, (ulong) of_flat_tree);
-#endif
-	if (dcache_status() || icache_status())
-		flush_cache((ulong)kernel, max(checkdcache(), checkicache()));
-
-	/*
-	 * Linux Kernel Parameters (passing device tree):
-	 * r3: pointer to the fdt, followed by the board info data
-	 */
-	kernel((unsigned int) of_flat_tree);
-	/* does not return */
-
-	return 1;
-}
diff --git a/arch/openrisc/lib/timer.c b/arch/openrisc/lib/timer.c
deleted file mode 100644
index db8ddbd..0000000
--- a/arch/openrisc/lib/timer.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/system.h>
-#include <asm/openrisc_exc.h>
-
-static ulong timestamp;
-
-/* how many counter cycles in a jiffy */
-#define TIMER_COUNTER_CYCLES  (CONFIG_SYS_CLK_FREQ/CONFIG_SYS_OPENRISC_TMR_HZ)
-/* how many ms elapses between each timer interrupt */
-#define TIMER_TIMESTAMP_INC   (1000/CONFIG_SYS_OPENRISC_TMR_HZ)
-/* how many cycles per ms */
-#define TIMER_CYCLES_MS       (CONFIG_SYS_CLK_FREQ/1000)
-/* how many cycles per us */
-#define TIMER_CYCLES_US       (CONFIG_SYS_CLK_FREQ/1000000uL)
-
-void timer_isr(void)
-{
-	timestamp += TIMER_TIMESTAMP_INC;
-	mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
-		(TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
-}
-
-int timer_init(void)
-{
-	/* Install timer exception handler */
-	exception_install_handler(EXC_TIMER, timer_isr);
-
-	/* Set up the timer for the first expiration. */
-	timestamp = 0;
-
-	mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
-		(TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
-
-	/* Enable tick timer exception in supervisor register */
-	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE);
-
-	return 0;
-}
-
-void reset_timer(void)
-{
-	timestamp = 0;
-
-	mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
-		(TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
-}
-
-/*
- * The timer value in ms is calculated by taking the
- * value accumulated by full timer revolutions plus the value
- * accumulated in this period
- */
-ulong get_timer(ulong base)
-{
-	return timestamp + mfspr(SPR_TTCR)/TIMER_CYCLES_MS - base;
-}
-
-void set_timer(ulong t)
-{
-	reset_timer();
-	timestamp = t;
-}
-
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
-
-void __udelay(ulong usec)
-{
-	ulong elapsed = 0;
-	ulong tick;
-	ulong last_tick;
-
-	last_tick = mfspr(SPR_TTCR);
-	while ((elapsed / TIMER_CYCLES_US) < usec) {
-		tick = mfspr(SPR_TTCR);
-		if (tick >= last_tick)
-			elapsed += (tick - last_tick);
-		else
-			elapsed += TIMER_COUNTER_CYCLES - (last_tick - tick);
-		last_tick = tick;
-	}
-}
diff --git a/arch/powerpc/cpu/mpc5xx/cpu_init.c b/arch/powerpc/cpu/mpc5xx/cpu_init.c
index 0f62c13..5bae39f 100644
--- a/arch/powerpc/cpu/mpc5xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc5xx/cpu_init.c
@@ -43,7 +43,7 @@ void cpu_init_f (volatile immap_t * immr)
 	immr->im_uimb.uimb_umcr = CONFIG_SYS_UMCR;
 
 	/* Time base and decrementer will be enables (TBE) */
-	/* in init_timebase() in time.c called from board_init_f(). */
+	/* in timer_init() in time.c called from board_init_f(). */
 
 	/* Initialize the PIT. Unlock PISCRK */
 	immr->im_sitk.sitk_piscrk = KAPWR_KEY;
diff --git a/arch/powerpc/cpu/mpc5xxx/spl_boot.c b/arch/powerpc/cpu/mpc5xxx/spl_boot.c
index e182dfb..2d7f6c4 100644
--- a/arch/powerpc/cpu/mpc5xxx/spl_boot.c
+++ b/arch/powerpc/cpu/mpc5xxx/spl_boot.c
@@ -32,7 +32,7 @@ void board_init_f(ulong bootflag)
 	/*
 	 * On MPC5200, the initial RAM (and gd) is located in the internal
 	 * SRAM. So we can actually call the preloader console init code
-	 * before calling initdram(). This makes serial output (printf)
+	 * before calling dram_init(). This makes serial output (printf)
 	 * available very early, even before SDRAM init, which has been
 	 * an U-Boot priciple from day 1.
 	 */
@@ -62,7 +62,7 @@ void board_init_f(ulong bootflag)
 	 * First we need to initialize the SDRAM, so that the real
 	 * U-Boot or the OS (Linux) can be loaded
 	 */
-	initdram(0);
+	dram_init();
 
 	/* Clear bss */
 	memset(__bss_start, '\0', __bss_end - __bss_start);
diff --git a/arch/powerpc/cpu/mpc8260/cpu.c b/arch/powerpc/cpu/mpc8260/cpu.c
index 9f2be3c..58d1c02 100644
--- a/arch/powerpc/cpu/mpc8260/cpu.c
+++ b/arch/powerpc/cpu/mpc8260/cpu.c
@@ -50,7 +50,14 @@ int checkcpu (void)
 	uint pvr = get_pvr ();
 	uint immr, rev, m, k;
 	char buf[32];
-
+	int ret;
+
+	ret = prt_8260_rsr();
+	if (ret)
+		return ret;
+	ret = prt_8260_clks();
+	if (ret)
+		return ret;
 	puts ("CPU:   ");
 
 	switch (pvr) {
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index c87f0fd..cb82621 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -33,6 +33,7 @@ int checkcpu(void)
 	u32 pvr = get_pvr();
 	u32 spridr;
 	char buf[32];
+	int ret;
 	int i;
 
 	const struct cpu_type {
@@ -61,6 +62,10 @@ int checkcpu(void)
 
 	immr = (immap_t *)CONFIG_SYS_IMMR;
 
+	ret = prt_83xx_rsr();
+	if (ret)
+		return ret;
+
 	puts("CPU:   ");
 
 	switch (pvr & 0xffff0000) {
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 3a0916b..2a9db0c 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -8,6 +8,7 @@
 #include <mpc83xx.h>
 #include <ioports.h>
 #include <asm/io.h>
+#include <asm/processor.h>
 #ifdef CONFIG_USB_EHCI_FSL
 #include <usb/ehci-ci.h>
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index cc30fa6..e3ef4ae 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -401,17 +401,19 @@ void mpc85xx_reginfo(void)
 #ifndef CONFIG_FSL_CORENET
 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
 	!defined(CONFIG_SYS_INIT_L2_ADDR)
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
 	defined(CONFIG_ARCH_QEMU_E500)
-	return fsl_ddr_sdram_size();
+	gd->ram_size = fsl_ddr_sdram_size();
 #else
-	return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 #endif
+
+	return 0;
 }
 #else /* CONFIG_SYS_RAMBOOT */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size = 0;
 
@@ -460,7 +462,9 @@ phys_size_t initdram(int board_type)
 #endif
 
 	debug("DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 #endif /* CONFIG_SYS_RAMBOOT */
 #endif
diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c
index 42442b8..e2295d2 100644
--- a/arch/powerpc/cpu/mpc8xx/speed.c
+++ b/arch/powerpc/cpu/mpc8xx/speed.c
@@ -237,18 +237,61 @@ int get_clocks (void)
 
 static long init_pll_866 (long clk);
 
+/* Adjust sdram refresh rate to actual CPU clock.
+ */
+static int sdram_adjust_866(void)
+{
+	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	long		  mamr;
+
+	mamr = immr->im_memctl.memc_mamr;
+	mamr &= ~MAMR_PTA_MSK;
+	mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+	immr->im_memctl.memc_mamr = mamr;
+
+	return 0;
+}
+
+/*
+ * Adjust sdram refresh rate to actual CPU clock
+ * and set timebase source according to actual CPU clock
+ */
+static int adjust_sdram_tbs_8xx(void)
+{
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) && \
+		!defined(CONFIG_TQM885D)
+	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	long		  mamr;
+	long              sccr;
+
+	mamr = immr->im_memctl.memc_mamr;
+	mamr &= ~MAMR_PTA_MSK;
+	mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+	immr->im_memctl.memc_mamr = mamr;
+
+	if (gd->cpu_clk < 67000000) {
+		sccr = immr->im_clkrst.car_sccr;
+		sccr |= SCCR_TBS;
+		immr->im_clkrst.car_sccr = sccr;
+	}
+#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
+
+	return 0;
+}
+
 /* This function sets up PLL (init_pll_866() is called) and
  * fills gd->cpu_clk and gd->bus_clk according to the environment
  * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk'
  * contains invalid value).
  * This functions requires an MPC866 or newer series CPU.
  */
-int get_clocks_866 (void)
+int get_clocks(void)
 {
 	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	char		  tmp[64];
 	long		  cpuclk = 0;
 	long		  sccr_reg;
+	int ret;
 
 	if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0)
 		cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
@@ -278,22 +321,11 @@ int get_clocks_866 (void)
 	}
 	immr->im_clkrst.car_sccr = sccr_reg;
 
-	return (0);
-}
-
-/* Adjust sdram refresh rate to actual CPU clock.
- */
-int sdram_adjust_866 (void)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	long		  mamr;
-
-	mamr = immr->im_memctl.memc_mamr;
-	mamr &= ~MAMR_PTA_MSK;
-	mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
-	immr->im_memctl.memc_mamr = mamr;
+	ret = sdram_adjust_866();
+	if (ret)
+		return ret;
 
-	return (0);
+	return adjust_sdram_tbs_8xx();
 }
 
 /* Configure PLL for MPC866/859/885 CPU series
@@ -369,32 +401,3 @@ static long init_pll_866 (long clk)
 }
 
 #endif /* CONFIG_8xx_CPUCLK_DEFAULT */
-
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
-    && !defined(CONFIG_TQM885D)
-/*
- * Adjust sdram refresh rate to actual CPU clock
- * and set timebase source according to actual CPU clock
- */
-int adjust_sdram_tbs_8xx (void)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	long		  mamr;
-	long              sccr;
-
-	mamr = immr->im_memctl.memc_mamr;
-	mamr &= ~MAMR_PTA_MSK;
-	mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
-	immr->im_memctl.memc_mamr = mamr;
-
-	if (gd->cpu_clk < 67000000) {
-		sccr = immr->im_clkrst.car_sccr;
-		sccr |= SCCR_TBS;
-		immr->im_clkrst.car_sccr = sccr;
-	}
-
-	return (0);
-}
-#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
-
-/* ------------------------------------------------------------------------- */
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index 7202c3f..ffc62a5 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -33,6 +33,8 @@
 
 #include "ecc.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)				\
 	do {								\
 		u32 data;						\
@@ -401,20 +403,20 @@ static unsigned char spd_read(uchar chip, uint addr)
 }
 
 /*-----------------------------------------------------------------------------+
- * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
+ * dram_init.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
  * Note: This routine runs from flash with a stack set up in the chip's
  * sram space.  It is important that the routine does not require .sbss, .bss or
  * .data sections.  It also cannot call routines that require these sections.
  *-----------------------------------------------------------------------------*/
 /*-----------------------------------------------------------------------------
- * Function:	 initdram
+ * Function:	 dram_init
  * Description:  Configures SDRAM memory banks for DDR operation.
  *		 Auto Memory Configuration option reads the DDR SDRAM EEPROMs
  *		 via the IIC bus and then configures the DDR SDRAM memory
  *		 banks appropriately. If Auto Memory Configuration is
  *		 not used, it is assumed that no DIMM is plugged
  *-----------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 	unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
@@ -429,7 +431,9 @@ phys_size_t initdram(int board_type)
 		 * Reduce RAM size to avoid overwriting memory used by
 		 * current stack? Not sure what is happening.
 		 */
-		return sdram_memsize() / 2;
+		gd->ram_size = sdram_memsize() / 2;
+
+		return 0;
 	}
 
 	num_dimm_banks = sizeof(iic0_dimm_addr);
@@ -650,7 +654,9 @@ phys_size_t initdram(int board_type)
 	 */
 	set_mcsr(get_mcsr());
 
-	return sdram_memsize();
+	gd->ram_size = sdram_memsize();
+
+	return 0;
 }
 
 static void get_spd_info(unsigned long *dimm_populated,
@@ -2849,13 +2855,13 @@ static void test(void)
 #else /* CONFIG_SPD_EEPROM */
 
 /*-----------------------------------------------------------------------------
- * Function:	initdram
+ * Function:	dram_init
  * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
  * 		The configuration is performed using static, compile-
  *		time parameters.
  * 		Configures the PPC405EX(r) and PPC460EX/GT
  *---------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	unsigned long val;
 
@@ -3011,7 +3017,9 @@ phys_size_t initdram(int board_type)
 	set_mcsr(get_mcsr());
 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
 
-	return (CONFIG_SYS_MBYTES_SDRAM << 20);
+	gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
+
+	return 0;
 }
 #endif /* CONFIG_SPD_EEPROM */
 
diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
index 455136c..c477853 100644
--- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
@@ -30,6 +30,8 @@
 #include <asm/mmu.h>
 #include <asm/cache.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_SPD_EEPROM) &&				\
 	(defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
 
@@ -985,20 +987,20 @@ static void program_ddr0_44(unsigned long dimm_ranks[],
 }
 
 /*-----------------------------------------------------------------------------+
- * initdram.  Initializes the 440EPx/GPx DDR SDRAM controller.
+ * dram_init.  Initializes the 440EPx/GPx DDR SDRAM controller.
  * Note: This routine runs from flash with a stack set up in the chip's
  * sram space.  It is important that the routine does not require .sbss, .bss or
  * .data sections.  It also cannot call routines that require these sections.
  *-----------------------------------------------------------------------------*/
 /*-----------------------------------------------------------------------------
- * Function:	 initdram
+ * Function:	 dram_init
  * Description:  Configures SDRAM memory banks for DDR operation.
  *		 Auto Memory Configuration option reads the DDR SDRAM EEPROMs
  *		 via the IIC bus and then configures the DDR SDRAM memory
  *		 banks appropriately. If Auto Memory Configuration is
  *		 not used, it is assumed that no DIMM is plugged
  *-----------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 	unsigned long dimm_ranks[MAXDIMMS];
@@ -1012,7 +1014,7 @@ phys_size_t initdram(int board_type)
 	unsigned long cas_latency = 0;	/* to quiet initialization warning */
 	unsigned long dram_size;
 
-	debug("\nEntering initdram()\n");
+	debug("\nEntering dram_init()\n");
 
 	/*------------------------------------------------------------------
 	 * Stop the DDR-SDRAM controller.
@@ -1212,7 +1214,9 @@ phys_size_t initdram(int board_type)
 #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
 
 	program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 void board_add_ram_info(int use_default)
diff --git a/arch/powerpc/cpu/ppc4xx/sdram.c b/arch/powerpc/cpu/ppc4xx/sdram.c
index cd63456..c416bce 100644
--- a/arch/powerpc/cpu/ppc4xx/sdram.c
+++ b/arch/powerpc/cpu/ppc4xx/sdram.c
@@ -17,6 +17,8 @@
 #include "sdram.h"
 #include "ecc.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_SDRAM_BANK0
 
 #ifndef CONFIG_440
@@ -148,7 +150,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
 /*
  * Autodetect onboard SDRAM on 405 platforms
  */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	ulong speed;
 	ulong sdtr1;
@@ -226,11 +228,13 @@ phys_size_t initdram(int board_type)
 			/*
 			 * OK, size detected -> all done
 			 */
-			return size;
+			gd->ram_size = size;
+
+			return 0;
 		}
 	}
 
-	return 0;
+	return -ENXIO;
 }
 
 #else /* CONFIG_440 */
@@ -349,7 +353,7 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
  *	 so this should be extended for other future boards
  *	 using this routine!
  */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	int i;
 	int tr1_bank1;
@@ -440,11 +444,13 @@ phys_size_t initdram(int board_type)
 			/*
 			 * OK, size detected -> all done
 			 */
-			return size;
+			gd->ram_size = size;
+
+			return 0;
 		}
 	}
 
-	return 0;				/* nothing found !		*/
+	return -ENXIO;			/* nothing found !		*/
 }
 
 #endif /* CONFIG_440 */
diff --git a/arch/powerpc/cpu/ppc4xx/spl_boot.c b/arch/powerpc/cpu/ppc4xx/spl_boot.c
index 318f23b..b30f169 100644
--- a/arch/powerpc/cpu/ppc4xx/spl_boot.c
+++ b/arch/powerpc/cpu/ppc4xx/spl_boot.c
@@ -26,7 +26,7 @@ void board_init_f(ulong bootflag)
 	 * First we need to initialize the SDRAM, so that the real
 	 * U-Boot or the OS (Linux) can be loaded
 	 */
-	initdram(0);
+	dram_init();
 
 	/* Clear bss */
 	memset(__bss_start, '\0', __bss_end - __bss_start);
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 81bae6f..fd38da9 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1354,6 +1354,10 @@ void ll_puts(const char *);
 /* In misc.c */
 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 
+int prt_83xx_rsr(void);
+int prt_8260_rsr(void);
+int prt_8260_clks(void);
+
 #endif /* ndef ASSEMBLY*/
 
 #ifdef CONFIG_MACH_SPECIFIC
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 3c97476..4f68613 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -17,6 +17,7 @@ MINIMAL=y
 endif
 endif
 
+obj-$(CONFIG_SYS_EXTBDINFO) += setup.o
 ifdef MINIMAL
 obj-y += cache.o time.o
 obj-y += ticks.o
diff --git a/arch/powerpc/lib/setup.c b/arch/powerpc/lib/setup.c
new file mode 100644
index 0000000..a421335
--- /dev/null
+++ b/arch/powerpc/lib/setup.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <version.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int setup_board_extra(void)
+{
+	bd_t *bd = gd->bd;
+
+	strncpy((char *)bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
+	strncpy((char *)bd->bi_r_version, U_BOOT_VERSION,
+		sizeof(bd->bi_r_version));
+
+	bd->bi_procfreq = gd->cpu_clk;	/* Processor Speed, In Hz */
+	bd->bi_plb_busfreq = gd->bus_clk;
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+		defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+		defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	bd->bi_pci_busfreq = get_PCI_freq();
+	bd->bi_opbfreq = get_OPB_freq();
+#elif defined(CONFIG_XILINX_405)
+	bd->bi_pci_busfreq = get_PCI_freq();
+#endif
+
+	return 0;
+}
diff --git a/arch/powerpc/lib/time.c b/arch/powerpc/lib/time.c
index 62b6c72..de5f0be 100644
--- a/arch/powerpc/lib/time.c
+++ b/arch/powerpc/lib/time.c
@@ -60,7 +60,7 @@ unsigned long ticks2usec(unsigned long ticks)
 #endif
 /* ------------------------------------------------------------------------- */
 
-int init_timebase (void)
+int timer_init(void)
 {
 	unsigned long temp;
 
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 6e4ec01..f605d4d 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -66,6 +66,11 @@ int sandbox_early_getopt_check(void)
 	os_exit(0);
 }
 
+int misc_init_f(void)
+{
+	return sandbox_early_getopt_check();
+}
+
 static int sandbox_cmdline_cb_help(struct sandbox_state *state, const char *arg)
 {
 	/* just flag to sandbox_early_getopt_check to show usage */
@@ -275,6 +280,12 @@ int board_run_command(const char *cmdline)
 	return 1;
 }
 
+static void setup_ram_buf(struct sandbox_state *state)
+{
+	gd->arch.ram_buf = state->ram_buf;
+	gd->ram_size = state->ram_size;
+}
+
 int main(int argc, char *argv[])
 {
 	struct sandbox_state *state;
@@ -302,6 +313,7 @@ int main(int argc, char *argv[])
 #ifdef CONFIG_SYS_MALLOC_F_LEN
 	gd->malloc_base = CONFIG_MALLOC_F_ADDR;
 #endif
+	setup_ram_buf(state);
 
 	/* Do pre- and post-relocation init */
 	board_init_f(0);
diff --git a/arch/sandbox/include/asm/types.h b/arch/sandbox/include/asm/types.h
index 42c09e2..623cdaf 100644
--- a/arch/sandbox/include/asm/types.h
+++ b/arch/sandbox/include/asm/types.h
@@ -50,7 +50,11 @@ typedef __INT64_TYPE__ s64;
 typedef __UINT64_TYPE__ u64;
 #endif
 
-#define BITS_PER_LONG	CONFIG_SANDBOX_BITS_PER_LONG
+/*
+ * Number of bits in a C 'long' on this architecture. Set this to 32 when
+ * building on a 32-bit machine.
+ */
+#define BITS_PER_LONG	32
 
 typedef unsigned long dma_addr_t;
 typedef u32 phys_addr_t;
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
deleted file mode 100644
index 1d1347b..0000000
--- a/arch/sparc/Kconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-menu "SPARC architecture"
-	depends on SPARC
-
-config LEON
-	bool
-
-config LEON2
-	bool
-	select LEON
-
-config LEON3
-	bool
-	select LEON
-
-config SYS_SPARC_NWINDOWS
-	int "Number of SPARC register windows"
-	range 2 32
-	default "8"
-	help
-	  Specify the number of SPARC register windows implemented by this
-	  processor. A SPARC implementation can have from 2 to 32 windows.
-	  If unsure, choose 8.
-
-choice
-	prompt "Board select"
-	optional
-
-config TARGET_GRSIM_LEON2
-	bool "GRSIM simulating a LEON2 board"
-	select LEON2
-
-config TARGET_GR_CPCI_AX2000
-	bool "Gaisler GR-CPCI-AX2000 board"
-	select LEON3
-
-config TARGET_GR_EP2S60
-	bool "Gaisler Template design for Altera NIOS board with Stratix EP2S60"
-	select LEON3
-	help
-	  Gaisler Research AB's Template design (GPL Open Source SPARC/LEON3
-	  96MHz) for Altera NIOS Development board Stratix II edition,
-	  with the FPGA device EP2S60.
-
-config TARGET_GR_XC3S_1500
-	bool "Gaisler GR-XC3S-1500 spartan board"
-	select LEON3
-
-config TARGET_GRSIM
-	bool "GRSIM simulating a LEON3 GR-XC3S-1500 board"
-	select LEON3
-
-endchoice
-
-config SYS_ARCH
-	default "sparc"
-
-config SYS_CPU
-	default "leon2" if LEON2
-	default "leon3" if LEON3
-
-config SYS_VENDOR
-	default "gaisler"
-
-source "board/gaisler/gr_cpci_ax2000/Kconfig"
-source "board/gaisler/gr_ep2s60/Kconfig"
-source "board/gaisler/gr_xc3s_1500/Kconfig"
-source "board/gaisler/grsim/Kconfig"
-source "board/gaisler/grsim_leon2/Kconfig"
-
-endmenu
diff --git a/arch/sparc/Makefile b/arch/sparc/Makefile
deleted file mode 100644
index 2d4c971..0000000
--- a/arch/sparc/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-head-y := arch/sparc/cpu/$(CPU)/start.o
-
-libs-y += arch/sparc/cpu/$(CPU)/
-libs-y += arch/sparc/lib/
diff --git a/arch/sparc/config.mk b/arch/sparc/config.mk
deleted file mode 100644
index 43faad4..0000000
--- a/arch/sparc/config.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# (C) Copyright 2015
-# Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := sparc-linux-
-endif
-
-# This GCC compiler is known to work:
-#  https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
-
-gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) \
-			       -T $(srctree)/examples/standalone/sparc.lds
-
-cpuflags-$(CONFIG_LEON2) := -mcpu=leon
-cpuflags-$(CONFIG_LEON3) := -mcpu=leon3
-
-PLATFORM_CPPFLAGS += $(cpuflags-y)
-
-PLATFORM_RELFLAGS += -fPIC
diff --git a/arch/sparc/cpu/leon2/Makefile b/arch/sparc/cpu/leon2/Makefile
deleted file mode 100644
index 8c95ca5..0000000
--- a/arch/sparc/cpu/leon2/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-extra-y	= start.o
-obj-y	= cpu_init.o serial.o cpu.o interrupts.o prom.o
diff --git a/arch/sparc/cpu/leon2/cpu.c b/arch/sparc/cpu/leon2/cpu.c
deleted file mode 100644
index d044c3a..0000000
--- a/arch/sparc/cpu/leon2/cpu.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* CPU specific code for the LEON2 CPU
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void _reset_reloc(void);
-
-int checkcpu(void)
-{
-	/* check LEON version here */
-	printf("CPU: LEON2\n");
-	return 0;
-}
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-
-int print_cpuinfo(void)
-{
-	printf("CPU:   LEON2\n");
-	return 0;
-}
-
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-void cpu_reset(void)
-{
-	/* Interrupts off */
-	disable_interrupts();
-
-	/* jump to restart in flash */
-	_reset_reloc();
-}
-
-int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	cpu_reset();
-
-	return 1;
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_GRETH
-int cpu_eth_init(bd_t *bis)
-{
-	return greth_initialize(bis);
-}
-#endif
diff --git a/arch/sparc/cpu/leon2/cpu_init.c b/arch/sparc/cpu/leon2/cpu_init.c
deleted file mode 100644
index 9dfb99c..0000000
--- a/arch/sparc/cpu/leon2/cpu_init.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* Initializes CPU and basic hardware such as memory
- * controllers, IRQ controller and system timer 0.
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/asi.h>
-#include <asm/leon.h>
-#include <asm/io.h>
-
-#include <config.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers.
- *
- * Run from FLASH/PROM:
- *  - until memory controller is set up, only registers available
- *  - no global variables available for writing
- *  - constants available
- */
-
-void cpu_init_f(void)
-{
-	LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
-
-	/* initialize the IRQMP */
-	leon2->Interrupt_Force = 0;
-	leon2->Interrupt_Pending = 0;
-	leon2->Interrupt_Clear = 0xfffe;	/* clear all old pending interrupts */
-	leon2->Interrupt_Mask = 0xfffe0000;	/* mask all IRQs */
-
-	/* cache */
-
-	/* I/O port setup */
-#ifdef LEON2_IO_PORT_DIR
-	leon2->PIO_Direction = LEON2_IO_PORT_DIR;
-#endif
-#ifdef LEON2_IO_PORT_DATA
-	leon2->PIO_Data = LEON2_IO_PORT_DATA;
-#endif
-#ifdef LEON2_IO_PORT_INT
-	leon2->PIO_Interrupt = LEON2_IO_PORT_INT;
-#else
-	leon2->PIO_Interrupt = 0;
-#endif
-
-	/* disable timers */
-	leon2->Timer_Control_1 = leon2->Timer_Control_2 = 0;
-}
-
-int arch_cpu_init(void)
-{
-	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
-	gd->bus_clk = CONFIG_SYS_CLK_FREQ;
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
-	return 0;
-}
-
-/*
- * initialize higher level parts of CPU
- */
-int cpu_init_r(void)
-{
-	return 0;
-}
-
-/* initiate and setup timer0 to configured HZ. Base clock is 1MHz.
- */
-int timer_init(void)
-{
-	LEON2_regs *leon2 = (LEON2_regs *)LEON2_PREGS;
-
-	/* initialize prescaler common to all timers to 1MHz */
-	leon2->Scaler_Counter = leon2->Scaler_Reload =
-		(((CONFIG_SYS_CLK_FREQ / 1000) + 500) / 1000) - 1;
-
-	/* SYS_HZ ticks per second */
-	leon2->Timer_Counter_1 = 0;
-	leon2->Timer_Reload_1 = (CONFIG_SYS_TIMER_RATE / CONFIG_SYS_HZ) - 1;
-	leon2->Timer_Control_1 = LEON2_TIMER_CTRL_EN | LEON2_TIMER_CTRL_RS |
-		LEON2_TIMER_CTRL_LD;
-
-	CONFIG_SYS_TIMER_COUNTER = (void *)&leon2->Timer_Counter_1;
-	return 0;
-}
diff --git a/arch/sparc/cpu/leon2/interrupts.c b/arch/sparc/cpu/leon2/interrupts.c
deleted file mode 100644
index 602e4a6..0000000
--- a/arch/sparc/cpu/leon2/interrupts.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
- *
- * (C) Copyright 2006
- * Detlev Zundel, DENX Software Engineering, dzu@denx.de
- *
- * (C) Copyright -2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/stack.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <asm/irq.h>
-
-#include <asm/leon.h>
-
-/* 15 normal irqs and a non maskable interrupt */
-#define NR_IRQS 15
-
-struct irq_action {
-	interrupt_handler_t *handler;
-	void *arg;
-	unsigned int count;
-};
-
-static struct irq_action irq_handlers[NR_IRQS] = { {0}, };
-static int spurious_irq_cnt = 0;
-static int spurious_irq = 0;
-
-static inline unsigned int leon2_get_irqmask(unsigned int irq)
-{
-	if ((irq < 0) || (irq >= NR_IRQS)) {
-		return 0;
-	} else {
-		return (1 << irq);
-	}
-}
-
-static void leon2_ic_disable(unsigned int irq)
-{
-	unsigned int mask, pil;
-	LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
-
-	pil = intLock();
-
-	/* get mask of interrupt */
-	mask = leon2_get_irqmask(irq);
-
-	/* set int level */
-	leon2->Interrupt_Mask =
-	    SPARC_NOCACHE_READ(&leon2->Interrupt_Mask) & (~mask);
-
-	intUnlock(pil);
-}
-
-static void leon2_ic_enable(unsigned int irq)
-{
-	unsigned int mask, pil;
-	LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
-
-	pil = intLock();
-
-	/* get mask of interrupt */
-	mask = leon2_get_irqmask(irq);
-
-	/* set int level */
-	leon2->Interrupt_Mask =
-	    SPARC_NOCACHE_READ(&leon2->Interrupt_Mask) | mask;
-
-	intUnlock(pil);
-}
-
-void handler_irq(int irq, struct pt_regs *regs)
-{
-	if (irq_handlers[irq].handler) {
-		if (((unsigned int)irq_handlers[irq].handler > CONFIG_SYS_RAM_END) ||
-		    ((unsigned int)irq_handlers[irq].handler < CONFIG_SYS_RAM_BASE)
-		    ) {
-			printf("handler_irq: bad handler: %x, irq number %d\n",
-			       (unsigned int)irq_handlers[irq].handler, irq);
-			return;
-		}
-		irq_handlers[irq].handler(irq_handlers[irq].arg);
-		irq_handlers[irq].count++;
-	} else {
-		spurious_irq_cnt++;
-		spurious_irq = irq;
-	}
-}
-
-void leon2_force_int(int irq)
-{
-	LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
-
-	if ((irq >= NR_IRQS) || (irq < 0))
-		return;
-	printf("Forcing interrupt %d\n", irq);
-
-	leon2->Interrupt_Force =
-	    SPARC_NOCACHE_READ(&leon2->Interrupt_Force) | (1 << irq);
-}
-
-/****************************************************************************/
-
-int interrupt_init_cpu(void)
-{
-	return (0);
-}
-
-/****************************************************************************/
-
-/*
- * Install and free a interrupt handler.
- */
-
-void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
-{
-	if (irq < 0 || irq >= NR_IRQS) {
-		printf("irq_install_handler: bad irq number %d\n", irq);
-		return;
-	}
-
-	if (irq_handlers[irq].handler != NULL)
-		printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
-		       (ulong) handler, (ulong) irq_handlers[irq].handler);
-
-	if (((unsigned int)handler > CONFIG_SYS_RAM_END) ||
-	    ((unsigned int)handler < CONFIG_SYS_RAM_BASE)
-	    ) {
-		printf("irq_install_handler: bad handler: %x, irq number %d\n",
-		       (unsigned int)handler, irq);
-		return;
-	}
-	irq_handlers[irq].handler = handler;
-	irq_handlers[irq].arg = arg;
-
-	/* enable irq on LEON2 hardware */
-	leon2_ic_enable(irq);
-
-}
-
-void irq_free_handler(int irq)
-{
-	if (irq < 0 || irq >= NR_IRQS) {
-		printf("irq_free_handler: bad irq number %d\n", irq);
-		return;
-	}
-
-	/* disable irq on LEON2 hardware */
-	leon2_ic_disable(irq);
-
-	irq_handlers[irq].handler = NULL;
-	irq_handlers[irq].arg = NULL;
-}
-
-/****************************************************************************/
-
-#if defined(CONFIG_CMD_IRQ)
-void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
-{
-	int irq;
-	unsigned int pil = get_pil();
-	printf("PIL level: %u\n\r", pil);
-	printf("Spurious IRQ: %u, last unknown IRQ: %d\n",
-	       spurious_irq_cnt, spurious_irq);
-
-	puts("\nInterrupt-Information:\n" "Nr  Routine   Arg       Count\n");
-
-	for (irq = 0; irq < NR_IRQS; irq++) {
-		if (irq_handlers[irq].handler != NULL) {
-			printf("%02d  %p  %p  %d\n", irq,
-			       irq_handlers[irq].handler,
-			       irq_handlers[irq].arg,
-			       irq_handlers[irq].count);
-		}
-	}
-}
-#endif
diff --git a/arch/sparc/cpu/leon2/prom.c b/arch/sparc/cpu/leon2/prom.c
deleted file mode 100644
index 7829e7a..0000000
--- a/arch/sparc/cpu/leon2/prom.c
+++ /dev/null
@@ -1,1032 +0,0 @@
-/* prom.c - emulates a sparc v0 PROM for the linux kernel.
- *
- * Copyright (C) 2003 Konrad Eisele <eiselekd@web.de>
- * Copyright (C) 2004 Stefan Holst <mail@s-holst.de>
- * Copyright (C) 2007 Daniel Hellstrom <daniel@gaisler.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/prom.h>
-#include <asm/machines.h>
-#include <asm/srmmu.h>
-#include <asm/processor.h>
-#include <asm/irq.h>
-#include <asm/leon.h>
-
-#include <config.h>
-/*
-#define PRINT_ROM_VEC
-*/
-extern struct linux_romvec *kernel_arg_promvec;
-
-#define PROM_PGT __attribute__ ((__section__ (".prom.pgt")))
-#define PROM_TEXT __attribute__ ((__section__ (".prom.text")))
-#define PROM_DATA __attribute__ ((__section__ (".prom.data")))
-
-void *__prom_start_reloc; /* relocated prom_start address */
-
-/* for __va */
-extern int __prom_start;
-#define PAGE_OFFSET 0xf0000000
-#define phys_base CONFIG_SYS_SDRAM_BASE
-#define PROM_OFFS 8192
-#define PROM_SIZE_MASK (PROM_OFFS-1)
-#define __va(x) ( \
-	(void *)( ((unsigned long)(x))-PROM_OFFS+ \
-	(CONFIG_SYS_PROM_OFFSET-phys_base)+PAGE_OFFSET-CONFIG_SYS_TEXT_BASE ) \
-	)
-#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CONFIG_SYS_PROM_OFFSET-CONFIG_SYS_TEXT_BASE))
-
-struct property {
-	char *name;
-	char *value;
-	int length;
-};
-
-struct node {
-	int level;
-	struct property *properties;
-};
-
-static void leon_reboot(char *bcommand);
-static void leon_halt(void);
-static int leon_nbputchar(int c);
-static int leon_nbgetchar(void);
-
-static int no_nextnode(int node);
-static int no_child(int node);
-static int no_proplen(int node, char *name);
-static int no_getprop(int node, char *name, char *value);
-static int no_setprop(int node, char *name, char *value, int len);
-static char *no_nextprop(int node, char *name);
-
-static struct property PROM_TEXT *find_property(int node, char *name);
-static int PROM_TEXT leon_strcmp(const char *s1, const char *s2);
-static void *PROM_TEXT leon_memcpy(void *dest, const void *src, size_t n);
-static void PROM_TEXT leon_reboot_physical(char *bcommand);
-
-void __inline__ leon_flush_cache_all(void)
-{
-	__asm__ __volatile__(" flush ");
-      __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH):"memory");
-}
-
-void __inline__ leon_flush_tlb_all(void)
-{
-	leon_flush_cache_all();
-	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x400),
-			     "i"(ASI_MMUFLUSH):"memory");
-}
-
-typedef struct {
-	unsigned int ctx_table[256];
-	unsigned int pgd_table[256];
-} sparc_srmmu_setup;
-
-sparc_srmmu_setup srmmu_tables PROM_PGT = {
-	{0},
-	{0x1e,
-	 0x10001e,
-	 0x20001e,
-	 0x30001e,
-	 0x40001e,
-	 0x50001e,
-	 0x60001e,
-	 0x70001e,
-	 0x80001e,
-	 0x90001e,
-	 0xa0001e,
-	 0xb0001e,
-	 0xc0001e,
-	 0xd0001e,
-	 0xe0001e,
-	 0xf0001e,
-	 0x100001e,
-	 0x110001e,
-	 0x120001e,
-	 0x130001e,
-	 0x140001e,
-	 0x150001e,
-	 0x160001e,
-	 0x170001e,
-	 0x180001e,
-	 0x190001e,
-	 0x1a0001e,
-	 0x1b0001e,
-	 0x1c0001e,
-	 0x1d0001e,
-	 0x1e0001e,
-	 0x1f0001e,
-	 0x200001e,
-	 0x210001e,
-	 0x220001e,
-	 0x230001e,
-	 0x240001e,
-	 0x250001e,
-	 0x260001e,
-	 0x270001e,
-	 0x280001e,
-	 0x290001e,
-	 0x2a0001e,
-	 0x2b0001e,
-	 0x2c0001e,
-	 0x2d0001e,
-	 0x2e0001e,
-	 0x2f0001e,
-	 0x300001e,
-	 0x310001e,
-	 0x320001e,
-	 0x330001e,
-	 0x340001e,
-	 0x350001e,
-	 0x360001e,
-	 0x370001e,
-	 0x380001e,
-	 0x390001e,
-	 0x3a0001e,
-	 0x3b0001e,
-	 0x3c0001e,
-	 0x3d0001e,
-	 0x3e0001e,
-	 0x3f0001e,
-	 0x400001e,
-	 0x410001e,
-	 0x420001e,
-	 0x430001e,
-	 0x440001e,
-	 0x450001e,
-	 0x460001e,
-	 0x470001e,
-	 0x480001e,
-	 0x490001e,
-	 0x4a0001e,
-	 0x4b0001e,
-	 0x4c0001e,
-	 0x4d0001e,
-	 0x4e0001e,
-	 0x4f0001e,
-	 0x500001e,
-	 0x510001e,
-	 0x520001e,
-	 0x530001e,
-	 0x540001e,
-	 0x550001e,
-	 0x560001e,
-	 0x570001e,
-	 0x580001e,
-	 0x590001e,
-	 0x5a0001e,
-	 0x5b0001e,
-	 0x5c0001e,
-	 0x5d0001e,
-	 0x5e0001e,
-	 0x5f0001e,
-	 0x600001e,
-	 0x610001e,
-	 0x620001e,
-	 0x630001e,
-	 0x640001e,
-	 0x650001e,
-	 0x660001e,
-	 0x670001e,
-	 0x680001e,
-	 0x690001e,
-	 0x6a0001e,
-	 0x6b0001e,
-	 0x6c0001e,
-	 0x6d0001e,
-	 0x6e0001e,
-	 0x6f0001e,
-	 0x700001e,
-	 0x710001e,
-	 0x720001e,
-	 0x730001e,
-	 0x740001e,
-	 0x750001e,
-	 0x760001e,
-	 0x770001e,
-	 0x780001e,
-	 0x790001e,
-	 0x7a0001e,
-	 0x7b0001e,
-	 0x7c0001e,
-	 0x7d0001e,
-	 0x7e0001e,
-	 0x7f0001e,
-	 0x800001e,
-	 0x810001e,
-	 0x820001e,
-	 0x830001e,
-	 0x840001e,
-	 0x850001e,
-	 0x860001e,
-	 0x870001e,
-	 0x880001e,
-	 0x890001e,
-	 0x8a0001e,
-	 0x8b0001e,
-	 0x8c0001e,
-	 0x8d0001e,
-	 0x8e0001e,
-	 0x8f0001e,
-	 0x900001e,
-	 0x910001e,
-	 0x920001e,
-	 0x930001e,
-	 0x940001e,
-	 0x950001e,
-	 0x960001e,
-	 0x970001e,
-	 0x980001e,
-	 0x990001e,
-	 0x9a0001e,
-	 0x9b0001e,
-	 0x9c0001e,
-	 0x9d0001e,
-	 0x9e0001e,
-	 0x9f0001e,
-	 0xa00001e,
-	 0xa10001e,
-	 0xa20001e,
-	 0xa30001e,
-	 0xa40001e,
-	 0xa50001e,
-	 0xa60001e,
-	 0xa70001e,
-	 0xa80001e,
-	 0xa90001e,
-	 0xaa0001e,
-	 0xab0001e,
-	 0xac0001e,
-	 0xad0001e,
-	 0xae0001e,
-	 0xaf0001e,
-	 0xb00001e,
-	 0xb10001e,
-	 0xb20001e,
-	 0xb30001e,
-	 0xb40001e,
-	 0xb50001e,
-	 0xb60001e,
-	 0xb70001e,
-	 0xb80001e,
-	 0xb90001e,
-	 0xba0001e,
-	 0xbb0001e,
-	 0xbc0001e,
-	 0xbd0001e,
-	 0xbe0001e,
-	 0xbf0001e,
-	 0xc00001e,
-	 0xc10001e,
-	 0xc20001e,
-	 0xc30001e,
-	 0xc40001e,
-	 0xc50001e,
-	 0xc60001e,
-	 0xc70001e,
-	 0xc80001e,
-	 0xc90001e,
-	 0xca0001e,
-	 0xcb0001e,
-	 0xcc0001e,
-	 0xcd0001e,
-	 0xce0001e,
-	 0xcf0001e,
-	 0xd00001e,
-	 0xd10001e,
-	 0xd20001e,
-	 0xd30001e,
-	 0xd40001e,
-	 0xd50001e,
-	 0xd60001e,
-	 0xd70001e,
-	 0xd80001e,
-	 0xd90001e,
-	 0xda0001e,
-	 0xdb0001e,
-	 0xdc0001e,
-	 0xdd0001e,
-	 0xde0001e,
-	 0xdf0001e,
-	 0xe00001e,
-	 0xe10001e,
-	 0xe20001e,
-	 0xe30001e,
-	 0xe40001e,
-	 0xe50001e,
-	 0xe60001e,
-	 0xe70001e,
-	 0xe80001e,
-	 0xe90001e,
-	 0xea0001e,
-	 0xeb0001e,
-	 0xec0001e,
-	 0xed0001e,
-	 0xee0001e,
-	 0xef0001e,
-	 0x400001e		/* default */
-	 }
-};
-
-/* a self contained prom info structure */
-struct leon_reloc_func {
-	struct property *(*find_property) (int node, char *name);
-	int (*strcmp) (char *s1, char *s2);
-	void *(*memcpy) (void *dest, const void *src, size_t n);
-	void (*reboot_physical) (char *cmd);
-};
-
-struct leon_prom_info {
-	int freq_khz;
-	int leon_nctx;
-	int mids[32];
-	int baudrates[2];
-	struct leon_reloc_func reloc_funcs;
-	struct property root_properties[4];
-	struct property cpu_properties[7];
-#undef  CPUENTRY
-#define CPUENTRY(idx) struct property cpu_properties##idx[4]
-	 CPUENTRY(1);
-	 CPUENTRY(2);
-	 CPUENTRY(3);
-	 CPUENTRY(4);
-	 CPUENTRY(5);
-	 CPUENTRY(6);
-	 CPUENTRY(7);
-	 CPUENTRY(8);
-	 CPUENTRY(9);
-	 CPUENTRY(10);
-	 CPUENTRY(11);
-	 CPUENTRY(12);
-	 CPUENTRY(13);
-	 CPUENTRY(14);
-	 CPUENTRY(15);
-	 CPUENTRY(16);
-	 CPUENTRY(17);
-	 CPUENTRY(18);
-	 CPUENTRY(19);
-	 CPUENTRY(20);
-	 CPUENTRY(21);
-	 CPUENTRY(22);
-	 CPUENTRY(23);
-	 CPUENTRY(24);
-	 CPUENTRY(25);
-	 CPUENTRY(26);
-	 CPUENTRY(27);
-	 CPUENTRY(28);
-	 CPUENTRY(29);
-	 CPUENTRY(30);
-	 CPUENTRY(31);
-	struct idprom idprom;
-	struct linux_nodeops nodeops;
-	struct linux_mlist_v0 *totphys_p;
-	struct linux_mlist_v0 totphys;
-	struct linux_mlist_v0 *avail_p;
-	struct linux_mlist_v0 avail;
-	struct linux_mlist_v0 *prommap_p;
-	void (*synchook) (void);
-	struct linux_arguments_v0 *bootargs_p;
-	struct linux_arguments_v0 bootargs;
-	struct linux_romvec romvec;
-	struct node nodes[35];
-	char s_device_type[12];
-	char s_cpu[4];
-	char s_mid[4];
-	char s_idprom[7];
-	char s_compatability[14];
-	char s_leon2[6];
-	char s_mmu_nctx[9];
-	char s_frequency[16];
-	char s_uart1_baud[11];
-	char s_uart2_baud[11];
-	char arg[256];
-};
-
-/* static prom info */
-static struct leon_prom_info PROM_DATA spi = {
-	CONFIG_SYS_CLK_FREQ / 1000,
-	256,
-	{
-#undef	CPUENTRY
-#define	CPUENTRY(idx) idx
-	 CPUENTRY(0),
-	 CPUENTRY(1),
-	 CPUENTRY(2),
-	 CPUENTRY(3),
-	 CPUENTRY(4),
-	 CPUENTRY(5),
-	 CPUENTRY(6),
-	 CPUENTRY(7),
-	 CPUENTRY(8),
-	 CPUENTRY(9),
-	 CPUENTRY(10),
-	 CPUENTRY(11),
-	 CPUENTRY(12),
-	 CPUENTRY(13),
-	 CPUENTRY(14),
-	 CPUENTRY(15),
-	 CPUENTRY(16),
-	 CPUENTRY(17),
-	 CPUENTRY(18),
-	 CPUENTRY(19),
-	 CPUENTRY(20),
-	 CPUENTRY(21),
-	 CPUENTRY(22),
-	 CPUENTRY(23),
-	 CPUENTRY(24),
-	 CPUENTRY(25),
-	 CPUENTRY(26),
-	 CPUENTRY(27),
-	 CPUENTRY(28),
-	 CPUENTRY(29),
-	 CPUENTRY(30),
-	 31},
-	{38400, 38400},
-	{
-	 __va(find_property),
-	 __va(leon_strcmp),
-	 __va(leon_memcpy),
-	 __phy(leon_reboot_physical),
-	 },
-	{
-	 {__va(spi.s_device_type), __va(spi.s_idprom), 4},
-	 {__va(spi.s_idprom), (char *)__va(&spi.idprom), sizeof(struct idprom)},
-	 {__va(spi.s_compatability), __va(spi.s_leon2), 5},
-	 {NULL, NULL, -1}
-	 },
-	{
-	 {__va(spi.s_device_type), __va(spi.s_cpu), 4},
-	 {__va(spi.s_mid), __va(&spi.mids[0]), 4},
-	 {__va(spi.s_mmu_nctx), (char *)__va(&spi.leon_nctx), 4},
-	 {__va(spi.s_frequency), (char *)__va(&spi.freq_khz), 4},
-	 {__va(spi.s_uart1_baud), (char *)__va(&spi.baudrates[0]), 4},
-	 {__va(spi.s_uart2_baud), (char *)__va(&spi.baudrates[1]), 4},
-	 {NULL, NULL, -1}
-	 },
-#undef  CPUENTRY
-#define CPUENTRY(idx) \
-	{ /* cpu_properties */						\
-		{__va(spi.s_device_type), __va(spi.s_cpu), 4},		\
-		{__va(spi.s_mid), __va(&spi.mids[idx]), 4},			\
-		{__va(spi.s_frequency), (char *)__va(&spi.freq_khz), 4},	\
-		{NULL, NULL, -1}						\
-	}
-	CPUENTRY(1),
-	CPUENTRY(2),
-	CPUENTRY(3),
-	CPUENTRY(4),
-	CPUENTRY(5),
-	CPUENTRY(6),
-	CPUENTRY(7),
-	CPUENTRY(8),
-	CPUENTRY(9),
-	CPUENTRY(10),
-	CPUENTRY(11),
-	CPUENTRY(12),
-	CPUENTRY(13),
-	CPUENTRY(14),
-	CPUENTRY(15),
-	CPUENTRY(16),
-	CPUENTRY(17),
-	CPUENTRY(18),
-	CPUENTRY(19),
-	CPUENTRY(20),
-	CPUENTRY(21),
-	CPUENTRY(22),
-	CPUENTRY(23),
-	CPUENTRY(24),
-	CPUENTRY(25),
-	CPUENTRY(26),
-	CPUENTRY(27),
-	CPUENTRY(28),
-	CPUENTRY(29),
-	CPUENTRY(30),
-	CPUENTRY(31),
-	{
-	 0x01,			/* format */
-	 M_LEON2 | M_LEON2_SOC,	/* machine type */
-	 {0, 0, 0, 0, 0, 0},	/* eth */
-	 0,			/* date */
-	 0,			/* sernum */
-	 0,			/* checksum */
-	 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}	/* reserved */
-	 },
-	{
-	 __va(no_nextnode),
-	 __va(no_child),
-	 __va(no_proplen),
-	 __va(no_getprop),
-	 __va(no_setprop),
-	 __va(no_nextprop)
-	 },
-	__va(&spi.totphys),
-	{
-	 NULL,
-	 (char *)CONFIG_SYS_SDRAM_BASE,
-	 0,
-	 },
-	__va(&spi.avail),
-	{
-	 NULL,
-	 (char *)CONFIG_SYS_SDRAM_BASE,
-	 0,
-	 },
-	NULL,			/* prommap_p */
-	NULL,
-	__va(&spi.bootargs),
-	{
-	 {NULL, __va(spi.arg), NULL /*... */ },
-	 /*... */
-	 },
-	{
-	 0,
-	 0,			/* sun4c v0 prom */
-	 0, 0,
-	 {__va(&spi.totphys_p), __va(&spi.prommap_p), __va(&spi.avail_p)},
-	 __va(&spi.nodeops),
-	 NULL, {NULL /* ... */ },
-	 NULL, NULL,
-	 NULL, NULL,		/* pv_getchar, pv_putchar */
-	 __va(leon_nbgetchar), __va(leon_nbputchar),
-	 NULL,
-	 __va(leon_reboot),
-	 NULL,
-	 NULL,
-	 NULL,
-	 __va(leon_halt),
-	 __va(&spi.synchook),
-	 {NULL},
-	 __va(&spi.bootargs_p)
-	 /*... */
-	 },
-	{
-	 {0, __va(spi.root_properties + 3) /* NULL, NULL, -1 */ },
-	 {0, __va(spi.root_properties)},
-	 /* cpu 0, must be spi.nodes[2] see leon_prom_init() */
-	 {1, __va(spi.cpu_properties)},
-
-#undef  CPUENTRY
-#define CPUENTRY(idx) \
-	  {1, __va(spi.cpu_properties##idx) }	/* cpu <idx> */
-	 CPUENTRY(1),
-	 CPUENTRY(2),
-	 CPUENTRY(3),
-	 CPUENTRY(4),
-	 CPUENTRY(5),
-	 CPUENTRY(6),
-	 CPUENTRY(7),
-	 CPUENTRY(8),
-	 CPUENTRY(9),
-	 CPUENTRY(10),
-	 CPUENTRY(11),
-	 CPUENTRY(12),
-	 CPUENTRY(13),
-	 CPUENTRY(14),
-	 CPUENTRY(15),
-	 CPUENTRY(16),
-	 CPUENTRY(17),
-	 CPUENTRY(18),
-	 CPUENTRY(19),
-	 CPUENTRY(20),
-	 CPUENTRY(21),
-	 CPUENTRY(22),
-	 CPUENTRY(23),
-	 CPUENTRY(24),
-	 CPUENTRY(25),
-	 CPUENTRY(26),
-	 CPUENTRY(27),
-	 CPUENTRY(28),
-	 CPUENTRY(29),
-	 CPUENTRY(30),
-	 CPUENTRY(31),
-	 {-1, __va(spi.root_properties + 3) /* NULL, NULL, -1 */ }
-	 },
-	"device_type",
-	"cpu",
-	"mid",
-	"idprom",
-	"compatability",
-	"leon2",
-	"mmu-nctx",
-	"clock-frequency",
-	"uart1_baud",
-	"uart2_baud",
-	CONFIG_DEFAULT_KERNEL_COMMAND_LINE
-};
-
-/* from arch/sparc/kernel/setup.c */
-#define RAMDISK_LOAD_FLAG 0x4000
-extern unsigned short root_flags;
-extern unsigned short root_dev;
-extern unsigned short ram_flags;
-extern unsigned int sparc_ramdisk_image;
-extern unsigned int sparc_ramdisk_size;
-extern int root_mountflags;
-
-extern char initrd_end, initrd_start;
-
-/* Reboot the CPU = jump to beginning of flash again.
- *
- * Make sure that all function are inlined here.
- */
-static void PROM_TEXT leon_reboot(char *bcommand)
-{
-	register char *arg = bcommand;
-	void __attribute__ ((noreturn)) (*reboot_physical) (char *cmd);
-
-	/* get physical address */
-	struct leon_prom_info *pspi =
-	    (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
-	unsigned int *srmmu_ctx_table;
-
-	/* Turn of Interrupts */
-	set_pil(0xf);
-
-	/* Set kernel's context, context zero */
-	srmmu_set_context(0);
-
-	/* Get physical address of the MMU shutdown routine */
-	reboot_physical = (void *)
-	    SPARC_BYPASS_READ(&pspi->reloc_funcs.reboot_physical);
-
-	/* Now that we know the physical address of the function
-	 * we can make the MMU allow jumping to it.
-	 */
-	srmmu_ctx_table = (unsigned int *)srmmu_get_ctable_ptr();
-
-	srmmu_ctx_table = (unsigned int *)SPARC_BYPASS_READ(srmmu_ctx_table);
-
-	/* get physical address of kernel's context table (assume ptd) */
-	srmmu_ctx_table = (unsigned int *)
-	    (((unsigned int)srmmu_ctx_table & 0xfffffffc) << 4);
-
-	/* enable access to physical address of MMU shutdown function */
-	SPARC_BYPASS_WRITE(&srmmu_ctx_table
-			   [((unsigned int)reboot_physical) >> 24],
-			   (((unsigned int)reboot_physical & 0xff000000) >> 4) |
-			   0x1e);
-
-	/* flush TLB cache */
-	leon_flush_tlb_all();
-
-	/* flash instruction & data cache */
-	sparc_icache_flush_all();
-	sparc_dcache_flush_all();
-
-	/* jump to physical address function
-	 * so that when the MMU is disabled
-	 * we can continue to execute
-	 */
-	reboot_physical(arg);
-}
-
-static void PROM_TEXT leon_reboot_physical(char *bcommand)
-{
-	void __attribute__ ((noreturn)) (*reset) (void);
-
-	/* Turn off MMU */
-	srmmu_set_mmureg(0);
-
-	/* Hardcoded start address */
-	reset = CONFIG_SYS_MONITOR_BASE;
-
-	/* flush data cache */
-	sparc_dcache_flush_all();
-
-	/* flush instruction cache */
-	sparc_icache_flush_all();
-
-	/* Jump to start in Flash */
-	reset();
-}
-
-static void PROM_TEXT leon_halt(void)
-{
-	while (1) ;
-}
-
-/* get single char, don't care for blocking*/
-static int PROM_TEXT leon_nbgetchar(void)
-{
-	return -1;
-}
-
-/* put single char, don't care for blocking*/
-static int PROM_TEXT leon_nbputchar(int c)
-{
-	LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
-
-	/***** put char in buffer... ***********
-	 * Make sure all functions are inline! *
-	 ***************************************/
-
-	/* Wait for last character to go. */
-	while (!(SPARC_BYPASS_READ(&leon2->UART_Status_1)
-		 & LEON2_UART_STAT_THE)) ;
-
-	/* Send data */
-	SPARC_BYPASS_WRITE(&leon2->UART_Channel_1, c);
-
-	/* Wait for data to be sent */
-	while (!(SPARC_BYPASS_READ(&leon2->UART_Status_1)
-		 & LEON2_UART_STAT_TSE)) ;
-
-	return 0;
-}
-
-/* node ops */
-
-/*#define nodes ((struct node *)__va(&pspi->nodes))*/
-#define nodes ((struct node *)(pspi->nodes))
-
-static int PROM_TEXT no_nextnode(int node)
-{
-	/* get physical address */
-	struct leon_prom_info *pspi =
-	    (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
-	/* convert into virtual address */
-	pspi = (struct leon_prom_info *)
-	    (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
-	if (nodes[node].level == nodes[node + 1].level)
-		return node + 1;
-	return -1;
-}
-
-static int PROM_TEXT no_child(int node)
-{
-	/* get physical address */
-	struct leon_prom_info *pspi = (struct leon_prom_info *)
-	    (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
-	/* convert into virtual address */
-	pspi = (struct leon_prom_info *)
-	    (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
-	if (nodes[node].level == nodes[node + 1].level - 1)
-		return node + 1;
-	return -1;
-}
-
-static struct property PROM_TEXT *find_property(int node, char *name)
-{
-	/* get physical address */
-	struct leon_prom_info *pspi = (struct leon_prom_info *)
-	    (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
-	/* convert into virtual address */
-	pspi = (struct leon_prom_info *)
-	    (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
-	struct property *prop = &nodes[node].properties[0];
-	while (prop && prop->name) {
-		if (pspi->reloc_funcs.strcmp(prop->name, name) == 0)
-			return prop;
-		prop++;
-	}
-	return NULL;
-}
-
-static int PROM_TEXT no_proplen(int node, char *name)
-{
-	/* get physical address */
-	struct leon_prom_info *pspi = (struct leon_prom_info *)
-	    (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
-	/* convert into virtual address */
-	pspi = (struct leon_prom_info *)
-	    (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
-	struct property *prop = pspi->reloc_funcs.find_property(node, name);
-	if (prop)
-		return prop->length;
-	return -1;
-}
-
-static int PROM_TEXT no_getprop(int node, char *name, char *value)
-{
-	/* get physical address */
-	struct leon_prom_info *pspi = (struct leon_prom_info *)
-	    (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
-	/* convert into virtual address */
-	pspi = (struct leon_prom_info *)
-	    (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
-	struct property *prop = pspi->reloc_funcs.find_property(node, name);
-	if (prop) {
-		pspi->reloc_funcs.memcpy(value, prop->value, prop->length);
-		return 1;
-	}
-	return -1;
-}
-
-static int PROM_TEXT no_setprop(int node, char *name, char *value, int len)
-{
-	return -1;
-}
-
-static char PROM_TEXT *no_nextprop(int node, char *name)
-{
-	/* get physical address */
-	struct leon_prom_info *pspi = (struct leon_prom_info *)
-	    (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-	struct property *prop;
-
-	/* convert into virtual address */
-	pspi = (struct leon_prom_info *)
-	    (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
-	if (!name || !name[0])
-		return nodes[node].properties[0].name;
-
-	prop = pspi->reloc_funcs.find_property(node, name);
-	if (prop)
-		return prop[1].name;
-	return NULL;
-}
-
-static int PROM_TEXT leon_strcmp(const char *s1, const char *s2)
-{
-	register char result;
-
-	while (1) {
-		result = *s1 - *s2;
-		if (result || !*s1)
-			break;
-		s2++;
-		s1++;
-	}
-
-	return result;
-}
-
-static void *PROM_TEXT leon_memcpy(void *dest, const void *src, size_t n)
-{
-	char *dst = (char *)dest, *source = (char *)src;
-
-	while (n--) {
-		*dst = *source;
-		dst++;
-		source++;
-	}
-	return dest;
-}
-
-#define GETREGSP(sp) __asm__ __volatile__("mov %%sp, %0" : "=r" (sp))
-
-void leon_prom_init(struct leon_prom_info *pspi)
-{
-	unsigned long i;
-	unsigned char cksum, *ptr;
-	char *addr_str, *end;
-	unsigned long sp;
-	GETREGSP(sp);
-
-	pspi->freq_khz = CONFIG_SYS_CLK_FREQ / 1000;
-
-	/* Set Available main memory size */
-	pspi->totphys.num_bytes = CONFIG_SYS_PROM_OFFSET - CONFIG_SYS_SDRAM_BASE;
-	pspi->avail.num_bytes = pspi->totphys.num_bytes;
-
-#undef nodes
-	pspi->nodes[3].level = -1;
-	pspi->nodes[3].properties = __va(spi.root_properties + 3);
-
-	/* Set Ethernet MAC address from environment */
-	if ((addr_str = getenv("ethaddr")) != NULL) {
-		for (i = 0; i < 6; i++) {
-			pspi->idprom.id_ethaddr[i] = addr_str ?
-			    simple_strtoul(addr_str, &end, 16) : 0;
-			if (addr_str) {
-				addr_str = (*end) ? end + 1 : end;
-			}
-		}
-	} else {
-		/* HW Address not found in environment,
-		 * Set default HW address
-		 */
-		pspi->idprom.id_ethaddr[0] = 0;
-		pspi->idprom.id_ethaddr[1] = 0;
-		pspi->idprom.id_ethaddr[2] = 0;
-		pspi->idprom.id_ethaddr[3] = 0;
-		pspi->idprom.id_ethaddr[4] = 0;
-		pspi->idprom.id_ethaddr[5] = 0;
-	}
-
-	ptr = (unsigned char *)&pspi->idprom;
-	for (i = cksum = 0; i <= 0x0E; i++)
-		cksum ^= *ptr++;
-	pspi->idprom.id_cksum = cksum;
-}
-
-static inline void set_cache(unsigned long regval)
-{
-	asm volatile ("sta %0, [%%g0] %1\n\t":: "r" (regval), "i"(2):"memory");
-}
-
-extern unsigned short bss_start, bss_end;
-
-/* mark as section .img.main.text, to be referenced in linker script */
-int prom_init(void)
-{
-	struct leon_prom_info *pspi = (void *)
-	    ((((unsigned int)&spi) & PROM_SIZE_MASK) + CONFIG_SYS_PROM_OFFSET);
-
-	/* disable mmu */
-	srmmu_set_mmureg(0x00000000);
-	__asm__ __volatile__("flush\n\t");
-
-	/* init prom info struct */
-	leon_prom_init(pspi);
-
-	kernel_arg_promvec = &pspi->romvec;
-#ifdef PRINT_ROM_VEC
-	printf("Kernel rom vec: 0x%lx\n", (unsigned int)(&pspi->romvec));
-#endif
-	return 0;
-}
-
-/* Copy current kernel boot argument to ROMvec */
-void prepare_bootargs(char *bootargs)
-{
-	struct leon_prom_info *pspi;
-	char *src, *dst;
-	int left;
-
-	/* if no bootargs set, skip copying ==> default bootline */
-	if (bootargs && (*bootargs != '\0')) {
-		pspi = (void *)((((unsigned int)&spi) & PROM_SIZE_MASK) +
-				CONFIG_SYS_PROM_OFFSET);
-		src = bootargs;
-		dst = &pspi->arg[0];
-		left = 255;	/* max len */
-		while (*src && left > 0) {
-			*dst++ = *src++;
-			left--;
-		}
-		/* terminate kernel command line string */
-		*dst = 0;
-	}
-}
-
-void srmmu_init_cpu(unsigned int entry)
-{
-	sparc_srmmu_setup *psrmmu_tables = (void *)
-	    ((((unsigned int)&srmmu_tables) & PROM_SIZE_MASK) +
-	     CONFIG_SYS_PROM_OFFSET);
-
-	/* Make context 0 (kernel's context) point
-	 * to our prepared memory mapping
-	 */
-#define PTD 1
-	psrmmu_tables->ctx_table[0] =
-	    ((unsigned int)&psrmmu_tables->pgd_table[0x00]) >> 4 | PTD;
-
-	/* Set virtual kernel address 0xf0000000
-	 * to SRAM/SDRAM address.
-	 * Make it READ/WRITE/EXEC to SuperUser
-	 */
-#define PTE 2
-#define ACC_SU_ALL 0x1c
-	psrmmu_tables->pgd_table[0xf0] =
-	    (CONFIG_SYS_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE;
-	psrmmu_tables->pgd_table[0xf1] =
-	    ((CONFIG_SYS_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE;
-	psrmmu_tables->pgd_table[0xf2] =
-	    ((CONFIG_SYS_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE;
-	psrmmu_tables->pgd_table[0xf3] =
-	    ((CONFIG_SYS_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE;
-	psrmmu_tables->pgd_table[0xf4] =
-	    ((CONFIG_SYS_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE;
-	psrmmu_tables->pgd_table[0xf5] =
-	    ((CONFIG_SYS_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE;
-	psrmmu_tables->pgd_table[0xf6] =
-	    ((CONFIG_SYS_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE;
-	psrmmu_tables->pgd_table[0xf7] =
-	    ((CONFIG_SYS_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE;
-
-	/* convert rom vec pointer to virtual address */
-	kernel_arg_promvec = (struct linux_romvec *)
-	    (((unsigned int)kernel_arg_promvec & 0x0fffffff) | 0xf0000000);
-
-	/* Set Context pointer to point to context table
-	 * 256 contexts supported.
-	 */
-	srmmu_set_ctable_ptr((unsigned int)&psrmmu_tables->ctx_table[0]);
-
-	/* Set kernel's context, context zero */
-	srmmu_set_context(0);
-
-	/* Invalidate all Cache */
-	__asm__ __volatile__("flush\n\t");
-
-	srmmu_set_mmureg(0x00000001);
-	leon_flush_tlb_all();
-	leon_flush_cache_all();
-}
diff --git a/arch/sparc/cpu/leon2/serial.c b/arch/sparc/cpu/leon2/serial.c
deleted file mode 100644
index 460abd1..0000000
--- a/arch/sparc/cpu/leon2/serial.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/* GRLIB APBUART Serial controller driver
- *
- * (C) Copyright 2008, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <serial.h>
-#include <watchdog.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static unsigned leon2_serial_calc_scaler(unsigned freq, unsigned baud)
-{
-	return (((freq*10) / (baud*8)) - 5) / 10;
-}
-
-static int leon2_serial_init(void)
-{
-	LEON2_regs *leon2 = (LEON2_regs *)LEON2_PREGS;
-	LEON2_Uart_regs *regs;
-	unsigned int tmp;
-
-#if LEON2_CONSOLE_SELECT == LEON_CONSOLE_UART1
-	regs = (LEON2_Uart_regs *)&leon2->UART_Channel_1;
-#else
-	regs = (LEON2_Uart_regs *)&leon2->UART_Channel_2;
-#endif
-
-	/* Set scaler / baud rate */
-	tmp = leon2_serial_calc_scaler(CONFIG_SYS_CLK_FREQ, CONFIG_BAUDRATE);
-	writel(tmp, &regs->UART_Scaler);
-
-	/* Let bit 11 be unchanged (debug bit for GRMON) */
-	tmp = readl(&regs->UART_Control) & LEON2_UART_CTRL_DBG;
-	tmp |= (LEON2_UART1_LOOPBACK_ENABLE << 7);
-	tmp |= (LEON2_UART1_FLOWCTRL_ENABLE << 6);
-	tmp |= (LEON2_UART1_PARITY_ENABLE << 5);
-	tmp |= (LEON2_UART1_ODDPAR_ENABLE << 4);
-	/* Receiver & transmitter enable */
-	tmp |= (LEON2_UART_CTRL_RE | LEON2_UART_CTRL_TE);
-	writel(tmp, &regs->UART_Control);
-
-	gd->arch.uart = regs;
-	return 0;
-}
-
-static inline LEON2_Uart_regs *leon2_get_uart_regs(void)
-{
-	LEON2_Uart_regs *uart = gd->arch.uart;
-
-	return uart;
-}
-
-static void leon2_serial_putc_raw(const char c)
-{
-	LEON2_Uart_regs *uart = leon2_get_uart_regs();
-
-	if (!uart)
-		return;
-
-	/* Wait for last character to go. */
-	while (!(readl(&uart->UART_Status) & LEON2_UART_STAT_THE))
-		WATCHDOG_RESET();
-
-	/* Send data */
-	writel(c, &uart->UART_Channel);
-
-#ifdef LEON_DEBUG
-	/* Wait for data to be sent */
-	while (!(readl(&uart->UART_Status) & LEON2_UART_STAT_TSE))
-		WATCHDOG_RESET();
-#endif
-}
-
-static void leon2_serial_putc(const char c)
-{
-	if (c == '\n')
-		leon2_serial_putc_raw('\r');
-
-	leon2_serial_putc_raw(c);
-}
-
-static int leon2_serial_getc(void)
-{
-	LEON2_Uart_regs *uart = leon2_get_uart_regs();
-
-	if (!uart)
-		return 0;
-
-	/* Wait for a character to arrive. */
-	while (!(readl(&uart->UART_Status) & LEON2_UART_STAT_DR))
-		WATCHDOG_RESET();
-
-	/* Read character data */
-	return readl(&uart->UART_Channel);
-}
-
-static int leon2_serial_tstc(void)
-{
-	LEON2_Uart_regs *uart = leon2_get_uart_regs();
-
-	if (!uart)
-		return 0;
-
-	return readl(&uart->UART_Status) & LEON2_UART_STAT_DR;
-}
-
-static void leon2_serial_setbrg(void)
-{
-	LEON2_Uart_regs *uart = leon2_get_uart_regs();
-	unsigned int scaler;
-
-	if (!uart)
-		return;
-
-	if (!gd->baudrate)
-		gd->baudrate = CONFIG_BAUDRATE;
-
-	scaler = leon2_serial_calc_scaler(CONFIG_SYS_CLK_FREQ, gd->baudrate);
-
-	writel(scaler, &uart->UART_Scaler);
-}
-
-static struct serial_device leon2_serial_drv = {
-	.name	= "leon2_serial",
-	.start	= leon2_serial_init,
-	.stop	= NULL,
-	.setbrg	= leon2_serial_setbrg,
-	.putc	= leon2_serial_putc,
-	.puts	= default_serial_puts,
-	.getc	= leon2_serial_getc,
-	.tstc	= leon2_serial_tstc,
-};
-
-void leon2_serial_initialize(void)
-{
-	serial_register(&leon2_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &leon2_serial_drv;
-}
diff --git a/arch/sparc/cpu/leon2/start.S b/arch/sparc/cpu/leon2/start.S
deleted file mode 100644
index 1b404da..0000000
--- a/arch/sparc/cpu/leon2/start.S
+++ /dev/null
@@ -1,695 +0,0 @@
-/* This is where the SPARC/LEON3 starts
- *
- * Copyright (C) 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/asmmacro.h>
-#include <asm/winmacro.h>
-#include <asm/psr.h>
-#include <asm/stack.h>
-#include <asm/leon.h>
-
-/* Entry for traps which jump to a programmer-specified trap handler.  */
-#define TRAPR(H)  \
-	wr	%g0, 0xfe0, %psr; \
-	mov	%g0, %tbr; \
-	ba	(H); \
-	mov	%g0, %wim;
-
-#define TRAP(H) \
-	mov	%psr, %l0; \
-	ba	(H); \
-	nop; nop;
-
-#define TRAPI(ilevel) \
-	mov	ilevel, %l7; \
-	mov	%psr, %l0; \
-	b	_irq_entry; \
-	mov	%wim, %l3
-
-/* Unexcpected trap will halt the processor by forcing it to error state */
-#undef BAD_TRAP
-#define BAD_TRAP ta 0; nop; nop; nop;
-
-/* Software trap. Treat as BAD_TRAP for the time being... */
-#define SOFT_TRAP TRAP(_hwerr)
-
-#define PSR_INIT   0x1FC0	/* Disable traps, set s and ps */
-#define WIM_INIT   2
-
-/* All traps low-level code here must end with this macro. */
-#define RESTORE_ALL b ret_trap_entry; clr %l6;
-
-#define WRITE_PAUSE nop;nop;nop
-
-WINDOWSIZE = (16 * 4)
-ARGPUSHSIZE = (6 * 4)
-ARGPUSH = (WINDOWSIZE + 4)
-MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4)
-
-/* Number of register windows */
-#ifndef CONFIG_SYS_SPARC_NWINDOWS
-#error Must define number of SPARC register windows, default is 8
-#endif
-
-/* Macros to load address into a register. Uses GOT table for PIC */
-#ifdef __PIC__
-
-#define SPARC_PIC_THUNK_CALL(reg) \
-	sethi	%pc22(_GLOBAL_OFFSET_TABLE_-4), %##reg; \
-	call	__sparc_get_pc_thunk.reg; \
-	 add	%##reg, %pc10(_GLOBAL_OFFSET_TABLE_+4), %##reg;
-
-#define SPARC_LOAD_ADDRESS(sym, got, reg) \
-	sethi	%gdop_hix22(sym), %##reg; \
-	xor	%##reg, %gdop_lox10(sym), %##reg; \
-	ld	[%##got + %##reg], %##reg, %gdop(sym);
-
-#else
-
-#define SPARC_PIC_THUNK_CALL(reg)
-#define SPARC_LOAD_ADDRESS(sym, got, tmp) \
-	set	sym, %##reg;
-
-#endif
-
-#define STACK_ALIGN	8
-#define SA(X)	(((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1))
-
-	.section ".start", "ax"
-	.globl	_start, start, _trap_table
-	.globl  _irq_entry, nmi_trap
-	.globl  _reset_reloc
-
-/* at address 0
- * Hardware traps
- */
-start:
-_start:
-_trap_table:
-	TRAPR(_hardreset);		! 00 reset trap
-	BAD_TRAP;			! 01 instruction_access_exception
-	BAD_TRAP;			! 02 illegal_instruction
-	BAD_TRAP;			! 03 priveleged_instruction
-	BAD_TRAP;			! 04 fp_disabled
-	TRAP(_window_overflow);		! 05 window_overflow
-	TRAP(_window_underflow);	! 06 window_underflow
-	BAD_TRAP;			! 07 Memory Address Not Aligned
-	BAD_TRAP;			! 08 Floating Point Exception
-	BAD_TRAP;			! 09 Data Miss Exception
-	BAD_TRAP;			! 0a Tagged Instruction Ovrflw
-	BAD_TRAP;			! 0b Watchpoint Detected
-	BAD_TRAP;			! 0c
-	BAD_TRAP;			! 0d
-	BAD_TRAP;			! 0e
-	BAD_TRAP;			! 0f
-	BAD_TRAP;			! 10
-	TRAPI(1);			! 11 IRQ level 1
-	TRAPI(2);			! 12 IRQ level 2
-	TRAPI(3);			! 13 IRQ level 3
-	TRAPI(4);			! 14 IRQ level 4
-	TRAPI(5);			! 15 IRQ level 5
-	TRAPI(6);			! 16 IRQ level 6
-	TRAPI(7);			! 17 IRQ level 7
-	TRAPI(8);			! 18 IRQ level 8
-	TRAPI(9);			! 19 IRQ level 9
-	TRAPI(10);			! 1a IRQ level 10
-	TRAPI(11);			! 1b IRQ level 11
-	TRAPI(12);			! 1c IRQ level 12
-	TRAPI(13);			! 1d IRQ level 13
-	TRAPI(14);			! 1e IRQ level 14
-	TRAP(_nmi_trap);		! 1f IRQ level 15 /
-					! NMI (non maskable interrupt)
-	BAD_TRAP;			! 20 r_register_access_error
-	BAD_TRAP;			! 21 instruction access error
-	BAD_TRAP;			! 22
-	BAD_TRAP;			! 23
-	BAD_TRAP;			! 24 co-processor disabled
-	BAD_TRAP;			! 25 uniplemented FLUSH
-	BAD_TRAP;			! 26
-	BAD_TRAP;			! 27
-	BAD_TRAP;			! 28 co-processor exception
-	BAD_TRAP;			! 29 data access error
-	BAD_TRAP;			! 2a division by zero
-	BAD_TRAP;			! 2b data store error
-	BAD_TRAP;			! 2c data access MMU miss
-	BAD_TRAP;			! 2d
-	BAD_TRAP;			! 2e
-	BAD_TRAP;			! 2f
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30-33
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34-37
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38-3b
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3c-3f
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40-43
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44-47
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48-4b
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4c-4f
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50-53
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54-57
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58-5b
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5c-5f
-
-	/* implementaion dependent */
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60-63
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64-67
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68-6b
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6c-6f
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70-73
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74-77
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78-7b
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 7c-7f
-
-	/* Software traps, not handled */
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 80-83
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 84-87
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 88-8b
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 8c-8f
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 90-93
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 94-97
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 98-9b
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 9c-9f
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! a0-a3
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! a4-a7
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! a8-ab
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! ac-af
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! b0-b3
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! b4-b7
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! b8-bb
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! bc-bf
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! c0-c3
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! c4-c7
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! c8-cb
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! cc-cf
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! d0-d3
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! d4-d7
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! d8-db
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! dc-df
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! e0-e3
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! e4-e7
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! e8-eb
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! ec-ef
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! f0-f3
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! f4-f7
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! f8-fb
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! fc-ff
-
-	.section	".text"
-	.align 4
-
-_hardreset:
-1000:
-	flush
-	nop
-	nop
-	nop
-
-	/* Init Cache */
-	set     (LEON2_PREGS+LEON_REG_CACHECTRL_OFFSET), %g1
-	set     0x0081000f, %g2
-	st      %g2, [%g1]
-
-	mov	%g0, %y
-	clr	%g1
-	clr	%g2
-	clr	%g3
-	clr	%g4
-	clr	%g5
-	clr	%g6
-	clr	%g7
-
-	mov	%asr17, %g3
-	and	%g3, 0x1f, %g3
-clear_window:
-	mov	%g0, %l0
-	mov	%g0, %l1
-	mov	%g0, %l2
-	mov	%g0, %l3
-	mov	%g0, %l4
-	mov	%g0, %l5
-	mov	%g0, %l6
-	mov	%g0, %l7
-	mov	%g0, %o0
-	mov	%g0, %o1
-	mov	%g0, %o2
-	mov	%g0, %o3
-	mov	%g0, %o4
-	mov	%g0, %o5
-	mov	%g0, %o6
-	mov	%g0, %o7
-	subcc	%g3, 1, %g3
-	bge	clear_window
-	save
-
-leon2_init:
-	/* LEON2 Register Base in g1 */
-	set	LEON2_PREGS, %g1
-
-leon2_init_cache:
-	/* Set Cache control register */
-	set	0x1000f, %g2
-	st	%g2, [%g1 + 0x14]
-
-leon2_init_clear:
-
-	/* Clear LEON2 registers */
-	st	%g0, [%g1 + LEON2_ECTRL]
-	st	%g0, [%g1 + LEON2_IMASK]
-	st	%g0, [%g1 + LEON2_IPEND]
-	st	%g0, [%g1 + LEON2_IFORCE]
-	st	%g0, [%g1 + LEON2_ICLEAR]
-	st	%g0, [%g1 + LEON2_IOREG]
-	st	%g0, [%g1 + LEON2_IODIR]
-	st	%g0, [%g1 + LEON2_IOICONF]
-	st	%g0, [%g1 + LEON2_UCTRL0]
-	st	%g0, [%g1 + LEON2_UCTRL1]
-
-leon2_init_ioport:
-	/* I/O port initialization */
-	set	0xaa00, %g2
-	st	%g2, [%g1 + LEON2_IOREG]
-
-leon2_init_mctrl:
-
-	/* memory config register 1 */
-	set	CONFIG_SYS_GRLIB_MEMCFG1, %g2
-	ld	[%g1], %g3		!
-	and	%g3, 0x300, %g3
-	or	%g2, %g3, %g2
-	st	%g2, [%g1 + LEON2_MCFG1]
-	set	CONFIG_SYS_GRLIB_MEMCFG2, %g2		! Load memory config register 2
-#if !( defined(TSIM) || !defined(BZIMAGE))
-	st	%g2, [%g1 + LEON2_MCFG2]	! only for prom version, else done by "dumon -i"
-#endif
-	set	CONFIG_SYS_GRLIB_MEMCFG3, %g2		! Init FT register
-	st	%g2, [%g1 + LEON2_ECTRL]
-	ld	[%g1 + LEON2_ECTRL], %g2
-	srl	%g2, 30, %g2
-	andcc	%g2, 3, %g6
-	bne,a	leon2_init_wim
-	 mov	%g0, %asr16		! clear err_reg
-
-leon2_init_wim:
-	set	WIM_INIT, %g3
-	mov	%g3, %wim
-
-leon2_init_psr:
-	set	0x1000, %g3
-	mov	%psr, %g2
-	wr	%g2, %g3, %psr
-	nop
-	nop
-	nop
-
-leon2_init_stackp:
-	set	CONFIG_SYS_INIT_SP_OFFSET, %fp
-	andn	%fp, 0x0f, %fp
-	sub	%fp, 64, %sp
-
-leon2_init_tbr:
-	set	CONFIG_SYS_TEXT_BASE, %g2
-	wr	%g0, %g2, %tbr
-	nop
-	nop
-	nop
-
-cpu_init_unreloc:
-	call	cpu_init_f
-	 nop
-
-board_init_unreloc:
-	call	board_init_f
-	 clr	%o0			! boot_flags
-
-dead_unreloc:
-	ba	dead_unreloc		! infinte loop
-	 nop
-
-!-------------------------------------------------------------------------------
-
-/* void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM after
- * relocating the monitor code.
- *
- * %o0 = Relocated stack pointer
- * %o1 = Relocated global data pointer
- * %o2 = Relocated text pointer
- */
-	.globl	relocate_code
-	.type	relocate_code, #function
-	.align	4
-relocate_code:
-	SPARC_PIC_THUNK_CALL(l7)
-
-/* un relocated start address of monitor */
-#define TEXT_START _text
-
-/* un relocated end address of monitor */
-#define DATA_END __init_end
-
-reloc:
-	SPARC_LOAD_ADDRESS(TEXT_START, l7, g2)
-	SPARC_LOAD_ADDRESS(DATA_END, l7, g3)
-	mov	%o2, %g4		! relocation address
-	sub	%g4, %g2, %g6		! relocation offset
-	/* copy .text & .data to relocated address */
-10:	ldd	[%g2], %l0
-	ldd	[%g2+8], %l2
-	std	%l0, [%g4]
-	std	%l2, [%g4+8]
-	inc	16, %g2			! src += 16
-	cmp	%g2, %g3
-	bcs	10b			! while (src < end)
-	 inc	16, %g4			! dst += 16
-
-	clr	%l0
-	clr	%l1
-	clr	%l2
-	clr	%l3
-	clr	%g2
-
-/* register g4 contain address to start
- * This means that BSS must be directly after data and code segments
- *
- * g3 is length of bss = (__bss_end-__bss_start)
- *
- */
-
-	/* clear bss area (the relocated) */
-clr_bss:
-	SPARC_LOAD_ADDRESS(__bss_start, l7, g2)
-	SPARC_LOAD_ADDRESS(__bss_end, l7, g3)
-	sub	%g3,%g2,%g3		! length of .bss area
-	add	%g3,%g4,%g3
-	/* clearing 16byte a time ==> linker script need to align to 16 byte offset */
-	clr	%g1	/* std %g0 uses g0 and g1 */
-20:
-	std	%g0, [%g4]
-	std	%g0, [%g4+8]
-	inc	16, %g4			! ptr += 16
-	cmp	%g4, %g3
-	bcs	20b			! while (ptr < end)
-	 nop
-
-	/* add offsets to GOT table */
-fixup_got:
-	SPARC_LOAD_ADDRESS(__got_start, l7, g4)
-	add	%g4, %g6, %g4
-	SPARC_LOAD_ADDRESS(__got_end, l7, g3)
-	add	%g3, %g6, %g3
-30:	ld	[%g4], %l0		! load old GOT-PTR
-#ifdef CONFIG_RELOC_GOT_SKIP_NULL
-	cmp	%l0, 0
-	be	32f
-#endif
-	add	%l0, %g6, %l0		! relocate GOT pointer
-	st	%l0, [%g4]
-32:	inc	4, %g4			! ptr += 4
-	cmp	%g4, %g3
-	bcs	30b			! while (ptr < end)
-	 nop
-
-prom_relocate:
-	SPARC_LOAD_ADDRESS(__prom_start, l7, g2)
-	SPARC_LOAD_ADDRESS(__prom_end, l7, g3)
-	/*
-	 * Calculated addres is stored in this variable by
-	 * reserve_prom() function in common/board_f.c
-	 */
-	SPARC_LOAD_ADDRESS(__prom_start_reloc, l7, g4)
-	ld	[%g4], %g4
-
-40:	ldd	[%g2], %l0
-	ldd	[%g2+8], %l2
-	std	%l0, [%g4]
-	std	%l2, [%g4+8]
-	inc	16, %g2
-	cmp	%g2, %g3
-	bcs	40b
-	 inc	16, %g4
-
-! %o0 = stack pointer (relocated)
-! %o1 = global data pointer (relocated)
-! %o2 = text pointer (relocated)
-
-! %g6 = relocation offset
-! %l7 = _GLOBAL_OFFSET_TABLE_
-
-/* Trap table has been moved, lets tell CPU about
- * the new trap table address
- */
-update_trap_table_address:
-	wr	%g0, %o2, %tbr
-	nop
-	nop
-	nop
-
-update_stack_pointers:
-	mov	%o0, %fp
-	andn	%fp, 0x0f, %fp	! align to 16 bytes
-	add	%fp, -64, %fp	! make space for a window push
-	mov	%fp, %sp	! setup stack pointer
-
-jump_board_init_r:
-	mov	%o1, %o0	! relocated global data pointer
-	mov	%o2, %o1	! relocated text pointer
-	SPARC_LOAD_ADDRESS(board_init_r, l7, o3)
-	add	%o3, %g6, %o3	! add relocation offset
-	call	%o3
-	 nop
-
-dead:	ta 0				! if call returns...
-	 nop
-
-!------------------------------------------------------------------------------
-
-/* Interrupt handler caller,
- * reg L7: interrupt number
- * reg L0: psr after interrupt
- * reg L1: PC
- * reg L2: next PC
- * reg L3: wim
- */
-_irq_entry:
-	SAVE_ALL
-
-	or	%l0, PSR_PIL, %g2
-	wr	%g2, 0x0, %psr
-	WRITE_PAUSE
-	wr	%g2, PSR_ET, %psr
-	WRITE_PAUSE
-	mov	%l7, %o0		! irq level
-	set	handler_irq, %o1
-	set	(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE), %o2
-	add	%o1, %o2, %o1
-	call	%o1
-	add	%sp, SF_REGS_SZ, %o1	! pt_regs ptr
-	or	%l0, PSR_PIL, %g2	! restore PIL after handler_irq
-	wr	%g2, PSR_ET, %psr	! keep ET up
-	WRITE_PAUSE
-
-	RESTORE_ALL
-
-!------------------------------------------------------------------------------
-
-/*
- * Window overflow trap handler.
- */
-	.global _window_overflow
-
-_window_overflow:
-
-	mov	%wim, %l3		! Calculate next WIM
-	mov	%g1, %l7
-	srl	%l3, 1, %g1
-	sll	%l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l4
-	or	%l4, %g1, %g1
-
-	save				! Get into window to be saved.
-	mov	%g1, %wim
-	nop; nop; nop
-	st	%l0, [%sp + 0];
-	st	%l1, [%sp + 4];
-	st	%l2, [%sp + 8];
-	st	%l3, [%sp + 12];
-	st	%l4, [%sp + 16];
-	st	%l5, [%sp + 20];
-	st	%l6, [%sp + 24];
-	st	%l7, [%sp + 28];
-	st	%i0, [%sp + 32];
-	st	%i1, [%sp + 36];
-	st	%i2, [%sp + 40];
-	st	%i3, [%sp + 44];
-	st	%i4, [%sp + 48];
-	st	%i5, [%sp + 52];
-	st	%i6, [%sp + 56];
-	st	%i7, [%sp + 60];
-	restore				! Go back to trap window.
-	mov	%l7, %g1
-	jmp	%l1			! Re-execute save.
-	rett	%l2
-
-/*
- * Window underflow trap handler.
- */
-	.global  _window_underflow
-
-_window_underflow:
-
-	mov  %wim, %l3			! Calculate next WIM
-	sll  %l3, 1, %l4
-	srl  %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l5
-	or   %l5, %l4, %l5
-	mov  %l5, %wim
-	nop; nop; nop
-	restore				! Two restores to get into the
-	restore				! window to restore
-	ld	[%sp + 0], %l0;		! Restore window from the stack
-	ld	[%sp + 4], %l1;
-	ld	[%sp + 8], %l2;
-	ld	[%sp + 12], %l3;
-	ld	[%sp + 16], %l4;
-	ld	[%sp + 20], %l5;
-	ld	[%sp + 24], %l6;
-	ld	[%sp + 28], %l7;
-	ld	[%sp + 32], %i0;
-	ld	[%sp + 36], %i1;
-	ld	[%sp + 40], %i2;
-	ld	[%sp + 44], %i3;
-	ld	[%sp + 48], %i4;
-	ld	[%sp + 52], %i5;
-	ld	[%sp + 56], %i6;
-	ld	[%sp + 60], %i7;
-	save				! Get back to the trap window.
-	save
-	jmp	%l1			! Re-execute restore.
-	rett	%l2
-
-!------------------------------------------------------------------------------
-
-_nmi_trap:
-	nop
-	jmp %l1
-	rett %l2
-
-_hwerr:
-	ta 0
-	nop
-	nop
-	b _hwerr			! loop infinite
-	nop
-
-/* Registers to not touch at all. */
-#define t_psr      l0 /* Set by caller */
-#define t_pc       l1 /* Set by caller */
-#define t_npc      l2 /* Set by caller */
-#define t_wim      l3 /* Set by caller */
-#define t_twinmask l4 /* Set at beginning of this entry routine. */
-#define t_kstack   l5 /* Set right before pt_regs frame is built */
-#define t_retpc    l6 /* If you change this, change winmacro.h header file */
-#define t_systable l7 /* Never touch this, could be the syscall table ptr. */
-#define curptr     g6 /* Set after pt_regs frame is built */
-
-trap_setup:
-/* build a pt_regs trap frame. */
-	sub	%fp, (SF_REGS_SZ + PT_REGS_SZ), %t_kstack
-	PT_STORE_ALL(t_kstack, t_psr, t_pc, t_npc, g2)
-
-	/* See if we are in the trap window. */
-	mov	1, %t_twinmask
-	sll	%t_twinmask, %t_psr, %t_twinmask ! t_twinmask = (1 << psr)
-	andcc	%t_twinmask, %t_wim, %g0
-	beq	1f		! in trap window, clean up
-	nop
-
-	/*-------------------------------------------------
-	 * Spill , adjust %wim and go.
-	 */
-	srl	%t_wim, 0x1, %g2		! begin computation of new %wim
-
-	set	(CONFIG_SYS_SPARC_NWINDOWS-1), %g3	!NWINDOWS-1
-
-	sll	%t_wim, %g3, %t_wim	! NWINDOWS-1
-	or	%t_wim, %g2, %g2
-	and	%g2, 0xff, %g2
-
-	save	%g0, %g0, %g0		! get in window to be saved
-
-	/* Set new %wim value */
-	wr	%g2, 0x0, %wim
-
-	/* Save the kernel window onto the corresponding stack. */
-	RW_STORE(sp)
-
-	restore	%g0, %g0, %g0
-	/*-------------------------------------------------*/
-
-1:
-	/* Trap from kernel with a window available.
-	 * Just do it...
-	 */
-	jmpl	%t_retpc + 0x8, %g0	! return to caller
-	 mov	%t_kstack, %sp		! jump onto new stack
-
-#define twin_tmp1 l4
-#define glob_tmp  g4
-#define curptr    g6
-ret_trap_entry:
-	wr	%t_psr, 0x0, %psr       ! enable nesting again, clear ET
-
-	/* Will the rett land us in the invalid window? */
-	mov	2, %g1
-	sll	%g1, %t_psr, %g1
-
-	set	CONFIG_SYS_SPARC_NWINDOWS, %g2	!NWINDOWS
-
-	srl	%g1, %g2, %g2
-	or	%g1, %g2, %g1
-	rd	%wim, %g2
-	andcc	%g2, %g1, %g0
-	be	1f		! Nope, just return from the trap
-	 sll	%g2, 0x1, %g1
-
-	/* We have to grab a window before returning. */
-	set	(CONFIG_SYS_SPARC_NWINDOWS-1), %g3	!NWINDOWS-1
-
-	srl	%g2, %g3,  %g2
-	or	%g1, %g2, %g1
-	and	%g1, 0xff, %g1
-
-	wr	%g1, 0x0, %wim
-
-	/* Grrr, make sure we load from the right %sp... */
-	PT_LOAD_ALL(sp, t_psr, t_pc, t_npc, g1)
-
-	restore	%g0, %g0, %g0
-	RW_LOAD(sp)
-	b	2f
-	save	%g0, %g0, %g0
-
-	/* Reload the entire frame in case this is from a
-	 * kernel system call or whatever...
-	 */
-1:
-	PT_LOAD_ALL(sp, t_psr, t_pc, t_npc, g1)
-2:
-	wr	%t_psr, 0x0, %psr
-	nop;
-	nop;
-	nop
-
-	jmp	%t_pc
-	rett	%t_npc
-
-/* This is called from relocated C-code.
- * It resets the system by jumping to _start
- */
-_reset_reloc:
-	set	start, %l0
-	call	%l0
-	nop
diff --git a/arch/sparc/cpu/leon3/Makefile b/arch/sparc/cpu/leon3/Makefile
deleted file mode 100644
index f4cf43c..0000000
--- a/arch/sparc/cpu/leon3/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-extra-y	= start.o
-obj-y	= cpu_init.o serial.o cpu.o ambapp.o ambapp_low.o ambapp_low_c.o \
-	interrupts.o prom.o usb_uhci.o memcfg.o memcfg_low.o
diff --git a/arch/sparc/cpu/leon3/ambapp.c b/arch/sparc/cpu/leon3/ambapp.c
deleted file mode 100644
index 47769cf..0000000
--- a/arch/sparc/cpu/leon3/ambapp.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/* GRLIB AMBA Plug&Play information scanning, relies on assembler
- * routines.
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* #define DEBUG */
-
-#include <common.h>
-#include <malloc.h>
-#include <ambapp.h>
-#include <config.h>
-
-/************ C INTERFACE OF ASSEMBLER SCAN ROUTINES ************/
-struct ambapp_find_apb_info {
-	/* Address of APB device Plug&Play information */
-	struct ambapp_pnp_apb	*pnp;
-	/* AHB Bus index of where the APB-Master Bridge device was found */
-	int			ahb_bus_index;
-	int			dec_index;
-};
-
-struct ambapp_find_ahb_info {
-	/* Address of AHB device Plug&Play information */
-	struct ambapp_pnp_ahb	*pnp;
-	/* AHB Bus index of where the AHB device was found */
-	int			ahb_bus_index;
-	int			dec_index;
-};
-
-extern void ambapp_find_buses(unsigned int ioarea, struct ambapp_bus *abus);
-
-extern int ambapp_find_apb(struct ambapp_bus *abus, unsigned int dev_vend,
-	int index, struct ambapp_find_apb_info *result);
-
-extern int ambapp_find_ahb(struct ambapp_bus *abus, unsigned int dev_vend,
-	int index, int type, struct ambapp_find_ahb_info *result);
-
-/************ C ROUTINES USED BY U-BOOT AMBA CORE DRIVERS ************/
-struct ambapp_bus ambapp_plb __section(.data);
-
-void ambapp_bus_init(
-	unsigned int ioarea,
-	unsigned int freq,
-	struct ambapp_bus *abus)
-{
-	int i;
-
-	ambapp_find_buses(ioarea, abus);
-	for (i = 0; i < 6; i++)
-		if (abus->ioareas[i] == 0)
-			break;
-	abus->buses = i;
-	abus->freq = freq;
-}
-
-/* Parse APB PnP Information */
-void ambapp_apb_parse(struct ambapp_find_apb_info *info, ambapp_apbdev *dev)
-{
-	struct ambapp_pnp_apb *apb = info->pnp;
-	unsigned int apbbase = (unsigned int)apb & 0xfff00000;
-
-	dev->vendor = amba_vendor(apb->id);
-	dev->device = amba_device(apb->id);
-	dev->irq = amba_irq(apb->id);
-	dev->ver = amba_ver(apb->id);
-	dev->address = (apbbase | (((apb->iobar & 0xfff00000) >> 12))) &
-			(((apb->iobar &	0x0000fff0) << 4) | 0xfff00000);
-	dev->mask = amba_apb_mask(apb->iobar);
-	dev->ahb_bus_index = info->ahb_bus_index - 1;
-}
-
-/* Parse AHB PnP information */
-void ambapp_ahb_parse(struct ambapp_find_ahb_info *info, ambapp_ahbdev *dev)
-{
-	struct ambapp_pnp_ahb *ahb = info->pnp;
-	unsigned int ahbbase = (unsigned int)ahb & 0xfff00000;
-	int i, type;
-	unsigned int addr, mask, mbar;
-
-	dev->vendor = amba_vendor(ahb->id);
-	dev->device = amba_device(ahb->id);
-	dev->irq = amba_irq(ahb->id);
-	dev->ver = amba_ver(ahb->id);
-	dev->userdef[0] = ahb->custom[0];
-	dev->userdef[1] = ahb->custom[1];
-	dev->userdef[2] = ahb->custom[2];
-	dev->ahb_bus_index = info->ahb_bus_index - 1;
-	for (i = 0; i < 4; i++) {
-		mbar = ahb->mbar[i];
-		addr = amba_membar_start(mbar);
-		type = amba_membar_type(mbar);
-		if (type == AMBA_TYPE_AHBIO) {
-			addr = amba_ahbio_adr(addr, ahbbase);
-			mask = (((unsigned int)
-				(amba_membar_mask((~mbar))<<8)|0xff))+1;
-		} else {
-			/* AHB memory area, absolute address */
-			mask = (~((unsigned int)
-				(amba_membar_mask(mbar)<<20)))+1;
-		}
-		dev->address[i] = addr;
-		dev->mask[i] = mask;
-		dev->type[i] = type;
-	}
-}
-
-int ambapp_apb_find(struct ambapp_bus *abus, int vendor, int device,
-	int index, ambapp_apbdev *dev)
-{
-	unsigned int devid = AMBA_PNP_ID(vendor, device);
-	int found;
-	struct ambapp_find_apb_info apbdev;
-
-	found = ambapp_find_apb(abus, devid, index, &apbdev);
-	if (found == 1)
-		ambapp_apb_parse(&apbdev, dev);
-
-	return found;
-}
-
-int ambapp_apb_count(struct ambapp_bus *abus, int vendor, int device)
-{
-	unsigned int devid = AMBA_PNP_ID(vendor, device);
-	int found;
-	struct ambapp_find_apb_info apbdev;
-
-	found = ambapp_find_apb(abus, devid, 63, &apbdev);
-	if (found == 1)
-		return 64;
-	else
-		return 63 - apbdev.dec_index;
-}
-
-int ambapp_ahb_find(struct ambapp_bus *abus, int vendor, int device,
-	int index, ambapp_ahbdev *dev, int type)
-{
-	int found;
-	struct ambapp_find_ahb_info ahbdev;
-	unsigned int devid = AMBA_PNP_ID(vendor, device);
-
-	found = ambapp_find_ahb(abus, devid, index, type, &ahbdev);
-	if (found == 1)
-		ambapp_ahb_parse(&ahbdev, dev);
-
-	return found;
-}
-
-int ambapp_ahbmst_find(struct ambapp_bus *abus, int vendor, int device,
-	int index, ambapp_ahbdev *dev)
-{
-	return ambapp_ahb_find(abus, vendor, device, index, dev, DEV_AHB_MST);
-}
-
-int ambapp_ahbslv_find(struct ambapp_bus *abus, int vendor, int device,
-	int index, ambapp_ahbdev *dev)
-{
-	return ambapp_ahb_find(abus, vendor, device, index, dev, DEV_AHB_SLV);
-}
-
-int ambapp_ahb_count(struct ambapp_bus *abus, int vendor, int device, int type)
-{
-	int found;
-	struct ambapp_find_ahb_info ahbdev;
-	unsigned int devid = AMBA_PNP_ID(vendor, device);
-
-	found = ambapp_find_ahb(abus, devid, 63, type, &ahbdev);
-	if (found == 1)
-		return 64;
-	else
-		return 63 - ahbdev.dec_index;
-}
-
-int ambapp_ahbmst_count(struct ambapp_bus *abus, int vendor, int device)
-{
-	return ambapp_ahb_count(abus, vendor, device, DEV_AHB_MST);
-}
-
-int ambapp_ahbslv_count(struct ambapp_bus *abus, int vendor, int device)
-{
-	return ambapp_ahb_count(abus, vendor, device, DEV_AHB_SLV);
-}
-
-/* The define CONFIG_SYS_GRLIB_SINGLE_BUS may be defined on GRLIB systems
- * where only one AHB Bus is available - no bridges are present. This option
- * is available only to reduce the footprint.
- *
- * Defining this on a multi-bus GRLIB system may also work depending on the
- * design.
- */
-
-#ifndef CONFIG_SYS_GRLIB_SINGLE_BUS
-
-/* GAISLER AHB2AHB Version 1 Bridge Definitions */
-#define AHB2AHB_V1_FLAG_FFACT     0x0f0	/* Frequency factor against top bus */
-#define AHB2AHB_V1_FLAG_FFACT_DIR 0x100	/* Factor direction, 0=down, 1=up */
-#define AHB2AHB_V1_FLAG_MBUS      0x00c	/* Master bus number mask */
-#define AHB2AHB_V1_FLAG_SBUS      0x003	/* Slave bus number mask */
-
-/* Get Parent bus frequency. Note that since we go from a "child" bus
- * to a parent bus, the frequency factor direction is inverted.
- */
-unsigned int gaisler_ahb2ahb_v1_freq(ambapp_ahbdev *ahb, unsigned int freq)
-{
-	int dir;
-	unsigned char ffact;
-
-	/* Get division/multiple factor */
-	ffact = (ahb->userdef[0] & AHB2AHB_V1_FLAG_FFACT) >> 4;
-	if (ffact != 0) {
-		dir = ahb->userdef[0] & AHB2AHB_V1_FLAG_FFACT_DIR;
-
-		/* Calculate frequency by dividing or
-		 * multiplying system frequency
-		 */
-		if (dir)
-			freq = freq * ffact;
-		else
-			freq = freq / ffact;
-	}
-
-	return freq;
-}
-
-/* AHB2AHB and L2CACHE ver 2 is not supported yet. */
-unsigned int gaisler_ahb2ahb_v2_freq(ambapp_ahbdev *ahb, unsigned int freq)
-{
-	panic("gaisler_ahb2ahb_v2_freq: AHB2AHB ver 2 not supported\n");
-	return -1;
-}
-#endif
-
-/* Return the frequency of a AHB bus identified by index found
- * note that this is not the AHB Bus number.
- */
-unsigned int ambapp_bus_freq(struct ambapp_bus *abus, int ahb_bus_index)
-{
-	unsigned int freq = abus->freq;
-#ifndef CONFIG_SYS_GRLIB_SINGLE_BUS
-	unsigned int ioarea, ioarea_parent, bridge_pnp_ofs;
-	struct ambapp_find_ahb_info ahbinfo;
-	ambapp_ahbdev ahb;
-	int parent;
-
-	debug("ambapp_bus_freq: get freq on bus %d\n", ahb_bus_index);
-
-	while (ahb_bus_index != 0) {
-		debug("  BUS[0]: 0x%08x\n", abus->ioareas[0]);
-		debug("  BUS[1]: 0x%08x\n", abus->ioareas[1]);
-		debug("  BUS[2]: 0x%08x\n", abus->ioareas[2]);
-		debug("  BUS[3]: 0x%08x\n", abus->ioareas[3]);
-		debug("  BUS[4]: 0x%08x\n", abus->ioareas[4]);
-		debug("  BUS[5]: 0x%08x\n", abus->ioareas[5]);
-
-		/* Get I/O area of AHB bus */
-		ioarea = abus->ioareas[ahb_bus_index];
-
-		debug("  IOAREA: 0x%08x\n", ioarea);
-
-		/* Get parent bus */
-		parent = (ioarea & 0x7);
-		if (parent == 0) {
-			panic("%s: parent=0 indicates no parent! Stopping.\n",
-				__func__);
-			return -1;
-		}
-		parent = parent - 1;
-		bridge_pnp_ofs = ioarea & 0x7e0;
-
-		debug("  PARENT: %d\n", parent);
-		debug("  BRIDGE_OFS: 0x%08x\n", bridge_pnp_ofs);
-
-		/* Get AHB/AHB bridge PnP address */
-		ioarea_parent = (abus->ioareas[parent] & 0xfff00000) |
-				AMBA_CONF_AREA | AMBA_AHB_SLAVE_CONF_AREA;
-		ahbinfo.pnp = (struct ambapp_pnp_ahb *)
-				(ioarea_parent | bridge_pnp_ofs);
-
-		debug("  IOAREA PARENT: 0x%08x\n", ioarea_parent);
-		debug("  BRIDGE PNP: 0x%p\n", ahbinfo.pnp);
-
-		/* Parse the AHB information */
-		ahbinfo.ahb_bus_index = parent;
-		ambapp_ahb_parse(&ahbinfo, &ahb);
-
-		debug("  BRIDGE ID: VENDOR=%d(0x%x), DEVICE=%d(0x%x)\n",
-			ahb.vendor, ahb.vendor, ahb.device, ahb.device);
-
-		/* Different bridges may convert frequency differently */
-		if ((ahb.vendor == VENDOR_GAISLER) &&
-			((ahb.device == GAISLER_AHB2AHB) ||
-			(ahb.device == GAISLER_L2CACHE))) {
-			/* Get new frequency */
-			if (ahb.ver > 1)
-				freq = gaisler_ahb2ahb_v2_freq(&ahb, freq);
-			else
-				freq = gaisler_ahb2ahb_v1_freq(&ahb, freq);
-
-			debug("  NEW FREQ: %dHz\n", freq);
-		} else {
-			panic("%s: unsupported AMBA bridge\n", __func__);
-			return -1;
-		}
-
-		/* Step upwards towards system top bus */
-		ahb_bus_index = parent;
-	}
-#endif
-
-	debug("ambapp_bus_freq: %dHz\n", freq);
-
-	return freq;
-}
diff --git a/arch/sparc/cpu/leon3/ambapp_low.S b/arch/sparc/cpu/leon3/ambapp_low.S
deleted file mode 100644
index 2863586..0000000
--- a/arch/sparc/cpu/leon3/ambapp_low.S
+++ /dev/null
@@ -1,784 +0,0 @@
-/* GRLIB AMBA Plug&Play information scanning implemented without
- * using memory (stack) and one register window. The code scan
- * the PnP info and inserts the AHB bridges/buses into register
- * i0-i5.
- * The code support
- *  - up to 6 AHB buses
- *  - multiple APB buses
- *  - support for AHB2AHB & L2CACHE bridges
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <ambapp.h>
-
-	.seg	"text"
-	.globl	_nomem_amba_init
-	.globl	_nomem_ambapp_find_buses
-	.globl	_nomem_find_apb
-	.globl	_nomem_find_ahb
-
-/* Overview
- * ========
- *
- * _nomem_amba_init         - Init AMBA bus and calls _nomem_ambapp_find_buses
- * _nomem_ambapp_find_buses - Scan AMBA PnP info for AHB buses/bridges and
- *                            place them in i0-i5, see below
- * _nomem_find_apb          - Find one APB device identified by VENDOR:DEVICE
- *                            ID and an index.
- * _nomem_find_ahb          - Find one AHB Master or Slave device identified
- *                            by VENDOR:DEVICE ID and an index.
- * init_ahb_bridges         - Local function. Clears i0-i5
- * insert_ahb_bridge        - Local function. Insert a new AHB bus into first
- *                            free register in i0-i5. It also checks that the
- *                            bus has not already been added.
- * get_ahb_bridge           - Local function. Get AHB bus from registers,
- *                            return register iN, where N is defined by o0.
- *
- * The _nomem_find_apb and _nomem_find_ahb function requires that i0-i5
- * are populated with the AHB buses of the system. The registers are
- * initialized by _nomem_ambapp_find_buses.
- *
- * AHB Bus result and requirements of i0-i5
- * ========================================
- *
- * i0: AHB BUS0 IOAREA, no parent bus
- * i1: AHB BUS1 IOAREA, parent bus is always i0 (AHB BUS0) and bridge address
- * i2: AHB BUS2 IOAREA, 3-bit parent bus number and bridge address
- * i3: AHB BUS3 IOAREA, 3-bit parent bus number and bridge address
- * i4: AHB BUS4 IOAREA, 3-bit parent bus number and bridge address
- * i5: AHB BUS5 IOAREA, 3-bit parent bus number and bridge address
- *
- * AHB BUS
- * -------
- * Bits 31-20 (0xfff00000) contain the found bus I/O Area (AHB PnP area).
- *
- * 3-bit Parent bus
- * ----------------
- * Bits 2-0 (0x00000007) contain parent bus number. Zero if no parent
- * bus, 1 = parent is AHB BUS 0 (i0), 2 = parent is AHB BUS 1 (i1)..
- *
- * Bridge Address
- * --------------
- * Bits 10-5 (0x000007e0) contain the index of the Bridge's PnP
- * information on the parent. Since all bridges are found in the
- * PnP information they all have a PnP entry. Together with the
- * parent bus number the PnP entry can be found:
- *  PnPEntry = (BRIDGE_ADDRESS + (iN & 0xfff00000)) | 0x000ff800
- *  where N is the parent bus minus one.
- *
- */
-
-/* Function initializes the AHB Bridge I/O AREA storage. (Clears i0-i5)
- *
- * Arguments
- *  none
- *
- * Results
- *  none
- *
- * Clobbered
- *  none
- */
-
-init_ahb_bridges:
-	mov	%g0, %i0
-	mov	%g0, %i1
-	mov	%g0, %i2
-	mov	%g0, %i3
-	mov	%g0, %i4
-	retl
-	 mov	%g0, %i5
-
-/* Function returns AHB Bridge I/O AREA for specified bus.
- *
- * Arguments
- *  - o0 = bus number
- *
- * Results
- *  - o0 = I/O AREA
- *
- * Clobbered
- *  none
- */
-get_ahb_bridge:
-	cmp	%o0, 1
-	be,a	L1
-	 mov	%i0, %o0
-
-	cmp	%o0, 2
-	be,a	L1
-	 mov	%i1, %o0
-
-	cmp	%o0, 3
-	be,a	L1
-	 mov	%i2, %o0
-
-	cmp	%o0, 4
-	be,a	L1
-	 mov	%i3, %o0
-
-	cmp	%o0, 5
-	be,a	L1
-	 mov	%i4, %o0
-
-	cmp	%o0, 6
-	be,a	L1
-	 mov	%i5, %o0
-
-	/* o0 > 6: only 6 buses supported */
-	mov	%g0, %o0
-L1:
-	retl
-	 nop
-
-/* Function adds a AHB Bridge I/O AREA to the i0-i5 registers if
- * not already added. It stores the bus PnP start information.
- *
- * Arguments
- *  - o0 = AHB Bridge I/O area
- *
- * Results
- *  none
- *
- * Clobbered
- *  o2, o3
- */
-insert_ahb_bridge:
-	/* Check that bridge hasn't already been added */
-	andn	%o0, 0x7ff, %o2
-	andn	%i0, 0x7ff, %o3
-	cmp	%o3, %o2
-	be	L2
-	 andn	%i1, 0x7ff, %o3
-	cmp	%o3, %o2
-	be	L2
-	 andn	%i2, 0x7ff, %o3
-	cmp	%o3, %o2
-	be	L2
-	 andn	%i3, 0x7ff, %o3
-	cmp	%o3, %o2
-	be	L2
-	 andn	%i4, 0x7ff, %o3
-	cmp	%o3, %o2
-	be	L2
-	 andn	%i5, 0x7ff, %o3
-	cmp	%o3, %o2
-	be	L2
-
-	/* Insert into first free posistion */
-	 cmp	%i0, %g0
-	be,a	L2
-	 mov	%o0, %i0
-
-	cmp	%i1, %g0
-	be,a	L2
-	 mov	%o0, %i1
-
-	cmp	%i2, %g0
-	be,a	L2
-	 mov	%o0, %i2
-
-	cmp	%i3, %g0
-	be,a	L2
-	 mov	%o0, %i3
-
-	cmp	%i4, %g0
-	be,a	L2
-	 mov	%o0, %i4
-
-	cmp	%i5, %g0
-	be,a	L2
-	 mov	%o0, %i5
-L2:
-	retl
-	 nop
-
-/* FUNCTION int _nomem_find_ahb_bus(
- *	unsigned int bridge,
- *	int vendor_device,
- *	int index,
- *	void **pconf,
- *	int not_used,
- *	int option
- *	)
- *
- * Scans the AHB Master or Slave area for a matching VENDOR:DEVICE, the
- * index is decremented when a matching device is found but index is
- * greater than zero. When index is zero and a matching DEVICE:VENDOR
- * is found the AHB configuration address and AHB I/O area is returned.
- *
- * i0-i7,l0,l1,l2,l3,l4,g2,o6 is not available for use.
- * o1,o5 Must be left untouched
- *
- * Results
- *  - o0 Number of found devices (1 or 0)
- *  - o2 is decremented for each matching VENDOR:DEVICE found, zero if found
- *  - o3 Address of the AHB PnP configuration entry (Only valid if o0=1)
- *
- * Clobbered
- *  - o3 (Clobbered when no device was found)
- *  - o4 (Number of Devices left to search)
- *  - o0 (Bus ID, PnP ID, Device)
- */
-_nomem_find_ahb_bus:
-
-	/* Get the number of Slaves/Masters.
-	 * Only AHB Bus 0 has 64 AHB Masters/Slaves the
-	 * other AHB buses has 16 slaves and 16 masters.
-	 */
-	add	%g0, 16, %o4		/* Defaulting to 16 */
-	andcc	%o0, 0x7, %g0		/* 3-bit bus id */
-	be,a	.L_maxloops_detected
-	 add	%g0, 64, %o4		/* AHB Bus 0 has 64 AHB Masters/Slaves */
-.L_maxloops_detected:
-
-	/* Get start address of AHB Slave or AHB Master area depending on what
-	 * we are searching for.
-	 */
-	andn	%o0, 0x7ff, %o0		/* Remove Bus ID and 5-bit AHB/AHB
-					 * Bridge PnP Address to get I/O Area */
-	set	AMBA_CONF_AREA,	%o3
-	or	%o3, %o0, %o3		/* Master area address */
-
-	cmp	%o5, DEV_AHB_SLV
-	be,a	.L_conf_area_calculated
-	 or	%o3, AMBA_AHB_SLAVE_CONF_AREA, %o3	/* Add 0x800 to get to slave area */
-.L_conf_area_calculated:
-
-	/* Iterate over all AHB device and try to find matching DEVICE:VENDOR
-	 * o1 - VENDOR|DEVICE
-	 * o2 - Index
-	 * o3 - Current AHB Device Configuration address
-	 * o5 - Type (leave untouched)
-	 *
-	 * o4 - Number of AHB device left to process
-	 * o0 - tmp
-	 */
-.L_process_one_conf:
-	ld	[%o3], %o0
-	andn	%o0, 0xfff, %o0
-	cmp	%o0, 0			/* No device if zero */
-	beq	.L_next_conf
-	 cmp	%o1, 0			/* If VENDOR:DEVICE==0, consider all matching */
-	beq	.L_process_ahb_dev_found
-	 cmp	%o0, %o1		/* Does VENDOR and DEVICE Match? */
-	bne	.L_next_conf
-	 nop
-.L_process_ahb_dev_found:
-	/* Found a Matching VENDOR:DEVICE, index must also match */
-	cmp	%o2, %g0
-	bne	.L_next_conf
-	 dec	%o2
-	/* Index matches also, return happy with o3 set to AHB Conf Address */
-	mov	%g0, %o2
-	retl
-	 add	%g0, 1, %o0
-
-.L_next_conf:
-	subcc	%o4, 1, %o4		/* One device has been processed,
-					 * Are there more devices to process? */
-	bne	.L_process_one_conf
-	 add	%o3, AMBA_AHB_CONF_LENGH, %o3	/* Next Configuration entry */
-	/* No Matching device found */
-	retl
-	 mov	%g0, %o0
-
-/* FUNCTION int _nomem_find_ahb(
- *      int unused,
- *	int vendor_device,
- *	int index,
- *	void **pconf,
- *	int *ahb_bus_index,
- *	int option,
- *	)
- *
- * Find a AHB Master or AHB Slave device, it puts the address of the AHB PnP
- * configuration in o3 (pconf), the I/O Area base address in o4 (pioarea).
- *
- * Calls _nomem_find_ahb_bus for every AHB bus.
- *
- * i0-i7, l0, l1, o6, g1, g4-g7 is not available for use.
- *
- * Arguments
- *  - o0 Unused
- *
- * Results
- *  - o0 Number of found devices (1 or 0)
- *  - o2 Decremented Index (Zero if found)
- *  - o3 Address of the AHB PnP configuration entry
- *  - o4 AHB Bus index the device was found on (if o0=1)
- *  - o5 Left untouched
- *
- * Clobbered
- *  - o0 (AHB Bridge and used by _nomem_find_ahb_bus)
- *  - o2 (index is decremented)
- *  - l2 (Current AHB Bus index)
- *  - g2 (return address)
- */
-_nomem_find_ahb:
-	mov	%o7, %g2		/* Save return address */
-	/* Scan all AHB Buses found for the AHB Master/Slave matching VENDOR:DEVICE */
-	clr	%l2
-.L_search_next_ahb_bus:
-	add	%l2, 1, %l2
-	call	get_ahb_bridge			/* Get bus %l0 I/O Area */
-	 mov	%l2, %o0
-	cmp	%o0, %g0
-	be	.L_no_device_found		/* If no more AHB bus is left to be scanned, proceed */
-	 nop
-	call	_nomem_find_ahb_bus		/* Scan AHB bus %o0 for VENDOR:DEVICE. Index in o3 is decremented  */
-	 nop
-	cmp	%o0, %g0			/* If VENDOR:DEVICE was not found scan next AHB Bus */
-	be	.L_search_next_ahb_bus		/* Do next bus is o0=0 (not found) */
-	 nop
-	/* The device was found, o0 is 1 */
-	mov	%g2, %o7		/* Restore return address */
-	retl
-	 mov	%l2, %o4		/* The AHB bus index the device was found on */
-
-	/* No device found matching */
-.L_no_device_found:
-	mov	%g2, %o7		/* Restore return address */
-	retl
-	 mov	%g0, %o0
-
-
-/* FUNCTION int _nomem_find_apb_bus(
- *      int apbmst,
- *	int vendor_device,
- *	int index,
- *	void **pconf
- *	)
- *
- * Find a APB Slave device, it puts the address of the APB PnP configuration
- * in o3 (pconf).
- *
- * Calls _nomem_find_ahb_bus for every AHB bus searching for AHB/APB Bridges.
- * The AHB/APB bridges are AHB Slaves with ID GAISLER_APBMST.
- *
- * Results
- *  - o0 Number of found devices (1 or 0)
- *  - o2 Decremented Index
- *  - o3 Address of the found APB device PnP configuration entry
- *
- * Clobbered
- *  - o5 PnP VENDOR:DEVICE ID
- */
-
-_nomem_find_apb_bus:
-	set	AMBA_CONF_AREA, %o3
-	or	%o0, %o3, %o3		/* Calc start of APB device PnP info */
-	add	%g0, 16, %o0		/* o0, number of APB Slaves left to scan */
-.L_process_one_apb_conf:
-	ld	[%o3], %o5
-	andn	%o5, 0xfff, %o5
-	cmp	%o5, 0			/* No device if zero */
-	beq	.L_process_apb_dev_not_found
-	 cmp	%o1, 0			/* If VENDOR:DEVICE == -1, consider all matching */
-	beq	.L_process_apb_dev_found
-	 cmp	%o1, %o5		/* Found VENDOR:DEVICE */
-	bne	.L_process_apb_dev_not_found
-	 nop
-
-.L_process_apb_dev_found:
-	/* Found matching device, compare index */
-	cmp	%o2, %g0
-	bne	.L_process_apb_dev_not_found
-	 dec	%o2
-	/* Matching index and VENDOR:DEVICE */
-	retl
-	 add	%g0, 1, %o0
-
-.L_process_apb_dev_not_found:
-	subcc	%o0, 1, %o0
-	bne	.L_process_one_apb_conf
-	 add	%o3, 8, %o3
-	retl
-	 mov	%g0, %o0
-
-/* FUNCTION int _nomem_find_apb(
- *      int unused,
- *	int vendor_device,
- *	int index,
- *	void **pconf,
- *	int *ahb_bus_index
- *	)
- *
- * Find a APB Slave device, it puts the address of the APB PnP configuration
- * in o3 (pconf), the APB Master I/O Area base address in o4 (papbarea).
- *
- * Calls _nomem_find_ahb_bus for every AHB bus searching for AHB/APB Bridges.
- * The AHB/APB bridges are AHB Slaves with ID GAISLER_APBMST.
- *
- * i0-i7, l0, l1, o6 is not available for use.
- *
- * Arguments
- *  - o0 Unused
- *
- * Results
- *  - o0 Number of found devices (1 or 0)
- *  - o2 Decremented Index if not found
- *  - o3 Address of the APB PnP configuration entry
- *  - o4 AHB Bus index of APB Bridge/APB Device
- *
- * Clobbered
- *  - o0 (AHB Bridge)
- *  - o2 (index is decremented)
- *  - l2 (APB DEV Index [7..4] : APBMST AHB Index [3..0])
- *  - l3 (Current AHB Bus index)
- *  - l4 (temporary storage for APB VENDOR:DEVICE)
- *  - o5 (AHB Slave ID)
- *  - o0 (clobbered by _nomem_find_ahb_bus)
- *  - g2 (Return address)
- */
-_nomem_find_apb:
-	/* Scan all AHB Buses found for AHB/APB Bridges */
-	mov	%o7, %g2		/* Save return address */
-	mov	%o1, %l4		/* Save APB VENDOR:DEVICE */
-	sll	%o2, 4, %l2		/* APB MST index = 0 */
-	add	%g0, 1, %l3		/* AHB Bus index = 0 */
-.L2_search_next_ahb_bus:
-	call	get_ahb_bridge		/* Get bus %l3 I/O Area */
-	 mov	%l3, %o0
-	cmp	%o0, %g0
-	be	.L2_no_device_found	/* If no more AHB bus is left to be scanned, proceed */
-	 add	%g0, DEV_AHB_SLV, %o5	/* Search for AHB Slave */
-	sethi	%hi(AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_APBMST)), %o1
-	call	_nomem_find_ahb_bus	/* Scan AHB bus %o0 for VENDOR:DEVICE. Index in o3 is decremented */
-	 and	%l2, 0xf, %o2		/* Set APBMST index */
-	cmp	%o0, %g0		/* If no AHB/APB Bridge was not found, scan next AHB Bus */
-	be	.L_no_apb_bridge_found	/* Do next bus */
-	 nop
-
-	/* The AHB/APB Bridge was found.
-         * Search for the requested APB Device on the APB bus using
-	 * find_apb_bus, it will decrement the index.
-         */
-	ld	[%o3 + AMBA_AHB_MBAR0_OFS], %o3
-	sll	%o3, 16, %o0
-	and	%o0, %o3, %o0		/* Address AND Address Mask */
-	sethi	%hi(0xfff00000), %o3
-	and	%o0, %o3, %o0		/* AHB/APB Bridge address */
-
-	srl	%l2, 4, %o2		/* APB DEV Index */
-	call	_nomem_find_apb_bus
-	 mov	%l4, %o1		/* APB VENDOR:DEVICE */
-	cmp	%o0, %g0
-	be	.L_apb_dev_not_found
-	 mov	%g2, %o7		/* Restore return address */
-	/* APB Device found
-	 * o0 1
-	 * o2 Index is decremented to zero
-	 * o3 APB configuration address,
-	 * o4 APB Bridge Configuration address.
-	 */
-	mov	%g0, %o2
-	retl
-	 mov	%l3, %o4
-
-.L_apb_dev_not_found:
-	/* Update APB DEV Index by saving output from find_apb_bus
-	 * (index parameter) into bits [31..4] in L2.
-	 */
-	sll	%o2, 4, %o2
-	and	%l2, 0xf, %l2
-	or	%o2, %l2, %l2
-	/* Try finding the next AHB/APB Bridge on the same AHB bus
-	 * to find more APB devices
-	 */
-	ba	.L2_search_next_ahb_bus	/* Find next AHB/APB bridge */
-	 inc	%l2
-
-.L_no_apb_bridge_found:
-	inc	%l3			/* Next AHB Bus */
-	ba	.L2_search_next_ahb_bus	/* Process next AHB bus */
-	 andn	%l2, 0xf, %l2		/* Start at APB Bridge index 0 at every AHB Bus */
-	/* No device found matching */
-.L2_no_device_found:
-	mov	%g2, %o7		/* Restore return address */
-	srl	%l2, 4, %o2		/* APB DEV Index */
-	retl
-	 mov	%g0, %o0
-
-
-
-/* FUNCTION _nomem_amba_scan_gaisler_ahb2ahb_bridge(unsigned int bridge, int bus)
- *
- * Constraints:
- *   - o1 may not be used
- *   - o0, o2, o3 may be used.
- *
- * Arguments
- *  - o0 PnP Address of Bridge AHB device
- *  - o2 PnP ID of AHB device
- *
- * Results
- *  - o0 Address of new bus PnP area or a 1 if AHB device is no bridge
- *
- * Clobbered
- *   - o0, o2
- *
- */
-_nomem_amba_scan_gaisler_ahb2ahb_bridge:
-	andn	%o2, 0xfff, %o2
-	sethi	%hi(AMBA_PNP_ID(VENDOR_GAISLER,GAISLER_AHB2AHB)), %o3
-	cmp	%o2, %o3
-	beq	.L_is_ahb2ahb_bridge
-	 nop
-
-	retl
-	 add	%g0, 1, %o0
-
-.L_is_ahb2ahb_bridge:
-	/* Found a GAISLER AHB2AHB bridge */
-	retl
-	 ld	[%o0 + AMBA_AHB_CUSTOM1_OFS], %o0 /* Get address of bridge PnP area */
-
-
-/* FUNCTION _nomem_amba_scan_gaisler_l2cache_bridge(unsigned int bridge, int bus)
- *
- * Constraints:
- *   - o1 may not be used
- *   - o0, o2, o3 may be used.
- *
- * Arguments
- *  - o0 PnP Address of Bridge AHB device
- *  - o2 PnP ID of AHB device
- *
- * Results
- *  - o0 Address of new bus PnP area or a 1 if AHB device is no bridge
- *
- * Clobbered
- *   - o0, o2
- *
- */
-_nomem_amba_scan_gaisler_l2cache_bridge:
-	andn	%o2, 0xfff, %o2
-	sethi	%hi(AMBA_PNP_ID(VENDOR_GAISLER,GAISLER_L2CACHE)), %o3
-	cmp	%o2, %o3
-	beq	.L_is_l2cache_bridge
-	 nop
-
-	retl
-	 add	%g0, 1, %o0
-
-.L_is_l2cache_bridge:
-	/* Found a GAISLER l2cache bridge */
-	retl
-	 ld	[%o0 + AMBA_AHB_CUSTOM1_OFS], %o0 /* Get address of bridge PnP area */
-
-
-/* FUNCTION _nomem_amba_scan(unsigned int bridge, int bus)
- *
- * Constraints:
- *  i0-i7, l0 is used by caller
- *  o5-o7 may not be used.
- *
- * Arguments
- *  - o0 Bridge Information: I/O AREA and parent bus
- *  - o1 Bus
- *
- * Results
- *  - o0 Number of AHB bridges found
- *
- * Clobbered
- *  - o0 (Current AHB slave conf address)
- *  - o2 (Used by insert_bridge)
- *  - o3 (Used by insert_bridge)
- *  - l1 (Number of AHB Slaves left to process)
- *  - l2 (Current AHB slave conf address)
- *  - g2 (Return address)
- */
-_nomem_amba_scan:
-	mov	%o7, %g2	/* Save return address */
-	set	16, %l1
-	cmp	%o1, 1
-	be,a	.L2_maxloops_detected
-	 add	%g0, 64, %l1
-.L2_maxloops_detected:
-
-	/* Clear 3-bit parent bus from bridge to get I/O AREA, then or
-	 * (AMBA_CONF_AREA | AMBA_AHB_SLAVE_CONF_AREA) to get first AHB slave
-	 * conf address.
-	 */
-	andn	%o0, 0x7ff, %o0
-	set	(AMBA_CONF_AREA | AMBA_AHB_SLAVE_CONF_AREA), %l2
-	or	%o0, %l2, %l2
-
-	/* Scan AHB Slave area for AHB<->AHB bridges. For each AHB device
-	 * all "bridge drivers" are called, the driver function interface:
-	 *
-	 * Input:
-	 *   - o0 PnP Address of Bridge AHB device
-	 *   - o2 PnP ID of AHB device
-	 * Return values:
-	 *   - o0 Address of new bus PnP area, returning a 1 in o2 means not found
-	 *
-	 * Constraints:
-	 *   - o1 may not be used
-	 *   - o0, o2, o3 may be used.
-	 *
-	 */
-.L_scan_one_ahb_slave:
-	ld	[%l2], %o2
-
-	cmp	%o2, %g0
-	beq	.L_scan_next_ahb_slave
-	 nop
-
-	/* Call the GAISLER AHB2AHB bridge driver */
-	call	_nomem_amba_scan_gaisler_ahb2ahb_bridge
-	 mov	%l2, %o0
-	cmp	%o0, 1
-	bne	.L_found_bridge
-	 ld	[%l2], %o2
-
-	/* Call the GAISLER L2CACHE bridge driver */
-	call	_nomem_amba_scan_gaisler_l2cache_bridge
-	 mov	%l2, %o0
-	cmp	%o0, 1
-	bne	.L_found_bridge
-	 ld	[%l2], %o2
-
-	/* Insert next bridge "driver" function here */
-
-
-	/* The PnP ID did not match a bridge - a new bus was not found ==>
-	 * step to next AHB device */
-	ba	.L_scan_next_ahb_slave
-	 nop
-
-	/* Add Found bus */
-.L_found_bridge:
-	and	%l2, 0x7e0, %o2
-	or	%o2, %o0, %o0		/* Add AHB/AHB Bridge PnP address */
-	call	insert_ahb_bridge	/* Insert Bridge into found buses storage */
-	 or	%o1, %o0, %o0		/* Add parent bus LSB 3-bits */
-
-.L_scan_next_ahb_slave:
-	/* More Slaves to process? */
-	subcc	%l1, 1, %l1
-	bne	.L_scan_one_ahb_slave
-	 add	%l2, AMBA_AHB_CONF_LENGH, %l2
-
-	/* No more AHB devices to process */
-	mov	%g2, %o7	/* Restore return address */
-	retl
-	 nop
-
-/* FUNCTION _nomem_ambapp_find_buses(unsigned int ioarea)
- *
- * Find AMBA AHB buses.
- *
- * Constraints:
- *  i6-i7, l7 is used by caller
- *
- * Arguments
- *  - o0 Bridge Information: I/O AREA and parent bus
- *
- * Results
- *  - o0 Number of AHB bridges found
- *  - i0-i5 initialized
- *
- * Clobbered
- *  - o0 (Current AHB slave conf address)
- *  - o2 (Used by insert_bridge)
- *  - o3 (Used by insert_bridge)
- *  - l0 (Current AHB Bus)
- *  - l1 (Used by nomem_amba_scan)
- *  - l2 (Used by nomem_amba_scan)
- *  - l3 (Used by nomem_amba_scan)
- *  - l4 (Used by nomem_amba_scan)
- *
- *  - g1 (level 1 return address)
- *  - g2 (Used by nomem_amba_scan)
- */
-_nomem_ambapp_find_buses:
-	mov	%o7, %g1	/* Save return address */
-
-	/* Initialize AHB Bus storage */
-	call	init_ahb_bridges
-	 nop
-
-	/* Insert AHB Bus 0 */
-	call	insert_ahb_bridge
-	 nop			/* Argument already prepared by caller */
-
-	/* Scan AHB Bus 0 for AHB Bridges */
-	call	_nomem_amba_scan
-	 add	%g0, 1, %o1
-
-	/* Scan all AHB Buses found for more AHB Bridges */
-	add	%g0, 2, %l0
-.L100_search_next_ahb_bus:
-	call	get_ahb_bridge			/* Get bus %l0 I/O Area */
-	 mov	%l0, %o0
-	cmp	%o0, %g0
-	be	.L100_return			/* If no more AHB bus is left to be scanned, proceed */
-	 nop
-	call	_nomem_amba_scan		/* Scan bus %l0 for AHB Bridges. i0-i7,l0 is used */
-	 mov	%l0, %o1			/* I/O AREA untouched in o0 */
-	ba	.L100_search_next_ahb_bus	/* Do next bus */
-	 add	%l0, 1, %l0
-
-.L100_return:
-	mov	%g1, %o7
-	retl
-	 nop
-
-
-/* FUNCTION _nomem_amba_init(unsigned int ioarea)
- *
- *  Find all AHB buses
- *
- * Constraints:
- *  i6, i7, o6, o7, l7, l6, g3, g4, g5, g6, g7 is used by caller
- *
- * Arguments
- *  - o0 Bridge Information: I/O AREA and parent bus
- *
- * Results
- *  - o0 Number of AHB bridges found
- *
- * Clobbered
- *  - l0, l1, l2, l3, l4, g1, g2 (used by _nomem_ambapp_find_buses)
- *  - o0, o1, o2, o3 (Used as arguments)
- *  - o5 (return address)
- *  - g1 (level 1 return address)
- *  - g2 (level 2 return address)
- */
-_nomem_amba_init:
-	mov	%o7, %o5	/* Save return address, o5 not used */
-
-	/* Scan for buses, it will init i0-i5 */
-	call	_nomem_ambapp_find_buses
-	 nop
-
-	mov	%o5, %o7
-	retl
-	 nop
-
-/* Call tree and their return address register
- *
- *_nomem_amba_scan           (g1)
- * -> init_ahb_bridges       (o7)
- * -> insert_ahb_bridge      (o7)
- * -> _nomem_amba_scan       (g2)
- *    -> insert_ahb_bridge   (o7)
- * -> get_ahb_bridge         (o7)
- *
- *
- * -> _nomem_find_apb        (g2)
- *    -> get_ahb_bridge      (o7)
- *    -> _nomem_find_ahb_bus (o7)
- *    -> _nomem_find_apb_bus (o7)
- * -> _nomem_find_ahb        (g2)
- *    -> get_ahb_bridge      (o7)
- *    -> _nomem_find_ahb_bus (o7)
- * -> mem_handler.func()     (o7)
- *
- */
diff --git a/arch/sparc/cpu/leon3/ambapp_low_c.S b/arch/sparc/cpu/leon3/ambapp_low_c.S
deleted file mode 100644
index 42288fa..0000000
--- a/arch/sparc/cpu/leon3/ambapp_low_c.S
+++ /dev/null
@@ -1,113 +0,0 @@
-/* C-interface for AMBA PnP scanning functions implemented in
- * ambapp_low.S. At the point the memory and stack can be
- * used.
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-	.seg	"text"
-	.extern	_nomem_ambapp_find_buses
-	.extern	_nomem_find_apb
-	.extern	_nomem_find_ahb
-
-	.globl	ambapp_find_buses
-	.globl	ambapp_find_apb
-	.globl	ambapp_find_ahb
-
-
-/* C-interface for _nomem_ambapp_find_buses used when memory is available.
- */
-ambapp_find_buses:
-	save	%sp, -104, %sp
-	mov	%i1, %l7	/* Save second argument */
-	call _nomem_ambapp_find_buses
-	 mov	%i0, %o0
-
-	/* Store result */
-	st	%g0, [%l7+0x00]
-	st	%i0, [%l7+0x04]
-	st	%i1, [%l7+0x08]
-	st	%i2, [%l7+0x0c]
-	st	%i3, [%l7+0x10]
-	st	%i4, [%l7+0x14]
-	st	%i5, [%l7+0x18]
-
-	ret
-	 restore
-
-/* C-interface for _nomem_find_apb used when memory is available.
- *
- * void ambapp_find_apb(
- *	struct ambapp_bus *abus,
- *	unsigned int dev_vend,
- *	int index,
- *	struct ambapp_find_apb_info *result
- *	);
- *
- */
-ambapp_find_apb:
-	save	%sp, -104, %sp
-
-	mov	%i3, %l7	/* Save second argument */
-	mov	%i1, %o1
-	mov	%i2, %o2
-
-	/* Initialize buses available in system */
-	ld	[%i0+0x08], %i1
-	ld	[%i0+0x0c], %i2
-	ld	[%i0+0x10], %i3
-	ld	[%i0+0x14], %i4
-	ld	[%i0+0x18], %i5
-
-	call _nomem_find_apb
-	 ld	[%i0+0x04], %i0
-
-	st	%o2, [%l7+0x08]	/* Decremented Index */
-	st	%o3, [%l7]	/* PnP configuration address of APB Device */
-	st	%o4, [%l7+0x04]	/* AHB Bus Index of AHB/APB bridge and APB Device */
-	mov	%o0, %i0
-	ret
-	 restore
-
-/* C-interface for _nomem_find_ahb used when memory is available.
- *
- * void ambapp_find_ahb(
- *	struct ambapp_bus *abus,
- *	unsigned int dev_vend,
- *	int index,
- *	int type,
- *	struct ambapp_find_ahb_info *result
- *	);
- *
- */
-ambapp_find_ahb:
-	save	%sp, -104, %sp
-
-	mov	%i4, %l7	/* Save second argument */
-	clr	%o0
-	mov	%i1, %o1
-	mov	%i2, %o2
-	clr	%o3
-	clr	%o4
-	mov	%i3, %o5
-
-	/* Initialize buses available in system */
-	ld	[%i0+0x08], %i1
-	ld	[%i0+0x0c], %i2
-	ld	[%i0+0x10], %i3
-	ld	[%i0+0x14], %i4
-	ld	[%i0+0x18], %i5
-
-	call _nomem_find_ahb
-	 ld	[%i0+0x04], %i0
-
-	st	%o2, [%l7+0x08]	/* Decremented Index */
-	st	%o3, [%l7]	/* PnP configuration address of AHB Device */
-	st	%o4, [%l7+0x04]	/* AHB Bus Index of AHB Device */
-	mov	%o0, %i0
-	ret
-	 restore
diff --git a/arch/sparc/cpu/leon3/cpu.c b/arch/sparc/cpu/leon3/cpu.c
deleted file mode 100644
index 149e5c6..0000000
--- a/arch/sparc/cpu/leon3/cpu.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* CPU specific code for the LEON3 CPU
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <netdev.h>
-
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <ambapp.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void _reset_reloc(void);
-
-int leon_cpu_cnt = 1;
-int leon_ver = 3;
-unsigned int leon_cpu_freq = CONFIG_SYS_CLK_FREQ;
-
-int cpu_freq(void)
-{
-	ambapp_ahbdev dev;
-
-	if (leon_ver == 3) {
-		ambapp_ahbmst_find(&ambapp_plb, VENDOR_GAISLER,
-			GAISLER_LEON3, 0, &dev);
-	} else {
-		ambapp_ahbmst_find(&ambapp_plb, VENDOR_GAISLER,
-			GAISLER_LEON4, 0, &dev);
-	}
-
-	leon_cpu_freq = ambapp_bus_freq(&ambapp_plb, dev.ahb_bus_index);
-
-	return 0;
-}
-
-int checkcpu(void)
-{
-	int cnt;
-	char str[4];
-
-	/* check LEON version here */
-	cnt = ambapp_ahbmst_count(&ambapp_plb, VENDOR_GAISLER, GAISLER_LEON3);
-	if (cnt <= 0) {
-		cnt = ambapp_ahbmst_count(&ambapp_plb, VENDOR_GAISLER,
-			GAISLER_LEON4);
-		if (cnt > 0)
-			leon_ver = 4;
-	}
-
-	cpu_freq();
-
-	str[0] = '\0';
-	if (cnt > 1) {
-		leon_cpu_cnt = cnt;
-		str[0] = '0' + cnt;
-		str[1] = 'x';
-		str[2] = '\0';
-	}
-	printf("CPU: %sLEON%d @ %dMHz\n", str, leon_ver,
-		leon_cpu_freq / 1000000);
-
-	return 0;
-}
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-
-int print_cpuinfo(void)
-{
-	printf("CPU:   LEON3\n");
-	return 0;
-}
-
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-void cpu_reset(void)
-{
-	/* Interrupts off */
-	disable_interrupts();
-
-	/* jump to restart in flash */
-	_reset_reloc();
-}
-
-int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	cpu_reset();
-
-	return 1;
-
-}
-
-u64 flash_read64(void *addr)
-{
-	return __raw_readq(addr);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_GRETH
-int cpu_eth_init(bd_t *bis)
-{
-	return greth_initialize(bis);
-}
-#endif
diff --git a/arch/sparc/cpu/leon3/cpu_init.c b/arch/sparc/cpu/leon3/cpu_init.c
deleted file mode 100644
index f25388c..0000000
--- a/arch/sparc/cpu/leon3/cpu_init.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* Initializes CPU and basic hardware such as memory
- * controllers, IRQ controller and system timer 0.
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/asi.h>
-#include <asm/leon.h>
-#include <asm/io.h>
-#include <ambapp.h>
-#include <grlib/irqmp.h>
-#include <grlib/gptimer.h>
-#include <debug_uart.h>
-
-#include <config.h>
-
-/* Default Plug&Play I/O area */
-#ifndef CONFIG_AMBAPP_IOAREA
-#define CONFIG_AMBAPP_IOAREA AMBA_DEFAULT_IOAREA
-#endif
-
-/* Select which TIMER that will become the time base */
-#ifndef CONFIG_SYS_GRLIB_GPTIMER_INDEX
-#define CONFIG_SYS_GRLIB_GPTIMER_INDEX 0
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-ambapp_dev_irqmp *irqmp = NULL;
-
-/*
- * Breath some life into the CPU...
- *
- * Run from FLASH/PROM:
- *  - until memory controller is set up, only registers available
- *  - memory controller has already been setup up, stack can be used
- *  - no global variables available for writing
- *  - constants available
- */
-void cpu_init_f(void)
-{
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
-}
-
-/* If cache snooping is available in hardware the result will be set
- * to 0x800000, otherwise 0.
- */
-static unsigned int snoop_detect(void)
-{
-	unsigned int result;
-	asm("lda [%%g0] 2, %0" : "=r"(result));
-	return result & 0x00800000;
-}
-
-int arch_cpu_init(void)
-{
-	ambapp_apbdev apbdev;
-	int index;
-
-	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
-	gd->bus_clk = CONFIG_SYS_CLK_FREQ;
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
-	gd->arch.snooping_available = snoop_detect();
-
-	/* Initialize the AMBA Plug & Play bus structure, the bus
-	 * structure represents the AMBA bus that the CPU is located at.
-	 */
-	ambapp_bus_init(CONFIG_AMBAPP_IOAREA, CONFIG_SYS_CLK_FREQ, &ambapp_plb);
-
-	/* Initialize/clear all the timers in the system.
-	 */
-	for (index = 0; ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER,
-		GAISLER_GPTIMER, index, &apbdev) == 1; index++) {
-		ambapp_dev_gptimer *timer;
-		unsigned int bus_freq;
-		int i, ntimers;
-
-		timer = (ambapp_dev_gptimer *)apbdev.address;
-
-		/* Different buses may have different frequency, the
-		 * frequency of the bus tell in which frequency the timer
-		 * prescaler operates.
-		 */
-		bus_freq = ambapp_bus_freq(&ambapp_plb, apbdev.ahb_bus_index);
-
-		/* Initialize prescaler common to all timers to 1MHz */
-		timer->scalar = timer->scalar_reload =
-			(((bus_freq / 1000) + 500) / 1000) - 1;
-
-		/* Clear all timers */
-		ntimers = timer->config & 0x7;
-		for (i = 0; i < ntimers; i++) {
-			timer->e[i].ctrl = GPTIMER_CTRL_IP;
-			timer->e[i].rld = 0;
-			timer->e[i].ctrl = GPTIMER_CTRL_LD;
-		}
-	}
-
-	return 0;
-}
-
-/*
- * initialize higher level parts of CPU like time base and timers
- */
-int cpu_init_r(void)
-{
-	ambapp_apbdev apbdev;
-	int cpu;
-
-	/*
-	 * Find AMBA APB IRQMP Controller,
-	 */
-	if (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER,
-		GAISLER_IRQMP, 0, &apbdev) != 1) {
-		panic("%s: IRQ controller not found\n", __func__);
-		return -1;
-	}
-	irqmp = (ambapp_dev_irqmp *)apbdev.address;
-
-	/* initialize the IRQMP */
-	irqmp->ilevel = 0xf;	/* all IRQ off */
-	irqmp->iforce = 0;
-	irqmp->ipend = 0;
-	irqmp->iclear = 0xfffe;	/* clear all old pending interrupts */
-	for (cpu = 0; cpu < 16; cpu++) {
-		/* mask and clear force for all IRQs on CPU[N] */
-		irqmp->cpu_mask[cpu] = 0;
-		irqmp->cpu_force[cpu] = 0;
-	}
-
-	return 0;
-}
-
-			;
-int timer_init(void)
-{
-	ambapp_dev_gptimer_element *tmr;
-	ambapp_dev_gptimer *gptimer;
-	ambapp_apbdev apbdev;
-	unsigned bus_freq;
-
-	if (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER, GAISLER_GPTIMER,
-		CONFIG_SYS_GRLIB_GPTIMER_INDEX, &apbdev) != 1) {
-		panic("%s: gptimer not found!\n", __func__);
-		return -1;
-	}
-
-	gptimer = (ambapp_dev_gptimer *) apbdev.address;
-
-	/* Different buses may have different frequency, the
-	 * frequency of the bus tell in which frequency the timer
-	 * prescaler operates.
-	 */
-	bus_freq = ambapp_bus_freq(&ambapp_plb, apbdev.ahb_bus_index);
-
-	/* initialize prescaler common to all timers to 1MHz */
-	gptimer->scalar = gptimer->scalar_reload =
-		(((bus_freq / 1000) + 500) / 1000) - 1;
-
-	tmr = (ambapp_dev_gptimer_element *)&gptimer->e[0];
-
-	tmr->val = 0;
-	tmr->rld = ~0;
-	tmr->ctrl = GPTIMER_CTRL_EN | GPTIMER_CTRL_RS | GPTIMER_CTRL_LD;
-
-	CONFIG_SYS_TIMER_COUNTER = (void *)&tmr->val;
-	return 0;
-}
diff --git a/arch/sparc/cpu/leon3/interrupts.c b/arch/sparc/cpu/leon3/interrupts.c
deleted file mode 100644
index 00c3288..0000000
--- a/arch/sparc/cpu/leon3/interrupts.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
- *
- * (C) Copyright 2006
- * Detlev Zundel, DENX Software Engineering, dzu@denx.de
- *
- * (C) Copyright -2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/stack.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <asm/irq.h>
-
-#include <asm/leon.h>
-#include <ambapp.h>
-#include <grlib/irqmp.h>
-#include <grlib/gptimer.h>
-
-/* 15 normal irqs and a non maskable interrupt */
-#define NR_IRQS 15
-
-struct irq_action {
-	interrupt_handler_t *handler;
-	void *arg;
-	unsigned int count;
-};
-
-extern ambapp_dev_irqmp *irqmp;
-extern ambapp_dev_gptimer *gptimer;
-
-static struct irq_action irq_handlers[NR_IRQS] = { {0}, };
-static int spurious_irq_cnt = 0;
-static int spurious_irq = 0;
-
-static inline unsigned int irqmp_get_irqmask(unsigned int irq)
-{
-	if ((irq < 0) || (irq >= NR_IRQS)) {
-		return 0;
-	} else {
-		return (1 << irq);
-	}
-
-}
-
-static void leon3_ic_disable(unsigned int irq)
-{
-	unsigned int mask, pil;
-	if (!irqmp)
-		return;
-
-	pil = intLock();
-
-	/* get mask of interrupt */
-	mask = irqmp_get_irqmask(irq);
-
-	/* set int level */
-	irqmp->cpu_mask[0] = SPARC_NOCACHE_READ(&irqmp->cpu_mask[0]) & (~mask);
-
-	intUnlock(pil);
-}
-
-static void leon3_ic_enable(unsigned int irq)
-{
-	unsigned int mask, pil;
-	if (!irqmp)
-		return;
-
-	pil = intLock();
-
-	/* get mask of interrupt */
-	mask = irqmp_get_irqmask(irq);
-
-	/* set int level */
-	irqmp->cpu_mask[0] = SPARC_NOCACHE_READ(&irqmp->cpu_mask[0]) | mask;
-
-	intUnlock(pil);
-
-}
-
-void handler_irq(int irq, struct pt_regs *regs)
-{
-	if (irq_handlers[irq].handler) {
-		if (((unsigned int)irq_handlers[irq].handler > CONFIG_SYS_RAM_END) ||
-		    ((unsigned int)irq_handlers[irq].handler < CONFIG_SYS_RAM_BASE)
-		    ) {
-			printf("handler_irq: bad handler: %x, irq number %d\n",
-			       (unsigned int)irq_handlers[irq].handler, irq);
-			return;
-		}
-		irq_handlers[irq].handler(irq_handlers[irq].arg);
-		irq_handlers[irq].count++;
-	} else {
-		spurious_irq_cnt++;
-		spurious_irq = irq;
-	}
-}
-
-void leon3_force_int(int irq)
-{
-	if (!irqmp || (irq >= NR_IRQS) || (irq < 0))
-		return;
-	printf("Forcing interrupt %d\n", irq);
-
-	irqmp->iforce = SPARC_NOCACHE_READ(&irqmp->iforce) | (1 << irq);
-}
-
-/****************************************************************************/
-
-int interrupt_init_cpu(void)
-{
-
-	return (0);
-}
-
-/****************************************************************************/
-
-/*
- * Install and free a interrupt handler.
- */
-
-void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
-{
-	if (irq < 0 || irq >= NR_IRQS) {
-		printf("irq_install_handler: bad irq number %d\n", irq);
-		return;
-	}
-
-	if (irq_handlers[irq].handler != NULL)
-		printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
-		       (ulong) handler, (ulong) irq_handlers[irq].handler);
-
-	if (((unsigned int)handler > CONFIG_SYS_RAM_END) ||
-	    ((unsigned int)handler < CONFIG_SYS_RAM_BASE)
-	    ) {
-		printf("irq_install_handler: bad handler: %x, irq number %d\n",
-		       (unsigned int)handler, irq);
-		return;
-	}
-	irq_handlers[irq].handler = handler;
-	irq_handlers[irq].arg = arg;
-
-	/* enable irq on IRQMP hardware */
-	leon3_ic_enable(irq);
-
-}
-
-void irq_free_handler(int irq)
-{
-	if (irq < 0 || irq >= NR_IRQS) {
-		printf("irq_free_handler: bad irq number %d\n", irq);
-		return;
-	}
-
-	/* disable irq on IRQMP hardware */
-	leon3_ic_disable(irq);
-
-	irq_handlers[irq].handler = NULL;
-	irq_handlers[irq].arg = NULL;
-}
-
-/****************************************************************************/
-
-#if defined(CONFIG_CMD_IRQ)
-void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
-{
-	int irq;
-	unsigned int pil = get_pil();
-	printf("PIL level: %u\n\r", pil);
-	printf("Spurious IRQ: %u, last unknown IRQ: %d\n",
-	       spurious_irq_cnt, spurious_irq);
-
-	puts("\nInterrupt-Information:\n" "Nr  Routine   Arg       Count\n");
-
-	for (irq = 0; irq < NR_IRQS; irq++) {
-		if (irq_handlers[irq].handler != NULL) {
-			printf("%02d  %p  %p  %d\n", irq,
-			       irq_handlers[irq].handler,
-			       irq_handlers[irq].arg,
-			       irq_handlers[irq].count);
-		}
-	}
-}
-#endif
diff --git a/arch/sparc/cpu/leon3/memcfg.c b/arch/sparc/cpu/leon3/memcfg.c
deleted file mode 100644
index b9eda44..0000000
--- a/arch/sparc/cpu/leon3/memcfg.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/* GRLIB Memory controller setup. The register values are used
- * from the associated low level assembler routine implemented
- * in memcfg_low.S.
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <ambapp.h>
-#include "memcfg.h"
-#include <config.h>
-
-#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL1
-struct mctrl_setup esa_mctrl1_cfg = {
-	.reg_mask = 0x7,
-	.regs = {
-		{
-			.mask = 0x00000300,
-			.value = CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1,
-		},
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2,
-		},
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3,
-		},
-	}
-};
-#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL2
-struct mctrl_setup esa_mctrl2_cfg = {
-	.reg_mask = 0x7,
-	.regs = {
-		{
-			.mask = 0x00000300,
-			.value = CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG1,
-		},
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG2,
-		},
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG3,
-		},
-	}
-};
-#endif
-#endif
-
-#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
-struct mctrl_setup gaisler_ftmctrl1_cfg = {
-	.reg_mask = 0x7,
-	.regs = {
-		{
-			.mask = 0x00000300,
-			.value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1,
-		},
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2,
-		},
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3,
-		},
-	}
-};
-#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2
-struct mctrl_setup gaisler_ftmctrl2_cfg = {
-	.reg_mask = 0x7,
-	.regs = {
-		{
-			.mask = 0x00000300,
-			.value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG1,
-		},
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG2,
-		},
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG3,
-		},
-	}
-};
-#endif
-#endif
-
-#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
-struct mctrl_setup gaisler_sdctrl1_cfg = {
-	.reg_mask = 0x1,
-	.regs = {
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_GAISLER_SDCTRL1_CTRL,
-		},
-	}
-};
-#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL2
-struct mctrl_setup gaisler_sdctrl2_cfg = {
-	.reg_mask = 0x1,
-	.regs = {
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_GAISLER_SDCTRL2_CTRL,
-		},
-	}
-};
-#endif
-#endif
-
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
-struct ahbmctrl_setup gaisler_ddr2spa1_cfg = {
-	.ahb_mbar_no = 1,
-	.reg_mask = 0xd,
-	.regs = {
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG1,
-		},
-		{ 0x00000000, 0},
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG3,
-		},
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG4,
-		},
-	}
-};
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2
-struct ahbmctrl_setup gaisler_ddr2spa2_cfg = {
-	.ahb_mbar_no = 1,
-	.reg_mask = 0xd,
-	.regs = {
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG1,
-		},
-		{ 0x00000000, 0},
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG3,
-		},
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG4,
-		},
-	}
-};
-#endif
-#endif
-
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
-struct ahbmctrl_setup gaisler_ddrspa1_cfg = {
-	.ahb_mbar_no = 1,
-	.reg_mask = 0x1,
-	.regs = {
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL,
-		},
-	}
-};
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA2
-struct ahbmctrl_setup gaisler_ddrspa2_cfg = {
-	.ahb_mbar_no = 1,
-	.reg_mask = 0x1,
-	.regs = {
-		{
-			.mask = 0x00000000,
-			.value = CONFIG_SYS_GRLIB_GAISLER_DDRSPA2_CTRL,
-		},
-	}
-};
-#endif
-#endif
-
-struct grlib_mctrl_handler grlib_mctrl_handlers[] = {
-/* ESA MCTRL (PROM/FLASH/IO/SRAM/SDRAM) */
-#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL1
-	{DEV_APB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_ESA, ESA_MCTRL),
-	_nomem_mctrl_init, (void *)&esa_mctrl1_cfg},
-#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL2
-	{DEV_APB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_ESA, ESA_MCTRL),
-	_nomem_mctrl_init, (void *)&esa_mctrl2_cfg},
-#endif
-#endif
-
-/* GAISLER Fault Tolerant Memory controller (PROM/FLASH/IO/SRAM/SDRAM) */
-#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
-	{DEV_APB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_FTMCTRL),
-	_nomem_mctrl_init, (void *)&gaisler_ftmctrl1_cfg},
-#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2
-	{DEV_APB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_FTMCTRL),
-	_nomem_mctrl_init, (void *)&gaisler_ftmctrl2_cfg},
-#endif
-#endif
-
-/* GAISLER SDRAM-only Memory controller (SDRAM) */
-#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
-	{DEV_APB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_SDCTRL),
-	_nomem_mctrl_init, (void *)&gaisler_sdctrl1_cfg},
-#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL2
-	{DEV_APB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_SDCTRL),
-	_nomem_mctrl_init, (void *)&gaisler_sdctrl2_cfg},
-#endif
-#endif
-
-/* GAISLER DDR Memory controller (DDR) */
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
-	{DEV_AHB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDRSP),
-	_nomem_ahbmctrl_init, (void *)&gaisler_ddrspa1_cfg},
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA2
-	{DEV_AHB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDRSP),
-	_nomem_ahbmctrl_init, (void *)&gaisler_ddrspa2_cfg},
-#endif
-#endif
-
-/* GAISLER DDR2 Memory controller (DDR2) */
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
-	{DEV_AHB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDR2SP),
-	_nomem_ahbmctrl_init, (void *)&gaisler_ddr2spa1_cfg},
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2
-	{DEV_AHB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDR2SP),
-	_nomem_ahbmctrl_init, (void *)&gaisler_ddr2spa2_cfg},
-#endif
-#endif
-
-	/* Mark end */
-	MH_END
-};
diff --git a/arch/sparc/cpu/leon3/memcfg.h b/arch/sparc/cpu/leon3/memcfg.h
deleted file mode 100644
index a524896..0000000
--- a/arch/sparc/cpu/leon3/memcfg.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* GRLIB Memory controller setup structures
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MEMCFG_H__
-#define __MEMCFG_H__
-
-/*********** Low Level Memory Controller Initalization ***********/
-
-#ifndef __ASSEMBLER__
-
-struct grlib_mctrl_handler;
-
-typedef void (*mctrl_handler_t)(
-	struct grlib_mctrl_handler *dev,
-	void *conf,
-	unsigned int ioarea
-	);
-
-/* Memory Controller Handler Structure */
-struct grlib_mctrl_handler {
-	unsigned char	type;		/* 0x00. MASK: AHB MST&SLV, APB SLV */
-	char		index;		/* 0x01. Unit number, 0, 1, 2... */
-	char		unused[2];	/* 0x02 */
-	unsigned int	ven_dev;	/* 0x04. Device and Vendor */
-	mctrl_handler_t	func;		/* 0x08. Memory Controller Handler */
-	void		*priv;		/* 0x0c. Optional private data, ptr to
-					 * info how to set up controller */
-};
-
-extern struct grlib_mctrl_handler grlib_mctrl_handlers[];
-
-#endif
-
-#define MH_STRUCT_SIZE		(4*4)
-#define MH_TYPE			0x00
-#define MH_INDEX		0x01
-#define MH_VENDOR_DEVICE	0x04
-#define MH_FUNC			0x08
-#define MH_PRIV			0x0c
-
-#define MH_TYPE_NONE	DEV_NONE
-#define MH_TYPE_AHB_MST	DEV_AHB_MST
-#define MH_TYPE_AHB_SLV	DEV_AHB_SLV
-#define MH_TYPE_APB_SLV	DEV_APB_SLV
-
-#define MH_UNUSED	{0, 0}
-#define MH_END		{DEV_NONE, 0, MH_UNUSED, AMBA_PNP_ID(0, 0), 0, 0}
-
-/*********** Low Level Memory Controller Initalization Handlers ***********/
-
-#ifndef __ASSEMBLER__
-extern void _nomem_mctrl_init(
-	struct grlib_mctrl_handler *dev,
-	void *conf,
-	unsigned int ioarea_apbmst);
-
-struct mctrl_setup {
-	unsigned int reg_mask;		/* Which registers to write */
-	struct {
-		unsigned int mask;	/* Mask used keep reg bits unchanged */
-		unsigned int value;	/* Value written to register */
-	} regs[8];
-};
-
-extern void _nomem_ahbmctrl_init(
-	struct grlib_mctrl_handler *dev,
-	void *conf,
-	unsigned int ioarea_apbmst);
-
-struct ahbmctrl_setup {
-	int ahb_mbar_no;		/* MBAR to get register address from */
-	unsigned int reg_mask;		/* Which registers to write */
-	struct {
-		unsigned int mask;	/* Mask used keep reg bits unchanged */
-		unsigned int value;	/* Value written to register */
-	} regs[8];
-};
-#endif
-
-/* mctrl_setup data structure defines */
-#define NREGS_OFS 0
-#define REGS_OFS 0x4
-#define REGS_SIZE 8
-
-#endif
diff --git a/arch/sparc/cpu/leon3/memcfg_low.S b/arch/sparc/cpu/leon3/memcfg_low.S
deleted file mode 100644
index 84a81a9..0000000
--- a/arch/sparc/cpu/leon3/memcfg_low.S
+++ /dev/null
@@ -1,253 +0,0 @@
-/* This is the memory initialization functions, the function
- * implemented below initializes each memory controller
- * found and specified by the input grlib_mctrl_handler structure.
- *
- * After the memory controllers have been initialized the stack
- * can be used.
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <ambapp.h>
-#include "memcfg.h"
-#include <config.h>
-
-	.seg	"text"
-	.globl	_nomem_memory_ctrl_init
-	.globl	_nomem_mctrl_init, _nomem_ahbmctrl_init
-	.extern	_nomem_find_apb
-	.extern	_nomem_find_ahb
-
-
-/* FUNCTION
- *   _nomem_memory_controller_init(struct grlib_mctrl_handler *mem_handlers)
- *
- * Initialize AMBA devices, _nomem_amba_init() has prepared i0-i5
- * with the AHB buses on the system.
- *
- * For each entry in mem_handlers find the VENDOR:DEVICE and handle it
- * by calling the handler function pointer.
- *
- * Constraints:
- *  i6, i7, o6, l7, l6, g3, g4, g5, g6, g7 is used by caller
- *  o7 is return address
- *  l5 reserved for this function for future use.
- *
- * Arguments
- *  - o0 Pointer to memory handler array
- *
- * Results
- *  - o0 Number of memory controllers found
- *
- * Clobbered
- *  - o0 (Current AHB slave conf address)
- *  - l0 (mem handler entry address)
- *  - l1 (Return value, number of memory controllers found)
- *  - o7 (function pointer)
- *  - l0, l1, l2, l3, l4, g1, g2 (used by _nomem_ambapp_find_buses)
- *  - o0, o1, o2, o3, o4, o5 (Used as arguments)
- *
- *  - g1 ( level 1 return address)
- *  - g2 ( level 2 return address)
- */
-
-_nomem_memory_ctrl_init:
-	/* At this point all AHB buses has been found and the I/O Areas of
-	 * all AHB buses is stored in the i0-i5 registers. Max 6 buses. Next,
-	 * memory controllers are found by searching all buses for matching
-	 * VENDOR:DEVICE. The VENDOR:DEVICE to search for are taken from the
-	 * mem_handlers array. For each match the function pointer stored in
-	 * the mem_handler entry is called to handle the hardware setup.
-	 */
-	mov	%o7, %g1	/* Save return address */
-	mov	%o0, %l0
-	mov	%g0, %l1	/* The return value */
-
-.L_do_one_mem_handler:
-	ld	[%l0 + MH_FUNC], %o7
-	cmp	%o7, %g0
-	be	.L_all_mctrl_handled
-	 nop
-
-	/*** Scan for memory controller ***/
-
-	/* Set up argments, o5 not used by _nomem_find_apb */
-	ldub	[%l0 + MH_TYPE], %o5
-	clr	%o4
-	clr	%o3
-	ldub	[%l0 + MH_INDEX], %o2
-	ld	[%l0 + MH_VENDOR_DEVICE], %o1
-
-	/* An empty config? */
-	cmp	%o5, DEV_NONE
-	beq	.L_all_mctrl_next
-
-	/* Select function (APB or AHB) */
-	 cmp	%o5, DEV_APB_SLV
-	bne	.L_find_ahb_memctrl
-	 clr	%o0
-.L_find_apb_memctrl:
-	call	_nomem_find_apb			/* Scan for APB slave device */
-	 nop
-
-	/* o3 = iobar address
-	 * o4 = AHB Bus index
-	 *
-	 * REG ADR = ((iobar >> 12) & (iobar << 4) & 0xfff00) | "APB Base"
-	 */
-	ld	[%o3 + AMBA_APB_IOBAR_OFS], %o5
-	srl	%o5, 12, %o2
-	sll	%o5, 4, %o5
-	and	%o2, %o5, %o5
-	set	0xfff00, %o2
-	and	%o2, %o5, %o5
-	sethi	%hi(0xfff00000), %o2
-	and	%o3, %o2, %o2
-	or	%o5, %o2, %o5	/* Register base address */
-
-	ba	.L_call_one_mem_handler
-	 nop
-
-.L_find_ahb_memctrl:
-	call	_nomem_find_ahb		/* Scan for AHB Slave or Master.
-					 * o5 determine type. */
-	 nop
-	clr	%o5
-
-	/* Call the handler function if the hardware was found
-	 *
-	 * o0 = mem_handler
-	 * o1 = Configuration address
-	 * o2 = AHB Bus index
-	 * o3 = APB Base register (if APB Slave)
-	 *
-	 * Constraints:
-	 * i0-i7, l0, l1, l5, g1, g3-g7 may no be used.
-	 */
-.L_call_one_mem_handler:
-	cmp	%o0, %g0
-	be	.L_all_mctrl_next
-	 mov	%l0, %o0			/* Mem handler pointer */
-	mov	%o3, %o1			/* AMBA PnP Configuration address */
-	mov	%o4, %o2			/* AHB Bus index */
-	ld	[%l0 + MH_FUNC], %o7	/* Get Function pointer */
-	call	%o7
-	 mov	%o5, %o3			/* APB Register Base Address */
-
-	inc	%l1				/* Number of Memory controllers
-						 * handled. */
-
-	/* Do next entry in mem_handlers */
-.L_all_mctrl_next:
-	ba	.L_do_one_mem_handler
-	 add	%l0, MH_STRUCT_SIZE, %l0
-
-.L_all_mctrl_handled:
-	mov	%g1, %o7	/* Restore return address */
-	retl
-	 mov	%l1, %o0
-
-
-
-/* Generic Memory controller initialization routine (APB Registers)
- *
- * o0 = mem_handler structure pointer
- * o1 = Configuration address
- * o2 = AHB Bus index
- * o3 = APB Base register
- *
- * Clobbered
- *  o0-o4
- */
-_nomem_mctrl_init:
-	ld	[%o0 + MH_PRIV], %o0	/* Get Private structure */
-	ld	[%o0], %o1		/* Get Reg Mask */
-	and	%o1, 0xff, %o1
-	add	%o0, REGS_OFS, %o0	/* Point to first reg */
-.L_do_one_reg:
-	andcc	%o1, 0x1, %g0
-	beq	.L_do_next_reg
-	 ld	[%o0], %o2
-	ld	[%o3], %o4
-	and	%o4, %o2, %o4
-	ld	[%o0 + 4], %o2
-	or	%o4, %o2, %o4
-	st	%o4, [%o3]
-
-.L_do_next_reg:
-	add	%o0, REGS_SIZE, %o0
-	add	%o3, 4, %o3
-	srl	%o1, 1, %o1
-	cmp	%o1, 0
-	bne	.L_do_one_reg
-	 nop
-
-	/* No more registers to write */
-	retl
-	 nop
-
-
-
-/* Generic Memory controller initialization routine (AHB Registers)
- *
- * o0 = mem_handler structure pointer
- * o1 = Configuration address of memory controller
- * o2 = AHB Bus index
- *
- * Clobbered
- *  o0-o5
- */
-_nomem_ahbmctrl_init:
-	ld	[%o0 + MH_PRIV], %o0		/* Get Private structure */
-
-	/* Get index of AHB MBAR to get registers from */
-	ld	[%o0], %o5
-	add	%o0, 4, %o0
-
-	/* Get Address of MBAR in PnP info */
-	add	%o5, 4, %o5
-	sll	%o5, 2, %o5
-	add	%o5, %o1, %o5			/* Address of MBAR */
-
-	/* Get Address of registers from PnP information
-	 * Address is in AHB I/O format, i.e. relative to bus
-	 *
-	 * ADR = (iobar & (iobar << 16) & 0xfff00000)
-	 * IOADR = (ADR >> 12) | "APB Base"
-	 */
-	ld	[%o5], %o5
-	sll	%o5, 16, %o4
-	and	%o5, %o4, %o5
-	sethi	%hi(0xfff00000), %o4
-	and	%o5, %o4, %o5			/* ADR */
-	and	%o4, %o1, %o4
-	srl	%o5, 12, %o5
-	or	%o5, %o4, %o3			/* IOADR in o3 */
-
-	ld	[%o0], %o1			/* Get Reg Mask */
-	and	%o1, 0xff, %o1
-	add	%o0, REGS_OFS, %o0		/* Point to first reg */
-.L_do_one_ahbreg:
-	andcc	%o1, 0x1, %g0
-	beq	.L_do_next_reg
-	 ld	[%o0], %o2
-	ld	[%o3], %o4
-	and	%o4, %o2, %o4
-	ld	[%o0 + 4], %o2
-	or	%o4, %o2, %o4
-	st	%o4, [%o3]
-
-.L_do_next_ahbreg:
-	add	%o0, REGS_SIZE, %o0
-	add	%o3, 4, %o3
-	srl	%o1, 1, %o1
-	cmp	%o1, 0
-	bne	.L_do_one_reg
-	 nop
-
-	/* No more registers to write */
-	retl
-	 nop
diff --git a/arch/sparc/cpu/leon3/prom.c b/arch/sparc/cpu/leon3/prom.c
deleted file mode 100644
index 1f185b7..0000000
--- a/arch/sparc/cpu/leon3/prom.c
+++ /dev/null
@@ -1,1067 +0,0 @@
-/* prom.c - emulates a sparc v0 PROM for the linux kernel.
- *
- * Copyright (C) 2003 Konrad Eisele <eiselekd@web.de>
- * Copyright (C) 2004 Stefan Holst <mail@s-holst.de>
- * Copyright (C) 2007 Daniel Hellstrom <daniel@gaisler.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/prom.h>
-#include <asm/machines.h>
-#include <asm/srmmu.h>
-#include <asm/processor.h>
-#include <asm/irq.h>
-#include <asm/leon.h>
-#include <ambapp.h>
-#include <grlib/apbuart.h>
-#include <grlib/irqmp.h>
-#include <grlib/gptimer.h>
-
-#include <config.h>
-/*
-#define PRINT_ROM_VEC
-*/
-extern struct linux_romvec *kernel_arg_promvec;
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define PROM_PGT __attribute__ ((__section__ (".prom.pgt")))
-#define PROM_TEXT __attribute__ ((__section__ (".prom.text")))
-#define PROM_DATA __attribute__ ((__section__ (".prom.data")))
-
-ambapp_dev_gptimer *gptimer;
-
-void *__prom_start_reloc; /* relocated prom_start address */
-
-/* for __va */
-extern int __prom_start;
-#define PAGE_OFFSET 0xf0000000
-#define phys_base CONFIG_SYS_SDRAM_BASE
-#define PROM_OFFS 8192
-#define PROM_SIZE_MASK (PROM_OFFS-1)
-#define __va(x) ( \
-	(void *)( ((unsigned long)(x))-PROM_OFFS+ \
-	(CONFIG_SYS_PROM_OFFSET-phys_base)+PAGE_OFFSET-CONFIG_SYS_TEXT_BASE ) \
-	)
-#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CONFIG_SYS_PROM_OFFSET-CONFIG_SYS_TEXT_BASE))
-
-struct property {
-	char *name;
-	char *value;
-	int length;
-};
-
-struct node {
-	int level;
-	struct property *properties;
-};
-
-static void leon_reboot(char *bcommand);
-static void leon_halt(void);
-static int leon_nbputchar(int c);
-static int leon_nbgetchar(void);
-
-static int no_nextnode(int node);
-static int no_child(int node);
-static int no_proplen(int node, char *name);
-static int no_getprop(int node, char *name, char *value);
-static int no_setprop(int node, char *name, char *value, int len);
-static char *no_nextprop(int node, char *name);
-
-static struct property PROM_TEXT *find_property(int node, char *name);
-static int PROM_TEXT leon_strcmp(const char *s1, const char *s2);
-static void *PROM_TEXT leon_memcpy(void *dest, const void *src, size_t n);
-static void PROM_TEXT leon_reboot_physical(char *bcommand);
-
-void __inline__ leon_flush_cache_all(void)
-{
-	__asm__ __volatile__(" flush ");
-      __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH):"memory");
-}
-
-void __inline__ leon_flush_tlb_all(void)
-{
-	leon_flush_cache_all();
-	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x400),
-			     "i"(ASI_MMUFLUSH):"memory");
-}
-
-typedef struct {
-	unsigned int ctx_table[256];
-	unsigned int pgd_table[256];
-} sparc_srmmu_setup;
-
-sparc_srmmu_setup srmmu_tables PROM_PGT = {
-	{0},
-	{0x1e,
-	 0x10001e,
-	 0x20001e,
-	 0x30001e,
-	 0x40001e,
-	 0x50001e,
-	 0x60001e,
-	 0x70001e,
-	 0x80001e,
-	 0x90001e,
-	 0xa0001e,
-	 0xb0001e,
-	 0xc0001e,
-	 0xd0001e,
-	 0xe0001e,
-	 0xf0001e,
-	 0x100001e,
-	 0x110001e,
-	 0x120001e,
-	 0x130001e,
-	 0x140001e,
-	 0x150001e,
-	 0x160001e,
-	 0x170001e,
-	 0x180001e,
-	 0x190001e,
-	 0x1a0001e,
-	 0x1b0001e,
-	 0x1c0001e,
-	 0x1d0001e,
-	 0x1e0001e,
-	 0x1f0001e,
-	 0x200001e,
-	 0x210001e,
-	 0x220001e,
-	 0x230001e,
-	 0x240001e,
-	 0x250001e,
-	 0x260001e,
-	 0x270001e,
-	 0x280001e,
-	 0x290001e,
-	 0x2a0001e,
-	 0x2b0001e,
-	 0x2c0001e,
-	 0x2d0001e,
-	 0x2e0001e,
-	 0x2f0001e,
-	 0x300001e,
-	 0x310001e,
-	 0x320001e,
-	 0x330001e,
-	 0x340001e,
-	 0x350001e,
-	 0x360001e,
-	 0x370001e,
-	 0x380001e,
-	 0x390001e,
-	 0x3a0001e,
-	 0x3b0001e,
-	 0x3c0001e,
-	 0x3d0001e,
-	 0x3e0001e,
-	 0x3f0001e,
-	 0x400001e,
-	 0x410001e,
-	 0x420001e,
-	 0x430001e,
-	 0x440001e,
-	 0x450001e,
-	 0x460001e,
-	 0x470001e,
-	 0x480001e,
-	 0x490001e,
-	 0x4a0001e,
-	 0x4b0001e,
-	 0x4c0001e,
-	 0x4d0001e,
-	 0x4e0001e,
-	 0x4f0001e,
-	 0x500001e,
-	 0x510001e,
-	 0x520001e,
-	 0x530001e,
-	 0x540001e,
-	 0x550001e,
-	 0x560001e,
-	 0x570001e,
-	 0x580001e,
-	 0x590001e,
-	 0x5a0001e,
-	 0x5b0001e,
-	 0x5c0001e,
-	 0x5d0001e,
-	 0x5e0001e,
-	 0x5f0001e,
-	 0x600001e,
-	 0x610001e,
-	 0x620001e,
-	 0x630001e,
-	 0x640001e,
-	 0x650001e,
-	 0x660001e,
-	 0x670001e,
-	 0x680001e,
-	 0x690001e,
-	 0x6a0001e,
-	 0x6b0001e,
-	 0x6c0001e,
-	 0x6d0001e,
-	 0x6e0001e,
-	 0x6f0001e,
-	 0x700001e,
-	 0x710001e,
-	 0x720001e,
-	 0x730001e,
-	 0x740001e,
-	 0x750001e,
-	 0x760001e,
-	 0x770001e,
-	 0x780001e,
-	 0x790001e,
-	 0x7a0001e,
-	 0x7b0001e,
-	 0x7c0001e,
-	 0x7d0001e,
-	 0x7e0001e,
-	 0x7f0001e,
-	 0x800001e,
-	 0x810001e,
-	 0x820001e,
-	 0x830001e,
-	 0x840001e,
-	 0x850001e,
-	 0x860001e,
-	 0x870001e,
-	 0x880001e,
-	 0x890001e,
-	 0x8a0001e,
-	 0x8b0001e,
-	 0x8c0001e,
-	 0x8d0001e,
-	 0x8e0001e,
-	 0x8f0001e,
-	 0x900001e,
-	 0x910001e,
-	 0x920001e,
-	 0x930001e,
-	 0x940001e,
-	 0x950001e,
-	 0x960001e,
-	 0x970001e,
-	 0x980001e,
-	 0x990001e,
-	 0x9a0001e,
-	 0x9b0001e,
-	 0x9c0001e,
-	 0x9d0001e,
-	 0x9e0001e,
-	 0x9f0001e,
-	 0xa00001e,
-	 0xa10001e,
-	 0xa20001e,
-	 0xa30001e,
-	 0xa40001e,
-	 0xa50001e,
-	 0xa60001e,
-	 0xa70001e,
-	 0xa80001e,
-	 0xa90001e,
-	 0xaa0001e,
-	 0xab0001e,
-	 0xac0001e,
-	 0xad0001e,
-	 0xae0001e,
-	 0xaf0001e,
-	 0xb00001e,
-	 0xb10001e,
-	 0xb20001e,
-	 0xb30001e,
-	 0xb40001e,
-	 0xb50001e,
-	 0xb60001e,
-	 0xb70001e,
-	 0xb80001e,
-	 0xb90001e,
-	 0xba0001e,
-	 0xbb0001e,
-	 0xbc0001e,
-	 0xbd0001e,
-	 0xbe0001e,
-	 0xbf0001e,
-	 0xc00001e,
-	 0xc10001e,
-	 0xc20001e,
-	 0xc30001e,
-	 0xc40001e,
-	 0xc50001e,
-	 0xc60001e,
-	 0xc70001e,
-	 0xc80001e,
-	 0xc90001e,
-	 0xca0001e,
-	 0xcb0001e,
-	 0xcc0001e,
-	 0xcd0001e,
-	 0xce0001e,
-	 0xcf0001e,
-	 0xd00001e,
-	 0xd10001e,
-	 0xd20001e,
-	 0xd30001e,
-	 0xd40001e,
-	 0xd50001e,
-	 0xd60001e,
-	 0xd70001e,
-	 0xd80001e,
-	 0xd90001e,
-	 0xda0001e,
-	 0xdb0001e,
-	 0xdc0001e,
-	 0xdd0001e,
-	 0xde0001e,
-	 0xdf0001e,
-	 0xe00001e,
-	 0xe10001e,
-	 0xe20001e,
-	 0xe30001e,
-	 0xe40001e,
-	 0xe50001e,
-	 0xe60001e,
-	 0xe70001e,
-	 0xe80001e,
-	 0xe90001e,
-	 0xea0001e,
-	 0xeb0001e,
-	 0xec0001e,
-	 0xed0001e,
-	 0xee0001e,
-	 0xef0001e,
-	 0x400001e		/* default */
-	 }
-};
-
-/* a self contained prom info structure */
-struct leon_reloc_func {
-	struct property *(*find_property) (int node, char *name);
-	int (*strcmp) (char *s1, char *s2);
-	void *(*memcpy) (void *dest, const void *src, size_t n);
-	void (*reboot_physical) (char *cmd);
-	ambapp_dev_apbuart *leon3_apbuart;
-};
-
-struct leon_prom_info {
-	int freq_khz;
-	int leon_nctx;
-	int mids[32];
-	int baudrates[2];
-	struct leon_reloc_func reloc_funcs;
-	struct property root_properties[4];
-	struct property cpu_properties[7];
-#undef  CPUENTRY
-#define CPUENTRY(idx) struct property cpu_properties##idx[4]
-	 CPUENTRY(1);
-	 CPUENTRY(2);
-	 CPUENTRY(3);
-	 CPUENTRY(4);
-	 CPUENTRY(5);
-	 CPUENTRY(6);
-	 CPUENTRY(7);
-	 CPUENTRY(8);
-	 CPUENTRY(9);
-	 CPUENTRY(10);
-	 CPUENTRY(11);
-	 CPUENTRY(12);
-	 CPUENTRY(13);
-	 CPUENTRY(14);
-	 CPUENTRY(15);
-	 CPUENTRY(16);
-	 CPUENTRY(17);
-	 CPUENTRY(18);
-	 CPUENTRY(19);
-	 CPUENTRY(20);
-	 CPUENTRY(21);
-	 CPUENTRY(22);
-	 CPUENTRY(23);
-	 CPUENTRY(24);
-	 CPUENTRY(25);
-	 CPUENTRY(26);
-	 CPUENTRY(27);
-	 CPUENTRY(28);
-	 CPUENTRY(29);
-	 CPUENTRY(30);
-	 CPUENTRY(31);
-	struct idprom idprom;
-	struct linux_nodeops nodeops;
-	struct linux_mlist_v0 *totphys_p;
-	struct linux_mlist_v0 totphys;
-	struct linux_mlist_v0 *avail_p;
-	struct linux_mlist_v0 avail;
-	struct linux_mlist_v0 *prommap_p;
-	void (*synchook) (void);
-	struct linux_arguments_v0 *bootargs_p;
-	struct linux_arguments_v0 bootargs;
-	struct linux_romvec romvec;
-	struct node nodes[35];
-	char s_device_type[12];
-	char s_cpu[4];
-	char s_mid[4];
-	char s_idprom[7];
-	char s_compatability[14];
-	char s_leon2[6];
-	char s_mmu_nctx[9];
-	char s_frequency[16];
-	char s_uart1_baud[11];
-	char s_uart2_baud[11];
-	char arg[256];
-};
-
-/* static prom info */
-static struct leon_prom_info PROM_DATA spi = {
-	CONFIG_SYS_CLK_FREQ / 1000,
-	256,
-	{
-#undef	CPUENTRY
-#define	CPUENTRY(idx) idx
-	 CPUENTRY(0),
-	 CPUENTRY(1),
-	 CPUENTRY(2),
-	 CPUENTRY(3),
-	 CPUENTRY(4),
-	 CPUENTRY(5),
-	 CPUENTRY(6),
-	 CPUENTRY(7),
-	 CPUENTRY(8),
-	 CPUENTRY(9),
-	 CPUENTRY(10),
-	 CPUENTRY(11),
-	 CPUENTRY(12),
-	 CPUENTRY(13),
-	 CPUENTRY(14),
-	 CPUENTRY(15),
-	 CPUENTRY(16),
-	 CPUENTRY(17),
-	 CPUENTRY(18),
-	 CPUENTRY(19),
-	 CPUENTRY(20),
-	 CPUENTRY(21),
-	 CPUENTRY(22),
-	 CPUENTRY(23),
-	 CPUENTRY(24),
-	 CPUENTRY(25),
-	 CPUENTRY(26),
-	 CPUENTRY(27),
-	 CPUENTRY(28),
-	 CPUENTRY(29),
-	 CPUENTRY(30),
-	 31},
-	{38400, 38400},
-	{
-	 __va(find_property),
-	 __va(leon_strcmp),
-	 __va(leon_memcpy),
-	 __phy(leon_reboot_physical),
-	 },
-	{
-	 {__va(spi.s_device_type), __va(spi.s_idprom), 4},
-	 {__va(spi.s_idprom), (char *)__va(&spi.idprom), sizeof(struct idprom)},
-	 {__va(spi.s_compatability), __va(spi.s_leon2), 5},
-	 {NULL, NULL, -1}
-	 },
-	{
-	 {__va(spi.s_device_type), __va(spi.s_cpu), 4},
-	 {__va(spi.s_mid), __va(&spi.mids[0]), 4},
-	 {__va(spi.s_mmu_nctx), (char *)__va(&spi.leon_nctx), 4},
-	 {__va(spi.s_frequency), (char *)__va(&spi.freq_khz), 4},
-	 {__va(spi.s_uart1_baud), (char *)__va(&spi.baudrates[0]), 4},
-	 {__va(spi.s_uart2_baud), (char *)__va(&spi.baudrates[1]), 4},
-	 {NULL, NULL, -1}
-	 },
-#undef  CPUENTRY
-#define CPUENTRY(idx) \
-	{ /* cpu_properties */						\
-		{__va(spi.s_device_type), __va(spi.s_cpu), 4},		\
-		{__va(spi.s_mid), __va(&spi.mids[idx]), 4},			\
-		{__va(spi.s_frequency), (char *)__va(&spi.freq_khz), 4},	\
-		{NULL, NULL, -1}						\
-	}
-	CPUENTRY(1),
-	CPUENTRY(2),
-	CPUENTRY(3),
-	CPUENTRY(4),
-	CPUENTRY(5),
-	CPUENTRY(6),
-	CPUENTRY(7),
-	CPUENTRY(8),
-	CPUENTRY(9),
-	CPUENTRY(10),
-	CPUENTRY(11),
-	CPUENTRY(12),
-	CPUENTRY(13),
-	CPUENTRY(14),
-	CPUENTRY(15),
-	CPUENTRY(16),
-	CPUENTRY(17),
-	CPUENTRY(18),
-	CPUENTRY(19),
-	CPUENTRY(20),
-	CPUENTRY(21),
-	CPUENTRY(22),
-	CPUENTRY(23),
-	CPUENTRY(24),
-	CPUENTRY(25),
-	CPUENTRY(26),
-	CPUENTRY(27),
-	CPUENTRY(28),
-	CPUENTRY(29),
-	CPUENTRY(30),
-	CPUENTRY(31),
-	{
-	 0x01,			/* format */
-	 M_LEON2 | M_LEON2_SOC,	/* machine type */
-	 {0, 0, 0, 0, 0, 0},	/* eth */
-	 0,			/* date */
-	 0,			/* sernum */
-	 0,			/* checksum */
-	 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}	/* reserved */
-	 },
-	{
-	 __va(no_nextnode),
-	 __va(no_child),
-	 __va(no_proplen),
-	 __va(no_getprop),
-	 __va(no_setprop),
-	 __va(no_nextprop)
-	 },
-	__va(&spi.totphys),
-	{
-	 NULL,
-	 (char *)CONFIG_SYS_SDRAM_BASE,
-	 0,
-	 },
-	__va(&spi.avail),
-	{
-	 NULL,
-	 (char *)CONFIG_SYS_SDRAM_BASE,
-	 0,
-	 },
-	NULL,			/* prommap_p */
-	NULL,
-	__va(&spi.bootargs),
-	{
-	 {NULL, __va(spi.arg), NULL /*... */ },
-	 /*... */
-	 },
-	{
-	 0,
-	 0,			/* sun4c v0 prom */
-	 0, 0,
-	 {__va(&spi.totphys_p), __va(&spi.prommap_p), __va(&spi.avail_p)},
-	 __va(&spi.nodeops),
-	 NULL, {NULL /* ... */ },
-	 NULL, NULL,
-	 NULL, NULL,		/* pv_getchar, pv_putchar */
-	 __va(leon_nbgetchar), __va(leon_nbputchar),
-	 NULL,
-	 __va(leon_reboot),
-	 NULL,
-	 NULL,
-	 NULL,
-	 __va(leon_halt),
-	 __va(&spi.synchook),
-	 {NULL},
-	 __va(&spi.bootargs_p)
-	 /*... */
-	 },
-	{
-	 {0, __va(spi.root_properties + 3) /* NULL, NULL, -1 */ },
-	 {0, __va(spi.root_properties)},
-	 /* cpu 0, must be spi.nodes[2] see leon_prom_init() */
-	 {1, __va(spi.cpu_properties)},
-
-#undef  CPUENTRY
-#define CPUENTRY(idx) \
-	  {1, __va(spi.cpu_properties##idx) }	/* cpu <idx> */
-	 CPUENTRY(1),
-	 CPUENTRY(2),
-	 CPUENTRY(3),
-	 CPUENTRY(4),
-	 CPUENTRY(5),
-	 CPUENTRY(6),
-	 CPUENTRY(7),
-	 CPUENTRY(8),
-	 CPUENTRY(9),
-	 CPUENTRY(10),
-	 CPUENTRY(11),
-	 CPUENTRY(12),
-	 CPUENTRY(13),
-	 CPUENTRY(14),
-	 CPUENTRY(15),
-	 CPUENTRY(16),
-	 CPUENTRY(17),
-	 CPUENTRY(18),
-	 CPUENTRY(19),
-	 CPUENTRY(20),
-	 CPUENTRY(21),
-	 CPUENTRY(22),
-	 CPUENTRY(23),
-	 CPUENTRY(24),
-	 CPUENTRY(25),
-	 CPUENTRY(26),
-	 CPUENTRY(27),
-	 CPUENTRY(28),
-	 CPUENTRY(29),
-	 CPUENTRY(30),
-	 CPUENTRY(31),
-	 {-1, __va(spi.root_properties + 3) /* NULL, NULL, -1 */ }
-	 },
-	"device_type",
-	"cpu",
-	"mid",
-	"idprom",
-	"compatability",
-	"leon2",
-	"mmu-nctx",
-	"clock-frequency",
-	"uart1_baud",
-	"uart2_baud",
-	CONFIG_DEFAULT_KERNEL_COMMAND_LINE
-};
-
-/* from arch/sparc/kernel/setup.c */
-#define RAMDISK_LOAD_FLAG 0x4000
-extern unsigned short root_flags;
-extern unsigned short root_dev;
-extern unsigned short ram_flags;
-extern unsigned int sparc_ramdisk_image;
-extern unsigned int sparc_ramdisk_size;
-extern int root_mountflags;
-
-extern char initrd_end, initrd_start;
-
-/* Reboot the CPU = jump to beginning of flash again.
- *
- * Make sure that all function are inlined here.
- */
-static void PROM_TEXT leon_reboot(char *bcommand)
-{
-	register char *arg = bcommand;
-	void __attribute__ ((noreturn)) (*reboot_physical) (char *cmd);
-
-	/* get physical address */
-	struct leon_prom_info *pspi =
-	    (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
-	unsigned int *srmmu_ctx_table;
-
-	/* Turn of Interrupts */
-	set_pil(0xf);
-
-	/* Set kernel's context, context zero */
-	srmmu_set_context(0);
-
-	/* Get physical address of the MMU shutdown routine */
-	reboot_physical = (void *)
-	    SPARC_BYPASS_READ(&pspi->reloc_funcs.reboot_physical);
-
-	/* Now that we know the physical address of the function
-	 * we can make the MMU allow jumping to it.
-	 */
-	srmmu_ctx_table = (unsigned int *)srmmu_get_ctable_ptr();
-
-	srmmu_ctx_table = (unsigned int *)SPARC_BYPASS_READ(srmmu_ctx_table);
-
-	/* get physical address of kernel's context table (assume ptd) */
-	srmmu_ctx_table = (unsigned int *)
-	    (((unsigned int)srmmu_ctx_table & 0xfffffffc) << 4);
-
-	/* enable access to physical address of MMU shutdown function */
-	SPARC_BYPASS_WRITE(&srmmu_ctx_table
-			   [((unsigned int)reboot_physical) >> 24],
-			   (((unsigned int)reboot_physical & 0xff000000) >> 4) |
-			   0x1e);
-
-	/* flush TLB cache */
-	leon_flush_tlb_all();
-
-	/* flash instruction & data cache */
-	sparc_icache_flush_all();
-	sparc_dcache_flush_all();
-
-	/* jump to physical address function
-	 * so that when the MMU is disabled
-	 * we can continue to execute
-	 */
-	reboot_physical(arg);
-}
-
-static void PROM_TEXT leon_reboot_physical(char *bcommand)
-{
-	void __attribute__ ((noreturn)) (*reset) (void);
-
-	/* Turn off MMU */
-	srmmu_set_mmureg(0);
-
-	/* Hardcoded start address */
-	reset = CONFIG_SYS_MONITOR_BASE;
-
-	/* flush data cache */
-	sparc_dcache_flush_all();
-
-	/* flush instruction cache */
-	sparc_icache_flush_all();
-
-	/* Jump to start in Flash */
-	reset();
-}
-
-static void PROM_TEXT leon_halt(void)
-{
-	while (1) ;
-}
-
-/* get single char, don't care for blocking*/
-static int PROM_TEXT leon_nbgetchar(void)
-{
-	return -1;
-}
-
-/* put single char, don't care for blocking*/
-static int PROM_TEXT leon_nbputchar(int c)
-{
-	ambapp_dev_apbuart *uart;
-
-	/* get physical address */
-	struct leon_prom_info *pspi =
-	    (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
-	uart = (ambapp_dev_apbuart *)
-	    SPARC_BYPASS_READ(&pspi->reloc_funcs.leon3_apbuart);
-
-	/* no UART? */
-	if (!uart)
-		return 0;
-
-	/***** put char in buffer... ***********
-	 * Make sure all functions are inline! *
-	 ***************************************/
-
-	/* Wait for last character to go. */
-	while (!(SPARC_BYPASS_READ(&uart->status)
-		 & APBUART_STATUS_THE));
-
-	/* Send data */
-	SPARC_BYPASS_WRITE(&uart->data, c);
-
-	/* Wait for data to be sent */
-	while (!(SPARC_BYPASS_READ(&uart->status)
-		 & APBUART_STATUS_TSE));
-
-	return 0;
-}
-
-/* node ops */
-
-/*#define nodes ((struct node *)__va(&pspi->nodes))*/
-#define nodes ((struct node *)(pspi->nodes))
-
-static int PROM_TEXT no_nextnode(int node)
-{
-	/* get physical address */
-	struct leon_prom_info *pspi =
-	    (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
-	/* convert into virtual address */
-	pspi = (struct leon_prom_info *)
-	    (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
-	if (nodes[node].level == nodes[node + 1].level)
-		return node + 1;
-	return -1;
-}
-
-static int PROM_TEXT no_child(int node)
-{
-	/* get physical address */
-	struct leon_prom_info *pspi = (struct leon_prom_info *)
-	    (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
-	/* convert into virtual address */
-	pspi = (struct leon_prom_info *)
-	    (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
-	if (nodes[node].level == nodes[node + 1].level - 1)
-		return node + 1;
-	return -1;
-}
-
-static struct property PROM_TEXT *find_property(int node, char *name)
-{
-	/* get physical address */
-	struct leon_prom_info *pspi = (struct leon_prom_info *)
-	    (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
-	/* convert into virtual address */
-	pspi = (struct leon_prom_info *)
-	    (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
-	struct property *prop = &nodes[node].properties[0];
-	while (prop && prop->name) {
-		if (pspi->reloc_funcs.strcmp(prop->name, name) == 0)
-			return prop;
-		prop++;
-	}
-	return NULL;
-}
-
-static int PROM_TEXT no_proplen(int node, char *name)
-{
-	/* get physical address */
-	struct leon_prom_info *pspi = (struct leon_prom_info *)
-	    (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
-	/* convert into virtual address */
-	pspi = (struct leon_prom_info *)
-	    (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
-	struct property *prop = pspi->reloc_funcs.find_property(node, name);
-	if (prop)
-		return prop->length;
-	return -1;
-}
-
-static int PROM_TEXT no_getprop(int node, char *name, char *value)
-{
-	/* get physical address */
-	struct leon_prom_info *pspi = (struct leon_prom_info *)
-	    (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
-	/* convert into virtual address */
-	pspi = (struct leon_prom_info *)
-	    (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
-	struct property *prop = pspi->reloc_funcs.find_property(node, name);
-	if (prop) {
-		pspi->reloc_funcs.memcpy(value, prop->value, prop->length);
-		return 1;
-	}
-	return -1;
-}
-
-static int PROM_TEXT no_setprop(int node, char *name, char *value, int len)
-{
-	return -1;
-}
-
-static char PROM_TEXT *no_nextprop(int node, char *name)
-{
-	/* get physical address */
-	struct leon_prom_info *pspi = (struct leon_prom_info *)
-	    (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-	struct property *prop;
-
-	/* convert into virtual address */
-	pspi = (struct leon_prom_info *)
-	    (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
-	if (!name || !name[0])
-		return nodes[node].properties[0].name;
-
-	prop = pspi->reloc_funcs.find_property(node, name);
-	if (prop)
-		return prop[1].name;
-	return NULL;
-}
-
-static int PROM_TEXT leon_strcmp(const char *s1, const char *s2)
-{
-	register char result;
-
-	while (1) {
-		result = *s1 - *s2;
-		if (result || !*s1)
-			break;
-		s2++;
-		s1++;
-	}
-
-	return result;
-}
-
-static void *PROM_TEXT leon_memcpy(void *dest, const void *src, size_t n)
-{
-	char *dst = (char *)dest, *source = (char *)src;
-
-	while (n--) {
-		*dst = *source;
-		dst++;
-		source++;
-	}
-	return dest;
-}
-
-#define GETREGSP(sp) __asm__ __volatile__("mov %%sp, %0" : "=r" (sp))
-
-void leon_prom_init(struct leon_prom_info *pspi)
-{
-	unsigned long i;
-	unsigned char cksum, *ptr;
-	char *addr_str, *end;
-	unsigned long sp;
-	GETREGSP(sp);
-
-	pspi->freq_khz = CONFIG_SYS_CLK_FREQ / 1000;
-
-	/* Set Available main memory size */
-	pspi->totphys.num_bytes = CONFIG_SYS_PROM_OFFSET - CONFIG_SYS_SDRAM_BASE;
-	pspi->avail.num_bytes = pspi->totphys.num_bytes;
-
-	/* Set the pointer to the Console UART in romvec */
-	pspi->reloc_funcs.leon3_apbuart = gd->arch.uart;
-
-	{
-		int j = 1;
-#ifdef CONFIG_SMP
-		ambapp_dev_irqmp *b;
-		b = (ambapp_dev_irqmp *) leon3_getapbbase(VENDOR_GAISLER,
-							  GAISLER_IRQMP);
-		if (b) {
-			j = 1 + ((LEON3_BYPASS_LOAD_PA(&(b->mpstatus))
-				  >> LEON3_IRQMPSTATUS_CPUNR) & 0xf);
-		}
-#endif
-#undef nodes
-		pspi->nodes[2 + j].level = -1;
-		pspi->nodes[2 + j].properties = __va(spi.root_properties + 3);
-	}
-
-	/* Set Ethernet MAC address from environment */
-	if ((addr_str = getenv("ethaddr")) != NULL) {
-		for (i = 0; i < 6; i++) {
-			pspi->idprom.id_ethaddr[i] = addr_str ?
-			    simple_strtoul(addr_str, &end, 16) : 0;
-			if (addr_str) {
-				addr_str = (*end) ? end + 1 : end;
-			}
-		}
-	} else {
-		/* HW Address not found in environment,
-		 * Set default HW address
-		 */
-		pspi->idprom.id_ethaddr[0] = 0;
-		pspi->idprom.id_ethaddr[1] = 0;
-		pspi->idprom.id_ethaddr[2] = 0;
-		pspi->idprom.id_ethaddr[3] = 0;
-		pspi->idprom.id_ethaddr[4] = 0;
-		pspi->idprom.id_ethaddr[5] = 0;
-	}
-
-	ptr = (unsigned char *)&pspi->idprom;
-	for (i = cksum = 0; i <= 0x0E; i++)
-		cksum ^= *ptr++;
-	pspi->idprom.id_cksum = cksum;
-}
-
-static inline void set_cache(unsigned long regval)
-{
-	asm volatile ("sta %0, [%%g0] %1\n\t":: "r" (regval), "i"(2):"memory");
-}
-
-extern unsigned short bss_start, bss_end;
-
-/* mark as section .img.main.text, to be referenced in linker script */
-int prom_init(void)
-{
-	struct leon_prom_info *pspi = (void *)
-	    ((((unsigned int)&spi) & PROM_SIZE_MASK) + CONFIG_SYS_PROM_OFFSET);
-
-	/* disable mmu */
-	srmmu_set_mmureg(0x00000000);
-	__asm__ __volatile__("flush\n\t");
-
-	/* init prom info struct */
-	leon_prom_init(pspi);
-
-	kernel_arg_promvec = &pspi->romvec;
-#ifdef PRINT_ROM_VEC
-	printf("Kernel rom vec: 0x%lx\n", (unsigned int)(&pspi->romvec));
-#endif
-	return 0;
-}
-
-/* Copy current kernel boot argument to ROMvec */
-void prepare_bootargs(char *bootargs)
-{
-	struct leon_prom_info *pspi;
-	char *src, *dst;
-	int left;
-
-	/* if no bootargs set, skip copying ==> default bootline */
-	if (bootargs && (*bootargs != '\0')) {
-		pspi = (void *)((((unsigned int)&spi) & PROM_SIZE_MASK) +
-				CONFIG_SYS_PROM_OFFSET);
-		src = bootargs;
-		dst = &pspi->arg[0];
-		left = 255;	/* max len */
-		while (*src && left > 0) {
-			*dst++ = *src++;
-			left--;
-		}
-		/* terminate kernel command line string */
-		*dst = 0;
-	}
-}
-
-void srmmu_init_cpu(unsigned int entry)
-{
-	sparc_srmmu_setup *psrmmu_tables = (void *)
-	    ((((unsigned int)&srmmu_tables) & PROM_SIZE_MASK) +
-	     CONFIG_SYS_PROM_OFFSET);
-
-	/* Make context 0 (kernel's context) point
-	 * to our prepared memory mapping
-	 */
-#define PTD 1
-	psrmmu_tables->ctx_table[0] =
-	    ((unsigned int)&psrmmu_tables->pgd_table[0x00]) >> 4 | PTD;
-
-	/* Set virtual kernel address 0xf0000000
-	 * to SRAM/SDRAM address.
-	 * Make it READ/WRITE/EXEC to SuperUser
-	 */
-#define PTE 2
-#define ACC_SU_ALL 0x1c
-	psrmmu_tables->pgd_table[0xf0] =
-	    (CONFIG_SYS_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE;
-	psrmmu_tables->pgd_table[0xf1] =
-	    ((CONFIG_SYS_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE;
-	psrmmu_tables->pgd_table[0xf2] =
-	    ((CONFIG_SYS_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE;
-	psrmmu_tables->pgd_table[0xf3] =
-	    ((CONFIG_SYS_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE;
-	psrmmu_tables->pgd_table[0xf4] =
-	    ((CONFIG_SYS_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE;
-	psrmmu_tables->pgd_table[0xf5] =
-	    ((CONFIG_SYS_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE;
-	psrmmu_tables->pgd_table[0xf6] =
-	    ((CONFIG_SYS_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE;
-	psrmmu_tables->pgd_table[0xf7] =
-	    ((CONFIG_SYS_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE;
-
-	/* convert rom vec pointer to virtual address */
-	kernel_arg_promvec = (struct linux_romvec *)
-	    (((unsigned int)kernel_arg_promvec & 0x0fffffff) | 0xf0000000);
-
-	/* Set Context pointer to point to context table
-	 * 256 contexts supported.
-	 */
-	srmmu_set_ctable_ptr((unsigned int)&psrmmu_tables->ctx_table[0]);
-
-	/* Set kernel's context, context zero */
-	srmmu_set_context(0);
-
-	/* Invalidate all Cache */
-	__asm__ __volatile__("flush\n\t");
-
-	srmmu_set_mmureg(0x00000001);
-	leon_flush_tlb_all();
-	leon_flush_cache_all();
-}
diff --git a/arch/sparc/cpu/leon3/serial.c b/arch/sparc/cpu/leon3/serial.c
deleted file mode 100644
index bc6e7a1..0000000
--- a/arch/sparc/cpu/leon3/serial.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/* GRLIB APBUART Serial controller driver
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <ambapp.h>
-#include <grlib/apbuart.h>
-#include <serial.h>
-#include <watchdog.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Select which UART that will become u-boot console */
-#ifndef CONFIG_SYS_GRLIB_APBUART_INDEX
-/* Try to use CONFIG_CONS_INDEX, if available, it is numbered from 1 */
-#ifdef CONFIG_CONS_INDEX
-#define CONFIG_SYS_GRLIB_APBUART_INDEX (CONFIG_CONS_INDEX - 1)
-#else
-#define CONFIG_SYS_GRLIB_APBUART_INDEX 0
-#endif
-#endif
-
-static unsigned apbuart_calc_scaler(unsigned apbuart_freq, unsigned baud)
-{
-	return (((apbuart_freq * 10) / (baud * 8)) - 5) / 10;
-}
-
-static int leon3_serial_init(void)
-{
-	ambapp_dev_apbuart *uart;
-	ambapp_apbdev apbdev;
-	unsigned int tmp;
-
-	/* find UART */
-	if (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER, GAISLER_APBUART,
-		CONFIG_SYS_GRLIB_APBUART_INDEX, &apbdev) != 1) {
-		gd->flags &= ~GD_FLG_SERIAL_READY;
-		panic("%s: apbuart not found!\n", __func__);
-		return -1; /* didn't find hardware */
-	}
-
-	/* found apbuart, let's init .. */
-	uart = (ambapp_dev_apbuart *) apbdev.address;
-
-	/* APBUART Frequency is equal to bus frequency */
-	gd->arch.uart_freq = ambapp_bus_freq(&ambapp_plb, apbdev.ahb_bus_index);
-
-	/* Set scaler / baud rate */
-	tmp = apbuart_calc_scaler(gd->arch.uart_freq, CONFIG_BAUDRATE);
-	writel(tmp, &uart->scaler);
-
-	/* Let bit 11 be unchanged (debug bit for GRMON) */
-	tmp = readl(&uart->ctrl) & APBUART_CTRL_DBG;
-	/* Receiver & transmitter enable */
-	tmp |= APBUART_CTRL_RE | APBUART_CTRL_TE;
-	writel(tmp, &uart->ctrl);
-
-	gd->arch.uart = uart;
-	return 0;
-}
-
-static inline ambapp_dev_apbuart *leon3_get_uart_regs(void)
-{
-	ambapp_dev_apbuart *uart = gd->arch.uart;
-	return uart;
-}
-
-static void leon3_serial_putc_raw(const char c)
-{
-	ambapp_dev_apbuart * const uart = leon3_get_uart_regs();
-
-	if (!uart)
-		return;
-
-	/* Wait for last character to go. */
-	while (!(readl(&uart->status) & APBUART_STATUS_THE))
-		WATCHDOG_RESET();
-
-	/* Send data */
-	writel(c, &uart->data);
-
-#ifdef LEON_DEBUG
-	/* Wait for data to be sent */
-	while (!(readl(&uart->status) & APBUART_STATUS_TSE))
-		WATCHDOG_RESET();
-#endif
-}
-
-static void leon3_serial_putc(const char c)
-{
-	if (c == '\n')
-		leon3_serial_putc_raw('\r');
-
-	leon3_serial_putc_raw(c);
-}
-
-static int leon3_serial_getc(void)
-{
-	ambapp_dev_apbuart * const uart = leon3_get_uart_regs();
-
-	if (!uart)
-		return 0;
-
-	/* Wait for a character to arrive. */
-	while (!(readl(&uart->status) & APBUART_STATUS_DR))
-		WATCHDOG_RESET();
-
-	/* Read character data */
-	return readl(&uart->data);
-}
-
-static int leon3_serial_tstc(void)
-{
-	ambapp_dev_apbuart * const uart = leon3_get_uart_regs();
-
-	if (!uart)
-		return 0;
-
-	return readl(&uart->status) & APBUART_STATUS_DR;
-}
-
-/* set baud rate for uart */
-static void leon3_serial_setbrg(void)
-{
-	ambapp_dev_apbuart * const uart = leon3_get_uart_regs();
-	unsigned int scaler;
-
-	if (!uart)
-		return;
-
-	if (!gd->baudrate)
-		gd->baudrate = CONFIG_BAUDRATE;
-
-	if (!gd->arch.uart_freq)
-		gd->arch.uart_freq = CONFIG_SYS_CLK_FREQ;
-
-	scaler = apbuart_calc_scaler(gd->arch.uart_freq, gd->baudrate);
-
-	writel(scaler, &uart->scaler);
-}
-
-static struct serial_device leon3_serial_drv = {
-	.name	= "leon3_serial",
-	.start	= leon3_serial_init,
-	.stop	= NULL,
-	.setbrg	= leon3_serial_setbrg,
-	.putc	= leon3_serial_putc,
-	.puts	= default_serial_puts,
-	.getc	= leon3_serial_getc,
-	.tstc	= leon3_serial_tstc,
-};
-
-void leon3_serial_initialize(void)
-{
-	serial_register(&leon3_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &leon3_serial_drv;
-}
-
-#ifdef CONFIG_DEBUG_UART_APBUART
-
-#include <debug_uart.h>
-
-static inline void _debug_uart_init(void)
-{
-	ambapp_dev_apbuart *uart = (ambapp_dev_apbuart *)CONFIG_DEBUG_UART_BASE;
-	uart->scaler = apbuart_calc_scaler(CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
-	uart->ctrl = APBUART_CTRL_RE | APBUART_CTRL_TE;
-}
-
-static inline void _debug_uart_putc(int ch)
-{
-	ambapp_dev_apbuart *uart = (ambapp_dev_apbuart *)CONFIG_DEBUG_UART_BASE;
-	while (!(readl(&uart->status) & APBUART_STATUS_THE))
-		WATCHDOG_RESET();
-	writel(ch, &uart->data);
-}
-
-DEBUG_UART_FUNCS
-
-#endif
diff --git a/arch/sparc/cpu/leon3/start.S b/arch/sparc/cpu/leon3/start.S
deleted file mode 100644
index 1527d72..0000000
--- a/arch/sparc/cpu/leon3/start.S
+++ /dev/null
@@ -1,681 +0,0 @@
-/* This is where the SPARC/LEON3 starts
- *
- * Copyright (C) 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/asmmacro.h>
-#include <asm/winmacro.h>
-#include <asm/psr.h>
-#include <asm/stack.h>
-#include <asm/leon.h>
-#include <ambapp.h>
-
-/* Default Plug&Play I/O area */
-#ifndef CONFIG_AMBAPP_IOAREA
-#define CONFIG_AMBAPP_IOAREA AMBA_DEFAULT_IOAREA
-#endif
-
-/* Default number of SPARC register windows */
-#ifndef CONFIG_SYS_SPARC_NWINDOWS
-#define CONFIG_SYS_SPARC_NWINDOWS 8
-#endif
-
-/* Entry for traps which jump to a programmer-specified trap handler.  */
-#define TRAPR(H)  \
-	wr	%g0, 0xfe0, %psr; \
-	mov	%g0, %tbr; \
-	ba	(H); \
-	mov	%g0, %wim;
-
-#define TRAP(H) \
-	mov	%psr, %l0; \
-	ba	(H); \
-	nop; nop;
-
-#define TRAPI(ilevel) \
-	mov	ilevel, %l7; \
-	mov	%psr, %l0; \
-	b	_irq_entry; \
-	mov	%wim, %l3
-
-/* Unexcpected trap will halt the processor by forcing it to error state */
-#undef BAD_TRAP
-#define BAD_TRAP ta 0; nop; nop; nop;
-
-/* Software trap. Treat as BAD_TRAP for the time being... */
-#define SOFT_TRAP TRAP(_hwerr)
-
-#define PSR_INIT   0x1FC0	/* Disable traps, set s and ps */
-#define WIM_INIT   2
-
-/* All traps low-level code here must end with this macro. */
-#define RESTORE_ALL b ret_trap_entry; clr %l6;
-
-#define WRITE_PAUSE nop;nop;nop
-
-WINDOWSIZE = (16 * 4)
-ARGPUSHSIZE = (6 * 4)
-ARGPUSH = (WINDOWSIZE + 4)
-MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4)
-
-/* Number of register windows */
-#ifndef CONFIG_SYS_SPARC_NWINDOWS
-#error Must define number of SPARC register windows, default is 8
-#endif
-
-/* Macros to load address into a register. Uses GOT table for PIC */
-#ifdef __PIC__
-
-#define SPARC_PIC_THUNK_CALL(reg) \
-	sethi	%pc22(_GLOBAL_OFFSET_TABLE_-4), %##reg; \
-	call	__sparc_get_pc_thunk.reg; \
-	 add	%##reg, %pc10(_GLOBAL_OFFSET_TABLE_+4), %##reg;
-
-#define SPARC_LOAD_ADDRESS(sym, got, reg) \
-	sethi	%gdop_hix22(sym), %##reg; \
-	xor	%##reg, %gdop_lox10(sym), %##reg; \
-	ld	[%##got + %##reg], %##reg, %gdop(sym);
-
-#else
-
-#define SPARC_PIC_THUNK_CALL(reg)
-#define SPARC_LOAD_ADDRESS(sym, got, tmp) \
-	set	sym, %##reg;
-
-#endif
-
-#define STACK_ALIGN	8
-#define SA(X)	(((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1))
-
-	.section ".start", "ax"
-	.globl	_start, start, _trap_table
-	.globl  _irq_entry, nmi_trap
-	.globl  _reset_reloc
-
-/* at address 0
- * Hardware traps
- */
-start:
-_start:
-_trap_table:
-	TRAPR(_hardreset);		! 00 reset trap
-	BAD_TRAP;			! 01 instruction_access_exception
-	BAD_TRAP;			! 02 illegal_instruction
-	BAD_TRAP;			! 03 priveleged_instruction
-	BAD_TRAP;			! 04 fp_disabled
-	TRAP(_window_overflow);		! 05 window_overflow
-	TRAP(_window_underflow);	! 06 window_underflow
-	BAD_TRAP;			! 07 Memory Address Not Aligned
-	BAD_TRAP;			! 08 Floating Point Exception
-	BAD_TRAP;			! 09 Data Miss Exception
-	BAD_TRAP;			! 0a Tagged Instruction Ovrflw
-	BAD_TRAP;			! 0b Watchpoint Detected
-	BAD_TRAP;			! 0c
-	BAD_TRAP;			! 0d
-	BAD_TRAP;			! 0e
-	BAD_TRAP;			! 0f
-	BAD_TRAP;			! 10
-	TRAPI(1);			! 11 IRQ level 1
-	TRAPI(2);			! 12 IRQ level 2
-	TRAPI(3);			! 13 IRQ level 3
-	TRAPI(4);			! 14 IRQ level 4
-	TRAPI(5);			! 15 IRQ level 5
-	TRAPI(6);			! 16 IRQ level 6
-	TRAPI(7);			! 17 IRQ level 7
-	TRAPI(8);			! 18 IRQ level 8
-	TRAPI(9);			! 19 IRQ level 9
-	TRAPI(10);			! 1a IRQ level 10
-	TRAPI(11);			! 1b IRQ level 11
-	TRAPI(12);			! 1c IRQ level 12
-	TRAPI(13);			! 1d IRQ level 13
-	TRAPI(14);			! 1e IRQ level 14
-	TRAP(_nmi_trap);		! 1f IRQ level 15 /
-					! NMI (non maskable interrupt)
-	BAD_TRAP;			! 20 r_register_access_error
-	BAD_TRAP;			! 21 instruction access error
-	BAD_TRAP;			! 22
-	BAD_TRAP;			! 23
-	BAD_TRAP;			! 24 co-processor disabled
-	BAD_TRAP;			! 25 uniplemented FLUSH
-	BAD_TRAP;			! 26
-	BAD_TRAP;			! 27
-	BAD_TRAP;			! 28 co-processor exception
-	BAD_TRAP;			! 29 data access error
-	BAD_TRAP;			! 2a division by zero
-	BAD_TRAP;			! 2b data store error
-	BAD_TRAP;			! 2c data access MMU miss
-	BAD_TRAP;			! 2d
-	BAD_TRAP;			! 2e
-	BAD_TRAP;			! 2f
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30-33
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34-37
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38-3b
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3c-3f
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40-43
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44-47
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48-4b
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4c-4f
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50-53
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54-57
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58-5b
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5c-5f
-
-	/* implementaion dependent */
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60-63
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64-67
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68-6b
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6c-6f
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70-73
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74-77
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78-7b
-	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 7c-7f
-
-	/* Software traps, not handled */
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 80-83
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 84-87
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 88-8b
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 8c-8f
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 90-93
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 94-97
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 98-9b
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 9c-9f
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! a0-a3
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! a4-a7
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! a8-ab
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! ac-af
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! b0-b3
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! b4-b7
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! b8-bb
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! bc-bf
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! c0-c3
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! c4-c7
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! c8-cb
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! cc-cf
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! d0-d3
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! d4-d7
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! d8-db
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! dc-df
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! e0-e3
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! e4-e7
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! e8-eb
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! ec-ef
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! f0-f3
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! f4-f7
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! f8-fb
-	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! fc-ff
-
-	.section	".text"
-	.extern	_nomem_amba_init, _nomem_memory_ctrl_init
-	.align 4
-
-_hardreset:
-1000:
-	flush
-
-	/* Enable I/D-Cache and Snooping */
-	set	0x0081000f, %g2
-	sta	%g2, [%g0] 2
-
-	mov	%g0, %y
-	clr	%g1
-	clr	%g2
-	clr	%g3
-	clr	%g4
-	clr	%g5
-	clr	%g6
-	clr	%g7
-
-	mov	%asr17, %g3
-	and	%g3, 0x1f, %g3
-clear_window:
-	mov	%g0, %l0
-	mov	%g0, %l1
-	mov	%g0, %l2
-	mov	%g0, %l3
-	mov	%g0, %l4
-	mov	%g0, %l5
-	mov	%g0, %l6
-	mov	%g0, %l7
-	mov	%g0, %o0
-	mov	%g0, %o1
-	mov	%g0, %o2
-	mov	%g0, %o3
-	mov	%g0, %o4
-	mov	%g0, %o5
-	mov	%g0, %o6
-	mov	%g0, %o7
-	subcc	%g3, 1, %g3
-	bge	clear_window
-	save
-
-wiminit:
-	set	WIM_INIT, %g3
-	mov	%g3, %wim
-
-stackinit:
-	set	CONFIG_SYS_INIT_SP_OFFSET, %fp
-	andn	%fp, 0x0f, %fp
-	sub	%fp, 64, %sp
-
-tbrinit:
-	set	CONFIG_SYS_TEXT_BASE, %g2
-	wr	%g0, %g2, %tbr
-	nop
-	nop
-	nop
-
-/* Obtain the address of _GLOBAL_OFFSET_TABLE_ */
-	SPARC_PIC_THUNK_CALL(l7)
-
-/* Scan AMBA Bus for AMBA buses using PnP information. All found
- * AMBA buses I/O area will be located in i0-i5 upon return.
- * The i0-i5 registers are later used by _nomem_amba_init2
- */
-ambainit:
-	call	_nomem_amba_init
-	 sethi	%hi(CONFIG_AMBAPP_IOAREA), %o0
-
-/* Scan AMBA Buses for memory controllers, then initialize the
- * memory controllers. Note that before setting up the memory controller
- * the stack can not be used.
- */
-memory_ctrl_init:
-	SPARC_LOAD_ADDRESS(grlib_mctrl_handlers, l7, o0)
-
-	call	_nomem_memory_ctrl_init
-	 nop
-
-/* The return valu indicate how many memory controllers where found and
- * initialized, if no memory controller was initialized, we can not continue
- * because from here on we expect memory to be working.
- */
-	cmp	%o0, 0
-memory_ctrl_init_failed:
-	beq	memory_ctrl_init_failed
-	 nop
-
-/*** From now on the stack can be used. ***/
-
-cpu_init_unreloc:
-	call	cpu_init_f
-	 nop
-
-board_init_unreloc:
-	call	board_init_f
-	 clr	%o0			! boot_flags
-
-dead_unreloc:
-	mov	1, %g1			! For GRMON2 to exit normally.
-	ta 0				! If board_init_f call returns.. (unlikely)
-	 nop
-	nop
-	ba	dead_unreloc		! infinte loop
-	 nop
-
-!-------------------------------------------------------------------------------
-
-/* void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM after
- * relocating the monitor code.
- *
- * %o0 = Relocated stack pointer
- * %o1 = Relocated global data pointer
- * %o2 = Relocated text pointer
- *
- * %l7 = _GLOBAL_OFFSET_TABLE_ address
- */
-	.globl	relocate_code
-	.type	relocate_code, #function
-	.align	4
-relocate_code:
-	!SPARC_PIC_THUNK_CALL(l7)
-reloc:
-	SPARC_LOAD_ADDRESS(_text, l7, g2)	! start address of monitor
-	SPARC_LOAD_ADDRESS(__init_end, l7, g3)	! end address of monitor
-	mov	%o2, %g4		! relocation address
-	sub	%g4, %g2, %g6		! relocation offset
-	/* copy .text & .data to relocated address */
-10:	ldd	[%g2], %l0
-	ldd	[%g2+8], %l2
-	std	%l0, [%g4]
-	std	%l2, [%g4+8]
-	inc	16, %g2			! src += 16
-	cmp	%g2, %g3
-	bcs	10b			! while (src < end)
-	 inc	16, %g4			! dst += 16
-
-	clr	%l0
-	clr	%l1
-	clr	%l2
-	clr	%l3
-	clr	%g2
-
-/* register g4 contain address to start
- * This means that BSS must be directly after data and code segments
- *
- * g3 is length of bss = (__bss_end-__bss_start)
- *
- */
-
-	/* clear the relocated .bss area */
-clr_bss:
-	SPARC_LOAD_ADDRESS(__bss_start, l7, g2)
-	SPARC_LOAD_ADDRESS(__bss_end, l7, g3)
-	sub	%g3,%g2,%g3		! length of .bss area
-	add	%g3,%g4,%g3
-	/* clearing 16byte a time ==> linker script need to align to 16 byte offset */
-	clr	%g1	/* std %g0 uses g0 and g1 */
-20:
-	std	%g0, [%g4]
-	std	%g0, [%g4+8]
-	inc	16, %g4			! ptr += 16
-	cmp	%g4, %g3
-	bcs	20b			! while (ptr < end)
-	 nop
-
-	/* add offsets to GOT table */
-fixup_got:
-	SPARC_LOAD_ADDRESS(__got_start, l7, g4)
-	add	%g4, %g6, %g4
-	SPARC_LOAD_ADDRESS(__got_end, l7, g3)
-	add	%g3, %g6, %g3
-30:	ld	[%g4], %l0
-#ifdef CONFIG_RELOC_GOT_SKIP_NULL
-	cmp	%l0, 0
-	be	32f
-#endif
-	add	%l0, %g6, %l0		! relocate GOT pointer
-	st	%l0, [%g4]
-32:	inc	4, %g4			! ptr += 4
-	cmp	%g4, %g3
-	bcs	30b			! while (ptr < end)
-	 nop
-
-prom_relocate:
-	SPARC_LOAD_ADDRESS(__prom_start, l7, g2)
-	SPARC_LOAD_ADDRESS(__prom_end, l7, g3)
-	/*
-	 * Calculated addres is stored in this variable by
-	 * reserve_prom() function in common/board_f.c
-	 */
-	SPARC_LOAD_ADDRESS(__prom_start_reloc, l7, g4)
-	ld	[%g4], %g4
-
-40:	ldd	[%g2], %l0
-	ldd	[%g2+8], %l2
-	std	%l0, [%g4]
-	std	%l2, [%g4+8]
-	inc	16, %g2
-	cmp	%g2, %g3
-	bcs	40b
-	 inc	16, %g4
-
-! %o0 = stack pointer (relocated)
-! %o1 = global data pointer (relocated)
-! %o2 = text pointer (relocated)
-
-! %g6 = relocation offset
-! %l7 = _GLOBAL_OFFSET_TABLE_
-
-/* Trap table has been moved, lets tell CPU about
- * the new trap table address
- */
-update_trap_table_address:
-	wr	%g0, %o2, %tbr
-	nop
-	nop
-	nop
-
-update_stack_pointers:
-	mov	%o0, %fp
-	andn	%fp, 0x0f, %fp	! align to 16 bytes
-	add	%fp, -64, %fp	! make space for a window push
-	mov	%fp, %sp	! setup stack pointer
-
-jump_board_init_r:
-	mov	%o1, %o0	! relocated global data pointer
-	mov	%o2, %o1	! relocated text pointer
-	SPARC_LOAD_ADDRESS(board_init_r, l7, o3)
-	add	%o3, %g6, %o3	! add relocation offset
-	call	%o3
-	 nop
-
-dead:
-	mov	1, %g1			! For GRMON2 to exit normally.
-	ta 0				! if call returns.. (unlikely)
-	 nop
-	b	dead			! infinte loop
-	 nop
-
-!------------------------------------------------------------------------------
-
-/* Interrupt handler caller,
- * reg L7: interrupt number
- * reg L0: psr after interrupt
- * reg L1: PC
- * reg L2: next PC
- * reg L3: wim
- */
-_irq_entry:
-	SAVE_ALL
-
-	or	%l0, PSR_PIL, %g2
-	wr	%g2, 0x0, %psr
-	WRITE_PAUSE
-	wr	%g2, PSR_ET, %psr
-	WRITE_PAUSE
-	mov	%l7, %o0		! irq level
-	set	handler_irq, %o1
-	set	(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE), %o2
-	add	%o1, %o2, %o1
-	call	%o1
-	add	%sp, SF_REGS_SZ, %o1	! pt_regs ptr
-	or	%l0, PSR_PIL, %g2	! restore PIL after handler_irq
-	wr	%g2, PSR_ET, %psr	! keep ET up
-	WRITE_PAUSE
-
-	RESTORE_ALL
-
-!------------------------------------------------------------------------------
-
-/*
- * Window overflow trap handler
- */
-	.global _window_overflow
-
-_window_overflow:
-
-	mov	%wim, %l3		! Calculate next WIM
-	mov     %g1, %l7
-	srl     %l3, 1, %g1
-	sll	%l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l4
-	or      %g1, %l4, %g1
-	save				! Get into window to be saved.
-	mov     %g1, %wim
-	nop; nop; nop
-	st      %l0, [%sp + 0]		! Save window to the stack
-	st      %l1, [%sp + 4]
-	st      %l2, [%sp + 8]
-	st      %l3, [%sp + 12]
-	st      %l4, [%sp + 16]
-	st      %l5, [%sp + 20]
-	st      %l6, [%sp + 24]
-	st      %l7, [%sp + 28]
-	st      %i0, [%sp + 32]
-	st      %i1, [%sp + 36]
-	st      %i2, [%sp + 40]
-	st      %i3, [%sp + 44]
-	st      %i4, [%sp + 48]
-	st      %i5, [%sp + 52]
-	st      %i6, [%sp + 56]
-	st      %i7, [%sp + 60]
-	restore				! Go back to trap window.
-	mov     %l7, %g1
-	jmp	%l1			! Re-execute save.
-	 rett	%l2
-
-/*
- * Window underflow trap handler
- */
-	.global  _window_underflow
-
-_window_underflow:
-
-	mov	%wim, %l3		! Calculate next WIM
-	srl	%l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l5
-	sll	%l3, 1, %l4
-	or	%l5, %l4, %l5
-	mov 	%l5, %wim
-	nop; nop; nop
-	restore				! Two restores to get into the
-	restore				! window to restore
-	ld	[%sp + 0], %l0;		! Restore window from the stack
-	ld	[%sp + 4], %l1;
-	ld	[%sp + 8], %l2;
-	ld	[%sp + 12], %l3;
-	ld	[%sp + 16], %l4;
-	ld	[%sp + 20], %l5;
-	ld	[%sp + 24], %l6;
-	ld	[%sp + 28], %l7;
-	ld	[%sp + 32], %i0;
-	ld	[%sp + 36], %i1;
-	ld	[%sp + 40], %i2;
-	ld	[%sp + 44], %i3;
-	ld	[%sp + 48], %i4;
-	ld	[%sp + 52], %i5;
-	ld	[%sp + 56], %i6;
-	ld	[%sp + 60], %i7;
-	save				! Get back to the trap window.
-	save
-	jmp	%l1			! Re-execute restore.
-	 rett	%l2
-
-!------------------------------------------------------------------------------
-
-_nmi_trap:
-	nop
-	jmp %l1
-	rett %l2
-
-_hwerr:
-	ta 0
-	nop
-	nop
-	b _hwerr			! loop infinite
-	nop
-
-/* Registers to not touch at all. */
-#define t_psr      l0 /* Set by caller */
-#define t_pc       l1 /* Set by caller */
-#define t_npc      l2 /* Set by caller */
-#define t_wim      l3 /* Set by caller */
-#define t_twinmask l4 /* Set at beginning of this entry routine. */
-#define t_kstack   l5 /* Set right before pt_regs frame is built */
-#define t_retpc    l6 /* If you change this, change winmacro.h header file */
-#define t_systable l7 /* Never touch this, could be the syscall table ptr. */
-#define curptr     g6 /* Set after pt_regs frame is built */
-
-trap_setup:
-/* build a pt_regs trap frame. */
-	sub	%fp, (SF_REGS_SZ + PT_REGS_SZ), %t_kstack
-	PT_STORE_ALL(t_kstack, t_psr, t_pc, t_npc, g2)
-
-	/* See if we are in the trap window. */
-	mov	1, %t_twinmask
-	sll	%t_twinmask, %t_psr, %t_twinmask ! t_twinmask = (1 << psr)
-	andcc	%t_twinmask, %t_wim, %g0
-	beq	1f		! in trap window, clean up
-	nop
-
-	/*-------------------------------------------------
-	 * Spill , adjust %wim and go.
-	 */
-	srl	%t_wim, 0x1, %g2		! begin computation of new %wim
-
-	set	(CONFIG_SYS_SPARC_NWINDOWS-1), %g3	!NWINDOWS-1
-
-	sll	%t_wim, %g3, %t_wim	! NWINDOWS-1
-	or	%t_wim, %g2, %g2
-	and	%g2, 0xff, %g2
-
-	save	%g0, %g0, %g0           ! get in window to be saved
-
-	/* Set new %wim value */
-	wr	%g2, 0x0, %wim
-
-	/* Save the kernel window onto the corresponding stack. */
-	RW_STORE(sp)
-
-	restore	%g0, %g0, %g0
-	/*-------------------------------------------------*/
-
-1:
-	/* Trap from kernel with a window available.
-	 * Just do it...
-	 */
-	jmpl	%t_retpc + 0x8, %g0	! return to caller
-	 mov	%t_kstack, %sp		! jump onto new stack
-
-#define twin_tmp1 l4
-#define glob_tmp  g4
-#define curptr    g6
-ret_trap_entry:
-	wr	%t_psr, 0x0, %psr       ! enable nesting again, clear ET
-
-	/* Will the rett land us in the invalid window? */
-	mov	2, %g1
-	sll	%g1, %t_psr, %g1
-
-	set	CONFIG_SYS_SPARC_NWINDOWS, %g2	!NWINDOWS
-
-	srl	%g1, %g2, %g2
-	or	%g1, %g2, %g1
-	rd	%wim, %g2
-	andcc	%g2, %g1, %g0
-	be	1f		! Nope, just return from the trap
-	 sll	%g2, 0x1, %g1
-
-	/* We have to grab a window before returning. */
-	set	(CONFIG_SYS_SPARC_NWINDOWS-1), %g3	!NWINDOWS-1
-
-	srl	%g2, %g3,  %g2
-	or	%g1, %g2, %g1
-	and	%g1, 0xff, %g1
-
-	wr	%g1, 0x0, %wim
-
-	/* Grrr, make sure we load from the right %sp... */
-	PT_LOAD_ALL(sp, t_psr, t_pc, t_npc, g1)
-
-	restore	%g0, %g0, %g0
-	RW_LOAD(sp)
-	b	2f
-	save	%g0, %g0, %g0
-
-	/* Reload the entire frame in case this is from a
-	 * kernel system call or whatever...
-	 */
-1:
-	PT_LOAD_ALL(sp, t_psr, t_pc, t_npc, g1)
-2:
-	wr	%t_psr, 0x0, %psr
-	nop;
-	nop;
-	nop
-
-	jmp	%t_pc
-	rett	%t_npc
-
-/* This is called from relocated C-code.
- * It resets the system by jumping to _start
- */
-_reset_reloc:
-	set	start, %l0
-	call	%l0
-	nop
diff --git a/arch/sparc/cpu/leon3/usb_uhci.c b/arch/sparc/cpu/leon3/usb_uhci.c
deleted file mode 100644
index 67bd124..0000000
--- a/arch/sparc/cpu/leon3/usb_uhci.c
+++ /dev/null
@@ -1,1195 +0,0 @@
-/*
- * Part of this code has been derived from linux:
- * Universal Host Controller Interface driver for USB (take II).
- *
- * (c) 1999-2001 Georg Acher, acher@in.tum.de (executive slave) (base guitar)
- *               Deti Fliegl, deti@fliegl.de (executive slave) (lead voice)
- *               Thomas Sailer, sailer@ife.ee.ethz.ch (chief consultant) (cheer leader)
- *               Roman Weissgaerber, weissg@vienna.at (virt root hub) (studio porter)
- * (c) 2000      Yggdrasil Computing, Inc. (port of new PCI interface support
- *               from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
- * (C) 2000      David Brownell, david-b@pacbell.net (usb-ohci.c)
- *
- * HW-initalization based on material of
- *
- * (C) Copyright 1999 Linus Torvalds
- * (C) Copyright 1999 Johannes Erdfelt
- * (C) Copyright 1999 Randy Dunlap
- * (C) Copyright 1999 Gregory P. Smith
- *
- *
- * Adapted for U-Boot:
- * (C) Copyright 2001 Denis Peter, MPL AG Switzerland
- * (C) Copyright 2008, Daniel Hellström, daniel@gaisler.com
- *     Added AMBA Plug&Play detection of GRUSB, modified interrupt handler.
- *     Added cache flushes where needed.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/**********************************************************************
- * How it works:
- * -------------
- * The framelist / Transfer descriptor / Queue Heads are similar like
- * in the linux usb_uhci.c.
- *
- * During initialization, the following skeleton is allocated in init_skel:
- *
- *         framespecific           |           common chain
- *
- * framelist[]
- * [  0 ]-----> TD ---------\
- * [  1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL
- *   ...        TD ---------/
- * [1023]-----> TD --------/
- *
- *              ^^             ^^         ^^          ^^          ^^
- *              7 TDs for      1 TD for   Start of    Start of    End Chain
- *              INT (2-128ms)  1ms-INT    CTRL Chain  BULK Chain
- *
- *
- * Since this is a bootloader, the isochronous transfer descriptor have been removed.
- *
- * Interrupt Transfers.
- * --------------------
- * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
- * will be inserted after the appropriate (depending the interval setting) skeleton TD.
- * If an interrupt has been detected the dev->irqhandler is called. The status and number
- * of transferred bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
- * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned,
- * the interrupt TD will be reactivated.
- *
- * Control Transfers
- * -----------------
- * Control Transfers are issued by filling the tmp_td with the appropriate data and connect
- * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued,
- * the programm has to wait for completion. This does not allows asynchronous data transfer.
- *
- * Bulk Transfers
- * --------------
- * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect
- * them to the qh_bulk queue header. Before other control/bulk transfers can be issued,
- * the programm has to wait for completion. This does not allows asynchronous data transfer.
- *
- *
- */
-
-#include <common.h>
-#include <ambapp.h>
-#include <asm/leon.h>
-#include <asm/leon3.h>
-#include <asm/processor.h>
-
-#ifdef CONFIG_USB_UHCI
-
-#include <usb.h>
-#include "usb_uhci.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define USB_MAX_TEMP_TD      128	/* number of temporary TDs for bulk and control transfers */
-#define USB_MAX_TEMP_INT_TD  32	/* number of temporary TDs for Interrupt transfers */
-
-/*
-#define out16r(address,data) (*(unsigned short *)(address) = \
- (unsigned short)( \
- (((unsigned short)(data)&0xff)<<8) | \
- (((unsigned short)(data)&0xff00)>>8) \
- ))
- */
-#define out16r(address,data) _out16r((unsigned int)(address), (unsigned short)(data))
-void _out16r(unsigned int address, unsigned short data)
-{
-	unsigned short val = (unsigned short)((((unsigned short)(data) & 0xff)
-					       << 8) | (((unsigned short)(data)
-							 & 0xff00) >> 8));
-#ifdef UHCI_DEBUG_REGS
-	printf("out16r(0x%lx,0x%04x = 0x%04x)\n", address, val, data);
-#endif
-	*(unsigned short *)(address) = val;
-}
-
-#define out32r(address,data) _out32r((unsigned int)(address), (unsigned int)(data))
-void _out32r(unsigned int address, unsigned int data)
-{
-	unsigned int val = (unsigned int)((((unsigned int)(data) & 0x000000ff)
-					   << 24) | (((unsigned int)(data) &
-						      0x0000ff00) << 8) |
-					  (((unsigned int)(data) & 0x00ff0000)
-					   >> 8) | (((unsigned int)(data) &
-						     0xff000000) >> 24));
-#ifdef UHCI_DEBUG_REGS
-	printf("out32r(0x%lx,0x%lx = 0x%lx)\n", address, val, data);
-#endif
-	*(unsigned int *)address = val;
-}
-
-#define in16r(address) _in16r((unsigned int)(address))
-unsigned short _in16r(unsigned int address)
-{
-	unsigned short val = sparc_load_reg_cachemiss_word(address);
-	val = ((val << 8) & 0xff00) | ((val >> 8) & 0xff);
-#ifdef UHCI_DEBUG_REGS
-	printf("in16r(0x%lx): 0x%04x\n", address, val);
-#endif
-	return val;
-}
-
-#define in32r(address) _in32r((unsigned int)(address))
-unsigned int _in32r(unsigned int address)
-{
-	unsigned int val = sparc_load_reg_cachemiss(address);
-	val =
-	    ((val << 24) & 0xff000000) | ((val << 8) & 0xff0000) | ((val >> 8) &
-								    0xff00) |
-	    ((val >> 24) & 0xff);
-#ifdef UHCI_DEBUG_REGS
-	printf("in32r(0x%lx): 0x%08x\n", address, val);
-#endif
-	return val;
-}
-
-#define READ32(address) sparc_load_reg_cachemiss((unsigned int)(address))
-
-/*#define USB_UHCI_DEBUG*/
-#undef USB_UHCI_DEBUG
-
-void usb_show_td(int max);
-#ifdef	USB_UHCI_DEBUG
-void grusb_show_regs(void);
-#define	USB_UHCI_PRINTF(fmt,args...)	printf (fmt ,##args)
-#else
-#define USB_UHCI_PRINTF(fmt,args...)
-#endif
-
-static int grusb_irq = -1;	/* irq vector, if -1 uhci is stopped / reseted */
-unsigned int usb_base_addr;	/* base address */
-
-static uhci_td_t td_int[8] __attribute__ ((aligned(16)));	/* Interrupt Transfer descriptors */
-static uhci_qh_t qh_cntrl __attribute__ ((aligned(16)));	/* control Queue Head */
-static uhci_qh_t qh_bulk __attribute__ ((aligned(16)));	/*  bulk Queue Head */
-static uhci_qh_t qh_end __attribute__ ((aligned(16)));	/* end Queue Head */
-static uhci_td_t td_last __attribute__ ((aligned(16)));	/* last TD (linked with end chain) */
-
-/* temporary tds */
-static uhci_td_t tmp_td[USB_MAX_TEMP_TD] __attribute__ ((aligned(16)));	/* temporary bulk/control td's  */
-static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD] __attribute__ ((aligned(16)));	/* temporary interrupt td's  */
-
-static unsigned long framelist[1024] __attribute__ ((aligned(0x1000)));	/* frame list */
-
-static struct virt_root_hub rh;	/* struct for root hub */
-
-/**********************************************************************
- * some forward decleration
- */
-int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
-		       void *buffer, int transfer_len,
-		       struct devrequest *setup);
-
-/* fill a td with the approproiate data. Link, status, info and buffer
- * are used by the USB controller itselfes, dev is used to identify the
- * "connected" device
- */
-void usb_fill_td(uhci_td_t * td, unsigned long link, unsigned long status,
-		 unsigned long info, unsigned long buffer, unsigned long dev)
-{
-	td->link = swap_32(link);
-	td->status = swap_32(status);
-	if ((info & UHCI_PID) == 0)
-		info |= USB_PID_OUT;
-	td->info = swap_32(info);
-	td->buffer = swap_32(buffer);
-	td->dev_ptr = dev;
-}
-
-/* fill a qh with the approproiate data. Head and element are used by the USB controller
- * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh.
- * Please note, that after completion of the td chain, the entry element is removed /
- * marked invalid by the USB controller.
- */
-void usb_fill_qh(uhci_qh_t * qh, unsigned long head, unsigned long element)
-{
-	qh->head = swap_32(head);
-	qh->element = swap_32(element);
-	qh->dev_ptr = 0L;
-}
-
-/* get the status of a td->status
- */
-unsigned long usb_uhci_td_stat(unsigned long status)
-{
-	unsigned long result = 0;
-	result |= (status & TD_CTRL_NAK) ? USB_ST_NAK_REC : 0;
-	result |= (status & TD_CTRL_STALLED) ? USB_ST_STALLED : 0;
-	result |= (status & TD_CTRL_DBUFERR) ? USB_ST_BUF_ERR : 0;
-	result |= (status & TD_CTRL_BABBLE) ? USB_ST_BABBLE_DET : 0;
-	result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0;
-	result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0;
-	result |= (status & TD_CTRL_ACTIVE) ? USB_ST_NOT_PROC : 0;
-	return result;
-}
-
-/* get the status and the transferred len of a td chain.
- * called from the completion handler
- */
-int usb_get_td_status(uhci_td_t * td, struct usb_device *dev)
-{
-	unsigned long temp, info;
-	unsigned long stat;
-	uhci_td_t *mytd = td;
-
-	if (dev->devnum == rh.devnum)
-		return 0;
-	dev->act_len = 0;
-	stat = 0;
-	do {
-		temp = swap_32((unsigned long)READ32(&mytd->status));
-		stat = usb_uhci_td_stat(temp);
-		info = swap_32((unsigned long)READ32(&mytd->info));
-		if (((info & 0xff) != USB_PID_SETUP) && (((info >> 21) & 0x7ff) != 0x7ff) && (temp & 0x7FF) != 0x7ff) {	/* if not setup and not null data pack */
-			dev->act_len += (temp & 0x7FF) + 1;	/* the transferred len is act_len + 1 */
-		}
-		if (stat) {	/* status no ok */
-			dev->status = stat;
-			return -1;
-		}
-		temp = swap_32((unsigned long)READ32(&mytd->link));
-		mytd = (uhci_td_t *) (temp & 0xfffffff0);
-	} while ((temp & 0x1) == 0);	/* process all TDs */
-	dev->status = stat;
-	return 0;		/* Ok */
-}
-
-/*-------------------------------------------------------------------
- *                         LOW LEVEL STUFF
- *          assembles QHs und TDs for control, bulk and iso
- *-------------------------------------------------------------------*/
-int dummy(void)
-{
-	USB_UHCI_PRINTF("DUMMY\n");
-	return 0;
-}
-
-/* Submits a control message. That is a Setup, Data and Status transfer.
- * Routine does not wait for completion.
- */
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		       int transfer_len, struct devrequest *setup)
-{
-	unsigned long destination, status;
-	int maxsze = usb_maxpacket(dev, pipe);
-	unsigned long dataptr;
-	int len;
-	int pktsze;
-	int i = 0;
-
-	if (!maxsze) {
-		USB_UHCI_PRINTF
-		    ("uhci_submit_control_urb: pipesize for pipe %lx is zero\n",
-		     pipe);
-		return -1;
-	}
-	if (((pipe >> 8) & 0x7f) == rh.devnum) {
-		/* this is the root hub -> redirect it */
-		return uhci_submit_rh_msg(dev, pipe, buffer, transfer_len,
-					  setup);
-	}
-	USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",
-			transfer_len, maxsze);
-	/* The "pipe" thing contains the destination in bits 8--18 */
-	destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP;	/* Setup stage */
-	/* 3 errors */
-	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
-	/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */
-	/*  Build the TD for the control request, try forever, 8 bytes of data */
-	usb_fill_td(&tmp_td[i], UHCI_PTR_TERM, status, destination | (7 << 21),
-		    (unsigned long)setup, (unsigned long)dev);
-#ifdef DEBUG_EXTRA
-	{
-		char *sp = (char *)setup;
-		printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe,
-		       sp[0], sp[1], sp[2], sp[3], sp[4], sp[5], sp[6], sp[7]);
-	}
-#endif
-	dataptr = (unsigned long)buffer;
-	len = transfer_len;
-
-	/* If direction is "send", change the frame from SETUP (0x2D)
-	   to OUT (0xE1). Else change it from SETUP to IN (0x69). */
-	destination =
-	    (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN) ==
-					0 ? USB_PID_OUT : USB_PID_IN);
-	while (len > 0) {
-		/* data stage */
-		pktsze = len;
-		i++;
-		if (pktsze > maxsze)
-			pktsze = maxsze;
-		destination ^= 1 << TD_TOKEN_TOGGLE;	/* toggle DATA0/1 */
-		usb_fill_td(&tmp_td[i], UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21), dataptr, (unsigned long)dev);	/* Status, pktsze bytes of data */
-		tmp_td[i - 1].link = swap_32((unsigned long)&tmp_td[i]);
-
-		dataptr += pktsze;
-		len -= pktsze;
-	}
-
-	/*  Build the final TD for control status */
-	/* It's only IN if the pipe is out AND we aren't expecting data */
-
-	destination &= ~UHCI_PID;
-	if (((pipe & USB_DIR_IN) == 0) || (transfer_len == 0))
-		destination |= USB_PID_IN;
-	else
-		destination |= USB_PID_OUT;
-	destination |= 1 << TD_TOKEN_TOGGLE;	/* End in Data1 */
-	i++;
-	status &= ~TD_CTRL_SPD;
-	/* no limit on errors on final packet , 0 bytes of data */
-	usb_fill_td(&tmp_td[i], UHCI_PTR_TERM, status | TD_CTRL_IOC,
-		    destination | (UHCI_NULL_DATA_SIZE << 21), 0,
-		    (unsigned long)dev);
-	tmp_td[i - 1].link = swap_32((unsigned long)&tmp_td[i]);	/* queue status td */
-	/* usb_show_td(i+1); */
-	USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n", i);
-	/* first mark the control QH element terminated */
-	qh_cntrl.element = 0xffffffffL;
-	/* set qh active */
-	qh_cntrl.dev_ptr = (unsigned long)dev;
-	/* fill in tmp_td_chain */
-	dummy();
-	qh_cntrl.element = swap_32((unsigned long)&tmp_td[0]);
-	return 0;
-}
-
-/*-------------------------------------------------------------------
- * Prepare TDs for bulk transfers.
- */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		    int transfer_len)
-{
-	unsigned long destination, status, info;
-	unsigned long dataptr;
-	int maxsze = usb_maxpacket(dev, pipe);
-	int len;
-	int i = 0;
-
-	if (transfer_len < 0) {
-		printf("Negative transfer length in submit_bulk\n");
-		return -1;
-	}
-	if (!maxsze)
-		return -1;
-	/* The "pipe" thing contains the destination in bits 8--18. */
-	destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid(pipe);
-	/* 3 errors */
-	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
-	/*      ((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */
-	/* Build the TDs for the bulk request */
-	len = transfer_len;
-	dataptr = (unsigned long)buffer;
-	do {
-		int pktsze = len;
-		if (pktsze > maxsze)
-			pktsze = maxsze;
-		/* pktsze bytes of data  */
-		info =
-		    destination | (((pktsze - 1) & UHCI_NULL_DATA_SIZE) << 21) |
-		    (usb_gettoggle
-		     (dev, usb_pipeendpoint(pipe),
-		      usb_pipeout(pipe)) << TD_TOKEN_TOGGLE);
-
-		if ((len - pktsze) == 0)
-			status |= TD_CTRL_IOC;	/* last one generates INT */
-
-		usb_fill_td(&tmp_td[i], UHCI_PTR_TERM, status, info, dataptr, (unsigned long)dev);	/* Status, pktsze bytes of data */
-		if (i > 0)
-			tmp_td[i - 1].link = swap_32((unsigned long)&tmp_td[i]);
-		i++;
-		dataptr += pktsze;
-		len -= pktsze;
-		usb_dotoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
-	} while (len > 0);
-	/* first mark the bulk QH element terminated */
-	qh_bulk.element = 0xffffffffL;
-	/* set qh active */
-	qh_bulk.dev_ptr = (unsigned long)dev;
-	/* fill in tmp_td_chain */
-	qh_bulk.element = swap_32((unsigned long)&tmp_td[0]);
-	return 0;
-}
-
-/* search a free interrupt td
- */
-uhci_td_t *uhci_alloc_int_td(void)
-{
-	int i;
-	for (i = 0; i < USB_MAX_TEMP_INT_TD; i++) {
-		if (tmp_int_td[i].dev_ptr == 0)	/* no device assigned -> free TD */
-			return &tmp_int_td[i];
-	}
-	return NULL;
-}
-
-/*-------------------------------------------------------------------
- * submits USB interrupt (ie. polling ;-)
- */
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		   int transfer_len, int interval)
-{
-	int nint, n;
-	unsigned long status, destination;
-	unsigned long info, tmp;
-	uhci_td_t *mytd;
-	if (interval < 0 || interval >= 256)
-		return -1;
-
-	if (interval == 0)
-		nint = 0;
-	else {
-		for (nint = 0, n = 1; nint <= 8; nint++, n += n) {	/* round interval down to 2^n */
-			if (interval < n) {
-				interval = n / 2;
-				break;
-			}
-		}
-		nint--;
-	}
-
-	USB_UHCI_PRINTF("Rounded interval to %i, chain  %i\n", interval, nint);
-	mytd = uhci_alloc_int_td();
-	if (mytd == NULL) {
-		printf("No free INT TDs found\n");
-		return -1;
-	}
-	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27);
-/*		(urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27);
-*/
-
-	destination =
-	    (pipe & PIPE_DEVEP_MASK) | usb_packetid(pipe) |
-	    (((transfer_len - 1) & 0x7ff) << 21);
-
-	info =
-	    destination |
-	    (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) <<
-	     TD_TOKEN_TOGGLE);
-	tmp = swap_32(td_int[nint].link);
-	usb_fill_td(mytd, tmp, status, info, (unsigned long)buffer,
-		    (unsigned long)dev);
-	/* Link it */
-	tmp = swap_32((unsigned long)mytd);
-	td_int[nint].link = tmp;
-
-	usb_dotoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
-
-	return 0;
-}
-
-/**********************************************************************
- * Low Level functions
- */
-
-void reset_hc(void)
-{
-
-	/* Global reset for 100ms */
-	out16r(usb_base_addr + USBPORTSC1, 0x0204);
-	out16r(usb_base_addr + USBPORTSC2, 0x0204);
-	out16r(usb_base_addr + USBCMD, USBCMD_GRESET | USBCMD_RS);
-	/* Turn off all interrupts */
-	out16r(usb_base_addr + USBINTR, 0);
-	mdelay(50);
-	out16r(usb_base_addr + USBCMD, 0);
-	mdelay(10);
-}
-
-void start_hc(void)
-{
-	int timeout = 1000;
-
-	while (in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) {
-		if (!--timeout) {
-			printf("USBCMD_HCRESET timed out!\n");
-			break;
-		}
-	}
-	/* Turn on all interrupts */
-	out16r(usb_base_addr + USBINTR,
-	       USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP);
-	/* Start at frame 0 */
-	out16r(usb_base_addr + USBFRNUM, 0);
-	/* set Framebuffer base address */
-	out32r(usb_base_addr + USBFLBASEADD, (unsigned long)&framelist);
-	/* Run and mark it configured with a 64-byte max packet */
-	out16r(usb_base_addr + USBCMD, USBCMD_RS | USBCMD_CF | USBCMD_MAXP);
-}
-
-/* Initialize the skeleton
- */
-void usb_init_skel(void)
-{
-	unsigned long temp;
-	int n;
-
-	for (n = 0; n < USB_MAX_TEMP_INT_TD; n++)
-		tmp_int_td[n].dev_ptr = 0L;	/* no devices connected */
-	/* last td */
-	usb_fill_td(&td_last, UHCI_PTR_TERM, TD_CTRL_IOC, USB_PID_OUT, 0, 0L);
-	/* usb_fill_td(&td_last,UHCI_PTR_TERM,0,0,0); */
-	/* End Queue Header */
-	usb_fill_qh(&qh_end, UHCI_PTR_TERM, (unsigned long)&td_last);
-	/* Bulk Queue Header */
-	temp = (unsigned long)&qh_end;
-	usb_fill_qh(&qh_bulk, temp | UHCI_PTR_QH, UHCI_PTR_TERM);
-	/* Control Queue Header */
-	temp = (unsigned long)&qh_bulk;
-	usb_fill_qh(&qh_cntrl, temp | UHCI_PTR_QH, UHCI_PTR_TERM);
-	/* 1ms Interrupt td */
-	temp = (unsigned long)&qh_cntrl;
-	usb_fill_td(&td_int[0], temp | UHCI_PTR_QH, 0, USB_PID_OUT, 0, 0L);
-	temp = (unsigned long)&td_int[0];
-	for (n = 1; n < 8; n++)
-		usb_fill_td(&td_int[n], temp, 0, USB_PID_OUT, 0, 0L);
-	for (n = 0; n < 1024; n++) {
-		/* link all framelist pointers to one of the interrupts */
-		int m, o;
-		if ((n & 127) == 127)
-			framelist[n] = swap_32((unsigned long)&td_int[0]);
-		else
-			for (o = 1, m = 2; m <= 128; o++, m += m)
-				if ((n & (m - 1)) == ((m - 1) / 2))
-					framelist[n] =
-					    swap_32((unsigned long)&td_int[o]);
-
-	}
-}
-
-/* check the common skeleton for completed transfers, and update the status
- * of the "connected" device. Called from the IRQ routine.
- */
-void usb_check_skel(void)
-{
-	struct usb_device *dev;
-	/* start with the control qh */
-	if (qh_cntrl.dev_ptr != 0) {	/* it's a device assigned check if this caused IRQ */
-		dev = (struct usb_device *)qh_cntrl.dev_ptr;
-		/* Flush cache now that hardware updated DATA and TDs/QHs */
-		if (!gd->arch.snooping_avail)
-			sparc_dcache_flush_all();
-		usb_get_td_status(&tmp_td[0], dev);	/* update status */
-		if (!(dev->status & USB_ST_NOT_PROC)) {	/* is not active anymore, disconnect devices */
-			qh_cntrl.dev_ptr = 0;
-		}
-	}
-	/* now process the bulk */
-	if (qh_bulk.dev_ptr != 0) {	/* it's a device assigned check if this caused IRQ */
-		dev = (struct usb_device *)qh_bulk.dev_ptr;
-		/* Flush cache now that hardware updated DATA and TDs/QHs */
-		if (!gd->arch.snooping_avail)
-			sparc_dcache_flush_all();
-		usb_get_td_status(&tmp_td[0], dev);	/* update status */
-		if (!(dev->status & USB_ST_NOT_PROC)) {	/* is not active anymore, disconnect devices */
-			qh_bulk.dev_ptr = 0;
-		}
-	}
-}
-
-/* check the interrupt chain, ubdate the status of the appropriate device,
- * call the appropriate irqhandler and reactivate the TD if the irqhandler
- * returns with 1
- */
-void usb_check_int_chain(void)
-{
-	int i, res;
-	unsigned long link, status;
-	struct usb_device *dev;
-	uhci_td_t *td, *prevtd;
-
-	for (i = 0; i < 8; i++) {
-		prevtd = &td_int[i];	/* the first previous td is the skeleton td */
-		link = swap_32(READ32(&td_int[i].link)) & 0xfffffff0;	/* next in chain */
-		td = (uhci_td_t *) link;	/* assign it */
-		/* all interrupt TDs are finally linked to the td_int[0].
-		 * so we process all until we find the td_int[0].
-		 * if int0 chain points to a QH, we're also done
-		 */
-		while (((i > 0) && (link != (unsigned long)&td_int[0])) ||
-		       ((i == 0)
-			&& !(swap_32(READ32(&td->link)) & UHCI_PTR_QH))) {
-			/* check if a device is assigned with this td */
-			status = swap_32(READ32(&td->status));
-			if ((td->dev_ptr != 0L) && !(status & TD_CTRL_ACTIVE)) {
-				/* td is not active and a device is assigned -> call irqhandler */
-				dev = (struct usb_device *)td->dev_ptr;
-				dev->irq_act_len = ((status & 0x7FF) == 0x7FF) ? 0 : (status & 0x7FF) + 1;	/* transferred length */
-				dev->irq_status = usb_uhci_td_stat(status);	/* get status */
-				res = dev->irq_handle(dev);	/* call irqhandler */
-				if (res == 1) {
-					/* reactivate */
-					status |= TD_CTRL_ACTIVE;
-					td->status = swap_32(status);
-					prevtd = td;	/* previous td = this td */
-				} else {
-					prevtd->link = READ32(&td->link);	/* link previous td directly to the nex td -> unlinked */
-					/* remove device pointer */
-					td->dev_ptr = 0L;
-				}
-			}	/* if we call the irq handler */
-			link = swap_32(READ32(&td->link)) & 0xfffffff0;	/* next in chain */
-			td = (uhci_td_t *) link;	/* assign it */
-		}		/* process all td in this int chain */
-	}			/* next interrupt chain */
-}
-
-/* usb interrupt service routine.
- */
-void handle_usb_interrupt(void)
-{
-	unsigned short status;
-	static int error = 0;
-
-	/*
-	 * Read the interrupt status, and write it back to clear the
-	 * interrupt cause
-	 */
-
-	status = in16r(usb_base_addr + USBSTS);
-
-	if (!status)		/* shared interrupt, not mine */
-		return;
-	if (status != 1) {
-		/* remove host controller halted state */
-		if ((status & (USBSTS_HCPE | USBSTS_HCH)) ==
-		    (USBSTS_HCPE | USBSTS_HCH)) {
-			/* Stop due to bug in driver, or hardware */
-			out16r(usb_base_addr + USBSTS, status);
-			out16r(usb_base_addr + USBCMD,
-			       USBCMD_HCRESET | USBCMD_GRESET);
-			printf
-			    ("GRUSB: HW detected error(s) in USB Descriptors (STS: 0x%x)\n",
-			     status);
-			usb_show_td(8);
-			return;
-		} else if ((status & 0x20)
-			   && ((in16r(usb_base_addr + USBCMD) & USBCMD_RS) ==
-			       0)) {
-			if (error < 10) {
-				out16r(usb_base_addr + USBCMD,
-				       USBCMD_RS | in16r(usb_base_addr +
-							 USBCMD));
-				error++;
-			}
-		} else
-			error = 0;
-	}
-	usb_check_int_chain();	/* call interrupt handlers for int tds */
-	usb_check_skel();	/* call completion handler for common transfer routines */
-	out16r(usb_base_addr + USBSTS, status);
-}
-
-/* init uhci
- */
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
-{
-	ambapp_ahbdev ahbdev;
-
-	/* Find GRUSB core using AMBA Plug&Play information */
-	if (ambapp_ahbslv_find(&ambapp_plb, VENDOR_GAISLER, GAISLER_UHCI,
-		CONFIG_SYS_GRLIB_GRUSB_INDEX, &ahbdev) != 1) {
-		printf("USB UHCI: Failed to find GRUSB controller\n");
-		return -1;
-	}
-	usb_base_addr = ahbdev.address[0];
-	grusb_irq = ahbdev.irq;
-	/*
-	   usb_base_addr = 0xfffa0000;
-	   grusb_irq = 10;
-	 */
-#ifdef USB_UHCI_DEBUG
-	grusb_show_regs();
-#endif
-	memset(td_int, 0, sizeof(td_int));
-	memset(tmp_td, 0, sizeof(tmp_td));
-	memset(tmp_int_td, 0, sizeof(tmp_int_td));
-	memset(&qh_cntrl, 0, sizeof(qh_cntrl));
-	memset(&qh_end, 0, sizeof(qh_end));
-	memset(&td_last, 0, sizeof(td_last));
-
-	irq_free_handler(grusb_irq);
-	USB_UHCI_PRINTF("GRUSB: at 0x%lx irq %d\n", usb_base_addr, grusb_irq);
-	rh.devnum = 0;
-	usb_init_skel();
-	reset_hc();
-	start_hc();
-	irq_install_handler(grusb_irq,
-			    (interrupt_handler_t *) handle_usb_interrupt, NULL);
-	return 0;
-}
-
-/* stop uhci
- */
-int usb_lowlevel_stop(int index)
-{
-	if (grusb_irq == -1)
-		return 1;
-	irq_free_handler(grusb_irq);
-	reset_hc();
-	grusb_irq = -1;
-	return 0;
-}
-
-/*******************************************************************************************
- * Virtual Root Hub
- * Since the uhci does not have a real HUB, we simulate one ;-)
- */
-#undef	USB_RH_DEBUG
-
-#ifdef	USB_RH_DEBUG
-#define	USB_RH_PRINTF(fmt,args...)	printf (fmt ,##args)
-static void usb_display_wValue(unsigned short wValue, unsigned short wIndex);
-static void usb_display_Req(unsigned short req);
-#else
-#define USB_RH_PRINTF(fmt,args...)
-static void usb_display_wValue(unsigned short wValue, unsigned short wIndex)
-{
-}
-static void usb_display_Req(unsigned short req)
-{
-}
-#endif
-
-#define WANT_USB_ROOT_HUB_HUB_DES
-#include <usbroothubdes.h>
-#undef WANT_USB_ROOT_HUB_HUB_DES
-
-/*
- * Root Hub Control Pipe (interrupt Pipes are not supported)
- */
-
-int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		       int transfer_len, struct devrequest *cmd)
-{
-	void *data = buffer;
-	int leni = transfer_len;
-	int len = 0;
-	int status = 0;
-	int stat = 0;
-	int i;
-
-	unsigned short cstatus;
-
-	unsigned short bmRType_bReq;
-	unsigned short wValue;
-	unsigned short wIndex;
-	unsigned short wLength;
-
-	if (usb_pipeint(pipe)) {
-		printf("Root-Hub submit IRQ: NOT implemented\n");
-		return 0;
-	}
-	bmRType_bReq = cmd->requesttype | cmd->request << 8;
-	wValue = swap_16(cmd->value);
-	wIndex = swap_16(cmd->index);
-	wLength = swap_16(cmd->length);
-	usb_display_Req(bmRType_bReq);
-	for (i = 0; i < 8; i++)
-		rh.c_p_r[i] = 0;
-	USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n",
-		      dev->devnum, 8, cmd->requesttype, cmd->request, wValue,
-		      wIndex, wLength);
-
-	switch (bmRType_bReq) {
-		/* Request Destination:
-		   without flags: Device,
-		   RH_INTERFACE: interface,
-		   RH_ENDPOINT: endpoint,
-		   RH_CLASS means HUB here,
-		   RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
-		 */
-
-	case RH_GET_STATUS:
-		*(unsigned short *)data = swap_16(1);
-		len = 2;
-		break;
-	case RH_GET_STATUS | RH_INTERFACE:
-		*(unsigned short *)data = swap_16(0);
-		len = 2;
-		break;
-	case RH_GET_STATUS | RH_ENDPOINT:
-		*(unsigned short *)data = swap_16(0);
-		len = 2;
-		break;
-	case RH_GET_STATUS | RH_CLASS:
-		*(unsigned long *)data = swap_32(0);
-		len = 4;
-		break;		/* hub power ** */
-	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
-
-		status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1));
-		cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) |
-		    ((status & USBPORTSC_PEC) >> (3 - 1)) |
-		    (rh.c_p_r[wIndex - 1] << (0 + 4));
-		status = (status & USBPORTSC_CCS) | ((status & USBPORTSC_PE) >> (2 - 1)) | ((status & USBPORTSC_SUSP) >> (12 - 2)) | ((status & USBPORTSC_PR) >> (9 - 4)) | (1 << 8) |	/* power on ** */
-		    ((status & USBPORTSC_LSDA) << (-8 + 9));
-
-		*(unsigned short *)data = swap_16(status);
-		*(unsigned short *)(data + 2) = swap_16(cstatus);
-		len = 4;
-		break;
-	case RH_CLEAR_FEATURE | RH_ENDPOINT:
-		switch (wValue) {
-		case (RH_ENDPOINT_STALL):
-			len = 0;
-			break;
-		}
-		break;
-
-	case RH_CLEAR_FEATURE | RH_CLASS:
-		switch (wValue) {
-		case (RH_C_HUB_OVER_CURRENT):
-			len = 0;	/* hub power over current ** */
-			break;
-		}
-		break;
-
-	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
-		usb_display_wValue(wValue, wIndex);
-		switch (wValue) {
-		case (RH_PORT_ENABLE):
-			status =
-			    in16r(usb_base_addr + USBPORTSC1 +
-				  2 * (wIndex - 1));
-			status = (status & 0xfff5) & ~USBPORTSC_PE;
-			out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
-			       status);
-			len = 0;
-			break;
-		case (RH_PORT_SUSPEND):
-			status =
-			    in16r(usb_base_addr + USBPORTSC1 +
-				  2 * (wIndex - 1));
-			status = (status & 0xfff5) & ~USBPORTSC_SUSP;
-			out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
-			       status);
-			len = 0;
-			break;
-		case (RH_PORT_POWER):
-			len = 0;	/* port power ** */
-			break;
-		case (RH_C_PORT_CONNECTION):
-			status =
-			    in16r(usb_base_addr + USBPORTSC1 +
-				  2 * (wIndex - 1));
-			status = (status & 0xfff5) | USBPORTSC_CSC;
-			out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
-			       status);
-			len = 0;
-			break;
-		case (RH_C_PORT_ENABLE):
-			status =
-			    in16r(usb_base_addr + USBPORTSC1 +
-				  2 * (wIndex - 1));
-			status = (status & 0xfff5) | USBPORTSC_PEC;
-			out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
-			       status);
-			len = 0;
-			break;
-		case (RH_C_PORT_SUSPEND):
-/*** WR_RH_PORTSTAT(RH_PS_PSSC); */
-			len = 0;
-			break;
-		case (RH_C_PORT_OVER_CURRENT):
-			len = 0;
-			break;
-		case (RH_C_PORT_RESET):
-			rh.c_p_r[wIndex - 1] = 0;
-			len = 0;
-			break;
-		}
-		break;
-	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
-		usb_display_wValue(wValue, wIndex);
-		switch (wValue) {
-		case (RH_PORT_SUSPEND):
-			status =
-			    in16r(usb_base_addr + USBPORTSC1 +
-				  2 * (wIndex - 1));
-			status = (status & 0xfff5) | USBPORTSC_SUSP;
-			out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
-			       status);
-			len = 0;
-			break;
-		case (RH_PORT_RESET):
-			status =
-			    in16r(usb_base_addr + USBPORTSC1 +
-				  2 * (wIndex - 1));
-			status = (status & 0xfff5) | USBPORTSC_PR;
-			out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
-			       status);
-			mdelay(10);
-			status = (status & 0xfff5) & ~USBPORTSC_PR;
-			out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
-			       status);
-			udelay(10);
-			status = (status & 0xfff5) | USBPORTSC_PE;
-			out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
-			       status);
-			mdelay(10);
-			status = (status & 0xfff5) | 0xa;
-			out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
-			       status);
-			len = 0;
-			break;
-		case (RH_PORT_POWER):
-			len = 0;	/* port power ** */
-			break;
-		case (RH_PORT_ENABLE):
-			status =
-			    in16r(usb_base_addr + USBPORTSC1 +
-				  2 * (wIndex - 1));
-			status = (status & 0xfff5) | USBPORTSC_PE;
-			out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
-			       status);
-			len = 0;
-			break;
-		}
-		break;
-
-	case RH_SET_ADDRESS:
-		rh.devnum = wValue;
-		len = 0;
-		break;
-	case RH_GET_DESCRIPTOR:
-		switch ((wValue & 0xff00) >> 8) {
-		case (0x01):	/* device descriptor */
-			i = sizeof(root_hub_config_des);
-			status = i > wLength ? wLength : i;
-			len = leni > status ? status : leni;
-			memcpy(data, root_hub_dev_des, len);
-			break;
-		case (0x02):	/* configuration descriptor */
-			i = sizeof(root_hub_config_des);
-			status = i > wLength ? wLength : i;
-			len = leni > status ? status : leni;
-			memcpy(data, root_hub_config_des, len);
-			break;
-		case (0x03):	/*string descriptors */
-			if (wValue == 0x0300) {
-				i = sizeof(root_hub_str_index0);
-				status = i > wLength ? wLength : i;
-				len = leni > status ? status : leni;
-				memcpy(data, root_hub_str_index0, len);
-				break;
-			}
-			if (wValue == 0x0301) {
-				i = sizeof(root_hub_str_index1);
-				status = i > wLength ? wLength : i;
-				len = leni > status ? status : leni;
-				memcpy(data, root_hub_str_index1, len);
-				break;
-			}
-			stat = USB_ST_STALLED;
-		}
-		break;
-
-	case RH_GET_DESCRIPTOR | RH_CLASS:
-		root_hub_hub_des[2] = 2;
-		i = sizeof(root_hub_hub_des);
-		status = i > wLength ? wLength : i;
-		len = leni > status ? status : leni;
-		memcpy(data, root_hub_hub_des, len);
-		break;
-	case RH_GET_CONFIGURATION:
-		*(unsigned char *)data = 0x01;
-		len = 1;
-		break;
-	case RH_SET_CONFIGURATION:
-		len = 0;
-		break;
-	default:
-		stat = USB_ST_STALLED;
-	}
-	USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n", stat,
-		      in16r(usb_base_addr + USBPORTSC1),
-		      in16r(usb_base_addr + USBPORTSC2));
-	dev->act_len = len;
-	dev->status = stat;
-	return stat;
-
-}
-
-/********************************************************************************
- * Some Debug Routines
- */
-
-#ifdef	USB_RH_DEBUG
-
-static void usb_display_Req(unsigned short req)
-{
-	USB_RH_PRINTF("- Root-Hub Request: ");
-	switch (req) {
-	case RH_GET_STATUS:
-		USB_RH_PRINTF("Get Status ");
-		break;
-	case RH_GET_STATUS | RH_INTERFACE:
-		USB_RH_PRINTF("Get Status Interface ");
-		break;
-	case RH_GET_STATUS | RH_ENDPOINT:
-		USB_RH_PRINTF("Get Status Endpoint ");
-		break;
-	case RH_GET_STATUS | RH_CLASS:
-		USB_RH_PRINTF("Get Status Class");
-		break;		/* hub power ** */
-	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
-		USB_RH_PRINTF("Get Status Class Others");
-		break;
-	case RH_CLEAR_FEATURE | RH_ENDPOINT:
-		USB_RH_PRINTF("Clear Feature Endpoint ");
-		break;
-	case RH_CLEAR_FEATURE | RH_CLASS:
-		USB_RH_PRINTF("Clear Feature Class ");
-		break;
-	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
-		USB_RH_PRINTF("Clear Feature Other Class ");
-		break;
-	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
-		USB_RH_PRINTF("Set Feature Other Class ");
-		break;
-	case RH_SET_ADDRESS:
-		USB_RH_PRINTF("Set Address ");
-		break;
-	case RH_GET_DESCRIPTOR:
-		USB_RH_PRINTF("Get Descriptor ");
-		break;
-	case RH_GET_DESCRIPTOR | RH_CLASS:
-		USB_RH_PRINTF("Get Descriptor Class ");
-		break;
-	case RH_GET_CONFIGURATION:
-		USB_RH_PRINTF("Get Configuration ");
-		break;
-	case RH_SET_CONFIGURATION:
-		USB_RH_PRINTF("Get Configuration ");
-		break;
-	default:
-		USB_RH_PRINTF("****UNKNOWN**** 0x%04X ", req);
-	}
-	USB_RH_PRINTF("\n");
-
-}
-
-static void usb_display_wValue(unsigned short wValue, unsigned short wIndex)
-{
-	switch (wValue) {
-	case (RH_PORT_ENABLE):
-		USB_RH_PRINTF("Root-Hub: Enable Port %d\n", wIndex);
-		break;
-	case (RH_PORT_SUSPEND):
-		USB_RH_PRINTF("Root-Hub: Suspend Port %d\n", wIndex);
-		break;
-	case (RH_PORT_POWER):
-		USB_RH_PRINTF("Root-Hub: Port Power %d\n", wIndex);
-		break;
-	case (RH_C_PORT_CONNECTION):
-		USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n", wIndex);
-		break;
-	case (RH_C_PORT_ENABLE):
-		USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n", wIndex);
-		break;
-	case (RH_C_PORT_SUSPEND):
-		USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n", wIndex);
-		break;
-	case (RH_C_PORT_OVER_CURRENT):
-		USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",
-			      wIndex);
-		break;
-	case (RH_C_PORT_RESET):
-		USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n", wIndex);
-		break;
-	default:
-		USB_RH_PRINTF("Root-Hub: unknown %x %x\n", wValue, wIndex);
-		break;
-	}
-}
-
-#endif
-
-/*#ifdef	USB_UHCI_DEBUG*/
-
-static int usb_display_td(uhci_td_t * td)
-{
-	unsigned long tmp;
-	int valid;
-
-	printf("TD at %p:\n", td);
-
-	tmp = swap_32(READ32(&td->link));
-	printf("Link points to 0x%08lX, %s first, %s, %s\n", tmp & 0xfffffff0,
-	       ((tmp & 0x4) == 0x4) ? "Depth" : "Breath",
-	       ((tmp & 0x2) == 0x2) ? "QH" : "TD",
-	       ((tmp & 0x1) == 0x1) ? "invalid" : "valid");
-	valid = ((tmp & 0x1) == 0x0);
-	tmp = swap_32(READ32(&td->status));
-	printf
-	    ("     %s %ld Errors %s %s %s \n     %s %s %s %s %s %s\n     Len 0x%lX\n",
-	     (((tmp >> 29) & 0x1) == 0x1) ? "SPD Enable" : "SPD Disable",
-	     ((tmp >> 28) & 0x3),
-	     (((tmp >> 26) & 0x1) == 0x1) ? "Low Speed" : "Full Speed",
-	     (((tmp >> 25) & 0x1) == 0x1) ? "ISO " : "",
-	     (((tmp >> 24) & 0x1) == 0x1) ? "IOC " : "",
-	     (((tmp >> 23) & 0x1) == 0x1) ? "Active " : "Inactive ",
-	     (((tmp >> 22) & 0x1) == 0x1) ? "Stalled" : "",
-	     (((tmp >> 21) & 0x1) == 0x1) ? "Data Buffer Error" : "",
-	     (((tmp >> 20) & 0x1) == 0x1) ? "Babble" : "",
-	     (((tmp >> 19) & 0x1) == 0x1) ? "NAK" : "",
-	     (((tmp >> 18) & 0x1) == 0x1) ? "Bitstuff Error" : "",
-	     (tmp & 0x7ff));
-	tmp = swap_32(READ32(&td->info));
-	printf("     MaxLen 0x%lX\n", ((tmp >> 21) & 0x7FF));
-	printf("     %sEndpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",
-	       ((tmp >> 19) & 0x1) == 0x1 ? "TOGGLE " : "", ((tmp >> 15) & 0xF),
-	       ((tmp >> 8) & 0x7F), tmp & 0xFF);
-	tmp = swap_32(READ32(&td->buffer));
-	printf("     Buffer 0x%08lX\n", tmp);
-	printf("     DEV %08lX\n", td->dev_ptr);
-	return valid;
-}
-
-void usb_show_td(int max)
-{
-	int i;
-	if (max > 0) {
-		for (i = 0; i < max; i++) {
-			usb_display_td(&tmp_td[i]);
-		}
-	} else {
-		i = 0;
-		do {
-			printf("tmp_td[%d]\n", i);
-		} while (usb_display_td(&tmp_td[i++]));
-	}
-}
-
-void grusb_show_regs(void)
-{
-	unsigned int tmp;
-
-	tmp = in16r(usb_base_addr + USBCMD);
-	printf(" USBCMD:   0x%04x\n", tmp);
-	tmp = in16r(usb_base_addr + USBSTS);
-	printf(" USBSTS:   0x%04x\n", tmp);
-	tmp = in16r(usb_base_addr + USBINTR);
-	printf(" USBINTR:   0x%04x\n", tmp);
-	tmp = in16r(usb_base_addr + USBFRNUM);
-	printf(" FRNUM:   0x%04x\n", tmp);
-	tmp = in32r(usb_base_addr + USBFLBASEADD);
-	printf(" FLBASEADD:   0x%08x\n", tmp);
-	tmp = in16r(usb_base_addr + USBSOF);
-	printf(" SOFMOD:   0x%04x\n", tmp);
-	tmp = in16r(usb_base_addr + USBPORTSC1);
-	printf(" PORTSC1:   0x%04x\n", tmp);
-}
-
-/*#endif*/
-#endif				/* CONFIG_USB_UHCI */
-
-/* EOF */
diff --git a/arch/sparc/cpu/leon3/usb_uhci.h b/arch/sparc/cpu/leon3/usb_uhci.h
deleted file mode 100644
index 034814a..0000000
--- a/arch/sparc/cpu/leon3/usb_uhci.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Note: Part of this code has been derived from linux
- */
-#ifndef _USB_UHCI_H_
-#define _USB_UHCI_H_
-
-/* Command register */
-#define USBCMD		0
-#define   USBCMD_RS       0x0001	/* Run/Stop */
-#define   USBCMD_HCRESET  0x0002	/* Host reset */
-#define   USBCMD_GRESET   0x0004	/* Global reset */
-#define   USBCMD_EGSM     0x0008	/* Global Suspend Mode */
-#define   USBCMD_FGR      0x0010	/* Force Global Resume */
-#define   USBCMD_SWDBG    0x0020	/* SW Debug mode */
-#define   USBCMD_CF       0x0040	/* Config Flag (sw only) */
-#define   USBCMD_MAXP     0x0080	/* Max Packet (0 = 32, 1 = 64) */
-
-/* Status register */
-#define USBSTS		2
-#define   USBSTS_USBINT   0x0001	/* Interrupt due to IOC */
-#define   USBSTS_ERROR    0x0002	/* Interrupt due to error */
-#define   USBSTS_RD       0x0004	/* Resume Detect */
-#define   USBSTS_HSE      0x0008	/* Host System Error - basically PCI problems */
-#define   USBSTS_HCPE     0x0010	/* Host Controller Process Error - the scripts were buggy */
-#define   USBSTS_HCH      0x0020	/* HC Halted */
-
-/* Interrupt enable register */
-#define USBINTR		4
-#define   USBINTR_TIMEOUT 0x0001	/* Timeout/CRC error enable */
-#define   USBINTR_RESUME  0x0002	/* Resume interrupt enable */
-#define   USBINTR_IOC     0x0004	/* Interrupt On Complete enable */
-#define   USBINTR_SP      0x0008	/* Short packet interrupt enable */
-
-#define USBFRNUM      6
-#define USBFLBASEADD  8
-#define USBSOF        12
-
-/* USB port status and control registers */
-#define USBPORTSC1	16
-#define USBPORTSC2	18
-#define   USBPORTSC_CCS   0x0001	/* Current Connect Status ("device present") */
-#define   USBPORTSC_CSC   0x0002	/* Connect Status Change */
-#define   USBPORTSC_PE    0x0004	/* Port Enable */
-#define   USBPORTSC_PEC   0x0008	/* Port Enable Change */
-#define   USBPORTSC_LS    0x0030	/* Line Status */
-#define   USBPORTSC_RD    0x0040	/* Resume Detect */
-#define   USBPORTSC_LSDA  0x0100	/* Low Speed Device Attached */
-#define   USBPORTSC_PR    0x0200	/* Port Reset */
-#define   USBPORTSC_SUSP  0x1000	/* Suspend */
-
-/* Legacy support register */
-#define USBLEGSUP 0xc0
-#define USBLEGSUP_DEFAULT 0x2000	/* only PIRQ enable set */
-
-#define UHCI_NULL_DATA_SIZE 0x7ff	/* for UHCI controller TD */
-#define UHCI_PID            0xff	/* PID MASK */
-
-#define UHCI_PTR_BITS       0x000F
-#define UHCI_PTR_TERM       0x0001
-#define UHCI_PTR_QH         0x0002
-#define UHCI_PTR_DEPTH      0x0004
-
-/* for TD <status>: */
-#define TD_CTRL_SPD         (1 << 29)	/* Short Packet Detect */
-#define TD_CTRL_C_ERR_MASK  (3 << 27)	/* Error Counter bits */
-#define TD_CTRL_LS          (1 << 26)	/* Low Speed Device */
-#define TD_CTRL_IOS         (1 << 25)	/* Isochronous Select */
-#define TD_CTRL_IOC         (1 << 24)	/* Interrupt on Complete */
-#define TD_CTRL_ACTIVE      (1 << 23)	/* TD Active */
-#define TD_CTRL_STALLED     (1 << 22)	/* TD Stalled */
-#define TD_CTRL_DBUFERR     (1 << 21)	/* Data Buffer Error */
-#define TD_CTRL_BABBLE      (1 << 20)	/* Babble Detected */
-#define TD_CTRL_NAK         (1 << 19)	/* NAK Received */
-#define TD_CTRL_CRCTIMEO    (1 << 18)	/* CRC/Time Out Error */
-#define TD_CTRL_BITSTUFF    (1 << 17)	/* Bit Stuff Error */
-#define TD_CTRL_ACTLEN_MASK 0x7ff	/* actual length, encoded as n - 1 */
-
-#define TD_CTRL_ANY_ERROR	(TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
-				 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
-
-#define TD_TOKEN_TOGGLE		19
-
-/* ------------------------------------------------------------------------------------
-   Virtual Root HUB
-   ------------------------------------------------------------------------------------ */
-/* destination of request */
-#define RH_INTERFACE               0x01
-#define RH_ENDPOINT                0x02
-#define RH_OTHER                   0x03
-
-#define RH_CLASS                   0x20
-#define RH_VENDOR                  0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS           0x0080
-#define RH_CLEAR_FEATURE        0x0100
-#define RH_SET_FEATURE          0x0300
-#define RH_SET_ADDRESS          0x0500
-#define RH_GET_DESCRIPTOR       0x0680
-#define RH_SET_DESCRIPTOR       0x0700
-#define RH_GET_CONFIGURATION    0x0880
-#define RH_SET_CONFIGURATION    0x0900
-#define RH_GET_STATE            0x0280
-#define RH_GET_INTERFACE        0x0A80
-#define RH_SET_INTERFACE        0x0B00
-#define RH_SYNC_FRAME           0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP               0x2000
-
-/* Hub port features */
-#define RH_PORT_CONNECTION         0x00
-#define RH_PORT_ENABLE             0x01
-#define RH_PORT_SUSPEND            0x02
-#define RH_PORT_OVER_CURRENT       0x03
-#define RH_PORT_RESET              0x04
-#define RH_PORT_POWER              0x08
-#define RH_PORT_LOW_SPEED          0x09
-#define RH_C_PORT_CONNECTION       0x10
-#define RH_C_PORT_ENABLE           0x11
-#define RH_C_PORT_SUSPEND          0x12
-#define RH_C_PORT_OVER_CURRENT     0x13
-#define RH_C_PORT_RESET            0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER       0x00
-#define RH_C_HUB_OVER_CURRENT      0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP    0x00
-#define RH_ENDPOINT_STALL          0x01
-
-/* Our Vendor Specific feature */
-#define RH_REMOVE_EP               0x00
-
-#define RH_ACK                     0x01
-#define RH_REQ_ERR                 -1
-#define RH_NACK                    0x00
-
-/* Transfer descriptor structure */
-typedef struct {
-	unsigned long link;	/* next td/qh (LE) */
-	unsigned long status;	/* status of the td */
-	unsigned long info;	/* Max Lenght / Endpoint / device address and PID */
-	unsigned long buffer;	/* pointer to data buffer (LE) */
-	unsigned long dev_ptr;	/* pointer to the assigned device (BE) */
-	unsigned long res[3];	/* reserved (TDs must be 8Byte aligned) */
-} uhci_td_t, *puhci_td_t;
-
-/* Queue Header structure */
-typedef struct {
-	unsigned long head;	/* Next QH (LE) */
-	unsigned long element;	/* Queue element pointer (LE) */
-	unsigned long res[5];	/* reserved */
-	unsigned long dev_ptr;	/* if 0 no tds have been assigned to this qh */
-} uhci_qh_t, *puhci_qh_t;
-
-struct virt_root_hub {
-	int devnum;		/* Address of Root Hub endpoint */
-	int numports;		/* number of ports */
-	int c_p_r[8];		/* C_PORT_RESET */
-};
-
-#endif				/* _USB_UHCI_H_ */
diff --git a/arch/sparc/cpu/u-boot.lds b/arch/sparc/cpu/u-boot.lds
deleted file mode 100644
index 1ade3b3..0000000
--- a/arch/sparc/cpu/u-boot.lds
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
-	. = + SIZEOF_HEADERS;
-	.interp : { *(.interp) }
-	.hash          : { *(.hash) }
-	.dynsym        : { *(.dynsym) }
-	.dynstr        : { *(.dynstr) }
-	.rel.text      : { *(.rel.text) }
-	.rela.text     : { *(.rela.text) }
-	.rel.data      : { *(.rel.data) }
-	.rela.data     : { *(.rela.data) }
-	.rel.rodata    : { *(.rel.rodata) }
-	.rela.rodata   : { *(.rela.rodata) }
-	.rel.got       : { *(.rel.got) }
-	.rela.got      : { *(.rela.got) }
-	.rel.ctors     : { *(.rel.ctors) }
-	.rela.ctors    : { *(.rela.ctors) }
-	.rel.dtors     : { *(.rel.dtors) }
-	.rela.dtors    : { *(.rela.dtors) }
-	.rel.bss       : { *(.rel.bss) }
-	.rela.bss      : { *(.rela.bss) }
-	.rel.plt       : { *(.rel.plt) }
-	.rela.plt      : { *(.rela.plt) }
-	.init          : { *(.init) }
-	.plt : { *(.plt) }
-
-	.text : {
-		_load_addr = .;
-		_text = .;
-
-		*(.start)
-		*/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
-		. = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
-		__prom_start = .;
-		*(.prom.pgt)
-		*(.prom.data)
-		*(.prom.text)
-		. = ALIGN(16);
-		__prom_end = .;
-		*(.text)
-		*(.fixup)
-		*(.gnu.warning)
-/*		*(.got1)*/
-		. = ALIGN(16);
-		*(.eh_frame)
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-	. = ALIGN(4);
-	_etext = .;
-
-	/* CMD Table */
-
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	.data	:
-	{
-		*(.data)
-		*(.data1)
-		*(.data.rel)
-		*(.data.rel.*)
-		*(.sdata)
-		*(.sdata2)
-		*(.dynamic)
-		CONSTRUCTORS
-	}
-	_edata	=	.;
-	PROVIDE (edata = .);
-
-	. = ALIGN(4);
-	__got_start = .;
-	.got : {
-		*(.got)
-/*		*(.data.rel)
-		*(.data.rel.local)*/
-		. = ALIGN(16);
-	}
-	__got_end = .;
-
-/*	.data.rel : { } */
-
-
-	. = ALIGN(4096);
-	__init_begin = .;
-	.text.init : { *(.text.init) }
-	.data.init : { *(.data.init) }
-	. = ALIGN(4096);
-	__init_end = .;
-
-	__bss_start = .;
-	.bss	:
-	{
-	 *(.sbss) *(.scommon)
-	 *(.dynbss)
-	 *(.bss)
-	 *(COMMON)
-	. = ALIGN(16); /* to speed clearing of bss up */
-	}
-	__bss_end = . ;
-	__bss_end = . ;
-	PROVIDE (end = .);
-
-/* Relocated into main memory */
-
-	/* Start of main memory */
-	/*. = 0x40000000;*/
-
-	.stack (NOLOAD)	: { *(.stack) }
-
-	/* PROM CODE */
-
-	/* global data in RAM passed to kernel after booting */
-
-
-	.stab 0		: { *(.stab) }
-	.stabstr 0		: { *(.stabstr) }
-	.stab.excl 0		: { *(.stab.excl) }
-	.stab.exclstr 0	: { *(.stab.exclstr) }
-	.stab.index 0		: { *(.stab.index) }
-	.stab.indexstr 0	: { *(.stab.indexstr) }
-	.comment 0		: { *(.comment) }
-
-}
diff --git a/arch/sparc/include/asm/arch-leon2/asi.h b/arch/sparc/include/asm/arch-leon2/asi.h
deleted file mode 100644
index 045bd77..0000000
--- a/arch/sparc/include/asm/arch-leon2/asi.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* asi.h:  Address Space Identifier values for the LEON2 sparc.
- *
- * Copyright (C) 2008 Daniel Hellstrom (daniel@gaisler.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _LEON2_ASI_H
-#define _LEON2_ASI_H
-
-#define ASI_CACHEMISS		0x01	/* Force D-Cache miss on load (lda) */
-#define ASI_M_FLUSH_PROBE	0x03	/* MMU Flush/Probe */
-#define ASI_IFLUSH		0x05	/* Flush I-Cache */
-#define ASI_DFLUSH		0x06	/* Flush D-Cache */
-#define ASI_BYPASS		0x1c	/* Bypass MMU (Physical address) */
-#define ASI_MMUFLUSH		0x18	/* FLUSH TLB */
-#define ASI_M_MMUREGS		0x19	/* READ/Write MMU Registers */
-
-#endif	/* _LEON2_ASI_H */
diff --git a/arch/sparc/include/asm/arch-leon3/asi.h b/arch/sparc/include/asm/arch-leon3/asi.h
deleted file mode 100644
index 61ffcc4..0000000
--- a/arch/sparc/include/asm/arch-leon3/asi.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* asi.h:  Address Space Identifier values for the LEON3 sparc.
- *
- * Copyright (C) 2008 Daniel Hellstrom (daniel@gaisler.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _LEON3_ASI_H
-#define _LEON3_ASI_H
-
-#define ASI_CACHEMISS		0x01	/* Force D-Cache miss on load (lda) */
-#define ASI_M_FLUSH_PROBE	0x03	/* MMU Flush/Probe */
-#define ASI_IFLUSH		0x10	/* Flush I-Cache */
-#define ASI_DFLUSH		0x11	/* Flush D-Cache */
-#define ASI_BYPASS		0x1c	/* Bypass MMU (Physical address) */
-#define ASI_MMUFLUSH		0x18	/* FLUSH TLB */
-#define ASI_M_MMUREGS		0x19	/* READ/Write MMU Registers */
-
-#endif	/* _LEON3_ASI_H */
diff --git a/arch/sparc/include/asm/asi.h b/arch/sparc/include/asm/asi.h
deleted file mode 100644
index 16942f4..0000000
--- a/arch/sparc/include/asm/asi.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Address Space Identifier (ASI) values for sparc processors.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SPARC_ASI_H
-#define _SPARC_ASI_H
-
-/* ASI numbers are processor implementation specific */
-#include <asm/arch/asi.h>
-
-#endif	/* _SPARC_ASI_H */
diff --git a/arch/sparc/include/asm/asmmacro.h b/arch/sparc/include/asm/asmmacro.h
deleted file mode 100644
index 653f2e4..0000000
--- a/arch/sparc/include/asm/asmmacro.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Assembler macros for SPARC
- *
- * (C) Copyright 2007, taken from linux asm-sparc/asmmacro.h
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SPARC_ASMMACRO_H__
-#define __SPARC_ASMMACRO_H__
-
-#include <config.h>
-
-/* All trap entry points _must_ begin with this macro or else you
- * lose.  It makes sure the kernel has a proper window so that
- * c-code can be called.
- */
-#define SAVE_ALL_HEAD \
-	sethi	%hi(trap_setup+(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE)), %l4; \
-	jmpl	%l4 + %lo(trap_setup+(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE)), %l6;
-#define SAVE_ALL \
-	SAVE_ALL_HEAD \
-	nop;
-
-/* All traps low-level code here must end with this macro. */
-#define RESTORE_ALL b ret_trap_entry; clr %l6;
-
-#endif
diff --git a/arch/sparc/include/asm/atomic.h b/arch/sparc/include/asm/atomic.h
deleted file mode 100644
index 35236d0..0000000
--- a/arch/sparc/include/asm/atomic.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPARC atomic operations
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_SPARC_ATOMIC_H_
-#define _ASM_SPARC_ATOMIC_H_
-
-#endif	/* _ASM_SPARC_ATOMIC_H_ */
diff --git a/arch/sparc/include/asm/bitops.h b/arch/sparc/include/asm/bitops.h
deleted file mode 100644
index c66f730..0000000
--- a/arch/sparc/include/asm/bitops.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Bit string operations on the SPARC
- *
- * (C) Copyright 2007, taken from asm-ppc/bitops.h
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SPARC_BITOPS_H
-#define _SPARC_BITOPS_H
-
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/__ffs.h>
-
-#endif				/* _SPARC_BITOPS_H */
diff --git a/arch/sparc/include/asm/byteorder.h b/arch/sparc/include/asm/byteorder.h
deleted file mode 100644
index bdc5e63..0000000
--- a/arch/sparc/include/asm/byteorder.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SPARC_BYTEORDER_H
-#define _SPARC_BYTEORDER_H
-
-#include <asm/types.h>
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-#define __BYTEORDER_HAS_U64__
-#define __SWAB_64_THRU_32__
-#endif
-#include <linux/byteorder/big_endian.h>
-#endif				/* _SPARC_BYTEORDER_H */
diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h
deleted file mode 100644
index d9671d1..0000000
--- a/arch/sparc/include/asm/cache.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * (C) Copyright 2008,
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SPARC_CACHE_H__
-#define __SPARC_CACHE_H__
-
-#include <asm/processor.h>
-
-/*
- * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment.  Otherwise
- * use 32-bytes, the cacheline size for Sparc.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN	32
-#endif
-
-#endif
diff --git a/arch/sparc/include/asm/config.h b/arch/sparc/include/asm/config.h
deleted file mode 100644
index 455fbc1..0000000
--- a/arch/sparc/include/asm/config.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright 2015,
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_CONFIG_H_
-#define _ASM_CONFIG_H_
-
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
-#define CONFIG_NEEDS_MANUAL_RELOC
-
-#define CONFIG_LMB
-#define CONFIG_SYS_BOOT_RAMDISK_HIGH
-
-#define CONFIG_SYS_TIMER_RATE		1000000		/* 1MHz */
-#define CONFIG_SYS_TIMER_COUNTER	gd->arch.timer
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-
-#endif
diff --git a/arch/sparc/include/asm/global_data.h b/arch/sparc/include/asm/global_data.h
deleted file mode 100644
index af38d17..0000000
--- a/arch/sparc/include/asm/global_data.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * (C) Copyright 2002-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham, Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef	__ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-
-#include "asm/types.h"
-
-/* Architecture-specific global data */
-struct arch_global_data {
-	void *timer;
-	void *uart;
-	unsigned int uart_freq;
-#ifdef CONFIG_LEON3
-	unsigned int snooping_available;
-#endif
-};
-
-#include <asm-generic/global_data.h>
-
-#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("%g7")
-
-#endif				/* __ASM_GBL_DATA_H */
diff --git a/arch/sparc/include/asm/io.h b/arch/sparc/include/asm/io.h
deleted file mode 100644
index a317d13..0000000
--- a/arch/sparc/include/asm/io.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPARC I/O definitions
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SPARC_IO_H
-#define _SPARC_IO_H
-
-/* Nothing to sync, total store ordering (TSO)... */
-#define sync()
-
-/*
- * Generic virtual read/write.
- */
-
-#ifndef CONFIG_SYS_HAS_NO_CACHE
-
-/* Forces a cache miss on read/load.
- * On some architectures we need to bypass the cache when reading
- * I/O registers so that we are not reading the same status word
- * over and over again resulting in a hang (until an IRQ if lucky)
- */
-
-#define __arch_getb(a)		SPARC_NOCACHE_READ_BYTE((unsigned int)(a))
-#define __arch_getw(a)		SPARC_NOCACHE_READ_HWORD((unsigned int)(a))
-#define __arch_getl(a)		SPARC_NOCACHE_READ((unsigned int)(a))
-#define __arch_getq(a)		SPARC_NOCACHE_READ_DWORD((unsigned int)(a))
-
-#else
-
-#define __arch_getb(a)		(*(volatile unsigned char *)(a))
-#define __arch_getw(a)		(*(volatile unsigned short *)(a))
-#define __arch_getl(a)		(*(volatile unsigned int *)(a))
-#define __arch_getq(a)		(*(volatile unsigned long long *)(a))
-
-#endif /* CONFIG_SYS_HAS_NO_CACHE */
-
-#define __arch_putb(v, a)	(*(volatile unsigned char *)(a) = (v))
-#define __arch_putw(v, a)	(*(volatile unsigned short *)(a) = (v))
-#define __arch_putl(v, a)	(*(volatile unsigned int *)(a) = (v))
-#define __arch_putq(v, a)	(*(volatile unsigned long long *)(a) = (v))
-
-#define __raw_writeb(v, a)		__arch_putb(v, a)
-#define __raw_writew(v, a)		__arch_putw(v, a)
-#define __raw_writel(v, a)		__arch_putl(v, a)
-#define __raw_writeq(v, a)		__arch_putq(v, a)
-
-#define __raw_readb(a)			__arch_getb(a)
-#define __raw_readw(a)			__arch_getw(a)
-#define __raw_readl(a)			__arch_getl(a)
-#define __raw_readq(a)			__arch_getq(a)
-
-#define writeb				__raw_writeb
-#define writew				__raw_writew
-#define writel				__raw_writel
-#define writeq				__raw_writeq
-
-#define readb				__raw_readb
-#define readw				__raw_readw
-#define readl				__raw_readl
-#define readq				__raw_readq
-
-/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
- */
-
-#define MAP_NOCACHE	(0)
-#define MAP_WRCOMBINE	(0)
-#define MAP_WRBACK	(0)
-#define MAP_WRTHROUGH	(0)
-
-static inline void *map_physmem(phys_addr_t paddr, unsigned long len,
-				unsigned long flags)
-{
-	return (void *)paddr;
-}
-
-/*
- * Take down a mapping set up by map_physmem().
- */
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-
-}
-
-static inline phys_addr_t virt_to_phys(void * vaddr)
-{
-	return (phys_addr_t)(vaddr);
-}
-
-#endif
diff --git a/arch/sparc/include/asm/irq.h b/arch/sparc/include/asm/irq.h
deleted file mode 100644
index 5d0f756..0000000
--- a/arch/sparc/include/asm/irq.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* IRQ functions
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SPARC_IRQ_H__
-#define __SPARC_IRQ_H__
-
-#include <asm/psr.h>
-
-/* Set SPARC Processor Interrupt Level */
-static inline void set_pil(unsigned int level)
-{
-	unsigned int psr = get_psr();
-
-	put_psr((psr & ~PSR_PIL) | ((level & 0xf) << PSR_PIL_OFS));
-}
-
-/* Get SPARC Processor Interrupt Level */
-static inline unsigned int get_pil(void)
-{
-	unsigned int psr = get_psr();
-	return (psr & PSR_PIL) >> PSR_PIL_OFS;
-}
-
-/* Disables interrupts and return current PIL value */
-extern int intLock(void);
-
-/* Sets the PIL to oldLevel */
-extern void intUnlock(int oldLevel);
-
-/* Return non-zero if interrupts are currently enabled */
-extern int interrupt_is_enabled(void);
-
-#endif
diff --git a/arch/sparc/include/asm/leon.h b/arch/sparc/include/asm/leon.h
deleted file mode 100644
index cc7c7f3..0000000
--- a/arch/sparc/include/asm/leon.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* LEON Header File select
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_LEON_H__
-#define __ASM_LEON_H__
-
-#if defined(CONFIG_LEON3)
-
-#include <asm/leon3.h>
-
-#elif defined(CONFIG_LEON2)
-
-#include <asm/leon2.h>
-
-#else
-
-#error Unknown LEON processor
-
-#endif
-
-/* Common stuff */
-
-#endif
diff --git a/arch/sparc/include/asm/leon2.h b/arch/sparc/include/asm/leon2.h
deleted file mode 100644
index ffac0de..0000000
--- a/arch/sparc/include/asm/leon2.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/* LEON2 header file. LEON2 is a SOC processor.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __LEON2_H__
-#define __LEON2_H__
-
-#ifdef CONFIG_LEON2
-
-/* LEON 2 I/O register definitions */
-#define LEON2_PREGS	0x80000000
-#define LEON2_MCFG1	0x00
-#define LEON2_MCFG2	0x04
-#define LEON2_ECTRL	0x08
-#define LEON2_FADDR	0x0C
-#define LEON2_MSTAT	0x10
-#define LEON2_CCTRL	0x14
-#define LEON2_PWDOWN	0x18
-#define LEON2_WPROT1	0x1C
-#define LEON2_WPROT2	0x20
-#define LEON2_LCONF	0x24
-#define LEON2_TCNT0	0x40
-#define LEON2_TRLD0	0x44
-#define LEON2_TCTRL0	0x48
-#define LEON2_TCNT1	0x50
-#define LEON2_TRLD1	0x54
-#define LEON2_TCTRL1	0x58
-#define LEON2_SCNT	0x60
-#define LEON2_SRLD	0x64
-#define LEON2_UART0	0x70
-#define LEON2_UDATA0	0x70
-#define LEON2_USTAT0	0x74
-#define LEON2_UCTRL0	0x78
-#define LEON2_USCAL0	0x7C
-#define LEON2_UART1	0x80
-#define LEON2_UDATA1	0x80
-#define LEON2_USTAT1	0x84
-#define LEON2_UCTRL1	0x88
-#define LEON2_USCAL1	0x8C
-#define LEON2_IMASK	0x90
-#define LEON2_IPEND	0x94
-#define LEON2_IFORCE	0x98
-#define LEON2_ICLEAR	0x9C
-#define LEON2_IOREG	0xA0
-#define LEON2_IODIR	0xA4
-#define LEON2_IOICONF	0xA8
-#define LEON2_IPEND2	0xB0
-#define LEON2_IMASK2	0xB4
-#define LEON2_ISTAT2	0xB8
-#define LEON2_ICLEAR2	0xBC
-
-#ifndef __ASSEMBLER__
-/*
- *  Structure for LEON memory mapped registers.
- *
- *  Source: Section 6.1 - On-chip registers
- *
- *  NOTE:  There is only one of these structures per CPU, its base address
- *         is 0x80000000, and the variable LEON_REG is placed there by the
- *         linkcmds file.
- */
-typedef struct {
-	volatile unsigned int Memory_Config_1;
-	volatile unsigned int Memory_Config_2;
-	volatile unsigned int Edac_Control;
-	volatile unsigned int Failed_Address;
-	volatile unsigned int Memory_Status;
-	volatile unsigned int Cache_Control;
-	volatile unsigned int Power_Down;
-	volatile unsigned int Write_Protection_1;
-	volatile unsigned int Write_Protection_2;
-	volatile unsigned int Leon_Configuration;
-	volatile unsigned int dummy2;
-	volatile unsigned int dummy3;
-	volatile unsigned int dummy4;
-	volatile unsigned int dummy5;
-	volatile unsigned int dummy6;
-	volatile unsigned int dummy7;
-	volatile unsigned int Timer_Counter_1;
-	volatile unsigned int Timer_Reload_1;
-	volatile unsigned int Timer_Control_1;
-	volatile unsigned int Watchdog;
-	volatile unsigned int Timer_Counter_2;
-	volatile unsigned int Timer_Reload_2;
-	volatile unsigned int Timer_Control_2;
-	volatile unsigned int dummy8;
-	volatile unsigned int Scaler_Counter;
-	volatile unsigned int Scaler_Reload;
-	volatile unsigned int dummy9;
-	volatile unsigned int dummy10;
-	volatile unsigned int UART_Channel_1;
-	volatile unsigned int UART_Status_1;
-	volatile unsigned int UART_Control_1;
-	volatile unsigned int UART_Scaler_1;
-	volatile unsigned int UART_Channel_2;
-	volatile unsigned int UART_Status_2;
-	volatile unsigned int UART_Control_2;
-	volatile unsigned int UART_Scaler_2;
-	volatile unsigned int Interrupt_Mask;
-	volatile unsigned int Interrupt_Pending;
-	volatile unsigned int Interrupt_Force;
-	volatile unsigned int Interrupt_Clear;
-	volatile unsigned int PIO_Data;
-	volatile unsigned int PIO_Direction;
-	volatile unsigned int PIO_Interrupt;
-} LEON2_regs;
-
-typedef struct {
-	volatile unsigned int UART_Channel;
-	volatile unsigned int UART_Status;
-	volatile unsigned int UART_Control;
-	volatile unsigned int UART_Scaler;
-} LEON2_Uart_regs;
-
-#endif
-
-/*
- *  The following constants are intended to be used ONLY in assembly
- *  language files.
- *
- *  NOTE:  The intended style of usage is to load the address of LEON REGS
- *         into a register and then use these as displacements from
- *         that register.
- */
-#define  LEON_REG_MEMCFG1_OFFSET                                  0x00
-#define  LEON_REG_MEMCFG2_OFFSET                                  0x04
-#define  LEON_REG_EDACCTRL_OFFSET                                 0x08
-#define  LEON_REG_FAILADDR_OFFSET                                 0x0C
-#define  LEON_REG_MEMSTATUS_OFFSET                                0x10
-#define  LEON_REG_CACHECTRL_OFFSET                                0x14
-#define  LEON_REG_POWERDOWN_OFFSET                                0x18
-#define  LEON_REG_WRITEPROT1_OFFSET                               0x1C
-#define  LEON_REG_WRITEPROT2_OFFSET                               0x20
-#define  LEON_REG_LEONCONF_OFFSET                                 0x24
-#define  LEON_REG_UNIMPLEMENTED_2_OFFSET                          0x28
-#define  LEON_REG_UNIMPLEMENTED_3_OFFSET                          0x2C
-#define  LEON_REG_UNIMPLEMENTED_4_OFFSET                          0x30
-#define  LEON_REG_UNIMPLEMENTED_5_OFFSET                          0x34
-#define  LEON_REG_UNIMPLEMENTED_6_OFFSET                          0x38
-#define  LEON_REG_UNIMPLEMENTED_7_OFFSET                          0x3C
-#define  LEON_REG_TIMERCNT1_OFFSET                                0x40
-#define  LEON_REG_TIMERLOAD1_OFFSET                               0x44
-#define  LEON_REG_TIMERCTRL1_OFFSET                               0x48
-#define  LEON_REG_WDOG_OFFSET                                     0x4C
-#define  LEON_REG_TIMERCNT2_OFFSET                                0x50
-#define  LEON_REG_TIMERLOAD2_OFFSET                               0x54
-#define  LEON_REG_TIMERCTRL2_OFFSET                               0x58
-#define  LEON_REG_UNIMPLEMENTED_8_OFFSET                          0x5C
-#define  LEON_REG_SCALERCNT_OFFSET                                0x60
-#define  LEON_REG_SCALER_LOAD_OFFSET                              0x64
-#define  LEON_REG_UNIMPLEMENTED_9_OFFSET                          0x68
-#define  LEON_REG_UNIMPLEMENTED_10_OFFSET                         0x6C
-#define  LEON_REG_UARTDATA1_OFFSET                                0x70
-#define  LEON_REG_UARTSTATUS1_OFFSET                              0x74
-#define  LEON_REG_UARTCTRL1_OFFSET                                0x78
-#define  LEON_REG_UARTSCALER1_OFFSET                              0x7C
-#define  LEON_REG_UARTDATA2_OFFSET                                0x80
-#define  LEON_REG_UARTSTATUS2_OFFSET                              0x84
-#define  LEON_REG_UARTCTRL2_OFFSET                                0x88
-#define  LEON_REG_UARTSCALER2_OFFSET                              0x8C
-#define  LEON_REG_IRQMASK_OFFSET                                  0x90
-#define  LEON_REG_IRQPEND_OFFSET                                  0x94
-#define  LEON_REG_IRQFORCE_OFFSET                                 0x98
-#define  LEON_REG_IRQCLEAR_OFFSET                                 0x9C
-#define  LEON_REG_PIODATA_OFFSET                                  0xA0
-#define  LEON_REG_PIODIR_OFFSET                                   0xA4
-#define  LEON_REG_PIOIRQ_OFFSET                                   0xA8
-#define  LEON_REG_SIM_RAM_SIZE_OFFSET                             0xF4
-#define  LEON_REG_SIM_ROM_SIZE_OFFSET                             0xF8
-
-/*
- *  Interrupt Sources
- *
- *  The interrupt source numbers directly map to the trap type and to
- *  the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
- *  and the Interrupt Pending Registers.
- */
-#define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR	1
-#define LEON_INTERRUPT_UART_1_RX_TX		2
-#define LEON_INTERRUPT_UART_0_RX_TX		3
-#define LEON_INTERRUPT_EXTERNAL_0		4
-#define LEON_INTERRUPT_EXTERNAL_1		5
-#define LEON_INTERRUPT_EXTERNAL_2		6
-#define LEON_INTERRUPT_EXTERNAL_3		7
-#define LEON_INTERRUPT_TIMER1			8
-#define LEON_INTERRUPT_TIMER2			9
-#define LEON_INTERRUPT_EMPTY1			10
-#define LEON_INTERRUPT_EMPTY2			11
-#define LEON_INTERRUPT_OPEN_ETH			12
-#define LEON_INTERRUPT_EMPTY4			13
-#define LEON_INTERRUPT_EMPTY5			14
-#define LEON_INTERRUPT_EMPTY6			15
-
-/* Timer Bits */
-#define LEON2_TIMER_CTRL_EN	0x1	/* Timer enable */
-#define LEON2_TIMER_CTRL_RS	0x2	/* Timer reStart  */
-#define LEON2_TIMER_CTRL_LD	0x4	/* Timer reLoad */
-#define LEON2_TIMER1_IRQNO	8	/* Timer 1 IRQ number */
-#define LEON2_TIMER2_IRQNO	9	/* Timer 2 IRQ number */
-#define LEON2_TIMER1_IE		(1<<LEON2_TIMER1_IRQNO)	/* Timer 1 interrupt enable */
-#define LEON2_TIMER2_IE		(1<<LEON2_TIMER2_IRQNO)	/* Timer 2 interrupt enable */
-
-/* UART bits */
-#define LEON2_UART_CTRL_RE	1	/* UART Receiver enable */
-#define LEON2_UART_CTRL_TE	2	/* UART Transmitter enable */
-#define LEON2_UART_CTRL_RI	4	/* UART Receiver Interrupt enable */
-#define LEON2_UART_CTRL_TI	8	/* UART Transmitter Interrupt enable */
-#define LEON2_UART_CTRL_DBG (1<<11)	/* Debug Bit used by GRMON */
-
-#define LEON2_UART_STAT_DR	1	/* UART Data Ready */
-#define LEON2_UART_STAT_TSE	2	/* UART Transmit Shift Reg empty */
-#define LEON2_UART_STAT_THE	4	/* UART Transmit Hold Reg empty */
-
-#else
-#error Include LEON2 header file only if LEON2 processor
-#endif
-
-#endif
diff --git a/arch/sparc/include/asm/leon3.h b/arch/sparc/include/asm/leon3.h
deleted file mode 100644
index a9f32b9..0000000
--- a/arch/sparc/include/asm/leon3.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* LEON3 header file. LEON3 is a free GPL SOC processor available
- * at www.gaisler.com.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __LEON3_H__
-#define __LEON3_H__
-
-#ifndef CONFIG_LEON3
-#error Include LEON3 header file only if LEON3 processor
-#endif
-
-/* Not much to define, most is Plug and Play and GRLIB dependent
- * not LEON3 dependent. See <ambapp.h> for GRLIB timers, interrupt
- * ctrl, memory controllers etc.
- */
-
-
-#ifndef __ASSEMBLER__
-/* The frequency of the CPU */
-extern unsigned int leon_cpu_freq;
-
-/* Number of LEON processors in system */
-extern int leon_cpu_cnt;
-
-/* Ver/subversion of CPU */
-extern int leon_ver;
-
-#endif /* __ASSEMBLER__ */
-
-#endif
diff --git a/arch/sparc/include/asm/linkage.h b/arch/sparc/include/asm/linkage.h
deleted file mode 100644
index e69de29..0000000
--- a/arch/sparc/include/asm/linkage.h
+++ /dev/null
diff --git a/arch/sparc/include/asm/machines.h b/arch/sparc/include/asm/machines.h
deleted file mode 100644
index e209f3f..0000000
--- a/arch/sparc/include/asm/machines.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* machines.h:  Defines for taking apart the machine type value in the
- *              idprom and determining the kind of machine we are on.
- *
- * Taken from the SPARC port of Linux.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 2007 Daniel Hellstrom (daniel@gaisler.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SPARC_MACHINES_H__
-#define __SPARC_MACHINES_H__
-
-struct Sun_Machine_Models {
-	char *name;
-	unsigned char id_machtype;
-};
-
-/* Current number of machines we know about that has an IDPROM
- * machtype entry including one entry for the 0x80 OBP machines.
- */
-#define NUM_SUN_MACHINES   16
-
-extern struct Sun_Machine_Models Sun_Machines[NUM_SUN_MACHINES];
-
-/* The machine type in the idprom area looks like this:
- *
- * ---------------
- * | ARCH | MACH |
- * ---------------
- *  7    4 3    0
- *
- * The ARCH field determines the architecture line (sun4, sun4c, etc).
- * The MACH field determines the machine make within that architecture.
- */
-
-#define SM_ARCH_MASK  0xf0
-#define SM_SUN4       0x20
-#define  M_LEON2      0x30
-#define SM_SUN4C      0x50
-#define SM_SUN4M      0x70
-#define SM_SUN4M_OBP  0x80
-
-#define SM_TYP_MASK   0x0f
-/* Sun4 machines */
-#define SM_4_260      0x01	/* Sun 4/200 series */
-#define SM_4_110      0x02	/* Sun 4/100 series */
-#define SM_4_330      0x03	/* Sun 4/300 series */
-#define SM_4_470      0x04	/* Sun 4/400 series */
-
-/* Leon machines */
-#define M_LEON2_SOC   0x01	/* Leon2 SoC */
-
-/* Sun4c machines                Full Name              - PROM NAME */
-#define SM_4C_SS1     0x01	/* Sun4c SparcStation 1   - Sun 4/60  */
-#define SM_4C_IPC     0x02	/* Sun4c SparcStation IPC - Sun 4/40  */
-#define SM_4C_SS1PLUS 0x03	/* Sun4c SparcStation 1+  - Sun 4/65  */
-#define SM_4C_SLC     0x04	/* Sun4c SparcStation SLC - Sun 4/20  */
-#define SM_4C_SS2     0x05	/* Sun4c SparcStation 2   - Sun 4/75  */
-#define SM_4C_ELC     0x06	/* Sun4c SparcStation ELC - Sun 4/25  */
-#define SM_4C_IPX     0x07	/* Sun4c SparcStation IPX - Sun 4/50  */
-
-/* Sun4m machines, these predate the OpenBoot.  These values only mean
- * something if the value in the ARCH field is SM_SUN4M, if it is
- * SM_SUN4M_OBP then you have the following situation:
- * 1) You either have a sun4d, a sun4e, or a recently made sun4m.
- * 2) You have to consult OpenBoot to determine which machine this is.
- */
-#define SM_4M_SS60    0x01	/* Sun4m SparcSystem 600                  */
-#define SM_4M_SS50    0x02	/* Sun4m SparcStation 10                  */
-#define SM_4M_SS40    0x03	/* Sun4m SparcStation 5                   */
-
-/* Sun4d machines -- N/A */
-/* Sun4e machines -- N/A */
-/* Sun4u machines -- N/A */
-
-#endif				/* !(_SPARC_MACHINES_H) */
diff --git a/arch/sparc/include/asm/page.h b/arch/sparc/include/asm/page.h
deleted file mode 100644
index 181d1c1..0000000
--- a/arch/sparc/include/asm/page.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* page.h:  Various defines and such for MMU operations on the Sparc for
- *          the Linux kernel.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 2007 Daniel Hellstrom (daniel@gaisler.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SPARC_PAGE_H
-#define _SPARC_PAGE_H
-
-#ifdef CONFIG_SUN4
-#define PAGE_SHIFT   13
-#else
-#define PAGE_SHIFT   12
-#endif
-
-#ifndef __ASSEMBLY__
-/* I have my suspicions... -DaveM */
-#define PAGE_SIZE    (1UL << PAGE_SHIFT)
-#else
-#define PAGE_SIZE    (1 << PAGE_SHIFT)
-#endif
-
-#define PAGE_MASK    (~(PAGE_SIZE-1))
-
-#endif				/* _SPARC_PAGE_H */
diff --git a/arch/sparc/include/asm/posix_types.h b/arch/sparc/include/asm/posix_types.h
deleted file mode 100644
index 61d3bbc..0000000
--- a/arch/sparc/include/asm/posix_types.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * (C) Copyright 2000 - 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2007, taken from asm-ppc/posix_types.h
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SPARC_POSIX_TYPES_H__
-#define __SPARC_POSIX_TYPES_H__
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned int __kernel_dev_t;
-typedef unsigned int __kernel_ino_t;
-typedef unsigned int __kernel_mode_t;
-typedef unsigned short __kernel_nlink_t;
-typedef long __kernel_off_t;
-typedef int __kernel_pid_t;
-typedef unsigned int __kernel_uid_t;
-typedef unsigned int __kernel_gid_t;
-typedef unsigned int __kernel_size_t;
-typedef int __kernel_ssize_t;
-typedef long __kernel_ptrdiff_t;
-typedef long __kernel_time_t;
-typedef long __kernel_suseconds_t;
-typedef long __kernel_clock_t;
-typedef int __kernel_daddr_t;
-typedef char *__kernel_caddr_t;
-typedef short __kernel_ipc_pid_t;
-typedef unsigned short __kernel_uid16_t;
-typedef unsigned short __kernel_gid16_t;
-typedef unsigned int __kernel_uid32_t;
-typedef unsigned int __kernel_gid32_t;
-
-typedef unsigned int __kernel_old_uid_t;
-typedef unsigned int __kernel_old_gid_t;
-
-#ifdef __GNUC__
-typedef long long __kernel_loff_t;
-#endif
-
-typedef struct {
-	int val[2];
-} __kernel_fsid_t;
-
-#ifndef __GNUC__
-
-#define	__FD_SET(d, set)	((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
-#define	__FD_CLR(d, set)	((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
-#define	__FD_ISSET(d, set)	((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
-#define	__FD_ZERO(set)	\
-  ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
-
-#else				/* __GNUC__ */
-
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
-    || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
-/* With GNU C, use inline functions instead so args are evaluated only once: */
-
-#undef __FD_SET
-static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set * fdsetp)
-{
-	unsigned long _tmp = fd / __NFDBITS;
-	unsigned long _rem = fd % __NFDBITS;
-	fdsetp->fds_bits[_tmp] |= (1UL << _rem);
-}
-
-#undef __FD_CLR
-static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set * fdsetp)
-{
-	unsigned long _tmp = fd / __NFDBITS;
-	unsigned long _rem = fd % __NFDBITS;
-	fdsetp->fds_bits[_tmp] &= ~(1UL << _rem);
-}
-
-#undef __FD_ISSET
-static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set * p)
-{
-	unsigned long _tmp = fd / __NFDBITS;
-	unsigned long _rem = fd % __NFDBITS;
-	return (p->fds_bits[_tmp] & (1UL << _rem)) != 0;
-}
-
-/*
- * This will unroll the loop for the normal constant case (8 ints,
- * for a 256-bit fd_set)
- */
-#undef __FD_ZERO
-static __inline__ void __FD_ZERO(__kernel_fd_set * p)
-{
-	unsigned int *tmp = (unsigned int *)p->fds_bits;
-	int i;
-
-	if (__builtin_constant_p(__FDSET_LONGS)) {
-		switch (__FDSET_LONGS) {
-		case 8:
-			tmp[0] = 0;
-			tmp[1] = 0;
-			tmp[2] = 0;
-			tmp[3] = 0;
-			tmp[4] = 0;
-			tmp[5] = 0;
-			tmp[6] = 0;
-			tmp[7] = 0;
-			return;
-		}
-	}
-	i = __FDSET_LONGS;
-	while (i) {
-		i--;
-		*tmp = 0;
-		tmp++;
-	}
-}
-
-#endif				/* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
-#endif				/* __GNUC__ */
-#endif				/* _SPARC_POSIX_TYPES_H */
diff --git a/arch/sparc/include/asm/processor.h b/arch/sparc/include/asm/processor.h
deleted file mode 100644
index 9a6535d..0000000
--- a/arch/sparc/include/asm/processor.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* SPARC Processor specifics
- * taken from the SPARC port of Linux (ptrace.h).
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_SPARC_PROCESSOR_H
-#define __ASM_SPARC_PROCESSOR_H
-
-#include <asm/arch/asi.h>
-
-#ifdef CONFIG_LEON
-
-/* All LEON processors supported */
-#include <asm/leon.h>
-
-#else
-/* other processors */
-#error Unknown SPARC Processor
-#endif
-
-#ifndef __ASSEMBLY__
-
-/* flush data cache */
-static __inline__ void sparc_dcache_flush_all(void)
-{
-      __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH):"memory");
-}
-
-/* flush instruction cache */
-static __inline__ void sparc_icache_flush_all(void)
-{
-      __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_IFLUSH):"memory");
-}
-
-/* do a cache miss load */
-static __inline__ unsigned long long sparc_load_reg_cachemiss_qword(unsigned
-								    long paddr)
-{
-	unsigned long long retval;
-	__asm__ __volatile__("ldda [%1] %2, %0\n\t":
-			     "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
-	return retval;
-}
-
-static __inline__ unsigned long sparc_load_reg_cachemiss(unsigned long paddr)
-{
-	unsigned long retval;
-	__asm__ __volatile__("lda [%1] %2, %0\n\t":
-			     "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
-	return retval;
-}
-
-static __inline__ unsigned short sparc_load_reg_cachemiss_word(unsigned long
-							       paddr)
-{
-	unsigned short retval;
-	__asm__ __volatile__("lduha [%1] %2, %0\n\t":
-			     "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
-	return retval;
-}
-
-static __inline__ unsigned char sparc_load_reg_cachemiss_byte(unsigned long
-							      paddr)
-{
-	unsigned char retval;
-	__asm__ __volatile__("lduba [%1] %2, %0\n\t":
-			     "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
-	return retval;
-}
-
-/* do a physical address bypass write, i.e. for 0x80000000 */
-static __inline__ void sparc_store_reg_bypass(unsigned long paddr,
-					      unsigned long value)
-{
-	__asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(value), "r"(paddr),
-			     "i"(ASI_BYPASS):"memory");
-}
-
-static __inline__ unsigned long sparc_load_reg_bypass(unsigned long paddr)
-{
-	unsigned long retval;
-	__asm__ __volatile__("lda [%1] %2, %0\n\t":
-			     "=r"(retval):"r"(paddr), "i"(ASI_BYPASS));
-	return retval;
-}
-
-/* Macros for bypassing cache when reading */
-#define SPARC_NOCACHE_READ_DWORD(address) sparc_load_reg_cachemiss_qword((unsigned int)(address))
-#define SPARC_NOCACHE_READ(address)       sparc_load_reg_cachemiss((unsigned int)(address))
-#define SPARC_NOCACHE_READ_HWORD(address) sparc_load_reg_cachemiss_word((unsigned int)(address))
-#define SPARC_NOCACHE_READ_BYTE(address)  sparc_load_reg_cachemiss_byte((unsigned int)(address))
-
-#define SPARC_BYPASS_READ(address)        sparc_load_reg_bypass((unsigned int)(address))
-#define SPARC_BYPASS_WRITE(address,value) sparc_store_reg_bypass((unsigned int)(address),(unsigned int)(value))
-
-#endif
-
-#endif				/* __ASM_SPARC_PROCESSOR_H */
diff --git a/arch/sparc/include/asm/prom.h b/arch/sparc/include/asm/prom.h
deleted file mode 100644
index 8906ef6..0000000
--- a/arch/sparc/include/asm/prom.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/* OpenProm defines mainly taken from linux kernel header files
- *
- * openprom.h:  Prom structures and defines for access to the OPENBOOT
- *              prom routines and data areas.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 2007 Daniel Hellstrom (daniel@gaisler.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SPARC_OPENPROM_H__
-#define __SPARC_OPENPROM_H__
-
-/* Empirical constants... */
-#define	LINUX_OPPROM_MAGIC      0x10010407
-
-#ifndef __ASSEMBLY__
-/* V0 prom device operations. */
-struct linux_dev_v0_funcs {
-	int (*v0_devopen) (char *device_str);
-	int (*v0_devclose) (int dev_desc);
-	int (*v0_rdblkdev) (int dev_desc, int num_blks, int blk_st, char *buf);
-	int (*v0_wrblkdev) (int dev_desc, int num_blks, int blk_st, char *buf);
-	int (*v0_wrnetdev) (int dev_desc, int num_bytes, char *buf);
-	int (*v0_rdnetdev) (int dev_desc, int num_bytes, char *buf);
-	int (*v0_rdchardev) (int dev_desc, int num_bytes, int dummy, char *buf);
-	int (*v0_wrchardev) (int dev_desc, int num_bytes, int dummy, char *buf);
-	int (*v0_seekdev) (int dev_desc, long logical_offst, int from);
-};
-
-/* V2 and later prom device operations. */
-struct linux_dev_v2_funcs {
-	int (*v2_inst2pkg) (int d);	/* Convert ihandle to phandle */
-	char *(*v2_dumb_mem_alloc) (char *va, unsigned sz);
-	void (*v2_dumb_mem_free) (char *va, unsigned sz);
-
-	/* To map devices into virtual I/O space. */
-	char *(*v2_dumb_mmap) (char *virta, int which_io, unsigned paddr,
-			       unsigned sz);
-	void (*v2_dumb_munmap) (char *virta, unsigned size);
-
-	int (*v2_dev_open) (char *devpath);
-	void (*v2_dev_close) (int d);
-	int (*v2_dev_read) (int d, char *buf, int nbytes);
-	int (*v2_dev_write) (int d, char *buf, int nbytes);
-	int (*v2_dev_seek) (int d, int hi, int lo);
-
-	/* Never issued (multistage load support) */
-	void (*v2_wheee2) (void);
-	void (*v2_wheee3) (void);
-};
-
-struct linux_mlist_v0 {
-	struct linux_mlist_v0 *theres_more;
-	char *start_adr;
-	unsigned num_bytes;
-};
-
-struct linux_mem_v0 {
-	struct linux_mlist_v0 **v0_totphys;
-	struct linux_mlist_v0 **v0_prommap;
-	struct linux_mlist_v0 **v0_available;	/* What we can use */
-};
-
-/* Arguments sent to the kernel from the boot prompt. */
-struct linux_arguments_v0 {
-	char * const argv[8];
-	char args[100];
-	char boot_dev[2];
-	int boot_dev_ctrl;
-	int boot_dev_unit;
-	int dev_partition;
-	char *kernel_file_name;
-	void *aieee1;		/* XXX */
-};
-
-/* V2 and up boot things. */
-struct linux_bootargs_v2 {
-	char **bootpath;
-	char **bootargs;
-	int *fd_stdin;
-	int *fd_stdout;
-};
-
-/* The top level PROM vector. */
-struct linux_romvec {
-	/* Version numbers. */
-	unsigned int pv_magic_cookie;
-	unsigned int pv_romvers;
-	unsigned int pv_plugin_revision;
-	unsigned int pv_printrev;
-
-	/* Version 0 memory descriptors. */
-	struct linux_mem_v0 pv_v0mem;
-
-	/* Node operations. */
-	struct linux_nodeops *pv_nodeops;
-
-	char **pv_bootstr;
-	struct linux_dev_v0_funcs pv_v0devops;
-
-	char *pv_stdin;
-	char *pv_stdout;
-#define	PROMDEV_KBD	0	/* input from keyboard */
-#define	PROMDEV_SCREEN	0	/* output to screen */
-#define	PROMDEV_TTYA	1	/* in/out to ttya */
-#define	PROMDEV_TTYB	2	/* in/out to ttyb */
-
-	/* Blocking getchar/putchar.  NOT REENTRANT! (grr) */
-	int (*pv_getchar) (void);
-	void (*pv_putchar) (int ch);
-
-	/* Non-blocking variants. */
-	int (*pv_nbgetchar) (void);
-	int (*pv_nbputchar) (int ch);
-
-	void (*pv_putstr) (char *str, int len);
-
-	/* Miscellany. */
-	void (*pv_reboot) (char *bootstr);
-	void (*pv_printf) (__const__ char *fmt, ...);
-	void (*pv_abort) (void);
-	__volatile__ int *pv_ticks;
-	void (*pv_halt) (void);
-	void (**pv_synchook) (void);
-
-	/* Evaluate a forth string, not different proto for V0 and V2->up. */
-	union {
-		void (*v0_eval) (int len, char *str);
-		void (*v2_eval) (char *str);
-	} pv_fortheval;
-
-	struct linux_arguments_v0 **pv_v0bootargs;
-
-	/* Get ether address. */
-	unsigned int (*pv_enaddr) (int d, char *enaddr);
-
-	struct linux_bootargs_v2 pv_v2bootargs;
-	struct linux_dev_v2_funcs pv_v2devops;
-
-	int filler[15];
-
-	/* This one is sun4c/sun4 only. */
-	void (*pv_setctxt) (int ctxt, char *va, int pmeg);
-
-	/* Prom version 3 Multiprocessor routines. This stuff is crazy.
-	 * No joke. Calling these when there is only one cpu probably
-	 * crashes the machine, have to test this. :-)
-	 */
-
-	/* v3_cpustart() will start the cpu 'whichcpu' in mmu-context
-	 * 'thiscontext' executing at address 'prog_counter'
-	 */
-	int (*v3_cpustart) (unsigned int whichcpu, int ctxtbl_ptr,
-			    int thiscontext, char *prog_counter);
-
-	/* v3_cpustop() will cause cpu 'whichcpu' to stop executing
-	 * until a resume cpu call is made.
-	 */
-	int (*v3_cpustop) (unsigned int whichcpu);
-
-	/* v3_cpuidle() will idle cpu 'whichcpu' until a stop or
-	 * resume cpu call is made.
-	 */
-	int (*v3_cpuidle) (unsigned int whichcpu);
-
-	/* v3_cpuresume() will resume processor 'whichcpu' executing
-	 * starting with whatever 'pc' and 'npc' were left at the
-	 * last 'idle' or 'stop' call.
-	 */
-	int (*v3_cpuresume) (unsigned int whichcpu);
-};
-
-/* Routines for traversing the prom device tree. */
-struct linux_nodeops {
-	int (*no_nextnode) (int node);
-	int (*no_child) (int node);
-	int (*no_proplen) (int node, char *name);
-	int (*no_getprop) (int node, char *name, char *val);
-	int (*no_setprop) (int node, char *name, char *val, int len);
-	char *(*no_nextprop) (int node, char *name);
-};
-
-/* More fun PROM structures for device probing. */
-#define PROMREG_MAX     16
-#define PROMVADDR_MAX   16
-#define PROMINTR_MAX    15
-
-struct linux_prom_registers {
-	unsigned int which_io;	/* is this in OBIO space? */
-	unsigned int phys_addr;	/* The physical address of this register */
-	unsigned int reg_size;	/* How many bytes does this register take up? */
-};
-
-struct linux_prom_irqs {
-	int pri;		/* IRQ priority */
-	int vector;		/* This is foobar, what does it do? */
-};
-
-/* Element of the "ranges" vector */
-struct linux_prom_ranges {
-	unsigned int ot_child_space;
-	unsigned int ot_child_base;	/* Bus feels this */
-	unsigned int ot_parent_space;
-	unsigned int ot_parent_base;	/* CPU looks from here */
-	unsigned int or_size;
-};
-
-/* Ranges and reg properties are a bit different for PCI. */
-struct linux_prom_pci_registers {
-	/*
-	 * We don't know what information this field contain.
-	 * We guess, PCI device function is in bits 15:8
-	 * So, ...
-	 */
-	unsigned int which_io;	/* Let it be which_io */
-
-	unsigned int phys_hi;
-	unsigned int phys_lo;
-
-	unsigned int size_hi;
-	unsigned int size_lo;
-};
-
-struct linux_prom_pci_ranges {
-	unsigned int child_phys_hi;	/* Only certain bits are encoded here. */
-	unsigned int child_phys_mid;
-	unsigned int child_phys_lo;
-
-	unsigned int parent_phys_hi;
-	unsigned int parent_phys_lo;
-
-	unsigned int size_hi;
-	unsigned int size_lo;
-};
-
-struct linux_prom_pci_assigned_addresses {
-	unsigned int which_io;
-
-	unsigned int phys_hi;
-	unsigned int phys_lo;
-
-	unsigned int size_hi;
-	unsigned int size_lo;
-};
-
-struct linux_prom_ebus_ranges {
-	unsigned int child_phys_hi;
-	unsigned int child_phys_lo;
-
-	unsigned int parent_phys_hi;
-	unsigned int parent_phys_mid;
-	unsigned int parent_phys_lo;
-
-	unsigned int size;
-};
-
-/* Offset into the EEPROM where the id PROM is located on the 4c */
-#define IDPROM_OFFSET  0x7d8
-
-/* On sun4m; physical. */
-/* MicroSPARC(-II) does not decode 31rd bit, but it works. */
-#define IDPROM_OFFSET_M  0xfd8
-
-struct idprom {
-	unsigned char id_format;	/* Format identifier (always 0x01) */
-	unsigned char id_machtype;	/* Machine type */
-	unsigned char id_ethaddr[6];	/* Hardware ethernet address */
-	long id_date;		/* Date of manufacture */
-	unsigned int id_sernum:24;	/* Unique serial number */
-	unsigned char id_cksum;	/* Checksum - xor of the data bytes */
-	unsigned char reserved[16];
-};
-
-extern struct idprom *idprom;
-extern void idprom_init(void);
-
-#define IDPROM_SIZE  (sizeof(struct idprom))
-
-#endif				/* !(__ASSEMBLY__) */
-
-#endif
diff --git a/arch/sparc/include/asm/psr.h b/arch/sparc/include/asm/psr.h
deleted file mode 100644
index a91bdc9..0000000
--- a/arch/sparc/include/asm/psr.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* psr.h: This file holds the macros for masking off various parts of
- *        the processor status register on the Sparc. This is valid
- *        for Version 8. On the V9 this is renamed to the PSTATE
- *        register and its members are accessed as fields like
- *        PSTATE.PRIV for the current CPU privilege level.
- *
- * taken from the SPARC port of Linux,
- *
- * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 2007 Daniel Hellstrom (daniel@gaisler.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SPARC_PSR_H__
-#define __SPARC_PSR_H__
-
-/* The Sparc PSR fields are laid out as the following:
- *
- *  ------------------------------------------------------------------------
- *  | impl  | vers  | icc   | resv  | EC | EF | PIL  | S | PS | ET |  CWP  |
- *  | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6  | 5  |  4-0  |
- *  ------------------------------------------------------------------------
- */
-#define PSR_CWP     0x0000001f	/* current window pointer     */
-#define PSR_ET      0x00000020	/* enable traps field         */
-#define PSR_PS      0x00000040	/* previous privilege level   */
-#define PSR_S       0x00000080	/* current privilege level    */
-#define PSR_PIL     0x00000f00	/* processor interrupt level  */
-#define PSR_EF      0x00001000	/* enable floating point      */
-#define PSR_EC      0x00002000	/* enable co-processor        */
-#define PSR_LE      0x00008000	/* SuperSparcII little-endian */
-#define PSR_ICC     0x00f00000	/* integer condition codes    */
-#define PSR_C       0x00100000	/* carry bit                  */
-#define PSR_V       0x00200000	/* overflow bit               */
-#define PSR_Z       0x00400000	/* zero bit                   */
-#define PSR_N       0x00800000	/* negative bit               */
-#define PSR_VERS    0x0f000000	/* cpu-version field          */
-#define PSR_IMPL    0xf0000000	/* cpu-implementation field   */
-
-#define PSR_PIL_OFS  8
-
-#ifndef __ASSEMBLY__
-/* Get the %psr register. */
-static __inline__ unsigned int get_psr(void)
-{
-	unsigned int psr;
-	__asm__ __volatile__("rd	%%psr, %0\n\t"
-			     "nop\n\t" "nop\n\t" "nop\n\t":"=r"(psr)
-			     :	/* no inputs */
-			     :"memory");
-
-	return psr;
-}
-
-static __inline__ void put_psr(unsigned int new_psr)
-{
-	__asm__ __volatile__("wr	%0, 0x0, %%psr\n\t" "nop\n\t" "nop\n\t" "nop\n\t":	/* no outputs */
-			     :"r"(new_psr)
-			     :"memory", "cc");
-}
-
-/* Get the %fsr register.  Be careful, make sure the floating point
- * enable bit is set in the %psr when you execute this or you will
- * incur a trap.
- */
-
-extern unsigned int fsr_storage;
-
-static __inline__ unsigned int get_fsr(void)
-{
-	unsigned int fsr = 0;
-
-	__asm__ __volatile__("st	%%fsr, %1\n\t"
-			     "ld	%1, %0\n\t":"=r"(fsr)
-			     :"m"(fsr_storage));
-
-	return fsr;
-}
-
-#endif				/* !(__ASSEMBLY__) */
-
-#endif				/* !(__SPARC_PSR_H__) */
diff --git a/arch/sparc/include/asm/ptrace.h b/arch/sparc/include/asm/ptrace.h
deleted file mode 100644
index 33cfbac..0000000
--- a/arch/sparc/include/asm/ptrace.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/* Contain the Stack frame layout on interrupt. pt_regs.
- * taken from the SPARC port of Linux (ptrace.h).
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SPARC_PTRACE_H__
-#define __SPARC_PTRACE_H__
-
-#include <asm/psr.h>
-
-/* This struct defines the way the registers are stored on the
- * stack during a system call and basically all traps.
- */
-
-#ifndef __ASSEMBLY__
-
-struct pt_regs {
-	unsigned long psr;
-	unsigned long pc;
-	unsigned long npc;
-	unsigned long y;
-	unsigned long u_regs[16];	/* globals and ins */
-};
-
-#define UREG_G0        0
-#define UREG_G1        1
-#define UREG_G2        2
-#define UREG_G3        3
-#define UREG_G4        4
-#define UREG_G5        5
-#define UREG_G6        6
-#define UREG_G7        7
-#define UREG_I0        8
-#define UREG_I1        9
-#define UREG_I2        10
-#define UREG_I3        11
-#define UREG_I4        12
-#define UREG_I5        13
-#define UREG_I6        14
-#define UREG_I7        15
-#define UREG_WIM       UREG_G0
-#define UREG_FADDR     UREG_G0
-#define UREG_FP        UREG_I6
-#define UREG_RETPC     UREG_I7
-
-/* A register window */
-struct reg_window {
-	unsigned long locals[8];
-	unsigned long ins[8];
-};
-
-/* A Sparc stack frame */
-struct sparc_stackf {
-	unsigned long locals[8];
-	unsigned long ins[6];
-	struct sparc_stackf *fp;
-	unsigned long callers_pc;
-	char *structptr;
-	unsigned long xargs[6];
-	unsigned long xxargs[1];
-};
-
-#define TRACEREG_SZ   sizeof(struct pt_regs)
-#define STACKFRAME_SZ sizeof(struct sparc_stackf)
-
-#else				/* __ASSEMBLY__ */
-/* For assembly code. */
-#define TRACEREG_SZ       0x50
-#define STACKFRAME_SZ     0x60
-#endif
-
-/*
- * The asm_offsets.h is a generated file, so we cannot include it.
- * It may be OK for glibc headers, but it's utterly pointless for C code.
- * The assembly code using those offsets has to include it explicitly.
- */
-/* #include <asm/asm_offsets.h> */
-
-/* These are for pt_regs. */
-#define PT_PSR    0x0
-#define PT_PC     0x4
-#define PT_NPC    0x8
-#define PT_Y      0xc
-#define PT_G0     0x10
-#define PT_WIM    PT_G0
-#define PT_G1     0x14
-#define PT_G2     0x18
-#define PT_G3     0x1c
-#define PT_G4     0x20
-#define PT_G5     0x24
-#define PT_G6     0x28
-#define PT_G7     0x2c
-#define PT_I0     0x30
-#define PT_I1     0x34
-#define PT_I2     0x38
-#define PT_I3     0x3c
-#define PT_I4     0x40
-#define PT_I5     0x44
-#define PT_I6     0x48
-#define PT_FP     PT_I6
-#define PT_I7     0x4c
-
-/* Reg_window offsets */
-#define RW_L0     0x00
-#define RW_L1     0x04
-#define RW_L2     0x08
-#define RW_L3     0x0c
-#define RW_L4     0x10
-#define RW_L5     0x14
-#define RW_L6     0x18
-#define RW_L7     0x1c
-#define RW_I0     0x20
-#define RW_I1     0x24
-#define RW_I2     0x28
-#define RW_I3     0x2c
-#define RW_I4     0x30
-#define RW_I5     0x34
-#define RW_I6     0x38
-#define RW_I7     0x3c
-
-/* Stack_frame offsets */
-#define SF_L0     0x00
-#define SF_L1     0x04
-#define SF_L2     0x08
-#define SF_L3     0x0c
-#define SF_L4     0x10
-#define SF_L5     0x14
-#define SF_L6     0x18
-#define SF_L7     0x1c
-#define SF_I0     0x20
-#define SF_I1     0x24
-#define SF_I2     0x28
-#define SF_I3     0x2c
-#define SF_I4     0x30
-#define SF_I5     0x34
-#define SF_FP     0x38
-#define SF_PC     0x3c
-#define SF_RETP   0x40
-#define SF_XARG0  0x44
-#define SF_XARG1  0x48
-#define SF_XARG2  0x4c
-#define SF_XARG3  0x50
-#define SF_XARG4  0x54
-#define SF_XARG5  0x58
-#define SF_XXARG  0x5c
-
-/* Stuff for the ptrace system call */
-#define PTRACE_SUNATTACH          10
-#define PTRACE_SUNDETACH          11
-#define PTRACE_GETREGS            12
-#define PTRACE_SETREGS            13
-#define PTRACE_GETFPREGS          14
-#define PTRACE_SETFPREGS          15
-#define PTRACE_READDATA           16
-#define PTRACE_WRITEDATA          17
-#define PTRACE_READTEXT           18
-#define PTRACE_WRITETEXT          19
-#define PTRACE_GETFPAREGS         20
-#define PTRACE_SETFPAREGS         21
-
-#define PTRACE_GETUCODE           29	/* stupid bsd-ism */
-
-#endif				/* !(_SPARC_PTRACE_H) */
diff --git a/arch/sparc/include/asm/sections.h b/arch/sparc/include/asm/sections.h
deleted file mode 100644
index 65ad891..0000000
--- a/arch/sparc/include/asm/sections.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2012 The Chromium OS Authors.
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_SPARC_SECTIONS_H
-#define __ASM_SPARC_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/arch/sparc/include/asm/srmmu.h b/arch/sparc/include/asm/srmmu.h
deleted file mode 100644
index 8da2f67..0000000
--- a/arch/sparc/include/asm/srmmu.h
+++ /dev/null
@@ -1,287 +0,0 @@
-/* SRMMU page table defines and code,
- * taken from the SPARC port of Linux
- *
- * Copyright (C) 2007 Daniel Hellstrom (daniel@gaisler.com)
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SPARC_SRMMU_H__
-#define __SPARC_SRMMU_H__
-
-#include <asm/asi.h>
-#include <asm/page.h>
-
-/* Number of contexts is implementation-dependent; 64k is the most we support */
-#define SRMMU_MAX_CONTEXTS	65536
-
-/* PMD_SHIFT determines the size of the area a second-level page table entry can map */
-#define SRMMU_REAL_PMD_SHIFT		18
-#define SRMMU_REAL_PMD_SIZE		(1UL << SRMMU_REAL_PMD_SHIFT)
-#define SRMMU_REAL_PMD_MASK		(~(SRMMU_REAL_PMD_SIZE-1))
-#define SRMMU_REAL_PMD_ALIGN(__addr)	(((__addr)+SRMMU_REAL_PMD_SIZE-1)&SRMMU_REAL_PMD_MASK)
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define SRMMU_PGDIR_SHIFT       24
-#define SRMMU_PGDIR_SIZE        (1UL << SRMMU_PGDIR_SHIFT)
-#define SRMMU_PGDIR_MASK        (~(SRMMU_PGDIR_SIZE-1))
-#define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
-
-#define SRMMU_REAL_PTRS_PER_PTE	64
-#define SRMMU_REAL_PTRS_PER_PMD	64
-#define SRMMU_PTRS_PER_PGD	256
-
-#define SRMMU_REAL_PTE_TABLE_SIZE	(SRMMU_REAL_PTRS_PER_PTE*4)
-#define SRMMU_PMD_TABLE_SIZE		(SRMMU_REAL_PTRS_PER_PMD*4)
-#define SRMMU_PGD_TABLE_SIZE		(SRMMU_PTRS_PER_PGD*4)
-
-/*
- * To support pagetables in highmem, Linux introduces APIs which
- * return struct page* and generally manipulate page tables when
- * they are not mapped into kernel space. Our hardware page tables
- * are smaller than pages. We lump hardware tabes into big, page sized
- * software tables.
- *
- * PMD_SHIFT determines the size of the area a second-level page table entry
- * can map, and our pmd_t is 16 times larger than normal.  The values which
- * were once defined here are now generic for 4c and srmmu, so they're
- * found in pgtable.h.
- */
-#define SRMMU_PTRS_PER_PMD	4
-
-/* Definition of the values in the ET field of PTD's and PTE's */
-#define SRMMU_ET_MASK         0x3
-#define SRMMU_ET_INVALID      0x0
-#define SRMMU_ET_PTD          0x1
-#define SRMMU_ET_PTE          0x2
-#define SRMMU_ET_REPTE        0x3	/* AIEEE, SuperSparc II reverse endian page! */
-
-/* Physical page extraction from PTP's and PTE's. */
-#define SRMMU_CTX_PMASK    0xfffffff0
-#define SRMMU_PTD_PMASK    0xfffffff0
-#define SRMMU_PTE_PMASK    0xffffff00
-
-/* The pte non-page bits.  Some notes:
- * 1) cache, dirty, valid, and ref are frobbable
- *    for both supervisor and user pages.
- * 2) exec and write will only give the desired effect
- *    on user pages
- * 3) use priv and priv_readonly for changing the
- *    characteristics of supervisor ptes
- */
-#define SRMMU_CACHE        0x80
-#define SRMMU_DIRTY        0x40
-#define SRMMU_REF          0x20
-#define SRMMU_NOREAD       0x10
-#define SRMMU_EXEC         0x08
-#define SRMMU_WRITE        0x04
-#define SRMMU_VALID        0x02	/* SRMMU_ET_PTE */
-#define SRMMU_PRIV         0x1c
-#define SRMMU_PRIV_RDONLY  0x18
-
-#define SRMMU_FILE         0x40	/* Implemented in software */
-
-#define SRMMU_PTE_FILE_SHIFT     8	/* == 32-PTE_FILE_MAX_BITS */
-
-#define SRMMU_CHG_MASK    (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
-
-/* SRMMU swap entry encoding
- *
- * We use 5 bits for the type and 19 for the offset.  This gives us
- * 32 swapfiles of 4GB each.  Encoding looks like:
- *
- * oooooooooooooooooootttttRRRRRRRR
- * fedcba9876543210fedcba9876543210
- *
- * The bottom 8 bits are reserved for protection and status bits, especially
- * FILE and PRESENT.
- */
-#define SRMMU_SWP_TYPE_MASK	0x1f
-#define SRMMU_SWP_TYPE_SHIFT	SRMMU_PTE_FILE_SHIFT
-#define SRMMU_SWP_OFF_MASK	0x7ffff
-#define SRMMU_SWP_OFF_SHIFT	(SRMMU_PTE_FILE_SHIFT + 5)
-
-/* Some day I will implement true fine grained access bits for
- * user pages because the SRMMU gives us the capabilities to
- * enforce all the protection levels that vma's can have.
- * XXX But for now...
- */
-#define SRMMU_PAGE_NONE    __pgprot(SRMMU_CACHE | \
-				    SRMMU_PRIV | SRMMU_REF)
-#define SRMMU_PAGE_SHARED  __pgprot(SRMMU_VALID | SRMMU_CACHE | \
-				    SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
-#define SRMMU_PAGE_COPY    __pgprot(SRMMU_VALID | SRMMU_CACHE | \
-				    SRMMU_EXEC | SRMMU_REF)
-#define SRMMU_PAGE_RDONLY  __pgprot(SRMMU_VALID | SRMMU_CACHE | \
-				    SRMMU_EXEC | SRMMU_REF)
-#define SRMMU_PAGE_KERNEL  __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
-				    SRMMU_DIRTY | SRMMU_REF)
-
-/* SRMMU Register addresses in ASI 0x4.  These are valid for all
- * current SRMMU implementations that exist.
- */
-#define SRMMU_CTRL_REG           0x00000000
-#define SRMMU_CTXTBL_PTR         0x00000100
-#define SRMMU_CTX_REG            0x00000200
-#define SRMMU_FAULT_STATUS       0x00000300
-#define SRMMU_FAULT_ADDR         0x00000400
-
-#define WINDOW_FLUSH(tmp1, tmp2)					\
-	mov	0, tmp1;						\
-98:	ld	[%g6 + TI_UWINMASK], tmp2;				\
-	orcc	%g0, tmp2, %g0;						\
-	add	tmp1, 1, tmp1;						\
-	bne	98b;							\
-	 save	%sp, -64, %sp;						\
-99:	subcc	tmp1, 1, tmp1;						\
-	bne	99b;							\
-	 restore %g0, %g0, %g0;
-
-#ifndef __ASSEMBLY__
-
-/* This makes sense. Honest it does - Anton */
-/* XXX Yes but it's ugly as sin.  FIXME. -KMW */
-extern void *srmmu_nocache_pool;
-#define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool))
-#define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
-#define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
-
-/* Accessing the MMU control register. */
-static __inline__ unsigned int srmmu_get_mmureg(void)
-{
-	unsigned int retval;
-	__asm__ __volatile__("lda [%%g0] %1, %0\n\t":
-			     "=r"(retval):"i"(ASI_M_MMUREGS));
-	return retval;
-}
-
-static __inline__ void srmmu_set_mmureg(unsigned long regval)
-{
-	__asm__ __volatile__("sta %0, [%%g0] %1\n\t"::"r"(regval),
-			     "i"(ASI_M_MMUREGS):"memory");
-
-}
-
-static __inline__ void srmmu_set_ctable_ptr(unsigned long paddr)
-{
-	paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
-	__asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(paddr),
-			     "r"(SRMMU_CTXTBL_PTR),
-			     "i"(ASI_M_MMUREGS):"memory");
-}
-
-static __inline__ unsigned long srmmu_get_ctable_ptr(void)
-{
-	unsigned int retval;
-
-	__asm__ __volatile__("lda [%1] %2, %0\n\t":
-			     "=r"(retval):
-			     "r"(SRMMU_CTXTBL_PTR), "i"(ASI_M_MMUREGS));
-	return (retval & SRMMU_CTX_PMASK) << 4;
-}
-
-static __inline__ void srmmu_set_context(int context)
-{
-	__asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(context),
-			     "r"(SRMMU_CTX_REG), "i"(ASI_M_MMUREGS):"memory");
-}
-
-static __inline__ int srmmu_get_context(void)
-{
-	register int retval;
-	__asm__ __volatile__("lda [%1] %2, %0\n\t":
-			     "=r"(retval):
-			     "r"(SRMMU_CTX_REG), "i"(ASI_M_MMUREGS));
-	return retval;
-}
-
-static __inline__ unsigned int srmmu_get_fstatus(void)
-{
-	unsigned int retval;
-
-	__asm__ __volatile__("lda [%1] %2, %0\n\t":
-			     "=r"(retval):
-			     "r"(SRMMU_FAULT_STATUS), "i"(ASI_M_MMUREGS));
-	return retval;
-}
-
-static __inline__ unsigned int srmmu_get_faddr(void)
-{
-	unsigned int retval;
-
-	__asm__ __volatile__("lda [%1] %2, %0\n\t":
-			     "=r"(retval):
-			     "r"(SRMMU_FAULT_ADDR), "i"(ASI_M_MMUREGS));
-	return retval;
-}
-
-/* This is guaranteed on all SRMMU's. */
-static __inline__ void srmmu_flush_whole_tlb(void)
-{
-	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x400),	/* Flush entire TLB!! */
-			     "i"(ASI_M_FLUSH_PROBE):"memory");
-
-}
-
-/* These flush types are not available on all chips... */
-static __inline__ void srmmu_flush_tlb_ctx(void)
-{
-	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x300),	/* Flush TLB ctx.. */
-			     "i"(ASI_M_FLUSH_PROBE):"memory");
-
-}
-
-static __inline__ void srmmu_flush_tlb_region(unsigned long addr)
-{
-	addr &= SRMMU_PGDIR_MASK;
-	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(addr | 0x200),	/* Flush TLB region.. */
-			     "i"(ASI_M_FLUSH_PROBE):"memory");
-
-}
-
-static __inline__ void srmmu_flush_tlb_segment(unsigned long addr)
-{
-	addr &= SRMMU_REAL_PMD_MASK;
-	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(addr | 0x100),	/* Flush TLB segment.. */
-			     "i"(ASI_M_FLUSH_PROBE):"memory");
-
-}
-
-static __inline__ void srmmu_flush_tlb_page(unsigned long page)
-{
-	page &= PAGE_MASK;
-	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(page),	/* Flush TLB page.. */
-			     "i"(ASI_M_FLUSH_PROBE):"memory");
-
-}
-
-static __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr)
-{
-	unsigned long retval;
-
-	vaddr &= PAGE_MASK;
-	__asm__ __volatile__("lda [%1] %2, %0\n\t":
-			     "=r"(retval):
-			     "r"(vaddr | 0x400), "i"(ASI_M_FLUSH_PROBE));
-
-	return retval;
-}
-
-static __inline__ int srmmu_get_pte(unsigned long addr)
-{
-	register unsigned long entry;
-
-	__asm__ __volatile__("\n\tlda [%1] %2,%0\n\t":
-			     "=r"(entry):
-			     "r"((addr & 0xfffff000) | 0x400),
-			     "i"(ASI_M_FLUSH_PROBE));
-	return entry;
-}
-
-extern unsigned long (*srmmu_read_physical) (unsigned long paddr);
-extern void (*srmmu_write_physical) (unsigned long paddr, unsigned long word);
-
-#endif				/* !(__ASSEMBLY__) */
-
-#endif				/* !(__SPARC_SRMMU_H__) */
diff --git a/arch/sparc/include/asm/stack.h b/arch/sparc/include/asm/stack.h
deleted file mode 100644
index fcab920..0000000
--- a/arch/sparc/include/asm/stack.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPARC stack layout Macros and structures,
- * mainly taken from BCC (the Bare C compiler for
- * SPARC LEON2/3) sources.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SPARC_STACK_H__
-#define __SPARC_STACK_H__
-
-#include <asm/ptrace.h>
-
-#ifndef __ASSEMBLER__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define PT_REGS_SZ   sizeof(struct pt_regs)
-
-/* A Sparc stack frame */
-	struct sparc_stackframe_regs {
-		unsigned long sf_locals[8];
-		unsigned long sf_ins[6];
-		struct sparc_stackframe_regs *sf_fp;
-		unsigned long sf_callers_pc;
-		char *sf_structptr;
-		unsigned long sf_xargs[6];
-		unsigned long sf_xxargs[1];
-	};
-#define SF_REGS_SZ sizeof(struct sparc_stackframe_regs)
-
-/* A register window */
-	struct sparc_regwindow_regs {
-		unsigned long locals[8];
-		unsigned long ins[8];
-	};
-#define RW_REGS_SZ sizeof(struct sparc_regwindow_regs)
-
-/* A fpu window */
-	struct sparc_fpuwindow_regs {
-		unsigned long locals[32];
-		unsigned long fsr;
-		unsigned long lastctx;
-	};
-#define FW_REGS_SZ sizeof(struct sparc_fpuwindow_regs)
-
-#ifdef __cplusplus
-}
-#endif
-#else
-#define PT_REGS_SZ	0x50	/* 20*4 */
-#define SF_REGS_SZ	0x60	/* 24*4 */
-#define RW_REGS_SZ	0x20	/* 16*4 */
-#define FW_REGS_SZ	0x88	/* 34*4 */
-#endif				/* !ASM */
-
-/* These are for pt_regs. */
-#define PT_PSR		0x0
-#define PT_PC		0x4
-#define PT_NPC		0x8
-#define PT_Y		0xc
-#define PT_G0		0x10
-#define PT_WIM		PT_G0
-#define PT_G1		0x14
-#define PT_G2		0x18
-#define PT_G3		0x1c
-#define PT_G4		0x20
-#define PT_G5		0x24
-#define PT_G6		0x28
-#define PT_G7		0x2c
-#define PT_I0		0x30
-#define PT_I1		0x34
-#define PT_I2		0x38
-#define PT_I3		0x3c
-#define PT_I4		0x40
-#define PT_I5		0x44
-#define PT_I6		0x48
-#define PT_FP		PT_I6
-#define PT_I7		0x4c
-
-/* Stack_frame offsets */
-#define SF_L0		0x00
-#define SF_L1		0x04
-#define SF_L2		0x08
-#define SF_L3		0x0c
-#define SF_L4		0x10
-#define SF_L5		0x14
-#define SF_L6		0x18
-#define SF_L7		0x1c
-#define SF_I0		0x20
-#define SF_I1		0x24
-#define SF_I2		0x28
-#define SF_I3		0x2c
-#define SF_I4		0x30
-#define SF_I5		0x34
-#define SF_FP		0x38
-#define SF_PC		0x3c
-#define SF_RETP		0x40
-#define SF_XARG0	0x44
-#define	SF_XARG1	0x48
-#define	SF_XARG2	0x4c
-#define	SF_XARG3	0x50
-#define	SF_XARG4	0x54
-#define	SF_XARG5	0x58
-#define	SF_XXARG	0x5c
-
-/* Reg_window offsets */
-#define RW_L0		0x00
-#define RW_L1		0x04
-#define RW_L2		0x08
-#define RW_L3		0x0c
-#define RW_L4		0x10
-#define RW_L5		0x14
-#define RW_L6		0x18
-#define RW_L7		0x1c
-#define RW_I0		0x20
-#define RW_I1		0x24
-#define RW_I2		0x28
-#define RW_I3		0x2c
-#define RW_I4		0x30
-#define RW_I5		0x34
-#define RW_I6		0x38
-#define RW_I7		0x3c
-
-/* Fpu_window offsets */
-#define FW_F0		0x00
-#define FW_F2		0x08
-#define FW_F4		0x10
-#define FW_F6		0x18
-#define FW_F8		0x20
-#define FW_F10		0x28
-#define FW_F12		0x30
-#define FW_F14		0x38
-#define FW_F16		0x40
-#define FW_F18		0x48
-#define FW_F20		0x50
-#define FW_F22		0x58
-#define FW_F24		0x60
-#define FW_F26		0x68
-#define FW_F28		0x70
-#define FW_F30		0x78
-#define FW_FSR		0x80
-
-#endif
diff --git a/arch/sparc/include/asm/string.h b/arch/sparc/include/asm/string.h
deleted file mode 100644
index d9cc5db..0000000
--- a/arch/sparc/include/asm/string.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2000 - 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SPARC_STRING_H_
-#define _SPARC_STRING_H_
-
-/*
-#define __HAVE_ARCH_STRCPY
-#define __HAVE_ARCH_STRNCPY
-#define __HAVE_ARCH_STRLEN
-#define __HAVE_ARCH_STRCMP
-#define __HAVE_ARCH_STRCAT
-#define __HAVE_ARCH_MEMSET
-#define __HAVE_ARCH_BCOPY
-#define __HAVE_ARCH_MEMCPY
-#define __HAVE_ARCH_MEMMOVE
-#define __HAVE_ARCH_MEMCMP
-#define __HAVE_ARCH_MEMCHR
-*/
-
-extern int strcasecmp(const char *, const char *);
-extern int strncasecmp(const char *, const char *, __kernel_size_t);
-extern char *strcpy(char *, const char *);
-extern char *strncpy(char *, const char *, __kernel_size_t);
-extern __kernel_size_t strlen(const char *);
-extern int strcmp(const char *, const char *);
-extern char *strcat(char *, const char *);
-extern void *memset(void *, int, __kernel_size_t);
-extern void *memcpy(void *, const void *, __kernel_size_t);
-extern void *memmove(void *, const void *, __kernel_size_t);
-extern int memcmp(const void *, const void *, __kernel_size_t);
-extern void *memchr(const void *, int, __kernel_size_t);
-
-#endif
diff --git a/arch/sparc/include/asm/types.h b/arch/sparc/include/asm/types.h
deleted file mode 100644
index 72030b2..0000000
--- a/arch/sparc/include/asm/types.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * (C) Copyright 2000 - 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SPARC_TYPES_H
-#define _SPARC_TYPES_H
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned short umode_t;
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
-#endif
-
-typedef struct {
-	__u32 u[4];
-} __attribute__((aligned(16))) vector128;
-
-#ifdef __KERNEL__
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long long s64;
-typedef unsigned long long u64;
-
-#define BITS_PER_LONG 32
-
-/* DMA addresses are 32-bits wide */
-typedef u32 dma_addr_t;
-
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
-
-#endif				/* __KERNEL__ */
-#endif				/* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/sparc/include/asm/u-boot.h b/arch/sparc/include/asm/u-boot.h
deleted file mode 100644
index 75ac7dc..0000000
--- a/arch/sparc/include/asm/u-boot.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2000 - 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __U_BOOT_H__
-#define __U_BOOT_H__
-
-/* Currently, this board information is not passed to
- * Linux kernel from U-Boot, but may be passed to other
- * Operating systems. This is because U-Boot emulates
- * a SUN PROM loader (from Linux point of view).
- */
-#include <asm-generic/u-boot.h>
-
-/* For image.h:image_check_target_arch() */
-#define IH_ARCH_DEFAULT IH_ARCH_SPARC
-
-#endif
diff --git a/arch/sparc/include/asm/unaligned.h b/arch/sparc/include/asm/unaligned.h
deleted file mode 100644
index 0e646f7..0000000
--- a/arch/sparc/include/asm/unaligned.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _ASM_SPARC_UNALIGNED_H
-#define _ASM_SPARC_UNALIGNED_H
-
-/*
- * The SPARC can not do unaligned accesses, it must be split into multiple
- * byte accesses. The SPARC is in big endian mode.
- */
-#include <asm-generic/unaligned.h>
-
-#endif	/* _ASM_SPARC_UNALIGNED_H */
diff --git a/arch/sparc/include/asm/winmacro.h b/arch/sparc/include/asm/winmacro.h
deleted file mode 100644
index 916ee9c..0000000
--- a/arch/sparc/include/asm/winmacro.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Added to U-Boot,
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
- * Copyright (C) 2007
- *
- * LEON2/3 LIBIO low-level routines
- * Written by Jiri Gaisler.
- * Copyright (C) 2004  Gaisler Research AB
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SPARC_WINMACRO_H__
-#define __SPARC_WINMACRO_H__
-
-#include <asm/asmmacro.h>
-#include <asm/stack.h>
-
-/* Store the register window onto the 8-byte aligned area starting
- * at %reg.  It might be %sp, it might not, we don't care.
- */
-#define RW_STORE(reg) \
-	std	%l0, [%reg + RW_L0]; \
-	std	%l2, [%reg + RW_L2]; \
-	std	%l4, [%reg + RW_L4]; \
-	std	%l6, [%reg + RW_L6]; \
-	std	%i0, [%reg + RW_I0]; \
-	std	%i2, [%reg + RW_I2]; \
-	std	%i4, [%reg + RW_I4]; \
-	std	%i6, [%reg + RW_I6];
-
-/* Load a register window from the area beginning at %reg. */
-#define RW_LOAD(reg) \
-	ldd	[%reg + RW_L0], %l0; \
-	ldd	[%reg + RW_L2], %l2; \
-	ldd	[%reg + RW_L4], %l4; \
-	ldd	[%reg + RW_L6], %l6; \
-	ldd	[%reg + RW_I0], %i0; \
-	ldd	[%reg + RW_I2], %i2; \
-	ldd	[%reg + RW_I4], %i4; \
-	ldd	[%reg + RW_I6], %i6;
-
-/* Loading and storing struct pt_reg trap frames. */
-#define PT_LOAD_INS(base_reg) \
-	ldd	[%base_reg + SF_REGS_SZ + PT_I0], %i0; \
-	ldd	[%base_reg + SF_REGS_SZ + PT_I2], %i2; \
-	ldd	[%base_reg + SF_REGS_SZ + PT_I4], %i4; \
-	ldd	[%base_reg + SF_REGS_SZ + PT_I6], %i6;
-
-#define PT_LOAD_GLOBALS(base_reg) \
-	ld	[%base_reg + SF_REGS_SZ + PT_G1], %g1; \
-	ldd	[%base_reg + SF_REGS_SZ + PT_G2], %g2; \
-	ldd	[%base_reg + SF_REGS_SZ + PT_G4], %g4; \
-	ldd	[%base_reg + SF_REGS_SZ + PT_G6], %g6;
-
-#define PT_LOAD_YREG(base_reg, scratch) \
-	ld	[%base_reg + SF_REGS_SZ + PT_Y], %scratch; \
-	wr	%scratch, 0x0, %y;
-
-#define PT_LOAD_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
-	ld	[%base_reg + SF_REGS_SZ + PT_PSR], %pt_psr; \
-	ld	[%base_reg + SF_REGS_SZ + PT_PC], %pt_pc; \
-	ld	[%base_reg + SF_REGS_SZ + PT_NPC], %pt_npc;
-
-#define PT_LOAD_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \
-	PT_LOAD_YREG(base_reg, scratch) \
-	PT_LOAD_INS(base_reg) \
-	PT_LOAD_GLOBALS(base_reg) \
-	PT_LOAD_PRIV(base_reg, pt_psr, pt_pc, pt_npc)
-
-#define PT_STORE_INS(base_reg) \
-	std	%i0, [%base_reg + SF_REGS_SZ + PT_I0]; \
-	std	%i2, [%base_reg + SF_REGS_SZ + PT_I2]; \
-	std	%i4, [%base_reg + SF_REGS_SZ + PT_I4]; \
-	std	%i6, [%base_reg + SF_REGS_SZ + PT_I6];
-
-#define PT_STORE_GLOBALS(base_reg) \
-	st	%g1, [%base_reg + SF_REGS_SZ + PT_G1]; \
-	std	%g2, [%base_reg + SF_REGS_SZ + PT_G2]; \
-	std	%g4, [%base_reg + SF_REGS_SZ + PT_G4]; \
-	std	%g6, [%base_reg + SF_REGS_SZ + PT_G6];
-
-#define PT_STORE_YREG(base_reg, scratch) \
-	rd	%y, %scratch; \
-	st	%scratch, [%base_reg + SF_REGS_SZ + PT_Y];
-
-#define PT_STORE_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
-	st	%pt_psr, [%base_reg + SF_REGS_SZ + PT_PSR]; \
-	st	%pt_pc,  [%base_reg + SF_REGS_SZ + PT_PC]; \
-	st	%pt_npc, [%base_reg + SF_REGS_SZ + PT_NPC];
-
-#define PT_STORE_ALL(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \
-	PT_STORE_PRIV(base_reg, reg_psr, reg_pc, reg_npc) \
-	PT_STORE_GLOBALS(base_reg) \
-	PT_STORE_YREG(base_reg, g_scratch) \
-	PT_STORE_INS(base_reg)
-
-/* Store the fpu register window*/
-#define FW_STORE(reg) \
-	std	%f0, [reg + FW_F0]; \
-	std	%f2, [reg + FW_F2]; \
-	std	%f4, [reg + FW_F4]; \
-	std	%f6, [reg + FW_F6]; \
-	std	%f8, [reg + FW_F8]; \
-	std	%f10, [reg + FW_F10]; \
-	std	%f12, [reg + FW_F12]; \
-	std	%f14, [reg + FW_F14]; \
-	std	%f16, [reg + FW_F16]; \
-	std	%f18, [reg + FW_F18]; \
-	std	%f20, [reg + FW_F20]; \
-	std	%f22, [reg + FW_F22]; \
-	std	%f24, [reg + FW_F24]; \
-	std	%f26, [reg + FW_F26]; \
-	std	%f28, [reg + FW_F28]; \
-	std	%f30, [reg + FW_F30]; \
-	st	%fsr, [reg + FW_FSR];
-
-/* Load a fpu register window from the area beginning at reg. */
-#define FW_LOAD(reg) \
-	ldd	[reg + FW_F0], %f0; \
-	ldd	[reg + FW_F2], %f2; \
-	ldd	[reg + FW_F4], %f4; \
-	ldd	[reg + FW_F6], %f6; \
-	ldd	[reg + FW_F8], %f8; \
-	ldd	[reg + FW_F10], %f10; \
-	ldd	[reg + FW_F12], %f12; \
-	ldd	[reg + FW_F14], %f14; \
-	ldd	[reg + FW_F16], %f16; \
-	ldd	[reg + FW_F18], %f18; \
-	ldd	[reg + FW_F20], %f20; \
-	ldd	[reg + FW_F22], %f22; \
-	ldd	[reg + FW_F24], %f24; \
-	ldd	[reg + FW_F26], %f26; \
-	ldd	[reg + FW_F28], %f28; \
-	ldd	[reg + FW_F30], %f30; \
-	ld	[reg + FW_FSR], %fsr;
-
-#endif
diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile
deleted file mode 100644
index 6b7ad6d..0000000
--- a/arch/sparc/lib/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2015
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y = cache.o interrupts.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/sparc/lib/bootm.c b/arch/sparc/lib/bootm.c
deleted file mode 100644
index 927a351..0000000
--- a/arch/sparc/lib/bootm.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/* SPARC code for booting linux 2.6
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/byteorder.h>
-#include <asm/prom.h>
-#include <asm/cache.h>
-#include <image.h>
-
-#define PRINT_KERNEL_HEADER
-
-extern image_header_t header;
-extern void srmmu_init_cpu(unsigned int entry);
-extern void prepare_bootargs(char *bootargs);
-
-/* sparc kernel argument (the ROM vector) */
-struct linux_romvec *kernel_arg_promvec;
-
-/* page szie is 4k */
-#define PAGE_SIZE 0x1000
-#define RAMDISK_IMAGE_START_MASK	0x07FF
-#define RAMDISK_PROMPT_FLAG		0x8000
-#define RAMDISK_LOAD_FLAG		0x4000
-struct __attribute__ ((packed)) {
-	char traptable[PAGE_SIZE];
-	char swapper_pg_dir[PAGE_SIZE];
-	char pg0[PAGE_SIZE];
-	char pg1[PAGE_SIZE];
-	char pg2[PAGE_SIZE];
-	char pg3[PAGE_SIZE];
-	char empty_bad_page[PAGE_SIZE];
-	char empty_bad_page_table[PAGE_SIZE];
-	char empty_zero_page[PAGE_SIZE];
-	unsigned char hdr[4];	/* ascii "HdrS" */
-	/* 00.02.06.0b is for Linux kernel 2.6.11 */
-	unsigned char linuxver_mega_major;
-	unsigned char linuxver_major;
-	unsigned char linuxver_minor;
-	unsigned char linuxver_revision;
-	/* header version 0x0203 */
-	unsigned short hdr_ver;
-	union __attribute__ ((packed)) {
-		struct __attribute__ ((packed)) {
-			unsigned short root_flags;
-			unsigned short root_dev;
-			unsigned short ram_flags;
-			unsigned int sparc_ramdisk_image;
-			unsigned int sparc_ramdisk_size;
-			unsigned int reboot_command;
-			unsigned int resv[3];
-			unsigned int end;
-		} ver_0203;
-	} hdr_input;
-} *linux_hdr;
-
-/* temporary initrd image holder */
-image_header_t ihdr;
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
-	/* Reserve the space used by PROM and stack. This is done
-	 * to avoid that the RAM image is copied over stack or
-	 * PROM.
-	 */
-	lmb_reserve(lmb, CONFIG_SYS_RELOC_MONITOR_BASE, CONFIG_SYS_RAM_END);
-}
-
-/* boot the linux kernel */
-int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t * images)
-{
-	char *bootargs;
-	ulong rd_len;
-	void (*kernel) (struct linux_romvec *, void *);
-	int ret;
-
-	/*
-	 * allow the PREP bootm subcommand, it is required for bootm to work
-	 */
-	if (flag & BOOTM_STATE_OS_PREP)
-		return 0;
-
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
-
-	/* Get virtual address of kernel start */
-	linux_hdr = (void *)images->os.load;
-
-	/* */
-	kernel = (void (*)(struct linux_romvec *, void *))images->ep;
-
-	/* check for a SPARC kernel */
-	if ((linux_hdr->hdr[0] != 'H') ||
-	    (linux_hdr->hdr[1] != 'd') ||
-	    (linux_hdr->hdr[2] != 'r') || (linux_hdr->hdr[3] != 'S')) {
-		puts("Error reading header of SPARC Linux kernel, aborting\n");
-		goto error;
-	}
-#ifdef PRINT_KERNEL_HEADER
-	printf("## Found SPARC Linux kernel %d.%d.%d ...\n",
-	       linux_hdr->linuxver_major,
-	       linux_hdr->linuxver_minor, linux_hdr->linuxver_revision);
-#endif
-
-	/* set basic boot params in kernel header now that it has been
-	 * extracted and is writeable.
-	 */
-
-	ret = image_setup_linux(images);
-	if (ret) {
-		puts("### Failed to relocate RAM disk\n");
-		goto error;
-	}
-
-	/* Calc length of RAM disk, if zero no ramdisk available */
-	rd_len = images->rd_end - images->rd_start;
-
-	if (rd_len) {
-		/* Update SPARC kernel header so that Linux knows
-		 * what is going on and where to find RAM disk.
-		 *
-		 * Set INITRD Image address relative to RAM Start
-		 */
-		linux_hdr->hdr_input.ver_0203.sparc_ramdisk_image =
-			images->initrd_start - CONFIG_SYS_RAM_BASE;
-		linux_hdr->hdr_input.ver_0203.sparc_ramdisk_size = rd_len;
-		/* Clear READ ONLY flag if set to non-zero */
-		linux_hdr->hdr_input.ver_0203.root_flags = 1;
-		/* Set root device to: Root_RAM0 */
-		linux_hdr->hdr_input.ver_0203.root_dev = 0x100;
-		linux_hdr->hdr_input.ver_0203.ram_flags = 0;
-	} else {
-		/* NOT using RAMDISK image, overwriting kernel defaults */
-		linux_hdr->hdr_input.ver_0203.sparc_ramdisk_image = 0;
-		linux_hdr->hdr_input.ver_0203.sparc_ramdisk_size = 0;
-		/* Leave to kernel defaults
-		   linux_hdr->hdr_input.ver_0203.root_flags = 1;
-		   linux_hdr->hdr_input.ver_0203.root_dev = 0;
-		   linux_hdr->hdr_input.ver_0203.ram_flags = 0;
-		 */
-	}
-
-	/* Copy bootargs from bootargs variable to kernel readable area */
-	bootargs = getenv("bootargs");
-	prepare_bootargs(bootargs);
-
-	/* turn on mmu & setup context table & page table for process 0 (kernel) */
-	srmmu_init_cpu((unsigned int)kernel);
-
-	/* Enter SPARC Linux kernel
-	 * From now on the only code in u-boot that will be
-	 * executed is the PROM code.
-	 */
-	kernel(kernel_arg_promvec, (void *)images->ep);
-
-	/* It will never come to this... */
-	while (1) ;
-
-      error:
-	return 1;
-}
diff --git a/arch/sparc/lib/cache.c b/arch/sparc/lib/cache.c
deleted file mode 100644
index fd17467..0000000
--- a/arch/sparc/lib/cache.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Sparc cache library
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-void flush_cache(ulong start_addr, ulong size)
-{
-	/* Flush All Cache */
-	sparc_dcache_flush_all();
-	sparc_icache_flush_all();
-}
diff --git a/arch/sparc/lib/interrupts.c b/arch/sparc/lib/interrupts.c
deleted file mode 100644
index cb73d17..0000000
--- a/arch/sparc/lib/interrupts.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Gleb Natapov <gnatapov@mrv.com>
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/irq.h>
-
-/* Implemented by SPARC CPUs */
-extern int interrupt_init_cpu(void);
-extern void timer_interrupt_cpu(void *arg);
-extern int timer_interrupt_init_cpu(void);
-
-int intLock(void)
-{
-	unsigned int pil;
-
-	pil = get_pil();
-
-	/* set PIL to 15 ==> no pending interrupts will interrupt CPU */
-	set_pil(15);
-
-	return pil;
-}
-
-void intUnlock(int oldLevel)
-{
-	set_pil(oldLevel);
-}
-
-void enable_interrupts(void)
-{
-	set_pil(0);		/* enable all interrupts */
-}
-
-int disable_interrupts(void)
-{
-	return intLock();
-}
-
-int interrupt_is_enabled(void)
-{
-	if (get_pil() == 15)
-		return 0;
-	return 1;
-}
-
-int interrupt_init(void)
-{
-	int ret;
-
-	/* call cpu specific function from $(CPU)/interrupts.c */
-	ret = interrupt_init_cpu();
-
-	/* enable global interrupts */
-	enable_interrupts();
-
-	return ret;
-}
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index dfdd756..9ead3eb 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -83,6 +83,8 @@ endchoice
 # subarchitectures-specific options below
 config INTEL_MID
 	bool "Intel MID platform support"
+	select REGMAP
+	select SYSCON
 	help
 	  Select to build a U-Boot capable of supporting Intel MID
 	  (Mobile Internet Device) platform systems which do not have
@@ -316,6 +318,22 @@ config X86_RAMTEST
 	  to work correctly. It is not exhaustive but can save time by
 	  detecting obvious failures.
 
+config FLASH_DESCRIPTOR_FILE
+	string "Flash descriptor binary filename"
+	depends on HAVE_INTEL_ME
+	default "descriptor.bin"
+	help
+	  The filename of the file to use as flash descriptor in the
+	  board directory.
+
+config INTEL_ME_FILE
+	string "Intel Management Engine binary filename"
+	depends on HAVE_INTEL_ME
+	default "me.bin"
+	help
+	  The filename of the file to use as Intel Management Engine in the
+	  board directory.
+
 config HAVE_FSP
 	bool "Add an Firmware Support Package binary"
 	depends on !EFI
diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
index 1b71d56..294dfa6 100644
--- a/arch/x86/cpu/broadwell/cpu.c
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -131,10 +131,8 @@ int arch_cpu_init(void)
 	return x86_cpu_init_f();
 }
 
-int print_cpuinfo(void)
+int checkcpu(void)
 {
-	char processor_name[CPU_MAX_NAME_LEN];
-	const char *name;
 	int ret;
 
 	set_max_freq();
@@ -144,6 +142,14 @@ int print_cpuinfo(void)
 		return ret;
 	gd->arch.pei_boot_mode = PEI_BOOT_NONE;
 
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	char processor_name[CPU_MAX_NAME_LEN];
+	const char *name;
+
 	/* Print processor name */
 	name = cpu_get_name(processor_name);
 	printf("CPU:   %s\n", name);
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index 74736cd..774aba6 100644
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -28,9 +28,11 @@ ulong board_get_usable_ram_top(ulong total_size)
 	return mrc_common_board_get_usable_ram_top(total_size);
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	mrc_common_dram_init_banksize();
+
+	return 0;
 }
 
 void broadwell_fill_pei_data(struct pei_data *pei_data)
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 1b04203..658b900 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -34,6 +34,11 @@ int board_early_init_f(void)
 	return 0;
 }
 
+int checkcpu(void)
+{
+	return 0;
+}
+
 int print_cpuinfo(void)
 {
 	return default_print_cpuinfo();
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
index 7115e7a..82407af 100644
--- a/arch/x86/cpu/coreboot/sdram.c
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -104,7 +104,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	int i, j;
 
@@ -121,4 +121,6 @@ void dram_init_banksize(void)
 			}
 		}
 	}
+
+	return 0;
 }
diff --git a/arch/x86/cpu/efi/efi.c b/arch/x86/cpu/efi/efi.c
index 993ab8d..741613f 100644
--- a/arch/x86/cpu/efi/efi.c
+++ b/arch/x86/cpu/efi/efi.c
@@ -18,6 +18,11 @@ int board_early_init_f(void)
 	return 0;
 }
 
+int checkcpu(void)
+{
+	return 0;
+}
+
 int print_cpuinfo(void)
 {
 	return default_print_cpuinfo();
diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c
index 5159944..413e55b 100644
--- a/arch/x86/cpu/efi/sdram.c
+++ b/arch/x86/cpu/efi/sdram.c
@@ -22,8 +22,10 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = efi_get_ram_base();
 	gd->bd->bi_dram[0].size = CONFIG_EFI_RAM_SIZE;
+
+	return 0;
 }
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index c4aca08..099cb94 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -74,7 +74,7 @@ int arch_cpu_init_dm(void)
 	/*
 	 * We should do as little as possible before the serial console is
 	 * up. Perhaps this should move to later. Our next lot of init
-	 * happens in print_cpuinfo() when we have a console
+	 * happens in checkcpu() when we have a console
 	 */
 	ret = set_flex_ratio_to_tdp_nominal();
 	if (ret)
@@ -125,12 +125,10 @@ static void enable_usb_bar(struct udevice *bus)
 	pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
 }
 
-int print_cpuinfo(void)
+int checkcpu(void)
 {
 	enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
-	char processor_name[CPU_MAX_NAME_LEN];
 	struct udevice *dev, *lpc;
-	const char *name;
 	uint32_t pm1_cnt;
 	uint16_t pm1_sts;
 	int ret;
@@ -182,6 +180,14 @@ int print_cpuinfo(void)
 
 	gd->arch.pei_boot_mode = boot_mode;
 
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	char processor_name[CPU_MAX_NAME_LEN];
+	const char *name;
+
 	/* Print processor name */
 	name = cpu_get_name(processor_name);
 	printf("CPU:   %s\n", name);
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 201368c..643d804 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -46,9 +46,11 @@ ulong board_get_usable_ram_top(ulong total_size)
 	return mrc_common_board_get_usable_ram_top(total_size);
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	mrc_common_dram_init_banksize();
+
+	return 0;
 }
 
 static int read_seed_from_cmos(struct pei_data *pei_data)
diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c
index a88d0d2..9d84af5 100644
--- a/arch/x86/cpu/qemu/dram.c
+++ b/arch/x86/cpu/qemu/dram.c
@@ -26,10 +26,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = 0;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 /*
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 7153eb2..35a146c 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -148,6 +148,12 @@ int arch_cpu_init(void)
 
 #if !CONFIG_IS_ENABLED(EFI_STUB) && \
 	!CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
+
+int checkcpu(void)
+{
+	return 0;
+}
+
 int print_cpuinfo(void)
 {
 	post_code(POST_CPU_INFO);
diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c
index 40c830a..47beb86 100644
--- a/arch/x86/cpu/quark/dram.c
+++ b/arch/x86/cpu/quark/dram.c
@@ -162,10 +162,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = 0;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 /*
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index bdd360a..0c2cea4 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -264,6 +264,11 @@ int arch_cpu_init_dm(void)
 	return 0;
 }
 
+int checkcpu(void)
+{
+	return 0;
+}
+
 int print_cpuinfo(void)
 {
 	post_code(POST_CPU_INFO);
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index f307c62..94668a4 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -76,13 +76,13 @@ static int __maybe_unused disable_igd(void)
 	 *
 	 * So the only option we have is to manually remove these two devices.
 	 */
-	ret = device_remove(igd);
+	ret = device_remove(igd, DM_REMOVE_NORMAL);
 	if (ret)
 		return ret;
 	ret = device_unbind(igd);
 	if (ret)
 		return ret;
-	ret = device_remove(sdvo);
+	ret = device_remove(sdvo, DM_REMOVE_NORMAL);
 	if (ret)
 		return ret;
 	ret = device_unbind(sdvo);
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index db171f7..cafae15 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -67,6 +67,11 @@ int misc_init_r(void)
 	return 0;
 }
 
+int checkcpu(void)
+{
+	return 0;
+}
+
 int print_cpuinfo(void)
 {
 	return 0;
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 69c1c1d..a4321d3 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -17,8 +17,10 @@
 		size = <CONFIG_ROM_SIZE>;
 #ifdef CONFIG_HAVE_INTEL_ME
 		intel-descriptor {
+			filename = CONFIG_FLASH_DESCRIPTOR_FILE;
 		};
 		intel-me {
+			filename = CONFIG_INTEL_ME_FILE;
 		};
 #endif
 #ifdef CONFIG_SPL
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index c651f2f..c00687a 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -54,6 +54,8 @@ enum {
 	X86_NONE,
 	X86_SYSCON_ME,		/* Intel Management Engine */
 	X86_SYSCON_PINCONF,	/* Intel x86 pin configuration */
+	X86_SYSCON_PMU,		/* Power Management Unit */
+	X86_SYSCON_SCU,		/* System Controller Unit */
 };
 
 struct cpuid_result {
diff --git a/arch/x86/include/asm/pmu.h b/arch/x86/include/asm/pmu.h
new file mode 100644
index 0000000..96b968f
--- /dev/null
+++ b/arch/x86/include/asm/pmu.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _X86_ASM_PMU_IPC_H_
+#define _X86_ASM_PMU_IPC_H_
+
+int pmu_turn_power(unsigned int lss, bool on);
+
+#endif	/* _X86_ASM_PMU_IPC_H_ */
diff --git a/arch/x86/include/asm/relocate.h b/arch/x86/include/asm/relocate.h
deleted file mode 100644
index cff3abc..0000000
--- a/arch/x86/include/asm/relocate.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * (C) Copyright 2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _RELOCATE_H_
-#define _RELOCATE_H_
-
-#include <common.h>
-
-int copy_uboot_to_ram(void);
-int clear_bss(void);
-int do_elf_reloc_fixups(void);
-
-#endif	/* !_RELOCATE_H_ */
diff --git a/arch/x86/include/asm/scu.h b/arch/x86/include/asm/scu.h
new file mode 100644
index 0000000..4d40e49
--- /dev/null
+++ b/arch/x86/include/asm/scu.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _X86_ASM_SCU_IPC_H_
+#define _X86_ASM_SCU_IPC_H_
+
+/* IPC defines the following message types */
+#define IPCMSG_WARM_RESET	0xf0
+#define IPCMSG_COLD_RESET	0xf1
+#define IPCMSG_SOFT_RESET	0xf2
+#define IPCMSG_COLD_BOOT	0xf3
+#define IPCMSG_GET_FW_REVISION	0xf4
+#define IPCMSG_WATCHDOG_TIMER	0xf8	/* Set Kernel Watchdog Threshold */
+
+struct ipc_ifwi_version {
+	u16	minor;
+	u8	major;
+	u8	hardware_id;
+	u32	reserved[3];
+};
+
+/* Issue commands to the SCU with or without data */
+int scu_ipc_simple_command(u32 cmd, u32 sub);
+int scu_ipc_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out, int outlen);
+
+#endif	/* _X86_ASM_SCU_IPC_H_ */
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 4f901f9..d2d6039 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -41,7 +41,6 @@ void x86_disable_caches(void);
 int x86_init_cache(void);
 void reset_cpu(ulong addr);
 ulong board_get_usable_ram_top(ulong total_size);
-void dram_init_banksize(void);
 int default_print_cpuinfo(void);
 
 /* Set up a UART which can be used with printch(), printhex8(), etc. */
@@ -55,9 +54,6 @@ u32 isa_map_rom(u32 bus_addr, int size);
 /* arch/x86/lib/... */
 int video_bios_init(void);
 
-/* arch/x86/lib/fsp/... */
-int x86_fsp_init(void);
-
 void	board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
 void	board_init_f_r(void) __attribute__ ((noreturn));
 
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 1c2c085..d1ad37a 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -31,7 +31,9 @@ obj-y	+= pinctrl_ich6.o
 obj-y	+= pirq_routing.o
 obj-y	+= relocate.o
 obj-y += physmem.o
+obj-$(CONFIG_INTEL_MID) += pmu.o
 obj-$(CONFIG_X86_RAMTEST) += ramtest.o
+obj-$(CONFIG_INTEL_MID) += scu.o
 obj-y	+= sections.o
 obj-y += sfi.o
 obj-y	+= string.o
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 3c3d9e1..75bab90 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -100,7 +100,7 @@ static int boot_prep_linux(bootm_headers_t *images)
 		}
 		is_zimage = 1;
 #if defined(CONFIG_FIT)
-	} else if (images->fit_uname_os && is_zimage) {
+	} else if (images->fit_uname_os) {
 		ret = fit_image_get_data(images->fit_hdr_os,
 				images->fit_noffset_os,
 				(const void **)&data, &len);
diff --git a/arch/x86/lib/efi/efi.c b/arch/x86/lib/efi/efi.c
index ede5d56..b1746fa 100644
--- a/arch/x86/lib/efi/efi.c
+++ b/arch/x86/lib/efi/efi.c
@@ -92,7 +92,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	struct efi_mem_desc *desc, *end;
 	struct efi_entry_memmap *map;
@@ -103,7 +103,7 @@ void dram_init_banksize(void)
 	if (ret) {
 		/* We should have stopped in dram_init(), something is wrong */
 		debug("%s: Missing memory map\n", __func__);
-		return;
+		return -ENXIO;
 	}
 	end = (struct efi_mem_desc *)((ulong)map + size);
 	desc = map->desc;
@@ -123,6 +123,13 @@ void dram_init_banksize(void)
 			EFI_PAGE_SHIFT;
 		num_banks++;
 	}
+
+	return 0;
+}
+
+int checkcpu(void)
+{
+	return 0;
 }
 
 int print_cpuinfo(void)
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index 8479af1..66a388d 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -14,6 +14,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int checkcpu(void)
+{
+	return 0;
+}
+
 int print_cpuinfo(void)
 {
 	post_code(POST_CPU_INFO);
@@ -70,7 +75,7 @@ static __maybe_unused void *fsp_prepare_mrc_cache(void)
 	return cache->data;
 }
 
-int x86_fsp_init(void)
+int arch_fsp_init(void)
 {
 	void *nvs;
 
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index fcfe693..8b880cd 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -41,10 +41,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = 0;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 /*
diff --git a/arch/x86/lib/pmu.c b/arch/x86/lib/pmu.c
new file mode 100644
index 0000000..4ceab8d
--- /dev/null
+++ b/arch/x86/lib/pmu.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/cpu.h>
+#include <asm/pmu.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+/* Registers */
+struct pmu_regs {
+	u32	sts;
+	u32	cmd;
+	u32	ics;
+	u32	reserved;
+	u32	wkc[4];
+	u32	wks[4];
+	u32	ssc[4];
+	u32	sss[4];
+};
+
+/* Bits in PMU_REGS_STS */
+#define PMU_REGS_STS_BUSY		(1 << 8)
+
+struct pmu_mid {
+	struct pmu_regs *regs;
+};
+
+static int pmu_read_status(struct pmu_regs *regs)
+{
+	int retry = 500000;
+	u32 val;
+
+	do {
+		val = readl(&regs->sts);
+		if (!(val & PMU_REGS_STS_BUSY))
+			return 0;
+
+		udelay(1);
+	} while (--retry);
+
+	printf("WARNING: PMU still busy\n");
+	return -EBUSY;
+}
+
+static int pmu_power_lss(struct pmu_regs *regs, unsigned int lss, bool on)
+{
+	unsigned int offset = (lss * 2) / 32;
+	unsigned int shift = (lss * 2) % 32;
+	u32 ssc;
+	int ret;
+
+	/* Check PMU status */
+	ret = pmu_read_status(regs);
+	if (ret)
+		return ret;
+
+	/* Read PMU values */
+	ssc = readl(&regs->sss[offset]);
+
+	/* Modify PMU values */
+	if (on)
+		ssc &= ~(0x3 << shift);		/* D0 */
+	else
+		ssc |= 0x3 << shift;		/* D3hot */
+
+	/* Write modified PMU values */
+	writel(ssc, &regs->ssc[offset]);
+
+	/* Update modified PMU values */
+	writel(0x00002201, &regs->cmd);
+
+	/* Check PMU status */
+	return pmu_read_status(regs);
+}
+
+int pmu_turn_power(unsigned int lss, bool on)
+{
+	struct pmu_mid *pmu;
+	struct udevice *dev;
+	int ret;
+
+	ret = syscon_get_by_driver_data(X86_SYSCON_PMU, &dev);
+	if (ret)
+		return ret;
+
+	pmu = dev_get_priv(dev);
+
+	return pmu_power_lss(pmu->regs, lss, on);
+}
+
+static int pmu_mid_probe(struct udevice *dev)
+{
+	struct pmu_mid *pmu = dev_get_priv(dev);
+
+	pmu->regs = syscon_get_first_range(X86_SYSCON_PMU);
+
+	return 0;
+}
+
+static const struct udevice_id pmu_mid_match[] = {
+	{ .compatible = "intel,pmu-mid", .data = X86_SYSCON_PMU },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(intel_mid_pmu) = {
+	.name		= "pmu_mid",
+	.id		= UCLASS_SYSCON,
+	.of_match	= pmu_mid_match,
+	.probe		= pmu_mid_probe,
+	.priv_auto_alloc_size = sizeof(struct pmu_mid),
+};
diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c
index 1da5210..114f602 100644
--- a/arch/x86/lib/relocate.c
+++ b/arch/x86/lib/relocate.c
@@ -17,8 +17,8 @@
 
 #include <common.h>
 #include <inttypes.h>
+#include <relocate.h>
 #include <asm/u-boot-x86.h>
-#include <asm/relocate.h>
 #include <asm/sections.h>
 #include <elf.h>
 
diff --git a/arch/x86/lib/scu.c b/arch/x86/lib/scu.c
new file mode 100644
index 0000000..bb23d0b
--- /dev/null
+++ b/arch/x86/lib/scu.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * Intel Mobile Internet Devices (MID) based on Intel Atom SoCs have few
+ * microcontrollers inside to do some auxiliary tasks. One of such
+ * microcontroller is System Controller Unit (SCU) which, in particular,
+ * is servicing watchdog and controlling system reset function.
+ *
+ * This driver enables IPC channel to SCU.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/cpu.h>
+#include <asm/scu.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+/* SCU register map */
+struct ipc_regs {
+	u32 cmd;
+	u32 status;
+	u32 sptr;
+	u32 dptr;
+	u32 reserved[28];
+	u32 wbuf[4];
+	u32 rbuf[4];
+};
+
+struct scu {
+	struct ipc_regs *regs;
+};
+
+/**
+ * scu_ipc_send_command() - send command to SCU
+ * @regs: register map of SCU
+ * @cmd: command
+ *
+ * Command Register (Write Only):
+ * A write to this register results in an interrupt to the SCU core processor
+ * Format:
+ * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
+ */
+static void scu_ipc_send_command(struct ipc_regs *regs, u32 cmd)
+{
+	writel(cmd, &regs->cmd);
+}
+
+/**
+ * scu_ipc_check_status() - check status of last command
+ * @regs: register map of SCU
+ *
+ * Status Register (Read Only):
+ * Driver will read this register to get the ready/busy status of the IPC
+ * block and error status of the IPC command that was just processed by SCU
+ * Format:
+ * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
+ */
+static int scu_ipc_check_status(struct ipc_regs *regs)
+{
+	int loop_count = 100000;
+	int status;
+
+	do {
+		status = readl(&regs->status);
+		if (!(status & BIT(0)))
+			break;
+
+		udelay(1);
+	} while (--loop_count);
+	if (!loop_count)
+		return -ETIMEDOUT;
+
+	if (status & BIT(1)) {
+		printf("%s() status=0x%08x\n", __func__, status);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int scu_ipc_cmd(struct ipc_regs *regs, u32 cmd, u32 sub,
+		       u32 *in, int inlen, u32 *out, int outlen)
+{
+	int i, err;
+
+	for (i = 0; i < inlen; i++)
+		writel(*in++, &regs->wbuf[i]);
+
+	scu_ipc_send_command(regs, (inlen << 16) | (sub << 12) | cmd);
+	err = scu_ipc_check_status(regs);
+
+	if (!err) {
+		for (i = 0; i < outlen; i++)
+			*out++ = readl(&regs->rbuf[i]);
+	}
+
+	return err;
+}
+
+/**
+ * scu_ipc_simple_command() - send a simple command
+ * @cmd: command
+ * @sub: sub type
+ *
+ * Issue a simple command to the SCU. Do not use this interface if
+ * you must then access data as any data values may be overwritten
+ * by another SCU access by the time this function returns.
+ *
+ * This function may sleep. Locking for SCU accesses is handled for
+ * the caller.
+ */
+int scu_ipc_simple_command(u32 cmd, u32 sub)
+{
+	struct scu *scu;
+	struct udevice *dev;
+	int ret;
+
+	ret = syscon_get_by_driver_data(X86_SYSCON_SCU, &dev);
+	if (ret)
+		return ret;
+
+	scu = dev_get_priv(dev);
+
+	scu_ipc_send_command(scu->regs, sub << 12 | cmd);
+	return scu_ipc_check_status(scu->regs);
+}
+
+int scu_ipc_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out, int outlen)
+{
+	struct scu *scu;
+	struct udevice *dev;
+	int ret;
+
+	ret = syscon_get_by_driver_data(X86_SYSCON_SCU, &dev);
+	if (ret)
+		return ret;
+
+	scu = dev_get_priv(dev);
+
+	return scu_ipc_cmd(scu->regs, cmd, sub, in, inlen, out, outlen);
+}
+
+static int scu_ipc_probe(struct udevice *dev)
+{
+	struct scu *scu = dev_get_priv(dev);
+
+	scu->regs = syscon_get_first_range(X86_SYSCON_SCU);
+
+	return 0;
+}
+
+static const struct udevice_id scu_ipc_match[] = {
+	{ .compatible = "intel,scu-ipc", .data = X86_SYSCON_SCU },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(scu_ipc) = {
+	.name		= "scu_ipc",
+	.id		= UCLASS_SYSCON,
+	.of_match	= scu_ipc_match,
+	.probe		= scu_ipc_probe,
+	.priv_auto_alloc_size = sizeof(struct scu),
+};
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index ed2d40b..2b1b450 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -6,9 +6,9 @@
 
 #include <common.h>
 #include <debug_uart.h>
+#include <init_helpers.h>
 #include <spl.h>
 #include <asm/cpu.h>
-#include <asm/init_helpers.h>
 #include <asm/mtrr.h>
 #include <asm/processor.h>
 #include <asm-generic/sections.h>
diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c
index 6787a61..7044480 100644
--- a/arch/xtensa/cpu/cpu.c
+++ b/arch/xtensa/cpu/cpu.c
@@ -47,3 +47,8 @@ int arch_cpu_init(void)
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 	return 0;
 }
+
+int dram_init(void)
+{
+	return 0;
+}
diff --git a/arch/xtensa/include/asm/relocate.h b/arch/xtensa/include/asm/relocate.h
deleted file mode 100644
index 9c4ce23..0000000
--- a/arch/xtensa/include/asm/relocate.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2016 Cadence Design Systems Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_XTENSA_RELOCATE_H
-#define _ASM_XTENSA_RELOCATE_H
-
-#include <common.h>
-
-int clear_bss(void);
-
-#endif	/* _ASM_XTENSA_RELOCATE_H */
diff --git a/arch/xtensa/lib/relocate.c b/arch/xtensa/lib/relocate.c
index 3f747ec..010c1b0 100644
--- a/arch/xtensa/lib/relocate.c
+++ b/arch/xtensa/lib/relocate.c
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <asm/relocate.h>
+#include <relocate.h>
 #include <asm/sections.h>
 #include <asm/string.h>
 
diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c
index 84c77f7..805a266 100644
--- a/board/AndesTech/adp-ag101p/adp-ag101p.c
+++ b/board/AndesTech/adp-ag101p/adp-ag101p.c
@@ -49,12 +49,14 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
 	gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 int board_eth_init(bd_t *bd)
diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c
index 3a775be..cd484fc 100644
--- a/board/Arcturus/ucp1020/spl.c
+++ b/board/Arcturus/ucp1020/spl.c
@@ -110,7 +110,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	gd->ram_size = initdram(0);
+	dram_init();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else
diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c
index 9747f32..fd1965d 100644
--- a/board/Barix/ipam390/ipam390.c
+++ b/board/Barix/ipam390/ipam390.c
@@ -188,9 +188,7 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-#ifndef CONFIG_USE_IRQ
 	irq_init();
-#endif
 
 	/* arch number of the board */
 	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c
index b1740ee..a00a83a 100644
--- a/board/BuS/eb_cpu5282/eb_cpu5282.c
+++ b/board/BuS/eb_cpu5282/eb_cpu5282.c
@@ -35,7 +35,7 @@ int checkboard (void)
 	return 0;
 }
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	int size, i;
 
@@ -92,7 +92,9 @@ phys_size_t initdram (int board_type)
 	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
 	size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
 #endif
-	return size;
+	gd->ram_size = size;
+
+	return 0;
 }
 
 #if defined(CONFIG_SYS_DRAM_TEST)
diff --git a/board/Marvell/mvebu_db-88f3720/MAINTAINERS b/board/Marvell/mvebu_armada-37xx/MAINTAINERS
index 4e80917..52a3869 100644
--- a/board/Marvell/mvebu_db-88f3720/MAINTAINERS
+++ b/board/Marvell/mvebu_armada-37xx/MAINTAINERS
@@ -1,6 +1,6 @@
 MVEBU_DB_88F3720 BOARD
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
-F:	board/Marvell/mvebu_db-88f3720/
-F:	include/configs/mvebu_db-88f3720.h
+F:	board/Marvell/mvebu_armada-37xx/
+F:	include/configs/mvebu_armada-37xx.h
 F:	configs/mvebu_db-88f3720_defconfig
diff --git a/board/Marvell/mvebu_db-88f3720/Makefile b/board/Marvell/mvebu_armada-37xx/Makefile
index ed39738..ed39738 100644
--- a/board/Marvell/mvebu_db-88f3720/Makefile
+++ b/board/Marvell/mvebu_armada-37xx/Makefile
diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c
new file mode 100644
index 0000000..8dc1f46
--- /dev/null
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -0,0 +1,258 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <phy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* IO expander I2C device */
+#define I2C_IO_EXP_ADDR		0x22
+#define I2C_IO_CFG_REG_0	0x6
+#define I2C_IO_DATA_OUT_REG_0	0x2
+#define I2C_IO_REG_0_SATA_OFF	2
+#define I2C_IO_REG_0_USB_H_OFF	1
+
+/* The pin control values are the same for DB and Espressobin */
+#define PINCTRL_NB_REG_VALUE	0x000173fa
+#define PINCTRL_SB_REG_VALUE	0x00007a23
+
+/* Ethernet switch registers */
+/* SMI addresses for multi-chip mode */
+#define MVEBU_PORT_CTRL_SMI_ADDR(p)	(16 + (p))
+#define MVEBU_SW_G2_SMI_ADDR		(28)
+
+/* Multi-chip mode */
+#define MVEBU_SW_SMI_DATA_REG		(1)
+#define MVEBU_SW_SMI_CMD_REG		(0)
+ #define SW_SMI_CMD_REG_ADDR_OFF	0
+ #define SW_SMI_CMD_DEV_ADDR_OFF	5
+ #define SW_SMI_CMD_SMI_OP_OFF		10
+ #define SW_SMI_CMD_SMI_MODE_OFF	12
+ #define SW_SMI_CMD_SMI_BUSY_OFF	15
+
+/* Single-chip mode */
+/* Switch Port Registers */
+#define MVEBU_SW_LINK_CTRL_REG		(1)
+#define MVEBU_SW_PORT_CTRL_REG		(4)
+
+/* Global 2 Registers */
+#define MVEBU_G2_SMI_PHY_CMD_REG	(24)
+#define MVEBU_G2_SMI_PHY_DATA_REG	(25)
+
+int board_early_init_f(void)
+{
+	const void *blob = gd->fdt_blob;
+	const char *bank_name;
+	const char *compat = "marvell,armada-3700-pinctl";
+	int off, len;
+	void __iomem *addr;
+
+	/* FIXME
+	 * Temporary WA for setting correct pin control values
+	 * until the real pin control driver is awailable.
+	 */
+	off = fdt_node_offset_by_compatible(blob, -1, compat);
+	while (off != -FDT_ERR_NOTFOUND) {
+		bank_name = fdt_getprop(blob, off, "bank-name", &len);
+		addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(
+				blob, off, "reg", 0, NULL, true);
+		if (!strncmp(bank_name, "armada-3700-nb", len))
+			writel(PINCTRL_NB_REG_VALUE, addr);
+		else if (!strncmp(bank_name, "armada-3700-sb", len))
+			writel(PINCTRL_SB_REG_VALUE, addr);
+
+		off = fdt_node_offset_by_compatible(blob, off, compat);
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+/* Board specific AHCI / SATA enable code */
+int board_ahci_enable(void)
+{
+	struct udevice *dev;
+	int ret;
+	u8 buf[8];
+
+	/* Only DB requres this configuration */
+	if (!of_machine_is_compatible("marvell,armada-3720-db"))
+		return 0;
+
+	/* Configure IO exander PCA9555: 7bit address 0x22 */
+	ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
+	if (ret) {
+		printf("Cannot find PCA9555: %d\n", ret);
+		return 0;
+	}
+
+	ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to read IO expander value via I2C\n");
+		return -EIO;
+	}
+
+	/*
+	 * Enable SATA power via IO expander connected via I2C by setting
+	 * the corresponding bit to output mode to enable power for SATA
+	 */
+	buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
+	ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to set IO expander via I2C\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/* Board specific xHCI enable code */
+int board_xhci_enable(void)
+{
+	struct udevice *dev;
+	int ret;
+	u8 buf[8];
+
+	/* Only DB requres this configuration */
+	if (!of_machine_is_compatible("marvell,armada-3720-db"))
+		return 0;
+
+	/* Configure IO exander PCA9555: 7bit address 0x22 */
+	ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
+	if (ret) {
+		printf("Cannot find PCA9555: %d\n", ret);
+		return 0;
+	}
+
+	printf("Enable USB VBUS\n");
+
+	/*
+	 * Read configuration (direction) and set VBUS pin as output
+	 * (reset pin = output)
+	 */
+	ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to read IO expander value via I2C\n");
+		return -EIO;
+	}
+	buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
+	ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to set IO expander via I2C\n");
+		return -EIO;
+	}
+
+	/* Read VBUS output value and disable it */
+	ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to read IO expander value via I2C\n");
+		return -EIO;
+	}
+	buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
+	ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to set IO expander via I2C\n");
+		return -EIO;
+	}
+
+	/*
+	 * Required delay for configuration to settle - must wait for
+	 * power on port is disabled in case VBUS signal was high,
+	 * required 3 seconds delay to let VBUS signal fully settle down
+	 */
+	mdelay(3000);
+
+	/* Enable VBUS power: Set output value of VBUS pin as enabled */
+	buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
+	ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to set IO expander via I2C\n");
+		return -EIO;
+	}
+
+	mdelay(500); /* required delay to let output value settle */
+
+	return 0;
+}
+
+/* Helper function for accessing switch devices in multi-chip connection mode */
+static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
+				     int smi_addr, int reg, u16 value)
+{
+	u16 smi_cmd = 0;
+
+	if (bus->write(bus, dev_smi_addr, 0,
+		       MVEBU_SW_SMI_DATA_REG, value) != 0) {
+		printf("Error writing to the PHY addr=%02x reg=%02x\n",
+		       smi_addr, reg);
+		return -EFAULT;
+	}
+
+	smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
+		  (1 << SW_SMI_CMD_SMI_MODE_OFF) |
+		  (1 << SW_SMI_CMD_SMI_OP_OFF) |
+		  (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
+		  (reg << SW_SMI_CMD_REG_ADDR_OFF);
+	if (bus->write(bus, dev_smi_addr, 0,
+		       MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
+		printf("Error writing to the PHY addr=%02x reg=%02x\n",
+		       smi_addr, reg);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/* Bring-up board-specific network stuff */
+int board_network_enable(struct mii_dev *bus)
+{
+	if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
+		return 0;
+
+	/*
+	 * FIXME: remove this code once Topaz driver gets available
+	 * A3720 Community Board Only
+	 * Configure Topaz switch (88E6341)
+	 * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
+	 */
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
+				  MVEBU_SW_PORT_CTRL_REG, 0x7f);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
+				  MVEBU_SW_PORT_CTRL_REG, 0x7f);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
+				  MVEBU_SW_PORT_CTRL_REG, 0x7f);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
+				  MVEBU_SW_PORT_CTRL_REG, 0x7f);
+
+	/* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
+				  MVEBU_SW_LINK_CTRL_REG, 0xe002);
+
+	/* Power up PHY 1, 2, 3 (through Global 2 registers) */
+	mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
+				  MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
+				  MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
+				  MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
+				  MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
+
+	return 0;
+}
diff --git a/board/Marvell/mvebu_db-88f3720/board.c b/board/Marvell/mvebu_db-88f3720/board.c
deleted file mode 100644
index edf88c7..0000000
--- a/board/Marvell/mvebu_db-88f3720/board.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Copyright (C) 2016 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* IO expander I2C device */
-#define I2C_IO_EXP_ADDR		0x22
-#define I2C_IO_CFG_REG_0	0x6
-#define I2C_IO_DATA_OUT_REG_0	0x2
-#define I2C_IO_REG_0_SATA_OFF	2
-#define I2C_IO_REG_0_USB_H_OFF	1
-
-int board_early_init_f(void)
-{
-	/* Nothing to do (yet), perhaps later some pin-muxing etc */
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	return 0;
-}
-
-/* Board specific AHCI / SATA enable code */
-int board_ahci_enable(void)
-{
-	struct udevice *dev;
-	int ret;
-	u8 buf[8];
-
-	/* Configure IO exander PCA9555: 7bit address 0x22 */
-	ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
-	if (ret) {
-		printf("Cannot find PCA9555: %d\n", ret);
-		return 0;
-	}
-
-	ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
-	if (ret) {
-		printf("Failed to read IO expander value via I2C\n");
-		return -EIO;
-	}
-
-	/*
-	 * Enable SATA power via IO expander connected via I2C by setting
-	 * the corresponding bit to output mode to enable power for SATA
-	 */
-	buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
-	ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
-	if (ret) {
-		printf("Failed to set IO expander via I2C\n");
-		return -EIO;
-	}
-
-	return 0;
-}
-
-/* Board specific xHCI enable code */
-int board_xhci_enable(void)
-{
-	struct udevice *dev;
-	int ret;
-	u8 buf[8];
-
-	/* Configure IO exander PCA9555: 7bit address 0x22 */
-	ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
-	if (ret) {
-		printf("Cannot find PCA9555: %d\n", ret);
-		return 0;
-	}
-
-	printf("Enable USB VBUS\n");
-
-	/*
-	 * Read configuration (direction) and set VBUS pin as output
-	 * (reset pin = output)
-	 */
-	ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
-	if (ret) {
-		printf("Failed to read IO expander value via I2C\n");
-		return -EIO;
-	}
-	buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
-	ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
-	if (ret) {
-		printf("Failed to set IO expander via I2C\n");
-		return -EIO;
-	}
-
-	/* Read VBUS output value and disable it */
-	ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
-	if (ret) {
-		printf("Failed to read IO expander value via I2C\n");
-		return -EIO;
-	}
-	buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
-	ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
-	if (ret) {
-		printf("Failed to set IO expander via I2C\n");
-		return -EIO;
-	}
-
-	/*
-	 * Required delay for configuration to settle - must wait for
-	 * power on port is disabled in case VBUS signal was high,
-	 * required 3 seconds delay to let VBUS signal fully settle down
-	 */
-	mdelay(3000);
-
-	/* Enable VBUS power: Set output value of VBUS pin as enabled */
-	buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
-	ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
-	if (ret) {
-		printf("Failed to set IO expander via I2C\n");
-		return -EIO;
-	}
-
-	mdelay(500); /* required delay to let output value settle */
-
-	return 0;
-}
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c
index 55d0bc8..7e16aaf 100644
--- a/board/a3m071/a3m071.c
+++ b/board/a3m071/a3m071.c
@@ -72,11 +72,11 @@ static void sdram_start(int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
@@ -153,7 +153,9 @@ phys_size_t initdram(int board_type)
 	if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
 		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
 
-	return dramsize + dramsize2;
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
 }
 
 static void get_revisions(int *failsavelevel, int *digiboardversion,
diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c
index 20d8b80..6f0d448 100644
--- a/board/a4m072/a4m072.c
+++ b/board/a4m072/a4m072.c
@@ -23,6 +23,8 @@
 
 #include "mt46v32m16.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
@@ -66,12 +68,12 @@ static void sdram_start (int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 	uint svr, pvr;
@@ -150,7 +152,9 @@ phys_size_t initdram (int board_type)
 		__asm__ volatile ("sync");
 	}
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 }
 
 int checkboard (void)
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 9673118..36500da 100644
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -15,6 +15,8 @@
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern void board_pll_init_f(void);
 
 static void cram_bcr_write(u32 wr_val)
@@ -41,7 +43,7 @@ static void cram_bcr_write(u32 wr_val)
 	return;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	int i;
 	u32 val;
@@ -77,5 +79,7 @@ phys_size_t initdram(int board_type)
 	for (i=0; i<200000; i++)
 		;
 
-	return (CONFIG_SYS_MBYTES_RAM << 20);
+	gd->ram_size = CONFIG_SYS_MBYTES_RAM << 20;
+
+	return 0;
 }
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 2838f9a..6a50b39 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -12,6 +12,8 @@
 #include <asm/ppc440.h>
 #include "bamboo.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void ext_bus_cntlr_init(void);
 void configure_ppc440ep_pins(void);
 int is_nand_selected(void);
@@ -436,9 +438,11 @@ int checkboard(void)
 }
 
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
-	return spd_sdram();
+	gd->ram_size = spd_sdram();
+
+	return 0;
 }
 
 /*----------------------------------------------------------------------------+
diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c
index 9043de6..c73424d 100644
--- a/board/amcc/bubinga/bubinga.c
+++ b/board/amcc/bubinga/bubinga.c
@@ -9,6 +9,8 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 long int spd_sdram(void);
 
 int board_early_init_f(void)
@@ -52,10 +54,12 @@ int checkboard(void)
 }
 
 /* -------------------------------------------------------------------------
-  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  dram_init() reads EEPROM via I2c. EEPROM contains all of
   the necessary info for SDRAM controller configuration
    ------------------------------------------------------------------------- */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return spd_sdram();
+	gd->ram_size = spd_sdram();
+
+	return 0;
 }
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index 67640d7..ea98717 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -20,6 +20,8 @@
 #include <asm/io.h>
 #include <asm/ppc440.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*-----------------------------------------------------------------------------+
  * Prototypes
  *-----------------------------------------------------------------------------*/
@@ -28,10 +30,10 @@ extern void denali_core_search_data_eye(void);
 
 /*************************************************************************
  *
- * initdram -- 440EPx's DDR controller is a DENALI Core
+ * dram_init -- 440EPx's DDR controller is a DENALI Core
  *
  ************************************************************************/
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 #if !defined(CONFIG_SYS_RAMBOOT)
 	ulong speed = get_bus_freq(0);
@@ -88,5 +90,7 @@ phys_size_t initdram (int board_type)
 	 */
 	set_mcsr(get_mcsr());
 
-	return (CONFIG_SYS_MBYTES_SDRAM << 20);
+	gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
+
+	return 0;
 }
diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c
index c948209..b21daa0 100644
--- a/board/amcc/walnut/walnut.c
+++ b/board/amcc/walnut/walnut.c
@@ -9,6 +9,8 @@
 #include <asm/processor.h>
 #include <spd_sdram.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int board_early_init_f(void)
 {
 	/*-------------------------------------------------------------------------+
@@ -71,10 +73,12 @@ int checkboard(void)
 }
 
 /*
- * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ * dram_init() reads EEPROM via I2c. EEPROM contains all of
  * the necessary info for SDRAM controller configuration
  */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return spd_sdram();
+	gd->ram_size = spd_sdram();
+
+	return 0;
 }
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 56b5191..f46aacf 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -205,7 +205,7 @@ int checkboard(void)
 }
 
 /*************************************************************************
- *  initdram -- doesn't use serial presence detect.
+ *  dram_init -- doesn't use serial presence detect.
  *
  *  Assumes:    256 MB, ECC, non-registered
  *              PLB @ 133 MHz
@@ -286,7 +286,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
 	*tr1_value = (first_good + last_bad) / 2;
 }
 
-phys_size_t initdram(int board)
+int dram_init(void)
 {
 	register uint reg;
 	int tr1_bank1, tr1_bank2;
@@ -334,7 +334,10 @@ phys_size_t initdram(int board)
 	sdram_tr1_set(0x08000000, &tr1_bank2);
 	mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
 
-	return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024);	/* return bytes */
+	gd->ram_size = CONFIG_SYS_SDRAM_BANKS *
+		(CONFIG_SYS_KBYTES_SDRAM * 1024);	/* set bytes */
+
+	return 0;
 }
 
 /*************************************************************************
diff --git a/board/aries/m53evk/m53evk.c b/board/aries/m53evk/m53evk.c
index cbfc2a2..14c60fc 100644
--- a/board/aries/m53evk/m53evk.c
+++ b/board/aries/m53evk/m53evk.c
@@ -59,13 +59,15 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = mx53_dram_size[0];
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+	return 0;
 }
 
 static void setup_iomux_uart(void)
diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
index 16adf6e..1abfe88 100644
--- a/board/armadeus/apf27/apf27.c
+++ b/board/armadeus/apf27/apf27.c
@@ -193,7 +193,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size  = get_ram_size((void *)PHYS_SDRAM_1,
@@ -204,6 +204,8 @@ void dram_init_banksize(void)
 					     PHYS_SDRAM_2_SIZE);
 	else
 		gd->bd->bi_dram[1].size = 0;
+
+	return 0;
 }
 
 ulong board_get_usable_ram_top(ulong total_size)
diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c
index d3b3b31..458f1d8 100644
--- a/board/armltd/vexpress/vexpress_common.c
+++ b/board/armltd/vexpress/vexpress_common.c
@@ -109,7 +109,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size =
@@ -117,6 +117,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size =
 			get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+	return 0;
 }
 
 /*
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index e34af6c..0a22417 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -70,7 +70,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
@@ -78,6 +78,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 #endif
+
+	return 0;
 }
 
 /*
diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c
index 7ec7cb3..d011ae5 100644
--- a/board/astro/mcf5373l/mcf5373l.c
+++ b/board/astro/mcf5373l/mcf5373l.c
@@ -27,7 +27,7 @@ int checkboard(void)
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
 	sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
@@ -79,8 +79,10 @@ phys_size_t initdram(int board_type)
 	 * (Do not rely on the SDCS register(s) being set to 0x00000000
 	 * during reset as stated in the data sheet.)
 	 */
-	return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				0x80000000 - CONFIG_SYS_SDRAM_BASE);
+
+	return 0;
 }
 
 #define UART_BASE MMAP_UART0
diff --git a/board/bct-brettl2/Kconfig b/board/bct-brettl2/Kconfig
deleted file mode 100644
index 9c5407e..0000000
--- a/board/bct-brettl2/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BCT_BRETTL2
-
-config SYS_BOARD
-	default "bct-brettl2"
-
-config SYS_CONFIG_NAME
-	default "bct-brettl2"
-
-endif
diff --git a/board/bct-brettl2/MAINTAINERS b/board/bct-brettl2/MAINTAINERS
deleted file mode 100644
index 32245d4..0000000
--- a/board/bct-brettl2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BCT-BRETTL2 BOARD
-M:	Peter Meerwald <devel@bct-electronic.com>
-S:	Maintained
-F:	board/bct-brettl2/
-F:	include/configs/bct-brettl2.h
-F:	configs/bct-brettl2_defconfig
diff --git a/board/bct-brettl2/Makefile b/board/bct-brettl2/Makefile
deleted file mode 100644
index 28fccc0..0000000
--- a/board/bct-brettl2/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bct-brettl2.o gpio_cfi_flash.o cled.o
-obj-$(CONFIG_BFIN_MAC) += smsc9303.o
diff --git a/board/bct-brettl2/bct-brettl2.c b/board/bct-brettl2/bct-brettl2.c
deleted file mode 100644
index adb8605..0000000
--- a/board/bct-brettl2/bct-brettl2.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * U-Boot - main board file for BCT brettl2
- *
- * Copyright (c) 2010 BCT Electronic GmbH
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-#include <asm/gpio.h>
-#include <net.h>
-#include <netdev.h>
-#include <miiphy.h>
-
-#include "../cm-bf537e/gpio_cfi_flash.h"
-#include "smsc9303.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: bct-brettl2 board\n");
-	printf("       Support: http://www.bct-electronic.com/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
-	int retry = 3;
-	int ret;
-
-	ret = bfin_EMAC_initialize(bis);
-
-	uchar enetaddr[6];
-	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
-		printf("setting MAC %pM\n", enetaddr);
-	}
-	puts("       ");
-
-	puts("initialize SMSC LAN9303i ethernet switch\n");
-
-	while (retry-- > 0) {
-		if (init_smsc9303i_mii())
-			return ret;
-	}
-
-	return ret;
-}
-#endif
-
-static void init_tlv320aic31(void)
-{
-	puts("Audio: setup TIMER0 to enable 16.384 MHz clock for tlv320aic31\n");
-	peripheral_request(P_TMR0, "tlv320aic31 clock");
-	bfin_write_TIMER0_CONFIG(0x020d);
-	bfin_write_TIMER0_PERIOD(0x0008);
-	bfin_write_TIMER0_WIDTH(0x0008/2);
-	bfin_write_TIMER_ENABLE(bfin_read_TIMER_ENABLE() | 1);
-	SSYNC();
-	udelay(10000);
-
-	puts("       resetting tlv320aic31\n");
-
-	gpio_request(GPIO_PF2, "tlv320aic31");
-	gpio_direction_output(GPIO_PF2, 0);
-	udelay(10000);
-	gpio_direction_output(GPIO_PF2, 1);
-	udelay(10000);
-	gpio_free(GPIO_PF2);
-}
-
-static void init_mute_pin(void)
-{
-	printf("       unmute class D amplifier\n");
-
-	gpio_request(GPIO_PF5, "mute");
-	gpio_direction_output(GPIO_PF5, 1);
-	gpio_free(GPIO_PF5);
-}
-
-/* sometimes LEDs (speech, status) are still on after reboot, turn 'em off */
-static void turn_leds_off(void)
-{
-	printf("       turn LEDs off\n");
-
-	gpio_request(GPIO_PF6, "led");
-	gpio_direction_output(GPIO_PF6, 0);
-	gpio_free(GPIO_PF6);
-
-	gpio_request(GPIO_PF15, "led");
-	gpio_direction_output(GPIO_PF15, 0);
-	gpio_free(GPIO_PF15);
-}
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-	gpio_cfi_flash_init();
-	init_tlv320aic31();
-	init_mute_pin();
-	turn_leds_off();
-
-	return 0;
-}
diff --git a/board/bct-brettl2/cled.c b/board/bct-brettl2/cled.c
deleted file mode 100644
index dcb91bd..0000000
--- a/board/bct-brettl2/cled.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * cled.c - control color led
- *
- * Copyright (c) 2010 BCT Electronic GmbH
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include <asm/io.h>
-
-int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong addr = 0x20000000 + 0x200000; /* AMS2 */
-	uchar data;
-
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	data = simple_strtoul(argv[1], NULL, 10);
-	outb(data, addr);
-
-	printf("cled, write %02x\n", data);
-
-	return 0;
-}
-
-U_BOOT_CMD(cled, 2, 0, do_cled,
-	"set/clear color LED",
-	"");
diff --git a/board/bct-brettl2/gpio_cfi_flash.c b/board/bct-brettl2/gpio_cfi_flash.c
deleted file mode 100644
index b385c7f..0000000
--- a/board/bct-brettl2/gpio_cfi_flash.c
+++ /dev/null
@@ -1,4 +0,0 @@
-#define GPIO_PIN_1 GPIO_PG5
-#define GPIO_PIN_2 GPIO_PG6
-#define GPIO_PIN_3 GPIO_PG7
-#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/bct-brettl2/smsc9303.c b/board/bct-brettl2/smsc9303.c
deleted file mode 100644
index 15eea7a..0000000
--- a/board/bct-brettl2/smsc9303.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * smsc9303.c - routines to initialize SMSC 9303 switch
- *
- * Copyright (c) 2010 BCT Electronic GmbH
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <miiphy.h>
-
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-
-static int smc9303i_write_mii(unsigned char addr, unsigned char reg, unsigned short data)
-{
-	const char *devname = miiphy_get_current_dev();
-
-	if (!devname)
-	    return 0;
-
-	if (miiphy_write(devname, addr, reg, data) != 0)
-	    return 0;
-
-	return 1;
-}
-
-static int smc9303i_write_reg(unsigned short reg, unsigned int data)
-{
-	const char *devname = miiphy_get_current_dev();
-	unsigned char mii_addr = 0x10 | (reg >> 6);
-	unsigned char mii_reg = (reg & 0x3c) >> 1;
-
-	if (!devname)
-	    return 0;
-
-	if (miiphy_write(devname, mii_addr, mii_reg|0, data & 0xffff) != 0)
-	    return 0;
-
-	if (miiphy_write(devname, mii_addr, mii_reg|1, data >> 16) != 0)
-	    return 0;
-
-	return 1;
-}
-
-static int smc9303i_read_reg(unsigned short reg, unsigned int *data)
-{
-	const char *devname = miiphy_get_current_dev();
-	unsigned char mii_addr = 0x10 | (reg >> 6);
-	unsigned char mii_reg = (reg & 0x3c) >> 1;
-	unsigned short tmp1, tmp2;
-
-	if (!devname)
-	    return 0;
-
-	if (miiphy_read(devname, mii_addr, mii_reg|0, &tmp1) != 0)
-	    return 0;
-
-	if (miiphy_read(devname, mii_addr, mii_reg|1, &tmp2) != 0)
-	    return 0;
-
-	*data = (tmp2 << 16) | tmp1;
-
-	return 1;
-}
-
-#if 0
-static int smc9303i_read_mii(unsigned char addr, unsigned char reg, unsigned short *data)
-{
-	const char *devname = miiphy_get_current_dev();
-
-	if (!devname)
-	    return 0;
-
-	if (miiphy_read(devname, addr, reg, data) != 0)
-	    return 0;
-
-	return 1;
-}
-#endif
-
-typedef struct {
-	unsigned short reg;
-	unsigned int value;
-} smsc9303i_config_entry1_t;
-
-static const smsc9303i_config_entry1_t smsc9303i_config_table1[] =
-{
-	{0x1a0, 0x00000006}, /* Port 1 Manual Flow Control Register */
-	{0x1a4, 0x00000006}, /* Port 2 Manual Flow Control Register */
-	{0x1a8, 0x00000006}, /* Port 0 Manual Flow Control Register */
-};
-
-typedef struct
-{
-	unsigned char addr;
-	unsigned char reg;
-	unsigned short value;
-} smsc9303i_config_entry2_t;
-
-static const smsc9303i_config_entry2_t smsc9303i_config_table2[] =
-{
-	{0x01, 0x00, 0x0100}, /* Port0 PHY Basic Control Register */
-	{0x02, 0x00, 0x1100}, /* Port1 PHY Basic Control Register */
-	{0x03, 0x00, 0x1100}, /* Port2 PHY Basic Control Register */
-
-	{0x01, 0x04, 0x0001}, /* Port0 PHY Auto-Negotiation Advertisement Register */
-	{0x02, 0x04, 0x2de1}, /* Port1 PHY Auto-Negotiation Advertisement Register */
-	{0x03, 0x04, 0x2de1}, /* Port2 PHY Auto-Negotiation Advertisement Register */
-
-	{0x01, 0x11, 0x0000}, /* Port0 PHY Mode Control/Status Register */
-	{0x02, 0x11, 0x0000}, /* Port1 PHY Mode Control/Status Register */
-	{0x03, 0x11, 0x0000}, /* Port2 PHY Mode Control/Status Register */
-
-	{0x01, 0x12, 0x0021}, /* Port0 PHY Special Modes Register */
-	{0x02, 0x12, 0x00e2}, /* Port1 PHY Special Modes Register */
-	{0x03, 0x12, 0x00e3}, /* Port2 PHY Special Modes Register */
-	{0x01, 0x1b, 0x0000}, /* Port0 PHY Special Control/Status Indication Register */
-	{0x02, 0x1b, 0x0000}, /* Port1 PHY Special Control/Status Indication Register */
-	{0x03, 0x1b, 0x0000}, /* Port2 PHY Special Control/Status Indication Register */
-	{0x01, 0x1e, 0x0000}, /* Port0 PHY Interrupt Source Flags Register */
-	{0x02, 0x1e, 0x0000}, /* Port1 PHY Interrupt Source Flags Register */
-	{0x03, 0x1e, 0x0000}, /* Port2 PHY Interrupt Source Flags Register */
-};
-
-int init_smsc9303i_mii(void)
-{
-	unsigned int data;
-	unsigned int i;
-
-	printf("       reset SMSC LAN9303i\n");
-
-	gpio_request(GPIO_PG10, "smsc9303");
-	gpio_direction_output(GPIO_PG10, 0);
-	udelay(10000);
-	gpio_direction_output(GPIO_PG10, 1);
-	udelay(10000);
-
-	gpio_free(GPIO_PG10);
-
-#if defined(CONFIG_MII_INIT)
-	mii_init();
-#endif
-
-	printf("       write SMSC LAN9303i configuration\n");
-
-	if (!smc9303i_read_reg(0x50, &data))
-		return 0;
-
-	if ((data >> 16) != 0x9303)	{
-		/* chip id not found */
-		printf("       error identifying SMSC LAN9303i\n");
-		return 0;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table1); i++) {
-		const smsc9303i_config_entry1_t *entry = &smsc9303i_config_table1[i];
-
-		if (!smc9303i_write_reg(entry->reg, entry->value)) {
-			printf("       error writing SMSC LAN9303i configuration\n");
-			return 0;
-		}
-	}
-
-	for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table2); i++) {
-		const smsc9303i_config_entry2_t *entry = &smsc9303i_config_table2[i];
-
-		if (!smc9303i_write_mii(entry->addr, entry->reg, entry->value)) {
-			printf("       error writing SMSC LAN9303i configuration\n");
-			return 0;
-		}
-	}
-
-	return 1;
-}
diff --git a/board/bct-brettl2/smsc9303.h b/board/bct-brettl2/smsc9303.h
deleted file mode 100644
index a4ba40e..0000000
--- a/board/bct-brettl2/smsc9303.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * smsc9303.h - routines to initialize SMSC 9303 switch
- *
- * Copyright (c) 2010 BCT Electronic GmbH
- *
- * Licensed under the GPL-2 or later.
- */
-
-int init_smsc9303i_mii(void);
diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c
index 9b3ac22..c5d55dc 100644
--- a/board/beckhoff/mx53cx9020/mx53cx9020.c
+++ b/board/beckhoff/mx53cx9020/mx53cx9020.c
@@ -86,13 +86,15 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = mx53_dram_size[0];
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+	return 0;
 }
 
 u32 get_board_rev(void)
diff --git a/board/bf506f-ezkit/Kconfig b/board/bf506f-ezkit/Kconfig
deleted file mode 100644
index e6fc12c..0000000
--- a/board/bf506f-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF506F_EZKIT
-
-config SYS_BOARD
-	default "bf506f-ezkit"
-
-config SYS_CONFIG_NAME
-	default "bf506f-ezkit"
-
-endif
diff --git a/board/bf506f-ezkit/MAINTAINERS b/board/bf506f-ezkit/MAINTAINERS
deleted file mode 100644
index aaf1b7e..0000000
--- a/board/bf506f-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF506F-EZKIT BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf506f-ezkit/
-F:	include/configs/bf506f-ezkit.h
-F:	configs/bf506f-ezkit_defconfig
diff --git a/board/bf506f-ezkit/Makefile b/board/bf506f-ezkit/Makefile
deleted file mode 100644
index 7efe1bc..0000000
--- a/board/bf506f-ezkit/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf506f-ezkit.o
diff --git a/board/bf506f-ezkit/bf506f-ezkit.c b/board/bf506f-ezkit/bf506f-ezkit.c
deleted file mode 100644
index 77e40ae..0000000
--- a/board/bf506f-ezkit/bf506f-ezkit.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-
-int checkboard(void)
-{
-	printf("Board: ADI BF506F EZ-Kit board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	bfin_write_EBIU_MODE(1);
-	SSYNC();
-	bfin_write_FLASH_CONTROL_CLEAR(1);
-	udelay(1);
-	bfin_write_FLASH_CONTROL_SET(1);
-	return 0;
-}
diff --git a/board/bf518f-ezbrd/Kconfig b/board/bf518f-ezbrd/Kconfig
deleted file mode 100644
index a0e80a8..0000000
--- a/board/bf518f-ezbrd/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF518F_EZBRD
-
-config SYS_BOARD
-	default "bf518f-ezbrd"
-
-config SYS_CONFIG_NAME
-	default "bf518f-ezbrd"
-
-endif
diff --git a/board/bf518f-ezbrd/MAINTAINERS b/board/bf518f-ezbrd/MAINTAINERS
deleted file mode 100644
index 6727ae4..0000000
--- a/board/bf518f-ezbrd/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF518F-EZBRD BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf518f-ezbrd/
-F:	include/configs/bf518f-ezbrd.h
-F:	configs/bf518f-ezbrd_defconfig
diff --git a/board/bf518f-ezbrd/Makefile b/board/bf518f-ezbrd/Makefile
deleted file mode 100644
index e9e23ed..0000000
--- a/board/bf518f-ezbrd/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf518f-ezbrd.o
diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c
deleted file mode 100644
index 30d5285..0000000
--- a/board/bf518f-ezbrd/bf518f-ezbrd.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <spi.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/otp.h>
-#include <asm/sdh.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF518F EZ-Board board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#if defined(CONFIG_BFIN_MAC)
-static void board_init_enetaddr(uchar *mac_addr)
-{
-#ifdef CONFIG_MTD_NOR_FLASH
-	/* we cram the MAC in the last flash sector */
-	uchar *board_mac_addr = (uchar *)0x203F0096;
-	if (is_valid_ethaddr(board_mac_addr)) {
-		memcpy(mac_addr, board_mac_addr, 6);
-		eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-#endif
-}
-
-/* Only the first run of boards had a KSZ switch */
-#if defined(CONFIG_BFIN_SPI) && __SILICON_REVISION__ == 0
-# define KSZ_POSSIBLE 1
-#else
-# define KSZ_POSSIBLE 0
-#endif
-
-#define KSZ_MAX_HZ    5000000
-
-#define KSZ_WRITE     0x02
-#define KSZ_READ      0x03
-
-#define KSZ_REG_CHID  0x00	/* Register 0: Chip ID0 */
-#define KSZ_REG_STPID 0x01	/* Register 1: Chip ID1 / Start Switch */
-#define KSZ_REG_GC9   0x0b	/* Register 11: Global Control 9 */
-#define KSZ_REG_P3C0  0x30	/* Register 48: Port 3 Control 0 */
-
-static int ksz8893m_transfer(struct spi_slave *slave, uchar dir, uchar reg,
-			     uchar data, uchar result[3])
-{
-	unsigned char dout[3] = { dir, reg, data, };
-	return spi_xfer(slave, sizeof(dout) * 8, dout, result, SPI_XFER_BEGIN | SPI_XFER_END);
-}
-
-static int ksz8893m_reg_set(struct spi_slave *slave, uchar reg, uchar data)
-{
-	unsigned char din[3];
-	return ksz8893m_transfer(slave, KSZ_WRITE, reg, data, din);
-}
-
-static int ksz8893m_reg_read(struct spi_slave *slave, uchar reg)
-{
-	int ret;
-	unsigned char din[3];
-	ret = ksz8893m_transfer(slave, KSZ_READ, reg, 0, din);
-	return ret ? ret : din[2];
-}
-
-static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask)
-{
-	return ksz8893m_reg_set(slave, reg, ksz8893m_reg_read(slave, reg) & mask);
-}
-
-static int ksz8893m_reset(struct spi_slave *slave)
-{
-	int ret = 0;
-
-	/* Disable STPID mode */
-	ret |= ksz8893m_reg_clear(slave, KSZ_REG_GC9, 0x01);
-
-	/* Disable VLAN tag insert on Port3 */
-	ret |= ksz8893m_reg_clear(slave, KSZ_REG_P3C0, 0x04);
-
-	/* Start switch */
-	ret |= ksz8893m_reg_set(slave, KSZ_REG_STPID, 0x01);
-
-	return ret;
-}
-
-static bool board_ksz_init(void)
-{
-	static bool switch_is_alive = false;
-
-	if (!switch_is_alive) {
-		struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, SPI_MODE_3);
-		if (slave) {
-			if (!spi_claim_bus(slave)) {
-				bool phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88);
-				int ret = phy_is_ksz ? ksz8893m_reset(slave) : 0;
-				switch_is_alive = (ret == 0);
-				spi_release_bus(slave);
-			}
-			spi_free_slave(slave);
-		}
-	}
-
-	return switch_is_alive;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	if (KSZ_POSSIBLE) {
-		if (!board_ksz_init())
-			return 0;
-	}
-	return bfin_EMAC_initialize(bis);
-}
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
-
-#ifdef CONFIG_MTD_NOR_FLASH
-	/* we use the last sector for the MAC address / POST LDR */
-	extern flash_info_t flash_info[];
-	flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
-#endif
-
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	/* connect async banks by default */
-	const unsigned short pins[] = {
-		P_AMS2, P_AMS3, 0,
-	};
-	return peripheral_request_list(pins, "async");
-}
-
-#ifdef CONFIG_BFIN_SDH
-int board_mmc_init(bd_t *bis)
-{
-	return bfin_mmc_init(bis);
-}
-#endif
diff --git a/board/bf525-ucr2/Kconfig b/board/bf525-ucr2/Kconfig
deleted file mode 100644
index cd52daa..0000000
--- a/board/bf525-ucr2/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF525_UCR2
-
-config SYS_BOARD
-	default "bf525-ucr2"
-
-config SYS_CONFIG_NAME
-	default "bf525-ucr2"
-
-endif
diff --git a/board/bf525-ucr2/MAINTAINERS b/board/bf525-ucr2/MAINTAINERS
deleted file mode 100644
index f2e9575..0000000
--- a/board/bf525-ucr2/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-BF525-UCR2 BOARD
-M:	Haitao Zhang <hzhang@ucrobotics.com>
-M:	Chong Huang <chuang@ucrobotics.com>
-S:	Maintained
-F:	board/bf525-ucr2/
-F:	include/configs/bf525-ucr2.h
-F:	configs/bf525-ucr2_defconfig
diff --git a/board/bf525-ucr2/Makefile b/board/bf525-ucr2/Makefile
deleted file mode 100644
index 1be1d31..0000000
--- a/board/bf525-ucr2/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf525-ucr2.o
diff --git a/board/bf525-ucr2/bf525-ucr2.c b/board/bf525-ucr2/bf525-ucr2.c
deleted file mode 100644
index 36a725c..0000000
--- a/board/bf525-ucr2/bf525-ucr2.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* U-Boot - bf525-ucr2.c  board specific routines
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-
-int checkboard(void)
-{
-	printf("Board: bf525-ucr2\n");
-	printf("Support: http://www.ucrobotics.com/\n");
-	return 0;
-}
diff --git a/board/bf526-ezbrd/Kconfig b/board/bf526-ezbrd/Kconfig
deleted file mode 100644
index e138ea5..0000000
--- a/board/bf526-ezbrd/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF526_EZBRD
-
-config SYS_BOARD
-	default "bf526-ezbrd"
-
-config SYS_CONFIG_NAME
-	default "bf526-ezbrd"
-
-endif
diff --git a/board/bf526-ezbrd/MAINTAINERS b/board/bf526-ezbrd/MAINTAINERS
deleted file mode 100644
index f7c2d18..0000000
--- a/board/bf526-ezbrd/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF526-EZBRD BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf526-ezbrd/
-F:	include/configs/bf526-ezbrd.h
-F:	configs/bf526-ezbrd_defconfig
diff --git a/board/bf526-ezbrd/Makefile b/board/bf526-ezbrd/Makefile
deleted file mode 100644
index c4882c9..0000000
--- a/board/bf526-ezbrd/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf526-ezbrd.o
diff --git a/board/bf526-ezbrd/bf526-ezbrd.c b/board/bf526-ezbrd/bf526-ezbrd.c
deleted file mode 100644
index ae75520..0000000
--- a/board/bf526-ezbrd/bf526-ezbrd.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/otp.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF526 EZ-Board board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
-#ifdef CONFIG_MTD_NOR_FLASH
-	/* we cram the MAC in the last flash sector */
-	uchar *board_mac_addr = (uchar *)0x203F0096;
-	if (is_valid_ethaddr(board_mac_addr)) {
-		memcpy(mac_addr, board_mac_addr, 6);
-		eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-#endif
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
-
-#ifdef CONFIG_MTD_NOR_FLASH
-	/* we use the last sector for the MAC address / POST LDR */
-	extern flash_info_t flash_info[];
-	flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
-#endif
-
-	return 0;
-}
diff --git a/board/bf527-ad7160-eval/Kconfig b/board/bf527-ad7160-eval/Kconfig
deleted file mode 100644
index fe56241..0000000
--- a/board/bf527-ad7160-eval/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF527_AD7160_EVAL
-
-config SYS_BOARD
-	default "bf527-ad7160-eval"
-
-config SYS_CONFIG_NAME
-	default "bf527-ad7160-eval"
-
-endif
diff --git a/board/bf527-ad7160-eval/MAINTAINERS b/board/bf527-ad7160-eval/MAINTAINERS
deleted file mode 100644
index e93de1a..0000000
--- a/board/bf527-ad7160-eval/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF527-AD7160-EVAL BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf527-ad7160-eval/
-F:	include/configs/bf527-ad7160-eval.h
-F:	configs/bf527-ad7160-eval_defconfig
diff --git a/board/bf527-ad7160-eval/Makefile b/board/bf527-ad7160-eval/Makefile
deleted file mode 100644
index c225f72..0000000
--- a/board/bf527-ad7160-eval/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf527-ad7160-eval.o
diff --git a/board/bf527-ad7160-eval/bf527-ad7160-eval.c b/board/bf527-ad7160-eval/bf527-ad7160-eval.c
deleted file mode 100644
index 9180630..0000000
--- a/board/bf527-ad7160-eval/bf527-ad7160-eval.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/pll.h>
-
-int checkboard(void)
-{
-	printf("Board: ADI BF527 AD7160-EVAL board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	/* CLKIN Buffer Output Enable */
-	bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
-	return 0;
-}
diff --git a/board/bf527-ezkit/Kconfig b/board/bf527-ezkit/Kconfig
deleted file mode 100644
index df49d7a..0000000
--- a/board/bf527-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF527_EZKIT
-
-config SYS_BOARD
-	default "bf527-ezkit"
-
-config SYS_CONFIG_NAME
-	default "bf527-ezkit"
-
-endif
diff --git a/board/bf527-ezkit/MAINTAINERS b/board/bf527-ezkit/MAINTAINERS
deleted file mode 100644
index 7a95396..0000000
--- a/board/bf527-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-BF527-EZKIT BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf527-ezkit/
-F:	include/configs/bf527-ezkit.h
-F:	configs/bf527-ezkit_defconfig
-F:	configs/bf527-ezkit-v2_defconfig
diff --git a/board/bf527-ezkit/Makefile b/board/bf527-ezkit/Makefile
deleted file mode 100644
index 53ec9e7..0000000
--- a/board/bf527-ezkit/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf527-ezkit.o
-obj-$(CONFIG_VIDEO)      += video.o
diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c
deleted file mode 100644
index c4f58fa..0000000
--- a/board/bf527-ezkit/bf527-ezkit.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/mach-common/bits/otp.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF527 EZ-Kit board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
-	/* the MAC is stored in OTP memory page 0xDF */
-	uint32_t ret;
-	uint64_t otp_mac;
-
-	ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
-	if (!(ret & OTP_MASTER_ERROR)) {
-		uchar *otp_mac_p = (uchar *)&otp_mac;
-
-		for (ret = 0; ret < 6; ++ret)
-			mac_addr[ret] = otp_mac_p[5 - ret];
-
-		if (is_valid_ethaddr(mac_addr))
-			eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
-
-	return 0;
-}
-
-#ifdef CONFIG_USB_BLACKFIN
-void board_musb_init(void)
-{
-	/*
-	 * BF527 EZ-KITs require PG13 to be high for HOST mode
-	 */
-	gpio_request(GPIO_PG13, "musb-vbus");
-	gpio_direction_output(GPIO_PG13, 1);
-}
-#endif
diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c
deleted file mode 100644
index a57f9fe..0000000
--- a/board/bf527-ezkit/video.c
+++ /dev/null
@@ -1,445 +0,0 @@
-/*
- * video.c - run splash screen on lcd
- *
- * Copyright (c) 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/dma.h>
-#include <spi.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-
-#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDec.h>
-#include <lzma/LzmaTools.h>
-
-#include <asm/mach-common/bits/ppi.h>
-#include <asm/mach-common/bits/timer.h>
-
-#define LCD_X_RES		320	/* Horizontal Resolution */
-#define LCD_Y_RES		240	/* Vertical Resolution */
-#define DMA_BUS_SIZE		16
-
-#include EASYLOGO_HEADER
-
-#ifdef CONFIG_BF527_EZKIT_REV_2_1 /* lq035q1 */
-
-/* Interface 16/18-bit TFT over an 8-bit wide PPI using a
- * small Programmable Logic Device (CPLD)
- * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
- */
-
-#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
-#define LCD_BPP		16	/* Bit Per Pixel */
-#define CLOCKS_PPIX	2	/* Clocks per pixel */
-#define CPLD_DELAY	3	/* RGB565 pipeline delay */
-#endif
-
-#ifdef CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
-#define LCD_BPP		24	/* Bit Per Pixel */
-#define CLOCKS_PPIX	3	/* Clocks per pixel */
-#define CPLD_DELAY	5	/* RGB888 pipeline delay */
-#endif
-
-/*
- * HS and VS timing parameters (all in number of PPI clk ticks)
- */
-
-#define H_ACTPIX	(LCD_X_RES * CLOCKS_PPIX)	/* active horizontal pixel */
-#define H_PERIOD	(336 * CLOCKS_PPIX)		/* HS period */
-#define H_PULSE		(2 * CLOCKS_PPIX)		/* HS pulse width */
-#define H_START		(7 * CLOCKS_PPIX + CPLD_DELAY)	/* first valid pixel */
-
-#define U_LINE		4				/* Blanking Lines */
-
-#define V_LINES		(LCD_Y_RES + U_LINE)		/* total vertical lines */
-#define V_PULSE		(2 * CLOCKS_PPIX)		/* VS pulse width (1-5 H_PERIODs) */
-#define V_PERIOD	(H_PERIOD * V_LINES)		/* VS period */
-
-#define ACTIVE_VIDEO_MEM_OFFSET	((U_LINE / 2) * LCD_X_RES * (LCD_BPP / 8))
-
-/*
- * LCD Modes
- */
-#define LQ035_RL	(0 << 8)	/* Right -> Left Scan */
-#define LQ035_LR	(1 << 8)	/* Left -> Right Scan */
-#define LQ035_TB	(1 << 9)	/* Top -> Botton Scan */
-#define LQ035_BT	(0 << 9)	/* Botton -> Top Scan */
-#define LQ035_BGR	(1 << 11)	/* Use BGR format */
-#define LQ035_RGB	(0 << 11)	/* Use RGB format */
-#define LQ035_NORM	(1 << 13)	/* Reversal */
-#define LQ035_REV	(0 << 13)	/* Reversal */
-
-#define LQ035_INDEX			0x74
-#define LQ035_DATA			0x76
-
-#define LQ035_DRIVER_OUTPUT_CTL		0x1
-#define LQ035_SHUT_CTL			0x11
-
-#define LQ035_DRIVER_OUTPUT_MASK	(LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV)
-#define LQ035_DRIVER_OUTPUT_DEFAULT	(0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)
-
-#define LQ035_SHUT			(1 << 0)	/* Shutdown */
-#define LQ035_ON			(0 << 0)	/* Shutdown */
-
-#ifndef CONFIG_LQ035Q1_LCD_MODE
-#define CONFIG_LQ035Q1_LCD_MODE		(LQ035_NORM | LQ035_RL | LQ035_TB | LQ035_BGR)
-#endif
-
-#else /* t350mcqb */
-
-#define LCD_BPP		24	/* Bit Per Pixel */
-#define CLOCKS_PPIX	3	/* Clocks per pixel */
-
-/* HS and VS timing parameters (all in number of PPI clk ticks) */
-#define H_ACTPIX	(LCD_X_RES * CLOCKS_PPIX)	/* active horizontal pixel */
-#define H_PERIOD	(408 * CLOCKS_PPIX)		/* HS period */
-#define H_PULSE		90				/* HS pulse width */
-#define H_START		204				/* first valid pixel */
-
-#define U_LINE		1				/* Blanking Lines */
-
-#define V_LINES		(LCD_Y_RES + U_LINE)		/* total vertical lines */
-#define V_PULSE		(3 * H_PERIOD)			/* VS pulse width (1-5 H_PERIODs) */
-#define V_PERIOD	(H_PERIOD * V_LINES)		/* VS period */
-
-#define ACTIVE_VIDEO_MEM_OFFSET	(U_LINE * H_ACTPIX)
-#endif
-
-#define LCD_PIXEL_SIZE		(LCD_BPP / 8)
-#define DMA_SIZE16		2
-
-#define PPI_TX_MODE		0x2
-#define PPI_XFER_TYPE_11	0xC
-#define PPI_PORT_CFG_01		0x10
-#define PPI_PACK_EN		0x80
-#define PPI_POLS_1		0x8000
-
-#ifdef CONFIG_BF527_EZKIT_REV_2_1
-static struct spi_slave *slave;
-static int lq035q1_control(unsigned char reg, unsigned short value)
-{
-	int ret;
-	u8 regs[3] = {LQ035_INDEX, 0, 0};
-	u8 data[3] = {LQ035_DATA, 0, 0};
-	u8 dummy[3];
-
-	regs[2] = reg;
-	data[1] = value >> 8;
-	data[2] = value & 0xFF;
-
-	if (!slave) {
-		/* FIXME: Verify the max SCK rate */
-		slave = spi_setup_slave(CONFIG_LQ035Q1_SPI_BUS,
-				CONFIG_LQ035Q1_SPI_CS, 20000000,
-				SPI_MODE_3);
-		if (!slave)
-			return -1;
-	}
-
-	if (spi_claim_bus(slave))
-		return -1;
-
-	ret = spi_xfer(slave, 24, regs, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
-	ret |= spi_xfer(slave, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
-
-	spi_release_bus(slave);
-
-	return ret;
-}
-#endif
-
-/* enable and disable PPI functions */
-void EnablePPI(void)
-{
-	bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
-}
-
-void DisablePPI(void)
-{
-	bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
-}
-
-void Init_Ports(void)
-{
-	const unsigned short pins[] = {
-		P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
-		P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_FS2, 0,
-	};
-	peripheral_request_list(pins, "lcd");
-}
-
-void Init_PPI(void)
-{
-
-	bfin_write_PPI_DELAY(H_START);
-	bfin_write_PPI_COUNT(H_ACTPIX - 1);
-	bfin_write_PPI_FRAME(V_LINES);
-
-	/* PPI control, to be replaced with definitions */
-	bfin_write_PPI_CONTROL(
-			PPI_TX_MODE		|	/* output mode , PORT_DIR */
-			PPI_XFER_TYPE_11	|	/* sync mode XFR_TYPE */
-			PPI_PORT_CFG_01		|	/* two frame sync PORT_CFG */
-			PPI_PACK_EN		|	/* packing enabled PACK_EN */
-			PPI_POLS_1			/* faling edge syncs POLS */
-	);
-}
-
-void Init_DMA(void *dst)
-{
-	bfin_write_DMA0_START_ADDR(dst);
-
-	/* X count */
-	bfin_write_DMA0_X_COUNT(H_ACTPIX / 2);
-	bfin_write_DMA0_X_MODIFY(DMA_BUS_SIZE / 8);
-
-	/* Y count */
-	bfin_write_DMA0_Y_COUNT(V_LINES);
-	bfin_write_DMA0_Y_MODIFY(DMA_BUS_SIZE / 8);
-
-	/* DMA Config */
-	bfin_write_DMA0_CONFIG(
-		WDSIZE_16	|	/* 16 bit DMA */
-		DMA2D 		|	/* 2D DMA */
-		FLOW_AUTO		/* autobuffer mode */
-	);
-}
-
-void EnableDMA(void)
-{
-	bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() | DMAEN);
-}
-
-void DisableDMA(void)
-{
-	bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN);
-}
-
-/* Init TIMER0 as Frame Sync 1 generator */
-void InitTIMER0(void)
-{
-	bfin_write_TIMER_DISABLE(TIMDIS0);			/* disable Timer */
-	SSYNC();
-	bfin_write_TIMER_STATUS(TIMIL0 | TOVF_ERR0 | TRUN0);	/* clear status */
-	SSYNC();
-
-	bfin_write_TIMER0_PERIOD(H_PERIOD);
-	SSYNC();
-	bfin_write_TIMER0_WIDTH(H_PULSE);
-	SSYNC();
-
-	bfin_write_TIMER0_CONFIG(
-				PWM_OUT |
-				PERIOD_CNT   |
-				TIN_SEL      |
-				CLK_SEL      |
-				EMU_RUN
-	);
-	SSYNC();
-}
-
-void EnableTIMER0(void)
-{
-	bfin_write_TIMER_ENABLE(TIMEN0);
-	SSYNC();
-}
-
-void DisableTIMER0(void)
-{
-	bfin_write_TIMER_DISABLE(TIMDIS0);
-	SSYNC();
-}
-
-
-void InitTIMER1(void)
-{
-	bfin_write_TIMER_DISABLE(TIMDIS1);			/* disable Timer */
-	SSYNC();
-	bfin_write_TIMER_STATUS(TIMIL1 | TOVF_ERR1 | TRUN1);	/* clear status */
-	SSYNC();
-
-	bfin_write_TIMER1_PERIOD(V_PERIOD);
-	SSYNC();
-	bfin_write_TIMER1_WIDTH(V_PULSE);
-	SSYNC();
-
-	bfin_write_TIMER1_CONFIG(
-				PWM_OUT |
-				PERIOD_CNT   |
-				TIN_SEL      |
-				CLK_SEL      |
-				EMU_RUN
-	);
-	SSYNC();
-}
-
-void EnableTIMER1(void)
-{
-	bfin_write_TIMER_ENABLE(TIMEN1);
-	SSYNC();
-}
-
-void DisableTIMER1(void)
-{
-	bfin_write_TIMER_DISABLE(TIMDIS1);
-	SSYNC();
-}
-
-void EnableTIMER12(void)
-{
-	bfin_write_TIMER_ENABLE(TIMEN1 | TIMEN0);
-	SSYNC();
-}
-
-int video_init(void *dst)
-{
-
-#ifdef CONFIG_BF527_EZKIT_REV_2_1
-	lq035q1_control(LQ035_SHUT_CTL, LQ035_ON);
-	lq035q1_control(LQ035_DRIVER_OUTPUT_CTL, (CONFIG_LQ035Q1_LCD_MODE &
-		LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT);
-#endif
-	Init_Ports();
-	Init_DMA(dst);
-	EnableDMA();
-	InitTIMER0();
-	InitTIMER1();
-	Init_PPI();
-	EnablePPI();
-
-#ifdef CONFIG_BF527_EZKIT_REV_2_1
-	EnableTIMER12();
-#else
-	/* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
-	EnableTIMER1();
-	/* Add Some Delay ... */
-	SSYNC();
-	SSYNC();
-	SSYNC();
-	SSYNC();
-
-	/* now start frame sync 1 */
-	EnableTIMER0();
-#endif
-
-	return 0;
-}
-
-static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
-{
-	if (dcache_status())
-		blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
-
-	bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-	/* Setup destination start address */
-	bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
-					+ (y * LCD_X_RES * LCD_PIXEL_SIZE));
-	/* Setup destination xcount */
-	bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
-	/* Setup destination xmodify */
-	bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
-
-	/* Setup destination ycount */
-	bfin_write_MDMA_D0_Y_COUNT(logo->height);
-	/* Setup destination ymodify */
-	bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
-
-
-	/* Setup Source start address */
-	bfin_write_MDMA_S0_START_ADDR(logo->data);
-	/* Setup Source xcount */
-	bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
-	/* Setup Source xmodify */
-	bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
-
-	/* Setup Source ycount */
-	bfin_write_MDMA_S0_Y_COUNT(logo->height);
-	/* Setup Source ymodify */
-	bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
-
-
-	/* Enable source DMA */
-	bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
-	SSYNC();
-	bfin_write_MDMA_D0_CONFIG(WNR | DMAEN  | WDSIZE_16 | DMA2D);
-
-	while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
-
-	bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
-	bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
-
-}
-
-void video_stop(void)
-{
-	DisablePPI();
-	DisableDMA();
-	DisableTIMER0();
-	DisableTIMER1();
-#ifdef CONFIG_BF527_EZKIT_REV_2_1
-	lq035q1_control(LQ035_SHUT_CTL, LQ035_SHUT);
-#endif
-}
-
-int drv_video_init(void)
-{
-	int error, devices = 1;
-	struct stdio_dev videodev;
-
-	u8 *dst;
-	u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
-
-	dst = malloc(fbmem_size);
-
-	if (dst == NULL) {
-		printf("Failed to alloc FB memory\n");
-		return -1;
-	}
-
-#ifdef EASYLOGO_ENABLE_GZIP
-	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
-	unsigned long src_len = EASYLOGO_ENABLE_GZIP;
-	error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
-	bfin_logo.data = data;
-#elif defined(EASYLOGO_ENABLE_LZMA)
-	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
-	SizeT lzma_len = bfin_logo.size;
-	error = lzmaBuffToBuffDecompress(data, &lzma_len,
-		bfin_logo.data, EASYLOGO_ENABLE_LZMA);
-	bfin_logo.data = data;
-#else
-	error = 0;
-#endif
-
-	if (error) {
-		puts("Failed to decompress logo\n");
-		free(dst);
-		return -1;
-	}
-
-	memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
-
-	dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
-			(LCD_X_RES - bfin_logo.width) / 2,
-			(LCD_Y_RES - bfin_logo.height) / 2);
-
-	video_init(dst);		/* Video initialization */
-
-	memset(&videodev, 0, sizeof(videodev));
-
-	strcpy(videodev.name, "video");
-
-	error = stdio_register(&videodev);
-
-	return (error == 0) ? devices : error;
-}
diff --git a/board/bf527-sdp/Kconfig b/board/bf527-sdp/Kconfig
deleted file mode 100644
index 928bd77..0000000
--- a/board/bf527-sdp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF527_SDP
-
-config SYS_BOARD
-	default "bf527-sdp"
-
-config SYS_CONFIG_NAME
-	default "bf527-sdp"
-
-endif
diff --git a/board/bf527-sdp/MAINTAINERS b/board/bf527-sdp/MAINTAINERS
deleted file mode 100644
index 32ccfc5..0000000
--- a/board/bf527-sdp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF527-SDP BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf527-sdp/
-F:	include/configs/bf527-sdp.h
-F:	configs/bf527-sdp_defconfig
diff --git a/board/bf527-sdp/Makefile b/board/bf527-sdp/Makefile
deleted file mode 100644
index 77acb42..0000000
--- a/board/bf527-sdp/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf527-sdp.o
diff --git a/board/bf527-sdp/bf527-sdp.c b/board/bf527-sdp/bf527-sdp.c
deleted file mode 100644
index 0c6094b..0000000
--- a/board/bf527-sdp/bf527-sdp.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/mach-common/bits/pll.h>
-
-int checkboard(void)
-{
-	printf("Board: ADI BF527 SDP board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-
-	/* Enable access to parallel flash */
-	gpio_request(GPIO_PG0, "parallel-flash");
-	gpio_direction_output(GPIO_PG0, 0);
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	/* CLKIN Buffer Output Enable */
-	bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
-
-	return 0;
-}
diff --git a/board/bf527-sdp/config.mk b/board/bf527-sdp/config.mk
deleted file mode 100644
index 1d46cfc..0000000
--- a/board/bf527-sdp/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6
diff --git a/board/bf533-ezkit/Kconfig b/board/bf533-ezkit/Kconfig
deleted file mode 100644
index 555ab29..0000000
--- a/board/bf533-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF533_EZKIT
-
-config SYS_BOARD
-	default "bf533-ezkit"
-
-config SYS_CONFIG_NAME
-	default "bf533-ezkit"
-
-endif
diff --git a/board/bf533-ezkit/MAINTAINERS b/board/bf533-ezkit/MAINTAINERS
deleted file mode 100644
index bfa7c3c..0000000
--- a/board/bf533-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF533-EZKIT BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf533-ezkit/
-F:	include/configs/bf533-ezkit.h
-F:	configs/bf533-ezkit_defconfig
diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile
deleted file mode 100644
index bf7a2c4..0000000
--- a/board/bf533-ezkit/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf533-ezkit.o flash.o
diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c
deleted file mode 100644
index 6879319..0000000
--- a/board/bf533-ezkit/bf533-ezkit.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include "psd4256.h"
-#include "flash-defines.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF533 EZ-Kit Lite board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-	/* Set direction bits for Video en/decoder reset as output      */
-	*(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DIR) =
-	    PSDA_VDEC_RST | PSDA_VENC_RST;
-	/* Deactivate Video en/decoder reset lines                      */
-	*(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DOUT) =
-	    PSDA_VDEC_RST | PSDA_VENC_RST;
-
-	return 0;
-}
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
-	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk
deleted file mode 100644
index 7f9138b..0000000
--- a/board/bf533-ezkit/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf533-ezkit/flash-defines.h b/board/bf533-ezkit/flash-defines.h
deleted file mode 100644
index 7822a9d..0000000
--- a/board/bf533-ezkit/flash-defines.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * U-Boot - flash-defines.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __FLASHDEFINES_H__
-#define __FLASHDEFINES_H__
-
-#include <common.h>
-
-#define V_ULONG(a)		(*(volatile unsigned long *)( a ))
-#define V_BYTE(a)		(*(volatile unsigned char *)( a ))
-#define BUFFER_SIZE		0x80000
-#define NO_COMMAND		0
-#define GET_CODES		1
-#define RESET			2
-#define WRITE			3
-#define FILL			4
-#define ERASE_ALL		5
-#define ERASE_SECT		6
-#define READ			7
-#define GET_SECTNUM		8
-#define FLASH_START_L		0x0000
-#define FLASH_START_H		0x2000
-#define FLASH_TOT_SECT		40
-#define FLASH_SIZE		0x220000
-#define FLASH_MAN_ST		2
-#define CONFIG_SYS_FLASH0_BASE		0x20000000
-#define CONFIG_SYS_FLASH1_BASE		0x20200000
-#define RESET_VAL		0xF0
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-int get_codes(void);
-int poll_toggle_bit(long lOffset);
-void reset_flash(void);
-int erase_flash(void);
-int erase_block_flash(int, unsigned long);
-void unlock_flash(long lOffset);
-int write_data(long lStart, long lCount, uchar *pnData);
-int FillData(long lStart, long lCount, long lStride, int *pnData);
-int read_data(long lStart, long lCount, long lStride, int *pnData);
-int read_flash(long nOffset, int *pnValue);
-int write_flash(long nOffset, int nValue);
-void get_sector_number(long lOffset, int *pnSector);
-int GetSectorProtectionStatus(flash_info_t * info, int nSector);
-int GetOffset(int nBlock);
-
-#define WRITESEQ1		0x0AAA
-#define WRITESEQ2		0x0554
-#define WRITESEQ3		0x0AAA
-#define WRITESEQ4		0x0AAA
-#define WRITESEQ5		0x0554
-#define WRITESEQ6		0x0AAA
-#define WRITEDATA1		0xaa
-#define WRITEDATA2		0x55
-#define WRITEDATA3		0x80
-#define WRITEDATA4		0xaa
-#define WRITEDATA5		0x55
-#define WRITEDATA6		0x10
-#define PriFlashABegin		0
-#define SecFlashABegin		32
-#define SecFlashBBegin		36
-#define PriFlashAOff		0x0
-#define PriFlashBOff		0x100000
-#define SecFlashAOff		0x200000
-#define SecFlashBOff		0x280000
-#define INVALIDLOCNSTART	0x20270000
-#define INVALIDLOCNEND		0x20280000
-#define BlockEraseVal		0x30
-#define UNLOCKDATA1		0xaa
-#define UNLOCKDATA2		0x55
-#define UNLOCKDATA3		0xa0
-#define GETCODEDATA1		0xaa
-#define GETCODEDATA2		0x55
-#define GETCODEDATA3		0x90
-#define SecFlashASec1Off	0x200000
-#define SecFlashASec2Off	0x204000
-#define SecFlashASec3Off	0x206000
-#define SecFlashASec4Off	0x208000
-#define SecFlashAEndOff		0x210000
-#define SecFlashBSec1Off	0x280000
-#define SecFlashBSec2Off	0x284000
-#define SecFlashBSec3Off	0x286000
-#define SecFlashBSec4Off	0x288000
-#define SecFlashBEndOff		0x290000
-
-#define SECT32			32
-#define SECT33			33
-#define SECT34			34
-#define SECT35			35
-#define SECT36			36
-#define SECT37			37
-#define SECT38			38
-#define SECT39			39
-
-#define FLASH_SUCCESS	0
-#define FLASH_FAIL	-1
-
-#endif
diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c
deleted file mode 100644
index a7b3519..0000000
--- a/board/bf533-ezkit/flash.c
+++ /dev/null
@@ -1,473 +0,0 @@
-/*
- * U-Boot - flash.c Flash driver for PSD4256GV
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/io.h>
-#include "flash-defines.h"
-
-int AFP_NumSectors = 40;
-long AFP_SectorSize1 = 0x10000;
-int AFP_SectorSize2 = 0x4000;
-
-void flash_reset(void)
-{
-	reset_flash();
-}
-
-unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
-{
-	int id = 0, i = 0;
-	static int FlagDev = 1;
-
-	id = get_codes();
-	if (FlagDev) {
-#ifdef DEBUG
-		printf("Device ID of the Flash is %x\n", id);
-#endif
-		FlagDev = 0;
-	}
-	info->flash_id = id;
-
-	switch (bank_flag) {
-	case 0:
-		for (i = PriFlashABegin; i < SecFlashABegin; i++)
-			info->start[i] = (baseaddr + (i * AFP_SectorSize1));
-		info->size = 0x200000;
-		info->sector_count = 32;
-		break;
-	case 1:
-		info->start[0] = baseaddr + SecFlashASec1Off;
-		info->start[1] = baseaddr + SecFlashASec2Off;
-		info->start[2] = baseaddr + SecFlashASec3Off;
-		info->start[3] = baseaddr + SecFlashASec4Off;
-		info->size = 0x10000;
-		info->sector_count = 4;
-		break;
-	case 2:
-		info->start[0] = baseaddr + SecFlashBSec1Off;
-		info->start[1] = baseaddr + SecFlashBSec2Off;
-		info->start[2] = baseaddr + SecFlashBSec3Off;
-		info->start[3] = baseaddr + SecFlashBSec4Off;
-		info->size = 0x10000;
-		info->sector_count = 4;
-		break;
-	}
-	return (info->size);
-}
-
-unsigned long flash_init(void)
-{
-	unsigned long size_b0, size_b1, size_b2;
-	int i;
-
-	size_b0 = size_b1 = size_b2 = 0;
-#ifdef DEBUG
-	printf("Flash Memory Start 0x%x\n", CONFIG_SYS_FLASH_BASE);
-	printf("Memory Map for the Flash\n");
-	printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n");
-	printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n");
-	printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n");
-	printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n");
-	printf("Please type command flinfo for information on Sectors \n");
-#endif
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	size_b0 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[0], 0);
-	size_b1 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[1], 1);
-	size_b2 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[2], 2);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
-		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-		       size_b0, size_b0 >> 20);
-	}
-
-	(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH0_BASE,
-			    (flash_info[0].start[2] - 1), &flash_info[0]);
-
-	return (size_b0 + size_b1 + size_b2);
-}
-
-void flash_print_info(flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id) {
-	case FLASH_PSD4256GV:
-		printf("ST Microelectronics ");
-		break;
-	default:
-		printf("Unknown Vendor: (0x%08lX) ", info->flash_id);
-		break;
-	}
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf("\n   ");
-		printf(" %08lX%s",
-		       info->start[i], info->protect[i] ? " (RO)" : "     ");
-	}
-	printf("\n");
-	return;
-}
-
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
-	int cnt = 0, i;
-	int prot, sect;
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot)
-		printf("- Warning: %d protected sectors will not be erased!\n",
-		       prot);
-	else
-		printf("\n");
-
-	cnt = s_last - s_first + 1;
-
-	if (cnt == FLASH_TOT_SECT) {
-		printf("Erasing flash, Please Wait \n");
-		if (erase_flash() < 0) {
-			printf("Erasing flash failed \n");
-			return FLASH_FAIL;
-		}
-	} else {
-		printf("Erasing Flash locations, Please Wait\n");
-		for (i = s_first; i <= s_last; i++) {
-			if (info->protect[i] == 0) {	/* not protected */
-				if (erase_block_flash(i, info->start[i]) < 0) {
-					printf("Error Sector erasing \n");
-					return FLASH_FAIL;
-				}
-			}
-		}
-	}
-	return FLASH_SUCCESS;
-}
-
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	int ret;
-	int d;
-	if (addr % 2) {
-		read_flash(addr - 1 - CONFIG_SYS_FLASH_BASE, &d);
-		d = (int)((d & 0x00FF) | (*src++ << 8));
-		ret = write_data(addr - 1, 2, (uchar *) & d);
-		if (ret == FLASH_FAIL)
-			return ERR_NOT_ERASED;
-		ret = write_data(addr + 1, cnt - 1, src);
-	} else
-		ret = write_data(addr, cnt, src);
-	if (ret == FLASH_FAIL)
-		return ERR_NOT_ERASED;
-	return FLASH_SUCCESS;
-}
-
-int write_data(long lStart, long lCount, uchar * pnData)
-{
-	long i = 0;
-	unsigned long ulOffset = lStart - CONFIG_SYS_FLASH_BASE;
-	int d;
-	int nSector = 0;
-	int flag = 0;
-
-	if (lCount % 2) {
-		flag = 1;
-		lCount = lCount - 1;
-	}
-
-	for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
-		get_sector_number(ulOffset, &nSector);
-		read_flash(ulOffset, &d);
-		if (d != 0xffff) {
-			printf
-			    ("Flash not erased at offset 0x%lx Please erase to reprogram\n",
-			     ulOffset);
-			return FLASH_FAIL;
-		}
-		unlock_flash(ulOffset);
-		d = (int)(pnData[i] | pnData[i + 1] << 8);
-		write_flash(ulOffset, d);
-		if (poll_toggle_bit(ulOffset) < 0) {
-			printf("Error programming the flash \n");
-			return FLASH_FAIL;
-		}
-		if ((i > 0) && (!(i % AFP_SectorSize2)))
-			printf(".");
-	}
-	if (flag) {
-		get_sector_number(ulOffset, &nSector);
-		read_flash(ulOffset, &d);
-		if (d != 0xffff) {
-			printf
-			    ("Flash not erased at offset 0x%lx Please erase to reprogram\n",
-			     ulOffset);
-			return FLASH_FAIL;
-		}
-		unlock_flash(ulOffset);
-		d = (int)(pnData[i] | (d & 0xFF00));
-		write_flash(ulOffset, d);
-		if (poll_toggle_bit(ulOffset) < 0) {
-			printf("Error programming the flash \n");
-			return FLASH_FAIL;
-		}
-	}
-	return FLASH_SUCCESS;
-}
-
-int read_data(long ulStart, long lCount, long lStride, int *pnData)
-{
-	long i = 0;
-	int j = 0;
-	long ulOffset = ulStart;
-	int iShift = 0;
-	int iNumWords = 2;
-	int nLeftover = lCount % 4;
-	int nHi, nLow;
-	int nSector = 0;
-
-	for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
-		for (iShift = 0, j = 0; j < iNumWords; j += 2) {
-			if ((ulOffset >= INVALIDLOCNSTART)
-			    && (ulOffset < INVALIDLOCNEND))
-				return FLASH_FAIL;
-
-			get_sector_number(ulOffset, &nSector);
-			read_flash(ulOffset, &nLow);
-			ulOffset += (lStride * 2);
-			read_flash(ulOffset, &nHi);
-			ulOffset += (lStride * 2);
-			pnData[i] = (nHi << 16) | nLow;
-		}
-	}
-	if (nLeftover > 0) {
-		if ((ulOffset >= INVALIDLOCNSTART)
-		    && (ulOffset < INVALIDLOCNEND))
-			return FLASH_FAIL;
-
-		get_sector_number(ulOffset, &nSector);
-		read_flash(ulOffset, &pnData[i]);
-	}
-	return FLASH_SUCCESS;
-}
-
-int write_flash(long nOffset, int nValue)
-{
-	long addr;
-
-	addr = (CONFIG_SYS_FLASH_BASE + nOffset);
-	SSYNC();
-	*(unsigned volatile short *)addr = nValue;
-	SSYNC();
-	if (poll_toggle_bit(nOffset) < 0)
-		return FLASH_FAIL;
-	return FLASH_SUCCESS;
-}
-
-int read_flash(long nOffset, int *pnValue)
-{
-	int nValue = 0x0;
-	long addr = (CONFIG_SYS_FLASH_BASE + nOffset);
-
-	if (nOffset != 0x2)
-		reset_flash();
-	SSYNC();
-	nValue = *(volatile unsigned short *)addr;
-	SSYNC();
-	*pnValue = nValue;
-	return true;
-}
-
-int poll_toggle_bit(long lOffset)
-{
-	unsigned int u1, u2;
-	unsigned long timeout = 0xFFFFFFFF;
-	volatile unsigned long *FB =
-	    (volatile unsigned long *)(0x20000000 + lOffset);
-	while (1) {
-		if (timeout < 0)
-			break;
-		u1 = *(volatile unsigned short *)FB;
-		u2 = *(volatile unsigned short *)FB;
-		if ((u1 & 0x0040) == (u2 & 0x0040))
-			return FLASH_SUCCESS;
-		if ((u2 & 0x0020) == 0x0000)
-			continue;
-		u1 = *(volatile unsigned short *)FB;
-		if ((u2 & 0x0040) == (u1 & 0x0040))
-			return FLASH_SUCCESS;
-		else {
-			reset_flash();
-			return FLASH_FAIL;
-		}
-		timeout--;
-	}
-	printf("Time out occurred \n");
-	if (timeout < 0)
-		return FLASH_FAIL;
-}
-
-void reset_flash(void)
-{
-	write_flash(WRITESEQ1, RESET_VAL);
-	/* Wait for 10 micro seconds */
-	udelay(10);
-}
-
-int erase_flash(void)
-{
-	write_flash(WRITESEQ1, WRITEDATA1);
-	write_flash(WRITESEQ2, WRITEDATA2);
-	write_flash(WRITESEQ3, WRITEDATA3);
-	write_flash(WRITESEQ4, WRITEDATA4);
-	write_flash(WRITESEQ5, WRITEDATA5);
-	write_flash(WRITESEQ6, WRITEDATA6);
-
-	if (poll_toggle_bit(0x0000) < 0)
-		return FLASH_FAIL;
-
-	write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1);
-	write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2);
-	write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3);
-	write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4);
-	write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5);
-	write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6);
-
-	if (poll_toggle_bit(SecFlashASec1Off) < 0)
-		return FLASH_FAIL;
-
-	write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1);
-	write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2);
-	write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3);
-	write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4);
-	write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5);
-	write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6);
-
-	if (poll_toggle_bit(PriFlashBOff) < 0)
-		return FLASH_FAIL;
-
-	write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1);
-	write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2);
-	write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3);
-	write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4);
-	write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5);
-	write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6);
-
-	if (poll_toggle_bit(SecFlashBOff) < 0)
-		return FLASH_FAIL;
-
-	return FLASH_SUCCESS;
-}
-
-int erase_block_flash(int nBlock, unsigned long address)
-{
-	long ulSectorOff = 0x0;
-
-	if ((nBlock < 0) || (nBlock > AFP_NumSectors))
-		return false;
-
-	ulSectorOff = (address - CONFIG_SYS_FLASH_BASE);
-
-	write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
-	write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
-	write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
-	write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
-	write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
-
-	write_flash(ulSectorOff, BlockEraseVal);
-
-	if (poll_toggle_bit(ulSectorOff) < 0)
-		return FLASH_FAIL;
-
-	return FLASH_SUCCESS;
-}
-
-void unlock_flash(long ulOffset)
-{
-	unsigned long ulOffsetAddr = ulOffset;
-	ulOffsetAddr &= 0xFFFF0000;
-
-	write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
-	write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
-	write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
-}
-
-int get_codes()
-{
-	int dev_id = 0;
-
-	write_flash(WRITESEQ1, GETCODEDATA1);
-	write_flash(WRITESEQ2, GETCODEDATA2);
-	write_flash(WRITESEQ3, GETCODEDATA3);
-
-	read_flash(0x0002, &dev_id);
-	dev_id &= 0x00FF;
-
-	reset_flash();
-
-	return dev_id;
-}
-
-void get_sector_number(long ulOffset, int *pnSector)
-{
-	int nSector = 0;
-
-	if (ulOffset >= SecFlashAOff) {
-		if ((ulOffset < SecFlashASec1Off)
-		    && (ulOffset < SecFlashASec2Off)) {
-			nSector = SECT32;
-		} else if ((ulOffset >= SecFlashASec2Off)
-			   && (ulOffset < SecFlashASec3Off)) {
-			nSector = SECT33;
-		} else if ((ulOffset >= SecFlashASec3Off)
-			   && (ulOffset < SecFlashASec4Off)) {
-			nSector = SECT34;
-		} else if ((ulOffset >= SecFlashASec4Off)
-			   && (ulOffset < SecFlashAEndOff)) {
-			nSector = SECT35;
-		}
-	} else if (ulOffset >= SecFlashBOff) {
-		if ((ulOffset < SecFlashBSec1Off)
-		    && (ulOffset < SecFlashBSec2Off)) {
-			nSector = SECT36;
-		}
-		if ((ulOffset < SecFlashBSec2Off)
-		    && (ulOffset < SecFlashBSec3Off)) {
-			nSector = SECT37;
-		}
-		if ((ulOffset < SecFlashBSec3Off)
-		    && (ulOffset < SecFlashBSec4Off)) {
-			nSector = SECT38;
-		}
-		if ((ulOffset < SecFlashBSec4Off)
-		    && (ulOffset < SecFlashBEndOff)) {
-			nSector = SECT39;
-		}
-	} else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) {
-		nSector = ulOffset & 0xffff0000;
-		nSector = ulOffset >> 16;
-		nSector = nSector & 0x000ff;
-	}
-
-	if ((nSector >= 0) && (nSector < AFP_NumSectors)) {
-		*pnSector = nSector;
-	}
-}
diff --git a/board/bf533-ezkit/psd4256.h b/board/bf533-ezkit/psd4256.h
deleted file mode 100644
index 9256696..0000000
--- a/board/bf533-ezkit/psd4256.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * U-Boot - psd4256.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Flash A/B Port A configuration registers.
- * Addresses are offset values to CONFIG_SYS_FLASH1_BASE
- * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B.
- */
-
-#define	PSD_PORTA_DIN	0x070000
-#define	PSD_PORTA_DOUT	0x070004
-#define	PSD_PORTA_DIR	0x070006
-
-/*
- * Flash A/B Port B configuration registers
- * Addresses are offset values to CONFIG_SYS_FLASH1_BASE
- * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B.
- */
-
-#define	PSD_PORTB_DIN	0x070001
-#define	PSD_PORTB_DOUT	0x070005
-#define	PSD_PORTB_DIR	0x070007
-
-/*
- * Flash A Port A Bit definitions
- */
-
-#define	PSDA_PPICLK1	0x20	/* PPI Clock select bit 1               */
-#define	PSDA_PPICLK0	0x10	/* PPI Clock select bit 0               */
-#define	PSDA_VDEC_RST	0x08	/* Video decoder reset, 0 = RESET       */
-#define	PSDA_VENC_RST	0x04	/* Video encoder reset, 0 = RESET       */
-#define	PSDA_CODEC_RST	0x01	/* Codec reset, 0 = RESET               */
-
-/*
- * Flash A Port B Bit definitions
- */
-
-#define	PSDA_LED9	0x20	/* LED 9, 1 = LED ON                    */
-#define	PSDA_LED8	0x10	/* LED 8, 1 = LED ON                    */
-#define	PSDA_LED7	0x08	/* LED 7, 1 = LED ON                    */
-#define	PSDA_LED6	0x04	/* LED 6, 1 = LED ON                    */
-#define	PSDA_LED5	0x02	/* LED 5, 1 = LED ON                    */
-#define	PSDA_LED4	0x01	/* LED 4, 1 = LED ON                    */
diff --git a/board/bf533-stamp/Kconfig b/board/bf533-stamp/Kconfig
deleted file mode 100644
index 0cffde3..0000000
--- a/board/bf533-stamp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF533_STAMP
-
-config SYS_BOARD
-	default "bf533-stamp"
-
-config SYS_CONFIG_NAME
-	default "bf533-stamp"
-
-endif
diff --git a/board/bf533-stamp/MAINTAINERS b/board/bf533-stamp/MAINTAINERS
deleted file mode 100644
index c7aeefa..0000000
--- a/board/bf533-stamp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF533-STAMP BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf533-stamp/
-F:	include/configs/bf533-stamp.h
-F:	configs/bf533-stamp_defconfig
diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile
deleted file mode 100644
index 041c98e..0000000
--- a/board/bf533-stamp/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf533-stamp.o
-obj-$(CONFIG_STAMP_CF) += ide-cf.o
-obj-$(CONFIG_VIDEO) += video.o
diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
deleted file mode 100644
index 185a651..0000000
--- a/board/bf533-stamp/bf533-stamp.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF533 Stamp board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-/* PF0 and PF1 are used to switch between the ethernet and flash:
- *         PF0  PF1
- *  flash:  0    0
- *  ether:  1    0
- */
-void swap_to(int device_id)
-{
-	gpio_request(GPIO_PF0, "eth_flash_swap");
-	gpio_request(GPIO_PF1, "eth_flash_swap");
-	gpio_direction_output(GPIO_PF0, device_id == ETHERNET);
-	gpio_direction_output(GPIO_PF1, 0);
-	SSYNC();
-}
-
-#if defined(CONFIG_MISC_INIT_R)
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-#ifdef CONFIG_STAMP_CF
-	cf_ide_init();
-#endif
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_LED_STATUS_OFF 0
-#define CONFIG_LED_STATUS_ON  1
-
-static int gpio_setup;
-
-static void stamp_led_set(int LED1, int LED2, int LED3)
-{
-	if (!gpio_setup) {
-		gpio_request(GPIO_PF2, "boot_progress");
-		gpio_request(GPIO_PF3, "boot_progress");
-		gpio_request(GPIO_PF4, "boot_progress");
-		gpio_direction_output(GPIO_PF2, LED1);
-		gpio_direction_output(GPIO_PF3, LED2);
-		gpio_direction_output(GPIO_PF4, LED3);
-		gpio_setup = 1;
-	} else {
-		gpio_set_value(GPIO_PF2, LED1);
-		gpio_set_value(GPIO_PF3, LED2);
-		gpio_set_value(GPIO_PF4, LED3);
-	}
-}
-
-void show_boot_progress(int status)
-{
-	switch (status) {
-	case BOOTSTAGE_ID_CHECK_MAGIC:
-		stamp_led_set(CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_OFF,
-			      CONFIG_LED_STATUS_ON);
-		break;
-	case BOOTSTAGE_ID_CHECK_HEADER:
-		stamp_led_set(CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_ON,
-			      CONFIG_LED_STATUS_OFF);
-		break;
-	case BOOTSTAGE_ID_CHECK_CHECKSUM:
-		stamp_led_set(CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_ON,
-			      CONFIG_LED_STATUS_ON);
-		break;
-	case BOOTSTAGE_ID_CHECK_ARCH:
-		stamp_led_set(CONFIG_LED_STATUS_ON, CONFIG_LED_STATUS_OFF,
-			      CONFIG_LED_STATUS_OFF);
-		break;
-	case BOOTSTAGE_ID_CHECK_IMAGETYPE:
-	case BOOTSTAGE_ID_DECOMP_IMAGE:
-		stamp_led_set(CONFIG_LED_STATUS_ON, CONFIG_LED_STATUS_OFF,
-			      CONFIG_LED_STATUS_ON);
-		break;
-	case BOOTSTAGE_ID_KERNEL_LOADED:
-	case BOOTSTAGE_ID_CHECK_BOOT_OS:
-		stamp_led_set(CONFIG_LED_STATUS_ON, CONFIG_LED_STATUS_ON,
-			      CONFIG_LED_STATUS_OFF);
-		break;
-	case BOOTSTAGE_ID_BOOT_OS_RETURNED:
-	case BOOTSTAGE_ID_RD_MAGIC:
-	case BOOTSTAGE_ID_RD_HDR_CHECKSUM:
-	case BOOTSTAGE_ID_RD_CHECKSUM:
-	case BOOTSTAGE_ID_RAMDISK:
-	case BOOTSTAGE_ID_NO_RAMDISK:
-	case BOOTSTAGE_ID_RUN_OS:
-		stamp_led_set(CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_OFF,
-			      CONFIG_LED_STATUS_OFF);
-		break;
-	default:
-		stamp_led_set(CONFIG_LED_STATUS_ON, CONFIG_LED_STATUS_ON,
-			      CONFIG_LED_STATUS_ON);
-		break;
-	}
-}
-#endif
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
-	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk
deleted file mode 100644
index 7f9138b..0000000
--- a/board/bf533-stamp/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf533-stamp/ide-cf.c b/board/bf533-stamp/ide-cf.c
deleted file mode 100644
index 3e4080e..0000000
--- a/board/bf533-stamp/ide-cf.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * CF IDE addon card code
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-void cf_outb(unsigned char val, volatile unsigned char *addr)
-{
-	/* "ETHERNET" means the expansion memory banks */
-	swap_to(ETHERNET);
-
-	*addr = val;
-	SSYNC();
-
-	swap_to(FLASH);
-}
-
-unsigned char cf_inb(volatile unsigned char *addr)
-{
-	unsigned char c;
-
-	swap_to(ETHERNET);
-
-	c = *addr;
-	SSYNC();
-
-	swap_to(FLASH);
-
-	return c;
-}
-
-void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
-{
-	int i;
-
-	swap_to(ETHERNET);
-
-	for (i = 0; i < words; i++) {
-		*(sect_buf + i) = *addr;
-		SSYNC();
-	}
-
-	swap_to(FLASH);
-}
-
-void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
-{
-	int i;
-
-	swap_to(ETHERNET);
-
-	for (i = 0; i < words; i++) {
-		*addr = *(sect_buf + i);
-		SSYNC();
-	}
-
-	swap_to(FLASH);
-}
-
-/* Definitions used in  Compact Flash Boot support */
-#define FIO_EDGE_CF_BITS	0x0000
-#define FIO_POLAR_CF_BITS	0x0000
-#define FIO_EDGE_BITS		0x1E0
-#define FIO_POLAR_BITS		0x160
-
-/* Compact flash status bits in status register */
-#define CF_STAT_BITS	0x00000060
-
-void cf_ide_init(void)
-{
-	int i, cf_stat;
-
-	/* Check whether CF card is inserted */
-	bfin_write_FIO_EDGE(FIO_EDGE_CF_BITS);
-	bfin_write_FIO_POLAR(FIO_POLAR_CF_BITS);
-	for (i = 0; i < 0x300; i++)
-		asm volatile("nop;");
-
-	cf_stat = bfin_read_FIO_FLAG_S() & CF_STAT_BITS;
-
-	bfin_write_FIO_EDGE(FIO_EDGE_BITS);
-	bfin_write_FIO_POLAR(FIO_POLAR_BITS);
-
-	if (!cf_stat) {
-		for (i = 0; i < 0x3000; i++)
-			asm volatile("nop;");
-
-		ide_init();
-	}
-}
diff --git a/board/bf533-stamp/video.c b/board/bf533-stamp/video.c
deleted file mode 100644
index e9b9a9a..0000000
--- a/board/bf533-stamp/video.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * BF533-STAMP splash driver
- *
- * Copyright (c) 2006-2008 Analog Devices Inc.
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
- * (C) Copyright 2002
- * Wolfgang Denk, wd@denx.de
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/dma.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-
-#define DMA_SIZE16	2
-
-#include <asm/mach-common/bits/ppi.h>
-
-#define NTSC_FRAME_ADDR 0x06000000
-#include "video.h"
-
-/* NTSC OUTPUT SIZE  720 * 240 */
-#define VERTICAL	2
-#define HORIZONTAL	4
-
-int is_vblank_line(const int line)
-{
-	/*
-	 *  This array contains a single bit for each line in
-	 *  an NTSC frame.
-	 */
-	if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
-		return true;
-
-	return false;
-}
-
-int NTSC_framebuffer_init(char *base_address)
-{
-	const int NTSC_frames = 1;
-	const int NTSC_lines = 525;
-	char *dest = base_address;
-	int frame_num, line_num;
-
-	for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
-		for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
-			unsigned int code;
-			int offset = 0;
-			int i;
-
-			if (is_vblank_line(line_num))
-				offset++;
-
-			if (line_num > 266 || line_num < 3)
-				offset += 2;
-
-			/* Output EAV code */
-			code = system_code_map[offset].eav;
-			write_dest_byte((char)(code >> 24) & 0xff);
-			write_dest_byte((char)(code >> 16) & 0xff);
-			write_dest_byte((char)(code >> 8) & 0xff);
-			write_dest_byte((char)(code) & 0xff);
-
-			/* Output horizontal blanking */
-			for (i = 0; i < 67 * 2; ++i) {
-				write_dest_byte(0x80);
-				write_dest_byte(0x10);
-			}
-
-			/* Output SAV */
-			code = system_code_map[offset].sav;
-			write_dest_byte((char)(code >> 24) & 0xff);
-			write_dest_byte((char)(code >> 16) & 0xff);
-			write_dest_byte((char)(code >> 8) & 0xff);
-			write_dest_byte((char)(code) & 0xff);
-
-			/* Output empty horizontal data */
-			for (i = 0; i < 360 * 2; ++i) {
-				write_dest_byte(0x80);
-				write_dest_byte(0x10);
-			}
-		}
-	}
-
-	return dest - base_address;
-}
-
-void fill_frame(char *Frame, int Value)
-{
-	int *OddPtr32;
-	int OddLine;
-	int *EvenPtr32;
-	int EvenLine;
-	int i;
-	int *data;
-	int m, n;
-
-	/* fill odd and even frames */
-	for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
-		OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
-		EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
-		for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
-			*OddPtr32 = Value;
-			*EvenPtr32 = Value;
-		}
-	}
-
-	for (m = 0; m < VERTICAL; m++) {
-		data = (int *)u_boot_logo.data;
-		for (OddLine = (22 + m), EvenLine = (285 + m);
-		     OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
-		     OddLine += VERTICAL, EvenLine += VERTICAL) {
-			OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
-			EvenPtr32 =
-			    (int *)((Frame + ((EvenLine) * 1716)) + 276);
-			for (i = 0; i < u_boot_logo.width / 2; i++) {
-				/* enlarge one pixel to m x n */
-				for (n = 0; n < HORIZONTAL; n++) {
-					*OddPtr32++ = *data;
-					*EvenPtr32++ = *data;
-				}
-				data++;
-			}
-		}
-	}
-}
-
-static void video_init(char *NTSCFrame)
-{
-	NTSC_framebuffer_init(NTSCFrame);
-	fill_frame(NTSCFrame, BLUE);
-
-	bfin_write_PPI_CONTROL(0x0082);
-	bfin_write_PPI_FRAME(0x020D);
-
-	bfin_write_DMA0_START_ADDR(NTSCFrame);
-	bfin_write_DMA0_X_COUNT(0x035A);
-	bfin_write_DMA0_X_MODIFY(0x0002);
-	bfin_write_DMA0_Y_COUNT(0x020D);
-	bfin_write_DMA0_Y_MODIFY(0x0002);
-	bfin_write_DMA0_CONFIG(0x1015);
-	bfin_write_PPI_CONTROL(0x0083);
-}
-
-void video_stop(void)
-{
-	bfin_write_PPI_CONTROL(0);
-	bfin_write_DMA0_CONFIG(0);
-}
-
-int drv_video_init(void)
-{
-	struct stdio_dev videodev;
-
-	video_init((void *)NTSC_FRAME_ADDR);
-
-	memset(&videodev, 0, sizeof(videodev));
-	strcpy(videodev.name, "video");
-
-	return stdio_register(&videodev);
-}
diff --git a/board/bf533-stamp/video.h b/board/bf533-stamp/video.h
deleted file mode 100644
index 949c3d8..0000000
--- a/board/bf533-stamp/video.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#include <video_logo.h>
-#define write_dest_byte(val) {*dest++=val;}
-#define BLACK   (0x01800180)	/* black pixel pattern   */
-#define BLUE    (0x296E29F0)	/* blue pixel pattern    */
-#define RED     (0x51F0515A)	/* red pixel pattern     */
-#define MAGENTA (0x6ADE6ACA)	/* magenta pixel pattern */
-#define GREEN   (0x91229136)	/* green pixel pattern   */
-#define CYAN    (0xAA10AAA6)	/* cyan pixel pattern    */
-#define YELLOW  (0xD292D210)	/* yellow pixel pattern  */
-#define WHITE   (0xFE80FE80)	/* white pixel pattern   */
-
-typedef struct {
-	unsigned int sav;
-	unsigned int eav;
-} system_code_type;
-
-const system_code_type system_code_map[] = {
-	{ 0xFF000080, 0xFF00009D },
-	{ 0xFF0000AB, 0xFF0000B6 },
-	{ 0xFF0000C7, 0xFF0000DA },
-	{ 0xFF0000EC, 0xFF0000F1 },
-};
diff --git a/board/bf537-minotaur/Kconfig b/board/bf537-minotaur/Kconfig
deleted file mode 100644
index 204f609..0000000
--- a/board/bf537-minotaur/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF537_MINOTAUR
-
-config SYS_BOARD
-	default "bf537-minotaur"
-
-config SYS_CONFIG_NAME
-	default "bf537-minotaur"
-
-endif
diff --git a/board/bf537-minotaur/MAINTAINERS b/board/bf537-minotaur/MAINTAINERS
deleted file mode 100644
index 04643b1..0000000
--- a/board/bf537-minotaur/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF537-MINOTAUR BOARD
-M:	Martin Strubel <strubel@section5.ch>
-S:	Maintained
-F:	board/bf537-minotaur/
-F:	include/configs/bf537-minotaur.h
-F:	configs/bf537-minotaur_defconfig
diff --git a/board/bf537-minotaur/Makefile b/board/bf537-minotaur/Makefile
deleted file mode 100644
index 13ed8bf..0000000
--- a/board/bf537-minotaur/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf537-minotaur.o
diff --git a/board/bf537-minotaur/bf537-minotaur.c b/board/bf537-minotaur/bf537-minotaur.c
deleted file mode 100644
index 34750ec..0000000
--- a/board/bf537-minotaur/bf537-minotaur.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <net.h>
-#include <asm/blackfin.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: CSP BF537 Minotaur board\n");
-	printf("       Support: http://www.camsig.co.uk/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/bf537-minotaur/config.mk b/board/bf537-minotaur/config.mk
deleted file mode 100644
index 7402f44..0000000
--- a/board/bf537-minotaur/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/bf537-pnav/Kconfig b/board/bf537-pnav/Kconfig
deleted file mode 100644
index acb1f89..0000000
--- a/board/bf537-pnav/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF537_PNAV
-
-config SYS_BOARD
-	default "bf537-pnav"
-
-config SYS_CONFIG_NAME
-	default "bf537-pnav"
-
-endif
diff --git a/board/bf537-pnav/MAINTAINERS b/board/bf537-pnav/MAINTAINERS
deleted file mode 100644
index b8b22a3..0000000
--- a/board/bf537-pnav/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF537-PNAV BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf537-pnav/
-F:	include/configs/bf537-pnav.h
-F:	configs/bf537-pnav_defconfig
diff --git a/board/bf537-pnav/Makefile b/board/bf537-pnav/Makefile
deleted file mode 100644
index f7af8cd..0000000
--- a/board/bf537-pnav/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf537-pnav.o
diff --git a/board/bf537-pnav/bf537-pnav.c b/board/bf537-pnav/bf537-pnav.c
deleted file mode 100644
index c3b06f0..0000000
--- a/board/bf537-pnav/bf537-pnav.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <net.h>
-#include <asm/blackfin.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF537 PNAV board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/bf537-srv1/Kconfig b/board/bf537-srv1/Kconfig
deleted file mode 100644
index 2ddcd69..0000000
--- a/board/bf537-srv1/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF537_SRV1
-
-config SYS_BOARD
-	default "bf537-srv1"
-
-config SYS_CONFIG_NAME
-	default "bf537-srv1"
-
-endif
diff --git a/board/bf537-srv1/MAINTAINERS b/board/bf537-srv1/MAINTAINERS
deleted file mode 100644
index c8f1458..0000000
--- a/board/bf537-srv1/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF537-SRV1 BOARD
-M:	Martin Strubel <strubel@section5.ch>
-S:	Maintained
-F:	board/bf537-srv1/
-F:	include/configs/bf537-srv1.h
-F:	configs/bf537-srv1_defconfig
diff --git a/board/bf537-srv1/Makefile b/board/bf537-srv1/Makefile
deleted file mode 100644
index 1815fc5..0000000
--- a/board/bf537-srv1/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf537-srv1.o
diff --git a/board/bf537-srv1/bf537-srv1.c b/board/bf537-srv1/bf537-srv1.c
deleted file mode 100644
index fc22c07..0000000
--- a/board/bf537-srv1/bf537-srv1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <net.h>
-#include <asm/blackfin.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Surveyor SRV1 board\n");
-	printf("       Support: http://www.surveyor.com/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/bf537-srv1/config.mk b/board/bf537-srv1/config.mk
deleted file mode 100644
index 7402f44..0000000
--- a/board/bf537-srv1/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/bf537-stamp/Kconfig b/board/bf537-stamp/Kconfig
deleted file mode 100644
index 4f86128..0000000
--- a/board/bf537-stamp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF537_STAMP
-
-config SYS_BOARD
-	default "bf537-stamp"
-
-config SYS_CONFIG_NAME
-	default "bf537-stamp"
-
-endif
diff --git a/board/bf537-stamp/MAINTAINERS b/board/bf537-stamp/MAINTAINERS
deleted file mode 100644
index 7d9c133..0000000
--- a/board/bf537-stamp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF537-STAMP BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf537-stamp/
-F:	include/configs/bf537-stamp.h
-F:	configs/bf537-stamp_defconfig
diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile
deleted file mode 100644
index 4008e3a..0000000
--- a/board/bf537-stamp/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf537-stamp.o
-obj-$(CONFIG_BFIN_IDE)   += ide-cf.o
-obj-$(CONFIG_HAS_POST)   += post-memory.o
diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c
deleted file mode 100644
index 1f90c00..0000000
--- a/board/bf537-stamp/bf537-stamp.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include <net.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF537 stamp board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
-#ifdef CONFIG_MTD_NOR_FLASH
-	/* we cram the MAC in the last flash sector */
-	uchar *board_mac_addr = (uchar *)0x203F0000;
-	if (is_valid_ethaddr(board_mac_addr)) {
-		memcpy(mac_addr, board_mac_addr, 6);
-		eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-#endif
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
-
-#ifdef CONFIG_MTD_NOR_FLASH
-	/* we use the last sector for the MAC address / POST LDR */
-	extern flash_info_t flash_info[];
-	flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
-#endif
-
-#ifdef CONFIG_BFIN_IDE
-	cf_ide_init();
-#endif
-
-	return 0;
-}
diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk
deleted file mode 100644
index ab0fbec..0000000
--- a/board/bf537-stamp/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
-LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/bf537-stamp/ide-cf.c b/board/bf537-stamp/ide-cf.c
deleted file mode 100644
index 5a3720d..0000000
--- a/board/bf537-stamp/ide-cf.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * CF IDE addon card code
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <asm/blackfin.h>
-
-void cf_outb(unsigned char val, volatile unsigned char *addr)
-{
-	*(addr) = val;
-	SSYNC();
-}
-
-unsigned char cf_inb(volatile unsigned char *addr)
-{
-	volatile unsigned char c;
-
-	c = *(addr);
-	SSYNC();
-
-	return c;
-}
-
-void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
-{
-	int i;
-
-	for (i = 0; i < words; i++)
-		*(sect_buf + i) = *(addr);
-	SSYNC();
-}
-
-void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
-{
-	int i;
-
-	for (i = 0; i < words; i++)
-		*(addr) = *(sect_buf + i);
-	SSYNC();
-}
-
-void cf_ide_init(void)
-{
-#if defined(CONFIG_BFIN_TRUE_IDE)
-	/* Enable ATASEL when in True IDE mode */
-	printf("Using CF True IDE Mode\n");
-	cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
-	udelay(1000);
-#elif defined(CONFIG_BFIN_CF_IDE)
-	/* Disable ATASEL when we're in Common Memory Mode */
-	printf("Using CF Common Memory Mode\n");
-	cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
-	udelay(1000);
-#elif defined(CONFIG_BFIN_HDD_IDE)
-	printf("Using HDD IDE Mode\n");
-#endif
-	ide_init();
-}
diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c
deleted file mode 100644
index 2dea92f..0000000
--- a/board/bf537-stamp/post-memory.c
+++ /dev/null
@@ -1,257 +0,0 @@
-#include <common.h>
-#include <asm/io.h>
-
-#include <post.h>
-#include <watchdog.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
-#define CLKIN 25000000
-#define PATTERN1 0x5A5A5A5A
-#define PATTERN2 0xAAAAAAAA
-
-#define CCLK_NUM	4
-#define SCLK_NUM	3
-
-void post_out_buff(char *buff);
-void post_init_pll(int mult, int div);
-int post_init_sdram(int sclk);
-void post_init_uart(int sclk);
-
-const int pll[CCLK_NUM][SCLK_NUM][2] = {
-	{ {20, 4}, {20, 5}, {20, 10} },	/* CCLK = 500M */
-	{ {16, 4}, {16, 5}, {16, 8} },	/* CCLK = 400M */
-	{ {8, 2}, {8, 4}, {8, 5} },	/* CCLK = 200M */
-	{ {4, 1}, {4, 2}, {4, 4} }	/* CCLK = 100M */
-};
-const char *const log[CCLK_NUM][SCLK_NUM] = {
-	{"CCLK-500MHz SCLK-125MHz:    Writing...\0",
-	 "CCLK-500MHz SCLK-100MHz:    Writing...\0",
-	 "CCLK-500MHz SCLK- 50MHz:    Writing...\0",},
-	{"CCLK-400MHz SCLK-100MHz:    Writing...\0",
-	 "CCLK-400MHz SCLK- 80MHz:    Writing...\0",
-	 "CCLK-400MHz SCLK- 50MHz:    Writing...\0",},
-	{"CCLK-200MHz SCLK-100MHz:    Writing...\0",
-	 "CCLK-200MHz SCLK- 50MHz:    Writing...\0",
-	 "CCLK-200MHz SCLK- 40MHz:    Writing...\0",},
-	{"CCLK-100MHz SCLK-100MHz:    Writing...\0",
-	 "CCLK-100MHz SCLK- 50MHz:    Writing...\0",
-	 "CCLK-100MHz SCLK- 25MHz:    Writing...\0",},
-};
-
-int memory_post_test(int flags)
-{
-	int addr;
-	int m, n;
-	int sclk, sclk_temp;
-	int ret = 1;
-
-	sclk_temp = CLKIN / 1000000;
-	sclk_temp = sclk_temp * CONFIG_VCO_MULT;
-	for (sclk = 0; sclk_temp > 0; sclk++)
-		sclk_temp -= CONFIG_SCLK_DIV;
-	sclk = sclk * 1000000;
-	post_init_uart(sclk);
-	if (post_hotkeys_pressed() == 0)
-		return 0;
-
-	for (m = 0; m < CCLK_NUM; m++) {
-		for (n = 0; n < SCLK_NUM; n++) {
-			/* Calculate the sclk */
-			sclk_temp = CLKIN / 1000000;
-			sclk_temp = sclk_temp * pll[m][n][0];
-			for (sclk = 0; sclk_temp > 0; sclk++)
-				sclk_temp -= pll[m][n][1];
-			sclk = sclk * 1000000;
-
-			post_init_pll(pll[m][n][0], pll[m][n][1]);
-			post_init_sdram(sclk);
-			post_init_uart(sclk);
-			post_out_buff("\n\r\0");
-			post_out_buff(log[m][n]);
-			for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4)
-				*(unsigned long *)addr = PATTERN1;
-			post_out_buff("Reading...\0");
-			for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4) {
-				if ((*(unsigned long *)addr) != PATTERN1) {
-					post_out_buff("Error\n\r\0");
-					ret = 0;
-				}
-			}
-			post_out_buff("OK\n\r\0");
-		}
-	}
-	if (ret)
-		post_out_buff("memory POST passed\n\r\0");
-	else
-		post_out_buff("memory POST failed\n\r\0");
-
-	post_out_buff("\n\r\n\r\0");
-	return 1;
-}
-
-void post_init_uart(int sclk)
-{
-	int divisor;
-
-	for (divisor = 0; sclk > 0; divisor++)
-		sclk -= 57600 * 16;
-
-	bfin_write_PORTF_FER(0x000F);
-	bfin_write_PORTH_FER(0xFFFF);
-
-	bfin_write_UART_GCTL(0x00);
-	bfin_write_UART_LCR(0x83);
-	SSYNC();
-	bfin_write_UART_DLL(divisor & 0xFF);
-	SSYNC();
-	bfin_write_UART_DLH((divisor >> 8) & 0xFF);
-	SSYNC();
-	bfin_write_UART_LCR(0x03);
-	SSYNC();
-	bfin_write_UART_GCTL(0x01);
-	SSYNC();
-}
-
-void post_out_buff(char *buff)
-{
-
-	int i = 0;
-	for (i = 0; i < 0x80000; i++)
-		;
-	i = 0;
-	while ((buff[i] != '\0') && (i != 100)) {
-		while (!(bfin_read_pUART_LSR() & 0x20)) ;
-		bfin_write_UART_THR(buff[i]);
-		SSYNC();
-		i++;
-	}
-	for (i = 0; i < 0x80000; i++)
-		;
-}
-
-void post_init_pll(int mult, int div)
-{
-
-	bfin_write_SIC_IWR(0x01);
-	bfin_write_PLL_CTL((mult << 9));
-	bfin_write_PLL_DIV(div);
-	asm("CLI R2;");
-	asm("IDLE;");
-	asm("STI R2;");
-	while (!(bfin_read_PLL_STAT() & 0x20)) ;
-}
-
-int post_init_sdram(int sclk)
-{
-	int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num, SDRAM_tRCD,
-	    SDRAM_tWR;
-	int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE, SDRAM_WIDTH,
-	    mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
-
-	if ((sclk > 119402985)) {
-		SDRAM_tRP = TRP_2;
-		SDRAM_tRP_num = 2;
-		SDRAM_tRAS = TRAS_7;
-		SDRAM_tRAS_num = 7;
-		SDRAM_tRCD = TRCD_2;
-		SDRAM_tWR = TWR_2;
-	} else if ((sclk > 104477612) && (sclk <= 119402985)) {
-		SDRAM_tRP = TRP_2;
-		SDRAM_tRP_num = 2;
-		SDRAM_tRAS = TRAS_6;
-		SDRAM_tRAS_num = 6;
-		SDRAM_tRCD = TRCD_2;
-		SDRAM_tWR = TWR_2;
-	} else if ((sclk > 89552239) && (sclk <= 104477612)) {
-		SDRAM_tRP = TRP_2;
-		SDRAM_tRP_num = 2;
-		SDRAM_tRAS = TRAS_5;
-		SDRAM_tRAS_num = 5;
-		SDRAM_tRCD = TRCD_2;
-		SDRAM_tWR = TWR_2;
-	} else if ((sclk > 74626866) && (sclk <= 89552239)) {
-		SDRAM_tRP = TRP_2;
-		SDRAM_tRP_num = 2;
-		SDRAM_tRAS = TRAS_4;
-		SDRAM_tRAS_num = 4;
-		SDRAM_tRCD = TRCD_2;
-		SDRAM_tWR = TWR_2;
-	} else if ((sclk > 66666667) && (sclk <= 74626866)) {
-		SDRAM_tRP = TRP_2;
-		SDRAM_tRP_num = 2;
-		SDRAM_tRAS = TRAS_3;
-		SDRAM_tRAS_num = 3;
-		SDRAM_tRCD = TRCD_2;
-		SDRAM_tWR = TWR_2;
-	} else if ((sclk > 59701493) && (sclk <= 66666667)) {
-		SDRAM_tRP = TRP_1;
-		SDRAM_tRP_num = 1;
-		SDRAM_tRAS = TRAS_4;
-		SDRAM_tRAS_num = 4;
-		SDRAM_tRCD = TRCD_1;
-		SDRAM_tWR = TWR_2;
-	} else if ((sclk > 44776119) && (sclk <= 59701493)) {
-		SDRAM_tRP = TRP_1;
-		SDRAM_tRP_num = 1;
-		SDRAM_tRAS = TRAS_3;
-		SDRAM_tRAS_num = 3;
-		SDRAM_tRCD = TRCD_1;
-		SDRAM_tWR = TWR_2;
-	} else if ((sclk > 29850746) && (sclk <= 44776119)) {
-		SDRAM_tRP = TRP_1;
-		SDRAM_tRP_num = 1;
-		SDRAM_tRAS = TRAS_2;
-		SDRAM_tRAS_num = 2;
-		SDRAM_tRCD = TRCD_1;
-		SDRAM_tWR = TWR_2;
-	} else if (sclk <= 29850746) {
-		SDRAM_tRP = TRP_1;
-		SDRAM_tRP_num = 1;
-		SDRAM_tRAS = TRAS_1;
-		SDRAM_tRAS_num = 1;
-		SDRAM_tRCD = TRCD_1;
-		SDRAM_tWR = TWR_2;
-	} else {
-		SDRAM_tRP = TRP_1;
-		SDRAM_tRP_num = 1;
-		SDRAM_tRAS = TRAS_1;
-		SDRAM_tRAS_num = 1;
-		SDRAM_tRCD = TRCD_1;
-		SDRAM_tWR = TWR_2;
-	}
-	/*SDRAM INFORMATION: */
-	SDRAM_Tref = 64;	/* Refresh period in milliseconds */
-	SDRAM_NRA = 4096;	/* Number of row addresses in SDRAM */
-	SDRAM_CL = CL_3;	/* 2 */
-
-	SDRAM_SIZE = EBSZ_64;
-	SDRAM_WIDTH = EBCAW_10;
-
-	mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
-
-	/* Equation from section 17 (p17-46) of BF533 HRM */
-	mem_SDRRC =
-	    (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) -
-	    (SDRAM_tRAS_num + SDRAM_tRP_num);
-
-	/* Enable SCLK Out */
-	mem_SDGCTL =
-	    (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
-	     | PSS);
-
-	SSYNC();
-
-	bfin_write_EBIU_SDGCTL(bfin_write_EBIU_SDGCTL() | 0x1000000);
-	/* Set the SDRAM Refresh Rate control register based on SSCLK value */
-	bfin_write_EBIU_SDRRC(mem_SDRRC);
-
-	/* SDRAM Memory Bank Control Register */
-	bfin_write_EBIU_SDBCTL(mem_SDBCTL);
-
-	/* SDRAM Memory Global Control Register */
-	bfin_write_EBIU_SDGCTL(mem_SDGCTL);
-	SSYNC();
-	return mem_SDRRC;
-}
-
-#endif				/* CONFIG_POST & CONFIG_SYS_POST_MEMORY */
diff --git a/board/bf538f-ezkit/Kconfig b/board/bf538f-ezkit/Kconfig
deleted file mode 100644
index e40fcdb..0000000
--- a/board/bf538f-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF538F_EZKIT
-
-config SYS_BOARD
-	default "bf538f-ezkit"
-
-config SYS_CONFIG_NAME
-	default "bf538f-ezkit"
-
-endif
diff --git a/board/bf538f-ezkit/MAINTAINERS b/board/bf538f-ezkit/MAINTAINERS
deleted file mode 100644
index 7964735..0000000
--- a/board/bf538f-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF538F-EZKIT BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf538f-ezkit/
-F:	include/configs/bf538f-ezkit.h
-F:	configs/bf538f-ezkit_defconfig
diff --git a/board/bf538f-ezkit/Makefile b/board/bf538f-ezkit/Makefile
deleted file mode 100644
index eb1703e..0000000
--- a/board/bf538f-ezkit/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf538f-ezkit.o
diff --git a/board/bf538f-ezkit/bf538f-ezkit.c b/board/bf538f-ezkit/bf538f-ezkit.c
deleted file mode 100644
index 2dd4c0c..0000000
--- a/board/bf538f-ezkit/bf538f-ezkit.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF538F EZ-Kit Lite board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
-	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk
deleted file mode 100644
index 7f9138b..0000000
--- a/board/bf538f-ezkit/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf548-ezkit/Kconfig b/board/bf548-ezkit/Kconfig
deleted file mode 100644
index 550227f..0000000
--- a/board/bf548-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF548_EZKIT
-
-config SYS_BOARD
-	default "bf548-ezkit"
-
-config SYS_CONFIG_NAME
-	default "bf548-ezkit"
-
-endif
diff --git a/board/bf548-ezkit/MAINTAINERS b/board/bf548-ezkit/MAINTAINERS
deleted file mode 100644
index e2683bb..0000000
--- a/board/bf548-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF548-EZKIT BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf548-ezkit/
-F:	include/configs/bf548-ezkit.h
-F:	configs/bf548-ezkit_defconfig
diff --git a/board/bf548-ezkit/Makefile b/board/bf548-ezkit/Makefile
deleted file mode 100644
index e4d0caa..0000000
--- a/board/bf548-ezkit/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf548-ezkit.o
-obj-$(CONFIG_VIDEO)      += video.o
diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c
deleted file mode 100644
index 31d6eee..0000000
--- a/board/bf548-ezkit/bf548-ezkit.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/sdh.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF548 EZ-Kit board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	/* Set async addr lines as peripheral */
-	const unsigned short pins[] = {
-		P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
-		P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
-		P_A21, P_A22, P_A23, P_A24, 0
-	};
-	return peripheral_request_list(pins, "async");
-}
-
-#ifdef CONFIG_SMC911X
-int board_eth_init(bd_t *bis)
-{
-	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
-
-#ifdef CONFIG_BFIN_SDH
-int board_mmc_init(bd_t *bis)
-{
-	return bfin_mmc_init(bis);
-}
-#endif
-
-#ifdef CONFIG_USB_BLACKFIN
-void board_musb_init(void)
-{
-	/*
-	 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both device
-	 * and OTG host modes, while rev 1.1 and greater require PE7 to
-	 * be low for device mode and high for host mode.  We set it high
-	 * here because we are in host mode.
-	 */
-	gpio_request(GPIO_PE7, "musb-vbus");
-	gpio_direction_output(GPIO_PE7, 1);
-}
-#endif
diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk
deleted file mode 100644
index 7bb8e9c..0000000
--- a/board/bf548-ezkit/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA       := --dma 6
-LDR_FLAGS-BFIN_BOOT_FIFO       := --dma 1
-LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
-LDR_FLAGS-BFIN_BOOT_UART       := --dma 1
-LDR_FLAGS-BFIN_BOOT_NAND       := --dma 6
diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c
deleted file mode 100644
index 3765993..0000000
--- a/board/bf548-ezkit/video.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/*
- * video.c - run splash screen on lcd
- *
- * Copyright (c) 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/dma.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-
-#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDec.h>
-#include <lzma/LzmaTools.h>
-
-#define DMA_SIZE16	2
-
-#include <asm/mach-common/bits/eppi.h>
-
-#include EASYLOGO_HEADER
-
-#define LCD_X_RES		480	/*Horizontal Resolution */
-#define LCD_Y_RES		272	/* Vertical Resolution */
-
-#define LCD_BPP			24	/* Bit Per Pixel */
-#define LCD_PIXEL_SIZE		(LCD_BPP / 8)
-#define	DMA_BUS_SIZE		32
-#define ACTIVE_VIDEO_MEM_OFFSET 0
-
-/* 	-- Horizontal synchronizing --
- *
- * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
- * (LCY-W-06602A Page 9 of 22)
- *
- * Clock Frequency 	1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
- *
- * Period 		TH - 525 - Clock
- * Pulse width 		THp - 41 - Clock
- * Horizontal period 	THd - 480 - Clock
- * Back porch 		THb - 2 - Clock
- * Front porch 		THf - 2 - Clock
- *
- * -- Vertical synchronizing --
- * Period 		TV - 286 - Line
- * Pulse width 		TVp - 10 - Line
- * Vertical period 	TVd - 272 - Line
- * Back porch 		TVb - 2 - Line
- * Front porch 		TVf - 2 - Line
- */
-
-#define	LCD_CLK         	(8*1000*1000)	/* 8MHz */
-
-/* # active data to transfer after Horizontal Delay clock */
-#define EPPI_HCOUNT		LCD_X_RES
-
-/* # active lines to transfer after Vertical Delay clock */
-#define EPPI_VCOUNT		LCD_Y_RES
-
-/* Samples per Line = 480 (active data) + 45 (padding) */
-#define EPPI_LINE		525
-
-/* Lines per Frame = 272 (active data) + 14 (padding) */
-#define EPPI_FRAME		286
-
-/* FS1 (Hsync) Width (Typical)*/
-#define EPPI_FS1W_HBL		41
-
-/* FS1 (Hsync) Period (Typical) */
-#define EPPI_FS1P_AVPL		EPPI_LINE
-
-/* Horizontal Delay clock after assertion of Hsync (Typical) */
-#define EPPI_HDELAY		43
-
-/* FS2 (Vsync) Width    = FS1 (Hsync) Period * 10 */
-#define EPPI_FS2W_LVB		(EPPI_LINE * 10)
-
- /* FS2 (Vsync) Period   = FS1 (Hsync) Period * Lines per Frame */
-#define EPPI_FS2P_LAVF		(EPPI_LINE * EPPI_FRAME)
-
-/* Vertical Delay after assertion of Vsync (2 Lines) */
-#define EPPI_VDELAY		12
-
-#define EPPI_CLIP		0xFF00FF00
-
-/* EPPI Control register configuration value for RGB out
- * - EPPI as Output
- * GP 2 frame sync mode,
- * Internal Clock generation disabled, Internal FS generation enabled,
- * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
- * FS1 & FS2 are active high,
- * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
- * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
- * Swapping Enabled,
- * One (DMA) Channel Mode,
- * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
- * Regular watermark - when FIFO is 100% full,
- * Urgent watermark - when FIFO is 75% full
- */
-
-#define EPPI_CONTROL		(0x20136E2E)
-
-static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
-{
-	u32 sclk = get_sclk();
-
-	/* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
-
-	return (((sclk / target_ppi_clk) / 2) - 1);
-}
-
-void Init_PPI(void)
-{
-	u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
-
-	bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
-	bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
-	bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
-	bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
-	bfin_write_EPPI0_CLIP(EPPI_CLIP);
-
-	bfin_write_EPPI0_FRAME(EPPI_FRAME);
-	bfin_write_EPPI0_LINE(EPPI_LINE);
-
-	bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
-	bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
-	bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
-	bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
-
-	bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
-
-/*
- * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
- * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
- */
-#if defined(CONFIG_VIDEO_RGB666)
-		bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
-					 RGB_FMT_EN);
-#else
-		bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
-					 ~RGB_FMT_EN);
-#endif
-
-}
-
-#define               DEB2_URGENT  0x2000     /* DEB2 Urgent */
-
-void Init_DMA(void *dst)
-{
-
-#if defined(CONFIG_DEB_DMA_URGENT)
-	bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
-#endif
-
-	bfin_write_DMA12_START_ADDR(dst);
-
-	/* X count */
-	bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
-	bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
-
-	/* Y count */
-	bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
-	bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
-
-	/* DMA Config */
-	bfin_write_DMA12_CONFIG(
-		WDSIZE_32	|	/* 32 bit DMA */
-		DMA2D 		|	/* 2D DMA */
-		FLOW_AUTO		/* autobuffer mode */
-	);
-}
-
-void Init_Ports(void)
-{
-	const unsigned short pins[] = {
-		P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
-		P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
-		P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
-		P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
-#if !defined(CONFIG_VIDEO_RGB666)
-		P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
-		P_PPI0_D23,
-#endif
-		P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
-	};
-	peripheral_request_list(pins, "lcd");
-
-	gpio_request(GPIO_PE3, "lcd-disp");
-	gpio_direction_output(GPIO_PE3, 1);
-}
-
-void EnableDMA(void)
-{
-	bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
-}
-
-void DisableDMA(void)
-{
-	bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
-}
-
-/* enable and disable PPI functions */
-void EnablePPI(void)
-{
-	bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
-}
-
-void DisablePPI(void)
-{
-	bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
-}
-
-int video_init(void *dst)
-{
-	Init_Ports();
-	Init_DMA(dst);
-	EnableDMA();
-	Init_PPI();
-	EnablePPI();
-
-	return 0;
-}
-
-void video_stop(void)
-{
-	DisablePPI();
-	DisableDMA();
-}
-
-static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
-{
-	if (dcache_status())
-		blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
-
-	bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-	/* Setup destination start address */
-	bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
-					+ (y * LCD_X_RES * LCD_PIXEL_SIZE));
-	/* Setup destination xcount */
-	bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
-	/* Setup destination xmodify */
-	bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
-
-	/* Setup destination ycount */
-	bfin_write_MDMA_D0_Y_COUNT(logo->height);
-	/* Setup destination ymodify */
-	bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
-
-
-	/* Setup Source start address */
-	bfin_write_MDMA_S0_START_ADDR(logo->data);
-	/* Setup Source xcount */
-	bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
-	/* Setup Source xmodify */
-	bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
-
-	/* Setup Source ycount */
-	bfin_write_MDMA_S0_Y_COUNT(logo->height);
-	/* Setup Source ymodify */
-	bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
-
-
-	/* Enable source DMA */
-	bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
-	SSYNC();
-	bfin_write_MDMA_D0_CONFIG(WNR | DMAEN  | WDSIZE_16 | DMA2D);
-
-	while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
-
-	bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
-	bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
-
-}
-
-int drv_video_init(void)
-{
-	int error, devices = 1;
-	struct stdio_dev videodev;
-
-	u8 *dst;
-	u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
-
-	dst = malloc(fbmem_size);
-
-	if (dst == NULL) {
-		printf("Failed to alloc FB memory\n");
-		return -1;
-	}
-
-#ifdef EASYLOGO_ENABLE_GZIP
-	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
-	unsigned long src_len = EASYLOGO_ENABLE_GZIP;
-	error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
-	bfin_logo.data = data;
-#elif defined(EASYLOGO_ENABLE_LZMA)
-	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
-	SizeT lzma_len = bfin_logo.size;
-	error = lzmaBuffToBuffDecompress(data, &lzma_len,
-		bfin_logo.data, EASYLOGO_ENABLE_LZMA);
-	bfin_logo.data = data;
-#else
-	error = 0;
-#endif
-
-	if (error) {
-		puts("Failed to decompress logo\n");
-		free(dst);
-		return -1;
-	}
-
-	memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
-
-	dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
-			(LCD_X_RES - bfin_logo.width) / 2,
-			(LCD_Y_RES - bfin_logo.height) / 2);
-
-	video_init(dst);		/* Video initialization */
-
-	memset(&videodev, 0, sizeof(videodev));
-
-	strcpy(videodev.name, "video");
-
-	error = stdio_register(&videodev);
-
-	return (error == 0) ? devices : error;
-}
diff --git a/board/bf561-acvilon/Kconfig b/board/bf561-acvilon/Kconfig
deleted file mode 100644
index ba1580d..0000000
--- a/board/bf561-acvilon/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF561_ACVILON
-
-config SYS_BOARD
-	default "bf561-acvilon"
-
-config SYS_CONFIG_NAME
-	default "bf561-acvilon"
-
-endif
diff --git a/board/bf561-acvilon/MAINTAINERS b/board/bf561-acvilon/MAINTAINERS
deleted file mode 100644
index 056ee0b..0000000
--- a/board/bf561-acvilon/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF561-ACVILON BOARD
-M:	Valentin Yakovenkov <yakovenkov@niistt.ru>
-S:	Maintained
-F:	board/bf561-acvilon/
-F:	include/configs/bf561-acvilon.h
-F:	configs/bf561-acvilon_defconfig
diff --git a/board/bf561-acvilon/Makefile b/board/bf561-acvilon/Makefile
deleted file mode 100644
index 08e2fad..0000000
--- a/board/bf561-acvilon/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2009 CJSC "NII STT", Russia, Smolensk
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf561-acvilon.o
diff --git a/board/bf561-acvilon/bf561-acvilon.c b/board/bf561-acvilon/bf561-acvilon.c
deleted file mode 100644
index da4c844..0000000
--- a/board/bf561-acvilon/bf561-acvilon.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * File:         board/bf561-acvilon/bf561-acvilon.c
- * Based on:     board/bf561-ezkit/bf561-ezkit.c
- * Author:
- *
- * Created:      2009-06-23
- * Description:  Acvilon System On Module board file
- *
- * Modified:
- *               Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
- *               Copyright (c) 2005-2008 Analog Devices Inc.
- *
- *               (C) Copyright 2000-2004
- *               Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Bugs:
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board:  CJSC \"NII STT\"-=Acvilon Platform=- [U-Boot]\n");
-	printf("       Support: http://www.niistt.ru/\n");
-	return 0;
-}
-
-#ifdef CONFIG_SMC911X
-int board_eth_init(bd_t *bis)
-{
-	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
diff --git a/board/bf561-acvilon/config.mk b/board/bf561-acvilon/config.mk
deleted file mode 100644
index 854d7db..0000000
--- a/board/bf561-acvilon/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/bf561-ezkit/Kconfig b/board/bf561-ezkit/Kconfig
deleted file mode 100644
index 495a5c5..0000000
--- a/board/bf561-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF561_EZKIT
-
-config SYS_BOARD
-	default "bf561-ezkit"
-
-config SYS_CONFIG_NAME
-	default "bf561-ezkit"
-
-endif
diff --git a/board/bf561-ezkit/MAINTAINERS b/board/bf561-ezkit/MAINTAINERS
deleted file mode 100644
index 5ced3bb..0000000
--- a/board/bf561-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF561-EZKIT BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf561-ezkit/
-F:	include/configs/bf561-ezkit.h
-F:	configs/bf561-ezkit_defconfig
diff --git a/board/bf561-ezkit/Makefile b/board/bf561-ezkit/Makefile
deleted file mode 100644
index 3d534d2..0000000
--- a/board/bf561-ezkit/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf561-ezkit.o
diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c
deleted file mode 100644
index 534c39c..0000000
--- a/board/bf561-ezkit/bf561-ezkit.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF561 EZ-Kit Lite board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
-	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk
deleted file mode 100644
index 854d7db..0000000
--- a/board/bf561-ezkit/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/bf609-ezkit/Kconfig b/board/bf609-ezkit/Kconfig
deleted file mode 100644
index 7992e1e..0000000
--- a/board/bf609-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF609_EZKIT
-
-config SYS_BOARD
-	default "bf609-ezkit"
-
-config SYS_CONFIG_NAME
-	default "bf609-ezkit"
-
-endif
diff --git a/board/bf609-ezkit/MAINTAINERS b/board/bf609-ezkit/MAINTAINERS
deleted file mode 100644
index acfc6c7..0000000
--- a/board/bf609-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF609-EZKIT BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf609-ezkit/
-F:	include/configs/bf609-ezkit.h
-F:	configs/bf609-ezkit_defconfig
diff --git a/board/bf609-ezkit/Makefile b/board/bf609-ezkit/Makefile
deleted file mode 100644
index e4184ee..0000000
--- a/board/bf609-ezkit/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf609-ezkit.o
-obj-$(CONFIG_BFIN_SOFT_SWITCH)   += soft_switch.o
diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c
deleted file mode 100644
index c993ca6..0000000
--- a/board/bf609-ezkit/bf609-ezkit.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/io.h>
-#include <asm/sdh.h>
-#include <asm/portmux.h>
-#include "soft_switch.h"
-
-int checkboard(void)
-{
-	printf("Board: ADI BF609 EZ-Kit board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	static const unsigned short pins[] = {
-		P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
-		P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
-		P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
-	};
-	peripheral_request_list(pins, "smc0");
-
-	return 0;
-}
-
-#ifdef CONFIG_ETH_DESIGNWARE
-int board_eth_init(bd_t *bis)
-{
-	int ret = 0;
-
-	if (CONFIG_DW_PORTS & 1) {
-		static const unsigned short pins[] = P_RMII0;
-		if (!peripheral_request_list(pins, "emac0"))
-			ret += designware_initialize(EMAC0_MACCFG, 0);
-	}
-	if (CONFIG_DW_PORTS & 2) {
-		static const unsigned short pins[] = P_RMII1;
-		if (!peripheral_request_list(pins, "emac1"))
-			ret += designware_initialize(EMAC1_MACCFG, 0);
-	}
-
-	return ret;
-}
-#endif
-
-#ifdef CONFIG_BFIN_SDH
-int board_mmc_init(bd_t *bis)
-{
-	return bfin_mmc_init(bis);
-}
-#endif
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-	printf("other init\n");
-	return setup_board_switches();
-}
diff --git a/board/bf609-ezkit/soft_switch.c b/board/bf609-ezkit/soft_switch.c
deleted file mode 100644
index 7c117ea..0000000
--- a/board/bf609-ezkit/soft_switch.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "soft_switch.h"
-
-struct switch_config {
-	uchar dir0; /* IODIRA */
-	uchar dir1; /* IODIRB */
-	uchar value0; /* OLATA */
-	uchar value1; /* OLATB */
-};
-
-static struct switch_config switch_config_array[NUM_SWITCH] = {
-	{
-/*
-	U45 Port A                     U45 Port B
-
-	7---------------  RMII_CLK_EN  |  7--------------- ~TEMP_THERM_EN
-	| 6------------- ~CNT0ZM_EN    |  | 6------------- ~TEMP_IRQ_EN
-	| | 5----------- ~CNT0DG_EN    |  | | 5----------- ~UART0CTS_146_EN
-	| | | 4--------- ~CNT0UD_EN    |  | | | 4--------- ~UART0CTS_RST_EN
-	| | | | 3------- ~CAN0RX_EN    |  | | | | 3------- ~UART0CTS_RTS_LPBK
-	| | | | | 2----- ~CAN0_ERR_EN  |  | | | | | 2----- ~UART0CTS_EN
-	| | | | | | 1--- ~CAN_STB      |  | | | | | | 1--- ~UART0RX_EN
-	| | | | | | | 0-  CAN_EN       |  | | | | | | | 0- ~UART0RTS_EN
-	| | | | | | | |                |  | | | | | | | |
-	O O O O O O O O                |  O O O O O O O O   (I/O direction)
-	1 0 0 0 0 0 1 1                |  1 1 1 1 1 0 0 0   (value being set)
-*/
-		.dir0 = 0x0, /* all output */
-		.dir1 = 0x0, /* all output */
-		.value0 = RMII_CLK_EN | CAN_STB | CAN_EN,
-		.value1 = TEMP_THERM_EN | TEMP_IRQ_EN | UART0CTS_146_EN
-				| UART0CTS_RST_EN | UART0CTS_RTS_LPBK,
-	},
-	{
-/*
-	U46 Port A                       U46 Port B
-
-	7--------------- ~LED4_GPIO_EN   |  7---------------  EMPTY
-	| 6------------- ~LED3_GPIO_EN   |  | 6------------- ~SPI0D3_EN
-	| | 5----------- ~LED2_GPIO_EN   |  | | 5----------- ~SPI0D2_EN
-	| | | 4--------- ~LED1_GPIO_EN   |  | | | 4--------- ~SPIFLASH_CS_EN
-	| | | | 3-------  SMC0_LP0_EN    |  | | | | 3------- ~SD_WP_EN
-	| | | | | 2-----  EMPTY          |  | | | | | 2----- ~SD_CD_EN
-	| | | | | | 1---  SMC0_EPPI2     |  | | | | | | 1--- ~PUSHBUTTON2_EN
-			  _LP1_SWITCH
-	| | | | | | | 0-  OVERRIDE_SMC0  |  | | | | | | | 0- ~PUSHBUTTON1_EN
-			  _LP0_BOOT
-	| | | | | | | |                  |  | | | | | | | |
-	O O O O O O O O                  |  O O O O O O O O   (I/O direction)
-	0 0 0 0 0 X 0 1                  |  X 0 0 0 0 0 0 0   (value being set)
-*/
-		.dir0 = 0x0, /* all output */
-		.dir1 = 0x0, /* all output */
-#ifdef CONFIG_BFIN_LINKPORT
-		.value0 = OVERRIDE_SMC0_LP0_BOOT,
-#else
-		.value0 = SMC0_EPPI2_LP1_SWITCH,
-#endif
-		.value1 = 0x0,
-	},
-	{
-/*
-	U47 Port A                         U47 Port B
-
-	7--------------- ~PD2_SPI0MISO |  7---------------  EMPTY
-			  _EI3_EN
-	| 6------------- ~PD1_SPI0D3   |  | 6-------------  EMPTY
-			  _EPPI1D17
-			  _SPI0SEL2
-			  _EI3_EN
-	| | 5----------- ~PD0_SPI0D2   |  | | 5-----------  EMPTY
-			  _EPPI1D16
-			  _SPI0SEL3
-			  _EI3_EN
-	| | | 4--------- ~WAKE_PUSH    |  | | | 4---------  EMPTY
-			  BUTTON_EN
-	| | | | 3------- ~ETHERNET_EN  |  | | | | 3-------  EMPTY
-	| | | | | 2-----  PHYAD0       |  | | | | | 2-----  EMPTY
-	| | | | | | 1---  PHY_PWR      |  | | | | | | 1--- ~PD4_SPI0CK_EI3_EN
-			  _DWN_INT
-	| | | | | | | 0- ~PHYINT_EN    |  | | | | | | | 0- ~PD3_SPI0MOSI_EI3_EN
-	| | | | | | | |                |  | | | | | | | |
-	O O O O O I I O                |  O O O O O O O O   (I/O direction)
-	1 1 1 0 0 0 0 0                |  X X X X X X 1 1   (value being set)
-*/
-		.dir0 = 0x6, /* bits 1 and 2 input, all others output */
-		.dir1 = 0x0, /* all output */
-		.value0 = PD1_SPI0D3_EN | PD0_SPI0D2_EN,
-		.value1 = 0,
-	},
-};
-
-static int setup_soft_switch(int addr, struct switch_config *config)
-{
-	int ret = 0;
-
-	ret = i2c_write(addr, OLATA, 1, &config->value0, 1);
-	if (ret)
-		return ret;
-	ret = i2c_write(addr, OLATB, 1, &config->value1, 1);
-	if (ret)
-		return ret;
-
-	ret = i2c_write(addr, IODIRA, 1, &config->dir0, 1);
-	if (ret)
-		return ret;
-	return i2c_write(addr, IODIRB, 1, &config->dir1, 1);
-}
-
-int config_switch_bit(int addr, int port, int bit, int dir, uchar value)
-{
-	int ret, data_reg, dir_reg;
-	uchar tmp;
-
-	if (port == IO_PORT_A) {
-		data_reg = OLATA;
-		dir_reg = IODIRA;
-	} else {
-		data_reg = OLATB;
-		dir_reg = IODIRB;
-	}
-
-	if (dir == IO_PORT_INPUT) {
-		ret = i2c_read(addr, dir_reg, 1, &tmp, 1);
-		if (ret)
-			return ret;
-		tmp |= bit;
-		return i2c_write(addr, dir_reg, 1, &tmp, 1);
-	} else {
-		ret = i2c_read(addr, data_reg, 1, &tmp, 1);
-		if (ret)
-			return ret;
-		if (value)
-			tmp |= bit;
-		else
-			tmp &= ~bit;
-		ret = i2c_write(addr, data_reg, 1, &tmp, 1);
-		if (ret)
-			return ret;
-		ret = i2c_read(addr, dir_reg, 1, &tmp, 1);
-		if (ret)
-			return ret;
-		tmp &= ~bit;
-		return i2c_write(addr, dir_reg, 1, &tmp, 1);
-	}
-}
-
-int setup_board_switches(void)
-{
-	int ret;
-	int i;
-
-	for (i = 0; i < NUM_SWITCH; i++) {
-		ret = setup_soft_switch(SWITCH_ADDR + i,
-				&switch_config_array[i]);
-		if (ret)
-			return ret;
-	}
-	return 0;
-}
diff --git a/board/bf609-ezkit/soft_switch.h b/board/bf609-ezkit/soft_switch.h
deleted file mode 100644
index 75d64e2..0000000
--- a/board/bf609-ezkit/soft_switch.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BOARD_SOFT_SWITCH_H__
-#define __BOARD_SOFT_SWITCH_H__
-
-#include <asm/soft_switch.h>
-
-/* switch 0 port A */
-#define CAN_EN                 0x1
-#define CAN_STB                0x2
-#define CAN0_ERR_EN            0x4
-#define CAN0RX_EN              0x8
-#define CNT0UD_EN              0x10
-#define CNT0DG_EN              0x20
-#define CNT0ZM_EN              0x40
-#define RMII_CLK_EN            0x80
-
-/* switch 0 port B */
-#define UART0RTS_EN            0x1
-#define UART0RX_EN             0x2
-#define UART0CTS_EN            0x4
-#define UART0CTS_RTS_LPBK      0x8
-#define UART0CTS_RST_EN        0x10
-#define UART0CTS_146_EN        0x20
-#define TEMP_IRQ_EN            0x40
-#define TEMP_THERM_EN          0x80
-
-/* switch 1 port A */
-#define OVERRIDE_SMC0_LP0_BOOT 0x1
-#define SMC0_EPPI2_LP1_SWITCH  0x2
-#define SMC0_LP0_EN            0x8
-#define LED1_GPIO_EN           0x10
-#define LED2_GPIO_EN           0x20
-#define LED3_GPIO_EN           0x40
-#define LED4_GPIO_EN           0x80
-
-/* switch 1 port B */
-#define PUSHBUTTON1_EN         0x1
-#define PUSHBUTTON2_EN         0x2
-#define SD_CD_EN               0x4
-#define SD_WP_EN               0x8
-#define SPIFLASH_CS_EN         0x10
-#define SPI0D2_EN              0x20
-#define SPI0D3_EN              0x40
-
-/* switch 2 port A */
-#define PHYINT_EN              0x1
-#define PHY_PWR_DWN_INT        0x2
-#define PHYAD0                 0x4
-#define ETHERNET_EN            0x8
-#define WAKE_PUSHBUTTON_EN     0x10
-#define PD0_SPI0D2_EN          0x20
-#define PD1_SPI0D3_EN          0x40
-#define PD2_SPI0MISO_EN        0x80
-
-/* switch 2 port B */
-#define PD3_SPI0MOSI_EN        0x1
-#define PD4_SPI0CK_EN          0x2
-
-#ifdef CONFIG_BFIN_BOARD_VERSION_1_0
-#define SWITCH_ADDR     0x21
-#else
-#define SWITCH_ADDR     0x20
-#endif
-
-#define NUM_SWITCH      3
-#define IODIRA          0x0
-#define IODIRB          0x1
-#define OLATA           0x14
-#define OLATB           0x15
-
-int setup_board_switches(void);
-
-#endif /* __BOARD_SOFT_SWITCH_H__ */
diff --git a/board/blackstamp/Kconfig b/board/blackstamp/Kconfig
deleted file mode 100644
index 7ce086a..0000000
--- a/board/blackstamp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BLACKSTAMP
-
-config SYS_BOARD
-	default "blackstamp"
-
-config SYS_CONFIG_NAME
-	default "blackstamp"
-
-endif
diff --git a/board/blackstamp/MAINTAINERS b/board/blackstamp/MAINTAINERS
deleted file mode 100644
index a0d72c6..0000000
--- a/board/blackstamp/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-BLACKSTAMP BOARD
-M:	Wojtek Skulski <skulski@pas.rochester.edu>
-M:	Wojtek Skulski <info@skutek.com>
-M:	Benjamin Matthews <mben12@gmail.com>
-S:	Maintained
-F:	board/blackstamp/
-F:	include/configs/blackstamp.h
-F:	configs/blackstamp_defconfig
diff --git a/board/blackstamp/Makefile b/board/blackstamp/Makefile
deleted file mode 100644
index 2ae79da..0000000
--- a/board/blackstamp/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= blackstamp.o
diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c
deleted file mode 100644
index d233b8a..0000000
--- a/board/blackstamp/blackstamp.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * U-Boot - blackstamp.c BlackStamp board specific routines
- * Most code stolen from boards/bf533-stamp/bf533-stamp.c
- * Edited to the BlackStamp by Ben Matthews for UR LLE
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: BlackStamp\n");
-	printf("Support: http://blackfin.uclinux.org/gf/project/blackstamp/\n");
-	return 0;
-}
-
-#ifdef SHARED_RESOURCES
-void swap_to(int device_id)
-{
-	gpio_request(GPIO_PF0, "eth_flash_swap");
-	gpio_direction_output(GPIO_PF0, device_id == ETHERNET);
-	SSYNC();
-}
-#endif
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
-	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/blackvme/Kconfig b/board/blackvme/Kconfig
deleted file mode 100644
index 5e73f84..0000000
--- a/board/blackvme/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BLACKVME
-
-config SYS_BOARD
-	default "blackvme"
-
-config SYS_CONFIG_NAME
-	default "blackvme"
-
-endif
diff --git a/board/blackvme/MAINTAINERS b/board/blackvme/MAINTAINERS
deleted file mode 100644
index 3f8b32c..0000000
--- a/board/blackvme/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-BLACKVME BOARD
-M:	Wojtek Skulski <skulski@pas.rochester.edu>
-M:	Wojtek Skulski <info@skutek.com>
-M:	Benjamin Matthews <mben12@gmail.com>
-S:	Maintained
-F:	board/blackvme/
-F:	include/configs/blackvme.h
-F:	configs/blackvme_defconfig
diff --git a/board/blackvme/Makefile b/board/blackvme/Makefile
deleted file mode 100644
index 9a61775..0000000
--- a/board/blackvme/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= blackvme.o
diff --git a/board/blackvme/blackvme.c b/board/blackvme/blackvme.c
deleted file mode 100644
index d8932ed..0000000
--- a/board/blackvme/blackvme.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* U-Boot - blackvme.c  board specific routines
- * (c) Wojtek Skulski 2010 info@skutek.com
- * Board info: http://www.skutek.com
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
-	printf("Board: BlackVME\n");
-	printf("Support: http://www.skutek.com/\n");
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_AX88180
-/*
- * The ax88180 driver had to be patched to work around a bug
- * in Marvell 88E1111 B2 silicon. E-mail me for explanations.
- */
-int board_eth_init(bd_t *bis)
-{
-	return ax88180_initialize(bis);
-}
-#endif	/* CONFIG_DRIVER_AX88180 */
diff --git a/board/br4/Kconfig b/board/br4/Kconfig
deleted file mode 100644
index a10a060..0000000
--- a/board/br4/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BR4
-
-config SYS_BOARD
-	default "br4"
-
-config SYS_CONFIG_NAME
-	default "br4"
-
-endif
diff --git a/board/br4/MAINTAINERS b/board/br4/MAINTAINERS
deleted file mode 100644
index 4085da5..0000000
--- a/board/br4/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BR4 BOARD
-M:	Dimitar Penev <dpn@switchfin.org>
-S:	Maintained
-F:	board/br4/
-F:	include/configs/br4.h
-F:	configs/br4_defconfig
diff --git a/board/br4/Makefile b/board/br4/Makefile
deleted file mode 100644
index c6c03ab..0000000
--- a/board/br4/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) Switchfin Org. <dpn@switchfin.org>
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= br4.o
diff --git a/board/br4/br4.c b/board/br4/br4.c
deleted file mode 100644
index 6f3f170..0000000
--- a/board/br4/br4.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) Switchfin Org. <dpn@switchfin.org>
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
-	printf("Board: Switchvoice BR4 Appliance\n");
-	printf("       Support: http://www.switchvoice.com/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/broadcom/bcm23550_w1d/bcm23550_w1d.c b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
index 533e99e..5f4c634 100644
--- a/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
+++ b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
@@ -62,10 +62,12 @@ int dram_init(void)
 }
 
 /* This is called after dram_init() so use get_ram_size result */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 #ifdef CONFIG_MMC_SDHCI_KONA
diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c
index b868812..f5b94f6 100644
--- a/board/broadcom/bcm28155_ap/bcm28155_ap.c
+++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c
@@ -69,10 +69,12 @@ int dram_init(void)
 }
 
 /* This is called after dram_init() so use get_ram_size result */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 #ifdef CONFIG_MMC_SDHCI_KONA
diff --git a/board/broadcom/bcm958712k/MAINTAINERS b/board/broadcom/bcm958712k/MAINTAINERS
new file mode 100644
index 0000000..024fb14
--- /dev/null
+++ b/board/broadcom/bcm958712k/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM958712K BOARD
+M:	Jon Mason <jon.mason@broadcom.com>
+S:	Maintained
+F:	board/broadcom/bcmns2/
+F:	include/configs/bcm_northstar2.h
+F:	configs/bcm958712k_defconfig
diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c
index c28b203..a409622 100644
--- a/board/broadcom/bcm_ep/board.c
+++ b/board/broadcom/bcm_ep/board.c
@@ -37,10 +37,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 int board_early_init_f(void)
diff --git a/board/broadcom/bcmns2/Kconfig b/board/broadcom/bcmns2/Kconfig
new file mode 100644
index 0000000..3ac6724
--- /dev/null
+++ b/board/broadcom/bcmns2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BCMNS2
+
+config SYS_BOARD
+	default "bcmns2"
+
+config SYS_VENDOR
+	default "broadcom"
+
+config SYS_SOC
+	default "ns2"
+
+config SYS_CONFIG_NAME
+	default "bcm_northstar2"
+
+endif
diff --git a/board/broadcom/bcmns2/Makefile b/board/broadcom/bcmns2/Makefile
new file mode 100644
index 0000000..f6ddd80
--- /dev/null
+++ b/board/broadcom/bcmns2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Broadcom Ltd.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= northstar2.o
diff --git a/board/broadcom/bcmns2/northstar2.c b/board/broadcom/bcmns2/northstar2.c
new file mode 100644
index 0000000..10279a5
--- /dev/null
+++ b/board/broadcom/bcmns2/northstar2.c
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2016 Broadcom Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region ns2_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0xff80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = ns2_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+				    PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE);
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset();
+}
diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c
index 5899aa6..39b9b12 100644
--- a/board/cadence/xtfpga/xtfpga.c
+++ b/board/cadence/xtfpga/xtfpga.c
@@ -48,10 +48,12 @@ int checkboard(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
 	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 int board_postclk_init(void)
diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c
index 15c934d..54de0e2 100644
--- a/board/canmb/canmb.c
+++ b/board/canmb/canmb.c
@@ -18,6 +18,8 @@
 #include "mt48lc16m32s2-75.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
@@ -60,12 +62,12 @@ static void sdram_start (int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
@@ -163,7 +165,9 @@ phys_size_t initdram (int board_type)
 
 #endif /* CONFIG_SYS_RAMBOOT */
 
-	return dramsize + dramsize2;
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
 }
 
 int checkboard (void)
diff --git a/board/cirrus/edb93xx/edb93xx.c b/board/cirrus/edb93xx/edb93xx.c
index 51ff162..720b490 100644
--- a/board/cirrus/edb93xx/edb93xx.c
+++ b/board/cirrus/edb93xx/edb93xx.c
@@ -216,9 +216,11 @@ static unsigned dram_init_banksize_int(int print)
 	return dram_total;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	dram_init_banksize_int(0);
+
+	return 0;
 }
 
 /* called in board_init_f (before relocation) */
diff --git a/board/cm-bf527/Kconfig b/board/cm-bf527/Kconfig
deleted file mode 100644
index 8d14179..0000000
--- a/board/cm-bf527/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF527
-
-config SYS_BOARD
-	default "cm-bf527"
-
-config SYS_CONFIG_NAME
-	default "cm-bf527"
-
-endif
diff --git a/board/cm-bf527/MAINTAINERS b/board/cm-bf527/MAINTAINERS
deleted file mode 100644
index fefcfcf..0000000
--- a/board/cm-bf527/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF527 BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/cm-bf527/
-F:	include/configs/cm-bf527.h
-F:	configs/cm-bf527_defconfig
diff --git a/board/cm-bf527/Makefile b/board/cm-bf527/Makefile
deleted file mode 100644
index 1d662c6..0000000
--- a/board/cm-bf527/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm-bf527.o gpio_cfi_flash.o
diff --git a/board/cm-bf527/cm-bf527.c b/board/cm-bf527/cm-bf527.c
deleted file mode 100644
index 0c2138b..0000000
--- a/board/cm-bf527/cm-bf527.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/otp.h>
-#include "../cm-bf537e/gpio_cfi_flash.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix CM-BF527 board\n");
-	printf("       Support: http://www.bluetechnix.at/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
-	/* the MAC is stored in OTP memory page 0xDF */
-	uint32_t ret;
-	uint64_t otp_mac;
-
-	ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
-	if (!(ret & OTP_MASTER_ERROR)) {
-		uchar *otp_mac_p = (uchar *)&otp_mac;
-
-		for (ret = 0; ret < 6; ++ret)
-			mac_addr[ret] = otp_mac_p[5 - ret];
-
-		if (is_valid_ethaddr(mac_addr))
-			eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
-
-	gpio_cfi_flash_init();
-
-	return 0;
-}
diff --git a/board/cm-bf527/gpio_cfi_flash.c b/board/cm-bf527/gpio_cfi_flash.c
deleted file mode 100644
index 6e62fff..0000000
--- a/board/cm-bf527/gpio_cfi_flash.c
+++ /dev/null
@@ -1,3 +0,0 @@
-#define GPIO_PIN_1 GPIO_PH9
-#define GPIO_PIN_2 GPIO_PG11
-#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/cm-bf533/Kconfig b/board/cm-bf533/Kconfig
deleted file mode 100644
index cedd752..0000000
--- a/board/cm-bf533/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF533
-
-config SYS_BOARD
-	default "cm-bf533"
-
-config SYS_CONFIG_NAME
-	default "cm-bf533"
-
-endif
diff --git a/board/cm-bf533/MAINTAINERS b/board/cm-bf533/MAINTAINERS
deleted file mode 100644
index 0bf51fb..0000000
--- a/board/cm-bf533/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF533 BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/cm-bf533/
-F:	include/configs/cm-bf533.h
-F:	configs/cm-bf533_defconfig
diff --git a/board/cm-bf533/Makefile b/board/cm-bf533/Makefile
deleted file mode 100644
index 41e100d..0000000
--- a/board/cm-bf533/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm-bf533.o
diff --git a/board/cm-bf533/cm-bf533.c b/board/cm-bf533/cm-bf533.c
deleted file mode 100644
index 02ef076..0000000
--- a/board/cm-bf533/cm-bf533.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix CM-BF533 board\n");
-	printf("       Support: http://www.bluetechnix.at/\n");
-	return 0;
-}
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
-	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk
deleted file mode 100644
index 7f9138b..0000000
--- a/board/cm-bf533/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537e/Kconfig b/board/cm-bf537e/Kconfig
deleted file mode 100644
index af2e548..0000000
--- a/board/cm-bf537e/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF537E
-
-config SYS_BOARD
-	default "cm-bf537e"
-
-config SYS_CONFIG_NAME
-	default "cm-bf537e"
-
-endif
diff --git a/board/cm-bf537e/MAINTAINERS b/board/cm-bf537e/MAINTAINERS
deleted file mode 100644
index 63d2428..0000000
--- a/board/cm-bf537e/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF537E BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/cm-bf537e/
-F:	include/configs/cm-bf537e.h
-F:	configs/cm-bf537e_defconfig
diff --git a/board/cm-bf537e/Makefile b/board/cm-bf537e/Makefile
deleted file mode 100644
index 317098c..0000000
--- a/board/cm-bf537e/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm-bf537e.o gpio_cfi_flash.o
diff --git a/board/cm-bf537e/cm-bf537e.c b/board/cm-bf537e/cm-bf537e.c
deleted file mode 100644
index 7e4cfc2..0000000
--- a/board/cm-bf537e/cm-bf537e.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include "gpio_cfi_flash.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix CM-BF537E board\n");
-	printf("       Support: http://www.bluetechnix.at/\n");
-	return 0;
-}
-
-#ifndef CONFIG_BFIN_MAC
-# define bfin_EMAC_initialize(x) 1
-#endif
-#ifndef CONFIG_SMC911X
-# define smc911x_initialize(n, x) 1
-#endif
-int board_eth_init(bd_t *bis)
-{
-	/* return ok if at least 1 eth device works */
-	return bfin_EMAC_initialize(bis) &
-	       smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-
-int misc_init_r(void)
-{
-	gpio_cfi_flash_init();
-
-	return 0;
-}
diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk
deleted file mode 100644
index 7f9138b..0000000
--- a/board/cm-bf537e/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537e/gpio_cfi_flash.c b/board/cm-bf537e/gpio_cfi_flash.c
deleted file mode 100644
index 1075cc4..0000000
--- a/board/cm-bf537e/gpio_cfi_flash.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
- *
- * Copyright (c) 2009-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include "gpio_cfi_flash.h"
-
-/* Allow this driver to be shared among boards */
-#ifndef GPIO_PIN_1
-#define GPIO_PIN_1  GPIO_PF4
-#endif
-#define GPIO_MASK_1 (1 << 21)
-#ifndef GPIO_PIN_2
-#define GPIO_MASK_2 (0)
-#else
-#define GPIO_MASK_2 (1 << 22)
-#endif
-#ifndef GPIO_PIN_3
-#define GPIO_MASK_3 (0)
-#else
-#define GPIO_MASK_3 (1 << 23)
-#endif
-#define GPIO_MASK   (GPIO_MASK_1 | GPIO_MASK_2 | GPIO_MASK_3)
-
-void *gpio_cfi_flash_swizzle(void *vaddr)
-{
-	unsigned long addr = (unsigned long)vaddr;
-
-	gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
-
-#ifdef GPIO_PIN_2
-	gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
-#endif
-
-#ifdef GPIO_PIN_3
-	gpio_set_value(GPIO_PIN_3, addr & GPIO_MASK_3);
-#endif
-
-	SSYNC();
-	udelay(1);
-
-	return (void *)(addr & ~GPIO_MASK);
-}
-
-#define __raw_writeq(value, addr) *(volatile u64 *)addr = value
-#define __raw_readq(addr) *(volatile u64 *)addr
-
-#define MAKE_FLASH(size, sfx) \
-void flash_write##size(u##size value, void *addr) \
-{ \
-	__raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \
-} \
-u##size flash_read##size(void *addr) \
-{ \
-	return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \
-}
-MAKE_FLASH(8, b)  /* flash_write8()  flash_read8() */
-MAKE_FLASH(16, w) /* flash_write16() flash_read16() */
-MAKE_FLASH(32, l) /* flash_write32() flash_read32() */
-MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
-
-void gpio_cfi_flash_init(void)
-{
-	gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
-	gpio_direction_output(GPIO_PIN_1, 0);
-#ifdef GPIO_PIN_2
-	gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
-	gpio_direction_output(GPIO_PIN_2, 0);
-#endif
-#ifdef GPIO_PIN_3
-	gpio_request(GPIO_PIN_3, "gpio_cfi_flash");
-	gpio_direction_output(GPIO_PIN_3, 0);
-#endif
-}
diff --git a/board/cm-bf537e/gpio_cfi_flash.h b/board/cm-bf537e/gpio_cfi_flash.h
deleted file mode 100644
index 5211e97..0000000
--- a/board/cm-bf537e/gpio_cfi_flash.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
- *
- * Copyright (c) 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-void *gpio_cfi_flash_swizzle(void *vaddr);
-void gpio_cfi_flash_init(void);
diff --git a/board/cm-bf537u/Kconfig b/board/cm-bf537u/Kconfig
deleted file mode 100644
index baf9e8c..0000000
--- a/board/cm-bf537u/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF537U
-
-config SYS_BOARD
-	default "cm-bf537u"
-
-config SYS_CONFIG_NAME
-	default "cm-bf537u"
-
-endif
diff --git a/board/cm-bf537u/MAINTAINERS b/board/cm-bf537u/MAINTAINERS
deleted file mode 100644
index a89cfca..0000000
--- a/board/cm-bf537u/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF537U BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/cm-bf537u/
-F:	include/configs/cm-bf537u.h
-F:	configs/cm-bf537u_defconfig
diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile
deleted file mode 100644
index 835d5b7..0000000
--- a/board/cm-bf537u/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm-bf537u.o gpio_cfi_flash.o
diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c
deleted file mode 100644
index aad72a9..0000000
--- a/board/cm-bf537u/cm-bf537u.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include "../cm-bf537e/gpio_cfi_flash.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix CM-BF537U board\n");
-	printf("       Support: http://www.bluetechnix.at/\n");
-	return 0;
-}
-
-#ifndef CONFIG_BFIN_MAC
-# define bfin_EMAC_initialize(x) 1
-#endif
-#ifndef CONFIG_SMC911X
-# define smc911x_initialize(n, x) 1
-#endif
-int board_eth_init(bd_t *bis)
-{
-	/* return ok if at least 1 eth device works */
-	return bfin_EMAC_initialize(bis) &
-	       smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-
-int misc_init_r(void)
-{
-	gpio_cfi_flash_init();
-
-	return 0;
-}
diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk
deleted file mode 100644
index 7f9138b..0000000
--- a/board/cm-bf537u/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537u/gpio_cfi_flash.c b/board/cm-bf537u/gpio_cfi_flash.c
deleted file mode 100644
index ef5ea8b..0000000
--- a/board/cm-bf537u/gpio_cfi_flash.c
+++ /dev/null
@@ -1,2 +0,0 @@
-#define GPIO_PIN_1 GPIO_PH0
-#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/cm-bf548/Kconfig b/board/cm-bf548/Kconfig
deleted file mode 100644
index b96cb5f..0000000
--- a/board/cm-bf548/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF548
-
-config SYS_BOARD
-	default "cm-bf548"
-
-config SYS_CONFIG_NAME
-	default "cm-bf548"
-
-endif
diff --git a/board/cm-bf548/MAINTAINERS b/board/cm-bf548/MAINTAINERS
deleted file mode 100644
index b7f5779..0000000
--- a/board/cm-bf548/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF548 BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/cm-bf548/
-F:	include/configs/cm-bf548.h
-F:	configs/cm-bf548_defconfig
diff --git a/board/cm-bf548/Makefile b/board/cm-bf548/Makefile
deleted file mode 100644
index 1e11b8c..0000000
--- a/board/cm-bf548/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm-bf548.o
-obj-$(CONFIG_VIDEO)      += video.o
diff --git a/board/cm-bf548/cm-bf548.c b/board/cm-bf548/cm-bf548.c
deleted file mode 100644
index d9d018b..0000000
--- a/board/cm-bf548/cm-bf548.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix CM-BF548 board\n");
-	printf("       Support: http://www.bluetechnix.at/\n");
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	/* Set async addr lines as peripheral */
-	const unsigned short pins[] = {
-		P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
-		P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
-		P_A21, P_A22, P_A23, P_A24, 0
-	};
-	return peripheral_request_list(pins, "async");
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC911X
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
-	return rc;
-}
diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk
deleted file mode 100644
index beb9834..0000000
--- a/board/cm-bf548/config.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA       := --dma 6
-LDR_FLAGS-BFIN_BOOT_FIFO       := --dma 1
-LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
-LDR_FLAGS-BFIN_BOOT_UART       := --dma 1
diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c
deleted file mode 100644
index b8cc873..0000000
--- a/board/cm-bf548/video.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * video.c - run splash screen on lcd
- *
- * Copyright (c) 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/dma.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-
-#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDec.h>
-#include <lzma/LzmaTools.h>
-
-#define DMA_SIZE16	2
-
-#include <asm/mach-common/bits/eppi.h>
-
-#include EASYLOGO_HEADER
-
-#define LCD_X_RES		480	/*Horizontal Resolution */
-#define LCD_Y_RES		272	/* Vertical Resolution */
-
-#define LCD_BPP			24	/* Bit Per Pixel */
-#define LCD_PIXEL_SIZE		(LCD_BPP / 8)
-#define	DMA_BUS_SIZE		32
-#define ACTIVE_VIDEO_MEM_OFFSET 0
-
-/* 	-- Horizontal synchronizing --
- *
- * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
- * (LCY-W-06602A Page 9 of 22)
- *
- * Clock Frequency 	1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
- *
- * Period 		TH - 525 - Clock
- * Pulse width 		THp - 41 - Clock
- * Horizontal period 	THd - 480 - Clock
- * Back porch 		THb - 2 - Clock
- * Front porch 		THf - 2 - Clock
- *
- * -- Vertical synchronizing --
- * Period 		TV - 286 - Line
- * Pulse width 		TVp - 10 - Line
- * Vertical period 	TVd - 272 - Line
- * Back porch 		TVb - 2 - Line
- * Front porch 		TVf - 2 - Line
- */
-
-#define	LCD_CLK         	(8*1000*1000)	/* 8MHz */
-
-/* # active data to transfer after Horizontal Delay clock */
-#define EPPI_HCOUNT		LCD_X_RES
-
-/* # active lines to transfer after Vertical Delay clock */
-#define EPPI_VCOUNT		LCD_Y_RES
-
-/* Samples per Line = 480 (active data) + 45 (padding) */
-#define EPPI_LINE		525
-
-/* Lines per Frame = 272 (active data) + 14 (padding) */
-#define EPPI_FRAME		286
-
-/* FS1 (Hsync) Width (Typical)*/
-#define EPPI_FS1W_HBL		41
-
-/* FS1 (Hsync) Period (Typical) */
-#define EPPI_FS1P_AVPL		EPPI_LINE
-
-/* Horizontal Delay clock after assertion of Hsync (Typical) */
-#define EPPI_HDELAY		43
-
-/* FS2 (Vsync) Width    = FS1 (Hsync) Period * 10 */
-#define EPPI_FS2W_LVB		(EPPI_LINE * 10)
-
- /* FS2 (Vsync) Period   = FS1 (Hsync) Period * Lines per Frame */
-#define EPPI_FS2P_LAVF		(EPPI_LINE * EPPI_FRAME)
-
-/* Vertical Delay after assertion of Vsync (2 Lines) */
-#define EPPI_VDELAY		12
-
-#define EPPI_CLIP		0xFF00FF00
-
-/* EPPI Control register configuration value for RGB out
- * - EPPI as Output
- * GP 2 frame sync mode,
- * Internal Clock generation disabled, Internal FS generation enabled,
- * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
- * FS1 & FS2 are active high,
- * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
- * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
- * Swapping Enabled,
- * One (DMA) Channel Mode,
- * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
- * Regular watermark - when FIFO is 100% full,
- * Urgent watermark - when FIFO is 75% full
- */
-
-#define EPPI_CONTROL		(0x20136E2E)
-
-static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
-{
-	u32 sclk = get_sclk();
-
-	/* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
-
-	return (((sclk / target_ppi_clk) / 2) - 1);
-}
-
-void Init_PPI(void)
-{
-	u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
-
-	bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
-	bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
-	bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
-	bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
-	bfin_write_EPPI0_CLIP(EPPI_CLIP);
-
-	bfin_write_EPPI0_FRAME(EPPI_FRAME);
-	bfin_write_EPPI0_LINE(EPPI_LINE);
-
-	bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
-	bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
-	bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
-	bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
-
-	bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
-
-/*
- * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
- * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
- */
-#if defined(CONFIG_VIDEO_RGB666)
-	bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
-				 RGB_FMT_EN);
-#else
-	bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
-				 ~RGB_FMT_EN);
-#endif
-
-}
-
-#define               DEB2_URGENT  0x2000	/* DEB2 Urgent */
-
-void Init_DMA(void *dst)
-{
-#if defined(CONFIG_DEB_DMA_URGENT)
-	bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
-#endif
-
-	bfin_write_DMA12_START_ADDR(dst);
-
-	/* X count */
-	bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
-	bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
-
-	/* Y count */
-	bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
-	bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
-
-	/* DMA Config */
-	bfin_write_DMA12_CONFIG(
-	    WDSIZE_32 |	/* 32 bit DMA */
-	    DMA2D |		/* 2D DMA */
-	    FLOW_AUTO		/* autobuffer mode */
-	);
-}
-
-void Init_Ports(void)
-{
-	const unsigned short pins[] = {
-		P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
-		P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
-		P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
-		P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
-#if !defined(CONFIG_VIDEO_RGB666)
-		P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
-		P_PPI0_D23,
-#endif
-		P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
-	};
-	peripheral_request_list(pins, "lcd");
-
-	gpio_request(GPIO_PE3, "lcd-disp");
-	gpio_direction_output(GPIO_PE3, 1);
-}
-
-void EnableDMA(void)
-{
-	bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
-}
-
-void DisableDMA(void)
-{
-	bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
-}
-
-/* enable and disable PPI functions */
-void EnablePPI(void)
-{
-	bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
-}
-
-void DisablePPI(void)
-{
-	bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
-}
-
-int video_init(void *dst)
-{
-	Init_Ports();
-	Init_DMA(dst);
-	EnableDMA();
-	Init_PPI();
-	EnablePPI();
-
-	return 0;
-}
-
-void video_stop(void)
-{
-	DisablePPI();
-	DisableDMA();
-}
-
-static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
-{
-	if (dcache_status())
-		blackfin_dcache_flush_range(logo->data,
-					    logo->data + logo->size);
-
-	bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-	/* Setup destination start address */
-	bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
-				      + (y * LCD_X_RES * LCD_PIXEL_SIZE));
-	/* Setup destination xcount */
-	bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
-	/* Setup destination xmodify */
-	bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
-
-	/* Setup destination ycount */
-	bfin_write_MDMA_D0_Y_COUNT(logo->height);
-	/* Setup destination ymodify */
-	bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE +
-				    DMA_SIZE16);
-
-	/* Setup Source start address */
-	bfin_write_MDMA_S0_START_ADDR(logo->data);
-	/* Setup Source xcount */
-	bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
-	/* Setup Source xmodify */
-	bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
-
-	/* Setup Source ycount */
-	bfin_write_MDMA_S0_Y_COUNT(logo->height);
-	/* Setup Source ymodify */
-	bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
-
-	/* Enable source DMA */
-	bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
-	SSYNC();
-	bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
-
-	while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) ;
-
-	bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE
-				      | DMA_ERR);
-	bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE
-				      | DMA_ERR);
-
-}
-
-int drv_video_init(void)
-{
-	int error, devices = 1;
-	struct stdio_dev videodev;
-
-	u8 *dst;
-	u32 fbmem_size =
-	    LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
-
-	dst = malloc(fbmem_size);
-
-	if (dst == NULL) {
-		printf("Failed to alloc FB memory\n");
-		return -1;
-	}
-
-#ifdef EASYLOGO_ENABLE_GZIP
-	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
-	unsigned long src_len = EASYLOGO_ENABLE_GZIP;
-	error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
-	bfin_logo.data = data;
-#elif defined(EASYLOGO_ENABLE_LZMA)
-	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
-	SizeT lzma_len = bfin_logo.size;
-	error = lzmaBuffToBuffDecompress(data, &lzma_len,
-		bfin_logo.data, EASYLOGO_ENABLE_LZMA);
-	bfin_logo.data = data;
-#else
-	error = 0;
-#endif
-
-	if (error) {
-		puts("Failed to decompress logo\n");
-		free(dst);
-		return -1;
-	}
-
-	memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0],
-	       fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
-
-	dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
-		    (LCD_X_RES - bfin_logo.width) / 2,
-		    (LCD_Y_RES - bfin_logo.height) / 2);
-
-	video_init(dst);	/* Video initialization */
-
-	memset(&videodev, 0, sizeof(videodev));
-
-	strcpy(videodev.name, "video");
-
-	error = stdio_register(&videodev);
-
-	return (error == 0) ? devices : error;
-}
diff --git a/board/cm-bf561/Kconfig b/board/cm-bf561/Kconfig
deleted file mode 100644
index 8b302a5..0000000
--- a/board/cm-bf561/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF561
-
-config SYS_BOARD
-	default "cm-bf561"
-
-config SYS_CONFIG_NAME
-	default "cm-bf561"
-
-endif
diff --git a/board/cm-bf561/MAINTAINERS b/board/cm-bf561/MAINTAINERS
deleted file mode 100644
index 9c86c8d..0000000
--- a/board/cm-bf561/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF561 BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/cm-bf561/
-F:	include/configs/cm-bf561.h
-F:	configs/cm-bf561_defconfig
diff --git a/board/cm-bf561/Makefile b/board/cm-bf561/Makefile
deleted file mode 100644
index e0f0c34..0000000
--- a/board/cm-bf561/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm-bf561.o
diff --git a/board/cm-bf561/cm-bf561.c b/board/cm-bf561/cm-bf561.c
deleted file mode 100644
index 99b7eb2..0000000
--- a/board/cm-bf561/cm-bf561.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix CM-BF561 core module\n");
-	printf("       Support: http://www.bluetechnix.at/\n");
-	return 0;
-}
-
-#ifdef CONFIG_SMC911X
-int board_eth_init(bd_t *bis)
-{
-	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk
deleted file mode 100644
index 854d7db..0000000
--- a/board/cm-bf561/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
index fce998d..7b86235 100644
--- a/board/cm5200/cm5200.c
+++ b/board/cm5200/cm5200.c
@@ -97,14 +97,14 @@ static mem_conf_t* get_mem_config(int board_type)
 /*
  * Initalize SDRAM - configure SDRAM controller, detect memory size.
  */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 #ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 	mem_conf_t *mem_conf;
 
-	mem_conf = get_mem_config(board_type);
+	mem_conf = get_mem_config(gd->board_type);
 
 	/* configure SDRAM start/end for detection */
 	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
@@ -150,7 +150,9 @@ phys_size_t initdram(int board_type)
 	*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
 	__asm__ volatile ("sync");
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 }
 
 
diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c
index 0f3bcc5..0ceaa1f 100644
--- a/board/cobra5272/cobra5272.c
+++ b/board/cobra5272/cobra5272.c
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <asm/immap.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard (void)
 {
@@ -16,7 +17,7 @@ int checkboard (void)
 	return 0;
 };
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
 
@@ -26,7 +27,9 @@ phys_size_t initdram (int board_type)
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *) 0) = 0;
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 };
 
 int testdram (void)
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 5b88bcc..80b5dc9 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -688,7 +688,7 @@ int misc_init_r(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
@@ -720,6 +720,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[1].size = 0x7FF00000;
 		break;
 	}
+
+	return 0;
 }
 
 int dram_init(void)
diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
index 1b6c40f..e3441ca 100644
--- a/board/davedenx/aria/aria.c
+++ b/board/davedenx/aria/aria.c
@@ -18,9 +18,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
-	return fixed_sdram(NULL, NULL, 0);
+	gd->ram_size = fixed_sdram(NULL, NULL, 0);
+
+	return 0;
 }
 
 int misc_init_r(void)
diff --git a/board/davinci/da8xxevm/README.da850 b/board/davinci/da8xxevm/README.da850
index 29cb4ec..519267e 100644
--- a/board/davinci/da8xxevm/README.da850
+++ b/board/davinci/da8xxevm/README.da850
@@ -47,6 +47,47 @@ U-Boot > sf erase 0 +320000
 U-Boot > tftp u-boot.ais
 U-Boot > sf write c0700000 0 $filesize
 
+Flashing the images to NAND
+===========================
+The AIS image can be written to NAND using the u-boot "nand" commands.
+
+Example:
+
+OMAPL138_LCDK requires the AIS image to be written to the second block of
+the NAND flash.
+
+From the "nand info" command we see that the second block would start at
+offset 0x20000:
+
+  U-Boot > nand info
+      sector size      128 KiB (0x20000)
+      Page size       2048 b
+
+From the tftp command we see that we need to copy 0x74908 bytes from
+memory address 0xc0700000 (0x75000 if we align a page of 2048):
+
+  U-Boot > tftp u-boot.ais
+      Load address: 0xc0700000
+      Bytes transferred = 477448 (74908 hex)
+
+The commands to write the image from memory to NAND would be:
+
+  U-Boot > nand erase 0x20000 0x75000
+  U-Boot > nand write 0xc0700000 0x20000 0x75000
+
+Alternatively, MTD partitions may be defined. Using "mtdparts" to
+conveniently have a bootloader partition starting at the second block
+(offset 0x20000):
+
+  setenv mtdids nand0=davinci_nand.0
+  setenv mtdparts mtdparts=davinci_nand.0:128k(bootenv),2m(bootloader)
+
+In this case the commands would be simplified to:
+
+  U-Boot > tftp u-boot.ais
+  U-Boot > nand erase.part bootloader
+  U-Boot > nand write 0xc0700000 bootloader
+
 Flashing the images to MMC
 ==========================
 If the boot pins are set to boot from mmc, the RBL will try to load the
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 37d2f54..9e17eb8 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -323,9 +323,7 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-#ifndef CONFIG_USE_IRQ
 	irq_init();
-#endif
 
 #ifdef CONFIG_NAND_DAVINCI
 	/*
diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c
index 3ce1992..d941285 100644
--- a/board/davinci/da8xxevm/omapl138_lcdk.c
+++ b/board/davinci/da8xxevm/omapl138_lcdk.c
@@ -171,9 +171,7 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-#ifndef CONFIG_USE_IRQ
 	irq_init();
-#endif
 
 	/* arch number of the board */
 	gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index 66804d7..6edfa17 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -203,9 +203,7 @@ int board_early_init_f(void)
 	/* Set LCD_B_PWR low to power down LCD Backlight*/
 	gpio_direction_output(102, 0);
 
-#ifndef CONFIG_USE_IRQ
 	irq_init();
-#endif
 
 	/*
 	 * NAND CS setup - cycle counts based on da850evm NAND timings in the
diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c
index 75e6f0e..81285d7 100644
--- a/board/dbau1x00/dbau1x00.c
+++ b/board/dbau1x00/dbau1x00.c
@@ -11,11 +11,15 @@
 #include <asm/mipsregs.h>
 #include <asm/io.h>
 
-phys_size_t initdram(int board_type)
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
 {
 	/* Sdram is setup by assembler code */
 	/* If memory could be changed, we should return the true value here */
-	return MEM_SIZE*1024*1024;
+	gd->ram_size = MEM_SIZE * 1024 * 1024;
+
+	return 0;
 }
 
 #define BCSR_PCMCIA_PC0DRVEN		0x0010
diff --git a/board/dnp5370/Kconfig b/board/dnp5370/Kconfig
deleted file mode 100644
index 797081d..0000000
--- a/board/dnp5370/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_DNP5370
-
-config SYS_BOARD
-	default "dnp5370"
-
-config SYS_CONFIG_NAME
-	default "dnp5370"
-
-endif
diff --git a/board/dnp5370/MAINTAINERS b/board/dnp5370/MAINTAINERS
deleted file mode 100644
index 8333891..0000000
--- a/board/dnp5370/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DNP5370 BOARD
-M:	M.Hasewinkel (MHA) <info@ssv-embedded.de>
-S:	Maintained
-F:	board/dnp5370/
-F:	include/configs/dnp5370.h
-F:	configs/dnp5370_defconfig
diff --git a/board/dnp5370/Makefile b/board/dnp5370/Makefile
deleted file mode 100644
index c0271da..0000000
--- a/board/dnp5370/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= dnp5370.o
diff --git a/board/dnp5370/README b/board/dnp5370/README
deleted file mode 100644
index 0172698..0000000
--- a/board/dnp5370/README
+++ /dev/null
@@ -1,67 +0,0 @@
-This document describes the board support for
-Dil/NetPC DNP/5370 (http://www.dilnetpc.com/dnp0086.htm) module.
-The distributor is SSV (http://www.ssv-embedded.de),
-
-The module used to develop the support files contains:
-
-*   Processor: Blackfin BF537 Rev 0.3 (600 MHz core / 120MHz RAM)
-
-*   RAM: 32 MB SDRAM
-    Hynix HY57V561620FTP-H 810EA
-    Connected to Blackfin via "Expansion Bus"
-    Address range 0x0000.0000 - 0x1fff.ffff
-
-*   NOR flash: 32 MBit (4 MByte)
-    Exel Semiconductor ES29LVS320EB
-    Connected to Blackfin via "Expansion Bus",
-    Chip Selects 0, 1 and 2, each is connected
-    to a 1 MB memory bank at Blackfin, therefore
-    only 3 MB accessible.
-    Address range 0x2000.0000 - 0x202f.ffff
-    CFI compatible
-
-    Exel Semiconductor was bought by Rohm Semiconductor (www.rohm.com).
-
-*   NAND flash: 64 MBit (8 MByte)
-    Atmel 45DB642D-CNU
-    Connected to Blackfin via SPI
-    CFI compatible
-
-*   Davicom DM9161EP Ethernet PHY
-
-*   A SD card reader, connected via SPI
-
-*   Hardware watchdog MAX823 or TPS3823
-
-(other devices not listed here)
-
-To run it, the module must be inserted in a 64 pin DIL socket
-on another board, e.g. DNP/EVA13 (together: SSV SK28).
-
-The Blackfin is booted from NOR flash. The NOR flash data begins
-with the U-Boot code and is then followed by the Linux code.
-Finally, the MAC is stored in the last sector.
-You may need to adjust these settings to your needs.
-The memory map used to develop the board support is:
-
-Memory map:
-0x00000000 .. 0x01ffffff SDRAM
-0x20000000 .. 0x202fffff NOR flash
-
-RAM use:
-0x01f9bffc .. 0x01fbbffb U-Boot stack
-0x01f9c000 .. 0x01f9ffff U-Boot global data
-0x01fa0000 .. 0x01fbffff U-Boot malloc() RAM
-0x01fc0000 .. 0x01ffffff U-Boot execution RAM
-
-NOR flash use:
-0x20000000 .. 0x0002ffff U-Boot
-0x20004000 .. 0x20005fff U-Boot environment
-0x20030000 .. 0x202effff Linux kernel image
-0x202f0000 .. 0x202fffff MAC address sector
-
-NOR flash is 0x00300000 (3145728) bytes large (3 MB).
-Max space for compressed kernel in flash is 0x002c0000 (2883584) bytes (2.75 MB)
-Max space for u-boot in flash is 0x00030000 (196608) bytes (192 KB)
-
-The module is hardwired to BYPASS boot mode.
diff --git a/board/dnp5370/dnp5370.c b/board/dnp5370/dnp5370.c
deleted file mode 100644
index 719203d..0000000
--- a/board/dnp5370/dnp5370.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * (C) Copyright 2010 3ality Digital Systems
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/gpio.h>
-
-static void disable_external_watchdog(void)
-{
-#ifdef CONFIG_DNP5370_EXT_WD_DISABLE
-	/* disable external HW watchdog with PH13 = WD1 = 1 */
-	gpio_request(GPIO_PH13, "ext_wd");
-	gpio_direction_output(GPIO_PH13, 1);
-#endif
-}
-
-int checkboard(void)
-{
-	printf("Board: SSV DilNet DNP5370\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
-#ifdef CONFIG_MTD_NOR_FLASH
-	/* we cram the MAC in the last flash sector */
-	uchar *board_mac_addr = (uchar *)0x202F0000;
-	if (is_valid_ethaddr(board_mac_addr)) {
-		memcpy(mac_addr, board_mac_addr, 6);
-		eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-#endif
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-	disable_external_watchdog();
-
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
-
-#ifdef CONFIG_MTD_NOR_FLASH
-	/* we use the last sector for the MAC address / POST LDR */
-	extern flash_info_t flash_info[];
-	flash_protect(FLAG_PROTECT_SET, 0x202F0000, 0x202FFFFF, &flash_info[0]);
-#endif
-
-	return 0;
-}
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
index 656f0fa..66dc407 100644
--- a/board/esd/mecp5123/mecp5123.c
+++ b/board/esd/mecp5123/mecp5123.c
@@ -62,9 +62,11 @@ int board_early_init_f(void)
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
+	gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0));
+
+	return 0;
 }
 
 int misc_init_r(void)
diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
index fe781dc..19b673e 100644
--- a/board/esd/meesc/meesc.c
+++ b/board/esd/meesc/meesc.c
@@ -132,10 +132,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 int board_eth_init(bd_t *bis)
diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c
index e7f8115..c379e77 100644
--- a/board/esd/pmc440/sdram.c
+++ b/board/esd/pmc440/sdram.c
@@ -24,6 +24,8 @@
 #include <asm/mmu.h>
 #include <asm/ppc440.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern int denali_wait_for_dlllock(void);
 extern void denali_core_search_data_eye(void);
 
@@ -40,7 +42,7 @@ struct sdram_conf_s sdram_conf[] = {
 };
 
 /*
- * initdram -- 440EPx's DDR controller is a DENALI Core
+ * dram_init -- 440EPx's DDR controller is a DENALI Core
  */
 int initdram_by_rb(int rows, int banks)
 {
@@ -105,7 +107,7 @@ int initdram_by_rb(int rows, int banks)
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t size;
 	int n;
@@ -125,12 +127,14 @@ phys_size_t initdram(int board_type)
 			       sdram_conf[n].banks);
 
 		/* check for suitable configuration */
-		if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size)
-			return size;
+		if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size) {
+			gd->ram_size = size;
+			return 0;
+		}
 
 		/* delete TLB entries */
 		remove_tlb(CONFIG_SYS_SDRAM_BASE, size);
 	}
 
-	return 0;
+	return -ENXIO;
 }
diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c
index f8f1834..36a5519 100644
--- a/board/esd/vme8349/vme8349.c
+++ b/board/esd/vme8349/vme8349.c
@@ -26,15 +26,17 @@
 #include <i2c.h>
 #include <netdev.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void ddr_enable_ecc(unsigned int dram_size);
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main memory */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
@@ -52,7 +54,9 @@ phys_size_t initdram(int board_type)
 	msize = get_ram_size(0, msize);
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize * 1024 * 1024;
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index 99cd884..5cc2f73 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -176,7 +176,7 @@ found:
 	popts->cpo_sample = 0x3e;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -189,7 +189,9 @@ phys_size_t initdram(int board_type)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c
index 35b812c..60d7f0d 100644
--- a/board/freescale/b4860qds/spl.c
+++ b/board/freescale/b4860qds/spl.c
@@ -108,7 +108,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	puts("\n\n");
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_boot();
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
index 6613216..94093f1 100644
--- a/board/freescale/c29xpcie/spl.c
+++ b/board/freescale/c29xpcie/spl.c
@@ -67,7 +67,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("TPL\n");
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 2b723a4..7396aa2 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -27,6 +27,10 @@
 #define CHECK_KEY_LEN(key_len)	(((key_len) == 2 * KEY_SIZE_BYTES / 4) || \
 				 ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
 				 ((key_len) == 2 * KEY_SIZE_BYTES))
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+/* Global data structure */
+static struct fsl_secboot_glb glb;
+#endif
 
 /* This array contains DER value for SHA-256 */
 static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
@@ -60,7 +64,7 @@ self:
 #if defined(CONFIG_FSL_ISBC_KEY_EXT)
 static u32 check_ie(struct fsl_secboot_img_priv *img)
 {
-	if (img->hdr.ie_flag)
+	if (img->hdr.ie_flag & IE_FLAG_MASK)
 		return 1;
 
 	return 0;
@@ -119,7 +123,21 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
 }
 #endif
 
-static int get_ie_info_addr(u32 *ie_addr)
+#if defined(CONFIG_ESBC_HDR_LS)
+static int get_ie_info_addr(uintptr_t *ie_addr)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	/* For LS-CH3, the address of IE Table is
+	 * stated in Scratch13 and scratch14 of DCFG.
+	 * Bootrom validates this table while validating uboot.
+	 * DCFG is LE*/
+	*ie_addr = in_le32(&gur->scratchrw[SCRATCH_IE_HIGH_ADR - 1]);
+	*ie_addr = *ie_addr << 32;
+	*ie_addr |= in_le32(&gur->scratchrw[SCRATCH_IE_LOW_ADR - 1]);
+	return 0;
+}
+#else /* CONFIG_ESBC_HDR_LS */
+static int get_ie_info_addr(uintptr_t *ie_addr)
 {
 	struct fsl_secboot_img_hdr *hdr;
 	struct fsl_secboot_sg_table *sg_tbl;
@@ -147,16 +165,17 @@ static int get_ie_info_addr(u32 *ie_addr)
 
 	/* IE Key Table is the first entry in the SG Table */
 #if defined(CONFIG_MPC85xx)
-	*ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
-		   flash_base_addr;
+	*ie_addr = (uintptr_t)((sg_tbl->src_addr &
+			~(CONFIG_SYS_PBI_FLASH_BASE)) +
+			flash_base_addr);
 #else
-	*ie_addr = sg_tbl->src_addr;
+	*ie_addr = (uintptr_t)sg_tbl->src_addr;
 #endif
 
-	debug("IE Table address is %x\n", *ie_addr);
+	debug("IE Table address is %lx\n", *ie_addr);
 	return 0;
 }
-
+#endif /* CONFIG_ESBC_HDR_LS */
 #endif
 
 #ifdef CONFIG_KEY_REVOCATION
@@ -164,7 +183,10 @@ static int get_ie_info_addr(u32 *ie_addr)
 static u32 check_srk(struct fsl_secboot_img_priv *img)
 {
 #ifdef CONFIG_ESBC_HDR_LS
-	/* In LS, No SRK Flag as SRK is always present*/
+	/* In LS, No SRK Flag as SRK is always present if IE not present*/
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+	return !check_ie(img);
+#endif
 	return 1;
 #else
 	if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
@@ -253,14 +275,29 @@ static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
 #endif /* CONFIG_ESBC_HDR_LS */
 
 #if defined(CONFIG_FSL_ISBC_KEY_EXT)
+
+static void install_ie_tbl(uintptr_t ie_tbl_addr,
+		struct fsl_secboot_img_priv *img)
+{
+	/* Copy IE tbl to Global Data */
+	memcpy(&glb.ie_tbl, (u8 *)ie_tbl_addr, sizeof(struct ie_key_info));
+	img->ie_addr = (uintptr_t)&glb.ie_tbl;
+	glb.ie_addr = img->ie_addr;
+}
+
 static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
 {
 	struct fsl_secboot_img_hdr *hdr = &img->hdr;
 	u32 ie_key_len, ie_revoc_flag, ie_num;
 	struct ie_key_info *ie_info;
 
-	if (get_ie_info_addr(&img->ie_addr))
-		return ERROR_IE_TABLE_NOT_FOUND;
+	if (!img->ie_addr) {
+		if (get_ie_info_addr(&img->ie_addr))
+			return ERROR_IE_TABLE_NOT_FOUND;
+		else
+			install_ie_tbl(img->ie_addr, img);
+		}
+
 	ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr;
 	if (ie_info->num_keys == 0 || ie_info->num_keys > 32)
 		return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY;
@@ -786,6 +823,26 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)
 
 	return 0;
 }
+/* Function to initialize img priv and global data structure
+ */
+static int secboot_init(struct fsl_secboot_img_priv **img_ptr)
+{
+	*img_ptr = malloc(sizeof(struct fsl_secboot_img_priv));
+
+	struct fsl_secboot_img_priv *img = *img_ptr;
+
+	if (!img)
+		return -ENOMEM;
+	memset(img, 0, sizeof(struct fsl_secboot_img_priv));
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+	if (glb.ie_addr)
+		img->ie_addr = glb.ie_addr;
+#endif
+	return 0;
+}
+
+
 /* haddr - Address of the header of image to be validated.
  * arg_hash_str - Option hash string. If provided, this
  * overrides the key hash in the SFP fuses.
@@ -839,12 +896,9 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
 		hash_cmd = 1;
 	}
 
-	img = malloc(sizeof(struct fsl_secboot_img_priv));
-
-	if (!img)
-		return -1;
-
-	memset(img, 0, sizeof(struct fsl_secboot_img_priv));
+	ret = secboot_init(&img);
+	if (ret)
+		goto exit;
 
 	/* Update the information in Private Struct */
 	hdr = &img->hdr;
@@ -899,5 +953,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
 	}
 
 exit:
+	/* Free Img as it was malloc'ed*/
+	free(img);
 	return ret;
 }
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 9c1a4c2..496d841 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -260,7 +260,7 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -278,5 +278,7 @@ phys_size_t initdram(int board_type)
 	dram_size *= 0x100000;
 
 	debug("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index 2f66ba9..d16a69f 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -164,7 +164,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -179,11 +179,15 @@ phys_size_t initdram(int board_type)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 79078d2..d81d8ab 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -162,9 +162,7 @@ int dram_init(void)
 	 * before accessing DDR SPD.
 	 */
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-	gd->ram_size = initdram(0);
-
-	return 0;
+	return fsl_initdram();
 }
 
 #ifdef CONFIG_FSL_ESDHC
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index c740062..2643f5b 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -108,7 +108,7 @@ found:
 #endif
 }
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -125,5 +125,7 @@ phys_size_t initdram(int board_type)
 	fsl_dp_ddr_restore();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 6507c09..2df63e4 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <i2c.h>
 #include <fdt_support.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
@@ -153,7 +154,7 @@ int dram_init(void)
 	 * before accessing DDR SPD.
 	 */
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-	gd->ram_size = initdram(0);
+	fsl_initdram();
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 	/* This will break-before-make MMU for DDR */
 	update_early_mmu_table();
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index f90b85d..36d27ec 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -170,7 +170,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 }
 #endif
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -186,5 +186,7 @@ phys_size_t initdram(int board_type)
 	fsl_dp_ddr_restore();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 2333843..728de2e 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -23,9 +23,7 @@
 #ifdef CONFIG_U_QE
 #include <fsl_qe.h>
 #endif
-#ifdef CONFIG_FSL_LS_PPA
 #include <asm/arch/ppa.h>
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c
index dc4d689..d37af34 100644
--- a/board/freescale/ls1046aqds/ddr.c
+++ b/board/freescale/ls1046aqds/ddr.c
@@ -92,7 +92,7 @@ found:
 	popts->cpo_sample = 0x70;
 }
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -110,5 +110,7 @@ phys_size_t initdram(int board_type)
 
 	erratum_a008850_post();
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index af3f70a..69fc15b 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <i2c.h>
 #include <fdt_support.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
@@ -149,7 +150,7 @@ int dram_init(void)
 	 * before accessing DDR SPD.
 	 */
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-	gd->ram_size = initdram(0);
+	fsl_initdram();
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 	/* This will break-before-make MMU for DDR */
 	update_early_mmu_table();
diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c
index efe2ba6..a16f7bc 100644
--- a/board/freescale/ls1046ardb/ddr.c
+++ b/board/freescale/ls1046ardb/ddr.c
@@ -96,7 +96,7 @@ found:
 	popts->cpo_sample = 0x70;
 }
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -110,5 +110,7 @@ phys_size_t initdram(int board_type)
 
 	erratum_a008850_post();
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c
index 5ed9e14..9d176d3 100644
--- a/board/freescale/ls2080a/ddr.c
+++ b/board/freescale/ls2080a/ddr.c
@@ -158,14 +158,13 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 	return 0;
 }
 #endif
-phys_size_t initdram(int board_type)
-{
-	phys_size_t dram_size;
 
+int fsl_initdram(void)
+{
 	puts("Initializing DDR....");
 
 	puts("using SPD\n");
-	dram_size = fsl_ddr_sdram();
+	gd->ram_size = fsl_ddr_sdram();
 
-	return dram_size;
+	return 0;
 }
diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c
index 0408c0f..22a2676 100644
--- a/board/freescale/ls2080aqds/ddr.c
+++ b/board/freescale/ls2080aqds/ddr.c
@@ -155,17 +155,15 @@ found:
 	}
 }
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
-	phys_size_t dram_size;
-
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-	return fsl_ddr_sdram_size();
+	gd->ram_size = fsl_ddr_sdram_size();
 #else
 	puts("Initializing DDR....using SPD\n");
 
-	dram_size = fsl_ddr_sdram();
+	gd->ram_size = fsl_ddr_sdram();
 #endif
 
-	return dram_size;
+	return 0;
 }
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 277013b..6da9c6c 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -19,6 +19,8 @@
 #include <asm/arch/soc.h>
 #include <hwconfig.h>
 #include <fsl_sec.h>
+#include <asm/arch/ppa.h>
+
 
 #include "../common/qixis.h"
 #include "ls2080aqds_qixis.h"
@@ -225,6 +227,14 @@ int board_init(void)
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 	rtc_enable_32khz_output();
 
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
 	return 0;
 }
 
@@ -266,9 +276,6 @@ void detail_board_ddr_info(void)
 #if defined(CONFIG_ARCH_MISC_INIT)
 int arch_misc_init(void)
 {
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c
index 2851d5b..7002dfb 100644
--- a/board/freescale/ls2080ardb/ddr.c
+++ b/board/freescale/ls2080ardb/ddr.c
@@ -158,17 +158,15 @@ found:
 	}
 }
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
-	phys_size_t dram_size;
-
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-	return fsl_ddr_sdram_size();
+	gd->ram_size = fsl_ddr_sdram_size();
 #else
 	puts("Initializing DDR....using SPD\n");
 
-	dram_size = fsl_ddr_sdram();
+	gd->ram_size = fsl_ddr_sdram();
 #endif
 
-	return dram_size;
+	return 0;
 }
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 4c01f56..ea05ec6 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -19,6 +19,7 @@
 #include <i2c.h>
 #include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
+#include <asm/arch/ppa.h>
 #include <fsl_sec.h>
 
 #include "../common/qixis.h"
@@ -181,10 +182,17 @@ int board_init(void)
 
 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
 #ifdef CONFIG_FSL_MC_ENET
 	/* invert AQR405 IRQ pins polarity */
 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 #endif
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
 
 	return 0;
 }
@@ -223,9 +231,6 @@ void detail_board_ddr_info(void)
 #if defined(CONFIG_ARCH_MISC_INIT)
 int arch_misc_init(void)
 {
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
 	return 0;
 }
 #endif
diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c
index 1df128b..4b841c6 100644
--- a/board/freescale/m5208evbe/m5208evbe.c
+++ b/board/freescale/m5208evbe/m5208evbe.c
@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
@@ -68,7 +68,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c
index a1127e5..e4dfb6f 100644
--- a/board/freescale/m52277evb/m52277evb.c
+++ b/board/freescale/m52277evb/m52277evb.c
@@ -21,7 +21,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	u32 dramsize;
 
@@ -78,7 +78,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 #endif
-	return (dramsize);
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index 68c1631..93403f6 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
@@ -97,7 +97,9 @@ phys_size_t initdram(int board_type)
 		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
 	}
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c
index 7ae842c..7c9b599 100644
--- a/board/freescale/m5249evb/m5249evb.c
+++ b/board/freescale/m5249evb/m5249evb.c
@@ -10,6 +10,8 @@
 #include <malloc.h>
 #include <asm/immap.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard (void) {
 	ulong val;
 	uchar val8;
@@ -29,7 +31,8 @@ int checkboard (void) {
 };
 
 
-phys_size_t initdram (int board_type) {
+int dram_init(void)
+{
 	unsigned long	junk = 0xa5a59696;
 
 	/*
@@ -81,7 +84,9 @@ phys_size_t initdram (int board_type) {
 	mbar_writeLong(MCFSIM_DACR0, 0x0000b364);  /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
 	*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 };
 
 
diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index 7e516bf..c2cc2d7 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -13,6 +13,8 @@
 #include <netdev.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard(void)
 {
 	puts("Board: ");
@@ -20,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	u32 dramsize = 0;
 
@@ -73,7 +75,9 @@ phys_size_t initdram(int board_type)
 		mb();
 	}
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 }
 
 int testdram(void)
diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c
index 15ff755..c1ed431 100644
--- a/board/freescale/m5253evbe/m5253evbe.c
+++ b/board/freescale/m5253evbe/m5253evbe.c
@@ -12,6 +12,8 @@
 #include <asm/immap.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard(void)
 {
 	puts("Board: ");
@@ -19,7 +21,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	/*
 	 * Check to see if the SDRAM has already been initialized
@@ -66,7 +68,9 @@ phys_size_t initdram(int board_type)
 		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
 	}
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 }
 
 int testdram(void)
diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c
index 3ed4a7d..efff465 100644
--- a/board/freescale/m5272c3/m5272c3.c
+++ b/board/freescale/m5272c3/m5272c3.c
@@ -11,6 +11,7 @@
 #include <asm/immap.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard (void) {
 	puts ("Board: ");
@@ -18,7 +19,8 @@ int checkboard (void) {
 	return 0;
 	};
 
-phys_size_t initdram (int board_type) {
+int dram_init(void)
+{
 	sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
 
 	out_be16(&sdp->sdram_sdtr, 0xf539);
@@ -27,7 +29,9 @@ phys_size_t initdram (int board_type) {
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *)0) = 0;
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 	};
 
 int testdram (void) {
diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c
index 16083d1..5a9831d 100644
--- a/board/freescale/m5275evb/m5275evb.c
+++ b/board/freescale/m5275evb/m5275evb.c
@@ -13,6 +13,8 @@
 #include <asm/immap.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PERIOD		13	/* system bus period in ns */
 #define SDRAM_TREFI	7800	/* in ns */
 
@@ -23,7 +25,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
 	gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
@@ -88,7 +90,9 @@ phys_size_t initdram(int board_type)
 		| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
 		| MCF_SDRAMC_SDCR_DQS_OE(0x3));
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c
index 39f12fb..eb618b5 100644
--- a/board/freescale/m5282evb/m5282evb.c
+++ b/board/freescale/m5282evb/m5282evb.c
@@ -16,7 +16,7 @@ int checkboard (void)
 	return 0;
 }
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	u32 dramsize, i, dramclk;
 
@@ -80,5 +80,7 @@ phys_size_t initdram (int board_type)
 		/* Write to the SDRAM Mode Register */
 		*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
 	}
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 }
diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c
index dbe886b..71cca35 100644
--- a/board/freescale/m53017evb/m53017evb.c
+++ b/board/freescale/m53017evb/m53017evb.c
@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
@@ -68,7 +68,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c
index 1f77adf..4e0b4e4 100644
--- a/board/freescale/m5329evb/m5329evb.c
+++ b/board/freescale/m5329evb/m5329evb.c
@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
@@ -62,7 +62,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c
index bfcc4b2..f2ed298 100644
--- a/board/freescale/m5373evb/m5373evb.c
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
@@ -62,7 +62,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m54418twr/m54418twr.c b/board/freescale/m54418twr/m54418twr.c
index 5375d16..4335394 100644
--- a/board/freescale/m54418twr/m54418twr.c
+++ b/board/freescale/m54418twr/m54418twr.c
@@ -25,7 +25,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	u32 dramsize;
 
@@ -104,7 +104,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 #endif
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
index d2ad42c..050624b 100644
--- a/board/freescale/m54451evb/m54451evb.c
+++ b/board/freescale/m54451evb/m54451evb.c
@@ -26,7 +26,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	u32 dramsize;
 #ifdef CONFIG_CF_SBF
@@ -82,7 +82,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 #endif
-	return (dramsize);
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c
index 76b4322..d6b0650 100644
--- a/board/freescale/m54455evb/m54455evb.c
+++ b/board/freescale/m54455evb/m54455evb.c
@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	u32 dramsize;
 #ifdef CONFIG_CF_SBF
@@ -75,7 +75,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 #endif
-	return (dramsize << 1);
+	gd->ram_size = dramsize << 1;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c
index 1e3cb61..d28f43d 100644
--- a/board/freescale/m547xevb/m547xevb.c
+++ b/board/freescale/m547xevb/m547xevb.c
@@ -23,7 +23,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	siu_t *siu = (siu_t *) (MMAP_SIU);
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
@@ -79,7 +79,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c
index 0536155..56060b6 100644
--- a/board/freescale/m548xevb/m548xevb.c
+++ b/board/freescale/m548xevb/m548xevb.c
@@ -23,7 +23,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	siu_t *siu = (siu_t *) (MMAP_SIU);
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
@@ -79,7 +79,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
index 7c44282..f87579f 100644
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -95,7 +95,7 @@ int is_micron(void){
 	return(ismicron);
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	u32 msize = 0;
 	/*
@@ -167,7 +167,9 @@ phys_size_t initdram(int board_type)
 				sizeof(elpida_init_sequence)/sizeof(u32));
 	}
 
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }
 
 int misc_init_r(void)
diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c
index 89b665e..81e155a 100644
--- a/board/freescale/mpc8308rdb/sdram.c
+++ b/board/freescale/mpc8308rdb/sdram.c
@@ -65,17 +65,19 @@ static long fixed_sdram(void)
 	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;
 
 	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM */
 	msize = fixed_sdram();
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index eac193e..8974378 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -133,8 +133,8 @@ void board_init_f(ulong bootflag)
 	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
 		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 	puts("NAND boot... ");
-	init_timebase();
-	initdram(0);
+	timer_init();
+	dram_init();
 	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
 		      CONFIG_SYS_NAND_U_BOOT_RELOC);
 }
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 6282c3d..a4128cb 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -97,14 +97,14 @@ static long fixed_sdram(void)
 	return msize;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile fsl_lbc_t *lbc = &im->im_lbc;
 	u32 msize;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	msize = fixed_sdram();
@@ -120,5 +120,7 @@ phys_size_t initdram(int board_type)
 #endif
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
index 3cec09b..22f1565 100644
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ b/board/freescale/mpc8315erdb/mpc8315erdb.c
@@ -221,8 +221,8 @@ void board_init_f(ulong bootflag)
 	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
 		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 	puts("NAND boot... ");
-	init_timebase();
-	initdram(0);
+	timer_init();
+	dram_init();
 	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
 		      CONFIG_SYS_NAND_U_BOOT_RELOC);
 }
diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
index 6c94312..b69c86b 100644
--- a/board/freescale/mpc8315erdb/sdram.c
+++ b/board/freescale/mpc8315erdb/sdram.c
@@ -92,13 +92,13 @@ static long fixed_sdram(void)
 }
 #endif /* CONFIG_SYS_RAMBOOT */
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM */
 	msize = fixed_sdram();
@@ -106,6 +106,8 @@ phys_size_t initdram(int board_type)
 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
 		resume_from_sleep();
 
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
 }
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index 0a0152a..f30a151 100644
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -21,6 +21,8 @@
 #endif
 #include <asm/mmu.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* UCC3 */
 	{1,  0, 1, 0, 1}, /* TxD0 */
@@ -68,21 +70,23 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 
 	msize = fixed_sdram();
 
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return (msize * 1024 * 1024);
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 /*************************************************************************
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
index adf4254..b49e03e 100644
--- a/board/freescale/mpc832xemds/mpc832xemds.c
+++ b/board/freescale/mpc832xemds/mpc832xemds.c
@@ -23,6 +23,8 @@
 #include "../common/pq-mds-pib.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* ETH3 */
 	{1,  0, 1, 0, 1}, /* TxD0 */
@@ -88,21 +90,23 @@ int board_early_init_r(void)
 
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 
 	msize = fixed_sdram();
 
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return (msize * 1024 * 1024);
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 /*************************************************************************
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index 02b5040..5f502e2 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -22,6 +22,8 @@
 #include <libfdt.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int fixed_sdram(void);
 void sdram_init(void);
 
@@ -46,13 +48,13 @@ int board_early_init_f (void)
 
 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	phys_size_t msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
@@ -73,8 +75,10 @@ phys_size_t initdram (int board_type)
 	 */
 	sdram_init();
 
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
 }
 
 #if !defined(CONFIG_SPD_EEPROM)
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 22a1d99..895e9ff 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -20,6 +20,8 @@
 #include <libfdt.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SPD_EEPROM
 /*************************************************************************
  *  fixed sdram init -- doesn't use serial presence detect.
@@ -116,7 +118,7 @@ volatile static struct pci_controller hose[] = {
 };
 #endif				/* CONFIG_PCI */
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
@@ -125,7 +127,7 @@ phys_size_t initdram(int board_type)
 #endif
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
@@ -144,7 +146,9 @@ phys_size_t initdram(int board_type)
 #endif
 
 	/* return total bus RAM size(bytes) */
-	return msize * 1024 * 1024;
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index 045841d..2330492 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -20,6 +20,8 @@
 #include "pci.h"
 #include "../common/pq-mds-pib.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int board_early_init_f(void)
 {
 	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
@@ -216,13 +218,13 @@ extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 #if defined(CONFIG_SPD_EEPROM)
 	msize = spd_sdram();
@@ -236,7 +238,9 @@ phys_size_t initdram(int board_type)
 #endif
 
 	/* return total bus DDR size(bytes) */
-	return (msize * 1024 * 1024);
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 #if !defined(CONFIG_SPD_EEPROM)
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 07c0599..319f047 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -16,6 +16,8 @@
 #include <vsc7385.h>
 #include <fsl_esdhc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_SYS_DRAM_TEST)
 int
 testdram(void)
@@ -60,13 +62,13 @@ void ddr_enable_ecc(unsigned int dram_size);
 #endif
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 #if defined(CONFIG_SPD_EEPROM)
 	msize = spd_sdram();
@@ -79,7 +81,9 @@ phys_size_t initdram(int board_type)
 	ddr_enable_ecc(msize * 1024 * 1024);
 #endif
 	/* return total bus DDR size(bytes) */
-	return (msize * 1024 * 1024);
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 #if !defined(CONFIG_SPD_EEPROM)
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 95e398c..d97562c 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -19,6 +19,8 @@
 #include <spd_sdram.h>
 #include <netdev.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void sdram_init(void);
 phys_size_t fixed_sdram(void);
 int mpc8610hpcd_diu_init(void);
@@ -116,8 +118,7 @@ int checkboard(void)
 }
 
 
-phys_size_t
-initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size = 0;
 
@@ -130,7 +131,9 @@ initdram(int board_type)
 	setup_ddr_bat(dram_size);
 
 	debug(" DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 94633b5..2604a51 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -16,6 +16,8 @@
 #include <fdt_support.h>
 #include <netdev.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 phys_size_t fixed_sdram(void);
 
 int checkboard(void)
@@ -37,8 +39,7 @@ int checkboard(void)
 	return 0;
 }
 
-phys_size_t
-initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size = 0;
 
@@ -51,7 +52,9 @@ initdram(int board_type)
 	setup_ddr_bat(dram_size);
 
 	debug("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c
index fb0ab77..123fb11 100644
--- a/board/freescale/mx35pdk/mx35pdk.c
+++ b/board/freescale/mx35pdk/mx35pdk.c
@@ -47,13 +47,15 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return 0;
 }
 
 #define I2C_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c
index a6e46b9..eb9f743 100644
--- a/board/freescale/mx53ard/mx53ard.c
+++ b/board/freescale/mx53ard/mx53ard.c
@@ -32,13 +32,15 @@ int dram_init(void)
 
 	return 0;
 }
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_NAND_MXC
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index 9e1072f..3741fa1 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -58,13 +58,15 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = mx53_dram_size[0];
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+	return 0;
 }
 
 u32 get_board_rev(void)
diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c
index 938c611..630d671 100644
--- a/board/freescale/mx53smd/mx53smd.c
+++ b/board/freescale/mx53smd/mx53smd.c
@@ -30,13 +30,15 @@ int dram_init(void)
 
 	return 0;
 }
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return 0;
 }
 
 #define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index 05c76f2..2cebc2c 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -94,7 +94,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("\nTertiary program loader running in sram...");
 #else
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
index ef38551..a117dc3 100644
--- a/board/freescale/p1022ds/spl.c
+++ b/board/freescale/p1022ds/spl.c
@@ -111,7 +111,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	gd->ram_size = initdram(0);
+	dram_init();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index 2af5576..1cf3497 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -108,7 +108,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	gd->ram_size = initdram(0);
+	dram_init();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else
diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c
index b2493e1..1ab98fc 100644
--- a/board/freescale/p2041rdb/ddr.c
+++ b/board/freescale/p2041rdb/ddr.c
@@ -12,6 +12,8 @@
 #include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 struct board_specific_parameters {
 	u32 n_ranks;
 	u32 datarate_mhz_high;
@@ -116,7 +118,7 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size = 0;
 
@@ -127,12 +129,14 @@ phys_size_t initdram(int board_type)
 		dram_size = fsl_ddr_sdram();
 	} else {
 		puts("no SPD and fixed parameters\n");
-		return dram_size;
+		return -ENXIO;
 	}
 
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
 	debug("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
index b6b1191..d822d3f 100644
--- a/board/freescale/t102xqds/ddr.c
+++ b/board/freescale/t102xqds/ddr.c
@@ -169,7 +169,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -187,5 +187,7 @@ phys_size_t initdram(int board_type)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c
index 3e96b33..b987ece 100644
--- a/board/freescale/t102xqds/spl.c
+++ b/board/freescale/t102xqds/spl.c
@@ -142,7 +142,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index e666578..49460a0 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -229,7 +229,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -249,5 +249,7 @@ phys_size_t initdram(int board_type)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index b70c2c5..dc6d9ee 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -129,7 +129,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
index cb58d1e..8f7909d 100644
--- a/board/freescale/t1040qds/ddr.c
+++ b/board/freescale/t1040qds/ddr.c
@@ -117,7 +117,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -134,5 +134,7 @@ phys_size_t initdram(int board_type)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index 302f19b..4e55844 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -120,7 +120,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -137,5 +137,7 @@ phys_size_t initdram(int board_type)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index 4402e0f..2e43307 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -125,7 +125,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	puts("\n\n");
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c
index d6e4554..ba65049 100644
--- a/board/freescale/t208xqds/ddr.c
+++ b/board/freescale/t208xqds/ddr.c
@@ -104,7 +104,7 @@ found:
 	popts->cpo_sample = 0x64;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -118,5 +118,7 @@ phys_size_t initdram(int board_type)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index 334f508..d7d716b 100644
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c
@@ -128,7 +128,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c
index 3487261..50dc69a 100644
--- a/board/freescale/t208xrdb/ddr.c
+++ b/board/freescale/t208xrdb/ddr.c
@@ -97,7 +97,7 @@ found:
 	popts->cpo_sample = 0x54;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -111,5 +111,7 @@ phys_size_t initdram(int board_type)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index aa8e928..b431401 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -98,7 +98,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 842073b..7408970 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -112,7 +112,7 @@ found:
 	popts->cpo_sample = 0x63;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -127,5 +127,7 @@ phys_size_t initdram(int board_type)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c
index 5e946dc..9ecdaed 100644
--- a/board/freescale/t4qds/spl.c
+++ b/board/freescale/t4qds/spl.c
@@ -133,7 +133,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
index 7b05821..8415527 100644
--- a/board/freescale/t4rdb/ddr.c
+++ b/board/freescale/t4rdb/ddr.c
@@ -105,7 +105,7 @@ found:
 	popts->cpo_sample = 0x64;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -120,5 +120,7 @@ phys_size_t initdram(int board_type)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index a32e34e..5feab1c 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c
@@ -91,7 +91,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 	mmc_boot();
 }
diff --git a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c b/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c
index d26212e..f186855 100644
--- a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c
+++ b/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c
@@ -10,9 +10,11 @@
 #include <config.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return 1;
+	/* Does not set gd->ram_size here */
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/gaisler/gr_ep2s60/gr_ep2s60.c b/board/gaisler/gr_ep2s60/gr_ep2s60.c
index 98fb45f..a73d89d 100644
--- a/board/gaisler/gr_ep2s60/gr_ep2s60.c
+++ b/board/gaisler/gr_ep2s60/gr_ep2s60.c
@@ -10,9 +10,11 @@
 #include <config.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return 1;
+	/* Does not set gd->ram_size here */
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c b/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c
index 32fbbe2..d86047a 100644
--- a/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c
+++ b/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c
@@ -9,9 +9,11 @@
 #include <config.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return 1;
+	/* Does not set gd->ram_size here */
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/gaisler/grsim/grsim.c b/board/gaisler/grsim/grsim.c
index fd73920..99262b0 100644
--- a/board/gaisler/grsim/grsim.c
+++ b/board/gaisler/grsim/grsim.c
@@ -10,9 +10,11 @@
 #include <common.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return 1;
+	/* Does not set gd->ram_size here */
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/gaisler/grsim_leon2/grsim_leon2.c b/board/gaisler/grsim_leon2/grsim_leon2.c
index 882b0a4..c6c4bb4 100644
--- a/board/gaisler/grsim_leon2/grsim_leon2.c
+++ b/board/gaisler/grsim_leon2/grsim_leon2.c
@@ -10,9 +10,11 @@
 #include <common.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return 1;
+	/* Does not set gd->ram_size here */
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/gdsys/a38x/.gitignore b/board/gdsys/a38x/.gitignore
new file mode 100644
index 0000000..775b934
--- /dev/null
+++ b/board/gdsys/a38x/.gitignore
@@ -0,0 +1 @@
+kwbimage.cfg
diff --git a/board/gdsys/a38x/Kconfig b/board/gdsys/a38x/Kconfig
new file mode 100644
index 0000000..3fdef64
--- /dev/null
+++ b/board/gdsys/a38x/Kconfig
@@ -0,0 +1,36 @@
+if TARGET_CONTROLCENTERDC
+
+config SYS_BOARD
+	default "a38x"
+
+config SYS_VENDOR
+	default "gdsys"
+
+config SYS_SOC
+	default "mvebu"
+
+config SYS_CONFIG_NAME
+	default "controlcenterdc"
+
+menu "Controlcenter DC board options"
+
+choice
+	prompt "Select boot method"
+
+config SPL_BOOT_DEVICE_SPI
+	bool "SPI"
+
+config SPL_BOOT_DEVICE_MMC
+	bool "MMC"
+	select SPL_LIBDISK_SUPPORT
+
+endchoice
+
+#config SPL_BOOT_DEVICE
+#	int
+#	default 1 if SPL_BOOT_DEVICE_SPI
+#	default 2 if SPL_BOOT_DEVICE_MMC
+
+endmenu
+
+endif
diff --git a/board/gdsys/a38x/MAINTAINERS b/board/gdsys/a38x/MAINTAINERS
new file mode 100644
index 0000000..3cb9b63
--- /dev/null
+++ b/board/gdsys/a38x/MAINTAINERS
@@ -0,0 +1,7 @@
+A38X BOARD
+M:	Dirk Eibach <eibach@gdsys.cc>
+M:	Mario Six <six@gdsys.de>
+S:	Maintained
+F:	board/gdsys/a38x/
+F:	include/configs/controlcenterdc.h
+F:	configs/controlcenterdc_defconfig
diff --git a/board/gdsys/a38x/Makefile b/board/gdsys/a38x/Makefile
new file mode 100644
index 0000000..e1f0bd8
--- /dev/null
+++ b/board/gdsys/a38x/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+# Copyright (C) 2015 Reinhard Pfau <reinhard.pfau@gdsys.cc>
+# Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_TARGET_CONTROLCENTERDC) += controlcenterdc.o hre.o spl.o keyprogram.o dt_helpers.o
+
+ifeq ($(CONFIG_SPL_BUILD),)
+
+obj-$(CONFIG_TARGET_CONTROLCENTERDC) += hydra.o ihs_phys.o
+
+extra-$(CONFIG_TARGET_CONTROLCENTERDC) += kwbimage.cfg
+
+KWB_REPLACE += BOOT_FROM
+ifneq ($(CONFIG_SPL_BOOT_DEVICE_SPI),)
+	KWB_CFG_BOOT_FROM=spi
+endif
+ifneq ($(CONFIG_SPL_BOOT_DEVICE_MMC),)
+	KWB_CFG_BOOT_FROM=sdio
+endif
+
+ifneq ($(CONFIG_SECURED_MODE_IMAGE),)
+KWB_REPLACE += CSK_INDEX
+KWB_CFG_CSK_INDEX = $(CONFIG_SECURED_MODE_CSK_INDEX)
+
+KWB_REPLACE += SEC_BOOT_DEV
+KWB_CFG_SEC_BOOT_DEV=$(patsubst "%",%, \
+	$(if $(findstring BOOT_SPI_NOR_FLASH,$(CONFIG_SPL_BOOT_DEVICE)),0x34) \
+	$(if $(findstring BOOT_SDIO_MMC_CARD,$(CONFIG_SPL_BOOT_DEVICE)),0x31) \
+	)
+
+KWB_REPLACE += SEC_FUSE_DUMP
+KWB_CFG_SEC_FUSE_DUMP = a38x
+endif
+
+$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
+		include/config/auto.conf
+	$(Q)sed -ne '$(foreach V,$(KWB_REPLACE),s/^#@$(V)/$(V) $(KWB_CFG_$(V))/;)p' \
+	<$< >$(dir $<)$(@F)
+
+endif
diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
new file mode 100644
index 0000000..f0efb53
--- /dev/null
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -0,0 +1,279 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <miiphy.h>
+#include <tpm.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm-generic/gpio.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
+
+#include "keyprogram.h"
+#include "dt_helpers.h"
+#include "hydra.h"
+#include "ihs_phys.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ETH_PHY_CTRL_REG		0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT	11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK	(1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+#define DB_GP_88F68XX_GPP_OUT_ENA_LOW	0x7fffffff
+#define DB_GP_88F68XX_GPP_OUT_ENA_MID	0xffffefff
+
+#define DB_GP_88F68XX_GPP_OUT_VAL_LOW	0x0
+#define DB_GP_88F68XX_GPP_OUT_VAL_MID	0x00001000
+#define DB_GP_88F68XX_GPP_POL_LOW	0x0
+#define DB_GP_88F68XX_GPP_POL_MID	0x0
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct hws_topology_map ddr_topology_map = {
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1600K,	/* speed_bin */
+	    BUS_WIDTH_16,		/* memory_width */
+	    MEM_4G,			/* mem_size */
+	    DDR_FREQ_533,		/* frequency */
+	    0, 0,			/* cas_l cas_wl */
+	    HWS_TEMP_LOW} },		/* temperature */
+	5,				/* Num Of Bus Per Interface*/
+	BUS_MASK_32BIT			/* Busses mask */
+};
+
+static struct serdes_map serdes_topology_map[] = {
+	{SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	/* SATA tx polarity is inverted */
+	{SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
+	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+	*serdes_map_array = serdes_topology_map;
+	*count = ARRAY_SIZE(serdes_topology_map);
+	return 0;
+}
+
+void board_pex_config(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	uint k;
+	struct gpio_desc gpio = {};
+
+	if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
+		/* prepare FPGA reconfiguration */
+		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
+		dm_gpio_set_value(&gpio, 0);
+
+		/* give lunatic PCIe clock some time to stabilize */
+		mdelay(500);
+
+		/* start FPGA reconfiguration */
+		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
+	}
+
+	/* wait for FPGA done */
+	if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
+		for (k = 0; k < 20; ++k) {
+			if (dm_gpio_get_value(&gpio)) {
+				printf("FPGA done after %u rounds\n", k);
+				break;
+			}
+			mdelay(100);
+		}
+	}
+
+	/* disable FPGA reset */
+	if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
+		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
+		dm_gpio_set_value(&gpio, 1);
+	}
+
+	/* wait for FPGA ready */
+	if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
+		for (k = 0; k < 2; ++k) {
+			if (!dm_gpio_get_value(&gpio))
+				break;
+			mdelay(100);
+		}
+	}
+#endif
+}
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+	return &ddr_topology_map;
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	/* Configure MPP */
+	writel(0x00111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x40040000, MVEBU_MPP_BASE + 0x04);
+	writel(0x00466444, MVEBU_MPP_BASE + 0x08);
+	writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
+	writel(0x44400000, MVEBU_MPP_BASE + 0x10);
+	writel(0x20000334, MVEBU_MPP_BASE + 0x14);
+	writel(0x40000000, MVEBU_MPP_BASE + 0x18);
+	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+void init_host_phys(struct mii_dev *bus)
+{
+	uint k;
+
+	for (k = 0; k < 2; ++k) {
+		struct phy_device *phydev;
+
+		phydev = phy_find_by_mask(bus, 1 << k,
+					  PHY_INTERFACE_MODE_SGMII);
+
+		if (phydev)
+			phy_config(phydev);
+	}
+}
+
+int ccdc_eth_init(void)
+{
+	uint k;
+	uint octo_phy_mask = 0;
+	int ret;
+	struct mii_dev *bus;
+
+	/* Init SoC's phys */
+	bus = miiphy_get_dev_by_name("ethernet@34000");
+
+	if (bus)
+		init_host_phys(bus);
+
+	bus = miiphy_get_dev_by_name("ethernet@70000");
+
+	if (bus)
+		init_host_phys(bus);
+
+	/* Init octo phys */
+	octo_phy_mask = calculate_octo_phy_mask();
+
+	printf("IHS PHYS: %08x", octo_phy_mask);
+
+	ret = init_octo_phys(octo_phy_mask);
+
+	if (ret)
+		return ret;
+
+	printf("\n");
+
+	if (!get_fpga()) {
+		puts("fpga was NULL\n");
+		return 1;
+	}
+
+	/* reset all FPGA-QSGMII instances */
+	for (k = 0; k < 80; ++k)
+		writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
+
+	udelay(100);
+
+	for (k = 0; k < 80; ++k)
+		writel(0, get_fpga()->qsgmii_port_state[k]);
+	return 0;
+}
+
+#endif
+
+int board_late_init(void)
+{
+#ifndef CONFIG_SPL_BUILD
+	hydra_initialize();
+#endif
+	return 0;
+}
+
+int board_fix_fdt(void *rw_fdt_blob)
+{
+	struct udevice *bus = NULL;
+	uint k;
+	char name[64];
+	int err;
+
+	err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
+
+	if (err) {
+		printf("Could not get I2C bus.\n");
+		return err;
+	}
+
+	for (k = 0x21; k <= 0x26; k++) {
+		snprintf(name, 64,
+			 "/soc/internal-regs/i2c@11000/pca9698@%02x", k);
+
+		if (!dm_i2c_simple_probe(bus, k))
+			fdt_disable_by_ofname(rw_fdt_blob, name);
+	}
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+#ifndef CONFIG_SPL_BUILD
+	ccdc_eth_init();
+#endif
+	if (tpm_init() || tpm_startup(TPM_ST_CLEAR) ||
+	    tpm_continue_self_test()) {
+		return 1;
+	}
+
+	mdelay(37);
+
+	flush_keys();
+	load_and_run_keyprog();
+
+	return 0;
+}
diff --git a/board/gdsys/a38x/dt_helpers.c b/board/gdsys/a38x/dt_helpers.c
new file mode 100644
index 0000000..759d82a
--- /dev/null
+++ b/board/gdsys/a38x/dt_helpers.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+
+int fdt_disable_by_ofname(void *rw_fdt_blob, char *ofname)
+{
+	int offset = fdt_path_offset(rw_fdt_blob, ofname);
+
+	return fdt_status_disabled(rw_fdt_blob, offset);
+}
+
+bool dm_i2c_simple_probe(struct udevice *bus, uint chip_addr)
+{
+	struct udevice *dev;
+
+	return !dm_i2c_probe(bus, chip_addr, DM_I2C_CHIP_RD_ADDRESS |
+			     DM_I2C_CHIP_WR_ADDRESS, &dev);
+}
+
+int request_gpio_by_name(struct gpio_desc *gpio, const char *gpio_dev_name,
+			 uint offset, char *gpio_name)
+{
+	struct udevice *gpio_dev = NULL;
+
+	if (uclass_get_device_by_name(UCLASS_GPIO, gpio_dev_name, &gpio_dev))
+		return 1;
+
+	gpio->dev = gpio_dev;
+	gpio->offset = offset;
+	gpio->flags = 0;
+
+	return dm_gpio_request(gpio, gpio_name);
+}
+
diff --git a/board/gdsys/a38x/dt_helpers.h b/board/gdsys/a38x/dt_helpers.h
new file mode 100644
index 0000000..1b95262
--- /dev/null
+++ b/board/gdsys/a38x/dt_helpers.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __DT_HELPERS_H
+#define __DT_HELPERS_H
+
+int fdt_disable_by_ofname(void *rw_fdt_blob, char *ofname);
+bool dm_i2c_simple_probe(struct udevice *bus, uint chip_addr);
+int request_gpio_by_name(struct gpio_desc *gpio, const char *gpio_dev_name,
+			 uint offset, char *gpio_name);
+
+#endif /* __DT_HELPERS_H */
diff --git a/board/gdsys/a38x/hre.c b/board/gdsys/a38x/hre.c
new file mode 100644
index 0000000..1689d44
--- /dev/null
+++ b/board/gdsys/a38x/hre.c
@@ -0,0 +1,516 @@
+/*
+ * (C) Copyright 2013
+ * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <fs.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <tpm.h>
+#include <u-boot/sha1.h>
+#include <asm/byteorder.h>
+#include <asm/unaligned.h>
+#include <pca9698.h>
+
+#include "hre.h"
+
+/* other constants */
+enum {
+	ESDHC_BOOT_IMAGE_SIG_OFS	= 0x40,
+	ESDHC_BOOT_IMAGE_SIZE_OFS	= 0x48,
+	ESDHC_BOOT_IMAGE_ADDR_OFS	= 0x50,
+	ESDHC_BOOT_IMAGE_TARGET_OFS	= 0x58,
+	ESDHC_BOOT_IMAGE_ENTRY_OFS	= 0x60,
+};
+
+enum {
+	I2C_SOC_0 = 0,
+	I2C_SOC_1 = 1,
+};
+
+enum access_mode {
+	HREG_NONE	= 0,
+	HREG_RD		= 1,
+	HREG_WR		= 2,
+	HREG_RDWR	= 3,
+};
+
+/* register constants */
+enum {
+	FIX_HREG_DEVICE_ID_HASH	= 0,
+	FIX_HREG_UNUSED1	= 1,
+	FIX_HREG_UNUSED2	= 2,
+	FIX_HREG_VENDOR		= 3,
+	COUNT_FIX_HREGS
+};
+
+static struct h_reg pcr_hregs[24];
+static struct h_reg fix_hregs[COUNT_FIX_HREGS];
+static struct h_reg var_hregs[8];
+
+/* hre opcodes */
+enum {
+	/* opcodes w/o data */
+	HRE_NOP		= 0x00,
+	HRE_SYNC	= HRE_NOP,
+	HRE_CHECK0	= 0x01,
+	/* opcodes w/o data, w/ sync dst */
+	/* opcodes w/ data */
+	HRE_LOAD	= 0x81,
+	/* opcodes w/data, w/sync dst */
+	HRE_XOR		= 0xC1,
+	HRE_AND		= 0xC2,
+	HRE_OR		= 0xC3,
+	HRE_EXTEND	= 0xC4,
+	HRE_LOADKEY	= 0xC5,
+};
+
+/* hre errors */
+enum {
+	HRE_E_OK	= 0,
+	HRE_E_TPM_FAILURE,
+	HRE_E_INVALID_HREG,
+};
+
+static uint64_t device_id;
+static uint64_t device_cl;
+static uint64_t device_type;
+
+static uint32_t platform_key_handle;
+
+static uint32_t hre_tpm_err;
+static int hre_err = HRE_E_OK;
+
+#define IS_PCR_HREG(spec) ((spec) & 0x20)
+#define IS_FIX_HREG(spec) (((spec) & 0x38) == 0x08)
+#define IS_VAR_HREG(spec) (((spec) & 0x38) == 0x10)
+#define HREG_IDX(spec) ((spec) & (IS_PCR_HREG(spec) ? 0x1f : 0x7))
+
+static const uint8_t vendor[] = "Guntermann & Drunck";
+
+/**
+ * @brief get the size of a given (TPM) NV area
+ * @param index	NV index of the area to get size for
+ * @param size	pointer to the size
+ * @return 0 on success, != 0 on error
+ */
+static int get_tpm_nv_size(uint32_t index, uint32_t *size)
+{
+	uint32_t err;
+	uint8_t info[72];
+	uint8_t *ptr;
+	uint16_t v16;
+
+	err = tpm_get_capability(TPM_CAP_NV_INDEX, index,
+		info, sizeof(info));
+	if (err) {
+		printf("tpm_get_capability(CAP_NV_INDEX, %08x) failed: %u\n",
+		       index, err);
+		return 1;
+	}
+
+	/* skip tag and nvIndex */
+	ptr = info + 6;
+	/* skip 2 pcr info fields */
+	v16 = get_unaligned_be16(ptr);
+	ptr += 2 + v16 + 1 + 20;
+	v16 = get_unaligned_be16(ptr);
+	ptr += 2 + v16 + 1 + 20;
+	/* skip permission and flags */
+	ptr += 6 + 3;
+
+	*size = get_unaligned_be32(ptr);
+	return 0;
+}
+
+/**
+ * @brief search for a key by usage auth and pub key hash.
+ * @param auth	usage auth of the key to search for
+ * @param pubkey_digest	(SHA1) hash of the pub key structure of the key
+ * @param[out] handle	the handle of the key iff found
+ * @return 0 if key was found in TPM; != 0 if not.
+ */
+static int find_key(const uint8_t auth[20], const uint8_t pubkey_digest[20],
+		uint32_t *handle)
+{
+	uint16_t key_count;
+	uint32_t key_handles[10];
+	uint8_t buf[288];
+	uint8_t *ptr;
+	uint32_t err;
+	uint8_t digest[20];
+	size_t buf_len;
+	unsigned int i;
+
+	/* fetch list of already loaded keys in the TPM */
+	err = tpm_get_capability(TPM_CAP_HANDLE, TPM_RT_KEY, buf, sizeof(buf));
+	if (err)
+		return -1;
+	key_count = get_unaligned_be16(buf);
+	ptr = buf + 2;
+	for (i = 0; i < key_count; ++i, ptr += 4)
+		key_handles[i] = get_unaligned_be32(ptr);
+
+	/* now search a(/ the) key which we can access with the given auth */
+	for (i = 0; i < key_count; ++i) {
+		buf_len = sizeof(buf);
+		err = tpm_get_pub_key_oiap(key_handles[i], auth, buf, &buf_len);
+		if (err && err != TPM_AUTHFAIL)
+			return -1;
+		if (err)
+			continue;
+		sha1_csum(buf, buf_len, digest);
+		if (!memcmp(digest, pubkey_digest, 20)) {
+			*handle = key_handles[i];
+			return 0;
+		}
+	}
+	return 1;
+}
+
+/**
+ * @brief read CCDM common data from TPM NV
+ * @return 0 if CCDM common data was found and read, !=0 if something failed.
+ */
+static int read_common_data(void)
+{
+	uint32_t size = 0;
+	uint32_t err;
+	uint8_t buf[256];
+	sha1_context ctx;
+
+	if (get_tpm_nv_size(NV_COMMON_DATA_INDEX, &size) ||
+	    size < NV_COMMON_DATA_MIN_SIZE)
+		return 1;
+	err = tpm_nv_read_value(NV_COMMON_DATA_INDEX,
+		buf, min(sizeof(buf), size));
+	if (err) {
+		printf("tpm_nv_read_value() failed: %u\n", err);
+		return 1;
+	}
+
+	device_id = get_unaligned_be64(buf);
+	device_cl = get_unaligned_be64(buf + 8);
+	device_type = get_unaligned_be64(buf + 16);
+
+	sha1_starts(&ctx);
+	sha1_update(&ctx, buf, 24);
+	sha1_finish(&ctx, fix_hregs[FIX_HREG_DEVICE_ID_HASH].digest);
+	fix_hregs[FIX_HREG_DEVICE_ID_HASH].valid = true;
+
+	platform_key_handle = get_unaligned_be32(buf + 24);
+
+	return 0;
+}
+
+/**
+ * @brief get pointer to  hash register by specification
+ * @param spec	specification of a hash register
+ * @return pointer to hash register or NULL if @a spec does not qualify a
+ * valid hash register; NULL else.
+ */
+static struct h_reg *get_hreg(uint8_t spec)
+{
+	uint8_t idx;
+
+	idx = HREG_IDX(spec);
+	if (IS_FIX_HREG(spec)) {
+		if (idx < ARRAY_SIZE(fix_hregs))
+			return fix_hregs + idx;
+		hre_err = HRE_E_INVALID_HREG;
+	} else if (IS_PCR_HREG(spec)) {
+		if (idx < ARRAY_SIZE(pcr_hregs))
+			return pcr_hregs + idx;
+		hre_err = HRE_E_INVALID_HREG;
+	} else if (IS_VAR_HREG(spec)) {
+		if (idx < ARRAY_SIZE(var_hregs))
+			return var_hregs + idx;
+		hre_err = HRE_E_INVALID_HREG;
+	}
+	return NULL;
+}
+
+/**
+ * @brief get pointer of a hash register by specification and usage.
+ * @param spec	specification of a hash register
+ * @param mode	access mode (read or write or read/write)
+ * @return pointer to hash register if found and valid; NULL else.
+ *
+ * This func uses @a get_reg() to determine the hash register for a given spec.
+ * If a register is found it is validated according to the desired access mode.
+ * The value of automatic registers (PCR register and fixed registers) is
+ * loaded or computed on read access.
+ */
+static struct h_reg *access_hreg(uint8_t spec, enum access_mode mode)
+{
+	struct h_reg *result;
+
+	result = get_hreg(spec);
+	if (!result)
+		return NULL;
+
+	if (mode & HREG_WR) {
+		if (IS_FIX_HREG(spec)) {
+			hre_err = HRE_E_INVALID_HREG;
+			return NULL;
+		}
+	}
+	if (mode & HREG_RD) {
+		if (!result->valid) {
+			if (IS_PCR_HREG(spec)) {
+				hre_tpm_err = tpm_pcr_read(HREG_IDX(spec),
+					result->digest, 20);
+				result->valid = (hre_tpm_err == TPM_SUCCESS);
+			} else if (IS_FIX_HREG(spec)) {
+				switch (HREG_IDX(spec)) {
+				case FIX_HREG_DEVICE_ID_HASH:
+					read_common_data();
+					break;
+				case FIX_HREG_VENDOR:
+					memcpy(result->digest, vendor, 20);
+					result->valid = true;
+					break;
+				}
+			} else {
+				result->valid = true;
+			}
+		}
+		if (!result->valid) {
+			hre_err = HRE_E_INVALID_HREG;
+			return NULL;
+		}
+	}
+
+	return result;
+}
+
+static void *compute_and(void *_dst, const void *_src, size_t n)
+{
+	uint8_t *dst = _dst;
+	const uint8_t *src = _src;
+	size_t i;
+
+	for (i = n; i-- > 0; )
+		*dst++ &= *src++;
+
+	return _dst;
+}
+
+static void *compute_or(void *_dst, const void *_src, size_t n)
+{
+	uint8_t *dst = _dst;
+	const uint8_t *src = _src;
+	size_t i;
+
+	for (i = n; i-- > 0; )
+		*dst++ |= *src++;
+
+	return _dst;
+}
+
+static void *compute_xor(void *_dst, const void *_src, size_t n)
+{
+	uint8_t *dst = _dst;
+	const uint8_t *src = _src;
+	size_t i;
+
+	for (i = n; i-- > 0; )
+		*dst++ ^= *src++;
+
+	return _dst;
+}
+
+static void *compute_extend(void *_dst, const void *_src, size_t n)
+{
+	uint8_t digest[20];
+	sha1_context ctx;
+
+	sha1_starts(&ctx);
+	sha1_update(&ctx, _dst, n);
+	sha1_update(&ctx, _src, n);
+	sha1_finish(&ctx, digest);
+	memcpy(_dst, digest, min(n, sizeof(digest)));
+
+	return _dst;
+}
+
+static int hre_op_loadkey(struct h_reg *src_reg, struct h_reg *dst_reg,
+		const void *key, size_t key_size)
+{
+	uint32_t parent_handle;
+	uint32_t key_handle;
+
+	if (!src_reg || !dst_reg || !src_reg->valid || !dst_reg->valid)
+		return -1;
+	if (find_key(src_reg->digest, dst_reg->digest, &parent_handle))
+		return -1;
+	hre_tpm_err = tpm_load_key2_oiap(parent_handle, key, key_size,
+		src_reg->digest, &key_handle);
+	if (hre_tpm_err) {
+		hre_err = HRE_E_TPM_FAILURE;
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief executes the next opcode on the hash register engine.
+ * @param[in,out] ip	pointer to the opcode (instruction pointer)
+ * @param[in,out] code_size	(remaining) size of the code
+ * @return new instruction pointer on success, NULL on error.
+ */
+static const uint8_t *hre_execute_op(const uint8_t **ip, size_t *code_size)
+{
+	bool dst_modified = false;
+	uint32_t ins;
+	uint8_t opcode;
+	uint8_t src_spec;
+	uint8_t dst_spec;
+	uint16_t data_size;
+	struct h_reg *src_reg, *dst_reg;
+	uint8_t buf[20];
+	const uint8_t *src_buf, *data;
+	uint8_t *ptr;
+	int i;
+	void * (*bin_func)(void *, const void *, size_t);
+
+	if (*code_size < 4)
+		return NULL;
+
+	ins = get_unaligned_be32(*ip);
+	opcode = **ip;
+	data = *ip + 4;
+	src_spec = (ins >> 18) & 0x3f;
+	dst_spec = (ins >> 12) & 0x3f;
+	data_size = (ins & 0x7ff);
+
+	debug("HRE: ins=%08x (op=%02x, s=%02x, d=%02x, L=%d)\n", ins,
+	      opcode, src_spec, dst_spec, data_size);
+
+	if ((opcode & 0x80) && (data_size + 4) > *code_size)
+		return NULL;
+
+	src_reg = access_hreg(src_spec, HREG_RD);
+	if (hre_err || hre_tpm_err)
+		return NULL;
+	dst_reg = access_hreg(dst_spec, (opcode & 0x40) ? HREG_RDWR : HREG_WR);
+	if (hre_err || hre_tpm_err)
+		return NULL;
+
+	switch (opcode) {
+	case HRE_NOP:
+		goto end;
+	case HRE_CHECK0:
+		if (src_reg) {
+			for (i = 0; i < 20; ++i) {
+				if (src_reg->digest[i])
+					return NULL;
+			}
+		}
+		break;
+	case HRE_LOAD:
+		bin_func = memcpy;
+		goto do_bin_func;
+	case HRE_XOR:
+		bin_func = compute_xor;
+		goto do_bin_func;
+	case HRE_AND:
+		bin_func = compute_and;
+		goto do_bin_func;
+	case HRE_OR:
+		bin_func = compute_or;
+		goto do_bin_func;
+	case HRE_EXTEND:
+		bin_func = compute_extend;
+do_bin_func:
+		if (!dst_reg)
+			return NULL;
+		if (src_reg) {
+			src_buf = src_reg->digest;
+		} else {
+			if (!data_size) {
+				memset(buf, 0, 20);
+				src_buf = buf;
+			} else if (data_size == 1) {
+				memset(buf, *data, 20);
+				src_buf = buf;
+			} else if (data_size >= 20) {
+				src_buf = data;
+			} else {
+				src_buf = buf;
+				for (ptr = (uint8_t *)src_buf, i = 20; i > 0;
+					i -= data_size, ptr += data_size)
+					memcpy(ptr, data,
+					       min_t(size_t, i, data_size));
+			}
+		}
+		bin_func(dst_reg->digest, src_buf, 20);
+		dst_reg->valid = true;
+		dst_modified = true;
+		break;
+	case HRE_LOADKEY:
+		if (hre_op_loadkey(src_reg, dst_reg, data, data_size))
+			return NULL;
+		break;
+	default:
+		return NULL;
+	}
+
+	if (dst_reg && dst_modified && IS_PCR_HREG(dst_spec)) {
+		hre_tpm_err = tpm_extend(HREG_IDX(dst_spec), dst_reg->digest,
+			dst_reg->digest);
+		if (hre_tpm_err) {
+			hre_err = HRE_E_TPM_FAILURE;
+			return NULL;
+		}
+	}
+end:
+	*ip += 4;
+	*code_size -= 4;
+	if (opcode & 0x80) {
+		*ip += data_size;
+		*code_size -= data_size;
+	}
+
+	return *ip;
+}
+
+/**
+ * @brief runs a program on the hash register engine.
+ * @param code		pointer to the (HRE) code.
+ * @param code_size	size of the code (in bytes).
+ * @return 0 on success, != 0 on failure.
+ */
+int hre_run_program(const uint8_t *code, size_t code_size)
+{
+	size_t code_left;
+	const uint8_t *ip = code;
+
+	code_left = code_size;
+	hre_tpm_err = 0;
+	hre_err = HRE_E_OK;
+	while (code_left > 0)
+		if (!hre_execute_op(&ip, &code_left))
+			return -1;
+
+	return hre_err;
+}
+
+int hre_verify_program(struct key_program *prg)
+{
+	uint32_t crc;
+
+	crc = crc32(0, prg->code, prg->code_size);
+
+	if (crc != prg->code_crc) {
+		printf("HRC crc mismatch: %08x != %08x\n",
+		       crc, prg->code_crc);
+		return 1;
+	}
+	return 0;
+}
diff --git a/board/gdsys/a38x/hre.h b/board/gdsys/a38x/hre.h
new file mode 100644
index 0000000..84ce279
--- /dev/null
+++ b/board/gdsys/a38x/hre.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2013
+ * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __HRE_H
+#define __HRE_H
+
+struct key_program {
+	uint32_t magic;
+	uint32_t code_crc;
+	uint32_t code_size;
+	uint8_t code[];
+};
+
+struct h_reg {
+	bool valid;
+	uint8_t digest[20];
+};
+
+/* CCDM specific contants */
+enum {
+	/* NV indices */
+	NV_COMMON_DATA_INDEX	= 0x40000001,
+	/* magics for key blob chains */
+	MAGIC_KEY_PROGRAM	= 0x68726500,
+	MAGIC_HMAC		= 0x68616300,
+	MAGIC_END_OF_CHAIN	= 0x00000000,
+	/* sizes */
+	NV_COMMON_DATA_MIN_SIZE	= 3 * sizeof(uint64_t) + 2 * sizeof(uint16_t),
+};
+
+int hre_verify_program(struct key_program *prg);
+int hre_run_program(const uint8_t *code, size_t code_size);
+
+#endif /* __HRE_H */
diff --git a/board/gdsys/a38x/hydra.c b/board/gdsys/a38x/hydra.c
new file mode 100644
index 0000000..fa50ad2
--- /dev/null
+++ b/board/gdsys/a38x/hydra.c
@@ -0,0 +1,138 @@
+#include <common.h>
+#include <console.h> /* ctrlc */
+#include <asm/io.h>
+
+#include "hydra.h"
+
+enum {
+	HWVER_100 = 0,
+	HWVER_110 = 1,
+	HWVER_120 = 2,
+};
+
+static struct pci_device_id hydra_supported[] = {
+	{ 0x6d5e, 0xcdc1 },
+	{}
+};
+
+static struct ihs_fpga *fpga;
+
+struct ihs_fpga *get_fpga(void)
+{
+	return fpga;
+}
+
+void print_hydra_version(uint index)
+{
+	u32 versions = readl(&fpga->versions);
+	u32 fpga_version = readl(&fpga->fpga_version);
+
+	uint hardware_version = versions & 0xf;
+
+	printf("FPGA%u: mapped to %p\n       ", index, fpga);
+
+	switch (hardware_version) {
+	case HWVER_100:
+		printf("HW-Ver 1.00\n");
+		break;
+
+	case HWVER_110:
+		printf("HW-Ver 1.10\n");
+		break;
+
+	case HWVER_120:
+		printf("HW-Ver 1.20\n");
+		break;
+
+	default:
+		printf("HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d\n",
+	       fpga_version / 100, fpga_version % 100);
+}
+
+void hydra_initialize(void)
+{
+	uint i;
+	pci_dev_t devno;
+
+	/* Find and probe all the matching PCI devices */
+	for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
+		u32 val;
+
+		/* Try to enable I/O accesses and bus-mastering */
+		val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+		pci_write_config_dword(devno, PCI_COMMAND, val);
+
+		/* Make sure it worked */
+		pci_read_config_dword(devno, PCI_COMMAND, &val);
+		if (!(val & PCI_COMMAND_MEMORY)) {
+			puts("Can't enable I/O memory\n");
+			continue;
+		}
+		if (!(val & PCI_COMMAND_MASTER)) {
+			puts("Can't enable bus-mastering\n");
+			continue;
+		}
+
+		/* read FPGA details */
+		fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
+				   PCI_REGION_MEM);
+
+		print_hydra_version(i);
+	}
+}
+
+#define REFL_PATTERN (0xdededede)
+#define REFL_PATTERN_INV (~REFL_PATTERN)
+
+int do_hydrate(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	uint k = 0;
+	void __iomem *pcie2_base = (void __iomem *)(MVEBU_REG_PCIE_BASE +
+						    0x4000);
+
+	if (!fpga)
+		return -1;
+
+	while (1) {
+		u32 res;
+
+		writel(REFL_PATTERN, &fpga->reflection_low);
+		res = readl(&fpga->reflection_low);
+		if (res != REFL_PATTERN_INV)
+			printf("round %u: read %08x, expected %08x\n",
+			       k, res, REFL_PATTERN_INV);
+		writel(REFL_PATTERN_INV, &fpga->reflection_low);
+		res = readl(&fpga->reflection_low);
+		if (res != REFL_PATTERN)
+			printf("round %u: read %08x, expected %08x\n",
+			       k, res, REFL_PATTERN);
+
+		res = readl(pcie2_base + 0x118) & 0x1f;
+		if (res)
+			printf("FrstErrPtr %u\n", res);
+		res = readl(pcie2_base + 0x104);
+		if (res) {
+			printf("Uncorrectable Error Status 0x%08x\n", res);
+			writel(res, pcie2_base + 0x104);
+		}
+
+		if (!(++k % 10000))
+			printf("round %u\n", k);
+
+		if (ctrlc())
+			break;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	hydrate,	1,	0,	do_hydrate,
+	"hydra reflection test",
+	"hydra reflection test"
+);
diff --git a/board/gdsys/a38x/hydra.h b/board/gdsys/a38x/hydra.h
new file mode 100644
index 0000000..26562a5
--- /dev/null
+++ b/board/gdsys/a38x/hydra.h
@@ -0,0 +1,14 @@
+struct ihs_fpga {
+	u32 reflection_low;		/* 0x0000 */
+	u32 versions;			/* 0x0004 */
+	u32 fpga_version;		/* 0x0008 */
+	u32 fpga_features;		/* 0x000c */
+	u32 reserved0[4];		/* 0x0010 */
+	u32 control;			/* 0x0020 */
+	u32 reserved1[375];		/* 0x0024 */
+	u32 qsgmii_port_state[80];	/* 0x0600 */
+};
+
+void print_hydra_version(uint index);
+void hydra_initialize(void);
+struct ihs_fpga *get_fpga(void);
diff --git a/board/gdsys/a38x/ihs_phys.c b/board/gdsys/a38x/ihs_phys.c
new file mode 100644
index 0000000..494de18
--- /dev/null
+++ b/board/gdsys/a38x/ihs_phys.c
@@ -0,0 +1,355 @@
+#include <common.h>
+#include <dm.h>
+#include <miiphy.h>
+#include <asm-generic/gpio.h>
+
+#include "ihs_phys.h"
+#include "dt_helpers.h"
+
+enum {
+	PORTTYPE_MAIN_CAT,
+	PORTTYPE_TOP_CAT,
+	PORTTYPE_16C_16F,
+	PORTTYPE_UNKNOWN
+};
+
+static struct porttype {
+	bool phy_invert_in_pol;
+	bool phy_invert_out_pol;
+} porttypes[] = {
+	{ true, false },
+	{ false, true },
+	{ false, false },
+};
+
+static void ihs_phy_config(struct phy_device *phydev, bool qinpn, bool qoutpn)
+{
+	u16 reg;
+
+	phy_config(phydev);
+
+	/* enable QSGMII autonegotiation with flow control */
+	phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0004);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 16);
+	reg |= (3 << 6);
+	phy_write(phydev, MDIO_DEVAD_NONE, 16, reg);
+
+	/*
+	 * invert QSGMII Q_INP/N and Q_OUTP/N if required
+	 * and perform global reset
+	 */
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 26);
+	if (qinpn)
+		reg |= (1 << 13);
+	if (qoutpn)
+		reg |= (1 << 12);
+	reg |= (1 << 15);
+	phy_write(phydev, MDIO_DEVAD_NONE, 26, reg);
+
+	/* advertise 1000BASE-T full-duplex only  */
+	phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 4);
+	reg &= ~0x1e0;
+	phy_write(phydev, MDIO_DEVAD_NONE, 4, reg);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 9);
+	reg = (reg & ~0x300) | 0x200;
+	phy_write(phydev, MDIO_DEVAD_NONE, 9, reg);
+
+	/* copper power up */
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 16);
+	reg &= ~0x0004;
+	phy_write(phydev, MDIO_DEVAD_NONE, 16, reg);
+}
+
+uint calculate_octo_phy_mask(void)
+{
+	uint k;
+	uint octo_phy_mask = 0;
+	struct gpio_desc gpio = {};
+	char gpio_name[64];
+	static const char * const dev_name[] = {"pca9698@23", "pca9698@21",
+						"pca9698@24", "pca9698@25",
+						"pca9698@26"};
+
+	/* mark all octo phys that should be present */
+	for (k = 0; k < 5; ++k) {
+		snprintf(gpio_name, 64, "cat-gpio-%u", k);
+
+		if (request_gpio_by_name(&gpio, dev_name[k], 0x20, gpio_name))
+			continue;
+
+		/* check CAT flag */
+		if (dm_gpio_get_value(&gpio))
+			octo_phy_mask |= (1 << (k * 2));
+		else
+			/* If CAT == 0, there's no second octo phy -> skip */
+			continue;
+
+		snprintf(gpio_name, 64, "second-octo-gpio-%u", k);
+
+		if (request_gpio_by_name(&gpio, dev_name[k], 0x27, gpio_name)) {
+			/* default: second octo phy is present */
+			octo_phy_mask |= (1 << (k * 2 + 1));
+			continue;
+		}
+
+		if (dm_gpio_get_value(&gpio) == 0)
+			octo_phy_mask |= (1 << (k * 2 + 1));
+	}
+
+	return octo_phy_mask;
+}
+
+int register_miiphy_bus(uint k, struct mii_dev **bus)
+{
+	int retval;
+	struct mii_dev *mdiodev = mdio_alloc();
+	char *name = bb_miiphy_buses[k].name;
+
+	if (!mdiodev)
+		return -ENOMEM;
+	strncpy(mdiodev->name,
+		name,
+		MDIO_NAME_LEN);
+	mdiodev->read = bb_miiphy_read;
+	mdiodev->write = bb_miiphy_write;
+
+	retval = mdio_register(mdiodev);
+	if (retval < 0)
+		return retval;
+	*bus = miiphy_get_dev_by_name(name);
+
+	return 0;
+}
+
+struct porttype *get_porttype(uint octo_phy_mask, uint k)
+{
+	uint octo_index = k * 4;
+
+	if (!k) {
+		if (octo_phy_mask & 0x01)
+			return &porttypes[PORTTYPE_MAIN_CAT];
+		else if (!(octo_phy_mask & 0x03))
+			return &porttypes[PORTTYPE_16C_16F];
+	} else {
+		if (octo_phy_mask & (1 << octo_index))
+			return &porttypes[PORTTYPE_TOP_CAT];
+	}
+
+	return NULL;
+}
+
+int init_single_phy(struct porttype *porttype, struct mii_dev *bus,
+		    uint bus_idx, uint m, uint phy_idx)
+{
+	struct phy_device *phydev = phy_find_by_mask(
+		bus, 1 << (m * 8 + phy_idx),
+		PHY_INTERFACE_MODE_MII);
+
+	printf(" %u", bus_idx * 32 + m * 8 + phy_idx);
+
+	if (!phydev)
+		puts("!");
+	else
+		ihs_phy_config(phydev, porttype->phy_invert_in_pol,
+			       porttype->phy_invert_out_pol);
+
+	return 0;
+}
+
+int init_octo_phys(uint octo_phy_mask)
+{
+	uint bus_idx;
+
+	/* there are up to four octo-phys on each mdio bus */
+	for (bus_idx = 0; bus_idx < bb_miiphy_buses_num; ++bus_idx) {
+		uint m;
+		uint octo_index = bus_idx * 4;
+		struct mii_dev *bus = NULL;
+		struct porttype *porttype = NULL;
+		int ret;
+
+		porttype = get_porttype(octo_phy_mask, bus_idx);
+
+		if (!porttype)
+			continue;
+
+		for (m = 0; m < 4; ++m) {
+			uint phy_idx;
+
+			/**
+			 * Register a bus device if there is at least one phy
+			 * on the current bus
+			 */
+			if (!m && octo_phy_mask & (0xf << octo_index)) {
+				ret = register_miiphy_bus(bus_idx, &bus);
+				if (ret)
+					return ret;
+			}
+
+			if (!(octo_phy_mask & BIT(octo_index + m)))
+				continue;
+
+			for (phy_idx = 0; phy_idx < 8; ++phy_idx)
+				init_single_phy(porttype, bus, bus_idx, m,
+						phy_idx);
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * MII GPIO bitbang implementation
+ * MDC MDIO bus
+ * 13  14   PHY1-4
+ * 25  45   PHY5-8
+ * 46  24   PHY9-10
+ */
+
+struct gpio_mii {
+	int index;
+	struct gpio_desc mdc_gpio;
+	struct gpio_desc mdio_gpio;
+	int mdc_num;
+	int mdio_num;
+	int mdio_value;
+} gpio_mii_set[] = {
+	{ 0, {}, {}, 13, 14, 1 },
+	{ 1, {}, {}, 25, 45, 1 },
+	{ 2, {}, {}, 46, 24, 1 },
+};
+
+static int mii_mdio_init(struct bb_miiphy_bus *bus)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+	char name[32] = {};
+	struct udevice *gpio_dev1 = NULL;
+	struct udevice *gpio_dev2 = NULL;
+
+	if (uclass_get_device_by_name(UCLASS_GPIO, "gpio@18100", &gpio_dev1) ||
+	    uclass_get_device_by_name(UCLASS_GPIO, "gpio@18140", &gpio_dev2)) {
+		printf("Could not get GPIO device.\n");
+		return 1;
+	}
+
+	if (gpio_mii->mdc_num > 31) {
+		gpio_mii->mdc_gpio.dev = gpio_dev2;
+		gpio_mii->mdc_gpio.offset = gpio_mii->mdc_num - 32;
+	} else {
+		gpio_mii->mdc_gpio.dev = gpio_dev1;
+		gpio_mii->mdc_gpio.offset = gpio_mii->mdc_num;
+	}
+	gpio_mii->mdc_gpio.flags = 0;
+	snprintf(name, 32, "bb_miiphy_bus-%d-mdc", gpio_mii->index);
+	dm_gpio_request(&gpio_mii->mdc_gpio, name);
+
+	if (gpio_mii->mdio_num > 31) {
+		gpio_mii->mdio_gpio.dev = gpio_dev2;
+		gpio_mii->mdio_gpio.offset = gpio_mii->mdio_num - 32;
+	} else {
+		gpio_mii->mdio_gpio.dev = gpio_dev1;
+		gpio_mii->mdio_gpio.offset = gpio_mii->mdio_num;
+	}
+	gpio_mii->mdio_gpio.flags = 0;
+	snprintf(name, 32, "bb_miiphy_bus-%d-mdio", gpio_mii->index);
+	dm_gpio_request(&gpio_mii->mdio_gpio, name);
+
+	dm_gpio_set_dir_flags(&gpio_mii->mdc_gpio, GPIOD_IS_OUT);
+	dm_gpio_set_value(&gpio_mii->mdc_gpio, 1);
+
+	return 0;
+}
+
+static int mii_mdio_active(struct bb_miiphy_bus *bus)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_value(&gpio_mii->mdc_gpio, gpio_mii->mdio_value);
+
+	return 0;
+}
+
+static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_IN);
+
+	return 0;
+}
+
+static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_OUT);
+	dm_gpio_set_value(&gpio_mii->mdio_gpio, v);
+	gpio_mii->mdio_value = v;
+
+	return 0;
+}
+
+static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_IN);
+	*v = (dm_gpio_get_value(&gpio_mii->mdio_gpio));
+
+	return 0;
+}
+
+static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_value(&gpio_mii->mdc_gpio, v);
+
+	return 0;
+}
+
+static int mii_delay(struct bb_miiphy_bus *bus)
+{
+	udelay(1);
+
+	return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+	{
+		.name = "ihs0",
+		.init = mii_mdio_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &gpio_mii_set[0],
+	},
+	{
+		.name = "ihs1",
+		.init = mii_mdio_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &gpio_mii_set[1],
+	},
+	{
+		.name = "ihs2",
+		.init = mii_mdio_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &gpio_mii_set[2],
+	},
+};
+
+int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
diff --git a/board/gdsys/a38x/ihs_phys.h b/board/gdsys/a38x/ihs_phys.h
new file mode 100644
index 0000000..c4bec4d
--- /dev/null
+++ b/board/gdsys/a38x/ihs_phys.h
@@ -0,0 +1,2 @@
+uint calculate_octo_phy_mask(void);
+int init_octo_phys(uint octo_phy_mask);
diff --git a/board/gdsys/a38x/keyprogram.c b/board/gdsys/a38x/keyprogram.c
new file mode 100644
index 0000000..a4a6f1c
--- /dev/null
+++ b/board/gdsys/a38x/keyprogram.c
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <tpm.h>
+#include <malloc.h>
+#include <linux/ctype.h>
+#include <asm/unaligned.h>
+
+#include "hre.h"
+
+int flush_keys(void)
+{
+	u16 key_count;
+	u8 buf[288];
+	u8 *ptr;
+	u32 err;
+	uint i;
+
+	/* fetch list of already loaded keys in the TPM */
+	err = tpm_get_capability(TPM_CAP_HANDLE, TPM_RT_KEY, buf, sizeof(buf));
+	if (err)
+		return -1;
+	key_count = get_unaligned_be16(buf);
+	ptr = buf + 2;
+	for (i = 0; i < key_count; ++i, ptr += 4) {
+		err = tpm_flush_specific(get_unaligned_be32(ptr), TPM_RT_KEY);
+		if (err && err != TPM_KEY_OWNER_CONTROL)
+			return err;
+	}
+
+	return 0;
+}
+
+int decode_hexstr(char *hexstr, u8 **result)
+{
+	int len = strlen(hexstr);
+	int bytes = len / 2;
+	int i;
+	u8 acc = 0;
+
+	if (len % 2 == 1)
+		return 1;
+
+	*result = (u8 *)malloc(bytes);
+
+	for (i = 0; i < len; i++) {
+		char cur = tolower(hexstr[i]);
+		u8 val;
+
+		if ((cur >= 'a' && cur <= 'f') || (cur >= '0' && cur <= '9')) {
+			val = cur - (cur > '9' ? 87 : 48);
+
+			if (i % 2 == 0)
+				acc = 16 * val;
+			else
+				(*result)[i / 2] = acc + val;
+		} else {
+			free(*result);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+int extract_subprogram(u8 **progdata, u32 expected_magic,
+		       struct key_program **result)
+{
+	struct key_program *prog = *result;
+	u32 magic, code_crc, code_size;
+
+	magic = get_unaligned_be32(*progdata);
+	code_crc = get_unaligned_be32(*progdata + 4);
+	code_size = get_unaligned_be32(*progdata + 8);
+
+	*progdata += 12;
+
+	if (magic != expected_magic)
+		return -1;
+
+	*result = malloc(sizeof(struct key_program) + code_size);
+
+	if (!*result)
+		return -1;
+
+	prog->magic = magic;
+	prog->code_crc = code_crc;
+	prog->code_size = code_size;
+	memcpy(prog->code, *progdata, code_size);
+
+	*progdata += code_size;
+
+	if (hre_verify_program(prog)) {
+		free(prog);
+		return -1;
+	}
+
+	return 0;
+}
+
+struct key_program *parse_and_check_keyprog(u8 *progdata)
+{
+	struct key_program *result = NULL, *hmac = NULL;
+
+	/* Part 1: Load key program */
+
+	if (extract_subprogram(&progdata, MAGIC_KEY_PROGRAM, &result))
+		return NULL;
+
+	/* Part 2: Load hmac program */
+
+	if (extract_subprogram(&progdata, MAGIC_HMAC, &hmac))
+		return NULL;
+
+	free(hmac);
+
+	return result;
+}
+
+int load_and_run_keyprog(void)
+{
+	char *cmd = NULL;
+	u8 *binprog = NULL;
+	char *hexprog;
+	struct key_program *prog;
+
+	cmd = getenv("loadkeyprogram");
+
+	if (!cmd || run_command(cmd, 0))
+		return 1;
+
+	hexprog = getenv("keyprogram");
+
+	if (decode_hexstr(hexprog, &binprog))
+		return 1;
+
+	prog = parse_and_check_keyprog(binprog);
+	free(binprog);
+
+	if (!prog)
+		return 1;
+
+	if (hre_run_program(prog->code, prog->code_size)) {
+		free(prog);
+		return 1;
+	}
+
+	printf("\nSD code ran successfully\n");
+
+	free(prog);
+
+	return 0;
+}
diff --git a/board/gdsys/a38x/keyprogram.h b/board/gdsys/a38x/keyprogram.h
new file mode 100644
index 0000000..a5ea7d3
--- /dev/null
+++ b/board/gdsys/a38x/keyprogram.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __KEYPROGRAM_H
+#define __KEYPROGRAM_H
+
+int load_and_run_keyprog(void);
+int flush_keys(void);
+
+#endif /* __KEYPROGRAM_H */
diff --git a/board/gdsys/a38x/kwbimage.cfg.in b/board/gdsys/a38x/kwbimage.cfg.in
new file mode 100644
index 0000000..72e67d7
--- /dev/null
+++ b/board/gdsys/a38x/kwbimage.cfg.in
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada 38x uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+#@BOOT_FROM
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl.bin 0000005b 00000068
diff --git a/board/gdsys/a38x/spl.c b/board/gdsys/a38x/spl.c
new file mode 100644
index 0000000..2d05a9c
--- /dev/null
+++ b/board/gdsys/a38x/spl.c
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/cpu.h>
+
+void spl_board_init(void)
+{
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+	u32 *bootrom_save = (u32 *)CONFIG_SPL_BOOTROM_SAVE;
+	u32 *regs = (u32 *)(*bootrom_save);
+
+	printf("Returning to BootROM (return address %08x)...\n", regs[13]);
+	return_to_bootrom();
+#endif
+}
diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c
index 0fce8cf..5d2ec89 100644
--- a/board/gdsys/mpc8308/sdram.c
+++ b/board/gdsys/mpc8308/sdram.c
@@ -66,17 +66,19 @@ static long fixed_sdram(void)
 	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;
 
 	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM */
 	msize = fixed_sdram();
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 2fc1144..0acf655 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -103,8 +103,9 @@ static void setup_iomux_enet(void)
 
 	/* Reset AR8033 PHY */
 	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
-	udelay(500);
+	mdelay(10);
 	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
+	mdelay(1);
 }
 
 static iomux_v3_cfg_t const usdhc2_pads[] = {
@@ -306,7 +307,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev)
 	/* set debug port address: SerDes Test and System Mode Control */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 	/* enable rgmii tx clock delay */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+	/* set the reserved bits to avoid board specific voltage peak issue*/
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 
 	return 0;
 }
diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index df3b5e7..0f0eb3a 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -410,7 +410,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	/*
 	 * Reserve regions below from DT memory node (which gets generated
@@ -442,6 +442,8 @@ void dram_init_banksize(void)
 
 	gd->bd->bi_dram[5].start = 0x22000000;
 	gd->bd->bi_dram[5].size = 0x1c000000;
+
+	return 0;
 }
 
 void reset_cpu(ulong addr)
diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c
index e7838dc..4433e8c 100644
--- a/board/ids/ids8313/ids8313.c
+++ b/board/ids/ids8313/ids8313.c
@@ -119,14 +119,14 @@ static int setup_sdram(void)
 	return msize;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	fsl_lbc_t *lbc = &im->im_lbc;
 	u32 msize = 0;
 
 	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	msize = setup_sdram();
 
@@ -134,7 +134,9 @@ phys_size_t initdram(int board_type)
 	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
 	sync();
 
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c
index 75bf1bb..3486137 100644
--- a/board/ifm/ac14xx/ac14xx.c
+++ b/board/ifm/ac14xx/ac14xx.c
@@ -310,9 +310,12 @@ u32 sdram_init_seq[] = {
 	/* EMPTY, optional, we don't do it */
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
+	gd->ram_size = fixed_sdram(NULL, sdram_init_seq,
+				   ARRAY_SIZE(sdram_init_seq));
+
+	return 0;
 }
 
 int misc_init_r(void)
diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c
index 4fc6809..7770806 100644
--- a/board/ifm/o2dnt2/o2dnt2.c
+++ b/board/ifm/o2dnt2/o2dnt2.c
@@ -62,11 +62,11 @@ static void sdram_start(int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	struct mpc5xxx_mmap_ctl *mmap_ctl =
 		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
@@ -181,7 +181,9 @@ phys_size_t initdram(int board_type)
 	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
 		out_be32(&sdram->sdelay, 0x04);
 
-	return dramsize + dramsize2;
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
 }
 
 
diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c
index ceffef6..3479b98 100644
--- a/board/imgtec/boston/ddr.c
+++ b/board/imgtec/boston/ddr.c
@@ -10,11 +10,16 @@
 
 #include "boston-regs.h"
 
-phys_size_t initdram(int board_type)
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
 {
 	u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0);
 
-	return (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) << 30;
+	gd->ram_size = (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) <<
+			30;
+
+	return 0;
 }
 
 ulong board_get_usable_ram_top(ulong total_size)
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 4955043..de81aa0 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -19,6 +19,8 @@
 
 #include "superio.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 enum core_card {
 	CORE_UNKNOWN,
 	CORE_LV,
@@ -83,9 +85,11 @@ static enum sys_con malta_sys_con(void)
 	}
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return CONFIG_SYS_MEM_SIZE;
+	gd->ram_size = CONFIG_SYS_MEM_SIZE;
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c
index 77a1952..841d614 100644
--- a/board/imgtec/xilfpga/xilfpga.c
+++ b/board/imgtec/xilfpga/xilfpga.c
@@ -11,10 +11,14 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* initialize the DDR Controller and PHY */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	/* MIG IP block is smart and doesn't need SW
 	 * to do any init */
-	return CONFIG_SYS_SDRAM_SIZE;	/* in bytes */
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;	/* in bytes */
+
+	return 0;
 }
diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c
index 0a32f0e..88cae59 100644
--- a/board/inka4x0/inka4x0.c
+++ b/board/inka4x0/inka4x0.c
@@ -36,6 +36,8 @@
 #error "INKA4x0 SDRAM: invalid chip type specified!"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
@@ -72,12 +74,12 @@ static void sdram_start (int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *	      is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	volatile struct mpc5xxx_mmap_ctl *mm =
 		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
@@ -139,7 +141,9 @@ phys_size_t initdram (int board_type)
 	}
 #endif /* CONFIG_SYS_RAMBOOT */
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 }
 
 int checkboard (void)
diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c
index 05d673d..b8bc045 100644
--- a/board/intercontrol/digsy_mtc/digsy_mtc.c
+++ b/board/intercontrol/digsy_mtc/digsy_mtc.c
@@ -74,12 +74,12 @@ static void sdram_start(int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  *            CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
  */
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
@@ -172,7 +172,9 @@ phys_size_t initdram(int board_type)
 	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
 		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
 
-	return dramsize + dramsize2;
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/ip04/Kconfig b/board/ip04/Kconfig
deleted file mode 100644
index 670bf89..0000000
--- a/board/ip04/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_IP04
-
-config SYS_BOARD
-	default "ip04"
-
-config SYS_CONFIG_NAME
-	default "ip04"
-
-endif
diff --git a/board/ip04/MAINTAINERS b/board/ip04/MAINTAINERS
deleted file mode 100644
index c37b011..0000000
--- a/board/ip04/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IP04 BOARD
-#M:	Brent Kandetzki <brentk@teleco.com>
-S:	Orphan (since 2014-06)
-F:	board/ip04/
-F:	include/configs/ip04.h
-F:	configs/ip04_defconfig
diff --git a/board/ip04/Makefile b/board/ip04/Makefile
deleted file mode 100644
index 44fa684..0000000
--- a/board/ip04/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2010 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ip04.o
diff --git a/board/ip04/config.mk b/board/ip04/config.mk
deleted file mode 100644
index ab0fbec..0000000
--- a/board/ip04/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
-LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/ip04/ip04.c b/board/ip04/ip04.c
deleted file mode 100644
index c7bc334..0000000
--- a/board/ip04/ip04.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2007 David Rowe,
- *           (c) 2006 Ivan Danov
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
-	printf("Board: IP04 IP-PBX\n");
-	printf("       http://www.rowetel.com/ucasterisk/ip04.html\n");
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
-	return dm9000_initialize(bis);
-}
-#endif
diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c
index 2e62355..133db8c 100644
--- a/board/ipek01/ipek01.c
+++ b/board/ipek01/ipek01.c
@@ -75,12 +75,12 @@ static void sdram_start (int hi_addr)
 }
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real
+ * ATTENTION: Although partially referenced dram_init does NOT make real
  *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  *	      CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	struct mpc5xxx_mmap_ctl *mmap_ctl =
 		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
@@ -135,7 +135,9 @@ phys_size_t initdram (int board_type)
 	 */
 	out_be32 (&sdram->sdelay, 0x04);
 
-	return dramsize + dramsize2;
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
 }
 
 int checkboard (void)
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
index d56902b..ea24eaa 100644
--- a/board/jupiter/jupiter.c
+++ b/board/jupiter/jupiter.c
@@ -29,6 +29,8 @@
 #define SDRAM_CONFIG2	0x88b70004
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
@@ -71,12 +73,12 @@ static void sdram_start (int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
@@ -194,7 +196,9 @@ phys_size_t initdram (int board_type)
 		__asm__ volatile ("sync");
 	}
 
-	return dramsize + dramsize2;
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
 }
 
 int checkboard (void)
diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c
index c2a7a5f..51b4571 100644
--- a/board/keymile/km82xx/km82xx.c
+++ b/board/keymile/km82xx/km82xx.c
@@ -15,6 +15,8 @@
 #include <i2c.h>
 #include "../common/common.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
 
 /*
@@ -289,7 +291,7 @@ static long probe_sdram(memctl8260_t *memctl)
 #endif /* CONFIG_SYS_SDRAM_LIST */
 
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	memctl8260_t *memctl = &immap->im_memctl;
@@ -305,7 +307,9 @@ phys_size_t initdram(int board_type)
 
 	icache_enable();
 
-	return psize;
+	gd->ram_size = psize;
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index 154f974..8020c37 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -28,6 +28,8 @@
 
 #include "../common/common.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
 
 const qe_iop_conf_t qe_iop_conf_tab[] = {
@@ -328,13 +330,13 @@ static int fixed_sdram(void)
 	return msize;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	out_be32(&im->sysconf.ddrlaw[0].bar,
 		CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
@@ -348,7 +350,9 @@ phys_size_t initdram(int board_type)
 #endif
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize * 1024 * 1024;
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c
index 77af184..6f82e15 100644
--- a/board/keymile/kmp204x/ddr.c
+++ b/board/keymile/kmp204x/ddr.c
@@ -14,6 +14,8 @@
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
@@ -48,7 +50,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size = 0;
 
@@ -60,5 +62,7 @@ phys_size_t initdram(int board_type)
 	dram_size *= 0x100000;
 
 	debug("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c
index 7e1766c..0ad33ea 100644
--- a/board/lego/ev3/legoev3.c
+++ b/board/lego/ev3/legoev3.c
@@ -145,9 +145,7 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-#ifndef CONFIG_USE_IRQ
 	irq_init();
-#endif
 
 	/* arch number of the board */
 	/* LEGO didn't register for a unique number and uses da850evm */
diff --git a/board/liebherr/lwmon5/sdram.c b/board/liebherr/lwmon5/sdram.c
index bcb3449..4a65d74 100644
--- a/board/liebherr/lwmon5/sdram.c
+++ b/board/liebherr/lwmon5/sdram.c
@@ -25,6 +25,8 @@
 #include <asm/ppc440.h>
 #include <watchdog.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
  * region. Right now the cache should still be disabled in U-Boot because of the
@@ -142,10 +144,10 @@ static void program_ecc(u32 start_address,
 
 /*************************************************************************
  *
- * initdram -- 440EPx's DDR controller is a DENALI Core
+ * dram_init -- 440EPx's DDR controller is a DENALI Core
  *
  ************************************************************************/
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	/* CL=4 */
 	mtsdram(DDR0_02, 0x00000000);
@@ -241,5 +243,7 @@ phys_size_t initdram (int board_type)
 	 */
 	set_mcsr(get_mcsr());
 
-	return (CONFIG_SYS_MBYTES_SDRAM << 20);
+	gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
+
+	return 0;
 }
diff --git a/board/micronas/vct/vct.c b/board/micronas/vct/vct.c
index 0745cee..8bf8d5f 100644
--- a/board/micronas/vct/vct.c
+++ b/board/micronas/vct/vct.c
@@ -28,6 +28,8 @@
 #define BOARD_NAME_ADD	" NOR"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int board_early_init_f(void)
 {
 	/*
@@ -59,10 +61,12 @@ void _machine_restart(void)
  * SDRAM is already configured by the bootstrap code, only return the
  * auto-detected size here
  */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 			    CONFIG_SYS_MBYTES_SDRAM << 20);
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/mini-box/picosam9g45/picosam9g45.c b/board/mini-box/picosam9g45/picosam9g45.c
index 32ba9c6..5eb2ad7 100644
--- a/board/mini-box/picosam9g45/picosam9g45.c
+++ b/board/mini-box/picosam9g45/picosam9g45.c
@@ -283,7 +283,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
@@ -291,6 +291,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
 							PHYS_SDRAM_2_SIZE);
+
+	return 0;
 }
 
 #ifdef CONFIG_RESET_PHY_R
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
index 7fa81b8..7883a17 100644
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@@ -19,6 +19,8 @@
 #include <status_led.h>
 #endif /* CONFIG_LED_STATUS */
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Kollmorgen DPR initialization data */
 struct init_elem {
 	unsigned long addr;
@@ -116,7 +118,7 @@ static void sdram_start(int hi_addr)
 /*
  * Initalize SDRAM - configure SDRAM controller, detect memory size.
  */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 #ifndef CONFIG_SYS_RAMBOOT
@@ -172,7 +174,9 @@ phys_size_t initdram(int board_type)
 #endif /* CONFIG_SYS_RAMBOOT */
 
 	/* return total ram size */
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 }
 
 
diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c
index da36f63..05c477d 100644
--- a/board/mpc8308_p1m/sdram.c
+++ b/board/mpc8308_p1m/sdram.c
@@ -61,7 +61,7 @@ static long fixed_sdram(void)
 	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;
@@ -72,6 +72,8 @@ phys_size_t initdram(int board_type)
 	/* DDR SDRAM */
 	msize = fixed_sdram();
 
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
 }
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index 8b9892b..4d8671f 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -615,14 +615,14 @@ int checkboard (void)
 /* ------------------------------------------------------------------------- */
 /* ------------------------------------------------------------------------- */
 /*
-  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  dram_init() reads EEPROM via I2c. EEPROM contains all of
   the necessary info for SDRAM controller configuration
 */
 /* ------------------------------------------------------------------------- */
 /* ------------------------------------------------------------------------- */
 static int test_dram (unsigned long ramsize);
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 
 	unsigned long bank_reg[4], tmp, bank_size;
@@ -655,7 +655,9 @@ phys_size_t initdram (int board_type)
 	printf ("ECC ");
 
 	test_dram (TotalSize * MEGA_BYTE);
-	return (TotalSize * MEGA_BYTE);
+	gd->ram_size = TotalSize * MEGA_BYTE;
+
+	return 0;
 }
 
 /* ------------------------------------------------------------------------- */
diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c
index ddc2108..1288f74 100644
--- a/board/mpl/pati/pati.c
+++ b/board/mpl/pati/pati.c
@@ -55,6 +55,8 @@
 		asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /************************************************************************
  * Early debug routines
  */
@@ -133,7 +135,7 @@ extern int mem_test (unsigned long start, unsigned long ramsize, int quiet);
 /*
  * Get RAM size.
  */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	unsigned char board_rev;
 	unsigned long reg;
@@ -209,8 +211,10 @@ phys_size_t initdram(int board_type)
 	/* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */
 	lmr<<=2;
 	in32(CONFIG_SYS_SDRAM_BASE + lmr);
-	/* ok, we're done, return SDRAM size */
-	return ((0x400000 << sdram_table[i].sz));		/* log2 value of 4MByte  */
+	/* ok, we're done, set SDRAM size to log2 value of 4MByte*/
+	gd->ram_size = 0x400000 << sdram_table[i].sz;
+
+	return 0;
 }
 
 
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index 1bd2fbf..408518d 100644
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -605,14 +605,14 @@ int checkboard (void)
 /* ------------------------------------------------------------------------- */
 /* ------------------------------------------------------------------------- */
 /*
-  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  dram_init() reads EEPROM via I2c. EEPROM contains all of
   the necessary info for SDRAM controller configuration
 */
 /* ------------------------------------------------------------------------- */
 /* ------------------------------------------------------------------------- */
 static int test_dram (unsigned long ramsize);
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	unsigned long bank_reg[4], tmp, bank_size;
 	int i, ds;
@@ -648,7 +648,9 @@ phys_size_t initdram (int board_type)
 	(void) get_clocks();
 	if (gd->cpu_clk > 220000000)
 		TotalSize /= 2;
-	return (TotalSize * 1024 * 1024);
+	gd->ram_size = TotalSize * 1024 * 1024;
+
+	return 0;
 }
 
 /* ------------------------------------------------------------------------- */
diff --git a/board/mqmaker/miqi_rk3288/Kconfig b/board/mqmaker/miqi_rk3288/Kconfig
new file mode 100644
index 0000000..232a112
--- /dev/null
+++ b/board/mqmaker/miqi_rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MIQI_RK3288
+
+config SYS_BOARD
+	default "miqi_rk3288"
+
+config SYS_VENDOR
+	default "mqmaker"
+
+config SYS_CONFIG_NAME
+	default "miqi_rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/mqmaker/miqi_rk3288/MAINTAINERS b/board/mqmaker/miqi_rk3288/MAINTAINERS
new file mode 100644
index 0000000..053a5e6
--- /dev/null
+++ b/board/mqmaker/miqi_rk3288/MAINTAINERS
@@ -0,0 +1,6 @@
+MIQI
+M:	Jernej Skrabec <jernej.skrabec@siol.net>
+S:	Maintained
+F:	board/mqmaker/miqi_rk3288
+F:	include/configs/miqi_rk3288.h
+F:	configs/miqi-rk3288_defconfig
diff --git a/board/mqmaker/miqi_rk3288/Makefile b/board/mqmaker/miqi_rk3288/Makefile
new file mode 100644
index 0000000..ec95aff
--- /dev/null
+++ b/board/mqmaker/miqi_rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= miqi-rk3288.o
diff --git a/board/mqmaker/miqi_rk3288/miqi-rk3288.c b/board/mqmaker/miqi_rk3288/miqi-rk3288.c
new file mode 100644
index 0000000..a82f0ae
--- /dev/null
+++ b/board/mqmaker/miqi_rk3288/miqi-rk3288.c
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	/* eMMC prior to sdcard. */
+	spl_boot_list[0] = BOOT_DEVICE_MMC2;
+	spl_boot_list[1] = BOOT_DEVICE_MMC1;
+}
diff --git a/board/munices/munices.c b/board/munices/munices.c
index 8f292ea..468eb37 100644
--- a/board/munices/munices.c
+++ b/board/munices/munices.c
@@ -11,6 +11,8 @@
 
 #include "mt48lc16m16a2-75.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
@@ -53,12 +55,12 @@ static void sdram_start (int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
@@ -125,7 +127,9 @@ phys_size_t initdram (int board_type)
 
 #endif /* CONFIG_SYS_RAMBOOT */
 
-	return dramsize + dramsize2;
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
 }
 
 int checkboard (void)
diff --git a/board/omicron/calimain/calimain.c b/board/omicron/calimain/calimain.c
index 32f2b20..80a142e 100644
--- a/board/omicron/calimain/calimain.c
+++ b/board/omicron/calimain/calimain.c
@@ -100,9 +100,7 @@ int board_init(void)
 {
 	int val;
 
-#ifndef CONFIG_USE_IRQ
 	irq_init();
-#endif
 
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
diff --git a/board/openrisc/openrisc-generic/Kconfig b/board/openrisc/openrisc-generic/Kconfig
deleted file mode 100644
index cd2a94f..0000000
--- a/board/openrisc/openrisc-generic/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OPENRISC_GENERIC
-
-config SYS_BOARD
-	default "openrisc-generic"
-
-config SYS_VENDOR
-	default "openrisc"
-
-config SYS_CONFIG_NAME
-	default "openrisc-generic"
-
-endif
diff --git a/board/openrisc/openrisc-generic/MAINTAINERS b/board/openrisc/openrisc-generic/MAINTAINERS
deleted file mode 100644
index c8dbc74..0000000
--- a/board/openrisc/openrisc-generic/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-OPENRISC-GENERIC BOARD
-M:	Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
-S:	Maintained
-F:	board/openrisc/openrisc-generic/
-F:	include/configs/openrisc-generic.h
-F:	configs/openrisc-generic_defconfig
diff --git a/board/openrisc/openrisc-generic/Makefile b/board/openrisc/openrisc-generic/Makefile
deleted file mode 100644
index 342bc80..0000000
--- a/board/openrisc/openrisc-generic/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= openrisc-generic.o
diff --git a/board/openrisc/openrisc-generic/config.mk b/board/openrisc/openrisc-generic/config.mk
deleted file mode 100644
index dd6595f..0000000
--- a/board/openrisc/openrisc-generic/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2011, Julius Baxter <julius@opencores.org>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mhard-mul -mhard-div
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
diff --git a/board/openrisc/openrisc-generic/openrisc-generic.c b/board/openrisc/openrisc-generic/openrisc-generic.c
deleted file mode 100644
index 4f82600..0000000
--- a/board/openrisc/openrisc-generic/openrisc-generic.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Based on nios2-generic.c:
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-int board_early_init_f(void)
-{
-	return 0;
-}
-
-int checkboard(void)
-{
-	printf("BOARD: %s\n", CONFIG_BOARD_NAME);
-	return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-
-#ifdef CONFIG_ETHOC
-	rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/openrisc/openrisc-generic/or1ksim.cfg b/board/openrisc/openrisc-generic/or1ksim.cfg
deleted file mode 100644
index 2bd8642..0000000
--- a/board/openrisc/openrisc-generic/or1ksim.cfg
+++ /dev/null
@@ -1,871 +0,0 @@
-/* sim.cfg -- Simulator configuration script file
-   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
-
-This file is part of OpenRISC 1000 Architectural Simulator.
-It contains the default configuration and help about configuring
-the simulator.
-
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-/* INTRODUCTION
-
-   The ork1sim has various parameters, that are set in configuration files
-   like this one. The user can switch between configurations at startup by
-   specifying the required configuration file with the -f <filename.cfg> option.
-   If no configuration file is specified or1ksim searches for the default
-   configuration file sim.cfg. First it searches for './sim.cfg'. If this
-   file is not found, it searches for '~/or1k/sim.cfg'. If this file is
-   not found too, it reverts to the built-in default configuration.
-
-   NOTE: Users should not rely on the built-in configuration, since the
-	 default configuration may differ between version.
-	 Rather create a configuration file that sets all critical values.
-
-   This file may contain (standard C) comments only - no // support.
-
-   Configure files may be be included, using:
-   include "file_name_to_include"
-
-   Like normal configuration files, the included file is divided into
-   sections. Each section is described in detail also.
-
-   Some section have subsections. One example of such a subsection is:
-
-   device <index>
-     instance specific parameters...
-   enddevice
-
-   which creates a device instance.
-*/
-
-
-/* MEMORY SECTION
-
-   This section specifies how the memory is generated and the blocks
-   it consists of.
-
-   type = random/unknown/pattern
-      Specifies the initial memory values.
-      'random' generates random memory using seed 'random_seed'.
-      'pattern' fills memory with 'pattern'.
-      'unknown' does not specify how memory should be generated,
-      leaving the memory in a undefined state. This is the fastest
-      option.
-
-   random_seed = <value>
-      random seed for randomizer, used if type = 'random'.
-
-   pattern = <value>
-      pattern to fill memory, used if type = 'pattern'.
-
-   nmemories = <value>
-      number of memory instances connected
-
-   baseaddr = <hex_value>
-      memory start address
-
-   size = <hex_value>
-      memory size
-
-   name = "<string>"
-      memory block name
-
-   ce = <value>
-      chip enable index of the memory instance
-
-   mc = <value>
-      memory controller this memory is connected to
-
-   delayr = <value>
-      cycles, required for read access, -1 if instance does not support reading
-
-   delayw = <value>
-      cycles, required for write access, -1 if instance does not support writing
-
-   log = "<filename>"
-      filename, where to log memory accesses to, no log, if log command is not specified
-*/
-
-
-section memory
-  pattern = 0x00
-  type = unknown /* Fastest */
-
-  name = "FLASH"
-  ce = 0
-  mc = 0
-  baseaddr = 0xf0000000
-  size = 0x01000000
-  delayr =  1
-  delayw = -1
-end
-
-section memory
-  pattern = 0x00
-  type = unknown /* Fastest */
-
-  name = "RAM"
-  ce = 1
-  mc = 0
-  baseaddr = 0x00000000
-  size = 0x02000000
-  delayr = 1
-  delayw = 1
-end
-
-section memory
-  pattern = 0x00
-  type = unknown /* Fastest */
-
-  name = "SRAM"
-  mc = 0
-  ce = 2
-  baseaddr = 0xa4000000
-  size = 0x00100000
-  delayr = 1
-  delayw = 2
-end
-
-
-/* IMMU SECTION
-
-    This section configures the Instruction Memory Manangement Unit
-
-    enabled = 0/1
-       '0': disabled
-       '1': enabled
-       (NOTE: UPR bit is set)
-
-    nsets = <value>
-       number of ITLB sets; must be power of two
-
-    nways = <value>
-       number of ITLB ways
-
-    pagesize = <value>
-       instruction page size; must be power of two
-
-    entrysize = <value>
-       instruction entry size in bytes
-
-    ustates = <value>
-       number of ITLB usage states (2, 3, 4 etc., max is 4)
-
-    hitdelay = <value>
-       number of cycles immu hit costs
-
-    missdelay = <value>
-       number of cycles immu miss costs
-*/
-
-section immu
-  enabled = 1
-  nsets = 64
-  nways = 1
-  pagesize = 8192
-  hitdelay = 0
-  missdelay = 0
-end
-
-
-/* DMMU SECTION
-
-    This section configures the Data Memory Manangement Unit
-
-    enabled = 0/1
-       '0': disabled
-       '1': enabled
-       (NOTE: UPR bit is set)
-
-    nsets = <value>
-       number of DTLB sets; must be power of two
-
-    nways = <value>
-       number of DTLB ways
-
-    pagesize = <value>
-       data page size; must be power of two
-
-    entrysize = <value>
-       data entry size in bytes
-
-    ustates = <value>
-       number of DTLB usage states (2, 3, 4 etc., max is 4)
-
-    hitdelay = <value>
-       number of cycles dmmu hit costs
-
-    missdelay = <value>
-       number of cycles dmmu miss costs
-*/
-
-section dmmu
-  enabled = 1
-  nsets = 64
-  nways = 1
-  pagesize = 8192
-  hitdelay = 0
-  missdelay = 0
-end
-
-
-/* IC SECTION
-
-   This section configures the Instruction Cache
-
-   enabled = 0/1
-       '0': disabled
-       '1': enabled
-      (NOTE: UPR bit is set)
-
-   nsets = <value>
-      number of IC sets; must be power of two
-
-   nways = <value>
-      number of IC ways
-
-   blocksize = <value>
-      IC block size in bytes; must be power of two
-
-   ustates = <value>
-      number of IC usage states (2, 3, 4 etc., max is 4)
-
-   hitdelay = <value>
-      number of cycles ic hit costs
-
-    missdelay = <value>
-      number of cycles ic miss costs
-*/
-
-section ic
-  enabled = 1
-  nsets = 512
-  nways = 1
-  blocksize = 16
-  hitdelay = 1
-  missdelay = 1
-end
-
-
-/* DC SECTION
-
-   This section configures the Data Cache
-
-   enabled = 0/1
-       '0': disabled
-       '1': enabled
-      (NOTE: UPR bit is set)
-
-   nsets = <value>
-      number of DC sets; must be power of two
-
-   nways = <value>
-      number of DC ways
-
-   blocksize = <value>
-      DC block size in bytes; must be power of two
-
-   ustates = <value>
-      number of DC usage states (2, 3, 4 etc., max is 4)
-
-   load_hitdelay = <value>
-      number of cycles dc load hit costs
-
-   load_missdelay = <value>
-      number of cycles dc load miss costs
-
-   store_hitdelay = <value>
-      number of cycles dc load hit costs
-
-   store_missdelay = <value>
-      number of cycles dc load miss costs
-*/
-
-section dc
-  enabled = 1
-  nsets = 512
-  nways = 1
-  blocksize = 16
-  load_hitdelay = 1
-  load_missdelay = 1
-  store_hitdelay = 1
-  store_missdelay = 1
-end
-
-
-/* SIM SECTION
-
-  This section specifies how or1ksim should behave.
-
-  verbose = 0/1
-       '0': don't print extra messages
-       '1': print extra messages
-
-  debug = 0-9
-      0  : no debug messages
-      1-9: debug message level.
-	   higher numbers produce more messages
-
-  profile = 0/1
-      '0': don't generate profiling file 'sim.profile'
-      '1': don't generate profiling file 'sim.profile'
-
-  prof_fn = "<filename>"
-      optional filename for the profiling file.
-      valid only if 'profile' is set
-
-  mprofile = 0/1
-      '0': don't generate memory profiling file 'sim.mprofile'
-      '1': generate memory profiling file 'sim.mprofile'
-
-  mprof_fn = "<filename>"
-      optional filename for the memory profiling file.
-      valid only if 'mprofile' is set
-
-  history = 0/1
-      '0': don't track execution flow
-      '1': track execution flow
-      Execution flow can be tracked for the simulator's
-      'hist' command. Useful for back-trace debugging.
-
-  iprompt = 0/1
-     '0': start in <not interactive prompt> (so what do we start in ???)
-     '1': start in interactive prompt.
-
-  exe_log = 0/1
-      '0': don't generate execution log.
-      '1': generate execution log.
-
-  exe_log = default/hardware/simple/software
-      type of execution log, default is used when not specified
-
-  exe_log_start = <value>
-      index of first instruction to start logging, default = 0
-
-  exe_log_end = <value>
-      index of last instruction to end logging; not limited, if omitted
-
-  exe_log_marker = <value>
-      <value> specifies number of instructions before horizontal marker is
-      printed; if zero, markers are disabled (default)
-
-  exe_log_fn = "<filename>"
-      filename for the exection log file.
-      valid only if 'exe_log' is set
-
-  clkcycle = <value>[ps|ns|us|ms]
-      specifies time measurement for one cycle
-*/
-
-section sim
-  verbose = 1
-  debug = 0
-  profile = 0
-  history = 0
-
-  clkcycle = 10ns
-end
-
-
-/* SECTION VAPI
-
-    This section configures the Verification API, used for Advanced
-    Core Verification.
-
-    enabled = 0/1
-	'0': disbable VAPI server
-	'1': enable/start VAPI server
-
-    server_port = <value>
-	TCP/IP port to start VAPI server on
-
-    log_enabled = 0/1
-       '0': disable VAPI requests logging
-       '1': enable VAPI requests logging
-
-    hide_device_id = 0/1
-       '0': don't log device id (for compatability with old version)
-       '1': log device id
-
-
-    vapi_fn = <filename>
-       filename for the log file.
-       valid only if log_enabled is set
-*/
-
-section VAPI
-  enabled = 0
-  server_port = 9998
-  log_enabled = 0
-  vapi_log_fn = "vapi.log"
-end
-
-
-/* CPU SECTION
-
-   This section specifies various CPU parameters.
-
-   ver = <value>
-   rev = <value>
-      specifies version and revision of the CPU used
-
-   upr = <value>
-      changes the upr register
-
-   sr = <value>
-      sets the initial Supervision Register value
-      supervisor mode (SM) and fixed one (FO) set = 0x8001
-      exception prefix high (EPH, vectors@0xf0000000) = 0x4000
-      together, (SM | FO | EPH) = 0xc001
-   superscalar = 0/1
-      '0': CPU is scalar
-      '1': CPU is superscalar
-      (modify cpu/or32/execute.c to tune superscalar model)
-
-   hazards = 0/1
-      '0': don't track data hazards in superscalar CPU
-      '1': track data hazards in superscalar CPU
-      If tracked, data hazards can be displayed using the
-      simulator's 'r' command.
-
-   dependstats = 0/1
-      '0': don't calculate inter-instruction dependencies.
-      '1': calculate inter-instruction dependencies.
-      If calculated, inter-instruction dependencies can be
-      displayed using the simulator's 'stat' command.
-
-   sbuf_len = <value>
-      length of store buffer (<= 256), 0 = disabled
-*/
-
-section cpu
-  ver = 0x12
-  cfg = 0x00
-  rev = 0x01
-  sr =  0x8001 /*SPR_SR_FO  | SPR_SR_SM | SPR_SR_EPH */
-  /* upr = */
-  superscalar = 0
-  hazards = 0
-  dependstats = 0
-  sbuf_len = 0
-end
-
-
-/* PM SECTION
-
-   This section specifies Power Management parameters
-
-   enabled = 0/1
-      '0': disable power management
-      '1': enable power management
-*/
-
-section pm
-  enabled = 0
-end
-
-
-/* BPB SECTION
-
-   This section specifies how branch prediction should behave.
-
-   enabled = 0/1
-     '0': disable branch prediction
-     '1': enable branch prediction
-
-   btic = 0/1
-     '0': disable branch target instruction cache model
-     '1': enable branch target instruction cache model
-
-   sbp_bf_fwd = 0/1
-     Static branch prediction for 'l.bf'
-     '0': don't use forward prediction
-     '1': use forward prediction
-
-   sbp_bnf_fwd = 0/1
-     Static branch prediction for 'l.bnf'
-     '0': don't use forward prediction
-     '1': use forward prediction
-
-   hitdelay = <value>
-       number of cycles bpb hit costs
-
-   missdelay = <value>
-       number of cycles bpb miss costs
-*/
-
-section bpb
-  enabled = 0
-  btic = 0
-  sbp_bf_fwd = 0
-  sbp_bnf_fwd = 0
-  hitdelay = 0
-  missdelay = 0
-end
-
-
-/* DEBUG SECTION
-
-   This sections specifies how the debug unit should behave.
-
-   enabled = 0/1
-      '0': disable debug unit
-      '1': enable debug unit
-
-   gdb_enabled = 0/1
-      '0': don't start gdb server
-      '1': start gdb server at port 'server_port'
-
-   server_port = <value>
-      TCP/IP port to start gdb server on
-      valid only if gdb_enabled is set
-
-   vapi_id = <hex_value>
-      Used to create "fake" vapi log file containing the JTAG proxy messages.
-*/
-section debug
-  enabled = 0
-/*  gdb_enabled = 0 */
-/*  server_port = 9999*/
-  rsp_enabled = 1
-  rsp_port = 50001
-end
-
-
-/* MC SECTION
-
-   This section configures the memory controller
-
-   enabled = 0/1
-     '0': disable memory controller
-     '1': enable memory controller
-
-   baseaddr = <hex_value>
-      address of first MC register
-
-   POC = <hex_value>
-      Power On Configuration register
-
-   index = <value>
-      Index of this memory controller amongst all the memory controllers
-*/
-
-section mc
-  enabled = 0
-  baseaddr = 0x93000000
-  POC = 0x00000008                 /* Power on configuration register */
-  index = 0
-end
-
-
-/* UART SECTION
-
-   This section configures the UARTs
-
-     enabled = <0|1>
-	Enable/disable the peripheral.  By default if it is enabled.
-
-     baseaddr = <hex_value>
-	address of first UART register for this device
-
-
-     channel = <channeltype>:<args>
-
-	The channel parameter indicates the source of received UART characters
-	and the sink for transmitted UART characters.
-
-	The <channeltype> can be either "file", "xterm", "tcp", "fd", or "tty"
-	(without quotes).
-
-	  A) To send/receive characters from a pair of files, use a file
-	     channel:
-
-	       channel=file:<rxfile>,<txfile>
-
-	  B) To create an interactive terminal window, use an xterm channel:
-
-	       channel=xterm:[<xterm_arg>]*
-
-	  C) To create a bidirectional tcp socket which one could, for example,
-	     access via telnet, use a tcp channel:
-
-	       channel=tcp:<port number>
-
-	  D) To cause the UART to read/write from existing numeric file
-	     descriptors, use an fd channel:
-
-	       channel=fd:<rx file descriptor num>,<tx file descriptor num>
-
-	  E) To connect the UART to a physical serial port, create a tty
-	     channel:
-
-	       channel=tty:device=/dev/ttyS0,baud=9600
-
-     irq = <value>
-	irq number for this device
-
-     16550 = 0/1
-	'0': this device is a UART16450
-	'1': this device is a UART16550
-
-     jitter = <value>
-	in msecs... time to block, -1 to disable it
-
-     vapi_id = <hex_value>
-	VAPI id of this instance
-*/
-
-section uart
-  enabled = 1
-  baseaddr = 0x90000000
-  irq = 2
-  /* channel = "file:uart0.rx,uart0.tx" */
-  /* channel = "tcp:10084" */
-  channel = "xterm:"
-  jitter = -1                     /* async behaviour */
-  16550 = 1
-end
-
-
-/* DMA SECTION
-
-   This section configures the DMAs
-
-     enabled = <0|1>
-	Enable/disable the peripheral.  By default if it is enabled.
-
-     baseaddr = <hex_value>
-	address of first DMA register for this device
-
-     irq = <value>
-	irq number for this device
-
-     vapi_id = <hex_value>
-	VAPI id of this instance
-*/
-
-section dma
-  enabled = 1
-  baseaddr = 0x9a000000
-  irq = 11
-end
-
-
-/* ETHERNET SECTION
-
-   This section configures the ETHERNETs
-
-     enabled = <0|1>
-	Enable/disable the peripheral.  By default if it is enabled.
-
-     baseaddr = <hex_value>
-	address of first ethernet register for this device
-
-     dma = <value>
-	which controller is this ethernet "connected" to
-
-     irq = <value>
-	ethernet mac IRQ level
-
-     rtx_type = <value>
-	use 0 - file interface, 1 - socket interface
-
-     rx_channel = <value>
-	DMA channel used for RX
-
-     tx_channel = <value>
-	DMA channel used for TX
-
-     rxfile = "<filename>"
-	filename, where to read data from
-
-     txfile = "<filename>"
-	filename, where to write data to
-
-     sockif = "<ifacename>"
-	interface name of ethernet socket
-
-     vapi_id = <hex_value>
-	VAPI id of this instance
-*/
-
-section ethernet
-  enabled = 1
-  baseaddr = 0x92000000
-  /* dma = 0 */
-  irq = 4
-  rtx_type = "tap"
-  tap_dev = "tap0"
-  /* tx_channel = 0 */
-  /* rx_channel = 1 */
-  rxfile = "eth0.rx"
-  txfile = "eth0.tx"
-  sockif = "eth0"
-end
-
-
-/* GPIO SECTION
-
-   This section configures the GPIOs
-
-     enabled = <0|1>
-	Enable/disable the peripheral.  By default if it is enabled.
-
-     baseaddr = <hex_value>
-	address of first GPIO register for this device
-
-     irq = <value>
-	irq number for this device
-
-     base_vapi_id = <hex_value>
-	first VAPI id of this instance
-	GPIO uses 8 consecutive VAPI IDs
-*/
-
-section gpio
-  enabled = 0
-  baseaddr = 0x91000000
-  irq = 3
-  base_vapi_id = 0x0200
-end
-
-/* VGA SECTION
-
-    This section configures the VGA/LCD controller
-
-      enabled = <0|1>
-	Enable/disable the peripheral.  By default if it is enabled.
-
-      baseaddr = <hex_value>
-	address of first VGA register
-
-      irq = <value>
-	irq number for this device
-
-      refresh_rate = <value>
-	number of cycles between screen dumps
-
-      filename = "<filename>"
-	template name for generated names (e.g. "primary" produces "primary0023.bmp")
-*/
-
-section vga
-  enabled = 0
-  baseaddr = 0x97100000
-  irq = 8
-  refresh_rate = 100000
-  filename = "primary"
-end
-
-
-/* TICK TIMER SECTION
-
-    This section configures tick timer
-
-    enabled = 0/1
-      whether tick timer is enabled
-*/
-
-section pic
-  enabled = 1
-  edge_trigger = 1
-end
-
-/* FB SECTION
-
-    This section configures the frame buffer
-
-    enabled = <0|1>
-      Enable/disable the peripheral.  By default if it is enabled.
-
-    baseaddr = <hex_value>
-      base address of frame buffer
-
-    paladdr = <hex_value>
-      base address of first palette entry
-
-    refresh_rate = <value>
-      number of cycles between screen dumps
-
-    filename = "<filename>"
-      template name for generated names (e.g. "primary" produces "primary0023.bmp")
-*/
-
-section fb
-  enabled = 0
-  baseaddr = 0x97000000
-  refresh_rate = 1000000
-  filename = "primary"
-end
-
-
-/* KBD SECTION
-
-    This section configures the PS/2 compatible keyboard
-
-    baseaddr = <hex_value>
-      base address of the keyboard device
-
-    rxfile = "<filename>"
-      filename, where to read data from
-*/
-
-section kbd
-  enabled = 0
-  irq = 5
-  baseaddr = 0x94000000
-  rxfile = "kbd.rx"
-end
-
-
-/* ATA SECTION
-
-    This section configures the ATA/ATAPI host controller
-
-      baseaddr = <hex_value>
-	address of first ATA register
-
-      enabled = <0|1>
-	Enable/disable the peripheral.  By default if it is enabled.
-
-      irq = <value>
-	irq number for this device
-
-      debug = <value>
-	debug level for ata models.
-	0: no debug messages
-	1: verbose messages
-	3: normal messages (more messages than verbose)
-	5: debug messages (normal debug messages)
-	7: flow control messages (debug statemachine flows)
-	9: low priority message (display everything the code does)
-
-      dev_type0/1 = <value>
-	ata device 0 type
-	0: NO_CONNeCT: none (not connected)
-	1: FILE      : simulated harddisk
-	2: LOCAL     : local system harddisk
-
-      dev_file0/1 = "<filename>"
-	filename for simulated ATA device
-	valid only if dev_type0 == 1
-
-      dev_size0/1 = <value>
-	size of simulated hard-disk (in MBytes)
-	valid only if dev_type0 == 1
-
-      dev_packet0/1 = <value>
-	0: simulated ATA device does NOT implement PACKET command feature set
-	1: simulated ATA device does implement PACKET command feature set
-
-   FIXME: irq number
-*/
-
-section ata
-  enabled = 0
-  baseaddr = 0x9e000000
-  irq = 15
-
-end
diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c
index eb92914..1c0540a 100644
--- a/board/pb1x00/pb1x00.c
+++ b/board/pb1x00/pb1x00.c
@@ -11,11 +11,15 @@
 #include <asm/mipsregs.h>
 #include <asm/io.h>
 
-phys_size_t initdram(int board_type)
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
 {
 	/* Sdram is setup by assembler code */
 	/* If memory could be changed, we should return the true value here */
-	return 64*1024*1024;
+	gd->ram_size = 64 * 1024 * 1024;
+
+	return 0;
 }
 
 #define BCSR_PCMCIA_PC0DRVEN		0x0010
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
index d91d427..9db31d3 100644
--- a/board/pdm360ng/pdm360ng.c
+++ b/board/pdm360ng/pdm360ng.c
@@ -48,7 +48,7 @@ sdram_conf_t mddrc_config[] = {
 	},
 };
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	int i;
 	u32 msize = 0;
@@ -95,7 +95,9 @@ phys_size_t initdram (int board_type)
 			break;
 	}
 
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }
 
 static int set_lcd_brightness(char *);
diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c
index 8a9de0d..983559e 100644
--- a/board/phytec/pcm030/pcm030.c
+++ b/board/phytec/pcm030/pcm030.c
@@ -18,6 +18,8 @@
 
 #include "mt46v32m16-75.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start(int hi_addr)
 {
@@ -67,13 +69,13 @@ static void sdram_start(int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make
+ * ATTENTION: Although partially referenced dram_init does NOT make
  *	real use of CONFIG_SYS_SDRAM_BASE. The code does not
  *	work if CONFIG_SYS_SDRAM_BASE
  *	is something else than 0x00000000.
  */
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile struct mpc5xxx_mmap_ctl *mm =
 		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
@@ -143,7 +145,9 @@ phys_size_t initdram(int board_type)
 
 #endif /* CONFIG_SYS_RAMBOOT */
 
-	return dramsize + dramsize2;
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/pr1/Kconfig b/board/pr1/Kconfig
deleted file mode 100644
index fb04648..0000000
--- a/board/pr1/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PR1
-
-config SYS_BOARD
-	default "pr1"
-
-config SYS_CONFIG_NAME
-	default "pr1"
-
-endif
diff --git a/board/pr1/MAINTAINERS b/board/pr1/MAINTAINERS
deleted file mode 100644
index 23fdbc7..0000000
--- a/board/pr1/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PR1 BOARD
-M:	Dimitar Penev <dpn@switchfin.org>
-S:	Maintained
-F:	board/pr1/
-F:	include/configs/pr1.h
-F:	configs/pr1_defconfig
diff --git a/board/pr1/Makefile b/board/pr1/Makefile
deleted file mode 100644
index 8caa360..0000000
--- a/board/pr1/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) Switchfin Org. <dpn@switchfin.org>
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= pr1.o
diff --git a/board/pr1/pr1.c b/board/pr1/pr1.c
deleted file mode 100644
index 3fffabd..0000000
--- a/board/pr1/pr1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) Switchfin Org. <dpn@switchfin.org>
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
-	printf("Board: Switchvoice PR1 Appliance\n");
-	printf("       Support: http://www.switchvoice.com/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/qemu-mips/qemu-mips.c b/board/qemu-mips/qemu-mips.c
index 563044e..583acc2 100644
--- a/board/qemu-mips/qemu-mips.c
+++ b/board/qemu-mips/qemu-mips.c
@@ -11,11 +11,15 @@
 #include <asm/io.h>
 #include <netdev.h>
 
-phys_size_t initdram(int board_type)
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
 {
 	/* Sdram is setup by assembler code */
 	/* If memory could be changed, we should return the true value here */
-	return MEM_SIZE*1024*1024;
+	gd->ram_size = MEM_SIZE * 1024 * 1024;
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 818ae04..e923ddc 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -19,10 +19,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 
diff --git a/board/radxa/rock/Kconfig b/board/radxa/rock/Kconfig
new file mode 100644
index 0000000..855b9b6
--- /dev/null
+++ b/board/radxa/rock/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ROCK
+
+config SYS_BOARD
+	default "rock"
+
+config SYS_VENDOR
+	default "radxa"
+
+config SYS_CONFIG_NAME
+	default "rock"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/radxa/rock/MAINTAINERS b/board/radxa/rock/MAINTAINERS
new file mode 100644
index 0000000..c5f59c0
--- /dev/null
+++ b/board/radxa/rock/MAINTAINERS
@@ -0,0 +1,6 @@
+RADXA_ROCK
+M:	Heiko Stuebner <heiko@sntech.de>
+S:	Maintained
+F:	board/radxa/rock
+F:	include/configs/rock.h
+F:	configs/rock_defconfig
diff --git a/board/radxa/rock/Makefile b/board/radxa/rock/Makefile
new file mode 100644
index 0000000..fe94b60
--- /dev/null
+++ b/board/radxa/rock/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Heiko Stuebner
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= rock.o
diff --git a/board/radxa/rock/rock.c b/board/radxa/rock/rock.c
new file mode 100644
index 0000000..5119e95
--- /dev/null
+++ b/board/radxa/rock/rock.c
@@ -0,0 +1,7 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c
index 7e70f38..a7895cb 100644
--- a/board/rockchip/evb_rk3328/evb-rk3328.c
+++ b/board/rockchip/evb_rk3328/evb-rk3328.c
@@ -22,11 +22,13 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	/* Reserve 0x200000 for ATF bl31 */
 	gd->bd->bi_dram[0].start = 0x200000;
 	gd->bd->bi_dram[0].size = 0x7e000000;
+
+	return 0;
 }
 
 int usb_gadget_handle_interrupts(void)
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c
index c437f1b..362fa0b 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -67,9 +67,11 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	/* Reserve 0x200000 for ATF bl31 */
 	gd->bd->bi_dram[0].start = 0x200000;
 	gd->bd->bi_dram[0].size = 0x7e000000;
+
+	return 0;
 }
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index e2cb94e..79073d8 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -264,10 +264,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_RESET_PHY_R
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index e9f9b67..accf16f 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -360,10 +360,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_RESET_PHY_R
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index c2707e0..c122580 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -144,10 +144,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_RESET_PHY_R
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
index 881d080..405ed3b 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@@ -55,7 +55,7 @@ int power_init_board(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	int i;
 	u32 addr, size;
@@ -67,6 +67,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[i].start = addr;
 		gd->bd->bi_dram[i].size = size;
 	}
+
+	return 0;
 }
 
 #ifdef CONFIG_GENERIC_MMC
diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile
index ef1a8f3..fa85f7d 100644
--- a/board/samsung/common/Makefile
+++ b/board/samsung/common/Makefile
@@ -5,7 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
 obj-$(CONFIG_USB_GADGET_DOWNLOAD) += gadget.o
 obj-$(CONFIG_MISC_COMMON) += misc.o
 
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index ba928e0..49e4db2 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -108,7 +108,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	unsigned int i;
 	unsigned long addr, size;
@@ -120,6 +120,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[i].start = addr;
 		gd->bd->bi_dram[i].size = size;
 	}
+
+	return 0;
 }
 
 static int board_uart_init(void)
diff --git a/board/samsung/common/multi_i2c.c b/board/samsung/common/multi_i2c.c
deleted file mode 100644
index 71c32c0..0000000
--- a/board/samsung/common/multi_i2c.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- *  Copyright (C) 2012 Samsung Electronics
- *  Lukasz Majewski <l.majewski@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#ifndef CONFIG_SOFT_I2C_I2C10_SCL
-#define CONFIG_SOFT_I2C_I2C10_SCL 0
-#endif
-
-#ifndef CONFIG_SOFT_I2C_I2C10_SDA
-#define CONFIG_SOFT_I2C_I2C10_SDA 0
-#endif
-
-/* Handle multiple I2C buses instances */
-int get_multi_scl_pin(void)
-{
-	unsigned int bus = i2c_get_bus_num();
-
-	switch (bus) {
-	case I2C_0:
-		return CONFIG_SOFT_I2C_I2C5_SCL;
-	case I2C_1:
-		return CONFIG_SOFT_I2C_I2C9_SCL;
-	case I2C_2:
-		return CONFIG_SOFT_I2C_I2C10_SCL;
-	default:
-		printf("I2C_%d not supported!\n", bus);
-	};
-
-	return 0;
-}
-
-int get_multi_sda_pin(void)
-{
-	unsigned int bus = i2c_get_bus_num();
-
-	switch (bus) {
-	case I2C_0:
-		return CONFIG_SOFT_I2C_I2C5_SDA;
-	case I2C_1:
-		return CONFIG_SOFT_I2C_I2C9_SDA;
-	case I2C_2:
-		return CONFIG_SOFT_I2C_I2C10_SDA;
-	default:
-		printf("I2C_%d not supported!\n", bus);
-	};
-
-	return 0;
-}
-
-int multi_i2c_init(void)
-{
-	return 0;
-}
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index 9c48d71..35ed398 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -52,7 +52,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
@@ -60,6 +60,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
 	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_DISPLAY_BOARDINFO
diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c
index 66b6a98..79e127d 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -51,10 +51,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_DISPLAY_BOARDINFO
diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c
index fc0e8d2..c730ac0 100644
--- a/board/samsung/smdkv310/smdkv310.c
+++ b/board/samsung/smdkv310/smdkv310.c
@@ -52,7 +52,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
@@ -66,6 +66,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
 							PHYS_SDRAM_4_SIZE);
+
+	return 0;
 }
 
 int board_eth_init(bd_t *bis)
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 7200c2e..00059a1 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -23,6 +23,7 @@
 #include <power/max8997_muic.h>
 #include <power/battery.h>
 #include <power/max17042_fg.h>
+#include <power/pmic.h>
 #include <libtizen.h>
 #include <usb.h>
 #include <usb_mass_storage.h>
@@ -51,26 +52,6 @@ int exynos_init(void)
 	return 0;
 }
 
-void i2c_init_board(void)
-{
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
-	int err;
-
-	/* I2C_5 -> PMIC */
-	err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("I2C%d not configured\n", (I2C_5));
-		return;
-	}
-
-	/* I2C_8 -> FG */
-	gpio_request(EXYNOS4_GPIO_Y40, "i2c_clk");
-	gpio_request(EXYNOS4_GPIO_Y41, "i2c_data");
-	gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
-	gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
-#endif
-}
-
 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 static void trats_low_power_mode(void)
 {
@@ -129,156 +110,6 @@ static void trats_low_power_mode(void)
 	writel(0x0, &clk->gate_ip_image);	/* IMAGE */
 	writel(0x0, &clk->gate_ip_gps);	/* GPS */
 }
-
-static int pmic_init_max8997(void)
-{
-	struct pmic *p = pmic_get("MAX8997_PMIC");
-	int i = 0, ret = 0;
-	u32 val;
-
-	if (pmic_probe(p))
-		return -1;
-
-	/* BUCK1 VARM: 1.2V */
-	val = (1200000 - 650000) / 25000;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
-	val = ENBUCK | ACTIVE_DISCHARGE;		/* DVS OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
-
-	/* BUCK2 VINT: 1.1V */
-	val = (1100000 - 650000) / 25000;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
-	val = ENBUCK | ACTIVE_DISCHARGE;		/* DVS OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
-
-
-	/* BUCK3 G3D: 1.1V - OFF */
-	ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
-	val &= ~ENBUCK;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
-
-	val = (1100000 - 750000) / 50000;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
-
-	/* BUCK4 CAMISP: 1.2V - OFF */
-	ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
-	val &= ~ENBUCK;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
-
-	val = (1200000 - 650000) / 25000;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
-
-	/* BUCK5 VMEM: 1.2V */
-	val = (1200000 - 650000) / 25000;
-	for (i = 0; i < 8; i++)
-		ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
-
-	val = ENBUCK | ACTIVE_DISCHARGE;		/* DVS OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
-
-	/* BUCK6 CAM AF: 2.8V */
-	/* No Voltage Setting Register */
-	/* GNSLCT 3.0X */
-	val = GNSLCT;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
-
-	/* BUCK7 VCC_SUB: 2.0V */
-	val = (2000000 - 750000) / 50000;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
-
-	/* LDO1 VADC: 3.3V */
-	val = max8997_reg_ldo(3300000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
-
-	/* LDO1 Disable active discharging */
-	ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
-	val &= ~LDO_ADE;
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
-
-	/* LDO2 VALIVE: 1.1V */
-	val = max8997_reg_ldo(1100000) | EN_LDO;
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
-
-	/* LDO3 VUSB/MIPI: 1.1V */
-	val = max8997_reg_ldo(1100000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
-
-	/* LDO4 VMIPI: 1.8V */
-	val = max8997_reg_ldo(1800000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
-
-	/* LDO5 VHSIC: 1.2V */
-	val = max8997_reg_ldo(1200000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
-
-	/* LDO6 VCC_1.8V_PDA: 1.8V */
-	val = max8997_reg_ldo(1800000) | EN_LDO;
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
-
-	/* LDO7 CAM_ISP: 1.8V */
-	val = max8997_reg_ldo(1800000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
-
-	/* LDO8 VDAC/VUSB: 3.3V */
-	val = max8997_reg_ldo(3300000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
-
-	/* LDO9 VCC_2.8V_PDA: 2.8V */
-	val = max8997_reg_ldo(2800000) | EN_LDO;
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
-
-	/* LDO10 VPLL: 1.1V */
-	val = max8997_reg_ldo(1100000) | EN_LDO;
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
-
-	/* LDO11 TOUCH: 2.8V */
-	val = max8997_reg_ldo(2800000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
-
-	/* LDO12 VTCAM: 1.8V */
-	val = max8997_reg_ldo(1800000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
-
-	/* LDO13 VCC_3.0_LCD: 3.0V */
-	val = max8997_reg_ldo(3000000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
-
-	/* LDO14 MOTOR: 3.0V */
-	val = max8997_reg_ldo(3000000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
-
-	/* LDO15 LED_A: 2.8V */
-	val = max8997_reg_ldo(2800000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
-
-	/* LDO16 CAM_SENSOR: 1.8V */
-	val = max8997_reg_ldo(1800000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
-
-	/* LDO17 VTF: 2.8V */
-	val = max8997_reg_ldo(2800000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
-
-	/* LDO18 TOUCH_LED 3.3V */
-	val = max8997_reg_ldo(3300000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
-
-	/* LDO21 VDDQ: 1.2V */
-	val = max8997_reg_ldo(1200000) | EN_LDO;
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
-
-	/* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
-	val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
-		ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
-	ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
-
-	if (ret) {
-		puts("MAX8997 PMIC setting error!\n");
-		return -1;
-	}
-
-	return 0;
-}
 #endif
 
 int exynos_power_init(void)
@@ -295,9 +126,7 @@ int exynos_power_init(void)
 	 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
 	 * to logical I2C adapter 1
 	 */
-	ret = pmic_init(I2C_5);
-	ret |= pmic_init_max8997();
-	ret |= power_fg_init(I2C_9);
+	ret = power_fg_init(I2C_9);
 	ret |= power_muic_init(I2C_5);
 	ret |= power_bat_init(0);
 	if (ret)
@@ -391,39 +220,59 @@ static void check_hw_revision(void)
 #ifdef CONFIG_USB_GADGET
 static int s5pc210_phy_control(int on)
 {
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
-	int ret = 0;
-	u32 val = 0;
-	struct pmic *p = pmic_get("MAX8997_PMIC");
-	if (!p)
-		return -ENODEV;
+	struct udevice *dev;
+	int reg, ret;
 
-	if (pmic_probe(p))
-		return -1;
+	ret = pmic_get("max8997-pmic", &dev);
+	if (ret)
+		return ret;
 
 	if (on) {
-		ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
-				      ENSAFEOUT1, LDO_ON);
-		ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
-		ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
-
-		ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
-		ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
+		reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL);
+		reg |= ENSAFEOUT1;
+		ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
+		reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL);
+		reg |= EN_LDO;
+		ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
+		reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL);
+		reg |= EN_LDO;
+		ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
 	} else {
-		ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
-		ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
-
-		ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
-		ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
-		ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
-				      ENSAFEOUT1, LDO_OFF);
-	}
+		reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL);
+		reg &= DIS_LDO;
+		ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
+		reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL);
+		reg &= DIS_LDO;
+		ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
+		reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL);
+		reg &= ~ENSAFEOUT1;
+		ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
 
-	if (ret) {
-		puts("MAX8997 LDO setting error!\n");
-		return -1;
 	}
-#endif
 
 	return 0;
 }
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index 150503e..f9acbd3 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -100,50 +100,6 @@ static void board_external_gpio_init(void)
 	gpio_set_pull(EXYNOS4X12_GPIO_X37, S5P_GPIO_PULL_NONE);	/* HDMI_HPD */
 }
 
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-static void board_init_i2c(void)
-{
-	int err;
-
-	/* I2C_7 */
-	err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("I2C%d not configured\n", (I2C_7));
-		return;
-	}
-
-	/* I2C_8 */
-	gpio_request(EXYNOS4X12_GPIO_F14, "i2c8_clk");
-	gpio_request(EXYNOS4X12_GPIO_F15, "i2c8_data");
-	gpio_direction_output(EXYNOS4X12_GPIO_F14, 1);
-	gpio_direction_output(EXYNOS4X12_GPIO_F15, 1);
-
-	/* I2C_9 */
-	gpio_request(EXYNOS4X12_GPIO_M21, "i2c9_clk");
-	gpio_request(EXYNOS4X12_GPIO_M20, "i2c9_data");
-	gpio_direction_output(EXYNOS4X12_GPIO_M21, 1);
-	gpio_direction_output(EXYNOS4X12_GPIO_M20, 1);
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_SOFT
-int get_soft_i2c_scl_pin(void)
-{
-	if (I2C_ADAP_HWNR)
-		return EXYNOS4X12_GPIO_M21; /* I2C9 */
-	else
-		return EXYNOS4X12_GPIO_F14; /* I2C8 */
-}
-
-int get_soft_i2c_sda_pin(void)
-{
-	if (I2C_ADAP_HWNR)
-		return EXYNOS4X12_GPIO_M20; /* I2C9 */
-	else
-		return EXYNOS4X12_GPIO_F15; /* I2C8 */
-}
-#endif
-
 int exynos_early_init_f(void)
 {
 	board_external_gpio_init();
@@ -179,11 +135,6 @@ int exynos_power_init(void)
 	struct power_battery *pb;
 	struct pmic *p_chrg, *p_muic, *p_fg, *p_bat;
 
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-	board_init_i2c();
-#endif
-	pmic_init(I2C_7);		/* I2C adapter 7 - bus name s3c24x0_7 */
-	pmic_init_max77686();
 	pmic_init_max77693(I2C_10);	/* I2C adapter 10 - bus name soft1 */
 	power_muic_init(I2C_10);	/* I2C adapter 10 - bus name soft1 */
 	power_fg_init(I2C_9);		/* I2C adapter 9 - bus name soft0 */
@@ -331,61 +282,6 @@ int g_dnl_board_usb_cable_connected(void)
 }
 #endif
 
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
-static int pmic_init_max77686(void)
-{
-	struct pmic *p = pmic_get("MAX77686_PMIC");
-
-	if (pmic_probe(p))
-		return -1;
-
-	/* BUCK/LDO Output Voltage */
-	max77686_set_ldo_voltage(p, 21, 2800000);	/* LDO21 VTF_2.8V */
-	max77686_set_ldo_voltage(p, 23, 3300000);	/* LDO23 TSP_AVDD_3.3V*/
-	max77686_set_ldo_voltage(p, 24, 1800000);	/* LDO24 TSP_VDD_1.8V */
-
-	/* BUCK/LDO Output Mode */
-	max77686_set_buck_mode(p, 1, OPMODE_STANDBY);	/* BUCK1 VMIF_1.1V_AP */
-	max77686_set_buck_mode(p, 2, OPMODE_ON);	/* BUCK2 VARM_1.0V_AP */
-	max77686_set_buck_mode(p, 3, OPMODE_ON);	/* BUCK3 VINT_1.0V_AP */
-	max77686_set_buck_mode(p, 4, OPMODE_ON);	/* BUCK4 VG3D_1.0V_AP */
-	max77686_set_buck_mode(p, 5, OPMODE_ON);	/* BUCK5 VMEM_1.2V_AP */
-	max77686_set_buck_mode(p, 6, OPMODE_ON);	/* BUCK6 VCC_SUB_1.35V*/
-	max77686_set_buck_mode(p, 7, OPMODE_ON);	/* BUCK7 VCC_SUB_2.0V */
-	max77686_set_buck_mode(p, 8, OPMODE_OFF);	/* VMEM_VDDF_2.85V */
-	max77686_set_buck_mode(p, 9, OPMODE_OFF);	/* CAM_ISP_CORE_1.2V*/
-
-	max77686_set_ldo_mode(p, 1, OPMODE_LPM);	/* LDO1 VALIVE_1.0V_AP*/
-	max77686_set_ldo_mode(p, 2, OPMODE_STANDBY);	/* LDO2 VM1M2_1.2V_AP */
-	max77686_set_ldo_mode(p, 3, OPMODE_LPM);	/* LDO3 VCC_1.8V_AP */
-	max77686_set_ldo_mode(p, 4, OPMODE_LPM);	/* LDO4 VCC_2.8V_AP */
-	max77686_set_ldo_mode(p, 5, OPMODE_OFF);	/* LDO5_VCC_1.8V_IO */
-	max77686_set_ldo_mode(p, 6, OPMODE_STANDBY);	/* LDO6 VMPLL_1.0V_AP */
-	max77686_set_ldo_mode(p, 7, OPMODE_STANDBY);	/* LDO7 VPLL_1.0V_AP */
-	max77686_set_ldo_mode(p, 8, OPMODE_LPM);	/* LDO8 VMIPI_1.0V_AP */
-	max77686_set_ldo_mode(p, 9, OPMODE_OFF);	/* CAM_ISP_MIPI_1.2*/
-	max77686_set_ldo_mode(p, 10, OPMODE_LPM);	/* LDO10 VMIPI_1.8V_AP*/
-	max77686_set_ldo_mode(p, 11, OPMODE_STANDBY);	/* LDO11 VABB1_1.8V_AP*/
-	max77686_set_ldo_mode(p, 12, OPMODE_LPM);	/* LDO12 VUOTG_3.0V_AP*/
-	max77686_set_ldo_mode(p, 13, OPMODE_OFF);	/* LDO13 VC2C_1.8V_AP */
-	max77686_set_ldo_mode(p, 14, OPMODE_STANDBY);	/* VABB02_1.8V_AP */
-	max77686_set_ldo_mode(p, 15, OPMODE_STANDBY);	/* LDO15 VHSIC_1.0V_AP*/
-	max77686_set_ldo_mode(p, 16, OPMODE_STANDBY);	/* LDO16 VHSIC_1.8V_AP*/
-	max77686_set_ldo_mode(p, 17, OPMODE_OFF);	/* CAM_SENSOR_CORE_1.2*/
-	max77686_set_ldo_mode(p, 18, OPMODE_OFF);	/* CAM_ISP_SEN_IO_1.8V*/
-	max77686_set_ldo_mode(p, 19, OPMODE_OFF);	/* LDO19 VT_CAM_1.8V */
-	max77686_set_ldo_mode(p, 20, OPMODE_ON);	/* LDO20 VDDQ_PRE_1.8V*/
-	max77686_set_ldo_mode(p, 21, OPMODE_OFF);	/* LDO21 VTF_2.8V */
-	max77686_set_ldo_mode(p, 22, OPMODE_OFF);	/* LDO22 VMEM_VDD_2.8V*/
-	max77686_set_ldo_mode(p, 23, OPMODE_OFF);	/* LDO23 TSP_AVDD_3.3V*/
-	max77686_set_ldo_mode(p, 24, OPMODE_OFF);	/* LDO24 TSP_VDD_1.8V */
-	max77686_set_ldo_mode(p, 25, OPMODE_OFF);	/* LDO25 VCC_3.3V_LCD */
-	max77686_set_ldo_mode(p, 26, OPMODE_OFF);	/*LDO26 VCC_3.0V_MOTOR*/
-
-	return 0;
-}
-#endif
-
 /*
  * LCD
  */
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 72786d2..a3395ed 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -19,6 +19,8 @@
 #include <libfdt.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int fixed_sdram(void);
 void sdram_init(void);
 
@@ -35,7 +37,7 @@ int board_early_init_f (void)
 
 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
@@ -61,8 +63,10 @@ phys_size_t initdram (int board_type)
 	 */
 	ddr_enable_ecc(msize * 1024 * 1024);
 #endif
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return (msize * 1024 * 1024);
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 #if !defined(CONFIG_SPD_EEPROM)
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 6bdf1a2..08ced10 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -23,6 +23,8 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 long int fixed_sdram (void);
 
 int board_early_init_f (void)
@@ -37,7 +39,7 @@ int checkboard (void)
 	return 0;
 }
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	long dram_size = 0;
 
@@ -48,7 +50,9 @@ phys_size_t initdram (int board_type)
 #endif
 
 	debug ("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 #if defined(CONFIG_SYS_DRAM_TEST)
diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c
index bc92cd6..d6a84db 100644
--- a/board/spear/common/spr_misc.c
+++ b/board/spear/common/spr_misc.c
@@ -33,10 +33,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 int board_early_init_f()
diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c
index 0c06bca..92b0695 100644
--- a/board/st/stih410-b2260/board.c
+++ b/board/st/stih410-b2260/board.c
@@ -16,11 +16,21 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
 }
+#endif
 
 int board_init(void)
 {
diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c
index add1ce1..6a19730 100644
--- a/board/st/stv0991/stv0991.c
+++ b/board/st/stv0991/stv0991.c
@@ -93,10 +93,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_CMD_NET
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 37b4252..a667c9e 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -3,6 +3,7 @@ if ARCH_SUNXI
 config IDENT_STRING
 	default " Allwinner Technology"
 
+# FIXME: Should not redefine these Kconfig symbols
 config PRE_CONSOLE_BUFFER
 	default y
 
@@ -19,6 +20,7 @@ config SPL_LIBGENERIC_SUPPORT
 	default y
 
 config SPL_MMC_SUPPORT
+	depends on SPL && GENERIC_MMC
 	default y
 
 config SPL_POWER_SUPPORT
@@ -27,6 +29,17 @@ config SPL_POWER_SUPPORT
 config SPL_SERIAL_SUPPORT
 	default y
 
+config SUNXI_HIGH_SRAM
+	bool
+	default n
+	---help---
+	Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
+	with the first SRAM region being located at address 0.
+	Some newer SoCs map the boot ROM at address 0 instead and move the
+	SRAM to 64KB, just behind the mask ROM.
+	Chips using the latter setup are supposed to select this option to
+	adjust the addresses accordingly.
+
 # Note only one of these may be selected at a time! But hidden choices are
 # not supported by Kconfig
 config SUNXI_GEN_SUN4I
@@ -43,6 +56,11 @@ config SUNXI_GEN_SUN6I
 	watchdog, etc.
 
 
+config MACH_SUNXI_H3_H5
+	bool
+	select SUNXI_GEN_SUN6I
+	select SUPPORT_SPL
+
 choice
 	prompt "Sunxi SoC Variant"
 	optional
@@ -50,12 +68,14 @@ choice
 config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
 	select CPU_V7
+	select ARM_CORTEX_CPU_IS_UP
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 
 config MACH_SUN5I
 	bool "sun5i (Allwinner A13)"
 	select CPU_V7
+	select ARM_CORTEX_CPU_IS_UP
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 
@@ -111,13 +131,13 @@ config MACH_SUN8I_H3
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
-	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
+	select MACH_SUNXI_H3_H5
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config MACH_SUN9I
 	bool "sun9i (Allwinner A80)"
 	select CPU_V7
+	select SUNXI_HIGH_SRAM
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 
@@ -125,14 +145,21 @@ config MACH_SUN50I
 	bool "sun50i (Allwinner A64)"
 	select ARM64
 	select SUNXI_GEN_SUN6I
+	select SUNXI_HIGH_SRAM
 	select SUPPORT_SPL
 
+config MACH_SUN50I_H5
+	bool "sun50i (Allwinner H5)"
+	select ARM64
+	select MACH_SUNXI_H3_H5
+	select SUNXI_HIGH_SRAM
+
 endchoice
 
 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
 config MACH_SUN8I
 	bool
-	default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
+	default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUNXI_H3_H5 || MACH_SUN8I_A83T
 
 config RESERVE_ALLWINNER_BOOT0_HEADER
 	bool "reserve space for Allwinner boot0 header"
@@ -320,7 +347,7 @@ config OLD_SUNXI_KERNEL_COMPAT
 
 config MMC0_CD_PIN
 	string "Card detect pin for mmc0"
-	default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
+	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
 	default ""
 	---help---
 	Set the card detect pin for mmc0, leave empty to not use cd. This
@@ -485,7 +512,7 @@ config AXP_GPIO
 
 config VIDEO
 	bool "Enable graphical uboot console on HDMI, LCD or VGA"
-	depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
+	depends on !MACH_SUN8I_A83T && !MACH_SUNXI_H3_H5 && !MACH_SUN9I && !MACH_SUN50I
 	default y
 	---help---
 	Say Y here to add support for using a cfb console on the HDMI, LCD
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 2321b8b..91ca6ea 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -242,6 +242,11 @@ M:	Icenowy Zheng <icenowy@aosc.xyz>
 S:	Maintained
 F:	configs/orangepi_zero_defconfig
 
+ORANGEPI PC 2 BOARD
+M:	Andre Przywara <andre.przywara@arm.com>
+S:	Maintained
+F:	configs/orangepi_pc2_defconfig
+
 R16 EVB PARROT BOARD
 M:	Quentin Schulz <quentin.schulz@free-electrons.com>
 S:	Maintained
@@ -264,6 +269,12 @@ M:	VishnuPatekar <vishnupatekar0510@gmail.com>
 S:	Maintained
 F:	configs/Sinovoip_BPI_M3_defconfig
 
+SUNCHIP CX-A99 BOARD
+M:	Rask Ingemann Lambertsen <rask@formelder.dk>
+S:	Maintained
+F:	configs/Sunchip_CX-A99_defconfig
+W:	https://linux-sunxi.org/Sunchip_CX-A99
+
 WEXLER-TAB7200 BOARD
 M:	Aleksei Mamlin <mamlinav@gmail.com>
 S:	Maintained
diff --git a/board/sunxi/README.nand b/board/sunxi/README.nand
new file mode 100644
index 0000000..a5d4ff0
--- /dev/null
+++ b/board/sunxi/README.nand
@@ -0,0 +1,54 @@
+Allwinner NAND flashing
+=======================
+
+A lot of Allwinner devices, especially the older ones (pre-H3 era),
+comes with a NAND. NANDs storages are a pretty weak choice when it
+comes to the reliability, and it comes with a number of flaws like
+read and write disturbs, data retention issues, bloks becoming
+unusable, etc.
+
+In order to mitigate that, various strategies have been found to be
+able to recover from those issues like ECC, hardware randomization,
+and of course, redundancy for the critical parts.
+
+This is obviously something that we will take into account when
+creating our images. However, the BROM will use a quite weird pattern
+when accessing the NAND, and will access only at most 4kB per page,
+which means that we also have to split that binary accross several
+pages.
+
+In order to accomodate that, we create a tool that will generate an
+SPL image that is ready to be programmed directly embedding the ECCs,
+randomized, and with the necessary bits needed to reduce the number of
+bitflips. The U-Boot build system, when configured for the NAND will
+also generate the image sunxi-spl-with-ecc.bin that will have been
+generated by that tool.
+
+In order to flash your U-Boot image onto a board, assuming that the
+board is in FEL mode, you'll need the sunxi-tools that you can find at
+this repository: https://github.com/linux-sunxi/sunxi-tools
+
+Then, you'll need to first load an SPL to initialise the RAM:
+sunxi-fel spl spl/sunxi-spl.bin
+
+Load the binaries we'll flash into RAM:
+sunxi-fel write 0x4a000000 u-boot-dtb.bin
+sunxi-fel write 0x43000000 spl/sunxi-spl-with-ecc.bin
+
+And execute U-Boot
+sunxi-fel exe 0x4a000000
+
+On your board, you'll now have all the needed binaries into RAM, so
+you only need to erase the NAND...
+
+nand erase.chip
+
+Then write the SPL and its backup:
+
+nand write.raw.noverify 0x43000000 0 40
+nand write.raw.noverify 0x43000000 0x400000 40
+
+And finally write the U-Boot binary:
+nand write 0x4a000000 0x800000 0xc0000
+
+You can now reboot and enjoy your NAND.
\ No newline at end of file
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 5365638..b966012 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -100,14 +100,14 @@ int board_init(void)
 		 * we avoid the risk of writing to it.
 		 */
 		asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
-		if (freq != CONFIG_TIMER_CLK_FREQ) {
+		if (freq != COUNTER_FREQUENCY) {
 			debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
-			      freq, CONFIG_TIMER_CLK_FREQ);
+			      freq, COUNTER_FREQUENCY);
 #ifdef CONFIG_NON_SECURE
 			printf("arch timer frequency is wrong, but cannot adjust it\n");
 #else
 			asm volatile("mcr p15, 0, %0, c14, c0, 0"
-				     : : "r"(CONFIG_TIMER_CLK_FREQ));
+				     : : "r"(COUNTER_FREQUENCY));
 #endif
 		}
 	}
diff --git a/board/synopsys/axs10x/Kconfig b/board/synopsys/axs10x/Kconfig
index c60b6a2..dd1305a 100644
--- a/board/synopsys/axs10x/Kconfig
+++ b/board/synopsys/axs10x/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_AXS10X
+if TARGET_AXS101 || TARGET_AXS103
 
 config SYS_BOARD
 	default "axs10x"
diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c
index a5e774b..e6b69da 100644
--- a/board/synopsys/axs10x/axs10x.c
+++ b/board/synopsys/axs10x/axs10x.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <dwmmc.h>
 #include <malloc.h>
+#include <asm/arcregs.h>
 #include "axs10x.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -61,16 +62,32 @@ void smp_kick_all_cpus(void)
 {
 /* CPU start CREG */
 #define AXC003_CREG_CPU_START	0xF0001400
-
 /* Bits positions in CPU start CREG */
 #define BITS_START	0
-#define BITS_POLARITY	8
+#define BITS_START_MODE	4
 #define BITS_CORE_SEL	9
-#define BITS_MULTICORE	12
 
-#define CMD	(1 << BITS_MULTICORE) | (1 << BITS_CORE_SEL) | \
-		(1 << BITS_POLARITY) | (1 << BITS_START)
+/*
+ * In axs103 v1.1 START bits semantics has changed quite a bit.
+ * We used to have a generic START bit for all cores selected by CORE_SEL mask.
+ * But now we don't touch CORE_SEL at all because we have a dedicated START bit
+ * for each core:
+ *     bit 0: Core 0 (master)
+ *     bit 1: Core 1 (slave)
+ */
+#define BITS_START_CORE1	1
+
+#define ARCVER_HS38_3_0	0x53
+
+	int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
+	int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
 
-	writel(CMD, (void __iomem *)AXC003_CREG_CPU_START);
+	if (core_family < ARCVER_HS38_3_0) {
+		cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
+		cmd &= ~(1 << BITS_START_MODE);
+	} else {
+		cmd |= (1 << BITS_START_CORE1);
+	}
+	writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
 }
 #endif
diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c
index 77b5000..3bfe511 100644
--- a/board/sysam/amcore/amcore.c
+++ b/board/sysam/amcore/amcore.c
@@ -14,6 +14,8 @@
 #include <dm.h>
 #include <dm/platform_data/serial_coldfire.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void init_lcd(void)
 {
 	/* setup for possible K0108 lcd connected on the parallel port */
@@ -38,7 +40,7 @@ int checkboard(void)
 }
 
 /*
- * in initdram we are here executing from flash
+ * in dram_init we are here executing from flash
  * case 1:
  * is with no ACR/flash cache enabled
  * nop = 40ns (scope measured)
@@ -49,7 +51,7 @@ void fudelay(int usec)
 		asm volatile ("nop");
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	u32 dramsize, RC;
 
@@ -99,7 +101,10 @@ phys_size_t initdram(int board_type)
 	out_be32(&dc->dacr0, 0x0000b344);
 	out_be32((u32 *)0x00000c00, 0xbeaddeed);
 
-	return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
 }
 
 static struct coldfire_serial_platdata mcf5307_serial_plat = {
diff --git a/board/tcm-bf518/Kconfig b/board/tcm-bf518/Kconfig
deleted file mode 100644
index 558c2fe..0000000
--- a/board/tcm-bf518/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_TCM_BF518
-
-config SYS_BOARD
-	default "tcm-bf518"
-
-config SYS_CONFIG_NAME
-	default "tcm-bf518"
-
-endif
diff --git a/board/tcm-bf518/MAINTAINERS b/board/tcm-bf518/MAINTAINERS
deleted file mode 100644
index 1690122..0000000
--- a/board/tcm-bf518/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TCM-BF518 BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/tcm-bf518/
-F:	include/configs/tcm-bf518.h
-F:	configs/tcm-bf518_defconfig
diff --git a/board/tcm-bf518/Makefile b/board/tcm-bf518/Makefile
deleted file mode 100644
index 1ce8f64..0000000
--- a/board/tcm-bf518/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= tcm-bf518.o
diff --git a/board/tcm-bf518/tcm-bf518.c b/board/tcm-bf518/tcm-bf518.c
deleted file mode 100644
index 7923eae..0000000
--- a/board/tcm-bf518/tcm-bf518.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/otp.h>
-#include <asm/sdh.h>
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix TCM-BF518 board\n");
-	printf("       Support: http://www.bluetechnix.com/\n");
-	printf("                http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#if defined(CONFIG_BFIN_MAC)
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_BFIN_SDH
-int board_mmc_init(bd_t *bis)
-{
-	return bfin_mmc_init(bis);
-}
-#endif
diff --git a/board/tcm-bf537/Kconfig b/board/tcm-bf537/Kconfig
deleted file mode 100644
index e0127c6..0000000
--- a/board/tcm-bf537/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_TCM_BF537
-
-config SYS_BOARD
-	default "tcm-bf537"
-
-config SYS_CONFIG_NAME
-	default "tcm-bf537"
-
-endif
diff --git a/board/tcm-bf537/MAINTAINERS b/board/tcm-bf537/MAINTAINERS
deleted file mode 100644
index 1cd4845..0000000
--- a/board/tcm-bf537/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TCM-BF537 BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/tcm-bf537/
-F:	include/configs/tcm-bf537.h
-F:	configs/tcm-bf537_defconfig
diff --git a/board/tcm-bf537/Makefile b/board/tcm-bf537/Makefile
deleted file mode 100644
index 0fe25e8..0000000
--- a/board/tcm-bf537/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= tcm-bf537.o gpio_cfi_flash.o
diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk
deleted file mode 100644
index 7f9138b..0000000
--- a/board/tcm-bf537/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/tcm-bf537/gpio_cfi_flash.c b/board/tcm-bf537/gpio_cfi_flash.c
deleted file mode 100644
index c4fef9f..0000000
--- a/board/tcm-bf537/gpio_cfi_flash.c
+++ /dev/null
@@ -1,3 +0,0 @@
-#define GPIO_PIN_1 GPIO_PF4
-#define GPIO_PIN_2 GPIO_PF5
-#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c
deleted file mode 100644
index 19df51a..0000000
--- a/board/tcm-bf537/tcm-bf537.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include "../cm-bf537e/gpio_cfi_flash.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix TCM-BF537 board\n");
-	printf("       Support: http://www.bluetechnix.at/\n");
-	return 0;
-}
-
-#ifndef CONFIG_BFIN_MAC
-# define bfin_EMAC_initialize(x) 1
-#endif
-#ifndef CONFIG_SMC911X
-# define smc911x_initialize(n, x) 1
-#endif
-int board_eth_init(bd_t *bis)
-{
-	/* return ok if at least 1 eth device works */
-	return bfin_EMAC_initialize(bis) &
-	       smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-
-int misc_init_r(void)
-{
-	gpio_cfi_flash_init();
-
-	return 0;
-}
diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
index d621682..9b56620 100644
--- a/board/theadorable/theadorable.c
+++ b/board/theadorable/theadorable.c
@@ -115,6 +115,13 @@ MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
 	},
 };
 
+/*
+ * Define a board-specific detection pulse-width array for the SerDes PCIe
+ * interfaces. If not defined in the board code, the default of currently 2
+ * is used. Values from 0...3 are possible (2 bits).
+ */
+u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
+
 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
 {
 	/* Only one mode supported for this board */
@@ -287,3 +294,44 @@ int board_late_init(void)
 	return 0;
 }
 #endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
+int do_pcie_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	pci_dev_t bdf;
+	u16 ven_id, dev_id;
+
+	if (argc != 3)
+		return cmd_usage(cmdtp);
+
+	ven_id = simple_strtoul(argv[1], NULL, 16);
+	dev_id = simple_strtoul(argv[2], NULL, 16);
+
+	printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
+	       ven_id, dev_id);
+
+	/*
+	 * Check if the PCIe device is detected (somtimes its not available
+	 * on the PCIe bus)
+	 */
+	bdf = pci_find_device(ven_id, dev_id, 0);
+	if (bdf == -1) {
+		/* PCIe device not found! */
+		printf("Failed to find PCIe device\n");
+	} else {
+		/* PCIe device found! */
+		printf("PCIe device found, resetting board...\n");
+
+		/* default handling: SOFT reset */
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	pcie,   3,   0,     do_pcie_test,
+	"Test for presence of a PCIe device",
+	"<VendorID> <DeviceID>"
+);
+#endif
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 8eaf3e9..3e842d3 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -651,6 +651,21 @@ int board_late_init(void)
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	char *name = NULL;
 
+	if (board_is_bone_lt()) {
+		/* BeagleBoard.org BeagleBone Black Wireless: */
+		if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
+			name = "BBBW";
+		}
+		/* SeeedStudio BeagleBone Green Wireless */
+		if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
+			name = "BBGW";
+		}
+		/* BeagleBoard.org BeagleBone Blue */
+		if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
+			name = "BBBL";
+		}
+	}
+
 	if (board_is_bbg1())
 		name = "BBG1";
 	set_board_info_env(name);
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index df9039c..1cfc08b 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -50,9 +50,23 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define GPIO_ETH_LCD		GPIO_TO_PIN(2, 22)
 /* GPIO 7_11 */
 #define GPIO_DDR_VTT_EN 203
 
+/* Touch screen controller to identify the LCD */
+#define OSD_TS_FT_BUS_ADDRESS	0
+#define OSD_TS_FT_CHIP_ADDRESS	0x38
+#define OSD_TS_FT_REG_ID	0xA3
+/*
+ * Touchscreen IDs for various OSD panels
+ * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
+ */
+/* Used on newer osd101t2587 Panels */
+#define OSD_TS_FT_ID_5x46	0x54
+/* Used on older osd101t2045 Panels */
+#define OSD_TS_FT_ID_5606	0x08
+
 #define SYSINFO_BOARD_NAME_MAX_LEN	45
 
 #define TPS65903X_PRIMARY_SECONDARY_PAD2	0xFB
@@ -449,6 +463,21 @@ void hw_data_init(void)
 	*ctrl = &dra7xx_ctrl;
 }
 
+bool am571x_idk_needs_lcd(void)
+{
+	bool needs_lcd;
+
+	gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
+	if (gpio_get_value(GPIO_ETH_LCD))
+		needs_lcd = false;
+	else
+		needs_lcd = true;
+
+	gpio_free(GPIO_ETH_LCD);
+
+	return needs_lcd;
+}
+
 int board_init(void)
 {
 	gpmc_init();
@@ -457,6 +486,62 @@ int board_init(void)
 	return 0;
 }
 
+void am57x_idk_lcd_detect(void)
+{
+	int r = -ENODEV;
+	char *idk_lcd = "no";
+	uint8_t buf = 0;
+
+	/* Only valid for IDKs */
+	if (board_is_x15() || board_is_am572x_evm())
+		return;
+
+	/* Only AM571x IDK has gpio control detect.. so check that */
+	if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
+		goto out;
+
+	r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
+	if (r) {
+		printf("%s: Failed to set bus address to %d: %d\n",
+		       __func__, OSD_TS_FT_BUS_ADDRESS, r);
+		goto out;
+	}
+	r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
+	if (r) {
+		/* AM572x IDK has no explicit settings for optional LCD kit */
+		if (board_is_am571x_idk()) {
+			printf("%s: Touch screen detect failed: %d!\n",
+			       __func__, r);
+		}
+		goto out;
+	}
+
+	/* Read FT ID */
+	r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
+	if (r) {
+		printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
+		       __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
+		       OSD_TS_FT_REG_ID, r);
+		goto out;
+	}
+
+	switch (buf) {
+	case OSD_TS_FT_ID_5606:
+		idk_lcd = "osd101t2045";
+		break;
+	case OSD_TS_FT_ID_5x46:
+		idk_lcd = "osd101t2587";
+		break;
+	default:
+		printf("%s: Unidentifed Touch screen ID 0x%02x\n",
+		       __func__, buf);
+		/* we will let default be "no lcd" */
+	}
+out:
+	setenv("idk_lcd", idk_lcd);
+	return;
+}
+
 int board_late_init(void)
 {
 	setup_board_eeprom_env();
@@ -489,6 +574,12 @@ int board_late_init(void)
 
 	omap_die_id_serial();
 
+	am57x_idk_lcd_detect();
+
+#if !defined(CONFIG_SPL_BUILD)
+	board_ti_set_ethaddr(2);
+#endif
+
 	return 0;
 }
 
@@ -551,6 +642,17 @@ void recalibrate_iodelay(void)
 		do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 	}
 
+	if (board_is_am571x_idk()) {
+		if (am571x_idk_needs_lcd()) {
+			pconf = core_padconf_array_vout_am571x_idk;
+			pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
+		} else {
+			pconf = core_padconf_array_icss1eth_am571x_idk;
+			pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
+		}
+		do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
+	}
+
 	/* Setup IOdelay configuration */
 	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 err:
diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h
index 2f5243e..aff274c 100644
--- a/board/ti/am57xx/mux_data.h
+++ b/board/ti/am57xx/mux_data.h
@@ -212,7 +212,7 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{MCASP5_FSX, (M3 | PIN_OUTPUT_PULLDOWN)},	/* mcasp5_fsx.uart9_txd */
 	{MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp5_axr0.uart9_ctsn */
 	{MCASP5_AXR1, (M3 | PIN_OUTPUT_PULLUP)},	/* mcasp5_axr1.uart9_rtsn */
-	{MMC1_CLK, (M0 | PIN_OUTPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
 	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
 	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
 	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
@@ -221,7 +221,7 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)},	/* mmc1_sdcd.gpio6_27 */
 	{GPIO6_10, (M10 | PIN_OUTPUT_PULLDOWN)},	/* gpio6_10.ehrpwm2A */
 	{GPIO6_11, (M0 | PIN_INPUT_PULLUP)},	/* gpio6_11.gpio6_11 */
-	{MMC3_CLK, (M0 | PIN_OUTPUT_PULLUP | MANUAL_MODE)},	/* mmc3_clk.mmc3_clk */
+	{MMC3_CLK, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_clk.mmc3_clk */
 	{MMC3_CMD, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_cmd.mmc3_cmd */
 	{MMC3_DAT0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat0.mmc3_dat0 */
 	{MMC3_DAT1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat1.mmc3_dat1 */
@@ -549,13 +549,6 @@ const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = {
 	{VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d0.pr1_uart0_rxd */
 	{VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d1.pr1_uart0_txd */
 	{VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)},	/* vin2a_d2.eCAP1_in_PWM1_out */
-	{VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d3.pr1_mi1_col */
-	{VIN2A_D4, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d4.pr1_mii1_txd1 */
-	{VIN2A_D5, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d5.pr1_mii1_txd0 */
-	{VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d6.pr1_mii_mt1_clk */
-	{VIN2A_D7, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d7.pr1_mii1_txen */
-	{VIN2A_D8, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d8.pr1_mii1_txd3 */
-	{VIN2A_D9, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d9.pr1_mii1_txd2 */
 	{VIN2A_D10, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d10.pr1_mdio_mdclk */
 	{VIN2A_D11, (M11 | PIN_INPUT_PULLUP)},	/* vin2a_d11.pr1_mdio_data */
 	{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
@@ -570,35 +563,7 @@ const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = {
 	{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
 	{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
 	{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
-	{VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_clk.vout1_clk */
-	{VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_de.vout1_de */
 	{VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)},	/* vout1_fld.gpio4_21 */
-	{VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_hsync.vout1_hsync */
-	{VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_vsync.vout1_vsync */
-	{VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d0.vout1_d0 */
-	{VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d1.vout1_d1 */
-	{VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d2.vout1_d2 */
-	{VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d3.vout1_d3 */
-	{VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d4.vout1_d4 */
-	{VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d5.vout1_d5 */
-	{VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d6.vout1_d6 */
-	{VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d7.vout1_d7 */
-	{VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d8.vout1_d8 */
-	{VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d9.vout1_d9 */
-	{VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d10.vout1_d10 */
-	{VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d11.vout1_d11 */
-	{VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d12.vout1_d12 */
-	{VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d13.vout1_d13 */
-	{VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d14.vout1_d14 */
-	{VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d15.vout1_d15 */
-	{VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d16.vout1_d16 */
-	{VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d17.vout1_d17 */
-	{VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d18.vout1_d18 */
-	{VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d19.vout1_d19 */
-	{VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d20.vout1_d20 */
-	{VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d21.vout1_d21 */
-	{VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d22.vout1_d22 */
-	{VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d23.vout1_d23 */
 	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_mclk.mdio_mclk */
 	{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_d.mdio_d */
 	{RMII_MHZ_50_CLK, (M13 | PIN_INPUT_PULLDOWN)},	/* RMII_MHZ_50_CLK.pr2_pru1_gpo2 */
@@ -621,46 +586,46 @@ const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = {
 	{GPIO6_14, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_14.gpio6_14 */
 	{GPIO6_15, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_15.gpio6_15 */
 	{GPIO6_16, (M14 | PIN_INPUT_PULLDOWN)},	/* gpio6_16.gpio6_16 */
-	{XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk0.pr2_mii1_col */
-	{XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk1.pr2_mii1_crs */
+	{XREF_CLK0, (M11 | PIN_INPUT)},	/* xref_clk0.pr2_mii1_col */
+	{XREF_CLK1, (M11 | PIN_INPUT_PULLUP)},	/* xref_clk1.pr2_mii1_crs */
 	{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.gpio6_19 */
 	{XREF_CLK3, (M15 | PIN_INPUT_PULLDOWN)},	/* xref_clk3.Driveroff */
 	{MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp1_aclkx.pr2_mdio_mdclk */
 	{MCASP1_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_fsx.pr2_mdio_data */
 	{MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)},	/* mcasp1_aclkr.gpio5_0 */
 	{MCASP1_FSR, (M14 | PIN_INPUT_PULLUP)},	/* mcasp1_fsr.gpio5_1 */
-	{MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.pr2_mii0_rxer */
-	{MCASP1_AXR1, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr1.pr2_mii_mt0_clk */
+	{MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP)},	/* mcasp1_axr0.pr2_mii0_rxer */
+	{MCASP1_AXR1, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr1.pr2_mii_mt0_clk */
 	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
 	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLUP)},	/* mcasp1_axr3.gpio5_5 */
 	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
 	{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr5.gpio5_7 */
 	{MCASP1_AXR6, (M14 | PIN_INPUT_PULLUP)},	/* mcasp1_axr6.gpio5_8 */
 	{MCASP1_AXR7, (M14 | PIN_INPUT_PULLUP)},	/* mcasp1_axr7.gpio5_9 */
-	{MCASP1_AXR8, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr8.pr2_mii0_txen */
-	{MCASP1_AXR9, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr9.pr2_mii0_txd3 */
-	{MCASP1_AXR10, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr10.pr2_mii0_txd2 */
-	{MCASP1_AXR11, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr11.pr2_mii0_txd1 */
-	{MCASP1_AXR12, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr12.pr2_mii0_txd0 */
-	{MCASP1_AXR13, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.pr2_mii_mr0_clk */
-	{MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},	/* mcasp1_axr14.pr2_mii0_rxdv */
-	{MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr15.pr2_mii0_rxd3 */
-	{MCASP2_ACLKX, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_aclkx.pr2_mii0_rxd2 */
-	{MCASP2_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_fsx.pr2_mii0_rxd1 */
+	{MCASP1_AXR8, (M11 | PIN_OUTPUT)},	/* mcasp1_axr8.pr2_mii0_txen */
+	{MCASP1_AXR9, (M11 | PIN_OUTPUT)},	/* mcasp1_axr9.pr2_mii0_txd3 */
+	{MCASP1_AXR10, (M11 | PIN_OUTPUT)},	/* mcasp1_axr10.pr2_mii0_txd2 */
+	{MCASP1_AXR11, (M11 | PIN_OUTPUT)},	/* mcasp1_axr11.pr2_mii0_txd1 */
+	{MCASP1_AXR12, (M11 | PIN_OUTPUT)},	/* mcasp1_axr12.pr2_mii0_txd0 */
+	{MCASP1_AXR13, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr13.pr2_mii_mr0_clk */
+	{MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr14.pr2_mii0_rxdv */
+	{MCASP1_AXR15, (M11 | PIN_INPUT)},	/* mcasp1_axr15.pr2_mii0_rxd3 */
+	{MCASP2_ACLKX, (M11 | PIN_INPUT)},	/* mcasp2_aclkx.pr2_mii0_rxd2 */
+	{MCASP2_FSX, (M11 | PIN_INPUT)},	/* mcasp2_fsx.pr2_mii0_rxd1 */
 	{MCASP2_ACLKR, (M15 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkr.Driveroff */
 	{MCASP2_FSR, (M15 | PIN_INPUT_PULLDOWN)},	/* mcasp2_fsr.Driveroff */
 	{MCASP2_AXR0, (M15 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr0.Driveroff */
 	{MCASP2_AXR1, (M15 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr1.Driveroff */
-	{MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_axr2.pr2_mii0_rxd0 */
-	{MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},	/* mcasp2_axr3.pr2_mii0_rxlink */
+	{MCASP2_AXR2, (M11 | PIN_INPUT)},	/* mcasp2_axr2.pr2_mii0_rxd0 */
+	{MCASP2_AXR3, (M11 | PIN_INPUT)},	/* mcasp2_axr3.pr2_mii0_rxlink */
 	{MCASP2_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr4.gpio1_4 */
 	{MCASP2_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr5.gpio6_7 */
 	{MCASP2_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr6.gpio2_29 */
 	{MCASP2_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr7.gpio1_5 */
-	{MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.pr2_mii0_crs */
-	{MCASP3_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.pr2_mii0_col */
-	{MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr0.pr2_mii1_rxer */
-	{MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr1.pr2_mii1_rxlink */
+	{MCASP3_ACLKX, (M11 | PIN_INPUT_PULLUP)},	/* mcasp3_aclkx.pr2_mii0_crs */
+	{MCASP3_FSX, (M11 | PIN_INPUT)},	/* mcasp3_fsx.pr2_mii0_col */
+	{MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP)},	/* mcasp3_axr0.pr2_mii1_rxer */
+	{MCASP3_AXR1, (M11 | PIN_INPUT)},	/* mcasp3_axr1.pr2_mii1_rxlink */
 	{MCASP4_ACLKX, (M2 | PIN_INPUT_PULLDOWN)},	/* mcasp4_aclkx.spi3_sclk */
 	{MCASP4_FSX, (M2 | PIN_INPUT_PULLDOWN)},	/* mcasp4_fsx.spi3_d1 */
 	{MCASP4_AXR0, (M15 | PIN_INPUT_PULLDOWN)},	/* mcasp4_axr0.Driveroff */
@@ -677,18 +642,18 @@ const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = {
 	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
 	{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)},	/* mmc1_sdcd.gpio6_27 */
 	{MMC1_SDWP, (M0 | PIN_OUTPUT)},	/* mmc1_sdwp.mmc1_sdwp */
-	{GPIO6_10, (M11 | PIN_INPUT_PULLUP)},	/* gpio6_10.pr2_mii_mt1_clk */
-	{GPIO6_11, (M11 | PIN_INPUT_PULLUP)},	/* gpio6_11.pr2_mii1_txen */
-	{MMC3_CLK, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_clk.pr2_mii1_txd3 */
-	{MMC3_CMD, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_cmd.pr2_mii1_txd2 */
-	{MMC3_DAT0, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat0.pr2_mii1_txd1 */
-	{MMC3_DAT1, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat1.pr2_mii1_txd0 */
-	{MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat2.pr2_mii_mr1_clk */
+	{GPIO6_10, (M11 | PIN_INPUT_PULLDOWN)},	/* gpio6_10.pr2_mii_mt1_clk */
+	{GPIO6_11, (M11 | PIN_OUTPUT)},	/* gpio6_11.pr2_mii1_txen */
+	{MMC3_CLK, (M11 | PIN_OUTPUT)},	/* mmc3_clk.pr2_mii1_txd3 */
+	{MMC3_CMD, (M11 | PIN_OUTPUT)},	/* mmc3_cmd.pr2_mii1_txd2 */
+	{MMC3_DAT0, (M11 | PIN_OUTPUT)},	/* mmc3_dat0.pr2_mii1_txd1 */
+	{MMC3_DAT1, (M11 | PIN_OUTPUT)},	/* mmc3_dat1.pr2_mii1_txd0 */
+	{MMC3_DAT2, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat2.pr2_mii_mr1_clk */
 	{MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat3.pr2_mii1_rxdv */
-	{MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat4.pr2_mii1_rxd3 */
-	{MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat5.pr2_mii1_rxd2 */
-	{MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat6.pr2_mii1_rxd1 */
-	{MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat7.pr2_mii1_rxd0 */
+	{MMC3_DAT4, (M11 | PIN_INPUT)},	/* mmc3_dat4.pr2_mii1_rxd3 */
+	{MMC3_DAT5, (M11 | PIN_INPUT)},	/* mmc3_dat5.pr2_mii1_rxd2 */
+	{MMC3_DAT6, (M11 | PIN_INPUT)},	/* mmc3_dat6.pr2_mii1_rxd1 */
+	{MMC3_DAT7, (M11 | PIN_INPUT)},	/* mmc3_dat7.pr2_mii1_rxd0 */
 	{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.gpio7_7 */
 	{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.gpio7_8 */
 	{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.gpio7_9 */
@@ -727,6 +692,75 @@ const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = {
 	{RSTOUTN, (M0 | PIN_OUTPUT_PULLDOWN)},	/* rstoutn.rstoutn */
 };
 
+const struct pad_conf_entry core_padconf_array_icss1eth_am571x_idk[] = {
+	/* PR1 MII0 */
+	{VOUT1_D8, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d8.pr1_mii_mt0_clk */
+	{VOUT1_D9, (M13 | PIN_OUTPUT)},		/* vout1_d9.pr1_mii0_txd3 */
+	{VOUT1_D10, (M13 | PIN_OUTPUT)},	/* vout1_d10.pr1_mii0_txd2 */
+	{VOUT1_D11, (M13 | PIN_OUTPUT)},	/* vout1_d11.pr1_mii0_txen */
+	{VOUT1_D12, (M13 | PIN_OUTPUT)},	/* vout1_d12.pr1_mii0_txd1 */
+	{VOUT1_D13, (M13 | PIN_OUTPUT)},	/* vout1_d13.pr1_mii0_txd0 */
+	{VOUT1_D14, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d14.pr1_mii_mr0_clk */
+	{VOUT1_D15, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d15.pr1_mii0_rxdv */
+	{VOUT1_D16, (M12 | PIN_INPUT)},	/* vout1_d16.pr1_mii0_rxd3 */
+	{VOUT1_D17, (M12 | PIN_INPUT)},	/* vout1_d17.pr1_mii0_rxd2 */
+	{VOUT1_D18, (M12 | PIN_INPUT)},	/* vout1_d18.pr1_mii0_rxd1 */
+	{VOUT1_D19, (M12 | PIN_INPUT)},	/* vout1_d19.pr1_mii0_rxd0 */
+	{VOUT1_D20, (M12 | PIN_INPUT_PULLUP)},	/* vout1_d20.pr1_mii0_rxer */
+	{VOUT1_D21, (M12 | PIN_INPUT)},	/* vout1_d21.pr1_mii0_rxlink */
+	{VOUT1_D22, (M12 | PIN_INPUT)},	/* vout1_d22.pr1_mii0_col */
+	{VOUT1_D23, (M12 | PIN_INPUT_PULLUP)},	/* vout1_d23.pr1_mii0_crs */
+
+	/* PR1 MII1 */
+	{VIN2A_D3, (M12 | PIN_INPUT)},	/* vin2a_d3.pr1_mi1_col */
+	{VIN2A_D4, (M13 | PIN_OUTPUT)},	/* vin2a_d4.pr1_mii1_txd1 */
+	{VIN2A_D5, (M13 | PIN_OUTPUT)},	/* vin2a_d5.pr1_mii1_txd0 */
+	{VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d6.pr1_mii_mt1_clk */
+	{VIN2A_D7, (M11 | PIN_OUTPUT)},	/* vin2a_d7.pr1_mii1_txen */
+	{VIN2A_D8, (M11 | PIN_OUTPUT)},	/* vin2a_d8.pr1_mii1_txd3 */
+	{VIN2A_D9, (M11 | PIN_OUTPUT)},	/* vin2a_d9.pr1_mii1_txd2 */
+	{VOUT1_VSYNC, (M12 | PIN_INPUT_PULLUP)},	/* vout1_vsync.pr1_mii1_rxer */
+	{VOUT1_D0, (M12 | PIN_INPUT)},	/* vout1_d0.pr1_mii1_rxlink */
+	{VOUT1_D1, (M12 | PIN_INPUT_PULLUP)},	/* vout1_d1.pr1_mii1_crs */
+	{VOUT1_D2, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d2.pr1_mii_mr1_clk */
+	{VOUT1_D3, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d3.pr1_mii1_rxdv */
+	{VOUT1_D4, (M12 | PIN_INPUT)},	/* vout1_d4.pr1_mii1_rxd3 */
+	{VOUT1_D5, (M12 | PIN_INPUT)},	/* vout1_d5.pr1_mii1_rxd2 */
+	{VOUT1_D6, (M12 | PIN_INPUT)},	/* vout1_d6.pr1_mii1_rxd1 */
+	{VOUT1_D7, (M12 | PIN_INPUT)},	/* vout1_d7.pr1_mii1_rxd0 */
+};
+
+const struct pad_conf_entry core_padconf_array_vout_am571x_idk[] = {
+	{VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_de.vout1_de */
+	{VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d23.vout1_d23 */
+};
+
 const struct pad_conf_entry early_padconf[] = {
 	{UART2_CTSN, (M2 | PIN_INPUT_SLEW)},	/* uart2_ctsn.uart3_rxd */
 	{UART2_RTSN, (M1 | PIN_INPUT_SLEW)},	/* uart2_rtsn.uart3_txd */
diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig
index adf73ab..15b5ccf 100644
--- a/board/ti/common/Kconfig
+++ b/board/ti/common/Kconfig
@@ -3,3 +3,13 @@ config TI_I2C_BOARD_DETECT
 	help
 	   Support for detection board information on Texas Instrument's
 	   Evaluation Boards which have I2C based EEPROM detection
+
+config EEPROM_BUS_ADDRESS
+	int "Board EEPROM's I2C bus address"
+	range 0 8
+	default 0
+
+config EEPROM_CHIP_ADDRESS
+	hex "Board EEPROM's I2C chip address"
+	range 0 0xff
+	default 0x50
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index a5dba94..c55e24e 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -314,3 +314,65 @@ void __maybe_unused set_board_info_env(char *name)
 	else
 		setenv("board_serial", unknown);
 }
+
+static u64 mac_to_u64(u8 mac[6])
+{
+	int i;
+	u64 addr = 0;
+
+	for (i = 0; i < 6; i++) {
+		addr <<= 8;
+		addr |= mac[i];
+	}
+
+	return addr;
+}
+
+static void u64_to_mac(u64 addr, u8 mac[6])
+{
+	mac[5] = addr;
+	mac[4] = addr >> 8;
+	mac[3] = addr >> 16;
+	mac[2] = addr >> 24;
+	mac[1] = addr >> 32;
+	mac[0] = addr >> 40;
+}
+
+void board_ti_set_ethaddr(int index)
+{
+	uint8_t mac_addr[6];
+	int i;
+	u64 mac1, mac2;
+	u8 mac_addr1[6], mac_addr2[6];
+	int num_macs;
+	/*
+	 * Export any Ethernet MAC addresses from EEPROM.
+	 * The 2 MAC addresses in EEPROM define the address range.
+	 */
+	board_ti_get_eth_mac_addr(0, mac_addr1);
+	board_ti_get_eth_mac_addr(1, mac_addr2);
+
+	if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
+		mac1 = mac_to_u64(mac_addr1);
+		mac2 = mac_to_u64(mac_addr2);
+
+		/* must contain an address range */
+		num_macs = mac2 - mac1 + 1;
+		if (num_macs <= 0)
+			return;
+
+		if (num_macs > 50) {
+			printf("%s: Too many MAC addresses: %d. Limiting to 50\n",
+			       __func__, num_macs);
+			num_macs = 50;
+		}
+
+		for (i = 0; i < num_macs; i++) {
+			u64_to_mac(mac1 + i, mac_addr);
+			if (is_valid_ethaddr(mac_addr)) {
+				eth_setenv_enetaddr_by_index("eth", i + index,
+							     mac_addr);
+			}
+		}
+	}
+}
diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h
index 343fcb4..88b0a59 100644
--- a/board/ti/common/board_detect.h
+++ b/board/ti/common/board_detect.h
@@ -98,7 +98,7 @@ struct ti_common_eeprom {
 };
 
 #define TI_EEPROM_DATA ((struct ti_common_eeprom *)\
-				OMAP_SRAM_SCRATCH_BOARD_EEPROM_START)
+				TI_SRAM_SCRATCH_BOARD_EEPROM_START)
 
 /**
  * ti_i2c_eeprom_am_get() - Consolidated eeprom data collection for AM* TI EVMs
@@ -193,4 +193,16 @@ u64 board_ti_get_emif2_size(void);
  */
 void set_board_info_env(char *name);
 
+/**
+ * board_ti_set_ethaddr- Sets the ethaddr environment from EEPROM
+ * @index: The first eth<index>addr environment variable to set
+ *
+ * EEPROM should be already read before calling this function.
+ * The EEPROM contains 2 MAC addresses which define the MAC address
+ * range (i.e. first and last MAC address).
+ * This function sets the ethaddr environment variable for all
+ * the available MAC addresses starting from eth<index>addr.
+ */
+void board_ti_set_ethaddr(int index);
+
 #endif	/* __BOARD_DETECT_H */
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index de6fc19..ae2d59d 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -498,7 +498,7 @@ int board_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	u64 ram_size;
 
@@ -510,6 +510,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[1].start = 0x200000000;
 		gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
 	}
+
+	return 0;
 }
 
 int board_late_init(void)
diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig
index c0568ec..9477f53 100644
--- a/board/ti/ks2_evm/Kconfig
+++ b/board/ti/ks2_evm/Kconfig
@@ -49,3 +49,5 @@ config SYS_CONFIG_NAME
 	default "k2g_evm"
 
 endif
+
+source "board/ti/common/Kconfig"
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 372fc35..79e110e 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -12,6 +12,7 @@
 #include <asm/arch/psc_defs.h>
 #include <asm/arch/mmc_host_def.h>
 #include "mux-k2g.h"
+#include "../common/board_detect.h"
 
 #define SYS_CLK		24000000
 
@@ -149,6 +150,24 @@ int board_early_init_f(void)
 }
 #endif
 
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
+	int rc;
+
+	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+			CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc)
+		printf("ti_i2c_eeprom_init failed %d\n", rc);
+
+	board_ti_set_ethaddr(1);
+#endif
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 void spl_init_keystone_plls(void)
 {
diff --git a/board/toradex/apalis-tk1/Kconfig b/board/toradex/apalis-tk1/Kconfig
new file mode 100644
index 0000000..05407ad
--- /dev/null
+++ b/board/toradex/apalis-tk1/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_APALIS_TK1
+
+config SYS_BOARD
+	default "apalis-tk1"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "apalis-tk1"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/board/toradex/apalis-tk1/MAINTAINERS b/board/toradex/apalis-tk1/MAINTAINERS
new file mode 100644
index 0000000..3c908e1
--- /dev/null
+++ b/board/toradex/apalis-tk1/MAINTAINERS
@@ -0,0 +1,7 @@
+Apalis TK1
+M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
+S:	Maintained
+F:	board/toradex/apalis-tk1/
+F:	include/configs/apalis-tk1.h
+F:	configs/apalis-tk1_defconfig
+F:	arch/arm/dts/tegra124-apalis.dtb
diff --git a/board/toradex/apalis-tk1/Makefile b/board/toradex/apalis-tk1/Makefile
new file mode 100644
index 0000000..9ef06dd
--- /dev/null
+++ b/board/toradex/apalis-tk1/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2016 Toradex, Inc.
+# SPDX-License-Identifier:      GPL-2.0+
+
+obj-y	+= as3722_init.o
+obj-y	+= apalis-tk1.o
diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c
new file mode 100644
index 0000000..c7e519c
--- /dev/null
+++ b/board/toradex/apalis-tk1/apalis-tk1.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <power/as3722.h>
+
+#include "../common/tdx-common.h"
+#include "pinmux-config-apalis-tk1.h"
+
+#define LAN_RESET_N TEGRA_GPIO(S, 2)
+
+int arch_misc_init(void)
+{
+	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
+	    NVBOOTTYPE_RECOVERY)
+		printf("USB recovery mode\n");
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Model: Toradex Apalis TK1 2GB\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_clear_tristate_input_clamping();
+
+	gpio_config_table(apalis_tk1_gpio_inits,
+			  ARRAY_SIZE(apalis_tk1_gpio_inits));
+
+	pinmux_config_pingrp_table(apalis_tk1_pingrps,
+				   ARRAY_SIZE(apalis_tk1_pingrps));
+
+	pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
+				   ARRAY_SIZE(apalis_tk1_drvgrps));
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+	struct udevice *pmic;
+	int err;
+
+	err = as3722_init(&pmic);
+	if (err) {
+		error("failed to initialize AS3722 PMIC: %d\n", err);
+		return err;
+	}
+
+	err = as3722_sd_enable(pmic, 4);
+	if (err < 0) {
+		error("failed to enable SD4: %d\n", err);
+		return err;
+	}
+
+	err = as3722_sd_set_voltage(pmic, 4, 0x24);
+	if (err < 0) {
+		error("failed to set SD4 voltage: %d\n", err);
+		return err;
+	}
+
+	err = as3722_gpio_configure(pmic, 1, AS3722_GPIO_OUTPUT_VDDH |
+					     AS3722_GPIO_INVERT);
+	if (err < 0) {
+		error("failed to configure GPIO#1 as output: %d\n", err);
+		return err;
+	}
+
+	err = as3722_gpio_direction_output(pmic, 2, 1);
+	if (err < 0) {
+		error("failed to set GPIO#2 high: %d\n", err);
+		return err;
+	}
+
+	/* Reset I210 Gigabit Ethernet Controller */
+	gpio_request(LAN_RESET_N, "LAN_RESET_N");
+	gpio_direction_output(LAN_RESET_N, 0);
+
+	/*
+	 * Make sure we don't get any back feeding from LAN_WAKE_N resp.
+	 * DEV_OFF_N
+	 */
+	gpio_request(TEGRA_GPIO(O, 5), "LAN_WAKE_N");
+	gpio_direction_output(TEGRA_GPIO(O, 5), 0);
+
+	gpio_request(TEGRA_GPIO(O, 6), "LAN_DEV_OFF_N");
+	gpio_direction_output(TEGRA_GPIO(O, 6), 0);
+
+	/* Make sure LDO9 and LDO10 are initially enabled @ 0V */
+	err = as3722_ldo_enable(pmic, 9);
+	if (err < 0) {
+		error("failed to enable LDO9: %d\n", err);
+		return err;
+	}
+	err = as3722_ldo_enable(pmic, 10);
+	if (err < 0) {
+		error("failed to enable LDO10: %d\n", err);
+		return err;
+	}
+	err = as3722_ldo_set_voltage(pmic, 9, 0x80);
+	if (err < 0) {
+		error("failed to set LDO9 voltage: %d\n", err);
+		return err;
+	}
+	err = as3722_ldo_set_voltage(pmic, 10, 0x80);
+	if (err < 0) {
+		error("failed to set LDO10 voltage: %d\n", err);
+		return err;
+	}
+
+	mdelay(100);
+
+	/* Make sure controller gets enabled by disabling DEV_OFF_N */
+	gpio_set_value(TEGRA_GPIO(O, 6), 1);
+
+	/* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototypes */
+	err = as3722_ldo_set_voltage(pmic, 9, 0xff);
+	if (err < 0) {
+		error("failed to set LDO9 voltage: %d\n", err);
+		return err;
+	}
+	err = as3722_ldo_set_voltage(pmic, 10, 0xff);
+	if (err < 0) {
+		error("failed to set LDO10 voltage: %d\n", err);
+		return err;
+	}
+
+	mdelay(100);
+	gpio_set_value(LAN_RESET_N, 1);
+
+#ifdef APALIS_TK1_PCIE_EVALBOARD_INIT
+#define PEX_PERST_N	TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
+#define RESET_MOCI_CTRL	TEGRA_GPIO(U, 4)
+
+	/* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis Evaluation
+	   Board */
+	gpio_request(PEX_PERST_N, "PEX_PERST_N");
+	gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
+	gpio_direction_output(PEX_PERST_N, 0);
+	gpio_direction_output(RESET_MOCI_CTRL, 0);
+	/* Must be asserted for 100 ms after power and clocks are stable */
+	mdelay(100);
+	gpio_set_value(PEX_PERST_N, 1);
+	/* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed Until
+	   900 us After PEX_PERST# De-assertion */
+	mdelay(1);
+	gpio_set_value(RESET_MOCI_CTRL, 1);
+#endif /* APALIS_T30_PCIE_EVALBOARD_INIT */
+
+	return 0;
+}
+#endif /* CONFIG_PCI_TEGRA */
diff --git a/board/toradex/apalis-tk1/as3722_init.c b/board/toradex/apalis-tk1/as3722_init.c
new file mode 100644
index 0000000..4917034
--- /dev/null
+++ b/board/toradex/apalis-tk1/as3722_init.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2012-2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include "as3722_init.h"
+
+/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(addr, &reg->cmd_addr0);
+	writel(config, &reg->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(data, &reg->cmd_data1);
+	writel(config, &reg->cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+	debug("%s entry\n", __func__);
+
+#ifdef AS3722_SD1VOLTAGE_DATA
+	/* Set up VDD_CORE, for boards where OTP is incorrect*/
+	debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
+	/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+#endif
+
+	debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
+	/*
+	 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
+	/*
+	 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
+	/*
+	 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.2V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__);
+	/*
+	 * Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus.
+	 * First set it to value closest to 3.3V, then enable the regulator
+	 *
+	 * NOTE: We do this early because doing it later seems to hose the CPU
+	 * power rail/partition startup. Need to debug.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__);
+	/*
+	 * Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus.
+	 * First set it to bypass 3.3V straight thru, then enable the regulator
+	 *
+	 * NOTE: We do this early because doing it later seems to hose the CPU
+	 * power rail/partition startup. Need to debug.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+}
diff --git a/board/toradex/apalis-tk1/as3722_init.h b/board/toradex/apalis-tk1/as3722_init.h
new file mode 100644
index 0000000..64898a3
--- /dev/null
+++ b/board/toradex/apalis-tk1/as3722_init.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2012-2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* AS3722-PMIC-specific early init regs */
+
+#define AS3722_I2C_ADDR		0x80
+
+#define AS3722_SD0VOLTAGE_REG	0x00	/* CPU */
+#define AS3722_SD1VOLTAGE_REG	0x01	/* CORE, already set by OTP */
+#define AS3722_SD6VOLTAGE_REG	0x06	/* GPU */
+#define AS3722_SDCONTROL_REG	0x4D
+
+#define AS3722_LDO1VOLTAGE_REG	0x11	/* VDD_SDMMC1 */
+#define AS3722_LDO2VOLTAGE_REG	0x12	/* VPP_FUSE */
+#define AS3722_LDO6VOLTAGE_REG	0x16	/* VDD_SDMMC3 */
+#define AS3722_LDCONTROL_REG	0x4E
+
+#define AS3722_SD0VOLTAGE_DATA	(0x3C00 | AS3722_SD0VOLTAGE_REG)
+#define AS3722_SD0CONTROL_DATA	(0x0100 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD1VOLTAGE_DATA	(0x3200 | AS3722_SD1VOLTAGE_REG)
+#define AS3722_SD1CONTROL_DATA	(0x0200 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD6CONTROL_DATA	(0x4000 | AS3722_SDCONTROL_REG)
+#define AS3722_SD6VOLTAGE_DATA	(0x2800 | AS3722_SD6VOLTAGE_REG)
+
+#define AS3722_LDO1CONTROL_DATA	(0x0200 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO1VOLTAGE_DATA	(0x7F00 | AS3722_LDO1VOLTAGE_REG)
+
+#define AS3722_LDO2CONTROL_DATA	(0x0400 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO2VOLTAGE_DATA	(0x1000 | AS3722_LDO2VOLTAGE_REG)
+
+#define AS3722_LDO6CONTROL_DATA	(0x4000 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO6VOLTAGE_DATA	(0x3F00 | AS3722_LDO6VOLTAGE_REG)
+
+#define I2C_SEND_2_BYTES	0x0A02
+
+void pmic_enable_cpu_vdd(void);
diff --git a/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h b/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
new file mode 100644
index 0000000..5ed0da3
--- /dev/null
+++ b/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright (c) 2016, Toradex, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_APALIS_TK1_H_
+#define _PINMUX_CONFIG_APALIS_TK1_H_
+
+#define GPIO_INIT(_port, _gpio, _init)			\
+	{						\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
+		.init	= TEGRA_GPIO_INIT_##_init,	\
+	}
+
+static const struct tegra_gpio_config apalis_tk1_gpio_inits[] = {
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    1,   IN),
+	GPIO_INIT(B,    1,   IN),
+	GPIO_INIT(C,    0,   OUT0),
+	GPIO_INIT(I,    5,   IN),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(J,    2,   IN),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    7,   IN),
+	GPIO_INIT(N,    2,   OUT1),
+	GPIO_INIT(N,    4,   OUT1),
+	GPIO_INIT(N,    5,   OUT1),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(O,    5,   IN),
+	GPIO_INIT(Q,    0,   OUT0), /* Shift_CTRL_OE[0] */
+	GPIO_INIT(Q,    1,   OUT0), /* Shift_CTRL_OE[1] */
+	GPIO_INIT(Q,    2,   OUT0), /* Shift_CTRL_OE[2] */
+	GPIO_INIT(Q,    4,   OUT0), /* Shift_CTRL_OE[4] */
+	GPIO_INIT(Q,    5,   OUT1), /* Shift_CTRL_Dir_Out[0] */
+	GPIO_INIT(Q,    6,   OUT1), /* Shift_CTRL_Dir_Out[1] */
+	GPIO_INIT(Q,    7,   OUT1), /* Shift_CTRL_Dir_Out[2] */
+	GPIO_INIT(R,    0,   OUT0), /* Shift_CTRL_Dir_In[0] */
+	GPIO_INIT(R,    1,   OUT0), /* Shift_CTRL_Dir_In[1] */
+	GPIO_INIT(R,    2,   OUT0), /* Shift_CTRL_OE[3] */
+	GPIO_INIT(S,    3,   OUT0), /* Shift_CTRL_Dir_In[2] */
+	GPIO_INIT(U,    4,   OUT1),
+	GPIO_INIT(W,    3,   IN),
+	GPIO_INIT(W,    5,   IN),
+	GPIO_INIT(BB,   0,  IN),
+	GPIO_INIT(BB,   3,  OUT0),
+	GPIO_INIT(BB,   4,  IN),
+	GPIO_INIT(BB,   5,  OUT1),
+	GPIO_INIT(BB,   6,  OUT0),
+	GPIO_INIT(CC,   5,  IN),
+	GPIO_INIT(DD,   3,  IN),
+	GPIO_INIT(EE,   3,  IN),
+	GPIO_INIT(EE,   5,  IN),
+	GPIO_INIT(FF,   1,  IN),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.rcv_sel	= PMUX_PIN_RCV_SEL_##_rcv_sel,	\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+static const struct pmux_pingrp_config apalis_tk1_pingrps[] = {
+	/*     pingrp,                 mux,          pull,   tri,      e_input, od,      rcv_sel */
+	PINCFG(CLK_32K_OUT_PA0,        SOC,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_CTS_N_PA1,        GMI,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_FS_PA2,            HDA,          NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_SCLK_PA3,          HDA,          NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_DIN_PA4,           HDA,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_DOUT_PA5,          HDA,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CLK_PA6,         SDMMC3,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CMD_PA7,         SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PB0,                    UARTD,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PB1,                    RSVD2,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT3_PB4,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT2_PB5,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT1_PB6,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT0_PB7,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_RTS_N_PC0,        GMI,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_TXD_PC2,          IRDA,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_RXD_PC3,          IRDA,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GEN1_I2C_SCL_PC4,       I2C1,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(GEN1_I2C_SDA_PC5,       I2C1,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PC7,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG0,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG1,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG2,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG3,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG4,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG5,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG6,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG7,                    SPI4,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH0,                    PWM0,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH1,                    PWM1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH2,                    PWM2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH3,                    PWM3,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH4,                    RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH5,                    RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH6,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH7,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI0,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI1,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI2,                    RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI3,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI4,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI5,                    RSVD2,        UP,     TRISTATE, INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PI6,                    RSVD1,        UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI7,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PJ0,                    RSVD1,        UP,     TRISTATE, INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PJ2,                    RSVD1,        UP,     TRISTATE, INPUT,   ENABLE,  DEFAULT),
+	PINCFG(UART2_CTS_N_PJ5,        UARTB,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART2_RTS_N_PJ6,        UARTB,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PJ7,                    UARTD,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK0,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK1,                    RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK2,                    RSVD1,        UP,     TRISTATE, INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PK3,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK4,                    RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SPDIF_OUT_PK5,          SPDIF,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SPDIF_IN_PK6,           SPDIF,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PK7,                    RSVD2,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP1_FS_PN0,            RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_DIN_PN1,           RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_DOUT_PN2,          SATA,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_SCLK_PN3,          RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(USB_VBUS_EN0_PN4,       RSVD2,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+	PINCFG(USB_VBUS_EN1_PN5,       RSVD2,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+	PINCFG(HDMI_INT_PN7,           RSVD1,        DOWN,   TRISTATE, INPUT,   DEFAULT, NORMAL),
+	PINCFG(ULPI_DATA7_PO0,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA0_PO1,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA1_PO2,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA2_PO3,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA3_PO4,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA4_PO5,         ULPI,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA5_PO6,         ULPI,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA6_PO7,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_FS_PP0,            I2S2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_DIN_PP1,           I2S2,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP3_DOUT_PP2,          I2S2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_SCLK_PP3,          I2S2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_FS_PP4,            RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_DIN_PP5,           RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_DOUT_PP6,          RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_SCLK_PP7,          RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL0_PQ0,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL1_PQ1,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL2_PQ2,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL3_PQ3,            KBC,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL4_PQ4,            KBC,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL5_PQ5,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL6_PQ6,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL7_PQ7,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW0_PR0,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW1_PR1,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW2_PR2,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW3_PR3,            KBC,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW4_PR4,            RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW5_PR5,            RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW6_PR6,            KBC,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW7_PR7,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW8_PS0,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW9_PS1,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW10_PS2,           RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW11_PS3,           RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW12_PS4,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW13_PS5,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW14_PS6,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW15_PS7,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW16_PT0,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW17_PT1,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GEN2_I2C_SCL_PT5,       I2C2,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(GEN2_I2C_SDA_PT6,       I2C2,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC4_CMD_PT7,         SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU0,                    UARTA,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU1,                    UARTA,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU2,                    UARTA,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU3,                    UARTA,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU4,                    GMI,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU5,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU6,                    PWM3,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PV0,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PV1,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CD_N_PV2,        RSVD3,        UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_WP_N_PV3,        SDMMC1,       UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DDC_SCL_PV4,            RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DDC_SDA_PV5,            RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GPIO_W2_AUD_PW2,        SPI2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_W3_AUD_PW3,        SPI6,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP_MCLK1_PW4,          EXTPERIPH1,   NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK2_OUT_PW5,           RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_TXD_PW6,          UARTC,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART3_RXD_PW7,          UARTC,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DVFS_PWM_PX0,           CLDVFS,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X1_AUD_PX1,        RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DVFS_CLK_PX2,           CLDVFS,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X3_AUD_PX3,        RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X4_AUD_PX4,        SPI2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X5_AUD_PX5,        SPI2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X6_AUD_PX6,        SPI2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X7_AUD_PX7,        SPI2,         NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_CLK_PY0,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DIR_PY1,           SPI1,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_NXT_PY2,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_STP_PY3,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT3_PY4,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT2_PY5,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT1_PY6,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT0_PY7,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_CLK_PZ0,         SDMMC1,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_CMD_PZ1,         SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PWR_I2C_SCL_PZ6,        I2CPWR,       NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PWR_I2C_SDA_PZ7,        I2CPWR,       NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC4_DAT0_PAA0,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT1_PAA1,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT2_PAA2,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT3_PAA3,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT4_PAA4,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT5_PAA5,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT6_PAA6,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT7_PAA7,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PBB0,                   VGP6,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CAM_I2C_SCL_PBB1,       I2C3,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(CAM_I2C_SDA_PBB2,       I2C3,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PBB3,                   VGP3,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB4,                   VGP4,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PBB5,                   VGP5,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB6,                   RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB7,                   RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CAM_MCLK_PCC0,          VI_ALT3,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PCC1,                   RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PCC2,                   RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_CLK_PCC4,        SDMMC4,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CLK2_REQ_PCC5,          RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_RST_N_PDD1,      RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_CLKREQ_N_PDD2,   RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_WAKE_N_PDD3,        RSVD2,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_RST_N_PDD5,      RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_CLKREQ_N_PDD6,   RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CLK3_OUT_PEE0,          EXTPERIPH3,   NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK3_REQ_PEE1,          RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP_MCLK1_REQ_PEE2,     RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(HDMI_CEC_PEE3,          CEC,          NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	/*
+	 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output driver enabled aka not
+	 * tristated and input driver enabled as well as it features some magic
+	 * properties even though the external loopback is disabled and the internal
+	 * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
+	 * being set to 0xfffd according to the TRM!
+	 */
+	PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CLK_LB_IN_PEE5,  RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DP_HPD_PFF0,            DP,           NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(USB_VBUS_EN2_PFF1,      RSVD2,        NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	PINCFG(PFF2,                   RSVD2,        NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	PINCFG(CORE_PWR_REQ,           PWRON,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CPU_PWR_REQ,            CPU,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PWR_INT_N,              PMI,          UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(RESET_OUT_N,            RESET_OUT_N,  NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(OWR,                    RSVD2,        NORMAL, TRISTATE, OUTPUT,  DEFAULT, NORMAL),
+	PINCFG(CLK_32K_IN,             CLK,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(JTAG_RTCK,              RTCK,         UP,     NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{						\
+		.drvgrp = PMUX_DRVGRP_##_drvgrp,	\
+		.slwf   = _slwf,			\
+		.slwr   = _slwr,			\
+		.drvup  = _drvup,			\
+		.drvdn  = _drvdn,			\
+		.lpmd   = PMUX_LPMD_##_lpmd,		\
+		.schmt  = PMUX_SCHMT_##_schmt,		\
+		.hsm    = PMUX_HSM_##_hsm,		\
+	}
+
+static const struct pmux_drvgrp_config apalis_tk1_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_APALIS_TK1_H */
diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c
index fef9d2b..92db093 100644
--- a/board/tqc/tqm5200/tqm5200.c
+++ b/board/tqc/tqm5200/tqm5200.c
@@ -128,12 +128,12 @@ static void sdram_start (int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *	      is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
@@ -252,10 +252,12 @@ phys_size_t initdram (int board_type)
 	}
 
 #if defined(CONFIG_TQM5200_B)
-	return dramsize + dramsize2;
+	gd->ram_size = dramsize + dramsize2;
 #else
-	return dramsize;
+	gd->ram_size = dramsize;
 #endif /* CONFIG_TQM5200_B */
+
+	return 0;
 }
 
 int checkboard (void)
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
index eca218c..4642342 100644
--- a/board/tqc/tqm834x/tqm834x.c
+++ b/board/tqc/tqm834x/tqm834x.c
@@ -66,7 +66,7 @@ int board_early_init_r (void) {
 /**************************************************************************
  * DRAM initalization and size detection
  */
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	long bank_size;
 	long size;
@@ -112,7 +112,9 @@ phys_size_t initdram (int board_type)
 		if(size < DDR_MAX_SIZE_PER_CS) break;
 	}
 
-	return size;
+	gd->ram_size = size;
+
+	return 0;
 }
 
 /**************************************************************************
diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c
index 6d17830..58bd7fa 100644
--- a/board/tqc/tqm8xx/tqm8xx.c
+++ b/board/tqc/tqm8xx/tqm8xx.c
@@ -126,13 +126,14 @@ int checkboard (void)
 
 /* ------------------------------------------------------------------------- */
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size8, size9, size10;
 	long int size_b0 = 0;
 	long int size_b1 = 0;
+	int board_type = gd->board_type;
 
 	upmconfig (UPMA, (uint *) sdram_table,
 			   sizeof (sdram_table) / sizeof (uint));
@@ -389,7 +390,9 @@ phys_size_t initdram (int board_type)
 	memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
 	memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
 #endif							/* CONFIG_ISP1362_USB */
-	return (size_b0 + size_b1);
+	gd->ram_size = size_b0 + size_b1;
+
+	return 0;
 }
 
 /* ------------------------------------------------------------------------- */
diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c
index a337729..73227c1 100644
--- a/board/v38b/v38b.c
+++ b/board/v38b/v38b.c
@@ -13,6 +13,7 @@
 #include <net.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start(int hi_addr)
@@ -56,7 +57,7 @@ static void sdram_start(int hi_addr)
 #endif /* !CONFIG_SYS_RAMBOOT */
 
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
@@ -166,7 +167,9 @@ phys_size_t initdram(int board_type)
 		__asm__ volatile ("sync");
 	}
 
-	return dramsize + dramsize2;
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
 }
 
 
diff --git a/board/varisys/cyrus/ddr.c b/board/varisys/cyrus/ddr.c
index bb1d29a..2ba7b3a 100644
--- a/board/varisys/cyrus/ddr.c
+++ b/board/varisys/cyrus/ddr.c
@@ -168,7 +168,7 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -184,5 +184,7 @@ phys_size_t initdram(int board_type)
 	dram_size *= 0x100000;
 
 	debug("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index 7f24a30..3818ab9 100644
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -88,7 +88,7 @@ static long fixed_sdram(void)
 	return msize;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile fsl_lbc_t *lbc = &im->im_lbc;
@@ -106,7 +106,9 @@ phys_size_t initdram(int board_type)
 	sync();
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }
 
 #define VE8313_WDT_EN	0x00020000
diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c
index 3b8a668..ef646fa 100644
--- a/board/xes/xpedite1000/xpedite1000.c
+++ b/board/xes/xpedite1000/xpedite1000.c
@@ -116,9 +116,11 @@ int checkboard(void)
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return spd_sdram();
+	gd->ram_size = spd_sdram();
+
+	return 0;
 }
 
 /*
diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c
index 0028870..19b96f6 100644
--- a/board/xes/xpedite517x/xpedite517x.c
+++ b/board/xes/xpedite517x/xpedite517x.c
@@ -13,6 +13,8 @@
 #include <pca953x.h>
 #include "../common/fsl_8xxx_misc.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
 extern void ft_board_pci_setup(void *blob, bd_t *bd);
 #endif
@@ -56,7 +58,7 @@ int board_early_init_r(void)
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size = fsl_ddr_sdram();
 
@@ -65,7 +67,9 @@ phys_size_t initdram(int board_type)
 	ddr_enable_ecc(dram_size);
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index ccd4ec9..aa55eba 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -25,10 +25,12 @@ static int reset_pin = -1;
 
 ulong ram_base;
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = ram_base;
 	gd->bd->bi_dram[0].size = get_effective_memsize();
+
+	return 0;
 }
 
 int dram_init(void)
diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
index 3729f07..be6b4dc 100644
--- a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
+++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
@@ -10,6 +10,8 @@
 #include <common.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 ulong get_PCI_freq(void)
 {
 	return 0;
@@ -21,10 +23,12 @@ int checkboard(void)
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
+	gd->ram_size = get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
 			    CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
+
+	return 0;
 }
 
 void get_sys_info(sys_info_t *sys_info)
diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
index d823352..07a3ab7 100644
--- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
+++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
@@ -11,16 +11,20 @@
 #include <netdev.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard(void)
 {
 	puts("Xilinx PPC440 Generic Board\n");
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
+	gd->ram_size = get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
 			    CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
+
+	return 0;
 }
 
 void get_sys_info(sys_info_t *sys_info)
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 6a3cbe0..b2fbecf 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -130,9 +130,11 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 }
 
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	fdtdec_setup_memory_banksize();
+
+	return 0;
 }
 
 int dram_init(void)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 4e5871b..3849b58 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -180,9 +180,11 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 }
 
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	fdtdec_setup_memory_banksize();
+
+	return 0;
 }
 
 int dram_init(void)
diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c
index d3ca939..e81d6ff 100644
--- a/board/zipitz2/zipitz2.c
+++ b/board/zipitz2/zipitz2.c
@@ -69,10 +69,12 @@ void usb_board_stop(void)
 }
 #endif
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 #ifdef	CONFIG_CMD_MMC
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 25e3b78..661ae7a 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -452,9 +452,29 @@ config CMD_MMC
 
 config CMD_NAND
 	bool "nand"
+	default y if NAND_SUNXI
 	help
 	  NAND support.
 
+if CMD_NAND
+config CMD_NAND_TRIMFFS
+	bool "nand write.trimffs"
+	default y if ARCH_SUNXI
+	help
+	  Allows one to skip empty pages when flashing something on a NAND.
+
+config CMD_NAND_LOCK_UNLOCK
+	bool "nand lock/unlock"
+	help
+	  NAND locking support.
+
+config CMD_NAND_TORTURE
+	bool "nand torture"
+	help
+	  NAND torture support.
+
+endif # CMD_NAND
+
 config CMD_PART
 	bool "part"
 	select PARTITION_UUIDS
@@ -622,20 +642,6 @@ endmenu
 
 menu "Misc commands"
 
-config CMD_AMBAPP
-	bool "ambapp"
-	depends on LEON3
-	default y
-	help
-	  Lists AMBA Plug-n-Play information.
-
-config SYS_AMBAPP_PRINT_ON_STARTUP
-	bool "Show AMBA PnP info on startup"
-	depends on CMD_AMBAPP
-	default n
-	help
-	  Show AMBA Plug-n-Play information on startup.
-
 config CMD_BKOPS_ENABLE
 	bool "mmc bkops enable"
 	depends on CMD_MMC
@@ -815,12 +821,33 @@ config CMD_FS_GENERIC
 	help
 	  Enables filesystem commands (e.g. load, ls) that work for multiple
 	  fs types.
+
+config CMD_MTDPARTS
+	depends on ARCH_SUNXI
+	bool "MTD partition support"
+	help
+	  MTD partition support
+
+config MTDIDS_DEFAULT
+	string "Default MTD IDs"
+	depends on CMD_MTDPARTS
+	help
+	  Defines a default MTD ID
+
+config MTDPARTS_DEFAULT
+	string "Default MTD partition scheme"
+	depends on CMD_MTDPARTS
+	help
+	  Defines a default MTD partitioning scheme in the Linux MTD command
+	  line partitions format
+
 endmenu
 
 config CMD_UBI
 	tristate "Enable UBI - Unsorted block images commands"
 	select CRC32
 	select MTD_UBI
+	default y if NAND_SUNXI
 	help
 	  UBI is a software layer above MTD layer which admits use of LVM-like
 	  logical volumes on top of MTD devices, hides some complexities of
@@ -829,4 +856,14 @@ config CMD_UBI
 	  (www.linux-mtd.infradead.org). Activate this option if you want
 	  to use U-Boot UBI commands.
 
+config CMD_UBIFS
+	tristate "Enable UBIFS - Unsorted block images filesystem commands"
+	depends on CMD_UBI
+	select CRC32
+	select RBTREE if ARCH_SUNXI
+	select LZO if ARCH_SUNXI
+	default y if NAND_SUNXI
+	help
+	  UBIFS is a file system for flash devices which works on top of UBI.
+
 endmenu
diff --git a/cmd/Makefile b/cmd/Makefile
index f13bb8c..ef1406b 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -14,7 +14,6 @@ obj-y += version.o
 
 # command
 obj-$(CONFIG_CMD_AES) += aes.o
-obj-$(CONFIG_CMD_AMBAPP) += ambapp.o
 obj-$(CONFIG_CMD_ARMFLASH) += armflash.o
 obj-$(CONFIG_SOURCE) += source.o
 obj-$(CONFIG_CMD_SOURCE) += source.o
diff --git a/cmd/aes.c b/cmd/aes.c
index 76da3ef..ee1ae13 100644
--- a/cmd/aes.c
+++ b/cmd/aes.c
@@ -9,7 +9,7 @@
 #include <common.h>
 #include <command.h>
 #include <environment.h>
-#include <aes.h>
+#include <uboot_aes.h>
 #include <malloc.h>
 #include <asm/byteorder.h>
 #include <linux/compiler.h>
diff --git a/cmd/ambapp.c b/cmd/ambapp.c
deleted file mode 100644
index 4b6d174..0000000
--- a/cmd/ambapp.c
+++ /dev/null
@@ -1,575 +0,0 @@
-/*
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * AMBA Plug&Play information list command
- *
- */
-#include <common.h>
-#include <command.h>
-#include <ambapp.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-typedef struct {
-	int device_id;
-	char *name;
-	char *desc;
-} ambapp_device_name;
-
-typedef struct {
-	unsigned int vendor_id;
-	char *name;
-	char *desc;
-	ambapp_device_name *devices;
-} ambapp_vendor_devnames;
-
-/** Vendor GAISLER devices */
-static ambapp_device_name GAISLER_devices[] = {
-	{GAISLER_LEON2DSU, "LEON2DSU", "Leon2 Debug Support Unit"},
-	{GAISLER_LEON3, "LEON3", "Leon3 SPARC V8 Processor"},
-	{GAISLER_LEON3DSU, "LEON3DSU", "Leon3 Debug Support Unit"},
-	{GAISLER_ETHAHB, "ETHAHB", "OC ethernet AHB interface"},
-	{GAISLER_APBMST, "APBMST", "AHB/APB Bridge"},
-	{GAISLER_AHBUART, "AHBUART", "AHB Debug UART"},
-	{GAISLER_SRCTRL, "SRCTRL", "Simple SRAM Controller"},
-	{GAISLER_SDCTRL, "SDCTRL", "PC133 SDRAM Controller"},
-	{GAISLER_SSRCTRL, "SSRCTRL", "Synchronous SRAM Controller"},
-	{GAISLER_APBUART, "APBUART", "Generic UART"},
-	{GAISLER_IRQMP, "IRQMP", "Multi-processor Interrupt Ctrl."},
-	{GAISLER_AHBRAM, "AHBRAM", "Single-port AHB SRAM module"},
-	{GAISLER_AHBDPRAM, "AHBDPRAM", "Dual-port AHB SRAM module"},
-	{GAISLER_GPTIMER, "GPTIMER", "Modular Timer Unit"},
-	{GAISLER_PCITRG, "PCITRG", "Simple 32-bit PCI Target"},
-	{GAISLER_PCISBRG, "PCISBRG", "Simple 32-bit PCI Bridge"},
-	{GAISLER_PCIFBRG, "PCIFBRG", "Fast 32-bit PCI Bridge"},
-	{GAISLER_PCITRACE, "PCITRACE", "32-bit PCI Trace Buffer"},
-	{GAISLER_DMACTRL, "DMACTRL", "AMBA DMA controller"},
-	{GAISLER_AHBTRACE, "AHBTRACE", "AMBA Trace Buffer"},
-	{GAISLER_DSUCTRL, "DSUCTRL", "DSU/ETH controller"},
-	{GAISLER_CANAHB, "CANAHB", "OC CAN AHB interface"},
-	{GAISLER_GPIO, "GPIO", "General Purpose I/O port"},
-	{GAISLER_AHBROM, "AHBROM", "Generic AHB ROM"},
-	{GAISLER_AHBJTAG, "AHBJTAG", "JTAG Debug Link"},
-	{GAISLER_ETHMAC, "ETHMAC", "GR Ethernet MAC"},
-	{GAISLER_SWNODE, "SWNODE", "SpaceWire Node Interface"},
-	{GAISLER_SPW, "SPW", "SpaceWire Serial Link"},
-	{GAISLER_AHB2AHB, "AHB2AHB", "AHB-to-AHB Bridge"},
-	{GAISLER_USBDC, "USBDC", "GR USB 2.0 Device Controller"},
-	{GAISLER_USB_DCL, "USB_DCL", "USB Debug Communication Link"},
-	{GAISLER_DDRMP, "DDRMP", "Multi-port DDR controller"},
-	{GAISLER_ATACTRL, "ATACTRL", "ATA controller"},
-	{GAISLER_DDRSP, "DDRSP", "Single-port DDR266 controller"},
-	{GAISLER_EHCI, "EHCI", "USB Enhanced Host Controller"},
-	{GAISLER_UHCI, "UHCI", "USB Universal Host Controller"},
-	{GAISLER_I2CMST, "I2CMST", "AMBA Wrapper for OC I2C-master"},
-	{GAISLER_SPW2, "SPW2", "GRSPW2 SpaceWire Serial Link"},
-	{GAISLER_AHBDMA, "AHBDMA", ""},
-	{GAISLER_NUHOSP3, "NUHOSP3", "Nuhorizons Spartan3 IO I/F"},
-	{GAISLER_CLKGATE, "CLKGATE", "Clock gating unit"},
-	{GAISLER_SPICTRL, "SPICTRL", "SPI Controller"},
-	{GAISLER_DDR2SP, "DDR2SP", "Single-port DDR2 controller"},
-	{GAISLER_SLINK, "SLINK", "SLINK Master"},
-	{GAISLER_GRTM, "GRTM", "CCSDS Telemetry Encoder"},
-	{GAISLER_GRTC, "GRTC", "CCSDS Telecommand Decoder"},
-	{GAISLER_GRPW, "GRPW", "PacketWire to AMBA AHB I/F"},
-	{GAISLER_GRCTM, "GRCTM", "CCSDS Time Manager"},
-	{GAISLER_GRHCAN, "GRHCAN", "ESA HurriCANe CAN with DMA"},
-	{GAISLER_GRFIFO, "GRFIFO", "FIFO Controller"},
-	{GAISLER_GRADCDAC, "GRADCDAC", "ADC / DAC Interface"},
-	{GAISLER_GRPULSE, "GRPULSE", "General Purpose I/O with Pulses"},
-	{GAISLER_GRTIMER, "GRTIMER", "Timer Unit with Latches"},
-	{GAISLER_AHB2PP, "AHB2PP", "AMBA AHB to Packet Parallel I/F"},
-	{GAISLER_GRVERSION, "GRVERSION", "Version and Revision Register"},
-	{GAISLER_APB2PW, "APB2PW", "PacketWire Transmit Interface"},
-	{GAISLER_PW2APB, "PW2APB", "PacketWire Receive Interface"},
-	{GAISLER_GRCAN, "GRCAN", "CAN Controller with DMA"},
-	{GAISLER_I2CSLV, "I2CSLV", "I2C Slave"},
-	{GAISLER_U16550, "U16550", "Simple 16550 UART"},
-	{GAISLER_AHBMST_EM, "AHBMST_EM", "AMBA Master Emulator"},
-	{GAISLER_AHBSLV_EM, "AHBSLV_EM", "AMBA Slave Emulator"},
-	{GAISLER_GRTESTMOD, "GRTESTMOD", "Test report module"},
-	{GAISLER_ASCS, "ASCS", "ASCS Master"},
-	{GAISLER_IPMVBCTRL, "IPMVBCTRL", "IPM-bus/MVBC memory controller"},
-	{GAISLER_SPIMCTRL, "SPIMCTRL", "SPI Memory Controller"},
-	{GAISLER_L4STAT, "L4STAT", "Leon4 Statistics Module"},
-	{GAISLER_LEON4, "LEON4", "Leon4 SPARC V8 Processor"},
-	{GAISLER_LEON4DSU, "LEON4DSU", "Leon4 Debug Support Unit"},
-	{GAISLER_PWM, "PWM", "PWM generator"},
-	{GAISLER_L2CACHE, "L2CACHE", "L2-Cache Controller"},
-	{GAISLER_SDCTRL64, "SDCTRL64", "64-bit PC133 SDRAM Controller"},
-	{GAISLER_GR1553B, "GR1553B", "MIL-STD-1553B Interface"},
-	{GAISLER_1553TST, "1553TST", "MIL-STD-1553B Test Device"},
-	{GAISLER_GRIOMMU, "GRIOMMU", "I/O Memory Management Unit"},
-	{GAISLER_FTAHBRAM, "FTAHBRAM", "Generic FT AHB SRAM module"},
-	{GAISLER_FTSRCTRL, "FTSRCTRL", "Simple FT SRAM Controller"},
-	{GAISLER_AHBSTAT, "AHBSTAT", "AHB Status Register"},
-	{GAISLER_LEON3FT, "LEON3FT", "Leon3-FT SPARC V8 Processor"},
-	{GAISLER_FTMCTRL, "FTMCTRL", "Memory controller with EDAC"},
-	{GAISLER_FTSDCTRL, "FTSDCTRL", "FT PC133 SDRAM Controller"},
-	{GAISLER_FTSRCTRL8, "FTSRCTRL8", "FT 8-bit SRAM/16-bit IO Ctrl"},
-	{GAISLER_MEMSCRUB, "MEMSCRUB", "AHB Memory Scrubber"},
-	{GAISLER_FTSDCTRL64, "FTSDCTRL64", "64-bit FT SDRAM Controller"},
-	{GAISLER_APBPS2, "APBPS2", "PS2 interface"},
-	{GAISLER_VGACTRL, "VGACTRL", "VGA controller"},
-	{GAISLER_LOGAN, "LOGAN", "On chip Logic Analyzer"},
-	{GAISLER_SVGACTRL, "SVGACTRL", "SVGA frame buffer"},
-	{GAISLER_T1AHB, "T1AHB", "Niagara T1 PCX/AHB bridge"},
-	{GAISLER_MP7WRAP, "MP7WRAP", "CoreMP7 wrapper"},
-	{GAISLER_GRSYSMON, "GRSYSMON", "AMBA wrapper for System Monitor"},
-	{GAISLER_GRACECTRL, "GRACECTRL", "System ACE I/F Controller"},
-	{GAISLER_ATAHBSLV, "ATAHBSLV", "AMBA Test Framework AHB Slave"},
-	{GAISLER_ATAHBMST, "ATAHBMST", "AMBA Test Framework AHB Master"},
-	{GAISLER_ATAPBSLV, "ATAPBSLV", "AMBA Test Framework APB Slave"},
-	{GAISLER_B1553BC, "B1553BC", "AMBA Wrapper for Core1553BBC"},
-	{GAISLER_B1553RT, "B1553RT", "AMBA Wrapper for Core1553BRT"},
-	{GAISLER_B1553BRM, "B1553BRM", "AMBA Wrapper for Core1553BRM"},
-	{GAISLER_AES, "AES", "Advanced Encryption Standard"},
-	{GAISLER_ECC, "ECC", "Elliptic Curve Cryptography"},
-	{GAISLER_PCIF, "PCIF", "AMBA Wrapper for CorePCIF"},
-	{GAISLER_CLKMOD, "CLKMOD", "CPU Clock Switching Ctrl module"},
-	{GAISLER_HAPSTRAK, "HAPSTRAK", "HAPS HapsTrak I/O Port"},
-	{GAISLER_TEST_1X2, "TEST_1X2", "HAPS TEST_1x2 interface"},
-	{GAISLER_WILD2AHB, "WILD2AHB", "WildCard CardBus interface"},
-	{GAISLER_BIO1, "BIO1", "Basic I/O board BIO1"},
-	{GAISLER_AESDMA, "AESDMA", "AES 256 DMA"},
-	{GAISLER_SATCAN, "SATCAN", "SatCAN controller"},
-	{GAISLER_CANMUX, "CANMUX", "CAN Bus multiplexer"},
-	{GAISLER_GRTMRX, "GRTMRX", "CCSDS Telemetry Receiver"},
-	{GAISLER_GRTCTX, "GRTCTX", "CCSDS Telecommand Transmitter"},
-	{GAISLER_GRTMDESC, "GRTMDESC", "CCSDS Telemetry Descriptor"},
-	{GAISLER_GRTMVC, "GRTMVC", "CCSDS Telemetry VC Generator"},
-	{GAISLER_GEFFE, "GEFFE", "Geffe Generator"},
-	{GAISLER_GPREG, "GPREG", "General Purpose Register"},
-	{GAISLER_GRTMPAHB, "GRTMPAHB", "CCSDS Telemetry VC AHB Input"},
-	{GAISLER_SPWCUC, "SPWCUC", "CCSDS CUC / SpaceWire I/F"},
-	{GAISLER_SPW2_DMA, "SPW2_DMA", "GRSPW Router DMA interface"},
-	{GAISLER_SPWROUTER, "SPWROUTER", "GRSPW Router"},
-	{0, NULL, NULL}
-};
-
-
-/** Vendor PENDER devices */
-static ambapp_device_name PENDER_devices[] = {
-	{0, NULL, NULL}
-};
-
-
-/** Vendor ESA devices */
-static ambapp_device_name ESA_devices[] = {
-	{ESA_LEON2, "LEON2", "Leon2 SPARC V8 Processor"},
-	{ESA_LEON2APB, "LEON2APB", "Leon2 Peripheral Bus"},
-	{ESA_IRQ, "IRQ", "Leon2 Interrupt Controller"},
-	{ESA_TIMER, "TIMER", "Leon2 Timer"},
-	{ESA_UART, "UART", "Leon2 UART"},
-	{ESA_CFG, "CFG", "Leon2 Configuration Register"},
-	{ESA_IO, "IO", "Leon2 Input/Output"},
-	{ESA_MCTRL, "MCTRL", "Leon2 Memory Controller"},
-	{ESA_PCIARB, "PCIARB", "PCI Arbiter"},
-	{ESA_HURRICANE, "HURRICANE", "HurriCANe/HurryAMBA CAN Ctrl"},
-	{ESA_SPW_RMAP, "SPW_RMAP", "UoD/Saab SpaceWire/RMAP link"},
-	{ESA_AHBUART, "AHBUART", "Leon2 AHB Debug UART"},
-	{ESA_SPWA, "SPWA", "ESA/ASTRIUM SpaceWire link"},
-	{ESA_BOSCHCAN, "BOSCHCAN", "SSC/BOSCH CAN Ctrl"},
-	{ESA_IRQ2, "IRQ2", "Leon2 Secondary Irq Controller"},
-	{ESA_AHBSTAT, "AHBSTAT", "Leon2 AHB Status Register"},
-	{ESA_WPROT, "WPROT", "Leon2 Write Protection"},
-	{ESA_WPROT2, "WPROT2", "Leon2 Extended Write Protection"},
-	{ESA_PDEC3AMBA, "PDEC3AMBA", "ESA CCSDS PDEC3AMBA TC Decoder"},
-	{ESA_PTME3AMBA, "PTME3AMBA", "ESA CCSDS PTME3AMBA TM Encoder"},
-	{0, NULL, NULL}
-};
-
-
-/** Vendor ASTRIUM devices */
-static ambapp_device_name ASTRIUM_devices[] = {
-	{0, NULL, NULL}
-};
-
-
-/** Vendor OPENCHIP devices */
-static ambapp_device_name OPENCHIP_devices[] = {
-	{OPENCHIP_APBGPIO, "APBGPIO", "APB General Purpose IO"},
-	{OPENCHIP_APBI2C, "APBI2C", "APB I2C Interface"},
-	{OPENCHIP_APBSPI, "APBSPI", "APB SPI Interface"},
-	{OPENCHIP_APBCHARLCD, "APBCHARLCD", "APB Character LCD"},
-	{OPENCHIP_APBPWM, "APBPWM", "APB PWM"},
-	{OPENCHIP_APBPS2, "APBPS2", "APB PS/2 Interface"},
-	{OPENCHIP_APBMMCSD, "APBMMCSD", "APB MMC/SD Card Interface"},
-	{OPENCHIP_APBNAND, "APBNAND", "APB NAND(SmartMedia) Interface"},
-	{OPENCHIP_APBLPC, "APBLPC", "APB LPC Interface"},
-	{OPENCHIP_APBCF, "APBCF", "APB CompactFlash (IDE)"},
-	{OPENCHIP_APBSYSACE, "APBSYSACE", "APB SystemACE Interface"},
-	{OPENCHIP_APB1WIRE, "APB1WIRE", "APB 1-Wire Interface"},
-	{OPENCHIP_APBJTAG, "APBJTAG", "APB JTAG TAP Master"},
-	{OPENCHIP_APBSUI, "APBSUI", "APB Simple User Interface"},
-	{0, NULL, NULL}
-};
-
-
-/** Vendor OPENCORES devices */
-static ambapp_device_name OPENCORES_devices[] = {
-	{OPENCORES_PCIBR, "PCIBR", "PCI Bridge"},
-	{OPENCORES_ETHMAC, "ETHMAC", "Ethernet MAC"},
-	{0, NULL}
-};
-
-
-/** Vendor CONTRIB devices */
-static ambapp_device_name CONTRIB_devices[] = {
-	{CONTRIB_CORE1, "CORE1", "Contributed core 1"},
-	{CONTRIB_CORE2, "CORE2", "Contributed core 2"},
-	{0, NULL, NULL}
-};
-
-
-/** Vendor EONIC devices */
-static ambapp_device_name EONIC_devices[] = {
-	{0, NULL, NULL}
-};
-
-
-/** Vendor RADIONOR devices */
-static ambapp_device_name RADIONOR_devices[] = {
-	{0, NULL, NULL}
-};
-
-
-/** Vendor GLEICHMANN devices */
-static ambapp_device_name GLEICHMANN_devices[] = {
-	{GLEICHMANN_CUSTOM, "CUSTOM", "Custom device"},
-	{GLEICHMANN_GEOLCD01, "GEOLCD01", "GEOLCD01 graphics system"},
-	{GLEICHMANN_DAC, "DAC", "Sigma delta DAC"},
-	{GLEICHMANN_HPI, "HPI", "AHB-to-HPI bridge"},
-	{GLEICHMANN_SPI, "SPI", "SPI master"},
-	{GLEICHMANN_HIFC, "HIFC", "Human interface controller"},
-	{GLEICHMANN_ADCDAC, "ADCDAC", "Sigma delta ADC/DAC"},
-	{GLEICHMANN_SPIOC, "SPIOC", ""},
-	{GLEICHMANN_AC97, "AC97", ""},
-	{0, NULL, NULL}
-};
-
-
-/** Vendor MENTA devices */
-static ambapp_device_name MENTA_devices[] = {
-	{0, NULL, NULL}
-};
-
-
-/** Vendor SUN devices */
-static ambapp_device_name SUN_devices[] = {
-	{SUN_T1, "T1", "Niagara T1 SPARC V9 Processor"},
-	{SUN_S1, "S1", "Niagara S1 SPARC V9 Processor"},
-	{0, NULL, NULL}
-};
-
-
-/** Vendor MOVIDIA devices */
-static ambapp_device_name MOVIDIA_devices[] = {
-	{0, NULL, NULL}
-};
-
-
-/** Vendor ORBITA devices */
-static ambapp_device_name ORBITA_devices[] = {
-	{ORBITA_1553B, "1553B", "MIL-STD-1553B Controller"},
-	{ORBITA_429, "429", "429 Interface"},
-	{ORBITA_SPI, "SPI", "SPI Interface"},
-	{ORBITA_I2C, "I2C", "I2C Interface"},
-	{ORBITA_SMARTCARD, "SMARTCARD", "Smart Card Reader"},
-	{ORBITA_SDCARD, "SDCARD", "SD Card Reader"},
-	{ORBITA_UART16550, "UART16550", "16550 UART"},
-	{ORBITA_CRYPTO, "CRYPTO", "Crypto Engine"},
-	{ORBITA_SYSIF, "SYSIF", "System Interface"},
-	{ORBITA_PIO, "PIO", "Programmable IO module"},
-	{ORBITA_RTC, "RTC", "Real-Time Clock"},
-	{ORBITA_COLORLCD, "COLORLCD", "Color LCD Controller"},
-	{ORBITA_PCI, "PCI", "PCI Module"},
-	{ORBITA_DSP, "DSP", "DPS Co-Processor"},
-	{ORBITA_USBHOST, "USBHOST", "USB Host"},
-	{ORBITA_USBDEV, "USBDEV", "USB Device"},
-	{0, NULL, NULL}
-};
-
-
-/** Vendor SYNOPSYS devices */
-static ambapp_device_name SYNOPSYS_devices[] = {
-	{0, NULL, NULL}
-};
-
-
-/** Vendor NASA devices */
-static ambapp_device_name NASA_devices[] = {
-	{NASA_EP32, "EP32", "EP32 Forth processor"},
-	{0, NULL, NULL}
-};
-
-
-/** Vendor CAL devices */
-static ambapp_device_name CAL_devices[] = {
-	{CAL_DDRCTRL, "DDRCTRL", ""},
-	{0, NULL, NULL}
-};
-
-
-/** Vendor EMBEDDIT devices */
-static ambapp_device_name EMBEDDIT_devices[] = {
-	{0, NULL, NULL}
-};
-
-
-/** Vendor CETON devices */
-static ambapp_device_name CETON_devices[] = {
-	{0, NULL, NULL}
-};
-
-
-/** Vendor S3 devices */
-static ambapp_device_name S3_devices[] = {
-	{0, NULL, NULL}
-};
-
-
-/** Vendor ACTEL devices */
-static ambapp_device_name ACTEL_devices[] = {
-	{ACTEL_COREMP7, "COREMP7", "CoreMP7 Processor"},
-	{0, NULL, NULL}
-};
-
-
-/** Vendor APPLECORE devices */
-static ambapp_device_name APPLECORE_devices[] = {
-	{APPLECORE_UTLEON3, "UTLEON3", "AppleCore uT-LEON3 Processor"},
-	{APPLECORE_UTLEON3DSU, "UTLEON3DSU", "AppleCore uT-LEON3 DSU"},
-	{0, NULL, NULL}
-};
-
-
-/** Vendors and their devices */
-static ambapp_vendor_devnames vendors[] = {
-	{VENDOR_GAISLER, "GAISLER", "Gaisler Research", GAISLER_devices},
-	{VENDOR_PENDER, "PENDER", "", PENDER_devices},
-	{VENDOR_ESA, "ESA", "European Space Agency", ESA_devices},
-	{VENDOR_ASTRIUM, "ASTRIUM", "", ASTRIUM_devices},
-	{VENDOR_OPENCHIP, "OPENCHIP", "OpenChip", OPENCHIP_devices},
-	{VENDOR_OPENCORES, "OPENCORES", "OpenCores", OPENCORES_devices},
-	{VENDOR_CONTRIB, "CONTRIB", "Various contributions", CONTRIB_devices},
-	{VENDOR_EONIC, "EONIC", "Eonic BV", EONIC_devices},
-	{VENDOR_RADIONOR, "RADIONOR", "Radionor Communications", RADIONOR_devices},
-	{VENDOR_GLEICHMANN, "GLEICHMANN", "Gleichmann Electronics", GLEICHMANN_devices},
-	{VENDOR_MENTA, "MENTA", "Menta", MENTA_devices},
-	{VENDOR_SUN, "SUN", "Sun Microsystems", SUN_devices},
-	{VENDOR_MOVIDIA, "MOVIDIA", "", MOVIDIA_devices},
-	{VENDOR_ORBITA, "ORBITA", "Orbita", ORBITA_devices},
-	{VENDOR_SYNOPSYS, "SYNOPSYS", "Synopsys Inc.", SYNOPSYS_devices},
-	{VENDOR_NASA, "NASA", "NASA", NASA_devices},
-	{VENDOR_S3, "S3", "S3 Group", S3_devices},
-	{VENDOR_CAL, "CAL", "", CAL_devices},
-	{VENDOR_EMBEDDIT, "EMBEDDIT", "Embedd.it", EMBEDDIT_devices},
-	{VENDOR_CETON, "CETON", "Ceton Corporation", CETON_devices},
-	{VENDOR_ACTEL, "ACTEL", "Actel Corporation", ACTEL_devices},
-	{VENDOR_APPLECORE, "APPLECORE", "AppleCore", APPLECORE_devices},
-	{0, NULL, NULL, NULL}
-};
-
-static ambapp_device_name *ambapp_get_dev(ambapp_device_name *devs, int id)
-{
-	if (!devs)
-		return NULL;
-
-	while (devs->device_id > 0) {
-		if (devs->device_id == id)
-			return devs;
-		devs++;
-	}
-	return NULL;
-}
-
-char *ambapp_device_id2str(int vendor, int id)
-{
-	ambapp_vendor_devnames *ven = &vendors[0];
-	ambapp_device_name *dev;
-
-	while (ven->vendor_id > 0) {
-		if (ven->vendor_id == vendor) {
-			dev = ambapp_get_dev(ven->devices, id);
-			if (!dev)
-				return NULL;
-			return dev->name;
-		}
-		ven++;
-	}
-	return NULL;
-}
-
-char *ambapp_device_id2desc(int vendor, int id)
-{
-	ambapp_vendor_devnames *ven = &vendors[0];
-	ambapp_device_name *dev;
-
-	while (ven->vendor_id > 0) {
-		if (ven->vendor_id == vendor) {
-			dev = ambapp_get_dev(ven->devices, id);
-			if (!dev)
-				return NULL;
-			return dev->desc;
-		}
-		ven++;
-	}
-	return NULL;
-}
-
-char *ambapp_vendor_id2str(int vendor)
-{
-	ambapp_vendor_devnames *ven = &vendors[0];
-
-	while (ven->vendor_id > 0) {
-		if (ven->vendor_id == vendor) {
-			return ven->name;
-		}
-		ven++;
-	}
-	return NULL;
-}
-
-static char *unknown = "unknown";
-
-char *ambapp_type_names[4] = {
-	/* 0 */ "UNUSED",
-	/* 1 */ "apb",
-	/* 2 */ "ahbmem",
-	/* 3 */ "ahbio"
-};
-
-/* Print one APB device */
-void ambapp_print_apb(ambapp_apbdev *dev, int index)
-{
-	char *dev_str, *ven_str;
-	unsigned int freq;
-
-	ven_str = ambapp_vendor_id2str(dev->vendor);
-	if (!ven_str) {
-		ven_str = unknown;
-		dev_str = unknown;
-	} else {
-		dev_str = ambapp_device_id2str(dev->vendor, dev->device);
-		if (!dev_str)
-			dev_str = unknown;
-	}
-
-	/* Get Frequency of Core */
-	freq = ambapp_bus_freq(&ambapp_plb, dev->ahb_bus_index);
-
-	printf("0x%02x:0x%02x:0x%02x: %s  %s  (%dkHz)\n"
-	       "   apb: 0x%08x - 0x%08x\n"
-	       "   irq: %-2d (ver: %-2d)\n",
-	       index, dev->vendor, dev->device, ven_str, dev_str, freq / 1000,
-	       dev->address, dev->address + (dev->mask-1),
-	       dev->irq, dev->ver);
-}
-
-void ambapp_print_ahb(ambapp_ahbdev *dev, int index)
-{
-	char *dev_str, *ven_str, *type_str;
-	int i;
-	unsigned int freq;
-
-	ven_str = ambapp_vendor_id2str(dev->vendor);
-	if (!ven_str) {
-		ven_str = unknown;
-		dev_str = unknown;
-	} else {
-		dev_str = ambapp_device_id2str(dev->vendor, dev->device);
-		if (!dev_str)
-			dev_str = unknown;
-	}
-
-	/* Get Frequency of Core */
-	freq = ambapp_bus_freq(&ambapp_plb, dev->ahb_bus_index);
-
-	printf("0x%02x:0x%02x:0x%02x: %s  %s  (%dkHz)\n",
-	       index, dev->vendor, dev->device, ven_str, dev_str, freq / 1000);
-
-	for (i = 0; i < 4; i++) {
-		if (dev->type[i] == 0)
-			continue;
-		type_str = ambapp_type_names[dev->type[i]];
-		printf("   %-7s: 0x%08x - 0x%08x\n", type_str, dev->address[i],
-			dev->address[i] + (dev->mask[i]-1));
-	}
-
-	printf("   irq: %-2d (ver: %d)\n", dev->irq, dev->ver);
-}
-
-int do_ambapp_print(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	int index;
-	ambapp_apbdev apbdev;
-	ambapp_ahbdev ahbdev;
-
-	/* Print AHB Masters */
-	puts("\n--------- AHB Masters ---------\n");
-	index = 0;
-	while (ambapp_ahbmst_find(&ambapp_plb, 0, 0, index, &ahbdev) == 1) {
-		/* Found a AHB Master Device */
-		ambapp_print_ahb(&ahbdev, index);
-		index++;
-	}
-
-	/* Print AHB Slaves */
-	puts("\n--------- AHB Slaves  ---------\n");
-	index = 0;
-	while (ambapp_ahbslv_find(&ambapp_plb, 0, 0, index, &ahbdev) == 1) {
-		/* Found a AHB Slave Device */
-		ambapp_print_ahb(&ahbdev, index);
-		index++;
-	}
-
-	/* Print APB Slaves */
-	puts("\n--------- APB Slaves  ---------\n");
-	index = 0;
-	while (ambapp_apb_find(&ambapp_plb, 0, 0, index, &apbdev) == 1) {
-		/* Found a APB Slave Device */
-		ambapp_print_apb(&apbdev, index);
-		index++;
-	}
-
-	puts("\n");
-	return 0;
-}
-
-int ambapp_init_reloc(void)
-{
-	ambapp_vendor_devnames *vend = vendors;
-	ambapp_device_name *dev;
-
-	while (vend->vendor_id && vend->name) {
-		vend->name = (char *)((unsigned int)vend->name + gd->reloc_off);
-		vend->desc = (char *)((unsigned int)vend->desc + gd->reloc_off);
-		vend->devices = (ambapp_device_name *)
-			((unsigned int)vend->devices + gd->reloc_off);
-		dev = vend->devices;
-		vend++;
-		if (!dev)
-			continue;
-		while (dev->device_id && dev->name) {
-			dev->name =
-			    (char *)((unsigned int)dev->name + gd->reloc_off);
-			dev->desc =
-			    (char *)((unsigned int)dev->desc + gd->reloc_off);
-			dev++;
-		}
-	}
-	return 0;
-}
-
-U_BOOT_CMD(
-	ambapp, 1, 1, do_ambapp_print,
-	"list AMBA Plug&Play information",
-	"ambapp\n"
-	"    - lists AMBA (AHB & APB) Plug&Play devices present on the system"
-);
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 19b8fd8..ff3cce0 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -114,7 +114,7 @@ static inline void print_bi_flash(const bd_t *bd)
 	print_num("flash size     ",	(ulong)bd->bi_flashsize);
 	print_num("flash offset   ",	(ulong)bd->bi_flashoffset);
 
-#elif defined(CONFIG_NIOS2) || defined(CONFIG_OPENRISC)
+#elif defined(CONFIG_NIOS2)
 	print_num("flash start",	(ulong)bd->bi_flashstart);
 	print_num("flash size",		(ulong)bd->bi_flashsize);
 	print_num("flash offset",	(ulong)bd->bi_flashoffset);
@@ -152,8 +152,6 @@ static inline void print_baudrate(void)
 {
 #if defined(CONFIG_PPC)
 	printf("baudrate    = %6u bps\n", gd->baudrate);
-#elif defined(CONFIG_SPARC)
-	printf("baudrate               = %6u bps\n", gd->baudrate);
 #else
 	printf("baudrate    = %u bps\n", gd->baudrate);
 #endif
@@ -277,36 +275,6 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
-#elif defined(CONFIG_SPARC)
-
-int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	bd_t *bd = gd->bd;
-
-#ifdef DEBUG
-	print_num("bd address             ", (ulong) bd);
-#endif
-	print_num("memstart               ", bd->bi_memstart);
-	print_lnum("memsize                ", bd->bi_memsize);
-	print_num("flashstart             ", bd->bi_flashstart);
-	print_num("CONFIG_SYS_MONITOR_BASE       ", CONFIG_SYS_MONITOR_BASE);
-	print_num("CONFIG_ENV_ADDR           ", CONFIG_ENV_ADDR);
-	printf("CONFIG_SYS_RELOC_MONITOR_BASE = 0x%x (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE,
-	       CONFIG_SYS_MONITOR_LEN);
-	printf("CONFIG_SYS_MALLOC_BASE        = 0x%x (%d)\n", CONFIG_SYS_MALLOC_BASE,
-	       CONFIG_SYS_MALLOC_LEN);
-	printf("CONFIG_SYS_INIT_SP_OFFSET     = 0x%x (%d)\n", CONFIG_SYS_INIT_SP_OFFSET,
-	       CONFIG_SYS_STACK_SIZE);
-	printf("CONFIG_SYS_PROM_OFFSET        = 0x%x (%d)\n", CONFIG_SYS_PROM_OFFSET,
-	       CONFIG_SYS_PROM_SIZE);
-	printf("CONFIG_SYS_GBL_DATA_OFFSET    = 0x%x (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
-	       GENERATED_GBL_DATA_SIZE);
-
-	print_eth_ip_addr();
-	print_baudrate();
-	return 0;
-}
-
 #elif defined(CONFIG_M68K)
 
 int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -338,24 +306,6 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
-#elif defined(CONFIG_BLACKFIN)
-
-int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	bd_t *bd = gd->bd;
-
-	printf("U-Boot      = %s\n", bd->bi_r_version);
-	printf("CPU         = %s\n", bd->bi_cpu);
-	printf("Board       = %s\n", bd->bi_board_name);
-	print_mhz("VCO",	bd->bi_vco);
-	print_mhz("CCLK",	bd->bi_cclk);
-	print_mhz("SCLK",	bd->bi_sclk);
-
-	print_std_bdinfo(bd);
-
-	return 0;
-}
-
 #elif defined(CONFIG_MIPS)
 
 int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -493,20 +443,6 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
-#elif defined(CONFIG_OPENRISC)
-
-int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	bd_t *bd = gd->bd;
-
-	print_bi_mem(bd);
-	print_bi_flash(bd);
-	print_eth_ip_addr();
-	print_baudrate();
-
-	return 0;
-}
-
 #elif defined(CONFIG_ARC)
 
 int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/cmd/cros_ec.c b/cmd/cros_ec.c
index 9d42f87..af0b4ee 100644
--- a/cmd/cros_ec.c
+++ b/cmd/cros_ec.c
@@ -110,7 +110,7 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		/* Remove any existing device */
 		ret = uclass_find_device(UCLASS_CROS_EC, 0, &udev);
 		if (!ret)
-			device_remove(udev);
+			device_remove(udev, DM_REMOVE_NORMAL);
 		ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev);
 		if (ret) {
 			printf("Could not init cros_ec device (err %d)\n", ret);
diff --git a/cmd/i2c.c b/cmd/i2c.c
index 473153f..3dd7c6b 100644
--- a/cmd/i2c.c
+++ b/cmd/i2c.c
@@ -151,6 +151,16 @@ static int cmd_i2c_set_bus_num(unsigned int busnum)
 
 static int i2c_get_cur_bus(struct udevice **busp)
 {
+#ifdef CONFIG_I2C_SET_DEFAULT_BUS_NUM
+	if (!i2c_cur_bus) {
+		if (cmd_i2c_set_bus_num(CONFIG_I2C_DEFAULT_BUS_NUMBER)) {
+			printf("Default I2C bus %d not found\n",
+			       CONFIG_I2C_DEFAULT_BUS_NUMBER);
+			return -ENODEV;
+		}
+	}
+#endif
+
 	if (!i2c_cur_bus) {
 		puts("No I2C bus selected\n");
 		return -ENODEV;
diff --git a/cmd/mem.c b/cmd/mem.c
index 83d34fa..b6e200b 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -112,27 +112,6 @@ static int do_mem_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		}
 	} while (nbytes > 0);
 #else
-
-# if defined(CONFIG_BLACKFIN)
-	/* See if we're trying to display L1 inst */
-	if (addr_bfin_on_chip_mem(addr)) {
-		char linebuf[DISP_LINE_LEN];
-		ulong linebytes, nbytes = length * size;
-		do {
-			linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
-			memcpy(linebuf, (void *)addr, linebytes);
-			print_buffer(addr, linebuf, size, linebytes/size, DISP_LINE_LEN/size);
-
-			nbytes -= linebytes;
-			addr += linebytes;
-			if (ctrlc()) {
-				rc = 1;
-				break;
-			}
-		} while (nbytes > 0);
-	} else
-# endif
-
 	{
 		ulong bytes = size * length;
 		const void *buf = map_sysmem(addr, bytes);
@@ -314,13 +293,6 @@ static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	}
 #endif
 
-#ifdef CONFIG_BLACKFIN
-	if (addr_bfin_on_chip_mem(addr1) || addr_bfin_on_chip_mem(addr2)) {
-		puts ("Comparison with L1 instruction memory not supported.\n\r");
-		return 0;
-	}
-#endif
-
 	bytes = size * count;
 	base = buf1 = map_sysmem(addr1, bytes);
 	buf2 = map_sysmem(addr2, bytes);
@@ -455,14 +427,6 @@ static int do_mem_cp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	}
 #endif
 
-#ifdef CONFIG_BLACKFIN
-	/* See if we're copying to/from L1 inst */
-	if (addr_bfin_on_chip_mem(dest) || addr_bfin_on_chip_mem(addr)) {
-		memcpy((void *)dest, (void *)addr, count * size);
-		return 0;
-	}
-#endif
-
 	memcpy((void *)dest, (void *)addr, count * size);
 
 	return 0;
@@ -1115,13 +1079,6 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
 	}
 #endif
 
-#ifdef CONFIG_BLACKFIN
-	if (addr_bfin_on_chip_mem(addr)) {
-		puts ("Can't modify L1 instruction in place. Use cp instead.\n\r");
-		return 0;
-	}
-#endif
-
 	/* Print the address, followed by value.  Then accept input for
 	 * the next value.  A non-converted value exits.
 	 */
diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
index b9b160d..112bf1f 100644
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -110,11 +110,19 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* default values for mtdids and mtdparts variables */
 #if !defined(MTDIDS_DEFAULT)
+#ifdef CONFIG_MTDIDS_DEFAULT
+#define MTDIDS_DEFAULT CONFIG_MTDIDS_DEFAULT
+#else
 #define MTDIDS_DEFAULT NULL
 #endif
+#endif
 #if !defined(MTDPARTS_DEFAULT)
+#ifdef CONFIG_MTDPARTS_DEFAULT
+#define MTDPARTS_DEFAULT CONFIG_MTDPARTS_DEFAULT
+#else
 #define MTDPARTS_DEFAULT NULL
 #endif
+#endif
 #if defined(CONFIG_SYS_MTDPARTS_RUNTIME)
 extern void board_mtdparts_default(const char **mtdids, const char **mtdparts);
 #endif
diff --git a/cmd/pci.c b/cmd/pci.c
index 7993c1a..41b4fff 100644
--- a/cmd/pci.c
+++ b/cmd/pci.c
@@ -606,6 +606,47 @@ static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
 	return 0;
 }
 
+#ifdef CONFIG_DM_PCI
+static const struct pci_flag_info {
+	uint flag;
+	const char *name;
+} pci_flag_info[] = {
+	{ PCI_REGION_IO, "io" },
+	{ PCI_REGION_PREFETCH, "prefetch" },
+	{ PCI_REGION_SYS_MEMORY, "sysmem" },
+	{ PCI_REGION_RO, "readonly" },
+	{ PCI_REGION_IO, "io" },
+};
+
+static void pci_show_regions(struct udevice *bus)
+{
+	struct pci_controller *hose = dev_get_uclass_priv(bus);
+	const struct pci_region *reg;
+	int i, j;
+
+	if (!hose) {
+		printf("Bus '%s' is not a PCI controller\n", bus->name);
+		return;
+	}
+
+	printf("#   %-16s %-16s %-16s  %s\n", "Bus start", "Phys start", "Size",
+	       "Flags");
+	for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
+		printf("%d   %#016llx %#016llx %#016llx  ", i,
+		       (unsigned long long)reg->bus_start,
+		       (unsigned long long)reg->phys_start,
+		       (unsigned long long)reg->size);
+		if (!(reg->flags & PCI_REGION_TYPE))
+			printf("mem ");
+		for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) {
+			if (reg->flags & pci_flag_info[j].flag)
+				printf("%s ", pci_flag_info[j].name);
+		}
+		printf("\n");
+	}
+}
+#endif
+
 /* PCI Configuration Space access commands
  *
  * Syntax:
@@ -657,10 +698,11 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		pci_init();
 		return 0;
 #endif
+	case 'r': /* no break */
 	default:		/* scan bus */
 		value = 1; /* short listing */
 		if (argc > 1) {
-			if (argv[argc-1][0] == 'l') {
+			if (cmd != 'r' && argv[argc-1][0] == 'l') {
 				value = 0;
 				argc--;
 			}
@@ -673,7 +715,10 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			printf("No such bus\n");
 			return CMD_RET_FAILURE;
 		}
-		pciinfo(bus, value);
+		if (cmd == 'r')
+			pci_show_regions(bus);
+		else
+			pciinfo(bus, value);
 #else
 		pciinfo(busnum, value);
 #endif
@@ -745,6 +790,8 @@ static char pci_help_text[] =
 #ifdef CONFIG_DM_PCI
 	"pci bar b.d.f\n"
 	"    - show BARs base and size for device b.d.f'\n"
+	"pci regions\n"
+	"    - show PCI regions\n"
 #endif
 	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
 	"    - display PCI configuration space (CFG)\n"
diff --git a/cmd/reginfo.c b/cmd/reginfo.c
index 5f19e79..a3696d1 100644
--- a/cmd/reginfo.c
+++ b/cmd/reginfo.c
@@ -172,64 +172,7 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
 
 #elif defined(CONFIG_MPC85xx)
 	mpc85xx_reginfo();
-
-#elif defined(CONFIG_BLACKFIN)
-	puts("\nSystem Configuration registers\n");
-#ifndef __ADSPBF60x__
-	puts("\nPLL Registers\n");
-	printf("\tPLL_DIV:   0x%04x   PLL_CTL:      0x%04x\n",
-		bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
-	printf("\tPLL_STAT:  0x%04x   PLL_LOCKCNT:  0x%04x\n",
-		bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
-	printf("\tVR_CTL:    0x%04x\n", bfin_read_VR_CTL());
-
-	puts("\nEBIU AMC Registers\n");
-	printf("\tEBIU_AMGCTL:   0x%04x\n", bfin_read_EBIU_AMGCTL());
-	printf("\tEBIU_AMBCTL0:  0x%08x   EBIU_AMBCTL1:  0x%08x\n",
-		bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
-# ifdef EBIU_MODE
-	printf("\tEBIU_MBSCTL:   0x%08x   EBIU_ARBSTAT:  0x%08x\n",
-		bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
-	printf("\tEBIU_MODE:     0x%08x   EBIU_FCTL:     0x%08x\n",
-		bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
-# endif
-
-# ifdef EBIU_RSTCTL
-	puts("\nEBIU DDR Registers\n");
-	printf("\tEBIU_DDRCTL0:  0x%08x   EBIU_DDRCTL1:  0x%08x\n",
-		bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
-	printf("\tEBIU_DDRCTL2:  0x%08x   EBIU_DDRCTL3:  0x%08x\n",
-		bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
-	printf("\tEBIU_DDRQUE:   0x%08x   EBIU_RSTCTL    0x%04x\n",
-		bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
-	printf("\tEBIU_ERRADD:   0x%08x   EBIU_ERRMST:   0x%04x\n",
-		bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
-# else
-	puts("\nEBIU SDC Registers\n");
-	printf("\tEBIU_SDRRC:   0x%04x   EBIU_SDBCTL:  0x%04x\n",
-		bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
-	printf("\tEBIU_SDSTAT:  0x%04x   EBIU_SDGCTL:  0x%08x\n",
-		bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
-# endif
-#else
-	puts("\nCGU Registers\n");
-	printf("\tCGU_DIV:   0x%08x   CGU_CTL:      0x%08x\n",
-		bfin_read_CGU_DIV(), bfin_read_CGU_CTL());
-	printf("\tCGU_STAT:  0x%08x   CGU_LOCKCNT:  0x%08x\n",
-		bfin_read_CGU_STAT(), bfin_read_CGU_CLKOUTSEL());
-
-	puts("\nSMC DDR Registers\n");
-	printf("\tDDR_CFG:   0x%08x   DDR_TR0:      0x%08x\n",
-		bfin_read_DMC0_CFG(), bfin_read_DMC0_TR0());
-	printf("\tDDR_TR1:   0x%08x   DDR_TR2:      0x%08x\n",
-		bfin_read_DMC0_TR1(), bfin_read_DMC0_TR2());
-	printf("\tDDR_MR:    0x%08x   DDR_EMR1:     0x%08x\n",
-		bfin_read_DMC0_MR(), bfin_read_DMC0_EMR1());
-	printf("\tDDR_CTL:   0x%08x   DDR_STAT:     0x%08x\n",
-		bfin_read_DMC0_CTL(), bfin_read_DMC0_STAT());
-	printf("\tDDR_DLLCTL:0x%08x\n", bfin_read_DMC0_DLLCTL());
 #endif
-#endif /* CONFIG_BLACKFIN */
 
 	return 0;
 }
diff --git a/cmd/sf.c b/cmd/sf.c
index 65b117f..f971eec 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -124,7 +124,7 @@ static int do_spi_flash_probe(int argc, char * const argv[])
 	/* Remove the old device, otherwise probe will just be a nop */
 	ret = spi_find_bus_and_cs(bus, cs, &bus_dev, &new);
 	if (!ret) {
-		device_remove(new);
+		device_remove(new, DM_REMOVE_NORMAL);
 	}
 	flash = NULL;
 	ret = spi_flash_probe_bus_cs(bus, cs, speed, mode, &new);
diff --git a/cmd/tpm.c b/cmd/tpm.c
index 625fc43..0c4bc73 100644
--- a/cmd/tpm.c
+++ b/cmd/tpm.c
@@ -592,6 +592,45 @@ static int do_tpm_oiap(cmd_tbl_t *cmdtp, int flag,
 	return report_return_code(err);
 }
 
+#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
+static int do_tpm_load_key_by_sha1(cmd_tbl_t *cmdtp, int flag, int argc, char *
+				   const argv[])
+{
+	uint32_t parent_handle = 0;
+	uint32_t key_len, key_handle, err;
+	uint8_t usage_auth[DIGEST_LENGTH];
+	uint8_t parent_hash[DIGEST_LENGTH];
+	void *key;
+
+	if (argc < 5)
+		return CMD_RET_USAGE;
+
+	parse_byte_string(argv[1], parent_hash, NULL);
+	key = (void *)simple_strtoul(argv[2], NULL, 0);
+	key_len = simple_strtoul(argv[3], NULL, 0);
+	if (strlen(argv[4]) != 2 * DIGEST_LENGTH)
+		return CMD_RET_FAILURE;
+	parse_byte_string(argv[4], usage_auth, NULL);
+
+	err = tpm_find_key_sha1(usage_auth, parent_hash, &parent_handle);
+	if (err) {
+		printf("Could not find matching parent key (err = %d)\n", err);
+		return CMD_RET_FAILURE;
+	}
+
+	printf("Found parent key %08x\n", parent_handle);
+
+	err = tpm_load_key2_oiap(parent_handle, key, key_len, usage_auth,
+				 &key_handle);
+	if (!err) {
+		printf("Key handle is 0x%x\n", key_handle);
+		setenv_hex("key_handle", key_handle);
+	}
+
+	return report_return_code(err);
+}
+#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
+
 static int do_tpm_load_key2_oiap(cmd_tbl_t *cmdtp, int flag,
 		int argc, char * const argv[])
 {
@@ -652,31 +691,36 @@ static int do_tpm_flush(cmd_tbl_t *cmdtp, int flag, int argc,
 {
 	int type = 0;
 
-	if (argc != 2)
+	if (argc != 3)
 		return CMD_RET_USAGE;
 
-	if (strcasecmp(argv[1], "key"))
+	if (!strcasecmp(argv[1], "key"))
 		type = TPM_RT_KEY;
-	else if (strcasecmp(argv[1], "auth"))
+	else if (!strcasecmp(argv[1], "auth"))
 		type = TPM_RT_AUTH;
-	else if (strcasecmp(argv[1], "hash"))
+	else if (!strcasecmp(argv[1], "hash"))
 		type = TPM_RT_HASH;
-	else if (strcasecmp(argv[1], "trans"))
+	else if (!strcasecmp(argv[1], "trans"))
 		type = TPM_RT_TRANS;
-	else if (strcasecmp(argv[1], "context"))
+	else if (!strcasecmp(argv[1], "context"))
 		type = TPM_RT_CONTEXT;
-	else if (strcasecmp(argv[1], "counter"))
+	else if (!strcasecmp(argv[1], "counter"))
 		type = TPM_RT_COUNTER;
-	else if (strcasecmp(argv[1], "delegate"))
+	else if (!strcasecmp(argv[1], "delegate"))
 		type = TPM_RT_DELEGATE;
-	else if (strcasecmp(argv[1], "daa_tpm"))
+	else if (!strcasecmp(argv[1], "daa_tpm"))
 		type = TPM_RT_DAA_TPM;
-	else if (strcasecmp(argv[1], "daa_v0"))
+	else if (!strcasecmp(argv[1], "daa_v0"))
 		type = TPM_RT_DAA_V0;
-	else if (strcasecmp(argv[1], "daa_v1"))
+	else if (!strcasecmp(argv[1], "daa_v1"))
 		type = TPM_RT_DAA_V1;
 
-	if (strcasecmp(argv[2], "all")) {
+	if (!type) {
+		printf("Resource type %s unknown.\n", argv[1]);
+		return -1;
+	}
+
+	if (!strcasecmp(argv[2], "all")) {
 		uint16_t res_count;
 		uint8_t buf[288];
 		uint8_t *ptr;
@@ -686,8 +730,10 @@ static int do_tpm_flush(cmd_tbl_t *cmdtp, int flag, int argc,
 		/* fetch list of already loaded resources in the TPM */
 		err = tpm_get_capability(TPM_CAP_HANDLE, type, buf,
 					 sizeof(buf));
-		if (err)
+		if (err) {
+			printf("tpm_get_capability returned error %d.\n", err);
 			return -1;
+		}
 		res_count = get_unaligned_be16(buf);
 		ptr = buf + 2;
 		for (i = 0; i < res_count; ++i, ptr += 4)
@@ -695,8 +741,10 @@ static int do_tpm_flush(cmd_tbl_t *cmdtp, int flag, int argc,
 	} else {
 		uint32_t handle = simple_strtoul(argv[2], NULL, 0);
 
-		if (!handle)
+		if (!handle) {
+			printf("Illegal resource handle %s\n", argv[2]);
 			return -1;
+		}
 		tpm_flush_specific(cpu_to_be32(handle), type);
 	}
 
@@ -704,6 +752,68 @@ static int do_tpm_flush(cmd_tbl_t *cmdtp, int flag, int argc,
 }
 #endif /* CONFIG_TPM_FLUSH_RESOURCES */
 
+#ifdef CONFIG_TPM_LIST_RESOURCES
+static int do_tpm_list(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	int type = 0;
+	uint16_t res_count;
+	uint8_t buf[288];
+	uint8_t *ptr;
+	int err;
+	uint i;
+
+	if (argc != 2)
+		return CMD_RET_USAGE;
+
+	if (!strcasecmp(argv[1], "key"))
+		type = TPM_RT_KEY;
+	else if (!strcasecmp(argv[1], "auth"))
+		type = TPM_RT_AUTH;
+	else if (!strcasecmp(argv[1], "hash"))
+		type = TPM_RT_HASH;
+	else if (!strcasecmp(argv[1], "trans"))
+		type = TPM_RT_TRANS;
+	else if (!strcasecmp(argv[1], "context"))
+		type = TPM_RT_CONTEXT;
+	else if (!strcasecmp(argv[1], "counter"))
+		type = TPM_RT_COUNTER;
+	else if (!strcasecmp(argv[1], "delegate"))
+		type = TPM_RT_DELEGATE;
+	else if (!strcasecmp(argv[1], "daa_tpm"))
+		type = TPM_RT_DAA_TPM;
+	else if (!strcasecmp(argv[1], "daa_v0"))
+		type = TPM_RT_DAA_V0;
+	else if (!strcasecmp(argv[1], "daa_v1"))
+		type = TPM_RT_DAA_V1;
+
+	if (!type) {
+		printf("Resource type %s unknown.\n", argv[1]);
+		return -1;
+	}
+
+	/* fetch list of already loaded resources in the TPM */
+	err = tpm_get_capability(TPM_CAP_HANDLE, type, buf,
+				 sizeof(buf));
+	if (err) {
+		printf("tpm_get_capability returned error %d.\n", err);
+		return -1;
+	}
+	res_count = get_unaligned_be16(buf);
+	ptr = buf + 2;
+
+	printf("Resources of type %s (%02x):\n", argv[1], type);
+	if (!res_count) {
+		puts("None\n");
+	} else {
+		for (i = 0; i < res_count; ++i, ptr += 4)
+			printf("Index %d: %08x\n", i, get_unaligned_be32(ptr));
+	}
+
+	return 0;
+}
+#endif /* CONFIG_TPM_LIST_RESOURCES */
+
 #define MAKE_TPM_CMD_ENTRY(cmd) \
 	U_BOOT_CMD_MKENT(cmd, 0, 1, do_tpm_ ## cmd, "", "")
 
@@ -756,6 +866,10 @@ static cmd_tbl_t tpm_commands[] = {
 			 do_tpm_end_oiap, "", ""),
 	U_BOOT_CMD_MKENT(load_key2_oiap, 0, 1,
 			 do_tpm_load_key2_oiap, "", ""),
+#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
+	U_BOOT_CMD_MKENT(load_key_by_sha1, 0, 1,
+			 do_tpm_load_key_by_sha1, "", ""),
+#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
 	U_BOOT_CMD_MKENT(get_pub_key_oiap, 0, 1,
 			 do_tpm_get_pub_key_oiap, "", ""),
 #endif /* CONFIG_TPM_AUTH_SESSIONS */
@@ -763,6 +877,10 @@ static cmd_tbl_t tpm_commands[] = {
 	U_BOOT_CMD_MKENT(flush, 0, 1,
 			 do_tpm_flush, "", ""),
 #endif /* CONFIG_TPM_FLUSH_RESOURCES */
+#ifdef CONFIG_TPM_LIST_RESOURCES
+	U_BOOT_CMD_MKENT(list, 0, 1,
+			 do_tpm_list, "", ""),
+#endif /* CONFIG_TPM_LIST_RESOURCES */
 };
 
 static int do_tpm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -812,20 +930,34 @@ U_BOOT_CMD(tpm, CONFIG_SYS_MAXARGS, 1, do_tpm,
 "  get_capability cap_area sub_cap addr count\n"
 "    - Read <count> bytes of TPM capability indexed by <cap_area> and\n"
 "      <sub_cap> to memory address <addr>.\n"
-#ifdef CONFIG_TPM_FLUSH_RESOURCES
+#if defined(CONFIG_TPM_FLUSH_RESOURCES) || defined(CONFIG_TPM_LIST_RESOURCES)
 "Resource management functions\n"
+#endif
+#ifdef CONFIG_TPM_FLUSH_RESOURCES
 "  flush resource_type id\n"
 "    - flushes a resource of type <resource_type> (may be one of key, auth,\n"
 "      hash, trans, context, counter, delegate, daa_tpm, daa_v0, daa_v1),\n"
 "      and id <id> from the TPM. Use an <id> of \"all\" to flush all\n"
 "      resources of that type.\n"
 #endif /* CONFIG_TPM_FLUSH_RESOURCES */
+#ifdef CONFIG_TPM_LIST_RESOURCES
+"  list resource_type\n"
+"    - lists resources of type <resource_type> (may be one of key, auth,\n"
+"      hash, trans, context, counter, delegate, daa_tpm, daa_v0, daa_v1),\n"
+"      contained in the TPM.\n"
+#endif /* CONFIG_TPM_LIST_RESOURCES */
 #ifdef CONFIG_TPM_AUTH_SESSIONS
 "Storage functions\n"
 "  loadkey2_oiap parent_handle key_addr key_len usage_auth\n"
 "    - loads a key data from memory address <key_addr>, <key_len> bytes\n"
 "      into TPM using the parent key <parent_handle> with authorization\n"
 "      <usage_auth> (20 bytes hex string).\n"
+#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
+"  load_key_by_sha1 parent_hash key_addr key_len usage_auth\n"
+"    - loads a key data from memory address <key_addr>, <key_len> bytes\n"
+"      into TPM using the parent hash <parent_hash> (20 bytes hex string)\n"
+"      with authorization <usage_auth> (20 bytes hex string).\n"
+#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
 "  get_pub_key_oiap key_handle usage_auth\n"
 "    - get the public key portion of a loaded key <key_handle> using\n"
 "      authorization <usage auth> (20 bytes hex string)\n"
diff --git a/common/Kconfig b/common/Kconfig
index 8f73c8f..1879aef 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -90,7 +90,7 @@ config BOOTSTAGE_STASH_ADDR
 
 config BOOTSTAGE_STASH_SIZE
 	hex "Size of boot timing stash region"
-	default 4096
+	default 0x1000
 	help
 	  This should be large enough to hold the bootstage stash. A value of
 	  4096 (4KiB) is normally plenty.
@@ -158,6 +158,75 @@ config SPI_BOOT
 
 endmenu
 
+menu "Environment"
+
+if ARCH_SUNXI
+
+choice
+	prompt "Environment Device"
+	default ENV_IS_IN_MMC if ARCH_SUNXI
+
+config ENV_IS_IN_MMC
+	bool "Environment in an MMC device"
+	depends on CMD_MMC
+	help
+	  Define this if you have an MMC device which you want to use for the
+	  environment.
+
+config ENV_IS_IN_NAND
+	bool "Environment in a NAND device"
+	depends on CMD_NAND
+	help
+	  Define this if you have a NAND device which you want to use for the
+	  environment.
+
+config ENV_IS_IN_UBI
+	bool "Environment in a UBI volume"
+	depends on CMD_UBI
+	depends on CMD_MTDPARTS
+	help
+	  Define this if you have a UBI volume which you want to use for the
+	  environment.
+
+config ENV_IS_NOWHERE
+	bool "Environment is not stored"
+	help
+	  Define this if you don't want to or can't have an environment stored
+	  on a storage medium
+
+endchoice
+
+config ENV_OFFSET
+	hex "Environment Offset"
+	depends on !ENV_IS_IN_UBI
+	depends on !ENV_IS_NOWHERE
+	default 0x88000 if ARCH_SUNXI
+	help
+	  Offset from the start of the device (or partition)
+
+config ENV_SIZE
+	hex "Environment Size"
+	depends on !ENV_IS_NOWHERE
+	default 0x20000 if ARCH_SUNXI
+	help
+	  Size of the environment storage area
+
+config ENV_UBI_PART
+	string "UBI partition name"
+	depends on ENV_IS_IN_UBI
+	help
+	  MTD partition containing the UBI device
+
+config ENV_UBI_VOLUME
+	string "UBI volume name"
+	depends on ENV_IS_IN_UBI
+	help
+	  Name of the volume that you want to store the environment in.
+
+endif
+
+endmenu
+
 config BOOTDELAY
 	int "delay in seconds before automatically booting"
 	default 2
@@ -379,7 +448,7 @@ config BOARD_LATE_INIT
 
 config DISPLAY_CPUINFO
 	bool "Display information about the CPU during start up"
-	default y if ARM || BLACKFIN || NIOS2 || X86 || XTENSA || MPC5xxx
+	default y if ARM || NIOS2 || X86 || XTENSA || MPC5xxx
 	help
 	  Display information about the CPU that U-Boot is running on
 	  when U-Boot starts up. The function print_cpuinfo() is called
@@ -387,7 +456,7 @@ config DISPLAY_CPUINFO
 
 config DISPLAY_BOARDINFO
 	bool "Display information about the board during start up"
-	default y if ARM || M68K || MIPS || PPC || SPARC || XTENSA
+	default y if ARM || M68K || MIPS || PPC || XTENSA
 	help
 	  Display information about the board that U-Boot is running on
 	  when U-Boot starts up. The board function checkboard() is called
diff --git a/common/board_f.c b/common/board_f.c
index 7d1ede0..d9431ee 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -11,58 +11,33 @@
  */
 
 #include <common.h>
-#include <linux/compiler.h>
-#include <version.h>
 #include <console.h>
 #include <environment.h>
 #include <dm.h>
 #include <fdtdec.h>
 #include <fs.h>
-#if defined(CONFIG_CMD_IDE)
-#include <ide.h>
-#endif
 #include <i2c.h>
 #include <initcall.h>
+#include <init_helpers.h>
 #include <logbuff.h>
 #include <malloc.h>
 #include <mapmem.h>
-
-/* TODO: Can we move these into arch/ headers? */
-#ifdef CONFIG_8xx
-#include <mpc8xx.h>
-#endif
-#ifdef CONFIG_5xx
-#include <mpc5xx.h>
-#endif
-#ifdef CONFIG_MPC5xxx
-#include <mpc5xxx.h>
-#endif
-#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
-#include <asm/mp.h>
-#endif
-
 #include <os.h>
 #include <post.h>
+#include <relocate.h>
 #include <spi.h>
 #include <status_led.h>
 #include <timer.h>
 #include <trace.h>
 #include <video.h>
 #include <watchdog.h>
-#include <linux/errno.h>
+#if defined(CONFIG_MP) && defined(CONFIG_PPC)
+#include <asm/mp.h>
+#endif
 #include <asm/io.h>
 #include <asm/sections.h>
-#if defined(CONFIG_X86) || defined(CONFIG_ARC)
-#include <asm/init_helpers.h>
-#endif
-#if defined(CONFIG_X86) || defined(CONFIG_ARC) || defined(CONFIG_XTENSA)
-#include <asm/relocate.h>
-#endif
-#ifdef CONFIG_SANDBOX
-#include <asm/state.h>
-#endif
 #include <dm/root.h>
-#include <linux/compiler.h>
+#include <linux/errno.h>
 
 /*
  * Pointer to initial global data area
@@ -109,15 +84,11 @@ __weak void blue_led_off(void) {}
  * a structure...
  */
 
-/*
- * Could the CONFIG_SPL_BUILD infection become a flag in gd?
- */
-
 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
 static int init_func_watchdog_init(void)
 {
-# if defined(CONFIG_HW_WATCHDOG) && (defined(CONFIG_BLACKFIN) || \
-	defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
+# if defined(CONFIG_HW_WATCHDOG) && \
+	(defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
 	defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \
 	defined(CONFIG_DESIGNWARE_WATCHDOG) || \
 	defined(CONFIG_IMX_WATCHDOG))
@@ -166,11 +137,6 @@ static int display_text_info(void)
 		text_base, bss_start, bss_end);
 #endif
 
-#ifdef CONFIG_USE_IRQ
-	debug("IRQ Stack: %08lx\n", IRQ_STACK_START);
-	debug("FIQ Stack: %08lx\n", FIQ_STACK_START);
-#endif
-
 	return 0;
 }
 
@@ -180,25 +146,6 @@ static int announce_dram_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
-static int init_func_ram(void)
-{
-#ifdef	CONFIG_BOARD_TYPES
-	int board_type = gd->board_type;
-#else
-	int board_type = 0;	/* use dummy arg */
-#endif
-
-	gd->ram_size = initdram(board_type);
-
-	if (gd->ram_size > 0)
-		return 0;
-
-	puts("*** failed ***\n");
-	return 1;
-}
-#endif
-
 static int show_dram_config(void)
 {
 	unsigned long long size;
@@ -227,12 +174,14 @@ static int show_dram_config(void)
 	return 0;
 }
 
-__weak void dram_init_banksize(void)
+__weak int dram_init_banksize(void)
 {
 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = get_effective_memsize();
 #endif
+
+	return 0;
 }
 
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
@@ -273,8 +222,7 @@ static int setup_mon_len(void)
 	gd->mon_len = (ulong)&__bss_end - (ulong)_start;
 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
 	gd->mon_len = (ulong)&_end - (ulong)_init;
-#elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) || \
-	defined(CONFIG_XTENSA)
+#elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
 	gd->mon_len = CONFIG_SYS_MONITOR_LEN;
 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH)
 	gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
@@ -295,18 +243,6 @@ __weak int mach_cpu_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_SANDBOX
-static int setup_ram_buf(void)
-{
-	struct sandbox_state *state = state_get_current();
-
-	gd->arch.ram_buf = state->ram_buf;
-	gd->ram_size = state->ram_size;
-
-	return 0;
-}
-#endif
-
 /* Get the top of usable RAM */
 __weak ulong board_get_usable_ram_top(ulong total_size)
 {
@@ -365,27 +301,16 @@ static int setup_dest_addr(void)
 	return 0;
 }
 
-#if defined(CONFIG_SPARC)
-static int reserve_prom(void)
-{
-	/* defined in arch/sparc/cpu/leon?/prom.c */
-	extern void *__prom_start_reloc;
-	int size = 8192; /* page table = 2k, prom = 6k */
-	gd->relocaddr -= size;
-	__prom_start_reloc = map_sysmem(gd->relocaddr + 2048, size - 2048);
-	debug("Reserving %dk for PROM and page table at %08lx\n", size,
-		gd->relocaddr);
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
+#if defined(CONFIG_LOGBUFFER)
 static int reserve_logbuffer(void)
 {
+#ifndef CONFIG_ALT_LB_ADDR
 	/* reserve kernel log buffer */
 	gd->relocaddr -= LOGBUFF_RESERVE;
 	debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
 		gd->relocaddr);
+#endif
+
 	return 0;
 }
 #endif
@@ -411,10 +336,10 @@ static int reserve_round_4k(void)
 	return 0;
 }
 
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
-		defined(CONFIG_ARM)
+#ifdef CONFIG_ARM
 static int reserve_mmu(void)
 {
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 	/* reserve TLB table */
 	gd->arch.tlb_size = PGTABLE_SIZE;
 	gd->relocaddr -= gd->arch.tlb_size;
@@ -433,14 +358,15 @@ static int reserve_mmu(void)
 	 */
 	gd->arch.tlb_allocated = gd->arch.tlb_addr;
 #endif
+#endif
 
 	return 0;
 }
 #endif
 
-#ifdef CONFIG_DM_VIDEO
 static int reserve_video(void)
 {
+#ifdef CONFIG_DM_VIDEO
 	ulong addr;
 	int ret;
 
@@ -449,14 +375,7 @@ static int reserve_video(void)
 	if (ret)
 		return ret;
 	gd->relocaddr = addr;
-
-	return 0;
-}
-#else
-
-# ifdef CONFIG_LCD
-static int reserve_lcd(void)
-{
+#elif defined(CONFIG_LCD)
 #  ifdef CONFIG_FB_ADDR
 	gd->fb_base = CONFIG_FB_ADDR;
 #  else
@@ -464,24 +383,17 @@ static int reserve_lcd(void)
 	gd->relocaddr = lcd_setmem(gd->relocaddr);
 	gd->fb_base = gd->relocaddr;
 #  endif /* CONFIG_FB_ADDR */
-
-	return 0;
-}
-# endif /* CONFIG_LCD */
-
-# if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \
+#elif defined(CONFIG_VIDEO) && \
+		(!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \
 		!defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
-		!defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K)
-static int reserve_legacy_video(void)
-{
+		!defined(CONFIG_M68K)
 	/* reserve memory for video display (always full pages) */
 	gd->relocaddr = video_setmem(gd->relocaddr);
 	gd->fb_base = gd->relocaddr;
+#endif
 
 	return 0;
 }
-# endif
-#endif /* !CONFIG_DM_VIDEO */
 
 static int reserve_trace(void)
 {
@@ -516,7 +428,6 @@ static int reserve_uboot(void)
 	return 0;
 }
 
-#ifndef CONFIG_SPL_BUILD
 /* reserve memory for malloc() area */
 static int reserve_malloc(void)
 {
@@ -538,7 +449,6 @@ static int reserve_board(void)
 	}
 	return 0;
 }
-#endif
 
 static int setup_machine(void)
 {
@@ -668,30 +578,6 @@ static int setup_board_part2(void)
 }
 #endif
 
-#ifdef CONFIG_SYS_EXTBDINFO
-static int setup_board_extra(void)
-{
-	bd_t *bd = gd->bd;
-
-	strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
-	strncpy((char *) bd->bi_r_version, U_BOOT_VERSION,
-		sizeof(bd->bi_r_version));
-
-	bd->bi_procfreq = gd->cpu_clk;	/* Processor Speed, In Hz */
-	bd->bi_plb_busfreq = gd->bus_clk;
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
-		defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-		defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-	bd->bi_pci_busfreq = get_PCI_freq();
-	bd->bi_opbfreq = get_OPB_freq();
-#elif defined(CONFIG_XILINX_405)
-	bd->bi_pci_busfreq = get_PCI_freq();
-#endif
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_POST
 static int init_post(void)
 {
@@ -702,14 +588,6 @@ static int init_post(void)
 }
 #endif
 
-static int setup_dram_config(void)
-{
-	/* Ram is board specific, so move it to board code ... */
-	dram_init_banksize();
-
-	return 0;
-}
-
 static int reloc_fdt(void)
 {
 #ifndef CONFIG_OF_EMBED
@@ -751,6 +629,13 @@ static int setup_reloc(void)
 	return 0;
 }
 
+#ifdef CONFIG_OF_BOARD_FIXUP
+static int fix_fdt(void)
+{
+	return board_fix_fdt((void *)gd->fdt_blob);
+}
+#endif
+
 /* ARM calls relocate_code from its crt0.S */
 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
 		!CONFIG_IS_ENABLED(X86_64)
@@ -831,9 +716,6 @@ __weak int arch_cpu_init_dm(void)
 }
 
 static const init_fnc_t init_sequence_f[] = {
-#ifdef CONFIG_SANDBOX
-	setup_ram_buf,
-#endif
 	setup_mon_len,
 #ifdef CONFIG_OF_CONTROL
 	fdtdec_setup,
@@ -843,8 +725,8 @@ static const init_fnc_t init_sequence_f[] = {
 #endif
 	initf_malloc,
 	initf_console_record,
-#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
-	x86_fsp_init,
+#if defined(CONFIG_HAVE_FSP)
+	arch_fsp_init,
 #endif
 	arch_cpu_init,		/* basic arch cpu dependent setup */
 	mach_cpu_init,		/* SoC/machine dependent CPU setup */
@@ -854,51 +736,22 @@ static const init_fnc_t init_sequence_f[] = {
 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 	board_early_init_f,
 #endif
-	/* TODO: can any of this go into arch_cpu_init()? */
-#if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT)
+#if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
+	/* get CPU and bus clocks according to the environment variable */
 	get_clocks,		/* get CPU and bus clocks (etc.) */
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
-		&& !defined(CONFIG_TQM885D)
-	adjust_sdram_tbs_8xx,
-#endif
-	/* TODO: can we rename this to timer_init()? */
-	init_timebase,
 #endif
-#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \
-		defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \
-		defined(CONFIG_SH) || defined(CONFIG_SPARC)
 	timer_init,		/* initialize timer */
-#endif
 #if defined(CONFIG_BOARD_POSTCLK_INIT)
 	board_postclk_init,
 #endif
-#if defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
-	get_clocks,
-#endif
 	env_init,		/* initialize environment */
-#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
-	/* get CPU and bus clocks according to the environment variable */
-	get_clocks_866,
-	/* adjust sdram refresh rate according to the new clock */
-	sdram_adjust_866,
-	init_timebase,
-#endif
 	init_baud_rate,		/* initialze baudrate settings */
 	serial_init,		/* serial communications setup */
 	console_init_f,		/* stage 1 init of console */
-#ifdef CONFIG_SANDBOX
-	sandbox_early_getopt_check,
-#endif
 	display_options,	/* say that we are here */
 	display_text_info,	/* show debugging info if required */
-#if defined(CONFIG_MPC8260)
-	prt_8260_rsr,
-	prt_8260_clks,
-#endif /* CONFIG_MPC8260 */
-#if defined(CONFIG_MPC83xx)
-	prt_83xx_rsr,
-#endif
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH)
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \
+		defined(CONFIG_X86)
 	checkcpu,
 #endif
 #if defined(CONFIG_DISPLAY_CPUINFO)
@@ -919,15 +772,7 @@ static const init_fnc_t init_sequence_f[] = {
 	init_func_spi,
 #endif
 	announce_dram_init,
-	/* TODO: unify all these dram functions? */
-#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_NDS32) || \
-		defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) || \
-		defined(CONFIG_SH)
 	dram_init,		/* configure available RAM banks */
-#endif
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
-	init_func_ram,
-#endif
 #ifdef CONFIG_POST
 	post_init_f,
 #endif
@@ -954,51 +799,27 @@ static const init_fnc_t init_sequence_f[] = {
 	 *  - board info struct
 	 */
 	setup_dest_addr,
-#if defined(CONFIG_BLACKFIN) || defined(CONFIG_XTENSA)
-	/* Blackfin u-boot monitor should be on top of the ram */
-	reserve_uboot,
-#endif
-#if defined(CONFIG_SPARC)
-	reserve_prom,
-#endif
-#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
+#if defined(CONFIG_LOGBUFFER)
 	reserve_logbuffer,
 #endif
 #ifdef CONFIG_PRAM
 	reserve_pram,
 #endif
 	reserve_round_4k,
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
-		defined(CONFIG_ARM)
+#ifdef CONFIG_ARM
 	reserve_mmu,
 #endif
-#ifdef CONFIG_DM_VIDEO
 	reserve_video,
-#else
-# ifdef CONFIG_LCD
-	reserve_lcd,
-# endif
-	/* TODO: Why the dependency on CONFIG_8xx? */
-# if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \
-		!defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
-		!defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K)
-	reserve_legacy_video,
-# endif
-#endif /* CONFIG_DM_VIDEO */
 	reserve_trace,
-#if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_XTENSA)
 	reserve_uboot,
-#endif
-#ifndef CONFIG_SPL_BUILD
 	reserve_malloc,
 	reserve_board,
-#endif
 	setup_machine,
 	reserve_global_data,
 	reserve_fdt,
 	reserve_arch,
 	reserve_stacks,
-	setup_dram_config,
+	dram_init_banksize,
 	show_dram_config,
 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
 	defined(CONFIG_SH)
@@ -1012,6 +833,9 @@ static const init_fnc_t init_sequence_f[] = {
 #ifdef CONFIG_SYS_EXTBDINFO
 	setup_board_extra,
 #endif
+#ifdef CONFIG_OF_BOARD_FIXUP
+	fix_fdt,
+#endif
 	INIT_FUNC_WATCHDOG_RESET
 	reloc_fdt,
 	setup_reloc,
diff --git a/common/board_r.c b/common/board_r.c
index 5c9e698..d69a33c 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -27,6 +27,7 @@
 #include <ide.h>
 #endif
 #include <initcall.h>
+#include <init_helpers.h>
 #ifdef CONFIG_PS2KBD
 #include <keyboard.h>
 #endif
@@ -49,16 +50,10 @@
 #include <timer.h>
 #include <trace.h>
 #include <watchdog.h>
-#ifdef CONFIG_CMD_AMBAPP
-#include <ambapp.h>
-#endif
 #ifdef CONFIG_ADDR_MAP
 #include <asm/mmu.h>
 #endif
 #include <asm/sections.h>
-#ifdef CONFIG_X86
-#include <asm/init_helpers.h>
-#endif
 #include <dm/root.h>
 #include <linux/compiler.h>
 #include <linux/err.h>
@@ -69,10 +64,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_SPARC)
-extern int prom_init(void);
-#endif
-
 ulong monitor_flash_len;
 
 __weak int board_flash_wp_on(void)
@@ -426,6 +417,7 @@ static int initr_nand(void)
 {
 	puts("NAND:  ");
 	nand_init();
+	printf("%lu MiB\n", nand_size() / 1024);
 	return 0;
 }
 #endif
@@ -597,18 +589,6 @@ static int initr_status_led(void)
 }
 #endif
 
-#if defined(CONFIG_CMD_AMBAPP) && defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP)
-extern int do_ambapp_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-static int initr_ambapp_print(void)
-{
-	puts("AMBA:\n");
-	do_ambapp_print(NULL, 0, 0, NULL);
-
-	return 0;
-}
-#endif
-
 #if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
 static int initr_scsi(void)
 {
@@ -822,8 +802,7 @@ static init_fnc_t init_sequence_r[] = {
 	initr_flash,
 #endif
 	INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86) || \
-	defined(CONFIG_SPARC)
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86)
 	/* initialize higher level parts of CPU like time base and timers */
 	cpu_init_r,
 #endif
@@ -894,12 +873,6 @@ static init_fnc_t init_sequence_r[] = {
 #ifdef CONFIG_BOARD_LATE_INIT
 	board_late_init,
 #endif
-#if defined(CONFIG_CMD_AMBAPP)
-	ambapp_init_reloc,
-#if defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP)
-	initr_ambapp_print,
-#endif
-#endif
 #if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
 	INIT_FUNC_WATCHDOG_RESET
 	initr_scsi,
@@ -939,9 +912,6 @@ static init_fnc_t init_sequence_r[] = {
 #ifdef CONFIG_PS2KBD
 	initr_kbd,
 #endif
-#if defined(CONFIG_SPARC)
-	prom_init,
-#endif
 	run_main_loop,
 };
 
diff --git a/common/env_common.c b/common/env_common.c
index 7fb62e8..6845f8d 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -140,7 +140,7 @@ int set_default_vars(int nvars, char * const vars[])
 }
 
 #ifdef CONFIG_ENV_AES
-#include <aes.h>
+#include <uboot_aes.h>
 /**
  * env_aes_cbc_get_key() - Get AES-128-CBC key for the environment
  *
diff --git a/common/env_flags.c b/common/env_flags.c
index 921d377..3c50620 100644
--- a/common/env_flags.c
+++ b/common/env_flags.c
@@ -11,6 +11,7 @@
 #ifdef USE_HOSTCC /* Eliminate "ANSI does not permit..." warnings */
 #include <stdint.h>
 #include <stdio.h>
+#include "fw_env_private.h"
 #include "fw_env.h"
 #include <env_attr.h>
 #include <env_flags.h>
diff --git a/common/env_mmc.c b/common/env_mmc.c
index 16f6a17..a5d14d4 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -82,10 +82,6 @@ static int mmc_set_env_part(struct mmc *mmc)
 	int dev = mmc_get_env_dev();
 	int ret = 0;
 
-#ifdef CONFIG_SPL_BUILD
-	dev = 0;
-#endif
-
 	env_mmc_orig_hwpart = mmc_get_blk_desc(mmc)->hwpart;
 	ret = blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part);
 	if (ret)
@@ -116,9 +112,6 @@ static void fini_mmc_for_env(struct mmc *mmc)
 #ifdef CONFIG_SYS_MMC_ENV_PART
 	int dev = mmc_get_env_dev();
 
-#ifdef CONFIG_SPL_BUILD
-	dev = 0;
-#endif
 	blk_select_hwpart_devnum(IF_TYPE_MMC, dev, env_mmc_orig_hwpart);
 #endif
 }
@@ -223,10 +216,6 @@ void env_relocate_spec(void)
 	ALLOC_CACHE_ALIGN_BUFFER(env_t, tmp_env1, 1);
 	ALLOC_CACHE_ALIGN_BUFFER(env_t, tmp_env2, 1);
 
-#ifdef CONFIG_SPL_BUILD
-	dev = 0;
-#endif
-
 	mmc = find_mmc_device(dev);
 
 	errmsg = init_mmc_for_env(mmc);
@@ -306,10 +295,6 @@ void env_relocate_spec(void)
 	int dev = mmc_get_env_dev();
 	const char *errmsg;
 
-#ifdef CONFIG_SPL_BUILD
-	dev = 0;
-#endif
-
 	mmc = find_mmc_device(dev);
 
 	errmsg = init_mmc_for_env(mmc);
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 55d4d6f..c6a76b7 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -482,7 +482,6 @@ void fdt_fixup_ethernet(void *fdt)
 	/* Cycle through all aliases */
 	for (prop = 0; ; prop++) {
 		const char *name;
-		int len = strlen("ethernet");
 
 		/* FDT might have been edited, recompute the offset */
 		offset = fdt_first_property_offset(fdt,
@@ -495,8 +494,13 @@ void fdt_fixup_ethernet(void *fdt)
 			break;
 
 		path = fdt_getprop_by_offset(fdt, offset, &name, NULL);
-		if (!strncmp(name, "ethernet", len)) {
-			i = trailing_strtol(name);
+		if (!strncmp(name, "ethernet", 8)) {
+			/* Treat plain "ethernet" same as "ethernet0". */
+			if (!strcmp(name, "ethernet"))
+				i = 0;
+			else
+				i = trailing_strtol(name);
+
 			if (i != -1) {
 				if (i == 0)
 					strcpy(mac, "ethaddr");
diff --git a/common/image-fdt.c b/common/image-fdt.c
index e7540be..7468b90 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -494,7 +494,6 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,
 			goto err;
 		}
 	}
-	fdt_fixup_ethernet(blob);
 
 	/* Delete the old LMB reservation */
 	if (lmb)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 6752b5c..ea6fbb6 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -371,7 +371,7 @@ config SPL_LIBGENERIC_SUPPORT
 
 config SPL_MMC_SUPPORT
 	bool "Support MMC"
-	depends on SPL
+	depends on SPL && GENERIC_MMC
 	help
 	  Enable support for MMC (Multimedia Card) within SPL. This enables
 	  the MMC protocol implementation and allows any enabled drivers to
diff --git a/common/spl/spl.c b/common/spl/spl.c
index d98b9fc..a3e73b8 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -85,6 +85,9 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image)
 {
 	spl_image->size = CONFIG_SYS_MONITOR_LEN;
 	spl_image->entry_point = CONFIG_SYS_UBOOT_START;
+#ifdef CONFIG_CPU_V7M
+	spl_image->entry_point |= 0x1;
+#endif
 	spl_image->load_addr = CONFIG_SYS_TEXT_BASE;
 	spl_image->os = IH_OS_U_BOOT;
 	spl_image->name = "U-Boot";
@@ -227,10 +230,11 @@ int spl_early_init(void)
 int spl_init(void)
 {
 	int ret;
+	bool setup_malloc = !(IS_ENABLED(CONFIG_SPL_STACK_R) &&
+			IS_ENABLED(CONFIG_SPL_SYS_MALLOC_SIMPLE));
 
 	if (!(gd->flags & GD_FLG_SPL_EARLY_INIT)) {
-		ret = spl_common_init(
-			!IS_ENABLED(CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN));
+		ret = spl_common_init(setup_malloc);
 		if (ret)
 			return ret;
 	}
diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c
index 0fba017..85fe508 100644
--- a/common/spl/spl_net.c
+++ b/common/spl/spl_net.c
@@ -11,19 +11,29 @@
 #include <errno.h>
 #include <spl.h>
 #include <net.h>
+#include <libfdt.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)
+static ulong spl_net_load_read(struct spl_load_info *load, ulong sector,
+			       ulong count, void *buf)
+{
+	debug("%s: sector %lx, count %lx, buf %lx\n",
+	      __func__, sector, count, (ulong)buf);
+	memcpy(buf, (void *)(load_addr + sector), count);
+	return count;
+}
+
 static int spl_net_load_image(struct spl_image_info *spl_image,
 			      struct spl_boot_device *bootdev)
 {
+	struct image_header *header = (struct image_header *)load_addr;
 	int rv;
 
 	env_init();
 	env_relocate();
 	setenv("autoload", "yes");
-	load_addr = CONFIG_SYS_TEXT_BASE - sizeof(struct image_header);
 	rv = eth_initialize();
 	if (rv == 0) {
 		printf("No Ethernet devices found\n");
@@ -36,8 +46,26 @@ static int spl_net_load_image(struct spl_image_info *spl_image,
 		printf("Problem booting with BOOTP\n");
 		return rv;
 	}
-	return spl_parse_image_header(spl_image,
-				      (struct image_header *)load_addr);
+
+	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	    image_get_magic(header) == FDT_MAGIC) {
+		struct spl_load_info load;
+
+		debug("Found FIT\n");
+		load.bl_len = 1;
+		load.read = spl_net_load_read;
+		rv = spl_load_simple_fit(spl_image, &load, 0, header);
+	} else {
+		debug("Legacy image\n");
+
+		rv = spl_parse_image_header(spl_image, header);
+		if (rv)
+			return rv;
+
+		memcpy((void *)spl_image->load_addr, header, spl_image->size);
+	}
+
+	return rv;
 }
 #endif
 
diff --git a/common/xyzModem.c b/common/xyzModem.c
index e0d87db..a0c5dfe 100644
--- a/common/xyzModem.c
+++ b/common/xyzModem.c
@@ -39,25 +39,17 @@
 #define CAN 0x18
 #define EOF 0x1A		/* ^Z for DOS officionados */
 
-#define USE_YMODEM_LENGTH
-
 /* Data & state local to the protocol */
 static struct
 {
-#ifdef REDBOOT
-  hal_virtual_comm_table_t *__chan;
-#else
   int *__chan;
-#endif
   unsigned char pkt[1024], *bufp;
   unsigned char blk, cblk, crc1, crc2;
   unsigned char next_blk;	/* Expected block */
   int len, mode, total_retries;
   int total_SOH, total_STX, total_CAN;
   bool crc_mode, at_eof, tx_ack;
-#ifdef USE_YMODEM_LENGTH
   unsigned long file_length, read_length;
-#endif
 } xyz;
 
 #define xyzModem_CHAR_TIMEOUT            2000	/* 2 seconds */
@@ -66,7 +58,6 @@ static struct
 #define xyzModem_CAN_COUNT                3	/* Wait for 3 CAN before quitting */
 
 
-#ifndef REDBOOT			/*SB */
 typedef int cyg_int32;
 static int
 CYGACC_COMM_IF_GETC_TIMEOUT (char chan, char *c)
@@ -156,17 +147,7 @@ parse_num (char *s, unsigned long *val, char **es, char *delim)
       if (_is_hex (c) && ((digit = _from_hex (c)) < radix))
 	{
 	  /* Valid digit */
-#ifdef CYGPKG_HAL_MIPS
-	  /* FIXME: tx49 compiler generates 0x2539018 for MUL which */
-	  /* isn't any good. */
-	  if (16 == radix)
-	    result = result << 4;
-	  else
-	    result = 10 * result;
-	  result += digit;
-#else
 	  result = (result * radix) + digit;
-#endif
 	}
       else
 	{
@@ -190,54 +171,15 @@ parse_num (char *s, unsigned long *val, char **es, char *delim)
   return true;
 }
 
-#endif
 
-#define USE_SPRINTF
 #ifdef DEBUG
-#ifndef USE_SPRINTF
-/*
- * Note: this debug setup only works if the target platform has two serial ports
- * available so that the other one (currently only port 1) can be used for debug
- * messages.
- */
-static int
-zm_dprintf (char *fmt, ...)
-{
-  int cur_console;
-  va_list args;
-
-  va_start (args, fmt);
-#ifdef REDBOOT
-  cur_console =
-    CYGACC_CALL_IF_SET_CONSOLE_COMM
-    (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
-  CYGACC_CALL_IF_SET_CONSOLE_COMM (1);
-#endif
-  diag_vprintf (fmt, args);
-#ifdef REDBOOT
-  CYGACC_CALL_IF_SET_CONSOLE_COMM (cur_console);
-#endif
-}
-
-static void
-zm_flush (void)
-{
-}
-
-#else
 /*
  * Note: this debug setup works by storing the strings in a fixed buffer
  */
-#define FINAL
-#ifdef FINAL
-static char *zm_out = (char *) 0x00380000;
-static char *zm_out_start = (char *) 0x00380000;
-#else
-static char zm_buf[8192];
-static char *zm_out = zm_buf;
-static char *zm_out_start = zm_buf;
+static char zm_debug_buf[8192];
+static char *zm_out = zm_debug_buf;
+static char *zm_out_start = zm_debug_buf;
 
-#endif
 static int
 zm_dprintf (char *fmt, ...)
 {
@@ -253,23 +195,13 @@ zm_dprintf (char *fmt, ...)
 static void
 zm_flush (void)
 {
-#ifdef REDBOOT
-  char *p = zm_out_start;
-  while (*p)
-    mon_write_char (*p++);
-#endif
   zm_out = zm_out_start;
 }
-#endif
 
 static void
 zm_dump_buf (void *buf, int len)
 {
-#ifdef REDBOOT
-  diag_vdump_buf_with_offset (zm_dprintf, buf, len, 0);
-#else
 
-#endif
 }
 
 static unsigned char zm_buf[2048];
@@ -476,9 +408,6 @@ xyzModem_get_hdr (void)
 int
 xyzModem_stream_open (connection_info_t * info, int *err)
 {
-#ifdef REDBOOT
-  int console_chan;
-#endif
   int stat = 0;
   int retries = xyzModem_MAX_RETRIES;
   int crc_retries = xyzModem_MAX_RETRIES_WITH_CRC;
@@ -492,29 +421,9 @@ xyzModem_stream_open (connection_info_t * info, int *err)
     }
 #endif
 
-#ifdef REDBOOT
-  /* Set up the I/O channel.  Note: this allows for using a different port in the future */
-  console_chan =
-    CYGACC_CALL_IF_SET_CONSOLE_COMM
-    (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
-  if (info->chan >= 0)
-    {
-      CYGACC_CALL_IF_SET_CONSOLE_COMM (info->chan);
-    }
-  else
-    {
-      CYGACC_CALL_IF_SET_CONSOLE_COMM (console_chan);
-    }
-  xyz.__chan = CYGACC_CALL_IF_CONSOLE_PROCS ();
-
-  CYGACC_CALL_IF_SET_CONSOLE_COMM (console_chan);
-  CYGACC_COMM_IF_CONTROL (*xyz.__chan, __COMMCTL_SET_TIMEOUT,
-			  xyzModem_CHAR_TIMEOUT);
-#else
 /* TODO: CHECK ! */
   int dummy = 0;
   xyz.__chan = &dummy;
-#endif
   xyz.len = 0;
   xyz.crc_mode = true;
   xyz.at_eof = false;
@@ -524,10 +433,8 @@ xyzModem_stream_open (connection_info_t * info, int *err)
   xyz.total_SOH = 0;
   xyz.total_STX = 0;
   xyz.total_CAN = 0;
-#ifdef USE_YMODEM_LENGTH
   xyz.read_length = 0;
   xyz.file_length = 0;
-#endif
 
   CYGACC_COMM_IF_PUTC (*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
 
@@ -546,12 +453,10 @@ xyzModem_stream_open (connection_info_t * info, int *err)
 	  /* Y-modem file information header */
 	  if (xyz.blk == 0)
 	    {
-#ifdef USE_YMODEM_LENGTH
 	      /* skip filename */
 	      while (*xyz.bufp++);
 	      /* get the length */
 	      parse_num ((char *) xyz.bufp, &xyz.file_length, NULL, " ");
-#endif
 	      /* The rest of the file name data block quietly discarded */
 	      xyz.tx_ack = true;
 	    }
@@ -604,13 +509,8 @@ xyzModem_stream_read (char *buf, int size, int *err)
 				("ACK block %d (%d)\n", xyz.blk, __LINE__));
 		      xyz.next_blk = (xyz.next_blk + 1) & 0xFF;
 
-#if defined(xyzModem_zmodem) || defined(USE_YMODEM_LENGTH)
 		      if (xyz.mode == xyzModem_xmodem || xyz.file_length == 0)
 			{
-#else
-		      if (1)
-			{
-#endif
 			  /* Data blocks can be padded with ^Z (EOF) characters */
 			  /* This code tries to detect and remove them */
 			  if ((xyz.bufp[xyz.len - 1] == EOF) &&
@@ -625,7 +525,6 @@ xyzModem_stream_read (char *buf, int size, int *err)
 			    }
 			}
 
-#ifdef USE_YMODEM_LENGTH
 		      /*
 		       * See if accumulated length exceeds that of the file.
 		       * If so, reduce size (i.e., cut out pad bytes)
@@ -640,7 +539,6 @@ xyzModem_stream_read (char *buf, int size, int *err)
 			      xyz.len -= (xyz.read_length - xyz.file_length);
 			    }
 			}
-#endif
 		      break;
 		    }
 		  else if (xyz.blk == ((xyz.next_blk - 1) & 0xFF))
@@ -809,10 +707,3 @@ xyzModem_error (int err)
 /*
  * RedBoot interface
  */
-#if 0				/* SB */
-GETC_IO_FUNCS (xyzModem_io, xyzModem_stream_open, xyzModem_stream_close,
-	       xyzModem_stream_terminate, xyzModem_stream_read,
-	       xyzModem_error);
-RedBoot_load (xmodem, xyzModem_io, false, false, xyzModem_xmodem);
-RedBoot_load (ymodem, xyzModem_io, false, false, xyzModem_ymodem);
-#endif
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index 1cd3f1f..6634139 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -14,6 +14,10 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_NET_ETHADDR_EEPROM=y
+CONFIG_NET_ETHADDR_EEPROM_I2C=y
+CONFIG_NET_ETHADDR_EEPROM_I2C_BUS=1
+CONFIG_I2C1_ENABLE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index a4ade72..4c720b3 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -21,6 +21,10 @@ CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DFU_RAM=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_NET_ETHADDR_EEPROM=y
+CONFIG_NET_ETHADDR_EEPROM_I2C=y
+CONFIG_NET_ETHADDR_EEPROM_I2C_BUS=1
+CONFIG_I2C1_ENABLE=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 4fe4e4a..564ae25 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -16,6 +16,10 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_NET_ETHADDR_EEPROM=y
+CONFIG_NET_ETHADDR_EEPROM_I2C=y
+CONFIG_NET_ETHADDR_EEPROM_I2C_BUS=1
+CONFIG_I2C1_ENABLE=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index e1d91e3..93be13b 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -19,6 +19,10 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_NET_ETHADDR_EEPROM=y
+CONFIG_NET_ETHADDR_EEPROM_I2C=y
+CONFIG_NET_ETHADDR_EEPROM_I2C_BUS=1
+CONFIG_I2C1_ENABLE=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig
new file mode 100644
index 0000000..df43e5a
--- /dev/null
+++ b/configs/CHIP_pro_defconfig
@@ -0,0 +1,33 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_SPL_MMC_SUPPORT is not set
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
+CONFIG_USB0_VBUS_PIN="PB10"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-gr8-chip-pro"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,SYS_NAND_BLOCK_SIZE=0x40000,SYS_NAND_PAGE_SIZE=4096,SYS_NAND_OOBSIZE=256"
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_UBI_PART="UBI"
+CONFIG_ENV_UBI_VOLUME="uboot-env"
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=sunxi-nand.0:256k(spl),256k(spl-backup),2m(uboot),2m(uboot-backup),-(UBI)"
+# CONFIG_MMC is not set
+CONFIG_NAND_SUNXI=y
+CONFIG_AXP_ALDO3_VOLT=3300
+CONFIG_AXP_ALDO4_VOLT=3300
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
+CONFIG_G_DNL_PRODUCT_NUM=0x1010
diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig
new file mode 100644
index 0000000..7530d7d
--- /dev/null
+++ b/configs/Sunchip_CX-A99_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN9I=y
+CONFIG_DRAM_CLK=600
+CONFIG_DRAM_ZQ=3881915
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PH17"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_VBUS_PIN="PH15"
+CONFIG_USB0_VBUS_DET=""
+CONFIG_USB0_ID_DET=""
+CONFIG_USB1_VBUS_PIN="PL7"
+CONFIG_USB3_VBUS_PIN="PL8"
+CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cx-a99"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index afbfb0d..b8e2864 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -2,9 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_RMOBILE=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_ALT=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_BOOTDELAY=3
 CONFIG_VERSION_VARIABLE=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index ff5bf64..8ab8653 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -14,6 +14,7 @@ CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
@@ -32,12 +33,15 @@ CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
 # CONFIG_BLK is not set
 CONFIG_DFU_MMC=y
 CONFIG_DFU_NAND=y
 CONFIG_DFU_RAM=y
 CONFIG_DM_I2C=y
+CONFIG_MISC=y
 CONFIG_DM_MMC=y
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_MMC_OMAP_HS=y
@@ -48,8 +52,10 @@ CONFIG_SYS_NS16550=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_TI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 5d238ce..1f68af6 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_AM43XX=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
@@ -72,4 +73,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 3aafeca..68bb6d8 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
 CONFIG_SPL_ETH_SUPPORT=y
 CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_NET_SUPPORT=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index b7f1488..5923983 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_AM43XX=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_ISW_ENTRY_ADDR=0x40300350
 CONFIG_SPL_STACK_R_ADDR=0x82000000
@@ -70,4 +71,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index f1c9445..795dfd7 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_AM43XX=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_ISW_ENTRY_ADDR=0x403018e0
@@ -9,12 +10,19 @@ CONFIG_FIT=y
 CONFIG_FIT_IMAGE_POST_PROCESS=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1, NAND"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ETH_SUPPORT=y
 CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USBETH_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -40,6 +48,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ISO_PARTITION=y
 CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
 CONFIG_DM=y
 # CONFIG_BLK is not set
 CONFIG_DFU_MMC=y
@@ -52,8 +61,8 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_DM_ETH=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
@@ -73,4 +82,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 789cc97..97bd08e 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -1,12 +1,13 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_AM57XX_EVM=y
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ARMV7_LPAE=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
+CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_BOARD_SETUP=y
@@ -14,7 +15,9 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_DMA_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_HUSH_PARSER=y
@@ -52,8 +55,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ISO_PARTITION=y
 CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am572x-idk am571x-idk"
 CONFIG_DM=y
+CONFIG_SPL_DM=y
 # CONFIG_BLK is not set
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
@@ -87,4 +92,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 2e27e08..99907f5 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -1,13 +1,15 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_TARGET_AM57XX_EVM=y
-CONFIG_TI_SECURE_EMIF_REGION_START=0xbe000000
+CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ARMV7_LPAE=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
 CONFIG_FIT=y
@@ -19,7 +21,9 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_DMA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_FASTBOOT=y
@@ -48,6 +52,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -55,7 +60,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ISO_PARTITION=y
 CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am572x-idk am571x-idk"
 CONFIG_DM=y
+CONFIG_SPL_DM=y
 # CONFIG_BLK is not set
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
@@ -68,6 +76,10 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PALMAS=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PALMAS=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
@@ -85,4 +97,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
new file mode 100644
index 0000000..10862e5
--- /dev/null
+++ b/configs/apalis-tk1_defconfig
@@ -0,0 +1,47 @@
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA124=y
+CONFIG_TARGET_APALIS_TK1=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra124-apalis"
+CONFIG_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=1
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="Apalis TK1 # "
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Toradex"
+CONFIG_G_DNL_VENDOR_NUM=0x1b67
+CONFIG_G_DNL_PRODUCT_NUM=0xffff
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index aed41aa..1af505d 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -1,8 +1,9 @@
 CONFIG_ARC=y
 CONFIG_SYS_DCACHE_OFF=y
+CONFIG_TARGET_AXS101=y
 CONFIG_SYS_TEXT_BASE=0x81000000
 CONFIG_SYS_CLK_FREQ=750000000
-CONFIG_DEFAULT_DEVICE_TREE="axs10x"
+CONFIG_DEFAULT_DEVICE_TREE="axs101"
 CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_PROMPT="AXS# "
@@ -18,7 +19,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
-CONFIG_CLK=y
 CONFIG_SYS_I2C_DW=y
 CONFIG_MMC=y
 CONFIG_MMC_DW=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index b62e0ad..fb8e72f 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARC=y
 CONFIG_ISA_ARCV2=y
 CONFIG_SYS_TEXT_BASE=0x81000000
 CONFIG_SYS_CLK_FREQ=100000000
-CONFIG_DEFAULT_DEVICE_TREE="axs10x"
+CONFIG_DEFAULT_DEVICE_TREE="axs103"
 CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_PROMPT="AXS# "
@@ -18,7 +18,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
-CONFIG_CLK=y
 CONFIG_SYS_I2C_DW=y
 CONFIG_MMC=y
 CONFIG_MMC_DW=y
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index c6aa24f..d2f9f24 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -48,6 +48,7 @@ CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_MMC=y
+CONFIG_MMC_PCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/bcm958712k_defconfig b/configs/bcm958712k_defconfig
new file mode 100644
index 0000000..96e4bce
--- /dev/null
+++ b/configs/bcm958712k_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_TARGET_BCMNS2=y
+CONFIG_IDENT_STRING=" Broadcom Northstar 2"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="u-boot> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/bct-brettl2_defconfig b/configs/bct-brettl2_defconfig
deleted file mode 100644
index 4aab03b..0000000
--- a/configs/bct-brettl2_defconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BCT_BRETTL2=y
-CONFIG_BOOTDELAY=1
-CONFIG_SILENT_CONSOLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/bf506f-ezkit_defconfig b/configs/bf506f-ezkit_defconfig
deleted file mode 100644
index 942d50c..0000000
--- a/configs/bf506f-ezkit_defconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF506F_EZKIT=y
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
diff --git a/configs/bf518f-ezbrd_defconfig b/configs/bf518f-ezbrd_defconfig
deleted file mode 100644
index ef83ac8..0000000
--- a/configs/bf518f-ezbrd_defconfig
+++ /dev/null
@@ -1,26 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF518F_EZBRD=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf525-ucr2_defconfig b/configs/bf525-ucr2_defconfig
deleted file mode 100644
index 68d2f48..0000000
--- a/configs/bf525-ucr2_defconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF525_UCR2=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_EON=y
diff --git a/configs/bf526-ezbrd_defconfig b/configs/bf526-ezbrd_defconfig
deleted file mode 100644
index 92cdb3c..0000000
--- a/configs/bf526-ezbrd_defconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF526_EZBRD=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/bf527-ad7160-eval_defconfig b/configs/bf527-ad7160-eval_defconfig
deleted file mode 100644
index 9f75eb0..0000000
--- a/configs/bf527-ad7160-eval_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF527_AD7160_EVAL=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig
deleted file mode 100644
index c2f8df9..0000000
--- a/configs/bf527-ezkit-v2_defconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF527_EZKIT=y
-CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1"
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_LIB_RAND=y
diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig
deleted file mode 100644
index 9325984..0000000
--- a/configs/bf527-ezkit_defconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF527_EZKIT=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-# CONFIG_NET_TFTP_VARS is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/bf527-sdp_defconfig b/configs/bf527-sdp_defconfig
deleted file mode 100644
index 21377a8..0000000
--- a/configs/bf527-sdp_defconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF527_SDP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf533-ezkit_defconfig b/configs/bf533-ezkit_defconfig
deleted file mode 100644
index e95d134..0000000
--- a/configs/bf533-ezkit_defconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF533_EZKIT=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/bf533-stamp_defconfig b/configs/bf533-stamp_defconfig
deleted file mode 100644
index 35c69f0..0000000
--- a/configs/bf533-stamp_defconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF533_STAMP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-# CONFIG_REGEX is not set
-CONFIG_LIB_RAND=y
diff --git a/configs/bf537-minotaur_defconfig b/configs/bf537-minotaur_defconfig
deleted file mode 100644
index 8a6fb15..0000000
--- a/configs/bf537-minotaur_defconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF537_MINOTAUR=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_PROMPT="minotaur> "
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_BAUDRATE=57600
diff --git a/configs/bf537-pnav_defconfig b/configs/bf537-pnav_defconfig
deleted file mode 100644
index 4c479fe..0000000
--- a/configs/bf537-pnav_defconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF537_PNAV=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/bf537-srv1_defconfig b/configs/bf537-srv1_defconfig
deleted file mode 100644
index dc88c44..0000000
--- a/configs/bf537-srv1_defconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF537_SRV1=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_PROMPT="srv1> "
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/bf537-stamp_defconfig b/configs/bf537-stamp_defconfig
deleted file mode 100644
index 0b38c52..0000000
--- a/configs/bf537-stamp_defconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF537_STAMP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/bf538f-ezkit_defconfig b/configs/bf538f-ezkit_defconfig
deleted file mode 100644
index 417728e..0000000
--- a/configs/bf538f-ezkit_defconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF538F_EZKIT=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_REGEX is not set
-CONFIG_LIB_RAND=y
diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig
deleted file mode 100644
index 05d5e26..0000000
--- a/configs/bf548-ezkit_defconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF548_EZKIT=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/bf561-acvilon_defconfig b/configs/bf561-acvilon_defconfig
deleted file mode 100644
index 809a06c..0000000
--- a/configs/bf561-acvilon_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF561_ACVILON=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_PROMPT="Acvilon> "
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_BAUDRATE=57600
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/bf561-ezkit_defconfig b/configs/bf561-ezkit_defconfig
deleted file mode 100644
index 88169c3..0000000
--- a/configs/bf561-ezkit_defconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF561_EZKIT=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/bf609-ezkit_defconfig b/configs/bf609-ezkit_defconfig
deleted file mode 100644
index 11c0000..0000000
--- a/configs/bf609-ezkit_defconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF609_EZKIT=y
-CONFIG_SILENT_CONSOLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_NETDEVICES=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_LIB_RAND=y
diff --git a/configs/blackstamp_defconfig b/configs/blackstamp_defconfig
deleted file mode 100644
index 6e66331..0000000
--- a/configs/blackstamp_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BLACKSTAMP=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_BAUDRATE=57600
diff --git a/configs/blackvme_defconfig b/configs/blackvme_defconfig
deleted file mode 100644
index 9ef3044..0000000
--- a/configs/blackvme_defconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BLACKVME=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_BAUDRATE=57600
diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig
index 70da41d..5664421 100644
--- a/configs/blanche_defconfig
+++ b/configs/blanche_defconfig
@@ -2,9 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_RMOBILE=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_BLANCHE=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_VERSION_VARIABLE=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/br4_defconfig b/configs/br4_defconfig
deleted file mode 100644
index 90ce839..0000000
--- a/configs/br4_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BR4=y
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_PROMPT="br4>"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/cm-bf527_defconfig b/configs/cm-bf527_defconfig
deleted file mode 100644
index 080fc15..0000000
--- a/configs/cm-bf527_defconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_CM_BF527=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf533_defconfig b/configs/cm-bf533_defconfig
deleted file mode 100644
index abac6d9..0000000
--- a/configs/cm-bf533_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_CM_BF533=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/cm-bf537e_defconfig b/configs/cm-bf537e_defconfig
deleted file mode 100644
index 86af797..0000000
--- a/configs/cm-bf537e_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_CM_BF537E=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf537u_defconfig b/configs/cm-bf537u_defconfig
deleted file mode 100644
index e5e0a8d..0000000
--- a/configs/cm-bf537u_defconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_CM_BF537U=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf548_defconfig b/configs/cm-bf548_defconfig
deleted file mode 100644
index 373895e..0000000
--- a/configs/cm-bf548_defconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_CM_BF548=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-# CONFIG_REGEX is not set
-CONFIG_LIB_RAND=y
diff --git a/configs/cm-bf561_defconfig b/configs/cm-bf561_defconfig
deleted file mode 100644
index 59f7c41..0000000
--- a/configs/cm-bf561_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_CM_BF561=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
index 890d28c..d96bfcb 100644
--- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
@@ -50,6 +50,7 @@ CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_INTEL=y
 CONFIG_WINBOND_W83627=y
 CONFIG_MMC=y
+CONFIG_MMC_PCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 6e4cd84..1642bf2 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -49,6 +49,7 @@ CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_INTEL=y
 CONFIG_WINBOND_W83627=y
 CONFIG_MMC=y
+CONFIG_MMC_PCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig
new file mode 100644
index 0000000..e1c4f0c
--- /dev/null
+++ b/configs/controlcenterdc_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_CONTROLCENTERDC=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-38x-controlcenterdc"
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_EFI_PARTITION=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_MV=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_TPM_ATMEL_TWI=y
+CONFIG_TPM_AUTH_SESSIONS=y
+CONFIG_TPM_FLUSH_RESOURCES=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_TPM=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 13a00c2..4a88f5f 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -37,6 +37,7 @@ CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_MMC=y
+CONFIG_MMC_PCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig
index ce447f5..d5bd66f 100644
--- a/configs/dfi-bt700-q7x-151_defconfig
+++ b/configs/dfi-bt700-q7x-151_defconfig
@@ -47,6 +47,7 @@ CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_NUVOTON_NCT6102D=y
 CONFIG_MMC=y
+CONFIG_MMC_PCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/dnp5370_defconfig b/configs/dnp5370_defconfig
deleted file mode 100644
index 2d0d779..0000000
--- a/configs/dnp5370_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_DNP5370=y
-# CONFIG_AUTOBOOT is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 0293d45..42f87b3 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -1,7 +1,8 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
-CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 # CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_TARGET_DRA7XX_EVM=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ARMV7_LPAE=y
@@ -14,7 +15,9 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_DMA_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_HUSH_PARSER=y
@@ -52,8 +55,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ISO_PARTITION=y
 CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
 CONFIG_DM=y
+CONFIG_SPL_DM=y
 # CONFIG_BLK is not set
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
@@ -96,4 +101,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 3b95650..871604f 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -3,12 +3,13 @@ CONFIG_OMAP54XX=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_TI_SECURE_EMIF_REGION_START=0xbe000000
+CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ARMV7_LPAE=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
 CONFIG_FIT=y
@@ -20,7 +21,9 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_DMA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_FASTBOOT=y
@@ -57,8 +60,10 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ISO_PARTITION=y
 CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
 CONFIG_DM=y
+CONFIG_SPL_DM=y
 # CONFIG_BLK is not set
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
@@ -101,4 +106,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index bedc1fd..50b0d74 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -12,6 +12,8 @@ CONFIG_SPL_ATF_TEXT_BASE=0x00010000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 570f9ea..f60abc3 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -42,6 +42,7 @@ CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_MMC=y
+CONFIG_MMC_PCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index 4878203..761d758 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -2,9 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_RMOBILE=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_GOSE=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_BOOTDELAY=3
 CONFIG_VERSION_VARIABLE=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/gr_cpci_ax2000_defconfig b/configs/gr_cpci_ax2000_defconfig
deleted file mode 100644
index 362698b..0000000
--- a/configs/gr_cpci_ax2000_defconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-CONFIG_SPARC=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_IDENT_STRING=" Gaisler LEON3 GR-CPCI-AX2000"
-CONFIG_TARGET_GR_CPCI_AX2000=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_BAUDRATE=38400
diff --git a/configs/gr_ep2s60_defconfig b/configs/gr_ep2s60_defconfig
deleted file mode 100644
index c3ac42f..0000000
--- a/configs/gr_ep2s60_defconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-CONFIG_SPARC=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_IDENT_STRING=" Gaisler LEON3 EP2S60"
-CONFIG_TARGET_GR_EP2S60=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_BAUDRATE=38400
diff --git a/configs/gr_xc3s_1500_defconfig b/configs/gr_xc3s_1500_defconfig
deleted file mode 100644
index ecf0886..0000000
--- a/configs/gr_xc3s_1500_defconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-CONFIG_SPARC=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_IDENT_STRING=" Gaisler LEON3 GR-XC3S-1500"
-CONFIG_TARGET_GR_XC3S_1500=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_BAUDRATE=38400
diff --git a/configs/grsim_defconfig b/configs/grsim_defconfig
deleted file mode 100644
index 0d6ab4a..0000000
--- a/configs/grsim_defconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-CONFIG_SPARC=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_IDENT_STRING=" Gaisler GRSIM"
-CONFIG_TARGET_GRSIM=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_MEMORY is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP=y
-CONFIG_BAUDRATE=38400
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_APBUART=y
-CONFIG_DEBUG_UART_BASE=0x80000100
-CONFIG_DEBUG_UART_CLOCK=40000000
diff --git a/configs/grsim_leon2_defconfig b/configs/grsim_leon2_defconfig
deleted file mode 100644
index 2875840..0000000
--- a/configs/grsim_leon2_defconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-CONFIG_SPARC=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_IDENT_STRING=" Gaisler GRSIM LEON2"
-CONFIG_TARGET_GRSIM_LEON2=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_MEMORY is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_BAUDRATE=38400
diff --git a/configs/ibf-dsp561_defconfig b/configs/ibf-dsp561_defconfig
deleted file mode 100644
index 13a7b19..0000000
--- a/configs/ibf-dsp561_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_IBF_DSP561=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_LIB_RAND=y
diff --git a/configs/ip04_defconfig b/configs/ip04_defconfig
deleted file mode 100644
index 1e05d3e..0000000
--- a/configs/ip04_defconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_IP04=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index d319705..63db1ae 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_TEXT_BASE=0x0c000000
 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
new file mode 100644
index 0000000..d515ced
--- /dev/null
+++ b/configs/k2e_hs_evm_defconfig
@@ -0,0 +1,51 @@
+CONFIG_ARM=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_SYS_TEXT_BASE=0x0c000060
+CONFIG_TARGET_K2E_EVM=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
+CONFIG_FIT=y
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="K2E HS EVM # "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_TI_AEMIF=y
+# CONFIG_MMC is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index bbdcc2f..44c9dff 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_TEXT_BASE=0x0c000000
 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
new file mode 100644
index 0000000..9c21867
--- /dev/null
+++ b/configs/k2g_hs_evm_defconfig
@@ -0,0 +1,55 @@
+CONFIG_ARM=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_TARGET_K2G_EVM=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_TEXT_BASE=0x0c000060
+CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_REMOTEPROC_TI_POWER=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index b22086d..12b8047 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_TEXT_BASE=0x0c000000
 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
new file mode 100644
index 0000000..9fe91ea
--- /dev/null
+++ b/configs/k2hk_hs_evm_defconfig
@@ -0,0 +1,51 @@
+CONFIG_ARM=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_SYS_TEXT_BASE=0x0c000060
+CONFIG_TARGET_K2HK_EVM=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
+CONFIG_FIT=y
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="K2HK EVM # "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_TI_AEMIF=y
+# CONFIG_MMC is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 5a28112..39a992d 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_TEXT_BASE=0x0c000000
 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index 6df0e25..e6b1684 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -2,9 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_RMOBILE=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_KOELSCH=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_BOOTDELAY=3
 CONFIG_VERSION_VARIABLE=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index 040efc0..a123b37 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -2,9 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_RMOBILE=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_LAGER=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_BOOTDELAY=3
 CONFIG_VERSION_VARIABLE=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 4f4ae5a..ed429cb 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -9,6 +9,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
 CONFIG_NAND_BOOT=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index e57c42b..02b5b54 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -9,6 +9,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_SD_BOOT=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index 9beb050..711fc10 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,EMMC_BOOT"
 CONFIG_SD_BOOT=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 032aab3..a3965f2 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
 CONFIG_SD_BOOT=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 0344d5f..fb9a3e4 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080AQDS=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index c4d8204..a1e552d 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080ARDB=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 5f61f2a..8dac1d7 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -47,6 +47,7 @@ CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_MMC=y
+CONFIG_MMC_PCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
new file mode 100644
index 0000000..203824b
--- /dev/null
+++ b/configs/miqi-rk3288_defconfig
@@ -0,0 +1,73 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3288=y
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_TARGET_MIQI_RK3288=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi"
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_ACT8846=y
+CONFIG_REGULATOR_ACT8846=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_ROCKCHIP_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index 80f2599..3e548a8 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_MVEBU_DB_88F3720=y
+CONFIG_TARGET_MVEBU_ARMADA_37XX=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -33,9 +33,11 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
 CONFIG_BLOCK_CACHE=y
 CONFIG_DM_I2C=y
-CONFIG_DM_I2C_COMPAT=y
 CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
diff --git a/configs/mvebu_db-88f7040_defconfig b/configs/mvebu_db-88f7040_defconfig
index f20158a..797eabb 100644
--- a/configs/mvebu_db-88f7040_defconfig
+++ b/configs/mvebu_db-88f7040_defconfig
@@ -47,7 +47,8 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_PHY_MARVELL=y
+CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCIE_DW_MVEBU=y
diff --git a/configs/mvebu_db-88f8040_defconfig b/configs/mvebu_db-88f8040_defconfig
index 3611b84..046da09 100644
--- a/configs/mvebu_db-88f8040_defconfig
+++ b/configs/mvebu_db-88f8040_defconfig
@@ -47,7 +47,8 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_PHY_MARVELL=y
+CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCIE_DW_MVEBU=y
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
new file mode 100644
index 0000000..f02ae64
--- /dev/null
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -0,0 +1,66 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MVEBU_ARMADA_37XX=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-3720-espressobin"
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_BOARD_EARLY_INIT_F=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_BLOCK_CACHE=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_MVEBU_A3700_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=25804800
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_MVEBU_A3700_UART=y
+CONFIG_MVEBU_A3700_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig
new file mode 100644
index 0000000..0de3d9e
--- /dev/null
+++ b/configs/mvebu_mcbin-88f8040_defconfig
@@ -0,0 +1,74 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MVEBU_ARMADA_8K=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-8040-mcbin"
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_BLOCK_CACHE=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_DM_GPIO=y
+CONFIG_MVEBU_GPIO=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_DW_MVEBU=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig
new file mode 100644
index 0000000..9598bd5
--- /dev/null
+++ b/configs/nanopi_neo_air_defconfig
@@ -0,0 +1,17 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo-air"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_EHCI_HCD=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 352c9b4..7c8228b 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -27,6 +27,8 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000
 CONFIG_SPI_FLASH=y
diff --git a/configs/openrisc-generic_defconfig b/configs/openrisc-generic_defconfig
deleted file mode 100644
index 55f0122..0000000
--- a/configs/openrisc-generic_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_OPENRISC=y
-CONFIG_TARGET_OPENRISC_GENERIC=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_NETDEVICES=y
-CONFIG_ETHOC=y
-CONFIG_SYS_NS16550=y
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index e14cb9d..201771e 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=672
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
new file mode 100644
index 0000000..19a5c2b
--- /dev/null
+++ b/configs/orangepi_pc2_defconfig
@@ -0,0 +1,19 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_SPL=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881977
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index 0f7f97f..206ba47 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -2,9 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_RMOBILE=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_PORTER=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_BOOTDELAY=3
 CONFIG_VERSION_VARIABLE=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/pr1_defconfig b/configs/pr1_defconfig
deleted file mode 100644
index a26ba61..0000000
--- a/configs/pr1_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_PR1=y
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_PROMPT="pr1>"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
new file mode 100644
index 0000000..d4e12d7
--- /dev/null
+++ b/configs/puma-rk3399_defconfig
@@ -0,0 +1,72 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma"
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_SOURCE="board/rockchip/evb_rk3399/fit_spl_atf.its"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ9031=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_ROCKCHIP_RK3399_PINCTRL=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=115200
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xFF180000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
new file mode 100644
index 0000000..20a065a
--- /dev/null
+++ b/configs/rock_defconfig
@@ -0,0 +1,51 @@
+CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3188=y
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_TARGET_ROCK=y
+CONFIG_SPL_STACK_R_ADDR=0x60080000
+CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_OF_PLATDATA=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+# CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_ROCKCHIP_RK3188_PINCTRL=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_PMIC_ACT8846=y
+CONFIG_REGULATOR_ACT8846=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_RAM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x20064000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/salvator-x_defconfig b/configs/salvator-x_defconfig
index aa946d0..b150029 100644
--- a/configs/salvator-x_defconfig
+++ b/configs/salvator-x_defconfig
@@ -3,9 +3,6 @@ CONFIG_ARCH_RMOBILE=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_RCAR_GEN3=y
 CONFIG_TARGET_SALVATOR_X=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_VERSION_VARIABLE=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index eeba819..293b08e 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -2,9 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_RMOBILE=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SILK=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_BOOTDELAY=3
 CONFIG_VERSION_VARIABLE=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index 9646ec7..aaa8502 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -2,9 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_RMOBILE=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_STOUT=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_BOOTDELAY=3
 CONFIG_VERSION_VARIABLE=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig
new file mode 100644
index 0000000..296df00
--- /dev/null
+++ b/configs/sun8i_a23_evb_defconfig
@@ -0,0 +1,19 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A23=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=63351
+CONFIG_USB0_VBUS_PIN="axp_drivebus"
+CONFIG_USB0_VBUS_DET="axp_vbus_detect"
+CONFIG_USB1_VBUS_PIN="PH7"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-evb"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_EHCI_HCD=y
diff --git a/configs/tcm-bf518_defconfig b/configs/tcm-bf518_defconfig
deleted file mode 100644
index 4485210..0000000
--- a/configs/tcm-bf518_defconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_TCM_BF518=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/tcm-bf537_defconfig b/configs/tcm-bf537_defconfig
deleted file mode 100644
index eaeeb53..0000000
--- a/configs/tcm-bf537_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_TCM_BF537=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig
index cde33bb..1703cee 100644
--- a/configs/theadorable-x86-dfi-bt700_defconfig
+++ b/configs/theadorable-x86-dfi-bt700_defconfig
@@ -47,6 +47,7 @@ CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_NUVOTON_NCT6102D=y
 CONFIG_MMC=y
+CONFIG_MMC_PCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index ab76aa3..6f9bdb2 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -34,11 +34,15 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ISO_PARTITION=y
 CONFIG_OF_CONTROL=y
+CONFIG_DM_I2C_GPIO=y
 CONFIG_DFU_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_S5P=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_MAX77686=y
+CONFIG_SYS_I2C_S3C24X0=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 7fe6c3d..23024fd 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -34,10 +34,14 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_ISO_PARTITION=y
 CONFIG_OF_CONTROL=y
 CONFIG_DFU_MMC=y
+CONFIG_DM_I2C_GPIO=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_S5P=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_MAX8997=y
+CONFIG_SYS_I2C_S3C24X0=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
diff --git a/disk/Kconfig b/disk/Kconfig
index 16ff52d..9396562 100644
--- a/disk/Kconfig
+++ b/disk/Kconfig
@@ -22,7 +22,6 @@ config PARTITIONS
 config MAC_PARTITION
 	bool "Enable Apple's MacOS partition table"
 	depends on PARTITIONS
-	default y if SPARC
 	help
 	  Say Y here if you would like to use device under U-Boot which
 	  were partitioned on a Macintosh.
@@ -36,7 +35,7 @@ config DOS_PARTITION
 	bool "Enable MS Dos partition table"
 	depends on PARTITIONS
 	default y if DISTRO_DEFAULTS
-	default y if x86 || SPARC || CMD_FAT || USB_STORAGE
+	default y if x86 || CMD_FAT || USB_STORAGE
 	help
 	  traditional on the Intel architecture, USB sticks, etc.
 
@@ -49,7 +48,7 @@ config ISO_PARTITION
 	bool "Enable ISO partition table"
 	depends on PARTITIONS
 	default y if DISTRO_DEFAULTS
-	default y if SPARC || MIPS || TEGRA
+	default y if MIPS || TEGRA
 
 config SPL_ISO_PARTITION
 	bool "Enable ISO partition table for SPL"
@@ -79,6 +78,19 @@ config EFI_PARTITION
 	  common when EFI is the bootloader.  Note 2TB partition limit;
 	  see disk/part_efi.c
 
+config EFI_PARTITION_ENTRIES_OFF
+        int "Offset (in bytes) of the EFI partition entries"
+	depends on EFI_PARTITION
+	default 0
+	help
+	  Specify an earliest location (in bytes) where the partition
+	  entries may be located. This is meant to allow "punching a
+	  hole into a device" to create a gap for an SPL, its payload
+	  and the U-Boot environment.
+
+	  If unsure, leave at 0 (which will locate the partition
+	  entries at the first possible LBA following the GPT header).
+
 config SPL_EFI_PARTITION
 	bool "Enable EFI GPT partition table for SPL"
 	depends on  SPL && PARTITIONS
diff --git a/disk/part_efi.c b/disk/part_efi.c
index db0c890..1b7ba27 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -13,11 +13,13 @@
 #include <asm/unaligned.h>
 #include <common.h>
 #include <command.h>
+#include <fdtdec.h>
 #include <ide.h>
 #include <inttypes.h>
 #include <malloc.h>
 #include <memalign.h>
 #include <part_efi.h>
+#include <linux/compiler.h>
 #include <linux/ctype.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -373,8 +375,8 @@ int write_gpt_table(struct blk_desc *dev_desc,
 	if (blk_dwrite(dev_desc, 1, 1, gpt_h) != 1)
 		goto err;
 
-	if (blk_dwrite(dev_desc, 2, pte_blk_cnt, gpt_e)
-	    != pte_blk_cnt)
+	if (blk_dwrite(dev_desc, le64_to_cpu(gpt_h->partition_entry_lba),
+		       pte_blk_cnt, gpt_e) != pte_blk_cnt)
 		goto err;
 
 	prepare_backup_gpt_header(gpt_h);
@@ -498,6 +500,49 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
 	return 0;
 }
 
+static uint32_t partition_entries_offset(struct blk_desc *dev_desc)
+{
+	uint32_t offset_blks = 2;
+	int __maybe_unused config_offset;
+
+#if defined(CONFIG_EFI_PARTITION_ENTRIES_OFF)
+	/*
+	 * Some architectures require their SPL loader at a fixed
+	 * address within the first 16KB of the disk.  To avoid an
+	 * overlap with the partition entries of the EFI partition
+	 * table, the first safe offset (in bytes, from the start of
+	 * the disk) for the entries can be set in
+	 * CONFIG_EFI_PARTITION_ENTRIES_OFF.
+	 */
+	offset_blks =
+		PAD_TO_BLOCKSIZE(CONFIG_EFI_PARTITION_ENTRIES_OFF, dev_desc);
+#endif
+
+#if defined(CONFIG_OF_CONTROL)
+	/*
+	 * Allow the offset of the first partition entires (in bytes
+	 * from the start of the device) to be specified as a property
+	 * of the device tree '/config' node.
+	 */
+	config_offset = fdtdec_get_config_int(gd->fdt_blob,
+					      "u-boot,efi-partition-entries-offset",
+					      -EINVAL);
+	if (config_offset != -EINVAL)
+		offset_blks = PAD_TO_BLOCKSIZE(config_offset, dev_desc);
+#endif
+
+	debug("efi: partition entries offset (in blocks): %d\n", offset_blks);
+
+	/*
+	 * The earliest LBA this can be at is LBA#2 (i.e. right behind
+	 * the (protective) MBR and the GPT header.
+	 */
+	if (offset_blks < 2)
+		offset_blks = 2;
+
+	return offset_blks;
+}
+
 int gpt_fill_header(struct blk_desc *dev_desc, gpt_header *gpt_h,
 		char *str_guid, int parts_count)
 {
@@ -506,9 +551,11 @@ int gpt_fill_header(struct blk_desc *dev_desc, gpt_header *gpt_h,
 	gpt_h->header_size = cpu_to_le32(sizeof(gpt_header));
 	gpt_h->my_lba = cpu_to_le64(1);
 	gpt_h->alternate_lba = cpu_to_le64(dev_desc->lba - 1);
-	gpt_h->first_usable_lba = cpu_to_le64(34);
 	gpt_h->last_usable_lba = cpu_to_le64(dev_desc->lba - 34);
-	gpt_h->partition_entry_lba = cpu_to_le64(2);
+	gpt_h->partition_entry_lba =
+		cpu_to_le64(partition_entries_offset(dev_desc));
+	gpt_h->first_usable_lba =
+		cpu_to_le64(le64_to_cpu(gpt_h->partition_entry_lba) + 32);
 	gpt_h->num_partition_entries = cpu_to_le32(GPT_ENTRY_NUMBERS);
 	gpt_h->sizeof_partition_entry = cpu_to_le32(sizeof(gpt_entry));
 	gpt_h->header_crc32 = 0;
diff --git a/doc/README.fdt-control b/doc/README.fdt-control
index 2913fcb..c965629 100644
--- a/doc/README.fdt-control
+++ b/doc/README.fdt-control
@@ -168,22 +168,6 @@ After board configuration is done, fdt supported u-boot can be build in two ways
     $ make DEVICE_TREE=<dts-file-name>
 
 
-Configuration Options
----------------------
-
-A number of run-time configuration options are provided in the /config node
-of the control device tree. You can access these using fdtdec_get_config_int(),
-fdtdec_get_config_bool() and fdtdec_get_config_string().
-
-Available options are:
-
-silent-console
-	If present and non-zero, the console is silenced by default on boot.
-
-no-keyboard
-	Tells U-Boot not to expect an attached keyboard with a VGA console
-
-
 Limitations
 -----------
 
diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx
index f9b023f..93ed641 100644
--- a/doc/README.mpc85xx
+++ b/doc/README.mpc85xx
@@ -156,7 +156,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
        Disable	  : 15, 14
 
    11) Create DDR's TLB entriy
-       Location	  : Board_init_f -> init_func_ram -> initdram
+       Location	  : Board_init_f -> dram_init
        TLB entry  : Search free TLB entry
 
    12) Update Flash's TLB entry
diff --git a/doc/README.rockchip b/doc/README.rockchip
index 186a1a0..2d8cf9f 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -36,15 +36,16 @@ You will need:
 Building
 ========
 
-At present seven RK3288 boards are supported:
+At present eight RK3288 boards are supported:
 
    - EVB RK3288 - use evb-rk3288 configuration
    - Fennec RK3288 - use fennec-rk3288 configuration
    - Firefly RK3288 - use firefly-rk3288 configuration
    - Hisense Chromebook - use chromebook_jerry configuration
-   - Tinker RK3288 - use tinker-rk3288 configuration
+   - MiQi RK3288 - use miqi-rk3288 configuration
    - PopMetal RK3288 - use popmetal-rk3288 configuration
    - Radxa Rock 2 - use rock2 configuration
+   - Tinker RK3288 - use tinker-rk3288 configuration
 
 Two RK3036 board are supported:
 
@@ -147,6 +148,32 @@ For evb_rk3036 board:
 Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, the
       debug uart must be disabled
 
+
+Booting from an SD card on RK3188
+=================================
+
+For rk3188 boards the general storage onto the card stays the same as
+described above, but the image creation needs a bit more care.
+
+The bootrom of rk3188 expects to find a small 1kb loader which returns
+control to the bootrom, after which it will load the real loader, which
+can then be up to 29kb in size and does the regular ddr init.
+
+Additionally the rk3188 requires everything the bootrom loads to be
+rc4-encrypted. Except for the very first stage the bootrom always reads
+and decodes 2kb pages, so files should be sized accordingly.
+
+# copy tpl, pad to 1020 bytes and append spl
+cat tpl/u-boot-tpl.bin > tplspl.bin
+truncate -s 1020 tplspl.bin
+cat spl/u-boot-spl.bin >> tplspl.bin
+tools/mkimage -n rk3188 -T rksd -d tplspl.bin out
+
+# truncate, encode and append u-boot.bin
+truncate -s %2048 u-boot.bin
+cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 7C4E0304550509072D2C7B38170D1711' >> out
+
+
 Using fastboot on rk3288
 ========================
 - Write GPT partition layout to mmc device which fastboot want to use it to
diff --git a/doc/README.ti-secure b/doc/README.ti-secure
index 9b0fbf9..4b5380c 100644
--- a/doc/README.ti-secure
+++ b/doc/README.ti-secure
@@ -133,6 +133,26 @@ Booting of U-Boot SPL
 	u-boot-spl_HS_X-LOADER - boot image for all other flash memories
 		including QSPI and NOR flash
 
+	Invoking the script for Keystone2 Secure Devices
+	=============================================
+
+	create-boot-image.sh \
+		<UNUSED> <INPUT_FILE> <OUTPUT_FILE> <UNUSED>
+
+	<UNUSED> is currently ignored and reserved for future use.
+
+	<INPUT_FILE> is the full path and filename of the public world boot
+	loader binary file (only u-boot.bin is currently supported on
+	Keystone2 devices, u-boot-spl.bin is not currently supported).
+
+	<OUTPUT_FILE> is the full path and filename of the final secure image.
+	The output binary images should be used in place of the standard
+	non-secure binary images (see the platform-specific user's guides
+	and releases notes for how the non-secure images are typically used)
+	u-boot_HS_MLO - signed and encrypted boot image that can be used to
+		boot from all media. Secure boot from SPI NOR flash is not
+		currently supported.
+
 Booting of Primary U-Boot (u-boot.img)
 ======================================
 
diff --git a/doc/device-tree-bindings/chosen.txt b/doc/device-tree-bindings/chosen.txt
index bf9a30a..5625d21 100644
--- a/doc/device-tree-bindings/chosen.txt
+++ b/doc/device-tree-bindings/chosen.txt
@@ -41,3 +41,25 @@ Example
 		reg = <0xf00 0x10>;
 	};
 };
+
+u-boot,spl-boot-order property
+------------------------------
+
+In a system using an SPL stage and having multiple boot sources
+(e.g. SPI NOR flash, on-board eMMC and a removable SD-card), the boot
+device may be probed by reading the image and verifying an image
+signature.
+
+If the SPL is configured through the device-tree, the boot-order can
+be configured with the spl-boot-order property under the /chosen node.
+Each list element of the property should specify a device to be probed
+in the order they are listed: references (i.e. implicit paths), a full
+path or an alias is expected for each entry.
+
+Example
+-------
+/ {
+	chosen {
+		u-boot,spl-boot-order = &sdmmc, "/sdhci@fe330000";
+	};
+};
diff --git a/doc/device-tree-bindings/config.txt b/doc/device-tree-bindings/config.txt
new file mode 100644
index 0000000..5640bae
--- /dev/null
+++ b/doc/device-tree-bindings/config.txt
@@ -0,0 +1,22 @@
+The /config node (Configuration Options)
+----------------------------------------
+
+A number of run-time configuration options are provided in the /config node
+of the control device tree. You can access these using fdtdec_get_config_int(),
+fdtdec_get_config_bool() and fdtdec_get_config_string().
+
+Available options are:
+
+silent-console
+	If present and non-zero, the console is silenced by default on boot.
+
+no-keyboard
+	Tells U-Boot not to expect an attached keyboard with a VGA console
+
+u-boot,efi-partition-entries-offset
+	If present, this provides an offset (in bytes, from the start of a
+	device) that should be skipped over before the partition entries.
+	This is used by the EFI/GPT partition implementation when a device
+	is formatted.
+
+	This setting will override any values configured via Kconfig.
diff --git a/doc/device-tree-bindings/net/fixed-link.txt b/doc/device-tree-bindings/net/fixed-link.txt
new file mode 100644
index 0000000..5829bd8
--- /dev/null
+++ b/doc/device-tree-bindings/net/fixed-link.txt
@@ -0,0 +1,30 @@
+Fixed link Device Tree binding
+------------------------------
+
+Some Ethernet MACs have a "fixed link", and are not connected to a
+normal MDIO-managed PHY device. For those situations, a Device Tree
+binding allows to describe a "fixed link".
+
+Such a fixed link situation is described by creating a 'fixed-link'
+sub-node of the Ethernet MAC device node, with the following
+properties:
+
+* 'speed' (integer, mandatory), to indicate the link speed. Accepted
+  values are 10, 100 and 1000
+* 'full-duplex' (boolean, optional), to indicate that full duplex is
+  used. When absent, half duplex is assumed.
+* 'pause' (boolean, optional), to indicate that pause should be
+  enabled.
+* 'asym-pause' (boolean, optional), to indicate that asym_pause should
+  be enabled.
+
+Examples:
+
+ethernet@0 {
+	...
+	fixed-link {
+	      speed = <1000>;
+	      full-duplex;
+	};
+	...
+};
diff --git a/doc/device-tree-bindings/pci/armada8k-pcie.txt b/doc/device-tree-bindings/pci/armada8k-pcie.txt
new file mode 100644
index 0000000..7230f10
--- /dev/null
+++ b/doc/device-tree-bindings/pci/armada8k-pcie.txt
@@ -0,0 +1,49 @@
+Armada-8K PCIe DT details:
+==========================
+
+Armada-8k uses synopsis designware PCIe controller.
+
+Required properties:
+- compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie".
+- reg: base addresses and lengths of the pcie control and global control registers.
+ "ctrl" registers points to the global control registers, while the "config" space
+ points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below.
+- interrupt-map-mask and interrupt-map, standard PCI properties to
+  define the mapping of the PCIe interface to interrupt numbers.
+- All other definitions as per generic PCI bindings
+See Linux kernel documentation:
+"Documentation/devicetree/bindings/pci/designware-pcie.txt"
+
+Optional properties:
+PHY support is still not supported for armada-8k, once it will, the following parameters can be used:
+- phys		    : phandle to phy node associated with pcie controller.
+- phy-names	    : must be "pcie-phy"
+- marvell,reset-gpio :  specifies a gpio that needs to be activated for plug-in
+			card reset signal release.
+Example:
+
+cpm_pcie0: pcie@f2600000 {
+	compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+	reg = <0 0xf2600000 0 0x10000>,
+	      <0 0xf6f00000 0 0x80000>;
+	reg-names = "ctrl", "config";
+	#address-cells = <3>;
+	#size-cells = <2>;
+	#interrupt-cells = <1>;
+	device_type = "pci";
+	dma-coherent;
+
+	bus-range = <0 0xff>;
+	ranges =
+		/* downstream I/O */
+		<0x81000000 0 0xf9000000 0  0xf9000000 0 0x10000
+		/* non-prefetchable memory */
+		0x82000000 0 0xf6000000 0  0xf6000000 0 0xf00000>;
+	interrupt-map-mask = <0 0 0 0>;
+	interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+	num-lanes = <1>;
+	clocks = <&cpm_syscon0 1 13>;
+	marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>;
+	status = "disabled";
+};
diff --git a/doc/device-tree-bindings/timer/arc_timer.txt b/doc/device-tree-bindings/timer/arc_timer.txt
new file mode 100644
index 0000000..5493b21
--- /dev/null
+++ b/doc/device-tree-bindings/timer/arc_timer.txt
@@ -0,0 +1,24 @@
+ARC Timer
+
+Required properties:
+
+- compatible : should be "snps,arc-timer".
+- reg : Specifies timer ID, could be either 0 or 1.
+- clocks : Specifies clocks that drives the counter.
+
+Examples:
+
+timer@0 {
+	compatible = "snps,arc-timer";
+	clocks = <&core_clk>;
+	reg = <0>;
+};
+
+timer@1 {
+	compatible = "snps,arc-timer";
+	clocks = <&core_clk>;
+	reg = <1>;
+};
+
+NOTE: if you specify both timers, clocks always should be the same
+as each timer is driven by the same core clock.
diff --git a/doc/device-tree-bindings/usb/marvell.xhci-usb.txt b/doc/device-tree-bindings/usb/marvell.xhci-usb.txt
new file mode 100644
index 0000000..e042d1b
--- /dev/null
+++ b/doc/device-tree-bindings/usb/marvell.xhci-usb.txt
@@ -0,0 +1,28 @@
+Marvell SOC USB controllers
+
+This controller is integrated in Armada 3700/8K.
+It uses the same properties as a generic XHCI host controller
+
+Required properties :
+ - compatible: should be one or more of:
+   - "marvell,armada3700-xhci", "generic-xhci" for Armada 37xx SoCs
+   - "marvell,armada-8k-xhci", "generic-xhci" for Armada A8K SoCs
+ - reg: should contain address and length of the standard XHCI
+   register set for the device.
+ - interrupts: one XHCI interrupt should be described here.
+
+Optional properties:
+ - clocks: phandle to system controller clock driving this unit
+ - vbus-supply : If present, specifies the fixed regulator to be turned on
+   for providing power to the USB VBUS rail.
+
+Example:
+	cpm_usb3_0: usb3@500000 {
+		compatible = "marvell,armada-8k-xhci",
+			     "generic-xhci";
+		reg = <0x500000 0x4000>;
+		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cpm_syscon0 1 22>;
+		vbus-supply = <&reg_usb3h0_vbus>;
+		status = "disabled";
+	};
diff --git a/doc/driver-model/fdt-fixup.txt b/doc/driver-model/fdt-fixup.txt
new file mode 100644
index 0000000..70344bd
--- /dev/null
+++ b/doc/driver-model/fdt-fixup.txt
@@ -0,0 +1,132 @@
+Pre-relocation device tree manipulation
+=======================================
+
+Contents:
+
+1. Purpose
+2. Implementation
+3. Example
+4. Work to be done
+
+1. Purpose
+----------
+
+In certain markets, it is beneficial for manufacturers of embedded devices to
+offer certain ranges of products, where the functionality of the devices within
+one series either don't differ greatly from another, or can be thought of as
+"extensions" of each other, where one device only differs from another in the
+addition of a small number of features (e.g. an additional output connector).
+
+To realize this in hardware, one method is to have a motherboard, and several
+possible daughter boards that can be attached to this mother board. Different
+daughter boards then either offer the slightly different functionality, or the
+addition of the daughter board to the device realizes the "extension" of
+functionality to the device described previously.
+
+For the software, we obviously want to reuse components for all these
+variations of the device. This means that the software somehow needs to cope
+with the situation that certain ICs may or may not be present on any given
+system, depending on which daughter boards are connected to the motherboard.
+
+In the Linux kernel, one possible solution to this problem is to employ the
+device tree overlay mechanism: There exists one "base" device tree, which
+features only the components guaranteed to exist in all varieties of the
+device. At the start of the kernel, the presence and type of the daughter
+boards is then detected, and the corresponding device tree overlays are applied
+to support the components on the daughter boards.
+
+Note that the components present on every variety of the board must, of course,
+provide a way to find out if and which daughter boards are installed for this
+mechanism to work.
+
+In the U-Boot boot loader, support for device tree overlays has recently been
+integrated, and is used on some boards to alter the device tree that is later
+passed to Linux. But since U-Boot's driver model, which is device tree-based as
+well, is being used in more and more drivers, the same problem of altering the
+device tree starts cropping up in U-Boot itself as well.
+
+An additional problem with the device tree in U-Boot is that it is read-only,
+and the current mechanisms don't allow easy manipulation of the device tree
+after the driver model has been initialized. While migrating to a live device
+tree (at least after the relocation) would greatly simplify the solution of
+this problem, it is a non-negligible task to implement it, an a interim
+solution is needed to address the problem at least in the medium-term.
+
+Hence, we propose a solution to this problem by offering a board-specific
+call-back function, which is passed a writeable pointer to the device tree.
+This function is called before the device tree is relocated, and specifically
+before the main U-Boot's driver model is instantiated, hence the main U-Boot
+"sees" all modifications to the device tree made in this function. Furthermore,
+we have the pre-relocation driver model at our disposal at this stage, which
+means that we can query the hardware for the existence and variety of the
+components easily.
+
+2. Implementation
+-----------------
+
+To take advantage of the pre-relocation device tree manipulation mechanism,
+boards have to implement the function board_fix_fdt, which has the following
+signature:
+
+int board_fix_fdt (void *rw_fdt_blob)
+
+The passed-in void pointer is a writeable pointer to the device tree, which can
+be used to manipulate the device tree using e.g. functions from
+include/fdt_support.h. The return value should either be 0 in case of
+successful execution of the device tree manipulation or something else for a
+failure. Note that returning a non-null value from the function will
+unrecoverably halt the boot process, as with any function from init_sequence_f
+(in common/board_f.c).
+
+Furthermore, the Kconfig option OF_BOARD_FIXUP has to be set for the function
+to be called:
+
+Device Tree Control
+-> [*] Board-specific manipulation of Device Tree
+
++----------------------------------------------------------+
+| WARNING: The actual manipulation of the device tree has  |
+| to be the _last_ set of operations in board_fix_fdt!     |
+| Since the pre-relocation driver model does not adapt to  |
+| changes made to the device tree either, its references   |
+| into the device tree will be invalid after manipulating  |
+| it, and unpredictable behavior might occur when          |
+| functions that rely on them are executed!                |
++----------------------------------------------------------+
+
+Hence, the recommended layout of the board_fixup_fdt call-back function is the
+following:
+
+int board_fix_fdt(void *rw_fdt_blob)
+{
+	/* Collect information about device's hardware and store them in e.g.
+	   local variables */
+
+	/* Do device tree manipulation using the values previously collected */
+
+	/* Return 0 on successful manipulation and non-zero otherwise */
+}
+
+If this convention is kept, both an "additive" approach, meaning that nodes for
+detected components are added to the device tree, as well as a "subtractive"
+approach, meaning that nodes for absent components are removed from the tree,
+as well as a combination of both approaches should work.
+
+3. Example
+----------
+
+The controlcenterdc board (board/gdsys/a38x/controlcenterdc.c) features a
+board_fix_fdt function, in which six GPIO expanders (which might be present or
+not, since they are on daughter boards) on a I2C bus are queried for, and
+subsequently deactivated in the device tree if they are not present.
+
+Note that the dm_i2c_simple_probe function does not use the device tree, hence
+it is safe to call it after the tree has already been manipulated.
+
+4. Work to be done
+------------------
+
+* The application of device tree overlay should be possible in board_fixup_fdt,
+  but has not been tested at this stage.
+
+2017-01-06, Mario Six <mario.six@gdsys.cc>
diff --git a/drivers/Makefile b/drivers/Makefile
index 34c55bf..5d8baa5 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_$(SPL_)DM)		+= core/
+obj-$(CONFIG_$(SPL_TPL_)DM)	+= core/
 obj-$(CONFIG_$(SPL_)CLK)	+= clk/
 obj-$(CONFIG_$(SPL_)LED)	+= led/
 obj-$(CONFIG_$(SPL_)PINCTRL)	+= pinctrl/
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index 38cb938..af3c35f 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -530,7 +530,7 @@ int blk_unbind_all(int if_type)
 		struct blk_desc *desc = dev_get_uclass_platdata(dev);
 
 		if (desc->if_type == if_type) {
-			ret = device_remove(dev);
+			ret = device_remove(dev, DM_REMOVE_NORMAL);
 			if (ret)
 				return ret;
 			ret = device_unbind(dev);
diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
index 36c2ff3..34d1c63 100644
--- a/drivers/block/sandbox.c
+++ b/drivers/block/sandbox.c
@@ -98,7 +98,7 @@ int host_dev_bind(int devnum, char *filename)
 	/* Remove and unbind the old device, if any */
 	ret = blk_get_device(IF_TYPE_HOST, devnum, &dev);
 	if (ret == 0) {
-		ret = device_remove(dev);
+		ret = device_remove(dev, DM_REMOVE_NORMAL);
 		if (ret)
 			return ret;
 		ret = device_unbind(dev);
diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile
index 6f1c419..ed9659a 100644
--- a/drivers/bootcount/Makefile
+++ b/drivers/bootcount/Makefile
@@ -4,7 +4,6 @@
 
 obj-y				+= bootcount.o
 obj-$(CONFIG_AT91SAM9XE)	+= bootcount_at91.o
-obj-$(CONFIG_BLACKFIN)		+= bootcount_blackfin.o
 obj-$(CONFIG_SOC_DA8XX)		+= bootcount_davinci.o
 obj-$(CONFIG_BOOTCOUNT_AM33XX)	+= bootcount_davinci.o
 obj-$(CONFIG_BOOTCOUNT_RAM)	+= bootcount_ram.o
diff --git a/drivers/bootcount/bootcount_blackfin.c b/drivers/bootcount/bootcount_blackfin.c
deleted file mode 100644
index 6cf6dd5..0000000
--- a/drivers/bootcount/bootcount_blackfin.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * functions for handling bootcount support
- *
- * Copyright (c) 2010 Analog Devices Inc.
- *
- * Licensed under the 2-clause BSD.
- */
-
-/* This version uses one 32bit storage and combines the magic/count */
-
-#include <common.h>
-
-/* We abuse the EVT0 MMR for bootcount storage by default */
-#ifndef CONFIG_SYS_BOOTCOUNT_ADDR
-# define CONFIG_SYS_BOOTCOUNT_ADDR EVT0
-#endif
-
-#define MAGIC_MASK 0xffff0000
-#define COUNT_MASK 0x0000ffff
-
-void bootcount_store(ulong cnt)
-{
-	ulong magic = (BOOTCOUNT_MAGIC & MAGIC_MASK) | (cnt & COUNT_MASK);
-	bfin_write32(CONFIG_SYS_BOOTCOUNT_ADDR, magic);
-}
-
-ulong bootcount_load(void)
-{
-	ulong magic = bfin_read32(CONFIG_SYS_BOOTCOUNT_ADDR);
-	if ((magic & MAGIC_MASK) == (BOOTCOUNT_MAGIC & MAGIC_MASK))
-		return magic & COUNT_MASK;
-	else
-		return 0;
-}
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index 459649f..d36cf8f 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -168,6 +168,65 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf,
 	return 0;
 }
 
+static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf,
+			      unsigned int hz, bool has_bwadj)
+{
+	static const struct pll_div apll_cfg[] = {
+		{.nf = 50, .nr = 1, .no = 2},
+		{.nf = 67, .nr = 1, .no = 1},
+	};
+	int div_core_peri, div_aclk_core, cfg;
+
+	/*
+	 * We support two possible frequencies, the safe 600MHz
+	 * which will work with default pmic settings and will
+	 * be set in SPL to get away from the 24MHz default and
+	 * the maximum of 1.6Ghz, which boards can set if they
+	 * were able to get pmic support for it.
+	 */
+	switch (hz) {
+	case APLL_SAFE_HZ:
+		cfg = 0;
+		div_core_peri = 1;
+		div_aclk_core = 3;
+		break;
+	case APLL_HZ:
+		cfg = 1;
+		div_core_peri = 2;
+		div_aclk_core = 3;
+		break;
+	default:
+		debug("Unsupported ARMCLK frequency");
+		return -EINVAL;
+	}
+
+	/* pll enter slow-mode */
+	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
+		     APLL_MODE_SLOW << APLL_MODE_SHIFT);
+
+	rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj);
+
+	/* waiting for pll lock */
+	while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
+		udelay(1);
+
+	/* Set divider for peripherals attached to the cpu core. */
+	rk_clrsetreg(&cru->cru_clksel_con[0],
+		CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
+		div_core_peri << CORE_PERI_DIV_SHIFT);
+
+	/* set up dependent divisor for aclk_core */
+	rk_clrsetreg(&cru->cru_clksel_con[1],
+		CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT,
+		div_aclk_core << CORE_ACLK_DIV_SHIFT);
+
+	/* PLL enter normal-mode */
+	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
+		     APLL_MODE_NORMAL << APLL_MODE_SHIFT);
+
+	return hz;
+}
+
 /* Get pll rate by id */
 static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru,
 				   enum rk_clk_id clk_id)
@@ -435,6 +494,10 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
 	ulong new_rate;
 
 	switch (clk->id) {
+	case PLL_APLL:
+		new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate,
+					       priv->has_bwadj);
+		break;
 	case CLK_DDR:
 		new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate,
 					       priv->has_bwadj);
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 922ce7e..ff3cc37 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -47,9 +47,12 @@ struct pll_div {
 	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
 	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
 
+#if defined(CONFIG_SPL_BUILD)
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
+#else
 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
+#endif
 
 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
@@ -664,7 +667,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
 
 	if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
 			== CLK_EMMC_PLL_SEL_24M)
-		return DIV_TO_RATE(24*1024*1024, div);
+		return DIV_TO_RATE(24*1000*1000, div);
 	else
 		return DIV_TO_RATE(GPLL_HZ, div);
 }
@@ -682,7 +685,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
 
 		if (src_clk_div > 127) {
 			/* use 24MHz source for 400KHz clock */
-			src_clk_div = 24*1024*1024 / set_rate;
+			src_clk_div = 24*1000*1000 / set_rate;
 			rk_clrsetreg(&cru->clksel_con[16],
 				     CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 				     CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
@@ -799,6 +802,10 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 	case SCLK_EMMC:
 		ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
 		break;
+	case SCLK_MAC:
+		/* nothing to do, as this is an external clock */
+		ret = rate;
+		break;
 	case SCLK_I2C1:
 	case SCLK_I2C2:
 	case SCLK_I2C3:
@@ -1009,7 +1016,9 @@ static void pmuclk_init(struct rk3399_pmucru *pmucru)
 
 static int rk3399_pmuclk_probe(struct udevice *dev)
 {
+#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
 	struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
+#endif
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 8749561..405e9ad 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -21,6 +21,20 @@ config SPL_DM
 	  and devices in SPL, so 1KB should be enable. See
 	  CONFIG_SYS_MALLOC_F_LEN for more details on how to enable it.
 
+config TPL_DM
+	bool "Enable Driver Model for TPL"
+	depends on DM && TPL
+	help
+	  Enable driver model in TPL. You will need to provide a
+	  suitable malloc() implementation. If you are not using the
+	  full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
+	  consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
+	  must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
+	  In most cases driver model will only allocate a few uclasses
+	  and devices in SPL, so 1KB should be enough. See
+	  CONFIG_SYS_MALLOC_F_LEN for more details on how to enable it.
+	  Disable this for very small implementations.
+
 config DM_WARN
 	bool "Enable warnings in driver model"
 	depends on DM
diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
index a7f77b4..cc0043b 100644
--- a/drivers/core/device-remove.c
+++ b/drivers/core/device-remove.c
@@ -46,9 +46,10 @@ static int device_chld_unbind(struct udevice *dev)
 /**
  * device_chld_remove() - Stop all device's children
  * @dev:	The device whose children are to be removed
+ * @pre_os_remove: Flag, if this functions is called in the pre-OS stage
  * @return 0 on success, -ve on error
  */
-static int device_chld_remove(struct udevice *dev)
+static int device_chld_remove(struct udevice *dev, uint flags)
 {
 	struct udevice *pos, *n;
 	int ret;
@@ -56,7 +57,7 @@ static int device_chld_remove(struct udevice *dev)
 	assert(dev);
 
 	list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) {
-		ret = device_remove(pos);
+		ret = device_remove(pos, flags);
 		if (ret)
 			return ret;
 	}
@@ -151,7 +152,7 @@ void device_free(struct udevice *dev)
 	devres_release_probe(dev);
 }
 
-int device_remove(struct udevice *dev)
+int device_remove(struct udevice *dev, uint flags)
 {
 	const struct driver *drv;
 	int ret;
@@ -169,11 +170,17 @@ int device_remove(struct udevice *dev)
 	if (ret)
 		return ret;
 
-	ret = device_chld_remove(dev);
+	ret = device_chld_remove(dev, flags);
 	if (ret)
 		goto err;
 
-	if (drv->remove) {
+	/*
+	 * Remove the device if called with the "normal" remove flag set,
+	 * or if the remove flag matches any of the drivers remove flags
+	 */
+	if (drv->remove &&
+	    ((flags & DM_REMOVE_NORMAL) ||
+	     (flags & (drv->flags & DM_FLAG_ACTIVE_DMA)))) {
 		ret = drv->remove(dev);
 		if (ret)
 			goto err_remove;
@@ -187,10 +194,13 @@ int device_remove(struct udevice *dev)
 		}
 	}
 
-	device_free(dev);
+	if ((flags & DM_REMOVE_NORMAL) ||
+	    (flags & (drv->flags & DM_FLAG_ACTIVE_DMA))) {
+		device_free(dev);
 
-	dev->seq = -1;
-	dev->flags &= ~DM_FLAG_ACTIVATED;
+		dev->seq = -1;
+		dev->flags &= ~DM_FLAG_ACTIVATED;
+	}
 
 	return ret;
 
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 70fcfc2..e1b0ebf 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -378,7 +378,7 @@ int device_probe(struct udevice *dev)
 
 	return 0;
 fail_uclass:
-	if (device_remove(dev)) {
+	if (device_remove(dev, DM_REMOVE_NORMAL)) {
 		dm_warn("%s: Device '%s' failed to remove on error path\n",
 			__func__, dev->name);
 	}
diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index 833cd78..3bec3df 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -70,6 +70,7 @@ int regmap_init_mem(struct udevice *dev, struct regmap **mapp)
 	int addr_len, size_len, both_len;
 	int parent;
 	int len;
+	int index;
 
 	parent = dev_of_offset(dev->parent);
 	addr_len = fdt_address_cells(blob, parent);
@@ -86,13 +87,14 @@ int regmap_init_mem(struct udevice *dev, struct regmap **mapp)
 	if (!map)
 		return -ENOMEM;
 
-	map->base = fdtdec_get_number(cell, addr_len);
-
-	for (range = map->range; count > 0;
-	     count--, cell += both_len, range++) {
-		range->start = fdtdec_get_number(cell, addr_len);
-		range->size = fdtdec_get_number(cell + addr_len, size_len);
+	for (range = map->range, index = 0; count > 0;
+	     count--, cell += both_len, range++, index++) {
+		fdt_size_t sz;
+		range->start = fdtdec_get_addr_size_fixed(blob, dev->of_offset,
+				"reg", index, addr_len, size_len, &sz, true);
+		range->size = sz;
 	}
+	map->base = map->range[0].start;
 
 	*mapp = map;
 
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 93ab568..42679d0 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -44,8 +44,10 @@ struct udevice *dm_root(void)
 void dm_fixup_for_gd_move(struct global_data *new_gd)
 {
 	/* The sentinel node has moved, so update things that point to it */
-	new_gd->uclass_root.next->prev = &new_gd->uclass_root;
-	new_gd->uclass_root.prev->next = &new_gd->uclass_root;
+	if (gd->dm_root) {
+		new_gd->uclass_root.next->prev = &new_gd->uclass_root;
+		new_gd->uclass_root.prev->next = &new_gd->uclass_root;
+	}
 }
 
 fdt_addr_t dm_get_translation_offset(void)
@@ -176,12 +178,21 @@ int dm_init(void)
 
 int dm_uninit(void)
 {
-	device_remove(dm_root());
+	device_remove(dm_root(), DM_REMOVE_NORMAL);
 	device_unbind(dm_root());
 
 	return 0;
 }
 
+#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
+int dm_remove_devices_flags(uint flags)
+{
+	device_remove(dm_root(), flags);
+
+	return 0;
+}
+#endif
+
 int dm_scan_platdata(bool pre_reloc_only)
 {
 	int ret;
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 7de3706..d94d43a 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -116,7 +116,7 @@ int uclass_destroy(struct uclass *uc)
 	while (!list_empty(&uc->dev_head)) {
 		dev = list_first_entry(&uc->dev_head, struct udevice,
 				       uclass_node);
-		ret = device_remove(dev);
+		ret = device_remove(dev, DM_REMOVE_NORMAL);
 		if (ret)
 			return ret;
 		ret = device_unbind(dev);
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 159c22e..d0a7b3f 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -15,6 +15,8 @@
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
  * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
@@ -784,7 +786,7 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 		print_size(total_memory, " of memory\n");
 		printf("       This U-Boot only supports < 4G of DDR\n");
 		printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
-		printf("       "); /* re-align to match init_func_ram print */
+		printf("       "); /* re-align to match init_dram print */
 		total_memory = CONFIG_MAX_MEM_MAPPED;
 	}
 #endif
@@ -794,7 +796,7 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 
 /*
  * fsl_ddr_sdram(void) -- this is the main function to be
- * called by initdram() in the board file.
+ * called by dram_init() in the board file.
  *
  * It returns amount of memory configured in bytes.
  */
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 8ac7aaf..4e9afc1 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -49,6 +49,20 @@ config I2C_CROS_EC_LDO
 	avoid duplicating the logic in the TPS65090 regulator driver for
 	enabling/disabling an LDO.
 
+config I2C_SET_DEFAULT_BUS_NUM
+	bool "Set default I2C bus number"
+	depends on DM_I2C
+	help
+	  Set default number of I2C bus to be accessed. This option provides
+	  behaviour similar to old (i.e. pre DM) I2C bus driver.
+
+config I2C_DEFAULT_BUS_NUMBER
+	hex "I2C default bus number"
+	depends on I2C_SET_DEFAULT_BUS_NUM
+	default 0x0
+	help
+	  Number of default I2C bus to use
+
 config DM_I2C_GPIO
 	bool "Enable Driver Model for software emulated I2C bus driver"
 	depends on DM_I2C && DM_GPIO
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 446af22..4872c1d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
 
 obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o
 obj-$(CONFIG_I2C_MV) += mv_i2c.o
-obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
 obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
 obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
 obj-$(CONFIG_SYS_I2C) += i2c_core.o
diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 16b1aba..19769da 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -39,50 +39,6 @@ struct i2c_bus_hose i2c_bus[CONFIG_SYS_NUM_I2C_BUSES] =
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void i2c_reloc_fixup(void)
-{
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
-	struct i2c_adapter *i2c_adap_p = ll_entry_start(struct i2c_adapter,
-						i2c);
-	struct i2c_adapter *tmp = i2c_adap_p;
-	int max = ll_entry_count(struct i2c_adapter, i2c);
-	int		i;
-	unsigned long	addr;
-
-	if (gd->reloc_off == 0)
-		return;
-
-	for (i = 0; i < max; i++) {
-		/* i2c_init() */
-		addr = (unsigned long)i2c_adap_p->init;
-		addr += gd->reloc_off;
-		i2c_adap_p->init = (void *)addr;
-		/* i2c_probe() */
-		addr = (unsigned long)i2c_adap_p->probe;
-		addr += gd->reloc_off;
-		i2c_adap_p->probe = (void *)addr;
-		/* i2c_read() */
-		addr = (unsigned long)i2c_adap_p->read;
-		addr += gd->reloc_off;
-		i2c_adap_p->read = (void *)addr;
-		/* i2c_write() */
-		addr = (unsigned long)i2c_adap_p->write;
-		addr += gd->reloc_off;
-		i2c_adap_p->write = (void *)addr;
-		/* i2c_set_bus_speed() */
-		addr = (unsigned long)i2c_adap_p->set_bus_speed;
-		addr += gd->reloc_off;
-		i2c_adap_p->set_bus_speed = (void *)addr;
-		/* name */
-		addr = (unsigned long)i2c_adap_p->name;
-		addr += gd->reloc_off;
-		i2c_adap_p->name = (char *)addr;
-		tmp++;
-		i2c_adap_p = tmp;
-	}
-#endif
-}
-
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
 /*
  * i2c_mux_set()
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index b0167ab..661d031 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -5,9 +5,6 @@
  * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
  *
  * SPDX-License-Identifier:	GPL-2.0+
- *
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
  */
 
 #include <common.h>
@@ -15,6 +12,9 @@
 #include <i2c.h>
 #include <linux/errno.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/i2c.h>
+#include <dm.h>
+#include <mapmem.h>
 
 /*
  * Provide default speed and slave if target did not
@@ -28,25 +28,6 @@
 #define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
 #endif
 
-/* i2c register set */
-struct lpc32xx_i2c_registers {
-	union {
-		u32 rx;
-		u32 tx;
-	};
-	u32 stat;
-	u32 ctrl;
-	u32 clk_hi;
-	u32 clk_lo;
-	u32 adr;
-	u32 rxfl;
-	u32 txfl;
-	u32 rxb;
-	u32 txb;
-	u32 stx;
-	u32 stxfl;
-};
-
 /* TX register fields */
 #define LPC32XX_I2C_TX_START		0x00000100
 #define LPC32XX_I2C_TX_STOP		0x00000200
@@ -61,15 +42,17 @@ struct lpc32xx_i2c_registers {
 #define LPC32XX_I2C_STAT_NAI		0x00000004
 #define LPC32XX_I2C_STAT_TDI		0x00000001
 
-static struct lpc32xx_i2c_registers *lpc32xx_i2c[] = {
-	(struct lpc32xx_i2c_registers *)I2C1_BASE,
-	(struct lpc32xx_i2c_registers *)I2C2_BASE,
-	(struct lpc32xx_i2c_registers *)(USB_BASE + 0x300)
+#ifndef CONFIG_DM_I2C
+static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
+	(struct lpc32xx_i2c_base *)I2C1_BASE,
+	(struct lpc32xx_i2c_base *)I2C2_BASE,
+	(struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
 };
+#endif
 
 /* Set I2C bus speed */
-static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
-			unsigned int speed)
+static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
+					unsigned int speed, unsigned int chip)
 {
 	int half_period;
 
@@ -77,7 +60,7 @@ static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
 		return -EINVAL;
 
 	/* OTG I2C clock source and CLK registers are different */
-	if (adap->hwadapnr == 2) {
+	if (chip == 2) {
 		half_period = (get_periph_clk_rate() / speed) / 2;
 		if (half_period > 0xFF)
 			return -EINVAL;
@@ -87,38 +70,35 @@ static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
 			return -EINVAL;
 	}
 
-	writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_hi);
-	writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_lo);
+	writel(half_period, &base->clk_hi);
+	writel(half_period, &base->clk_lo);
 	return 0;
 }
 
 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
-static void _i2c_init(struct i2c_adapter *adap,
-	int requested_speed, int slaveadd)
+static void __i2c_init(struct lpc32xx_i2c_base *base,
+		       int requested_speed, int slaveadd, unsigned int chip)
 {
-	struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
-
 	/* soft reset (auto-clears) */
-	writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
+	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
 	/* set HI and LO periods for half of the default speed */
-	lpc32xx_i2c_set_bus_speed(adap, requested_speed);
+	__i2c_set_bus_speed(base, requested_speed, chip);
 }
 
 /* I2C probe called by cmd_i2c when doing 'i2c probe'. */
-static int lpc32xx_i2c_probe(struct i2c_adapter *adap, u8 dev)
+static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
 {
-	struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
 	int stat;
 
 	/* Soft-reset the controller */
-	writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
-	while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
+	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
+	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
 		;
 	/* Addre slave for write with start before and stop after */
 	writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
-	       &i2c->tx);
+	       &base->tx);
 	/* wait for end of transation */
-	while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
+	while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 		;
 	/* was there no acknowledge? */
 	return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
@@ -128,20 +108,19 @@ static int lpc32xx_i2c_probe(struct i2c_adapter *adap, u8 dev)
  * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
  * Begin write, send address byte(s), begin read, receive data bytes, end.
  */
-static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
-			 int alen, u8 *data, int length)
+static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
+		      int alen, u8 *data, int length)
 {
-	struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
 	int stat, wlen;
 
 	/* Soft-reset the controller */
-	writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
-	while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
+	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
+	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
 		;
 	/* do we need to write an address at all? */
 	if (alen) {
 		/* Address slave in write mode */
-		writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
+		writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
 		/* write address bytes */
 		while (alen--) {
 			/* compute address byte + stop for the last one */
@@ -149,44 +128,44 @@ static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 			if (!alen)
 				a |= LPC32XX_I2C_TX_STOP;
 			/* Send address byte */
-			writel(a, &i2c->tx);
+			writel(a, &base->tx);
 		}
 		/* wait for end of transation */
-		while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
+		while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 			;
 		/* clear end-of-transaction flag */
-		writel(1, &i2c->stat);
+		writel(1, &base->stat);
 	}
 	/* do we have to read data at all? */
 	if (length) {
 		/* Address slave in read mode */
-		writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
+		writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
 		wlen = length;
 		/* get data */
 		while (length | wlen) {
 			/* read status for TFF and RFE */
-			stat = readl(&i2c->stat);
+			stat = readl(&base->stat);
 			/* must we, can we write a trigger byte? */
 			if ((wlen > 0)
 			   & (!(stat & LPC32XX_I2C_STAT_TFF))) {
 				wlen--;
 				/* write trigger byte + stop if last */
 				writel(wlen ? 0 :
-				LPC32XX_I2C_TX_STOP, &i2c->tx);
+				LPC32XX_I2C_TX_STOP, &base->tx);
 			}
 			/* must we, can we read a data byte? */
 			if ((length > 0)
 			   & (!(stat & LPC32XX_I2C_STAT_RFE))) {
 				length--;
 				/* read byte */
-				*(data++) = readl(&i2c->rx);
+				*(data++) = readl(&base->rx);
 			}
 		}
 		/* wait for end of transation */
-		while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
+		while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 			;
 		/* clear end-of-transaction flag */
-		writel(1, &i2c->stat);
+		writel(1, &base->stat);
 	}
 	/* success */
 	return 0;
@@ -196,38 +175,37 @@ static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
  * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
  * Begin write, send address byte(s), send data bytes, end.
  */
-static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
-			  int alen, u8 *data, int length)
+static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
+		       int alen, u8 *data, int length)
 {
-	struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
 	int stat;
 
 	/* Soft-reset the controller */
-	writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
-	while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
+	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
+	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
 		;
 	/* do we need to write anything at all? */
 	if (alen | length)
 		/* Address slave in write mode */
-		writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
+		writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
 	else
 		return 0;
 	/* write address bytes */
 	while (alen) {
 		/* wait for transmit fifo not full */
-		stat = readl(&i2c->stat);
+		stat = readl(&base->stat);
 		if (!(stat & LPC32XX_I2C_STAT_TFF)) {
 			alen--;
 			int a = (addr >> (8 * alen)) & 0xff;
 			if (!(alen | length))
 				a |= LPC32XX_I2C_TX_STOP;
 			/* Send address byte */
-			writel(a, &i2c->tx);
+			writel(a, &base->tx);
 		}
 	}
 	while (length) {
 		/* wait for transmit fifo not full */
-		stat = readl(&i2c->stat);
+		stat = readl(&base->stat);
 		if (!(stat & LPC32XX_I2C_STAT_TFF)) {
 			/* compute data byte, add stop if length==0 */
 			length--;
@@ -235,34 +213,146 @@ static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 			if (!length)
 				d |= LPC32XX_I2C_TX_STOP;
 			/* Send data byte */
-			writel(d, &i2c->tx);
+			writel(d, &base->tx);
 		}
 	}
 	/* wait for end of transation */
-	while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
+	while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 		;
 	/* clear end-of-transaction flag */
-	writel(1, &i2c->stat);
+	writel(1, &base->stat);
 	return 0;
 }
 
-U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, _i2c_init, lpc32xx_i2c_probe,
+#ifndef CONFIG_DM_I2C
+static void lpc32xx_i2c_init(struct i2c_adapter *adap,
+			     int requested_speed, int slaveadd)
+{
+	__i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
+		   adap->hwadapnr);
+}
+
+static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
+{
+	return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
+}
+
+static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
+			    int alen, u8 *data, int length)
+{
+	return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
+			 alen, data, length);
+}
+
+static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
+			     int alen, u8 *data, int length)
+{
+	return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
+			  alen, data, length);
+}
+
+static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
+					      unsigned int speed)
+{
+	return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
+				  adap->hwadapnr);
+}
+
+U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
 			 lpc32xx_i2c_read, lpc32xx_i2c_write,
 			 lpc32xx_i2c_set_bus_speed,
 			 CONFIG_SYS_I2C_LPC32XX_SPEED,
 			 CONFIG_SYS_I2C_LPC32XX_SLAVE,
 			 0)
 
-U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, _i2c_init, lpc32xx_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
 			 lpc32xx_i2c_read, lpc32xx_i2c_write,
 			 lpc32xx_i2c_set_bus_speed,
 			 CONFIG_SYS_I2C_LPC32XX_SPEED,
 			 CONFIG_SYS_I2C_LPC32XX_SLAVE,
 			 1)
 
-U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, _i2c_init, NULL,
+U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
 			 lpc32xx_i2c_read, lpc32xx_i2c_write,
 			 lpc32xx_i2c_set_bus_speed,
 			 100000,
 			 0,
 			 2)
+#else /* CONFIG_DM_I2C */
+static int lpc32xx_i2c_probe(struct udevice *bus)
+{
+	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+	bus->seq = dev->index;
+
+	__i2c_init(dev->base, dev->speed, 0, dev->index);
+	return 0;
+}
+
+static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
+				  u32 chip_flags)
+{
+	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+	return __i2c_probe_chip(dev->base, chip_addr);
+}
+
+static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
+		int nmsgs)
+{
+	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+	struct i2c_msg *dmsg, *omsg, dummy;
+	uint i = 0, address = 0;
+
+	memset(&dummy, 0, sizeof(struct i2c_msg));
+
+	/* We expect either two messages (one with an offset and one with the
+	 * actual data) or one message (just data)
+	 */
+	if (nmsgs > 2 || nmsgs == 0) {
+		debug("%s: Only one or two messages are supported.", __func__);
+		return -1;
+	}
+
+	omsg = nmsgs == 1 ? &dummy : msg;
+	dmsg = nmsgs == 1 ? msg : msg + 1;
+
+	/* the address is expected to be a uint, not a array. */
+	address = omsg->buf[0];
+	for (i = 1; i < omsg->len; i++)
+		address = (address << 8) + omsg->buf[i];
+
+	if (dmsg->flags & I2C_M_RD)
+		return __i2c_read(dev->base, dmsg->addr, address,
+				  omsg->len, dmsg->buf, dmsg->len);
+	else
+		return __i2c_write(dev->base, dmsg->addr, address,
+				   omsg->len, dmsg->buf, dmsg->len);
+}
+
+static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+	return __i2c_set_bus_speed(dev->base, speed, dev->index);
+}
+
+static int lpc32xx_i2c_reset(struct udevice *bus)
+{
+	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+
+	__i2c_init(dev->base, dev->speed, 0, dev->index);
+	return 0;
+}
+
+static const struct dm_i2c_ops lpc32xx_i2c_ops = {
+	.xfer          = lpc32xx_i2c_xfer,
+	.probe_chip    = lpc32xx_i2c_probe_chip,
+	.deblock       = lpc32xx_i2c_reset,
+	.set_bus_speed = lpc32xx_i2c_set_bus_speed,
+};
+
+U_BOOT_DRIVER(i2c_lpc32xx) = {
+	.id                   = UCLASS_I2C,
+	.name                 = "i2c_lpc32xx",
+	.probe                = lpc32xx_i2c_probe,
+	.ops                  = &lpc32xx_i2c_ops,
+};
+#endif /* CONFIG_DM_I2C */
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 0006343..26996e9 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -64,36 +64,52 @@ struct omap_i2c {
 
 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
 {
-	unsigned int sampleclk, prescaler;
-	int fsscll, fssclh;
+	unsigned long internal_clk = 0, fclk;
+	unsigned int prescaler;
 
-	speed <<= 1;
-	prescaler = 0;
 	/*
-	 * some divisors may cause a precission loss, but shouldn't
-	 * be a big thing, because i2c_clk is then allready very slow.
+	 * This method is only called for Standard and Fast Mode speeds
+	 *
+	 * For some TI SoCs it is explicitly written in TRM (e,g, SPRUHZ6G,
+	 * page 5685, Table 24-7)
+	 * that the internal I2C clock (after prescaler) should be between
+	 * 7-12 MHz (at least for Fast Mode (FS)).
+	 *
+	 * Such approach is used in v4.9 Linux kernel in:
+	 * ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function).
 	 */
-	while (prescaler <= 0xFF) {
-		sampleclk = I2C_IP_CLK / (prescaler+1);
 
-		fsscll = sampleclk / speed;
-		fssclh = fsscll;
-		fsscll -= I2C_FASTSPEED_SCLL_TRIM;
-		fssclh -= I2C_FASTSPEED_SCLH_TRIM;
-
-		if (((fsscll > 0) && (fssclh > 0)) &&
-		    ((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) &&
-		    (fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM)))) {
-			if (pscl)
-				*pscl = fsscll;
-			if (psch)
-				*psch = fssclh;
-
-			return prescaler;
-		}
-		prescaler++;
+	speed /= 1000; /* convert speed to kHz */
+
+	if (speed > 100)
+		internal_clk = 9600;
+	else
+		internal_clk = 4000;
+
+	fclk = I2C_IP_CLK / 1000;
+	prescaler = fclk / internal_clk;
+	prescaler = prescaler - 1;
+
+	if (speed > 100) {
+		unsigned long scl;
+
+		/* Fast mode */
+		scl = internal_clk / speed;
+		*pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM;
+		*psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM;
+	} else {
+		/* Standard mode */
+		*pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM;
+		*psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM;
 	}
-	return -1;
+
+	debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch: 0x%x\n",
+	      __func__, speed, prescaler, *pscl, *psch);
+
+	if (*pscl <= 0 || *psch <= 0 || prescaler <= 0)
+		return -EINVAL;
+
+	return prescaler;
 }
 
 /*
diff --git a/drivers/i2c/omap24xx_i2c.h b/drivers/i2c/omap24xx_i2c.h
index 3dae295..8a4ae98 100644
--- a/drivers/i2c/omap24xx_i2c.h
+++ b/drivers/i2c/omap24xx_i2c.h
@@ -121,17 +121,17 @@
  * scll_trim = 7
  * sclh_trim = 5
  *
- * The linux 2.6.30 kernel uses
- * scll_trim = 6
- * sclh_trim = 6
+ * The linux 4.9 kernel uses
+ * scll_trim = 7
+ * sclh_trim = 5
  *
  * These are the trim values for standard and fast speed
  */
 #ifndef I2C_FASTSPEED_SCLL_TRIM
-#define I2C_FASTSPEED_SCLL_TRIM		6
+#define I2C_FASTSPEED_SCLL_TRIM		7
 #endif
 #ifndef I2C_FASTSPEED_SCLH_TRIM
-#define I2C_FASTSPEED_SCLH_TRIM		6
+#define I2C_FASTSPEED_SCLH_TRIM		5
 #endif
 
 /* These are the trim values for high speed */
diff --git a/drivers/i2c/pca9564_i2c.c b/drivers/i2c/pca9564_i2c.c
deleted file mode 100644
index 4ed0923..0000000
--- a/drivers/i2c/pca9564_i2c.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * File:         drivers/i2c/pca9564.c
- * Based on:     drivers/i2c/s3c44b0_i2c.c
- * Author:
- *
- * Created:      2009-06-23
- * Description:  PCA9564 i2c bridge driver
- *
- * Modified:
- *               Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
- *
- * Bugs:
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <pca9564.h>
-#include <asm/io.h>
-
-#define PCA_STA			(CONFIG_PCA9564_BASE + 0)
-#define PCA_TO			(CONFIG_PCA9564_BASE + 0)
-#define PCA_DAT			(CONFIG_PCA9564_BASE + (1 << 2))
-#define PCA_ADR			(CONFIG_PCA9564_BASE + (2 << 2))
-#define PCA_CON			(CONFIG_PCA9564_BASE + (3 << 2))
-
-static unsigned char pca_read_reg(unsigned int reg)
-{
-	return readb((void *)reg);
-}
-
-static void pca_write_reg(unsigned int reg, unsigned char value)
-{
-	writeb(value, (void *)reg);
-}
-
-static int pca_wait_busy(void)
-{
-	unsigned int timeout = 10000;
-
-	while (!(pca_read_reg(PCA_CON) & PCA_CON_SI) && --timeout)
-		udelay(1);
-
-	if (timeout == 0)
-		debug("I2C timeout!\n");
-
-	debug("CON = 0x%02x, STA = 0x%02x\n", pca_read_reg(PCA_CON),
-	       pca_read_reg(PCA_STA));
-
-	return timeout ? 0 : 1;
-}
-
-/*=====================================================================*/
-/*                         Public Functions                            */
-/*=====================================================================*/
-
-/*-----------------------------------------------------------------------
- * Initialization
- */
-void i2c_init(int speed, int slaveaddr)
-{
-	pca_write_reg(PCA_CON, PCA_CON_ENSIO | speed);
-}
-
-/*
- * Probe the given I2C chip address.  Returns 0 if a chip responded,
- * not 0 on failure.
- */
-
-int i2c_probe(uchar chip)
-{
-	unsigned char res;
-
-	pca_write_reg(PCA_CON, PCA_CON_STA | PCA_CON_ENSIO);
-	pca_wait_busy();
-
-	pca_write_reg(PCA_CON, PCA_CON_STA | PCA_CON_ENSIO);
-
-	pca_write_reg(PCA_DAT, (chip << 1) | 1);
-	res = pca_wait_busy();
-
-	if ((res == 0) && (pca_read_reg(PCA_STA) == 0x48))
-		res = 1;
-
-	pca_write_reg(PCA_CON, PCA_CON_STO | PCA_CON_ENSIO);
-
-	return res;
-}
-
-/*
- * Read/Write interface:
- *   chip:    I2C chip address, range 0..127
- *   addr:    Memory (register) address within the chip
- *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
- *              memories, 0 for register type devices with only one
- *              register)
- *   buffer:  Where to read/write the data
- *   len:     How many bytes to read/write
- *
- *   Returns: 0 on success, not 0 on failure
- */
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
-	int i;
-
-	pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA);
-	pca_wait_busy();
-
-	pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
-	pca_write_reg(PCA_DAT, (chip << 1));
-	pca_wait_busy();
-	pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
-	if (alen > 0) {
-		pca_write_reg(PCA_DAT, addr);
-		pca_wait_busy();
-		pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-	}
-
-	pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STO);
-
-	udelay(500);
-
-	pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA);
-	pca_wait_busy();
-	pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
-	pca_write_reg(PCA_DAT, (chip << 1) | 1);
-	pca_wait_busy();
-
-	for (i = 0; i < len; ++i) {
-		if (i == len - 1)
-			pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-		else
-			pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_AA);
-
-		pca_wait_busy();
-		buffer[i] = pca_read_reg(PCA_DAT);
-
-	}
-
-	pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STO);
-
-	return 0;
-}
-
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
-	int i;
-
-	pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA);
-	pca_wait_busy();
-	pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
-	pca_write_reg(PCA_DAT, chip << 1);
-	pca_wait_busy();
-	pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
-	if (alen > 0) {
-		pca_write_reg(PCA_DAT, addr);
-		pca_wait_busy();
-		pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-	}
-
-	for (i = 0; i < len; ++i) {
-		pca_write_reg(PCA_DAT, buffer[i]);
-		pca_wait_busy();
-		pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-	}
-
-	pca_write_reg(PCA_CON, PCA_CON_STO | PCA_CON_ENSIO);
-
-	return 0;
-}
diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c
index 7c701cb..af925ce 100644
--- a/drivers/i2c/rk_i2c.c
+++ b/drivers/i2c/rk_i2c.c
@@ -380,6 +380,8 @@ static const struct dm_i2c_ops rockchip_i2c_ops = {
 };
 
 static const struct udevice_id rockchip_i2c_ids[] = {
+	{ .compatible = "rockchip,rk3066-i2c" },
+	{ .compatible = "rockchip,rk3188-i2c" },
 	{ .compatible = "rockchip,rk3288-i2c" },
 	{ }
 };
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index ddef59a..560391f 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -122,6 +122,14 @@ config MMC_MXS
 
 	  If unsure, say N.
 
+config MMC_PCI
+	bool "Support for MMC controllers on PCI"
+	help
+	  This selects PCI-based MMC controllers.
+	  If you have an MMC controller on a PCI bus, say Y here.
+
+	  If unsure, say N.
+
 config MMC_OMAP_HS
 	bool "TI OMAP High Speed Multimedia Card Interface support"
 	help
@@ -317,6 +325,20 @@ config MMC_SDHCI_XENON
 
 	  If unsure, say N.
 
+config MMC_SDHCI_TANGIER
+	bool "Tangier SDHCI controller support"
+	depends on DM_MMC && BLK
+	depends on MMC_SDHCI
+	help
+	  This selects support for SDHCI controller on Tanginer
+	  SoC. Note that this controller does not sit on PCI bus and,
+	  hence, cannot be enumerated by standard PCI means.
+
+	  If you're using an Intel Tangier SoC (available on Intel
+	  Edison board), say Y here.
+
+	  If unsure, say N.
+
 config MMC_SDHCI_TEGRA
 	bool "SDHCI platform support for the Tegra SD/MMC Controller"
 	depends on TEGRA
@@ -345,6 +367,17 @@ config MMC_SUNXI
 
 endif
 
+config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
+	bool "Disable external clock loopback"
+	depends on MMC_SDHCI_TEGRA && TEGRA124
+	help
+	  Disable the external clock loopback and use the internal one on SDMMC3
+	  as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
+	  being set to 0xfffd according to the TRM.
+
+	  TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
+	  approach once proper kernel integration made it mainline.
+
 endmenu
 
 config SYS_FSL_ERRATUM_ESDHC111
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 6a488f1..6a26a52 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -34,7 +34,7 @@ obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o
 obj-$(CONFIG_MMC_OMAP_HS)		+= omap_hsmmc.o
 obj-$(CONFIG_MMC_MXC)			+= mxcmmc.o
 obj-$(CONFIG_MMC_MXS)			+= mxsmmc.o
-obj-$(CONFIG_X86) += pci_mmc.o
+obj-$(CONFIG_MMC_PCI)			+= pci_mmc.o
 obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
 obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
 obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
@@ -62,6 +62,7 @@ obj-$(CONFIG_MMC_SDHCI_ROCKCHIP)	+= rockchip_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_S5P)		+= s5p_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_SPEAR)		+= spear_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_STI) 		+= sti_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_TANGIER)		+= tangier_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_TEGRA)		+= tegra_mmc.o
 obj-$(CONFIG_MMC_SDHCI_XENON)		+= xenon_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_ZYNQ)		+= zynq_sdhci.o
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 5bb446b..9c07871 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -232,7 +232,7 @@ int mmc_unbind(struct udevice *dev)
 
 	device_find_first_child(dev, &bdev);
 	if (bdev) {
-		device_remove(bdev);
+		device_remove(bdev, DM_REMOVE_NORMAL);
 		device_unbind(bdev);
 	}
 
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 3648950..72fc177 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1111,7 +1111,6 @@ static int mmc_startup(struct mmc *mmc)
 	struct mmc_cmd cmd;
 	ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
 	ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
-	int timeout = 1000;
 	bool has_parts = false;
 	bool part_completed;
 	struct blk_desc *bdesc;
@@ -1167,9 +1166,6 @@ static int mmc_startup(struct mmc *mmc)
 
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 
-	/* Waiting for the ready status */
-	mmc_send_status(mmc, timeout);
-
 	if (err)
 		return err;
 
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 7ed5328..83dda09 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -56,9 +56,16 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SYSCTL_SRC	(1 << 25)
 #define SYSCTL_SRD	(1 << 26)
 
+struct omap_hsmmc_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
 struct omap_hsmmc_data {
 	struct hsmmc *base_addr;
+#ifndef CONFIG_DM_MMC
 	struct mmc_config cfg;
+#endif
 #ifdef OMAP_HSMMC_USE_GPIO
 #ifdef CONFIG_DM_MMC
 	struct gpio_desc cd_gpio;	/* Change Detect GPIO */
@@ -78,7 +85,25 @@ static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 			unsigned int siz);
 
-#if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC)
+static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
+{
+#ifdef CONFIG_DM_MMC
+	return dev_get_priv(mmc->dev);
+#else
+	return (struct omap_hsmmc_data *)mmc->priv;
+#endif
+}
+static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
+{
+#ifdef CONFIG_DM_MMC
+	struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
+	return &plat->cfg;
+#else
+	return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
+#endif
+}
+
+ #if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC)
 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 {
 	int ret;
@@ -102,6 +127,7 @@ static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 static unsigned char mmc_board_init(struct mmc *mmc)
 {
 #if defined(CONFIG_OMAP34XX)
+	struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 	t2_t *t2_base = (t2_t *)T2_BASE;
 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 	u32 pbias_lite;
@@ -142,7 +168,7 @@ static unsigned char mmc_board_init(struct mmc *mmc)
 		&t2_base->devconf1);
 
 	/* Change from default of 52MHz to 26MHz if necessary */
-	if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
+	if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 		writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 			&t2_base->ctl_prog_io1);
 
@@ -157,7 +183,7 @@ static unsigned char mmc_board_init(struct mmc *mmc)
 
 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
 	/* PBIAS config needed for MMC1 only */
-	if (mmc->block_dev.devnum == 0)
+	if (mmc_get_blk_desc(mmc)->devnum == 0)
 		vmmc_pbias_config(LDO_VOLT_3V0);
 #endif
 
@@ -194,12 +220,13 @@ void mmc_init_stream(struct hsmmc *mmc_base)
 
 static int omap_hsmmc_init_setup(struct mmc *mmc)
 {
+	struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 	struct hsmmc *mmc_base;
 	unsigned int reg_val;
 	unsigned int dsor;
 	ulong start;
 
-	mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
+	mmc_base = priv->base_addr;
 	mmc_board_init(mmc);
 
 	writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
@@ -304,11 +331,12 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 			struct mmc_data *data)
 {
+	struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 	struct hsmmc *mmc_base;
 	unsigned int flags, mmc_stat;
 	ulong start;
 
-	mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
+	mmc_base = priv->base_addr;
 	start = get_timer(0);
 	while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 		if (get_timer(0) - start > MAX_RETRY_MS) {
@@ -533,11 +561,12 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 
 static int omap_hsmmc_set_ios(struct mmc *mmc)
 {
+	struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 	struct hsmmc *mmc_base;
 	unsigned int dsor = 0;
 	ulong start;
 
-	mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
+	mmc_base = priv->base_addr;
 	/* configue bus width */
 	switch (mmc->bus_width) {
 	case 8:
@@ -591,7 +620,7 @@ static int omap_hsmmc_set_ios(struct mmc *mmc)
 #ifdef CONFIG_DM_MMC
 static int omap_hsmmc_getcd(struct mmc *mmc)
 {
-	struct omap_hsmmc_data *priv = mmc->priv;
+	struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 	int value;
 
 	value = dm_gpio_get_value(&priv->cd_gpio);
@@ -606,7 +635,7 @@ static int omap_hsmmc_getcd(struct mmc *mmc)
 
 static int omap_hsmmc_getwp(struct mmc *mmc)
 {
-	struct omap_hsmmc_data *priv = mmc->priv;
+	struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 	int value;
 
 	value = dm_gpio_get_value(&priv->wp_gpio);
@@ -618,11 +647,11 @@ static int omap_hsmmc_getwp(struct mmc *mmc)
 #else
 static int omap_hsmmc_getcd(struct mmc *mmc)
 {
-	struct omap_hsmmc_data *priv_data = mmc->priv;
+	struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 	int cd_gpio;
 
 	/* if no CD return as 1 */
-	cd_gpio = priv_data->cd_gpio;
+	cd_gpio = priv->cd_gpio;
 	if (cd_gpio < 0)
 		return 1;
 
@@ -632,11 +661,11 @@ static int omap_hsmmc_getcd(struct mmc *mmc)
 
 static int omap_hsmmc_getwp(struct mmc *mmc)
 {
-	struct omap_hsmmc_data *priv_data = mmc->priv;
+	struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 	int wp_gpio;
 
 	/* if no WP return as 0 */
-	wp_gpio = priv_data->wp_gpio;
+	wp_gpio = priv->wp_gpio;
 	if (wp_gpio < 0)
 		return 0;
 
@@ -661,23 +690,23 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 		int wp_gpio)
 {
 	struct mmc *mmc;
-	struct omap_hsmmc_data *priv_data;
+	struct omap_hsmmc_data *priv;
 	struct mmc_config *cfg;
 	uint host_caps_val;
 
-	priv_data = malloc(sizeof(*priv_data));
-	if (priv_data == NULL)
+	priv = malloc(sizeof(*priv));
+	if (priv == NULL)
 		return -1;
 
 	host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
 	switch (dev_index) {
 	case 0:
-		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
+		priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
 		break;
 #ifdef OMAP_HSMMC2_BASE
 	case 1:
-		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
+		priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 	defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
 	defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
@@ -689,7 +718,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 #endif
 #ifdef OMAP_HSMMC3_BASE
 	case 2:
-		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
+		priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
 		/* Enable 8-bit interface for eMMC on DRA7XX */
 		host_caps_val |= MMC_MODE_8BIT;
@@ -697,16 +726,16 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 		break;
 #endif
 	default:
-		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
+		priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
 		return 1;
 	}
 #ifdef OMAP_HSMMC_USE_GPIO
 	/* on error gpio values are set to -1, which is what we want */
-	priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
-	priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
+	priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
+	priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
 #endif
 
-	cfg = &priv_data->cfg;
+	cfg = &priv->cfg;
 
 	cfg->name = "OMAP SD/MMC";
 	cfg->ops = &omap_hsmmc_ops;
@@ -737,7 +766,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 		cfg->b_max = 1;
 #endif
-	mmc = mmc_create(cfg, priv_data);
+	mmc = mmc_create(cfg, priv);
 	if (mmc == NULL)
 		return -1;
 
@@ -747,14 +776,14 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
 {
 	struct omap_hsmmc_data *priv = dev_get_priv(dev);
+	struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
+	struct mmc_config *cfg = &plat->cfg;
 	const void *fdt = gd->fdt_blob;
 	int node = dev_of_offset(dev);
-	struct mmc_config *cfg;
 	int val;
 
 	priv->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *),
 				      MAP_NOCACHE);
-	cfg = &priv->cfg;
 
 	cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
 	val = fdtdec_get_int(fdt, node, "bus-width", -1);
@@ -786,20 +815,33 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
 	return 0;
 }
 
+#ifdef CONFIG_BLK
+
+static int omap_hsmmc_bind(struct udevice *dev)
+{
+	struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
+
+	return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+#endif
 static int omap_hsmmc_probe(struct udevice *dev)
 {
+	struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 	struct omap_hsmmc_data *priv = dev_get_priv(dev);
-	struct mmc_config *cfg;
+	struct mmc_config *cfg = &plat->cfg;
 	struct mmc *mmc;
 
-	cfg = &priv->cfg;
 	cfg->name = "OMAP SD/MMC";
 	cfg->ops = &omap_hsmmc_ops;
 
+#ifdef CONFIG_BLK
+	mmc = &plat->mmc;
+#else
 	mmc = mmc_create(cfg, priv);
 	if (mmc == NULL)
 		return -1;
+#endif
 
 #ifdef OMAP_HSMMC_USE_GPIO
 	gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
@@ -824,7 +866,11 @@ U_BOOT_DRIVER(omap_hsmmc) = {
 	.id	= UCLASS_MMC,
 	.of_match = omap_hsmmc_ids,
 	.ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
+#ifdef CONFIG_BLK
+	.bind = omap_hsmmc_bind,
+#endif
 	.probe	= omap_hsmmc_probe,
 	.priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
+	.platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
 };
 #endif
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 93cefd8..c94d58d 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -242,8 +242,10 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 
 	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 #ifdef CONFIG_MMC_SDHCI_SDMA
-	trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
-	flush_cache(start_addr, trans_bytes);
+	if (data != 0) {
+		trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
+		flush_cache(start_addr, trans_bytes);
+	}
 #endif
 	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 	start = get_timer(0);
diff --git a/drivers/mmc/tangier_sdhci.c b/drivers/mmc/tangier_sdhci.c
new file mode 100644
index 0000000..77b18e7
--- /dev/null
+++ b/drivers/mmc/tangier_sdhci.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <sdhci.h>
+
+#define SDHCI_TANGIER_FMAX	200000000
+#define SDHCI_TANGIER_FMIN	400000
+
+struct sdhci_tangier_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+	void __iomem *ioaddr;
+};
+
+static int sdhci_tangier_bind(struct udevice *dev)
+{
+	struct sdhci_tangier_plat *plat = dev_get_platdata(dev);
+
+	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static int sdhci_tangier_probe(struct udevice *dev)
+{
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	struct sdhci_tangier_plat *plat = dev_get_platdata(dev);
+	struct sdhci_host *host = dev_get_priv(dev);
+	fdt_addr_t base;
+	int ret;
+
+	base = dev_get_addr(dev);
+	if (base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	plat->ioaddr = devm_ioremap(dev, base, SZ_1K);
+	if (!plat->ioaddr)
+		return -ENOMEM;
+
+	host->name = dev->name;
+	host->ioaddr = plat->ioaddr;
+	host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
+		       SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD;
+
+	/* MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195 */
+	host->voltages = MMC_VDD_165_195;
+
+	ret = sdhci_setup_cfg(&plat->cfg, host, SDHCI_TANGIER_FMAX,
+			SDHCI_TANGIER_FMIN);
+	if (ret)
+		return ret;
+
+	upriv->mmc = &plat->mmc;
+	host->mmc = &plat->mmc;
+	host->mmc->priv = host;
+
+	return sdhci_probe(dev);
+}
+
+static const struct udevice_id sdhci_tangier_match[] = {
+	{ .compatible = "intel,sdhci-tangier" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sdhci_tangier) = {
+	.name		= "sdhci-tangier",
+	.id		= UCLASS_MMC,
+	.of_match	= sdhci_tangier_match,
+	.bind		= sdhci_tangier_bind,
+	.probe		= sdhci_tangier_probe,
+	.ops		= &sdhci_ops,
+	.priv_auto_alloc_size = sizeof(struct sdhci_host),
+	.platdata_auto_alloc_size = sizeof(struct sdhci_tangier_plat),
+};
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 0df74ef..6c6affb 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -513,6 +513,22 @@ static int tegra_mmc_init(struct mmc *mmc)
 
 	tegra_mmc_reset(priv, mmc);
 
+#if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
+	/*
+	 * Disable the external clock loopback and use the internal one on
+	 * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
+	 * bits being set to 0xfffd according to the TRM.
+	 *
+	 * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
+	 * approach once proper kernel integration made it mainline.
+	 */
+	if (priv->reg == (void *)0x700b0400) {
+		mask = readl(&priv->reg->venmiscctl);
+		mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
+		writel(mask, &priv->reg->venmiscctl);
+	}
+#endif
+
 	priv->version = readw(&priv->reg->hcver);
 	debug("host version = %x\n", priv->version);
 
diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c
index f678110..2a0d8b4 100644
--- a/drivers/mmc/xenon_sdhci.c
+++ b/drivers/mmc/xenon_sdhci.c
@@ -422,7 +422,8 @@ static int xenon_sdhci_probe(struct udevice *dev)
 
 	host->ops = &xenon_sdhci_ops;
 
-	ret = sdhci_setup_cfg(&plat->cfg, host, XENON_MMC_MAX_CLK, 0);
+	host->max_clk = XENON_MMC_MAX_CLK;
+	ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
 	if (ret)
 		return ret;
 
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index a2ea9b1..a7b76f4 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -67,12 +67,29 @@ config NAND_SUNXI
 	bool "Support for NAND on Allwinner SoCs"
 	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 	select SYS_NAND_SELF_INIT
+	select SYS_NAND_U_BOOT_LOCATIONS
 	---help---
 	Enable support for NAND. This option enables the standard and
 	SPL drivers.
 	The SPL driver only supports reading from the NAND using DMA
 	transfers.
 
+if NAND_SUNXI
+
+config NAND_SUNXI_SPL_ECC_STRENGTH
+	int "Allwinner NAND SPL ECC Strength"
+	default 64
+
+config NAND_SUNXI_SPL_ECC_SIZE
+	int "Allwinner NAND SPL ECC Step Size"
+	default 1024
+
+config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
+	int "Allwinner NAND SPL Usable Page Size"
+	default 1024
+
+endif
+
 config NAND_ARASAN
 	bool "Configure Arasan Nand"
 	help
@@ -127,7 +144,7 @@ config SYS_NAND_U_BOOT_LOCATIONS
 
 config SYS_NAND_U_BOOT_OFFS
 	hex "Location in NAND to read U-Boot from"
-	default 0x8000 if NAND_SUNXI
+	default 0x800000 if NAND_SUNXI
 	depends on SYS_NAND_U_BOOT_LOCATIONS
 	help
 	Set the offset from the start of the nand where u-boot should be
diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c
index a8a7a66..5b189a1 100644
--- a/drivers/mtd/nand/am335x_spl_bch.c
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -49,6 +49,13 @@ static int nand_command(int block, int page, uint32_t offs,
 
 	if (cmd == NAND_CMD_RESET) {
 		hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+		/*
+		 * Apply this short delay always to ensure that we do wait
+		 * tWB in any case on any machine.
+		 */
+		ndelay(150);
+
 		while (!this->dev_ready(mtd))
 			;
 		return 0;
@@ -78,23 +85,44 @@ static int nand_command(int block, int page, uint32_t offs,
 
 	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
-	if (cmd == NAND_CMD_READ0) {
-		/* Latch in address */
-		hwctrl(mtd, NAND_CMD_READSTART,
-			   NAND_CTRL_CLE | NAND_CTRL_CHANGE);
-		hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
-		/*
-		 * Wait a while for the data to be ready
-		 */
-		while (!this->dev_ready(mtd))
-			;
-	} else if (cmd == NAND_CMD_RNDOUT) {
+	/*
+	 * Program and erase have their own busy handlers status, sequential
+	 * in and status need no delay.
+	 */
+	switch (cmd) {
+	case NAND_CMD_CACHEDPROG:
+	case NAND_CMD_PAGEPROG:
+	case NAND_CMD_ERASE1:
+	case NAND_CMD_ERASE2:
+	case NAND_CMD_SEQIN:
+	case NAND_CMD_RNDIN:
+	case NAND_CMD_STATUS:
+		return 0;
+
+	case NAND_CMD_RNDOUT:
+		/* No ready / busy check necessary */
 		hwctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
-					NAND_CTRL_CHANGE);
+		       NAND_CTRL_CHANGE);
+		hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+		return 0;
+
+	case NAND_CMD_READ0:
+		/* Latch in address */
+		hwctrl(mtd, NAND_CMD_READSTART,
+		       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 		hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 	}
 
+	/*
+	 * Apply this short delay always to ensure that we do wait tWB in
+	 * any case on any machine.
+	 */
+	ndelay(150);
+
+	while (!this->dev_ready(mtd))
+		;
+
 	return 0;
 }
 
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index 0551241..168bac6 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -131,8 +131,23 @@ static void create_mtd_concat(void)
 }
 #endif
 
+unsigned long nand_size(void)
+{
+	return total_nand_size;
+}
+
 void nand_init(void)
 {
+	static int initialized;
+
+	/*
+	 * Avoid initializing NAND Flash multiple times,
+	 * otherwise it will calculate a wrong total size.
+	 */
+	if (initialized)
+		return;
+	initialized = 1;
+
 #ifdef CONFIG_SYS_NAND_SELF_INIT
 	board_nand_init();
 #else
@@ -142,8 +157,6 @@ void nand_init(void)
 		nand_init_chip(i);
 #endif
 
-	printf("%lu MiB\n", total_nand_size / 1024);
-
 #ifdef CONFIG_SYS_NAND_SELECT_DEVICE
 	/*
 	 * Select the chip in the board/cpu specific driver
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index d9e5fc9..b025001 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -241,7 +241,6 @@ static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
 	chip->write_buf(mtd, (uint8_t *)&word, 2);
 }
 
-#if !defined(CONFIG_BLACKFIN)
 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
 {
 	int i;
@@ -274,7 +273,6 @@ static void iowrite16_rep(void *addr, void *buf, int len)
         for (i = 0; i < len; i++)
                 writew(p[i], addr);
 }
-#endif
 
 /**
  * nand_write_buf - [DEFAULT] write buffer to chip
diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c
index 1ef7366..eed4472 100644
--- a/drivers/mtd/nand/sunxi_nand_spl.c
+++ b/drivers/mtd/nand/sunxi_nand_spl.c
@@ -245,7 +245,7 @@ static int nand_read_page(const struct nfc_config *conf, u32 offs,
 {
 	dma_addr_t dst = (dma_addr_t)dest;
 	int nsectors = len / conf->ecc_size;
-	u16 rand_seed;
+	u16 rand_seed = 0;
 	u32 val;
 	int page;
 
@@ -258,8 +258,9 @@ static int nand_read_page(const struct nfc_config *conf, u32 offs,
 	/* clear ecc status */
 	writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
 
-	/* Choose correct seed */
-	rand_seed = random_seed[page % conf->nseeds];
+	/* Choose correct seed if randomized */
+	if (conf->randomize)
+		rand_seed = random_seed[page % conf->nseeds];
 
 	writel((rand_seed << 16) | (conf->ecc_strength << 12) |
 		(conf->randomize ? NFC_ECC_RANDOM_EN : 0) |
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 1f23c8e..5ca0a71 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -132,7 +132,7 @@ if SPL
 
 config SPL_SPI_SUNXI
 	bool "Support for SPI Flash on Allwinner SoCs in SPL"
-	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_H3 || MACH_SUN50I
+	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
 	---help---
 	Enable support for SPI Flash. This option allows SPL to read from
 	sunxi SPI Flash. It uses the same method as the boot ROM, so does
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 36a50fe..a53f4eb 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -595,7 +595,7 @@ void sandbox_sf_unbind_emul(struct sandbox_state *state, int busnum, int cs)
 	struct udevice *dev;
 
 	dev = state->spi[busnum][cs].emul;
-	device_remove(dev);
+	device_remove(dev, DM_REMOVE_NORMAL);
 	device_unbind(dev);
 	state->spi[busnum][cs].emul = NULL;
 }
diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
index 19de964..8387648 100644
--- a/drivers/mtd/spi/sf-uclass.c
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -46,7 +46,7 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 
 void spi_flash_free(struct spi_flash *flash)
 {
-	device_remove(flash->spi->dev);
+	device_remove(flash->spi->dev, DM_REMOVE_NORMAL);
 }
 
 int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
diff --git a/drivers/mtd/spi/sunxi_spi_spl.c b/drivers/mtd/spi/sunxi_spi_spl.c
index a24c115..852abd4 100644
--- a/drivers/mtd/spi/sunxi_spi_spl.c
+++ b/drivers/mtd/spi/sunxi_spi_spl.c
@@ -185,14 +185,14 @@ static void spi0_deinit(void)
 #define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
 
 static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
-				 u32 spi_ctl_reg,
-				 u32 spi_ctl_xch_bitmask,
-				 u32 spi_fifo_reg,
-				 u32 spi_tx_reg,
-				 u32 spi_rx_reg,
-				 u32 spi_bc_reg,
-				 u32 spi_tc_reg,
-				 u32 spi_bcc_reg)
+				 ulong spi_ctl_reg,
+				 ulong spi_ctl_xch_bitmask,
+				 ulong spi_fifo_reg,
+				 ulong spi_tx_reg,
+				 ulong spi_rx_reg,
+				 ulong spi_bc_reg,
+				 ulong spi_tc_reg,
+				 ulong spi_bcc_reg)
 {
 	writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
 	writel(4, spi_tc_reg);           /* Transfer counter (bytes to send) */
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index 0c82395..cb9ba78 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -3,6 +3,7 @@ menu "UBI support"
 config MTD_UBI
 	bool "Enable UBI - Unsorted block images"
 	select CRC32
+	select RBTREE if ARCH_SUNXI
 	help
 	  UBI is a software layer above MTD layer which admits of LVM-like
 	  logical volumes on top of MTD devices, hides some complexities of
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 70e3661..8aa9279 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -124,12 +124,12 @@ config FEC_MXC
 	  NXP i.MX processors.
 
 config MVPP2
-	bool "Marvell Armada 375 network interface support"
-	depends on ARMADA_375
+	bool "Marvell Armada 375/7K/8K network interface support"
+	depends on ARMADA_375 || ARMADA_8K
 	select PHYLIB
 	help
 	  This driver supports the network interface units in the
-	  Marvell ARMADA 375 SoC.
+	  Marvell ARMADA 375, 7K and 8K SoCs.
 
 config MACB
 	bool "Cadence MACB/GEM Ethernet Interface"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 2493a48..ac7e07b 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -33,7 +33,6 @@ obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
 obj-$(CONFIG_FTGMAC100) += ftgmac100.o
 obj-$(CONFIG_FTMAC110) += ftmac110.o
 obj-$(CONFIG_FTMAC100) += ftmac100.o
-obj-$(CONFIG_GRETH) += greth.o
 obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
 obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
 obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
diff --git a/drivers/net/bcm-sf2-eth-gmac.c b/drivers/net/bcm-sf2-eth-gmac.c
index f2853cf..9ff72fa 100644
--- a/drivers/net/bcm-sf2-eth-gmac.c
+++ b/drivers/net/bcm-sf2-eth-gmac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 Broadcom Corporation.
+ * Copyright 2014-2017 Broadcom.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -28,6 +28,10 @@
 	} \
 }
 
+#define RX_BUF_SIZE_ALIGNED	ALIGN(RX_BUF_SIZE, ARCH_DMA_MINALIGN)
+#define TX_BUF_SIZE_ALIGNED	ALIGN(TX_BUF_SIZE, ARCH_DMA_MINALIGN)
+#define DESCP_SIZE_ALIGNED	ALIGN(sizeof(dma64dd_t), ARCH_DMA_MINALIGN)
+
 static int gmac_disable_dma(struct eth_dma *dma, int dir);
 static int gmac_enable_dma(struct eth_dma *dma, int dir);
 
@@ -114,7 +118,7 @@ static void dma_tx_dump(struct eth_dma *dma)
 	printf("TX Buffers:\n");
 	/* Initialize TX DMA descriptor table */
 	for (i = 0; i < TX_BUF_NUM; i++) {
-		bufp = (uint8_t *)(dma->tx_buf + i * TX_BUF_SIZE);
+		bufp = (uint8_t *)(dma->tx_buf + i * TX_BUF_SIZE_ALIGNED);
 		printf("buf%d:0x%x; ", i, (uint32_t)bufp);
 	}
 	printf("\n");
@@ -145,7 +149,7 @@ static void dma_rx_dump(struct eth_dma *dma)
 
 	printf("RX Buffers:\n");
 	for (i = 0; i < RX_BUF_NUM; i++) {
-		bufp = dma->rx_buf + i * RX_BUF_SIZE;
+		bufp = dma->rx_buf + i * RX_BUF_SIZE_ALIGNED;
 		printf("buf%d:0x%x; ", i, (uint32_t)bufp);
 	}
 	printf("\n");
@@ -163,15 +167,15 @@ static int dma_tx_init(struct eth_dma *dma)
 
 	/* clear descriptor memory */
 	memset((void *)(dma->tx_desc_aligned), 0,
-	       TX_BUF_NUM * sizeof(dma64dd_t));
-	memset(dma->tx_buf, 0, TX_BUF_NUM * TX_BUF_SIZE);
+	       TX_BUF_NUM * DESCP_SIZE_ALIGNED);
+	memset(dma->tx_buf, 0, TX_BUF_NUM * TX_BUF_SIZE_ALIGNED);
 
 	/* Initialize TX DMA descriptor table */
 	for (i = 0; i < TX_BUF_NUM; i++) {
 		descp = (dma64dd_t *)(dma->tx_desc_aligned) + i;
-		bufp = dma->tx_buf + i * TX_BUF_SIZE;
+		bufp = dma->tx_buf + i * TX_BUF_SIZE_ALIGNED;
 		/* clear buffer memory */
-		memset((void *)bufp, 0, TX_BUF_SIZE);
+		memset((void *)bufp, 0, TX_BUF_SIZE_ALIGNED);
 
 		ctrl = 0;
 		/* if last descr set endOfTable */
@@ -187,10 +191,11 @@ static int dma_tx_init(struct eth_dma *dma)
 	descp = dma->tx_desc_aligned;
 	bufp = dma->tx_buf;
 	flush_dcache_range((unsigned long)descp,
-			   (unsigned long)(descp +
-					   sizeof(dma64dd_t) * TX_BUF_NUM));
-	flush_dcache_range((unsigned long)(bufp),
-			   (unsigned long)(bufp + TX_BUF_SIZE * TX_BUF_NUM));
+			   (unsigned long)descp +
+			   DESCP_SIZE_ALIGNED * TX_BUF_NUM);
+	flush_dcache_range((unsigned long)bufp,
+			   (unsigned long)bufp +
+			   TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);
 
 	/* initialize the DMA channel */
 	writel((uint32_t)(dma->tx_desc_aligned), GMAC0_DMA_TX_ADDR_LOW_ADDR);
@@ -215,20 +220,20 @@ static int dma_rx_init(struct eth_dma *dma)
 
 	/* clear descriptor memory */
 	memset((void *)(dma->rx_desc_aligned), 0,
-	       RX_BUF_NUM * sizeof(dma64dd_t));
+	       RX_BUF_NUM * DESCP_SIZE_ALIGNED);
 	/* clear buffer memory */
-	memset(dma->rx_buf, 0, RX_BUF_NUM * RX_BUF_SIZE);
+	memset(dma->rx_buf, 0, RX_BUF_NUM * RX_BUF_SIZE_ALIGNED);
 
 	/* Initialize RX DMA descriptor table */
 	for (i = 0; i < RX_BUF_NUM; i++) {
 		descp = (dma64dd_t *)(dma->rx_desc_aligned) + i;
-		bufp = dma->rx_buf + i * RX_BUF_SIZE;
+		bufp = dma->rx_buf + i * RX_BUF_SIZE_ALIGNED;
 		ctrl = 0;
 		/* if last descr set endOfTable */
 		if (i == (RX_BUF_NUM - 1))
 			ctrl = D64_CTRL1_EOT;
 		descp->ctrl1 = ctrl;
-		descp->ctrl2 = RX_BUF_SIZE;
+		descp->ctrl2 = RX_BUF_SIZE_ALIGNED;
 		descp->addrlow = (uint32_t)bufp;
 		descp->addrhigh = 0;
 
@@ -240,10 +245,11 @@ static int dma_rx_init(struct eth_dma *dma)
 	bufp = dma->rx_buf;
 	/* flush descriptor and buffer */
 	flush_dcache_range((unsigned long)descp,
-			   (unsigned long)(descp +
-					   sizeof(dma64dd_t) * RX_BUF_NUM));
+			   (unsigned long)descp +
+			   DESCP_SIZE_ALIGNED * RX_BUF_NUM);
 	flush_dcache_range((unsigned long)(bufp),
-			   (unsigned long)(bufp + RX_BUF_SIZE * RX_BUF_NUM));
+			   (unsigned long)bufp +
+			   RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);
 
 	/* initailize the DMA channel */
 	writel((uint32_t)descp, GMAC0_DMA_RX_ADDR_LOW_ADDR);
@@ -292,14 +298,12 @@ static int dma_deinit(struct eth_dma *dma)
 
 	free(dma->tx_buf);
 	dma->tx_buf = NULL;
-	free(dma->tx_desc);
-	dma->tx_desc = NULL;
+	free(dma->tx_desc_aligned);
 	dma->tx_desc_aligned = NULL;
 
 	free(dma->rx_buf);
 	dma->rx_buf = NULL;
-	free(dma->rx_desc);
-	dma->rx_desc = NULL;
+	free(dma->rx_desc_aligned);
 	dma->rx_desc_aligned = NULL;
 
 	return 0;
@@ -307,7 +311,7 @@ static int dma_deinit(struct eth_dma *dma)
 
 int gmac_tx_packet(struct eth_dma *dma, void *packet, int length)
 {
-	uint8_t *bufp = dma->tx_buf + dma->cur_tx_index * TX_BUF_SIZE;
+	uint8_t *bufp = dma->tx_buf + dma->cur_tx_index * TX_BUF_SIZE_ALIGNED;
 
 	/* kick off the dma */
 	size_t len = length;
@@ -348,10 +352,11 @@ int gmac_tx_packet(struct eth_dma *dma, void *packet, int length)
 	descp->ctrl2 = ctrl;
 
 	/* flush descriptor and buffer */
-	flush_dcache_range((unsigned long)descp,
-			   (unsigned long)(descp + sizeof(dma64dd_t)));
+	flush_dcache_range((unsigned long)dma->tx_desc_aligned,
+			   (unsigned long)dma->tx_desc_aligned +
+			   DESCP_SIZE_ALIGNED * TX_BUF_NUM);
 	flush_dcache_range((unsigned long)bufp,
-			   (unsigned long)(bufp + TX_BUF_SIZE));
+			   (unsigned long)bufp + TX_BUF_SIZE_ALIGNED);
 
 	/* now update the dma last descriptor */
 	writel(last_desc, GMAC0_DMA_TX_PTR_ADDR);
@@ -426,14 +431,15 @@ int gmac_check_rx_done(struct eth_dma *dma, uint8_t *buf)
 		;
 
 	/* get the packet pointer that corresponds to the rx descriptor */
-	bufp = dma->rx_buf + index * RX_BUF_SIZE;
+	bufp = dma->rx_buf + index * RX_BUF_SIZE_ALIGNED;
 
 	descp = (dma64dd_t *)(dma->rx_desc_aligned) + index;
 	/* flush descriptor and buffer */
-	flush_dcache_range((unsigned long)descp,
-			   (unsigned long)(descp + sizeof(dma64dd_t)));
+	flush_dcache_range((unsigned long)dma->rx_desc_aligned,
+			   (unsigned long)dma->rx_desc_aligned +
+			   DESCP_SIZE_ALIGNED * RX_BUF_NUM);
 	flush_dcache_range((unsigned long)bufp,
-			   (unsigned long)(bufp + RX_BUF_SIZE));
+			   (unsigned long)bufp + RX_BUF_SIZE_ALIGNED);
 
 	buflen = (descp->ctrl2 & D64_CTRL2_BC_MASK);
 
@@ -457,12 +463,13 @@ int gmac_check_rx_done(struct eth_dma *dma, uint8_t *buf)
 	memcpy(buf, datap, rcvlen);
 
 	/* update descriptor that is being added back on ring */
-	descp->ctrl2 = RX_BUF_SIZE;
+	descp->ctrl2 = RX_BUF_SIZE_ALIGNED;
 	descp->addrlow = (uint32_t)bufp;
 	descp->addrhigh = 0;
 	/* flush descriptor */
-	flush_dcache_range((unsigned long)descp,
-			   (unsigned long)(descp + sizeof(dma64dd_t)));
+	flush_dcache_range((unsigned long)dma->rx_desc_aligned,
+			   (unsigned long)dma->rx_desc_aligned +
+			   DESCP_SIZE_ALIGNED * RX_BUF_NUM);
 
 	/* set the lastdscr for the rx ring */
 	writel(((uint32_t)descp) & D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR);
@@ -573,7 +580,7 @@ static int gmac_enable_dma(struct eth_dma *dma, int dir)
 		 * set the lastdscr for the rx ring
 		 */
 		writel(((uint32_t)(dma->rx_desc_aligned) +
-			(RX_BUF_NUM - 1) * RX_BUF_SIZE) &
+			(RX_BUF_NUM - 1) * RX_BUF_SIZE_ALIGNED) &
 		       D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR);
 	}
 
@@ -893,54 +900,52 @@ int gmac_add(struct eth_device *dev)
 	void *tmp;
 
 	/*
-	 * Desc has to be 16-byte aligned ?
-	 * If it is 8-byte aligned by malloc, fail Tx
+	 * Desc has to be 16-byte aligned. But for dcache flush it must be
+	 * aligned to ARCH_DMA_MINALIGN.
 	 */
-	tmp = malloc(sizeof(dma64dd_t) * TX_BUF_NUM + 8);
+	tmp = memalign(ARCH_DMA_MINALIGN, DESCP_SIZE_ALIGNED * TX_BUF_NUM);
 	if (tmp == NULL) {
 		printf("%s: Failed to allocate TX desc Buffer\n", __func__);
 		return -1;
 	}
 
-	dma->tx_desc = (void *)tmp;
-	dma->tx_desc_aligned = (void *)(((uint32_t)tmp) & (~0xf));
+	dma->tx_desc_aligned = (void *)tmp;
 	debug("TX Descriptor Buffer: %p; length: 0x%x\n",
-	      dma->tx_desc_aligned, sizeof(dma64dd_t) * TX_BUF_NUM);
+	      dma->tx_desc_aligned, DESCP_SIZE_ALIGNED * TX_BUF_NUM);
 
-	tmp = malloc(TX_BUF_SIZE * TX_BUF_NUM);
+	tmp = memalign(ARCH_DMA_MINALIGN, TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);
 	if (tmp == NULL) {
 		printf("%s: Failed to allocate TX Data Buffer\n", __func__);
-		free(dma->tx_desc);
+		free(dma->tx_desc_aligned);
 		return -1;
 	}
 	dma->tx_buf = (uint8_t *)tmp;
 	debug("TX Data Buffer: %p; length: 0x%x\n",
-	      dma->tx_buf, TX_BUF_SIZE * TX_BUF_NUM);
+	      dma->tx_buf, TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);
 
-	/* Desc has to be 16-byte aligned ? */
-	tmp = malloc(sizeof(dma64dd_t) * RX_BUF_NUM + 8);
+	/* Desc has to be 16-byte aligned */
+	tmp = memalign(ARCH_DMA_MINALIGN, DESCP_SIZE_ALIGNED * RX_BUF_NUM);
 	if (tmp == NULL) {
 		printf("%s: Failed to allocate RX Descriptor\n", __func__);
-		free(dma->tx_desc);
+		free(dma->tx_desc_aligned);
 		free(dma->tx_buf);
 		return -1;
 	}
-	dma->rx_desc = tmp;
-	dma->rx_desc_aligned = (void *)(((uint32_t)tmp) & (~0xf));
+	dma->rx_desc_aligned = (void *)tmp;
 	debug("RX Descriptor Buffer: %p, length: 0x%x\n",
-	      dma->rx_desc_aligned, sizeof(dma64dd_t) * RX_BUF_NUM);
+	      dma->rx_desc_aligned, DESCP_SIZE_ALIGNED * RX_BUF_NUM);
 
-	tmp = malloc(RX_BUF_SIZE * RX_BUF_NUM);
+	tmp = memalign(ARCH_DMA_MINALIGN, RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);
 	if (tmp == NULL) {
 		printf("%s: Failed to allocate RX Data Buffer\n", __func__);
-		free(dma->tx_desc);
+		free(dma->tx_desc_aligned);
 		free(dma->tx_buf);
-		free(dma->rx_desc);
+		free(dma->rx_desc_aligned);
 		return -1;
 	}
-	dma->rx_buf = tmp;
+	dma->rx_buf = (uint8_t *)tmp;
 	debug("RX Data Buffer: %p; length: 0x%x\n",
-	      dma->rx_buf, RX_BUF_SIZE * RX_BUF_NUM);
+	      dma->rx_buf, RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);
 
 	g_dmactrlflags = 0;
 
diff --git a/drivers/net/bcm-sf2-eth.h b/drivers/net/bcm-sf2-eth.h
index 6104aff..c4e2e01 100644
--- a/drivers/net/bcm-sf2-eth.h
+++ b/drivers/net/bcm-sf2-eth.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 Broadcom Corporation.
+ * Copyright 2014-2017 Broadcom.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -30,8 +30,6 @@ enum {
 struct eth_dma {
 	void *tx_desc_aligned;
 	void *rx_desc_aligned;
-	void *tx_desc;
-	void *rx_desc;
 
 	uint8_t *tx_buf;
 	uint8_t *rx_buf;
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
index 2fe323a..588a84d 100644
--- a/drivers/net/enc28j60.c
+++ b/drivers/net/enc28j60.c
@@ -489,10 +489,6 @@ static void enc_poll(enc_dev_t *enc)
 	u8 eir_reg;
 	u8 pkt_cnt;
 
-#ifdef CONFIG_USE_IRQ
-	/* clear global interrupt enable bit in enc28j60 */
-	enc_bclr(enc, CTL_REG_EIE, ENC_EIE_INTIE);
-#endif
 	(void)enc_r8(enc, CTL_REG_ESTAT);
 	eir_reg = enc_r8(enc, CTL_REG_EIR);
 	if (eir_reg & ENC_EIR_TXIF) {
@@ -520,10 +516,6 @@ static void enc_poll(enc_dev_t *enc)
 		printf("%s: tx error\n", enc->dev->name);
 		enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF);
 	}
-#ifdef CONFIG_USE_IRQ
-	/* set global interrupt enable bit in enc28j60 */
-	enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
-#endif
 }
 
 /*
@@ -693,15 +685,6 @@ static int enc_setup(enc_dev_t *enc)
 	/* Reset PDPXMD-bit => half duplex */
 	enc_phy_write(enc, PHY_REG_PHCON1, 0);
 
-#ifdef CONFIG_USE_IRQ
-	/* enable interrupts */
-	enc_bset(enc, CTL_REG_EIE, ENC_EIE_PKTIE);
-	enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXIE);
-	enc_bset(enc, CTL_REG_EIE, ENC_EIE_RXERIE);
-	enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXERIE);
-	enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
-#endif
-
 	return 0;
 }
 
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index e9b202a..5e2ca76 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -14,7 +14,9 @@
 #include <asm/io.h>
 #include <asm/arch/periph.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
 #include <asm/arch/grf_rk3288.h>
+#include <asm/arch/grf_rk3399.h>
 #include <dm/pinctrl.h>
 #include <dt-bindings/clock/rk3288-cru.h>
 #include "designware.h"
@@ -32,32 +34,45 @@ struct gmac_rockchip_platdata {
 	int rx_delay;
 };
 
+struct rk_gmac_ops {
+	int (*fix_mac_speed)(struct dw_eth_dev *priv);
+	void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
+};
+
+
 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
 {
 	struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+	const void *blob = gd->fdt_blob;
+	int node = dev_of_offset(dev);
+
+	/* Check the new naming-style first... */
+	pdata->tx_delay = fdtdec_get_int(blob, node, "tx_delay", -ENOENT);
+	pdata->rx_delay = fdtdec_get_int(blob, node, "rx_delay", -ENOENT);
 
-	pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-					 "tx-delay", 0x30);
-	pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-					 "rx-delay", 0x10);
+	/* ... and fall back to the old naming style or default, if necessary */
+	if (pdata->tx_delay == -ENOENT)
+		pdata->tx_delay = fdtdec_get_int(blob, node, "tx-delay", 0x30);
+	if (pdata->rx_delay == -ENOENT)
+		pdata->rx_delay = fdtdec_get_int(blob, node, "rx-delay", 0x10);
 
 	return designware_eth_ofdata_to_platdata(dev);
 }
 
-static int gmac_rockchip_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
 	struct rk3288_grf *grf;
 	int clk;
 
 	switch (priv->phydev->speed) {
 	case 10:
-		clk = GMAC_CLK_SEL_2_5M;
+		clk = RK3288_GMAC_CLK_SEL_2_5M;
 		break;
 	case 100:
-		clk = GMAC_CLK_SEL_25M;
+		clk = RK3288_GMAC_CLK_SEL_25M;
 		break;
 	case 1000:
-		clk = GMAC_CLK_SEL_125M;
+		clk = RK3288_GMAC_CLK_SEL_125M;
 		break;
 	default:
 		debug("Unknown phy speed: %d\n", priv->phydev->speed);
@@ -65,17 +80,83 @@ static int gmac_rockchip_fix_mac_speed(struct dw_eth_dev *priv)
 	}
 
 	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	rk_clrsetreg(&grf->soc_con1,
-		     GMAC_CLK_SEL_MASK << GMAC_CLK_SEL_SHIFT,
-		     clk << GMAC_CLK_SEL_SHIFT);
+	rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
+
+	return 0;
+}
+
+static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+	struct rk3399_grf_regs *grf;
+	int clk;
+
+	switch (priv->phydev->speed) {
+	case 10:
+		clk = RK3399_GMAC_CLK_SEL_2_5M;
+		break;
+	case 100:
+		clk = RK3399_GMAC_CLK_SEL_25M;
+		break;
+	case 1000:
+		clk = RK3399_GMAC_CLK_SEL_125M;
+		break;
+	default:
+		debug("Unknown phy speed: %d\n", priv->phydev->speed);
+		return -EINVAL;
+	}
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
 
 	return 0;
 }
 
+static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+	struct rk3288_grf *grf;
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->soc_con1,
+		     RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
+		     RK3288_GMAC_PHY_INTF_SEL_RGMII);
+
+	rk_clrsetreg(&grf->soc_con3,
+		     RK3288_RXCLK_DLY_ENA_GMAC_MASK |
+		     RK3288_TXCLK_DLY_ENA_GMAC_MASK |
+		     RK3288_CLK_RX_DL_CFG_GMAC_MASK |
+		     RK3288_CLK_TX_DL_CFG_GMAC_MASK,
+		     RK3288_RXCLK_DLY_ENA_GMAC_ENABLE |
+		     RK3288_TXCLK_DLY_ENA_GMAC_ENABLE |
+		     pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
+		     pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
+static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+	struct rk3399_grf_regs *grf;
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+	rk_clrsetreg(&grf->soc_con5,
+		     RK3399_GMAC_PHY_INTF_SEL_MASK,
+		     RK3399_GMAC_PHY_INTF_SEL_RGMII);
+
+	rk_clrsetreg(&grf->soc_con6,
+		     RK3399_RXCLK_DLY_ENA_GMAC_MASK |
+		     RK3399_TXCLK_DLY_ENA_GMAC_MASK |
+		     RK3399_CLK_RX_DL_CFG_GMAC_MASK |
+		     RK3399_CLK_TX_DL_CFG_GMAC_MASK,
+		     RK3399_RXCLK_DLY_ENA_GMAC_ENABLE |
+		     RK3399_TXCLK_DLY_ENA_GMAC_ENABLE |
+		     pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
+		     pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
 static int gmac_rockchip_probe(struct udevice *dev)
 {
 	struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
-	struct rk3288_grf *grf;
+	struct rk_gmac_ops *ops =
+		(struct rk_gmac_ops *)dev_get_driver_data(dev);
 	struct clk clk;
 	int ret;
 
@@ -89,21 +170,7 @@ static int gmac_rockchip_probe(struct udevice *dev)
 		return ret;
 
 	/* Set to RGMII mode */
-	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	rk_clrsetreg(&grf->soc_con1,
-		     RMII_MODE_MASK << RMII_MODE_SHIFT |
-		     GMAC_PHY_INTF_SEL_MASK << GMAC_PHY_INTF_SEL_SHIFT,
-		     GMAC_PHY_INTF_SEL_RGMII << GMAC_PHY_INTF_SEL_SHIFT);
-
-	rk_clrsetreg(&grf->soc_con3,
-		     RXCLK_DLY_ENA_GMAC_MASK <<  RXCLK_DLY_ENA_GMAC_SHIFT |
-		     TXCLK_DLY_ENA_GMAC_MASK <<  TXCLK_DLY_ENA_GMAC_SHIFT |
-		     CLK_RX_DL_CFG_GMAC_MASK <<  CLK_RX_DL_CFG_GMAC_SHIFT |
-		     CLK_TX_DL_CFG_GMAC_MASK <<  CLK_TX_DL_CFG_GMAC_SHIFT,
-		     RXCLK_DLY_ENA_GMAC_ENABLE << RXCLK_DLY_ENA_GMAC_SHIFT |
-		     TXCLK_DLY_ENA_GMAC_ENABLE << TXCLK_DLY_ENA_GMAC_SHIFT |
-		     pdata->rx_delay << CLK_RX_DL_CFG_GMAC_SHIFT |
-		     pdata->tx_delay << CLK_TX_DL_CFG_GMAC_SHIFT);
+	ops->set_to_rgmii(pdata);
 
 	return designware_eth_probe(dev);
 }
@@ -112,12 +179,14 @@ static int gmac_rockchip_eth_start(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct dw_eth_dev *priv = dev_get_priv(dev);
+	struct rk_gmac_ops *ops =
+		(struct rk_gmac_ops *)dev_get_driver_data(dev);
 	int ret;
 
 	ret = designware_eth_init(priv, pdata->enetaddr);
 	if (ret)
 		return ret;
-	ret = gmac_rockchip_fix_mac_speed(priv);
+	ret = ops->fix_mac_speed(priv);
 	if (ret)
 		return ret;
 	ret = designware_eth_enable(priv);
@@ -136,8 +205,21 @@ const struct eth_ops gmac_rockchip_eth_ops = {
 	.write_hwaddr		= designware_eth_write_hwaddr,
 };
 
+const struct rk_gmac_ops rk3288_gmac_ops = {
+	.fix_mac_speed = rk3288_gmac_fix_mac_speed,
+	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
+};
+
+const struct rk_gmac_ops rk3399_gmac_ops = {
+	.fix_mac_speed = rk3399_gmac_fix_mac_speed,
+	.set_to_rgmii = rk3399_gmac_set_to_rgmii,
+};
+
 static const struct udevice_id rockchip_gmac_ids[] = {
-	{ .compatible = "rockchip,rk3288-gmac" },
+	{ .compatible = "rockchip,rk3288-gmac",
+	  .data = (ulong)&rk3288_gmac_ops },
+	{ .compatible = "rockchip,rk3399-gmac",
+	  .data = (ulong)&rk3399_gmac_ops },
 	{ }
 };
 
diff --git a/drivers/net/greth.c b/drivers/net/greth.c
deleted file mode 100644
index aa5d711..0000000
--- a/drivers/net/greth.c
+++ /dev/null
@@ -1,677 +0,0 @@
-/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
- *
- * Driver use polling mode (no Interrupt)
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* #define DEBUG */
-
-#include <common.h>
-#include <command.h>
-#include <errno.h>
-#include <net.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <asm/processor.h>
-#include <ambapp.h>
-#include <asm/leon.h>
-
-#include <grlib/greth.h>
-
-/* Default to 3s timeout on autonegotiation */
-#ifndef GRETH_PHY_TIMEOUT_MS
-#define GRETH_PHY_TIMEOUT_MS 3000
-#endif
-
-/* Default to PHY adrress 0 not not specified */
-#ifdef CONFIG_SYS_GRLIB_GRETH_PHYADDR
-#define GRETH_PHY_ADR_DEFAULT CONFIG_SYS_GRLIB_GRETH_PHYADDR
-#else
-#define GRETH_PHY_ADR_DEFAULT 0
-#endif
-
-/* Let board select which GRETH to use as network interface, set
- * this to zero if only one GRETH is available.
- */
-#ifndef CONFIG_SYS_GRLIB_GRETH_INDEX
-#define CONFIG_SYS_GRLIB_GRETH_INDEX 0
-#endif
-
-/* ByPass Cache when reading regs */
-#define GRETH_REGLOAD(addr)		SPARC_NOCACHE_READ(addr)
-/* Write-through cache ==> no bypassing needed on writes */
-#define GRETH_REGSAVE(addr,data) (*(volatile unsigned int *)(addr) = (data))
-#define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data)
-#define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data)
-
-#define GRETH_RXBD_CNT 4
-#define GRETH_TXBD_CNT 1
-
-#define GRETH_RXBUF_SIZE 1540
-#define GRETH_BUF_ALIGN 4
-#define GRETH_RXBUF_EFF_SIZE \
-	( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN )
-
-typedef struct {
-	greth_regs *regs;
-	int irq;
-	struct eth_device *dev;
-
-	/* Hardware info */
-	unsigned char phyaddr;
-	int gbit_mac;
-
-	/* Current operating Mode */
-	int gb;			/* GigaBit */
-	int fd;			/* Full Duplex */
-	int sp;			/* 10/100Mbps speed (1=100,0=10) */
-	int auto_neg;		/* Auto negotiate done */
-
-	unsigned char hwaddr[6];	/* MAC Address */
-
-	/* Descriptors */
-	greth_bd *rxbd_base, *rxbd_max;
-	greth_bd *txbd_base, *txbd_max;
-
-	greth_bd *rxbd_curr;
-
-	/* rx buffers in rx descriptors */
-	void *rxbuf_base;	/* (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */
-
-	/* unused for gbit_mac, temp buffer for sending packets with unligned
-	 * start.
-	 * Pointer to packet allocated with malloc.
-	 */
-	void *txbuf;
-
-	struct {
-		/* rx status */
-		unsigned int rx_packets,
-		    rx_crc_errors, rx_frame_errors, rx_length_errors, rx_errors;
-
-		/* tx stats */
-		unsigned int tx_packets,
-		    tx_latecol_errors,
-		    tx_underrun_errors, tx_limit_errors, tx_errors;
-	} stats;
-} greth_priv;
-
-/* Read MII register 'addr' from core 'regs' */
-static int read_mii(int phyaddr, int regaddr, volatile greth_regs * regs)
-{
-	while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
-	}
-
-	GRETH_REGSAVE(&regs->mdio, ((phyaddr & 0x1F) << 11) | ((regaddr & 0x1F) << 6) | 2);
-
-	while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
-	}
-
-	if (!(GRETH_REGLOAD(&regs->mdio) & GRETH_MII_NVALID)) {
-		return (GRETH_REGLOAD(&regs->mdio) >> 16) & 0xFFFF;
-	} else {
-		return -1;
-	}
-}
-
-static void write_mii(int phyaddr, int regaddr, int data, volatile greth_regs * regs)
-{
-	while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
-	}
-
-	GRETH_REGSAVE(&regs->mdio,
-		      ((data & 0xFFFF) << 16) | ((phyaddr & 0x1F) << 11) |
-		      ((regaddr & 0x1F) << 6) | 1);
-
-	while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
-	}
-
-}
-
-/* init/start hardware and allocate descriptor buffers for rx side
- *
- */
-int greth_init(struct eth_device *dev, bd_t * bis)
-{
-	int i;
-
-	greth_priv *greth = dev->priv;
-	greth_regs *regs = greth->regs;
-
-	debug("greth_init\n");
-
-	/* Reset core */
-	GRETH_REGSAVE(&regs->control, (GRETH_RESET | (greth->gb << 8) |
-		(greth->sp << 7) | (greth->fd << 4)));
-
-	/* Wait for Reset to complete */
-	while ( GRETH_REGLOAD(&regs->control) & GRETH_RESET) ;
-
-	GRETH_REGSAVE(&regs->control,
-		((greth->gb << 8) | (greth->sp << 7) | (greth->fd << 4)));
-
-	if (!greth->rxbd_base) {
-
-		/* allocate descriptors */
-		greth->rxbd_base = (greth_bd *)
-		    memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
-		greth->txbd_base = (greth_bd *)
-		    memalign(0x1000, GRETH_TXBD_CNT * sizeof(greth_bd));
-
-		/* allocate buffers to all descriptors  */
-		greth->rxbuf_base =
-		    malloc(GRETH_RXBUF_EFF_SIZE * GRETH_RXBD_CNT);
-	}
-
-	/* initate rx decriptors */
-	for (i = 0; i < GRETH_RXBD_CNT; i++) {
-		greth->rxbd_base[i].addr = (unsigned int)
-		    greth->rxbuf_base + (GRETH_RXBUF_EFF_SIZE * i);
-		/* enable desciptor & set wrap bit if last descriptor */
-		if (i >= (GRETH_RXBD_CNT - 1)) {
-			greth->rxbd_base[i].stat = GRETH_BD_EN | GRETH_BD_WR;
-		} else {
-			greth->rxbd_base[i].stat = GRETH_BD_EN;
-		}
-	}
-
-	/* initiate indexes */
-	greth->rxbd_curr = greth->rxbd_base;
-	greth->rxbd_max = greth->rxbd_base + (GRETH_RXBD_CNT - 1);
-	greth->txbd_max = greth->txbd_base + (GRETH_TXBD_CNT - 1);
-	/*
-	 * greth->txbd_base->addr = 0;
-	 * greth->txbd_base->stat = GRETH_BD_WR;
-	 */
-
-	/* initate tx decriptors */
-	for (i = 0; i < GRETH_TXBD_CNT; i++) {
-		greth->txbd_base[i].addr = 0;
-		/* enable desciptor & set wrap bit if last descriptor */
-		if (i >= (GRETH_TXBD_CNT - 1)) {
-			greth->txbd_base[i].stat = GRETH_BD_WR;
-		} else {
-			greth->txbd_base[i].stat = 0;
-		}
-	}
-
-	/**** SET HARDWARE REGS ****/
-
-	/* Set pointer to tx/rx descriptor areas */
-	GRETH_REGSAVE(&regs->rx_desc_p, (unsigned int)&greth->rxbd_base[0]);
-	GRETH_REGSAVE(&regs->tx_desc_p, (unsigned int)&greth->txbd_base[0]);
-
-	/* Enable Transmitter, GRETH will now scan descriptors for packets
-	 * to transmitt */
-	debug("greth_init: enabling receiver\n");
-	GRETH_REGORIN(&regs->control, GRETH_RXEN);
-
-	return 0;
-}
-
-/* Initiate PHY to a relevant speed
- * return:
- *  - 0 = success
- *  - 1 = timeout/fail
- */
-int greth_init_phy(greth_priv * dev, bd_t * bis)
-{
-	greth_regs *regs = dev->regs;
-	int tmp, tmp1, tmp2, i;
-	unsigned int start, timeout;
-	int phyaddr = GRETH_PHY_ADR_DEFAULT;
-
-#ifndef CONFIG_SYS_GRLIB_GRETH_PHYADDR
-	/* If BSP doesn't provide a hardcoded PHY address the driver will
-	 * try to autodetect PHY address by stopping the search on the first
-	 * PHY address which has REG0 implemented.
-	 */
-	for (i=0; i<32; i++) {
-		tmp = read_mii(i, 0, regs);
-		if ( (tmp != 0) && (tmp != 0xffff) ) {
-			phyaddr = i;
-			break;
-		}
-	}
-#endif
-
-	/* Save PHY Address */
-	dev->phyaddr = phyaddr;
-
-	debug("GRETH PHY ADDRESS: %d\n", phyaddr);
-
-	/* X msecs to ticks */
-	timeout = GRETH_PHY_TIMEOUT_MS * 1000;
-
-	/* Get system timer0 current value
-	 * Total timeout is 5s
-	 */
-	start = get_timer(0);
-
-	/* get phy control register default values */
-
-	while ((tmp = read_mii(phyaddr, 0, regs)) & 0x8000) {
-		if (get_timer(start) > timeout) {
-			debug("greth_init_phy: PHY read 1 failed\n");
-			return 1;	/* Fail */
-		}
-	}
-
-	/* reset PHY and wait for completion */
-	write_mii(phyaddr, 0, 0x8000 | tmp, regs);
-
-	while (((tmp = read_mii(phyaddr, 0, regs))) & 0x8000) {
-		if (get_timer(start) > timeout) {
-			debug("greth_init_phy: PHY read 2 failed\n");
-			return 1;	/* Fail */
-		}
-	}
-
-	/* Check if PHY is autoneg capable and then determine operating
-	 * mode, otherwise force it to 10 Mbit halfduplex
-	 */
-	dev->gb = 0;
-	dev->fd = 0;
-	dev->sp = 0;
-	dev->auto_neg = 0;
-	if (!((tmp >> 12) & 1)) {
-		write_mii(phyaddr, 0, 0, regs);
-	} else {
-		/* wait for auto negotiation to complete and then check operating mode */
-		dev->auto_neg = 1;
-		i = 0;
-		while (!(((tmp = read_mii(phyaddr, 1, regs)) >> 5) & 1)) {
-			if (get_timer(start) > timeout) {
-				printf("Auto negotiation timed out. "
-				       "Selecting default config\n");
-				tmp = read_mii(phyaddr, 0, regs);
-				dev->gb = ((tmp >> 6) & 1)
-				    && !((tmp >> 13) & 1);
-				dev->sp = !((tmp >> 6) & 1)
-				    && ((tmp >> 13) & 1);
-				dev->fd = (tmp >> 8) & 1;
-				goto auto_neg_done;
-			}
-		}
-		if ((tmp >> 8) & 1) {
-			tmp1 = read_mii(phyaddr, 9, regs);
-			tmp2 = read_mii(phyaddr, 10, regs);
-			if ((tmp1 & GRETH_MII_EXTADV_1000FD) &&
-			    (tmp2 & GRETH_MII_EXTPRT_1000FD)) {
-				dev->gb = 1;
-				dev->fd = 1;
-			}
-			if ((tmp1 & GRETH_MII_EXTADV_1000HD) &&
-			    (tmp2 & GRETH_MII_EXTPRT_1000HD)) {
-				dev->gb = 1;
-				dev->fd = 0;
-			}
-		}
-		if ((dev->gb == 0) || ((dev->gb == 1) && (dev->gbit_mac == 0))) {
-			tmp1 = read_mii(phyaddr, 4, regs);
-			tmp2 = read_mii(phyaddr, 5, regs);
-			if ((tmp1 & GRETH_MII_100TXFD) &&
-			    (tmp2 & GRETH_MII_100TXFD)) {
-				dev->sp = 1;
-				dev->fd = 1;
-			}
-			if ((tmp1 & GRETH_MII_100TXHD) &&
-			    (tmp2 & GRETH_MII_100TXHD)) {
-				dev->sp = 1;
-				dev->fd = 0;
-			}
-			if ((tmp1 & GRETH_MII_10FD) && (tmp2 & GRETH_MII_10FD)) {
-				dev->fd = 1;
-			}
-			if ((dev->gb == 1) && (dev->gbit_mac == 0)) {
-				dev->gb = 0;
-				dev->fd = 0;
-				write_mii(phyaddr, 0, dev->sp << 13, regs);
-			}
-		}
-
-	}
-      auto_neg_done:
-	debug("%s GRETH Ethermac at [0x%x] irq %d. Running \
-		%d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000" : "10/100", (unsigned int)(regs), (unsigned int)(dev->irq), dev->gb ? 1000 : (dev->sp ? 100 : 10), dev->fd ? "full" : "half");
-	/* Read out PHY info if extended registers are available */
-	if (tmp & 1) {
-		tmp1 = read_mii(phyaddr, 2, regs);
-		tmp2 = read_mii(phyaddr, 3, regs);
-		tmp1 = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F);
-		tmp = tmp2 & 0xF;
-
-		tmp2 = (tmp2 >> 4) & 0x3F;
-		debug("PHY: Vendor %x   Device %x    Revision %d\n", tmp1,
-		       tmp2, tmp);
-	} else {
-		printf("PHY info not available\n");
-	}
-
-	/* set speed and duplex bits in control register */
-	GRETH_REGORIN(&regs->control,
-		      (dev->gb << 8) | (dev->sp << 7) | (dev->fd << 4));
-
-	return 0;
-}
-
-void greth_halt(struct eth_device *dev)
-{
-	greth_priv *greth;
-	greth_regs *regs;
-	int i;
-
-	debug("greth_halt\n");
-
-	if (!dev || !dev->priv)
-		return;
-
-	greth = dev->priv;
-	regs = greth->regs;
-
-	if (!regs)
-		return;
-
-	/* disable receiver/transmitter by clearing the enable bits */
-	GRETH_REGANDIN(&regs->control, ~(GRETH_RXEN | GRETH_TXEN));
-
-	/* reset rx/tx descriptors */
-	if (greth->rxbd_base) {
-		for (i = 0; i < GRETH_RXBD_CNT; i++) {
-			greth->rxbd_base[i].stat =
-			    (i >= (GRETH_RXBD_CNT - 1)) ? GRETH_BD_WR : 0;
-		}
-	}
-
-	if (greth->txbd_base) {
-		for (i = 0; i < GRETH_TXBD_CNT; i++) {
-			greth->txbd_base[i].stat =
-			    (i >= (GRETH_TXBD_CNT - 1)) ? GRETH_BD_WR : 0;
-		}
-	}
-}
-
-int greth_send(struct eth_device *dev, void *eth_data, int data_length)
-{
-	greth_priv *greth = dev->priv;
-	greth_regs *regs = greth->regs;
-	greth_bd *txbd;
-	void *txbuf;
-	unsigned int status;
-
-	debug("greth_send\n");
-
-	/* send data, wait for data to be sent, then return */
-	if (((unsigned int)eth_data & (GRETH_BUF_ALIGN - 1))
-	    && !greth->gbit_mac) {
-		/* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer
-		 * and copy data to before giving it to GRETH.
-		 */
-		if (!greth->txbuf) {
-			greth->txbuf = malloc(GRETH_RXBUF_SIZE);
-		}
-
-		txbuf = greth->txbuf;
-
-		/* copy data info buffer */
-		memcpy((char *)txbuf, (char *)eth_data, data_length);
-
-		/* keep buffer to next time */
-	} else {
-		txbuf = (void *)eth_data;
-	}
-	/* get descriptor to use, only 1 supported... hehe easy */
-	txbd = greth->txbd_base;
-
-	/* setup descriptor to wrap around to it self */
-	txbd->addr = (unsigned int)txbuf;
-	txbd->stat = GRETH_BD_EN | GRETH_BD_WR | data_length;
-
-	/* Remind Core which descriptor to use when sending */
-	GRETH_REGSAVE(&regs->tx_desc_p, (unsigned int)txbd);
-
-	/* initate send by enabling transmitter */
-	GRETH_REGORIN(&regs->control, GRETH_TXEN);
-
-	/* Wait for data to be sent */
-	while ((status = GRETH_REGLOAD(&txbd->stat)) & GRETH_BD_EN) {
-		;
-	}
-
-	/* was the packet transmitted succesfully? */
-	if (status & GRETH_TXBD_ERR_AL) {
-		greth->stats.tx_limit_errors++;
-	}
-
-	if (status & GRETH_TXBD_ERR_UE) {
-		greth->stats.tx_underrun_errors++;
-	}
-
-	if (status & GRETH_TXBD_ERR_LC) {
-		greth->stats.tx_latecol_errors++;
-	}
-
-	if (status &
-	    (GRETH_TXBD_ERR_LC | GRETH_TXBD_ERR_UE | GRETH_TXBD_ERR_AL)) {
-		/* any error */
-		greth->stats.tx_errors++;
-		return -1;
-	}
-
-	/* bump tx packet counter */
-	greth->stats.tx_packets++;
-
-	/* return succefully */
-	return 0;
-}
-
-int greth_recv(struct eth_device *dev)
-{
-	greth_priv *greth = dev->priv;
-	greth_regs *regs = greth->regs;
-	greth_bd *rxbd;
-	unsigned int status, len = 0, bad;
-	char *d;
-	int enable = 0;
-	int i;
-
-	/* Receive One packet only, but clear as many error packets as there are
-	 * available.
-	 */
-	{
-		/* current receive descriptor */
-		rxbd = greth->rxbd_curr;
-
-		/* get status of next received packet */
-		status = GRETH_REGLOAD(&rxbd->stat);
-
-		bad = 0;
-
-		/* stop if no more packets received */
-		if (status & GRETH_BD_EN) {
-			goto done;
-		}
-
-		debug("greth_recv: packet 0x%x, 0x%x, len: %d\n",
-		       (unsigned int)rxbd, status, status & GRETH_BD_LEN);
-
-		/* Check status for errors.
-		 */
-		if (status & GRETH_RXBD_ERR_FT) {
-			greth->stats.rx_length_errors++;
-			bad = 1;
-		}
-		if (status & (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE)) {
-			greth->stats.rx_frame_errors++;
-			bad = 1;
-		}
-		if (status & GRETH_RXBD_ERR_CRC) {
-			greth->stats.rx_crc_errors++;
-			bad = 1;
-		}
-		if (bad) {
-			greth->stats.rx_errors++;
-			printf
-			    ("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n",
-			     greth->stats.rx_length_errors,
-			     greth->stats.rx_frame_errors,
-			     greth->stats.rx_crc_errors, status,
-			     greth->stats.rx_packets);
-			/* print all rx descriptors */
-			for (i = 0; i < GRETH_RXBD_CNT; i++) {
-				printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i,
-				       GRETH_REGLOAD(&greth->rxbd_base[i].stat),
-				       GRETH_REGLOAD(&greth->rxbd_base[i].addr));
-			}
-		} else {
-			/* Process the incoming packet. */
-			len = status & GRETH_BD_LEN;
-			d = (char *)rxbd->addr;
-
-			debug
-			    ("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n",
-			     len, d[0], d[1], d[2], d[3], d[4], d[5], d[6],
-			     d[7]);
-
-			/* flush all data cache to make sure we're not reading old packet data */
-			sparc_dcache_flush_all();
-
-			/* pass packet on to network subsystem */
-			net_process_received_packet((void *)d, len);
-
-			/* bump stats counters */
-			greth->stats.rx_packets++;
-
-			/* bad is now 0 ==> will stop loop */
-		}
-
-		/* reenable descriptor to receive more packet with this descriptor, wrap around if needed */
-		rxbd->stat =
-		    GRETH_BD_EN |
-		    (((unsigned int)greth->rxbd_curr >=
-		      (unsigned int)greth->rxbd_max) ? GRETH_BD_WR : 0);
-		enable = 1;
-
-		/* increase index */
-		greth->rxbd_curr =
-		    ((unsigned int)greth->rxbd_curr >=
-		     (unsigned int)greth->rxbd_max) ? greth->
-		    rxbd_base : (greth->rxbd_curr + 1);
-
-	}
-
-	if (enable) {
-		GRETH_REGORIN(&regs->control, GRETH_RXEN);
-	}
-      done:
-	/* return positive length of packet or 0 if non received */
-	return len;
-}
-
-void greth_set_hwaddr(greth_priv * greth, unsigned char *mac)
-{
-	/* save new MAC address */
-	greth->dev->enetaddr[0] = greth->hwaddr[0] = mac[0];
-	greth->dev->enetaddr[1] = greth->hwaddr[1] = mac[1];
-	greth->dev->enetaddr[2] = greth->hwaddr[2] = mac[2];
-	greth->dev->enetaddr[3] = greth->hwaddr[3] = mac[3];
-	greth->dev->enetaddr[4] = greth->hwaddr[4] = mac[4];
-	greth->dev->enetaddr[5] = greth->hwaddr[5] = mac[5];
-	greth->regs->esa_msb = (mac[0] << 8) | mac[1];
-	greth->regs->esa_lsb =
-	    (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
-
-	debug("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
-	       mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-}
-
-int greth_initialize(bd_t * bis)
-{
-	greth_priv *greth;
-	ambapp_apbdev apbdev;
-	struct eth_device *dev;
-	int i;
-	char *addr_str, *end;
-	unsigned char addr[6];
-
-	debug("Scanning for GRETH\n");
-
-	/* Find Device & IRQ via AMBA Plug&Play information,
-	 * CONFIG_SYS_GRLIB_GRETH_INDEX select which GRETH if multiple
-	 * GRETHs in system.
-	 */
-	if (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER, GAISLER_ETHMAC,
-			CONFIG_SYS_GRLIB_GRETH_INDEX, &apbdev) != 1) {
-		return -1;	/* GRETH not found */
-	}
-
-	greth = (greth_priv *) malloc(sizeof(greth_priv));
-	dev = (struct eth_device *)malloc(sizeof(struct eth_device));
-	memset(dev, 0, sizeof(struct eth_device));
-	memset(greth, 0, sizeof(greth_priv));
-
-	greth->regs = (greth_regs *) apbdev.address;
-	greth->irq = apbdev.irq;
-	debug("Found GRETH at %p, irq %d\n", greth->regs, greth->irq);
-	dev->priv = (void *)greth;
-	dev->iobase = (unsigned int)greth->regs;
-	dev->init = greth_init;
-	dev->halt = greth_halt;
-	dev->send = greth_send;
-	dev->recv = greth_recv;
-	greth->dev = dev;
-
-	/* Reset Core */
-	GRETH_REGSAVE(&greth->regs->control, GRETH_RESET);
-
-	/* Wait for core to finish reset cycle */
-	while (GRETH_REGLOAD(&greth->regs->control) & GRETH_RESET) ;
-
-	/* Get the phy address which assumed to have been set
-	   correctly with the reset value in hardware */
-	greth->phyaddr = (GRETH_REGLOAD(&greth->regs->mdio) >> 11) & 0x1F;
-
-	/* Check if mac is gigabit capable */
-	greth->gbit_mac = (GRETH_REGLOAD(&greth->regs->control) >> 27) & 1;
-
-	/* Make descriptor string */
-	if (greth->gbit_mac) {
-		strcpy(dev->name, "GRETH_10/100/GB");
-	} else {
-		strcpy(dev->name, "GRETH_10/100");
-	}
-
-	/* initiate PHY, select speed/duplex depending on connected PHY */
-	if (greth_init_phy(greth, bis)) {
-		/* Failed to init PHY (timedout) */
-		debug("GRETH[%p]: Failed to init PHY\n", greth->regs);
-		return -1;
-	}
-
-	/* Register Device to EtherNet subsystem  */
-	eth_register(dev);
-
-	/* Get MAC address */
-	if ((addr_str = getenv("ethaddr")) != NULL) {
-		for (i = 0; i < 6; i++) {
-			addr[i] =
-			    addr_str ? simple_strtoul(addr_str, &end, 16) : 0;
-			if (addr_str) {
-				addr_str = (*end) ? end + 1 : end;
-			}
-		}
-	} else {
-		/* No ethaddr set */
-		return -EINVAL;
-	}
-
-	/* set and remember MAC address */
-	greth_set_hwaddr(greth, addr);
-
-	debug("GRETH[%p]: Initialized successfully\n", greth->regs);
-	return 0;
-}
diff --git a/drivers/net/greth.h b/drivers/net/greth.h
deleted file mode 100644
index 5299b28..0000000
--- a/drivers/net/greth.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define GRETH_FD 0x10
-#define GRETH_RESET 0x40
-#define GRETH_MII_BUSY 0x8
-#define GRETH_MII_NVALID 0x10
-
-/* MII registers */
-#define GRETH_MII_EXTADV_1000FD 0x00000200
-#define GRETH_MII_EXTADV_1000HD 0x00000100
-#define GRETH_MII_EXTPRT_1000FD 0x00000800
-#define GRETH_MII_EXTPRT_1000HD 0x00000400
-
-#define GRETH_MII_100T4 0x00000200
-#define GRETH_MII_100TXFD 0x00000100
-#define GRETH_MII_100TXHD 0x00000080
-#define GRETH_MII_10FD 0x00000040
-#define GRETH_MII_10HD 0x00000020
-
-#define GRETH_BD_EN 0x800
-#define GRETH_BD_WR 0x1000
-#define GRETH_BD_IE 0x2000
-#define GRETH_BD_LEN 0x7FF
-
-#define GRETH_TXEN 0x1
-#define GRETH_INT_TX 0x8
-#define GRETH_TXI 0x4
-#define GRETH_TXBD_STATUS 0x0001C000
-#define GRETH_TXBD_MORE 0x20000
-#define GRETH_TXBD_IPCS 0x40000
-#define GRETH_TXBD_TCPCS 0x80000
-#define GRETH_TXBD_UDPCS 0x100000
-#define GRETH_TXBD_ERR_LC 0x10000
-#define GRETH_TXBD_ERR_UE 0x4000
-#define GRETH_TXBD_ERR_AL 0x8000
-#define GRETH_TXBD_NUM 128
-#define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1)
-#define GRETH_TX_BUF_SIZE 2048
-
-#define GRETH_INT_RX         0x4
-#define GRETH_RXEN           0x2
-#define GRETH_RXI            0x8
-#define GRETH_RXBD_STATUS    0xFFFFC000
-#define GRETH_RXBD_ERR_AE    0x4000
-#define GRETH_RXBD_ERR_FT    0x8000
-#define GRETH_RXBD_ERR_CRC   0x10000
-#define GRETH_RXBD_ERR_OE    0x20000
-#define GRETH_RXBD_ERR_LE    0x40000
-#define GRETH_RXBD_IP_DEC    0x80000
-#define GRETH_RXBD_IP_CSERR  0x100000
-#define GRETH_RXBD_UDP_DEC   0x200000
-#define GRETH_RXBD_UDP_CSERR 0x400000
-#define GRETH_RXBD_TCP_DEC   0x800000
-#define GRETH_RXBD_TCP_CSERR 0x1000000
-
-#define GRETH_RXBD_NUM 128
-#define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1)
-#define GRETH_RX_BUF_SIZE 2048
-
-/* Ethernet configuration registers */
-typedef struct _greth_regs {
-	volatile unsigned int control;
-	volatile unsigned int status;
-	volatile unsigned int esa_msb;
-	volatile unsigned int esa_lsb;
-	volatile unsigned int mdio;
-	volatile unsigned int tx_desc_p;
-	volatile unsigned int rx_desc_p;
-} greth_regs;
-
-/* Ethernet buffer descriptor */
-typedef struct _greth_bd {
-	volatile unsigned int stat;
-	unsigned int addr;	/* Buffer address not changed by HW */
-} greth_bd;
diff --git a/drivers/net/ldpaa_eth/ls2080a.c b/drivers/net/ldpaa_eth/ls2080a.c
index 93ed4f1..673e428 100644
--- a/drivers/net/ldpaa_eth/ls2080a.c
+++ b/drivers/net/ldpaa_eth/ls2080a.c
@@ -79,3 +79,33 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
 
 	return PHY_INTERFACE_MODE_NONE;
 }
+
+void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
+{
+	switch (lane_prtcl) {
+	case QSGMII_A:
+		wriop_init_dpmac(sd, 5, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 6, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 7, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 8, (int)lane_prtcl);
+		break;
+	case QSGMII_B:
+		wriop_init_dpmac(sd, 1, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 2, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 3, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 4, (int)lane_prtcl);
+		break;
+	case QSGMII_C:
+		wriop_init_dpmac(sd, 13, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 14, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 15, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 16, (int)lane_prtcl);
+		break;
+	case QSGMII_D:
+		wriop_init_dpmac(sd, 9, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 10, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 11, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 12, (int)lane_prtcl);
+		break;
+	}
+}
diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index 674075f..8881cc7 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -191,11 +191,16 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MVNETA_GMAC_AUTONEG_CONFIG               0x2c0c
 #define      MVNETA_GMAC_FORCE_LINK_DOWN         BIT(0)
 #define      MVNETA_GMAC_FORCE_LINK_PASS         BIT(1)
+#define      MVNETA_GMAC_FORCE_LINK_UP           (BIT(0) | BIT(1))
+#define      MVNETA_GMAC_IB_BYPASS_AN_EN         BIT(3)
 #define      MVNETA_GMAC_CONFIG_MII_SPEED        BIT(5)
 #define      MVNETA_GMAC_CONFIG_GMII_SPEED       BIT(6)
 #define      MVNETA_GMAC_AN_SPEED_EN             BIT(7)
+#define      MVNETA_GMAC_SET_FC_EN               BIT(8)
+#define      MVNETA_GMAC_ADVERT_FC_EN            BIT(9)
 #define      MVNETA_GMAC_CONFIG_FULL_DUPLEX      BIT(12)
 #define      MVNETA_GMAC_AN_DUPLEX_EN            BIT(13)
+#define      MVNETA_GMAC_SAMPLE_TX_CFG_EN        BIT(15)
 #define MVNETA_MIB_COUNTERS_BASE                 0x3080
 #define      MVNETA_MIB_LATE_COLLISION           0x7c
 #define MVNETA_DA_FILT_SPEC_MCAST                0x3400
@@ -404,6 +409,15 @@ static struct buffer_location buffer_loc;
  */
 #define BD_SPACE	(1 << 20)
 
+/*
+ * Dummy implementation that can be overwritten by a board
+ * specific function
+ */
+__weak int board_network_enable(struct mii_dev *bus)
+{
+	return 0;
+}
+
 /* Utility/helper methods */
 
 /* Write helper method */
@@ -557,6 +571,13 @@ static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
 	mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
 }
 
+static int mvneta_port_is_fixed_link(struct mvneta_port *pp)
+{
+	/* phy_addr is set to invalid value for fixed link */
+	return pp->phyaddr > PHY_MAX_ADDR;
+}
+
+
 /* Start the Ethernet port RX and TX activity */
 static void mvneta_port_up(struct mvneta_port *pp)
 {
@@ -807,10 +828,12 @@ static void mvneta_defaults_set(struct mvneta_port *pp)
 	/* Assign port SDMA configuration */
 	mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
 
-	/* Enable PHY polling in hardware for U-Boot */
-	val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
-	val |= MVNETA_PHY_POLLING_ENABLE;
-	mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
+	/* Enable PHY polling in hardware if not in fixed-link mode */
+	if (!mvneta_port_is_fixed_link(pp)) {
+		val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
+		val |= MVNETA_PHY_POLLING_ENABLE;
+		mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
+	}
 
 	mvneta_set_ucast_table(pp, -1);
 	mvneta_set_special_mcast_table(pp, -1);
@@ -1128,6 +1151,11 @@ static void mvneta_adjust_link(struct udevice *dev)
 	struct phy_device *phydev = pp->phydev;
 	int status_change = 0;
 
+	if (mvneta_port_is_fixed_link(pp)) {
+		debug("Using fixed link, skip link adjust\n");
+		return;
+	}
+
 	if (phydev->link) {
 		if ((pp->speed != phydev->speed) ||
 		    (pp->duplex != phydev->duplex)) {
@@ -1498,28 +1526,54 @@ static int mvneta_start(struct udevice *dev)
 	mvneta_port_power_up(pp, pp->phy_interface);
 
 	if (!pp->init || pp->link == 0) {
-		/* Set phy address of the port */
-		mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
-		phydev = phy_connect(pp->bus, pp->phyaddr, dev,
-				     pp->phy_interface);
-
-		pp->phydev = phydev;
-		phy_config(phydev);
-		phy_startup(phydev);
-		if (!phydev->link) {
-			printf("%s: No link.\n", phydev->dev->name);
-			return -1;
-		}
+		if (mvneta_port_is_fixed_link(pp)) {
+			u32 val;
 
-		/* Full init on first call */
-		mvneta_init(dev);
-		pp->init = 1;
-	} else {
-		/* Upon all following calls, this is enough */
-		mvneta_port_up(pp);
-		mvneta_port_enable(pp);
+			pp->init = 1;
+			pp->link = 1;
+			mvneta_init(dev);
+
+			val = MVNETA_GMAC_FORCE_LINK_UP |
+			      MVNETA_GMAC_IB_BYPASS_AN_EN |
+			      MVNETA_GMAC_SET_FC_EN |
+			      MVNETA_GMAC_ADVERT_FC_EN |
+			      MVNETA_GMAC_SAMPLE_TX_CFG_EN;
+
+			if (pp->duplex)
+				val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
+
+			if (pp->speed == SPEED_1000)
+				val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
+			else if (pp->speed == SPEED_100)
+				val |= MVNETA_GMAC_CONFIG_MII_SPEED;
+
+			mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
+		} else {
+			/* Set phy address of the port */
+			mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
+
+			phydev = phy_connect(pp->bus, pp->phyaddr, dev,
+					     pp->phy_interface);
+
+			pp->phydev = phydev;
+			phy_config(phydev);
+			phy_startup(phydev);
+			if (!phydev->link) {
+				printf("%s: No link.\n", phydev->dev->name);
+				return -1;
+			}
+
+			/* Full init on first call */
+			mvneta_init(dev);
+			pp->init = 1;
+			return 0;
+		}
 	}
 
+	/* Upon all following calls, this is enough */
+	mvneta_port_up(pp);
+	mvneta_port_enable(pp);
+
 	return 0;
 }
 
@@ -1615,6 +1669,8 @@ static int mvneta_probe(struct udevice *dev)
 	struct mii_dev *bus;
 	unsigned long addr;
 	void *bd_space;
+	int ret;
+	int fl_node;
 
 	/*
 	 * Allocate buffer area for descs and rx_buffers. This is only
@@ -1647,10 +1703,19 @@ static int mvneta_probe(struct udevice *dev)
 	/* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
 	pp->phy_interface = pdata->phy_interface;
 
-	/* Now read phyaddr from DT */
-	addr = fdtdec_get_int(blob, node, "phy", 0);
-	addr = fdt_node_offset_by_phandle(blob, addr);
-	pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
+	/* fetch 'fixed-link' property from 'neta' node */
+	fl_node = fdt_subnode_offset(blob, node, "fixed-link");
+	if (fl_node != -FDT_ERR_NOTFOUND) {
+		/* set phy_addr to invalid value for fixed link */
+		pp->phyaddr = PHY_MAX_ADDR + 1;
+		pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
+		pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
+	} else {
+		/* Now read phyaddr from DT */
+		addr = fdtdec_get_int(blob, node, "phy", 0);
+		addr = fdt_node_offset_by_phandle(blob, addr);
+		pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
+	}
 
 	bus = mdio_alloc();
 	if (!bus) {
@@ -1664,7 +1729,11 @@ static int mvneta_probe(struct udevice *dev)
 	bus->priv = (void *)pp;
 	pp->bus = bus;
 
-	return mdio_register(bus);
+	ret = mdio_register(bus);
+	if (ret)
+		return ret;
+
+	return board_network_enable(bus);
 }
 
 static void mvneta_stop(struct udevice *dev)
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 88e88b9..8ffe6c8 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -6,7 +6,7 @@
  * Marcin Wojtas <mw@semihalf.com>
  *
  * U-Boot version:
- * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -91,9 +91,11 @@ do {									\
 #define     MVPP2_SNOOP_PKT_SIZE_MASK		0x1ff
 #define     MVPP2_SNOOP_BUF_HDR_MASK		BIT(9)
 #define     MVPP2_RXQ_POOL_SHORT_OFFS		20
-#define     MVPP2_RXQ_POOL_SHORT_MASK		0x700000
+#define     MVPP21_RXQ_POOL_SHORT_MASK		0x700000
+#define     MVPP22_RXQ_POOL_SHORT_MASK		0xf00000
 #define     MVPP2_RXQ_POOL_LONG_OFFS		24
-#define     MVPP2_RXQ_POOL_LONG_MASK		0x7000000
+#define     MVPP21_RXQ_POOL_LONG_MASK		0x7000000
+#define     MVPP22_RXQ_POOL_LONG_MASK		0xf000000
 #define     MVPP2_RXQ_PACKET_OFFSET_OFFS	28
 #define     MVPP2_RXQ_PACKET_OFFSET_MASK	0x70000000
 #define     MVPP2_RXQ_DISABLE_MASK		BIT(31)
@@ -141,6 +143,7 @@ do {									\
 /* Descriptor Manager Top Registers */
 #define MVPP2_RXQ_NUM_REG			0x2040
 #define MVPP2_RXQ_DESC_ADDR_REG			0x2044
+#define     MVPP22_DESC_ADDR_OFFS		8
 #define MVPP2_RXQ_DESC_SIZE_REG			0x2048
 #define     MVPP2_RXQ_DESC_SIZE_MASK		0x3ff0
 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq)	(0x3000 + 4 * (rxq))
@@ -182,6 +185,7 @@ do {									\
 #define MVPP2_TXQ_RSVD_CLR_REG			0x20b8
 #define     MVPP2_TXQ_RSVD_CLR_OFFSET		16
 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu)	(0x2100 + 4 * (cpu))
+#define     MVPP22_AGGR_TXQ_DESC_ADDR_OFFS	8
 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu)	(0x2140 + 4 * (cpu))
 #define     MVPP2_AGGR_TXQ_DESC_SIZE_MASK	0x3ff0
 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu)		(0x2180 + 4 * (cpu))
@@ -194,9 +198,51 @@ do {									\
 #define MVPP2_WIN_REMAP(w)			(0x4040 + ((w) << 2))
 #define MVPP2_BASE_ADDR_ENABLE			0x4060
 
+/* AXI Bridge Registers */
+#define MVPP22_AXI_BM_WR_ATTR_REG		0x4100
+#define MVPP22_AXI_BM_RD_ATTR_REG		0x4104
+#define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG	0x4110
+#define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG	0x4114
+#define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG	0x4118
+#define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG	0x411c
+#define MVPP22_AXI_RX_DATA_WR_ATTR_REG		0x4120
+#define MVPP22_AXI_TX_DATA_RD_ATTR_REG		0x4130
+#define MVPP22_AXI_RD_NORMAL_CODE_REG		0x4150
+#define MVPP22_AXI_RD_SNOOP_CODE_REG		0x4154
+#define MVPP22_AXI_WR_NORMAL_CODE_REG		0x4160
+#define MVPP22_AXI_WR_SNOOP_CODE_REG		0x4164
+
+/* Values for AXI Bridge registers */
+#define MVPP22_AXI_ATTR_CACHE_OFFS		0
+#define MVPP22_AXI_ATTR_DOMAIN_OFFS		12
+
+#define MVPP22_AXI_CODE_CACHE_OFFS		0
+#define MVPP22_AXI_CODE_DOMAIN_OFFS		4
+
+#define MVPP22_AXI_CODE_CACHE_NON_CACHE		0x3
+#define MVPP22_AXI_CODE_CACHE_WR_CACHE		0x7
+#define MVPP22_AXI_CODE_CACHE_RD_CACHE		0xb
+
+#define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM	2
+#define MVPP22_AXI_CODE_DOMAIN_SYSTEM		3
+
 /* Interrupt Cause and Mask registers */
 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq)		(0x5200 + 4 * (rxq))
-#define MVPP2_ISR_RXQ_GROUP_REG(rxq)		(0x5400 + 4 * (rxq))
+#define MVPP21_ISR_RXQ_GROUP_REG(rxq)		(0x5400 + 4 * (rxq))
+
+#define MVPP22_ISR_RXQ_GROUP_INDEX_REG          0x5400
+#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
+#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK   0x380
+#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
+
+#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
+#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK   0x380
+
+#define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG     0x5404
+#define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK    0x1f
+#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK      0xf00
+#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET    8
+
 #define MVPP2_ISR_ENABLE_REG(port)		(0x5420 + 4 * (port))
 #define     MVPP2_ISR_ENABLE_INTERRUPT(mask)	((mask) & 0xffff)
 #define     MVPP2_ISR_DISABLE_INTERRUPT(mask)	(((mask) << 16) & 0xffff0000)
@@ -251,14 +297,23 @@ do {									\
 #define MVPP2_BM_PHY_ALLOC_REG(pool)		(0x6400 + ((pool) * 4))
 #define     MVPP2_BM_PHY_ALLOC_GRNTD_MASK	BIT(0)
 #define MVPP2_BM_VIRT_ALLOC_REG			0x6440
+#define MVPP2_BM_ADDR_HIGH_ALLOC		0x6444
+#define     MVPP2_BM_ADDR_HIGH_PHYS_MASK	0xff
+#define     MVPP2_BM_ADDR_HIGH_VIRT_MASK	0xff00
+#define     MVPP2_BM_ADDR_HIGH_VIRT_SHIFT	8
 #define MVPP2_BM_PHY_RLS_REG(pool)		(0x6480 + ((pool) * 4))
 #define     MVPP2_BM_PHY_RLS_MC_BUFF_MASK	BIT(0)
 #define     MVPP2_BM_PHY_RLS_PRIO_EN_MASK	BIT(1)
 #define     MVPP2_BM_PHY_RLS_GRNTD_MASK		BIT(2)
 #define MVPP2_BM_VIRT_RLS_REG			0x64c0
-#define MVPP2_BM_MC_RLS_REG			0x64c4
+#define MVPP21_BM_MC_RLS_REG			0x64c4
 #define     MVPP2_BM_MC_ID_MASK			0xfff
 #define     MVPP2_BM_FORCE_RELEASE_MASK		BIT(12)
+#define MVPP22_BM_ADDR_HIGH_RLS_REG		0x64c4
+#define     MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK	0xff
+#define	    MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK	0xff00
+#define     MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT	8
+#define MVPP22_BM_MC_RLS_REG			0x64d4
 
 /* TX Scheduler registers */
 #define MVPP2_TXP_SCHED_PORT_INDEX_REG		0x8000
@@ -294,16 +349,13 @@ do {									\
 #define MVPP2_SRC_ADDR_HIGH			0x28
 #define MVPP2_PHY_AN_CFG0_REG			0x34
 #define     MVPP2_PHY_AN_STOP_SMI0_MASK		BIT(7)
-#define MVPP2_MIB_COUNTERS_BASE(port)		(0x1000 + ((port) >> 1) * \
-						0x400 + (port) * 0x400)
-#define     MVPP2_MIB_LATE_COLLISION		0x7c
-#define MVPP2_ISR_SUM_MASK_REG			0x220c
 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG	0x305c
-#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT		0x27
+#define     MVPP2_EXT_GLOBAL_CTRL_DEFAULT	0x27
 
 /* Per-port registers */
 #define MVPP2_GMAC_CTRL_0_REG			0x0
 #define      MVPP2_GMAC_PORT_EN_MASK		BIT(0)
+#define      MVPP2_GMAC_PORT_TYPE_MASK		BIT(1)
 #define      MVPP2_GMAC_MAX_RX_SIZE_OFFS	2
 #define      MVPP2_GMAC_MAX_RX_SIZE_MASK	0x7ffc
 #define      MVPP2_GMAC_MIB_CNTR_EN_MASK	BIT(15)
@@ -315,23 +367,131 @@ do {									\
 #define      MVPP2_GMAC_SA_LOW_OFFS		7
 #define MVPP2_GMAC_CTRL_2_REG			0x8
 #define      MVPP2_GMAC_INBAND_AN_MASK		BIT(0)
+#define      MVPP2_GMAC_SGMII_MODE_MASK		BIT(0)
 #define      MVPP2_GMAC_PCS_ENABLE_MASK		BIT(3)
 #define      MVPP2_GMAC_PORT_RGMII_MASK		BIT(4)
+#define      MVPP2_GMAC_PORT_DIS_PADING_MASK	BIT(5)
 #define      MVPP2_GMAC_PORT_RESET_MASK		BIT(6)
+#define      MVPP2_GMAC_CLK_125_BYPS_EN_MASK	BIT(9)
 #define MVPP2_GMAC_AUTONEG_CONFIG		0xc
 #define      MVPP2_GMAC_FORCE_LINK_DOWN		BIT(0)
 #define      MVPP2_GMAC_FORCE_LINK_PASS		BIT(1)
+#define      MVPP2_GMAC_EN_PCS_AN		BIT(2)
+#define      MVPP2_GMAC_AN_BYPASS_EN		BIT(3)
 #define      MVPP2_GMAC_CONFIG_MII_SPEED	BIT(5)
 #define      MVPP2_GMAC_CONFIG_GMII_SPEED	BIT(6)
 #define      MVPP2_GMAC_AN_SPEED_EN		BIT(7)
 #define      MVPP2_GMAC_FC_ADV_EN		BIT(9)
+#define      MVPP2_GMAC_EN_FC_AN		BIT(11)
 #define      MVPP2_GMAC_CONFIG_FULL_DUPLEX	BIT(12)
 #define      MVPP2_GMAC_AN_DUPLEX_EN		BIT(13)
+#define      MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG	BIT(15)
 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG		0x1c
 #define      MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS	6
 #define      MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK	0x1fc0
 #define      MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v)	(((v) << 6) & \
 					MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
+#define MVPP2_GMAC_CTRL_4_REG			0x90
+#define      MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK	BIT(0)
+#define      MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK	BIT(5)
+#define      MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK	BIT(6)
+#define      MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK	BIT(7)
+
+/*
+ * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
+ * relative to port->base.
+ */
+
+/* Port Mac Control0 */
+#define MVPP22_XLG_CTRL0_REG			0x100
+#define      MVPP22_XLG_PORT_EN			BIT(0)
+#define      MVPP22_XLG_MAC_RESETN		BIT(1)
+#define      MVPP22_XLG_RX_FC_EN		BIT(7)
+#define      MVPP22_XLG_MIBCNT_DIS		BIT(13)
+/* Port Mac Control1 */
+#define MVPP22_XLG_CTRL1_REG			0x104
+#define      MVPP22_XLG_MAX_RX_SIZE_OFFS	0
+#define      MVPP22_XLG_MAX_RX_SIZE_MASK	0x1fff
+/* Port Interrupt Mask */
+#define MVPP22_XLG_INTERRUPT_MASK_REG		0x118
+#define      MVPP22_XLG_INTERRUPT_LINK_CHANGE	BIT(1)
+/* Port Mac Control3 */
+#define MVPP22_XLG_CTRL3_REG			0x11c
+#define      MVPP22_XLG_CTRL3_MACMODESELECT_MASK	(7 << 13)
+#define      MVPP22_XLG_CTRL3_MACMODESELECT_GMAC	(0 << 13)
+#define      MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC	(1 << 13)
+/* Port Mac Control4 */
+#define MVPP22_XLG_CTRL4_REG			0x184
+#define      MVPP22_XLG_FORWARD_802_3X_FC_EN	BIT(5)
+#define      MVPP22_XLG_FORWARD_PFC_EN		BIT(6)
+#define      MVPP22_XLG_MODE_DMA_1G		BIT(12)
+#define      MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK	BIT(14)
+
+/* XPCS registers */
+
+/* Global Configuration 0 */
+#define MVPP22_XPCS_GLOBAL_CFG_0_REG		0x0
+#define      MVPP22_XPCS_PCSRESET		BIT(0)
+#define      MVPP22_XPCS_PCSMODE_OFFS		3
+#define      MVPP22_XPCS_PCSMODE_MASK		(0x3 << \
+						 MVPP22_XPCS_PCSMODE_OFFS)
+#define      MVPP22_XPCS_LANEACTIVE_OFFS	5
+#define      MVPP22_XPCS_LANEACTIVE_MASK	(0x3 << \
+						 MVPP22_XPCS_LANEACTIVE_OFFS)
+
+/* MPCS registers */
+
+#define PCS40G_COMMON_CONTROL			0x14
+#define      FORWARD_ERROR_CORRECTION_MASK	BIT(1)
+
+#define PCS_CLOCK_RESET				0x14c
+#define      TX_SD_CLK_RESET_MASK		BIT(0)
+#define      RX_SD_CLK_RESET_MASK		BIT(1)
+#define      MAC_CLK_RESET_MASK			BIT(2)
+#define      CLK_DIVISION_RATIO_OFFS		4
+#define      CLK_DIVISION_RATIO_MASK		(0x7 << CLK_DIVISION_RATIO_OFFS)
+#define      CLK_DIV_PHASE_SET_MASK		BIT(11)
+
+/* System Soft Reset 1 */
+#define GOP_SOFT_RESET_1_REG			0x108
+#define     NETC_GOP_SOFT_RESET_OFFS		6
+#define     NETC_GOP_SOFT_RESET_MASK		(0x1 << \
+						 NETC_GOP_SOFT_RESET_OFFS)
+
+/* Ports Control 0 */
+#define NETCOMP_PORTS_CONTROL_0_REG		0x110
+#define     NETC_BUS_WIDTH_SELECT_OFFS		1
+#define     NETC_BUS_WIDTH_SELECT_MASK		(0x1 << \
+						 NETC_BUS_WIDTH_SELECT_OFFS)
+#define     NETC_GIG_RX_DATA_SAMPLE_OFFS	29
+#define     NETC_GIG_RX_DATA_SAMPLE_MASK	(0x1 << \
+						 NETC_GIG_RX_DATA_SAMPLE_OFFS)
+#define     NETC_CLK_DIV_PHASE_OFFS		31
+#define     NETC_CLK_DIV_PHASE_MASK		(0x1 << NETC_CLK_DIV_PHASE_OFFS)
+/* Ports Control 1 */
+#define NETCOMP_PORTS_CONTROL_1_REG		0x114
+#define     NETC_PORTS_ACTIVE_OFFSET(p)		(0 + p)
+#define     NETC_PORTS_ACTIVE_MASK(p)		(0x1 << \
+						 NETC_PORTS_ACTIVE_OFFSET(p))
+#define     NETC_PORT_GIG_RF_RESET_OFFS(p)	(28 + p)
+#define     NETC_PORT_GIG_RF_RESET_MASK(p)	(0x1 << \
+						 NETC_PORT_GIG_RF_RESET_OFFS(p))
+#define NETCOMP_CONTROL_0_REG			0x120
+#define     NETC_GBE_PORT0_SGMII_MODE_OFFS	0
+#define     NETC_GBE_PORT0_SGMII_MODE_MASK	(0x1 << \
+						 NETC_GBE_PORT0_SGMII_MODE_OFFS)
+#define     NETC_GBE_PORT1_SGMII_MODE_OFFS	1
+#define     NETC_GBE_PORT1_SGMII_MODE_MASK	(0x1 << \
+						 NETC_GBE_PORT1_SGMII_MODE_OFFS)
+#define     NETC_GBE_PORT1_MII_MODE_OFFS	2
+#define     NETC_GBE_PORT1_MII_MODE_MASK	(0x1 << \
+						 NETC_GBE_PORT1_MII_MODE_OFFS)
+
+#define MVPP22_SMI_MISC_CFG_REG			(MVPP22_SMI + 0x04)
+#define      MVPP22_SMI_POLLING_EN		BIT(10)
+
+#define MVPP22_SMI_PHY_ADDR_REG(port)		(MVPP22_SMI + 0x04 + \
+						 (0x4 * (port)))
 
 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK	0xff
 
@@ -340,7 +500,9 @@ do {									\
 	(((index) < (q)->last_desc) ? ((index) + 1) : 0)
 
 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
-#define MVPP2_SMI				0x0054
+#define MVPP21_SMI				0x0054
+/* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
+#define MVPP22_SMI				0x1200
 #define     MVPP2_PHY_REG_MASK			0x1f
 /* SMI register fields */
 #define     MVPP2_SMI_DATA_OFFS			0	/* Data */
@@ -355,6 +517,48 @@ do {									\
 #define     MVPP2_PHY_ADDR_MASK			0x1f
 #define     MVPP2_PHY_REG_MASK			0x1f
 
+/* Additional PPv2.2 offsets */
+#define MVPP22_MPCS				0x007000
+#define MVPP22_XPCS				0x007400
+#define MVPP22_PORT_BASE			0x007e00
+#define MVPP22_PORT_OFFSET			0x001000
+#define MVPP22_RFU1				0x318000
+
+/* Maximum number of ports */
+#define MVPP22_GOP_MAC_NUM			4
+
+/* Sets the field located at the specified in data */
+#define MVPP2_RGMII_TX_FIFO_MIN_TH		0x41
+#define MVPP2_SGMII_TX_FIFO_MIN_TH		0x5
+#define MVPP2_SGMII2_5_TX_FIFO_MIN_TH		0xb
+
+/* Net Complex */
+enum mv_netc_topology {
+	MV_NETC_GE_MAC2_SGMII		=	BIT(0),
+	MV_NETC_GE_MAC3_SGMII		=	BIT(1),
+	MV_NETC_GE_MAC3_RGMII		=	BIT(2),
+};
+
+enum mv_netc_phase {
+	MV_NETC_FIRST_PHASE,
+	MV_NETC_SECOND_PHASE,
+};
+
+enum mv_netc_sgmii_xmi_mode {
+	MV_NETC_GBE_SGMII,
+	MV_NETC_GBE_XMII,
+};
+
+enum mv_netc_mii_mode {
+	MV_NETC_GBE_RGMII,
+	MV_NETC_GBE_MII,
+};
+
+enum mv_netc_lanes {
+	MV_NETC_LANE_23,
+	MV_NETC_LANE_45,
+};
+
 /* Various constants */
 
 /* Coalescing */
@@ -397,9 +601,6 @@ do {									\
 /* Maximum number of TXQs used by single port */
 #define MVPP2_MAX_TXQ			8
 
-/* Maximum number of RXQs used by single port */
-#define MVPP2_MAX_RXQ			8
-
 /* Default number of TXQs in use */
 #define MVPP2_DEFAULT_TXQ		1
 
@@ -407,9 +608,6 @@ do {									\
 #define MVPP2_DEFAULT_RXQ		1
 #define CONFIG_MV_ETH_RXQ		8	/* increment by 8 */
 
-/* Total number of RXQs available to all ports */
-#define MVPP2_RXQ_TOTAL_NUM		(MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
-
 /* Max number of Rx descriptors */
 #define MVPP2_MAX_RXD			16
 
@@ -429,9 +627,23 @@ do {									\
 #define MVPP2_TX_DESC_ALIGN		(MVPP2_DESC_ALIGNED_SIZE - 1)
 
 /* RX FIFO constants */
-#define MVPP2_RX_FIFO_PORT_DATA_SIZE	0x2000
-#define MVPP2_RX_FIFO_PORT_ATTR_SIZE	0x80
-#define MVPP2_RX_FIFO_PORT_MIN_PKT	0x80
+#define MVPP21_RX_FIFO_PORT_DATA_SIZE		0x2000
+#define MVPP21_RX_FIFO_PORT_ATTR_SIZE		0x80
+#define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE	0x8000
+#define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE	0x2000
+#define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE	0x1000
+#define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE	0x200
+#define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE	0x80
+#define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE	0x40
+#define MVPP2_RX_FIFO_PORT_MIN_PKT		0x80
+
+/* TX general registers */
+#define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port)	(0x8860 + ((eth_tx_port) << 2))
+#define MVPP22_TX_FIFO_SIZE_MASK		0xf
+
+/* TX FIFO constants */
+#define MVPP2_TX_FIFO_DATA_SIZE_10KB		0xa
+#define MVPP2_TX_FIFO_DATA_SIZE_3KB		0x3
 
 /* RX buffer constants */
 #define MVPP2_SKB_SHINFO_SIZE \
@@ -576,28 +788,28 @@ enum mvpp2_tag_type {
 /* Sram result info bits assignment */
 #define MVPP2_PRS_RI_MAC_ME_MASK		0x1
 #define MVPP2_PRS_RI_DSA_MASK			0x2
-#define MVPP2_PRS_RI_VLAN_MASK			0xc
-#define MVPP2_PRS_RI_VLAN_NONE			~(BIT(2) | BIT(3))
+#define MVPP2_PRS_RI_VLAN_MASK			(BIT(2) | BIT(3))
+#define MVPP2_PRS_RI_VLAN_NONE			0x0
 #define MVPP2_PRS_RI_VLAN_SINGLE		BIT(2)
 #define MVPP2_PRS_RI_VLAN_DOUBLE		BIT(3)
 #define MVPP2_PRS_RI_VLAN_TRIPLE		(BIT(2) | BIT(3))
 #define MVPP2_PRS_RI_CPU_CODE_MASK		0x70
 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC		BIT(4)
-#define MVPP2_PRS_RI_L2_CAST_MASK		0x600
-#define MVPP2_PRS_RI_L2_UCAST			~(BIT(9) | BIT(10))
+#define MVPP2_PRS_RI_L2_CAST_MASK		(BIT(9) | BIT(10))
+#define MVPP2_PRS_RI_L2_UCAST			0x0
 #define MVPP2_PRS_RI_L2_MCAST			BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST			BIT(10)
 #define MVPP2_PRS_RI_PPPOE_MASK			0x800
-#define MVPP2_PRS_RI_L3_PROTO_MASK		0x7000
-#define MVPP2_PRS_RI_L3_UN			~(BIT(12) | BIT(13) | BIT(14))
+#define MVPP2_PRS_RI_L3_PROTO_MASK		(BIT(12) | BIT(13) | BIT(14))
+#define MVPP2_PRS_RI_L3_UN			0x0
 #define MVPP2_PRS_RI_L3_IP4			BIT(12)
 #define MVPP2_PRS_RI_L3_IP4_OPT			BIT(13)
 #define MVPP2_PRS_RI_L3_IP4_OTHER		(BIT(12) | BIT(13))
 #define MVPP2_PRS_RI_L3_IP6			BIT(14)
 #define MVPP2_PRS_RI_L3_IP6_EXT			(BIT(12) | BIT(14))
 #define MVPP2_PRS_RI_L3_ARP			(BIT(13) | BIT(14))
-#define MVPP2_PRS_RI_L3_ADDR_MASK		0x18000
-#define MVPP2_PRS_RI_L3_UCAST			~(BIT(15) | BIT(16))
+#define MVPP2_PRS_RI_L3_ADDR_MASK		(BIT(15) | BIT(16))
+#define MVPP2_PRS_RI_L3_UCAST			0x0
 #define MVPP2_PRS_RI_L3_MCAST			BIT(15)
 #define MVPP2_PRS_RI_L3_BCAST			(BIT(15) | BIT(16))
 #define MVPP2_PRS_RI_IP_FRAG_MASK		0x20000
@@ -693,6 +905,14 @@ struct mvpp2 {
 	/* Shared registers' base addresses */
 	void __iomem *base;
 	void __iomem *lms_base;
+	void __iomem *iface_base;
+	void __iomem *mdio_base;
+
+	void __iomem *mpcs_base;
+	void __iomem *xpcs_base;
+	void __iomem *rfu1_base;
+
+	u32 netc_config;
 
 	/* List of pointers to port structures */
 	struct mvpp2_port **port_list;
@@ -711,7 +931,15 @@ struct mvpp2 {
 	/* Tclk value */
 	u32 tclk;
 
+	/* HW version */
+	enum { MVPP21, MVPP22 } hw_version;
+
+	/* Maximum number of RXQs per port */
+	unsigned int max_port_rxqs;
+
 	struct mii_dev *bus;
+
+	int probe_done;
 };
 
 struct mvpp2_pcpu_stats {
@@ -724,6 +952,11 @@ struct mvpp2_pcpu_stats {
 struct mvpp2_port {
 	u8 id;
 
+	/* Index of the port from the "group of ports" complex point
+	 * of view
+	 */
+	int gop_id;
+
 	int irq;
 
 	struct mvpp2 *priv;
@@ -757,6 +990,8 @@ struct mvpp2_port {
 	unsigned int duplex;
 	unsigned int speed;
 
+	unsigned int phy_speed;		/* SGMII 1Gbps vs 2.5Gbps */
+
 	struct mvpp2_bm_pool *pool_long;
 	struct mvpp2_bm_pool *pool_short;
 
@@ -798,22 +1033,24 @@ struct mvpp2_port {
 #define MVPP2_RXD_L3_IP6		BIT(30)
 #define MVPP2_RXD_BUF_HDR		BIT(31)
 
-struct mvpp2_tx_desc {
+/* HW TX descriptor for PPv2.1 */
+struct mvpp21_tx_desc {
 	u32 command;		/* Options used by HW for packet transmitting.*/
 	u8  packet_offset;	/* the offset from the buffer beginning	*/
 	u8  phys_txq;		/* destination queue ID			*/
 	u16 data_size;		/* data size of transmitted packet in bytes */
-	u32 buf_phys_addr;	/* physical addr of transmitted buffer	*/
+	u32 buf_dma_addr;	/* physical addr of transmitted buffer	*/
 	u32 buf_cookie;		/* cookie for access to TX buffer in tx path */
 	u32 reserved1[3];	/* hw_cmd (for future use, BM, PON, PNC) */
 	u32 reserved2;		/* reserved (for future use)		*/
 };
 
-struct mvpp2_rx_desc {
+/* HW RX descriptor for PPv2.1 */
+struct mvpp21_rx_desc {
 	u32 status;		/* info about received packet		*/
 	u16 reserved1;		/* parser_info (for future use, PnC)	*/
 	u16 data_size;		/* size of received packet in bytes	*/
-	u32 buf_phys_addr;	/* physical address of the buffer	*/
+	u32 buf_dma_addr;	/* physical address of the buffer	*/
 	u32 buf_cookie;		/* cookie for access to RX buffer in rx path */
 	u16 reserved2;		/* gem_port_id (for future use, PON)	*/
 	u16 reserved3;		/* csum_l4 (for future use, PnC)	*/
@@ -824,6 +1061,45 @@ struct mvpp2_rx_desc {
 	u32 reserved8;
 };
 
+/* HW TX descriptor for PPv2.2 */
+struct mvpp22_tx_desc {
+	u32 command;
+	u8  packet_offset;
+	u8  phys_txq;
+	u16 data_size;
+	u64 reserved1;
+	u64 buf_dma_addr_ptp;
+	u64 buf_cookie_misc;
+};
+
+/* HW RX descriptor for PPv2.2 */
+struct mvpp22_rx_desc {
+	u32 status;
+	u16 reserved1;
+	u16 data_size;
+	u32 reserved2;
+	u32 reserved3;
+	u64 buf_dma_addr_key_hash;
+	u64 buf_cookie_misc;
+};
+
+/* Opaque type used by the driver to manipulate the HW TX and RX
+ * descriptors
+ */
+struct mvpp2_tx_desc {
+	union {
+		struct mvpp21_tx_desc pp21;
+		struct mvpp22_tx_desc pp22;
+	};
+};
+
+struct mvpp2_rx_desc {
+	union {
+		struct mvpp21_rx_desc pp21;
+		struct mvpp22_rx_desc pp22;
+	};
+};
+
 /* Per-CPU Tx queue control */
 struct mvpp2_txq_pcpu {
 	int cpu;
@@ -868,7 +1144,7 @@ struct mvpp2_tx_queue {
 	struct mvpp2_tx_desc *descs;
 
 	/* DMA address of the Tx DMA descriptors array */
-	dma_addr_t descs_phys;
+	dma_addr_t descs_dma;
 
 	/* Index of the last Tx DMA descriptor */
 	int last_desc;
@@ -891,7 +1167,7 @@ struct mvpp2_rx_queue {
 	struct mvpp2_rx_desc *descs;
 
 	/* DMA address of the RX DMA descriptors array */
-	dma_addr_t descs_phys;
+	dma_addr_t descs_dma;
 
 	/* Index of the last RX DMA descriptor */
 	int last_desc;
@@ -963,33 +1239,14 @@ struct mvpp2_bm_pool {
 	int pkt_size;
 
 	/* BPPE virtual base address */
-	u32 *virt_addr;
-	/* BPPE physical base address */
-	dma_addr_t phys_addr;
+	unsigned long *virt_addr;
+	/* BPPE DMA base address */
+	dma_addr_t dma_addr;
 
 	/* Ports using BM pool */
 	u32 port_map;
-
-	/* Occupied buffers indicator */
-	int in_use_thresh;
 };
 
-struct mvpp2_buff_hdr {
-	u32 next_buff_phys_addr;
-	u32 next_buff_virt_addr;
-	u16 byte_count;
-	u16 info;
-	u8  reserved1;		/* bm_qset (for future use, BM)		*/
-};
-
-/* Buffer header info bits */
-#define MVPP2_B_HDR_INFO_MC_ID_MASK	0xfff
-#define MVPP2_B_HDR_INFO_MC_ID(info)	((info) & MVPP2_B_HDR_INFO_MC_ID_MASK)
-#define MVPP2_B_HDR_INFO_LAST_OFFS	12
-#define MVPP2_B_HDR_INFO_LAST_MASK	BIT(12)
-#define MVPP2_B_HDR_INFO_IS_LAST(info) \
-	   ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
-
 /* Static declaractions */
 
 /* Number of RXQs used by single port */
@@ -997,6 +1254,8 @@ static int rxq_number = MVPP2_DEFAULT_RXQ;
 /* Number of TXQs used by single port */
 static int txq_number = MVPP2_DEFAULT_TXQ;
 
+static int base_id;
+
 #define MVPP2_DRIVER_NAME "mvpp2"
 #define MVPP2_DRIVER_VERSION "1.0"
 
@@ -1007,8 +1266,8 @@ struct buffer_location {
 	struct mvpp2_tx_desc *aggr_tx_descs;
 	struct mvpp2_tx_desc *tx_descs;
 	struct mvpp2_rx_desc *rx_descs;
-	u32 *bm_pool[MVPP2_BM_POOLS_NUM];
-	u32 *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
+	unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
+	unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
 	int first_rxq;
 };
 
@@ -1036,6 +1295,96 @@ static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
 	return readl(priv->base + offset);
 }
 
+static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
+				      struct mvpp2_tx_desc *tx_desc,
+				      dma_addr_t dma_addr)
+{
+	if (port->priv->hw_version == MVPP21) {
+		tx_desc->pp21.buf_dma_addr = dma_addr;
+	} else {
+		u64 val = (u64)dma_addr;
+
+		tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
+		tx_desc->pp22.buf_dma_addr_ptp |= val;
+	}
+}
+
+static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
+				  struct mvpp2_tx_desc *tx_desc,
+				  size_t size)
+{
+	if (port->priv->hw_version == MVPP21)
+		tx_desc->pp21.data_size = size;
+	else
+		tx_desc->pp22.data_size = size;
+}
+
+static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
+				 struct mvpp2_tx_desc *tx_desc,
+				 unsigned int txq)
+{
+	if (port->priv->hw_version == MVPP21)
+		tx_desc->pp21.phys_txq = txq;
+	else
+		tx_desc->pp22.phys_txq = txq;
+}
+
+static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
+				 struct mvpp2_tx_desc *tx_desc,
+				 unsigned int command)
+{
+	if (port->priv->hw_version == MVPP21)
+		tx_desc->pp21.command = command;
+	else
+		tx_desc->pp22.command = command;
+}
+
+static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
+				    struct mvpp2_tx_desc *tx_desc,
+				    unsigned int offset)
+{
+	if (port->priv->hw_version == MVPP21)
+		tx_desc->pp21.packet_offset = offset;
+	else
+		tx_desc->pp22.packet_offset = offset;
+}
+
+static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
+					    struct mvpp2_rx_desc *rx_desc)
+{
+	if (port->priv->hw_version == MVPP21)
+		return rx_desc->pp21.buf_dma_addr;
+	else
+		return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
+}
+
+static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
+					     struct mvpp2_rx_desc *rx_desc)
+{
+	if (port->priv->hw_version == MVPP21)
+		return rx_desc->pp21.buf_cookie;
+	else
+		return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
+}
+
+static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
+				    struct mvpp2_rx_desc *rx_desc)
+{
+	if (port->priv->hw_version == MVPP21)
+		return rx_desc->pp21.data_size;
+	else
+		return rx_desc->pp22.data_size;
+}
+
+static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
+				   struct mvpp2_rx_desc *rx_desc)
+{
+	if (port->priv->hw_version == MVPP21)
+		return rx_desc->pp21.status;
+	else
+		return rx_desc->pp22.status;
+}
+
 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
 {
 	txq_pcpu->txq_get_index++;
@@ -2218,19 +2567,26 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
 {
 	u32 val;
 
+	/* Number of buffer pointers must be a multiple of 16, as per
+	 * hardware constraints
+	 */
+	if (!IS_ALIGNED(size, 16))
+		return -EINVAL;
+
 	bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
-	bm_pool->phys_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
+	bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
 	if (!bm_pool->virt_addr)
 		return -ENOMEM;
 
-	if (!IS_ALIGNED((u32)bm_pool->virt_addr, MVPP2_BM_POOL_PTR_ALIGN)) {
+	if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
+			MVPP2_BM_POOL_PTR_ALIGN)) {
 		dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
 			bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
 		return -ENOMEM;
 	}
 
 	mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
-		    bm_pool->phys_addr);
+		    lower_32_bits(bm_pool->dma_addr));
 	mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
 
 	val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
@@ -2337,17 +2693,20 @@ static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
 				    int lrxq, int long_pool)
 {
-	u32 val;
+	u32 val, mask;
 	int prxq;
 
 	/* Get queue physical ID */
 	prxq = port->rxqs[lrxq]->id;
 
-	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
-	val &= ~MVPP2_RXQ_POOL_LONG_MASK;
-	val |= ((long_pool << MVPP2_RXQ_POOL_LONG_OFFS) &
-		    MVPP2_RXQ_POOL_LONG_MASK);
+	if (port->priv->hw_version == MVPP21)
+		mask = MVPP21_RXQ_POOL_LONG_MASK;
+	else
+		mask = MVPP22_RXQ_POOL_LONG_MASK;
 
+	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
+	val &= ~mask;
+	val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 }
 
@@ -2363,26 +2722,48 @@ static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
 }
 
 /* Get pool number from a BM cookie */
-static inline int mvpp2_bm_cookie_pool_get(u32 cookie)
+static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
 {
 	return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
 }
 
 /* Release buffer to BM */
 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
-				     u32 buf_phys_addr, u32 buf_virt_addr)
+				     dma_addr_t buf_dma_addr,
+				     unsigned long buf_phys_addr)
 {
-	mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr);
-	mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr);
+	if (port->priv->hw_version == MVPP22) {
+		u32 val = 0;
+
+		if (sizeof(dma_addr_t) == 8)
+			val |= upper_32_bits(buf_dma_addr) &
+				MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
+
+		if (sizeof(phys_addr_t) == 8)
+			val |= (upper_32_bits(buf_phys_addr)
+				<< MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
+				MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
+
+		mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
+	}
+
+	/* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
+	 * returned in the "cookie" field of the RX
+	 * descriptor. Instead of storing the virtual address, we
+	 * store the physical address
+	 */
+	mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
+	mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
 }
 
 /* Refill BM pool */
 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
-			      u32 phys_addr, u32 cookie)
+			      dma_addr_t dma_addr,
+			      phys_addr_t phys_addr)
 {
 	int pool = mvpp2_bm_cookie_pool_get(bm);
 
-	mvpp2_bm_pool_put(port, pool, phys_addr, cookie);
+	mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
 }
 
 /* Allocate buffers for the pool */
@@ -2390,7 +2771,6 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 			     struct mvpp2_bm_pool *bm_pool, int buf_num)
 {
 	int i;
-	u32 bm;
 
 	if (buf_num < 0 ||
 	    (buf_num + bm_pool->buf_num > bm_pool->size)) {
@@ -2400,15 +2780,15 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 		return 0;
 	}
 
-	bm = mvpp2_bm_cookie_pool_set(0, bm_pool->id);
 	for (i = 0; i < buf_num; i++) {
-		mvpp2_pool_refill(port, bm, (u32)buffer_loc.rx_buffer[i],
-				  (u32)buffer_loc.rx_buffer[i]);
+		mvpp2_bm_pool_put(port, bm_pool->id,
+				  (dma_addr_t)buffer_loc.rx_buffer[i],
+				  (unsigned long)buffer_loc.rx_buffer[i]);
+
 	}
 
 	/* Update BM driver with number of buffers added to pool */
 	bm_pool->buf_num += i;
-	bm_pool->in_use_thresh = bm_pool->buf_num / 4;
 
 	return i;
 }
@@ -2502,6 +2882,7 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
 		val |= MVPP2_GMAC_INBAND_AN_MASK;
 		break;
 	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
 		val |= MVPP2_GMAC_PORT_RGMII_MASK;
 	default:
 		val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
@@ -2593,22 +2974,749 @@ static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
 	writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
 }
 
-/* Set defaults to the MVPP2 port */
-static void mvpp2_defaults_set(struct mvpp2_port *port)
+/* PPv2.2 GoP/GMAC config */
+
+/* Set the MAC to reset or exit from reset */
+static int gop_gmac_reset(struct mvpp2_port *port, int reset)
 {
-	int tx_port_num, val, queue, ptxq, lrxq;
+	u32 val;
+
+	/* read - modify - write */
+	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+	if (reset)
+		val |= MVPP2_GMAC_PORT_RESET_MASK;
+	else
+		val &= ~MVPP2_GMAC_PORT_RESET_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+	return 0;
+}
+
+/*
+ * gop_gpcs_mode_cfg
+ *
+ * Configure port to working with Gig PCS or don't.
+ */
+static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en)
+{
+	u32 val;
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+	if (en)
+		val |= MVPP2_GMAC_PCS_ENABLE_MASK;
+	else
+		val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
+	/* enable / disable PCS on this port */
+	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+	return 0;
+}
+
+static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en)
+{
+	u32 val;
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+	if (en)
+		val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
+	else
+		val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
+	/* enable / disable PCS on this port */
+	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+	return 0;
+}
+
+static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
+{
+	u32 val, thresh;
+
+	/*
+	 * Configure minimal level of the Tx FIFO before the lower part
+	 * starts to read a packet
+	 */
+	thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
+	val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+	val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
+	val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
+	writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+
+	/* Disable bypass of sync module */
+	val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
+	val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
+	/* configure DP clock select according to mode */
+	val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
+	/* configure QSGMII bypass according to mode */
+	val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+	val |= MVPP2_GMAC_PORT_DIS_PADING_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+	/*
+	 * Configure GIG MAC to 1000Base-X mode connected to a fiber
+	 * transceiver
+	 */
+	val |= MVPP2_GMAC_PORT_TYPE_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+
+	/* configure AN 0x9268 */
+	val = MVPP2_GMAC_EN_PCS_AN |
+		MVPP2_GMAC_AN_BYPASS_EN |
+		MVPP2_GMAC_CONFIG_MII_SPEED  |
+		MVPP2_GMAC_CONFIG_GMII_SPEED     |
+		MVPP2_GMAC_FC_ADV_EN    |
+		MVPP2_GMAC_CONFIG_FULL_DUPLEX |
+		MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
+	writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+}
 
-	/* Configure port to loopback if needed */
-	if (port->flags & MVPP2_F_LOOPBACK)
-		mvpp2_port_loopback_set(port);
+static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
+{
+	u32 val, thresh;
 
-	/* Update TX FIFO MIN Threshold */
+	/*
+	 * Configure minimal level of the Tx FIFO before the lower part
+	 * starts to read a packet
+	 */
+	thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
 	val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
 	val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
-	/* Min. TX threshold must be less than minimal packet length */
-	val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
+	val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
 	writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
 
+	/* Disable bypass of sync module */
+	val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
+	val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
+	/* configure DP clock select according to mode */
+	val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
+	/* configure QSGMII bypass according to mode */
+	val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+	val |= MVPP2_GMAC_PORT_DIS_PADING_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+	/* configure GIG MAC to SGMII mode */
+	val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+
+	/* configure AN */
+	val = MVPP2_GMAC_EN_PCS_AN |
+		MVPP2_GMAC_AN_BYPASS_EN |
+		MVPP2_GMAC_AN_SPEED_EN  |
+		MVPP2_GMAC_EN_FC_AN     |
+		MVPP2_GMAC_AN_DUPLEX_EN |
+		MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
+	writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+}
+
+static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
+{
+	u32 val, thresh;
+
+	/*
+	 * Configure minimal level of the Tx FIFO before the lower part
+	 * starts to read a packet
+	 */
+	thresh = MVPP2_RGMII_TX_FIFO_MIN_TH;
+	val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+	val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
+	val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
+	writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+
+	/* Disable bypass of sync module */
+	val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
+	val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
+	/* configure DP clock select according to mode */
+	val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
+	val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
+	val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+	val &= ~MVPP2_GMAC_PORT_DIS_PADING_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+	/* configure GIG MAC to SGMII mode */
+	val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+
+	/* configure AN 0xb8e8 */
+	val = MVPP2_GMAC_AN_BYPASS_EN |
+		MVPP2_GMAC_AN_SPEED_EN   |
+		MVPP2_GMAC_EN_FC_AN      |
+		MVPP2_GMAC_AN_DUPLEX_EN  |
+		MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
+	writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+}
+
+/* Set the internal mux's to the required MAC in the GOP */
+static int gop_gmac_mode_cfg(struct mvpp2_port *port)
+{
+	u32 val;
+
+	/* Set TX FIFO thresholds */
+	switch (port->phy_interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+		if (port->phy_speed == 2500)
+			gop_gmac_sgmii2_5_cfg(port);
+		else
+			gop_gmac_sgmii_cfg(port);
+		break;
+
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+		gop_gmac_rgmii_cfg(port);
+		break;
+
+	default:
+		return -1;
+	}
+
+	/* Jumbo frame support - 0x1400*2= 0x2800 bytes */
+	val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+	val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
+	val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS;
+	writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+
+	/* PeriodicXonEn disable */
+	val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
+	val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
+
+	return 0;
+}
+
+static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port)
+{
+	u32 val;
+
+	/* relevant only for MAC0 (XLG0 and GMAC0) */
+	if (port->gop_id > 0)
+		return;
+
+	/* configure 1Gig MAC mode */
+	val = readl(port->base + MVPP22_XLG_CTRL3_REG);
+	val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
+	val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
+	writel(val, port->base + MVPP22_XLG_CTRL3_REG);
+}
+
+static int gop_gpcs_reset(struct mvpp2_port *port, int reset)
+{
+	u32 val;
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+	if (reset)
+		val &= ~MVPP2_GMAC_SGMII_MODE_MASK;
+	else
+		val |= MVPP2_GMAC_SGMII_MODE_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+	return 0;
+}
+
+/* Set the internal mux's to the required PCS in the PI */
+static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
+{
+	u32 val;
+	int lane;
+
+	switch (num_of_lanes) {
+	case 1:
+		lane = 0;
+		break;
+	case 2:
+		lane = 1;
+		break;
+	case 4:
+		lane = 2;
+		break;
+	default:
+		return -1;
+	}
+
+	/* configure XG MAC mode */
+	val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+	val &= ~MVPP22_XPCS_PCSMODE_OFFS;
+	val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
+	val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
+	writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+	return 0;
+}
+
+static int gop_mpcs_mode(struct mvpp2_port *port)
+{
+	u32 val;
+
+	/* configure PCS40G COMMON CONTROL */
+	val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+	val &= ~FORWARD_ERROR_CORRECTION_MASK;
+	writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+
+	/* configure PCS CLOCK RESET */
+	val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
+	val &= ~CLK_DIVISION_RATIO_MASK;
+	val |= 1 << CLK_DIVISION_RATIO_OFFS;
+	writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+
+	val &= ~CLK_DIV_PHASE_SET_MASK;
+	val |= MAC_CLK_RESET_MASK;
+	val |= RX_SD_CLK_RESET_MASK;
+	val |= TX_SD_CLK_RESET_MASK;
+	writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+
+	return 0;
+}
+
+/* Set the internal mux's to the required MAC in the GOP */
+static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
+{
+	u32 val;
+
+	/* configure 10G MAC mode */
+	val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+	val |= MVPP22_XLG_RX_FC_EN;
+	writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+
+	val = readl(port->base + MVPP22_XLG_CTRL3_REG);
+	val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
+	val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
+	writel(val, port->base + MVPP22_XLG_CTRL3_REG);
+
+	/* read - modify - write */
+	val = readl(port->base + MVPP22_XLG_CTRL4_REG);
+	val &= ~MVPP22_XLG_MODE_DMA_1G;
+	val |= MVPP22_XLG_FORWARD_PFC_EN;
+	val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
+	val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
+	writel(val, port->base + MVPP22_XLG_CTRL4_REG);
+
+	/* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
+	val = readl(port->base + MVPP22_XLG_CTRL1_REG);
+	val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
+	val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
+	writel(val, port->base + MVPP22_XLG_CTRL1_REG);
+
+	/* unmask link change interrupt */
+	val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
+	val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
+	val |= 1; /* unmask summary bit */
+	writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
+
+	return 0;
+}
+
+/* Set PCS to reset or exit from reset */
+static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
+{
+	u32 val;
+
+	/* read - modify - write */
+	val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+	if (reset)
+		val &= ~MVPP22_XPCS_PCSRESET;
+	else
+		val |= MVPP22_XPCS_PCSRESET;
+	writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+	return 0;
+}
+
+/* Set the MAC to reset or exit from reset */
+static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
+{
+	u32 val;
+
+	/* read - modify - write */
+	val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+	if (reset)
+		val &= ~MVPP22_XLG_MAC_RESETN;
+	else
+		val |= MVPP22_XLG_MAC_RESETN;
+	writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+
+	return 0;
+}
+
+/*
+ * gop_port_init
+ *
+ * Init physical port. Configures the port mode and all it's elements
+ * accordingly.
+ * Does not verify that the selected mode/port number is valid at the
+ * core level.
+ */
+static int gop_port_init(struct mvpp2_port *port)
+{
+	int mac_num = port->gop_id;
+	int num_of_act_lanes;
+
+	if (mac_num >= MVPP22_GOP_MAC_NUM) {
+		netdev_err(NULL, "%s: illegal port number %d", __func__,
+			   mac_num);
+		return -1;
+	}
+
+	switch (port->phy_interface) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+		gop_gmac_reset(port, 1);
+
+		/* configure PCS */
+		gop_gpcs_mode_cfg(port, 0);
+		gop_bypass_clk_cfg(port, 1);
+
+		/* configure MAC */
+		gop_gmac_mode_cfg(port);
+		/* pcs unreset */
+		gop_gpcs_reset(port, 0);
+
+		/* mac unreset */
+		gop_gmac_reset(port, 0);
+		break;
+
+	case PHY_INTERFACE_MODE_SGMII:
+		/* configure PCS */
+		gop_gpcs_mode_cfg(port, 1);
+
+		/* configure MAC */
+		gop_gmac_mode_cfg(port);
+		/* select proper Mac mode */
+		gop_xlg_2_gig_mac_cfg(port);
+
+		/* pcs unreset */
+		gop_gpcs_reset(port, 0);
+		/* mac unreset */
+		gop_gmac_reset(port, 0);
+		break;
+
+	case PHY_INTERFACE_MODE_SFI:
+		num_of_act_lanes = 2;
+		mac_num = 0;
+		/* configure PCS */
+		gop_xpcs_mode(port, num_of_act_lanes);
+		gop_mpcs_mode(port);
+		/* configure MAC */
+		gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
+
+		/* pcs unreset */
+		gop_xpcs_reset(port, 0);
+
+		/* mac unreset */
+		gop_xlg_mac_reset(port, 0);
+		break;
+
+	default:
+		netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
+			   __func__, port->phy_interface);
+		return -1;
+	}
+
+	return 0;
+}
+
+static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable)
+{
+	u32 val;
+
+	val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+	if (enable) {
+		/* Enable port and MIB counters update */
+		val |= MVPP22_XLG_PORT_EN;
+		val &= ~MVPP22_XLG_MIBCNT_DIS;
+	} else {
+		/* Disable port */
+		val &= ~MVPP22_XLG_PORT_EN;
+	}
+	writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+}
+
+static void gop_port_enable(struct mvpp2_port *port, int enable)
+{
+	switch (port->phy_interface) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_SGMII:
+		if (enable)
+			mvpp2_port_enable(port);
+		else
+			mvpp2_port_disable(port);
+		break;
+
+	case PHY_INTERFACE_MODE_SFI:
+		gop_xlg_mac_port_enable(port, enable);
+
+		break;
+	default:
+		netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
+			   port->phy_interface);
+		return;
+	}
+}
+
+/* RFU1 functions */
+static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset)
+{
+	return readl(priv->rfu1_base + offset);
+}
+
+static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data)
+{
+	writel(data, priv->rfu1_base + offset);
+}
+
+static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
+{
+	u32 val = 0;
+
+	if (gop_id == 2) {
+		if (phy_type == PHY_INTERFACE_MODE_SGMII)
+			val |= MV_NETC_GE_MAC2_SGMII;
+	}
+
+	if (gop_id == 3) {
+		if (phy_type == PHY_INTERFACE_MODE_SGMII)
+			val |= MV_NETC_GE_MAC3_SGMII;
+		else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
+			 phy_type == PHY_INTERFACE_MODE_RGMII_ID)
+			val |= MV_NETC_GE_MAC3_RGMII;
+	}
+
+	return val;
+}
+
+static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)
+{
+	u32 reg;
+
+	reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
+	reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id));
+
+	val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id);
+	val &= NETC_PORTS_ACTIVE_MASK(gop_id);
+
+	reg |= val;
+
+	gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
+}
+
+static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)
+{
+	u32 reg;
+
+	reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
+	reg &= ~NETC_GBE_PORT1_MII_MODE_MASK;
+
+	val <<= NETC_GBE_PORT1_MII_MODE_OFFS;
+	val &= NETC_GBE_PORT1_MII_MODE_MASK;
+
+	reg |= val;
+
+	gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
+}
+
+static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)
+{
+	u32 reg;
+
+	reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG);
+	reg &= ~NETC_GOP_SOFT_RESET_MASK;
+
+	val <<= NETC_GOP_SOFT_RESET_OFFS;
+	val &= NETC_GOP_SOFT_RESET_MASK;
+
+	reg |= val;
+
+	gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg);
+}
+
+static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)
+{
+	u32 reg;
+
+	reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
+	reg &= ~NETC_CLK_DIV_PHASE_MASK;
+
+	val <<= NETC_CLK_DIV_PHASE_OFFS;
+	val &= NETC_CLK_DIV_PHASE_MASK;
+
+	reg |= val;
+
+	gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
+}
+
+static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)
+{
+	u32 reg;
+
+	reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
+	reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id));
+
+	val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id);
+	val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id);
+
+	reg |= val;
+
+	gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
+}
+
+static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id,
+					   u32 val)
+{
+	u32 reg, mask, offset;
+
+	if (gop_id == 2) {
+		mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
+		offset = NETC_GBE_PORT0_SGMII_MODE_OFFS;
+	} else {
+		mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
+		offset = NETC_GBE_PORT1_SGMII_MODE_OFFS;
+	}
+	reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
+	reg &= ~mask;
+
+	val <<= offset;
+	val &= mask;
+
+	reg |= val;
+
+	gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
+}
+
+static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)
+{
+	u32 reg;
+
+	reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
+	reg &= ~NETC_BUS_WIDTH_SELECT_MASK;
+
+	val <<= NETC_BUS_WIDTH_SELECT_OFFS;
+	val &= NETC_BUS_WIDTH_SELECT_MASK;
+
+	reg |= val;
+
+	gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
+}
+
+static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)
+{
+	u32 reg;
+
+	reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
+	reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
+
+	val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS;
+	val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
+
+	reg |= val;
+
+	gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
+}
+
+static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id,
+				  enum mv_netc_phase phase)
+{
+	switch (phase) {
+	case MV_NETC_FIRST_PHASE:
+		/* Set Bus Width to HB mode = 1 */
+		gop_netc_bus_width_select(priv, 1);
+		/* Select RGMII mode */
+		gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII);
+		break;
+
+	case MV_NETC_SECOND_PHASE:
+		/* De-assert the relevant port HB reset */
+		gop_netc_port_rf_reset(priv, gop_id, 1);
+		break;
+	}
+}
+
+static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id,
+				  enum mv_netc_phase phase)
+{
+	switch (phase) {
+	case MV_NETC_FIRST_PHASE:
+		/* Set Bus Width to HB mode = 1 */
+		gop_netc_bus_width_select(priv, 1);
+		/* Select SGMII mode */
+		if (gop_id >= 1) {
+			gop_netc_gbe_sgmii_mode_select(priv, gop_id,
+						       MV_NETC_GBE_SGMII);
+		}
+
+		/* Configure the sample stages */
+		gop_netc_sample_stages_timing(priv, 0);
+		/* Configure the ComPhy Selector */
+		/* gop_netc_com_phy_selector_config(netComplex); */
+		break;
+
+	case MV_NETC_SECOND_PHASE:
+		/* De-assert the relevant port HB reset */
+		gop_netc_port_rf_reset(priv, gop_id, 1);
+		break;
+	}
+}
+
+static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
+{
+	u32 c = priv->netc_config;
+
+	if (c & MV_NETC_GE_MAC2_SGMII)
+		gop_netc_mac_to_sgmii(priv, 2, phase);
+	else
+		gop_netc_mac_to_xgmii(priv, 2, phase);
+
+	if (c & MV_NETC_GE_MAC3_SGMII) {
+		gop_netc_mac_to_sgmii(priv, 3, phase);
+	} else {
+		gop_netc_mac_to_xgmii(priv, 3, phase);
+		if (c & MV_NETC_GE_MAC3_RGMII)
+			gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII);
+		else
+			gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII);
+	}
+
+	/* Activate gop ports 0, 2, 3 */
+	gop_netc_active_port(priv, 0, 1);
+	gop_netc_active_port(priv, 2, 1);
+	gop_netc_active_port(priv, 3, 1);
+
+	if (phase == MV_NETC_SECOND_PHASE) {
+		/* Enable the GOP internal clock logic */
+		gop_netc_gop_clock_logic_set(priv, 1);
+		/* De-assert GOP unit reset */
+		gop_netc_gop_reset(priv, 1);
+	}
+
+	return 0;
+}
+
+/* Set defaults to the MVPP2 port */
+static void mvpp2_defaults_set(struct mvpp2_port *port)
+{
+	int tx_port_num, val, queue, ptxq, lrxq;
+
+	if (port->priv->hw_version == MVPP21) {
+		/* Configure port to loopback if needed */
+		if (port->flags & MVPP2_F_LOOPBACK)
+			mvpp2_port_loopback_set(port);
+
+		/* Update TX FIFO MIN Threshold */
+		val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+		val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
+		/* Min. TX threshold must be less than minimal packet length */
+		val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
+		writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+	}
+
 	/* Disable Legacy WRR, Disable EJP, Release from reset */
 	tx_port_num = mvpp2_egress_port(port);
 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
@@ -2791,11 +3899,15 @@ static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
 }
 
 /* Obtain BM cookie information from descriptor */
-static u32 mvpp2_bm_cookie_build(struct mvpp2_rx_desc *rx_desc)
+static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
+				 struct mvpp2_rx_desc *rx_desc)
 {
-	int pool = (rx_desc->status & MVPP2_RXD_BM_POOL_ID_MASK) >>
-		   MVPP2_RXD_BM_POOL_ID_OFFS;
 	int cpu = smp_processor_id();
+	int pool;
+
+	pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
+		MVPP2_RXD_BM_POOL_ID_MASK) >>
+		MVPP2_RXD_BM_POOL_ID_OFFS;
 
 	return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
 	       ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
@@ -2944,9 +4056,11 @@ static int mvpp2_aggr_txq_init(struct udevice *dev,
 			       int desc_num, int cpu,
 			       struct mvpp2 *priv)
 {
+	u32 txq_dma;
+
 	/* Allocate memory for TX descriptors */
 	aggr_txq->descs = buffer_loc.aggr_tx_descs;
-	aggr_txq->descs_phys = (dma_addr_t)buffer_loc.aggr_tx_descs;
+	aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
 	if (!aggr_txq->descs)
 		return -ENOMEM;
 
@@ -2960,10 +4074,16 @@ static int mvpp2_aggr_txq_init(struct udevice *dev,
 	aggr_txq->next_desc_to_proc = mvpp2_read(priv,
 						 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
 
-	/* Set Tx descriptors queue starting address */
-	/* indirect access */
-	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu),
-		    aggr_txq->descs_phys);
+	/* Set Tx descriptors queue starting address indirect
+	 * access
+	 */
+	if (priv->hw_version == MVPP21)
+		txq_dma = aggr_txq->descs_dma;
+	else
+		txq_dma = aggr_txq->descs_dma >>
+			MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
+
+	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
 	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
 
 	return 0;
@@ -2974,11 +4094,13 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
 			  struct mvpp2_rx_queue *rxq)
 
 {
+	u32 rxq_dma;
+
 	rxq->size = port->rx_ring_size;
 
 	/* Allocate memory for RX descriptors */
 	rxq->descs = buffer_loc.rx_descs;
-	rxq->descs_phys = (dma_addr_t)buffer_loc.rx_descs;
+	rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
 	if (!rxq->descs)
 		return -ENOMEM;
 
@@ -2992,7 +4114,11 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
 
 	/* Set Rx descriptors queue starting address - indirect access */
 	mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
-	mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_phys);
+	if (port->priv->hw_version == MVPP21)
+		rxq_dma = rxq->descs_dma;
+	else
+		rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
+	mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
 	mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
 	mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
 
@@ -3017,10 +4143,11 @@ static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
 
 	for (i = 0; i < rx_received; i++) {
 		struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
-		u32 bm = mvpp2_bm_cookie_build(rx_desc);
+		u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
 
-		mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
-				  rx_desc->buf_cookie);
+		mvpp2_pool_refill(port, bm,
+				  mvpp2_rxdesc_dma_addr_get(port, rx_desc),
+				  mvpp2_rxdesc_cookie_get(port, rx_desc));
 	}
 	mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
 }
@@ -3034,7 +4161,7 @@ static void mvpp2_rxq_deinit(struct mvpp2_port *port,
 	rxq->descs             = NULL;
 	rxq->last_desc         = 0;
 	rxq->next_desc_to_proc = 0;
-	rxq->descs_phys        = 0;
+	rxq->descs_dma         = 0;
 
 	/* Clear Rx descriptors queue starting address and size;
 	 * free descriptor number
@@ -3057,7 +4184,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port,
 
 	/* Allocate memory for Tx descriptors */
 	txq->descs = buffer_loc.tx_descs;
-	txq->descs_phys = (dma_addr_t)buffer_loc.tx_descs;
+	txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
 	if (!txq->descs)
 		return -ENOMEM;
 
@@ -3069,7 +4196,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port,
 
 	/* Set Tx descriptors queue starting address - indirect access */
 	mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
-	mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_phys);
+	mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
 	mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
 					     MVPP2_TXQ_DESC_SIZE_MASK);
 	mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
@@ -3090,7 +4217,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port,
 
 	mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
 		    MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
-		    MVPP2_PREF_BUF_THRESH(desc_per_txq/2));
+		    MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
 
 	/* WRR / EJP configuration - indirect access */
 	tx_port_num = mvpp2_egress_port(port);
@@ -3121,7 +4248,7 @@ static void mvpp2_txq_deinit(struct mvpp2_port *port,
 	txq->descs             = NULL;
 	txq->last_desc         = 0;
 	txq->next_desc_to_proc = 0;
-	txq->descs_phys        = 0;
+	txq->descs_dma         = 0;
 
 	/* Set minimum bandwidth for disabled TXQs */
 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
@@ -3314,20 +4441,21 @@ static void mvpp2_link_event(struct mvpp2_port *port)
 static void mvpp2_rx_error(struct mvpp2_port *port,
 			   struct mvpp2_rx_desc *rx_desc)
 {
-	u32 status = rx_desc->status;
+	u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
+	size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
 
 	switch (status & MVPP2_RXD_ERR_CODE_MASK) {
 	case MVPP2_RXD_ERR_CRC:
-		netdev_err(port->dev, "bad rx status %08x (crc error), size=%d\n",
-			   status, rx_desc->data_size);
+		netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
+			   status, sz);
 		break;
 	case MVPP2_RXD_ERR_OVERRUN:
-		netdev_err(port->dev, "bad rx status %08x (overrun error), size=%d\n",
-			   status, rx_desc->data_size);
+		netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
+			   status, sz);
 		break;
 	case MVPP2_RXD_ERR_RESOURCE:
-		netdev_err(port->dev, "bad rx status %08x (resource error), size=%d\n",
-			   status, rx_desc->data_size);
+		netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
+			   status, sz);
 		break;
 	}
 }
@@ -3335,9 +4463,9 @@ static void mvpp2_rx_error(struct mvpp2_port *port,
 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
 static int mvpp2_rx_refill(struct mvpp2_port *port,
 			   struct mvpp2_bm_pool *bm_pool,
-			   u32 bm, u32 phys_addr)
+			   u32 bm, dma_addr_t dma_addr)
 {
-	mvpp2_pool_refill(port, bm, phys_addr, phys_addr);
+	mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
 	return 0;
 }
 
@@ -3347,7 +4475,10 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
 	mvpp2_gmac_max_rx_size_set(port);
 	mvpp2_txp_max_tx_size_set(port);
 
-	mvpp2_port_enable(port);
+	if (port->priv->hw_version == MVPP21)
+		mvpp2_port_enable(port);
+	else
+		gop_port_enable(port, 1);
 }
 
 /* Set hw internals when stopping port */
@@ -3357,7 +4488,11 @@ static void mvpp2_stop_dev(struct mvpp2_port *port)
 	mvpp2_ingress_disable(port);
 
 	mvpp2_egress_disable(port);
-	mvpp2_port_disable(port);
+
+	if (port->priv->hw_version == MVPP21)
+		mvpp2_port_disable(port);
+	else
+		gop_port_enable(port, 0);
 }
 
 static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
@@ -3449,9 +4584,14 @@ static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
 
 static void mvpp2_port_power_up(struct mvpp2_port *port)
 {
-	mvpp2_port_mii_set(port);
+	struct mvpp2 *priv = port->priv;
+
+	/* On PPv2.2 the GoP / interface configuration has already been done */
+	if (priv->hw_version == MVPP21)
+		mvpp2_port_mii_set(port);
 	mvpp2_port_periodic_xon_disable(port);
-	mvpp2_port_fc_adv_enable(port);
+	if (priv->hw_version == MVPP21)
+		mvpp2_port_fc_adv_enable(port);
 	mvpp2_port_reset(port);
 }
 
@@ -3462,12 +4602,16 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
 	struct mvpp2_txq_pcpu *txq_pcpu;
 	int queue, cpu, err;
 
-	if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM)
+	if (port->first_rxq + rxq_number >
+	    MVPP2_MAX_PORTS * priv->max_port_rxqs)
 		return -EINVAL;
 
 	/* Disable port */
 	mvpp2_egress_disable(port);
-	mvpp2_port_disable(port);
+	if (priv->hw_version == MVPP21)
+		mvpp2_port_disable(port);
+	else
+		gop_port_enable(port, 0);
 
 	port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
 				  GFP_KERNEL);
@@ -3523,7 +4667,19 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
 	}
 
 	/* Configure Rx queue group interrupt for this port */
-	mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), CONFIG_MV_ETH_RXQ);
+	if (priv->hw_version == MVPP21) {
+		mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
+			    CONFIG_MV_ETH_RXQ);
+	} else {
+		u32 val;
+
+		val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
+		mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
+
+		val = (CONFIG_MV_ETH_RXQ <<
+		       MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
+		mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
+	}
 
 	/* Create Rx descriptor rings */
 	for (queue = 0; queue < rxq_number; queue++) {
@@ -3554,20 +4710,14 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
 	return 0;
 }
 
-/* Ports initialization */
-static int mvpp2_port_probe(struct udevice *dev,
-			    struct mvpp2_port *port,
-			    int port_node,
-			    struct mvpp2 *priv,
-			    int *next_first_rxq)
+static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
 {
+	int port_node = dev_of_offset(dev);
+	const char *phy_mode_str;
 	int phy_node;
 	u32 id;
 	u32 phyaddr;
-	const char *phy_mode_str;
 	int phy_mode = -1;
-	int priv_common_regs_num = 2;
-	int err;
 
 	phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
 	if (phy_node < 0) {
@@ -3589,34 +4739,48 @@ static int mvpp2_port_probe(struct udevice *dev,
 		return -EINVAL;
 	}
 
+	/*
+	 * ToDo:
+	 * Not sure if this DT property "phy-speed" will get accepted, so
+	 * this might change later
+	 */
+	/* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
+	port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
+					 "phy-speed", 1000);
+
 	phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
 
-	port->priv = priv;
 	port->id = id;
-	port->first_rxq = *next_first_rxq;
+	if (port->priv->hw_version == MVPP21)
+		port->first_rxq = port->id * rxq_number;
+	else
+		port->first_rxq = port->id * port->priv->max_port_rxqs;
 	port->phy_node = phy_node;
 	port->phy_interface = phy_mode;
 	port->phyaddr = phyaddr;
 
-	port->base = (void __iomem *)dev_get_addr_index(dev->parent,
-							priv_common_regs_num
-							+ id);
-	if (IS_ERR(port->base))
-		return PTR_ERR(port->base);
+	return 0;
+}
+
+/* Ports initialization */
+static int mvpp2_port_probe(struct udevice *dev,
+			    struct mvpp2_port *port,
+			    int port_node,
+			    struct mvpp2 *priv)
+{
+	int err;
 
 	port->tx_ring_size = MVPP2_MAX_TXD;
 	port->rx_ring_size = MVPP2_MAX_RXD;
 
 	err = mvpp2_port_init(dev, port);
 	if (err < 0) {
-		dev_err(&pdev->dev, "failed to init port %d\n", id);
+		dev_err(&pdev->dev, "failed to init port %d\n", port->id);
 		return err;
 	}
 	mvpp2_port_power_up(port);
 
-	/* Increment the first Rx queue number to be used by the next port */
-	*next_first_rxq += CONFIG_MV_ETH_RXQ;
-	priv->port_list[id] = port;
+	priv->port_list[port->id] = port;
 	return 0;
 }
 
@@ -3659,10 +4823,35 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
 	int port;
 
 	for (port = 0; port < MVPP2_MAX_PORTS; port++) {
-		mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
-			    MVPP2_RX_FIFO_PORT_DATA_SIZE);
-		mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
-			    MVPP2_RX_FIFO_PORT_ATTR_SIZE);
+		if (priv->hw_version == MVPP22) {
+			if (port == 0) {
+				mvpp2_write(priv,
+					    MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+					    MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
+				mvpp2_write(priv,
+					    MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+					    MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
+			} else if (port == 1) {
+				mvpp2_write(priv,
+					    MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+					    MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
+				mvpp2_write(priv,
+					    MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+					    MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
+			} else {
+				mvpp2_write(priv,
+					    MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+					    MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
+				mvpp2_write(priv,
+					    MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+					    MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
+			}
+		} else {
+			mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+				    MVPP21_RX_FIFO_PORT_DATA_SIZE);
+			mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+				    MVPP21_RX_FIFO_PORT_ATTR_SIZE);
+		}
 	}
 
 	mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
@@ -3670,6 +4859,78 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
 	mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
 }
 
+/* Initialize Tx FIFO's */
+static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
+{
+	int port, val;
+
+	for (port = 0; port < MVPP2_MAX_PORTS; port++) {
+		/* Port 0 supports 10KB TX FIFO */
+		if (port == 0) {
+			val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
+				MVPP22_TX_FIFO_SIZE_MASK;
+		} else {
+			val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
+				MVPP22_TX_FIFO_SIZE_MASK;
+		}
+		mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
+	}
+}
+
+static void mvpp2_axi_init(struct mvpp2 *priv)
+{
+	u32 val, rdval, wrval;
+
+	mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
+
+	/* AXI Bridge Configuration */
+
+	rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
+		<< MVPP22_AXI_ATTR_CACHE_OFFS;
+	rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+		<< MVPP22_AXI_ATTR_DOMAIN_OFFS;
+
+	wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
+		<< MVPP22_AXI_ATTR_CACHE_OFFS;
+	wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+		<< MVPP22_AXI_ATTR_DOMAIN_OFFS;
+
+	/* BM */
+	mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
+	mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
+
+	/* Descriptors */
+	mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
+	mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
+	mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
+	mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
+
+	/* Buffer Data */
+	mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
+	mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
+
+	val = MVPP22_AXI_CODE_CACHE_NON_CACHE
+		<< MVPP22_AXI_CODE_CACHE_OFFS;
+	val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
+		<< MVPP22_AXI_CODE_DOMAIN_OFFS;
+	mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
+	mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
+
+	val = MVPP22_AXI_CODE_CACHE_RD_CACHE
+		<< MVPP22_AXI_CODE_CACHE_OFFS;
+	val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+		<< MVPP22_AXI_CODE_DOMAIN_OFFS;
+
+	mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
+
+	val = MVPP22_AXI_CODE_CACHE_WR_CACHE
+		<< MVPP22_AXI_CODE_CACHE_OFFS;
+	val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+		<< MVPP22_AXI_CODE_DOMAIN_OFFS;
+
+	mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
+}
+
 /* Initialize network controller common part HW */
 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 {
@@ -3678,7 +4939,8 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 	u32 val;
 
 	/* Checks for hardware constraints (U-Boot uses only one rxq) */
-	if ((rxq_number > MVPP2_MAX_RXQ) || (txq_number > MVPP2_MAX_TXQ)) {
+	if ((rxq_number > priv->max_port_rxqs) ||
+	    (txq_number > MVPP2_MAX_TXQ)) {
 		dev_err(&pdev->dev, "invalid queue size parameter\n");
 		return -EINVAL;
 	}
@@ -3688,10 +4950,20 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 	if (dram_target_info)
 		mvpp2_conf_mbus_windows(dram_target_info, priv);
 
-	/* Disable HW PHY polling */
-	val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
-	val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
-	writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
+	if (priv->hw_version == MVPP22)
+		mvpp2_axi_init(priv);
+
+	if (priv->hw_version == MVPP21) {
+		/* Disable HW PHY polling */
+		val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
+		val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
+		writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
+	} else {
+		/* Enable HW PHY polling */
+		val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
+		val |= MVPP22_SMI_POLLING_EN;
+		writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
+	}
 
 	/* Allocate and initialize aggregated TXQs */
 	priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
@@ -3712,13 +4984,32 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 	/* Rx Fifo Init */
 	mvpp2_rx_fifo_init(priv);
 
+	/* Tx Fifo Init */
+	if (priv->hw_version == MVPP22)
+		mvpp2_tx_fifo_init(priv);
+
 	/* Reset Rx queue group interrupt configuration */
-	for (i = 0; i < MVPP2_MAX_PORTS; i++)
-		mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i),
-			    CONFIG_MV_ETH_RXQ);
+	for (i = 0; i < MVPP2_MAX_PORTS; i++) {
+		if (priv->hw_version == MVPP21) {
+			mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
+				    CONFIG_MV_ETH_RXQ);
+			continue;
+		} else {
+			u32 val;
+
+			val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
+			mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
+
+			val = (CONFIG_MV_ETH_RXQ <<
+			       MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
+			mvpp2_write(priv,
+				    MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
+		}
+	}
 
-	writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
-	       priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
+	if (priv->hw_version == MVPP21)
+		writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
+		       priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
 
 	/* Allow cache snoop when transmiting packets */
 	mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
@@ -3749,7 +5040,7 @@ static int smi_wait_ready(struct mvpp2 *priv)
 	/* wait till the SMI is not busy */
 	do {
 		/* read smi register */
-		smi_reg = readl(priv->lms_base + MVPP2_SMI);
+		smi_reg = readl(priv->mdio_base);
 		if (timeout-- == 0) {
 			printf("Error: SMI busy timeout\n");
 			return -EFAULT;
@@ -3791,14 +5082,14 @@ static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 		| MVPP2_SMI_OPCODE_READ;
 
 	/* write the smi register */
-	writel(smi_reg, priv->lms_base + MVPP2_SMI);
+	writel(smi_reg, priv->mdio_base);
 
 	/* wait till read value is ready */
 	timeout = MVPP2_SMI_TIMEOUT;
 
 	do {
 		/* read smi register */
-		smi_reg = readl(priv->lms_base + MVPP2_SMI);
+		smi_reg = readl(priv->mdio_base);
 		if (timeout-- == 0) {
 			printf("Err: SMI read ready timeout\n");
 			return -EFAULT;
@@ -3809,7 +5100,7 @@ static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 	for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
 		;
 
-	return readl(priv->lms_base + MVPP2_SMI) & MVPP2_SMI_DATA_MASK;
+	return readl(priv->mdio_base) & MVPP2_SMI_DATA_MASK;
 }
 
 /*
@@ -3846,7 +5137,7 @@ static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 	smi_reg &= ~MVPP2_SMI_OPCODE_READ;
 
 	/* write the smi register */
-	writel(smi_reg, priv->lms_base + MVPP2_SMI);
+	writel(smi_reg, priv->mdio_base);
 
 	return 0;
 }
@@ -3856,7 +5147,7 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
 	struct mvpp2_port *port = dev_get_priv(dev);
 	struct mvpp2_rx_desc *rx_desc;
 	struct mvpp2_bm_pool *bm_pool;
-	dma_addr_t phys_addr;
+	dma_addr_t dma_addr;
 	u32 bm, rx_status;
 	int pool, rx_bytes, err;
 	int rx_received;
@@ -3885,18 +5176,15 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
 		return 0;
 
 	rx_desc = mvpp2_rxq_next_desc_get(rxq);
-	rx_status = rx_desc->status;
-	rx_bytes = rx_desc->data_size - MVPP2_MH_SIZE;
-	phys_addr = rx_desc->buf_phys_addr;
+	rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
+	rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
+	rx_bytes -= MVPP2_MH_SIZE;
+	dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
 
-	bm = mvpp2_bm_cookie_build(rx_desc);
+	bm = mvpp2_bm_cookie_build(port, rx_desc);
 	pool = mvpp2_bm_cookie_pool_get(bm);
 	bm_pool = &port->priv->bm_pools[pool];
 
-	/* Check if buffer header is used */
-	if (rx_status & MVPP2_RXD_BUF_HDR)
-		return 0;
-
 	/* In case of an error, release the requested buffer pointer
 	 * to the Buffer Manager. This request process is controlled
 	 * by the hardware, and the information about the buffer is
@@ -3905,12 +5193,11 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
 	if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
 		mvpp2_rx_error(port, rx_desc);
 		/* Return the buffer to the pool */
-		mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
-				  rx_desc->buf_cookie);
+		mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
 		return 0;
 	}
 
-	err = mvpp2_rx_refill(port, bm_pool, bm, phys_addr);
+	err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
 	if (err) {
 		netdev_err(port->dev, "failed to refill BM pools\n");
 		return 0;
@@ -3921,7 +5208,7 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
 	mvpp2_rxq_status_update(port, rxq->id, 1, 1);
 
 	/* give packet to stack - skip on first n bytes */
-	data = (u8 *)phys_addr + 2 + 32;
+	data = (u8 *)dma_addr + 2 + 32;
 
 	if (rx_bytes <= 0)
 		return 0;
@@ -3963,16 +5250,20 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length)
 
 	/* Get a descriptor for the first part of the packet */
 	tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
-	tx_desc->phys_txq = txq->id;
-	tx_desc->data_size = length;
-	tx_desc->packet_offset = (u32)packet & MVPP2_TX_DESC_ALIGN;
-	tx_desc->buf_phys_addr = (u32)packet & ~MVPP2_TX_DESC_ALIGN;
+	mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
+	mvpp2_txdesc_size_set(port, tx_desc, length);
+	mvpp2_txdesc_offset_set(port, tx_desc,
+				(dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
+	mvpp2_txdesc_dma_addr_set(port, tx_desc,
+				  (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
 	/* First and Last descriptor */
-	tx_desc->command = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
-		| MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
+	mvpp2_txdesc_cmd_set(port, tx_desc,
+			     MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
+			     | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
 
 	/* Flush tx data */
-	flush_dcache_range((u32)packet, (u32)packet + length);
+	flush_dcache_range((unsigned long)packet,
+			   (unsigned long)packet + ALIGN(length, PKTALIGN));
 
 	/* Enable transmit */
 	mb();
@@ -4034,43 +5325,14 @@ static void mvpp2_stop(struct udevice *dev)
 	mvpp2_cleanup_txqs(port);
 }
 
-static int mvpp2_probe(struct udevice *dev)
+static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
 {
-	struct mvpp2_port *port = dev_get_priv(dev);
-	struct mvpp2 *priv = dev_get_priv(dev->parent);
-	int err;
-
-	/* Initialize network controller */
-	err = mvpp2_init(dev, priv);
-	if (err < 0) {
-		dev_err(&pdev->dev, "failed to initialize controller\n");
-		return err;
-	}
+	writel(port->phyaddr, port->priv->iface_base +
+	       MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
 
-	return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv,
-				&buffer_loc.first_rxq);
+	return 0;
 }
 
-static const struct eth_ops mvpp2_ops = {
-	.start		= mvpp2_start,
-	.send		= mvpp2_send,
-	.recv		= mvpp2_recv,
-	.stop		= mvpp2_stop,
-};
-
-static struct driver mvpp2_driver = {
-	.name	= "mvpp2",
-	.id	= UCLASS_ETH,
-	.probe	= mvpp2_probe,
-	.ops	= &mvpp2_ops,
-	.priv_auto_alloc_size = sizeof(struct mvpp2_port),
-	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
-};
-
-/*
- * Use a MISC device to bind the n instances (child nodes) of the
- * network base controller in UCLASS_ETH.
- */
 static int mvpp2_base_probe(struct udevice *dev)
 {
 	struct mvpp2 *priv = dev_get_priv(dev);
@@ -4079,6 +5341,9 @@ static int mvpp2_base_probe(struct udevice *dev)
 	u32 size = 0;
 	int i;
 
+	/* Save hw-version */
+	priv->hw_version = dev_get_driver_data(dev);
+
 	/*
 	 * U-Boot special buffer handling:
 	 *
@@ -4089,35 +5354,66 @@ static int mvpp2_base_probe(struct udevice *dev)
 
 	/* Align buffer area for descs and rx_buffers to 1MiB */
 	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
-	mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
+	mmu_set_region_dcache_behaviour((unsigned long)bd_space,
+					BD_SPACE, DCACHE_OFF);
 
 	buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
 	size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
 
-	buffer_loc.tx_descs = (struct mvpp2_tx_desc *)((u32)bd_space + size);
+	buffer_loc.tx_descs =
+		(struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
 	size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
 
-	buffer_loc.rx_descs = (struct mvpp2_rx_desc *)((u32)bd_space + size);
+	buffer_loc.rx_descs =
+		(struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
 	size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
 
 	for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
-		buffer_loc.bm_pool[i] = (u32 *)((u32)bd_space + size);
-		size += MVPP2_BM_POOL_SIZE_MAX * sizeof(u32);
+		buffer_loc.bm_pool[i] =
+			(unsigned long *)((unsigned long)bd_space + size);
+		if (priv->hw_version == MVPP21)
+			size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
+		else
+			size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
 	}
 
 	for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
-		buffer_loc.rx_buffer[i] = (u32 *)((u32)bd_space + size);
+		buffer_loc.rx_buffer[i] =
+			(unsigned long *)((unsigned long)bd_space + size);
 		size += RX_BUFFER_SIZE;
 	}
 
+	/* Clear the complete area so that all descriptors are cleared */
+	memset(bd_space, 0, size);
+
 	/* Save base addresses for later use */
 	priv->base = (void *)dev_get_addr_index(dev, 0);
 	if (IS_ERR(priv->base))
 		return PTR_ERR(priv->base);
 
-	priv->lms_base = (void *)dev_get_addr_index(dev, 1);
-	if (IS_ERR(priv->lms_base))
-		return PTR_ERR(priv->lms_base);
+	if (priv->hw_version == MVPP21) {
+		priv->lms_base = (void *)dev_get_addr_index(dev, 1);
+		if (IS_ERR(priv->lms_base))
+			return PTR_ERR(priv->lms_base);
+
+		priv->mdio_base = priv->lms_base + MVPP21_SMI;
+	} else {
+		priv->iface_base = (void *)dev_get_addr_index(dev, 1);
+		if (IS_ERR(priv->iface_base))
+			return PTR_ERR(priv->iface_base);
+
+		priv->mdio_base = priv->iface_base + MVPP22_SMI;
+
+		/* Store common base addresses for all ports */
+		priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
+		priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
+		priv->rfu1_base = priv->iface_base + MVPP22_RFU1;
+	}
+
+	if (priv->hw_version == MVPP21)
+		priv->max_port_rxqs = 8;
+	else
+		priv->max_port_rxqs = 32;
 
 	/* Finally create and register the MDIO bus driver */
 	bus = mdio_alloc();
@@ -4135,6 +5431,96 @@ static int mvpp2_base_probe(struct udevice *dev)
 	return mdio_register(bus);
 }
 
+static int mvpp2_probe(struct udevice *dev)
+{
+	struct mvpp2_port *port = dev_get_priv(dev);
+	struct mvpp2 *priv = dev_get_priv(dev->parent);
+	int err;
+
+	/* Only call the probe function for the parent once */
+	if (!priv->probe_done) {
+		err = mvpp2_base_probe(dev->parent);
+		priv->probe_done = 1;
+	}
+
+	port->priv = dev_get_priv(dev->parent);
+
+	err = phy_info_parse(dev, port);
+	if (err)
+		return err;
+
+	/*
+	 * We need the port specific io base addresses at this stage, since
+	 * gop_port_init() accesses these registers
+	 */
+	if (priv->hw_version == MVPP21) {
+		int priv_common_regs_num = 2;
+
+		port->base = (void __iomem *)dev_get_addr_index(
+			dev->parent, priv_common_regs_num + port->id);
+		if (IS_ERR(port->base))
+			return PTR_ERR(port->base);
+	} else {
+		port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+					      "gop-port-id", -1);
+		if (port->id == -1) {
+			dev_err(&pdev->dev, "missing gop-port-id value\n");
+			return -EINVAL;
+		}
+
+		port->base = priv->iface_base + MVPP22_PORT_BASE +
+			port->gop_id * MVPP22_PORT_OFFSET;
+
+		/* Set phy address of the port */
+		mvpp22_smi_phy_addr_cfg(port);
+
+		/* GoP Init */
+		gop_port_init(port);
+	}
+
+	/* Initialize network controller */
+	err = mvpp2_init(dev, priv);
+	if (err < 0) {
+		dev_err(&pdev->dev, "failed to initialize controller\n");
+		return err;
+	}
+
+	err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
+	if (err)
+		return err;
+
+	if (priv->hw_version == MVPP22) {
+		priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id,
+							   port->phy_interface);
+
+		/* Netcomplex configurations for all ports */
+		gop_netc_init(priv, MV_NETC_FIRST_PHASE);
+		gop_netc_init(priv, MV_NETC_SECOND_PHASE);
+	}
+
+	return 0;
+}
+
+static const struct eth_ops mvpp2_ops = {
+	.start		= mvpp2_start,
+	.send		= mvpp2_send,
+	.recv		= mvpp2_recv,
+	.stop		= mvpp2_stop,
+};
+
+static struct driver mvpp2_driver = {
+	.name	= "mvpp2",
+	.id	= UCLASS_ETH,
+	.probe	= mvpp2_probe,
+	.ops	= &mvpp2_ops,
+	.priv_auto_alloc_size = sizeof(struct mvpp2_port),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+
+/*
+ * Use a MISC device to bind the n instances (child nodes) of the
+ * network base controller in UCLASS_ETH.
+ */
 static int mvpp2_base_bind(struct udevice *parent)
 {
 	const void *blob = gd->fdt_blob;
@@ -4145,6 +5531,7 @@ static int mvpp2_base_bind(struct udevice *parent)
 	char *name;
 	int subnode;
 	u32 id;
+	int base_id_add;
 
 	/* Lookup eth driver */
 	drv = lists_uclass_lookup(UCLASS_ETH);
@@ -4153,7 +5540,12 @@ static int mvpp2_base_bind(struct udevice *parent)
 		return -ENOENT;
 	}
 
+	base_id_add = base_id;
+
 	fdt_for_each_subnode(subnode, blob, node) {
+		/* Increment base_id for all subnodes, also the disabled ones */
+		base_id++;
+
 		/* Skip disabled ports */
 		if (!fdtdec_get_is_enabled(blob, subnode))
 			continue;
@@ -4163,6 +5555,7 @@ static int mvpp2_base_bind(struct udevice *parent)
 			return -ENOMEM;
 
 		id = fdtdec_get_int(blob, subnode, "port-id", -1);
+		id += base_id_add;
 
 		name = calloc(1, 16);
 		sprintf(name, "mvpp2-%d", id);
@@ -4176,7 +5569,14 @@ static int mvpp2_base_bind(struct udevice *parent)
 }
 
 static const struct udevice_id mvpp2_ids[] = {
-	{ .compatible = "marvell,armada-375-pp2" },
+	{
+		.compatible = "marvell,armada-375-pp2",
+		.data = MVPP21,
+	},
+	{
+		.compatible = "marvell,armada-7k-pp22",
+		.data = MVPP22,
+	},
 	{ }
 };
 
@@ -4185,6 +5585,5 @@ U_BOOT_DRIVER(mvpp2_base) = {
 	.id	= UCLASS_MISC,
 	.of_match = mvpp2_ids,
 	.bind	= mvpp2_base_bind,
-	.probe	= mvpp2_base_probe,
 	.priv_auto_alloc_size = sizeof(struct mvpp2),
 };
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 6ee8bc3..aca3990 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -103,4 +103,14 @@ config PHY_VITESSE
 config PHY_XILINX
 	bool "Xilinx Ethernet PHYs support"
 
+config PHY_FIXED
+	bool "Fixed-Link PHY"
+	depends on DM_ETH
+	help
+	  Fixed PHY is used for having a 'fixed-link' to another MAC with a direct
+	  connection (MII, RGMII, ...).
+	  There is nothing like autoneogation and so
+	  on, the link is always up with fixed speed and fixed duplex-setting.
+	  More information: doc/device-tree-bindings/net/fixed-link.txt
+
 endif #PHYLIB
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index d372971..88c00a5 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_PHY_TI) += ti.o
 obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o
 obj-$(CONFIG_PHY_VITESSE) += vitesse.o
 obj-$(CONFIG_PHY_MSCC) += mscc.o
+obj-$(CONFIG_PHY_FIXED) += fixed.o
diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c
new file mode 100644
index 0000000..df82356
--- /dev/null
+++ b/drivers/net/phy/fixed.c
@@ -0,0 +1,82 @@
+/*
+ * Fixed-Link phy
+ *
+ * Copyright 2017 Bernecker & Rainer Industrieelektronik GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <phy.h>
+#include <dm.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fixedphy_probe(struct phy_device *phydev)
+{
+	struct fixed_link *priv;
+	int ofnode = phydev->addr;
+	u32 val;
+
+	/* check for mandatory properties within fixed-link node */
+	val = fdt_getprop_u32_default_node(gd->fdt_blob,
+					   ofnode, 0, "speed", 0);
+	if (val != SPEED_10 && val != SPEED_100 && val != SPEED_1000) {
+		printf("ERROR: no/invalid speed given in fixed-link node!");
+		return -EINVAL;
+	}
+
+	priv = malloc(sizeof(*priv));
+	if (!priv)
+		return -ENOMEM;
+	memset(priv, 0, sizeof(*priv));
+
+	phydev->priv = priv;
+	phydev->addr = 0;
+
+	priv->link_speed = val;
+	priv->duplex = fdtdec_get_bool(gd->fdt_blob, ofnode, "full-duplex");
+	priv->pause = fdtdec_get_bool(gd->fdt_blob, ofnode, "pause");
+	priv->asym_pause = fdtdec_get_bool(gd->fdt_blob, ofnode, "asym-pause");
+
+	/* fixed-link phy must not be reset by core phy code */
+	phydev->flags |= PHY_FLAG_BROKEN_RESET;
+
+	return 0;
+}
+
+int fixedphy_startup(struct phy_device *phydev)
+{
+	struct fixed_link *priv = phydev->priv;
+
+	phydev->asym_pause = priv->asym_pause;
+	phydev->pause = priv->pause;
+	phydev->duplex = priv->duplex;
+	phydev->speed = priv->link_speed;
+	phydev->link = 1;
+
+	return 0;
+}
+
+int fixedphy_shutdown(struct phy_device *phydev)
+{
+	return 0;
+}
+
+static struct phy_driver fixedphy_driver = {
+	.uid		= PHY_FIXED_ID,
+	.mask		= 0xffffffff,
+	.name		= "Fixed PHY",
+	.features	= PHY_GBIT_FEATURES | SUPPORTED_MII,
+	.probe		= fixedphy_probe,
+	.startup	= fixedphy_startup,
+	.shutdown	= fixedphy_shutdown,
+};
+
+int phy_fixed_init(void)
+{
+	phy_register(&fixedphy_driver);
+	return 0;
+}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 8db6574..8bacd99 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -515,7 +515,9 @@ int phy_init(void)
 #ifdef CONFIG_PHY_MSCC
 	phy_mscc_init();
 #endif
-
+#ifdef CONFIG_PHY_FIXED
+	phy_fixed_init();
+#endif
 	return 0;
 }
 
@@ -854,9 +856,24 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 		struct eth_device *dev, phy_interface_t interface)
 #endif
 {
-	struct phy_device *phydev;
+	struct phy_device *phydev = NULL;
+#ifdef CONFIG_PHY_FIXED
+	int sn;
+	const char *name;
+	sn = fdt_first_subnode(gd->fdt_blob, dev->of_offset);
+	while (sn > 0) {
+		name = fdt_get_name(gd->fdt_blob, sn, NULL);
+		if (name != NULL && strcmp(name, "fixed-link") == 0) {
+			phydev = phy_device_create(bus,
+						   sn, PHY_FIXED_ID, interface);
+			break;
+		}
+		sn = fdt_next_subnode(gd->fdt_blob, sn);
+	}
+#endif
+	if (phydev == NULL)
+		phydev = phy_find_by_mask(bus, 1 << addr, interface);
 
-	phydev = phy_find_by_mask(bus, 1 << addr, interface);
 	if (phydev)
 		phy_connect_dev(phydev, dev);
 	else
diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h
index 5197f36..a31f6f6 100644
--- a/drivers/net/smc91111.h
+++ b/drivers/net/smc91111.h
@@ -253,8 +253,6 @@ struct smc91111_priv{
 
 #ifdef CONFIG_ADNPESC1
 #define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+((r)<<1))))
-#elif CONFIG_BLACKFIN
-#define	SMC_inw(a,r)	({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;})
 #elif CONFIG_ARM64
 #define	SMC_inw(a, r)	(*((volatile word*)((a)->iobase+((dword)(r)))))
 #else
@@ -264,11 +262,6 @@ struct smc91111_priv{
 
 #ifdef CONFIG_ADNPESC1
 #define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+((r)<<1))) = d)
-#elif CONFIG_BLACKFIN
-#define	SMC_outw(a, d, r)	\
-			({	(*((volatile word*)((a)->iobase+((r)))) = d); \
-				SSYNC(); \
-			})
 #elif CONFIG_ARM64
 #define	SMC_outw(a, d, r)	\
 			(*((volatile word*)((a)->iobase+((dword)(r)))) = d)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index b87210b..a3dbe28 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -21,6 +21,9 @@
 #include <malloc.h>
 #include <miiphy.h>
 #include <net.h>
+#ifdef CONFIG_DM_GPIO
+#include <asm-generic/gpio.h>
+#endif
 
 #define MDIO_CMD_MII_BUSY		BIT(0)
 #define MDIO_CMD_MII_WRITE		BIT(1)
@@ -62,7 +65,7 @@
 
 #define AHB_GATE_OFFSET_EPHY	0
 
-#if defined(CONFIG_MACH_SUN8I_H3)
+#if defined(CONFIG_MACH_SUNXI_H3_H5)
 #define SUN8I_GPD8_GMAC		2
 #else
 #define SUN8I_GPD8_GMAC		4
@@ -128,11 +131,22 @@ struct emac_eth_dev {
 	phys_addr_t sysctl_reg;
 	struct phy_device *phydev;
 	struct mii_dev *bus;
+#ifdef CONFIG_DM_GPIO
+	struct gpio_desc reset_gpio;
+#endif
+};
+
+
+struct sun8i_eth_pdata {
+	struct eth_pdata eth_pdata;
+	u32 reset_delays[3];
 };
 
+
 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 {
-	struct emac_eth_dev *priv = bus->priv;
+	struct udevice *dev = bus->priv;
+	struct emac_eth_dev *priv = dev_get_priv(dev);
 	ulong start;
 	u32 miiaddr = 0;
 	int timeout = CONFIG_MDIO_TIMEOUT;
@@ -164,7 +178,8 @@ static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 			    u16 val)
 {
-	struct emac_eth_dev *priv = bus->priv;
+	struct udevice *dev = bus->priv;
+	struct emac_eth_dev *priv = dev_get_priv(dev);
 	ulong start;
 	u32 miiaddr = 0;
 	int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
@@ -604,7 +619,41 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
 	setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
 }
 
-static int sun8i_mdio_init(const char *name, struct  emac_eth_dev *priv)
+#if defined(CONFIG_DM_GPIO)
+static int sun8i_mdio_reset(struct mii_dev *bus)
+{
+	struct udevice *dev = bus->priv;
+	struct emac_eth_dev *priv = dev_get_priv(dev);
+	struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
+	int ret;
+
+	if (!dm_gpio_is_valid(&priv->reset_gpio))
+		return 0;
+
+	/* reset the phy */
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret)
+		return ret;
+
+	udelay(pdata->reset_delays[0]);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+	if (ret)
+		return ret;
+
+	udelay(pdata->reset_delays[1]);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret)
+		return ret;
+
+	udelay(pdata->reset_delays[2]);
+
+	return 0;
+}
+#endif
+
+static int sun8i_mdio_init(const char *name, struct udevice *priv)
 {
 	struct mii_dev *bus = mdio_alloc();
 
@@ -617,6 +666,9 @@ static int sun8i_mdio_init(const char *name, struct  emac_eth_dev *priv)
 	bus->write = sun8i_mdio_write;
 	snprintf(bus->name, sizeof(bus->name), name);
 	bus->priv = (void *)priv;
+#if defined(CONFIG_DM_GPIO)
+	bus->reset = sun8i_mdio_reset;
+#endif
 
 	return  mdio_register(bus);
 }
@@ -696,7 +748,7 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
 	sun8i_emac_board_setup(priv);
 	sun8i_emac_set_syscon(priv);
 
-	sun8i_mdio_init(dev->name, priv);
+	sun8i_mdio_init(dev->name, dev);
 	priv->bus = miiphy_get_dev_by_name(dev->name);
 
 	return sun8i_phy_init(priv, dev);
@@ -713,11 +765,16 @@ static const struct eth_ops sun8i_emac_eth_ops = {
 
 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
 {
-	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
+	struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
 	struct emac_eth_dev *priv = dev_get_priv(dev);
 	const char *phy_mode;
 	int node = dev_of_offset(dev);
 	int offset = 0;
+#ifdef CONFIG_DM_GPIO
+	int reset_flags = GPIOD_IS_OUT;
+	int ret = 0;
+#endif
 
 	pdata->iobase = dev_get_addr_name(dev, "emac");
 	priv->sysctl_reg = dev_get_addr_name(dev, "syscon");
@@ -762,6 +819,23 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
 	if (!priv->use_internal_phy)
 		parse_phy_pins(dev);
 
+#ifdef CONFIG_DM_GPIO
+	if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+			    "snps,reset-active-low"))
+		reset_flags |= GPIOD_ACTIVE_LOW;
+
+	ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+				   &priv->reset_gpio, reset_flags);
+
+	if (ret == 0) {
+		ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+					   "snps,reset-delays-us",
+					   sun8i_pdata->reset_delays, 3);
+	} else if (ret == -ENOENT) {
+		ret = 0;
+	}
+#endif
+
 	return 0;
 }
 
@@ -782,6 +856,6 @@ U_BOOT_DRIVER(eth_sun8i_emac) = {
 	.probe  = sun8i_emac_eth_probe,
 	.ops    = &sun8i_emac_eth_ops,
 	.priv_auto_alloc_size = sizeof(struct emac_eth_dev),
-	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+	.platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
 	.flags = DM_FLAG_ALLOC_PRIV_DMA,
 };
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 11cd0ea..99339db 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -327,6 +327,20 @@ static void emac_reset(struct emac_eth_dev *priv)
 	udelay(200);
 }
 
+static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr)
+{
+	struct emac_regs *regs = priv->regs;
+	u32 enetaddr_lo, enetaddr_hi;
+
+	enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16);
+	enetaddr_hi = enetaddr[5] | (enetaddr[4] << 8) | (enetaddr[3] << 16);
+
+	writel(enetaddr_hi, &regs->mac_a1);
+	writel(enetaddr_lo, &regs->mac_a0);
+
+	return 0;
+}
+
 static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
 {
 	struct emac_regs *regs = priv->regs;
@@ -350,10 +364,7 @@ static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
 	/* Set up EMAC */
 	emac_setup(priv);
 
-	writel(enetaddr[0] << 16 | enetaddr[1] << 8 | enetaddr[2],
-	       &regs->mac_a1);
-	writel(enetaddr[3] << 16 | enetaddr[4] << 8 | enetaddr[5],
-	       &regs->mac_a0);
+	_sunxi_write_hwaddr(priv, enetaddr);
 
 	mdelay(1);
 
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index a1408f5..40f59c0 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -551,9 +551,10 @@ int dm_pci_hose_probe_bus(struct udevice *bus)
  * pci_match_one_device - Tell if a PCI device structure has a matching
  *                        PCI device id structure
  * @id: single PCI device id structure to match
- * @dev: the PCI device structure to match against
+ * @find: the PCI device id structure to match against
  *
- * Returns the matching pci_device_id structure or %NULL if there is no match.
+ * Returns true if the finding pci_device_id structure matched or false if
+ * there is no match.
  */
 static bool pci_match_one_id(const struct pci_device_id *id,
 			     const struct pci_device_id *find)
diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index 17fa024..d4776a9 100644
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -15,6 +15,7 @@
 #include <dm.h>
 #include <pci.h>
 #include <asm/io.h>
+#include <asm-generic/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -461,6 +462,25 @@ static int pcie_dw_mvebu_probe(struct udevice *dev)
 	struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
 	struct udevice *ctlr = pci_get_controller(dev);
 	struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+#ifdef CONFIG_DM_GPIO
+	struct gpio_desc reset_gpio;
+
+	gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio,
+			     GPIOD_IS_OUT);
+	/*
+	 * Issue reset to add-in card trough the dedicated GPIO.
+	 * Some boards are connecting the card reset pin to common system
+	 * reset wire and others are using separate GPIO port.
+	 * In the last case we have to release a reset of the addon card
+	 * using this GPIO.
+	 */
+	if (dm_gpio_is_valid(&reset_gpio)) {
+		dm_gpio_set_value(&reset_gpio, 1);
+		mdelay(200);
+	}
+#else
+	debug("PCIE Reset on GPIO support is missing\n");
+#endif /* CONFIG_DM_GPIO */
 
 	pcie->first_busno = dev->seq;
 
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index b6806cf..1c5a33a 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -167,6 +167,27 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie)
 	pci_get_regions(pcie->bus, &io, &mem, &pref);
 	idx = PCIE_ATU_REGION_INDEX1 + 1;
 
+	/* Fix the pcie memory map for LS2088A series SoCs */
+	svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+	    svr == SVR_LS2048A || svr == SVR_LS2044A) {
+		if (io)
+			io->phys_start = (io->phys_start &
+					 (PCIE_PHYS_SIZE - 1)) +
+					 LS2088A_PCIE1_PHYS_ADDR +
+					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+		if (mem)
+			mem->phys_start = (mem->phys_start &
+					 (PCIE_PHYS_SIZE - 1)) +
+					 LS2088A_PCIE1_PHYS_ADDR +
+					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+		if (pref)
+			pref->phys_start = (pref->phys_start &
+					 (PCIE_PHYS_SIZE - 1)) +
+					 LS2088A_PCIE1_PHYS_ADDR +
+					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+	}
+
 	if (io)
 		/* ATU : OUTBOUND : IO */
 		ls_pcie_atu_outbound_set(pcie, idx++,
@@ -409,6 +430,11 @@ static void ls_pcie_ep_setup_bars(void *bar_base)
 	ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
 }
 
+static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
+{
+	ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG);
+}
+
 static void ls_pcie_setup_ep(struct ls_pcie *pcie)
 {
 	u32 sriov;
@@ -432,6 +458,8 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie)
 		ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
 		ls_pcie_ep_setup_atu(pcie);
 	}
+
+	ls_pcie_ep_enable_cfg(pcie);
 }
 
 static int ls_pcie_probe(struct udevice *dev)
@@ -442,6 +470,7 @@ static int ls_pcie_probe(struct udevice *dev)
 	u8 header_type;
 	u16 link_sta;
 	bool ep_mode;
+	uint svr;
 	int ret;
 
 	pcie->bus = dev;
@@ -495,6 +524,19 @@ static int ls_pcie_probe(struct udevice *dev)
 		return ret;
 	}
 
+	/*
+	 * Fix the pcie memory map address and PF control registers address
+	 * for LS2088A series SoCs
+	 */
+	svr = get_svr();
+	svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+	    svr == SVR_LS2048A || svr == SVR_LS2044A) {
+		pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
+					LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+		pcie->ctrl = pcie->lut + 0x40000;
+	}
+
 	pcie->cfg0 = map_physmem(pcie->cfg_res.start,
 				 fdt_resource_size(&pcie->cfg_res),
 				 MAP_NOCACHE);
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 1e635ef..e3324a5 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -26,6 +26,10 @@
 #define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
 #endif
 
+#define PCIE_PHYS_SIZE			0x200000000
+#define LS2088A_PCIE_PHYS_SIZE		0x800000000
+#define LS2088A_PCIE1_PHYS_ADDR		0x2000000000
+
 /* iATU registers */
 #define PCIE_ATU_VIEWPORT		0x900
 #define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
@@ -94,8 +98,10 @@
 #define PCIE_LUT_ENTRY_COUNT	32
 
 /* PF Controll registers */
+#define PCIE_PF_CONFIG		0x14
 #define PCIE_PF_VF_CTRL		0x7F8
 #define PCIE_PF_DBG		0x7FC
+#define PCIE_CONFIG_READY	(1 << 0)
 
 #define PCIE_SRDS_PRTCL(idx)	(PCIE1 + (idx))
 #define PCIE_SYS_BASE_ADDR	0x3400000
@@ -107,6 +113,10 @@
 #define SVR_LS102XA		0
 #define SVR_VAR_PER_SHIFT	8
 #define SVR_LS102XA_MASK	0x700
+#define SVR_LS2088A		0x870900
+#define SVR_LS2084A		0x870910
+#define SVR_LS2048A		0x870920
+#define SVR_LS2044A		0x870930
 
 /* LS1021a PCIE space */
 #define LS1021_PCIE_SPACE_OFFSET	0x4000000000ULL
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index 19ede2f..d504bbd 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -15,7 +15,7 @@
 #include <fdt_support.h>
 #include "pcie_layerscape.h"
 
-#ifdef CONFIG_FSL_LSCH3
+#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
 /*
  * Return next available LUT index.
  */
@@ -72,19 +72,26 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
 	u32 *prop;
 	u32 phandle;
 	int nodeoffset;
+	uint svr;
+	char *compat = NULL;
 
 	/* find pci controller node */
 	nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
 						   pcie->dbi_res.start);
 	if (nodeoffset < 0) {
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
-		nodeoffset = fdt_node_offset_by_compat_reg(blob,
-				CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
+		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+		    svr == SVR_LS2048A || svr == SVR_LS2044A)
+			compat = "fsl,ls2088a-pcie";
+		else
+			compat = CONFIG_FSL_PCIE_COMPAT;
+		if (compat)
+			nodeoffset = fdt_node_offset_by_compat_reg(blob,
+					compat, pcie->dbi_res.start);
+#endif
 		if (nodeoffset < 0)
 			return;
-#else
-		return;
-#endif
 	}
 
 	/* get phandle to MSI controller */
@@ -103,6 +110,58 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
 	fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
 }
 
+/*
+ * An iommu-map is a property to be added to the pci controller
+ * node.  It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ *      iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
+ *                 [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
+				       u32 devid, u32 streamid)
+{
+	u32 *prop;
+	u32 iommu_map[4];
+	int nodeoffset;
+	int lenp;
+
+	/* find pci controller node */
+	nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
+						   pcie->dbi_res.start);
+	if (nodeoffset < 0) {
+#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
+		nodeoffset = fdt_node_offset_by_compat_reg(blob,
+				CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
+		if (nodeoffset < 0)
+			return;
+#else
+		return;
+#endif
+	}
+
+	/* get phandle to iommu controller */
+	prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
+	if (prop == NULL) {
+		debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
+		      __func__, pcie->idx);
+		return;
+	}
+
+	/* set iommu-map row */
+	iommu_map[0] = cpu_to_fdt32(devid);
+	iommu_map[1] = *++prop;
+	iommu_map[2] = cpu_to_fdt32(streamid);
+	iommu_map[3] = cpu_to_fdt32(1);
+
+	if (devid == 0) {
+		fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
+				    iommu_map, 16);
+	} else {
+		fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
+	}
+}
+
 static void fdt_fixup_pcie(void *blob)
 {
 	struct udevice *dev, *bus;
@@ -139,6 +198,9 @@ static void fdt_fixup_pcie(void *blob)
 		/* update msi-map in device tree */
 		fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
 					   streamid);
+		/* update iommu-map in device tree */
+		fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
+					     streamid);
 	}
 }
 #endif
@@ -146,19 +208,25 @@ static void fdt_fixup_pcie(void *blob)
 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
 {
 	int off;
+	uint svr;
+	char *compat = NULL;
 
 	off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
 					    pcie->dbi_res.start);
 	if (off < 0) {
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
-		off = fdt_node_offset_by_compat_reg(blob,
-						    CONFIG_FSL_PCIE_COMPAT,
-						    pcie->dbi_res.start);
+		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+		    svr == SVR_LS2048A || svr == SVR_LS2044A)
+			compat = "fsl,ls2088a-pcie";
+		else
+			compat = CONFIG_FSL_PCIE_COMPAT;
+		if (compat)
+			off = fdt_node_offset_by_compat_reg(blob,
+					compat, pcie->dbi_res.start);
+#endif
 		if (off < 0)
 			return;
-#else
-		return;
-#endif
 	}
 
 	if (pcie->enabled)
@@ -175,7 +243,7 @@ void ft_pci_setup(void *blob, bd_t *bd)
 	list_for_each_entry(pcie, &ls_pcie_list, list)
 		ft_pcie_ls_setup(blob, pcie);
 
-#ifdef CONFIG_FSL_LSCH3
+#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
 	fdt_fixup_pcie(blob);
 #endif
 }
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index f3e3072..9d0f501 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -133,7 +133,7 @@ config ROCKCHIP_RK3036_PINCTRL
 	  function.
 
 config ROCKCHIP_RK3188_PINCTRL
-	bool "Rockchip pin control driver"
+	bool "Rockchip rk3188 pin control driver"
 	depends on DM
 	help
 	  Support pin multiplexing control on Rockchip rk3188 SoCs. The driver
@@ -142,7 +142,7 @@ config ROCKCHIP_RK3188_PINCTRL
 	  function.
 
 config ROCKCHIP_RK3288_PINCTRL
-	bool "Rockchip pin control driver"
+	bool "Rockchip rk3288 pin control driver"
 	depends on DM
 	help
 	  Support pin multiplexing control on Rockchip rk3288 SoCs. The driver
@@ -158,7 +158,7 @@ config PINCTRL_AT91PIO4
 	  controller which is available on SAMA5D2 SoC.
 
 config ROCKCHIP_RK3328_PINCTRL
-	bool "Rockchip pin control driver"
+	bool "Rockchip rk3328 pin control driver"
 	depends on DM
 	help
 	  Support pin multiplexing control on Rockchip rk3328 SoCs. The driver
@@ -167,7 +167,7 @@ config ROCKCHIP_RK3328_PINCTRL
 	  function.
 
 config ROCKCHIP_RK3399_PINCTRL
-	bool "Rockchip pin control driver"
+	bool "Rockchip rk3399 pin control driver"
 	depends on DM
 	help
 	  Support pin multiplexing control on Rockchip rk3399 SoCs. The driver
@@ -212,6 +212,16 @@ config PINCTRL_STM32
 	  definitions and pin control functions for each available multiplex
 	  function.
 
+config PINCTRL_SINGLE
+	bool "Single register pin-control and pin-multiplex driver"
+	depends on DM
+	help
+	  This enables pinctrl driver for systems using a single register for
+	  pin configuration and multiplexing. TI's AM335X SoCs are examples of
+	  such systems.
+	  Depending on the platform make sure to also enable OF_TRANSLATE and
+	  eventually SPL_OF_TRANSLATE to get correct address translations.
+
 endif
 
 source "drivers/pinctrl/meson/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index b04ca86..2ac9c19 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,5 +16,6 @@ obj-$(CONFIG_PIC32_PINCTRL)	+= pinctrl_pic32.o
 obj-$(CONFIG_PINCTRL_EXYNOS)	+= exynos/
 obj-$(CONFIG_PINCTRL_MESON)	+= meson/
 obj-$(CONFIG_PINCTRL_MVEBU)	+= mvebu/
+obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o
 obj-$(CONFIG_PINCTRL_STI)	+= pinctrl-sti.o
 obj-$(CONFIG_PINCTRL_STM32)	+= pinctrl_stm32.o
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
new file mode 100644
index 0000000..d2dcec0
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+#include <libfdt.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct single_pdata {
+	fdt_addr_t base;	/* first configuration register */
+	int offset;		/* index of last configuration register */
+	u32 mask;		/* configuration-value mask bits */
+	int width;		/* configuration register bit width */
+};
+
+struct single_fdt_pin_cfg {
+	fdt32_t reg;		/* configuration register offset */
+	fdt32_t val;		/* configuration register value */
+};
+
+/**
+ * single_configure_pins() - Configure pins based on FDT data
+ *
+ * @dev: Pointer to single pin configuration device which is the parent of
+ *       the pins node holding the pin configuration data.
+ * @pins: Pointer to the first element of an array of register/value pairs
+ *        of type 'struct single_fdt_pin_cfg'. Each such pair describes the
+ *        the pin to be configured and the value to be used for configuration.
+ *        This pointer points to a 'pinctrl-single,pins' property in the
+ *        device-tree.
+ * @size: Size of the 'pins' array in bytes.
+ *        The number of register/value pairs in the 'pins' array therefore
+ *        equals to 'size / sizeof(struct single_fdt_pin_cfg)'.
+ */
+static int single_configure_pins(struct udevice *dev,
+				 const struct single_fdt_pin_cfg *pins,
+				 int size)
+{
+	struct single_pdata *pdata = dev->platdata;
+	int count = size / sizeof(struct single_fdt_pin_cfg);
+	int n, reg;
+	u32 val;
+
+	for (n = 0; n < count; n++) {
+		reg = fdt32_to_cpu(pins->reg);
+		if ((reg < 0) || (reg > pdata->offset)) {
+			dev_dbg(dev, "  invalid register offset 0x%08x\n", reg);
+			pins++;
+			continue;
+		}
+		reg += pdata->base;
+		switch (pdata->width) {
+		case 32:
+			val = readl(reg) & ~pdata->mask;
+			val |= fdt32_to_cpu(pins->val) & pdata->mask;
+			writel(val, reg);
+			dev_dbg(dev, "  reg/val 0x%08x/0x%08x\n",
+				reg, val);
+			break;
+		default:
+			dev_warn(dev, "unsupported register width %i\n",
+				 pdata->width);
+		}
+		pins++;
+	}
+	return 0;
+}
+
+static int single_set_state(struct udevice *dev,
+			    struct udevice *config)
+{
+	const void *fdt = gd->fdt_blob;
+	const struct single_fdt_pin_cfg *prop;
+	int len;
+
+	prop = fdt_getprop(fdt, config->of_offset, "pinctrl-single,pins", &len);
+	if (prop) {
+		dev_dbg(dev, "configuring pins for %s\n", config->name);
+		if (len % sizeof(struct single_fdt_pin_cfg)) {
+			dev_dbg(dev, "  invalid pin configuration in fdt\n");
+			return -FDT_ERR_BADSTRUCTURE;
+		}
+		single_configure_pins(dev, prop, len);
+		len = 0;
+	}
+
+	return len;
+}
+
+static int single_ofdata_to_platdata(struct udevice *dev)
+{
+	fdt_addr_t addr;
+	u32 of_reg[2];
+	int res;
+	struct single_pdata *pdata = dev->platdata;
+
+	pdata->width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+				      "pinctrl-single,register-width", 0);
+
+	res = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+				   "reg", of_reg, 2);
+	if (res)
+		return res;
+	pdata->offset = of_reg[1] - pdata->width / 8;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE) {
+		dev_dbg(dev, "no valid base register address\n");
+		return -EINVAL;
+	}
+	pdata->base = addr;
+
+	pdata->mask = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+				     "pinctrl-single,function-mask",
+				     0xffffffff);
+	return 0;
+}
+
+const struct pinctrl_ops single_pinctrl_ops = {
+	.set_state = single_set_state,
+};
+
+static const struct udevice_id single_pinctrl_match[] = {
+	{ .compatible = "pinctrl-single" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(single_pinctrl) = {
+	.name = "single-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = single_pinctrl_match,
+	.ops = &single_pinctrl_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+	.platdata_auto_alloc_size = sizeof(struct single_pdata),
+	.ofdata_to_platdata = single_ofdata_to_platdata,
+};
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index a74793a..507bec4 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -202,6 +202,39 @@ static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
 	}
 }
 
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id)
+{
+	rk_clrsetreg(&grf->gpio3a_iomux,
+		     GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK |
+		     GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK |
+		     GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK |
+		     GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK,
+		     GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT |
+		     GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT |
+		     GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT |
+		     GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT |
+		     GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT |
+		     GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT |
+		     GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT |
+		     GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT);
+	rk_clrsetreg(&grf->gpio3b_iomux,
+		     GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK |
+					    GRF_GPIO3B3_SEL_MASK |
+		     GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK |
+		     GRF_GPIO3B6_SEL_MASK,
+		     GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT |
+		     GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT |
+		     GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT |
+		     GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT |
+		     GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT |
+		     GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT);
+	rk_clrsetreg(&grf->gpio3c_iomux,
+		     GRF_GPIO3C1_SEL_MASK,
+		     GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT);
+}
+#endif
+
 static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
 {
 	struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
@@ -243,6 +276,11 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
 	case PERIPH_ID_SDMMC1:
 		pinctrl_rk3399_sdmmc_config(priv->grf, func);
 		break;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+	case PERIPH_ID_GMAC:
+		pinctrl_rk3399_gmac_config(priv->grf, func);
+		break;
+#endif
 	default:
 		return -EINVAL;
 	}
@@ -283,6 +321,10 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
 		return PERIPH_ID_I2C5;
 	case 65:
 		return PERIPH_ID_SDMMC1;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+	case 12:
+		return PERIPH_ID_GMAC;
+#endif
 	}
 #endif
 	return -ENOENT;
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index f2c5629..64e5bc2 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -12,7 +12,7 @@ choice
 	default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 	default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
 	default AXP818_POWER if MACH_SUN8I_A83T
-	default SUNXI_NO_PMIC if MACH_SUN8I_H3 || MACH_SUN50I
+	default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I
 
 config SUNXI_NO_PMIC
 	bool "board without a pmic"
@@ -60,7 +60,7 @@ config AXP818_POWER
 
 config SY8106A_POWER
 	bool "SY8106A pmic support"
-	depends on MACH_SUN8I_H3
+	depends on MACH_SUNXI_H3_H5
 	---help---
 	Select this to enable support for the SY8106A pmic found on some
 	H3 boards.
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c42b0bc..fa77ee4 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -20,6 +20,14 @@ config SANDBOX_RESET
 	  simply accepts requests to reset various HW modules without actually
 	  doing anything beyond a little error checking.
 
+config STI_RESET
+	bool "Enable the STi reset"
+	depends on ARCH_STI
+	help
+	  Support for reset controllers on STMicroelectronics STiH407 family SoCs.
+	  Say Y if you want to control reset signals provided by system config
+	  block.
+
 config TEGRA_CAR_RESET
 	bool "Enable Tegra CAR-based reset driver"
 	depends on TEGRA_CAR
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 5c4305c..2b96396 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -5,6 +5,7 @@
 obj-$(CONFIG_DM_RESET) += reset-uclass.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
+obj-$(CONFIG_STI_RESET) += sti-reset.o
 obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
 obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c
new file mode 100644
index 0000000..0c32a3d
--- /dev/null
+++ b/drivers/reset/sti-reset.c
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2017
+ * Patrice Chotard <patrice.chotard@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <wait_bit.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <dt-bindings/reset/stih407-resets.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sti_reset {
+	const struct syscfg_reset_controller_data *data;
+};
+
+/**
+ * Reset channel description for a system configuration register based
+ * reset controller.
+ *
+ * @compatible: Compatible string of the syscon containing this
+ *              channel's control and ack (status) bits.
+ * @reset_offset: Reset register offset in sysconf bank.
+ * @reset_bit: Bit number in reset register.
+ * @ack_offset: Ack reset register offset in syscon bank.
+ * @ack_bit: Bit number in Ack reset register.
+ */
+
+struct syscfg_reset_channel_data {
+	const char *compatible;
+	int reset_offset;
+	int reset_bit;
+	int ack_offset;
+	int ack_bit;
+};
+
+/**
+ * Description of a system configuration register based reset controller.
+ *
+ * @wait_for_ack: The controller will wait for reset assert and de-assert to
+ *                be "ack'd" in a channel's ack field.
+ * @active_low: Are the resets in this controller active low, i.e. clearing
+ *              the reset bit puts the hardware into reset.
+ * @nr_channels: The number of reset channels in this controller.
+ * @channels: An array of reset channel descriptions.
+ */
+struct syscfg_reset_controller_data {
+	bool wait_for_ack;
+	bool active_low;
+	int nr_channels;
+	const struct syscfg_reset_channel_data *channels;
+};
+
+/* STiH407 Peripheral powerdown definitions. */
+static const char stih407_core[] = "st,stih407-core-syscfg";
+static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
+static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
+
+#define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab)		\
+	{ .compatible	= _c,				\
+	  .reset_offset	= _rr,				\
+	  .reset_bit	= _rb,				\
+	  .ack_offset	= _ar,				\
+	  .ack_bit	= _ab,				}
+
+#define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb)		\
+	{ .compatible	= _c,				\
+	  .reset_offset	= _rr,				\
+	  .reset_bit	= _rb,				}
+
+#define STIH407_SRST_CORE(_reg, _bit) \
+	_SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
+
+#define STIH407_SRST_SBC(_reg, _bit) \
+	_SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
+
+#define STIH407_SRST_LPM(_reg, _bit) \
+	_SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
+
+#define STIH407_PDN_0(_bit) \
+	_SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
+#define STIH407_PDN_1(_bit) \
+	_SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
+#define STIH407_PDN_ETH(_bit, _stat) \
+	_SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
+
+/* Powerdown requests control 0 */
+#define SYSCFG_5000	0x0
+#define SYSSTAT_5500	0x7d0
+/* Powerdown requests control 1 (High Speed Links) */
+#define SYSCFG_5001	0x4
+#define SYSSTAT_5501	0x7d4
+
+/* Ethernet powerdown/status/reset */
+#define SYSCFG_4032	0x80
+#define SYSSTAT_4520	0x820
+#define SYSCFG_4002	0x8
+
+static const struct syscfg_reset_channel_data stih407_powerdowns[] = {
+	[STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1),
+	[STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
+	[STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6),
+	[STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5),
+	[STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4),
+	[STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3),
+	[STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2),
+	[STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1),
+	[STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
+	[STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2),
+};
+
+/* Reset Generator control 0/1 */
+#define SYSCFG_5128	0x200
+#define SYSCFG_5131	0x20c
+#define SYSCFG_5132	0x210
+
+#define LPM_SYSCFG_1	0x4	/* Softreset IRB & SBC UART */
+
+static const struct syscfg_reset_channel_data stih407_softresets[] = {
+	[STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4),
+	[STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3),
+	[STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28),
+	[STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29),
+	[STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30),
+	[STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6),
+	[STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6),
+	[STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15),
+	[STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7),
+	[STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16),
+	[STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4),
+	[STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13),
+	[STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22),
+	[STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5),
+	[STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14),
+	[STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3),
+	[STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10),
+	[STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11),
+	[STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12),
+	[STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14),
+	[STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15),
+	[STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21),
+	[STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23),
+	[STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24),
+	[STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30),
+	[STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0),
+	[STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1),
+	[STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2),
+	[STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8),
+	[STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26),
+	[STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27),
+	[STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28),
+	[STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2),
+};
+
+/* PicoPHY reset/control */
+#define SYSCFG_5061	0x0f4
+
+static const struct syscfg_reset_channel_data stih407_picophyresets[] = {
+	[STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5),
+	[STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6),
+	[STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7),
+};
+
+static const struct
+syscfg_reset_controller_data stih407_powerdown_controller = {
+	.wait_for_ack = true,
+	.nr_channels = ARRAY_SIZE(stih407_powerdowns),
+	.channels = stih407_powerdowns,
+};
+
+static const struct
+syscfg_reset_controller_data stih407_softreset_controller = {
+	.wait_for_ack = false,
+	.active_low = true,
+	.nr_channels = ARRAY_SIZE(stih407_softresets),
+	.channels = stih407_softresets,
+};
+
+static const struct
+syscfg_reset_controller_data stih407_picophyreset_controller = {
+	.wait_for_ack = false,
+	.nr_channels = ARRAY_SIZE(stih407_picophyresets),
+	.channels = stih407_picophyresets,
+};
+
+phys_addr_t sti_reset_get_regmap(const char *compatible)
+{
+	struct udevice *syscon;
+	struct regmap *regmap;
+	int node, ret;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+					     compatible);
+	if (node < 0) {
+		error("unable to find %s node\n", compatible);
+		return node;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_SYSCON, node, &syscon);
+	if (ret) {
+		error("%s: uclass_get_device_by_of_offset failed: %d\n",
+		      __func__, ret);
+		return ret;
+	}
+
+	regmap = syscon_get_regmap(syscon);
+	if (!regmap) {
+		error("unable to get regmap for %s\n", syscon->name);
+		return -ENODEV;
+	}
+
+	return regmap->base;
+}
+
+static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert)
+{
+	struct udevice *dev = reset_ctl->dev;
+	struct syscfg_reset_controller_data *reset_desc =
+		(struct syscfg_reset_controller_data *)(dev->driver_data);
+	struct syscfg_reset_channel_data ch;
+	phys_addr_t base;
+	u32 ctrl_val = reset_desc->active_low ? !assert : !!assert;
+	void __iomem *reg;
+
+	/* check if reset id is inside available range */
+	if (reset_ctl->id >= reset_desc->nr_channels)
+		return -EINVAL;
+
+	/* get reset sysconf register base address */
+	base = sti_reset_get_regmap(reset_desc->channels[reset_ctl->id].compatible);
+
+	ch = reset_desc->channels[reset_ctl->id];
+	reg = (void __iomem *)base + ch.reset_offset;
+
+	if (ctrl_val)
+		generic_set_bit(ch.reset_bit, reg);
+	else
+		generic_clear_bit(ch.reset_bit, reg);
+
+	if (!reset_desc->wait_for_ack)
+		return 0;
+
+	reg = (void __iomem *)base + ch.ack_offset;
+	if (wait_for_bit(__func__, reg, BIT(ch.ack_bit), ctrl_val,
+			 1000, false)) {
+		error("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n",
+		      reset_ctl, reset_ctl->dev, reset_ctl->id);
+
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static int sti_reset_request(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int sti_reset_free(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int sti_reset_assert(struct reset_ctl *reset_ctl)
+{
+	return sti_reset_program_hw(reset_ctl, true);
+}
+
+static int sti_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	return sti_reset_program_hw(reset_ctl, false);
+}
+
+struct reset_ops sti_reset_ops = {
+	.request = sti_reset_request,
+	.free = sti_reset_free,
+	.rst_assert = sti_reset_assert,
+	.rst_deassert = sti_reset_deassert,
+};
+
+static int sti_reset_probe(struct udevice *dev)
+{
+	struct sti_reset *priv = dev_get_priv(dev);
+
+	priv->data = (void *)dev_get_driver_data(dev);
+
+	return 0;
+}
+
+static const struct udevice_id sti_reset_ids[] = {
+	{
+		.compatible = "st,stih407-picophyreset",
+		.data = (ulong)&stih407_picophyreset_controller,
+	},
+	{
+		.compatible = "st,stih407-powerdown",
+		.data = (ulong)&stih407_powerdown_controller,
+	},
+	{
+		.compatible = "st,stih407-softreset",
+		.data = (ulong)&stih407_softreset_controller,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(sti_reset) = {
+	.name = "sti_reset",
+	.id = UCLASS_RESET,
+	.of_match = sti_reset_ids,
+	.probe = sti_reset_probe,
+	.priv_auto_alloc_size = sizeof(struct sti_reset),
+	.ops = &sti_reset_ops,
+};
diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c
index 300e9b3..89312c5 100644
--- a/drivers/rtc/rtc-uclass.c
+++ b/drivers/rtc/rtc-uclass.c
@@ -60,6 +60,36 @@ int rtc_write8(struct udevice *dev, unsigned int reg, int val)
 	return ops->write8(dev, reg, val);
 }
 
+int rtc_read16(struct udevice *dev, unsigned int reg, u16 *valuep)
+{
+	u16 value = 0;
+	int ret;
+	int i;
+
+	for (i = 0; i < sizeof(value); i++) {
+		ret = rtc_read8(dev, reg + i);
+		if (ret < 0)
+			return ret;
+		value |= ret << (i << 3);
+	}
+
+	*valuep = value;
+	return 0;
+}
+
+int rtc_write16(struct udevice *dev, unsigned int reg, u16 value)
+{
+	int i, ret;
+
+	for (i = 0; i < sizeof(value); i++) {
+		ret = rtc_write8(dev, reg + i, (value >> (i << 3)) & 0xff);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
 int rtc_read32(struct udevice *dev, unsigned int reg, u32 *valuep)
 {
 	u32 value = 0;
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index ca56a7e..c0ec2ec 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -53,6 +53,26 @@ config DM_SERIAL
 	  implements serial_putc() etc. The uclass interface is
 	  defined in include/serial.h.
 
+config SPL_DM_SERIAL
+	bool "Enable Driver Model for serial drivers"
+	depends on DM_SERIAL
+	default y if SPL && DM_SERIAL
+	help
+	  Enable driver model for serial in SPL. This replaces
+	  drivers/serial/serial.c with the serial uclass, which
+	  implements serial_putc() etc. The uclass interface is
+	  defined in include/serial.h.
+
+config TPL_DM_SERIAL
+	bool "Enable Driver Model for serial drivers"
+	depends on DM_SERIAL
+	default y if TPL && DM_SERIAL
+	help
+	  Enable driver model for serial in TPL. This replaces
+	  drivers/serial/serial.c with the serial uclass, which
+	  implements serial_putc() etc. The uclass interface is
+	  defined in include/serial.h.
+
 config DEBUG_UART
 	bool "Enable an early debug UART for debugging"
 	help
@@ -356,6 +376,15 @@ config SYS_NS16550
 	  be used. It can be a constant or a function to get clock, eg,
 	  get_serial_clock().
 
+config INTEL_MID_SERIAL
+	bool "Intel MID platform UART support"
+	depends on DM_SERIAL && OF_CONTROL
+	depends on INTEL_MID
+	select SYS_NS16550
+	help
+	  Select this to enable a UART for Intel MID platforms.
+	  This uses the ns16550 driver as a library.
+
 config ROCKCHIP_SERIAL
 	bool "Rockchip on-chip UART support"
 	depends on DM_SERIAL && SPL_OF_PLATDATA
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 84a22ce..4382cf9 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -6,7 +6,7 @@
 #
 
 ifdef CONFIG_DM_SERIAL
-obj-y += serial-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)DM_SERIAL) += serial-uclass.o
 obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
 else
 obj-y += serial.o
@@ -28,6 +28,7 @@ obj-$(CONFIG_S5P) += serial_s5p.o
 obj-$(CONFIG_MXC_UART) += serial_mxc.o
 obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
 obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
+obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
 endif
@@ -35,7 +36,6 @@ obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
 obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
 obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
 obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
-obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
 obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
 obj-$(CONFIG_FSL_LINFLEXUART) += serial_linflexuart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
diff --git a/drivers/serial/serial_bfin.c b/drivers/serial/serial_bfin.c
deleted file mode 100644
index 1d5be2a..0000000
--- a/drivers/serial/serial_bfin.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * U-Boot - serial.c Blackfin Serial Driver
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Copyright (c) 2003	Bas Vermeulen <bas@buyways.nl>,
- *			BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on:
- * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
- * Copyright(c) 2003	Metrowerks	<mwaddel@metrowerks.com>
- * Copyright(c)	2001	Tony Z. Kou	<tonyko@arcturusnetworks.com>
- * Copyright(c)	2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328 version serial driver imlpementation which was:
- * Copyright (C) 1995       David S. Miller    <davem@caip.rutgers.edu>
- * Copyright (C) 1998       Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne     <jeff@uclinux.org>
- * Copyright (C) 1999       Vladimir Gurevich  <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-/* Anomaly notes:
- *  05000086 - we don't support autobaud
- *  05000099 - we only use DR bit, so losing others is not a problem
- *  05000100 - we don't use the UART_IIR register
- *  05000215 - we poll the uart (no dma/interrupts)
- *  05000225 - no workaround possible, but this shouldnt cause errors ...
- *  05000230 - we tweak the baud rate calculation slightly
- *  05000231 - we always use 1 stop bit
- *  05000309 - we always enable the uart before we modify it in anyway
- *  05000350 - we always enable the uart regardless of boot mode
- *  05000363 - we don't support break signals, so don't generate one
- */
-
-#include <common.h>
-#include <post.h>
-#include <watchdog.h>
-#include <serial.h>
-#include <linux/compiler.h>
-#include <asm/blackfin.h>
-#include <asm/serial.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_UART_CONSOLE
-
-#ifdef CONFIG_DEBUG_SERIAL
-static uart_lsr_t cached_lsr[256];
-static uart_lsr_t cached_rbr[256];
-static size_t cache_count;
-
-/* The LSR is read-to-clear on some parts, so we have to make sure status
- * bits aren't inadvertently lost when doing various tests.  This also
- * works around anomaly 05000099 at the same time by keeping a cumulative
- * tally of all the status bits.
- */
-static uart_lsr_t uart_lsr_save;
-static uart_lsr_t uart_lsr_read(uint32_t uart_base)
-{
-	uart_lsr_t lsr = _lsr_read(pUART);
-	uart_lsr_save |= (lsr & (OE|PE|FE|BI));
-	return lsr | uart_lsr_save;
-}
-/* Just do the clear for everyone since it can't hurt. */
-static void uart_lsr_clear(uint32_t uart_base)
-{
-	uart_lsr_save = 0;
-	_lsr_write(pUART, -1);
-}
-#else
-/* When debugging is disabled, we only care about the DR bit, so if other
- * bits get set/cleared, we don't really care since we don't read them
- * anyways (and thus anomaly 05000099 is irrelevant).
- */
-static inline uart_lsr_t uart_lsr_read(uint32_t uart_base)
-{
-	return _lsr_read(pUART);
-}
-static void uart_lsr_clear(uint32_t uart_base)
-{
-	_lsr_write(pUART, -1);
-}
-#endif
-
-static void uart_putc(uint32_t uart_base, const char c)
-{
-	/* send a \r for compatibility */
-	if (c == '\n')
-		serial_putc('\r');
-
-	WATCHDOG_RESET();
-
-	/* wait for the hardware fifo to clear up */
-	while (!(uart_lsr_read(uart_base) & THRE))
-		continue;
-
-	/* queue the character for transmission */
-	bfin_write(&pUART->thr, c);
-	SSYNC();
-
-	WATCHDOG_RESET();
-}
-
-static int uart_tstc(uint32_t uart_base)
-{
-	WATCHDOG_RESET();
-	return (uart_lsr_read(uart_base) & DR) ? 1 : 0;
-}
-
-static int uart_getc(uint32_t uart_base)
-{
-	uint16_t uart_rbr_val;
-
-	/* wait for data ! */
-	while (!uart_tstc(uart_base))
-		continue;
-
-	/* grab the new byte */
-	uart_rbr_val = bfin_read(&pUART->rbr);
-
-#ifdef CONFIG_DEBUG_SERIAL
-	/* grab & clear the LSR */
-	uart_lsr_t uart_lsr_val = uart_lsr_read(uart_base);
-
-	cached_lsr[cache_count] = uart_lsr_val;
-	cached_rbr[cache_count] = uart_rbr_val;
-	cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr);
-
-	if (uart_lsr_val & (OE|PE|FE|BI)) {
-		printf("\n[SERIAL ERROR]\n");
-		do {
-			--cache_count;
-			printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count,
-				cached_rbr[cache_count], cached_lsr[cache_count]);
-		} while (cache_count > 0);
-		return -1;
-	}
-#endif
-	uart_lsr_clear(uart_base);
-
-	return uart_rbr_val;
-}
-
-#if CONFIG_POST & CONFIG_SYS_POST_UART
-# define LOOP(x) x
-#else
-# define LOOP(x)
-#endif
-
-#if BFIN_UART_HW_VER < 4
-
-LOOP(
-static void uart_loop(uint32_t uart_base, int state)
-{
-	u16 mcr;
-
-	/* Drain the TX fifo first so bytes don't come back */
-	while (!(uart_lsr_read(uart_base) & TEMT))
-		continue;
-
-	mcr = bfin_read(&pUART->mcr);
-	if (state)
-		mcr |= LOOP_ENA | MRTS;
-	else
-		mcr &= ~(LOOP_ENA | MRTS);
-	bfin_write(&pUART->mcr, mcr);
-}
-)
-
-#else
-
-LOOP(
-static void uart_loop(uint32_t uart_base, int state)
-{
-	u32 control;
-
-	/* Drain the TX fifo first so bytes don't come back */
-	while (!(uart_lsr_read(uart_base) & TEMT))
-		continue;
-
-	control = bfin_read(&pUART->control);
-	if (state)
-		control |= LOOP_ENA | MRTS;
-	else
-		control &= ~(LOOP_ENA | MRTS);
-	bfin_write(&pUART->control, control);
-}
-)
-
-#endif
-
-static inline void __serial_set_baud(uint32_t uart_base, uint32_t baud)
-{
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-	serial_early_set_baud(uart_base, baud);
-#else
-	uint16_t divisor = (get_uart_clk() + (baud * 8)) / (baud * 16)
-			- ANOMALY_05000230;
-
-	/* Program the divisor to get the baud rate we want */
-	serial_set_divisor(uart_base, divisor);
-#endif
-}
-
-static void uart_puts(uint32_t uart_base, const char *s)
-{
-	while (*s)
-		uart_putc(uart_base, *s++);
-}
-
-#define DECL_BFIN_UART(n) \
-static int uart##n##_init(void) \
-{ \
-	const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \
-	peripheral_request_list(pins, "bfin-uart"); \
-	uart_init(MMR_UART(n)); \
-	__serial_set_baud(MMR_UART(n), gd->baudrate); \
-	uart_lsr_clear(MMR_UART(n)); \
-	return 0; \
-} \
-\
-static int uart##n##_uninit(void) \
-{ \
-	return serial_early_uninit(MMR_UART(n)); \
-} \
-\
-static void uart##n##_setbrg(void) \
-{ \
-	__serial_set_baud(MMR_UART(n), gd->baudrate); \
-} \
-\
-static int uart##n##_getc(void) \
-{ \
-	return uart_getc(MMR_UART(n)); \
-} \
-\
-static int uart##n##_tstc(void) \
-{ \
-	return uart_tstc(MMR_UART(n)); \
-} \
-\
-static void uart##n##_putc(const char c) \
-{ \
-	uart_putc(MMR_UART(n), c); \
-} \
-\
-static void uart##n##_puts(const char *s) \
-{ \
-	uart_puts(MMR_UART(n), s); \
-} \
-\
-LOOP( \
-static void uart##n##_loop(int state) \
-{ \
-	uart_loop(MMR_UART(n), state); \
-} \
-) \
-\
-struct serial_device bfin_serial##n##_device = { \
-	.name   = "bfin_uart"#n, \
-	.start  = uart##n##_init, \
-	.stop   = uart##n##_uninit, \
-	.setbrg = uart##n##_setbrg, \
-	.getc   = uart##n##_getc, \
-	.tstc   = uart##n##_tstc, \
-	.putc   = uart##n##_putc, \
-	.puts   = uart##n##_puts, \
-	LOOP(.loop = uart##n##_loop) \
-};
-
-#ifdef UART0_RBR
-DECL_BFIN_UART(0)
-#endif
-#ifdef UART1_RBR
-DECL_BFIN_UART(1)
-#endif
-#ifdef UART2_RBR
-DECL_BFIN_UART(2)
-#endif
-#ifdef UART3_RBR
-DECL_BFIN_UART(3)
-#endif
-
-__weak struct serial_device *default_serial_console(void)
-{
-#if CONFIG_UART_CONSOLE == 0
-	return &bfin_serial0_device;
-#elif CONFIG_UART_CONSOLE == 1
-	return &bfin_serial1_device;
-#elif CONFIG_UART_CONSOLE == 2
-	return &bfin_serial2_device;
-#elif CONFIG_UART_CONSOLE == 3
-	return &bfin_serial3_device;
-#endif
-}
-
-void bfin_serial_initialize(void)
-{
-#ifdef UART0_RBR
-	serial_register(&bfin_serial0_device);
-#endif
-#ifdef UART1_RBR
-	serial_register(&bfin_serial1_device);
-#endif
-#ifdef UART2_RBR
-	serial_register(&bfin_serial2_device);
-#endif
-#ifdef UART3_RBR
-	serial_register(&bfin_serial3_device);
-#endif
-}
-
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-inline void uart_early_putc(uint32_t uart_base, const char c)
-{
-	/* send a \r for compatibility */
-	if (c == '\n')
-		uart_early_putc(uart_base, '\r');
-
-	/* wait for the hardware fifo to clear up */
-	while (!(_lsr_read(pUART) & THRE))
-		continue;
-
-	/* queue the character for transmission */
-	bfin_write(&pUART->thr, c);
-	SSYNC();
-}
-
-void uart_early_puts(const char *s)
-{
-	while (*s)
-		uart_early_putc(UART_BASE, *s++);
-}
-
-/* Symbol for our assembly to call. */
-void _serial_early_set_baud(uint32_t baud)
-{
-	serial_early_set_baud(UART_BASE, baud);
-}
-
-/* Symbol for our assembly to call. */
-void _serial_early_init(void)
-{
-	serial_early_init(UART_BASE);
-}
-#endif
-
-#elif defined(CONFIG_UART_MEM)
-
-char serial_logbuf[CONFIG_UART_MEM];
-char *serial_logbuf_head = serial_logbuf;
-
-int serial_mem_init(void)
-{
-	serial_logbuf_head = serial_logbuf;
-	return 0;
-}
-
-void serial_mem_setbrg(void)
-{
-}
-
-int serial_mem_tstc(void)
-{
-	return 0;
-}
-
-int serial_mem_getc(void)
-{
-	return 0;
-}
-
-void serial_mem_putc(const char c)
-{
-	*serial_logbuf_head = c;
-	if (++serial_logbuf_head == serial_logbuf + CONFIG_UART_MEM)
-		serial_logbuf_head = serial_logbuf;
-}
-
-void serial_mem_puts(const char *s)
-{
-	while (*s)
-		serial_putc(*s++);
-}
-
-struct serial_device bfin_serial_mem_device = {
-	.name   = "bfin_uart_mem",
-	.start  = serial_mem_init,
-	.setbrg = serial_mem_setbrg,
-	.getc   = serial_mem_getc,
-	.tstc   = serial_mem_tstc,
-	.putc   = serial_mem_putc,
-	.puts   = serial_mem_puts,
-};
-
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &bfin_serial_mem_device;
-}
-
-void bfin_serial_initialize(void)
-{
-	serial_register(&bfin_serial_mem_device);
-}
-#endif /* CONFIG_UART_MEM */
diff --git a/drivers/serial/serial_intel_mid.c b/drivers/serial/serial_intel_mid.c
new file mode 100644
index 0000000..777c09d
--- /dev/null
+++ b/drivers/serial/serial_intel_mid.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+
+/*
+ * The UART clock is calculated as
+ *
+ *	UART clock = XTAL * UART_MUL / UART_DIV
+ *
+ * The baudrate is calculated as
+ *
+ *	baud rate = UART clock / UART_PS / DLAB
+ */
+#define UART_PS		0x30
+#define UART_MUL	0x34
+#define UART_DIV	0x38
+
+static void mid_writel(struct ns16550_platdata *plat, int offset, int value)
+{
+	unsigned char *addr;
+
+	offset *= 1 << plat->reg_shift;
+	addr = (unsigned char *)plat->base + offset;
+
+	writel(value, addr + plat->reg_offset);
+}
+
+static int mid_serial_probe(struct udevice *dev)
+{
+	struct ns16550_platdata *plat = dev_get_platdata(dev);
+
+	/*
+	 * Initialize fractional divider correctly for Intel Edison
+	 * platform.
+	 *
+	 * For backward compatibility we have to set initial DLAB value
+	 * to 16 and speed to 115200 baud, where initial frequency is
+	 * 29491200Hz, and XTAL frequency is 38.4MHz.
+	 */
+	mid_writel(plat, UART_MUL, 96);
+	mid_writel(plat, UART_DIV, 125);
+	mid_writel(plat, UART_PS, 16);
+
+	return ns16550_serial_probe(dev);
+}
+
+static const struct udevice_id mid_serial_ids[] = {
+	{ .compatible = "intel,mid-uart" },
+	{}
+};
+
+U_BOOT_DRIVER(serial_intel_mid) = {
+	.name	= "serial_intel_mid",
+	.id	= UCLASS_SERIAL,
+	.of_match = mid_serial_ids,
+	.ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+	.priv_auto_alloc_size = sizeof(struct NS16550),
+	.probe	= mid_serial_probe,
+	.ops	= &ns16550_serial_ops,
+	.flags	= DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index a49134a..941b424 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -117,7 +117,7 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
 			divisor = UART_PL010_BAUD_9600;
 			break;
 		case 19200:
-			divisor = UART_PL010_BAUD_9600;
+			divisor = UART_PL010_BAUD_19200;
 			break;
 		case 38400:
 			divisor = UART_PL010_BAUD_38400;
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index fa9a1d2..c090562 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -19,8 +19,6 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
 obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
 obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
-obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
-obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
 obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o
 obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c
deleted file mode 100644
index 9a6fc78..0000000
--- a/drivers/spi/bfin_spi.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * Driver for Blackfin On-Chip SPI device
- *
- * Copyright (c) 2005-2010 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*#define DEBUG*/
-
-#include <common.h>
-#include <console.h>
-#include <malloc.h>
-#include <spi.h>
-
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/spi.h>
-
-struct bfin_spi_slave {
-	struct spi_slave slave;
-	void *mmr_base;
-	u16 ctl, baud, flg;
-};
-
-#define MAKE_SPI_FUNC(mmr, off) \
-static inline void write_##mmr(struct bfin_spi_slave *bss, u16 val) { bfin_write16(bss->mmr_base + off, val); } \
-static inline u16 read_##mmr(struct bfin_spi_slave *bss) { return bfin_read16(bss->mmr_base + off); }
-MAKE_SPI_FUNC(SPI_CTL,  0x00)
-MAKE_SPI_FUNC(SPI_FLG,  0x04)
-MAKE_SPI_FUNC(SPI_STAT, 0x08)
-MAKE_SPI_FUNC(SPI_TDBR, 0x0c)
-MAKE_SPI_FUNC(SPI_RDBR, 0x10)
-MAKE_SPI_FUNC(SPI_BAUD, 0x14)
-
-#define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
-
-#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
-#ifdef CONFIG_BFIN_SPI_GPIO_CS
-# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
-#else
-# define is_gpio_cs(cs) 0
-#endif
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	if (is_gpio_cs(cs))
-		return gpio_is_valid(gpio_cs(cs));
-	else
-		return (cs >= 1 && cs <= MAX_CTRL_CS);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
-	if (is_gpio_cs(slave->cs)) {
-		unsigned int cs = gpio_cs(slave->cs);
-		gpio_set_value(cs, bss->flg);
-		debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
-	} else {
-		write_SPI_FLG(bss,
-			(read_SPI_FLG(bss) &
-			~((!bss->flg << 8) << slave->cs)) |
-			(1 << slave->cs));
-		debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
-	}
-
-	SSYNC();
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
-	if (is_gpio_cs(slave->cs)) {
-		unsigned int cs = gpio_cs(slave->cs);
-		gpio_set_value(cs, !bss->flg);
-		debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
-	} else {
-		u16 flg;
-
-		/* make sure we force the cs to deassert rather than let the
-		 * pin float back up.  otherwise, exact timings may not be
-		 * met some of the time leading to random behavior (ugh).
-		 */
-		flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
-		write_SPI_FLG(bss, flg);
-		SSYNC();
-		debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
-
-		flg &= ~(1 << slave->cs);
-		write_SPI_FLG(bss, flg);
-		debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
-	}
-
-	SSYNC();
-}
-
-void spi_init()
-{
-}
-
-#ifdef SPI_CTL
-# define SPI0_CTL SPI_CTL
-#endif
-
-#define SPI_PINS(n) \
-	[n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
-static unsigned short pins[][5] = {
-#ifdef SPI0_CTL
-	SPI_PINS(0),
-#endif
-#ifdef SPI1_CTL
-	SPI_PINS(1),
-#endif
-#ifdef SPI2_CTL
-	SPI_PINS(2),
-#endif
-};
-
-#define SPI_CS_PINS(n) \
-	[n] = { \
-		P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
-		P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
-		P_SPI##n##_SSEL7, \
-	}
-static const unsigned short cs_pins[][7] = {
-#ifdef SPI0_CTL
-	SPI_CS_PINS(0),
-#endif
-#ifdef SPI1_CTL
-	SPI_CS_PINS(1),
-#endif
-#ifdef SPI2_CTL
-	SPI_CS_PINS(2),
-#endif
-};
-
-void spi_set_speed(struct spi_slave *slave, uint hz)
-{
-	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	ulong clk;
-	u32 baud;
-
-	clk = get_spi_clk();
-	/* baud should be rounded up */
-	baud = DIV_ROUND_UP(clk, 2 * hz);
-	if (baud < 2)
-		baud = 2;
-	else if (baud > (u16)-1)
-		baud = -1;
-	bss->baud = baud;
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-		unsigned int max_hz, unsigned int mode)
-{
-	struct bfin_spi_slave *bss;
-	u32 mmr_base;
-
-	if (!spi_cs_is_valid(bus, cs))
-		return NULL;
-
-	switch (bus) {
-#ifdef SPI0_CTL
-	case 0:
-		mmr_base = SPI0_CTL; break;
-#endif
-#ifdef SPI1_CTL
-	case 1:
-		mmr_base = SPI1_CTL; break;
-#endif
-#ifdef SPI2_CTL
-	case 2:
-		mmr_base = SPI2_CTL; break;
-#endif
-	default:
-		debug("%s: invalid bus %u\n", __func__, bus);
-		return NULL;
-	}
-
-	bss = spi_alloc_slave(struct bfin_spi_slave, bus, cs);
-	if (!bss)
-		return NULL;
-
-	bss->mmr_base = (void *)mmr_base;
-	bss->ctl = SPE | MSTR | TDBR_CORE;
-	if (mode & SPI_CPHA) bss->ctl |= CPHA;
-	if (mode & SPI_CPOL) bss->ctl |= CPOL;
-	if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
-	bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
-	spi_set_speed(&bss->slave, max_hz);
-
-	debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
-		bus, cs, mmr_base, bss->ctl, bss->baud, bss->flg);
-
-	return &bss->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	free(bss);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
-	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-
-	if (is_gpio_cs(slave->cs)) {
-		unsigned int cs = gpio_cs(slave->cs);
-		gpio_request(cs, "bfin-spi");
-		gpio_direction_output(cs, !bss->flg);
-		pins[slave->bus][0] = P_DONTCARE;
-	} else
-		pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
-	peripheral_request_list(pins[slave->bus], "bfin-spi");
-
-	write_SPI_CTL(bss, bss->ctl);
-	write_SPI_BAUD(bss, bss->baud);
-	SSYNC();
-
-	return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
-	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-
-	peripheral_free_list(pins[slave->bus]);
-	if (is_gpio_cs(slave->cs))
-		gpio_free(gpio_cs(slave->cs));
-
-	write_SPI_CTL(bss, 0);
-	SSYNC();
-}
-
-#ifndef CONFIG_BFIN_SPI_IDLE_VAL
-# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
-#endif
-
-static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
-			uint bytes)
-{
-	/* discard invalid data and clear RXS */
-	read_SPI_RDBR(bss);
-	/* todo: take advantage of hardware fifos  */
-	while (bytes--) {
-		u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
-		debug("%s: tx:%x ", __func__, value);
-		write_SPI_TDBR(bss, value);
-		SSYNC();
-		while ((read_SPI_STAT(bss) & TXS))
-			if (ctrlc())
-				return -1;
-		while (!(read_SPI_STAT(bss) & SPIF))
-			if (ctrlc())
-				return -1;
-		while (!(read_SPI_STAT(bss) & RXS))
-			if (ctrlc())
-				return -1;
-		value = read_SPI_RDBR(bss);
-		if (rx)
-			*rx++ = value;
-		debug("rx:%x\n", value);
-	}
-
-	return 0;
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-		void *din, unsigned long flags)
-{
-	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	const u8 *tx = dout;
-	u8 *rx = din;
-	uint bytes = bitlen / 8;
-	int ret = 0;
-
-	debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
-		slave->bus, slave->cs, bitlen, bytes, flags);
-
-	if (bitlen == 0)
-		goto done;
-
-	/* we can only do 8 bit transfers */
-	if (bitlen % 8) {
-		flags |= SPI_XFER_END;
-		goto done;
-	}
-
-	if (flags & SPI_XFER_BEGIN)
-		spi_cs_activate(slave);
-
-	ret = spi_pio_xfer(bss, tx, rx, bytes);
-
- done:
-	if (flags & SPI_XFER_END)
-		spi_cs_deactivate(slave);
-
-	return ret;
-}
diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c
deleted file mode 100644
index 9a27b78..0000000
--- a/drivers/spi/bfin_spi6xx.c
+++ /dev/null
@@ -1,305 +0,0 @@
-/*
- * Analog Devices SPI3 controller driver
- *
- * Copyright (c) 2011 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <console.h>
-#include <malloc.h>
-#include <spi.h>
-
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/spi6xx.h>
-
-struct bfin_spi_slave {
-	struct spi_slave slave;
-	u32 control, clock;
-	struct bfin_spi_regs *regs;
-	int cs_pol;
-};
-
-#define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
-
-#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
-#ifdef CONFIG_BFIN_SPI_GPIO_CS
-# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
-#else
-# define is_gpio_cs(cs) 0
-#endif
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	if (is_gpio_cs(cs))
-		return gpio_is_valid(gpio_cs(cs));
-	else
-		return (cs >= 1 && cs <= MAX_CTRL_CS);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
-	if (is_gpio_cs(slave->cs)) {
-		unsigned int cs = gpio_cs(slave->cs);
-		gpio_set_value(cs, bss->cs_pol);
-	} else {
-		u32 ssel;
-		ssel = bfin_read32(&bss->regs->ssel);
-		ssel |= 1 << slave->cs;
-		if (bss->cs_pol)
-			ssel |= BIT(8) << slave->cs;
-		else
-			ssel &= ~(BIT(8) << slave->cs);
-		bfin_write32(&bss->regs->ssel, ssel);
-	}
-
-	SSYNC();
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
-	if (is_gpio_cs(slave->cs)) {
-		unsigned int cs = gpio_cs(slave->cs);
-		gpio_set_value(cs, !bss->cs_pol);
-	} else {
-		u32 ssel;
-		ssel = bfin_read32(&bss->regs->ssel);
-		if (bss->cs_pol)
-			ssel &= ~(BIT(8) << slave->cs);
-		else
-			ssel |= BIT(8) << slave->cs;
-		/* deassert cs */
-		bfin_write32(&bss->regs->ssel, ssel);
-		SSYNC();
-		/* disable cs */
-		ssel &= ~(1 << slave->cs);
-		bfin_write32(&bss->regs->ssel, ssel);
-	}
-
-	SSYNC();
-}
-
-void spi_init()
-{
-}
-
-#define SPI_PINS(n) \
-	{ 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
-static unsigned short pins[][5] = {
-#ifdef SPI0_REGBASE
-	[0] = SPI_PINS(0),
-#endif
-#ifdef SPI1_REGBASE
-	[1] = SPI_PINS(1),
-#endif
-#ifdef SPI2_REGBASE
-	[2] = SPI_PINS(2),
-#endif
-};
-
-#define SPI_CS_PINS(n) \
-	{ \
-		P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
-		P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
-		P_SPI##n##_SSEL7, \
-	}
-static const unsigned short cs_pins[][7] = {
-#ifdef SPI0_REGBASE
-	[0] = SPI_CS_PINS(0),
-#endif
-#ifdef SPI1_REGBASE
-	[1] = SPI_CS_PINS(1),
-#endif
-#ifdef SPI2_REGBASE
-	[2] = SPI_CS_PINS(2),
-#endif
-};
-
-void spi_set_speed(struct spi_slave *slave, uint hz)
-{
-	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	ulong clk;
-	u32 clock;
-
-	clk = get_spi_clk();
-	clock = clk / hz;
-	if (clock)
-		clock--;
-	bss->clock = clock;
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-		unsigned int max_hz, unsigned int mode)
-{
-	struct bfin_spi_slave *bss;
-	u32 reg_base;
-
-	if (!spi_cs_is_valid(bus, cs))
-		return NULL;
-
-	switch (bus) {
-#ifdef SPI0_REGBASE
-	case 0:
-		reg_base = SPI0_REGBASE;
-		break;
-#endif
-#ifdef SPI1_REGBASE
-	case 1:
-		reg_base = SPI1_REGBASE;
-		break;
-#endif
-#ifdef SPI2_REGBASE
-	case 2:
-		reg_base = SPI2_REGBASE;
-		break;
-#endif
-	default:
-		debug("%s: invalid bus %u\n", __func__, bus);
-		return NULL;
-	}
-
-	bss = spi_alloc_slave(struct bfin_spi_slave, bus, cs);
-	if (!bss)
-		return NULL;
-
-	bss->regs = (struct bfin_spi_regs *)reg_base;
-	bss->control = SPI_CTL_EN | SPI_CTL_MSTR;
-	if (mode & SPI_CPHA)
-		bss->control |= SPI_CTL_CPHA;
-	if (mode & SPI_CPOL)
-		bss->control |= SPI_CTL_CPOL;
-	if (mode & SPI_LSB_FIRST)
-		bss->control |= SPI_CTL_LSBF;
-	bss->control &= ~SPI_CTL_ASSEL;
-	bss->cs_pol = mode & SPI_CS_HIGH ? 1 : 0;
-	spi_set_speed(&bss->slave, max_hz);
-
-	return &bss->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	free(bss);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
-	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-
-	if (is_gpio_cs(slave->cs)) {
-		unsigned int cs = gpio_cs(slave->cs);
-		gpio_request(cs, "bfin-spi");
-		gpio_direction_output(cs, !bss->cs_pol);
-		pins[slave->bus][0] = P_DONTCARE;
-	} else
-		pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
-	peripheral_request_list(pins[slave->bus], "bfin-spi");
-
-	bfin_write32(&bss->regs->control, bss->control);
-	bfin_write32(&bss->regs->clock, bss->clock);
-	bfin_write32(&bss->regs->delay, 0x0);
-	bfin_write32(&bss->regs->rx_control, SPI_RXCTL_REN);
-	bfin_write32(&bss->regs->tx_control, SPI_TXCTL_TEN | SPI_TXCTL_TTI);
-	SSYNC();
-
-	return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
-	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-
-	peripheral_free_list(pins[slave->bus]);
-	if (is_gpio_cs(slave->cs))
-		gpio_free(gpio_cs(slave->cs));
-
-	bfin_write32(&bss->regs->rx_control, 0x0);
-	bfin_write32(&bss->regs->tx_control, 0x0);
-	bfin_write32(&bss->regs->control, 0x0);
-	SSYNC();
-}
-
-#ifndef CONFIG_BFIN_SPI_IDLE_VAL
-# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
-#endif
-
-static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
-			uint bytes)
-{
-	/* discard invalid rx data and empty rfifo */
-	while (!(bfin_read32(&bss->regs->status) & SPI_STAT_RFE))
-		bfin_read32(&bss->regs->rfifo);
-
-	while (bytes--) {
-		u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
-		debug("%s: tx:%x ", __func__, value);
-		bfin_write32(&bss->regs->tfifo, value);
-		SSYNC();
-		while (bfin_read32(&bss->regs->status) & SPI_STAT_RFE)
-			if (ctrlc())
-				return -1;
-		value = bfin_read32(&bss->regs->rfifo);
-		if (rx)
-			*rx++ = value;
-		debug("rx:%x\n", value);
-	}
-
-	return 0;
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-		void *din, unsigned long flags)
-{
-	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	const u8 *tx = dout;
-	u8 *rx = din;
-	uint bytes = bitlen / 8;
-	int ret = 0;
-
-	debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
-		slave->bus, slave->cs, bitlen, bytes, flags);
-
-	if (bitlen == 0)
-		goto done;
-
-	/* we can only do 8 bit transfers */
-	if (bitlen % 8) {
-		flags |= SPI_XFER_END;
-		goto done;
-	}
-
-	if (flags & SPI_XFER_BEGIN)
-		spi_cs_activate(slave);
-
-	ret = spi_pio_xfer(bss, tx, rx, bytes);
-
- done:
-	if (flags & SPI_XFER_END)
-		spi_cs_deactivate(slave);
-
-	return ret;
-}
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index b2a0583..e61c67b 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -1037,8 +1037,11 @@ static int fsl_qspi_probe(struct udevice *bus)
 	 * setting the size of these devices to 0.  This would ensure
 	 * that the complete memory map is assigned to only one flash device.
 	 */
-	qspi_write32(priv->flags, &priv->regs->sfa1ad, priv->amba_base[1]);
+	qspi_write32(priv->flags, &priv->regs->sfa1ad,
+		     priv->amba_base[0] + amba_size_per_chip);
 	switch (priv->num_chipselect) {
+	case 1:
+		break;
 	case 2:
 		qspi_write32(priv->flags, &priv->regs->sfa2ad,
 			     priv->amba_base[1]);
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index ac17da0..c061c05 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -343,7 +343,7 @@ err:
 	debug("%s: Error path, created=%d, device '%s'\n", __func__,
 	      created, dev->name);
 	if (created) {
-		device_remove(dev);
+		device_remove(dev, DM_REMOVE_NORMAL);
 		device_unbind(dev);
 	}
 
@@ -384,7 +384,7 @@ struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
 
 void spi_free_slave(struct spi_slave *slave)
 {
-	device_remove(slave->dev);
+	device_remove(slave->dev, DM_REMOVE_NORMAL);
 	slave->dev = NULL;
 }
 
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 79955d7..3c4c9dd 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -17,6 +17,8 @@
 #include <asm/omap_common.h>
 #include <asm/ti-common/ti-edma3.h>
 #include <linux/kernel.h>
+#include <regmap.h>
+#include <syscon.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -549,21 +551,56 @@ static int ti_qspi_probe(struct udevice *bus)
 	return 0;
 }
 
+static void *map_syscon_chipselects(struct udevice *bus)
+{
+#if CONFIG_IS_ENABLED(SYSCON)
+	struct udevice *syscon;
+	struct regmap *regmap;
+	const fdt32_t *cell;
+	int len, err;
+
+	err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
+					   "syscon-chipselects", &syscon);
+	if (err) {
+		debug("%s: unable to find syscon device (%d)\n", __func__,
+		      err);
+		return NULL;
+	}
+
+	regmap = syscon_get_regmap(syscon);
+	if (IS_ERR(regmap)) {
+		debug("%s: unable to find regmap (%ld)\n", __func__,
+		      PTR_ERR(regmap));
+		return NULL;
+	}
+
+	cell = fdt_getprop(gd->fdt_blob, bus->of_offset, "syscon-chipselects",
+			   &len);
+	if (len < 2*sizeof(fdt32_t)) {
+		debug("%s: offset not available\n", __func__);
+		return NULL;
+	}
+
+	return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
+#else
+	fdt_addr_t addr;
+	addr = dev_get_addr_index(bus, 2);
+	return (addr == FDT_ADDR_T_NONE) ? NULL :
+		map_physmem(addr, 0, MAP_NOCACHE);
+#endif
+}
+
 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
 {
 	struct ti_qspi_priv *priv = dev_get_priv(bus);
 	const void *blob = gd->fdt_blob;
 	int node = dev_of_offset(bus);
-	fdt_addr_t addr;
-	void *mmap;
 
+	priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
 	priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs),
 				 MAP_NOCACHE);
 	priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0,
 				       MAP_NOCACHE);
-	addr = dev_get_addr_index(bus, 2);
-	mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE);
-	priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap;
 
 	priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
 	if (priv->max_hz < 0) {
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 72c1416..e038523 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -65,4 +65,13 @@ config STI_TIMER
 	help
 	  Select this to enable a timer for STi devices.
 
+config ARC_TIMER
+	bool "ARC timer support"
+	depends on TIMER && ARC && CLK
+	help
+	  Select this to enable built-in ARC timers.
+	  ARC cores may have up to 2 built-in timers: timer0 and timer1,
+	  usually at least one of them exists. Either of them is supported
+	  in U-Boot.
+
 endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index ae94be8..bfe65fc 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_X86_TSC_TIMER)	+= tsc_timer.o
 obj-$(CONFIG_OMAP_TIMER)	+= omap-timer.o
 obj-$(CONFIG_AST_TIMER)	+= ast_timer.o
 obj-$(CONFIG_STI_TIMER)		+= sti-timer.o
+obj-$(CONFIG_ARC_TIMER)	+= arc_timer.o
diff --git a/drivers/timer/arc_timer.c b/drivers/timer/arc_timer.c
new file mode 100644
index 0000000..e94e4a4
--- /dev/null
+++ b/drivers/timer/arc_timer.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <timer.h>
+#include <asm/arcregs.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define NH_MODE (1 << 1)
+
+/*
+ * ARC timer control registers are mapped to auxiliary address space.
+ * There are special ARC asm command to access that addresses.
+ * Therefore we use built-in functions to read from and write to timer
+ * control register.
+ */
+
+/* Driver private data. Contains timer id. Could be either 0 or 1. */
+struct arc_timer_priv {
+		uint timer_id;
+};
+
+static int arc_timer_get_count(struct udevice *dev, u64 *count)
+{
+	u32 val = 0;
+	struct arc_timer_priv *priv = dev_get_priv(dev);
+
+	switch (priv->timer_id) {
+	case 0:
+		val = read_aux_reg(ARC_AUX_TIMER0_CNT);
+		break;
+	case 1:
+		val = read_aux_reg(ARC_AUX_TIMER1_CNT);
+		break;
+	}
+	*count = timer_conv_64(val);
+
+	return 0;
+}
+
+static int arc_timer_probe(struct udevice *dev)
+{
+	int id;
+	struct arc_timer_priv *priv = dev_get_priv(dev);
+
+	/* Get registers offset and size */
+	id = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
+	if (id < 0)
+		return -EINVAL;
+
+	if (id > 1)
+		return -ENXIO;
+
+	priv->timer_id = (uint)id;
+
+	/*
+	 * In ARC core there're special registers (Auxiliary or AUX) in its
+	 * separate memory space that are used for accessing some hardware
+	 * features of the core. They are not mapped in normal memory space
+	 * and also always have the same location regardless core configuration.
+	 * Thus to simplify understanding of the programming model we chose to
+	 * access AUX regs of Timer0 and Timer1 separately instead of using
+	 * offsets from some base address.
+	 */
+
+	switch (priv->timer_id) {
+	case 0:
+		/* Disable timer if CPU is halted */
+		write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
+		/* Set max value for counter/timer */
+		write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
+		/* Set initial count value and restart counter/timer */
+		write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
+		break;
+	case 1:
+		/* Disable timer if CPU is halted */
+		write_aux_reg(ARC_AUX_TIMER1_CTRL, NH_MODE);
+		/* Set max value for counter/timer */
+		write_aux_reg(ARC_AUX_TIMER1_LIMIT, 0xffffffff);
+		/* Set initial count value and restart counter/timer */
+		write_aux_reg(ARC_AUX_TIMER1_CNT, 0);
+		break;
+	}
+
+	return 0;
+}
+
+
+static const struct timer_ops arc_timer_ops = {
+	.get_count = arc_timer_get_count,
+};
+
+static const struct udevice_id arc_timer_ids[] = {
+	{ .compatible = "snps,arc-timer" },
+	{}
+};
+
+U_BOOT_DRIVER(arc_timer) = {
+	.name	= "arc_timer",
+	.id	= UCLASS_TIMER,
+	.of_match = arc_timer_ids,
+	.probe = arc_timer_probe,
+	.ops	= &arc_timer_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+	.priv_auto_alloc_size = sizeof(struct arc_timer_priv),
+};
diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig
index 3490ee0..2a64bc4 100644
--- a/drivers/tpm/Kconfig
+++ b/drivers/tpm/Kconfig
@@ -88,4 +88,19 @@ config TPM_FLUSH_RESOURCES
 	help
 	  Enable support to flush specific resources (e.g. keys) from the TPM.
 	  The functionality is available via the 'tpm' command as well.
+
+config TPM_LOAD_KEY_BY_SHA1
+	bool "Enable TPM key loading by SHA1 support"
+	depends on TPM
+	help
+	  Enable support to load keys into the TPM by identifying
+	  their parent via the public key's SHA1 hash.
+	  The functionality is available via the 'tpm' command as well.
+
+config TPM_LIST_RESOURCES
+	bool "Enable TPM resource listing support"
+	depends on TPM
+	help
+	  Enable support to list specific resources (e.g. keys) within the TPM.
+	  The functionality is available via the 'tpm' command as well.
 endmenu
diff --git a/drivers/usb/emul/sandbox_hub.c b/drivers/usb/emul/sandbox_hub.c
index c3a8e73..f0939b1 100644
--- a/drivers/usb/emul/sandbox_hub.c
+++ b/drivers/usb/emul/sandbox_hub.c
@@ -156,7 +156,7 @@ static int clrset_post_state(struct udevice *hub, int port, int clear, int set)
 			} else if (clear & USB_PORT_STAT_POWER) {
 				debug("%s: %s: power off, removed, ret=%d\n",
 				      __func__, dev->name, ret);
-				ret = device_remove(dev);
+				ret = device_remove(dev, DM_REMOVE_NORMAL);
 				clear |= USB_PORT_STAT_CONNECTION;
 			}
 		}
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 5129a57..0bf8274 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -25,6 +25,7 @@ config USB_XHCI_MVEBU
 	bool "MVEBU USB 3.0 support"
 	default y
 	depends on ARCH_MVEBU
+	select DM_REGULATOR
 	help
 	  Choose this option to add support for USB 3.0 driver on mvebu
 	  SoCs, which includes Armada8K, Armada3700 and other Armada
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index 5bb97ff..068f24f 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -45,7 +45,7 @@ static int ehci_usb_probe(struct udevice *dev)
 	 * clocks resp. phys.
 	 */
 	priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
-#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
 	extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
 #endif
 	priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST;
diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
index 5cf1e9a..6eded4a 100644
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -154,7 +154,7 @@ int usb_stop(void)
 	uc_priv = uc->priv;
 
 	uclass_foreach_dev(bus, uc) {
-		ret = device_remove(bus);
+		ret = device_remove(bus, DM_REMOVE_NORMAL);
 		if (ret && !err)
 			err = ret;
 	}
@@ -358,7 +358,7 @@ int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp)
 	ret = uclass_find_device_by_seq(UCLASS_USB, 0, true, &dev);
 	if (ret)
 		return ret;
-	ret = device_remove(dev);
+	ret = device_remove(dev, DM_REMOVE_NORMAL);
 	if (ret)
 		return ret;
 
diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c
index 46eb937..d880af1 100644
--- a/drivers/usb/host/xhci-mvebu.c
+++ b/drivers/usb/host/xhci-mvebu.c
@@ -10,6 +10,7 @@
 #include <dm.h>
 #include <fdtdec.h>
 #include <usb.h>
+#include <power/regulator.h>
 #include <asm/gpio.h>
 
 #include "xhci.h"
@@ -44,12 +45,22 @@ static int xhci_usb_probe(struct udevice *dev)
 	struct mvebu_xhci_platdata *plat = dev_get_platdata(dev);
 	struct mvebu_xhci *ctx = dev_get_priv(dev);
 	struct xhci_hcor *hcor;
-	int len;
+	int len, ret;
+	struct udevice *regulator;
 
 	ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
 	len = HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase));
 	hcor = (struct xhci_hcor *)((uintptr_t)ctx->hcd + len);
 
+	ret = device_get_supply_regulator(dev, "vbus-supply", &regulator);
+	if (!ret) {
+		ret = regulator_set_enable(regulator, true);
+		if (ret) {
+			printf("Failed to turn ON the VBUS regulator\n");
+			return ret;
+		}
+	}
+
 	/* Enable USB xHCI (VBUS, reset etc) in board specific code */
 	board_xhci_enable();
 
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index 84cb21b..79e118e 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -116,12 +116,9 @@ static inline struct musb *dev_to_musb(struct device *dev)
 {
 	return dev_get_drvdata(dev);
 }
-#endif
 
 /*-------------------------------------------------------------------------*/
 
-#ifndef __UBOOT__
-#ifndef CONFIG_BLACKFIN
 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
 {
 	void __iomem *addr = phy->io_priv;
@@ -203,10 +200,6 @@ out:
 
 	return ret;
 }
-#else
-#define musb_ulpi_read		NULL
-#define musb_ulpi_write		NULL
-#endif
 
 static struct usb_phy_io_ops musb_ulpi_access = {
 	.read = musb_ulpi_read,
@@ -216,7 +209,7 @@ static struct usb_phy_io_ops musb_ulpi_access = {
 
 /*-------------------------------------------------------------------------*/
 
-#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
+#if !defined(CONFIG_USB_MUSB_TUSB6010)
 
 /*
  * Load an endpoint's FIFO
diff --git a/drivers/usb/musb-new/musb_core.h b/drivers/usb/musb-new/musb_core.h
index 4ae0ae2..6394bb0 100644
--- a/drivers/usb/musb-new/musb_core.h
+++ b/drivers/usb/musb-new/musb_core.h
@@ -152,8 +152,7 @@ enum musb_g_ep0_state {
  */
 
 #if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \
-		|| defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_BLACKFIN) \
-		|| defined(CONFIG_ARCH_OMAP4)
+		|| defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_ARCH_OMAP4)
 /* REVISIT indexed access seemed to
  * misbehave (on DaVinci) for at least peripheral IN ...
  */
@@ -455,34 +454,6 @@ static inline struct musb *gadget_to_musb(struct usb_gadget *g)
 	return container_of(g, struct musb, g);
 }
 
-#ifdef CONFIG_BLACKFIN
-static inline int musb_read_fifosize(struct musb *musb,
-		struct musb_hw_ep *hw_ep, u8 epnum)
-{
-	musb->nr_endpoints++;
-	musb->epmask |= (1 << epnum);
-
-	if (epnum < 5) {
-		hw_ep->max_packet_sz_tx = 128;
-		hw_ep->max_packet_sz_rx = 128;
-	} else {
-		hw_ep->max_packet_sz_tx = 1024;
-		hw_ep->max_packet_sz_rx = 1024;
-	}
-	hw_ep->is_shared_fifo = false;
-
-	return 0;
-}
-
-static inline void musb_configure_ep0(struct musb *musb)
-{
-	musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
-	musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
-	musb->endpoints[0].is_shared_fifo = true;
-}
-
-#else
-
 static inline int musb_read_fifosize(struct musb *musb,
 		struct musb_hw_ep *hw_ep, u8 epnum)
 {
@@ -519,8 +490,6 @@ static inline void musb_configure_ep0(struct musb *musb)
 	musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
 	musb->endpoints[0].is_shared_fifo = true;
 }
-#endif /* CONFIG_BLACKFIN */
-
 
 /***************************** Glue it together *****************************/
 
diff --git a/drivers/usb/musb-new/musb_dma.h b/drivers/usb/musb-new/musb_dma.h
index 30e39f5..c94abb8 100644
--- a/drivers/usb/musb-new/musb_dma.h
+++ b/drivers/usb/musb-new/musb_dma.h
@@ -56,17 +56,6 @@ struct musb_hw_ep;
 #define tusb_dma_omap()			0
 #endif
 
-/* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
- *	Only allow DMA mode 1 to be used when the USB will actually generate the
- *	interrupts we expect.
- */
-#ifdef CONFIG_BLACKFIN
-# undef USE_MODE1
-# if !ANOMALY_05000456
-#  define USE_MODE1
-# endif
-#endif
-
 /*
  * DMA channel status ... updated by the dma controller driver whenever that
  * status changes, and protected by the overall controller spinlock.
diff --git a/drivers/usb/musb-new/musb_io.h b/drivers/usb/musb-new/musb_io.h
index ea8efb3..7668212 100644
--- a/drivers/usb/musb-new/musb_io.h
+++ b/drivers/usb/musb-new/musb_io.h
@@ -23,8 +23,8 @@
 
 #if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH) \
 	&& !defined(CONFIG_AVR32) && !defined(CONFIG_PPC32) \
-	&& !defined(CONFIG_PPC64) && !defined(CONFIG_BLACKFIN) \
-	&& !defined(CONFIG_MIPS) && !defined(CONFIG_M68K)
+	&& !defined(CONFIG_PPC64) && !defined(CONFIG_MIPS) \
+	&& !defined(CONFIG_M68K)
 static inline void readsl(const void __iomem *addr, void *buf, int len)
 	{ insl((unsigned long)addr, buf, len); }
 static inline void readsw(const void __iomem *addr, void *buf, int len)
@@ -41,8 +41,6 @@ static inline void writesb(const void __iomem *addr, const void *buf, int len)
 
 #endif
 
-#ifndef CONFIG_BLACKFIN
-
 /* NOTE:  these offsets are all in bytes */
 
 static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
@@ -101,26 +99,4 @@ static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
 
 #endif	/* CONFIG_USB_MUSB_TUSB6010 */
 
-#else
-
-static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
-	{ return (u8) (bfin_read16(addr + offset)); }
-
-static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
-	{ return bfin_read16(addr + offset); }
-
-static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
-	{ return (u32) (bfin_read16(addr + offset)); }
-
-static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
-	{ bfin_write16(addr + offset, (u16) data); }
-
-static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
-	{ bfin_write16(addr + offset, data); }
-
-static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data)
-	{ bfin_write16(addr + offset, (u16) data); }
-
-#endif /* CONFIG_BLACKFIN */
-
 #endif
diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h
index 0f18dd7..a3cc38e 100644
--- a/drivers/usb/musb-new/musb_regs.h
+++ b/drivers/usb/musb-new/musb_regs.h
@@ -190,8 +190,6 @@
 #define MUSB_HUBADDR_MULTI_TT		0x80
 
 
-#ifndef CONFIG_BLACKFIN
-
 /* SUNXI has different reg addresses, but identical r/w functions */
 #ifndef CONFIG_ARCH_SUNXI 
 
@@ -526,193 +524,4 @@ static inline u8  musb_read_txhubport(void __iomem *mbase, u8 epnum)
 	return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT));
 }
 
-#else /* CONFIG_BLACKFIN */
-
-#define USB_BASE		USB_FADDR
-#define USB_OFFSET(reg)		(reg - USB_BASE)
-
-/*
- * Common USB registers
- */
-#define MUSB_FADDR		USB_OFFSET(USB_FADDR)	/* 8-bit */
-#define MUSB_POWER		USB_OFFSET(USB_POWER)	/* 8-bit */
-#define MUSB_INTRTX		USB_OFFSET(USB_INTRTX)	/* 16-bit */
-#define MUSB_INTRRX		USB_OFFSET(USB_INTRRX)
-#define MUSB_INTRTXE		USB_OFFSET(USB_INTRTXE)
-#define MUSB_INTRRXE		USB_OFFSET(USB_INTRRXE)
-#define MUSB_INTRUSB		USB_OFFSET(USB_INTRUSB)	/* 8 bit */
-#define MUSB_INTRUSBE		USB_OFFSET(USB_INTRUSBE)/* 8 bit */
-#define MUSB_FRAME		USB_OFFSET(USB_FRAME)
-#define MUSB_INDEX		USB_OFFSET(USB_INDEX)	/* 8 bit */
-#define MUSB_TESTMODE		USB_OFFSET(USB_TESTMODE)/* 8 bit */
-
-/* Get offset for a given FIFO from musb->mregs */
-#define MUSB_FIFO_OFFSET(epnum)	\
-	(USB_OFFSET(USB_EP0_FIFO) + ((epnum) * 8))
-
-/*
- * Additional Control Registers
- */
-
-#define MUSB_DEVCTL		USB_OFFSET(USB_OTG_DEV_CTL)	/* 8 bit */
-
-#define MUSB_LINKINFO		USB_OFFSET(USB_LINKINFO)/* 8 bit */
-#define MUSB_VPLEN		USB_OFFSET(USB_VPLEN)	/* 8 bit */
-#define MUSB_HS_EOF1		USB_OFFSET(USB_HS_EOF1)	/* 8 bit */
-#define MUSB_FS_EOF1		USB_OFFSET(USB_FS_EOF1)	/* 8 bit */
-#define MUSB_LS_EOF1		USB_OFFSET(USB_LS_EOF1)	/* 8 bit */
-
-/* Offsets to endpoint registers */
-#define MUSB_TXMAXP		0x00
-#define MUSB_TXCSR		0x04
-#define MUSB_CSR0		MUSB_TXCSR	/* Re-used for EP0 */
-#define MUSB_RXMAXP		0x08
-#define MUSB_RXCSR		0x0C
-#define MUSB_RXCOUNT		0x10
-#define MUSB_COUNT0		MUSB_RXCOUNT	/* Re-used for EP0 */
-#define MUSB_TXTYPE		0x14
-#define MUSB_TYPE0		MUSB_TXTYPE	/* Re-used for EP0 */
-#define MUSB_TXINTERVAL		0x18
-#define MUSB_NAKLIMIT0		MUSB_TXINTERVAL	/* Re-used for EP0 */
-#define MUSB_RXTYPE		0x1C
-#define MUSB_RXINTERVAL		0x20
-#define MUSB_TXCOUNT		0x28
-
-/* Offsets to endpoint registers in indexed model (using INDEX register) */
-#define MUSB_INDEXED_OFFSET(_epnum, _offset)	\
-	(0x40 + (_offset))
-
-/* Offsets to endpoint registers in flat models */
-#define MUSB_FLAT_OFFSET(_epnum, _offset)	\
-	(USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
-
-/* Not implemented - HW has separate Tx/Rx FIFO */
-#define MUSB_TXCSR_MODE			0x0000
-
-static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
-{
-}
-
-static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
-{
-}
-
-static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
-{
-}
-
-static inline void  musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
-{
-}
-
-static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
-{
-}
-
-static inline u8 musb_read_txfifosz(void __iomem *mbase)
-{
-	return 0;
-}
-
-static inline u16 musb_read_txfifoadd(void __iomem *mbase)
-{
-	return 0;
-}
-
-static inline u8 musb_read_rxfifosz(void __iomem *mbase)
-{
-	return 0;
-}
-
-static inline u16  musb_read_rxfifoadd(void __iomem *mbase)
-{
-	return 0;
-}
-
-static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
-{
-	return 0;
-}
-
-static inline u8 musb_read_configdata(void __iomem *mbase)
-{
-	return 0;
-}
-
-static inline u16 musb_read_hwvers(void __iomem *mbase)
-{
-	/*
-	 * This register is invisible on Blackfin, actually the MUSB
-	 * RTL version of Blackfin is 1.9, so just harcode its value.
-	 */
-	return MUSB_HWVERS_1900;
-}
-
-static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
-{
-	return NULL;
-}
-
-static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
-		u8 qh_addr_req)
-{
-}
-
-static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
-		u8 qh_h_addr_reg)
-{
-}
-
-static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
-		u8 qh_h_port_reg)
-{
-}
-
-static inline void  musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
-		u8 qh_addr_reg)
-{
-}
-
-static inline void  musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
-		u8 qh_addr_reg)
-{
-}
-
-static inline void  musb_write_txhubport(void __iomem *mbase, u8 epnum,
-		u8 qh_h_port_reg)
-{
-}
-
-static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
-{
-	return 0;
-}
-
-static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
-{
-	return 0;
-}
-
-static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
-{
-	return 0;
-}
-
-static inline u8  musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
-{
-	return 0;
-}
-
-static inline u8  musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
-{
-	return 0;
-}
-
-static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
-{
-	return 0;
-}
-
-#endif /* CONFIG_BLACKFIN */
-
 #endif	/* __MUSB_REGS_H__ */
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index bd2b7c5..9554edd 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -7,7 +7,6 @@
 
 obj-$(CONFIG_USB_MUSB_HCD) += musb_hcd.o musb_core.o
 obj-$(CONFIG_USB_MUSB_UDC) += musb_udc.o musb_core.o
-obj-$(CONFIG_USB_BLACKFIN) += blackfin_usb.o
 obj-$(CONFIG_USB_DAVINCI) += davinci.o
 obj-$(CONFIG_USB_OMAP3) += omap3.o
 obj-$(CONFIG_USB_DA8XX) += da8xx.o
diff --git a/drivers/usb/musb/blackfin_usb.c b/drivers/usb/musb/blackfin_usb.c
deleted file mode 100644
index 65fff88..0000000
--- a/drivers/usb/musb/blackfin_usb.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Blackfin MUSB HCD (Host Controller Driver) for u-boot
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-
-#include <usb.h>
-
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/mach-common/bits/usb.h>
-
-#include "musb_core.h"
-
-#ifndef CONFIG_USB_BLACKFIN_CLKIN
-#define CONFIG_USB_BLACKFIN_CLKIN 24
-#endif
-
-/* MUSB platform configuration */
-struct musb_config musb_cfg = {
-	.regs       = (struct musb_regs *)USB_FADDR,
-	.timeout    = 0x3FFFFFF,
-	.musb_speed = 0,
-};
-
-/*
- * This function read or write data to endpoint fifo
- * Blackfin use DMA polling method to avoid buffer alignment issues
- *
- * ep		- Endpoint number
- * length	- Number of bytes to write to FIFO
- * fifo_data	- Pointer to data buffer to be read/write
- * is_write	- Flag for read or write
- */
-void rw_fifo(u8 ep, u32 length, void *fifo_data, int is_write)
-{
-	struct bfin_musb_dma_regs *regs;
-	u32 val = (u32)fifo_data;
-
-	blackfin_dcache_flush_invalidate_range(fifo_data, fifo_data + length);
-
-	regs = (void *)USB_DMA_INTERRUPT;
-	regs += ep;
-
-	/* Setup DMA address register */
-	bfin_write16(&regs->addr_low, val);
-	SSYNC();
-
-	bfin_write16(&regs->addr_high, val >> 16);
-	SSYNC();
-
-	/* Setup DMA count register */
-	bfin_write16(&regs->count_low, length);
-	bfin_write16(&regs->count_high, 0);
-	SSYNC();
-
-	/* Enable the DMA */
-	val = (ep << 4) | DMA_ENA | INT_ENA;
-	if (is_write)
-		val |= DIRECTION;
-	bfin_write16(&regs->control, val);
-	SSYNC();
-
-	/* Wait for compelete */
-	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << ep)))
-		continue;
-
-	/* acknowledge dma interrupt */
-	bfin_write_USB_DMA_INTERRUPT(1 << ep);
-	SSYNC();
-
-	/* Reset DMA */
-	bfin_write16(&regs->control, 0);
-	SSYNC();
-}
-
-void write_fifo(u8 ep, u32 length, void *fifo_data)
-{
-	rw_fifo(ep, length, fifo_data, 1);
-}
-
-void read_fifo(u8 ep, u32 length, void *fifo_data)
-{
-	rw_fifo(ep, length, fifo_data, 0);
-}
-
-
-/*
- * CPU and board-specific MUSB initializations.  Aliased function
- * signals caller to move on.
- */
-static void __def_musb_init(void)
-{
-}
-void board_musb_init(void) __attribute__((weak, alias("__def_musb_init")));
-
-static void bfin_anomaly_init(void)
-{
-	u32 revid;
-
-	if (!ANOMALY_05000346 && !ANOMALY_05000347)
-		return;
-
-	revid = bfin_revid();
-
-#ifdef __ADSPBF54x__
-	if (revid > 0)
-		return;
-#endif
-#ifdef __ADSPBF52x__
-	if (ANOMALY_BF526 && revid > 0)
-		return;
-	if (ANOMALY_BF527 && revid > 1)
-		return;
-#endif
-
-	if (ANOMALY_05000346) {
-		bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
-		SSYNC();
-	}
-
-	if (ANOMALY_05000347) {
-		bfin_write_USB_APHY_CNTRL(0x0);
-		SSYNC();
-	}
-}
-
-int musb_platform_init(void)
-{
-	/* board specific initialization */
-	board_musb_init();
-
-	bfin_anomaly_init();
-
-	/* Configure PLL oscillator register */
-	bfin_write_USB_PLLOSC_CTRL(0x3080 |
-		((480 / CONFIG_USB_BLACKFIN_CLKIN) << 1));
-	SSYNC();
-
-	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
-	SSYNC();
-
-	bfin_write_USB_EP_NI0_RXMAXP(64);
-	SSYNC();
-
-	bfin_write_USB_EP_NI0_TXMAXP(64);
-	SSYNC();
-
-	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
-	bfin_write_USB_GLOBINTR(0x7);
-	SSYNC();
-
-	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
-				EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
-				EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
-				EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
-				EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
-	SSYNC();
-
-	return 0;
-}
-
-/*
- * This function performs Blackfin platform specific deinitialization for usb.
-*/
-void musb_platform_deinit(void)
-{
-}
diff --git a/drivers/usb/musb/blackfin_usb.h b/drivers/usb/musb/blackfin_usb.h
deleted file mode 100644
index de994bf..0000000
--- a/drivers/usb/musb/blackfin_usb.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Blackfin MUSB HCD (Host Controller Driver) for u-boot
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BLACKFIN_USB_H__
-#define __BLACKFIN_USB_H__
-
-#include <linux/types.h>
-
-/* Every register is 32bit aligned, but only 16bits in size */
-#define ureg(name) u16 name; u16 __pad_##name;
-
-#define musb_regs musb_regs
-struct musb_regs {
-	/* common registers */
-	ureg(faddr)
-	ureg(power)
-	ureg(intrtx)
-	ureg(intrrx)
-	ureg(intrtxe)
-	ureg(intrrxe)
-	ureg(intrusb)
-	ureg(intrusbe)
-	ureg(frame)
-	ureg(index)
-	ureg(testmode)
-	ureg(globintr)
-	ureg(global_ctl)
-	u32	reserved0[3];
-	/* indexed registers */
-	ureg(txmaxp)
-	ureg(txcsr)
-	ureg(rxmaxp)
-	ureg(rxcsr)
-	ureg(rxcount)
-	ureg(txtype)
-	ureg(txinterval)
-	ureg(rxtype)
-	ureg(rxinterval)
-	u32	reserved1;
-	ureg(txcount)
-	u32	reserved2[5];
-	/* fifo */
-	u16	fifox[32];
-	/* OTG, dynamic FIFO, version & vendor registers */
-	u32	reserved3[16];
-	ureg(devctl)
-	ureg(vbus_irq)
-	ureg(vbus_mask)
-	u32 reserved4[15];
-	ureg(linkinfo)
-	ureg(vplen)
-	ureg(hseof1)
-	ureg(fseof1)
-	ureg(lseof1)
-	u32 reserved5[41];
-	/* target address registers */
-	struct musb_tar_regs {
-		ureg(txmaxp)
-		ureg(txcsr)
-		ureg(rxmaxp)
-		ureg(rxcsr)
-		ureg(rxcount)
-		ureg(txtype)
-		ureg(txinternal)
-		ureg(rxtype)
-		ureg(rxinternal)
-		u32	reserved6;
-		ureg(txcount)
-		u32 reserved7[5];
-	} tar[8];
-} __attribute__((packed));
-
-struct bfin_musb_dma_regs {
-	ureg(interrupt);
-	ureg(control);
-	ureg(addr_low);
-	ureg(addr_high);
-	ureg(count_low);
-	ureg(count_high);
-	u32 reserved0[2];
-};
-
-#undef ureg
-
-/* EP5-EP7 are the only ones with 1024 byte FIFOs which BULK really needs */
-#define MUSB_BULK_EP 5
-
-/* Blackfin FIFO's are static */
-#define MUSB_NO_DYNAMIC_FIFO
-
-/* No HUB support :( */
-#define MUSB_NO_MULTIPOINT
-
-#endif
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index dc863bd..ae352ce 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -13,10 +13,6 @@
 #include <usb_defs.h>
 #include <asm/io.h>
 
-#ifdef CONFIG_USB_BLACKFIN
-# include "blackfin_usb.h"
-#endif
-
 #define MUSB_EP0_FIFOSIZE	64	/* This is non-configurable */
 
 /* EP0 */
@@ -336,28 +332,6 @@ extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt);
 extern void write_fifo(u8 ep, u32 length, void *fifo_data);
 extern void read_fifo(u8 ep, u32 length, void *fifo_data);
 
-#if defined(CONFIG_USB_BLACKFIN)
-/* Every USB register is accessed as a 16-bit even if the value itself
- * is only 8-bits in size.  Fun stuff.
- */
-# undef  readb
-# define readb(addr)     (u8)bfin_read16(addr)
-# undef  writeb
-# define writeb(b, addr) bfin_write16(addr, b)
-# undef MUSB_TXCSR_MODE /* not supported */
-# define MUSB_TXCSR_MODE 0
-/*
- * The USB PHY on current Blackfin processors is a UTMI+ level 2 PHY.
- * However, it has no ULPI support - so there are no registers at all.
- * That means accesses to ULPI_BUSCONTROL have to be abstracted away.
- */
-static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
-{
-	return 0;
-}
-static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
-{}
-#else
 static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
 {
 	return readb(&musbr->ulpi_busctl);
@@ -366,6 +340,5 @@ static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
 {
 	writeb(val, &musbr->ulpi_busctl);
 }
-#endif
 
 #endif	/* __MUSB_HDRC_DEFS_H__ */
diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c
index 4947936..fee0848 100644
--- a/drivers/usb/musb/musb_hcd.c
+++ b/drivers/usb/musb/musb_hcd.c
@@ -913,11 +913,6 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
 			nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
 					(len-txlen) : dev->epmaxpacketout[ep];
 
-#ifdef CONFIG_USB_BLACKFIN
-			/* Set the transfer data size */
-			writew(nextlen, &musbr->txcount);
-#endif
-
 			/* Write the data to the FIFO */
 			write_fifo(MUSB_BULK_EP, nextlen,
 					(void *)(((u8 *)buffer) + txlen));
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
new file mode 100644
index 0000000..8a53109
--- /dev/null
+++ b/drivers/video/dw_hdmi.c
@@ -0,0 +1,764 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ * Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include "dw_hdmi.h"
+
+struct tmds_n_cts {
+	u32 tmds;
+	u32 cts;
+	u32 n;
+};
+
+static const struct tmds_n_cts n_cts_table[] = {
+	{
+		.tmds = 25175000, .n = 6144, .cts = 25175,
+	}, {
+		.tmds = 25200000, .n = 6144, .cts = 25200,
+	}, {
+		.tmds = 27000000, .n = 6144, .cts = 27000,
+	}, {
+		.tmds = 27027000, .n = 6144, .cts = 27027,
+	}, {
+		.tmds = 40000000, .n = 6144, .cts = 40000,
+	}, {
+		.tmds = 54000000, .n = 6144, .cts = 54000,
+	}, {
+		.tmds = 54054000, .n = 6144, .cts = 54054,
+	}, {
+		.tmds = 65000000, .n = 6144, .cts = 65000,
+	}, {
+		.tmds = 74176000, .n = 11648, .cts = 140625,
+	}, {
+		.tmds = 74250000, .n = 6144, .cts = 74250,
+	}, {
+		.tmds = 83500000, .n = 6144, .cts = 83500,
+	}, {
+		.tmds = 106500000, .n = 6144, .cts = 106500,
+	}, {
+		.tmds = 108000000, .n = 6144, .cts = 108000,
+	}, {
+		.tmds = 148352000, .n = 5824, .cts = 140625,
+	}, {
+		.tmds = 148500000, .n = 6144, .cts = 148500,
+	}, {
+		.tmds = 297000000, .n = 5120, .cts = 247500,
+	}
+};
+
+static void hdmi_write(struct dw_hdmi *hdmi, u8 val, int offset)
+{
+	switch (hdmi->reg_io_width) {
+	case 1:
+		writeb(val, hdmi->ioaddr + offset);
+		break;
+	case 4:
+		writel(val, hdmi->ioaddr + (offset << 2));
+		break;
+	default:
+		debug("reg_io_width has unsupported width!\n");
+		break;
+	}
+}
+
+static u8 hdmi_read(struct dw_hdmi *hdmi, int offset)
+{
+	switch (hdmi->reg_io_width) {
+	case 1:
+		return readb(hdmi->ioaddr + offset);
+	case 4:
+		return readl(hdmi->ioaddr + (offset << 2));
+	default:
+		debug("reg_io_width has unsupported width!\n");
+		break;
+	}
+
+	return 0;
+}
+
+static void hdmi_mod(struct dw_hdmi *hdmi, unsigned reg, u8 mask, u8 data)
+{
+	u8 val = hdmi_read(hdmi, reg) & ~mask;
+
+	val |= data & mask;
+	hdmi_write(hdmi, val, reg);
+}
+
+static void hdmi_set_clock_regenerator(struct dw_hdmi *hdmi, u32 n, u32 cts)
+{
+	uint cts3;
+	uint n3;
+
+	/* first set ncts_atomic_write (if present) */
+	n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
+	hdmi_write(hdmi, n3, HDMI_AUD_N3);
+
+	/* set cts_manual (if present) */
+	cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
+
+	cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
+	cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
+
+	/* write cts values; cts3 must be written first */
+	hdmi_write(hdmi, cts3, HDMI_AUD_CTS3);
+	hdmi_write(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
+	hdmi_write(hdmi, cts & 0xff, HDMI_AUD_CTS1);
+
+	/* write n values; n1 must be written last */
+	n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK;
+	hdmi_write(hdmi, n3, HDMI_AUD_N3);
+	hdmi_write(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
+	hdmi_write(hdmi, n & 0xff, HDMI_AUD_N3);
+
+	hdmi_write(hdmi, HDMI_AUD_INPUTCLKFS_128, HDMI_AUD_INPUTCLKFS);
+}
+
+static int hdmi_lookup_n_cts(u32 pixel_clk)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(n_cts_table); i++)
+		if (pixel_clk <= n_cts_table[i].tmds)
+			break;
+
+	if (i >= ARRAY_SIZE(n_cts_table))
+		return -1;
+
+	return i;
+}
+
+static void hdmi_audio_set_samplerate(struct dw_hdmi *hdmi, u32 pixel_clk)
+{
+	u32 clk_n, clk_cts;
+	int index;
+
+	index = hdmi_lookup_n_cts(pixel_clk);
+	if (index == -1) {
+		debug("audio not supported for pixel clk %d\n", pixel_clk);
+		return;
+	}
+
+	clk_n = n_cts_table[index].n;
+	clk_cts = n_cts_table[index].cts;
+	hdmi_set_clock_regenerator(hdmi, clk_n, clk_cts);
+}
+
+/*
+ * this submodule is responsible for the video data synchronization.
+ * for example, for rgb 4:4:4 input, the data map is defined as
+ *			pin{47~40} <==> r[7:0]
+ *			pin{31~24} <==> g[7:0]
+ *			pin{15~8}  <==> b[7:0]
+ */
+static void hdmi_video_sample(struct dw_hdmi *hdmi)
+{
+	u32 color_format = 0x01;
+	uint val;
+
+	val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
+	      ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
+	      HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
+
+	hdmi_write(hdmi, val, HDMI_TX_INVID0);
+
+	/* enable tx stuffing: when de is inactive, fix the output data to 0 */
+	val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
+	      HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
+	      HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
+	hdmi_write(hdmi, val, HDMI_TX_INSTUFFING);
+	hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA0);
+	hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA1);
+	hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA0);
+	hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA1);
+	hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA0);
+	hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA1);
+}
+
+static void hdmi_video_packetize(struct dw_hdmi *hdmi)
+{
+	u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
+	u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
+	u32 color_depth = 0;
+	uint val, vp_conf;
+
+	/* set the packetizer registers */
+	val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
+		HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
+		((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
+		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
+	hdmi_write(hdmi, val, HDMI_VP_PR_CD);
+
+	hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PR_STUFFING_MASK,
+		 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE);
+
+	/* data from pixel repeater block */
+	vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
+		  HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
+
+	hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_PR_EN_MASK |
+		 HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf);
+
+	hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
+		 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET);
+
+	hdmi_write(hdmi, remap_size, HDMI_VP_REMAP);
+
+	vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
+		  HDMI_VP_CONF_PP_EN_DISABLE |
+		  HDMI_VP_CONF_YCC422_EN_DISABLE;
+
+	hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_BYPASS_EN_MASK |
+		 HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
+		 vp_conf);
+
+	hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PP_STUFFING_MASK |
+		 HDMI_VP_STUFF_YCC422_STUFFING_MASK,
+		 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
+		 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE);
+
+	hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
+		 output_select);
+}
+
+static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, uint bit)
+{
+	hdmi_mod(hdmi, HDMI_PHY_TST0, HDMI_PHY_TST0_TSTCLR_MASK,
+		 bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
+}
+
+static int hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, u32 msec)
+{
+	ulong start;
+	u32 val;
+
+	start = get_timer(0);
+	do {
+		val = hdmi_read(hdmi, HDMI_IH_I2CMPHY_STAT0);
+		if (val & 0x3) {
+			hdmi_write(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
+			return 0;
+		}
+
+		udelay(100);
+	} while (get_timer(start) < msec);
+
+	return 1;
+}
+
+static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, uint data, uint addr)
+{
+	hdmi_write(hdmi, 0xff, HDMI_IH_I2CMPHY_STAT0);
+	hdmi_write(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
+	hdmi_write(hdmi, (u8)(data >> 8), HDMI_PHY_I2CM_DATAO_1_ADDR);
+	hdmi_write(hdmi, (u8)(data >> 0), HDMI_PHY_I2CM_DATAO_0_ADDR);
+	hdmi_write(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
+		   HDMI_PHY_I2CM_OPERATION_ADDR);
+
+	hdmi_phy_wait_i2c_done(hdmi, 1000);
+}
+
+static void hdmi_phy_enable_power(struct dw_hdmi *hdmi, uint enable)
+{
+	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_PDZ_MASK,
+		 enable << HDMI_PHY_CONF0_PDZ_OFFSET);
+}
+
+static void hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, uint enable)
+{
+	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_ENTMDS_MASK,
+		 enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
+}
+
+static void hdmi_phy_enable_spare(struct dw_hdmi *hdmi, uint enable)
+{
+	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SPARECTRL_MASK,
+		 enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET);
+}
+
+static void hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, uint enable)
+{
+	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK,
+		 enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
+}
+
+static void hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, uint enable)
+{
+	hdmi_mod(hdmi, HDMI_PHY_CONF0,
+		 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK,
+		 enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
+}
+
+static void hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, uint enable)
+{
+	hdmi_mod(hdmi, HDMI_PHY_CONF0,
+		 HDMI_PHY_CONF0_SELDATAENPOL_MASK,
+		 enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
+}
+
+static void hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi,
+					   uint enable)
+{
+	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SELDIPIF_MASK,
+		 enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
+}
+
+static int hdmi_phy_configure(struct dw_hdmi *hdmi, u32 mpixelclock)
+{
+	ulong start;
+	uint i, val;
+
+	if (!hdmi->mpll_cfg || !hdmi->phy_cfg)
+		return -1;
+
+	/* gen2 tx power off */
+	hdmi_phy_gen2_txpwron(hdmi, 0);
+
+	/* gen2 pddq */
+	hdmi_phy_gen2_pddq(hdmi, 1);
+
+	/* phy reset */
+	hdmi_write(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
+	hdmi_write(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
+	hdmi_write(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
+
+	hdmi_phy_test_clear(hdmi, 1);
+	hdmi_write(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
+		   HDMI_PHY_I2CM_SLAVE_ADDR);
+	hdmi_phy_test_clear(hdmi, 0);
+
+	/* pll/mpll cfg - always match on final entry */
+	for (i = 0; hdmi->mpll_cfg[i].mpixelclock != (~0ul); i++)
+		if (mpixelclock <= hdmi->mpll_cfg[i].mpixelclock)
+			break;
+
+	hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
+	hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
+	hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].curr, PHY_PLLCURRCTRL);
+
+	hdmi_phy_i2c_write(hdmi, 0x0000, PHY_PLLPHBYCTRL);
+	hdmi_phy_i2c_write(hdmi, 0x0006, PHY_PLLCLKBISTPHASE);
+
+	for (i = 0; hdmi->phy_cfg[i].mpixelclock != (~0ul); i++)
+		if (mpixelclock <= hdmi->phy_cfg[i].mpixelclock)
+			break;
+
+	/*
+	 * resistance term 133ohm cfg
+	 * preemp cgf 0.00
+	 * tx/ck lvl 10
+	 */
+	hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].term, PHY_TXTERM);
+	hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].sym_ctr, PHY_CKSYMTXCTRL);
+	hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].vlev_ctr, PHY_VLEVCTRL);
+
+	/* remove clk term */
+	hdmi_phy_i2c_write(hdmi, 0x8000, PHY_CKCALCTRL);
+
+	hdmi_phy_enable_power(hdmi, 1);
+
+	/* toggle tmds enable */
+	hdmi_phy_enable_tmds(hdmi, 0);
+	hdmi_phy_enable_tmds(hdmi, 1);
+
+	/* gen2 tx power on */
+	hdmi_phy_gen2_txpwron(hdmi, 1);
+	hdmi_phy_gen2_pddq(hdmi, 0);
+
+	hdmi_phy_enable_spare(hdmi, 1);
+
+	/* wait for phy pll lock */
+	start = get_timer(0);
+	do {
+		val = hdmi_read(hdmi, HDMI_PHY_STAT0);
+		if (!(val & HDMI_PHY_TX_PHY_LOCK))
+			return 0;
+
+		udelay(100);
+	} while (get_timer(start) < 5);
+
+	return -1;
+}
+
+static void hdmi_av_composer(struct dw_hdmi *hdmi,
+			     const struct display_timing *edid)
+{
+	bool mdataenablepolarity = true;
+	uint inv_val;
+	uint hbl;
+	uint vbl;
+
+	hbl = edid->hback_porch.typ + edid->hfront_porch.typ +
+			edid->hsync_len.typ;
+	vbl = edid->vback_porch.typ + edid->vfront_porch.typ +
+			edid->vsync_len.typ;
+
+	/* set up hdmi_fc_invidconf */
+	inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
+
+	inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
+		   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
+		   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
+
+	inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
+		   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
+		   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
+
+	inv_val |= (mdataenablepolarity ?
+		   HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
+		   HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
+
+	/*
+	 * TODO(sjg@chromium.org>: Need to check for HDMI / DVI
+	 * inv_val |= (edid->hdmi_monitor_detected ?
+	 *	   HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
+	 *	   HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
+	 */
+	inv_val |= HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE;
+
+	inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
+
+	inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
+
+	hdmi_write(hdmi, inv_val, HDMI_FC_INVIDCONF);
+
+	/* set up horizontal active pixel width */
+	hdmi_write(hdmi, edid->hactive.typ >> 8, HDMI_FC_INHACTV1);
+	hdmi_write(hdmi, edid->hactive.typ, HDMI_FC_INHACTV0);
+
+	/* set up vertical active lines */
+	hdmi_write(hdmi, edid->vactive.typ >> 8, HDMI_FC_INVACTV1);
+	hdmi_write(hdmi, edid->vactive.typ, HDMI_FC_INVACTV0);
+
+	/* set up horizontal blanking pixel region width */
+	hdmi_write(hdmi, hbl >> 8, HDMI_FC_INHBLANK1);
+	hdmi_write(hdmi, hbl, HDMI_FC_INHBLANK0);
+
+	/* set up vertical blanking pixel region width */
+	hdmi_write(hdmi, vbl, HDMI_FC_INVBLANK);
+
+	/* set up hsync active edge delay width (in pixel clks) */
+	hdmi_write(hdmi, edid->hfront_porch.typ >> 8, HDMI_FC_HSYNCINDELAY1);
+	hdmi_write(hdmi, edid->hfront_porch.typ, HDMI_FC_HSYNCINDELAY0);
+
+	/* set up vsync active edge delay (in lines) */
+	hdmi_write(hdmi, edid->vfront_porch.typ, HDMI_FC_VSYNCINDELAY);
+
+	/* set up hsync active pulse width (in pixel clks) */
+	hdmi_write(hdmi, edid->hsync_len.typ >> 8, HDMI_FC_HSYNCINWIDTH1);
+	hdmi_write(hdmi, edid->hsync_len.typ, HDMI_FC_HSYNCINWIDTH0);
+
+	/* set up vsync active edge delay (in lines) */
+	hdmi_write(hdmi, edid->vsync_len.typ, HDMI_FC_VSYNCINWIDTH);
+}
+
+/* hdmi initialization step b.4 */
+static void hdmi_enable_video_path(struct dw_hdmi *hdmi)
+{
+	uint clkdis;
+
+	/* control period minimum duration */
+	hdmi_write(hdmi, 12, HDMI_FC_CTRLDUR);
+	hdmi_write(hdmi, 32, HDMI_FC_EXCTRLDUR);
+	hdmi_write(hdmi, 1, HDMI_FC_EXCTRLSPAC);
+
+	/* set to fill tmds data channels */
+	hdmi_write(hdmi, 0x0b, HDMI_FC_CH0PREAM);
+	hdmi_write(hdmi, 0x16, HDMI_FC_CH1PREAM);
+	hdmi_write(hdmi, 0x21, HDMI_FC_CH2PREAM);
+
+	hdmi_write(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
+		   HDMI_MC_FLOWCTRL);
+
+	/* enable pixel clock and tmds data path */
+	clkdis = 0x7f;
+	clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
+	hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
+
+	clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
+	hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
+
+	clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
+	hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
+}
+
+/* workaround to clear the overflow condition */
+static void hdmi_clear_overflow(struct dw_hdmi *hdmi)
+{
+	uint val, count;
+
+	/* tmds software reset */
+	hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
+
+	val = hdmi_read(hdmi, HDMI_FC_INVIDCONF);
+
+	for (count = 0; count < 4; count++)
+		hdmi_write(hdmi, val, HDMI_FC_INVIDCONF);
+}
+
+static void hdmi_audio_set_format(struct dw_hdmi *hdmi)
+{
+	hdmi_write(hdmi, HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0,
+		   HDMI_AUD_CONF0);
+
+
+	hdmi_write(hdmi, HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE |
+		   HDMI_AUD_CONF1_I2S_WIDTH_16BIT, HDMI_AUD_CONF1);
+
+	hdmi_write(hdmi, 0x00, HDMI_AUD_CONF2);
+}
+
+static void hdmi_audio_fifo_reset(struct dw_hdmi *hdmi)
+{
+	hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, HDMI_MC_SWRSTZ);
+	hdmi_write(hdmi, HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, HDMI_AUD_CONF0);
+
+	hdmi_write(hdmi, 0x00, HDMI_AUD_INT);
+	hdmi_write(hdmi, 0x00, HDMI_AUD_INT1);
+}
+
+static int hdmi_get_plug_in_status(struct dw_hdmi *hdmi)
+{
+	uint val = hdmi_read(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD;
+
+	return !!val;
+}
+
+static int hdmi_ddc_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
+{
+	u32 val;
+	ulong start;
+
+	start = get_timer(0);
+	do {
+		val = hdmi_read(hdmi, HDMI_IH_I2CM_STAT0);
+		if (val & 0x2) {
+			hdmi_write(hdmi, val, HDMI_IH_I2CM_STAT0);
+			return 0;
+		}
+
+		udelay(100);
+	} while (get_timer(start) < msec);
+
+	return 1;
+}
+
+static void hdmi_ddc_reset(struct dw_hdmi *hdmi)
+{
+	hdmi_mod(hdmi, HDMI_I2CM_SOFTRSTZ, HDMI_I2CM_SOFTRSTZ_MASK, 0);
+}
+
+static int hdmi_read_edid(struct dw_hdmi *hdmi, int block, u8 *buff)
+{
+	int shift = (block % 2) * 0x80;
+	int edid_read_err = 0;
+	u32 trytime = 5;
+	u32 n;
+
+	/* set ddc i2c clk which devided from ddc_clk to 100khz */
+	hdmi_write(hdmi, hdmi->i2c_clk_high, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
+	hdmi_write(hdmi, hdmi->i2c_clk_low, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
+	hdmi_mod(hdmi, HDMI_I2CM_DIV, HDMI_I2CM_DIV_FAST_STD_MODE,
+		 HDMI_I2CM_DIV_STD_MODE);
+
+	hdmi_write(hdmi, HDMI_I2CM_SLAVE_DDC_ADDR, HDMI_I2CM_SLAVE);
+	hdmi_write(hdmi, HDMI_I2CM_SEGADDR_DDC, HDMI_I2CM_SEGADDR);
+	hdmi_write(hdmi, block >> 1, HDMI_I2CM_SEGPTR);
+
+	while (trytime--) {
+		edid_read_err = 0;
+
+		for (n = 0; n < HDMI_EDID_BLOCK_SIZE; n++) {
+			hdmi_write(hdmi, shift + n, HDMI_I2CM_ADDRESS);
+
+			if (block == 0)
+				hdmi_write(hdmi, HDMI_I2CM_OP_RD8,
+					   HDMI_I2CM_OPERATION);
+			else
+				hdmi_write(hdmi, HDMI_I2CM_OP_RD8_EXT,
+					   HDMI_I2CM_OPERATION);
+
+			if (hdmi_ddc_wait_i2c_done(hdmi, 10)) {
+				hdmi_ddc_reset(hdmi);
+				edid_read_err = 1;
+				break;
+			}
+
+			buff[n] = hdmi_read(hdmi, HDMI_I2CM_DATAI);
+		}
+
+		if (!edid_read_err)
+			break;
+	}
+
+	return edid_read_err;
+}
+
+static const u8 pre_buf[] = {
+	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
+	0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00,
+	0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78,
+	0x2a, 0xd9, 0x45, 0xa2, 0x55, 0x4d, 0xa0, 0x27,
+	0x12, 0x50, 0x54, 0xb7, 0xef, 0x00, 0x71, 0x4f,
+	0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00,
+	0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x00, 0x02, 0x3a,
+	0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
+	0x45, 0x00, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
+	0x00, 0x00, 0x00, 0xff, 0x00, 0x44, 0x34, 0x4c,
+	0x4d, 0x54, 0x46, 0x30, 0x37, 0x35, 0x39, 0x37,
+	0x36, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32,
+	0x4b, 0x18, 0x53, 0x11, 0x00, 0x0a, 0x20, 0x20,
+	0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
+	0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x53,
+	0x32, 0x33, 0x38, 0x0a, 0x20, 0x20, 0x01, 0xb0,
+	0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03,
+	0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f,
+	0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x17, 0x07,
+	0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00,
+	0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0,
+	0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0xfd, 0x1e,
+	0x11, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72,
+	0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00,
+	0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 0x01, 0x1d,
+	0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28,
+	0x55, 0x40, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
+	0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20,
+	0x0c, 0x40, 0x55, 0x00, 0xfd, 0x1e, 0x11, 0x00,
+	0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9,
+};
+
+int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
+{
+	int i, ret;
+
+	/* hdmi phy spec says to do the phy initialization sequence twice */
+	for (i = 0; i < 2; i++) {
+		hdmi_phy_sel_data_en_pol(hdmi, 1);
+		hdmi_phy_sel_interface_control(hdmi, 0);
+		hdmi_phy_enable_tmds(hdmi, 0);
+		hdmi_phy_enable_power(hdmi, 0);
+
+		ret = hdmi_phy_configure(hdmi, mpixelclock);
+		if (ret) {
+			debug("hdmi phy config failure %d\n", ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi)
+{
+	ulong start;
+
+	start = get_timer(0);
+	do {
+		if (hdmi_get_plug_in_status(hdmi))
+			return 0;
+		udelay(100);
+	} while (get_timer(start) < 300);
+
+	return -1;
+}
+
+void dw_hdmi_phy_init(struct dw_hdmi *hdmi)
+{
+	/* enable phy i2cm done irq */
+	hdmi_write(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
+		   HDMI_PHY_I2CM_INT_ADDR);
+
+	/* enable phy i2cm nack & arbitration error irq */
+	hdmi_write(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
+		   HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
+		   HDMI_PHY_I2CM_CTLINT_ADDR);
+
+	/* enable cable hot plug irq */
+	hdmi_write(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
+
+	/* clear hotplug interrupts */
+	hdmi_write(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
+}
+
+int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size)
+{
+	u32 edid_size = HDMI_EDID_BLOCK_SIZE;
+	int ret;
+
+	if (0) {
+		edid_size = sizeof(pre_buf);
+		memcpy(buf, pre_buf, edid_size);
+	} else {
+		ret = hdmi_read_edid(hdmi, 0, buf);
+		if (ret) {
+			debug("failed to read edid.\n");
+			return -1;
+		}
+
+		if (buf[0x7e] != 0) {
+			hdmi_read_edid(hdmi, 1, buf + HDMI_EDID_BLOCK_SIZE);
+			edid_size += HDMI_EDID_BLOCK_SIZE;
+		}
+	}
+
+	return edid_size;
+}
+
+int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid)
+{
+	int ret;
+
+	debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
+	      edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ);
+
+	hdmi_av_composer(hdmi, edid);
+
+	ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
+	if (ret)
+		return ret;
+
+	hdmi_enable_video_path(hdmi);
+
+	hdmi_audio_fifo_reset(hdmi);
+	hdmi_audio_set_format(hdmi);
+	hdmi_audio_set_samplerate(hdmi, edid->pixelclock.typ);
+
+	hdmi_video_packetize(hdmi);
+	hdmi_video_sample(hdmi);
+
+	hdmi_clear_overflow(hdmi);
+
+	return 0;
+}
+
+void dw_hdmi_init(struct dw_hdmi *hdmi)
+{
+	uint ih_mute;
+
+	/*
+	 * boot up defaults are:
+	 * hdmi_ih_mute   = 0x03 (disabled)
+	 * hdmi_ih_mute_* = 0x00 (enabled)
+	 *
+	 * disable top level interrupt bits in hdmi block
+	 */
+	ih_mute = /*hdmi_read(hdmi, HDMI_IH_MUTE) |*/
+		  HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
+		  HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
+
+	hdmi_write(hdmi, ih_mute, HDMI_IH_MUTE);
+
+	/* enable i2c master done irq */
+	hdmi_write(hdmi, ~0x04, HDMI_I2CM_INT);
+
+	/* enable i2c client nack % arbitration error irq */
+	hdmi_write(hdmi, ~0x44, HDMI_I2CM_CTLINT);
+}
diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
index 7962f86..755350b 100644
--- a/drivers/video/rockchip/Makefile
+++ b/drivers/video/rockchip/Makefile
@@ -5,4 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o
+obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o ../dw_hdmi.o
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index c8608db..db07588 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -9,6 +9,7 @@
 #include <clk.h>
 #include <display.h>
 #include <dm.h>
+#include <dw_hdmi.h>
 #include <edid.h>
 #include <regmap.h>
 #include <syscon.h>
@@ -16,73 +17,13 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/grf_rk3288.h>
-#include <asm/arch/hdmi_rk3288.h>
 #include <power/regulator.h>
 
-struct tmds_n_cts {
-	u32 tmds;
-	u32 cts;
-	u32 n;
-};
-
 struct rk_hdmi_priv {
-	struct rk3288_hdmi *regs;
+	struct dw_hdmi hdmi;
 	struct rk3288_grf *grf;
 };
 
-static const struct tmds_n_cts n_cts_table[] = {
-	{
-		.tmds = 25175000, .n = 6144, .cts = 25175,
-	}, {
-		.tmds = 25200000, .n = 6144, .cts = 25200,
-	}, {
-		.tmds = 27000000, .n = 6144, .cts = 27000,
-	}, {
-		.tmds = 27027000, .n = 6144, .cts = 27027,
-	}, {
-		.tmds = 40000000, .n = 6144, .cts = 40000,
-	}, {
-		.tmds = 54000000, .n = 6144, .cts = 54000,
-	}, {
-		.tmds = 54054000, .n = 6144, .cts = 54054,
-	}, {
-		.tmds = 65000000, .n = 6144, .cts = 65000,
-	}, {
-		.tmds = 74176000, .n = 11648, .cts = 140625,
-	}, {
-		.tmds = 74250000, .n = 6144, .cts = 74250,
-	}, {
-		.tmds = 83500000, .n = 6144, .cts = 83500,
-	}, {
-		.tmds = 106500000, .n = 6144, .cts = 106500,
-	}, {
-		.tmds = 108000000, .n = 6144, .cts = 108000,
-	}, {
-		.tmds = 148352000, .n = 5824, .cts = 140625,
-	}, {
-		.tmds = 148500000, .n = 6144, .cts = 148500,
-	}, {
-		.tmds = 297000000, .n = 5120, .cts = 247500,
-	}
-};
-
-struct hdmi_mpll_config {
-	u64 mpixelclock;
-	/* Mode of Operation and PLL Dividers Control Register */
-	u32 cpce;
-	/* PLL Gmp Control Register */
-	u32 gmp;
-	/* PLL Current COntrol Register */
-	u32 curr;
-};
-
-struct hdmi_phy_config {
-	u64 mpixelclock;
-	u32 sym_ctr;    /* clock symbol and transmitter control */
-	u32 term;       /* transmission termination value */
-	u32 vlev_ctr;   /* voltage level control */
-};
-
 static const struct hdmi_phy_config rockchip_phy_config[] = {
 	{
 		.mpixelclock = 74250000,
@@ -124,693 +65,41 @@ static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
 	}
 };
 
-static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, u32 cts)
-{
-	uint cts3;
-	uint n3;
-
-	/* first set ncts_atomic_write (if present) */
-	n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
-	writel(n3, &regs->aud_n3);
-
-	/* set cts_manual (if present) */
-	cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
-
-	cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
-	cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
-
-	/* write cts values; cts3 must be written first */
-	writel(cts3, &regs->aud_cts3);
-	writel((cts >> 8) & 0xff, &regs->aud_cts2);
-	writel(cts & 0xff, &regs->aud_cts1);
-
-	/* write n values; n1 must be written last */
-	n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK;
-	writel(n3, &regs->aud_n3);
-	writel((n >> 8) & 0xff, &regs->aud_n2);
-	writel(n & 0xff, &regs->aud_n1);
-
-	writel(HDMI_AUD_INPUTCLKFS_128, &regs->aud_inputclkfs);
-}
-
-static int hdmi_lookup_n_cts(u32 pixel_clk)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(n_cts_table); i++)
-		if (pixel_clk <= n_cts_table[i].tmds)
-			break;
-
-	if (i >= ARRAY_SIZE(n_cts_table))
-		return -1;
-
-	return i;
-}
-
-static void hdmi_audio_set_samplerate(struct rk3288_hdmi *regs, u32 pixel_clk)
-{
-	u32 clk_n, clk_cts;
-	int index;
-
-	index = hdmi_lookup_n_cts(pixel_clk);
-	if (index == -1) {
-		debug("audio not supported for pixel clk %d\n", pixel_clk);
-		return;
-	}
-
-	clk_n = n_cts_table[index].n;
-	clk_cts = n_cts_table[index].cts;
-	hdmi_set_clock_regenerator(regs, clk_n, clk_cts);
-}
-
-/*
- * this submodule is responsible for the video data synchronization.
- * for example, for rgb 4:4:4 input, the data map is defined as
- *			pin{47~40} <==> r[7:0]
- *			pin{31~24} <==> g[7:0]
- *			pin{15~8}  <==> b[7:0]
- */
-static void hdmi_video_sample(struct rk3288_hdmi *regs)
-{
-	u32 color_format = 0x01;
-	uint val;
-
-	val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
-	      ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
-	      HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
-
-	writel(val, &regs->tx_invid0);
-
-	/* enable tx stuffing: when de is inactive, fix the output data to 0 */
-	val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
-	      HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
-	      HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
-	writel(val, &regs->tx_instuffing);
-	writel(0x0, &regs->tx_gydata0);
-	writel(0x0, &regs->tx_gydata1);
-	writel(0x0, &regs->tx_rcrdata0);
-	writel(0x0, &regs->tx_rcrdata1);
-	writel(0x0, &regs->tx_bcbdata0);
-	writel(0x0, &regs->tx_bcbdata1);
-}
-
-static void hdmi_video_packetize(struct rk3288_hdmi *regs)
-{
-	u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
-	u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
-	u32 color_depth = 0;
-	uint val, vp_conf;
-
-	/* set the packetizer registers */
-	val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
-		HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
-		((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
-		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
-	writel(val, &regs->vp_pr_cd);
-
-	clrsetbits_le32(&regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK,
-			HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE);
-
-	/* data from pixel repeater block */
-	vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
-		  HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
-
-	clrsetbits_le32(&regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK |
-			HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf);
-
-	clrsetbits_le32(&regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
-			1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET);
-
-	writel(remap_size, &regs->vp_remap);
-
-	vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
-		  HDMI_VP_CONF_PP_EN_DISABLE |
-		  HDMI_VP_CONF_YCC422_EN_DISABLE;
-
-	clrsetbits_le32(&regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK |
-			HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
-			vp_conf);
-
-	clrsetbits_le32(&regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK |
-			HDMI_VP_STUFF_YCC422_STUFFING_MASK,
-			HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
-			HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE);
-
-	clrsetbits_le32(&regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
-			output_select);
-}
-
-static inline void hdmi_phy_test_clear(struct rk3288_hdmi *regs, uint bit)
-{
-	clrsetbits_le32(&regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK,
-			bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
-}
-
-static int hdmi_phy_wait_i2c_done(struct rk3288_hdmi *regs, u32 msec)
-{
-	ulong start;
-	u32 val;
-
-	start = get_timer(0);
-	do {
-		val = readl(&regs->ih_i2cmphy_stat0);
-		if (val & 0x3) {
-			writel(val, &regs->ih_i2cmphy_stat0);
-			return 0;
-		}
-
-		udelay(100);
-	} while (get_timer(start) < msec);
-
-	return 1;
-}
-
-static void hdmi_phy_i2c_write(struct rk3288_hdmi *regs, uint data, uint addr)
-{
-	writel(0xff, &regs->ih_i2cmphy_stat0);
-	writel(addr, &regs->phy_i2cm_address_addr);
-	writel((u8)(data >> 8), &regs->phy_i2cm_datao_1_addr);
-	writel((u8)(data >> 0), &regs->phy_i2cm_datao_0_addr);
-	writel(HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
-	       &regs->phy_i2cm_operation_addr);
-
-	hdmi_phy_wait_i2c_done(regs, 1000);
-}
-
-static void hdmi_phy_enable_power(struct rk3288_hdmi *regs, uint enable)
-{
-	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK,
-			enable << HDMI_PHY_CONF0_PDZ_OFFSET);
-}
-
-static void hdmi_phy_enable_tmds(struct rk3288_hdmi *regs, uint enable)
-{
-	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK,
-			enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
-}
-
-static void hdmi_phy_enable_spare(struct rk3288_hdmi *regs, uint enable)
-{
-	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK,
-			enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET);
-}
-
-static void hdmi_phy_gen2_pddq(struct rk3288_hdmi *regs, uint enable)
-{
-	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK,
-			enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
-}
-
-static void hdmi_phy_gen2_txpwron(struct rk3288_hdmi *regs, uint enable)
-{
-	clrsetbits_le32(&regs->phy_conf0,
-			HDMI_PHY_CONF0_GEN2_TXPWRON_MASK,
-			enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
-}
-
-static void hdmi_phy_sel_data_en_pol(struct rk3288_hdmi *regs, uint enable)
-{
-	clrsetbits_le32(&regs->phy_conf0,
-			HDMI_PHY_CONF0_SELDATAENPOL_MASK,
-			enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
-}
-
-static void hdmi_phy_sel_interface_control(struct rk3288_hdmi *regs,
-					   uint enable)
-{
-	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK,
-			enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
-}
-
-static int hdmi_phy_configure(struct rk3288_hdmi *regs, u32 mpixelclock)
-{
-	ulong start;
-	uint i, val;
-
-	writel(HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
-	       &regs->mc_flowctrl);
-
-	/* gen2 tx power off */
-	hdmi_phy_gen2_txpwron(regs, 0);
-
-	/* gen2 pddq */
-	hdmi_phy_gen2_pddq(regs, 1);
-
-	/* phy reset */
-	writel(HDMI_MC_PHYRSTZ_DEASSERT, &regs->mc_phyrstz);
-	writel(HDMI_MC_PHYRSTZ_ASSERT, &regs->mc_phyrstz);
-	writel(HDMI_MC_HEACPHY_RST_ASSERT, &regs->mc_heacphy_rst);
-
-	hdmi_phy_test_clear(regs, 1);
-	writel(HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, &regs->phy_i2cm_slave_addr);
-	hdmi_phy_test_clear(regs, 0);
-
-	/* pll/mpll cfg - always match on final entry */
-	for (i = 0; rockchip_mpll_cfg[i].mpixelclock != (~0ul); i++)
-		if (mpixelclock <= rockchip_mpll_cfg[i].mpixelclock)
-			break;
-
-	hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
-	hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
-	hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].curr, PHY_PLLCURRCTRL);
-
-	hdmi_phy_i2c_write(regs, 0x0000, PHY_PLLPHBYCTRL);
-	hdmi_phy_i2c_write(regs, 0x0006, PHY_PLLCLKBISTPHASE);
-
-	for (i = 0; rockchip_phy_config[i].mpixelclock != (~0ul); i++)
-		if (mpixelclock <= rockchip_phy_config[i].mpixelclock)
-			break;
-
-	/*
-	 * resistance term 133ohm cfg
-	 * preemp cgf 0.00
-	 * tx/ck lvl 10
-	 */
-	hdmi_phy_i2c_write(regs, rockchip_phy_config[i].term, PHY_TXTERM);
-	hdmi_phy_i2c_write(regs, rockchip_phy_config[i].sym_ctr,
-			   PHY_CKSYMTXCTRL);
-	hdmi_phy_i2c_write(regs, rockchip_phy_config[i].vlev_ctr, PHY_VLEVCTRL);
-
-	/* remove clk term */
-	hdmi_phy_i2c_write(regs, 0x8000, PHY_CKCALCTRL);
-
-	hdmi_phy_enable_power(regs, 1);
-
-	/* toggle tmds enable */
-	hdmi_phy_enable_tmds(regs, 0);
-	hdmi_phy_enable_tmds(regs, 1);
-
-	/* gen2 tx power on */
-	hdmi_phy_gen2_txpwron(regs, 1);
-	hdmi_phy_gen2_pddq(regs, 0);
-
-	hdmi_phy_enable_spare(regs, 1);
-
-	/* wait for phy pll lock */
-	start = get_timer(0);
-	do {
-		val = readl(&regs->phy_stat0);
-		if (!(val & HDMI_PHY_TX_PHY_LOCK))
-			return 0;
-
-		udelay(100);
-	} while (get_timer(start) < 5);
-
-	return -1;
-}
-
-static int hdmi_phy_init(struct rk3288_hdmi *regs, uint mpixelclock)
-{
-	int i, ret;
-
-	/* hdmi phy spec says to do the phy initialization sequence twice */
-	for (i = 0; i < 2; i++) {
-		hdmi_phy_sel_data_en_pol(regs, 1);
-		hdmi_phy_sel_interface_control(regs, 0);
-		hdmi_phy_enable_tmds(regs, 0);
-		hdmi_phy_enable_power(regs, 0);
-
-		ret = hdmi_phy_configure(regs, mpixelclock);
-		if (ret) {
-			debug("hdmi phy config failure %d\n", ret);
-			return ret;
-		}
-	}
-
-	return 0;
-}
-
-static void hdmi_av_composer(struct rk3288_hdmi *regs,
-			     const struct display_timing *edid)
-{
-	bool mdataenablepolarity = true;
-	uint inv_val;
-	uint hbl;
-	uint vbl;
-
-	hbl = edid->hback_porch.typ + edid->hfront_porch.typ +
-			edid->hsync_len.typ;
-	vbl = edid->vback_porch.typ + edid->vfront_porch.typ +
-			edid->vsync_len.typ;
-
-	/* set up hdmi_fc_invidconf */
-	inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
-
-	inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
-		   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
-		   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
-
-	inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
-		   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
-		   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
-
-	inv_val |= (mdataenablepolarity ?
-		   HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
-		   HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
-
-	/*
-	 * TODO(sjg@chromium.org>: Need to check for HDMI / DVI
-	 * inv_val |= (edid->hdmi_monitor_detected ?
-	 *	   HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
-	 *	   HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
-	 */
-	inv_val |= HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE;
-
-	inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
-
-	inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
-
-	writel(inv_val, &regs->fc_invidconf);
-
-	/* set up horizontal active pixel width */
-	writel(edid->hactive.typ >> 8, &regs->fc_inhactv1);
-	writel(edid->hactive.typ, &regs->fc_inhactv0);
-
-	/* set up vertical active lines */
-	writel(edid->vactive.typ >> 8, &regs->fc_invactv1);
-	writel(edid->vactive.typ, &regs->fc_invactv0);
-
-	/* set up horizontal blanking pixel region width */
-	writel(hbl >> 8, &regs->fc_inhblank1);
-	writel(hbl, &regs->fc_inhblank0);
-
-	/* set up vertical blanking pixel region width */
-	writel(vbl, &regs->fc_invblank);
-
-	/* set up hsync active edge delay width (in pixel clks) */
-	writel(edid->hfront_porch.typ >> 8, &regs->fc_hsyncindelay1);
-	writel(edid->hfront_porch.typ, &regs->fc_hsyncindelay0);
-
-	/* set up vsync active edge delay (in lines) */
-	writel(edid->vfront_porch.typ, &regs->fc_vsyncindelay);
-
-	/* set up hsync active pulse width (in pixel clks) */
-	writel(edid->hsync_len.typ >> 8, &regs->fc_hsyncinwidth1);
-	writel(edid->hsync_len.typ, &regs->fc_hsyncinwidth0);
-
-	/* set up vsync active edge delay (in lines) */
-	writel(edid->vsync_len.typ, &regs->fc_vsyncinwidth);
-}
-
-/* hdmi initialization step b.4 */
-static void hdmi_enable_video_path(struct rk3288_hdmi *regs)
-{
-	uint clkdis;
-
-	/* control period minimum duration */
-	writel(12, &regs->fc_ctrldur);
-	writel(32, &regs->fc_exctrldur);
-	writel(1, &regs->fc_exctrlspac);
-
-	/* set to fill tmds data channels */
-	writel(0x0b, &regs->fc_ch0pream);
-	writel(0x16, &regs->fc_ch1pream);
-	writel(0x21, &regs->fc_ch2pream);
-
-	/* enable pixel clock and tmds data path */
-	clkdis = 0x7f;
-	clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
-	writel(clkdis, &regs->mc_clkdis);
-
-	clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
-	writel(clkdis, &regs->mc_clkdis);
-
-	clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
-	writel(clkdis, &regs->mc_clkdis);
-}
-
-/* workaround to clear the overflow condition */
-static void hdmi_clear_overflow(struct rk3288_hdmi *regs)
-{
-	uint val, count;
-
-	/* tmds software reset */
-	writel((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &regs->mc_swrstz);
-
-	val = readl(&regs->fc_invidconf);
-
-	for (count = 0; count < 4; count++)
-		writel(val, &regs->fc_invidconf);
-}
-
-static void hdmi_audio_set_format(struct rk3288_hdmi *regs)
-{
-	writel(HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0,
-	       &regs->aud_conf0);
-
-
-	writel(HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE |
-	       HDMI_AUD_CONF1_I2S_WIDTH_16BIT, &regs->aud_conf1);
-
-	writel(0x00, &regs->aud_conf2);
-}
-
-static void hdmi_audio_fifo_reset(struct rk3288_hdmi *regs)
-{
-	writel((u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, &regs->mc_swrstz);
-	writel(HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, &regs->aud_conf0);
-
-	writel(0x00, &regs->aud_int);
-	writel(0x00, &regs->aud_int1);
-}
-
-static void hdmi_init_interrupt(struct rk3288_hdmi *regs)
-{
-	uint ih_mute;
-
-	/*
-	 * boot up defaults are:
-	 * hdmi_ih_mute   = 0x03 (disabled)
-	 * hdmi_ih_mute_* = 0x00 (enabled)
-	 *
-	 * disable top level interrupt bits in hdmi block
-	 */
-	ih_mute = readl(&regs->ih_mute) |
-		  HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
-		  HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
-
-	writel(ih_mute, &regs->ih_mute);
-
-	/* enable i2c master done irq */
-	writel(~0x04, &regs->i2cm_int);
-
-	/* enable i2c client nack % arbitration error irq */
-	writel(~0x44, &regs->i2cm_ctlint);
-
-	/* enable phy i2cm done irq */
-	writel(HDMI_PHY_I2CM_INT_ADDR_DONE_POL, &regs->phy_i2cm_int_addr);
-
-	/* enable phy i2cm nack & arbitration error irq */
-	writel(HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
-		HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
-		&regs->phy_i2cm_ctlint_addr);
-
-	/* enable cable hot plug irq */
-	writel((u8)~HDMI_PHY_HPD, &regs->phy_mask0);
-
-	/* clear hotplug interrupts */
-	writel(HDMI_IH_PHY_STAT0_HPD, &regs->ih_phy_stat0);
-}
-
-static int hdmi_get_plug_in_status(struct rk3288_hdmi *regs)
-{
-	uint val = readl(&regs->phy_stat0) & HDMI_PHY_HPD;
-
-	return !!val;
-}
-
-static int hdmi_wait_for_hpd(struct rk3288_hdmi *regs)
-{
-	ulong start;
-
-	start = get_timer(0);
-	do {
-		if (hdmi_get_plug_in_status(regs))
-			return 0;
-		udelay(100);
-	} while (get_timer(start) < 300);
-
-	return -1;
-}
-
-static int hdmi_ddc_wait_i2c_done(struct rk3288_hdmi *regs, int msec)
-{
-	u32 val;
-	ulong start;
-
-	start = get_timer(0);
-	do {
-		val = readl(&regs->ih_i2cm_stat0);
-		if (val & 0x2) {
-			writel(val, &regs->ih_i2cm_stat0);
-			return 0;
-		}
-
-		udelay(100);
-	} while (get_timer(start) < msec);
-
-	return 1;
-}
-
-static void hdmi_ddc_reset(struct rk3288_hdmi *regs)
-{
-	clrbits_le32(&regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ);
-}
-
-static int hdmi_read_edid(struct rk3288_hdmi *regs, int block, u8 *buff)
-{
-	int shift = (block % 2) * 0x80;
-	int edid_read_err = 0;
-	u32 trytime = 5;
-	u32 n, j, val;
-
-	/* set ddc i2c clk which devided from ddc_clk to 100khz */
-	writel(0x7a, &regs->i2cm_ss_scl_hcnt_0_addr);
-	writel(0x8d, &regs->i2cm_ss_scl_lcnt_0_addr);
-
-	/*
-	 * TODO(sjg@chromium.org): The above values don't work - these ones
-	 * work better, but generate lots of errors in the data.
-	 */
-	writel(0x0d, &regs->i2cm_ss_scl_hcnt_0_addr);
-	writel(0x0d, &regs->i2cm_ss_scl_lcnt_0_addr);
-	clrsetbits_le32(&regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE,
-			HDMI_I2CM_DIV_STD_MODE);
-
-	writel(HDMI_I2CM_SLAVE_DDC_ADDR, &regs->i2cm_slave);
-	writel(HDMI_I2CM_SEGADDR_DDC, &regs->i2cm_segaddr);
-	writel(block >> 1, &regs->i2cm_segptr);
-
-	while (trytime--) {
-		edid_read_err = 0;
-
-		for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
-			writel(shift + 8 * n, &regs->i2c_address);
-
-			if (block == 0)
-				clrsetbits_le32(&regs->i2cm_operation,
-						HDMI_I2CM_OPT_RD8,
-						HDMI_I2CM_OPT_RD8);
-			else
-				clrsetbits_le32(&regs->i2cm_operation,
-						HDMI_I2CM_OPT_RD8_EXT,
-						HDMI_I2CM_OPT_RD8_EXT);
-
-			if (hdmi_ddc_wait_i2c_done(regs, 10)) {
-				hdmi_ddc_reset(regs);
-				edid_read_err = 1;
-				break;
-			}
-
-			for (j = 0; j < 8; j++) {
-				val = readl(&regs->i2cm_buf0 + j);
-				buff[8 * n + j] = val;
-			}
-		}
-
-		if (!edid_read_err)
-			break;
-	}
-
-	return edid_read_err;
-}
-
-static const u8 pre_buf[] = {
-	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
-	0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00,
-	0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78,
-	0x2a, 0xd9, 0x45, 0xa2, 0x55, 0x4d, 0xa0, 0x27,
-	0x12, 0x50, 0x54, 0xb7, 0xef, 0x00, 0x71, 0x4f,
-	0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00,
-	0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x00, 0x02, 0x3a,
-	0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
-	0x45, 0x00, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
-	0x00, 0x00, 0x00, 0xff, 0x00, 0x44, 0x34, 0x4c,
-	0x4d, 0x54, 0x46, 0x30, 0x37, 0x35, 0x39, 0x37,
-	0x36, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32,
-	0x4b, 0x18, 0x53, 0x11, 0x00, 0x0a, 0x20, 0x20,
-	0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
-	0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x53,
-	0x32, 0x33, 0x38, 0x0a, 0x20, 0x20, 0x01, 0xb0,
-	0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03,
-	0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f,
-	0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x17, 0x07,
-	0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00,
-	0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0,
-	0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0xfd, 0x1e,
-	0x11, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72,
-	0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00,
-	0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 0x01, 0x1d,
-	0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28,
-	0x55, 0x40, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
-	0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20,
-	0x0c, 0x40, 0x55, 0x00, 0xfd, 0x1e, 0x11, 0x00,
-	0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9,
-};
-
 static int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
 {
 	struct rk_hdmi_priv *priv = dev_get_priv(dev);
-	u32 edid_size = HDMI_EDID_BLOCK_SIZE;
-	int ret;
-
-	if (0) {
-		edid_size = sizeof(pre_buf);
-		memcpy(buf, pre_buf, edid_size);
-	} else {
-		ret = hdmi_read_edid(priv->regs, 0, buf);
-		if (ret) {
-			debug("failed to read edid.\n");
-			return -1;
-		}
 
-		if (buf[0x7e] != 0) {
-			hdmi_read_edid(priv->regs, 1,
-				       buf + HDMI_EDID_BLOCK_SIZE);
-			edid_size += HDMI_EDID_BLOCK_SIZE;
-		}
-	}
-
-	return edid_size;
+	return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
 }
 
 static int rk_hdmi_enable(struct udevice *dev, int panel_bpp,
 			  const struct display_timing *edid)
 {
 	struct rk_hdmi_priv *priv = dev_get_priv(dev);
-	struct rk3288_hdmi *regs = priv->regs;
-	int ret;
-
-	debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
-	      edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ);
 
-	hdmi_av_composer(regs, edid);
-
-	ret = hdmi_phy_init(regs, edid->pixelclock.typ);
-	if (ret)
-		return ret;
-
-	hdmi_enable_video_path(regs);
-
-	hdmi_audio_fifo_reset(regs);
-	hdmi_audio_set_format(regs);
-	hdmi_audio_set_samplerate(regs, edid->pixelclock.typ);
-
-	hdmi_video_packetize(regs);
-	hdmi_video_sample(regs);
-
-	hdmi_clear_overflow(regs);
-
-	return 0;
+	return dw_hdmi_enable(&priv->hdmi, edid);
 }
 
 static int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
 {
 	struct rk_hdmi_priv *priv = dev_get_priv(dev);
+	struct dw_hdmi *hdmi = &priv->hdmi;
+
+	hdmi->ioaddr = (ulong)dev_get_addr(dev);
+	hdmi->mpll_cfg = rockchip_mpll_cfg;
+	hdmi->phy_cfg = rockchip_phy_config;
+	hdmi->i2c_clk_high = 0x7a;
+	hdmi->i2c_clk_low = 0x8d;
+
+	/*
+	 * TODO(sjg@chromium.org): The above values don't work - these ones
+	 * work better, but generate lots of errors in the data.
+	 */
+	hdmi->i2c_clk_high = 0x0d;
+	hdmi->i2c_clk_low = 0x0d;
+	hdmi->reg_io_width = 4;
+	hdmi->phy_set = dw_hdmi_phy_cfg;
 
-	priv->regs = (struct rk3288_hdmi *)dev_get_addr(dev);
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 
 	return 0;
@@ -820,6 +109,7 @@ static int rk_hdmi_probe(struct udevice *dev)
 {
 	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
 	struct rk_hdmi_priv *priv = dev_get_priv(dev);
+	struct dw_hdmi *hdmi = &priv->hdmi;
 	struct udevice *reg;
 	struct clk clk;
 	int ret;
@@ -863,13 +153,14 @@ static int rk_hdmi_probe(struct udevice *dev)
 	rk_clrsetreg(&priv->grf->soc_con6, 1 << 4,
 		     (vop_id == 1) ? (1 << 4) : 0);
 
-	ret = hdmi_wait_for_hpd(priv->regs);
+	ret = dw_hdmi_phy_wait_for_hpd(hdmi);
 	if (ret < 0) {
 		debug("hdmi can not get hpd signal\n");
 		return -1;
 	}
 
-	hdmi_init_interrupt(priv->regs);
+	dw_hdmi_init(hdmi);
+	dw_hdmi_phy_init(hdmi);
 
 	return 0;
 }
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index aeecb58..bc02f80 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -20,7 +20,6 @@
 #include <asm/arch/cru_rk3288.h>
 #include <asm/arch/grf_rk3288.h>
 #include <asm/arch/edp_rk3288.h>
-#include <asm/arch/hdmi_rk3288.h>
 #include <asm/arch/vop_rk3288.h>
 #include <dm/device-internal.h>
 #include <dm/uclass-internal.h>
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index 7ea4b60..7b1f429 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -81,10 +81,32 @@ static int omap_wdt_set_timeout(unsigned int timeout)
 	return 0;
 }
 
+void hw_watchdog_disable(void)
+{
+	struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
+
+	/*
+	 * Disable watchdog
+	 */
+	writel(0xAAAA, &wdt->wdtwspr);
+	while (readl(&wdt->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdt->wdtwspr);
+	while (readl(&wdt->wdtwwps) != 0x0)
+		;
+}
+
 void hw_watchdog_init(void)
 {
 	struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
 
+	/*
+	 * Make sure the watchdog is disabled. This is unfortunately required
+	 * because writing to various registers with the watchdog running has no
+	 * effect.
+	 */
+	hw_watchdog_disable();
+
 	/* initialize prescaler */
 	while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
 		;
@@ -104,18 +126,3 @@ void hw_watchdog_init(void)
 	while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
 		;
 }
-
-void hw_watchdog_disable(void)
-{
-	struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
-
-	/*
-	 * Disable watchdog
-	 */
-	writel(0xAAAA, &wdt->wdtwspr);
-	while (readl(&wdt->wdtwwps) != 0x0)
-		;
-	writel(0x5555, &wdt->wdtwspr);
-	while (readl(&wdt->wdtwwps) != 0x0)
-		;
-}
diff --git a/dts/Kconfig b/dts/Kconfig
index 4b7d8b1..6fe7a5b 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -14,6 +14,16 @@ config OF_CONTROL
 	  This feature provides for run-time configuration of U-Boot
 	  via a flattened device tree.
 
+config OF_BOARD_FIXUP
+	bool "Board-specific manipulation of Device Tree"
+	help
+	  In certain circumstances it is necessary to be able to modify
+	  U-Boot's device tree (e.g. to delete device from it). This option
+	  make the Device Tree writeable and provides a board-specific
+	  "board_fix_fdt" callback (called during pre-relocation time), which
+	  enables the board initialization to modifiy the Device Tree. The
+	  modified copy is subsequently used by U-Boot after relocation.
+
 config SPL_OF_CONTROL
 	bool "Enable run-time configuration via Device Tree in SPL"
 	depends on SPL && OF_CONTROL
@@ -73,8 +83,8 @@ config OF_LIST
 config OF_SPL_REMOVE_PROPS
 	string "List of device tree properties to drop for SPL"
 	depends on SPL_OF_CONTROL
-	default "interrupt-parent" if SPL_PINCTRL_FULL && SPL_CLK
-	default "clocks clock-names interrupt-parent" if SPL_PINCTRL_FULL
+	default "interrupt-parent" if SPL_PINCTRL && SPL_CLK
+	default "clocks clock-names interrupt-parent" if SPL_PINCTRL
 	default "pinctrl-0 pinctrl-names interrupt-parent" if SPL_CLK
 	default "pinctrl-0 pinctrl-names clocks clock-names interrupt-parent"
 	help
diff --git a/dts/Makefile b/dts/Makefile
index c4ac153..3a93daf 100644
--- a/dts/Makefile
+++ b/dts/Makefile
@@ -12,10 +12,14 @@ ifeq ($(DEVICE_TREE),)
 DEVICE_TREE := unset
 endif
 
+ARCH_PATH := arch/$(ARCH)/dts
+dtb_depends := arch-dtbs
+
 ifneq ($(EXT_DTB),)
 DTB := $(EXT_DTB)
 else
-DTB := arch/$(ARCH)/dts/$(DEVICE_TREE).dtb
+DTB := $(ARCH_PATH)/$(DEVICE_TREE).dtb
+dtb_depends += $(DTB:.dtb=.dts)
 endif
 
 $(obj)/dt.dtb: $(DTB) FORCE
@@ -23,7 +27,10 @@ $(obj)/dt.dtb: $(DTB) FORCE
 
 targets += dt.dtb
 
-$(DTB): arch-dtbs
+$(DTB): $(dtb_depends)
+ifeq ($(EXT_DTB),)
+	$(Q)$(MAKE) $(build)=$(ARCH_PATH) $@
+endif
 	$(Q)test -e $@ || (						\
 	echo >&2;							\
 	echo >&2 "Device Tree Source is not correctly specified.";	\
@@ -33,7 +40,7 @@ $(DTB): arch-dtbs
 	/bin/false)
 
 arch-dtbs:
-	$(Q)$(MAKE) $(build)=arch/$(ARCH)/dts dtbs
+	$(Q)$(MAKE) $(build)=$(ARCH_PATH) dtbs
 
 .SECONDARY: $(obj)/dt.dtb.S
 
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index a8b7e14..a6a9fcf 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -141,19 +141,6 @@ gd_t *global_data;
 "	lwi	r5, r5, %1\n"			\
 "	bra	r5\n"				\
 	: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r5");
-#elif defined(CONFIG_BLACKFIN)
-/*
- * P3 holds the pointer to the global_data, P0 is a call-clobbered
- * register
- */
-#define EXPORT_FUNC(f, a, x, ...)			\
-	asm volatile (			\
-"	.globl _" #x "\n_"		\
-#x ":\n"				\
-"	P0 = [P3 + %0]\n"		\
-"	P0 = [P0 + %1]\n"		\
-"	JUMP (P0)\n"			\
-	: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "P0");
 #elif defined(CONFIG_AVR32)
 /*
  * r6 holds the pointer to the global_data. r8 is call clobbered.
@@ -185,21 +172,6 @@ gd_t *global_data;
 		"	nop\n"				\
 		"	nop\n"				\
 		: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r1", "r2");
-#elif defined(CONFIG_SPARC)
-/*
- * g7 holds the pointer to the global_data. g1 is call clobbered.
- */
-#define EXPORT_FUNC(f, a, x, ...)					\
-	asm volatile(					\
-"	.globl\t" #x "\n"				\
-#x ":\n"						\
-"	set %0, %%g1\n"					\
-"	or %%g1, %%g7, %%g1\n"				\
-"	ld [%%g1], %%g1\n"				\
-"	ld [%%g1 + %1], %%g1\n"				\
-"	jmp %%g1\n"					\
-"	nop\n"						\
-	: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "g1");
 #elif defined(CONFIG_NDS32)
 /*
  * r16 holds the pointer to the global_data. gp is call clobbered.
@@ -213,20 +185,6 @@ gd_t *global_data;
 "	lwi	$r16, [$r16 + (%1)]\n"	\
 "	jr	$r16\n"			\
 	: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "$r16");
-#elif defined(CONFIG_OPENRISC)
-/*
- * r10 holds the pointer to the global_data, r13 is a call-clobbered
- * register
- */
-#define EXPORT_FUNC(f, a, x, ...) \
-	asm volatile (			\
-"	.globl " #x "\n"		\
-#x ":\n"				\
-"	l.lwz	r13, %0(r10)\n"	\
-"	l.lwz	r13, %1(r13)\n"	\
-"	l.jr	r13\n"		\
-"	l.nop\n"				\
-	: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r13");
 #elif defined(CONFIG_ARC)
 /*
  * r25 holds the pointer to the global_data. r10 is call clobbered.
diff --git a/include/ambapp.h b/include/ambapp.h
deleted file mode 100644
index d79fced..0000000
--- a/include/ambapp.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/* Interface for accessing Gaisler AMBA Plug&Play Bus.
- * The AHB bus can be interfaced with a simpler bus -
- * the APB bus, also freely available in GRLIB at
- * www.gaisler.com.
- *
- * (C) Copyright 2009, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __AMBAPP_H__
-#define __AMBAPP_H__
-
-#include <ambapp_ids.h>
-
-#ifndef __ASSEMBLER__
-/* Structures used to access Plug&Play information directly */
-struct ambapp_pnp_ahb {
-	const unsigned int	id;		/* VENDOR, DEVICE, VER, IRQ, */
-	const unsigned int	custom[3];
-	const unsigned int	mbar[4];	/* MASK, ADDRESS, TYPE,
-						 * CACHABLE/PREFETCHABLE */
-};
-
-struct ambapp_pnp_apb {
-	const unsigned int	id;		/* VENDOR, DEVICE, VER, IRQ, */
-	const unsigned int	iobar;		/* MASK, ADDRESS, TYPE,
-						 * CACHABLE/PREFETCHABLE */
-};
-
-/* AMBA Plug&Play AHB Masters & Slaves information locations
- * Max devices is 64 supported by HW, however often only 16
- * are used.
- */
-struct ambapp_pnp_info {
-	struct ambapp_pnp_ahb	masters[64];
-	struct ambapp_pnp_ahb	slaves[63];
-	const unsigned int	unused[4];
-	const unsigned int	systemid[4];
-};
-
-/* Describes a AMBA PnP bus */
-struct ambapp_bus {
-	int		buses;		/* Number of buses */
-	unsigned int	ioareas[6];	/* PnP I/O AREAs of AHB buses */
-	unsigned int	freq;		/* Frequency of bus0 [Hz] */
-};
-
-/* Processor Local AMBA bus */
-extern struct ambapp_bus ambapp_plb;
-
-/* Get Bus frequency of a certain AMBA bus */
-extern unsigned int ambapp_bus_freq(
-	struct ambapp_bus *abus,
-	int ahb_bus_index
-	);
-
-/* AMBA PnP information of a APB Device */
-typedef struct {
-	unsigned int vendor;
-	unsigned int device;
-	unsigned char irq;
-	unsigned char ver;
-	unsigned int address;
-	unsigned int mask;
-	int ahb_bus_index;
-} ambapp_apbdev;
-
-/* AMBA PnP information of a AHB Device */
-typedef struct {
-	unsigned int vendor;
-	unsigned int device;
-	unsigned char irq;
-	unsigned char ver;
-	unsigned int userdef[3];
-	unsigned int address[4];
-	unsigned int mask[4];
-	int type[4];
-	int ahb_bus_index;
-} ambapp_ahbdev;
-
-/* Scan AMBA Bus for AHB Bridges */
-extern void ambapp_bus_init(
-	unsigned int ioarea,
-	unsigned int freq,
-	struct ambapp_bus *abus);
-
-/* Find APB Slave device by index using breath first search.
- *
- * When vendor and device are both set to zero, any device
- * with a non-zero device ID will match the search. It may be
- * useful when processing all devices on a AMBA bus.
- */
-extern int ambapp_apb_find(
-	struct ambapp_bus *abus,
-	int vendor,
-	int device,
-	int index,
-	ambapp_apbdev *dev
-	);
-
-/* Find AHB Master device by index using breath first search.
- *
- * When vendor and device are both set to zero, any device
- * with a non-zero device ID will match the search. It may be
- * useful when processing all devices on a AMBA bus.
- */
-extern int ambapp_ahbmst_find(
-	struct ambapp_bus *abus,
-	int vendor,
-	int device,
-	int index,
-	ambapp_ahbdev *dev
-	);
-
-/* Find AHB Slave device by index using breath first search.
- *
- * When vendor and device are both set to zero, any device
- * with a non-zero device ID will match the search. It may be
- * useful when processing all devices on a AMBA bus.
- */
-extern int ambapp_ahbslv_find(
-	struct ambapp_bus *abus,
-	int vendor,
-	int device,
-	int index,
-	ambapp_ahbdev *dev
-	);
-
-/* Return number of APB Slave devices of a certain ID (VENDOR:DEVICE)
- * zero is returned if no devices was found.
- */
-extern int ambapp_apb_count(struct ambapp_bus *abus, int vendor, int device);
-
-/* Return number of AHB Master devices of a certain ID (VENDOR:DEVICE)
- * zero is returned if no devices was found.
- */
-extern int ambapp_ahbmst_count(struct ambapp_bus *abus, int vendor, int device);
-
-/* Return number of AHB Slave devices of a certain ID (VENDOR:DEVICE)
- * zero is returned if no devices was found.
- */
-extern int ambapp_ahbslv_count(struct ambapp_bus *abus, int vendor, int device);
-
-#ifdef CONFIG_CMD_AMBAPP
-
-/* AMBA Plug&Play relocation & initialization */
-int ambapp_init_reloc(void);
-
-/* AMBA Plug&Play Name of Vendors and devices */
-
-/* Return name of device */
-char *ambapp_device_id2str(int vendor, int id);
-
-/* Return name of vendor */
-char *ambapp_vendor_id2str(int vendor);
-
-/* Return description of a device */
-char *ambapp_device_id2desc(int vendor, int id);
-
-#endif
-
-#endif /* defined(__ASSEMBLER__) */
-
-#define AMBA_DEFAULT_IOAREA 0xfff00000
-#define AMBA_CONF_AREA 0xff000
-#define AMBA_AHB_SLAVE_CONF_AREA 0x800
-
-#define DEV_NONE	0
-#define DEV_AHB_MST	1
-#define DEV_AHB_SLV	2
-#define DEV_APB_SLV	3
-
-#define AMBA_TYPE_APBIO 0x1
-#define AMBA_TYPE_MEM 0x2
-#define AMBA_TYPE_AHBIO 0x3
-
-/* ID layout for APB and AHB devices */
-#define AMBA_PNP_ID(vendor, device) (((vendor)<<24) | ((device)<<12))
-
-/* APB Slave PnP layout definitions */
-#define AMBA_APB_ID_OFS		(0*4)
-#define AMBA_APB_IOBAR_OFS	(1*4)
-#define AMBA_APB_CONF_LENGH	(2*4)
-
-/* AHB Master/Slave layout PnP definitions */
-#define AMBA_AHB_ID_OFS		(0*4)
-#define AMBA_AHB_CUSTOM0_OFS	(1*4)
-#define AMBA_AHB_CUSTOM1_OFS	(2*4)
-#define AMBA_AHB_CUSTOM2_OFS	(3*4)
-#define AMBA_AHB_MBAR0_OFS	(4*4)
-#define AMBA_AHB_MBAR1_OFS	(5*4)
-#define AMBA_AHB_MBAR2_OFS	(6*4)
-#define AMBA_AHB_MBAR3_OFS	(7*4)
-#define AMBA_AHB_CONF_LENGH	(8*4)
-
-/* Macros for extracting information from AMBA PnP information
- * registers.
- */
-
-#define amba_vendor(x) (((x) >> 24) & 0xff)
-
-#define amba_device(x) (((x) >> 12) & 0xfff)
-
-#define amba_irq(conf) ((conf) & 0x1f)
-
-#define amba_ver(conf) (((conf)>>5) & 0x1f)
-
-#define amba_iobar_start(base, iobar) \
-	((base) | ((((iobar) & 0xfff00000)>>12) & (((iobar) & 0xfff0)<<4)))
-
-#define amba_membar_start(mbar) \
-	(((mbar) & 0xfff00000) & (((mbar) & 0xfff0) << 16))
-
-#define amba_membar_type(mbar) ((mbar) & 0xf)
-
-#define amba_membar_mask(mbar) (((mbar) >> 4) & 0xfff)
-
-#define amba_ahbio_adr(addr, base_ioarea) \
-	((unsigned int)(base_ioarea) | ((addr) >> 12))
-
-#define amba_apb_mask(iobar) ((~(amba_membar_mask(iobar)<<8) & 0x000fffff) + 1)
-
-#endif
diff --git a/include/ambapp_ids.h b/include/ambapp_ids.h
deleted file mode 100644
index 1eae34e..0000000
--- a/include/ambapp_ids.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/* AMBA Plug & Play Bus Vendor and Device IDs.
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#ifndef __AMBAPP_IDS_H__
-#define __AMBAPP_IDS_H__
-
-/* Vendor ID defines */
-#define VENDOR_GAISLER       0x01
-#define VENDOR_PENDER        0x02
-#define VENDOR_ESA           0x04
-#define VENDOR_ASTRIUM       0x06
-#define VENDOR_OPENCHIP      0x07
-#define VENDOR_OPENCORES     0x08
-#define VENDOR_CONTRIB       0x09
-#define VENDOR_EONIC         0x0b
-#define VENDOR_RADIONOR      0x0f
-#define VENDOR_GLEICHMANN    0x10
-#define VENDOR_MENTA         0x11
-#define VENDOR_SUN           0x13
-#define VENDOR_MOVIDIA       0x14
-#define VENDOR_ORBITA        0x17
-#define VENDOR_SYNOPSYS      0x21
-#define VENDOR_NASA          0x22
-#define VENDOR_S3            0x31
-#define VENDOR_CAL           0xca
-#define VENDOR_EMBEDDIT      0xea
-#define VENDOR_CETON         0xcb
-#define VENDOR_ACTEL         0xac
-#define VENDOR_APPLECORE     0xae
-
-/* Aeroflex Gaisler device ID defines */
-#define GAISLER_LEON2DSU     0x002
-#define GAISLER_LEON3        0x003
-#define GAISLER_LEON3DSU     0x004
-#define GAISLER_ETHAHB       0x005
-#define GAISLER_APBMST       0x006
-#define GAISLER_AHBUART      0x007
-#define GAISLER_SRCTRL       0x008
-#define GAISLER_SDCTRL       0x009
-#define GAISLER_SSRCTRL      0x00a
-#define GAISLER_APBUART      0x00c
-#define GAISLER_IRQMP        0x00d
-#define GAISLER_AHBRAM       0x00e
-#define GAISLER_AHBDPRAM     0x00f
-#define GAISLER_GPTIMER      0x011
-#define GAISLER_PCITRG       0x012
-#define GAISLER_PCISBRG      0x013
-#define GAISLER_PCIFBRG      0x014
-#define GAISLER_PCITRACE     0x015
-#define GAISLER_DMACTRL      0x016
-#define GAISLER_AHBTRACE     0x017
-#define GAISLER_DSUCTRL      0x018
-#define GAISLER_CANAHB       0x019
-#define GAISLER_GPIO         0x01a
-#define GAISLER_AHBROM       0x01b
-#define GAISLER_AHBJTAG      0x01c
-#define GAISLER_ETHMAC       0x01d
-#define GAISLER_SWNODE       0x01e
-#define GAISLER_SPW          0x01f
-#define GAISLER_AHB2AHB      0x020
-#define GAISLER_USBDC        0x021
-#define GAISLER_USB_DCL      0x022
-#define GAISLER_DDRMP        0x023
-#define GAISLER_ATACTRL      0x024
-#define GAISLER_DDRSP        0x025
-#define GAISLER_EHCI         0x026
-#define GAISLER_UHCI         0x027
-#define GAISLER_I2CMST       0x028
-#define GAISLER_SPW2         0x029
-#define GAISLER_AHBDMA       0x02a
-#define GAISLER_NUHOSP3      0x02b
-#define GAISLER_CLKGATE      0x02c
-#define GAISLER_SPICTRL      0x02d
-#define GAISLER_DDR2SP       0x02e
-#define GAISLER_SLINK        0x02f
-#define GAISLER_GRTM         0x030
-#define GAISLER_GRTC         0x031
-#define GAISLER_GRPW         0x032
-#define GAISLER_GRCTM        0x033
-#define GAISLER_GRHCAN       0x034
-#define GAISLER_GRFIFO       0x035
-#define GAISLER_GRADCDAC     0x036
-#define GAISLER_GRPULSE      0x037
-#define GAISLER_GRTIMER      0x038
-#define GAISLER_AHB2PP       0x039
-#define GAISLER_GRVERSION    0x03a
-#define GAISLER_APB2PW       0x03b
-#define GAISLER_PW2APB       0x03c
-#define GAISLER_GRCAN        0x03d
-#define GAISLER_I2CSLV       0x03e
-#define GAISLER_U16550       0x03f
-#define GAISLER_AHBMST_EM    0x040
-#define GAISLER_AHBSLV_EM    0x041
-#define GAISLER_GRTESTMOD    0x042
-#define GAISLER_ASCS         0x043
-#define GAISLER_IPMVBCTRL    0x044
-#define GAISLER_SPIMCTRL     0x045
-#define GAISLER_L4STAT       0x047
-#define GAISLER_LEON4        0x048
-#define GAISLER_LEON4DSU     0x049
-#define GAISLER_PWM          0x04a
-#define GAISLER_L2CACHE      0x04b
-#define GAISLER_SDCTRL64     0x04c
-#define GAISLER_GR1553B      0x04d
-#define GAISLER_1553TST      0x04e
-#define GAISLER_GRIOMMU      0x04f
-#define GAISLER_FTAHBRAM     0x050
-#define GAISLER_FTSRCTRL     0x051
-#define GAISLER_AHBSTAT      0x052
-#define GAISLER_LEON3FT      0x053
-#define GAISLER_FTMCTRL      0x054
-#define GAISLER_FTSDCTRL     0x055
-#define GAISLER_FTSRCTRL8    0x056
-#define GAISLER_MEMSCRUB     0x057
-#define GAISLER_FTSDCTRL64   0x058
-#define GAISLER_APBPS2       0x060
-#define GAISLER_VGACTRL      0x061
-#define GAISLER_LOGAN        0x062
-#define GAISLER_SVGACTRL     0x063
-#define GAISLER_T1AHB        0x064
-#define GAISLER_MP7WRAP      0x065
-#define GAISLER_GRSYSMON     0x066
-#define GAISLER_GRACECTRL    0x067
-#define GAISLER_ATAHBSLV     0x068
-#define GAISLER_ATAHBMST     0x069
-#define GAISLER_ATAPBSLV     0x06a
-#define GAISLER_B1553BC      0x070
-#define GAISLER_B1553RT      0x071
-#define GAISLER_B1553BRM     0x072
-#define GAISLER_AES          0x073
-#define GAISLER_ECC          0x074
-#define GAISLER_PCIF         0x075
-#define GAISLER_CLKMOD       0x076
-#define GAISLER_HAPSTRAK     0x077
-#define GAISLER_TEST_1X2     0x078
-#define GAISLER_WILD2AHB     0x079
-#define GAISLER_BIO1         0x07a
-#define GAISLER_AESDMA       0x07b
-#define GAISLER_SATCAN       0x080
-#define GAISLER_CANMUX       0x081
-#define GAISLER_GRTMRX       0x082
-#define GAISLER_GRTCTX       0x083
-#define GAISLER_GRTMDESC     0x084
-#define GAISLER_GRTMVC       0x085
-#define GAISLER_GEFFE        0x086
-#define GAISLER_GPREG        0x087
-#define GAISLER_GRTMPAHB     0x088
-#define GAISLER_SPWCUC       0x089
-#define GAISLER_SPW2_DMA     0x08a
-#define GAISLER_SPWROUTER    0x08b
-
-/* European Space Agency device ID defines */
-#define ESA_LEON2            0x002
-#define ESA_LEON2APB         0x003
-#define ESA_IRQ              0x005
-#define ESA_TIMER            0x006
-#define ESA_UART             0x007
-#define ESA_CFG              0x008
-#define ESA_IO               0x009
-#define ESA_MCTRL            0x00f
-#define ESA_PCIARB           0x010
-#define ESA_HURRICANE        0x011
-#define ESA_SPW_RMAP         0x012
-#define ESA_AHBUART          0x013
-#define ESA_SPWA             0x014
-#define ESA_BOSCHCAN         0x015
-#define ESA_IRQ2             0x016
-#define ESA_AHBSTAT          0x017
-#define ESA_WPROT            0x018
-#define ESA_WPROT2           0x019
-#define ESA_PDEC3AMBA        0x020
-#define ESA_PTME3AMBA        0x021
-
-/* OpenChip device ID defines */
-#define OPENCHIP_APBGPIO     0x001
-#define OPENCHIP_APBI2C      0x002
-#define OPENCHIP_APBSPI      0x003
-#define OPENCHIP_APBCHARLCD  0x004
-#define OPENCHIP_APBPWM      0x005
-#define OPENCHIP_APBPS2      0x006
-#define OPENCHIP_APBMMCSD    0x007
-#define OPENCHIP_APBNAND     0x008
-#define OPENCHIP_APBLPC      0x009
-#define OPENCHIP_APBCF       0x00a
-#define OPENCHIP_APBSYSACE   0x00b
-#define OPENCHIP_APB1WIRE    0x00c
-#define OPENCHIP_APBJTAG     0x00d
-#define OPENCHIP_APBSUI      0x00e
-
-/* Various contributions device ID defines */
-#define CONTRIB_CORE1        0x001
-#define CONTRIB_CORE2        0x002
-
-/* Gleichmann Electronics device ID defines */
-#define GLEICHMANN_CUSTOM    0x001
-#define GLEICHMANN_GEOLCD01  0x002
-#define GLEICHMANN_DAC       0x003
-#define GLEICHMANN_HPI       0x004
-#define GLEICHMANN_SPI       0x005
-#define GLEICHMANN_HIFC      0x006
-#define GLEICHMANN_ADCDAC    0x007
-#define GLEICHMANN_SPIOC     0x008
-#define GLEICHMANN_AC97      0x009
-
-/* Sun Microsystems device ID defines */
-#define SUN_T1               0x001
-#define SUN_S1               0x011
-
-/* Orbita device ID defines */
-#define ORBITA_1553B         0x001
-#define ORBITA_429           0x002
-#define ORBITA_SPI           0x003
-#define ORBITA_I2C           0x004
-#define ORBITA_SMARTCARD     0x064
-#define ORBITA_SDCARD        0x065
-#define ORBITA_UART16550     0x066
-#define ORBITA_CRYPTO        0x067
-#define ORBITA_SYSIF         0x068
-#define ORBITA_PIO           0x069
-#define ORBITA_RTC           0x0c8
-#define ORBITA_COLORLCD      0x12c
-#define ORBITA_PCI           0x190
-#define ORBITA_DSP           0x1f4
-#define ORBITA_USBHOST       0x258
-#define ORBITA_USBDEV        0x2bc
-
-/* NASA device ID defines */
-#define NASA_EP32            0x001
-
-/* CAL device ID defines */
-#define CAL_DDRCTRL          0x188
-
-/* Actel Corporation device ID defines */
-#define ACTEL_COREMP7        0x001
-
-/* AppleCore device ID defines */
-#define APPLECORE_UTLEON3    0x001
-#define APPLECORE_UTLEON3DSU 0x002
-
-/* Opencores device id's */
-#define OPENCORES_PCIBR  0x4
-#define OPENCORES_ETHMAC 0x5
-
-#endif
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 5b356dd..1a77c98 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -110,6 +110,12 @@ typedef struct global_data {
 } gd_t;
 #endif
 
+#ifdef CONFIG_BOARD_TYPES
+#define gd_board_type()		gd->board_type
+#else
+#define gd_board_type()		0
+#endif
+
 /*
  * Global Data Flags - the top 16 bits are reserved for arch-specific flags
  */
diff --git a/include/common.h b/include/common.h
index fbbc2cb..83e4037 100644
--- a/include/common.h
+++ b/include/common.h
@@ -76,9 +76,6 @@ typedef volatile unsigned char	vu_char;
 #ifdef	CONFIG_4xx
 #include <asm/ppc4xx.h>
 #endif
-#ifdef CONFIG_BLACKFIN
-#include <asm/blackfin.h>
-#endif
 #ifdef CONFIG_SOC_DA8XX
 #include <asm/arch/hardware.h>
 #endif
@@ -206,14 +203,28 @@ typedef void (interrupt_handler_t)(void *);
  */
 int dram_init(void);
 
+/**
+ * dram_init_banksize() - Set up DRAM bank sizes
+ *
+ * This can be implemented by boards to set up the DRAM bank information in
+ * gd->bd->bi_dram(). It is called just before relocation, after dram_init()
+ * is called.
+ *
+ * If this is not provided, a default implementation will try to set up a
+ * single bank. It will do this if CONFIG_NR_DRAM_BANKS and
+ * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of
+ * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to
+ * get_effective_memsize().
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dram_init_banksize(void);
+
 void	hang		(void) __attribute__ ((noreturn));
 
 int	timer_init(void);
 int	cpu_init(void);
 
-/* */
-phys_size_t initdram (int);
-
 #include <display_options.h>
 
 /* common/main.c */
@@ -288,6 +299,22 @@ int print_cpuinfo(void);
 int update_flash_size(int flash_size);
 int arch_early_init_r(void);
 
+/*
+ * setup_board_extra() - Fill in extra details in the bd_t structure
+ *
+ * @return 0 if OK, -ve on error
+ */
+int setup_board_extra(void);
+
+/**
+ * arch_fsp_init() - perform firmware support package init
+ *
+ * Where U-Boot relies on binary blobs to handle part of the system init, this
+ * function can be used to set up the blobs. This is used on some Intel
+ * platforms.
+ */
+int arch_fsp_init(void);
+
 /**
  * arch_cpu_init_dm() - init CPU after driver model is available
  *
@@ -497,6 +524,7 @@ extern ssize_t spi_write (uchar *, int, uchar *, int);
 
 /* $(BOARD)/$(BOARD).c */
 int board_early_init_f (void);
+int board_fix_fdt (void *rw_fdt_blob); /* manipulate the U-Boot fdt before its relocation */
 int board_late_init (void);
 int board_postclk_init (void); /* after clocks/timebase, before env/serial */
 int board_early_init_r (void);
@@ -630,12 +658,7 @@ int serial_stub_tstc(struct stdio_dev *sdev);
 
 /* $(CPU)/speed.c */
 int	get_clocks (void);
-int	get_clocks_866 (void);
-int	sdram_adjust_866 (void);
-int	adjust_sdram_tbs_8xx (void);
-#if defined(CONFIG_MPC8260)
-int	prt_8260_clks (void);
-#elif defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_MPC5xxx)
 int	prt_mpc5xxx_clks (void);
 #endif
 #ifdef CONFIG_4xx
@@ -706,11 +729,6 @@ ulong cpu_init_f(void);
 #endif
 
 int	cpu_init_r    (void);
-#if defined(CONFIG_MPC8260)
-int	prt_8260_rsr  (void);
-#elif defined(CONFIG_MPC83xx)
-int	prt_83xx_rsr  (void);
-#endif
 
 /* $(CPU)/interrupts.c */
 int	interrupt_init	   (void);
@@ -776,7 +794,6 @@ void	wait_ticks    (unsigned long);
 /* arch/$(ARCH)/lib/time.c */
 ulong	usec2ticks    (unsigned long usec);
 ulong	ticks2usec    (unsigned long ticks);
-int	init_timebase (void);
 
 /* lib/gunzip.c */
 int gunzip(void *, int, unsigned char *, unsigned long *);
diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h
index 53a45b2..30dd9e5 100644
--- a/include/configs/advantech_dms-ba16.h
+++ b/include/configs/advantech_dms-ba16.h
@@ -230,7 +230,6 @@
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
 
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE               (128 * 1024)
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS           1
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 2712687..fc8a08f 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -17,7 +17,6 @@
 #define __CONFIG_AM335X_EVM_H
 
 #include <configs/ti_am335x_common.h>
-#include <environment/ti/dfu.h>
 
 #ifndef CONFIG_SPL_BUILD
 # define CONFIG_TIMESTAMP
@@ -96,6 +95,9 @@
 #include <config_distro_bootcmd.h>
 
 #ifndef CONFIG_SPL_BUILD
+#include <environment/ti/dfu.h>
+#include <environment/ti/mmc.h>
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
 	DEFAULT_MMC_TI_ARGS \
@@ -138,8 +140,14 @@
 			"setenv fdtfile am335x-bone.dtb; fi; " \
 		"if test $board_name = A335BNLT; then " \
 			"setenv fdtfile am335x-boneblack.dtb; fi; " \
+		"if test $board_name = BBBW; then " \
+			"setenv fdtfile am335x-boneblack-wireless.dtb; fi; " \
 		"if test $board_name = BBG1; then " \
 			"setenv fdtfile am335x-bonegreen.dtb; fi; " \
+		"if test $board_name = BBGW; then " \
+			"setenv fdtfile am335x-bonegreen-wireless.dtb; fi; " \
+		"if test $board_name = BBBL; then " \
+			"setenv fdtfile am335x-boneblue.dtb; fi; " \
 		"if test $board_name = A33515BB; then " \
 			"setenv fdtfile am335x-evm.dtb; fi; " \
 		"if test $board_name = A335X_SK; then " \
diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h
index 2b61405..7ee8ea7 100644
--- a/include/configs/am335x_igep0033.h
+++ b/include/configs/am335x_igep0033.h
@@ -117,9 +117,6 @@
 					"1m(uboot),256k(environment),"\
 					"-(filesystem)"
 
-/* Unsupported features */
-#undef CONFIG_USE_IRQ
-
 /* SPL */
 #define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
 
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 1d622ef..1feb946 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -13,14 +13,13 @@
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 21)	/* 2GB */
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 
-#include <environment/ti/dfu.h>
 #include <asm/arch/omap.h>
 
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550_CLK		48000000
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
+#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_REG_SIZE    (-4)
 #define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
 #endif
 
 /* I2C Configuration */
@@ -111,9 +110,6 @@
  * DM support in SPL
  */
 #ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_MMC
-#undef CONFIG_DM_SPI
-#undef CONFIG_DM_SPI_FLASH
 #undef CONFIG_TIMER
 #endif
 
@@ -165,6 +161,9 @@
 #define CONFIG_TI_EDMA3
 
 #ifndef CONFIG_SPL_BUILD
+#include <environment/ti/dfu.h>
+#include <environment/ti/mmc.h>
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
 	DEFAULT_MMC_TI_ARGS \
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index d545e1b..dc7a370 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -102,10 +102,6 @@
 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 						CONFIG_SYS_SCSI_MAX_LUN)
 
-/* EEPROM */
-#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
-#define CONFIG_EEPROM_BUS_ADDRESS 0
-
 /*
  * Default to using SPI for environment, etc.
  * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
@@ -120,11 +116,6 @@
 #define CONFIG_SYS_SPI_ARGS_OFFS        0x140000
 #define CONFIG_SYS_SPI_ARGS_SIZE        0x80000
 
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_SPI
-#undef CONFIG_DM_SPI_FLASH
-#endif
-
 /* SPI SPL */
 #define CONFIG_TI_EDMA3
 #define CONFIG_SPL_SPI_LOAD
diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
new file mode 100644
index 0000000..84652de
--- /dev/null
+++ b/include/configs/apalis-tk1.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2017 Toradex, Inc.
+ *
+ * Configuration settings for the Toradex Apalis TK1 modules.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+/* enable PMIC */
+#define CONFIG_AS3722_POWER
+
+#include "tegra124-common.h"
+
+#define CONFIG_ARCH_MISC_INIT
+
+/* High-level configuration options */
+#define CONFIG_DISPLAY_BOARDINFO_LATE	/* Calls show_board_info() */
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+
+/* SD/MMC support */
+#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
+
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
+					 CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		1
+
+/* USB host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+
+/* PCI host support */
+#undef CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+/* PCI networking support */
+#define CONFIG_E1000_NO_NVM
+
+/* General networking support */
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE		16352
+#define CONFIG_TFTP_TSIZE
+
+/* Miscellaneous commands */
+#define CONFIG_FAT_WRITE
+
+#undef CONFIG_IPADDR
+#define CONFIG_IPADDR		192.168.10.2
+#define CONFIG_NETMASK		255.255.255.0
+#undef CONFIG_SERVERIP
+#define CONFIG_SERVERIP		192.168.10.1
+
+#define CONFIG_BOOTCOMMAND \
+	"run emmcboot; setenv fdtfile ${soc}-apalis-${fdt_board}.dtb && " \
+		"run distro_bootcmd"
+
+#define DFU_ALT_EMMC_INFO	"apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \
+				"boot part 0 1 mmcpart 0; " \
+				"rootfs part 0 2 mmcpart 0; " \
+				"uImage fat 0 1 mmcpart 0; " \
+				"tegra124-apalis-eval.dtb fat 0 1 mmcpart 0"
+
+#define EMMC_BOOTCMD \
+	"emmcargs=ip=off root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait\0" \
+	"emmcboot=run setup; setenv bootargs ${defargs} ${emmcargs} " \
+		"${setupargs} ${vidargs}; echo Booting from internal eMMC " \
+		"chip...; run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
+		"${boot_file} && run fdt_fixup && " \
+		"bootm ${kernel_addr_r} - ${dtbparam}\0" \
+	"emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
+		"${soc}-apalis-${fdt_board}.dtb && " \
+		"setenv dtbparam ${fdt_addr_r}\0"
+
+#define NFS_BOOTCMD \
+	"nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
+	"nfsboot=pci enum; run setup; setenv bootargs ${defargs} ${nfsargs} " \
+		"${setupargs} ${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
+		"run nfsdtbload; dhcp ${kernel_addr_r} " \
+		"&& run fdt_fixup && bootm ${kernel_addr_r} - ${dtbparam}\0" \
+	"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} " \
+		"${soc}-apalis-${fdt_board}.dtb " \
+		"&& setenv dtbparam ${fdt_addr_r}\0"
+
+#define SD_BOOTCMD \
+	"sdargs=ip=off root=/dev/mmcblk1p2 rw rootfstype=ext3 rootwait\0" \
+	"sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
+		"${vidargs}; echo Booting from SD card in 8bit slot...; " \
+		"run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
+		"${boot_file} && run fdt_fixup && " \
+		"bootm ${kernel_addr_r} - ${dtbparam}\0" \
+	"sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
+		"${soc}-apalis-${fdt_board}.dtb " \
+		"&& setenv dtbparam ${fdt_addr_r}\0"
+
+#define USB_BOOTCMD \
+	"usbargs=ip=off root=/dev/sda2 rw rootfstype=ext3 rootwait\0" \
+	"usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
+		"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
+		"usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
+		"${boot_file} && run fdt_fixup && " \
+		"bootm ${kernel_addr_r} - ${dtbparam}\0" \
+	"usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
+		"${soc}-apalis-${fdt_board}.dtb " \
+		"&& setenv dtbparam ${fdt_addr_r}\0"
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+	"boot_file=uImage\0" \
+	"console=ttyS0\0" \
+	"defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \
+		"usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0\0" \
+	"dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
+	EMMC_BOOTCMD \
+	"fdt_board=eval\0" \
+	"fdt_fixup=;\0" \
+	NFS_BOOTCMD \
+	SD_BOOTCMD \
+	"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
+		"00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \
+		"flash_eth.img && source ${loadaddr}\0" \
+	"setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \
+		"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \
+		"|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1 " \
+		"${loadaddr} flash_blk.img && " \
+		"source ${loadaddr}\0" \
+	"setup=setenv setupargs igb_mac=${ethaddr} " \
+		"consoleblank=0 no_console_suspend=1 console=tty1 " \
+		"console=${console},${baudrate}n8 debug_uartport=lsport,0 " \
+		"${memargs}\0" \
+	"setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
+	"setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
+		"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+		"source ${loadaddr}\0" \
+	USB_BOOTCMD \
+	"vidargs=video=tegrafb0:640x480-16@60 fbcon=map:1\0"
+
+/* Increase console I/O buffer size */
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE		1024
+
+/* Increase arguments buffer size */
+#undef CONFIG_SYS_BARGSIZE
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* Increase print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Increase maximum number of arguments */
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS		32
+
+#define CONFIG_CMD_TIME
+
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+/* Reserve top 1M for secure RAM */
+#define CONFIG_ARMV7_SECURE_BASE		0xfff00000
+#define CONFIG_ARMV7_SECURE_RESERVE_SIZE	0x00100000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h
index 030f01c..5c27055 100644
--- a/include/configs/aristainetos-common.h
+++ b/include/configs/aristainetos-common.h
@@ -148,8 +148,6 @@
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
 #define CONFIG_SYS_MEMTEST_SCRATCH	0x10800000
 
-#define CONFIG_STACKSIZE		(128 * 1024)
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 708f032..4c27225 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -52,8 +52,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 
-#define CONFIG_STACKSIZE		(2048)
-
 #define CONFIG_BOOTARGS							\
 	"console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2"
 #define CONFIG_BOOTCOMMAND						\
diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h
index aa30848..64d7c45 100644
--- a/include/configs/atngw100mkii.h
+++ b/include/configs/atngw100mkii.h
@@ -71,8 +71,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 
-#define CONFIG_STACKSIZE		(2048)
-
 #define CONFIG_BOOTARGS							\
 	"root=mtd:main rootfstype=jffs2"
 #define CONFIG_BOOTCOMMAND						\
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 771a35a..3c03ed3 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -69,8 +69,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 
-#define CONFIG_STACKSIZE		(2048)
-
 #define CONFIG_BOOTARGS							\
 	"console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
 
diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h
index d60db65..768e8fb 100644
--- a/include/configs/axs10x.h
+++ b/include/configs/axs10x.h
@@ -11,8 +11,6 @@
 /*
  *  CPU configuration
  */
-#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_CLK_FREQ
-
 #define ARC_FPGA_PERIPHERAL_BASE	0xE0000000
 #define ARC_APB_PERIPHERAL_BASE		0xF0000000
 #define ARC_DWMMC_BASE			(ARC_FPGA_PERIPHERAL_BASE + 0x15000)
diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h
index 65e9e32..77d6e6a 100644
--- a/include/configs/bcm23550_w1d.h
+++ b/include/configs/bcm23550_w1d.h
@@ -25,7 +25,6 @@
 #define CONFIG_NR_DRAM_BANKS		1
 
 #define CONFIG_SYS_MALLOC_LEN		SZ_4M	/* see armv7/start.S. */
-#define CONFIG_STACKSIZE		SZ_256K
 
 /* GPIO Driver */
 #define CONFIG_KONA_GPIO
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index 2d9b0a8..03f4ca0 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -24,7 +24,6 @@
 #define CONFIG_NR_DRAM_BANKS		1
 
 #define CONFIG_SYS_MALLOC_LEN		SZ_4M	/* see armv7/start.S. */
-#define CONFIG_STACKSIZE		SZ_256K
 
 /* GPIO Driver */
 #define CONFIG_KONA_GPIO
diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h
index 868b0a8..c187df2 100644
--- a/include/configs/bcm_ep_board.h
+++ b/include/configs/bcm_ep_board.h
@@ -28,7 +28,6 @@
 #define CONFIG_NR_DRAM_BANKS		1
 
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-#define CONFIG_STACKSIZE		(256 * 1024)
 
 /* Some commands use this as the default load address */
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
diff --git a/include/configs/bcm_northstar2.h b/include/configs/bcm_northstar2.h
new file mode 100644
index 0000000..ec2ce3f
--- /dev/null
+++ b/include/configs/bcm_northstar2.h
@@ -0,0 +1,55 @@
+/*
+ * Configuration for Broadcom NS2.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BCM_NORTHSTAR2_H
+#define __BCM_NORTHSTAR2_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_HOSTNAME				northstar2
+
+/* Physical Memory Map */
+#define V2M_BASE				0x80000000
+#define PHYS_SDRAM_1				V2M_BASE
+
+#define CONFIG_NR_DRAM_BANKS			2
+#define PHYS_SDRAM_1_SIZE			(4UL * SZ_1G)
+#define PHYS_SDRAM_2_SIZE			(4UL * SZ_1G)
+#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
+
+/* define text_base for U-boot image */
+#define CONFIG_SYS_TEXT_BASE			0x85000000
+#define CONFIG_SYS_INIT_SP_ADDR			(PHYS_SDRAM_1 + 0x7ff00)
+#define CONFIG_SYS_LOAD_ADDR			0x90000000
+#define CONFIG_SYS_MALLOC_LEN			SZ_16M
+
+/* Serial Configuration */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE		(-4)
+#define CONFIG_SYS_NS16550_CLK			25000000
+#define CONFIG_SYS_NS16550_COM1			0x66100000
+#define CONFIG_SYS_NS16550_COM2			0x66110000
+#define CONFIG_SYS_NS16550_COM3			0x66120000
+#define CONFIG_SYS_NS16550_COM4			0x66130000
+#define CONFIG_CONS_INDEX			4
+#define CONFIG_BAUDRATE				115200
+
+#define CONFIG_ENV_SIZE				SZ_8K
+#define CONFIG_ENV_IS_NOWHERE
+
+/* console configuration */
+#define CONFIG_SYS_CBSIZE			SZ_1K
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
+						 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS			64
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
+
+/* version string, parser, etc */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_SYS_LONGHELP
+
+#endif /* __BCM_NORTHSTAR2_H */
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
deleted file mode 100644
index b965803..0000000
--- a/include/configs/bct-brettl2.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * U-Boot - Configuration file for BF536 brettl2 board
- */
-
-#ifndef __CONFIG_BCT_BRETTL2_H__
-#define __CONFIG_BCT_BRETTL2_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf536-0.3
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			16384000
-/* CLKIN_HALF controls the DF bit in PLL_CTL	  0 = CLKIN		*/
-/*						  1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*						  1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			24
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			3
-#define CONFIG_VR_CTL_VAL	(VLEV_110 | GAIN_20 | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	9
-#define CONFIG_MEM_SIZE		32
-
-/*
- * SDRAM Settings
- */
-#define CONFIG_EBIU_SDRRC_VAL	0x07f6
-#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_BFIN_MAC		1
-#define CONFIG_NETCONSOLE	1
-#define CONFIG_HOSTNAME		brettl2
-#define CONFIG_IPADDR		192.168.233.224
-#define CONFIG_GATEWAYIP	192.168.233.1
-#define CONFIG_SERVERIP		192.168.233.53
-#define CONFIG_ROOTPATH		"/romfs/brettl2"
-#endif
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_FLASH_BASE			0x20000000
-#define CONFIG_SYS_MAX_FLASH_BANKS		1
-#define CONFIG_SYS_MAX_FLASH_SECT		135
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET	0x4000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x12000
-
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#else
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
-	arch/blackfin/lib/built-in.o (.text*); \
-	arch/blackfin/cpu/built-in.o (.text*); \
-	. = DEFINED(env_offset) ? env_offset : .; \
-	common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Misc Settings
- */
-#define CONFIG_LOADADDR		0x800000
-#define CONFIG_MISC_INIT_R
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-/* disable unnecessary features */
-#undef CONFIG_BOOTM_RTEMS
-#undef CONFIG_BZIP2
-#undef CONFIG_KALLSYMS
-
-#endif
diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h
deleted file mode 100644
index b517af3..0000000
--- a/include/configs/bf506f-ezkit.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * U-Boot - Configuration file for BF506F EZ-Kit board
- */
-
-#ifndef __CONFIG_BF506F_EZKIT_H__
-#define __CONFIG_BF506F_EZKIT_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf506-0.0
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			16
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_SIZE		0
-
-#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL	0xffc2ffc2
-#define CONFIG_EBIU_AMBCTL1_VAL	0xffc2ffc2
-
-#define CONFIG_SYS_MONITOR_BASE (L1_DATA_A_SRAM_END)
-#define CONFIG_SYS_MONITOR_LEN	(4 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(4 * 1024)
-
-/*
- * Flash Settings
- */
-/*
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	71
-#define CONFIG_MONITOR_IS_IN_RAM
-*/
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x400
-
-/*
- * Misc Settings
- */
-#define CONFIG_ICACHE_OFF
-#define CONFIG_DCACHE_OFF
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BFIN_SERIAL
-
-#undef CONFIG_GZIP
-#undef CONFIG_ZLIB
-#undef CONFIG_BOOTM_RTEMS
-#undef CONFIG_BOOTM_LINUX
-
-#endif
diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
deleted file mode 100644
index e3c2286..0000000
--- a/include/configs/bf518f-ezbrd.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * U-Boot - Configuration file for BF518F EZBrd board
- */
-
-#ifndef __CONFIG_BF518F_EZBRD_H__
-#define __CONFIG_BF518F_EZBRD_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf518-0.0
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			16
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			5
-
-/*
- * Memory Settings
- */
-/* This board has a 64meg MT48H32M16 */
-#define CONFIG_MEM_ADD_WDTH	10
-#define CONFIG_MEM_SIZE		64
-
-#define CONFIG_EBIU_SDRRC_VAL	0x0096
-#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
-
-#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
-#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
-
-#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(384 * 1024)
-
-/*
- * Network Settings
- */
-#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_BFIN_MAC
-#define CONFIG_BFIN_MAC_PINS \
-	{ \
-	P_MII0_ETxD0, \
-	P_MII0_ETxD1, \
-	P_MII0_ETxD2, \
-	P_MII0_ETxD3, \
-	P_MII0_ETxEN, \
-	P_MII0_TxCLK, \
-	P_MII0_PHYINT, \
-	P_MII0_COL, \
-	P_MII0_ERxD0, \
-	P_MII0_ERxD1, \
-	P_MII0_ERxD2, \
-	P_MII0_ERxD3, \
-	P_MII0_ERxDV, \
-	P_MII0_ERxCLK, \
-	P_MII0_CRS, \
-	P_MII0_MDC, \
-	P_MII0_MDIO, \
-	0 }
-#define CONFIG_NETCONSOLE	1
-#endif
-#define CONFIG_HOSTNAME		bf518f-ezbrd
-#define CONFIG_PHY_ADDR		3
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	71
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x10000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET	0x4000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#endif
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * SDH Settings
- */
-#if !defined(__ADSPBF512__)
-#define CONFIG_BFIN_SDH
-#endif
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	0
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h
deleted file mode 100644
index 1c1a08f..0000000
--- a/include/configs/bf525-ucr2.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * U-Boot - Configuration file for bf525-ucr2 board
- * The board includes ADSP-BF525 rev. 0.2,
- * 32-bit SDRAM (SAMSUNG K4S561632H-UC75),
- * USB 2.0 High Speed OTG USB WIFI,
- * SPI flash (cFeon EN25Q128 16 MB),
- * Support PPI and ITU-R656,
- * See http://www.ucrobotics.com/?q=cn/ucr2
- */
-
-#ifndef __CONFIG_BF525_UCR2_H__
-#define __CONFIG_BF525_UCR2_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf525-0.2
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			24000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			20
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			4
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	9
-#define CONFIG_MEM_SIZE		32
-
-/*
- * SDRAM reference page
- * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
- */
-#define CONFIG_EBIU_SDRRC_VAL   0x3f8
-#define CONFIG_EBIU_SDGCTL_VAL  0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL  (AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN	(320 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(320 * 1024)
-
-/* support for serial flash */
-#define CONFIG_BFIN_SPI
-#define CONFIG_SF_DEFAULT_HZ	30000000
-
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_ENV_OFFSET	0x10000
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Misc Settings
- */
-#define CONFIG_UART_CONSOLE	0
-
-#define CONFIG_BFIN_SERIAL
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw"
-#define CONFIG_BOOTCOMMAND	"run sfboot"
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"sfboot=sf probe 1;" \
-		"sf read 0x1000000 0x20000 0x300000;" \
-		"bootm 0x1000000\0"
-
-#endif
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
deleted file mode 100644
index 7d75e73..0000000
--- a/include/configs/bf526-ezbrd.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * U-Boot - Configuration file for BF526 EZBrd board
- */
-
-#ifndef __CONFIG_BF526_EZBRD_H__
-#define __CONFIG_BF526_EZBRD_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf526-0.0
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			16
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			5
-
-/*
- * Memory Settings
- */
-/* This board has a 64meg MT48H32M16 */
-#define CONFIG_MEM_ADD_WDTH	10
-#define CONFIG_MEM_SIZE		64
-
-#define CONFIG_EBIU_SDRRC_VAL	0x0267
-#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | CL_2 | PASR_ALL | TRAS_6 | TRP_4 | TRCD_2 | TWR_2 | PSS)
-
-#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
-#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
-
-#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)
-
-/*
- * NAND Settings
- * (can't be used same time as ethernet)
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-# define CONFIG_BFIN_NFC
-# define CONFIG_BFIN_NFC_BOOTROM_ECC
-#endif
-#ifdef CONFIG_BFIN_NFC
-#define CONFIG_BFIN_NFC_CTL_VAL	0x0033
-#define CONFIG_DRIVER_NAND_BFIN
-#define CONFIG_SYS_NAND_BASE		0 /* not actually used */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_CMD_NAND
-#endif
-
-/*
- * Network Settings
- */
-#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
-    !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_BFIN_MAC
-#define CONFIG_RMII
-#define CONFIG_NETCONSOLE	1
-#endif
-#define CONFIG_HOSTNAME		bf526-ezbrd
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	71
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x4000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET	0x4000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#endif
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * USB Settings
- */
-#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
-#define CONFIG_USB_MUSB_HCD
-#define CONFIG_USB_BLACKFIN
-#define CONFIG_USB_MUSB_TIMEOUT 100000
-#endif
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	1
-
-/* define to enable run status via led */
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h
deleted file mode 100644
index e433aaa..0000000
--- a/include/configs/bf527-ad7160-eval.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * U-Boot - Configuration file for BF527 AD7160-EVAL board
- */
-
-#ifndef __CONFIG_BF527_AD7160_EVAL_H__
-#define __CONFIG_BF527_AD7160_EVAL_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf527-0.2
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			24000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			25
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	10
-#define CONFIG_MEM_SIZE		64
-
-#define CONFIG_EBIU_SDRRC_VAL	0x03F6
-#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
-
-#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
-#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
-
-#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
-
-/*
- * NAND Settings
- * (can't be used same time as ethernet)
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-# define CONFIG_BFIN_NFC
-# define CONFIG_BFIN_NFC_BOOTROM_ECC
-#endif
-#ifdef CONFIG_BFIN_NFC
-#define CONFIG_BFIN_NFC_CTL_VAL	0x0033
-#define CONFIG_DRIVER_NAND_BFIN
-#define CONFIG_SYS_NAND_BASE		0 /* not actually used */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#endif
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	259
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x10000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET	0x40000
-#define CONFIG_ENV_SIZE		0x20000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET	0x4000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * SPI_MMC Settings
- */
-#define CONFIG_MMC_SPI
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_UART_CONSOLE	0
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
deleted file mode 100644
index d945b8d..0000000
--- a/include/configs/bf527-ezkit.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * U-Boot - Configuration file for BF537 STAMP board
- */
-
-#ifndef __CONFIG_BF527_EZKIT_H__
-#define __CONFIG_BF527_EZKIT_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf527-0.0
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			21
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			4
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	10
-#define CONFIG_MEM_SIZE		64
-
-#define CONFIG_EBIU_SDRRC_VAL	0x03F6
-#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
-
-#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
-#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
-
-#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
-
-/*
- * NAND Settings
- * (can't be used same time as ethernet)
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-# define CONFIG_BFIN_NFC
-# define CONFIG_BFIN_NFC_BOOTROM_ECC
-#endif
-#ifdef CONFIG_BFIN_NFC
-#define CONFIG_BFIN_NFC_CTL_VAL	0x0033
-#define CONFIG_DRIVER_NAND_BFIN
-#define CONFIG_SYS_NAND_BASE		0 /* not actually used */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#endif
-
-/*
- * Network Settings
- */
-#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
-    !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_BFIN_MAC
-#define CONFIG_RMII
-#define CONFIG_NETCONSOLE	1
-#endif
-#define CONFIG_HOSTNAME		bf527-ezkit
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	259
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x10000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET	0x40000
-#define CONFIG_ENV_SIZE		0x20000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET	0x4000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * USB Settings
- */
-#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
-#define CONFIG_USB_MUSB_HCD
-#define CONFIG_USB_BLACKFIN
-#define CONFIG_USB_MUSB_TIMEOUT 100000
-#endif
-
-/* Don't waste time transferring a logo over the UART */
-
-/*
- * Video Settings
- */
-#ifdef CONFIG_VIDEO
-#ifdef CONFIG_BF527_EZKIT_REV_2_1
-# define CONFIG_LQ035Q1_SPI_BUS	0
-# define CONFIG_LQ035Q1_SPI_CS	7
-# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
-#else
-# define CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
-#endif
-
-#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
-# define EASYLOGO_HEADER <asm/bfin_logo_rgb565_230x230_lzma.h>
-#else
-# define EASYLOGO_HEADER <asm/bfin_logo_230x230_lzma.h>
-#endif
-#endif /* CONFIG_VIDEO */
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	1
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h
deleted file mode 100644
index 6b7d19e..0000000
--- a/include/configs/bf527-sdp.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * U-Boot - Configuration file for BF527 SDP board
- */
-
-#ifndef __CONFIG_BF527_SDP_H__
-#define __CONFIG_BF527_SDP_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf527-0.2
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			24000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			25
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			5
-
-#define CONFIG_PLL_LOCKCNT_VAL	0x0200
-#define CONFIG_PLL_CTL_VAL		0x2a00
-#define CONFIG_VR_CTL_VAL		0x7090
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	9
-#define CONFIG_MEM_SIZE		32
-
-#define CONFIG_EBIU_SDRRC_VAL	0x00FE
-#define CONFIG_EBIU_SDGCTL_VAL	0x8011998d
-
-#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
-#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
-
-#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	259
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-#define CONFIG_SPI_FLASH_ALL
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x10000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET	0x4000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_UART_CONSOLE	0
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
deleted file mode 100644
index e154812..0000000
--- a/include/configs/bf533-ezkit.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * U-Boot - Configuration file for BF533 EZKIT board
- */
-
-#ifndef __CONFIG_BF533_EZKIT_H__
-#define __CONFIG_BF533_EZKIT_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf533-0.3
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			27000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			22
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_SIZE		32
-/* Early EZKITs had 32megs, but later have 64megs */
-#if (CONFIG_MEM_SIZE == 64)
-# define CONFIG_MEM_ADD_WDTH	10
-#else
-# define CONFIG_MEM_ADD_WDTH	9
-#endif
-
-#define CONFIG_EBIU_SDRRC_VAL	0x398
-#define CONFIG_EBIU_SDGCTL_VAL	0x91118d
-
-#define CONFIG_EBIU_AMGCTL_VAL	0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_SMC91111	1
-#define CONFIG_SMC91111_BASE	0x20310300
-#define SMC91111_EEPROM_INIT() \
-	do { \
-		bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
-		bfin_write_FIO_FLAG_C(PF1); \
-		bfin_write_FIO_FLAG_S(PF0); \
-		SSYNC(); \
-	} while (0)
-#define CONFIG_HOSTNAME		bf533-ezkit
-
-/*
- * Flash Settings
- */
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	3
-#define CONFIG_SYS_MAX_FLASH_SECT	40
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR		0x20030000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define FLASH_TOT_SECT		40
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C_SOFT
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C
-#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
-#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
-#define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0
-#define I2C_DELAY              udelay(5)       /* 1/4 I2C clock duration */
-#endif
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	0
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
deleted file mode 100644
index 516fe2d..0000000
--- a/include/configs/bf533-stamp.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * U-Boot - Configuration file for BF533 STAMP board
- */
-
-#ifndef __CONFIG_BF533_STAMP_H__
-#define __CONFIG_BF533_STAMP_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf533-0.3
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			11059200
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			45
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			6 /* note: 1.2 boards can go faster */
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	11
-#define CONFIG_MEM_SIZE		128
-
-#define CONFIG_EBIU_SDRRC_VAL	0x268
-#define CONFIG_EBIU_SDGCTL_VAL	0x911109
-
-#define CONFIG_EBIU_AMGCTL_VAL	0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL	0xBBC3BBC3
-#define CONFIG_EBIU_AMBCTL1_VAL	0x99B39983
-
-#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(384 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_SMC91111	1
-#define CONFIG_SMC91111_BASE	0x20300300
-#define SMC91111_EEPROM_INIT() \
-	do { \
-		bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
-		bfin_write_FIO_FLAG_C(PF1); \
-		bfin_write_FIO_FLAG_S(PF0); \
-		SSYNC(); \
-	} while (0)
-#define CONFIG_HOSTNAME		bf533-stamp
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define CONFIG_SOFT_I2C_GPIO_SCL	GPIO_PF3
-#define CONFIG_SOFT_I2C_GPIO_SDA	GPIO_PF2
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	67
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-/*
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-#define CONFIG_SPI_FLASH_ALL
-*/
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x10000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET	0x4000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#endif
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#else
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
-	arch/blackfin/lib/built-in.o (.text*); \
-	arch/blackfin/cpu/built-in.o (.text*); \
-	. = DEFINED(env_offset) ? env_offset : .; \
-	common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C_SOFT
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C
-#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
-#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
-#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
-#define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0
-#endif
-
-/*
- * Compact Flash / IDE / ATA Settings
- */
-
-/* Enabled below option for CF support */
-/* #define CONFIG_STAMP_CF */
-#if defined(CONFIG_STAMP_CF)
-#define CONFIG_MISC_INIT_R
-#undef  CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
-#undef  CONFIG_IDE_LED			/* no led for ide supported */
-#undef  CONFIG_IDE_RESET		/* no reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS		1
-#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS * 1)
-
-#define CONFIG_SYS_ATA_BASE_ADDR	0x20200000
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x0007	/* alternate registers */
-
-#define CONFIG_SYS_ATA_STRIDE		2
-
-#undef CONFIG_EBIU_AMBCTL1_VAL
-#define CONFIG_EBIU_AMBCTL1_VAL	0x99B3ffc2
-#endif
-
-/*
- * Misc Settings
- */
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	0
-
-/* FLASH/ETHERNET uses the same async bank */
-#define SHARED_RESOURCES 	1
-
-/* define to enable boot progress via leds */
-/* #define CONFIG_SHOW_BOOT_PROGRESS */
-
-/* define to enable run status via led */
-
-/* define to enable splash screen support */
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
deleted file mode 100644
index 5d57b80..0000000
--- a/include/configs/bf537-minotaur.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * U-Boot - Configuration file for CSP Minotaur board
- *
- * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
- *    Minotaur config, brushed up for official uClinux dist.
- *    Parallel flash support disabled, SPI flash boot command
- *    added ('run flashboot').
- *
- * Flash image map:
- *
- * 0x00000000      u-boot bootstrap
- * 0x00010000      environment
- * 0x00020000      u-boot code
- * 0x00030000      uImage.initramfs
- *
- */
-
-#ifndef __CONFIG_BF537_MINOTAUR_H__
-#define __CONFIG_BF537_MINOTAUR_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			20
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_SIZE			32
-#define CONFIG_MEM_ADD_WDTH		9
-
-#define CONFIG_EBIU_SDRRC_VAL		0x306
-#define CONFIG_EBIU_SDGCTL_VAL		0x91114d
-
-#define CONFIG_EBIU_AMGCTL_VAL		0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define CONFIG_BFIN_MAC
-#define CONFIG_NETCONSOLE	1
-#endif
-#ifdef CONFIG_BFIN_MAC
-#define CONFIG_IPADDR		192.168.0.15
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_GATEWAYIP	192.168.0.1
-#define CONFIG_SERVERIP		192.168.0.2
-#define CONFIG_HOSTNAME		bf537-minotaur
-#endif
-
-#define CONFIG_SYS_AUTOLOAD	"no"
-#define CONFIG_ROOTPATH		"/romfs"
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x10000
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-#define CONFIG_SYS_I2C_SPEED		50000
-#define CONFIG_SYS_I2C_SLAVE		0
-
-/*
- * Misc Settings
- */
-#define CONFIG_SYS_LONGHELP		1
-#define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_ENV_OVERWRITE	1
-
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BFIN_SERIAL
-
-#define CONFIG_PANIC_HANG	1
-#define CONFIG_RTC_BFIN		1
-#define CONFIG_BOOT_RETRY_TIME	-1
-#define CONFIG_LOADS_ECHO		1
-
-#define CONFIG_CMD_BOOTLDR
-#define CONFIG_CMD_DATE
-
-#define CONFIG_BOOTCOMMAND	"run ramboot"
-#define CONFIG_BOOTARGS	"root=/dev/mtdblock0 rw"
-
-#define BOOT_ENV_SETTINGS \
-	"update=tftpboot $(loadaddr) u-boot.ldr;" \
-		"sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
-		"sf erase 0 0x30000;" \
-		"sf write $(loadaddr) 0 $(filesize)" \
-	"flashboot=sf read 0x1000000 0x30000 0x320000;" \
-		"bootm 0x1000000\0"
-#ifdef CONFIG_BFIN_MAC
-# define NETWORK_ENV_SETTINGS \
-	"nfsargs=setenv bootargs root=/dev/nfs rw " \
-		"nfsroot=$(serverip):$(rootpath)\0" \
-	"addip=setenv bootargs $(bootargs) " \
-		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
-		":$(hostname):eth0:off\0" \
-	"ramboot=tftpboot $(loadaddr) linux;" \
-		"run ramargs;run addip;bootelf\0" \
-	"nfsboot=tftpboot $(loadaddr) linux;" \
-		"run nfsargs;run addip;bootelf\0"
-#else
-# define NETWORK_ENV_SETTINGS
-#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	NETWORK_ENV_SETTINGS \
-	"ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \
-	BOOT_ENV_SETTINGS
-
-#endif
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
deleted file mode 100644
index 6d80592..0000000
--- a/include/configs/bf537-pnav.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * U-Boot - Configuration file for BF537 PNAV board
- */
-
-#ifndef __CONFIG_BF537_PNAV_H__
-#define __CONFIG_BF537_PNAV_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			24576000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			20
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			4
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	10
-#define CONFIG_MEM_SIZE		64
-
-#define CONFIG_EBIU_SDRRC_VAL	0x3b7
-#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL	0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB033B0
-#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_BFIN_MAC
-#define CONFIG_RMII
-#endif
-#define CONFIG_HOSTNAME		bf537-pnav
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	71
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x4000
-#else
-#define ENV_IS_EMBEDDED
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		0x20004000
-#define CONFIG_ENV_OFFSET	0x4000
-#endif
-#define CONFIG_ENV_SIZE		0x1000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
-	arch/blackfin/lib/built-in.o (.text*); \
-	arch/blackfin/cpu/built-in.o (.text*); \
-	. = DEFINED(env_offset) ? env_offset : .; \
-	common/env_embedded.o (.text*);
-#endif
-
-/*
- * NAND Settings
- */
-#define CONFIG_NAND_PLAT
-
-#define CONFIG_SYS_NAND_BASE		0x20100000
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
-#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
-#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_WRITE(addr, cmd) \
-	do { \
-		bfin_write8(addr, cmd); \
-		SSYNC(); \
-	} while (0)
-
-#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
-#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF12
-
-/*
- * I2C settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Misc Settings
- */
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	0
-
-/* JFFS Partition offset set  */
-#define CONFIG_SYS_JFFS2_FIRST_BANK	0
-#define CONFIG_SYS_JFFS2_NUM_BANKS	1
-/* 512k reserved for u-boot */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR	15
-
-#define CONFIG_BOOTCOMMAND	"run nandboot"
-#define CONFIG_BOOTARGS_ROOT	"/dev/mtdblock1 rw rootfstype=yaffs"
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
deleted file mode 100644
index 3b69e58..0000000
--- a/include/configs/bf537-srv1.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * U-Boot - Configuration file for CSP Minotaur board
- *
- * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
- *    Minotaur config, brushed up for official uClinux dist.
- *    Parallel flash support disabled, SPI flash boot command
- *    added ('run flashboot').
- *
- * Flash image map:
- *
- * 0x00000000      u-boot bootstrap
- * 0x00010000      environment
- * 0x00020000      u-boot code
- * 0x00030000      uImage.initramfs
- *
- */
-
-#ifndef __CONFIG_BF537_SRV1_H__
-#define __CONFIG_BF537_SRV1_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			22118400
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			20
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_SIZE			32
-#define CONFIG_MEM_ADD_WDTH		9
-
-#define CONFIG_EBIU_SDRRC_VAL		0x2ac
-#define CONFIG_EBIU_SDGCTL_VAL		0x91110d
-
-#define CONFIG_EBIU_AMGCTL_VAL		0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(384 << 10)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define CONFIG_BFIN_MAC
-#define CONFIG_NETCONSOLE	1
-#endif
-#ifdef CONFIG_BFIN_MAC
-#define CONFIG_IPADDR		192.168.0.15
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_GATEWAYIP	192.168.0.1
-#define CONFIG_SERVERIP		192.168.0.2
-#define CONFIG_HOSTNAME		bf537-srv1
-#endif
-
-#define CONFIG_SYS_AUTOLOAD	"no"
-#define CONFIG_ROOTPATH		"/romfs"
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x10000
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-#define CONFIG_SYS_I2C_SPEED		50000
-#define CONFIG_SYS_I2C_SLAVE		0
-
-/*
- * Misc Settings
- */
-#define CONFIG_SYS_LONGHELP		1
-#define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_ENV_OVERWRITE	1
-
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BFIN_SERIAL
-
-#define CONFIG_PANIC_HANG	1
-#define CONFIG_RTC_BFIN		1
-#define CONFIG_BOOT_RETRY_TIME	-1
-#define CONFIG_LOADS_ECHO		1
-
-#define CONFIG_CMD_BOOTLDR
-#define CONFIG_CMD_DATE
-
-#define CONFIG_BOOTCOMMAND	"run flashboot"
-#define CONFIG_BOOTARGS	"root=/dev/mtdblock0 rw"
-
-#define BOOT_ENV_SETTINGS \
-	"update=tftpboot $(loadaddr) u-boot.ldr;" \
-		"sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
-		"sf erase 0 0x30000;" \
-		"sf write $(loadaddr) 0 $(filesize)" \
-	"flashboot=sf read 0x1000000 0x30000 0x320000;" \
-		"bootm 0x1000000\0"
-#ifdef CONFIG_BFIN_MAC
-# define NETWORK_ENV_SETTINGS \
-	"nfsargs=setenv bootargs root=/dev/nfs rw " \
-		"nfsroot=$(serverip):$(rootpath)\0" \
-	"addip=setenv bootargs $(bootargs) " \
-		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
-		":$(hostname):eth0:off\0" \
-	"ramboot=tftpboot $(loadaddr) linux;" \
-		"run ramargs;run addip;bootelf\0" \
-	"nfsboot=tftpboot $(loadaddr) linux;" \
-		"run nfsargs;run addip;bootelf\0"
-#else
-# define NETWORK_ENV_SETTINGS
-#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	NETWORK_ENV_SETTINGS \
-	"ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \
-	BOOT_ENV_SETTINGS
-
-#endif
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
deleted file mode 100644
index 6858153..0000000
--- a/include/configs/bf537-stamp.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * U-Boot - Configuration file for BF537 STAMP board
- */
-
-#ifndef __CONFIG_BF537_STAMP_H__
-#define __CONFIG_BF537_STAMP_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			20
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			4
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	10
-#define CONFIG_MEM_SIZE		64
-
-#define CONFIG_EBIU_SDRRC_VAL	0x306
-#define CONFIG_EBIU_SDGCTL_VAL	0x91114d
-
-#define CONFIG_EBIU_AMGCTL_VAL	0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_BFIN_MAC
-#define CONFIG_NETCONSOLE	1
-#endif
-#define CONFIG_HOSTNAME		bf537-stamp
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
-#define CONFIG_SYS_MAX_FLASH_SECT	71
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-#define CONFIG_SPI_FLASH_ALL
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x10000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET	0x4000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#endif
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#else
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
-	arch/blackfin/lib/built-in.o (.text*); \
-	arch/blackfin/cpu/built-in.o (.text*); \
-	. = DEFINED(env_offset) ? env_offset : .; \
-	common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * SPI_MMC Settings
- */
-#define CONFIG_MMC_SPI
-
-/*
- * NAND Settings
- */
-/* #define CONFIG_NAND_PLAT */
-#ifdef CONFIG_NAND_PLAT
-#define CONFIG_SYS_NAND_BASE		0x20212000
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
-#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
-#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_WRITE(addr, cmd) \
-	do { \
-		bfin_write8(addr, cmd); \
-		SSYNC(); \
-	} while (0)
-
-#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
-#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF3
-#endif /* CONFIG_NAND_PLAT */
-
-/*
- * CF-CARD IDE-HDD Support
- */
-
-/*
- * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
- * Strange address mapping Blackfin A13 connects to CF_A0
- */
-
-/* #define CONFIG_BFIN_TRUE_IDE */
-
-/*
- * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
- * This should be the preferred mode
- */
-
-/* #define CONFIG_BFIN_CF_IDE */
-
-/*
- * Add IDE Disk Drive (HDD) support
- * See example interface here:
- * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
- */
-
-/* #define CONFIG_BFIN_HDD_IDE */
-
-#if defined(CONFIG_BFIN_CF_IDE) || \
-    defined(CONFIG_BFIN_HDD_IDE) || \
-    defined(CONFIG_BFIN_TRUE_IDE)
-# define CONFIG_BFIN_IDE	1
-# define CONFIG_CMD_IDE
-#endif
-
-#if defined(CONFIG_BFIN_IDE)
-
-/*
- * IDE/ATA stuff
- */
-#undef  CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
-#undef  CONFIG_IDE_LED		/* no led for ide supported */
-#undef  CONFIG_IDE_RESET	/* no reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS		1
-#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS * 1)
-
-#undef  CONFIG_EBIU_AMBCTL1_VAL
-#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC3FFC3
-
-#define CONFIG_CF_ATASEL_DIS	0x20311800
-#define CONFIG_CF_ATASEL_ENA	0x20311802
-
-#if defined(CONFIG_BFIN_TRUE_IDE)
-/*
- * Note that these settings aren't for the most part used in include/ata.h
- * when all of the ATA registers are setup
- */
-#define CONFIG_SYS_ATA_BASE_ADDR	0x2031C000
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* alternate registers */
-#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A13 */
-
-#elif defined(CONFIG_BFIN_CF_IDE)
-#define CONFIG_SYS_ATA_BASE_ADDR	0x20211800
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x000E	/* alternate registers */
-#define CONFIG_SYS_ATA_STRIDE		1	/* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
-
-#elif defined(CONFIG_BFIN_HDD_IDE)
-#define CONFIG_SYS_ATA_BASE_ADDR	0x20314000
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* alternate registers */
-#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A1 */
-#undef  CONFIG_SCLK_DIV
-#define CONFIG_SCLK_DIV		8
-#endif
-
-#endif
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	0
-
-/* Define if want to do post memory test */
-#undef CONFIG_POST
-#ifdef CONFIG_POST
-#define CONFIG_SYS_POST_HOTKEYS_GPIO	GPIO_PF5
-#define CONFIG_POST_BSPEC1_GPIO_LEDS \
-	GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
-#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
-	GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2,
-#define CONFIG_POST_BSPEC2_GPIO_NAMES \
-	10, 11, 12, 13,
-#define CONFIG_SYS_POST_FLASH_START	11
-#define CONFIG_SYS_POST_FLASH_END	71
-#endif
-
-/* These are for board tests */
-#if 0
-#define CONFIG_BOOTCOMMAND       "bootldr 0x203f0100"
-#endif
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
deleted file mode 100644
index a6d039c..0000000
--- a/include/configs/bf538f-ezkit.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * U-Boot - Configuration file for BF538F EZ-Kit Lite board
- */
-
-#ifndef __CONFIG_BF538F_EZKIT_H__
-#define __CONFIG_BF538F_EZKIT_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf538-0.4
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			21
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			4
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	10
-#define CONFIG_MEM_SIZE		64
-
-#define CONFIG_EBIU_SDRRC_VAL	(0x03F6)
-#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3)
-
-#define CONFIG_EBIU_AMGCTL_VAL	(CDPRIO | AMBEN_ALL | AMCKEN)
-#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(384 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_SMC91111	1
-#define CONFIG_SMC91111_BASE	0x20310300
-#define CONFIG_HOSTNAME		bf538f-ezkit
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	71
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-/*
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-#define CONFIG_SPI_FLASH_ALL
-*/
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x4000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#else
-#define	CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET	0x4000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		0x2000
-#define	CONFIG_ENV_SECT_SIZE	0x2000
-#endif
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#else
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
-	arch/blackfin/lib/built-in.o (.text*); \
-	arch/blackfin/cpu/built-in.o (.text*); \
-	. = DEFINED(env_offset) ? env_offset : .; \
-	common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Misc Settings
- */
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	0
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
deleted file mode 100644
index 35cbebd..0000000
--- a/include/configs/bf548-ezkit.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * U-Boot - Configuration file for BF548 STAMP board
- */
-
-#ifndef __CONFIG_BF548_EZKIT_H__
-#define __CONFIG_BF548_EZKIT_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf548-0.0
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			21
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			4
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	10
-#define CONFIG_MEM_SIZE		64
-
-#define CONFIG_EBIU_DDRCTL0_VAL	0x218A83FE
-#define CONFIG_EBIU_DDRCTL1_VAL	0x20022222
-#define CONFIG_EBIU_DDRCTL2_VAL	0x00000021
-
-/* Default EZ-Kit bank mapping:
- *	Async Bank 0 - 32MB Burst Flash
- *	Async Bank 1 - Ethernet
- *	Async Bank 2 - Nothing
- *	Async Bank 3 - Nothing
- */
-#define CONFIG_EBIU_AMGCTL_VAL	0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
-#define CONFIG_EBIU_FCTL_VAL	(BCLK_4)
-#define CONFIG_EBIU_MODE_VAL	(B0MODE_FLASH)
-
-#define CONFIG_SYS_MONITOR_LEN	(1024 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(768 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_SMC911X	1
-#define CONFIG_SMC911X_BASE	0x24000000
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_HOSTNAME		bf548-ezkit
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	259
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x10000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET	0x60000
-#define CONFIG_ENV_SIZE		0x20000
-#else
-/* The BF548-EZKIT uses a top boot flash */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_OFFSET	(0x1000000 - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE	0x8000
-#endif
-
-/*
- * NAND Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-#define CONFIG_BFIN_NFC_CTL_VAL        0x0033
-#define CONFIG_BFIN_NFC_BOOTROM_ECC
-#define CONFIG_DRIVER_NAND_BFIN
-#define CONFIG_SYS_NAND_BASE           0 /* not actually used */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * SATA
- */
-#if !defined(__ADSPBF544__)
-#define CONFIG_LIBATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_LBA48
-#define CONFIG_PATA_BFIN
-#define CONFIG_BFIN_ATAPI_BASE_ADDR	0xFFC03800
-#define CONFIG_BFIN_ATA_MODE	XFER_PIO_4
-#endif
-
-/*
- * SDH Settings
- */
-#if !defined(__ADSPBF544__)
-#define CONFIG_BFIN_SDH
-#endif
-
-/*
- * USB Settings
- */
-#if !defined(__ADSPBF544__)
-#define CONFIG_USB_MUSB_HCD
-#define CONFIG_USB_BLACKFIN
-#define CONFIG_USB_MUSB_TIMEOUT 100000
-#endif
-
-/*
- * Misc Settings
- */
-#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	1
-#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
-
-#define CONFIG_ADI_GPIO2
-
-#ifdef CONFIG_VIDEO
-#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h >
-#define CONFIG_DEB_DMA_URGENT
-#endif
-
-/* Define if want to do post memory test */
-#undef CONFIG_POST
-#ifdef CONFIG_POST
-#define CONFIG_POST_BSPEC1_GPIO_LEDS \
-	GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11,
-#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
-	GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11
-#define CONFIG_POST_BSPEC2_GPIO_NAMES \
-	13, 12, 11, 10,
-#define CONFIG_SYS_POST_FLASH_START	10
-#define CONFIG_SYS_POST_FLASH_END	127
-#endif
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
deleted file mode 100644
index bf2d7b6..0000000
--- a/include/configs/bf561-acvilon.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * U-Boot - Configuration file for BF561 Acvilon System On Module
- * For more information please go to http://www.niistt.ru/
- */
-
-#ifndef __CONFIG_BF561_ACVILON_H__
-#define __CONFIG_BF561_ACVILON_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf561-0.5
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ				12000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF			0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS			0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT				50
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV				1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV				5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH			10
-#define CONFIG_MEM_SIZE				128
-
-#define CONFIG_EBIU_SDRRC_VAL		0x300
-#define CONFIG_EBIU_SDGCTL_VAL		0x00B11189
-
-#define CONFIG_EBIU_AMGCTL_VAL		0x4e
-#define CONFIG_EBIU_AMBCTL0_VAL		0xffc2ffc2
-#define CONFIG_EBIU_AMBCTL1_VAL		0x99b35554
-
-#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
-
-/*
- * RTC Settings
- */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
-#define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
-#define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
-#define CONFIG_SYS_I2C_DTT_ADDR 0x49
-/*#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS       3*/
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK			1
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DTT
-
-#if defined(CONFIG_CMD_NET)
-
-#define CONFIG_SMC911X				1
-#define CONFIG_SMC911X_32_BIT
-/* #define CONFIG_SMC911X_16_BIT */
-#define CONFIG_SMC911X_BASE			0x28000000
-
-#endif /* (CONFIG_CMD_NET) */
-
-#define CONFIG_HOSTNAME		bf561-acvilon
-
-/*
- * I2C Settings
- */
-#define CONFIG_HARD_I2C
-/* Use 300kHz speed by default */
-#define CONFIG_SYS_I2C_SPEED			0x00
-#define CONFIG_PCA9564_I2C
-#define CONFIG_PCA9564_BASE			0x2c000000
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ		10000000
-#define CONFIG_SF_DEFAULT_SPEED		10000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SECT_SIZE		(1056 * 8)
-#define CONFIG_ENV_OFFSET			((16 + 256) * 1056)
-#define CONFIG_ENV_SIZE				(8 * 1056)
-
-/*
- * NAND Settings
- * We're using NAND_PLAT driver to make things simplier
- */
-#define CONFIG_NAND_PLAT
-#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x24000000
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
-#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
-#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3))
-#define BFIN_NAND_WRITE(addr, cmd) \
-	do { \
-		bfin_write8(addr, cmd); \
-		SSYNC(); \
-	} while (0)
-
-#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
-#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
-
-/*
- * Misc Settings
- */
-#define CONFIG_UART_CONSOLE			0
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif				/* __CONFIG_BF561_ACVILON_H__ */
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
deleted file mode 100644
index 2fefe98..0000000
--- a/include/configs/bf561-ezkit.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * U-Boot - Configuration file for BF561 EZKIT board
- */
-
-#ifndef __CONFIG_BF561_EZKIT_H__
-#define __CONFIG_BF561_EZKIT_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf561-0.3
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			30000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			20
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			6
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	9
-#define CONFIG_MEM_SIZE		64
-
-#define CONFIG_EBIU_SDRRC_VAL	0x306
-#define CONFIG_EBIU_SDGCTL_VAL	0x91114d
-
-#define CONFIG_EBIU_AMGCTL_VAL	0x3F
-#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_SMC91111	1
-#define CONFIG_SMC91111_BASE	0x2C010300
-#define CONFIG_SMC_USE_32_BIT	1
-#define CONFIG_HOSTNAME		bf561-ezkit
-
-/*
- * Flash Settings
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	135
-/* The BF561-EZKIT uses a top boot flash */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET	(0x800000 - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE	0x2000
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C_SOFT
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C
-#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
-#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
-#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
-#define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0
-#endif
-
-/*
- * Misc Settings
- */
-#define CONFIG_UART_CONSOLE	0
-
-/*
- * Run core 1 from L1 SRAM start address when init uboot on core 0
- */
-/* #define CONFIG_CORE1_RUN	1 */
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
deleted file mode 100644
index 5791810..0000000
--- a/include/configs/bf609-ezkit.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * U-Boot - Configuration file for BF609 EZ-Kit board
- */
-
-#ifndef __CONFIG_BF609_EZKIT_H__
-#define __CONFIG_BF609_EZKIT_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf609-0.0
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
-
-/* For ez-board version 1.0, else undef this */
-#define CONFIG_BFIN_BOARD_VERSION_1_0
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SYSCLK_DIV
- *	SCLK0 = SCLK / SCLK0_DIV
- *	SCLK1 = SCLK / SCLK1_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			(25000000)
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		(0)
-
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-127 (where 0 means 128)			*/
-#define CONFIG_VCO_MULT			(20)
-
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can range from 0-31 (where 0 means 32)			*/
-#define CONFIG_CCLK_DIV			(1)
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 0-31 (where 0 means 32)			*/
-#define CONFIG_SCLK_DIV		(4)
-/* Values can range from 0-7 (where 0 means 8)				*/
-#define CONFIG_SCLK0_DIV		(1)
-#define CONFIG_SCLK1_DIV		(1)
-/* DCLK_DIV controls the DDR clock divider				*/
-/* Values can range from 0-31 (where 0 means 32)			*/
-#define CONFIG_DCLK_DIV			(2)
-/* OCLK_DIV controls the output clock divider				*/
-/* Values can range from 0-127 (where 0 means 128)			*/
-#define CONFIG_OCLK_DIV			(16)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_SIZE		128
-
-#define CONFIG_SMC_GCTL_VAL	0x00000010
-#define CONFIG_SMC_B0CTL_VAL	0x01007011
-#define CONFIG_SMC_B0TIM_VAL	0x08170977
-#define CONFIG_SMC_B0ETIM_VAL	0x00092231
-
-#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)
-
-#define CONFIG_HW_WATCHDOG
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK
-#define CONFIG_NETCONSOLE
-#define CONFIG_HOSTNAME		"bf609-ezkit"
-#define CONFIG_PHY_ADDR		1
-#define CONFIG_DW_PORTS		1
-#define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_MII
-
-/* i2c Settings */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Flash Settings
- */
-#undef CONFIG_CMD_JFFS2
-#define CONFIG_SYS_FLASH_CFI_WIDTH     2
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE          0xb0000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS     1
-#define CONFIG_SYS_MAX_FLASH_SECT      131
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI6XX
-#define CONFIG_ENV_SPI_MAX_HZ	25000000
-#define CONFIG_SF_DEFAULT_SPEED	25000000
-#define CONFIG_SPI_FLASH_ALL
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET       0x10000
-#define CONFIG_ENV_SIZE         0x2000
-#define CONFIG_ENV_SECT_SIZE    0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET       0x60000
-#define CONFIG_ENV_SIZE         0x20000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_OFFSET       0x8000
-#define CONFIG_ENV_SIZE         0x8000
-#define CONFIG_ENV_SECT_SIZE    0x8000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-
-#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0xB0100000\0"
-
-/*
- * SDH Settings
- */
-#define CONFIG_BFIN_SDH
-
-/*
- * Misc Settings
- */
-#define CONFIG_UART_CONSOLE	0
-
-#define CONFIG_CMD_SOFTSWITCH
-
-#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4)
-#define CONFIG_BFIN_SOFT_SWITCH
-
-#define CONFIG_ADI_GPIO2
-
-#if 0
-#define CONFIG_UART_MEM 1024
-#undef CONFIG_UART_CONSOLE
-#undef CONFIG_JTAG_CONSOLE
-#undef CONFIG_UART_CONSOLE_IS_JTAG
-#endif
-
-#define CONFIG_BOARD_SIZE_LIMIT $$((512 * 1024))
-
-/*
- * Run core 1 from L1 SRAM start address when init uboot on core 0
- */
-/* #define CONFIG_CORE1_RUN	1 */
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-#endif
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
deleted file mode 100644
index a915b1a..0000000
--- a/include/configs/bfin_adi_common.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * U-Boot - Common settings for Analog Devices boards
- */
-
-#ifndef __CONFIG_BFIN_ADI_COMMON_H__
-#define __CONFIG_BFIN_ADI_COMMON_H__
-
-/*
- * Command Settings
- */
-#ifndef _CONFIG_CMD_DEFAULT_H
-# ifdef ADI_CMDS_NETWORK
-#  define CONFIG_BOOTP_SUBNETMASK
-#  define CONFIG_BOOTP_GATEWAY
-#  define CONFIG_BOOTP_DNS
-#  define CONFIG_BOOTP_NTPSERVER
-#  define CONFIG_BOOTP_RANDOM_DELAY
-#  define CONFIG_KEEP_SERVERADDR
-#  ifdef CONFIG_BFIN_MAC
-#  endif
-# endif
-# ifdef CONFIG_LIBATA
-#  define CONFIG_CMD_SATA
-# endif
-# ifdef CONFIG_MMC
-#  define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
-# endif
-# ifdef CONFIG_MMC_SPI
-#  define CONFIG_CMD_MMC_SPI
-# endif
-# ifdef CONFIG_USB
-#  define CONFIG_CMD_USB_STORAGE
-# endif
-# if defined(CONFIG_NAND_PLAT) || defined(CONFIG_DRIVER_NAND_BFIN)
-#  define CONFIG_CMD_NAND
-#  define CONFIG_CMD_NAND_LOCK_UNLOCK
-# endif
-# ifdef CONFIG_POST
-#  define CONFIG_CMD_DIAG
-# endif
-# ifdef CONFIG_RTC_BFIN
-#  define CONFIG_CMD_DATE
-#  ifdef ADI_CMDS_NETWORK
-#  endif
-# endif
-# ifdef CONFIG_SPI
-#  define CONFIG_CMD_EEPROM
-# endif
-# if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT)
-#  define CONFIG_SOFT_I2C_READ_REPEATED_START
-# endif
-# ifdef CONFIG_MTD_NOR_FLASH
-#  define CONFIG_CMD_JFFS2
-# endif
-# ifdef CONFIG_CMD_JFFS2
-#  define CONFIG_JFFS2_SUMMARY
-# endif
-# define CONFIG_CMD_BOOTLDR
-# define CONFIG_CMD_CPLBINFO
-# define CONFIG_CMD_KGDB
-# define CONFIG_CMD_LDRINFO
-# define CONFIG_CMD_REGINFO
-# define CONFIG_CMD_STRINGS
-# if defined(__ADSPBF51x__) || defined(__ADSPBF52x__) || defined(__ADSPBF54x__)
-#  define CONFIG_CMD_OTP
-#  define CONFIG_CMD_SPIBOOTLDR
-# endif
-#endif
-
-/*
- * Console Settings
- */
-#define CONFIG_SYS_LONGHELP	1
-#define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_AUTO_COMPLETE	1
-#define CONFIG_LOADS_ECHO	1
-#define CONFIG_JTAG_CONSOLE
-#ifdef CONFIG_UART_CONSOLE
-# define CONFIG_BFIN_SERIAL
-#endif
-
-/*
- * Debug Settings
- */
-#define CONFIG_ENV_OVERWRITE	1
-#define CONFIG_DEBUG_DUMP	1
-#define CONFIG_KALLSYMS		1
-#define CONFIG_PANIC_HANG	1
-
-/*
- * Env Settings
- */
-#ifndef CONFIG_BOOTCOMMAND
-# define CONFIG_BOOTCOMMAND	"run ramboot"
-#endif
-#ifdef CONFIG_VIDEO
-# define CONFIG_BOOTARGS_VIDEO "console=tty0 "
-#else
-# define CONFIG_BOOTARGS_VIDEO ""
-#endif
-#ifndef CONFIG_BOOTARGS_ROOT
-# define CONFIG_BOOTARGS_ROOT "/dev/mtdblock0 rw"
-#endif
-#ifndef FLASHBOOT_ENV_SETTINGS
-# define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20100000\0"
-#endif
-#define CONFIG_BOOTARGS	\
-	"root=" CONFIG_BOOTARGS_ROOT " " \
-	"clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
-	"earlyprintk=" \
-		"serial," \
-		"uart" __stringify(CONFIG_UART_CONSOLE) "," \
-		__stringify(CONFIG_BAUDRATE) " " \
-	CONFIG_BOOTARGS_VIDEO \
-	"console=ttyBF" __stringify(CONFIG_UART_CONSOLE) "," \
-			__stringify(CONFIG_BAUDRATE)
-#if defined(CONFIG_CMD_NAND)
-# define NAND_ENV_SETTINGS \
-	"nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
-	"nandboot=" \
-		"nand read $(loadaddr) 0x20000 0x100000;" \
-		"run nandargs;" \
-		"bootm" \
-		"\0"
-#else
-# define NAND_ENV_SETTINGS
-#endif
-#if defined(CONFIG_CMD_NET)
-# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#  define UBOOT_ENV_FILE "u-boot.bin"
-# else
-#  define UBOOT_ENV_FILE "u-boot.ldr"
-# endif
-# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#  ifdef CONFIG_SPI
-#   define UBOOT_ENV_UPDATE \
-		"eeprom write $(loadaddr) 0x0 $(filesize)"
-#  else
-#   ifndef CONFIG_BFIN_SPI_IMG_SIZE
-#    define CONFIG_BFIN_SPI_IMG_SIZE 0x40000
-#   endif
-#   define UBOOT_ENV_UPDATE \
-		"sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
-		"sf erase 0 " __stringify(CONFIG_BFIN_SPI_IMG_SIZE) ";" \
-		"sf write $(loadaddr) 0 $(filesize)"
-#  endif
-# elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-#  define UBOOT_ENV_UPDATE \
-		"nand unlock 0 0x40000;" \
-		"nand erase 0 0x40000;" \
-		"nand write $(loadaddr) 0 0x40000"
-# else
-#  ifndef UBOOT_ENV_UPDATE
-#   define UBOOT_ENV_UPDATE \
-		"protect off 0x20000000 +$(filesize);" \
-		"erase 0x20000000 +$(filesize);" \
-		"cp.b $(loadaddr) 0x20000000 $(filesize)"
-#  endif
-# endif
-# ifdef CONFIG_NETCONSOLE
-#  define NETCONSOLE_ENV \
-	"nc=" \
-		"set ncip ${serverip};" \
-		"set stdin nc;" \
-		"set stdout nc;" \
-		"set stderr nc" \
-		"\0"
-# else
-#  define NETCONSOLE_ENV
-# endif
-# define NETWORK_ENV_SETTINGS \
-	NETCONSOLE_ENV \
-	\
-	"ubootfile=" UBOOT_ENV_FILE "\0" \
-	"update=" \
-		"tftp $(loadaddr) $(ubootfile);" \
-		UBOOT_ENV_UPDATE \
-		"\0" \
-	"addip=set bootargs $(bootargs) " \
-		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
-		   "$(hostname):eth0:off" \
-		"\0" \
-	\
-	"ramfile=uImage\0" \
-	"ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
-	"ramboot=" \
-		"tftp $(loadaddr) $(ramfile);" \
-		"run ramargs;" \
-		"run addip;" \
-		"bootm" \
-		"\0" \
-	\
-	"nfsfile=vmImage\0" \
-	"nfsargs=set bootargs " \
-		"root=/dev/nfs rw " \
-		"nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
-		"\0" \
-	"nfsboot=" \
-		"tftp $(loadaddr) $(nfsfile);" \
-		"run nfsargs;" \
-		"run addip;" \
-		"bootm" \
-		"\0"
-#else
-# define NETWORK_ENV_SETTINGS
-#endif
-#ifndef BOARD_ENV_SETTINGS
-# define BOARD_ENV_SETTINGS
-#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	NAND_ENV_SETTINGS \
-	NETWORK_ENV_SETTINGS \
-	FLASHBOOT_ENV_SETTINGS \
-	BOARD_ENV_SETTINGS
-
-/*
- * Network Settings
- */
-#ifdef CONFIG_CMD_NET
-# define CONFIG_NETMASK		255.255.255.0
-# ifndef CONFIG_IPADDR
-#  define CONFIG_IPADDR		192.168.0.15
-#  define CONFIG_GATEWAYIP	192.168.0.1
-#  define CONFIG_SERVERIP	192.168.0.2
-# endif
-# ifndef CONFIG_ROOTPATH
-#  define CONFIG_ROOTPATH	"/romfs"
-# endif
-# ifdef CONFIG_CMD_DHCP
-#  ifndef CONFIG_SYS_AUTOLOAD
-#   define CONFIG_SYS_AUTOLOAD "no"
-#  endif
-# endif
-# define CONFIG_IP_DEFRAG
-# define CONFIG_NET_RETRY_COUNT 20
-#endif
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-
-/*
- * SPI Settings
- */
-#ifdef CONFIG_SPI_FLASH_ALL
-#endif
-
-/*
- * I2C Settings
- */
-#if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT)
-# ifndef CONFIG_SYS_I2C_SPEED
-#  define CONFIG_SYS_I2C_SPEED 50000
-# endif
-# ifndef CONFIG_SYS_I2C_SLAVE
-#  define CONFIG_SYS_I2C_SLAVE 0
-# endif
-#endif
-
-/*
- * Misc Settings
- */
-#ifndef CONFIG_BOARD_SIZE_LIMIT
-# define CONFIG_BOARD_SIZE_LIMIT $$(( 256 * 1024 ))
-#endif
-#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */
-#define CONFIG_LZMA
-#define CONFIG_MONITOR_IS_IN_RAM
-#ifdef CONFIG_HW_WATCHDOG
-# define CONFIG_BFIN_WATCHDOG
-# ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
-#  define CONFIG_WATCHDOG_TIMEOUT_MSECS 5000
-# endif
-#endif
-#ifndef CONFIG_ADI_GPIO2
-# define CONFIG_ADI_GPIO1
-#endif
-#endif
diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h
deleted file mode 100644
index 4f65a1d..0000000
--- a/include/configs/blackstamp.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * U-Boot - Configuration file for BlackStamp board
- * Configuration by Ben Matthews for UR LLE using bf533-stamp.h
- * as a template
- * See http://blackfin.uclinux.org/gf/project/blackstamp/
- */
-
-#ifndef __CONFIG_BLACKSTAMP_H__
-#define __CONFIG_BLACKSTAMP_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Debugging: Set these options if you're having problems
- */
-/*
- * #define CONFIG_DEBUG_EARLY_SERIAL
- * #define DEBUG
- * #define CONFIG_DEBUG_DUMP
- * #define CONFIG_DEBUG_DUMP_SYMS
-*/
-#define CONFIG_PANIC_HANG 0
-
-/* CPU Options
- * Be sure to set the Silicon Revision Correctly
- */
-#define CONFIG_BFIN_CPU		bf532-0.5
-#define CONFIG_BFIN_BOOT_MODE	BFIN_BOOT_SPI_MASTER
-
-/*
- * Board settings
- */
-#define CONFIG_SMC91111	1
-#define CONFIG_SMC91111_BASE	0x20300300
-
-/* FLASH/ETHERNET uses the same address range
- * Depending on what you have the CPLD doing
- * this probably isn't needed
- */
-#define SHARED_RESOURCES	1
-
-/* Is I2C bit-banged? */
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			16
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			3
-
-/*
- * Network settings
- */
-
-#ifdef CONFIG_SMC91111
-#define CONFIG_IPADDR		192.168.0.15
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_GATEWAYIP	192.168.0.1
-#define CONFIG_SERVERIP		192.168.0.2
-#define CONFIG_HOSTNAME		blackstamp
-#define CONFIG_ROOTPATH		"/checkout/uClinux-dist/romfs"
-#define CONFIG_SYS_AUTOLOAD		"no"
-#endif
-
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x40000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x40000
-
-/*
- * SDRAM settings & memory map
- */
-
-#define CONFIG_MEM_SIZE		64	/* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH	10	/* 8, 9, 10, 11    */
-
-#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
-#define CONFIG_SYS_MALLOC_LEN	(384 << 10)
-
-/*
- * Command settings
- */
-
-#define CONFIG_SYS_LONGHELP		1
-#define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_AUTO_COMPLETE	1
-#define CONFIG_ENV_OVERWRITE	1
-
-#define CONFIG_CMD_BOOTLDR
-#define CONFIG_CMD_CPLBINFO
-#define CONFIG_CMD_DATE
-
-#define CONFIG_BOOTCOMMAND   "run ramboot"
-#define CONFIG_BOOTARGS \
-	"root=/dev/mtdblock0 rw " \
-	"clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
-	"earlyprintk=" \
-		"serial," \
-		"uart" __stringify(CONFIG_UART_CONSOLE) "," \
-		__stringify(CONFIG_BAUDRATE) " " \
-	"console=ttyBF0," __stringify(CONFIG_BAUDRATE)
-
-#if defined(CONFIG_CMD_NET)
-# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#  define UBOOT_ENV_FILE "u-boot.bin"
-# else
-#  define UBOOT_ENV_FILE "u-boot.ldr"
-# endif
-# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#  ifdef CONFIG_SPI
-#   define UBOOT_ENV_UPDATE \
-		"eeprom write $(loadaddr) 0x0 $(filesize)"
-#  else
-#   define UBOOT_ENV_UPDATE \
-		"sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
-		"sf erase 0 0x40000;" \
-		"sf write $(loadaddr) 0 $(filesize)"
-#  endif
-# else
-#  define UBOOT_ENV_UPDATE \
-		"protect off 0x20000000 0x2003FFFF;" \
-		"erase 0x20000000 0x2003FFFF;" \
-		"cp.b $(loadaddr) 0x20000000 $(filesize)"
-# endif
-# define NETWORK_ENV_SETTINGS \
-	"ubootfile=" UBOOT_ENV_FILE "\0" \
-	"update=" \
-		"tftp $(loadaddr) $(ubootfile);" \
-		UBOOT_ENV_UPDATE \
-		"\0" \
-	"addip=set bootargs $(bootargs) " \
-		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
-		   "$(hostname):eth0:off" \
-		"\0" \
-	"ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
-	"ramboot=" \
-		"tftp $(loadaddr) uImage;" \
-		"run ramargs;" \
-		"run addip;" \
-		"bootm" \
-		"\0" \
-	"nfsargs=set bootargs " \
-		"root=/dev/nfs rw " \
-		"nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
-		"\0" \
-	"nfsboot=" \
-		"tftp $(loadaddr) vmImage;" \
-		"run nfsargs;" \
-		"run addip;" \
-		"bootm" \
-		"\0"
-#else
-# define NETWORK_ENV_SETTINGS
-#endif
-
-/*
- * Console settings
- */
-#define CONFIG_LOADS_ECHO	1
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BFIN_SERIAL
-
-/*
- * I2C settings
- * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
- * Located on the expansion connector on pins 86/85
- * Note these pins are arbitrarily chosen because we aren't using
- * them yet. You can (and probably should) change these values!
- */
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF9
-#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF8
-#define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_RTC_BFIN		1
-
-/*
- * Serial Flash Infomation
- */
-#define CONFIG_BFIN_SPI
-/* For the M25P64 SCK Should be Kept < 15Mhz */
-#define CONFIG_ENV_SPI_MAX_HZ	15000000
-#define CONFIG_SF_DEFAULT_SPEED	15000000
-
-/*
- * FLASH organization and environment definitions
- */
-
-#define CONFIG_EBIU_AMGCTL_VAL		0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL		0xBBC3BBC3
-#define CONFIG_EBIU_AMBCTL1_VAL		0x99B39983
-#define CONFIG_EBIU_SDRRC_VAL		0x268
-#define CONFIG_EBIU_SDGCTL_VAL		0x911109
-
-#undef CONFIG_CMD_JFFS2
-
-#endif
diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h
deleted file mode 100644
index fe823ba..0000000
--- a/include/configs/blackvme.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/* U-Boot for BlackVME. (C) Wojtek Skulski 2010.
- * The board includes ADSP-BF561 rev. 0.5,
- * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG),
- * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell),
- * SPI  boot flash on PF2 (M25P64 8MB, or M25P128 16 MB),
- * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB),
- * Spartan6-LX150 (memory-mapped; both PPIs also connected).
- * See http://www.skutek.com
- */
-
-#ifndef __CONFIG_BLACKVME_H__
-#define __CONFIG_BLACKVME_H__
-
-#include <asm/config-pre.h>
-
-/* Debugging: Set these options if you're having problems
- * #define CONFIG_DEBUG_EARLY_SERIAL
- * #define DEBUG
- * #define CONFIG_DEBUG_DUMP
- * #define CONFIG_DEBUG_DUMP_SYMS
- * CONFIG_PANIC_HANG means that the board will not auto-reboot
- */
-#define CONFIG_PANIC_HANG 0
-
-/* CPU Options */
-#define CONFIG_BFIN_CPU        bf561-0.5
-#define CONFIG_BFIN_BOOT_MODE  BFIN_BOOT_SPI_MASTER
-
-/*
- *		CLOCK SETTINGS CAVEAT
- * You CANNOT just change the clock settings, esp. the SCLK.
- * The SDRAM timing, SPI baud, and the serial UART baud
- * use SCLK frequency to set their own frequencies. Therefore,
- * if you change the SCLK_DIV, you may also have to adjust
- * SDRAM refresh and other timings.
- * --------------------------------------------------------------
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *		25 *  8 / 1 = 200 MHz
- *		25 * 16 / 1 = 400 MHz
- *		25 * 24 / 1 = 600 MHz
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- *		25 *  8 / 2 = 100 MHz
- *		25 * 24 / 6 = 100 MHz
- *		25 * 24 / 5 = 120 MHz
- *		25 * 16 / 3 = 133 MHz
- * 25 MHz because the oscillator also feeds the ether chip.
- * CONFIG_CLKIN_HZ is 25 MHz written in Hz
- * CLKIN_HALF controls the DF bit in PLL_CTL
- *	0 = CLKIN	1 = CLKIN / 2
- * PLL_BYPASS controls the BYPASS bit in PLL_CTL
- *	0 = do not bypass	1 = bypass PLL
- * VCO_MULT = MSEL (multiplier) in PLL_CTL
- * Values can range from 0-63 (where 0 means 64)
- * CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY)
- * SCLK_DIV = system clock divider, 1 to 15
- */
-#define CONFIG_CLKIN_HZ		25000000
-#define CONFIG_CLKIN_HALF	0
-#define CONFIG_PLL_BYPASS	0
-#define CONFIG_VCO_MULT		8
-#define CONFIG_CCLK_DIV		1
-#define CONFIG_SCLK_DIV		2
-
-/*
- * Ether chip in async memory space AMS3, same as BF561-EZ-KIT.
- * Used in 32-bit mode. 16-bit mode not supported.
- * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
- */
-/*
- * Network settings using a dedicated 2nd ether card in PC
- * Windows will automatically acquire IP of that card
- * Then use the dedicated card IP + 1 for the board
- * http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network
- */
-#define CONFIG_DRIVER_AX88180	1
-#define AX88180_BASE		0x2c000000
-
-#define CONFIG_HOSTNAME	blackvme	/* Bfin board  */
-#define CONFIG_IPADDR		169.254.144.145	/* Bfin board  */
-#define CONFIG_GATEWAYIP	169.254.144.144	/* dedic card  */
-#define CONFIG_SERVERIP	169.254.144.144	/* tftp server */
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_ROOTPATH		"/export/uClinux-dist/romfs"	/*NFS*/
-#define CFG_AUTOLOAD		"no"
-
-/*
- * SDRAM settings & memory map
- */
-
-#define CONFIG_MEM_SIZE		64	/* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH	 9	/* 8, 9, 10, 11    */
-/*
- * SDRAM reference page
- * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
- * NOTE: BlackVME populates only SDRAM bank 0
- */
-/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */
-#define CONFIG_EBIU_SDGCTL_VAL  0x91114d  /* global control */
-#define CONFIG_EBIU_SDRRC_VAL   0x306     /* refresh rate */
-
-/* Async memory global settings. (ASRAM, not SDRAM)
- * HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1
- * CLKOUT enabled, all async banks enabled, core has priority
- * bank 0&1 16 bit (FPGA)
- * bank 2&3 32 bit (ether and USB chips)
- */
-#define CONFIG_EBIU_AMGCTL_VAL  0x3F   /* ASRAM setup */
-
-/* Async mem timing: BF561 HRM page 16-12 and 16-15.
- * Default values 0xFFC2 FFC2 are the slowest supported.
- * Example settings of CONFIG_EBIU_AMBCTL1_VAL
- * 1. EZ-KIT settings: 0xFFC2 7BB0
- * 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx
- *    See the following page:
- *    http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
- * 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz:
- * AX88180  WEN = 5 clocks  REN 6 clocks @ SCLK = 100 MHz
- * One extra clock needed because AX88180 is asynchronous to CPU.
- */
-			   /* bank 1   0 */
-#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2
-			   /* bank 3   2 */
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2
-
-/* memory layout */
-
-#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
-#define CONFIG_SYS_MALLOC_LEN	(384 << 10)
-
-/*
- * Serial SPI Flash
- * For the M25P64 SCK should be kept < 15 MHz
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x40000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x40000
-
-#define CONFIG_ENV_SPI_MAX_HZ	15000000
-#define CONFIG_SF_DEFAULT_SPEED	15000000
-
-/*
- * Interactive command settings
- */
-
-#define CONFIG_SYS_LONGHELP	1
-#define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_AUTO_COMPLETE	1
-
-#define CONFIG_CMD_BOOTLDR
-#define CONFIG_CMD_CPLBINFO
-
-/*
- * Default: boot from SPI flash.
- * "sfboot" is a composite command defined in extra settings
- */
-#define CONFIG_BOOTCOMMAND	"run sfboot"
-
-/*
- * Console settings
- */
-#define CONFIG_LOADS_ECHO	1
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BFIN_SERIAL
-
-/*
- * U-Boot environment variables. Use "printenv" to examine.
- * http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env
- */
-#define CONFIG_BOOTARGS \
-	"root=/dev/mtdblock0 rw " \
-	"clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
-	"earlyprintk=serial,uart0," \
-	__stringify(CONFIG_BAUDRATE) " " \
-	"console=ttyBF0," __stringify(CONFIG_BAUDRATE) " "
-
-/* Convenience env variables & commands.
- * Reserve kernstart = 0x20000  = 128 kB for U-Boot.
- * Reserve kernarea  = 0x500000 = 5 MB   for kernel (reasonable size).
- * U-Boot image is saved at flash offset=0.
- * Kernel image is saved at flash offset=$kernstart.
- * Instructions. Ksave takes about a minute to complete.
- *	1. Update U-Boot: run uget; run usave
- *	2. Update kernel: run kget; run ksave
- * After updating U-Boot also update the kernel per above instructions
- * to make the saved environment consistent with the flash.
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"kernstart=0x20000\0" \
-	"kernarea=0x500000\0" \
-	"uget=tftp u-boot.ldr\0" \
-	"kget=tftp uImage\0" \
-	"usave=sf probe 2; " \
-		"sf erase 0 $(kernstart); " \
-		"sf write $(fileaddr) 0 $(filesize)\0" \
-	"ksave=sf probe 2; " \
-		"saveenv; " \
-		"echo Now patiently wait for the prompt...; " \
-		"sf erase $(kernstart) $(kernarea); " \
-		"sf write $(fileaddr) $(kernstart) $(filesize)\0" \
-	"sfboot=sf probe 2; " \
-		"sf read $(loadaddr) $(kernstart) $(filesize); " \
-		"run addip; bootm\0" \
-	"addip=setenv bootargs $(bootargs) " \
-	"ip=$(ipaddr):$(serverip):$(gatewayip):" \
-		"$(netmask):$(hostname):eth0:off\0"
-
-/*
- * Soft I2C settings (BF561 does not have hard I2C)
- * PF12,13 on SPI connector 0.
- */
-#ifdef CONFIG_SYS_I2C_SOFT
-# define CONFIG_SOFT_I2C_GPIO_SCL	GPIO_PF12
-# define CONFIG_SOFT_I2C_GPIO_SDA	GPIO_PF13
-# define CONFIG_SYS_I2C_SPEED		50000
-# define CONFIG_SYS_I2C_SLAVE		0xFE
-#endif
-
-#undef CONFIG_CMD_JFFS2
-
-#endif
diff --git a/include/configs/br4.h b/include/configs/br4.h
deleted file mode 100644
index 8a7a359..0000000
--- a/include/configs/br4.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * U-Boot - Configuration file for BR4 Appliance
- *
- * based on bf537-stamp.h
- * Copyright (c) Switchfin Org. <dpn@switchfin.org>
- */
-
-#ifndef __CONFIG_BR4_H__
-#define __CONFIG_BR4_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf537-0.3
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			24
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	10
-#define CONFIG_MEM_SIZE		64
-
-#define CONFIG_EBIU_SDRRC_VAL	0x306
-#define CONFIG_EBIU_SDGCTL_VAL	0x8091998d
-
-#define CONFIG_EBIU_AMGCTL_VAL	0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_BFIN_MAC
-#define CONFIG_NETCONSOLE
-#endif
-#define CONFIG_HOSTNAME		br4
-#define CONFIG_TFTP_BLOCKSIZE	4404
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x10000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * NAND Settings
- */
-#define CONFIG_NAND_PLAT
-#define CONFIG_SYS_NAND_BASE		0x20000000
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
-#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
-#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_WRITE(addr, cmd) \
-	do { \
-		bfin_write8(addr, cmd); \
-		SSYNC(); \
-	} while (0)
-
-#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
-#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF9
-
-/*
- * Misc Settings
- */
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BOOTCOMMAND	"run nandboot"
-#define CONFIG_LOADADDR		0x2000000
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-/*
- * Overwrite some settings defined in bfin_adi_common.h
- */
-#undef NAND_ENV_SETTINGS
-#define NAND_ENV_SETTINGS \
-	"nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
-	"nandboot=" \
-		"nand read $(loadaddr) 0x0 0x900000;" \
-		"run nandargs;" \
-		"bootm" \
-		"\0"
-
-#endif
diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h
deleted file mode 100644
index 3b6f9ba..0000000
--- a/include/configs/cm-bf527.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * U-Boot - Configuration file for CM-BF527 board
- */
-
-#ifndef __CONFIG_CM_BF527_H__
-#define __CONFIG_CM_BF527_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf527-0.0
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			21
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			4
-
-/* Decrease core voltage */
-#define CONFIG_VR_CTL_VAL (VLEV_120 | CLKBUFOE | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	9
-#define CONFIG_MEM_SIZE		32
-
-#define CONFIG_EBIU_SDRRC_VAL	0x3f8
-#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
-
-/*
- * NAND Settings
- * (can't be used sametime as ethernet)
- */
-/* #define CONFIG_BFIN_NFC */
-#ifdef CONFIG_BFIN_NFC
-#define CONFIG_BFIN_NFC_CTL_VAL	0x0033
-#define CONFIG_SYS_NAND_BASE		0 /* not actually used */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_CMD_NAND
-#endif
-
-/*
- * Network Settings
- */
-#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
-    !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_BFIN_MAC
-#define CONFIG_RMII
-#define CONFIG_NETCONSOLE	1
-#endif
-#define CONFIG_HOSTNAME		cm-bf527
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT 	67
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		0x20008000
-#define CONFIG_ENV_OFFSET	0x8000
-#define CONFIG_ENV_SIZE		0x8000
-#define CONFIG_ENV_SECT_SIZE	0x8000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BOOTCOMMAND	"run flashboot"
-#define FLASHBOOT_ENV_SETTINGS \
-	"flashboot=flread 20040000 1000000 300000;" \
-	"bootm 0x1000000\0"
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h
deleted file mode 100644
index 01a3579..0000000
--- a/include/configs/cm-bf533.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * U-Boot - Configuration file for CM-BF533 board
- */
-
-#ifndef __CONFIG_CM_BF533_H__
-#define __CONFIG_CM_BF533_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf533-0.3
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			22
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			5
-
-/* Decrease core voltage */
-#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	9
-#define CONFIG_MEM_SIZE		32
-
-#define CONFIG_EBIU_SDRRC_VAL	((((CONFIG_SCLK_HZ / 1000) * 64) / 8192) - (7 + 2))
-#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3)
-
-#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_SMC91111	1
-#define CONFIG_SMC91111_BASE	0x20200300
-#define CONFIG_HOSTNAME		cm-bf533
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	16
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET	0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_SIZE		0x10000
-
-/*
- * Misc Settings
- */
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BOOTCOMMAND	"run flashboot"
-#define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
deleted file mode 100644
index d9f91b5..0000000
--- a/include/configs/cm-bf537e.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * U-Boot - Configuration file for CM-BF537E board
- */
-
-#ifndef __CONFIG_CM_BF537E_H__
-#define __CONFIG_CM_BF537E_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			21
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			4
-
-/* Decrease core voltage */
-#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	9
-#define CONFIG_MEM_SIZE		32
-
-#define CONFIG_EBIU_SDRRC_VAL	0x3f8
-#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_BFIN_MAC
-#define CONFIG_SMC911X		1
-#define CONFIG_SMC911X_BASE	0x20308000
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_NETCONSOLE	1
-#endif
-#define CONFIG_HOSTNAME		cm-bf537e
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	35
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET	0x8000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE	0x8000
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
-	arch/blackfin/lib/built-in.o (.text*); \
-	arch/blackfin/cpu/built-in.o (.text*); \
-	. = DEFINED(env_offset) ? env_offset : .; \
-	common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * SPI_MMC Settings
- */
-#define CONFIG_MMC_SPI
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BOOTCOMMAND	"run flashboot"
-#define FLASHBOOT_ENV_SETTINGS \
-	"flashboot=flread 20040000 1000000 3c0000;" \
-	"bootm 0x1000000\0"
-#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
deleted file mode 100644
index af11ebe..0000000
--- a/include/configs/cm-bf537u.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * U-Boot - Configuration file for CM-BF537U board
- */
-
-#ifndef __CONFIG_CM_BF537U_H__
-#define __CONFIG_CM_BF537U_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			30000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			18
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			5
-/* Core voltage */
-#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	9
-#define CONFIG_MEM_SIZE		32
-
-#define CONFIG_EBIU_SDRRC_VAL	0x3f8
-#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_SMC911X		1
-#define CONFIG_SMC911X_BASE	0x20308000
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_NETCONSOLE	1
-#endif
-#define CONFIG_HOSTNAME		cm-bf537u
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	35
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET	0x8000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE	0x8000
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
-	arch/blackfin/lib/built-in.o (.text*); \
-	arch/blackfin/cpu/built-in.o (.text*); \
-	. = DEFINED(env_offset) ? env_offset : .; \
-	common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * SPI_MMC Settings
- */
-#define CONFIG_MMC_SPI
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BOOTCOMMAND	"run flashboot"
-#define FLASHBOOT_ENV_SETTINGS \
-	"flashboot=flread 20040000 1000000 300000;" \
-	"bootm 0x1000000\0"
-#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
deleted file mode 100644
index 10e8efd..0000000
--- a/include/configs/cm-bf548.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * U-Boot - Configuration file for cm-bf548 board
- */
-
-#ifndef __CONFIG_CM_BF548_H__
-#define __CONFIG_CM_BF548_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf548-0.0
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			21
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			4
-
-/* Decrease core voltage */
-#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	10
-#define CONFIG_MEM_SIZE		64
-
-#define CONFIG_EBIU_DDRCTL0_VAL	0x218A83FE
-#define CONFIG_EBIU_DDRCTL1_VAL	0x20022222
-#define CONFIG_EBIU_DDRCTL2_VAL	0x00000021
-
-/* Default bank mapping:
- *	Async Bank 0 - 32MB Burst Flash
- *	Async Bank 1 - Ethernet
- *	Async Bank 2 - Nothing
- *	Async Bank 3 - Nothing
- */
-#define CONFIG_EBIU_AMGCTL_VAL	0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
-#define CONFIG_EBIU_FCTL_VAL	(BCLK_4)
-#define CONFIG_EBIU_MODE_VAL	(B0MODE_FLASH)
-
-#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_SMC911X	1
-#define CONFIG_SMC911X_BASE	0x24000000
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_HOSTNAME		cm-bf548
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	259
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		0x20008000
-#define CONFIG_ENV_OFFSET	0x8000
-#define CONFIG_ENV_SIZE		0x8000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Misc Settings
- */
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	1
-#define CONFIG_BOOTCOMMAND	"run flashboot"
-#define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-
-#define CONFIG_ADI_GPIO2
-
-#ifndef __ADSPBF542__
-/* Don't waste time transferring a logo over the UART */
-# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
-#  define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h>
-# endif
-# define CONFIG_DEB_DMA_URGENT
-#endif
-
-/* Define if want to do post memory test */
-#undef CONFIG_POST
-#ifdef CONFIG_POST
-#define FLASH_START_POST_BLOCK 11       /* Should > = 11 */
-#define FLASH_END_POST_BLOCK   71       /* Should < = 71 */
-#endif
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h
deleted file mode 100644
index ac1646c..0000000
--- a/include/configs/cm-bf561.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * U-Boot - Configuration file for CM-BF561 board
- */
-
-#ifndef __CONFIG_CM_BF561_H__
-#define __CONFIG_CM_BF561_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf561-0.3
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			20
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			5
-
-/* Decrease core voltage */
-#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	9
-#define CONFIG_MEM_SIZE		64
-
-#define CONFIG_EBIU_SDRRC_VAL	((((CONFIG_SCLK_HZ / 1000) * 64) / 4096) - (7 + 2))
-#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3)
-
-#define CONFIG_EBIU_AMGCTL_VAL	(CDPRIO | B3_PEN | B2_PEN | B1_PEN | B0_PEN | AMBEN_ALL | AMCKEN)
-#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_SMC911X		1
-#define CONFIG_SMC911X_BASE	0x24008000 /* AMS1 */
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_HOSTNAME		cm-bf561
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	67
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET	0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * Misc Settings
- */
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BOOTCOMMAND	"run flashboot"
-#define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 45511be..14b25d4 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -237,7 +237,6 @@
 #define CONFIG_SERIAL_TAG
 
 /* misc */
-#define CONFIG_STACKSIZE			(128 * 1024)
 #define CONFIG_SYS_MALLOC_LEN			(10 * 1024 * 1024)
 #define CONFIG_MISC_INIT_R
 
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index 2c9c014..87d2012 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -136,8 +136,6 @@
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 #define CONFIG_SYS_HZ			1000
 
-#define CONFIG_STACKSIZE		SZ_128K
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 888899e..73b43bd 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -150,12 +150,6 @@
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_CMDLINE_EDITING
 
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
-
 /* Physical memory map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			(0x80000000)
diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h
new file mode 100644
index 0000000..add5f90
--- /dev/null
+++ b/include/configs/controlcenterdc.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_CONTROLCENTERDC_H
+#define _CONFIG_CONTROLCENTERDC_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_CUSTOMER_BOARD_SUPPORT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_LAST_STAGE_INIT
+#define CONFIG_SPL_BOARD_INIT
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define	CONFIG_SYS_TEXT_BASE	0x00800000
+
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+#define CONFIG_LOADADDR 		1000000
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_SPI
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_BUS		1
+#define CONFIG_SF_DEFAULT_SPEED		1000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+
+/*
+ * SDIO/MMC Card Configuration
+ */
+#define CONFIG_SYS_MMC_BASE		MVEBU_SDIO_BASE
+
+/*
+ * SATA/SCSI/AHCI configuration
+ */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	2
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					 CONFIG_SYS_SCSI_MAX_LUN)
+
+/* Additional FS support/configuration */
+#define CONFIG_SUPPORT_VFAT
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS		1
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
+
+#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+/*
+ * Software (bit-bang) MII driver configuration
+ */
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
+/* SPL */
+/*
+ * Select the boot device here
+ *
+ * Currently supported are:
+ * SPL_BOOT_SPI_NOR_FLASH	- Booting via SPI NOR flash
+ * SPL_BOOT_SDIO_MMC_CARD	- Booting via SDIO/MMC card (partition 1)
+ */
+#define SPL_BOOT_SPI_NOR_FLASH		1
+#define SPL_BOOT_SDIO_MMC_CARD		2
+#define CONFIG_SPL_BOOT_DEVICE		SPL_BOOT_SPI_NOR_FLASH
+
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_SIZE			(160 << 10)
+
+#if defined(CONFIG_SECURED_MODE_IMAGE)
+#define CONFIG_SPL_TEXT_BASE		0x40002614
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_SIZE - 0x2614)
+#else
+#define CONFIG_SPL_TEXT_BASE		0x40000030
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_SIZE - 0x30)
+#endif
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((212 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x30000
+#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
+#endif
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
+/* SPL related MMC defines */
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
+#define CONFIG_SYS_MMC_U_BOOT_OFFS		(168 << 10)
+#define CONFIG_SYS_U_BOOT_OFFS			CONFIG_SYS_MMC_U_BOOT_OFFS
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	(CONFIG_SYS_U_BOOT_OFFS / 512)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER	0x00180000	/* in SDRAM */
+#endif
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_HOSTNAME		ccdc
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"ccdc.img"
+
+#define CONFIG_PREBOOT		/* enable preboot variable */
+
+#define CONFIG_EXTRA_ENV_SETTINGS						\
+	"netdev=eth1\0"						\
+	"consoledev=ttyS1\0"							\
+	"u-boot=u-boot.bin\0"							\
+	"bootfile_addr=1000000\0"						\
+	"keyprogram_addr=3000000\0"						\
+	"keyprogram_file=keyprogram.img\0"						\
+	"fdtfile=controlcenterdc.dtb\0"						\
+	"load=tftpboot ${loadaddr} ${u-boot}\0"					\
+	"mmcdev=0:2\0"								\
+	"update=sf probe 1:0;"							\
+		" sf erase 0 +${filesize};"					\
+		" sf write ${fileaddr} 0 ${filesize}\0"				\
+	"upd=run load update\0"							\
+	"fdt_high=0x10000000\0"							\
+	"initrd_high=0x10000000\0"						\
+	"loadkeyprogram=tpm flush_keys;"					\
+		" mmc rescan;"							\
+		" ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\
+		" source ${keyprogram_addr}:script@1\0"				\
+	"gpio1=gpio@22_25\0"							\
+	"gpio2=A29\0"								\
+	"blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 "	\
+		  "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0"	\
+	"bootfail=for i in ${blinkseq}; do"					\
+		" if test $i -eq 0; then"					\
+		" gpio clear ${gpio1}; gpio set ${gpio2};"			\
+		" elif test $i -eq 1; then"					\
+		" gpio clear ${gpio1}; gpio clear ${gpio2};"			\
+		" elif test $i -eq 2; then"					\
+		" gpio set ${gpio1}; gpio set ${gpio2};"			\
+		" else;"							\
+		" gpio clear ${gpio1}; gpio set ${gpio2};"			\
+		" fi; sleep 0.12; done\0"
+
+#define CONFIG_NFSBOOTCOMMAND								\
+	"setenv bootargs root=/dev/nfs rw "						\
+	"nfsroot=${serverip}:${rootpath} "						\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off "	\
+	"console=${consoledev},${baudrate} ${othbootargs}; "				\
+	"tftpboot ${bootfile_addr} ${bootfile}; "						\
+	"bootm ${bootfile_addr}"
+
+#define CONFIG_MMCBOOTCOMMAND					\
+	"setenv bootargs root=/dev/mmcblk0p3 rw rootwait "	\
+	"console=${consoledev},${baudrate} ${othbootargs}; "	\
+	"ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; "	\
+	"bootm ${bootfile_addr}"
+
+#define CONFIG_BOOTCOMMAND			\
+	"if env exists keyprogram; then;"	\
+	" setenv keyprogram; run nfsboot;"	\
+        " fi;"					\
+        " run dobootfail"
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#endif /* _CONFIG_CONTROLCENTERDC_H */
diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h
deleted file mode 100644
index 1690dda..0000000
--- a/include/configs/dnp5370.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * U-Boot - Configuration file for SSV DNP5370 board
- */
-
-#ifndef __CONFIG_DNP5370_H__
-#define __CONFIG_DNP5370_H__
-
-/* this must come first */
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU       bf537-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-#define CONFIG_CLKIN_HZ                 25000000
-#define CONFIG_CLKIN_HALF               0
-#define CONFIG_PLL_BYPASS               0
-#define CONFIG_VCO_MULT                 24
-#define CONFIG_CCLK_DIV                 1
-#define CONFIG_SCLK_DIV                 5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH     9
-#define CONFIG_MEM_SIZE         32
-
-#define CONFIG_EBIU_SDRRC_VAL   0x03a0
-#define CONFIG_EBIU_SDBCTL_VAL  0x0013
-#define CONFIG_EBIU_SDGCTL_VAL  0x8091998d
-
-#define CONFIG_EBIU_AMGCTL_VAL  0xF7
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN  (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN   (128 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define CONFIG_ROOTPATH        "/romfs"
-
-#define CONFIG_BFIN_MAC         1
-#define CONFIG_PHY_ADDR         0
-#define CONFIG_RMII             1
-
-#endif
-
-/*
- * Flash Settings
- *
- * Only 3 MB of the 4 MB NOR flash are addressable.
- * But limiting the flash size does not seem to work.
- * It seems the CFI detection has precedence.
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE       0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS  1
-#define CONFIG_SYS_MAX_FLASH_SECT   71 /* (M29W320EB) */
-
-/* 512k reserved for u-boot */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH     1
-#define CONFIG_ENV_ADDR       0x20004000
-#define CONFIG_ENV_SIZE       0x00002000
-#define CONFIG_ENV_SECT_SIZE  0x00002000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_OFFSET     0x00004000 /* (CONFIG_ENV_ADDR - CONFIG_FLASH_BASE) */
-
-#define ENV_IS_EMBEDDED
-#define LDS_BOARD_TEXT \
-	arch/blackfin/lib/built-in.o (.text*); \
-	arch/blackfin/cpu/built-in.o (.text*); \
-	. = DEFINED(env_offset) ? env_offset : .; \
-	common/env_embedded.o (.text*);
-
-/*
- * Misc Settings
- */
-#define CONFIG_CMD_STRINGS
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_SYS_LONGHELP
-
-/* This disables the hardware watchdog (not inside the bfin) */
-#define CONFIG_DNP5370_EXT_WD_DISABLE 1
-
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BFIN_SERIAL
-#define CONFIG_BOOTCOMMAND  "bootm 0x20030000"
-#define CONFIG_BOOTARGS     "console=ttyBF0,115200 root=/dev/mtdblock3 rootfstype=ext2"
-
-/* Convenience commands to update Linux in NOR flash */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"fetchme=tftpboot 0x01000000 uImage;" \
-		"iminfo\0" \
-	"flashme=protect off 0x20030000 0x2003ffff;" \
-		"erase 0x20030000 0x202effff;" \
-		"cp.b 0x01000000 0x20030000 0x2c0000\0" \
-	"runme=bootm 0x01000000\0"
-
-#endif
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 43e74a2..7d6f7ff 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -122,11 +122,6 @@
 #define CONFIG_SF_DEFAULT_MODE                 SPI_MODE_0
 #define CONFIG_QSPI_QUAD_SUPPORT
 
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_SPI
-#undef CONFIG_DM_SPI_FLASH
-#endif
-
 /*
  * Default to using SPI for environment, etc.
  * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
@@ -260,8 +255,4 @@
 #endif
 #endif  /* NOR support */
 
-/* EEPROM */
-#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
-#define CONFIG_EEPROM_BUS_ADDRESS 0
-
 #endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
index 99f0dae..f012af5 100644
--- a/include/configs/edb93xx.h
+++ b/include/configs/edb93xx.h
@@ -74,7 +74,6 @@
 #define CONFIG_EP93XX		1		/* This is a Cirrus Logic 93xx SoC */
 
 #define CONFIG_SYS_CLK_FREQ	14745600	/* EP93xx has a 14.7456 clock */
-#undef CONFIG_USE_IRQ				/* Don't need IRQ/FIQ */
 
 /* Monitor configuration */
 #undef CONFIG_CMD_DATE
@@ -161,12 +160,6 @@
 
 /* Run-time memory allocatons */
 #define CONFIG_SYS_GBL_DATA_SIZE	128
-#define CONFIG_STACKSIZE		(128 * 1024)
-
-#if defined(CONFIG_USE_IRQ)
-#define CONFIG_STACKSIZE_IRQ	(4 * 1024)
-#define CONFIG_STACKSIZE_FIQ	(4 * 1024)
-#endif
 
 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
 
diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h
index afb5b73..0848397 100644
--- a/include/configs/el6x_common.h
+++ b/include/configs/el6x_common.h
@@ -99,8 +99,6 @@
 #define CONFIG_SYS_MEMTEST_END         0x10800000
 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
 
-#define CONFIG_STACKSIZE               (128 * 1024)
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS           1
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index 48c9e0b..658f4d9 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -76,8 +76,6 @@
 #define CONFIG_SYS_MEMTEST_END         0x10010000
 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
 
-#define CONFIG_STACKSIZE               (128 * 1024)
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS           1
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/evb_rk3288.h b/include/configs/evb_rk3288.h
index 6a068bb..bbd54a1 100644
--- a/include/configs/evb_rk3288.h
+++ b/include/configs/evb_rk3288.h
@@ -11,7 +11,7 @@
 #include <configs/rk3288_common.h>
 
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_DEV 0
 
 #define CONFIG_SYS_WHITE_ON_BLACK
 
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index b4f7530..ade66a4 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -23,7 +23,7 @@
 
 /* input clock of PLL: 24MHz input clock */
 #define CONFIG_SYS_CLK_FREQ		24000000
-#define CONFIG_TIMER_CLK_FREQ		CONFIG_SYS_CLK_FREQ
+#define COUNTER_FREQUENCY		CONFIG_SYS_CLK_FREQ
 
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
diff --git a/include/configs/fennec_rk3288.h b/include/configs/fennec_rk3288.h
index 6a068bb..bbd54a1 100644
--- a/include/configs/fennec_rk3288.h
+++ b/include/configs/fennec_rk3288.h
@@ -11,7 +11,7 @@
 #include <configs/rk3288_common.h>
 
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_DEV 0
 
 #define CONFIG_SYS_WHITE_ON_BLACK
 
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index f86e20c..43b1fb0 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -260,7 +260,6 @@
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
 
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE               (128 * 1024)
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS           1
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
deleted file mode 100644
index 2c8adab..0000000
--- a/include/configs/gr_cpci_ax2000.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/* Configuration header file for Gaisler GR-CPCI-AX2000
- * AX board. Note that since the AX is removable the configuration
- * for this board must be edited below.
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H__
-#define __CONFIG_H__
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_CPCI_AX2000	1	/* ... on GR-CPCI-AX2000 board */
-
-#define CONFIG_LEON_RAM_SRAM 1
-#define CONFIG_LEON_RAM_SDRAM 2
-#define CONFIG_LEON_RAM_SDRAM_NOSRAM 3
-
-/* Select Memory to run from
- *
- * SRAM          - UBoot is run in SRAM, SRAM-0x40000000, SDRAM-0x60000000
- * SDRAM         - UBoot is run in SDRAM, SRAM-0x40000000 and SDRAM-0x60000000
- * SDRAM_NOSRAM  - UBoot is run in SDRAM, SRAM not available, SDRAM at 0x40000000
- *
- * Note, if Linux is to be used, SDRAM or SDRAM_NOSRAM is required since
- * it doesn't fit into the 4Mb SRAM.
- *
- * SRAM is default since it will work for all systems, however will not
- * be able to boot linux.
- */
-#define CONFIG_LEON_RAM_SELECT CONFIG_LEON_RAM_SRAM
-
-/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ	20000000	/* 20MHz */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* Partitions */
-
-/*
- * Supported commands
- */
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_IRQ
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS_BASE					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw "	\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"getkernel=tftpboot $(scratch) $(bootfile)\0" \
-	"bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.206:192.168.0.20:192.168.0.1:255.255.255.0:ax2000:eth0\0"
-
-#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SRAM
-#define CONFIG_EXTRA_ENV_SETTINGS_SELECT \
-	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"scratch=40200000\0"					\
-	""
-#elif CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM
-#define CONFIG_EXTRA_ENV_SETTINGS_SELECT \
-	"net_nfs=tftp 60000000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"scratch=60800000\0"					\
-	""
-#else
-/* More than 4Mb is assumed when running from SDRAM */
-#define CONFIG_EXTRA_ENV_SETTINGS_SELECT \
-	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"scratch=40800000\0"					\
-	""
-#endif
-
-#define	CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_SETTINGS_BASE CONFIG_EXTRA_ENV_SETTINGS_SELECT
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.20
-#define CONFIG_IPADDR 192.168.0.206
-#define CONFIG_ROOTPATH "/export/rootfs"
-#define CONFIG_HOSTNAME  ax2000
-#define CONFIG_BOOTFILE "/uImage"
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/* Memory MAP
- *
- *  Flash:
- *  |--------------------------------|
- *  | 0x00000000 Text & Data & BSS   | *
- *  |            for Monitor         | *
- *  | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
- *  | UNUSED / Growth                | * 256kb
- *  |--------------------------------|
- *  | 0x00050000 Base custom area    | *
- *  |            kernel / FS         | *
- *  |                                | * Rest of Flash
- *  |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
- *  | END-0x00008000 Environment     | * 32kb
- *  |--------------------------------|
- *
- *
- *
- *  Main Memory (4Mb SRAM or XMb SDRAM):
- *  |--------------------------------|
- *  | UNUSED / scratch area          |
- *  |                                |
- *  |                                |
- *  |                                |
- *  |                                |
- *  |--------------------------------|
- *  | Monitor .Text / .DATA / .BSS   | * 256kb
- *  | Relocated!                     | *
- *  |--------------------------------|
- *  | Monitor Malloc                 | * 128kb (contains relocated environment)
- *  |--------------------------------|
- *  | Monitor/kernel STACK           | * 64kb
- *  |--------------------------------|
- *  | Page Table for MMU systems     | * 2k
- *  |--------------------------------|
- *  | PROM Code accessed from Linux  | * 6kb-128b
- *  |--------------------------------|
- *  | Global data (avail from kernel)| * 128b
- *  |--------------------------------|
- *
- */
-
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at  0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB
- *               0xFE000000 for 32 MB
- *               0xFF000000 for 16 MB
- *               0xFF800000 for  8 MB
- */
-#define CONFIG_SYS_FLASH_BASE		0x00000000
-#define CONFIG_SYS_FLASH_SIZE		0x00800000
-
-#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 128 KB sectors */
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
-
-/*** CFI CONFIG ***/
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-/* Bypass cache when reading regs from flash memory */
-#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
-/* Buffered writes (32byte/go) instead of single accesses */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/*
- * Environment settings
- */
-/*#define CONFIG_ENV_IS_NOWHERE 1*/
-#define CONFIG_ENV_IS_IN_FLASH	1
-/* CONFIG_ENV_ADDR need to be at sector boundary */
-#define CONFIG_ENV_SIZE		0x8000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- *
- * Always 4Mb SRAM available
- * SDRAM module may be available on 0x60000000, SDRAM
- * is configured as if a 128Mb SDRAM module is available.
- */
-
-#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#else
-#define CONFIG_SYS_SDRAM_BASE		0x60000000
-#endif
-
-#define CONFIG_SYS_SDRAM_SIZE		0x08000000
-#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
-
-/* 4Mb SRAM available */
-#if CONFIG_LEON_RAM_SELECT != CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CONFIG_SYS_SRAM_BASE 0x40000000
-#define CONFIG_SYS_SRAM_SIZE 0x400000
-#define CONFIG_SYS_SRAM_END  (CONFIG_SYS_SRAM_BASE+CONFIG_SYS_SRAM_SIZE)
-#endif
-
-/* Select RAM used to run U-BOOT from... */
-#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SRAM
-#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SRAM_SIZE
-#define CONFIG_SYS_RAM_END CONFIG_SYS_SRAM_END
-#else
-#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
-#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
-#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
-
-/* relocated monitor area */
-#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
-#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
-
-/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
-
-/*
- * Ethernet configuration uses on board SMC91C111
- */
-#define CONFIG_SMC91111          1
-#define CONFIG_SMC91111_BASE		0x20000300	/* chip select 3         */
-#define CONFIG_SMC_USE_32_BIT		1	/* 32 bit bus  */
-#undef  CONFIG_SMC_91111_EXT_PHY	/* we use internal phy   */
-/*#define CONFIG_SHOW_ACTIVITY*/
-#define CONFIG_NET_RETRY_COUNT		10	/* # of retries          */
-
-#define CONFIG_PHY_ADDR	 0x00
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-/*
- * Various low-level settings
- */
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00005000
-
-/***** Gaisler GRLIB IP-Cores Config ********/
-
-#define CONFIG_SYS_GRLIB_SDRAM    0
-
-/* No SDRAM Configuration */
-#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
-
-/* See, GRLIB Docs (grip.pdf) on how to set up
- * These the memory controller registers.
- */
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1   (0x10f800ff | (1<<11))
-#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2   0x82206000
-#else
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2   0x82205260
-#endif
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3   0x0809a000
-
-/* GRLIB FT-MCTRL configuration */
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1   (0x10f800ff | (1<<11))
-#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2   0x82206000
-#else
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2   0x82205260
-#endif
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3   0x0809a000
-
-/* no DDR controller */
-#undef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
-
-/* no DDR2 Controller */
-#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
-
-/* default kernel command line */
-#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
-
-#endif				/* __CONFIG_H */
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
deleted file mode 100644
index 2edb1b0..0000000
--- a/include/configs/gr_ep2s60.h
+++ /dev/null
@@ -1,304 +0,0 @@
-/* Configuration header file for Gaisler Research AB's Template
- * design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS
- * Development board Stratix II edition, with the FPGA device
- * EP2S60.
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H__
-#define __CONFIG_H__
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* Altera NIOS Development board, Stratix II board */
-#define CONFIG_GR_EP2S60	1
-
-/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ	96000000	/* 96MHz */
-
-/* Define this is the GR-2S60-MEZZ mezzanine is available and you
- * want to use the USB and GRETH functionality of the board
- */
-#undef GR_2S60_MEZZ
-
-#ifdef GR_2S60_MEZZ
-#define USE_GRETH 1
-#define USE_GRUSB 1
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* Partitions */
-
-/*
- * Supported commands
- */
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_IRQ
-
-/* USB support */
-#if USE_GRUSB
-#define CONFIG_USB_UHCI
-/* Enable needed helper functions */
-#endif
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw "	\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"scratch=40800000\0"					\
-	"getkernel=tftpboot $(scratch) $(bootfile)\0" \
-	"bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \
-	""
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.20
-#define CONFIG_IPADDR 192.168.0.207
-#define CONFIG_ROOTPATH "/export/rootfs"
-#define CONFIG_HOSTNAME  ml401
-#define CONFIG_BOOTFILE "/uImage"
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/* Memory MAP
- *
- *  Flash:
- *  |--------------------------------|
- *  | 0x00000000 Text & Data & BSS   | *
- *  |            for Monitor         | *
- *  | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
- *  | UNUSED / Growth                | * 256kb
- *  |--------------------------------|
- *  | 0x00050000 Base custom area    | *
- *  |            kernel / FS         | *
- *  |                                | * Rest of Flash
- *  |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
- *  | END-0x00008000 Environment     | * 32kb
- *  |--------------------------------|
- *
- *
- *
- *  Main Memory:
- *  |--------------------------------|
- *  | UNUSED / scratch area          |
- *  |                                |
- *  |                                |
- *  |                                |
- *  |                                |
- *  |--------------------------------|
- *  | Monitor .Text / .DATA / .BSS   | * 512kb
- *  | Relocated!                     | *
- *  |--------------------------------|
- *  | Monitor Malloc                 | * 128kb (contains relocated environment)
- *  |--------------------------------|
- *  | Monitor/kernel STACK           | * 64kb
- *  |--------------------------------|
- *  | Page Table for MMU systems     | * 2k
- *  |--------------------------------|
- *  | PROM Code accessed from Linux  | * 6kb-128b
- *  |--------------------------------|
- *  | Global data (avail from kernel)| * 128b
- *  |--------------------------------|
- *
- */
-
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at  0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB
- *               0xFE000000 for 32 MB
- *               0xFF000000 for 16 MB
- *               0xFF800000 for  8 MB
- */
-#define CONFIG_SYS_FLASH_BASE		0x00000000
-#define CONFIG_SYS_FLASH_SIZE		0x00400000	/* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */
-
-#define PHYS_FLASH_SECT_SIZE	0x00010000	/* 64 KB sectors */
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
-
-/*** CFI CONFIG ***/
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-/* Bypass cache when reading regs from flash memory */
-#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
-/* Buffered writes (32byte/go) instead of single accesses */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/*
- * Environment settings
- */
-/*#define CONFIG_ENV_IS_NOWHERE 1*/
-#define CONFIG_ENV_IS_IN_FLASH	1
-/* CONFIG_ENV_ADDR need to be at sector boundary */
-#define CONFIG_ENV_SIZE		0x8000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_SDRAM_SIZE		0x02000000
-#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
-
-/* no SRAM available */
-#undef CONFIG_SYS_SRAM_BASE
-#undef CONFIG_SYS_SRAM_SIZE
-
-#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
-#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor   */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
-#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
-
-/* relocated monitor area */
-#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
-#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
-
-/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
-
-/*
- * Ethernet configuration uses on board SMC91C111, however if a mezzanine
- * with a PHY is attached the GRETH can be used on this board.
- * Define USE_GRETH in order to use the mezzanine provided PHY with the
- * onchip GRETH network MAC, note that this is not supported by the
- * template design.
- */
-#ifndef USE_GRETH
-
-/* USE SMC91C111 MAC */
-#define CONFIG_SMC91111          1
-#define CONFIG_SMC91111_BASE		0x20000300	/* chip select 3         */
-#define CONFIG_SMC_USE_32_BIT		1	/* 32 bit bus  */
-#undef  CONFIG_SMC_91111_EXT_PHY	/* we use internal phy   */
-/*#define CONFIG_SHOW_ACTIVITY*/
-#define CONFIG_NET_RETRY_COUNT		10	/* # of retries          */
-
-#else
-
-/* USE GRETH Ethernet Driver */
-#define CONFIG_GRETH	1
-#endif
-
-#define CONFIG_PHY_ADDR	 0x00
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00005000
-
-/***** Gaisler GRLIB IP-Cores Config ********/
-
-#define CONFIG_SYS_GRLIB_SDRAM    0
-
-/* No SDRAM Configuration */
-#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
-
-/* See, GRLIB Docs (grip.pdf) on how to set up
- * These the memory controller registers.
- */
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1  (0x10f800ff | (1<<11))
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2  0x00000000
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3  0x00000000
-
-/* GRLIB FT-MCTRL configuration */
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1  (0x10f800ff | (1<<11))
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2  0x00000000
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3  0x00000000
-
-/* DDR controller */
-#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
-#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL  0xa900830a
-
-/* no DDR2 Controller */
-#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
-
-/* default kernel command line */
-#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
-
-#endif				/* __CONFIG_H */
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
deleted file mode 100644
index b8ac7d1..0000000
--- a/include/configs/gr_xc3s_1500.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/* Configuration header file for Gaisler GR-XC3S-1500
- * spartan board.
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H__
-#define __CONFIG_H__
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_GRXC3S1500	1	/* ... on GR-XC3S-1500 board */
-
-/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ	40000000	/* 40MHz */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* Partitions */
-
-/*
- * Supported commands
- */
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_IRQ
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw "	\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"scratch=40200000\0"					\
-	"getkernel=tftpboot $(scratch) $(bootfile)\0" \
-	"bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.206:192.168.0.20:192.168.0.1:255.255.255.0:grxc3s1500_daniel:eth0\0" \
-	""
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.20
-#define CONFIG_IPADDR 192.168.0.206
-#define CONFIG_ROOTPATH "/export/rootfs"
-#define CONFIG_HOSTNAME  grxc3s1500
-#define CONFIG_BOOTFILE "/uImage"
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/* Memory MAP
- *
- *  Flash:
- *  |--------------------------------|
- *  | 0x00000000 Text & Data & BSS   | *
- *  |            for Monitor         | *
- *  | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
- *  | UNUSED / Growth                | * 256kb
- *  |--------------------------------|
- *  | 0x00050000 Base custom area    | *
- *  |            kernel / FS         | *
- *  |                                | * Rest of Flash
- *  |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
- *  | END-0x00008000 Environment     | * 32kb
- *  |--------------------------------|
- *
- *
- *
- *  Main Memory:
- *  |--------------------------------|
- *  | UNUSED / scratch area          |
- *  |                                |
- *  |                                |
- *  |                                |
- *  |                                |
- *  |--------------------------------|
- *  | Monitor .Text / .DATA / .BSS   | * 256kb
- *  | Relocated!                     | *
- *  |--------------------------------|
- *  | Monitor Malloc                 | * 128kb (contains relocated environment)
- *  |--------------------------------|
- *  | Monitor/kernel STACK           | * 64kb
- *  |--------------------------------|
- *  | Page Table for MMU systems     | * 2k
- *  |--------------------------------|
- *  | PROM Code accessed from Linux  | * 6kb-128b
- *  |--------------------------------|
- *  | Global data (avail from kernel)| * 128b
- *  |--------------------------------|
- *
- */
-
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at  0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB
- *               0xFE000000 for 32 MB
- *               0xFF000000 for 16 MB
- *               0xFF800000 for  8 MB
- */
-#define CONFIG_SYS_FLASH_BASE		0x00000000
-#define CONFIG_SYS_FLASH_SIZE		0x00800000
-
-#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 128 KB sectors */
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
-
-/*** CFI CONFIG ***/
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-/* Bypass cache when reading regs from flash memory */
-#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
-/* Buffered writes (32byte/go) instead of single accesses */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/*
- * Environment settings
- */
-/*#define CONFIG_ENV_IS_NOWHERE 1*/
-#define CONFIG_ENV_IS_IN_FLASH	1
-/* CONFIG_ENV_ADDR need to be at sector boundary */
-#define CONFIG_ENV_SIZE		0x8000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_SDRAM_SIZE		0x4000000
-#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
-
-/* no SRAM available */
-#undef CONFIG_SYS_SRAM_BASE
-#undef CONFIG_SYS_SRAM_SIZE
-
-/* Always Run U-Boot from SDRAM */
-#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
-#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
-#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
-
-/* relocated monitor area */
-#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
-#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
-
-/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_GRETH	1
-
-#define CONFIG_PHY_ADDR	 0x00
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-/*
- * Various low-level settings
- */
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00005000
-
-/***** Gaisler GRLIB IP-Cores Config ********/
-
-#define CONFIG_SYS_GRLIB_SDRAM    0
-
-/* No SDRAM Configuration */
-#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
-
-/* See, GRLIB Docs (grip.pdf) on how to set up
- * These the memory controller registers.
- */
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1   (0x000000ff | (1<<11))
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2   0x82206000
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3   0x00136000
-
-/* GRLIB FT-MCTRL configuration */
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1   (0x000000ff | (1<<11))
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2   0x82206000
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3   0x00136000
-
-/* no DDR controller */
-#undef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
-
-/* no DDR2 Controller */
-#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
-
-/* default kernel command line */
-#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
-
-#endif				/* __CONFIG_H */
diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h
index d7b9c18..abc4214 100644
--- a/include/configs/grasshopper.h
+++ b/include/configs/grasshopper.h
@@ -69,9 +69,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 
-#define CONFIG_STACKSIZE		(2048)
-
-
 /*
  * After booting the board for the first time, new ethernet addresses
  * should be generated and assigned to the environment variables
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
deleted file mode 100644
index 4594b13..0000000
--- a/include/configs/grsim.h
+++ /dev/null
@@ -1,313 +0,0 @@
-/* Configuration header file for LEON3 GRSIM, trying to be similar
- * to Gaisler's GR-XC3S-1500 board.
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H__
-#define __CONFIG_H__
-
-/*
- * High Level Configuration Options
- * (easy to change)
- *
- * Select between TSIM or GRSIM by setting CONFIG_GRSIM or CONFIG_TSIM to 1.
- *
- * TSIM command:
- * $ tsim-leon3 -sdram 32768 -ram 4096 -rom 2048 -mmu -cas
- *
- * In the evaluation version of TSIM, the -sdram/-ram/-rom arguments are
- * hard-coded to these values and need not be specified. (see below)
- *
- * Get TSIM from http://www.gaisler.com/index.php/downloads/simulators
- */
-
-#define CONFIG_GRSIM		0	/* ... not running on GRSIM */
-#define CONFIG_TSIM		1	/* ... running on TSIM */
-
-/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ	40000000	/* 40MHz */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* Partitions */
-
-/*
- * Supported commands
- */
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_REGINFO
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/export/roofs\0"					\
-	"scratch=40000000\0"					\
-	"getkernel=tftpboot $(scratch) $(bootfile)\0" \
-	"bootargs=console=ttyS0,38400" \
-	""
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.81
-#define CONFIG_IPADDR 192.168.0.80
-#define CONFIG_ROOTPATH "/export/rootfs"
-#define CONFIG_HOSTNAME  grxc3s1500
-#define CONFIG_BOOTFILE "/uImage"
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/* Memory MAP
- *
- *  Flash:
- *  |--------------------------------|
- *  | 0x00000000 Text & Data & BSS   | *
- *  |            for Monitor         | *
- *  | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
- *  | UNUSED / Growth                | * 256kb
- *  |--------------------------------|
- *  | 0x00050000 Base custom area    | *
- *  |            kernel / FS         | *
- *  |                                | * Rest of Flash
- *  |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
- *  | END-0x00008000 Environment     | * 32kb
- *  |--------------------------------|
- *
- *
- *
- *  Main Memory:
- *  |--------------------------------|
- *  | UNUSED / scratch area          |
- *  |                                |
- *  |                                |
- *  |                                |
- *  |                                |
- *  |--------------------------------|
- *  | Monitor .Text / .DATA / .BSS   | * 256kb
- *  | Relocated!                     | *
- *  |--------------------------------|
- *  | Monitor Malloc                 | * 128kb (contains relocated environment)
- *  |--------------------------------|
- *  | Monitor/kernel STACK           | * 64kb
- *  |--------------------------------|
- *  | Page Table for MMU systems     | * 2k
- *  |--------------------------------|
- *  | PROM Code accessed from Linux  | * 6kb-128b
- *  |--------------------------------|
- *  | Global data (avail from kernel)| * 128b
- *  |--------------------------------|
- *
- */
-
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at  0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB
- *               0xFE000000 for 32 MB
- *               0xFF000000 for 16 MB
- *               0xFF800000 for  8 MB
- */
-#define CONFIG_SYS_FLASH_BASE		0x00000000
-#define CONFIG_SYS_FLASH_SIZE		0x00800000
-#define CONFIG_ENV_SIZE		0x8000
-
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SIZE)
-
-#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 128 KB sectors */
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-
-#ifdef ENABLE_FLASH_SUPPORT
-/* For use with grsim FLASH emulation extension */
-#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
-
-#undef CONFIG_FLASH_8BIT	/* Flash is 32-bit */
-
-/*** CFI CONFIG ***/
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#endif
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_NOWHERE 1
-/*#define CONFIG_ENV_IS_IN_FLASH*/
-/*#define CONFIG_ENV_SIZE		0x8000*/
-#define CONFIG_ENV_SECT_SIZE	0x40000
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_SDRAM_BASE		0x60000000
-#define CONFIG_SYS_SDRAM_SIZE		0x02000000 /* 32MiB SDRAM */
-#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE)
-
-#define CONFIG_SYS_SRAM_BASE		0x40000000
-#define CONFIG_SYS_SRAM_SIZE		0x00400000 /* 4MiB SRAM */
-#define CONFIG_SYS_SRAM_END		(CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE)
-
-/* Always Run U-Boot from SDRAM */
-#define CONFIG_SYS_RAM_BASE		CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_RAM_SIZE		CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SYS_RAM_END		CONFIG_SYS_SDRAM_END
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
-#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
-#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
-
-/* relocated monitor area */
-#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
-#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
-
-/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
-
-#ifdef CONFIG_CMD_NET
-/*
- * Ethernet configuration
- */
-#define CONFIG_GRETH	1
-
-/*
- * Define CONFIG_GRETH_10MBIT to force GRETH at 10Mb/s
- */
-/* #define CONFIG_GRETH_10MBIT 1 */
-#define CONFIG_PHY_ADDR		0x00
-
-#endif /* CONFIG_CMD_NET */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-/***** Gaisler GRLIB IP-Cores Config ********/
-
-#define CONFIG_SYS_GRLIB_SDRAM     0
-
-#define CONFIG_SYS_GRLIB_MEMCFG1   (0x000000ff | (1<<11))
-
-/* No SDRAM Configuration */
-#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
-
-/* LEON2 MCTRL configuration */
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1   (0x000000ff | (1<<11))
-#if CONFIG_GRSIM
-/* GRSIM configuration */
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2   0x82206000
-#else
-/* TSIM configuration */
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2   0x81805220
-#endif
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3   0x00136000
-
-/* GRLIB FT-MCTRL configuration */
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1   (0x000000ff | (1<<11))
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2   0x82206000
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3   0x00136000
-
-/* no DDR controller */
-#undef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
-
-/* no DDR2 Controller */
-#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
-
-/* default kernel command line */
-#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
-
-/* TSIM command:
- * $ ./tsim-leon3 -mmu -cas
- *
- *  This TSIM evaluation version will expire 2015-04-02
- *
- *
- *  TSIM/LEON3 SPARC simulator, version 2.0.35 (evaluation version)
- *
- *  Copyright (C) 2014, Aeroflex Gaisler - all rights reserved.
- *  This software may only be used with a valid license.
- *  For latest updates, go to http://www.gaisler.com/
- *  Comments or bug-reports to support@gaisler.com
- *
- * serial port A on stdin/stdout
- * allocated 4096 K SRAM memory, in 1 bank
- * allocated 32 M SDRAM memory, in 1 bank
- * allocated 2048 K ROM memory
- * icache: 1 * 4 kbytes, 16 bytes/line (4 kbytes total)
- * dcache: 1 * 4 kbytes, 16 bytes/line (4 kbytes total)
- * tsim> leon
- * 0x80000000   Memory configuration register 1   0x000002ff
- * 0x80000004   Memory configuration register 2   0x81805220
- * 0x80000008   Memory configuration register 3   0x00000000
- */
-
-#endif				/* __CONFIG_H */
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
deleted file mode 100644
index ea9e3e8..0000000
--- a/include/configs/grsim_leon2.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/* Configuration header file for LEON2 GRSIM.
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H__
-#define __CONFIG_H__
-
-/*
- * High Level Configuration Options
- * (easy to change)
- *
- * Select between TSIM or GRSIM by setting CONFIG_GRSIM or CONFIG_TSIM to 1.
- *
- * TSIM command
- *  tsim-leon -sdram 0 -ram 32000 -rom 8192 -mmu
- *
- */
-
-#define CONFIG_GRSIM		0	/* ... not running on GRSIM */
-#define CONFIG_TSIM		1	/* ... running on TSIM */
-
-/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ	40000000	/* 40MHz */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* Partitions */
-
-/*
- * Supported commands
- */
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_REGINFO
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/export/roofs\0"					\
-	"scratch=40000000\0"					\
-	"getkernel=tftpboot $(scratch) $(bootfile)\0" \
-	"bootargs=console=ttyS0,38400" \
-	""
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.81
-#define CONFIG_IPADDR 192.168.0.80
-#define CONFIG_ROOTPATH "/export/rootfs"
-#define CONFIG_HOSTNAME  grxc3s1500
-#define CONFIG_BOOTFILE "/uImage"
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/* Memory MAP
- *
- *  Flash:
- *  |--------------------------------|
- *  | 0x00000000 Text & Data & BSS   | *
- *  |            for Monitor         | *
- *  | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
- *  | UNUSED / Growth                | * 256kb
- *  |--------------------------------|
- *  | 0x00050000 Base custom area    | *
- *  |            kernel / FS         | *
- *  |                                | * Rest of Flash
- *  |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
- *  | END-0x00008000 Environment     | * 32kb
- *  |--------------------------------|
- *
- *
- *
- *  Main Memory:
- *  |--------------------------------|
- *  | UNUSED / scratch area          |
- *  |                                |
- *  |                                |
- *  |                                |
- *  |                                |
- *  |--------------------------------|
- *  | Monitor .Text / .DATA / .BSS   | * 256kb
- *  | Relocated!                     | *
- *  |--------------------------------|
- *  | Monitor Malloc                 | * 128kb (contains relocated environment)
- *  |--------------------------------|
- *  | Monitor/kernel STACK           | * 64kb
- *  |--------------------------------|
- *  | Page Table for MMU systems     | * 2k
- *  |--------------------------------|
- *  | PROM Code accessed from Linux  | * 6kb-128b
- *  |--------------------------------|
- *  | Global data (avail from kernel)| * 128b
- *  |--------------------------------|
- *
- */
-
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at  0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB
- *               0xFE000000 for 32 MB
- *               0xFF000000 for 16 MB
- *               0xFF800000 for  8 MB
- */
-#define CONFIG_SYS_FLASH_BASE		0x00000000
-#define CONFIG_SYS_FLASH_SIZE		0x00800000
-#define CONFIG_ENV_SIZE		0x8000
-
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SIZE)
-
-#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 128 KB sectors */
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-
-#ifdef ENABLE_FLASH_SUPPORT
-/* For use with grsim FLASH emulation extension */
-#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
-
-#undef CONFIG_FLASH_8BIT	/* Flash is 32-bit */
-
-/*** CFI CONFIG ***/
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#endif
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_NOWHERE 1
-/*#define CONFIG_ENV_IS_IN_FLASH*/
-/*#define CONFIG_ENV_SIZE		0x8000*/
-#define CONFIG_ENV_SECT_SIZE	0x40000
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_SDRAM_SIZE		0x00800000
-#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
-
-/* no SRAM available */
-#undef CONFIG_SYS_SRAM_BASE
-#undef CONFIG_SYS_SRAM_SIZE
-
-/* Always Run U-Boot from SDRAM */
-#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
-#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
-#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
-
-/* relocated monitor area */
-#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
-#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
-
-/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
-
-/*
- * Ethernet configuration
- */
-/*#define CONFIG_GRETH	1*/
-
-/*
- * Define CONFIG_GRETH_10MBIT to force GRETH at 10Mb/s
- */
-/* #define CONFIG_GRETH_10MBIT 1 */
-#define CONFIG_PHY_ADDR		0x00
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-/***** Gaisler GRLIB IP-Cores Config ********/
-
-#define CONFIG_SYS_GRLIB_SDRAM    0
-#define CONFIG_SYS_GRLIB_MEMCFG1  (0x000000ff | (1<<11))
-#if CONFIG_GRSIM
-#define CONFIG_SYS_GRLIB_MEMCFG2  0x82206000
-#else
-#define CONFIG_SYS_GRLIB_MEMCFG2  0x00001820
-#endif
-#define CONFIG_SYS_GRLIB_MEMCFG3  0x00136000
-
-/*** LEON2 UART 1 ***/
-
-/* UART1 Define to 1 or 0 */
-#define LEON2_UART1_LOOPBACK_ENABLE 0
-#define LEON2_UART1_FLOWCTRL_ENABLE 0
-#define LEON2_UART1_PARITY_ENABLE 0
-#define LEON2_UART1_ODDPAR_ENABLE 0
-
-/*** LEON2 UART 2 ***/
-
-/* UART2 Define to 1 or 0 */
-#define LEON2_UART2_LOOPBACK_ENABLE 0
-#define LEON2_UART2_FLOWCTRL_ENABLE 0
-#define LEON2_UART2_PARITY_ENABLE 0
-#define LEON2_UART2_ODDPAR_ENABLE 0
-
-#define LEON_CONSOLE_UART1 1
-#define LEON_CONSOLE_UART2 2
-
-/* Use UART2 as console */
-#define LEON2_CONSOLE_SELECT LEON_CONSOLE_UART1
-
-/* LEON2 I/O Port */
-/*#define LEON2_IO_PORT_DIR 0x0000aa00*/
-
-/* default kernel command line */
-#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
-
-#endif				/* __CONFIG_H */
diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h
deleted file mode 100644
index 4cd0f77..0000000
--- a/include/configs/ibf-dsp561.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * U-Boot - Configuration file for IBF-DSP561 board
- */
-
-#ifndef __CONFIG_IBF_DSP561__H__
-#define __CONFIG_IBF_DSP561__H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf561-0.5
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			24
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	9
-#define CONFIG_MEM_SIZE		64
-
-#define CONFIG_EBIU_SDRRC_VAL	0x377
-#define CONFIG_EBIU_SDGCTL_VAL	0x91998d
-#define CONFIG_EBIU_SDBCTL_VAL	0x15
-
-#define CONFIG_EBIU_AMGCTL_VAL	0x3F
-#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_DRIVER_AX88180	1
-#define AX88180_BASE		0x2c000000
-#define CONFIG_HOSTNAME		ibf-dsp561
-
-/*
- * Flash Settings
- */
-#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max number of sectors on one chip */
-/* The BF561-EZKIT uses a top boot flash */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		0x4000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x12000	/* Total Size of Environment Sector */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#else
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
-	arch/blackfin/lib/built-in.o (.text*); \
-	arch/blackfin/cpu/built-in.o (.text*); \
-	. = DEFINED(env_offset) ? env_offset : .; \
-	common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
-#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
-
-/*
- * Misc Settings
- */
-#define CONFIG_UART_CONSOLE	0
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
index bb95dd8..175ddc4 100644
--- a/include/configs/imx6_logic.h
+++ b/include/configs/imx6_logic.h
@@ -130,8 +130,6 @@
 #define CONFIG_SYS_MEMTEST_END         0x10010000
 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
 
-#define CONFIG_STACKSIZE               (128 * 1024)
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS           1
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/ip04.h b/include/configs/ip04.h
deleted file mode 100644
index 1531feb..0000000
--- a/include/configs/ip04.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * U-Boot - Configuration file for IP04 board (having BF532 processor)
- *
- * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com
- *
- * Copyright (c) 2005-2010 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __CONFIG_IP04_H__
-#define __CONFIG_IP04_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf532-0.5
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_NAND
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			10000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			40
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			3
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	10
-#define CONFIG_MEM_SIZE		64
-
-#define CONFIG_EBIU_SDRRC_VAL	0x408
-#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL	0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL	0xffc2ffc2
-#define CONFIG_EBIU_AMBCTL1_VAL	0xffc2ffc2
-
-#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_HOSTNAME		IP04
-
-#define CONFIG_DRIVER_DM9000	1
-#define CONFIG_DM9000_NO_SROM
-#define CONFIG_DM9000_BASE	0x20100000
-#define DM9000_IO		CONFIG_DM9000_BASE
-#define DM9000_DATA		(CONFIG_DM9000_BASE + 2)
-
-/*
- * Flash Settings
- */
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_PREBOOT		"echo starting from spi flash"
-#define CONFIG_ENV_OFFSET	0x30000
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-
-/*
- * NAND Settings
- */
-#define CONFIG_NAND_PLAT
-#define CONFIG_SYS_NAND_BASE		0x20000000
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
-#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
-#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_WRITE(addr, cmd) \
-	do { \
-		bfin_write8(addr, cmd); \
-		SSYNC(); \
-	} while (0)
-
-#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
-#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
-
-/*
- * Misc Settings
- */
-#define CONFIG_UART_CONSOLE	0
-
-#undef CONFIG_SHOW_BOOT_PROGRESS
-/* Enable this if bootretry required; currently it's disabled */
-#define CONFIG_BOOT_RETRY_TIME	-1
-#define CONFIG_BOOTCOMMAND	"run nandboot"
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index 777f225..3a7993e 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -10,6 +10,8 @@
 #ifndef __CONFIG_K2E_EVM_H
 #define __CONFIG_K2E_EVM_H
 
+#include <environment/ti/spi.h>
+
 /* Platform type */
 #define CONFIG_SOC_K2E
 
@@ -30,6 +32,9 @@
 /* SPL SPI Loader Configuration */
 #define CONFIG_SPL_TEXT_BASE           0x0c100000
 
+
+#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
+
 /* NAND Configuration */
 #define CONFIG_SYS_NAND_PAGE_2K
 
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index bd25231..bee1be7 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -10,6 +10,9 @@
 #ifndef __CONFIG_K2G_EVM_H
 #define __CONFIG_K2G_EVM_H
 
+#include <environment/ti/mmc.h>
+#include <environment/ti/spi.h>
+
 /* Platform type */
 #define CONFIG_SOC_K2G
 
@@ -76,4 +79,5 @@
 #define CONFIG_BOUNCE_BUFFER
 #endif
 
+#define SPI_MTD_PARTS	KEYSTONE_SPI1_MTD_PARTS
 #endif /* __CONFIG_K2G_EVM_H */
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index 4adb119..202167b 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -10,6 +10,8 @@
 #ifndef __CONFIG_K2HK_EVM_H
 #define __CONFIG_K2HK_EVM_H
 
+#include <environment/ti/spi.h>
+
 /* Platform type */
 #define CONFIG_SOC_K2HK
 
@@ -30,6 +32,8 @@
 /* SPL SPI Loader Configuration */
 #define CONFIG_SPL_TEXT_BASE		0x0c200000
 
+#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
+
 /* NAND Configuration */
 #define CONFIG_SYS_NAND_PAGE_2K
 
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index 9bdd565..a7ccdd1 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -10,6 +10,8 @@
 #ifndef __CONFIG_K2L_EVM_H
 #define __CONFIG_K2L_EVM_H
 
+#include <environment/ti/spi.h>
+
 /* Platform type */
 #define CONFIG_SOC_K2L
 
@@ -30,6 +32,8 @@
 /* SPL SPI Loader Configuration */
 #define CONFIG_SPL_TEXT_BASE		0x0c100000
 
+#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
+
 /* NAND Configuration */
 #define CONFIG_SYS_NAND_PAGE_4K
 
diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
index 2ce39ff..258fd3a 100644
--- a/include/configs/liteboard.h
+++ b/include/configs/liteboard.h
@@ -113,7 +113,6 @@
 #define CONFIG_SYS_HZ			1000
 
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE		SZ_128K
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index af07672..1a0c7f8 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -11,6 +11,7 @@
 #define CONFIG_GICV2
 
 #include <asm/arch/config.h>
+#include <asm/arch/stream_id_lsch2.h>
 
 #define CONFIG_SUPPORT_RAW_INITRD
 
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index db29fa2b..d8bbc80 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -36,11 +36,6 @@
 #define CONFIG_CMD_EXT2
 #endif
 
-/*
- * Generic Timer Definitions
- */
-#define GENERIC_TIMER_CLK		12500000
-
 #define CONFIG_SYS_CLK_FREQ		100000000
 #define CONFIG_DDR_CLK_FREQ		100000000
 
@@ -243,7 +238,7 @@
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
-#define CONFIG_TIMER_CLK_FREQ		12500000
+#define COUNTER_FREQUENCY		12500000
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		256
@@ -274,12 +269,6 @@
 
 #define CONFIG_LS102XA_STREAM_ID
 
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE		(30 * 1024)
-
 #define CONFIG_SYS_INIT_SP_OFFSET \
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR \
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 4fb8b0c..b349b36 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -27,11 +27,6 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
 
-/*
- * Generic Timer Definitions
- */
-#define GENERIC_TIMER_CLK		12500000
-
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
@@ -500,7 +495,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
-#define CONFIG_TIMER_CLK_FREQ		12500000
+#define COUNTER_FREQUENCY		12500000
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		256
@@ -542,12 +537,6 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_LS102XA_STREAM_ID
 
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE		(30 * 1024)
-
 #define CONFIG_SYS_INIT_SP_OFFSET \
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR \
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index c6438d5..fcf035b 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -56,11 +56,6 @@
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
 #endif
 
-/*
- * Generic Timer Definitions
- */
-#define GENERIC_TIMER_CLK		12500000
-
 #define CONFIG_SYS_CLK_FREQ		100000000
 #define CONFIG_DDR_CLK_FREQ		100000000
 
@@ -370,7 +365,7 @@
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
-#define CONFIG_TIMER_CLK_FREQ		12500000
+#define COUNTER_FREQUENCY		12500000
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		256
@@ -408,12 +403,6 @@
 
 #define CONFIG_LS102XA_STREAM_ID
 
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE		(30 * 1024)
-
 #define CONFIG_SYS_INIT_SP_OFFSET \
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR \
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 5a5f951..46d54a0 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -13,6 +13,7 @@
 #define CONFIG_MP
 #define CONFIG_GICV2
 
+#include <asm/arch/stream_id_lsch2.h>
 #include <asm/arch/config.h>
 
 /* Link Definitions */
@@ -187,12 +188,14 @@
 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
 			"5m(kernel),1m(dtb),9m(file_system)"
 #else
-#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
-			"1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
-			"1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
-			"1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
-			"1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
-			"40m(nor_bank4_fit);7e800000.flash:" \
+#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
+			"2m@0x100000(nor_bank0_uboot),"\
+			"40m@0x1100000(nor_bank0_fit)," \
+			"7m(nor_bank0_user)," \
+			"2m@0x4100000(nor_bank4_uboot)," \
+			"40m@0x5100000(nor_bank4_fit),"\
+			"-(nor_bank4_user);" \
+			"7e800000.flash:" \
 			"1m(nand_uboot),1m(nand_uboot_env)," \
 			"20m(nand_fit);spi0.0:1m(uboot)," \
 			"5m(kernel),1m(dtb),9m(file_system)"
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 6a345c0..b14e944 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -396,12 +396,6 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_SYS_HZ			1000
 
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE		(30 * 1024)
-
 #define CONFIG_SYS_INIT_SP_OFFSET \
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 1ed7517..cb79296 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -13,6 +13,7 @@
 #define CONFIG_GICV2
 
 #include <asm/arch/config.h>
+#include <asm/arch/stream_id_lsch2.h>
 
 /* Link Definitions */
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 4b3b21e..0cf6010 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -434,12 +434,6 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_SYS_HZ			1000
 
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE		(30 * 1024)
-
 #define CONFIG_SYS_INIT_SP_OFFSET \
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
@@ -485,12 +479,14 @@ unsigned long get_board_ddr_clk(void);
 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \
 			"14m(free)"
 #else
-#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
-			"1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
-			"1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
-			"1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
-			"1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
-			"40m(nor_bank4_fit);7e800000.flash:" \
+#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
+			"2m@0x100000(nor_bank0_uboot),"\
+			"40m@0x1100000(nor_bank0_fit)," \
+			"7m(nor_bank0_user)," \
+			"2m@0x4100000(nor_bank4_uboot)," \
+			"40m@0x5100000(nor_bank4_fit),"\
+			"-(nor_bank4_user);" \
+			"7e800000.flash:" \
 			"4m(nand_uboot),36m(nand_kernel)," \
 			"472m(nand_free);spi0.0:2m(uboot)," \
 			"14m(free)"
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 5072e20..427f623 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -13,7 +13,7 @@
 #define CONFIG_GICV3
 #define CONFIG_FSL_TZPC_BP147
 
-#include <asm/arch/ls2080a_stream_id.h>
+#include <asm/arch/stream_id_lsch3.h>
 #include <asm/arch/config.h>
 
 /* Link Definitions */
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 08d1586..beacb99 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -368,6 +368,7 @@ unsigned long get_board_ddr_clk(void);
 	"kernel_start=0x581100000\0"		\
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x2800000\0"		\
+	"mcmemsize=0x40000000\0"		\
 	"mcinitcmd=esbc_validate 0x580c80000;"  \
 	"esbc_validate 0x580cc0000;"            \
 	"fsl_mc start mc 0x580300000"           \
@@ -384,6 +385,7 @@ unsigned long get_board_ddr_clk(void);
 	"kernel_start=0x581100000\0"		\
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x2800000\0"		\
+	"mcmemsize=0x40000000\0"		\
 	"mcinitcmd=fsl_mc start mc 0x580300000" \
 	" 0x580800000 \0"
 #endif /* CONFIG_SECURE_BOOT */
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 408140f..2155a89 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -339,6 +339,7 @@ unsigned long get_board_sys_clk(void);
 	"kernel_start=0x581100000\0"		\
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x2800000\0"		\
+	"mcmemsize=0x40000000\0"		\
 	"fdtfile=fsl-ls2080a-rdb.dtb\0"		\
 	"mcinitcmd=esbc_validate 0x580c80000;"  \
 	"esbc_validate 0x580cc0000;"            \
@@ -362,6 +363,7 @@ unsigned long get_board_sys_clk(void);
 	"kernel_start=0x581100000\0"		\
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x2800000\0"		\
+	"mcmemsize=0x40000000\0"		\
 	"fdtfile=fsl-ls2080a-rdb.dtb\0"		\
 	"mcinitcmd=fsl_mc start mc 0x580300000" \
 	" 0x580800000 \0"                       \
diff --git a/include/configs/miqi_rk3288.h b/include/configs/miqi_rk3288.h
new file mode 100644
index 0000000..f686042
--- /dev/null
+++ b/include/configs/miqi_rk3288.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+		"stdin=serial,cros-ec-keyb\0" \
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
+
+#include <configs/rk3288_common.h>
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_SYS_WHITE_ON_BLACK
+
+#endif
diff --git a/include/configs/mvebu_db-88f3720.h b/include/configs/mvebu_armada-37xx.h
index 6bb78e0..5408490 100644
--- a/include/configs/mvebu_db-88f3720.h
+++ b/include/configs/mvebu_armada-37xx.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef _CONFIG_MVEBU_DB_88F3720_H
-#define _CONFIG_MVEBU_DB_88F3720_H
+#ifndef _CONFIG_MVEBU_ARMADA_37XX_H
+#define _CONFIG_MVEBU_ARMADA_37XX_H
 
 /*
  * High Level Configuration Options (easy to change)
@@ -92,6 +92,7 @@
 #define CONFIG_PHY_GIGE		/* GbE speed/duplex detect */
 #define CONFIG_ARP_TIMEOUT	200
 #define CONFIG_NET_RETRY_COUNT	50
+#define CONFIG_PHY_MARVELL
 
 /* USB 2.0 */
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
@@ -126,4 +127,4 @@
 
 #define CONFIG_SUPPORT_VFAT
 
-#endif /* _CONFIG_MVEBU_DB_88F3720_H */
+#endif /* _CONFIG_MVEBU_ARMADA_37XX_H */
diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
index a8a9d15..8ee5f27 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -81,6 +81,14 @@
 #define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
 #define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
 
+/*
+ * Ethernet Driver configuration
+ */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_PHY_GIGE		/* GbE speed/duplex detect */
+#define CONFIG_ARP_TIMEOUT	200
+#define CONFIG_NET_RETRY_COUNT	50
+
 /* USB 2.0 */
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index a2ab77a..c04ae96 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -180,8 +180,6 @@
 #define CONFIG_SYS_MEMTEST_END         0x10010000
 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
 
-#define CONFIG_STACKSIZE               (128 * 1024)
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS           1
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index f5af65d..2fff799 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -120,8 +120,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + SZ_512M)
 
-#define CONFIG_STACKSIZE		SZ_128K
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h
index 8215e63..62159a1 100644
--- a/include/configs/mx6sllevk.h
+++ b/include/configs/mx6sllevk.h
@@ -113,8 +113,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + SZ_128M)
 
-#define CONFIG_STACKSIZE		SZ_128K
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 0742b4b..971f6c2 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -95,8 +95,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000)
 
-#define CONFIG_STACKSIZE		SZ_128K
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
@@ -182,7 +180,4 @@
 #define CONFIG_SYS_MMC_ENV_DEV		0  /*USDHC3*/
 #endif
 
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x30, 8}, {0x32, 8}, {0x34, 8} }
-
 #endif				/* __CONFIG_H */
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index aff7a24..e63da43 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -123,8 +123,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000)
 
-#define CONFIG_STACKSIZE		SZ_128K
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index 71c22ff..f466c62 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -150,7 +150,6 @@
 #define CONFIG_SYS_HZ			1000
 
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE		SZ_128K
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
index c65a9e5..5bc26aa 100644
--- a/include/configs/mx6ullevk.h
+++ b/include/configs/mx6ullevk.h
@@ -137,8 +137,6 @@
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 #define CONFIG_SYS_HZ			1000
 
-#define CONFIG_STACKSIZE		SZ_128K
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 5bf8ad7..e2b05ca 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -21,7 +21,7 @@
 #define CONFIG_MXC_GPT_HCLK
 #define CONFIG_SYSCOUNTER_TIMER
 #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
-#define CONFIG_TIMER_CLK_FREQ CONFIG_SC_TIMER_CLK
+#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_SYS_BOOTM_LEN	0x1000000
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 81d769f..9807ace 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -178,8 +178,6 @@
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 #define CONFIG_SYS_HZ			1000
 
-#define CONFIG_STACKSIZE		SZ_128K
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index f6e4b3b..37f365d 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -88,7 +88,6 @@
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE		SZ_8K
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 6b128df..e99968c 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -48,7 +48,6 @@
 #define V_OSCK			26000000	/* Clock output from T2 */
 #define V_SCLK			(V_OSCK >> 1)
 
-#undef CONFIG_USE_IRQ				/* no support for IRQs */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_SKIP_LOWLEVEL_INIT		/* X-Loader set everything up */
 
@@ -381,13 +380,6 @@ int rx51_kp_getc(struct stdio_dev *sdev);
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
 
 /*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE		(128 << 10) /* regular stack 128 KiB */
-
-/*
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS		2
diff --git a/include/configs/nsim.h b/include/configs/nsim.h
index 0cc55b7..d6d26c7 100644
--- a/include/configs/nsim.h
+++ b/include/configs/nsim.h
@@ -10,11 +10,6 @@
 #include <linux/sizes.h>
 
 /*
- *  CPU configuration
- */
-#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_CLK_FREQ
-
-/*
  * Memory configuration
  */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 6700073..9d90e46 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -48,7 +48,6 @@
 #define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
 
 #define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE	(256*1024) /* regular stack */
 
 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
 	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
@@ -261,30 +260,27 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_REVISION_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS		"console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off"
 #define CONFIG_BOOTCOMMAND \
-	"if mmc rescan; then " \
-		"run mmcboot; " \
-	"else " \
-		"run spiboot; " \
-	"fi"
-#define CONFIG_EXTRA_ENV_SETTINGS \
+		"run envboot; " \
+		"run mmcboot; "
+
+#define DEFAULT_LINUX_BOOT_ENV \
+	"loadaddr=0xc0700000\0" \
 	"fdtaddr=0xc0600000\0" \
+	"scriptaddr=0xc0600000\0"
+
+#include <environment/ti/mmc.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	DEFAULT_MMC_TI_ARGS \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
 	"fdtfile=da850-lcdk.dtb\0" \
-	"fdtboot=bootz 0xc0700000 - ${fdtaddr};\0" \
-	"mmcboot=" \
-		"if fatload mmc 0 0xc0600000 boot.scr; then " \
-			"source 0xc0600000; " \
-		"else " \
-			"fatload mmc 0 0xc0700000 " \
-				__stringify(CONFIG_BOOTFILE) "; " \
-			"fatload mmc 0 ${fdtaddr} ${fdtfile}; " \
-			"run fdtboot; " \
-		"fi;\0" \
-	"spiboot=" \
-		"sf probe 0; " \
-		"sf read 0xc0700000 0x80000 0x220000; " \
-		"bootz 0xc0700000;\0"
+	"boot_fdt=yes\0" \
+	"boot_fit=0\0" \
+	"console=ttyS2,115200n8\0"
 
 /*
  * U-Boot commands
diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h
deleted file mode 100644
index 549b33c..0000000
--- a/include/configs/openrisc-generic.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson, stefan.kristianssons@saunalahti.fi
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * BOARD/CPU
- */
-#define CONFIG_SYS_CLK_FREQ		50000000
-#define CONFIG_SYS_RESET_ADDR		0x00000100
-
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_SIZE		0x02000000
-
-#define CONFIG_SYS_CACHELINE_SIZE	16
-
-#define CONFIG_SYS_UART_BASE		0x90000000
-#define CONFIG_SYS_UART_FREQ		CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_UART_BAUD		115200
-
-#define CONFIG_BOARD_NAME		"OpenRISC Generic"
-
-#define CONFIG_SYS_MAX_FLASH_SECT	0
-
-/*
- * SERIAL
- */
-# define CONFIG_SYS_NS16550_SERIAL
-# define CONFIG_SYS_NS16550_REG_SIZE	1
-# define CONFIG_CONS_INDEX		1
-# define CONFIG_SYS_NS16550_COM1	(0x90000000)
-# define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_CLK_FREQ
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{CONFIG_BAUDRATE}
-#define CONSOLE_ARG			"console=console=ttyS0,115200\0"
-
-/*
- * Ethernet
- */
-#define CONFIG_SYS_ETHOC_BASE		0x92000000
-
-#define CONFIG_BOOTFILE			"boot.img"
-#define CONFIG_LOADADDR			0x100000 /* 1MB mark */
-
-/*
- * TIMER
- */
-#define CONFIG_SYS_OPENRISC_TMR_HZ	100
-
-/*
- * Memory organisation:
- *
- * RAM start ---------------------------
- *           | ...                     |
- *           ---------------------------
- *           | Stack                   |
- *           ---------------------------
- *           | Global data             |
- *           ---------------------------
- *           | Environment             |
- *           ---------------------------
- *           | Monitor                 |
- * RAM end   ---------------------------
- */
-/* We're running in RAM */
-#define CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_LEN	0x40000	/* Reserve 256k */
-#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
-				CONFIG_SYS_SDRAM_SIZE - \
-				CONFIG_SYS_MONITOR_LEN)
-
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE		0x20000 /* Total Size of Environment, 128KB */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
-
-/*
- * Global data object and stack pointer
- */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_ENV_ADDR \
-					- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_GBL_DATA_ADDR	CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_STACK_LENGTH		0x10000 /* 64KB */
-#define CONFIG_SYS_MALLOC_LEN		0x400000 /* 4MB */
-#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_INIT_SP_OFFSET \
-					- CONFIG_SYS_STACK_LENGTH \
-					- CONFIG_SYS_MALLOC_LEN)
-/*
- * MISC
- */
-#define CONFIG_SYS_LONGHELP		/* Provide extended help */
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
-#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + \
-					16)	/* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x2000)
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP_ADDR - 0x20000)
-#define CONFIG_CMDLINE_EDITING
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_BSP
-
-#define CONFIG_LMB
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 286598d..f506c9c 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -226,12 +226,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
-
 /* Physical memory map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			(0x80000000)
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index dacb78a..9042dc2 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -37,7 +37,6 @@
 #define CONFIG_SYS_SDRAM_BASE		0x88000000
 #define CONFIG_SYS_MALLOC_LEN		(256 << 10)
 #define CONFIG_SYS_BOOTPARAMS_LEN	(4 << 10)
-#define CONFIG_STACKSIZE		(4 << 10) /* regular stack */
 
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN		(192 << 10)
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 8ad7fa6..26b1b11 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -117,7 +117,6 @@
 #define CONFIG_SYS_HZ			1000
 
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE		SZ_128K
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
diff --git a/include/configs/popmetal_rk3288.h b/include/configs/popmetal_rk3288.h
index 6a068bb..bbd54a1 100644
--- a/include/configs/popmetal_rk3288.h
+++ b/include/configs/popmetal_rk3288.h
@@ -11,7 +11,7 @@
 #include <configs/rk3288_common.h>
 
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_DEV 0
 
 #define CONFIG_SYS_WHITE_ON_BLACK
 
diff --git a/include/configs/pr1.h b/include/configs/pr1.h
deleted file mode 100644
index d3fba0d..0000000
--- a/include/configs/pr1.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * U-Boot - Configuration file for PR1 Appliance
- *
- * based on bf537-stamp.h
- * Copyright (c) Switchfin Org. <dpn@switchfin.org>
- */
-
-#ifndef __CONFIG_PR1_H__
-#define __CONFIG_PR1_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf537-0.3
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			24
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	11
-#define CONFIG_MEM_SIZE		128
-
-#define CONFIG_EBIU_SDRRC_VAL	0x306
-#define CONFIG_EBIU_SDGCTL_VAL	0x8091998d
-
-#define CONFIG_EBIU_AMGCTL_VAL	0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_BFIN_MAC
-#define CONFIG_NETCONSOLE
-#endif
-#define CONFIG_HOSTNAME		pr1
-#define CONFIG_TFTP_BLOCKSIZE	4404
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET	0x10000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * NAND Settings
- */
-#define CONFIG_NAND_PLAT
-#define CONFIG_SYS_NAND_BASE		0x20000000
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
-#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
-#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_WRITE(addr, cmd) \
-	do { \
-		bfin_write8(addr, cmd); \
-		SSYNC(); \
-	} while (0)
-
-#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
-#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF9
-
-/*
- * Misc Settings
- */
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BOOTCOMMAND	"run nandboot"
-#define CONFIG_LOADADDR		0x2000000
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-/*
- * Overwrite some settings defined in bfin_adi_common.h
- */
-#undef NAND_ENV_SETTINGS
-#define NAND_ENV_SETTINGS \
-	"nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
-	"nandboot=" \
-		"nand read $(loadaddr) 0x0 0x900000;" \
-		"run nandargs;" \
-		"bootm" \
-		"\0"
-
-#endif
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index d7e96ec..c5e508e 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -18,7 +18,6 @@
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
-#define CONFIG_SYS_THUMB_BUILD
 
 #define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
 #define CONFIG_SYS_TIMER_BASE		0x2000e000 /* TIMER3 */
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 4ba81ac..9d22e0c 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -17,17 +17,17 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 
+#define COUNTER_FREQUENCY               24000000
+
 #define CONFIG_SYS_NS16550_MEM32
 
 #define CONFIG_SYS_TEXT_BASE		0x00200000
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
 #define CONFIG_SYS_LOAD_ADDR		0x00800800
 #define CONFIG_SPL_STACK		0xff8effff
-#define CONFIG_SPL_TEXT_BASE		0xff8c2008
+#define CONFIG_SPL_TEXT_BASE		0xff8c2000
 #define CONFIG_SPL_MAX_SIZE		0x30000
 /*  BSS setup */
 #define CONFIG_SPL_BSS_START_ADDR       0xff8e0000
@@ -52,8 +52,6 @@
 #define CONFIG_SYS_SDRAM_BASE		0
 #define CONFIG_NR_DRAM_BANKS		1
 
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI
 #define CONFIG_SF_DEFAULT_SPEED 20000000
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/rock.h b/include/configs/rock.h
new file mode 100644
index 0000000..de5291c
--- /dev/null
+++ b/include/configs/rock.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3188_common.h>
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+/* SPL @ 32k for 34k
+ * u-boot directly after @ 68k for 400k or so
+ * ENV @ 992k
+ */
+#define CONFIG_ENV_OFFSET ((1024-32) * 1024)
+#else
+/* SPL @ 32k for ~36k
+ * ENV @ 96k
+ * u-boot @ 128K
+ */
+#define CONFIG_ENV_OFFSET (96 * 1024)
+#endif
+
+#endif
diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h
index 0b12bf3..398b3aa 100644
--- a/include/configs/s32v234evb.h
+++ b/include/configs/s32v234evb.h
@@ -199,12 +199,6 @@
 #define CONFIG_SYS_MALLOC_BASE		(DDR_BASE_ADDR)
 #endif
 
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
-
 #if 0
 /* Configure PXE */
 #define CONFIG_BOOTP_PXE
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 6b3cd18..4c112cc 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -25,12 +25,6 @@
 #define CONFIG_SYS_TIMER_RATE		1000000
 #endif
 
-/*
- * Number of bits in a C 'long' on this architecture. Set this to 32 when
- * building on a 32-bit machine.
- */
-#define CONFIG_SANDBOX_BITS_PER_LONG	64
-
 #define CONFIG_LMB
 #define CONFIG_ANDROID_BOOT_IMAGE
 
@@ -199,4 +193,6 @@
 #define CONFIG_SYS_SYSTEMACE_WIDTH	16
 #define CONFIG_SYS_SYSTEMACE_BASE	0
 
+#define CONFIG_MISC_INIT_F
+
 #endif
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 5a9ec02..d69f513 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -228,9 +228,6 @@
 # define CONFIG_ENV_SECT_SIZE		(4 << 10) /* 4 KB sectors */
 #endif /* SPI support */
 
-/* Unsupported features */
-#undef CONFIG_USE_IRQ
-
 #define CONFIG_DRIVER_TI_CPSW
 #define CONFIG_MII
 #define CONFIG_PHY_GIGE
diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
index a456e45..8609f2a 100644
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h
@@ -66,8 +66,6 @@
 
 #define CONFIG_SYS_MALLOC_LEN		(2 << 20)
 
-#define CONFIG_STACKSIZE		(64 << 10)
-
 #define CONFIG_BOOTARGS							\
 	"console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
 #define CONFIG_BOOTCOMMAND						\
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 55280f2..de3d661 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -12,9 +12,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR		0x20050000
 #define CONFIG_SYS_TEXT_BASE		0x08000000
 
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-
 /*
  * Configuration of the external SDRAM memory
  */
@@ -58,7 +55,6 @@
 
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
-#define CONFIG_STACKSIZE		(256 * 1024)
 
 #define CONFIG_BOOTARGS							\
 	"console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
@@ -79,4 +75,5 @@
 #define CONFIG_CMDLINE_EDITING
 
 #define CONFIG_CMD_MEM
+#define CONFIG_CMD_CACHE
 #endif /* __CONFIG_H */
diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h
index 3e5708b..1b7bfb6 100644
--- a/include/configs/sun50i.h
+++ b/include/configs/sun50i.h
@@ -18,7 +18,6 @@
 
 #define CONFIG_SUNXI_USB_PHYS	1
 
-#define COUNTER_FREQUENCY	CONFIG_TIMER_CLK_FREQ
 #define GICD_BASE		0x1c81000
 #define GICC_BASE		0x1c82000
 
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 05ea172..1d475b1 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -46,7 +46,7 @@
 #endif
 
 /* CPU */
-#define CONFIG_TIMER_CLK_FREQ		24000000
+#define COUNTER_FREQUENCY		24000000
 
 /*
  * The DRAM Base differs between some models. We cannot use macros for the
@@ -79,7 +79,7 @@
 
 #define CONFIG_SPL_BSS_MAX_SIZE		0x00080000 /* 512 KiB */
 
-#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
+#ifdef CONFIG_SUNXI_HIGH_SRAM
 /*
  * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
  * slightly bigger. Note that it is possible to map the first 32 KiB of the
@@ -125,6 +125,9 @@
 #define CONFIG_SYS_NAND_MAX_ECCPOS 1664
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_SYS_MAX_NAND_DEVICE 8
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
 #endif
 
 #ifdef CONFIG_SPL_SPI_SUNXI
@@ -134,9 +137,13 @@
 /* mmc config */
 #ifdef CONFIG_MMC
 #define CONFIG_MMC_SUNXI_SLOT		0
-#define CONFIG_ENV_IS_IN_MMC
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* first detected MMC controller */
 #define CONFIG_SYS_MMC_MAX_DEVICE	4
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE			(128 << 10)
 #endif
 
 /* 64MB of malloc() pool */
@@ -155,18 +162,10 @@
 /* standalone support */
 #define CONFIG_STANDALONE_LOAD_ADDR	CONFIG_SYS_LOAD_ADDR
 
-/* baudrate */
-
-/* The stack sizes are set up in start.S using the settings below */
-#define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
-
 /* FLASH and environment organization */
 
 #define CONFIG_SYS_MONITOR_LEN		(768 << 10)	/* 768 KiB */
 
-#define CONFIG_ENV_OFFSET		(544 << 10) /* (8 + 24 + 512) KiB */
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-
 #define CONFIG_FAT_WRITE	/* enable write access */
 
 #define CONFIG_SPL_FRAMEWORK
@@ -175,32 +174,24 @@
 #define CONFIG_SPL_BOARD_LOAD_IMAGE
 #endif
 
-#if defined(CONFIG_MACH_SUN9I)
+#ifdef CONFIG_SUNXI_HIGH_SRAM
 #define CONFIG_SPL_TEXT_BASE		0x10040		/* sram start+header */
-#define CONFIG_SPL_MAX_SIZE		0x5fc0		/* ? KiB on sun9i */
-#elif defined(CONFIG_MACH_SUN50I)
-#define CONFIG_SPL_TEXT_BASE		0x10040		/* sram start+header */
-#define CONFIG_SPL_MAX_SIZE		0x7fc0		/* 32 KiB on sun50i */
+#define CONFIG_SPL_MAX_SIZE		0x7fc0		/* 32 KiB */
+#define LOW_LEVEL_SRAM_STACK		0x00018000
 #else
 #define CONFIG_SPL_TEXT_BASE		0x40		/* sram start+header */
 #define CONFIG_SPL_MAX_SIZE		0x5fc0		/* 24KB on sun4i/sun7i */
+#define LOW_LEVEL_SRAM_STACK		0x00008000	/* End of sram */
 #endif
 
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
 #ifndef CONFIG_ARM64
 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
 #endif
 
 #define CONFIG_SPL_PAD_TO		32768		/* decimal for 'dd' */
 
-#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
-/* FIXME: 40 KiB instead of 32 KiB ? */
-#define LOW_LEVEL_SRAM_STACK		0x00018000
-#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
-#else
-/* end of 32 KiB in sram */
-#define LOW_LEVEL_SRAM_STACK		0x00008000 /* End of sram */
-#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
-#endif
 
 /* I2C */
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
@@ -338,13 +329,6 @@ extern int soft_i2c_gpio_scl;
 #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
 #endif
 
-#if !defined CONFIG_ENV_IS_IN_MMC && \
-    !defined CONFIG_ENV_IS_IN_NAND && \
-    !defined CONFIG_ENV_IS_IN_FAT && \
-    !defined CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
 #define CONFIG_MISC_INIT_R
 
 #ifndef CONFIG_SPL_BUILD
@@ -474,6 +458,20 @@ extern int soft_i2c_gpio_scl;
 	"stderr=serial\0"
 #endif
 
+#ifdef CONFIG_MTDIDS_DEFAULT
+#define SUNXI_MTDIDS_DEFAULT \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"
+#else
+#define SUNXI_MTDIDS_DEFAULT
+#endif
+
+#ifdef CONFIG_MTDPARTS_DEFAULT
+#define SUNXI_MTDPARTS_DEFAULT \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
+#else
+#define SUNXI_MTDPARTS_DEFAULT
+#endif
+
 #define CONSOLE_ENV_SETTINGS \
 	CONSOLE_STDIN_SETTINGS \
 	CONSOLE_STDOUT_SETTINGS
@@ -484,6 +482,8 @@ extern int soft_i2c_gpio_scl;
 	DFU_ALT_INFO_RAM \
 	"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
 	"console=ttyS0,115200\0" \
+	SUNXI_MTDIDS_DEFAULT \
+	SUNXI_MTDPARTS_DEFAULT \
 	BOOTCMD_SUNXI_COMPAT \
 	BOOTENV
 
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 035a932..3f2da57 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -196,13 +196,6 @@
 #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
 
 /*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
-
-/*
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index b719943..115b3b3 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -10,11 +10,6 @@
 #include <linux/sizes.h>
 
 /*
- *  CPU configuration
- */
-#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_CLK_FREQ
-
-/*
  * Memory configuration
  */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h
deleted file mode 100644
index 7924c8e..0000000
--- a/include/configs/tcm-bf518.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * U-Boot - Configuration file for Bluetechnix TCM-BF518 board
- */
-
-#ifndef __CONFIG_TCM_BF518_H__
-#define __CONFIG_TCM_BF518_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf518-0.0
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			16
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			4
-
-/*
- * Memory Settings
- */
-/* This board has a 32meg MT48H16M16 */
-#define CONFIG_MEM_ADD_WDTH	9
-#define CONFIG_MEM_SIZE		32
-
-#define CONFIG_EBIU_SDRRC_VAL	0x3f8
-#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(384 * 1024)
-
-/*
- * Network Settings
- */
-#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_BFIN_MAC
-#define CONFIG_NETCONSOLE	1
-#endif
-#define CONFIG_HOSTNAME		tcm-bf518
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	19
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-#define CONFIG_SF_DEFAULT_SPEED	30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET	0x8000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x8000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Misc Settings
- */
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BOOTCOMMAND	"run flashboot"
-#define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
deleted file mode 100644
index f9d9f84..0000000
--- a/include/configs/tcm-bf537.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * U-Boot - Configuration file for TCM-BF537 board
- */
-
-#ifndef __CONFIG_TCM_BF537_H__
-#define __CONFIG_TCM_BF537_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU             bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz					*/
-#define CONFIG_CLKIN_HZ			25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
-#define CONFIG_CLKIN_HALF		0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
-#define CONFIG_PLL_BYPASS		0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
-/* Values can range from 0-63 (where 0 means 64)			*/
-#define CONFIG_VCO_MULT			21
-/* CCLK_DIV controls the core clock divider				*/
-/* Values can be 1, 2, 4, or 8 ONLY					*/
-#define CONFIG_CCLK_DIV			1
-/* SCLK_DIV controls the system clock divider				*/
-/* Values can range from 1-15						*/
-#define CONFIG_SCLK_DIV			4
-
-/* Decrease core voltage */
-#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH	9
-#define CONFIG_MEM_SIZE		32
-
-#define CONFIG_EBIU_SDRRC_VAL	0x3f8
-#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK	1
-#define CONFIG_BFIN_MAC
-#define CONFIG_SMC911X		1
-#define CONFIG_SMC911X_BASE	0x20308000
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_NETCONSOLE	1
-#endif
-#define CONFIG_HOSTNAME		tcm-bf537
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_FLASH_BASE		0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	67
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ	30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET	0x8000
-#define CONFIG_ENV_SIZE		0x8000
-#define CONFIG_ENV_SECT_SIZE	0x8000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
-	arch/blackfin/lib/built-in.o (.text*); \
-	arch/blackfin/cpu/built-in.o (.text*); \
-	. = DEFINED(env_offset) ? env_offset : .; \
-	common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * SPI_MMC Settings
- */
-#define CONFIG_MMC_SPI
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BOOTCOMMAND	"run flashboot"
-#define FLASHBOOT_ENV_SETTINGS \
-	"flashboot=flread 20040000 1000000 300000;" \
-	"bootm 0x1000000\0"
-#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 319279e..baf818b 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -179,9 +179,6 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #endif
 
-/* Unsupported features */
-#undef CONFIG_USE_IRQ
-
 /* Ethernet */
 #define CONFIG_DRIVER_TI_CPSW
 #define CONFIG_MII
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index 2840467..b5af700 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -137,7 +137,4 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #endif
 
-/* Unsupported features */
-#undef CONFIG_USE_IRQ
-
 #endif
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index a4ec4ce..1561d54 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -51,74 +51,12 @@
 	"bootm_size=0x10000000\0" \
 	"boot_fdt=try\0"
 
-#define DEFAULT_MMC_TI_ARGS \
-	"mmcdev=0\0" \
-	"mmcrootfstype=ext4 rootwait\0" \
-	"finduuid=part uuid mmc ${bootpart} uuid\0" \
-	"args_mmc=run finduuid;setenv bootargs console=${console} " \
-		"${optargs} " \
-		"root=PARTUUID=${uuid} rw " \
-		"rootfstype=${mmcrootfstype}\0" \
-	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
-	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
-		"source ${loadaddr}\0" \
-	"bootenvfile=uEnv.txt\0" \
-	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
-		"env import -t ${loadaddr} ${filesize}\0" \
-	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \
-	"loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
-	"loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
-	"envboot=mmc dev ${mmcdev}; " \
-		"if mmc rescan; then " \
-			"echo SD/MMC found on device ${mmcdev};" \
-			"if run loadbootscript; then " \
-				"run bootscript;" \
-			"else " \
-				"if run loadbootenv; then " \
-					"echo Loaded env from ${bootenvfile};" \
-					"run importbootenv;" \
-				"fi;" \
-				"if test -n $uenvcmd; then " \
-					"echo Running uenvcmd ...;" \
-					"run uenvcmd;" \
-				"fi;" \
-			"fi;" \
-		"fi;\0" \
-	"mmcloados=run args_mmc; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"bootz ${loadaddr} - ${fdtaddr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
-				"else " \
-					"echo WARN: Cannot load the DT; " \
-				"fi; " \
-			"fi; " \
-		"else " \
-			"bootz; " \
-		"fi;\0" \
-	"mmcboot=mmc dev ${mmcdev}; " \
-		"setenv devnum ${mmcdev}; " \
-		"setenv devtype mmc; " \
-		"if mmc rescan; then " \
-			"echo SD/MMC found on device ${mmcdev};" \
-			"if run loadimage; then " \
-				"if test ${boot_fit} -eq 1; then " \
-					"run loadfit; " \
-				"else " \
-					"run mmcloados;" \
-				"fi;" \
-			"fi;" \
-		"fi;\0" \
-
 #define DEFAULT_FIT_TI_ARGS \
 	"boot_fit=0\0" \
 	"fit_loadaddr=0x88000000\0" \
-	"fit_bootfile=fitImage.itb\0" \
+	"fit_bootfile=fitImage\0" \
 	"update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}\0" \
-	"args_fit=setenv bootargs console=${console} \0" \
-	"loadfit=run args_fit; bootm ${loadaddr}#${fdtfile};\0" \
+	"loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};\0" \
 
 /*
  * DDR information.  If the CONFIG_NR_DRAM_BANKS is not defined,
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 5d4ef58..5d2a7ab 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -28,7 +28,6 @@
 #define CONFIG_NR_DRAM_BANKS		2
 #define CONFIG_SYS_LPAE_SDRAM_BASE	0x800000000
 #define CONFIG_MAX_RAM_BANK_SIZE	(2 << 30)       /* 2GB */
-#define CONFIG_STACKSIZE		(512 << 10)     /* 512 KiB */
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SPL_TEXT_BASE - \
 					GENERATED_GBL_DATA_SIZE)
 
@@ -55,6 +54,13 @@
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
 
+/* SRAM scratch space entries  */
+#define SRAM_SCRATCH_SPACE_ADDR	CONFIG_SPL_STACK + 0x8
+
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START	(SRAM_SCRATCH_SPACE_ADDR)
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_END	(SRAM_SCRATCH_SPACE_ADDR + 0x200)
+#define KEYSTONE_SRAM_SCRATCH_SPACE_END		(TI_SRAM_SCRATCH_BOARD_EEPROM_END)
+
 /* UART Configuration */
 #define CONFIG_SYS_NS16550_MEM32
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
@@ -213,6 +219,10 @@
 /* EDMA3 */
 #define CONFIG_TI_EDMA3
 
+#define KERNEL_MTD_PARTS						\
+	"mtdparts="							\
+	SPI_MTD_PARTS
+
 #define DEFAULT_FW_INITRAMFS_BOOT_ENV					\
 	"name_fw_rd=k2-fw-initrd.cpio.gz\0"				\
 	"set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0"		\
@@ -269,7 +279,8 @@
 		"sf write ${loadaddr} 0 ${filesize}\0"		\
 	"burn_uboot_nand=nand erase 0 0x100000; "			\
 		"nand write ${loadaddr} 0 ${filesize}\0"		\
-	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0"	\
+	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1 "	\
+		KERNEL_MTD_PARTS					\
 	"args_net=setenv bootargs ${bootargs} rootfstype=nfs "		\
 		"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root},"	\
 		"${nfs_options} ip=dhcp\0"				\
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index d07cb9f..b85db50 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -104,6 +104,7 @@
 	"run distro_bootcmd"
 
 #include <config_distro_bootcmd.h>
+#include <environment/ti/mmc.h>
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 7fb1bb6..d45baab 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -42,7 +42,7 @@
  * Hardware drivers
  */
 #define CONFIG_SYS_NS16550_CLK		48000000
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
+#if !defined(CONFIG_DM_SERIAL)
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
 #endif
@@ -58,6 +58,8 @@
 #define DFUARGS
 #endif
 
+#include <environment/ti/mmc.h>
+
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
@@ -160,14 +162,8 @@
 #define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
 #endif
 
-/*
- * Disable MMC DM for SPL build and can be re-enabled after adding
- * DM support in SPL
- */
 #ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_MMC
 #undef CONFIG_TIMER
-#undef CONFIG_DM_ETH
 #endif
 
 #endif /* __CONFIG_TI_OMAP5_COMMON_H */
diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h
index c398e07..5228528 100644
--- a/include/configs/tinker_rk3288.h
+++ b/include/configs/tinker_rk3288.h
@@ -16,7 +16,7 @@
 	func(MMC, mmc, 1)
 
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_DEV 1
 
 #define CONFIG_SYS_WHITE_ON_BLACK
 
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index e72332c..1bfc438 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -349,8 +349,6 @@
 	"panicboot=echo No boot device !!! reset\0"                            \
 	TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS                                      \
 
-#define CONFIG_STACKSIZE		(128u * SZ_1K)
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
index 1d737cc..c6f39c3 100644
--- a/include/configs/udoo_neo.h
+++ b/include/configs/udoo_neo.h
@@ -69,7 +69,6 @@
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000)
-#define CONFIG_STACKSIZE		SZ_128K
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index ee90045..3e7dc9b 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -209,12 +209,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x80010000
 #define CONFIG_SYS_MEMTEST_END		0x87C00000
 
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
-
 /* Physical memory map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			(0x80000000)
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index ade5c27..9a517a9 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h
@@ -33,8 +33,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000)
 
-#define CONFIG_STACKSIZE		SZ_128K
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/warp.h b/include/configs/warp.h
index 865f2ac..5274b27 100644
--- a/include/configs/warp.h
+++ b/include/configs/warp.h
@@ -35,8 +35,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + SZ_256M)
 
-#define CONFIG_STACKSIZE		SZ_128K
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index b3e1f2e..23b6eae 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -85,8 +85,6 @@
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 #define CONFIG_SYS_HZ			1000
 
-#define CONFIG_STACKSIZE		SZ_128K
-
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index 3f837e8..f546c38 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -119,13 +119,6 @@
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
 /*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
-
-/*
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS	1
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index f7796cf..d69e609 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -16,7 +16,6 @@
  * (easy to change)
  */
 #define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_ZBOOT_32
 #define CONFIG_PHYSMEM
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 #define CONFIG_LAST_STAGE_INIT
diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h
index 5169504..b1aa579 100644
--- a/include/configs/xtfpga.h
+++ b/include/configs/xtfpga.h
@@ -66,7 +66,6 @@
 # define CONFIG_SYS_MONITOR_LEN		0x00040000	/* 256KB */
 #endif
 
-#define CONFIG_SYS_STACKSIZE		(512 << 10)	/* stack 512KB */
 #define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* heap  256KB */
 
 /* Linux boot param area in RAM (used only when booting linux) */
@@ -110,7 +109,6 @@
 /* U-Boot general configuration */
 /*==============================*/
 
-#undef	CONFIG_USE_IRQ			/* Keep it simple, poll only */
 #define CONFIG_BOARD_POSTCLK_INIT
 #define CONFIG_MISC_INIT_R
 
diff --git a/include/debug_uart.h b/include/debug_uart.h
index 0d640b9..2980ae6 100644
--- a/include/debug_uart.h
+++ b/include/debug_uart.h
@@ -115,17 +115,23 @@ void printhex8(uint value);
  * Now define some functions - this should be inserted into the serial driver
  */
 #define DEBUG_UART_FUNCS \
-	void printch(int ch) \
+\
+	static inline void _printch(int ch) \
 	{ \
 		if (ch == '\n') \
 			_debug_uart_putc('\r'); \
 		_debug_uart_putc(ch); \
 	} \
 \
+	void printch(int ch) \
+	{ \
+		_printch(ch); \
+	} \
+\
 	void printascii(const char *str) \
 	{ \
 		while (*str) \
-			printch(*str++); \
+			_printch(*str++); \
 	} \
 \
 	static inline void printhex1(uint digit) \
diff --git a/include/div64.h b/include/div64.h
index d833144..cecb232 100644
--- a/include/div64.h
+++ b/include/div64.h
@@ -4,13 +4,16 @@
  * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
  * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
  *
+ * Optimization for constant divisors on 32-bit machines:
+ * Copyright (C) 2006-2015 Nicolas Pitre
+ *
  * The semantics of do_div() are:
  *
  * uint32_t do_div(uint64_t *n, uint32_t base)
  * {
- *	uint32_t remainder = *n % base;
- *	*n = *n / base;
- *	return remainder;
+ * 	uint32_t remainder = *n % base;
+ * 	*n = *n / base;
+ * 	return remainder;
  * }
  *
  * NOTE: macro parameter n is evaluated multiple times,
@@ -18,8 +21,182 @@
  */
 
 #include <linux/types.h>
+#include <linux/compiler.h>
+
+#if BITS_PER_LONG == 64
+
+# define do_div(n,base) ({					\
+	uint32_t __base = (base);				\
+	uint32_t __rem;						\
+	__rem = ((uint64_t)(n)) % __base;			\
+	(n) = ((uint64_t)(n)) / __base;				\
+	__rem;							\
+ })
+
+#elif BITS_PER_LONG == 32
+
+#include <linux/log2.h>
+
+/*
+ * If the divisor happens to be constant, we determine the appropriate
+ * inverse at compile time to turn the division into a few inline
+ * multiplications which ought to be much faster. And yet only if compiling
+ * with a sufficiently recent gcc version to perform proper 64-bit constant
+ * propagation.
+ *
+ * (It is unfortunate that gcc doesn't perform all this internally.)
+ */
+
+#ifndef __div64_const32_is_OK
+#define __div64_const32_is_OK (__GNUC__ >= 4)
+#endif
+
+#define __div64_const32(n, ___b)					\
+({									\
+	/*								\
+	 * Multiplication by reciprocal of b: n / b = n * (p / b) / p	\
+	 *								\
+	 * We rely on the fact that most of this code gets optimized	\
+	 * away at compile time due to constant propagation and only	\
+	 * a few multiplication instructions should remain.		\
+	 * Hence this monstrous macro (static inline doesn't always	\
+	 * do the trick here).						\
+	 */								\
+	uint64_t ___res, ___x, ___t, ___m, ___n = (n);			\
+	uint32_t ___p, ___bias;						\
+									\
+	/* determine MSB of b */					\
+	___p = 1 << ilog2(___b);					\
+									\
+	/* compute m = ((p << 64) + b - 1) / b */			\
+	___m = (~0ULL / ___b) * ___p;					\
+	___m += (((~0ULL % ___b + 1) * ___p) + ___b - 1) / ___b;	\
+									\
+	/* one less than the dividend with highest result */		\
+	___x = ~0ULL / ___b * ___b - 1;					\
+									\
+	/* test our ___m with res = m * x / (p << 64) */		\
+	___res = ((___m & 0xffffffff) * (___x & 0xffffffff)) >> 32;	\
+	___t = ___res += (___m & 0xffffffff) * (___x >> 32);		\
+	___res += (___x & 0xffffffff) * (___m >> 32);			\
+	___t = (___res < ___t) ? (1ULL << 32) : 0;			\
+	___res = (___res >> 32) + ___t;					\
+	___res += (___m >> 32) * (___x >> 32);				\
+	___res /= ___p;							\
+									\
+	/* Now sanitize and optimize what we've got. */			\
+	if (~0ULL % (___b / (___b & -___b)) == 0) {			\
+		/* special case, can be simplified to ... */		\
+		___n /= (___b & -___b);					\
+		___m = ~0ULL / (___b / (___b & -___b));			\
+		___p = 1;						\
+		___bias = 1;						\
+	} else if (___res != ___x / ___b) {				\
+		/*							\
+		 * We can't get away without a bias to compensate	\
+		 * for bit truncation errors.  To avoid it we'd need an	\
+		 * additional bit to represent m which would overflow	\
+		 * a 64-bit variable.					\
+		 *							\
+		 * Instead we do m = p / b and n / b = (n * m + m) / p.	\
+		 */							\
+		___bias = 1;						\
+		/* Compute m = (p << 64) / b */				\
+		___m = (~0ULL / ___b) * ___p;				\
+		___m += ((~0ULL % ___b + 1) * ___p) / ___b;		\
+	} else {							\
+		/*							\
+		 * Reduce m / p, and try to clear bit 31 of m when	\
+		 * possible, otherwise that'll need extra overflow	\
+		 * handling later.					\
+		 */							\
+		uint32_t ___bits = -(___m & -___m);			\
+		___bits |= ___m >> 32;					\
+		___bits = (~___bits) << 1;				\
+		/*							\
+		 * If ___bits == 0 then setting bit 31 is  unavoidable.	\
+		 * Simply apply the maximum possible reduction in that	\
+		 * case. Otherwise the MSB of ___bits indicates the	\
+		 * best reduction we should apply.			\
+		 */							\
+		if (!___bits) {						\
+			___p /= (___m & -___m);				\
+			___m /= (___m & -___m);				\
+		} else {						\
+			___p >>= ilog2(___bits);			\
+			___m >>= ilog2(___bits);			\
+		}							\
+		/* No bias needed. */					\
+		___bias = 0;						\
+	}								\
+									\
+	/*								\
+	 * Now we have a combination of 2 conditions:			\
+	 *								\
+	 * 1) whether or not we need to apply a bias, and		\
+	 *								\
+	 * 2) whether or not there might be an overflow in the cross	\
+	 *    product determined by (___m & ((1 << 63) | (1 << 31))).	\
+	 *								\
+	 * Select the best way to do (m_bias + m * n) / (1 << 64).	\
+	 * From now on there will be actual runtime code generated.	\
+	 */								\
+	___res = __arch_xprod_64(___m, ___n, ___bias);			\
+									\
+	___res /= ___p;							\
+})
+
+#ifndef __arch_xprod_64
+/*
+ * Default C implementation for __arch_xprod_64()
+ *
+ * Prototype: uint64_t __arch_xprod_64(const uint64_t m, uint64_t n, bool bias)
+ * Semantic:  retval = ((bias ? m : 0) + m * n) >> 64
+ *
+ * The product is a 128-bit value, scaled down to 64 bits.
+ * Assuming constant propagation to optimize away unused conditional code.
+ * Architectures may provide their own optimized assembly implementation.
+ */
+static inline uint64_t __arch_xprod_64(const uint64_t m, uint64_t n, bool bias)
+{
+	uint32_t m_lo = m;
+	uint32_t m_hi = m >> 32;
+	uint32_t n_lo = n;
+	uint32_t n_hi = n >> 32;
+	uint64_t res, tmp;
+
+	if (!bias) {
+		res = ((uint64_t)m_lo * n_lo) >> 32;
+	} else if (!(m & ((1ULL << 63) | (1ULL << 31)))) {
+		/* there can't be any overflow here */
+		res = (m + (uint64_t)m_lo * n_lo) >> 32;
+	} else {
+		res = m + (uint64_t)m_lo * n_lo;
+		tmp = (res < m) ? (1ULL << 32) : 0;
+		res = (res >> 32) + tmp;
+	}
+
+	if (!(m & ((1ULL << 63) | (1ULL << 31)))) {
+		/* there can't be any overflow here */
+		res += (uint64_t)m_lo * n_hi;
+		res += (uint64_t)m_hi * n_lo;
+		res >>= 32;
+	} else {
+		tmp = res += (uint64_t)m_lo * n_hi;
+		res += (uint64_t)m_hi * n_lo;
+		tmp = (res < tmp) ? (1ULL << 32) : 0;
+		res = (res >> 32) + tmp;
+	}
 
+	res += (uint64_t)m_hi * n_hi;
+
+	return res;
+}
+#endif
+
+#ifndef __div64_32
 extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
+#endif
 
 /* The unnecessary pointer compare is there
  * to check for type safety (n must be 64bit)
@@ -28,14 +205,32 @@ extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
 	uint32_t __base = (base);			\
 	uint32_t __rem;					\
 	(void)(((typeof((n)) *)0) == ((uint64_t *)0));	\
-	if (((n) >> 32) == 0) {			\
+	if (__builtin_constant_p(__base) &&		\
+	    is_power_of_2(__base)) {			\
+		__rem = (n) & (__base - 1);		\
+		(n) >>= ilog2(__base);			\
+	} else if (__div64_const32_is_OK &&		\
+		   __builtin_constant_p(__base) &&	\
+		   __base != 0) {			\
+		uint32_t __res_lo, __n_lo = (n);	\
+		(n) = __div64_const32(n, __base);	\
+		/* the remainder can be computed with 32-bit regs */ \
+		__res_lo = (n);				\
+		__rem = __n_lo - __res_lo * __base;	\
+	} else if (likely(((n) >> 32) == 0)) {		\
 		__rem = (uint32_t)(n) % __base;		\
 		(n) = (uint32_t)(n) / __base;		\
-	} else						\
+	} else 						\
 		__rem = __div64_32(&(n), __base);	\
 	__rem;						\
  })
 
+#else /* BITS_PER_LONG == ?? */
+
+# error do_div() does not yet support the C64
+
+#endif /* BITS_PER_LONG */
+
 /* Wrapper for do_div(). Doesn't modify dividend and returns
  * the result, not reminder.
  */
diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h
index 0bf8707..2cabc87 100644
--- a/include/dm/device-internal.h
+++ b/include/dm/device-internal.h
@@ -96,12 +96,13 @@ int device_probe(struct udevice *dev);
  * children are deactivated first.
  *
  * @dev: Pointer to device to remove
+ * @flags: Flags for selective device removal
  * @return 0 if OK, -ve on error (an error here is normally a very bad thing)
  */
 #if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
-int device_remove(struct udevice *dev);
+int device_remove(struct udevice *dev, uint flags);
 #else
-static inline int device_remove(struct udevice *dev) { return 0; }
+static inline int device_remove(struct udevice *dev, uint flags) { return 0; }
 #endif
 
 /**
diff --git a/include/dm/device.h b/include/dm/device.h
index 4e95fb7..079ec57 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -46,6 +46,32 @@ struct driver_info;
 
 #define DM_FLAG_OF_PLATDATA		(1 << 8)
 
+/*
+ * Call driver remove function to stop currently active DMA transfers or
+ * give DMA buffers back to the HW / controller. This may be needed for
+ * some drivers to do some final stage cleanup before the OS is called
+ * (U-Boot exit)
+ */
+#define DM_FLAG_ACTIVE_DMA		(1 << 9)
+
+/*
+ * One or multiple of these flags are passed to device_remove() so that
+ * a selective device removal as specified by the remove-stage and the
+ * driver flags can be done.
+ */
+enum {
+	/* Normal remove, remove all devices */
+	DM_REMOVE_NORMAL     = 1 << 0,
+
+	/* Remove devices with active DMA */
+	DM_REMOVE_ACTIVE_DMA = DM_FLAG_ACTIVE_DMA,
+
+	/* Add more use cases here */
+
+	/* Remove devices with any active flag */
+	DM_REMOVE_ACTIVE_ALL = DM_REMOVE_ACTIVE_DMA,
+};
+
 /**
  * struct udevice - An instance of a driver
  *
diff --git a/include/dm/root.h b/include/dm/root.h
index 3cf730d..058eb98 100644
--- a/include/dm/root.h
+++ b/include/dm/root.h
@@ -115,4 +115,20 @@ int dm_init(void);
  */
 int dm_uninit(void);
 
+#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
+/**
+ * dm_remove_devices_flags - Call remove function of all drivers with
+ *                           specific removal flags set to selectively
+ *                           remove drivers
+ *
+ * All devices with the matching flags set will be removed
+ *
+ * @flags: Flags for selective device removal
+ * @return 0 if OK, -ve on error
+ */
+int dm_remove_devices_flags(uint flags);
+#else
+static inline int dm_remove_devices_flags(uint flags) { return 0; }
+#endif
+
 #endif
diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
new file mode 100644
index 0000000..902abd4
--- /dev/null
+++ b/include/dw_hdmi.h
@@ -0,0 +1,486 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DW_HDMI_H
+#define _DW_HDMI_H
+
+#include <edid.h>
+
+#define HDMI_EDID_BLOCK_SIZE            128
+
+/* Identification Registers */
+#define HDMI_DESIGN_ID                          0x0000
+#define HDMI_REVISION_ID                        0x0001
+#define HDMI_PRODUCT_ID0                        0x0002
+#define HDMI_PRODUCT_ID1                        0x0003
+#define HDMI_CONFIG0_ID                         0x0004
+#define HDMI_CONFIG1_ID                         0x0005
+#define HDMI_CONFIG2_ID                         0x0006
+#define HDMI_CONFIG3_ID                         0x0007
+
+/* Interrupt Registers */
+#define HDMI_IH_FC_STAT0                        0x0100
+#define HDMI_IH_FC_STAT1                        0x0101
+#define HDMI_IH_FC_STAT2                        0x0102
+#define HDMI_IH_AS_STAT0                        0x0103
+#define HDMI_IH_PHY_STAT0                       0x0104
+#define HDMI_IH_I2CM_STAT0                      0x0105
+#define HDMI_IH_CEC_STAT0                       0x0106
+#define HDMI_IH_VP_STAT0                        0x0107
+#define HDMI_IH_I2CMPHY_STAT0                   0x0108
+#define HDMI_IH_AHBDMAAUD_STAT0                 0x0109
+
+#define HDMI_IH_MUTE_FC_STAT0                   0x0180
+#define HDMI_IH_MUTE_FC_STAT1                   0x0181
+#define HDMI_IH_MUTE_FC_STAT2                   0x0182
+#define HDMI_IH_MUTE_AS_STAT0                   0x0183
+#define HDMI_IH_MUTE_PHY_STAT0                  0x0184
+#define HDMI_IH_MUTE_I2CM_STAT0                 0x0185
+#define HDMI_IH_MUTE_CEC_STAT0                  0x0186
+#define HDMI_IH_MUTE_VP_STAT0                   0x0187
+#define HDMI_IH_MUTE_I2CMPHY_STAT0              0x0188
+#define HDMI_IH_MUTE_AHBDMAAUD_STAT0            0x0189
+#define HDMI_IH_MUTE                            0x01FF
+
+/* Video Sample Registers */
+#define HDMI_TX_INVID0                          0x0200
+#define HDMI_TX_INSTUFFING                      0x0201
+#define HDMI_TX_GYDATA0                         0x0202
+#define HDMI_TX_GYDATA1                         0x0203
+#define HDMI_TX_RCRDATA0                        0x0204
+#define HDMI_TX_RCRDATA1                        0x0205
+#define HDMI_TX_BCBDATA0                        0x0206
+#define HDMI_TX_BCBDATA1                        0x0207
+
+/* Video Packetizer Registers */
+#define HDMI_VP_STATUS                          0x0800
+#define HDMI_VP_PR_CD                           0x0801
+#define HDMI_VP_STUFF                           0x0802
+#define HDMI_VP_REMAP                           0x0803
+#define HDMI_VP_CONF                            0x0804
+#define HDMI_VP_STAT                            0x0805
+#define HDMI_VP_INT                             0x0806
+#define HDMI_VP_MASK                            0x0807
+#define HDMI_VP_POL                             0x0808
+
+/* Frame Composer Registers */
+#define HDMI_FC_INVIDCONF                       0x1000
+#define HDMI_FC_INHACTV0                        0x1001
+#define HDMI_FC_INHACTV1                        0x1002
+#define HDMI_FC_INHBLANK0                       0x1003
+#define HDMI_FC_INHBLANK1                       0x1004
+#define HDMI_FC_INVACTV0                        0x1005
+#define HDMI_FC_INVACTV1                        0x1006
+#define HDMI_FC_INVBLANK                        0x1007
+#define HDMI_FC_HSYNCINDELAY0                   0x1008
+#define HDMI_FC_HSYNCINDELAY1                   0x1009
+#define HDMI_FC_HSYNCINWIDTH0                   0x100A
+#define HDMI_FC_HSYNCINWIDTH1                   0x100B
+#define HDMI_FC_VSYNCINDELAY                    0x100C
+#define HDMI_FC_VSYNCINWIDTH                    0x100D
+#define HDMI_FC_INFREQ0                         0x100E
+#define HDMI_FC_INFREQ1                         0x100F
+#define HDMI_FC_INFREQ2                         0x1010
+#define HDMI_FC_CTRLDUR                         0x1011
+#define HDMI_FC_EXCTRLDUR                       0x1012
+#define HDMI_FC_EXCTRLSPAC                      0x1013
+#define HDMI_FC_CH0PREAM                        0x1014
+#define HDMI_FC_CH1PREAM                        0x1015
+#define HDMI_FC_CH2PREAM                        0x1016
+#define HDMI_FC_AVICONF3                        0x1017
+#define HDMI_FC_GCP                             0x1018
+#define HDMI_FC_AVICONF0                        0x1019
+#define HDMI_FC_AVICONF1                        0x101A
+#define HDMI_FC_AVICONF2                        0x101B
+#define HDMI_FC_AVIVID                          0x101C
+#define HDMI_FC_AVIETB0                         0x101D
+#define HDMI_FC_AVIETB1                         0x101E
+#define HDMI_FC_AVISBB0                         0x101F
+#define HDMI_FC_AVISBB1                         0x1020
+#define HDMI_FC_AVIELB0                         0x1021
+#define HDMI_FC_AVIELB1                         0x1022
+#define HDMI_FC_AVISRB0                         0x1023
+#define HDMI_FC_AVISRB1                         0x1024
+#define HDMI_FC_AUDICONF0                       0x1025
+#define HDMI_FC_AUDICONF1                       0x1026
+#define HDMI_FC_AUDICONF2                       0x1027
+#define HDMI_FC_AUDICONF3                       0x1028
+#define HDMI_FC_VSDIEEEID0                      0x1029
+#define HDMI_FC_VSDSIZE                         0x102A
+
+/* HDMI Source PHY Registers */
+#define HDMI_PHY_CONF0                          0x3000
+#define HDMI_PHY_TST0                           0x3001
+#define HDMI_PHY_TST1                           0x3002
+#define HDMI_PHY_TST2                           0x3003
+#define HDMI_PHY_STAT0                          0x3004
+#define HDMI_PHY_INT0                           0x3005
+#define HDMI_PHY_MASK0                          0x3006
+#define HDMI_PHY_POL0                           0x3007
+
+/* HDMI Master PHY Registers */
+#define HDMI_PHY_I2CM_SLAVE_ADDR                0x3020
+#define HDMI_PHY_I2CM_ADDRESS_ADDR              0x3021
+#define HDMI_PHY_I2CM_DATAO_1_ADDR              0x3022
+#define HDMI_PHY_I2CM_DATAO_0_ADDR              0x3023
+#define HDMI_PHY_I2CM_DATAI_1_ADDR              0x3024
+#define HDMI_PHY_I2CM_DATAI_0_ADDR              0x3025
+#define HDMI_PHY_I2CM_OPERATION_ADDR            0x3026
+#define HDMI_PHY_I2CM_INT_ADDR                  0x3027
+#define HDMI_PHY_I2CM_CTLINT_ADDR               0x3028
+#define HDMI_PHY_I2CM_DIV_ADDR                  0x3029
+#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR             0x302a
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR        0x302b
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR        0x302c
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR        0x302d
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR        0x302e
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR        0x302f
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR        0x3030
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR        0x3031
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR        0x3032
+
+/* Audio Sampler Registers */
+#define HDMI_AUD_CONF0                          0x3100
+#define HDMI_AUD_CONF1                          0x3101
+#define HDMI_AUD_INT                            0x3102
+#define HDMI_AUD_CONF2                          0x3103
+#define HDMI_AUD_INT1                           0x3104
+#define HDMI_AUD_N1                             0x3200
+#define HDMI_AUD_N2                             0x3201
+#define HDMI_AUD_N3                             0x3202
+#define HDMI_AUD_CTS1                           0x3203
+#define HDMI_AUD_CTS2                           0x3204
+#define HDMI_AUD_CTS3                           0x3205
+#define HDMI_AUD_INPUTCLKFS                     0x3206
+#define HDMI_AUD_SPDIFINT			0x3302
+#define HDMI_AUD_CONF0_HBR                      0x3400
+#define HDMI_AUD_HBR_STATUS                     0x3401
+#define HDMI_AUD_HBR_INT                        0x3402
+#define HDMI_AUD_HBR_POL                        0x3403
+#define HDMI_AUD_HBR_MASK                       0x3404
+
+/* Main Controller Registers */
+#define HDMI_MC_SFRDIV                          0x4000
+#define HDMI_MC_CLKDIS                          0x4001
+#define HDMI_MC_SWRSTZ                          0x4002
+#define HDMI_MC_OPCTRL                          0x4003
+#define HDMI_MC_FLOWCTRL                        0x4004
+#define HDMI_MC_PHYRSTZ                         0x4005
+#define HDMI_MC_LOCKONCLOCK                     0x4006
+#define HDMI_MC_HEACPHY_RST                     0x4007
+
+/* I2C Master Registers (E-DDC) */
+#define HDMI_I2CM_SLAVE                         0x7E00
+#define HDMI_I2CM_ADDRESS                       0x7E01
+#define HDMI_I2CM_DATAO                         0x7E02
+#define HDMI_I2CM_DATAI                         0x7E03
+#define HDMI_I2CM_OPERATION                     0x7E04
+#define HDMI_I2CM_INT                           0x7E05
+#define HDMI_I2CM_CTLINT                        0x7E06
+#define HDMI_I2CM_DIV                           0x7E07
+#define HDMI_I2CM_SEGADDR                       0x7E08
+#define HDMI_I2CM_SOFTRSTZ                      0x7E09
+#define HDMI_I2CM_SEGPTR                        0x7E0A
+#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR            0x7E0B
+#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR            0x7E0C
+#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR            0x7E0D
+#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR            0x7E0E
+#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR            0x7E0F
+#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR            0x7E10
+#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR            0x7E11
+#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR            0x7E12
+#define HDMI_I2CM_BUF0                          0x7E20
+
+enum {
+	/* HDMI PHY registers define */
+	PHY_OPMODE_PLLCFG = 0x06,
+	PHY_CKCALCTRL = 0x05,
+	PHY_CKSYMTXCTRL = 0x09,
+	PHY_VLEVCTRL = 0x0e,
+	PHY_PLLCURRCTRL = 0x10,
+	PHY_PLLPHBYCTRL = 0x13,
+	PHY_PLLGMPCTRL = 0x15,
+	PHY_PLLCLKBISTPHASE = 0x17,
+	PHY_TXTERM = 0x19,
+
+	/* ih_phy_stat0 field values */
+	HDMI_IH_PHY_STAT0_HPD = 0x1,
+
+	/* ih_mute field values */
+	HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
+	HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
+
+	/* tx_invid0 field values */
+	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
+	HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
+	HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
+
+	/* tx_instuffing field values */
+	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
+	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
+	HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
+
+	/* vp_pr_cd field values */
+	HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
+	HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
+	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
+	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
+
+	/* vp_stuff field values */
+	HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
+	HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
+	HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
+	HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
+	HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
+	HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
+	HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
+	HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
+
+	/* vp_conf field values */
+	HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
+	HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
+	HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
+	HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_PR_EN_MASK = 0x10,
+	HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
+	HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
+	HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
+	HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
+
+	/* vp_remap field values */
+	HDMI_VP_REMAP_YCC422_16BIT = 0x0,
+
+	/* fc_invidconf field values */
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
+	HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
+	HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
+	HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
+
+
+	/* fc_aviconf0-fc_aviconf3 field values */
+	HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
+	HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
+	HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
+	HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
+	HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
+	HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
+	HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
+	HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
+	HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
+	HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
+	HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
+	HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
+	HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
+
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
+	HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
+	HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
+	HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
+	HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
+	HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
+
+	HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
+	HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
+	HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
+	HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
+	HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
+	HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
+	HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
+	HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
+	HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
+	HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
+	HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
+	HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
+
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
+	HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
+	HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
+	HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
+
+	/* fc_gcp field values*/
+	HDMI_FC_GCP_SET_AVMUTE = 0x02,
+	HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
+
+	/* phy_conf0 field values */
+	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
+	HDMI_PHY_CONF0_PDZ_OFFSET = 7,
+	HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
+	HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
+	HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
+	HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
+	HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
+	HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
+	HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
+	HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
+	HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
+	HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
+	HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
+	HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
+
+	/* phy_tst0 field values */
+	HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
+	HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
+
+	/* phy_stat0 field values */
+	HDMI_PHY_HPD = 0x02,
+	HDMI_PHY_TX_PHY_LOCK = 0x01,
+
+	/* phy_i2cm_slave_addr field values */
+	HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
+
+	/* phy_i2cm_operation_addr field values */
+	HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
+
+	/* hdmi_phy_i2cm_int_addr */
+	HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
+
+	/* hdmi_phy_i2cm_ctlint_addr */
+	HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
+	HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
+
+	/* aud_conf0 field values */
+	HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
+	HDMI_AUD_CONF0_I2S_SELECT = 0x20,
+	HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
+	HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
+	HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
+	HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
+
+	/* aud_conf0 field values */
+	HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
+	HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
+
+	/* aud_n3 field values */
+	HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
+	HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
+
+	/* aud_cts3 field values */
+	HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
+	HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
+	HDMI_AUD_CTS3_N_SHIFT_1 = 0,
+	HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
+	HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
+	HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
+	HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
+	HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
+	HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
+	HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
+
+	/* aud_inputclkfs filed values */
+	HDMI_AUD_INPUTCLKFS_128 = 0x0,
+
+	/* mc_clkdis field values */
+	HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
+	HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
+	HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
+
+	/* mc_swrstz field values */
+	HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
+	HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
+
+	/* mc_flowctrl field values */
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
+
+	/* mc_phyrstz field values */
+	HDMI_MC_PHYRSTZ_ASSERT = 0x0,
+	HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
+
+	/* mc_heacphy_rst field values */
+	HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
+
+	/* i2cm filed values */
+	HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
+	HDMI_I2CM_SEGADDR_DDC = 0x30,
+	HDMI_I2CM_OP_RD8_EXT = 0x2,
+	HDMI_I2CM_OP_RD8 = 0x1,
+	HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
+	HDMI_I2CM_DIV_FAST_MODE = 0x8,
+	HDMI_I2CM_DIV_STD_MODE = 0x0,
+	HDMI_I2CM_SOFTRSTZ_MASK = 0x1,
+};
+
+struct hdmi_mpll_config {
+	u64 mpixelclock;
+	/* Mode of Operation and PLL Dividers Control Register */
+	u32 cpce;
+	/* PLL Gmp Control Register */
+	u32 gmp;
+	/* PLL Current Control Register */
+	u32 curr;
+};
+
+struct hdmi_phy_config {
+	u64 mpixelclock;
+	u32 sym_ctr;    /* clock symbol and transmitter control */
+	u32 term;       /* transmission termination value */
+	u32 vlev_ctr;   /* voltage level control */
+};
+
+struct dw_hdmi {
+	ulong ioaddr;
+	const struct hdmi_mpll_config *mpll_cfg;
+	const struct hdmi_phy_config *phy_cfg;
+	u8 i2c_clk_high;
+	u8 i2c_clk_low;
+	u8 reg_io_width;
+
+	int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
+};
+
+int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock);
+int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi);
+void dw_hdmi_phy_init(struct dw_hdmi *hdmi);
+
+int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid);
+int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size);
+void dw_hdmi_init(struct dw_hdmi *hdmi);
+
+#endif
diff --git a/include/environment.h b/include/environment.h
index b602e8a..6f94986 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -8,6 +8,8 @@
 #ifndef _ENVIRONMENT_H_
 #define _ENVIRONMENT_H_
 
+#include <linux/kconfig.h>
+
 /**************************************************************************
  *
  * The "environment" is stored as a list of '\0' terminated
diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h
new file mode 100644
index 0000000..b987f71
--- /dev/null
+++ b/include/environment/ti/mmc.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Environment variable definitions for MMC/SD on TI boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define DEFAULT_MMC_TI_ARGS \
+	"mmcdev=0\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"finduuid=part uuid mmc ${bootpart} uuid\0" \
+	"args_mmc=run finduuid;setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=PARTUUID=${uuid} rw " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
+	"bootenvfile=uEnv.txt\0" \
+	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \
+	"loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"envboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadbootscript; then " \
+				"run bootscript;" \
+			"else " \
+				"if run loadbootenv; then " \
+					"echo Loaded env from ${bootenvfile};" \
+					"run importbootenv;" \
+				"fi;" \
+				"if test -n $uenvcmd; then " \
+					"echo Running uenvcmd ...;" \
+					"run uenvcmd;" \
+				"fi;" \
+			"fi;" \
+		"fi;\0" \
+	"mmcloados=run args_mmc; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"setenv devnum ${mmcdev}; " \
+		"setenv devtype mmc; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadimage; then " \
+				"if test ${boot_fit} -eq 1; then " \
+					"run loadfit; " \
+				"else " \
+					"run mmcloados;" \
+				"fi;" \
+			"fi;" \
+		"fi;\0"
diff --git a/include/environment/ti/spi.h b/include/environment/ti/spi.h
new file mode 100644
index 0000000..18c857c
--- /dev/null
+++ b/include/environment/ti/spi.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Environment variable definitions for SPI on TI boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __TI_SPI_H
+#define __TI_SPI_H
+
+#define KEYSTONE_SPI0_MTD_PARTS "spi0.0:1m(u-boot-spl)ro,-(misc);\0"
+#define KEYSTONE_SPI1_MTD_PARTS "spi1.0:1m(u-boot-spl)ro,-(misc);\0"
+
+#endif
diff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h
index 6dc159d..8ae0fc0 100644
--- a/include/fsl-mc/ldpaa_wriop.h
+++ b/include/fsl-mc/ldpaa_wriop.h
@@ -68,4 +68,5 @@ phy_interface_t wriop_get_enet_if(int);
 void wriop_dpmac_disable(int);
 void wriop_dpmac_enable(int);
 phy_interface_t wriop_dpmac_enet_if(int, int);
+void wriop_init_dpmac_qsgmii(int, int);
 #endif	/* __LDPAA_WRIOP_H */
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index b8de46b..6a1f04b 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -477,4 +477,12 @@ typedef struct fixed_ddr_parm{
 	int max_freq;
 	fsl_ddr_cfg_regs_t *ddr_settings;
 } fixed_ddr_parm_t;
+
+/**
+ * fsl_initdram() - Set up the SDRAM
+ *
+ * @return 0 if OK, -ve on error
+ */
+int fsl_initdram(void);
+
 #endif
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index c350938..452c6df 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -40,8 +40,8 @@ struct fsl_secboot_img_hdr {
 		u8 num_srk;
 		u8 srk_sel;
 		u8 reserve;
-		u8 ie_flag;
 	} len_kr;
+	u8 ie_flag;
 
 	u32 uid_flag;
 
@@ -69,6 +69,11 @@ struct fsl_secboot_img_hdr {
 #define MAX_KEY_ENTRIES 8
 #endif
 
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+#define IE_FLAG_MASK 0x1
+#define SCRATCH_IE_LOW_ADR 13
+#define SCRATCH_IE_HIGH_ADR 14
+#endif
 
 #else /* CONFIG_ESBC_HDR_LS */
 
@@ -150,6 +155,10 @@ struct fsl_secboot_img_hdr {
 #define MAX_KEY_ENTRIES 4
 #endif
 
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+#define IE_FLAG_MASK 0xFFFFFFFF
+#endif
+
 #endif /* CONFIG_ESBC_HDR_LS */
 
 
@@ -202,6 +211,17 @@ struct fsl_secboot_sg_table {
 };
 #endif
 
+/* ESBC global structure.
+ * Data to be used across verification of different images.
+ * Stores follwoing Data:
+ * IE Table
+ */
+struct fsl_secboot_glb {
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+	uintptr_t ie_addr;
+	struct ie_key_info ie_tbl;
+#endif
+};
 /*
  * ESBC private structure.
  * Private structure used by ESBC to store following fields
@@ -213,7 +233,7 @@ struct fsl_secboot_sg_table {
  */
 struct fsl_secboot_img_priv {
 	uint32_t hdr_location;
-	u32 ie_addr;
+	uintptr_t ie_addr;
 	u32 key_len;
 	struct fsl_secboot_img_hdr hdr;
 
diff --git a/include/grlib/apbuart.h b/include/grlib/apbuart.h
deleted file mode 100644
index 1e1eb9a..0000000
--- a/include/grlib/apbuart.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* GRLIB APBUART definitions
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __GRLIB_APBUART_H__
-#define __GRLIB_APBUART_H__
-
-/* APBUART Register map */
-typedef struct {
-	volatile unsigned int data;
-	volatile unsigned int status;
-	volatile unsigned int ctrl;
-	volatile unsigned int scaler;
-} ambapp_dev_apbuart;
-
-/*
- *  The following defines the bits in the LEON UART Status Registers.
- */
-
-#define APBUART_STATUS_DR   0x00000001	/* Data Ready */
-#define APBUART_STATUS_TSE  0x00000002	/* TX Send Register Empty */
-#define APBUART_STATUS_THE  0x00000004	/* TX Hold Register Empty */
-#define APBUART_STATUS_BR   0x00000008	/* Break Error */
-#define APBUART_STATUS_OE   0x00000010	/* RX Overrun Error */
-#define APBUART_STATUS_PE   0x00000020	/* RX Parity Error */
-#define APBUART_STATUS_FE   0x00000040	/* RX Framing Error */
-#define APBUART_STATUS_ERR  0x00000078	/* Error Mask */
-
-/*
- *  The following defines the bits in the LEON UART Ctrl Registers.
- */
-
-#define APBUART_CTRL_RE     0x00000001	/* Receiver enable */
-#define APBUART_CTRL_TE     0x00000002	/* Transmitter enable */
-#define APBUART_CTRL_RI     0x00000004	/* Receiver interrupt enable */
-#define APBUART_CTRL_TI     0x00000008	/* Transmitter interrupt enable */
-#define APBUART_CTRL_PS     0x00000010	/* Parity select */
-#define APBUART_CTRL_PE     0x00000020	/* Parity enable */
-#define APBUART_CTRL_FL     0x00000040	/* Flow control enable */
-#define APBUART_CTRL_LB     0x00000080	/* Loop Back enable */
-#define APBUART_CTRL_DBG    (1<<11)	/* Debug Bit used by GRMON */
-
-#endif
diff --git a/include/grlib/gptimer.h b/include/grlib/gptimer.h
deleted file mode 100644
index 8b2b165..0000000
--- a/include/grlib/gptimer.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* GRLIB GPTIMER (General Purpose Timer) definitions
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __GRLIB_GPTIMER_H__
-#define __GRLIB_GPTIMER_H__
-
-typedef struct {
-	volatile unsigned int val;
-	volatile unsigned int rld;
-	volatile unsigned int ctrl;
-	volatile unsigned int unused;
-} ambapp_dev_gptimer_element;
-
-#define GPTIMER_CTRL_EN	0x1	/* Timer enable */
-#define GPTIMER_CTRL_RS	0x2	/* Timer reStart  */
-#define GPTIMER_CTRL_LD	0x4	/* Timer reLoad */
-#define GPTIMER_CTRL_IE	0x8	/* interrupt enable */
-#define GPTIMER_CTRL_IP	0x10	/* interrupt flag/pending */
-#define GPTIMER_CTRL_CH	0x20	/* Chain with previous timer */
-
-typedef struct {
-	volatile unsigned int scalar;
-	volatile unsigned int scalar_reload;
-	volatile unsigned int config;
-	volatile unsigned int unused;
-	volatile ambapp_dev_gptimer_element e[8];
-} ambapp_dev_gptimer;
-
-#endif
diff --git a/include/grlib/greth.h b/include/grlib/greth.h
deleted file mode 100644
index 89c1e49..0000000
--- a/include/grlib/greth.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Gaisler.com GRETH 10/100/1000 Ethernet MAC definitions
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __GRLIB_GRETH_H__
-#define __GRLIB_GRETH_H__
-
-#define GRETH_FD 0x10
-#define GRETH_RESET 0x40
-#define GRETH_MII_BUSY 0x8
-#define GRETH_MII_NVALID 0x10
-
-/* MII registers */
-#define GRETH_MII_EXTADV_1000FD 0x00000200
-#define GRETH_MII_EXTADV_1000HD 0x00000100
-#define GRETH_MII_EXTPRT_1000FD 0x00000800
-#define GRETH_MII_EXTPRT_1000HD 0x00000400
-
-#define GRETH_MII_100T4 0x00000200
-#define GRETH_MII_100TXFD 0x00000100
-#define GRETH_MII_100TXHD 0x00000080
-#define GRETH_MII_10FD 0x00000040
-#define GRETH_MII_10HD 0x00000020
-
-#define GRETH_BD_EN 0x800
-#define GRETH_BD_WR 0x1000
-#define GRETH_BD_IE 0x2000
-#define GRETH_BD_LEN 0x7FF
-
-#define GRETH_TXEN 0x1
-#define GRETH_INT_TX 0x8
-#define GRETH_TXI 0x4
-#define GRETH_TXBD_STATUS 0x0001C000
-#define GRETH_TXBD_MORE 0x20000
-#define GRETH_TXBD_IPCS 0x40000
-#define GRETH_TXBD_TCPCS 0x80000
-#define GRETH_TXBD_UDPCS 0x100000
-#define GRETH_TXBD_ERR_LC 0x10000
-#define GRETH_TXBD_ERR_UE 0x4000
-#define GRETH_TXBD_ERR_AL 0x8000
-#define GRETH_TXBD_NUM 128
-#define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1)
-#define GRETH_TX_BUF_SIZE 2048
-
-#define GRETH_INT_RX         0x4
-#define GRETH_RXEN           0x2
-#define GRETH_RXI            0x8
-#define GRETH_RXBD_STATUS    0xFFFFC000
-#define GRETH_RXBD_ERR_AE    0x4000
-#define GRETH_RXBD_ERR_FT    0x8000
-#define GRETH_RXBD_ERR_CRC   0x10000
-#define GRETH_RXBD_ERR_OE    0x20000
-#define GRETH_RXBD_ERR_LE    0x40000
-#define GRETH_RXBD_IP_DEC    0x80000
-#define GRETH_RXBD_IP_CSERR  0x100000
-#define GRETH_RXBD_UDP_DEC   0x200000
-#define GRETH_RXBD_UDP_CSERR 0x400000
-#define GRETH_RXBD_TCP_DEC   0x800000
-#define GRETH_RXBD_TCP_CSERR 0x1000000
-
-#define GRETH_RXBD_NUM 128
-#define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1)
-#define GRETH_RX_BUF_SIZE 2048
-
-/* Ethernet configuration registers */
-typedef struct _greth_regs {
-	volatile unsigned int control;
-	volatile unsigned int status;
-	volatile unsigned int esa_msb;
-	volatile unsigned int esa_lsb;
-	volatile unsigned int mdio;
-	volatile unsigned int tx_desc_p;
-	volatile unsigned int rx_desc_p;
-	volatile unsigned int edcl_ip;
-} greth_regs;
-
-/* Ethernet buffer descriptor */
-typedef struct _greth_bd {
-	volatile unsigned int stat;
-	unsigned int addr;	/* Buffer address not changed by HW */
-} greth_bd;
-
-#endif
diff --git a/include/grlib/irqmp.h b/include/grlib/irqmp.h
deleted file mode 100644
index 0354d5c..0000000
--- a/include/grlib/irqmp.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* GRLIB IRQMP (IRQ Multi-processor controller) definitions
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __GRLIB_IRQMP_H__
-#define __GRLIB_IRQMP_H__
-
-typedef struct {
-	volatile unsigned int ilevel;
-	volatile unsigned int ipend;
-	volatile unsigned int iforce;
-	volatile unsigned int iclear;
-	volatile unsigned int mstatus;
-	volatile unsigned int notused[11];
-	volatile unsigned int cpu_mask[16];
-	volatile unsigned int cpu_force[16];
-} ambapp_dev_irqmp;
-
-#endif
diff --git a/include/i2c.h b/include/i2c.h
index d500445..cd7f61e 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -791,21 +791,6 @@ unsigned int i2c_set_bus_speed(unsigned int speed);
 
 unsigned int i2c_get_bus_speed(void);
 
-/*
- * i2c_reloc_fixup:
- *
- * Adjusts I2C pointers after U-Boot is relocated to DRAM
- */
-void i2c_reloc_fixup(void);
-#if defined(CONFIG_SYS_I2C_SOFT)
-void i2c_soft_init(void);
-void i2c_soft_active(void);
-void i2c_soft_tristate(void);
-int i2c_soft_read(void);
-void i2c_soft_sda(int bit);
-void i2c_soft_scl(int bit);
-void i2c_soft_delay(void);
-#endif
 #else
 
 /*
@@ -945,13 +930,6 @@ enum {
 	I2C_8, I2C_9, I2C_10,
 };
 
-/* Multi I2C busses handling */
-#ifdef CONFIG_SOFT_I2C_MULTI_BUS
-extern int get_multi_scl_pin(void);
-extern int get_multi_sda_pin(void);
-extern int multi_i2c_init(void);
-#endif
-
 /**
  * Get FDT values for i2c bus.
  *
diff --git a/include/image.h b/include/image.h
index 2372518..3f26f9b 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1256,7 +1256,8 @@ void android_print_contents(const struct andr_img_hdr *hdr);
  */
 int board_fit_config_name_match(const char *name);
 
-#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+#if defined(CONFIG_SPL_FIT_IMAGE_POST_PROCESS) || \
+	defined(CONFIG_FIT_IMAGE_POST_PROCESS)
 /**
  * board_fit_image_post_process() - Do any post-process on FIT binary data
  *
diff --git a/arch/x86/include/asm/init_helpers.h b/include/init_helpers.h
index ef05ac4..3efcfdd 100644
--- a/arch/x86/include/asm/init_helpers.h
+++ b/include/init_helpers.h
@@ -8,6 +8,11 @@
 #ifndef _INIT_HELPERS_H_
 #define _INIT_HELPERS_H_
 
+/**
+ * init_cache_f_r() - Turn on the cache in preparation for relocation
+ *
+ * @return 0 if OK, -ve on error
+ */
 int init_cache_f_r(void);
 
-#endif	/* !_INIT_HELPERS_H_ */
+#endif	/* _INIT_HELPERS_H_ */
diff --git a/include/initcall.h b/include/initcall.h
index 65f67dc..fe7e903 100644
--- a/include/initcall.h
+++ b/include/initcall.h
@@ -4,6 +4,11 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#ifndef __INITCALL_H
+#define __INITCALL_H
+
 typedef int (*init_fnc_t)(void);
 
 int initcall_run_list(const init_fnc_t init_sequence[]);
+
+#endif
diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index 1b2e491..576b15d 100644
--- a/include/linux/bitops.h
+++ b/include/linux/bitops.h
@@ -2,6 +2,7 @@
 #define _LINUX_BITOPS_H
 
 #include <asm/types.h>
+#include <asm-generic/bitsperlong.h>
 #include <linux/compiler.h>
 
 #define BIT(nr)			(1UL << (nr))
diff --git a/include/linux/math64.h b/include/linux/math64.h
index 6d760d7..08584c8 100644
--- a/include/linux/math64.h
+++ b/include/linux/math64.h
@@ -1,10 +1,15 @@
 #ifndef _LINUX_MATH64_H
 #define _LINUX_MATH64_H
 
+#include <div64.h>
+#include <linux/bitops.h>
 #include <linux/types.h>
 
 #if BITS_PER_LONG == 64
 
+#define div64_long(x, y) div64_s64((x), (y))
+#define div64_ul(x, y)   div64_u64((x), (y))
+
 /**
  * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
  *
@@ -27,6 +32,15 @@ static inline s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder)
 }
 
 /**
+ * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
+ */
+static inline u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder)
+{
+	*remainder = dividend % divisor;
+	return dividend / divisor;
+}
+
+/**
  * div64_u64 - unsigned 64bit divide with 64bit divisor
  */
 static inline u64 div64_u64(u64 dividend, u64 divisor)
@@ -34,8 +48,19 @@ static inline u64 div64_u64(u64 dividend, u64 divisor)
 	return dividend / divisor;
 }
 
+/**
+ * div64_s64 - signed 64bit divide with 64bit divisor
+ */
+static inline s64 div64_s64(s64 dividend, s64 divisor)
+{
+	return dividend / divisor;
+}
+
 #elif BITS_PER_LONG == 32
 
+#define div64_long(x, y) div_s64((x), (y))
+#define div64_ul(x, y)   div_u64((x), (y))
+
 #ifndef div_u64_rem
 static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
 {
@@ -48,10 +73,18 @@ static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
 extern s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder);
 #endif
 
+#ifndef div64_u64_rem
+extern u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder);
+#endif
+
 #ifndef div64_u64
 extern u64 div64_u64(u64 dividend, u64 divisor);
 #endif
 
+#ifndef div64_s64
+extern s64 div64_s64(s64 dividend, s64 divisor);
+#endif
+
 #endif /* BITS_PER_LONG */
 
 /**
@@ -82,4 +115,143 @@ static inline s64 div_s64(s64 dividend, s32 divisor)
 
 u32 iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder);
 
+static __always_inline u32
+__iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder)
+{
+	u32 ret = 0;
+
+	while (dividend >= divisor) {
+		/* The following asm() prevents the compiler from
+		   optimising this loop into a modulo operation.  */
+		asm("" : "+rm"(dividend));
+
+		dividend -= divisor;
+		ret++;
+	}
+
+	*remainder = dividend;
+
+	return ret;
+}
+
+#ifndef mul_u32_u32
+/*
+ * Many a GCC version messes this up and generates a 64x64 mult :-(
+ */
+static inline u64 mul_u32_u32(u32 a, u32 b)
+{
+	return (u64)a * b;
+}
+#endif
+
+#if defined(CONFIG_ARCH_SUPPORTS_INT128) && defined(__SIZEOF_INT128__)
+
+#ifndef mul_u64_u32_shr
+static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift)
+{
+	return (u64)(((unsigned __int128)a * mul) >> shift);
+}
+#endif /* mul_u64_u32_shr */
+
+#ifndef mul_u64_u64_shr
+static inline u64 mul_u64_u64_shr(u64 a, u64 mul, unsigned int shift)
+{
+	return (u64)(((unsigned __int128)a * mul) >> shift);
+}
+#endif /* mul_u64_u64_shr */
+
+#else
+
+#ifndef mul_u64_u32_shr
+static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift)
+{
+	u32 ah, al;
+	u64 ret;
+
+	al = a;
+	ah = a >> 32;
+
+	ret = mul_u32_u32(al, mul) >> shift;
+	if (ah)
+		ret += mul_u32_u32(ah, mul) << (32 - shift);
+
+	return ret;
+}
+#endif /* mul_u64_u32_shr */
+
+#ifndef mul_u64_u64_shr
+static inline u64 mul_u64_u64_shr(u64 a, u64 b, unsigned int shift)
+{
+	union {
+		u64 ll;
+		struct {
+#ifdef __BIG_ENDIAN
+			u32 high, low;
+#else
+			u32 low, high;
+#endif
+		} l;
+	} rl, rm, rn, rh, a0, b0;
+	u64 c;
+
+	a0.ll = a;
+	b0.ll = b;
+
+	rl.ll = mul_u32_u32(a0.l.low, b0.l.low);
+	rm.ll = mul_u32_u32(a0.l.low, b0.l.high);
+	rn.ll = mul_u32_u32(a0.l.high, b0.l.low);
+	rh.ll = mul_u32_u32(a0.l.high, b0.l.high);
+
+	/*
+	 * Each of these lines computes a 64-bit intermediate result into "c",
+	 * starting at bits 32-95.  The low 32-bits go into the result of the
+	 * multiplication, the high 32-bits are carried into the next step.
+	 */
+	rl.l.high = c = (u64)rl.l.high + rm.l.low + rn.l.low;
+	rh.l.low = c = (c >> 32) + rm.l.high + rn.l.high + rh.l.low;
+	rh.l.high = (c >> 32) + rh.l.high;
+
+	/*
+	 * The 128-bit result of the multiplication is in rl.ll and rh.ll,
+	 * shift it right and throw away the high part of the result.
+	 */
+	if (shift == 0)
+		return rl.ll;
+	if (shift < 64)
+		return (rl.ll >> shift) | (rh.ll << (64 - shift));
+	return rh.ll >> (shift & 63);
+}
+#endif /* mul_u64_u64_shr */
+
+#endif
+
+#ifndef mul_u64_u32_div
+static inline u64 mul_u64_u32_div(u64 a, u32 mul, u32 divisor)
+{
+	union {
+		u64 ll;
+		struct {
+#ifdef __BIG_ENDIAN
+			u32 high, low;
+#else
+			u32 low, high;
+#endif
+		} l;
+	} u, rl, rh;
+
+	u.ll = a;
+	rl.ll = mul_u32_u32(u.l.low, mul);
+	rh.ll = mul_u32_u32(u.l.high, mul) + rl.l.high;
+
+	/* Bits 32-63 of the result will be in rh.l.low. */
+	rl.l.high = do_div(rh.ll, divisor);
+
+	/* Bits 0-31 of the result will be in rl.l.low.	*/
+	do_div(rl.ll, divisor);
+
+	rl.l.high = rh.l.low;
+	return rl.ll;
+}
+#endif /* mul_u64_u32_div */
+
 #endif /* _LINUX_MATH64_H */
diff --git a/include/linux/usb/musb.h b/include/linux/usb/musb.h
index 075d222..e1fdab0 100644
--- a/include/linux/usb/musb.h
+++ b/include/linux/usb/musb.h
@@ -91,14 +91,6 @@ struct musb_hdrc_config {
 	u8		ram_bits;	/* ram address size */
 
 	struct musb_hdrc_eps_bits *eps_bits __deprecated;
-#ifdef CONFIG_BLACKFIN
-	/* A GPIO controlling VRSEL in Blackfin */
-	unsigned int	gpio_vrsel;
-	unsigned int	gpio_vrsel_active;
-	/* musb CLKIN in Blackfin in MHZ */
-	unsigned char   clkin;
-#endif
-
 };
 
 struct musb_hdrc_platform_data {
diff --git a/include/nand.h b/include/nand.h
index b6eb223..a865528 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -28,6 +28,7 @@
 #endif
 
 extern void nand_init(void);
+unsigned long nand_size(void);
 
 #include <linux/compat.h>
 #include <linux/mtd/mtd.h>
diff --git a/include/netdev.h b/include/netdev.h
index 7a211bc..8eb8b46 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -50,7 +50,6 @@ int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
 int ftgmac100_initialize(bd_t *bits);
 int ftmac100_initialize(bd_t *bits);
 int ftmac110_initialize(bd_t *bits);
-int greth_initialize(bd_t *bis);
 void gt6426x_eth_initialize(bd_t *bis);
 int ks8851_mll_initialize(u8 dev_num, int base_addr);
 int lan91c96_initialize(u8 dev_num, int base_addr);
diff --git a/include/phy.h b/include/phy.h
index 5477496..4f2094b 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -15,6 +15,8 @@
 #include <linux/ethtool.h>
 #include <linux/mdio.h>
 
+#define PHY_FIXED_ID		0xa5a55a5a
+
 #define PHY_MAX_ADDR 32
 
 #define PHY_FLAG_BROKEN_RESET	(1 << 0) /* soft reset not supported */
@@ -61,6 +63,9 @@ typedef enum {
 	PHY_INTERFACE_MODE_RGMII_TXID,
 	PHY_INTERFACE_MODE_RTBI,
 	PHY_INTERFACE_MODE_XGMII,
+	PHY_INTERFACE_MODE_XAUI,
+	PHY_INTERFACE_MODE_RXAUI,
+	PHY_INTERFACE_MODE_SFI,
 	PHY_INTERFACE_MODE_NONE,	/* Must be last */
 
 	PHY_INTERFACE_MODE_COUNT,
@@ -80,6 +85,9 @@ static const char *phy_interface_strings[] = {
 	[PHY_INTERFACE_MODE_RGMII_TXID]		= "rgmii-txid",
 	[PHY_INTERFACE_MODE_RTBI]		= "rtbi",
 	[PHY_INTERFACE_MODE_XGMII]		= "xgmii",
+	[PHY_INTERFACE_MODE_XAUI]		= "xaui",
+	[PHY_INTERFACE_MODE_RXAUI]		= "rxaui",
+	[PHY_INTERFACE_MODE_SFI]		= "sfi",
 	[PHY_INTERFACE_MODE_NONE]		= "",
 };
 
@@ -267,6 +275,7 @@ int phy_ti_init(void);
 int phy_vitesse_init(void);
 int phy_xilinx_init(void);
 int phy_mscc_init(void);
+int phy_fixed_init(void);
 
 int board_phy_config(struct phy_device *phydev);
 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
diff --git a/include/relocate.h b/include/relocate.h
new file mode 100644
index 0000000..0d4b27a
--- /dev/null
+++ b/include/relocate.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _RELOCATE_H_
+#define _RELOCATE_H_
+
+#include <common.h>
+
+/**
+ * copy_uboot_to_ram() - Copy U-Boot to its new relocated position
+ *
+ * @return 0 if OK, -ve on error
+ */
+int copy_uboot_to_ram(void);
+
+/**
+ * clear_bss() - Clear the BSS (Blocked Start by Symbol) segment
+ *
+ * This clears the memory used by global variables
+ *
+ * @return 0 if OK, -ve on error
+ */
+int clear_bss(void);
+
+/**
+ * do_elf_reloc_fixups() - Fix up ELF relocations in the relocated code
+ *
+ * This processes the relocation tables to ensure that the code can run in its
+ * new location.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int do_elf_reloc_fixups(void);
+
+#endif	/* _RELOCATE_H_ */
diff --git a/include/rtc.h b/include/rtc.h
index 69fe8d4..49142b6 100644
--- a/include/rtc.h
+++ b/include/rtc.h
@@ -128,6 +128,26 @@ int rtc_read8(struct udevice *dev, unsigned int reg);
 int rtc_write8(struct udevice *dev, unsigned int reg, int val);
 
 /**
+ * rtc_read16() - Read a 16-bit value from the RTC
+ *
+ * @dev:	Device to read from
+ * @reg:	Offset to start reading from
+ * @valuep:	Place to put the value that is read
+ * @return 0 if OK, -ve on error
+ */
+int rtc_read16(struct udevice *dev, unsigned int reg, u16 *valuep);
+
+/**
+ * rtc_write16() - Write a 16-bit value to the RTC
+ *
+ * @dev:	Device to write to
+ * @reg:	Register to start writing to
+ * @value:	Value to write
+ * @return 0 if OK, -ve on error
+ */
+int rtc_write16(struct udevice *dev, unsigned int reg, u16 value);
+
+/**
  * rtc_read32() - Read a 32-bit value from the RTC
  *
  * @dev:	Device to read from
diff --git a/include/tpm.h b/include/tpm.h
index 800f29c..f88388f 100644
--- a/include/tpm.h
+++ b/include/tpm.h
@@ -639,4 +639,16 @@ uint32_t tpm_get_permissions(uint32_t index, uint32_t *perm);
  */
 uint32_t tpm_flush_specific(uint32_t key_handle, uint32_t resource_type);
 
+#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
+/**
+ * Search for a key by usage AuthData and the hash of the parent's pub key.
+ *
+ * @param auth	        Usage auth of the key to search for
+ * @param pubkey_digest	SHA1 hash of the pub key structure of the key
+ * @param[out] handle	The handle of the key (Non-null iff found)
+ * @return 0 if key was found in TPM; != 0 if not.
+ */
+uint32_t tpm_find_key_sha1(const uint8_t auth[20], const uint8_t
+			   pubkey_digest[20], uint32_t *handle);
+#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
 #endif /* __TPM_H */
diff --git a/include/aes.h b/include/uboot_aes.h
index 6315c02..6315c02 100644
--- a/include/aes.h
+++ b/include/uboot_aes.h
diff --git a/include/xyzModem.h b/include/xyzModem.h
index 0eddbbc..4b667f7 100644
--- a/include/xyzModem.h
+++ b/include/xyzModem.h
@@ -44,9 +44,6 @@
 #define xyzModem_abort 2
 
 
-#ifdef REDBOOT
-extern getc_io_funcs_t xyzModem_io;
-#else
 #define CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT
 #define CYGACC_CALL_IF_SET_CONSOLE_COMM(x)
 
@@ -60,12 +57,8 @@ typedef struct {
     char *filename;
     int   mode;
     int   chan;
-#ifdef CYGPKG_REDBOOT_NETWORKING
-    struct sockaddr_in *server;
-#endif
 } connection_info_t;
 
-#endif
 
 
 int   xyzModem_stream_open(connection_info_t *info, int *err);
diff --git a/lib/Kconfig b/lib/Kconfig
index 65c0157..a0d5d92 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -52,6 +52,18 @@ config LIB_RAND
 	help
 	  This library provides pseudo-random number generator functions.
 
+config SPL_TINY_MEMSET
+	bool "Use a very small memset() in SPL"
+	help
+	  The faster memset() is the arch-specific one (if available) enabled
+	  by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get
+	  better performance by writing a word at a time. But in very
+	  size-constrained envrionments even this may be too big. Enable this
+	  option to reduce code size slightly at the cost of some speed.
+
+config RBTREE
+	bool
+
 source lib/dhry/Kconfig
 
 source lib/rsa/Kconfig
@@ -123,6 +135,8 @@ config LZ4
 	  frame format currently (2015) implemented in the Linux kernel
 	  (generated by 'lz4 -l'). The two formats are incompatible.
 
+config LZO
+	bool
 endmenu
 
 config ERRNO_STR
diff --git a/lib/aes.c b/lib/aes.c
index 9d7a0a1..d6144e6 100644
--- a/lib/aes.c
+++ b/lib/aes.c
@@ -27,7 +27,7 @@
 #else
 #include <string.h>
 #endif
-#include "aes.h"
+#include "uboot_aes.h"
 
 /* forward s-box */
 static const u8 sbox[256] = {
diff --git a/lib/bch.c b/lib/bch.c
index 147715a..ec53483 100644
--- a/lib/bch.c
+++ b/lib/bch.c
@@ -54,10 +54,27 @@
  * finite fields GF(2^q). In Rapport de recherche INRIA no 2829, 1996.
  */
 
+#ifndef USE_HOSTCC
 #include <common.h>
 #include <ubi_uboot.h>
 
 #include <linux/bitops.h>
+#else
+#include <errno.h>
+#include <endian.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+
+#undef cpu_to_be32
+#define cpu_to_be32 htobe32
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+#define kmalloc(size, flags)	malloc(size)
+#define kzalloc(size, flags)	calloc(1, size)
+#define kfree free
+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+#endif
+
 #include <asm/byteorder.h>
 #include <linux/bch.h>
 
@@ -95,6 +112,37 @@ struct gf_poly_deg1 {
 	unsigned int   c[2];
 };
 
+#ifdef USE_HOSTCC
+static int fls(int x)
+{
+	int r = 32;
+
+	if (!x)
+		return 0;
+	if (!(x & 0xffff0000u)) {
+		x <<= 16;
+		r -= 16;
+	}
+	if (!(x & 0xff000000u)) {
+		x <<= 8;
+		r -= 8;
+	}
+	if (!(x & 0xf0000000u)) {
+		x <<= 4;
+		r -= 4;
+	}
+	if (!(x & 0xc0000000u)) {
+		x <<= 2;
+		r -= 2;
+	}
+	if (!(x & 0x80000000u)) {
+		x <<= 1;
+		r -= 1;
+	}
+	return r;
+}
+#endif
+
 /*
  * same as encode_bch(), but process input data one byte at a time
  */
diff --git a/lib/div64.c b/lib/div64.c
index 319fca5..206f582 100644
--- a/lib/div64.c
+++ b/lib/div64.c
@@ -13,14 +13,19 @@
  *
  * Code generated for this function might be very inefficient
  * for some CPUs. __div64_32() can be overridden by linking arch-specific
- * assembly versions such as arch/powerpc/lib/div64.S and arch/sh/lib/div64.S.
+ * assembly versions such as arch/ppc/lib/div64.S and arch/sh/lib/div64.S
+ * or by defining a preprocessor macro in arch/include/asm/div64.h.
  */
 
-#include <div64.h>
-#include <linux/types.h>
-#include <linux/compiler.h>
+#include <linux/compat.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
 
-uint32_t notrace __div64_32(uint64_t *n, uint32_t base)
+/* Not needed on 64bit architectures */
+#if BITS_PER_LONG == 32
+
+#ifndef __div64_32
+uint32_t __attribute__((weak)) __div64_32(uint64_t *n, uint32_t base)
 {
 	uint64_t rem = *n;
 	uint64_t b = base;
@@ -52,3 +57,129 @@ uint32_t notrace __div64_32(uint64_t *n, uint32_t base)
 	*n = res;
 	return rem;
 }
+EXPORT_SYMBOL(__div64_32);
+#endif
+
+#ifndef div_s64_rem
+s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder)
+{
+	u64 quotient;
+
+	if (dividend < 0) {
+		quotient = div_u64_rem(-dividend, abs(divisor), (u32 *)remainder);
+		*remainder = -*remainder;
+		if (divisor > 0)
+			quotient = -quotient;
+	} else {
+		quotient = div_u64_rem(dividend, abs(divisor), (u32 *)remainder);
+		if (divisor < 0)
+			quotient = -quotient;
+	}
+	return quotient;
+}
+EXPORT_SYMBOL(div_s64_rem);
+#endif
+
+/**
+ * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
+ * @dividend:	64bit dividend
+ * @divisor:	64bit divisor
+ * @remainder:  64bit remainder
+ *
+ * This implementation is a comparable to algorithm used by div64_u64.
+ * But this operation, which includes math for calculating the remainder,
+ * is kept distinct to avoid slowing down the div64_u64 operation on 32bit
+ * systems.
+ */
+#ifndef div64_u64_rem
+u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder)
+{
+	u32 high = divisor >> 32;
+	u64 quot;
+
+	if (high == 0) {
+		u32 rem32;
+		quot = div_u64_rem(dividend, divisor, &rem32);
+		*remainder = rem32;
+	} else {
+		int n = 1 + fls(high);
+		quot = div_u64(dividend >> n, divisor >> n);
+
+		if (quot != 0)
+			quot--;
+
+		*remainder = dividend - quot * divisor;
+		if (*remainder >= divisor) {
+			quot++;
+			*remainder -= divisor;
+		}
+	}
+
+	return quot;
+}
+EXPORT_SYMBOL(div64_u64_rem);
+#endif
+
+/**
+ * div64_u64 - unsigned 64bit divide with 64bit divisor
+ * @dividend:	64bit dividend
+ * @divisor:	64bit divisor
+ *
+ * This implementation is a modified version of the algorithm proposed
+ * by the book 'Hacker's Delight'.  The original source and full proof
+ * can be found here and is available for use without restriction.
+ *
+ * 'http://www.hackersdelight.org/hdcodetxt/divDouble.c.txt'
+ */
+#ifndef div64_u64
+u64 div64_u64(u64 dividend, u64 divisor)
+{
+	u32 high = divisor >> 32;
+	u64 quot;
+
+	if (high == 0) {
+		quot = div_u64(dividend, divisor);
+	} else {
+		int n = 1 + fls(high);
+		quot = div_u64(dividend >> n, divisor >> n);
+
+		if (quot != 0)
+			quot--;
+		if ((dividend - quot * divisor) >= divisor)
+			quot++;
+	}
+
+	return quot;
+}
+EXPORT_SYMBOL(div64_u64);
+#endif
+
+/**
+ * div64_s64 - signed 64bit divide with 64bit divisor
+ * @dividend:	64bit dividend
+ * @divisor:	64bit divisor
+ */
+#ifndef div64_s64
+s64 div64_s64(s64 dividend, s64 divisor)
+{
+	s64 quot, t;
+
+	quot = div64_u64(abs(dividend), abs(divisor));
+	t = (dividend ^ divisor) >> 63;
+
+	return (quot ^ t) - t;
+}
+EXPORT_SYMBOL(div64_s64);
+#endif
+
+#endif /* BITS_PER_LONG == 32 */
+
+/*
+ * Iterative div/mod for use when dividend is not expected to be much
+ * bigger than divisor.
+ */
+u32 iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder)
+{
+	return __iter_div_u64_rem(dividend, divisor, remainder);
+}
+EXPORT_SYMBOL(iter_div_u64_rem);
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 81f47ef..1edfbf2 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -112,7 +112,7 @@ fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node,
 		return FDT_ADDR_T_NONE;
 	}
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_OF_LIBFDT)
+#if CONFIG_IS_ENABLED(OF_TRANSLATE)
 	if (translate)
 		addr = fdt_translate_address(blob, node, prop_addr);
 	else
diff --git a/lib/libfdt/fdt_overlay.c b/lib/libfdt/fdt_overlay.c
index 56cb70e..ceb9687 100644
--- a/lib/libfdt/fdt_overlay.c
+++ b/lib/libfdt/fdt_overlay.c
@@ -21,14 +21,14 @@
  */
 static uint32_t overlay_get_target_phandle(const void *fdto, int fragment)
 {
-	const uint32_t *val;
+	const fdt32_t *val;
 	int len;
 
 	val = fdt_getprop(fdto, fragment, "target", &len);
 	if (!val)
 		return 0;
 
-	if ((len != sizeof(*val)) || (*val == (uint32_t)-1))
+	if ((len != sizeof(*val)) || (fdt32_to_cpu(*val) == (uint32_t)-1))
 		return (uint32_t)-1;
 
 	return fdt32_to_cpu(*val);
@@ -99,7 +99,7 @@ static int overlay_get_target(const void *fdt, const void *fdto,
 static int overlay_phandle_add_offset(void *fdt, int node,
 				      const char *name, uint32_t delta)
 {
-	const uint32_t *val;
+	const fdt32_t *val;
 	uint32_t adj_val;
 	int len;
 
@@ -210,7 +210,7 @@ static int overlay_update_local_node_references(void *fdto,
 	int ret;
 
 	fdt_for_each_property_offset(fixup_prop, fdto, fixup_node) {
-		const uint32_t *fixup_val;
+		const fdt32_t *fixup_val;
 		const char *tree_val;
 		const char *name;
 		int fixup_len;
@@ -234,7 +234,8 @@ static int overlay_update_local_node_references(void *fdto,
 		}
 
 		for (i = 0; i < (fixup_len / sizeof(uint32_t)); i++) {
-			uint32_t adj_val, poffset;
+			fdt32_t adj_val;
+			uint32_t poffset;
 
 			poffset = fdt32_to_cpu(fixup_val[i]);
 
@@ -246,9 +247,7 @@ static int overlay_update_local_node_references(void *fdto,
 			 */
 			memcpy(&adj_val, tree_val + poffset, sizeof(adj_val));
 
-			adj_val = fdt32_to_cpu(adj_val);
-			adj_val += delta;
-			adj_val = cpu_to_fdt32(adj_val);
+			adj_val = cpu_to_fdt32(fdt32_to_cpu(adj_val) + delta);
 
 			ret = fdt_setprop_inplace_namelen_partial(fdto,
 								  tree_node,
@@ -272,7 +271,7 @@ static int overlay_update_local_node_references(void *fdto,
 
 		tree_child = fdt_subnode_offset(fdto, tree_node,
 						fixup_child_name);
-		if (ret == -FDT_ERR_NOTFOUND)
+		if (tree_child == -FDT_ERR_NOTFOUND)
 			return -FDT_ERR_BADOVERLAY;
 		if (tree_child < 0)
 			return tree_child;
@@ -356,6 +355,7 @@ static int overlay_fixup_one_phandle(void *fdt, void *fdto,
 {
 	const char *symbol_path;
 	uint32_t phandle;
+	fdt32_t phandle_prop;
 	int symbol_off, fixup_off;
 	int prop_len;
 
@@ -381,10 +381,11 @@ static int overlay_fixup_one_phandle(void *fdt, void *fdto,
 	if (fixup_off < 0)
 		return fixup_off;
 
-	phandle = cpu_to_fdt32(phandle);
+	phandle_prop = cpu_to_fdt32(phandle);
 	return fdt_setprop_inplace_namelen_partial(fdto, fixup_off,
 						   name, name_len, poffset,
-						   &phandle, sizeof(phandle));
+						   &phandle_prop,
+						   sizeof(phandle_prop));
 };
 
 /**
diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c
index 87d4030..80a3212 100644
--- a/lib/libfdt/fdt_rw.c
+++ b/lib/libfdt/fdt_rw.c
@@ -242,7 +242,8 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name,
 	if (err)
 		return err;
 
-	memcpy(prop->data, val, len);
+	if (len)
+		memcpy(prop->data, val, len);
 	return 0;
 }
 
diff --git a/lib/libfdt/fdt_strerror.c b/lib/libfdt/fdt_strerror.c
index 7f8e02b..f89004c 100644
--- a/lib/libfdt/fdt_strerror.c
+++ b/lib/libfdt/fdt_strerror.c
@@ -36,6 +36,9 @@ static struct fdt_errtabent fdt_errtable[] = {
 	FDT_ERRTABENT(FDT_ERR_BADVERSION),
 	FDT_ERRTABENT(FDT_ERR_BADSTRUCTURE),
 	FDT_ERRTABENT(FDT_ERR_BADLAYOUT),
+	FDT_ERRTABENT(FDT_ERR_INTERNAL),
+	FDT_ERRTABENT(FDT_ERR_BADNCELLS),
+	FDT_ERRTABENT(FDT_ERR_BADVALUE),
 	FDT_ERRTABENT(FDT_ERR_BADOVERLAY),
 	FDT_ERRTABENT(FDT_ERR_NOPHANDLES),
 };
diff --git a/lib/libfdt/setup.py b/lib/libfdt/setup.py
index 62e7bcc..845a0c2 100644
--- a/lib/libfdt/setup.py
+++ b/lib/libfdt/setup.py
@@ -27,7 +27,7 @@ libfdt_module = Extension(
     extra_compile_args =  cflags
 )
 
-sys.argv = [progname, '--quiet', 'build_ext', '--inplace']
+sys.argv = [progname, '--quiet', 'build_ext', '--inplace', '--force']
 
 setup (name = 'libfdt',
        version = '0.1',
diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig
index 09ec358..fde1ac1 100644
--- a/lib/rsa/Kconfig
+++ b/lib/rsa/Kconfig
@@ -1,6 +1,6 @@
 config RSA
 	bool "Use RSA Library"
-	select RSA_FREESCALE_EXP if FSL_CAAM
+	select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5
 	select RSA_SOFTWARE_EXP if !RSA_FREESCALE_EXP
 	help
 	  RSA support. This enables the RSA algorithm used for FIT image
@@ -29,7 +29,7 @@ config RSA_SOFTWARE_EXP
 
 config RSA_FREESCALE_EXP
 	bool "Enable RSA Modular Exponentiation with FSL crypto accelerator"
-	depends on DM && RSA && FSL_CAAM
+	depends on DM && RSA && FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5
 	help
 	Enables driver for RSA modular exponentiation using Freescale cryptographic
 	accelerator - CAAM.
diff --git a/lib/string.c b/lib/string.c
index 67d5f6a..c1a28c1 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -437,8 +437,10 @@ char *strswab(const char *s)
 void * memset(void * s,int c,size_t count)
 {
 	unsigned long *sl = (unsigned long *) s;
-	unsigned long cl = 0;
 	char *s8;
+
+#if !CONFIG_IS_ENABLED(TINY_MEMSET)
+	unsigned long cl = 0;
 	int i;
 
 	/* do it one word at a time (32 bits or 64 bits) while possible */
@@ -452,7 +454,7 @@ void * memset(void * s,int c,size_t count)
 			count -= sizeof(*sl);
 		}
 	}
-	/* fill 8 bits at a time */
+#endif	/* fill 8 bits at a time */
 	s8 = (char *)sl;
 	while (count--)
 		*s8++ = c;
diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 6def8f9..0b04813 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -12,6 +12,7 @@
 #include <common.h>
 #include <stdarg.h>
 #include <serial.h>
+#include <linux/ctype.h>
 
 struct printf_info {
 	char *bf;	/* Digit buffer */
@@ -52,6 +53,154 @@ static void div_out(struct printf_info *info, unsigned long *num,
 		out_dgt(info, dgt);
 }
 
+#ifdef CONFIG_SPL_NET_SUPPORT
+static void string(struct printf_info *info, char *s)
+{
+	char ch;
+
+	while ((ch = *s++))
+		out(info, ch);
+}
+
+static const char hex_asc[] = "0123456789abcdef";
+#define hex_asc_lo(x)	hex_asc[((x) & 0x0f)]
+#define hex_asc_hi(x)	hex_asc[((x) & 0xf0) >> 4]
+
+static inline char *pack_hex_byte(char *buf, u8 byte)
+{
+	*buf++ = hex_asc_hi(byte);
+	*buf++ = hex_asc_lo(byte);
+	return buf;
+}
+
+static void mac_address_string(struct printf_info *info, u8 *addr,
+				bool separator)
+{
+	/* (6 * 2 hex digits), 5 colons and trailing zero */
+	char mac_addr[6 * 3];
+	char *p = mac_addr;
+	int i;
+
+	for (i = 0; i < 6; i++) {
+		p = pack_hex_byte(p, addr[i]);
+		if (separator && i != 5)
+			*p++ = ':';
+	}
+	*p = '\0';
+
+	string(info, mac_addr);
+}
+
+static char *put_dec_trunc(char *buf, unsigned int q)
+{
+	unsigned int d3, d2, d1, d0;
+	d1 = (q >> 4) & 0xf;
+	d2 = (q >> 8) & 0xf;
+	d3 = (q >> 12);
+
+	d0 = 6 * (d3 + d2 + d1) + (q & 0xf);
+	q = (d0 * 0xcd) >> 11;
+	d0 = d0 - 10 * q;
+	*buf++ = d0 + '0'; /* least significant digit */
+	d1 = q + 9 * d3 + 5 * d2 + d1;
+	if (d1 != 0) {
+		q = (d1 * 0xcd) >> 11;
+		d1 = d1 - 10 * q;
+		*buf++ = d1 + '0'; /* next digit */
+
+		d2 = q + 2 * d2;
+		if ((d2 != 0) || (d3 != 0)) {
+			q = (d2 * 0xd) >> 7;
+			d2 = d2 - 10 * q;
+			*buf++ = d2 + '0'; /* next digit */
+
+			d3 = q + 4 * d3;
+			if (d3 != 0) {
+				q = (d3 * 0xcd) >> 11;
+				d3 = d3 - 10 * q;
+				*buf++ = d3 + '0';  /* next digit */
+				if (q != 0)
+					*buf++ = q + '0'; /* most sign. digit */
+			}
+		}
+	}
+	return buf;
+}
+
+static void ip4_addr_string(struct printf_info *info, u8 *addr)
+{
+	/* (4 * 3 decimal digits), 3 dots and trailing zero */
+	char ip4_addr[4 * 4];
+	char temp[3];	/* hold each IP quad in reverse order */
+	char *p = ip4_addr;
+	int i, digits;
+
+	for (i = 0; i < 4; i++) {
+		digits = put_dec_trunc(temp, addr[i]) - temp;
+		/* reverse the digits in the quad */
+		while (digits--)
+			*p++ = temp[digits];
+		if (i != 3)
+			*p++ = '.';
+	}
+	*p = '\0';
+
+	string(info, ip4_addr);
+}
+#endif
+
+/*
+ * Show a '%p' thing.  A kernel extension is that the '%p' is followed
+ * by an extra set of characters that are extended format
+ * specifiers.
+ *
+ * Right now we handle:
+ *
+ * - 'M' For a 6-byte MAC address, it prints the address in the
+ *       usual colon-separated hex notation.
+ * - 'm' Same as above except there is no colon-separator.
+ * - 'I4'for IPv4 addresses printed in the usual way (dot-separated
+ *       decimal).
+ */
+
+static void pointer(struct printf_info *info, const char *fmt, void *ptr)
+{
+#ifdef DEBUG
+	unsigned long num = (uintptr_t)ptr;
+	unsigned long div;
+#endif
+
+	switch (*fmt) {
+#ifdef DEBUG
+	case 'a':
+
+		switch (fmt[1]) {
+		case 'p':
+		default:
+			num = *(phys_addr_t *)ptr;
+			break;
+		}
+		break;
+#endif
+#ifdef CONFIG_SPL_NET_SUPPORT
+	case 'm':
+		return mac_address_string(info, ptr, false);
+	case 'M':
+		return mac_address_string(info, ptr, true);
+	case 'I':
+		if (fmt[1] == '4')
+			return ip4_addr_string(info, ptr);
+#endif
+	default:
+		break;
+	}
+#ifdef DEBUG
+	div = 1UL << (sizeof(long) * 8 - 4);
+	for (; div; div /= 0x10)
+		div_out(info, &num, div);
+#endif
+}
+
 static int _vprintf(struct printf_info *info, const char *fmt, va_list va)
 {
 	char ch;
@@ -144,6 +293,11 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va)
 			case 's':
 				p = va_arg(va, char*);
 				break;
+			case 'p':
+				pointer(info, fmt, va_arg(va, void *));
+				while (isalnum(fmt[0]))
+					fmt++;
+				break;
 			case '%':
 				out(info, '%');
 			default:
diff --git a/lib/tpm.c b/lib/tpm.c
index fb12214..cd7f88f 100644
--- a/lib/tpm.c
+++ b/lib/tpm.c
@@ -996,4 +996,44 @@ uint32_t tpm_get_pub_key_oiap(uint32_t key_handle, const void *usage_auth,
 	return 0;
 }
 
+#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
+uint32_t tpm_find_key_sha1(const uint8_t auth[20], const uint8_t
+			   pubkey_digest[20], uint32_t *handle)
+{
+	uint16_t key_count;
+	uint32_t key_handles[10];
+	uint8_t buf[288];
+	uint8_t *ptr;
+	uint32_t err;
+	uint8_t digest[20];
+	size_t buf_len;
+	unsigned int i;
+
+	/* fetch list of already loaded keys in the TPM */
+	err = tpm_get_capability(TPM_CAP_HANDLE, TPM_RT_KEY, buf, sizeof(buf));
+	if (err)
+		return -1;
+	key_count = get_unaligned_be16(buf);
+	ptr = buf + 2;
+	for (i = 0; i < key_count; ++i, ptr += 4)
+		key_handles[i] = get_unaligned_be32(ptr);
+
+	/* now search a(/ the) key which we can access with the given auth */
+	for (i = 0; i < key_count; ++i) {
+		buf_len = sizeof(buf);
+		err = tpm_get_pub_key_oiap(key_handles[i], auth, buf, &buf_len);
+		if (err && err != TPM_AUTHFAIL)
+			return -1;
+		if (err)
+			continue;
+		sha1_csum(buf, buf_len, digest);
+		if (!memcmp(digest, pubkey_digest, 20)) {
+			*handle = key_handles[i];
+			return 0;
+		}
+	}
+	return 1;
+}
+#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
+
 #endif /* CONFIG_TPM_AUTH_SESSIONS */
diff --git a/net/eth_common.c b/net/eth_common.c
index e9d3c66..58fa295 100644
--- a/net/eth_common.c
+++ b/net/eth_common.c
@@ -34,6 +34,9 @@ int eth_setenv_enetaddr(const char *name, const uchar *enetaddr)
 {
 	char buf[ARP_HLEN_ASCII + 1];
 
+	if (eth_getenv_enetaddr(name, (uchar *)buf))
+		return -EEXIST;
+
 	sprintf(buf, "%pM", enetaddr);
 
 	return setenv(name, buf);
diff --git a/net/link_local.c b/net/link_local.c
index 27851b6..dfd240d 100644
--- a/net/link_local.c
+++ b/net/link_local.c
@@ -111,7 +111,7 @@ void link_local_start(void)
 		net_set_state(NETLOOP_FAIL);
 		return;
 	}
-	net_netmask.s_addr = IN_CLASSB_NET;
+	net_netmask.s_addr = htonl(IN_CLASSB_NET);
 
 	seed = seed_mac();
 	if (ip.s_addr == 0)
diff --git a/post/post.c b/post/post.c
index 4194edb..8c2c822 100644
--- a/post/post.c
+++ b/post/post.c
@@ -474,7 +474,7 @@ void post_reloc(void)
  */
 unsigned long post_time_ms(unsigned long base)
 {
-#if defined(CONFIG_PPC) || defined(CONFIG_BLACKFIN) || defined(CONFIG_ARM)
+#if defined(CONFIG_PPC) || defined(CONFIG_ARM)
 	return (unsigned long)lldiv(get_ticks(), get_tbclk() / CONFIG_SYS_HZ)
 		- base;
 #else
diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index 1b62aed..a3a5c59 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -321,6 +321,12 @@ endif
 
 ifdef CONFIG_SPL_BUILD
 SPL_ := SPL_
+ifeq ($(CONFIG_TPL_BUILD),y)
+SPL_TPL_ := TPL_
+else
+SPL_TPL_ := SPL_
+endif
 else
 SPL_ :=
+SPL_TPL_ :=
 endif
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 5370648..eb24292 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -37,8 +37,14 @@ endif
 
 ifdef CONFIG_SPL_BUILD
 SPL_ := SPL_
+ifeq ($(CONFIG_TPL_BUILD),y)
+SPL_TPL_ := TPL_
+else
+SPL_TPL_ := SPL_
+endif
 else
 SPL_ :=
+SPL_TPL_ :=
 endif
 
 include $(srctree)/config.mk
@@ -173,6 +179,10 @@ endif
 
 ifdef CONFIG_ARCH_SUNXI
 ALL-y	+= $(obj)/sunxi-spl.bin
+
+ifdef CONFIG_NAND_SUNXI
+ALL-y	+= $(obj)/sunxi-spl-with-ecc.bin
+endif
 endif
 
 ifeq ($(CONFIG_SYS_SOC),"at91")
@@ -281,6 +291,10 @@ $(obj)/u-boot-x86-16bit-spl.bin: $(obj)/u-boot-spl FORCE
 	$(call if_changed,objcopy)
 
 LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
+
+# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
+LDFLAGS_$(SPL_BIN) += $(call ld-option, --no-dynamic-linker)
+
 ifneq ($(CONFIG_SPL_TEXT_BASE),)
 LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
 endif
@@ -294,6 +308,17 @@ cmd_mksunxiboot = $(objtree)/tools/mksunxiboot $< $@
 $(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE
 	$(call if_changed,mksunxiboot)
 
+quiet_cmd_sunxi_spl_image_builder = SUNXI_SPL_IMAGE_BUILDER $@
+cmd_sunxi_spl_image_builder = $(objtree)/tools/sunxi-spl-image-builder \
+				-c $(CONFIG_NAND_SUNXI_SPL_ECC_STRENGTH)/$(CONFIG_NAND_SUNXI_SPL_ECC_SIZE) \
+				-p $(CONFIG_SYS_NAND_PAGE_SIZE) \
+				-o $(CONFIG_SYS_NAND_OOBSIZE) \
+				-u $(CONFIG_NAND_SUNXI_SPL_USABLE_PAGE_SIZE) \
+				-e $(CONFIG_SYS_NAND_BLOCK_SIZE) \
+				-s -b $< $@
+$(obj)/sunxi-spl-with-ecc.bin: $(obj)/sunxi-spl.bin
+	$(call if_changed,sunxi_spl_image_builder)
+
 # Rule to link u-boot-spl
 # May be overridden by arch/$(ARCH)/config.mk
 quiet_cmd_u-boot-spl ?= LD      $@
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 9f32cb2..7bc5169 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -66,8 +66,6 @@ CONFIG_ADDRESS
 CONFIG_ADDR_AUTO_INCR_BIT
 CONFIG_ADDR_MAP
 CONFIG_ADDR_STREAMING
-CONFIG_ADI_GPIO1
-CONFIG_ADI_GPIO2
 CONFIG_ADNPESC1
 CONFIG_ADP_AG101P
 CONFIG_AEABI
@@ -237,45 +235,10 @@ CONFIG_BCM_SF2_ETH
 CONFIG_BCM_SF2_ETH_DEFAULT_PORT
 CONFIG_BCM_SF2_ETH_GMAC
 CONFIG_BD_NUM_CPUS
-CONFIG_BF506_UART0_PORTF
-CONFIG_BF506_UART1_PORTG
-CONFIG_BF50x
-CONFIG_BF51x
-CONFIG_BF527_EZKIT_REV_2_1
-CONFIG_BF52x
-CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
-CONFIG_BF54x
-CONFIG_BF60x
-CONFIG_BFIN_ATAPI_BASE_ADDR
 CONFIG_BFIN_ATA_MODE
-CONFIG_BFIN_BOARD_VERSION_1_0
-CONFIG_BFIN_BOOTROM_USES_EVT1
-CONFIG_BFIN_BOOT_MODE
-CONFIG_BFIN_CF_IDE
-CONFIG_BFIN_CPU
-CONFIG_BFIN_GET_DCLK_M
-CONFIG_BFIN_GPIO_TRACK
-CONFIG_BFIN_HDD_IDE
-CONFIG_BFIN_IDE
-CONFIG_BFIN_INS_LOWOVERHEAD
-CONFIG_BFIN_LINKPORT
-CONFIG_BFIN_MAC
 CONFIG_BFIN_MAC_PINS
-CONFIG_BFIN_NFC
 CONFIG_BFIN_NFC_BOOTROM_ECC
-CONFIG_BFIN_NFC_CTL_VAL
 CONFIG_BFIN_NFC_NO_HW_ECC
-CONFIG_BFIN_SCRATCH_REG
-CONFIG_BFIN_SDH
-CONFIG_BFIN_SERIAL
-CONFIG_BFIN_SOFT_SWITCH
-CONFIG_BFIN_SPI
-CONFIG_BFIN_SPI6XX
-CONFIG_BFIN_SPI_GPIO_CS
-CONFIG_BFIN_SPI_IDLE_VAL
-CONFIG_BFIN_SPI_IMG_SIZE
-CONFIG_BFIN_TRUE_IDE
-CONFIG_BFIN_WATCHDOG
 CONFIG_BIOSEMU
 CONFIG_BITBANGMII_MULTI
 CONFIG_BKUP_FLASH
@@ -313,9 +276,7 @@ CONFIG_BOOGER
 CONFIG_BOOM
 CONFIG_BOOTARGS
 CONFIG_BOOTARGS_AXM
-CONFIG_BOOTARGS_ROOT
 CONFIG_BOOTARGS_TAURUS
-CONFIG_BOOTARGS_VIDEO
 CONFIG_BOOTBLOCK
 CONFIG_BOOTCOMMAND
 CONFIG_BOOTCOUNT_ALEN
@@ -386,17 +347,12 @@ CONFIG_BUILD_ENVCRC
 CONFIG_BUILD_TARGET
 CONFIG_BUS_WIDTH
 CONFIG_BZIP2
-CONFIG_CACHELINE_ALIGNED_L1
 CONFIG_CADDY2
 CONFIG_CALXEDA_XGMAC
 CONFIG_CAM5200
 CONFIG_CAM5200_NIOSFLASH
 CONFIG_CANMB
 CONFIG_CAN_DRIVER
-CONFIG_CCLK_ACT_DIV
-CONFIG_CCLK_DIV
-CONFIG_CCLK_DIV_not_defined_properly
-CONFIG_CCLK_HZ
 CONFIG_CDP_APPLIANCE_VLAN_TYPE
 CONFIG_CDP_CAPABILITIES
 CONFIG_CDP_DEVICE_ID
@@ -410,8 +366,6 @@ CONFIG_CFG_DATA_SECTOR
 CONFIG_CFG_FAT
 CONFIG_CFG_USB
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-CONFIG_CF_ATASEL_DIS
-CONFIG_CF_ATASEL_ENA
 CONFIG_CF_DSPI
 CONFIG_CF_SBF
 CONFIG_CF_SPI
@@ -419,8 +373,6 @@ CONFIG_CF_V2
 CONFIG_CF_V3
 CONFIG_CF_V4
 CONFIG_CF_V4E
-CONFIG_CGU_CTL_VAL
-CONFIG_CGU_DIV_VAL
 CONFIG_CHAIN_BOOT_CMD
 CONFIG_CHARON
 CONFIG_CHIP_SELECTS_PER_CTRL
@@ -430,8 +382,6 @@ CONFIG_CIS8201_PHY
 CONFIG_CI_UDC_HAS_HOSTPC
 CONFIG_CLK0_DIV
 CONFIG_CLK0_EN
-CONFIG_CLKIN_HALF
-CONFIG_CLKIN_HZ
 CONFIG_CLK_1000_200_200
 CONFIG_CLK_1000_330_165
 CONFIG_CLK_1000_400_200
@@ -452,13 +402,11 @@ CONFIG_CMD_BEDBUG
 CONFIG_CMD_BLOB
 CONFIG_CMD_BMODE
 CONFIG_CMD_BMP
-CONFIG_CMD_BOOTLDR
 CONFIG_CMD_BSP
 CONFIG_CMD_CBFS
 CONFIG_CMD_CHIP_CONFIG
 CONFIG_CMD_CLEAR
 CONFIG_CMD_CLK
-CONFIG_CMD_CPLBINFO
 CONFIG_CMD_CRAMFS
 CONFIG_CMD_DATE
 CONFIG_CMD_DEFAULTENV_VARS
@@ -506,7 +454,6 @@ CONFIG_CMD_IOTRACE
 CONFIG_CMD_IRQ
 CONFIG_CMD_JFFS2
 CONFIG_CMD_KGDB
-CONFIG_CMD_LDRINFO
 CONFIG_CMD_LOADY
 CONFIG_CMD_LZMADEC
 CONFIG_CMD_MAX6957
@@ -519,7 +466,6 @@ CONFIG_CMD_NAND_LOCK_UNLOCK
 CONFIG_CMD_NAND_TORTURE
 CONFIG_CMD_NAND_TRIMFFS
 CONFIG_CMD_ONENAND
-CONFIG_CMD_OTP
 CONFIG_CMD_PCA953X
 CONFIG_CMD_PCA953X_INFO
 CONFIG_CMD_PCI
@@ -536,8 +482,6 @@ CONFIG_CMD_SCSI
 CONFIG_CMD_SDRAM
 CONFIG_CMD_SF_TEST
 CONFIG_CMD_SH_ZIMAGEBOOT
-CONFIG_CMD_SOFTSWITCH
-CONFIG_CMD_SPIBOOTLDR
 CONFIG_CMD_SPL
 CONFIG_CMD_SPL_NAND_OFS
 CONFIG_CMD_SPL_WRITE_SIZE
@@ -551,7 +495,6 @@ CONFIG_CMD_TRACE
 CONFIG_CMD_TSI148
 CONFIG_CMD_UBIFS
 CONFIG_CMD_UNIVERSE
-CONFIG_CMD_USB_STORAGE
 CONFIG_CMD_UUID
 CONFIG_CMD_ZBOOT
 CONFIG_CMD_ZFS
@@ -590,7 +533,6 @@ CONFIG_CONS_SCIF7
 CONFIG_CONTROL
 CONFIG_CONTROLCENTERD
 CONFIG_CON_ROT
-CONFIG_CORE1_RUN
 CONFIG_CORE_COUNT
 CONFIG_CORTINA_FW_ADDR
 CONFIG_CORTINA_FW_LENGTH
@@ -672,9 +614,7 @@ CONFIG_DBG_MONITOR
 CONFIG_DB_784MP_GP
 CONFIG_DCACHE
 CONFIG_DCACHE_OFF
-CONFIG_DCACHE_WB
 CONFIG_DCFG_ADDR
-CONFIG_DCLK_DIV
 CONFIG_DDR_
 CONFIG_DDR_2HCLK
 CONFIG_DDR_2T_TIMING
@@ -704,19 +644,13 @@ CONFIG_DDR_RFDC_FIXED
 CONFIG_DDR_RQDC_FIXED
 CONFIG_DDR_SPD
 CONFIG_DEBUG
-CONFIG_DEBUG_DUMP
-CONFIG_DEBUG_DUMP_SYMS
-CONFIG_DEBUG_EARLY_SERIAL
 CONFIG_DEBUG_FS
 CONFIG_DEBUG_LED
 CONFIG_DEBUG_LOCK_ALLOC
-CONFIG_DEBUG_NULL_PTR
 CONFIG_DEBUG_SECTION_MISMATCH
 CONFIG_DEBUG_SEMIHOSTING
-CONFIG_DEBUG_SERIAL
 CONFIG_DEBUG_UART_LINFLEXUART
 CONFIG_DEBUG_WRITECOUNT
-CONFIG_DEB_DMA_URGENT
 CONFIG_DEEP_SLEEP
 CONFIG_DEFAULT
 CONFIG_DEFAULT_CONSOLE
@@ -765,15 +699,7 @@ CONFIG_DMA_COHERENT_SIZE
 CONFIG_DMA_LPC32XX
 CONFIG_DMA_NONCOHERENT
 CONFIG_DMA_REQ_BIT
-CONFIG_DMC_DDRCFG
-CONFIG_DMC_DDRCTL
-CONFIG_DMC_DDREMR1
-CONFIG_DMC_DDRMR
-CONFIG_DMC_DDRTR0
-CONFIG_DMC_DDRTR1
-CONFIG_DMC_DDRTR2
 CONFIG_DNET_AUTONEG_TIMEOUT
-CONFIG_DNP5370_EXT_WD_DISABLE
 CONFIG_DP_DDR_CTRL
 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
 CONFIG_DP_DDR_NUM_CTRLS
@@ -788,7 +714,6 @@ CONFIG_DRIVER_AX88796L
 CONFIG_DRIVER_DM9000
 CONFIG_DRIVER_EP93XX_MAC
 CONFIG_DRIVER_ETHER
-CONFIG_DRIVER_NAND_BFIN
 CONFIG_DRIVER_NE2000
 CONFIG_DRIVER_NE2000_BASE
 CONFIG_DRIVER_NE2000_CCR
@@ -851,7 +776,6 @@ CONFIG_DW_ALTDESCRIPTOR
 CONFIG_DW_AXI_BURST_LEN
 CONFIG_DW_GMAC_DEFAULT_DMA_PBL
 CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
-CONFIG_DW_PORTS
 CONFIG_DW_SERIAL
 CONFIG_DW_UDC
 CONFIG_DW_WDT_BASE
@@ -860,24 +784,7 @@ CONFIG_DYNAMIC_MMC_DEVNO
 CONFIG_E1000_NO_NVM
 CONFIG_E300
 CONFIG_E5500
-CONFIG_EBCAW_VAL
 CONFIG_EBC_PPC4xx_IBM_VER1
-CONFIG_EBIU_AMBCTL0_VAL
-CONFIG_EBIU_AMBCTL1_VAL
-CONFIG_EBIU_AMGCTL_VAL
-CONFIG_EBIU_DDRCTL0_VAL
-CONFIG_EBIU_DDRCTL1_VAL
-CONFIG_EBIU_DDRCTL2_VAL
-CONFIG_EBIU_DDRCTL3_VAL
-CONFIG_EBIU_DDRQUE_VAL
-CONFIG_EBIU_FCTL_VAL
-CONFIG_EBIU_MBSCTL_VAL
-CONFIG_EBIU_MODE_VAL
-CONFIG_EBIU_RSTCTL_VAL
-CONFIG_EBIU_SDBCTL_VAL
-CONFIG_EBIU_SDGCTL_VAL
-CONFIG_EBIU_SDRRC_VAL
-CONFIG_EBSZ_VAL
 CONFIG_ECC
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 CONFIG_ECC_MODE_MASK
@@ -939,7 +846,6 @@ CONFIG_ENV_FLAGS_LIST_DEFAULT
 CONFIG_ENV_FLAGS_LIST_STATIC
 CONFIG_ENV_FLASHBOOT
 CONFIG_ENV_IS_EMBEDDED
-CONFIG_ENV_IS_EMBEDDED_IN_LDR
 CONFIG_ENV_IS_IN_
 CONFIG_ENV_IS_IN_DATAFLASH
 CONFIG_ENV_IS_IN_EEPROM
@@ -1023,7 +929,6 @@ CONFIG_ETHER_ON_SCC
 CONFIG_ETHPRIME
 CONFIG_ETH_BUFSIZE
 CONFIG_ETH_RXSIZE
-CONFIG_EXCEPTION_DEFER
 CONFIG_EXT4_WRITE
 CONFIG_EXTRA_BOOTARGS
 CONFIG_EXTRA_CLOCK
@@ -1308,7 +1213,6 @@ CONFIG_HAS_FSL_DR_USB
 CONFIG_HAS_FSL_MPH_USB
 CONFIG_HAS_FSL_XHCI_USB
 CONFIG_HAS_POST
-CONFIG_HAS_VR
 CONFIG_HAVE_ACPI_RESUME
 CONFIG_HAVE_OWN_RESET
 CONFIG_HCLK_FREQ
@@ -1477,7 +1381,6 @@ CONFIG_HVBOOT
 CONFIG_HWCONFIG
 CONFIG_HW_ENV_SETTINGS
 CONFIG_HW_WATCHDOG
-CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
 CONFIG_HW_WATCHDOG_TIMEOUT_MS
 CONFIG_I2C
 CONFIG_I2CFAST
@@ -1505,7 +1408,6 @@ CONFIG_I2C_RTC_ADDR
 CONFIG_I2C_TIMEOUT
 CONFIG_IBM_EMAC4_V4
 CONFIG_ICACHE
-CONFIG_ICACHE_OFF
 CONFIG_ICON
 CONFIG_ICS307_REFCLK_HZ
 CONFIG_IDE_8xx_DIRECT
@@ -1566,7 +1468,6 @@ CONFIG_IPAM390_GPIO_BOOTMODE
 CONFIG_IPAM390_GPIO_LED_GREEN
 CONFIG_IPAM390_GPIO_LED_RED
 CONFIG_IPEK01
-CONFIG_IPIPE
 CONFIG_IPROC
 CONFIG_IPUV3_CLK
 CONFIG_IP_DEFRAG
@@ -1592,9 +1493,7 @@ CONFIG_JFFS2_PART_SIZE
 CONFIG_JFFS2_SUMMARY
 CONFIG_JRSTARTR_JR0
 CONFIG_JTAG_CONSOLE
-CONFIG_JTAG_CONSOLE_TIMEOUT
 CONFIG_JUPITER
-CONFIG_KALLSYMS
 CONFIG_KASAN
 CONFIG_KATMAI
 CONFIG_KCLK_DIS
@@ -1760,8 +1659,6 @@ CONFIG_LIBATA
 CONFIG_LIB_HW_RAND
 CONFIG_LIB_UUID
 CONFIG_LINUX
-CONFIG_LINUX_CMDLINE_ADDR
-CONFIG_LINUX_CMDLINE_SIZE
 CONFIG_LINUX_RESET_VEC
 CONFIG_LITTLETON_LCD
 CONFIG_LMB
@@ -1800,11 +1697,6 @@ CONFIG_LPC_BASE
 CONFIG_LPC_IO_BASE
 CONFIG_LPUART
 CONFIG_LPUART_32B_REG
-CONFIG_LQ035Q1_LCD_MODE
-CONFIG_LQ035Q1_SPI_BUS
-CONFIG_LQ035Q1_SPI_CS
-CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
-CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
 CONFIG_LQ038J7DH53
 CONFIG_LS102XA
 CONFIG_LS102XA_STREAM_ID
@@ -1885,11 +1777,9 @@ CONFIG_MECP5123
 CONFIG_MEMSIZE
 CONFIG_MEMSIZE_IN_BYTES
 CONFIG_MEMSIZE_MASK
-CONFIG_MEM_ADD_WDTH
 CONFIG_MEM_HOLE_16M
 CONFIG_MEM_INIT_VALUE
 CONFIG_MEM_REMAP
-CONFIG_MEM_SIZE
 CONFIG_MENUKEY
 CONFIG_MENUPROMPT
 CONFIG_MENU_SHOW
@@ -2109,7 +1999,6 @@ CONFIG_NAND_OMAP_ELM
 CONFIG_NAND_OMAP_GPMC
 CONFIG_NAND_OMAP_GPMC_PREFETCH
 CONFIG_NAND_OMAP_GPMC_WSCFG
-CONFIG_NAND_PLAT
 CONFIG_NAND_SECBOOT
 CONFIG_NAND_SPL
 CONFIG_NAND_U_BOOT
@@ -2158,7 +2047,6 @@ CONFIG_NS8382X
 CONFIG_NS87308
 CONFIG_NUM_DSP_CPUS
 CONFIG_NUM_PAMU
-CONFIG_OCLK_DIV
 CONFIG_ODROID_REV_AIN
 CONFIG_OFF_PADCONF
 CONFIG_OF_
@@ -2209,15 +2097,12 @@ CONFIG_PALMAS_SMPS7_FPWM
 CONFIG_PALMAS_USB_SS_PWR
 CONFIG_PANIC_HANG
 CONFIG_PARAVIRT
-CONFIG_PATA_BFIN
 CONFIG_PATI
 CONFIG_PB1000
 CONFIG_PB1100
 CONFIG_PB1500
 CONFIG_PB1X00
 CONFIG_PCA953X
-CONFIG_PCA9564_BASE
-CONFIG_PCA9564_I2C
 CONFIG_PCA9698
 CONFIG_PCI1
 CONFIG_PCI2
@@ -2338,10 +2223,6 @@ CONFIG_PLATINUM_TITANIUM
 CONFIG_PLL
 CONFIG_PLL1_CLK_FREQ
 CONFIG_PLL1_DIV2_CLK_FREQ
-CONFIG_PLL_BYPASS
-CONFIG_PLL_CTL_VAL
-CONFIG_PLL_DIV_VAL
-CONFIG_PLL_LOCKCNT_VAL
 CONFIG_PLU405
 CONFIG_PM
 CONFIG_PM9261
@@ -2380,10 +2261,7 @@ CONFIG_POST
 CONFIG_POSTBOOTMENU
 CONFIG_POST_ALT_LIST
 CONFIG_POST_BSPEC1
-CONFIG_POST_BSPEC1_GPIO_LEDS
 CONFIG_POST_BSPEC2
-CONFIG_POST_BSPEC2_GPIO_BUTTONS
-CONFIG_POST_BSPEC2_GPIO_NAMES
 CONFIG_POST_BSPEC3
 CONFIG_POST_BSPEC4
 CONFIG_POST_BSPEC5
@@ -2555,7 +2433,6 @@ CONFIG_ROOTPATH
 CONFIG_RSK7203
 CONFIG_RSK7264
 CONFIG_RSK7269
-CONFIG_RTC_BFIN
 CONFIG_RTC_DS1307
 CONFIG_RTC_DS1337
 CONFIG_RTC_DS1338
@@ -2640,10 +2517,6 @@ CONFIG_SCIF_A
 CONFIG_SCIF_CONSOLE
 CONFIG_SCIF_EXT_CLOCK
 CONFIG_SCIF_USE_EXT_CLK
-CONFIG_SCLK0_DIV
-CONFIG_SCLK1_DIV
-CONFIG_SCLK_DIV
-CONFIG_SCLK_HZ
 CONFIG_SCSI
 CONFIG_SCSI_AHCI
 CONFIG_SCSI_AHCI_PLAT
@@ -2693,7 +2566,6 @@ CONFIG_SFIO
 CONFIG_SF_DATAFLASH
 CONFIG_SF_DEFAULT_BUS
 CONFIG_SF_DEFAULT_CS
-CONFIG_SF_DEFAULT_HZ
 CONFIG_SF_DEFAULT_MODE
 CONFIG_SF_DEFAULT_SPEED
 CONFIG_SF_DUAL_FLASH
@@ -2778,19 +2650,6 @@ CONFIG_SMC911X_BASE
 CONFIG_SMC911X_NO_EEPROM
 CONFIG_SMC_91111_EXT_PHY
 CONFIG_SMC_AUTONEG_TIMEOUT
-CONFIG_SMC_B0CTL_VAL
-CONFIG_SMC_B0ETIM_VAL
-CONFIG_SMC_B0TIM_VAL
-CONFIG_SMC_B1CTL_VAL
-CONFIG_SMC_B1ETIM_VAL
-CONFIG_SMC_B1TIM_VAL
-CONFIG_SMC_B2CTL_VAL
-CONFIG_SMC_B2ETIM_VAL
-CONFIG_SMC_B2TIM_VAL
-CONFIG_SMC_B3CTL_VAL
-CONFIG_SMC_B3ETIM_VAL
-CONFIG_SMC_B3TIM_VAL
-CONFIG_SMC_GCTL_VAL
 CONFIG_SMC_USE_32_BIT
 CONFIG_SMC_USE_IOFUNCS
 CONFIG_SMDK5420
@@ -2838,7 +2697,6 @@ CONFIG_SOFT_I2C_I2C5_SCL
 CONFIG_SOFT_I2C_I2C5_SDA
 CONFIG_SOFT_I2C_I2C9_SCL
 CONFIG_SOFT_I2C_I2C9_SDA
-CONFIG_SOFT_I2C_MULTI_BUS
 CONFIG_SOFT_I2C_READ_REPEATED_START
 CONFIG_SOFT_SPI
 CONFIG_SOFT_TWS
@@ -2876,11 +2734,9 @@ CONFIG_SPEAR_USBBOOT
 CONFIG_SPEAR_USBTTY
 CONFIG_SPI
 CONFIG_SPI_ADDR
-CONFIG_SPI_BAUD_INITBLOCK
 CONFIG_SPI_BOOTING
 CONFIG_SPI_CS_IS_VALID
 CONFIG_SPI_DATAFLASH_WRITE_VERIFY
-CONFIG_SPI_FLASH_ALL
 CONFIG_SPI_FLASH_ISSI
 CONFIG_SPI_FLASH_QUAD
 CONFIG_SPI_FLASH_SIZE
@@ -3003,10 +2859,6 @@ CONFIG_SSP1_BASE
 CONFIG_SSP2_BASE
 CONFIG_SSP3_BASE
 CONFIG_STACKBASE
-CONFIG_STACKSIZE
-CONFIG_STACKSIZE_FIQ
-CONFIG_STACKSIZE_IRQ
-CONFIG_STAMP_CF
 CONFIG_STANDALONE_LOAD_ADDR
 CONFIG_STATIC_BOARD_REV
 CONFIG_STATIC_RELA
@@ -3149,7 +3001,6 @@ CONFIG_SYS_BCSR_ADDR
 CONFIG_SYS_BCSR_BASE
 CONFIG_SYS_BCSR_BASE_PHYS
 CONFIG_SYS_BCSR_SIZE
-CONFIG_SYS_BD_INFO_ADDR
 CONFIG_SYS_BD_REV
 CONFIG_SYS_BFTIC3_BASE
 CONFIG_SYS_BFTIC3_SIZE
@@ -3822,7 +3673,6 @@ CONFIG_SYS_FLASH1
 CONFIG_SYS_FLASH1_BASE
 CONFIG_SYS_FLASH1_BASE_PHYS
 CONFIG_SYS_FLASH1_BASE_PHYS_EARLY
-CONFIG_SYS_FLASH2_BASE
 CONFIG_SYS_FLASHBOOT
 CONFIG_SYS_FLASH_2ND_16BIT_DEV
 CONFIG_SYS_FLASH_2ND_ADDR
@@ -4506,7 +4356,6 @@ CONFIG_SYS_I2C_8574A_ADDR1
 CONFIG_SYS_I2C_8574A_ADDR2
 CONFIG_SYS_I2C_8574_ADDR1
 CONFIG_SYS_I2C_8574_ADDR2
-CONFIG_SYS_I2C_ADI
 CONFIG_SYS_I2C_BASE
 CONFIG_SYS_I2C_BASE0
 CONFIG_SYS_I2C_BASE1
@@ -6200,7 +6049,6 @@ CONFIG_SYS_SSD_BASE
 CONFIG_SYS_SSD_BASE_PHYS
 CONFIG_SYS_SST_SECT
 CONFIG_SYS_SST_SECTSZ
-CONFIG_SYS_STACKSIZE
 CONFIG_SYS_STACK_LENGTH
 CONFIG_SYS_STACK_SIZE
 CONFIG_SYS_STATUS_C
@@ -6453,7 +6301,6 @@ CONFIG_TI816X_EVM_DDR3
 CONFIG_TI816X_USE_EMIF0
 CONFIG_TI816X_USE_EMIF1
 CONFIG_TI81XX
-CONFIG_TIMER_CLK_FREQ
 CONFIG_TIMESTAMP
 CONFIG_TIZEN
 CONFIG_TI_KEYSTONE_SERDES
@@ -6529,9 +6376,6 @@ CONFIG_TZSW_RESERVED_DRAM_SIZE
 CONFIG_T_SH7706LSR
 CONFIG_UART_BASE
 CONFIG_UART_BR_PRELIM
-CONFIG_UART_CONSOLE
-CONFIG_UART_CONSOLE_IS_JTAG
-CONFIG_UART_MEM
 CONFIG_UART_OR_PRELIM
 CONFIG_UBIBLOCK
 CONFIG_UBIFS_SILENCE_MSG
@@ -6602,8 +6446,6 @@ CONFIG_USB_ATMEL
 CONFIG_USB_ATMEL_CLK_SEL_PLLB
 CONFIG_USB_ATMEL_CLK_SEL_UPLL
 CONFIG_USB_BIN_FIXUP
-CONFIG_USB_BLACKFIN
-CONFIG_USB_BLACKFIN_CLKIN
 CONFIG_USB_BOOTING
 CONFIG_USB_CABLE_CHECK
 CONFIG_USB_CLOCK
@@ -6716,7 +6558,6 @@ CONFIG_USB_XHCI_PCI
 CONFIG_USER_LOWLEVEL_INIT
 CONFIG_USE_FDT
 CONFIG_USE_INTERRUPT
-CONFIG_USE_IRQ
 CONFIG_USE_NAND
 CONFIG_USE_NETDEV
 CONFIG_USE_NOR
@@ -6731,8 +6572,6 @@ CONFIG_U_QE
 CONFIG_V38B
 CONFIG_VAL
 CONFIG_VAR_SIZE_SPL
-CONFIG_VCO_HZ
-CONFIG_VCO_MULT
 CONFIG_VCT_NOR
 CONFIG_VE8313
 CONFIG_VERY_BIG_RAM
@@ -6773,10 +6612,6 @@ CONFIG_VOL_MONITOR_INA220
 CONFIG_VOL_MONITOR_IR36021_READ
 CONFIG_VOL_MONITOR_IR36021_SET
 CONFIG_VOM405
-CONFIG_VR_CTL_CLKBUF
-CONFIG_VR_CTL_FREQ
-CONFIG_VR_CTL_VAL
-CONFIG_VR_CTL_VLEV
 CONFIG_VSC7385_ENET
 CONFIG_VSC7385_IMAGE
 CONFIG_VSC7385_IMAGE_SIZE
@@ -6828,7 +6663,6 @@ CONFIG_YAFFS_WINCE
 CONFIG_YELLOWSTONE
 CONFIG_YELLOW_LED
 CONFIG_YOSEMITE
-CONFIG_ZBOOT_32
 CONFIG_ZC770_XM010
 CONFIG_ZC770_XM011
 CONFIG_ZC770_XM012
diff --git a/test/dm/bus.c b/test/dm/bus.c
index d94dcf7..6a27735 100644
--- a/test/dm/bus.c
+++ b/test/dm/bus.c
@@ -222,7 +222,7 @@ static int test_bus_parent_data(struct unit_test_state *uts)
 	/* Check that it starts at 0 and goes away when device is removed */
 	parent_data->sum += 5;
 	ut_asserteq(5, parent_data->sum);
-	device_remove(dev);
+	device_remove(dev, DM_REMOVE_NORMAL);
 	ut_asserteq_ptr(NULL, dev_get_parent_priv(dev));
 
 	/* Check that we can do this twice */
@@ -323,7 +323,7 @@ static int dm_test_bus_parent_ops(struct unit_test_state *uts)
 			continue;
 		parent_data = dev_get_parent_priv(dev);
 		ut_asserteq(FLAG_CHILD_PROBED, parent_data->flag);
-		ut_assertok(device_remove(dev));
+		ut_assertok(device_remove(dev, DM_REMOVE_NORMAL));
 		ut_asserteq_ptr(NULL, dev_get_parent_priv(dev));
 		ut_asserteq_ptr(dms->removed, dev);
 	}
@@ -360,7 +360,7 @@ static int test_bus_parent_platdata(struct unit_test_state *uts)
 		plat->count++;
 		ut_asserteq(1, plat->count);
 		device_probe(dev);
-		device_remove(dev);
+		device_remove(dev, DM_REMOVE_NORMAL);
 
 		ut_asserteq_ptr(plat, dev_get_parent_platdata(dev));
 		ut_asserteq(1, plat->count);
@@ -370,7 +370,7 @@ static int test_bus_parent_platdata(struct unit_test_state *uts)
 	ut_asserteq(3, child_count);
 
 	/* Removing the bus should also have no effect (it is still bound) */
-	device_remove(bus);
+	device_remove(bus, DM_REMOVE_NORMAL);
 	for (device_find_first_child(bus, &dev), child_count = 0;
 	     dev;
 	     device_find_next_child(&dev)) {
diff --git a/test/dm/core.c b/test/dm/core.c
index 70bf4d0..50ee41b 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -67,6 +67,10 @@ static struct driver_info driver_info_pre_reloc = {
 	.platdata = &test_pdata_pre_reloc,
 };
 
+static struct driver_info driver_info_act_dma = {
+	.name = "test_act_dma_drv",
+};
+
 void dm_leak_check_start(struct unit_test_state *uts)
 {
 	uts->start = mallinfo();
@@ -319,7 +323,7 @@ static int dm_test_lifecycle(struct unit_test_state *uts)
 
 	/* Now remove device 3 */
 	ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]);
-	ut_assertok(device_remove(dev));
+	ut_assertok(device_remove(dev, DM_REMOVE_NORMAL));
 	ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]);
 
 	ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_UNBIND]);
@@ -352,7 +356,7 @@ static int dm_test_ordering(struct unit_test_state *uts)
 	ut_assert(dev_last);
 
 	/* Now remove device 3 */
-	ut_assertok(device_remove(dev));
+	ut_assertok(device_remove(dev, DM_REMOVE_NORMAL));
 	ut_assertok(device_unbind(dev));
 
 	/* The device numbering should have shifted down one */
@@ -371,9 +375,9 @@ static int dm_test_ordering(struct unit_test_state *uts)
 	ut_assert(pingret == 102);
 
 	/* Remove 3 and 4 */
-	ut_assertok(device_remove(dev_penultimate));
+	ut_assertok(device_remove(dev_penultimate, DM_REMOVE_NORMAL));
 	ut_assertok(device_unbind(dev_penultimate));
-	ut_assertok(device_remove(dev_last));
+	ut_assertok(device_remove(dev_last, DM_REMOVE_NORMAL));
 	ut_assertok(device_unbind(dev_last));
 
 	/* Our device should now be in position 3 */
@@ -381,7 +385,7 @@ static int dm_test_ordering(struct unit_test_state *uts)
 	ut_assert(dev == test_dev);
 
 	/* Now remove device 3 */
-	ut_assertok(device_remove(dev));
+	ut_assertok(device_remove(dev, DM_REMOVE_NORMAL));
 	ut_assertok(device_unbind(dev));
 
 	return 0;
@@ -457,7 +461,7 @@ static int dm_test_remove(struct unit_test_state *uts)
 		ut_assert(dev);
 		ut_assertf(dev->flags & DM_FLAG_ACTIVATED,
 			   "Driver %d/%s not activated", i, dev->name);
-		ut_assertok(device_remove(dev));
+		ut_assertok(device_remove(dev, DM_REMOVE_NORMAL));
 		ut_assertf(!(dev->flags & DM_FLAG_ACTIVATED),
 			   "Driver %d/%s should have deactivated", i,
 			   dev->name);
@@ -611,14 +615,14 @@ static int dm_test_children(struct unit_test_state *uts)
 	ut_asserteq(total, dm_testdrv_op_count[DM_TEST_OP_PROBE]);
 
 	/* Remove a top-level child and check that the children are removed */
-	ut_assertok(device_remove(top[2]));
+	ut_assertok(device_remove(top[2], DM_REMOVE_NORMAL));
 	ut_asserteq(NODE_COUNT + 1, dm_testdrv_op_count[DM_TEST_OP_REMOVE]);
 	dm_testdrv_op_count[DM_TEST_OP_REMOVE] = 0;
 
 	/* Try one with grandchildren */
 	ut_assertok(uclass_get_device(UCLASS_TEST, 5, &dev));
 	ut_asserteq_ptr(dev, top[5]);
-	ut_assertok(device_remove(dev));
+	ut_assertok(device_remove(dev, DM_REMOVE_NORMAL));
 	ut_asserteq(1 + NODE_COUNT * (1 + NODE_COUNT),
 		    dm_testdrv_op_count[DM_TEST_OP_REMOVE]);
 
@@ -656,6 +660,68 @@ static int dm_test_pre_reloc(struct unit_test_state *uts)
 }
 DM_TEST(dm_test_pre_reloc, 0);
 
+/*
+ * Test that removal of devices, either via the "normal" device_remove()
+ * API or via the device driver selective flag works as expected
+ */
+static int dm_test_remove_active_dma(struct unit_test_state *uts)
+{
+	struct dm_test_state *dms = uts->priv;
+	struct udevice *dev;
+
+	ut_assertok(device_bind_by_name(dms->root, false, &driver_info_act_dma,
+					&dev));
+	ut_assert(dev);
+
+	/* Probe the device */
+	ut_assertok(device_probe(dev));
+
+	/* Test if device is active right now */
+	ut_asserteq(true, device_active(dev));
+
+	/* Remove the device via selective remove flag */
+	dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+
+	/* Test if device is inactive right now */
+	ut_asserteq(false, device_active(dev));
+
+	/* Probe the device again */
+	ut_assertok(device_probe(dev));
+
+	/* Test if device is active right now */
+	ut_asserteq(true, device_active(dev));
+
+	/* Remove the device via "normal" remove API */
+	ut_assertok(device_remove(dev, DM_REMOVE_NORMAL));
+
+	/* Test if device is inactive right now */
+	ut_asserteq(false, device_active(dev));
+
+	/*
+	 * Test if a device without the active DMA flags is not removed upon
+	 * the active DMA remove call
+	 */
+	ut_assertok(device_unbind(dev));
+	ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual,
+					&dev));
+	ut_assert(dev);
+
+	/* Probe the device */
+	ut_assertok(device_probe(dev));
+
+	/* Test if device is active right now */
+	ut_asserteq(true, device_active(dev));
+
+	/* Remove the device via selective remove flag */
+	dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+
+	/* Test if device is still active right now */
+	ut_asserteq(true, device_active(dev));
+
+	return 0;
+}
+DM_TEST(dm_test_remove_active_dma, 0);
+
 static int dm_test_uclass_before_ready(struct unit_test_state *uts)
 {
 	struct uclass *uc;
diff --git a/test/dm/eth.c b/test/dm/eth.c
index 6288ae2..564ad36 100644
--- a/test/dm/eth.c
+++ b/test/dm/eth.c
@@ -116,7 +116,7 @@ static int dm_test_eth_act(struct unit_test_state *uts)
 	for (i = 0; i < DM_TEST_ETH_NUM; i++) {
 		ut_assertok(uclass_find_device_by_name(UCLASS_ETH,
 						       ethname[i], &dev[i]));
-		ut_assertok(device_remove(dev[i]));
+		ut_assertok(device_remove(dev[i], DM_REMOVE_NORMAL));
 
 		/* Invalidate MAC address */
 		strcpy(ethaddr[i], getenv(addrname[i]));
diff --git a/test/dm/spi.c b/test/dm/spi.c
index f52cb73..24fa2a4 100644
--- a/test/dm/spi.c
+++ b/test/dm/spi.c
@@ -36,7 +36,7 @@ static int dm_test_spi_find(struct unit_test_state *uts)
 	ut_asserteq(0, uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus));
 	ut_assertok(spi_cs_info(bus, cs, &info));
 	of_offset = dev_of_offset(info.dev);
-	device_remove(info.dev);
+	device_remove(info.dev, DM_REMOVE_NORMAL);
 	device_unbind(info.dev);
 
 	/*
diff --git a/test/dm/test-driver.c b/test/dm/test-driver.c
index d10af51..2b432a7 100644
--- a/test/dm/test-driver.c
+++ b/test/dm/test-driver.c
@@ -157,3 +157,14 @@ U_BOOT_DRIVER(test_pre_reloc_drv) = {
 	.unbind	= test_manual_unbind,
 	.flags	= DM_FLAG_PRE_RELOC,
 };
+
+U_BOOT_DRIVER(test_act_dma_drv) = {
+	.name	= "test_act_dma_drv",
+	.id	= UCLASS_TEST,
+	.ops	= &test_manual_ops,
+	.bind	= test_manual_bind,
+	.probe	= test_manual_probe,
+	.remove	= test_manual_remove,
+	.unbind	= test_manual_unbind,
+	.flags	= DM_FLAG_ACTIVE_DMA,
+};
diff --git a/test/image/test-fit.py b/test/image/test-fit.py
index db0649f..b0d0538 100755
--- a/test/image/test-fit.py
+++ b/test/image/test-fit.py
@@ -11,6 +11,9 @@
 # make O=sandbox sandbox_config
 # make O=sandbox
 # ./test/image/test-fit.py -u sandbox/u-boot
+#
+# Note: The above testing requires the Python development package, typically
+# called python-devel or something similar.
 
 import doctest
 from optparse import OptionParser
@@ -115,8 +118,8 @@ base_fdt = '''
 };
 '''
 
-# This is the U-Boot script that is run for each test. First load the fit,
-# then do the 'bootm' command, then save out memory from the places where
+# This is the U-Boot script that is run for each test. First load the FIT,
+# then run the 'bootm' command, then save out memory from the places where
 # we expect 'bootm' to write things. Then quit.
 base_script = '''
 sb load hostfs 0 %(fit_addr)x %(fit)s
@@ -266,7 +269,7 @@ def find_matching(text, match):
 
     >>> find_matching('first line:10\\nsecond_line:20', 'first line:')
     '10'
-    >>> find_matching('first line:10\\nsecond_line:20', 'second linex')
+    >>> find_matching('first line:10\\nsecond_line:20', 'second line')
     Traceback (most recent call last):
       ...
     ValueError: Test aborted
@@ -389,7 +392,7 @@ def run_fit_test(mkimage, u_boot):
         fail('Ramdisk loaded but should not be', stdout)
 
     # Find out the offset in the FIT where U-Boot has found the FDT
-    line = find_matching(stdout, 'Booting using the fdt blob at ')
+    line = find_matching(stdout, 'Booting using the FDT blob at ')
     fit_offset = int(line, 16) - params['fit_addr']
     fdt_magic = struct.pack('>L', 0xd00dfeed)
     data = read_file(fit)
@@ -469,7 +472,7 @@ def run_tests():
     print '\nTests passed'
     print 'Caveat: this is only a sanity check - test coverage is poor'
 
-    # Remove the tempoerary directory unless we are asked to keep it
+    # Remove the temporary directory unless we are asked to keep it
     if options.keep:
         print "Output files are in '%s'" % base_dir
     else:
diff --git a/tools/.gitignore b/tools/.gitignore
index 0d1f076..6ec71f5 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -16,6 +16,7 @@
 /mkexynosspl
 /mxsboot
 /mksunxiboot
+/sunxi-spl-image-builder
 /ncb
 /proftool
 /relocate-rela
diff --git a/tools/Makefile b/tools/Makefile
index a894b5c..fa1b85b 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -120,7 +120,7 @@ _libfdt.so-sharedobjs += $(LIBFDT_OBJS)
 libfdt:
 
 tools/_libfdt.so: $(patsubst %.o,%.c,$(LIBFDT_OBJS)) tools/libfdt_wrap.c
-	LDFLAGS="$(HOSTLDFLAGS)" python $(srctree)/lib/libfdt/setup.py \
+	LDFLAGS="$(HOSTLDFLAGS)" CFLAGS= python $(srctree)/lib/libfdt/setup.py \
 		"$(_hostc_flags)" $^
 	mv _libfdt.so $@
 
@@ -179,6 +179,8 @@ hostprogs-$(CONFIG_MX28) += mxsboot
 HOSTCFLAGS_mxsboot.o := -pedantic
 
 hostprogs-$(CONFIG_ARCH_SUNXI) += mksunxiboot
+hostprogs-$(CONFIG_ARCH_SUNXI) += sunxi-spl-image-builder
+sunxi-spl-image-builder-objs := sunxi-spl-image-builder.o lib/bch.o
 
 hostprogs-$(CONFIG_NETCONSOLE) += ncb
 hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1
diff --git a/tools/binman/etype/intel_descriptor.py b/tools/binman/etype/intel_descriptor.py
index 7f4ea0b..6435749 100644
--- a/tools/binman/etype/intel_descriptor.py
+++ b/tools/binman/etype/intel_descriptor.py
@@ -37,9 +37,6 @@ class Entry_intel_descriptor(Entry_blob):
         Entry_blob.__init__(self, image, etype, node)
         self._regions = []
 
-    def GetDefaultFilename(self):
-        return 'descriptor.bin'
-
     def GetPositions(self):
         pos = self.data.find(FD_SIGNATURE)
         if pos == -1:
diff --git a/tools/binman/etype/intel_me.py b/tools/binman/etype/intel_me.py
index 45ab50c..5e1c799 100644
--- a/tools/binman/etype/intel_me.py
+++ b/tools/binman/etype/intel_me.py
@@ -12,6 +12,3 @@ from blob import Entry_blob
 class Entry_intel_me(Entry_blob):
     def __init__(self, image, etype, node):
         Entry_blob.__init__(self, image, etype, node)
-
-    def GetDefaultFilename(self):
-        return 'me.bin'
diff --git a/tools/binman/test/30_x86-rom-me-no-desc.dts b/tools/binman/test/30_x86-rom-me-no-desc.dts
index 4578f66..68d3ce0 100644
--- a/tools/binman/test/30_x86-rom-me-no-desc.dts
+++ b/tools/binman/test/30_x86-rom-me-no-desc.dts
@@ -9,6 +9,7 @@
 		end-at-4gb;
 		size = <16>;
 		intel-me {
+			filename = "me.bin";
 			pos-unset;
 		};
 	};
diff --git a/tools/binman/test/31_x86-rom-me.dts b/tools/binman/test/31_x86-rom-me.dts
index b484ab3..ee3dac8 100644
--- a/tools/binman/test/31_x86-rom-me.dts
+++ b/tools/binman/test/31_x86-rom-me.dts
@@ -9,9 +9,11 @@
 		end-at-4gb;
 		size = <0x800000>;
 		intel-descriptor {
+			filename = "descriptor.bin";
 		};
 
 		intel-me {
+			filename = "me.bin";
 			pos-unset;
 		};
 	};
diff --git a/tools/binman/test/32_intel-vga.dts b/tools/binman/test/32_intel-vga.dts
index 1790833..9c532d0 100644
--- a/tools/binman/test/32_intel-vga.dts
+++ b/tools/binman/test/32_intel-vga.dts
@@ -8,6 +8,7 @@
 		size = <16>;
 
 		intel-vga {
+			filename = "vga.bin";
 		};
 	};
 };
diff --git a/tools/binman/test/42_intel-fsp.dts b/tools/binman/test/42_intel-fsp.dts
index e0a1e76..8a7c889 100644
--- a/tools/binman/test/42_intel-fsp.dts
+++ b/tools/binman/test/42_intel-fsp.dts
@@ -8,6 +8,7 @@
 		size = <16>;
 
 		intel-fsp {
+			filename = "fsp.bin";
 		};
 	};
 };
diff --git a/tools/binman/test/43_intel-cmc.dts b/tools/binman/test/43_intel-cmc.dts
index 26c456d..5a56c7d 100644
--- a/tools/binman/test/43_intel-cmc.dts
+++ b/tools/binman/test/43_intel-cmc.dts
@@ -8,6 +8,7 @@
 		size = <16>;
 
 		intel-cmc {
+			filename = "cmc.bin";
 		};
 	};
 };
diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py
index bf67ec8..afc5171 100755
--- a/tools/dtoc/dtoc.py
+++ b/tools/dtoc/dtoc.py
@@ -172,6 +172,21 @@ class DtbPlatdata:
         """
         self.fdt = fdt_select.FdtScan(self._dtb_fname)
 
+    def ScanNode(self, root):
+        for node in root.subnodes:
+            if 'compatible' in node.props:
+                status = node.props.get('status')
+                if (not options.include_disabled and not status or
+                    status.value != 'disabled'):
+                    self._valid_nodes.append(node)
+                    phandle_prop = node.props.get('phandle')
+                    if phandle_prop:
+                        phandle = phandle_prop.GetPhandle()
+                        self._phandle_node[phandle] = node
+
+            # recurse to handle any subnodes
+            self.ScanNode(node);
+
     def ScanTree(self):
         """Scan the device tree for useful information
 
@@ -180,8 +195,10 @@ class DtbPlatdata:
             _valid_nodes: A list of nodes we wish to consider include in the
                 platform data
         """
-        node_list = []
         self._phandle_node = {}
+        self._valid_nodes = []
+        return self.ScanNode(self.fdt.GetRoot());
+
         for node in self.fdt.GetRoot().subnodes:
             if 'compatible' in node.props:
                 status = node.props.get('status')
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 862a0b1..299e0c9 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -34,6 +34,7 @@
 # include <mtd/mtd-user.h>
 #endif
 
+#include "fw_env_private.h"
 #include "fw_env.h"
 
 struct env_opts default_opts = {
@@ -277,6 +278,7 @@ int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts)
 
 			printf ("%s\n", env);
 		}
+		fw_env_close(opts);
 		return 0;
 	}
 
@@ -299,10 +301,12 @@ int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts)
 		printf("%s=%s\n", name, val);
 	}
 
+	fw_env_close(opts);
+
 	return rc;
 }
 
-int fw_env_close(struct env_opts *opts)
+int fw_env_flush(struct env_opts *opts)
 {
 	int ret;
 
@@ -471,6 +475,7 @@ int fw_setenv(int argc, char *argv[], struct env_opts *opts)
 	char *name, **valv;
 	char *value = NULL;
 	int valc;
+	int ret;
 
 	if (!opts)
 		opts = &default_opts;
@@ -490,8 +495,10 @@ int fw_setenv(int argc, char *argv[], struct env_opts *opts)
 	valv = argv + 1;
 	valc = argc - 1;
 
-	if (env_flags_validate_env_set_params(name, valv, valc) < 0)
+	if (env_flags_validate_env_set_params(name, valv, valc) < 0) {
+		fw_env_close(opts);
 		return -1;
+	}
 
 	len = 0;
 	for (i = 0; i < valc; ++i) {
@@ -517,7 +524,10 @@ int fw_setenv(int argc, char *argv[], struct env_opts *opts)
 
 	free(value);
 
-	return fw_env_close(opts);
+	ret = fw_env_flush(opts);
+	fw_env_close(opts);
+
+	return ret;
 }
 
 /*
@@ -638,7 +648,9 @@ int fw_parse_script(char *fname, struct env_opts *opts)
 	if (strcmp(fname, "-") != 0)
 		fclose(fp);
 
-	ret |= fw_env_close(opts);
+	ret |= fw_env_flush(opts);
+
+	fw_env_close(opts);
 
 	return ret;
 }
@@ -1104,11 +1116,11 @@ int fw_env_open(struct env_opts *opts)
 {
 	int crc0, crc0_ok;
 	unsigned char flag0;
-	void *addr0;
+	void *addr0 = NULL;
 
 	int crc1, crc1_ok;
 	unsigned char flag1;
-	void *addr1;
+	void *addr1 = NULL;
 
 	int ret;
 
@@ -1119,14 +1131,15 @@ int fw_env_open(struct env_opts *opts)
 		opts = &default_opts;
 
 	if (parse_config(opts))		/* should fill envdevices */
-		return -1;
+		return -EINVAL;
 
 	addr0 = calloc(1, CUR_ENVSIZE);
 	if (addr0 == NULL) {
 		fprintf(stderr,
 			"Not enough memory for environment (%ld bytes)\n",
 			CUR_ENVSIZE);
-		return -1;
+		ret = -ENOMEM;
+		goto open_cleanup;
 	}
 
 	/* read environment from FLASH to local buffer */
@@ -1145,8 +1158,10 @@ int fw_env_open(struct env_opts *opts)
 	}
 
 	dev_current = 0;
-	if (flash_io (O_RDONLY))
-		return -1;
+	if (flash_io(O_RDONLY)) {
+		ret = -EIO;
+		goto open_cleanup;
+	}
 
 	crc0 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE);
 
@@ -1154,7 +1169,7 @@ int fw_env_open(struct env_opts *opts)
 		ret = env_aes_cbc_crypt(environment.data, 0,
 					opts->aes_key);
 		if (ret)
-			return ret;
+			goto open_cleanup;
 	}
 
 	crc0_ok = (crc0 == *environment.crc);
@@ -1173,7 +1188,8 @@ int fw_env_open(struct env_opts *opts)
 			fprintf(stderr,
 				"Not enough memory for environment (%ld bytes)\n",
 				CUR_ENVSIZE);
-			return -1;
+			ret = -ENOMEM;
+			goto open_cleanup;
 		}
 		redundant = addr1;
 
@@ -1182,8 +1198,10 @@ int fw_env_open(struct env_opts *opts)
 		 * other pointers in environment still point inside addr0
 		 */
 		environment.image = addr1;
-		if (flash_io (O_RDONLY))
-			return -1;
+		if (flash_io(O_RDONLY)) {
+			ret = -EIO;
+			goto open_cleanup;
+		}
 
 		/* Check flag scheme compatibility */
 		if (DEVTYPE(dev_current) == MTD_NORFLASH &&
@@ -1203,7 +1221,8 @@ int fw_env_open(struct env_opts *opts)
 			environment.flag_scheme = FLAG_INCREMENTAL;
 		} else {
 			fprintf (stderr, "Incompatible flash types!\n");
-			return -1;
+			ret = -EINVAL;
+			goto open_cleanup;
 		}
 
 		crc1 = crc32 (0, (uint8_t *) redundant->data, ENV_SIZE);
@@ -1212,7 +1231,7 @@ int fw_env_open(struct env_opts *opts)
 			ret = env_aes_cbc_crypt(redundant->data, 0,
 						opts->aes_key);
 			if (ret)
-				return ret;
+				goto open_cleanup;
 		}
 
 		crc1_ok = (crc1 == redundant->crc);
@@ -1284,6 +1303,28 @@ int fw_env_open(struct env_opts *opts)
 #endif
 	}
 	return 0;
+
+open_cleanup:
+	if (addr0)
+		free(addr0);
+
+	if (addr1)
+		free(addr0);
+
+	return ret;
+}
+
+/*
+ * Simply free allocated buffer with environment
+ */
+int fw_env_close(struct env_opts *opts)
+{
+	if (environment.image)
+		free(environment.image);
+
+	environment.image = NULL;
+
+	return 0;
 }
 
 static int check_device_config(int dev)
diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h
index 05588ab..04bb646 100644
--- a/tools/env/fw_env.h
+++ b/tools/env/fw_env.h
@@ -5,57 +5,15 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <aes.h>
 #include <stdint.h>
-
-/* Pull in the current config to define the default environment */
-#include <linux/kconfig.h>
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__ /* get only #defines from config.h */
-#include <config.h>
-#undef	__ASSEMBLY__
-#else
-#include <config.h>
-#endif
+#include <uboot_aes.h>
 
 /*
- * To build the utility with the static configuration
- * comment out the next line.
- * See included "fw_env.config" sample file
- * for notes on configuration.
+ * Programs using the library must check which API is available,
+ * that varies depending on the U-Boot version.
+ * This can be changed in future
  */
-#define CONFIG_FILE     "/etc/fw_env.config"
-
-#ifndef CONFIG_FILE
-#define HAVE_REDUND /* For systems with 2 env sectors */
-#define DEVICE1_NAME      "/dev/mtd1"
-#define DEVICE2_NAME      "/dev/mtd2"
-#define DEVICE1_OFFSET    0x0000
-#define ENV1_SIZE         0x4000
-#define DEVICE1_ESIZE     0x4000
-#define DEVICE1_ENVSECTORS     2
-#define DEVICE2_OFFSET    0x0000
-#define ENV2_SIZE         0x4000
-#define DEVICE2_ESIZE     0x4000
-#define DEVICE2_ENVSECTORS     2
-#endif
-
-#ifndef CONFIG_BAUDRATE
-#define CONFIG_BAUDRATE		115200
-#endif
-
-#ifndef CONFIG_BOOTDELAY
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#ifndef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; "								\
-	"setenv bootargs root=/dev/nfs nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
-	"bootm"
-#endif
+#define FW_ENV_API_VERSION	1
 
 struct env_opts {
 #ifdef CONFIG_FILE
@@ -95,7 +53,7 @@ int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts);
  * @opts: how to retrieve environment from flash, defaults are used if NULL
  *
  * Description:
- *  Uses fw_env_open, fw_env_write, fw_env_close
+ *  Uses fw_env_open, fw_env_write, fw_env_flush
  *
  * Return:
  *  0 on success, -1 on failure (modifies errno)
@@ -112,7 +70,7 @@ int fw_setenv(int argc, char *argv[], struct env_opts *opts);
  * @opts: encryption key, configuration file, defaults are used if NULL
  *
  * Description:
- *  Uses fw_env_open, fw_env_write, fw_env_close
+ *  Uses fw_env_open, fw_env_write, fw_env_flush
  *
  * Return:
  *  0 success, -1 on failure (modifies errno)
@@ -180,7 +138,17 @@ char *fw_getenv(char *name);
 int fw_env_write(char *name, char *value);
 
 /**
- * fw_env_close - write the environment from RAM cache back to flash
+ * fw_env_flush - write the environment from RAM cache back to flash
+ *
+ * @opts: encryption key, configuration file, defaults are used if NULL
+ *
+ * Return:
+ *  0 on success, -1 on failure (modifies errno)
+ */
+int fw_env_flush(struct env_opts *opts);
+
+/**
+ * fw_env_close - free allocated structure and close env
  *
  * @opts: encryption key, configuration file, defaults are used if NULL
  *
@@ -189,4 +157,13 @@ int fw_env_write(char *name, char *value);
  */
 int fw_env_close(struct env_opts *opts);
 
+
+/**
+ * fw_env_version - return the current version of the library
+ *
+ * Return:
+ *  version string of the library
+ */
+char *fw_env_version(void);
+
 unsigned long crc32(unsigned long, const unsigned char *, unsigned);
diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c
index 443de36..b8bff26 100644
--- a/tools/env/fw_env_main.c
+++ b/tools/env/fw_env_main.c
@@ -34,6 +34,7 @@
 #include <stdlib.h>
 #include <sys/file.h>
 #include <unistd.h>
+#include "fw_env_private.h"
 #include "fw_env.h"
 
 #define CMD_PRINTENV	"fw_printenv"
diff --git a/tools/env/fw_env_private.h b/tools/env/fw_env_private.h
new file mode 100644
index 0000000..0c27da0
--- /dev/null
+++ b/tools/env/fw_env_private.h
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2002-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Pull in the current config to define the default environment */
+#include <linux/kconfig.h>
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__ /* get only #defines from config.h */
+#include <config.h>
+#undef	__ASSEMBLY__
+#else
+#include <config.h>
+#endif
+
+/*
+ * To build the utility with the static configuration
+ * comment out the next line.
+ * See included "fw_env.config" sample file
+ * for notes on configuration.
+ */
+#define CONFIG_FILE     "/etc/fw_env.config"
+
+#ifndef CONFIG_FILE
+#define HAVE_REDUND /* For systems with 2 env sectors */
+#define DEVICE1_NAME      "/dev/mtd1"
+#define DEVICE2_NAME      "/dev/mtd2"
+#define DEVICE1_OFFSET    0x0000
+#define ENV1_SIZE         0x4000
+#define DEVICE1_ESIZE     0x4000
+#define DEVICE1_ENVSECTORS     2
+#define DEVICE2_OFFSET    0x0000
+#define ENV2_SIZE         0x4000
+#define DEVICE2_ESIZE     0x4000
+#define DEVICE2_ENVSECTORS     2
+#endif
+
+#ifndef CONFIG_BAUDRATE
+#define CONFIG_BAUDRATE		115200
+#endif
+
+#ifndef CONFIG_BOOTDELAY
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#ifndef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND						\
+	"bootp; "							\
+	"setenv bootargs root=/dev/nfs nfsroot=${serverip}:${rootpath} "\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "\
+	"bootm"
+#endif
diff --git a/tools/pblimage.c b/tools/pblimage.c
index 16d94c98..ffc3268 100644
--- a/tools/pblimage.c
+++ b/tools/pblimage.c
@@ -194,17 +194,20 @@ void pbl_load_uboot(int ifd, struct image_tool_params *params)
 	pbl_parser(params->imagename);
 
 	/* parse the pbi.cfg file. */
-	pbl_parser(params->imagename2);
+	if (params->imagename2[0] != '\0')
+		pbl_parser(params->imagename2);
+
+	if (params->datafile) {
+		fp_uboot = fopen(params->datafile, "r");
+		if (fp_uboot == NULL) {
+			printf("Error: %s open failed\n", params->datafile);
+			exit(EXIT_FAILURE);
+		}
 
-	fp_uboot = fopen(params->datafile, "r");
-	if (fp_uboot == NULL) {
-		printf("Error: %s open failed\n", params->datafile);
-		exit(EXIT_FAILURE);
+		load_uboot(fp_uboot);
+		fclose(fp_uboot);
 	}
-
-	load_uboot(fp_uboot);
 	add_end_cmd();
-	fclose(fp_uboot);
 	lseek(ifd, 0, SEEK_SET);
 
 	size = pbl_size;
@@ -265,21 +268,24 @@ int pblimage_check_params(struct image_tool_params *params)
 	if (!params)
 		return EXIT_FAILURE;
 
-	fp_uboot = fopen(params->datafile, "r");
-	if (fp_uboot == NULL) {
-		printf("Error: %s open failed\n", params->datafile);
-		exit(EXIT_FAILURE);
-	}
-	fd = fileno(fp_uboot);
+	if (params->datafile) {
+		fp_uboot = fopen(params->datafile, "r");
+		if (fp_uboot == NULL) {
+			printf("Error: %s open failed\n", params->datafile);
+			exit(EXIT_FAILURE);
+		}
+		fd = fileno(fp_uboot);
 
-	if (fstat(fd, &st) == -1) {
-		printf("Error: Could not determine u-boot image size. %s\n",
-		       strerror(errno));
-		exit(EXIT_FAILURE);
-	}
+		if (fstat(fd, &st) == -1) {
+			printf("Error: Could not determine u-boot image size. %s\n",
+			       strerror(errno));
+			exit(EXIT_FAILURE);
+		}
 
-	/* For the variable size, we need to pad it to 64 byte boundary */
-	uboot_size = roundup(st.st_size, 64);
+		/* For the variable size, pad it to 64 byte boundary */
+		uboot_size = roundup(st.st_size, 64);
+		fclose(fp_uboot);
+	}
 
 	if (params->arch == IH_ARCH_ARM) {
 		arch_flag = IH_ARCH_ARM;
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 6595e02..6cdb749 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -41,25 +41,37 @@ struct header0_info {
 };
 
 /**
+ * struct header1_info
+ */
+struct header1_info {
+	uint32_t magic;
+};
+
+/**
  * struct spl_info - spl info for each chip
  *
  * @imagename:		Image name(passed by "mkimage -n")
  * @spl_hdr:		Boot ROM requires a 4-bytes spl header
  * @spl_size:		Spl size(include extra 4-bytes spl header)
  * @spl_rc4:		RC4 encode the SPL binary (same key as header)
+ * @spl_boot0:          A new-style (ARM_SOC_BOOT0_HOOK) image that should
+ *                      have the boot magic (e.g. 'RK33') written to its first
+ *                      word.
  */
+
 struct spl_info {
 	const char *imagename;
 	const char *spl_hdr;
 	const uint32_t spl_size;
 	const bool spl_rc4;
+	const bool spl_boot0;
 };
 
 static struct spl_info spl_infos[] = {
-	{ "rk3036", "RK30", 0x1000, false },
-	{ "rk3188", "RK31", 0x8000 - 0x800, true },
-	{ "rk3288", "RK32", 0x8000, false },
-	{ "rk3399", "RK33", 0x20000, false },
+	{ "rk3036", "RK30", 0x1000, false, false },
+	{ "rk3188", "RK31", 0x8000 - 0x800, true, false },
+	{ "rk3288", "RK32", 0x8000, false, false },
+	{ "rk3399", "RK33", 0x20000, false, true },
 };
 
 static unsigned char rc4_key[16] = {
@@ -106,6 +118,7 @@ const char *rkcommon_get_spl_hdr(struct image_tool_params *params)
 	return info->spl_hdr;
 }
 
+
 int rkcommon_get_spl_size(struct image_tool_params *params)
 {
 	struct spl_info *info = rkcommon_get_spl_info(params->imagename);
@@ -126,16 +139,22 @@ bool rkcommon_need_rc4_spl(struct image_tool_params *params)
 	return info->spl_rc4;
 }
 
-int rkcommon_set_header(void *buf, uint file_size,
-			struct image_tool_params *params)
+bool rkcommon_spl_is_boot0(struct image_tool_params *params)
 {
-	struct header0_info *hdr;
+	struct spl_info *info = rkcommon_get_spl_info(params->imagename);
 
-	if (file_size > rkcommon_get_spl_size(params))
-		return -ENOSPC;
+	/*
+	 * info would not be NULL, because of we checked params before.
+	 */
+	return info->spl_boot0;
+}
+
+static void rkcommon_set_header0(void *buf, uint file_size,
+				 struct image_tool_params *params)
+{
+	struct header0_info *hdr = buf;
 
-	memset(buf,  '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
-	hdr = (struct header0_info *)buf;
+	memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
 	hdr->signature = RK_SIGNATURE;
 	hdr->disable_rc4 = !rkcommon_need_rc4_spl(params);
 	hdr->init_offset = RK_INIT_OFFSET;
@@ -145,6 +164,24 @@ int rkcommon_set_header(void *buf, uint file_size,
 	hdr->init_boot_size = hdr->init_size + RK_MAX_BOOT_SIZE / RK_BLK_SIZE;
 
 	rc4_encode(buf, RK_BLK_SIZE, rc4_key);
+}
+
+int rkcommon_set_header(void *buf, uint file_size,
+			struct image_tool_params *params)
+{
+	struct header1_info *hdr = buf + RK_SPL_HDR_START;
+
+	if (file_size > rkcommon_get_spl_size(params))
+		return -ENOSPC;
+
+	rkcommon_set_header0(buf, file_size, params);
+
+	/* Set up the SPL name and add the AArch64 'nop' padding, if needed */
+	memcpy(&hdr->magic, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE);
+
+	if (rkcommon_need_rc4_spl(params))
+		rkcommon_rc4_encode_spl(buf, RK_SPL_HDR_START,
+					params->file_size - RK_SPL_HDR_START);
 
 	return 0;
 }
@@ -161,3 +198,34 @@ void rkcommon_rc4_encode_spl(void *buf, unsigned int offset, unsigned int size)
 		remaining -= step;
 	}
 }
+
+void rkcommon_vrec_header(struct image_tool_params *params,
+			  struct image_type_params *tparams)
+{
+	/*
+	 * The SPL image looks as follows:
+	 *
+	 * 0x0    header0 (see rkcommon.c)
+	 * 0x800  spl_name ('RK30', ..., 'RK33')
+	 * 0x804  first instruction to be executed
+	 *        (image start for AArch32, 'nop' for AArch64))
+	 * 0x808  second instruction to be executed
+	 *        (image start for AArch64)
+	 *
+	 * For AArch64 (ARMv8) payloads, we receive an input file that
+	 * needs to start on an 8-byte boundary (natural alignment), so
+	 * we need to put a NOP at 0x804.
+	 *
+	 * Depending on this, the header is either 0x804 or 0x808 bytes
+	 * in length.
+	 */
+	if (rkcommon_spl_is_boot0(params))
+		tparams->header_size = RK_SPL_HDR_START;
+	else
+		tparams->header_size = RK_SPL_HDR_START + 4;
+
+	/* Allocate, clear and install the header */
+	tparams->hdr = malloc(tparams->header_size);
+	memset(tparams->hdr, 0, tparams->header_size);
+	tparams->header_size = tparams->header_size;
+}
diff --git a/tools/rkcommon.h b/tools/rkcommon.h
index b4f6f32..cc161a6 100644
--- a/tools/rkcommon.h
+++ b/tools/rkcommon.h
@@ -77,4 +77,14 @@ bool rkcommon_need_rc4_spl(struct image_tool_params *params);
  */
 void rkcommon_rc4_encode_spl(void *buf, unsigned int offset, unsigned int size);
 
+/**
+ * rkcommon_vrec_header() - allocate memory for the header
+ *
+ * @params:     Pointer to the tool params structure
+ * @tparams:    Pointer tot the image type structure (for setting
+ *              the header and header_size)
+ */
+void rkcommon_vrec_header(struct image_tool_params *params,
+			  struct image_type_params *tparams);
+
 #endif
diff --git a/tools/rksd.c b/tools/rksd.c
index ff2233f..ac8a67d 100644
--- a/tools/rksd.c
+++ b/tools/rksd.c
@@ -13,8 +13,6 @@
 #include "mkimage.h"
 #include "rkcommon.h"
 
-static char dummy_hdr[RK_IMAGE_HEADER_LEN];
-
 static int rksd_verify_header(unsigned char *buf,  int size,
 				 struct image_tool_params *params)
 {
@@ -38,13 +36,6 @@ static void rksd_set_header(void *buf,  struct stat *sbuf,  int ifd,
 		printf("Warning: SPL image is too large (size %#x) and will not boot\n",
 		       size);
 	}
-
-	memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params),
-	       RK_SPL_HDR_SIZE);
-
-	if (rkcommon_need_rc4_spl(params))
-		rkcommon_rc4_encode_spl(buf, RK_SPL_START - 4,
-					params->file_size - RK_SPL_START + 4);
 }
 
 static int rksd_extract_subimage(void *buf,  struct image_tool_params *params)
@@ -66,10 +57,12 @@ static int rksd_vrec_header(struct image_tool_params *params,
 {
 	int pad_size;
 
+	rkcommon_vrec_header(params, tparams);
+
 	pad_size = RK_SPL_HDR_START + rkcommon_get_spl_size(params);
 	debug("pad_size %x\n", pad_size);
 
-	return pad_size - params->file_size;
+	return pad_size - params->file_size - tparams->header_size;
 }
 
 /*
@@ -78,8 +71,8 @@ static int rksd_vrec_header(struct image_tool_params *params,
 U_BOOT_IMAGE_TYPE(
 	rksd,
 	"Rockchip SD Boot Image support",
-	RK_IMAGE_HEADER_LEN,
-	dummy_hdr,
+	0,
+	NULL,
 	rkcommon_check_params,
 	rksd_verify_header,
 	rksd_print_header,
diff --git a/tools/rkspi.c b/tools/rkspi.c
index 0271d2e..d2d3fdd 100644
--- a/tools/rkspi.c
+++ b/tools/rkspi.c
@@ -17,8 +17,6 @@ enum {
 	RKSPI_SECT_LEN		= RK_BLK_SIZE * 4,
 };
 
-static char dummy_hdr[RK_IMAGE_HEADER_LEN];
-
 static int rkspi_verify_header(unsigned char *buf, int size,
 			       struct image_tool_params *params)
 {
@@ -45,13 +43,6 @@ static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd,
 		       size);
 	}
 
-	memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params),
-	       RK_SPL_HDR_SIZE);
-
-	if (rkcommon_need_rc4_spl(params))
-		rkcommon_rc4_encode_spl(buf, RK_SPL_START - 4,
-					params->file_size - RK_SPL_START + 4);
-
 	/*
 	 * Spread the image out so we only use the first 2KB of each 4KB
 	 * region. This is a feature of the SPI format required by the Rockchip
@@ -86,6 +77,8 @@ static int rkspi_vrec_header(struct image_tool_params *params,
 {
 	int pad_size;
 
+	rkcommon_vrec_header(params, tparams);
+
 	pad_size = (rkcommon_get_spl_size(params) + 0x7ff) / 0x800 * 0x800;
 	params->orig_file_size = pad_size;
 
@@ -94,7 +87,7 @@ static int rkspi_vrec_header(struct image_tool_params *params,
 	pad_size += RK_SPL_HDR_START;
 	debug("pad_size %x\n", pad_size);
 
-	return pad_size - params->file_size;
+	return pad_size - params->file_size - tparams->header_size;
 }
 
 /*
@@ -103,8 +96,8 @@ static int rkspi_vrec_header(struct image_tool_params *params,
 U_BOOT_IMAGE_TYPE(
 	rkspi,
 	"Rockchip SPI Boot Image support",
-	RK_IMAGE_HEADER_LEN,
-	dummy_hdr,
+	0,
+	NULL,
 	rkcommon_check_params,
 	rkspi_verify_header,
 	rkspi_print_header,
diff --git a/tools/sunxi-spl-image-builder.c b/tools/sunxi-spl-image-builder.c
new file mode 100644
index 0000000..d538a38
--- /dev/null
+++ b/tools/sunxi-spl-image-builder.c
@@ -0,0 +1,484 @@
+/*
+ * Allwinner NAND randomizer and image builder implementation:
+ *
+ * Copyright © 2016 NextThing Co.
+ * Copyright © 2016 Free Electrons
+ *
+ * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
+ *
+ */
+
+#include <linux/bch.h>
+
+#include <getopt.h>
+#include <version.h>
+
+#define BCH_PRIMITIVE_POLY	0x5803
+
+#define ARRAY_SIZE(arr)		(sizeof(arr) / sizeof((arr)[0]))
+#define DIV_ROUND_UP(n,d)	(((n) + (d) - 1) / (d))
+
+struct image_info {
+	int ecc_strength;
+	int ecc_step_size;
+	int page_size;
+	int oob_size;
+	int usable_page_size;
+	int eraseblock_size;
+	int scramble;
+	int boot0;
+	off_t offset;
+	const char *source;
+	const char *dest;
+};
+
+static void swap_bits(uint8_t *buf, int len)
+{
+	int i, j;
+
+	for (j = 0; j < len; j++) {
+		uint8_t byte = buf[j];
+
+		buf[j] = 0;
+		for (i = 0; i < 8; i++) {
+			if (byte & (1 << i))
+				buf[j] |= (1 << (7 - i));
+		}
+	}
+}
+
+static uint16_t lfsr_step(uint16_t state, int count)
+{
+	state &= 0x7fff;
+	while (count--)
+		state = ((state >> 1) |
+			 ((((state >> 0) ^ (state >> 1)) & 1) << 14)) & 0x7fff;
+
+	return state;
+}
+
+static uint16_t default_scrambler_seeds[] = {
+	0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
+	0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
+	0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
+	0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
+	0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
+	0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
+	0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
+	0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
+	0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
+	0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
+	0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
+	0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
+	0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
+	0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
+	0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
+	0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
+};
+
+static uint16_t brom_scrambler_seeds[] = { 0x4a80 };
+
+static void scramble(const struct image_info *info,
+		     int page, uint8_t *data, int datalen)
+{
+	uint16_t state;
+	int i;
+
+	/* Boot0 is always scrambled no matter the command line option. */
+	if (info->boot0) {
+		state = brom_scrambler_seeds[0];
+	} else {
+		unsigned seedmod = info->eraseblock_size / info->page_size;
+
+		/* Bail out earlier if the user didn't ask for scrambling. */
+		if (!info->scramble)
+			return;
+
+		if (seedmod > ARRAY_SIZE(default_scrambler_seeds))
+			seedmod = ARRAY_SIZE(default_scrambler_seeds);
+
+		state = default_scrambler_seeds[page % seedmod];
+	}
+
+	/* Prepare the initial state... */
+	state = lfsr_step(state, 15);
+
+	/* and start scrambling data. */
+	for (i = 0; i < datalen; i++) {
+		data[i] ^= state;
+		state = lfsr_step(state, 8);
+	}
+}
+
+static int write_page(const struct image_info *info, uint8_t *buffer,
+		      FILE *src, FILE *rnd, FILE *dst,
+		      struct bch_control *bch, int page)
+{
+	int steps = info->usable_page_size / info->ecc_step_size;
+	int eccbytes = DIV_ROUND_UP(info->ecc_strength * 14, 8);
+	off_t pos = ftell(dst);
+	size_t pad, cnt;
+	int i;
+
+	if (eccbytes % 2)
+		eccbytes++;
+
+	memset(buffer, 0xff, info->page_size + info->oob_size);
+	cnt = fread(buffer, 1, info->usable_page_size, src);
+	if (!cnt) {
+		if (!feof(src)) {
+			fprintf(stderr,
+				"Failed to read data from the source\n");
+			return -1;
+		} else {
+			return 0;
+		}
+	}
+
+	fwrite(buffer, info->page_size + info->oob_size, 1, dst);
+
+	for (i = 0; i < info->usable_page_size; i++) {
+		if (buffer[i] !=  0xff)
+			break;
+	}
+
+	/* We leave empty pages at 0xff. */
+	if (i == info->usable_page_size)
+		return 0;
+
+	/* Restore the source pointer to read it again. */
+	fseek(src, -cnt, SEEK_CUR);
+
+	/* Randomize unused space if scrambling is required. */
+	if (info->scramble) {
+		int offs;
+
+		if (info->boot0) {
+			size_t ret;
+
+			offs = steps * (info->ecc_step_size + eccbytes + 4);
+			cnt = info->page_size + info->oob_size - offs;
+			ret = fread(buffer + offs, 1, cnt, rnd);
+			if (!ret && !feof(rnd)) {
+				fprintf(stderr,
+					"Failed to read random data\n");
+				return -1;
+			}
+		} else {
+			offs = info->page_size + (steps * (eccbytes + 4));
+			cnt = info->page_size + info->oob_size - offs;
+			memset(buffer + offs, 0xff, cnt);
+			scramble(info, page, buffer + offs, cnt);
+		}
+		fseek(dst, pos + offs, SEEK_SET);
+		fwrite(buffer + offs, cnt, 1, dst);
+	}
+
+	for (i = 0; i < steps; i++) {
+		int ecc_offs, data_offs;
+		uint8_t *ecc;
+
+		memset(buffer, 0xff, info->ecc_step_size + eccbytes + 4);
+		ecc = buffer + info->ecc_step_size + 4;
+		if (info->boot0) {
+			data_offs = i * (info->ecc_step_size + eccbytes + 4);
+			ecc_offs = data_offs + info->ecc_step_size + 4;
+		} else {
+			data_offs = i * info->ecc_step_size;
+			ecc_offs = info->page_size + 4 + (i * (eccbytes + 4));
+		}
+
+		cnt = fread(buffer, 1, info->ecc_step_size, src);
+		if (!cnt && !feof(src)) {
+			fprintf(stderr,
+				"Failed to read data from the source\n");
+			return -1;
+		}
+
+		pad = info->ecc_step_size - cnt;
+		if (pad) {
+			if (info->scramble && info->boot0) {
+				size_t ret;
+
+				ret = fread(buffer + cnt, 1, pad, rnd);
+				if (!ret && !feof(rnd)) {
+					fprintf(stderr,
+						"Failed to read random data\n");
+					return -1;
+				}
+			} else {
+				memset(buffer + cnt, 0xff, pad);
+			}
+		}
+
+		memset(ecc, 0, eccbytes);
+		swap_bits(buffer, info->ecc_step_size + 4);
+		encode_bch(bch, buffer, info->ecc_step_size + 4, ecc);
+		swap_bits(buffer, info->ecc_step_size + 4);
+		swap_bits(ecc, eccbytes);
+		scramble(info, page, buffer, info->ecc_step_size + 4 + eccbytes);
+
+		fseek(dst, pos + data_offs, SEEK_SET);
+		fwrite(buffer, info->ecc_step_size, 1, dst);
+		fseek(dst, pos + ecc_offs - 4, SEEK_SET);
+		fwrite(ecc - 4, eccbytes + 4, 1, dst);
+	}
+
+	/* Fix BBM. */
+	fseek(dst, pos + info->page_size, SEEK_SET);
+	memset(buffer, 0xff, 2);
+	fwrite(buffer, 2, 1, dst);
+
+	/* Make dst pointer point to the next page. */
+	fseek(dst, pos + info->page_size + info->oob_size, SEEK_SET);
+
+	return 0;
+}
+
+static int create_image(const struct image_info *info)
+{
+	off_t page = info->offset / info->page_size;
+	struct bch_control *bch;
+	FILE *src, *dst, *rnd;
+	uint8_t *buffer;
+
+	bch = init_bch(14, info->ecc_strength, BCH_PRIMITIVE_POLY);
+	if (!bch) {
+		fprintf(stderr, "Failed to init the BCH engine\n");
+		return -1;
+	}
+
+	buffer = malloc(info->page_size + info->oob_size);
+	if (!buffer) {
+		fprintf(stderr, "Failed to allocate the NAND page buffer\n");
+		return -1;
+	}
+
+	memset(buffer, 0xff, info->page_size + info->oob_size);
+
+	src = fopen(info->source, "r");
+	if (!src) {
+		fprintf(stderr, "Failed to open source file (%s)\n",
+			info->source);
+		return -1;
+	}
+
+	dst = fopen(info->dest, "w");
+	if (!dst) {
+		fprintf(stderr, "Failed to open dest file (%s)\n", info->dest);
+		return -1;
+	}
+
+	rnd = fopen("/dev/urandom", "r");
+	if (!rnd) {
+		fprintf(stderr, "Failed to open /dev/urandom\n");
+		return -1;
+	}
+
+	while (!feof(src)) {
+		int ret;
+
+		ret = write_page(info, buffer, src, rnd, dst, bch, page++);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static void display_help(int status)
+{
+	fprintf(status == EXIT_SUCCESS ? stdout : stderr,
+		"sunxi-nand-image-builder %s\n"
+		"\n"
+		"Usage: sunxi-nand-image-builder [OPTIONS] source-image output-image\n"
+		"\n"
+		"Creates a raw NAND image that can be read by the sunxi NAND controller.\n"
+		"\n"
+		"-h               --help               Display this help and exit\n"
+		"-c <str>/<step>  --ecc=<str>/<step>   ECC config (strength/step-size)\n"
+		"-p <size>        --page=<size>        Page size\n"
+		"-o <size>        --oob=<size>         OOB size\n"
+		"-u <size>        --usable=<size>      Usable page size\n"
+		"-e <size>        --eraseblock=<size>  Erase block size\n"
+		"-b               --boot0              Build a boot0 image.\n"
+		"-s               --scramble           Scramble data\n"
+		"-a <offset>      --address=<offset>   Where the image will be programmed.\n"
+		"\n"
+		"Notes:\n"
+		"All the information you need to pass to this tool should be part of\n"
+		"the NAND datasheet.\n"
+		"\n"
+		"The NAND controller only supports the following ECC configs\n"
+		"  Valid ECC strengths: 16, 24, 28, 32, 40, 48, 56, 60 and 64\n"
+		"  Valid ECC step size: 512 and 1024\n"
+		"\n"
+		"If you are building a boot0 image, you'll have specify extra options.\n"
+		"These options should be chosen based on the layouts described here:\n"
+		"  http://linux-sunxi.org/NAND#More_information_on_BROM_NAND\n"
+		"\n"
+		"  --usable should be assigned the 'Hardware page' value\n"
+		"  --ecc should be assigned the 'ECC capacity'/'ECC page' values\n"
+		"  --usable should be smaller than --page\n"
+		"\n"
+		"The --address option is only required for non-boot0 images that are \n"
+		"meant to be programmed at a non eraseblock aligned offset.\n"
+		"\n"
+		"Examples:\n"
+		"  The H27UCG8T2BTR-BC NAND exposes\n"
+		"  * 16k pages\n"
+		"  * 1280 OOB bytes per page\n"
+		"  * 4M eraseblocks\n"
+		"  * requires data scrambling\n"
+		"  * expects a minimum ECC of 40bits/1024bytes\n"
+		"\n"
+		"  A normal image can be generated with\n"
+		"    sunxi-nand-image-builder -p 16384 -o 1280 -e 0x400000 -s -c 40/1024\n"
+		"  A boot0 image can be generated with\n"
+		"    sunxi-nand-image-builder -p 16384 -o 1280 -e 0x400000 -s -b -u 4096 -c 64/1024\n",
+		PLAIN_VERSION);
+	exit(status);
+}
+
+static int check_image_info(struct image_info *info)
+{
+	static int valid_ecc_strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
+	int eccbytes, eccsteps;
+	unsigned i;
+
+	if (!info->page_size) {
+		fprintf(stderr, "--page is missing\n");
+		return -EINVAL;
+	}
+
+	if (!info->page_size) {
+		fprintf(stderr, "--oob is missing\n");
+		return -EINVAL;
+	}
+
+	if (!info->eraseblock_size) {
+		fprintf(stderr, "--eraseblock is missing\n");
+		return -EINVAL;
+	}
+
+	if (info->ecc_step_size != 512 && info->ecc_step_size != 1024) {
+		fprintf(stderr, "Invalid ECC step argument: %d\n",
+			info->ecc_step_size);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(valid_ecc_strengths); i++) {
+		if (valid_ecc_strengths[i] == info->ecc_strength)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(valid_ecc_strengths)) {
+		fprintf(stderr, "Invalid ECC strength argument: %d\n",
+			info->ecc_strength);
+		return -EINVAL;
+	}
+
+	eccbytes = DIV_ROUND_UP(info->ecc_strength * 14, 8);
+	if (eccbytes % 2)
+		eccbytes++;
+	eccbytes += 4;
+
+	eccsteps = info->usable_page_size / info->ecc_step_size;
+
+	if (info->page_size + info->oob_size <
+	    info->usable_page_size + (eccsteps * eccbytes)) {
+		fprintf(stderr,
+			"ECC bytes do not fit in the NAND page, choose a weaker ECC\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int main(int argc, char **argv)
+{
+	struct image_info info;
+
+	memset(&info, 0, sizeof(info));
+	/*
+	 * Process user arguments
+	 */
+	for (;;) {
+		int option_index = 0;
+		char *endptr = NULL;
+		static const struct option long_options[] = {
+			{"help", no_argument, 0, 'h'},
+			{"ecc", required_argument, 0, 'c'},
+			{"page", required_argument, 0, 'p'},
+			{"oob", required_argument, 0, 'o'},
+			{"usable", required_argument, 0, 'u'},
+			{"eraseblock", required_argument, 0, 'e'},
+			{"boot0", no_argument, 0, 'b'},
+			{"scramble", no_argument, 0, 's'},
+			{"address", required_argument, 0, 'a'},
+			{0, 0, 0, 0},
+		};
+
+		int c = getopt_long(argc, argv, "c:p:o:u:e:ba:sh",
+				long_options, &option_index);
+		if (c == EOF)
+			break;
+
+		switch (c) {
+		case 'h':
+			display_help(0);
+			break;
+		case 's':
+			info.scramble = 1;
+			break;
+		case 'c':
+			info.ecc_strength = strtol(optarg, &endptr, 0);
+			if (endptr || *endptr == '/')
+				info.ecc_step_size = strtol(endptr + 1, NULL, 0);
+			break;
+		case 'p':
+			info.page_size = strtol(optarg, NULL, 0);
+			break;
+		case 'o':
+			info.oob_size = strtol(optarg, NULL, 0);
+			break;
+		case 'u':
+			info.usable_page_size = strtol(optarg, NULL, 0);
+			break;
+		case 'e':
+			info.eraseblock_size = strtol(optarg, NULL, 0);
+			break;
+		case 'b':
+			info.boot0 = 1;
+			break;
+		case 'a':
+			info.offset = strtoull(optarg, NULL, 0);
+			break;
+		case '?':
+			display_help(-1);
+			break;
+		}
+	}
+
+	if ((argc - optind) != 2)
+		display_help(-1);
+
+	info.source = argv[optind];
+	info.dest = argv[optind + 1];
+
+	if (!info.boot0) {
+		info.usable_page_size = info.page_size;
+	} else if (!info.usable_page_size) {
+		if (info.page_size > 8192)
+			info.usable_page_size = 8192;
+		else if (info.page_size > 4096)
+			info.usable_page_size = 4096;
+		else
+			info.usable_page_size = 1024;
+	}
+
+	if (check_image_info(&info))
+		display_help(-1);
+
+	return create_image(&info);
+}