diff options
Diffstat (limited to 'board')
57 files changed, 1139 insertions, 209 deletions
diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 4c3a9ba..263bb54 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -13,7 +13,7 @@ #include <command.h> #include <i2c.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/arch/gpio.h> @@ -26,8 +26,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { /* GPIO configuration */ - kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH, - NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH); + mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH, + NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -77,7 +77,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2; /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 3773587..17e6296 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -12,7 +12,7 @@ #include <common.h> #include <command.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/arch/gpio.h> @@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { /* Gpio configuration */ - kw_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH, - NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH); + mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH, + NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -73,7 +73,7 @@ int board_init(void) gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c index 2dc5018..8620e4b 100644 --- a/board/LaCie/wireless_space/wireless_space.c +++ b/board/LaCie/wireless_space/wireless_space.c @@ -12,7 +12,7 @@ #include <common.h> #include <command.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/arch/gpio.h> @@ -97,8 +97,8 @@ struct mv88e61xx_config swcfg = { int board_early_init_f(void) { /* Gpio configuration */ - kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, - WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); + mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, + WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ kirkwood_mpp_conf(kwmpp_config, NULL); @@ -112,7 +112,7 @@ int board_init(void) gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig new file mode 100644 index 0000000..f94a444 --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/Kconfig @@ -0,0 +1,23 @@ +if TARGET_DB_MV784MP_GP + +config SYS_CPU + string + default "armv7" + +config SYS_BOARD + string + default "db-mv784mp-gp" + +config SYS_VENDOR + string + default "Marvell" + +config SYS_SOC + string + default "armada-xp" + +config SYS_CONFIG_NAME + string + default "db-mv784mp-gp" + +endif diff --git a/board/Marvell/db-mv784mp-gp/MAINTAINERS b/board/Marvell/db-mv784mp-gp/MAINTAINERS new file mode 100644 index 0000000..a095f89 --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/MAINTAINERS @@ -0,0 +1,6 @@ +DB_MV784MP_GP BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/Marvell/db-mv784mp-gp/ +F: include/configs/db-mv784mp-gp.h +F: configs/db-mv784mp-gp_defconfig diff --git a/board/Marvell/db-mv784mp-gp/Makefile b/board/Marvell/db-mv784mp-gp/Makefile new file mode 100644 index 0000000..8f5a7fb --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := db-mv784mp-gp.o diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c new file mode 100644 index 0000000..b3dae89 --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define BIT(nr) (1UL << (nr)) + +#define ETH_PHY_CTRL_REG 0 +#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) + +/* + * Those values and defines are taken from the Marvell U-Boot version + * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka + * "RD-AXP-GP rev 1.0". + * + * GPPs + * MPP# NAME IN/OUT + * ---------------------------------------------- + * 21 SW_Reset_ OUT + * 25 Phy_Int# IN + * 28 SDI_WP IN + * 29 SDI_Status IN + * 54-61 On GPP Connector ? + * 62 Switch Interrupt IN + * 63-65 Reserved from SW Board ? + * 66 SW_BRD connected IN + */ +#define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20))) +#define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27))) +#define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0)) + +#define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20)) +#define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27)) +#define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0 + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x00000000, MVEBU_MPP_BASE + 0x00); + writel(0x00000000, MVEBU_MPP_BASE + 0x04); + writel(0x33000000, MVEBU_MPP_BASE + 0x08); + writel(0x11000000, MVEBU_MPP_BASE + 0x0c); + writel(0x11111111, MVEBU_MPP_BASE + 0x10); + writel(0x00221100, MVEBU_MPP_BASE + 0x14); + writel(0x00000003, MVEBU_MPP_BASE + 0x18); + writel(0x00000000, MVEBU_MPP_BASE + 0x1c); + writel(0x00000000, MVEBU_MPP_BASE + 0x20); + + /* Configure GPIO */ + writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); + writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Marvell DB-MV784MP-GP\n"); + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1545 PHY */ +void reset_phy(void) +{ + u16 devadr = CONFIG_PHY_BASE_ADDR; + char *name = "neta0"; + u16 reg; + + if (miiphy_set_current_dev(name)) + return; + + /* Enable QSGMII AN */ + /* Set page to 4 */ + miiphy_write(name, devadr, 0x16, 4); + /* Enable AN */ + miiphy_write(name, devadr, 0x0, 0x1140); + /* Set page to 0 */ + miiphy_write(name, devadr, 0x16, 0); + + /* Phy C_ANEG */ + miiphy_read(name, devadr, 0x4, ®); + reg |= 0x1E0; + miiphy_write(name, devadr, 0x4, reg); + + /* Soft-Reset */ + miiphy_write(name, devadr, 22, 0x0000); + miiphy_write(name, devadr, 0, 0x9140); + + /* Power up the phy */ + miiphy_read(name, devadr, ETH_PHY_CTRL_REG, ®); + reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK); + miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg); + + printf("88E1545 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/db-mv784mp-gp/kwbimage.cfg b/board/Marvell/db-mv784mp-gp/kwbimage.cfg new file mode 100644 index 0000000..d7ef407 --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/Marvell/db-mv784mp-gp/binary.0 0000005b 00000068 diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index b53c810..0887d92 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -12,7 +12,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "dreamplug.h" @@ -25,9 +25,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(DREAMPLUG_OE_VAL_LOW, - DREAMPLUG_OE_VAL_HIGH, - DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH); + mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW, + DREAMPLUG_OE_VAL_HIGH, + DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -90,7 +90,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index 72bccc8..b0d5f1e 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -9,7 +9,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "guruplug.h" @@ -22,9 +22,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(GURUPLUG_OE_VAL_LOW, - GURUPLUG_OE_VAL_HIGH, - GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); + mvebu_config_gpio(GURUPLUG_OE_VAL_LOW, + GURUPLUG_OE_VAL_HIGH, + GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -92,7 +92,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index e1652c0..ef08ad8 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -11,7 +11,7 @@ #include <common.h> #include <netdev.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "mv88f6281gtw_ge.h" @@ -24,9 +24,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW, - MV88F6281GTW_GE_OE_VAL_HIGH, - MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH); + mvebu_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW, + MV88F6281GTW_GE_OE_VAL_HIGH, + MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -94,7 +94,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index a005a2f..55cf525 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -14,7 +14,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "openrd.h" @@ -27,9 +27,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(OPENRD_OE_VAL_LOW, - OPENRD_OE_VAL_HIGH, - OPENRD_OE_LOW, OPENRD_OE_HIGH); + mvebu_config_gpio(OPENRD_OE_VAL_LOW, + OPENRD_OE_VAL_HIGH, + OPENRD_OE_LOW, OPENRD_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -104,7 +104,7 @@ int board_init(void) #endif /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index 33ef0c7..b0020c9 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -10,7 +10,7 @@ #include <miiphy.h> #include <netdev.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "rd6281a.h" @@ -23,9 +23,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(RD6281A_OE_VAL_LOW, - RD6281A_OE_VAL_HIGH, - RD6281A_OE_LOW, RD6281A_OE_HIGH); + mvebu_config_gpio(RD6281A_OE_VAL_LOW, + RD6281A_OE_VAL_HIGH, + RD6281A_OE_LOW, RD6281A_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -93,7 +93,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_RD88F6281; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 87e49f4..8907fb5 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -9,7 +9,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "sheevaplug.h" @@ -22,9 +22,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW, - SHEEVAPLUG_OE_VAL_HIGH, - SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH); + mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW, + SHEEVAPLUG_OE_VAL_HIGH, + SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -92,7 +92,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index ff6a6a0..83ab1bc 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -11,7 +11,7 @@ #include <common.h> #include <miiphy.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/arch/cpu.h> #include <asm/io.h> @@ -26,9 +26,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(DOCKSTAR_OE_VAL_LOW, - DOCKSTAR_OE_VAL_HIGH, - DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH); + mvebu_config_gpio(DOCKSTAR_OE_VAL_LOW, + DOCKSTAR_OE_VAL_HIGH, + DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -96,7 +96,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR; /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } @@ -143,7 +143,7 @@ void reset_phy(void) static void set_leds(u32 leds, u32 blinking) { - struct kwgpio_registers *r = (struct kwgpio_registers *)KW_GPIO1_BASE; + struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; u32 oe = readl(&r->oe) | BOTH_LEDS; writel(oe & ~leds, &r->oe); /* active low */ u32 bl = readl(&r->blink_en) & ~BOTH_LEDS; diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c index a6598e9..1f4fb92 100644 --- a/board/Seagate/goflexhome/goflexhome.c +++ b/board/Seagate/goflexhome/goflexhome.c @@ -14,7 +14,7 @@ #include <common.h> #include <miiphy.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/arch/cpu.h> #include <asm/io.h> @@ -83,9 +83,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(GOFLEXHOME_OE_VAL_LOW, - GOFLEXHOME_OE_VAL_HIGH, - GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH); + mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW, + GOFLEXHOME_OE_VAL_HIGH, + GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH); kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } @@ -98,7 +98,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME; /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } @@ -149,7 +149,7 @@ static void set_leds(u32 leds, u32 blinking) u32 oe; u32 bl; - r = (struct kwgpio_registers *)KW_GPIO1_BASE; + r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; oe = readl(&r->oe) | BOTH_LEDS; writel(oe & ~leds, &r->oe); /* active low */ bl = readl(&r->blink_en) & ~BOTH_LEDS; diff --git a/board/atmel/at91rm9200ek/led.c b/board/atmel/at91rm9200ek/led.c index 2298e36..6761b14 100644 --- a/board/atmel/at91rm9200ek/led.c +++ b/board/atmel/at91rm9200ek/led.c @@ -14,6 +14,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pio.h> +#include <status_led.h> /* bit mask in PIO port B */ #define GREEN_LED (1<<0) diff --git a/board/atmel/at91sam9260ek/led.c b/board/atmel/at91sam9260ek/led.c index 56d811c..fbe15af 100644 --- a/board/atmel/at91sam9260ek/led.c +++ b/board/atmel/at91sam9260ek/led.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/gpio.h> +#include <status_led.h> void coloured_LED_init(void) { diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index c1cb07b..b0d49c4 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -15,7 +15,7 @@ #include <miiphy.h> #include <spi.h> #include <spi_flash.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/cpu.h> #include <asm/arch/mpp.h> #include <asm/arch/gpio.h> @@ -52,9 +52,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(LSXL_OE_VAL_LOW, - LSXL_OE_VAL_HIGH, - LSXL_OE_LOW, LSXL_OE_HIGH); + mvebu_config_gpio(LSXL_OE_VAL_LOW, + LSXL_OE_VAL_HIGH, + LSXL_OE_LOW, LSXL_OE_HIGH); /* * Multi-Purpose Pins Functionality configuration @@ -168,7 +168,7 @@ static void set_led(int state) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; set_led(LED_POWER_BLINKING); diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile index 4f2ac89..27ebe78 100644 --- a/board/chromebook-x86/coreboot/Makefile +++ b/board/chromebook-x86/coreboot/Makefile @@ -12,4 +12,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += coreboot_start.o +obj-y += coreboot_start.o coreboot.o diff --git a/board/chromebook-x86/coreboot/coreboot.c b/board/chromebook-x86/coreboot/coreboot.c new file mode 100644 index 0000000..0240c34 --- /dev/null +++ b/board/chromebook-x86/coreboot/coreboot.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <cros_ec.h> + +int arch_early_init_r(void) +{ + if (cros_ec_board_init()) + return -1; + + return 0; +} diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c index 0e63258..8309d06 100644 --- a/board/cloudengines/pogo_e02/pogo_e02.c +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -13,7 +13,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "pogo_e02.h" @@ -26,9 +26,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(POGO_E02_OE_VAL_LOW, - POGO_E02_OE_VAL_HIGH, - POGO_E02_OE_LOW, POGO_E02_OE_HIGH); + mvebu_config_gpio(POGO_E02_OE_VAL_LOW, + POGO_E02_OE_VAL_HIGH, + POGO_E02_OE_LOW, POGO_E02_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -64,7 +64,7 @@ int board_early_init_f(void) int board_init(void) { /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index f77ff48..82681b1 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -15,7 +15,6 @@ #include <netdev.h> #include <fdt_support.h> #include <sata.h> -#include <serial_mxc.h> #include <asm/arch/crm_regs.h> #include <asm/arch/sys_proto.h> #include <asm/arch/iomux.h> @@ -23,6 +22,7 @@ #include <asm/imx-common/sata.h> #include <asm/io.h> #include <asm/gpio.h> +#include <dm/platform_data/serial_mxc.h> #include "common.h" #include "../common/eeprom.h" diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c index ff70e94..a022daf 100644 --- a/board/d-link/dns325/dns325.c +++ b/board/d-link/dns325/dns325.c @@ -14,7 +14,7 @@ #include <miiphy.h> #include <netdev.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/arch/gpio.h> #include "dns325.h" @@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { /* Gpio configuration */ - kw_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH, - DNS325_OE_LOW, DNS325_OE_HIGH); + mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH, + DNS325_OE_LOW, DNS325_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -92,7 +92,7 @@ int board_early_init_f(void) int board_init(void) { /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c index c3443bd..086a473 100644 --- a/board/iomega/iconnect/iconnect.c +++ b/board/iomega/iconnect/iconnect.c @@ -9,7 +9,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "iconnect.h" @@ -22,9 +22,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(ICONNECT_OE_VAL_LOW, - ICONNECT_OE_VAL_HIGH, - ICONNECT_OE_LOW, ICONNECT_OE_HIGH); + mvebu_config_gpio(ICONNECT_OE_VAL_LOW, + ICONNECT_OE_VAL_HIGH, + ICONNECT_OE_LOW, ICONNECT_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -87,7 +87,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 3b2b1f1..7b87cc2 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -5,6 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> +#include <ns16550.h> #include <twl4030.h> #include <netdev.h> #include <asm/gpio.h> @@ -30,6 +32,17 @@ static const u32 gpmc_lan_config[] = { }; #endif +static const struct ns16550_platdata igep_serial = { + OMAP34XX_UART3, + 2, + V_NS16550_CLK +}; + +U_BOOT_DEVICE(igep_uart) = { + "serial_omap", + &igep_serial +}; + /* * Routine: board_init * Description: Early hardware init. diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c index ed0575c..35546d2 100644 --- a/board/karo/tk71/tk71.c +++ b/board/karo/tk71/tk71.c @@ -8,7 +8,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/io.h> @@ -26,9 +26,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(TK71_OE_VAL_LOW, - TK71_OE_VAL_HIGH, - TK71_OE_LOW, TK71_OE_HIGH); + mvebu_config_gpio(TK71_OE_VAL_LOW, + TK71_OE_VAL_HIGH, + TK71_OE_LOW, TK71_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -97,7 +97,7 @@ int board_init(void) gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 35402c8..1c7c108 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -20,7 +20,7 @@ #include <spi.h> #include <asm/io.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "../common/common.h" @@ -222,11 +222,11 @@ int board_early_init_f(void) u32 tmp; /* set the 2 bitbang i2c pins as output gpios */ - tmp = readl(KW_GPIO0_BASE + 4); - writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); + tmp = readl(MVEBU_GPIO0_BASE + 4); + writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4); #endif /* adjust SDRAM size for bank 0 */ - kw_sdram_size_adjust(0); + mvebu_sdram_size_adjust(0); kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } @@ -234,7 +234,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; /* * The KM_FLASH_GPIO_PIN switches between using a diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 461a852..9ef0026 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -15,6 +15,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> +#include <ns16550.h> #include <netdev.h> #include <twl4030.h> #include <asm/io.h> @@ -41,6 +43,17 @@ static const u32 gpmc_lab_enet[] = { /*CONF7- computed as params */ }; +static const struct ns16550_platdata zoom1_serial = { + OMAP34XX_UART3, + 2, + V_NS16550_CLK +}; + +U_BOOT_DEVICE(zoom1_uart) = { + "serial_omap", + &zoom1_serial +}; + /* * Routine: board_init * Description: Early hardware init. diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig new file mode 100644 index 0000000..d34e2ab --- /dev/null +++ b/board/maxbcm/Kconfig @@ -0,0 +1,19 @@ +if TARGET_MAXBCM + +config SYS_CPU + string + default "armv7" + +config SYS_BOARD + string + default "maxbcm" + +config SYS_SOC + string + default "armada-xp" + +config SYS_CONFIG_NAME + string + default "maxbcm" + +endif diff --git a/board/maxbcm/MAINTAINERS b/board/maxbcm/MAINTAINERS new file mode 100644 index 0000000..3c8af21 --- /dev/null +++ b/board/maxbcm/MAINTAINERS @@ -0,0 +1,6 @@ +MAXBCM BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/maxbcm/ +F: include/configs/maxbcm.h +F: configs/maxbcm_defconfig diff --git a/board/maxbcm/Makefile b/board/maxbcm/Makefile new file mode 100644 index 0000000..37c17d6 --- /dev/null +++ b/board/maxbcm/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := maxbcm.o diff --git a/board/maxbcm/kwbimage.cfg b/board/maxbcm/kwbimage.cfg new file mode 100644 index 0000000..5a3bc67 --- /dev/null +++ b/board/maxbcm/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/maxbcm/binary.0 0000005b 00000068 diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c new file mode 100644 index 0000000..7fc83ee --- /dev/null +++ b/board/maxbcm/maxbcm.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <linux/mbus.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Base addresses for the external device chip selects */ +#define DEV_CS0_BASE 0xe0000000 +#define DEV_CS1_BASE 0xe1000000 +#define DEV_CS2_BASE 0xe2000000 +#define DEV_CS3_BASE 0xe3000000 + +/* Needed for dynamic (board-specific) mbus configuration */ +extern struct mvebu_mbus_state mbus_state; + +int board_early_init_f(void) +{ + /* + * Don't configure MPP (pin multiplexing) and GPIO here, + * its already done in bin_hdr + */ + + /* + * Setup some board specific mbus address windows + */ + mbus_dt_setup_win(&mbus_state, DEV_CS0_BASE, 16 << 20, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0); + mbus_dt_setup_win(&mbus_state, DEV_CS1_BASE, 16 << 20, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1); + mbus_dt_setup_win(&mbus_state, DEV_CS2_BASE, 16 << 20, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2); + mbus_dt_setup_win(&mbus_state, DEV_CS3_BASE, 16 << 20, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: maxBCM\n"); + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E6185 switch */ +void reset_phy(void) +{ + u16 devadr = CONFIG_PHY_BASE_ADDR; + char *name = "neta0"; + u16 reg; + + if (miiphy_set_current_dev(name)) + return; + + /* todo: fill this with the real setup / config code */ + + printf("88E6185 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 03f055d..51125df 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -47,46 +47,19 @@ const struct tegra_sysinfo sysinfo = { CONFIG_TEGRA_BOARD_STRING }; -void __pinmux_init(void) -{ -} - -void pinmux_init(void) __attribute__((weak, alias("__pinmux_init"))); - -void __pin_mux_usb(void) -{ -} - -void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb"))); - -void __pin_mux_spi(void) -{ -} - -void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi"))); - -void __gpio_early_init_uart(void) -{ -} - -void gpio_early_init_uart(void) -__attribute__((weak, alias("__gpio_early_init_uart"))); +__weak void pinmux_init(void) {} +__weak void pin_mux_usb(void) {} +__weak void pin_mux_spi(void) {} +__weak void gpio_early_init_uart(void) {} +__weak void pin_mux_display(void) {} #if defined(CONFIG_TEGRA_NAND) -void __pin_mux_nand(void) +__weak void pin_mux_nand(void) { funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); } - -void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand"))); #endif -void __pin_mux_display(void) -{ -} - -void pin_mux_display(void) __attribute__((weak, alias("__pin_mux_display"))); - /* * Routine: power_det_init * Description: turn off power detects @@ -204,12 +177,10 @@ int board_late_init(void) } #if defined(CONFIG_TEGRA_MMC) -void __pin_mux_mmc(void) +__weak void pin_mux_mmc(void) { } -void pin_mux_mmc(void) __attribute__((weak, alias("__pin_mux_mmc"))); - /* this is a weak define that we are overriding */ int board_mmc_init(bd_t *bd) { diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c index 8124f8a..8c62f36 100644 --- a/board/nvidia/common/emc.c +++ b/board/nvidia/common/emc.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include "emc.h" #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/emc.h> diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h index d338818..de4eb35 100644 --- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h +++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h @@ -283,6 +283,11 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PEX_WAKE_N_PDD3, PE, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 6a243f0..11472eb 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -8,6 +8,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/tegra.h> +#include <asm/arch-tegra/board.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/gpio.h> diff --git a/board/overo/overo.c b/board/overo/overo.c index 66146ee..dfb8602 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -13,6 +13,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> +#include <ns16550.h> #include <netdev.h> #include <twl4030.h> #include <linux/mtd/nand.h> @@ -65,6 +67,17 @@ static struct { char env_setting[64]; } expansion_config = {0x0}; +static const struct ns16550_platdata overo_serial = { + OMAP34XX_UART3, + 2, + V_NS16550_CLK +}; + +U_BOOT_DEVICE(overo_uart) = { + "serial_omap", + &overo_serial +}; + /* * Routine: board_init * Description: Early hardware init. diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c index 976ba4c..f01fb1c 100644 --- a/board/raidsonic/ib62x0/ib62x0.c +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -11,7 +11,7 @@ #include <miiphy.h> #include <asm/io.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "ib62x0.h" @@ -24,9 +24,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(IB62x0_OE_VAL_LOW, - IB62x0_OE_VAL_HIGH, - IB62x0_OE_LOW, IB62x0_OE_HIGH); + mvebu_config_gpio(IB62x0_OE_VAL_LOW, + IB62x0_OE_VAL_HIGH, + IB62x0_OE_LOW, IB62x0_OE_HIGH); /* Set SATA activity LEDs to default off */ writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG); @@ -62,7 +62,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi_b/rpi_b.c index 447c940..7445f53 100644 --- a/board/raspberrypi/rpi_b/rpi_b.c +++ b/board/raspberrypi/rpi_b/rpi_b.c @@ -42,6 +42,12 @@ struct msg_get_arm_mem { u32 end_tag; }; +struct msg_get_mac_address { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_get_mac_address get_mac_address; + u32 end_tag; +}; + struct msg_set_power_state { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_set_power_state set_power_state; @@ -73,6 +79,29 @@ int dram_init(void) return 0; } +int misc_init_r(void) +{ + ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16); + int ret; + + if (getenv("usbethaddr")) + return 0; + + BCM2835_MBOX_INIT_HDR(msg); + BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS); + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); + if (ret) { + printf("bcm2835: Could not query MAC address\n"); + /* Ignore error; not critical */ + return 0; + } + + eth_setenv_enetaddr("usbethaddr", msg->get_mac_address.body.resp.mac); + + return 0; +} + static int power_on_module(u32 module) { ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16); diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index e1fc123..8b4c8e9 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -28,19 +28,15 @@ DECLARE_GLOBAL_DATA_PTR; -int __exynos_early_init_f(void) +__weak int exynos_early_init_f(void) { return 0; } -int exynos_early_init_f(void) - __attribute__((weak, alias("__exynos_early_init_f"))); -int __exynos_power_init(void) +__weak int exynos_power_init(void) { return 0; } -int exynos_power_init(void) - __attribute__((weak, alias("__exynos_power_init"))); #if defined CONFIG_EXYNOS_TMU /* Boot Time Thermal Analysis for SoC temperature threshold breach */ diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index bcd0a55..31a1503 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -1,25 +1,12 @@ -if TARGET_SUN4I +if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I || TARGET_SUN8I config SYS_CONFIG_NAME - default "sun4i" - -endif - -if TARGET_SUN5I - -config SYS_CONFIG_NAME - default "sun5i" - -endif - -if TARGET_SUN7I - -config SYS_CONFIG_NAME - default "sun7i" - -endif - -if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN7I + string + default "sun4i" if TARGET_SUN4I + default "sun5i" if TARGET_SUN5I + default "sun6i" if TARGET_SUN6I + default "sun7i" if TARGET_SUN7I + default "sun8i" if TARGET_SUN8I config SYS_CPU default "armv7" @@ -33,4 +20,45 @@ config SYS_SOC config FDTFILE string "Default fdtfile env setting for this board" +config OLD_SUNXI_KERNEL_COMPAT + boolean "Enable workarounds for booting old kernels" + default n + ---help--- + Set this to enable various workarounds for old kernels, this results in + sub-optimal settings for newer kernels, only enable if needed. + +config MMC0_CD_PIN + string "Card detect pin for mmc0" + default "" + ---help--- + Set the card detect pin for mmc0, leave empty to not use cd. This + takes a string in the format understood by sunxi_name_to_gpio, e.g. + PH1 for pin 1 of port H. + +config MMC1_CD_PIN + string "Card detect pin for mmc1" + default "" + ---help--- + See MMC0_CD_PIN help text. + +config MMC2_CD_PIN + string "Card detect pin for mmc2" + default "" + ---help--- + See MMC0_CD_PIN help text. + +config MMC3_CD_PIN + string "Card detect pin for mmc3" + default "" + ---help--- + See MMC0_CD_PIN help text. + +config MMC_SUNXI_SLOT_EXTRA + int "mmc extra slot number" + default -1 + ---help--- + sunxi builds always enable mmc0, some boards also have a second sdcard + slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable + support for this. + endif diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 4f32195..febd126 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -8,6 +8,7 @@ F: configs/ba10_tv_box_defconfig F: configs/Cubieboard_defconfig F: configs/Mele_A1000_defconfig F: configs/Mele_A1000G_defconfig +F: configs/Mele_M3_defconfig F: configs/Mini-X_defconfig F: configs/Mini-X-1Gb_defconfig F: include/configs/sun5i.h @@ -38,3 +39,19 @@ M: FUKAUMI Naoki <naobsd@gmail.com> S: Maintained F: board/sunxi/dram_a20_olinuxino_l.c F: configs/A20-OLinuXino-Lime_defconfig + +A20-OLINUXINO-LIME2 BOARD +M: Iain Paton <ipaton0@gmail.com> +S: Maintained +F: board/sunxi/dram_a20_olinuxino_l2.c +F: configs/A20-OLinuXino-Lime2_defconfig + +COLOMBUS BOARD +M: Maxime Ripard <maxime.ripard@free-electrons.com> +S: Maintained +F: configs/Colombus_defconfig + +IPPO-Q8H-V5 BOARD +M: CHen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/Ippo_q8h_v5_defconfig diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index 56073a0..6a2e4c9 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_A10S_OLINUXINO_M) += dram_a10s_olinuxino_m.o obj-$(CONFIG_A13_OLINUXINO) += dram_a13_olinuxino.o obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o obj-$(CONFIG_A20_OLINUXINO_L) += dram_a20_olinuxino_l.o +obj-$(CONFIG_A20_OLINUXINO_L2) += dram_a20_olinuxino_l2.o obj-$(CONFIG_A20_OLINUXINO_M) += dram_sun7i_384_1024_iow16.o # This is not a typo, uses the same mem settings as the a10s-olinuxino-m obj-$(CONFIG_AUXTEK_T004) += dram_a10s_olinuxino_m.o @@ -27,6 +28,7 @@ obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o obj-$(CONFIG_I12_TVBOX) += dram_sun7i_384_1024_iow16.o obj-$(CONFIG_MELE_A1000) += dram_sun4i_360_512.o obj-$(CONFIG_MELE_A1000G) += dram_sun4i_360_1024_iow8.o +obj-$(CONFIG_MELE_M3) += dram_sun7i_384_1024_iow16.o obj-$(CONFIG_MINI_X) += dram_sun4i_360_512.o obj-$(CONFIG_MINI_X_1GB) += dram_sun4i_360_1024_iow16.o obj-$(CONFIG_PCDUINO3) += dram_linksprite_pcduino3.o diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 2179e23..03890c8 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -12,6 +12,7 @@ */ #include <common.h> +#include <mmc.h> #ifdef CONFIG_AXP152_POWER #include <axp152.h> #endif @@ -70,9 +71,9 @@ static void mmc_pinmux_setup(int sdc) break; case 1: - /* CMD-PH22, CLK-PH23, D0~D3-PH24~27 : 5 */ - for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1); + /* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */ + for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN5I_GPG3_SDC1); sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); sunxi_gpio_set_drv(pin, 2); } @@ -104,11 +105,36 @@ static void mmc_pinmux_setup(int sdc) int board_mmc_init(bd_t *bis) { + __maybe_unused struct mmc *mmc0, *mmc1; + __maybe_unused char buf[512]; + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); - sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); -#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA) + mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); + if (!mmc0) + return -1; + +#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); - sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); + mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); + if (!mmc1) + return -1; +#endif + +#if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 + /* + * Both mmc0 and mmc2 are bootable, figure out where we're booting + * from. Try mmc0 first, just like the brom does. + */ + if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 && + mmc0->block_dev.block_read(0, 16, 1, buf) == 1) { + buf[12] = 0; + if (strcmp(&buf[4], "eGON.BT0") == 0) + return 0; + } + + /* no bootable card in mmc0, so we must be booting from mmc2, swap */ + mmc0->block_dev.dev = 1; + mmc1->block_dev.dev = 0; #endif return 0; diff --git a/board/sunxi/dram_a20_olinuxino_l2.c b/board/sunxi/dram_a20_olinuxino_l2.c new file mode 100644 index 0000000..2115d37 --- /dev/null +++ b/board/sunxi/dram_a20_olinuxino_l2.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include <common.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 480, + .type = 3, + .rank_num = 1, + .density = 4096, + .io_width = 16, + .bus_width = 32, + .cas = 9, + .zq = 0x7f, + .odt_en = 0, + .size = 1024, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0x4, + .emr2 = 0x10, + .emr3 = 0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index 054e7cc..a4aed3b 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -16,6 +16,8 @@ #include <asm/omap_gpio.h> #include <asm/arch/mmc_host_def.h> #include <i2c.h> +#include <spl.h> +#include <mmc.h> #include <asm/gpio.h> #ifdef CONFIG_USB_EHCI #include <usb.h> diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 94b99bf..4c5e381 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -14,6 +14,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> +#include <ns16550.h> #ifdef CONFIG_STATUS_LED #include <status_led.h> #endif @@ -70,6 +72,17 @@ static struct { char env_setting[64]; } expansion_config; +static const struct ns16550_platdata beagle_serial = { + OMAP34XX_UART3, + 2, + V_NS16550_CLK +}; + +U_BOOT_DEVICE(beagle_uart) = { + "serial_omap", + &beagle_serial +}; + /* * Routine: board_init * Description: Early hardware init. @@ -103,22 +116,22 @@ int board_init(void) */ static int get_board_revision(void) { - int revision; - - if (!gpio_request(171, "") && - !gpio_request(172, "") && - !gpio_request(173, "")) { - - gpio_direction_input(171); - gpio_direction_input(172); - gpio_direction_input(173); - - revision = gpio_get_value(173) << 2 | - gpio_get_value(172) << 1 | - gpio_get_value(171); - } else { - printf("Error: unable to acquire board revision GPIOs\n"); - revision = -1; + static int revision = -1; + + if (revision == -1) { + if (!gpio_request(171, "rev0") && + !gpio_request(172, "rev1") && + !gpio_request(173, "rev2")) { + gpio_direction_input(171); + gpio_direction_input(172); + gpio_direction_input(173); + + revision = gpio_get_value(173) << 2 | + gpio_get_value(172) << 1 | + gpio_get_value(171); + } else { + printf("Error: unable to acquire board revision GPIOs\n"); + } } return revision; @@ -258,7 +271,7 @@ static void beagle_dvi_pup(void) case REVISION_AXBX: case REVISION_CX: case REVISION_C4: - gpio_request(170, ""); + gpio_request(170, "dvi"); gpio_direction_output(170, 0); gpio_set_value(170, 1); break; diff --git a/board/ti/beagle/led.c b/board/ti/beagle/led.c index 89b8dd3..a913a4c 100644 --- a/board/ti/beagle/led.c +++ b/board/ti/beagle/led.c @@ -27,47 +27,46 @@ void green_led_on(void) } #endif +static int get_led_gpio(led_id_t mask) +{ +#ifdef STATUS_LED_BIT + if (STATUS_LED_BIT & mask) + return BEAGLE_LED_USR0; +#endif +#ifdef STATUS_LED_BIT1 + if (STATUS_LED_BIT1 & mask) + return BEAGLE_LED_USR1; +#endif + + return 0; +} + void __led_init (led_id_t mask, int state) { - __led_set (mask, state); + int toggle_gpio; + + toggle_gpio = get_led_gpio(mask); + + if (toggle_gpio && !gpio_request(toggle_gpio, "led")) + __led_set(mask, state); } void __led_toggle (led_id_t mask) { - int state, toggle_gpio = 0; -#ifdef STATUS_LED_BIT - if (!toggle_gpio && STATUS_LED_BIT & mask) - toggle_gpio = BEAGLE_LED_USR0; -#endif -#ifdef STATUS_LED_BIT1 - if (!toggle_gpio && STATUS_LED_BIT1 & mask) - toggle_gpio = BEAGLE_LED_USR1; -#endif + int state, toggle_gpio; + + toggle_gpio = get_led_gpio(mask); if (toggle_gpio) { - if (!gpio_request(toggle_gpio, "")) { - gpio_direction_output(toggle_gpio, 0); - state = gpio_get_value(toggle_gpio); - gpio_set_value(toggle_gpio, !state); - } + state = gpio_get_value(toggle_gpio); + gpio_direction_output(toggle_gpio, !state); } } void __led_set (led_id_t mask, int state) { -#ifdef STATUS_LED_BIT - if (STATUS_LED_BIT & mask) { - if (!gpio_request(BEAGLE_LED_USR0, "")) { - gpio_direction_output(BEAGLE_LED_USR0, 0); - gpio_set_value(BEAGLE_LED_USR0, state); - } - } -#endif -#ifdef STATUS_LED_BIT1 - if (STATUS_LED_BIT1 & mask) { - if (!gpio_request(BEAGLE_LED_USR1, "")) { - gpio_direction_output(BEAGLE_LED_USR1, 0); - gpio_set_value(BEAGLE_LED_USR1, state); - } - } -#endif + int toggle_gpio; + + toggle_gpio = get_led_gpio(mask); + if (toggle_gpio) + gpio_direction_output(toggle_gpio, state); } diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig new file mode 100644 index 0000000..f1dcda5 --- /dev/null +++ b/board/toradex/apalis_t30/Kconfig @@ -0,0 +1,12 @@ +if TARGET_APALIS_T30 + +config SYS_BOARD + default "apalis_t30" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "apalis_t30" + +endif diff --git a/board/toradex/apalis_t30/MAINTAINERS b/board/toradex/apalis_t30/MAINTAINERS new file mode 100644 index 0000000..01bc73e --- /dev/null +++ b/board/toradex/apalis_t30/MAINTAINERS @@ -0,0 +1,7 @@ +Apalis T30 +M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +S: Maintained +F: board/toradex/apalis_t30/ +F: include/configs/apalis_t30.h +F: configs/apalis_t30_defconfig +F: arch/arm/dts/tegra30-apalis.dtb diff --git a/board/toradex/apalis_t30/Makefile b/board/toradex/apalis_t30/Makefile new file mode 100644 index 0000000..a968e6b --- /dev/null +++ b/board/toradex/apalis_t30/Makefile @@ -0,0 +1,6 @@ +# Copyright (c) 2014 Marcel Ziswiler +# SPDX-License-Identifier: GPL-2.0+ + +include $(srctree)/board/nvidia/common/common.mk + +obj-y += apalis_t30.o diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c new file mode 100644 index 0000000..b9d694a --- /dev/null +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2014 + * Marcel Ziswiler <marcel@ziswiler.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#include <asm/arch/gp_padctrl.h> +#include <asm/arch/pinmux.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <netdev.h> + +#include "pinmux-config-apalis_t30.h" + +#define PMU_I2C_ADDRESS 0x2D +#define MAX_I2C_RETRY 3 + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_pingrp_table(tegra3_pinmux_common, + ARRAY_SIZE(tegra3_pinmux_common)); + + pinmux_config_pingrp_table(unused_pins_lowpower, + ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + pinmux_config_drvgrp_table(apalis_t30_padctrl, + ARRAY_SIZE(apalis_t30_padctrl)); +} + +#ifdef CONFIG_PCI_TEGRA +int tegra_pcie_board_init(void) +{ + unsigned int old_bus; + u8 addr, data[1]; + int err; + + old_bus = i2c_get_bus_num(); + + err = i2c_set_bus_num(0); + if (err) { + debug("failed to set I2C bus\n"); + return err; + } + + /* TPS659110: VDD2_OP_REG = 1.05V */ + data[0] = 0x27; + addr = 0x25; + + err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1); + if (err) { + debug("failed to set VDD supply\n"); + return err; + } + + /* TPS659110: VDD2_REG 7.5 mV/us, ACTIVE */ + data[0] = 0x0D; + addr = 0x24; + + err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1); + if (err) { + debug("failed to enable VDD supply\n"); + return err; + } + + /* TPS659110: LDO6_REG = 1.1V, ACTIVE */ + data[0] = 0x0D; + addr = 0x35; + + err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1); + if (err) { + debug("failed to set AVDD supply\n"); + return err; + } + + i2c_set_bus_num(old_bus); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} +#endif /* CONFIG_PCI_TEGRA */ diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h new file mode 100644 index 0000000..c988d39 --- /dev/null +++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2014, Marcel Ziswiler + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _PINMUX_CONFIG_APALIS_T30_H_ +#define _PINMUX_CONFIG_APALIS_T30_H_ + +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static struct pmux_pingrp_config tegra3_pinmux_common[] = { + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, NORMAL, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, NORMAL, NORMAL, INPUT), + + /* SDMMC4 pinmux (eMMC) */ + LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C3 pinmux */ + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE), + + /* I2C4 pinmux */ + I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* Power I2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), + /* UARTA RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_SDIN_PZ2, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT_PN5, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_CS0_N_PN4, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_SCK_PZ4, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT), + LV_PINMUX(VI_D0_PT4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D1_PD5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D2_PL0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D3_PL1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D5_PL3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D7_PL5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D10_PT2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D11_PT3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_HSYNC_PD7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, PWM0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU0, RSVD1, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(PU1, RSVD1, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(PU2, RSVD1, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(PU3, PWM0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU6, PWM3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD10_PH2, NAND, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_A17_PB0, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_A18_PB1, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_A19_PK7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), + + /* multiplexed VI_D2, VI_D3, VI_D4, VI_D5, VI_D6, VI_D7, VI_D8 and VI_D9 + */ + DEFAULT_PINMUX(KB_ROW0_PR0, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, TRISTATE, INPUT), + + /* GPIOs */ + DEFAULT_PINMUX(KB_ROW10_PS2, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11_PS3, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12_PS4, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13_PS5, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14_PS6, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15_PS7, SDMMC2, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3_PQ3, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(PV0, RSVD1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT), + /* multiplexed KB_COL0 */ + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, TRISTATE, OUTPUT), + + DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD12_PH4, NAND, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD14_PH6, NAND, DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, NORMAL, INPUT), +}; + +static struct pmux_pingrp_config unused_pins_lowpower[] = { + DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CLK_PK1, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD0_PG0, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD1_PG1, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD2_PG2, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD3_PG3, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD4_PG4, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD5_PG5, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD6_PG6, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD7_PG7, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD11_PH3, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD13_PH5, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_DQS_PI2, NAND, DOWN, TRISTATE, OUTPUT), +}; + +static struct pmux_drvgrp_config apalis_t30_padctrl[] = { + /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), +}; +#endif /* _PINMUX_CONFIG_APALIS_T30_H_ */ diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index ed043f4..f4bc7d8 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -35,7 +35,7 @@ void pinmux_init(void) void pin_mux_usb(void) { /* Reset ASIX using LAN_RESET */ - gpio_request(GPIO_PDD0, NULL); + gpio_request(GPIO_PDD0, "LAN_RESET"); gpio_direction_output(GPIO_PDD0, 0); udelay(5); gpio_set_value(GPIO_PDD0, 1); diff --git a/board/w7o/fsboot.c b/board/w7o/fsboot.c index 25fbb55..8f4fe31 100644 --- a/board/w7o/fsboot.c +++ b/board/w7o/fsboot.c @@ -8,12 +8,11 @@ #include <common.h> #include <config.h> #include <command.h> +#include <elf.h> /* * FIXME: Add code to test image and it's header. */ -extern int valid_elf_image (unsigned long addr); - static int image_check(ulong addr) { |