diff options
Diffstat (limited to 'include')
169 files changed, 1837 insertions, 7871 deletions
diff --git a/include/ambapp.h b/include/ambapp.h deleted file mode 100644 index d79fced..0000000 --- a/include/ambapp.h +++ /dev/null @@ -1,225 +0,0 @@ -/* Interface for accessing Gaisler AMBA Plug&Play Bus. - * The AHB bus can be interfaced with a simpler bus - - * the APB bus, also freely available in GRLIB at - * www.gaisler.com. - * - * (C) Copyright 2009, 2015 - * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __AMBAPP_H__ -#define __AMBAPP_H__ - -#include <ambapp_ids.h> - -#ifndef __ASSEMBLER__ -/* Structures used to access Plug&Play information directly */ -struct ambapp_pnp_ahb { - const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */ - const unsigned int custom[3]; - const unsigned int mbar[4]; /* MASK, ADDRESS, TYPE, - * CACHABLE/PREFETCHABLE */ -}; - -struct ambapp_pnp_apb { - const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */ - const unsigned int iobar; /* MASK, ADDRESS, TYPE, - * CACHABLE/PREFETCHABLE */ -}; - -/* AMBA Plug&Play AHB Masters & Slaves information locations - * Max devices is 64 supported by HW, however often only 16 - * are used. - */ -struct ambapp_pnp_info { - struct ambapp_pnp_ahb masters[64]; - struct ambapp_pnp_ahb slaves[63]; - const unsigned int unused[4]; - const unsigned int systemid[4]; -}; - -/* Describes a AMBA PnP bus */ -struct ambapp_bus { - int buses; /* Number of buses */ - unsigned int ioareas[6]; /* PnP I/O AREAs of AHB buses */ - unsigned int freq; /* Frequency of bus0 [Hz] */ -}; - -/* Processor Local AMBA bus */ -extern struct ambapp_bus ambapp_plb; - -/* Get Bus frequency of a certain AMBA bus */ -extern unsigned int ambapp_bus_freq( - struct ambapp_bus *abus, - int ahb_bus_index - ); - -/* AMBA PnP information of a APB Device */ -typedef struct { - unsigned int vendor; - unsigned int device; - unsigned char irq; - unsigned char ver; - unsigned int address; - unsigned int mask; - int ahb_bus_index; -} ambapp_apbdev; - -/* AMBA PnP information of a AHB Device */ -typedef struct { - unsigned int vendor; - unsigned int device; - unsigned char irq; - unsigned char ver; - unsigned int userdef[3]; - unsigned int address[4]; - unsigned int mask[4]; - int type[4]; - int ahb_bus_index; -} ambapp_ahbdev; - -/* Scan AMBA Bus for AHB Bridges */ -extern void ambapp_bus_init( - unsigned int ioarea, - unsigned int freq, - struct ambapp_bus *abus); - -/* Find APB Slave device by index using breath first search. - * - * When vendor and device are both set to zero, any device - * with a non-zero device ID will match the search. It may be - * useful when processing all devices on a AMBA bus. - */ -extern int ambapp_apb_find( - struct ambapp_bus *abus, - int vendor, - int device, - int index, - ambapp_apbdev *dev - ); - -/* Find AHB Master device by index using breath first search. - * - * When vendor and device are both set to zero, any device - * with a non-zero device ID will match the search. It may be - * useful when processing all devices on a AMBA bus. - */ -extern int ambapp_ahbmst_find( - struct ambapp_bus *abus, - int vendor, - int device, - int index, - ambapp_ahbdev *dev - ); - -/* Find AHB Slave device by index using breath first search. - * - * When vendor and device are both set to zero, any device - * with a non-zero device ID will match the search. It may be - * useful when processing all devices on a AMBA bus. - */ -extern int ambapp_ahbslv_find( - struct ambapp_bus *abus, - int vendor, - int device, - int index, - ambapp_ahbdev *dev - ); - -/* Return number of APB Slave devices of a certain ID (VENDOR:DEVICE) - * zero is returned if no devices was found. - */ -extern int ambapp_apb_count(struct ambapp_bus *abus, int vendor, int device); - -/* Return number of AHB Master devices of a certain ID (VENDOR:DEVICE) - * zero is returned if no devices was found. - */ -extern int ambapp_ahbmst_count(struct ambapp_bus *abus, int vendor, int device); - -/* Return number of AHB Slave devices of a certain ID (VENDOR:DEVICE) - * zero is returned if no devices was found. - */ -extern int ambapp_ahbslv_count(struct ambapp_bus *abus, int vendor, int device); - -#ifdef CONFIG_CMD_AMBAPP - -/* AMBA Plug&Play relocation & initialization */ -int ambapp_init_reloc(void); - -/* AMBA Plug&Play Name of Vendors and devices */ - -/* Return name of device */ -char *ambapp_device_id2str(int vendor, int id); - -/* Return name of vendor */ -char *ambapp_vendor_id2str(int vendor); - -/* Return description of a device */ -char *ambapp_device_id2desc(int vendor, int id); - -#endif - -#endif /* defined(__ASSEMBLER__) */ - -#define AMBA_DEFAULT_IOAREA 0xfff00000 -#define AMBA_CONF_AREA 0xff000 -#define AMBA_AHB_SLAVE_CONF_AREA 0x800 - -#define DEV_NONE 0 -#define DEV_AHB_MST 1 -#define DEV_AHB_SLV 2 -#define DEV_APB_SLV 3 - -#define AMBA_TYPE_APBIO 0x1 -#define AMBA_TYPE_MEM 0x2 -#define AMBA_TYPE_AHBIO 0x3 - -/* ID layout for APB and AHB devices */ -#define AMBA_PNP_ID(vendor, device) (((vendor)<<24) | ((device)<<12)) - -/* APB Slave PnP layout definitions */ -#define AMBA_APB_ID_OFS (0*4) -#define AMBA_APB_IOBAR_OFS (1*4) -#define AMBA_APB_CONF_LENGH (2*4) - -/* AHB Master/Slave layout PnP definitions */ -#define AMBA_AHB_ID_OFS (0*4) -#define AMBA_AHB_CUSTOM0_OFS (1*4) -#define AMBA_AHB_CUSTOM1_OFS (2*4) -#define AMBA_AHB_CUSTOM2_OFS (3*4) -#define AMBA_AHB_MBAR0_OFS (4*4) -#define AMBA_AHB_MBAR1_OFS (5*4) -#define AMBA_AHB_MBAR2_OFS (6*4) -#define AMBA_AHB_MBAR3_OFS (7*4) -#define AMBA_AHB_CONF_LENGH (8*4) - -/* Macros for extracting information from AMBA PnP information - * registers. - */ - -#define amba_vendor(x) (((x) >> 24) & 0xff) - -#define amba_device(x) (((x) >> 12) & 0xfff) - -#define amba_irq(conf) ((conf) & 0x1f) - -#define amba_ver(conf) (((conf)>>5) & 0x1f) - -#define amba_iobar_start(base, iobar) \ - ((base) | ((((iobar) & 0xfff00000)>>12) & (((iobar) & 0xfff0)<<4))) - -#define amba_membar_start(mbar) \ - (((mbar) & 0xfff00000) & (((mbar) & 0xfff0) << 16)) - -#define amba_membar_type(mbar) ((mbar) & 0xf) - -#define amba_membar_mask(mbar) (((mbar) >> 4) & 0xfff) - -#define amba_ahbio_adr(addr, base_ioarea) \ - ((unsigned int)(base_ioarea) | ((addr) >> 12)) - -#define amba_apb_mask(iobar) ((~(amba_membar_mask(iobar)<<8) & 0x000fffff) + 1) - -#endif diff --git a/include/ambapp_ids.h b/include/ambapp_ids.h deleted file mode 100644 index 1eae34e..0000000 --- a/include/ambapp_ids.h +++ /dev/null @@ -1,250 +0,0 @@ -/* AMBA Plug & Play Bus Vendor and Device IDs. - * - * (C) Copyright 2010, 2015 - * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __AMBAPP_IDS_H__ -#define __AMBAPP_IDS_H__ - -/* Vendor ID defines */ -#define VENDOR_GAISLER 0x01 -#define VENDOR_PENDER 0x02 -#define VENDOR_ESA 0x04 -#define VENDOR_ASTRIUM 0x06 -#define VENDOR_OPENCHIP 0x07 -#define VENDOR_OPENCORES 0x08 -#define VENDOR_CONTRIB 0x09 -#define VENDOR_EONIC 0x0b -#define VENDOR_RADIONOR 0x0f -#define VENDOR_GLEICHMANN 0x10 -#define VENDOR_MENTA 0x11 -#define VENDOR_SUN 0x13 -#define VENDOR_MOVIDIA 0x14 -#define VENDOR_ORBITA 0x17 -#define VENDOR_SYNOPSYS 0x21 -#define VENDOR_NASA 0x22 -#define VENDOR_S3 0x31 -#define VENDOR_CAL 0xca -#define VENDOR_EMBEDDIT 0xea -#define VENDOR_CETON 0xcb -#define VENDOR_ACTEL 0xac -#define VENDOR_APPLECORE 0xae - -/* Aeroflex Gaisler device ID defines */ -#define GAISLER_LEON2DSU 0x002 -#define GAISLER_LEON3 0x003 -#define GAISLER_LEON3DSU 0x004 -#define GAISLER_ETHAHB 0x005 -#define GAISLER_APBMST 0x006 -#define GAISLER_AHBUART 0x007 -#define GAISLER_SRCTRL 0x008 -#define GAISLER_SDCTRL 0x009 -#define GAISLER_SSRCTRL 0x00a -#define GAISLER_APBUART 0x00c -#define GAISLER_IRQMP 0x00d -#define GAISLER_AHBRAM 0x00e -#define GAISLER_AHBDPRAM 0x00f -#define GAISLER_GPTIMER 0x011 -#define GAISLER_PCITRG 0x012 -#define GAISLER_PCISBRG 0x013 -#define GAISLER_PCIFBRG 0x014 -#define GAISLER_PCITRACE 0x015 -#define GAISLER_DMACTRL 0x016 -#define GAISLER_AHBTRACE 0x017 -#define GAISLER_DSUCTRL 0x018 -#define GAISLER_CANAHB 0x019 -#define GAISLER_GPIO 0x01a -#define GAISLER_AHBROM 0x01b -#define GAISLER_AHBJTAG 0x01c -#define GAISLER_ETHMAC 0x01d -#define GAISLER_SWNODE 0x01e -#define GAISLER_SPW 0x01f -#define GAISLER_AHB2AHB 0x020 -#define GAISLER_USBDC 0x021 -#define GAISLER_USB_DCL 0x022 -#define GAISLER_DDRMP 0x023 -#define GAISLER_ATACTRL 0x024 -#define GAISLER_DDRSP 0x025 -#define GAISLER_EHCI 0x026 -#define GAISLER_UHCI 0x027 -#define GAISLER_I2CMST 0x028 -#define GAISLER_SPW2 0x029 -#define GAISLER_AHBDMA 0x02a -#define GAISLER_NUHOSP3 0x02b -#define GAISLER_CLKGATE 0x02c -#define GAISLER_SPICTRL 0x02d -#define GAISLER_DDR2SP 0x02e -#define GAISLER_SLINK 0x02f -#define GAISLER_GRTM 0x030 -#define GAISLER_GRTC 0x031 -#define GAISLER_GRPW 0x032 -#define GAISLER_GRCTM 0x033 -#define GAISLER_GRHCAN 0x034 -#define GAISLER_GRFIFO 0x035 -#define GAISLER_GRADCDAC 0x036 -#define GAISLER_GRPULSE 0x037 -#define GAISLER_GRTIMER 0x038 -#define GAISLER_AHB2PP 0x039 -#define GAISLER_GRVERSION 0x03a -#define GAISLER_APB2PW 0x03b -#define GAISLER_PW2APB 0x03c -#define GAISLER_GRCAN 0x03d -#define GAISLER_I2CSLV 0x03e -#define GAISLER_U16550 0x03f -#define GAISLER_AHBMST_EM 0x040 -#define GAISLER_AHBSLV_EM 0x041 -#define GAISLER_GRTESTMOD 0x042 -#define GAISLER_ASCS 0x043 -#define GAISLER_IPMVBCTRL 0x044 -#define GAISLER_SPIMCTRL 0x045 -#define GAISLER_L4STAT 0x047 -#define GAISLER_LEON4 0x048 -#define GAISLER_LEON4DSU 0x049 -#define GAISLER_PWM 0x04a -#define GAISLER_L2CACHE 0x04b -#define GAISLER_SDCTRL64 0x04c -#define GAISLER_GR1553B 0x04d -#define GAISLER_1553TST 0x04e -#define GAISLER_GRIOMMU 0x04f -#define GAISLER_FTAHBRAM 0x050 -#define GAISLER_FTSRCTRL 0x051 -#define GAISLER_AHBSTAT 0x052 -#define GAISLER_LEON3FT 0x053 -#define GAISLER_FTMCTRL 0x054 -#define GAISLER_FTSDCTRL 0x055 -#define GAISLER_FTSRCTRL8 0x056 -#define GAISLER_MEMSCRUB 0x057 -#define GAISLER_FTSDCTRL64 0x058 -#define GAISLER_APBPS2 0x060 -#define GAISLER_VGACTRL 0x061 -#define GAISLER_LOGAN 0x062 -#define GAISLER_SVGACTRL 0x063 -#define GAISLER_T1AHB 0x064 -#define GAISLER_MP7WRAP 0x065 -#define GAISLER_GRSYSMON 0x066 -#define GAISLER_GRACECTRL 0x067 -#define GAISLER_ATAHBSLV 0x068 -#define GAISLER_ATAHBMST 0x069 -#define GAISLER_ATAPBSLV 0x06a -#define GAISLER_B1553BC 0x070 -#define GAISLER_B1553RT 0x071 -#define GAISLER_B1553BRM 0x072 -#define GAISLER_AES 0x073 -#define GAISLER_ECC 0x074 -#define GAISLER_PCIF 0x075 -#define GAISLER_CLKMOD 0x076 -#define GAISLER_HAPSTRAK 0x077 -#define GAISLER_TEST_1X2 0x078 -#define GAISLER_WILD2AHB 0x079 -#define GAISLER_BIO1 0x07a -#define GAISLER_AESDMA 0x07b -#define GAISLER_SATCAN 0x080 -#define GAISLER_CANMUX 0x081 -#define GAISLER_GRTMRX 0x082 -#define GAISLER_GRTCTX 0x083 -#define GAISLER_GRTMDESC 0x084 -#define GAISLER_GRTMVC 0x085 -#define GAISLER_GEFFE 0x086 -#define GAISLER_GPREG 0x087 -#define GAISLER_GRTMPAHB 0x088 -#define GAISLER_SPWCUC 0x089 -#define GAISLER_SPW2_DMA 0x08a -#define GAISLER_SPWROUTER 0x08b - -/* European Space Agency device ID defines */ -#define ESA_LEON2 0x002 -#define ESA_LEON2APB 0x003 -#define ESA_IRQ 0x005 -#define ESA_TIMER 0x006 -#define ESA_UART 0x007 -#define ESA_CFG 0x008 -#define ESA_IO 0x009 -#define ESA_MCTRL 0x00f -#define ESA_PCIARB 0x010 -#define ESA_HURRICANE 0x011 -#define ESA_SPW_RMAP 0x012 -#define ESA_AHBUART 0x013 -#define ESA_SPWA 0x014 -#define ESA_BOSCHCAN 0x015 -#define ESA_IRQ2 0x016 -#define ESA_AHBSTAT 0x017 -#define ESA_WPROT 0x018 -#define ESA_WPROT2 0x019 -#define ESA_PDEC3AMBA 0x020 -#define ESA_PTME3AMBA 0x021 - -/* OpenChip device ID defines */ -#define OPENCHIP_APBGPIO 0x001 -#define OPENCHIP_APBI2C 0x002 -#define OPENCHIP_APBSPI 0x003 -#define OPENCHIP_APBCHARLCD 0x004 -#define OPENCHIP_APBPWM 0x005 -#define OPENCHIP_APBPS2 0x006 -#define OPENCHIP_APBMMCSD 0x007 -#define OPENCHIP_APBNAND 0x008 -#define OPENCHIP_APBLPC 0x009 -#define OPENCHIP_APBCF 0x00a -#define OPENCHIP_APBSYSACE 0x00b -#define OPENCHIP_APB1WIRE 0x00c -#define OPENCHIP_APBJTAG 0x00d -#define OPENCHIP_APBSUI 0x00e - -/* Various contributions device ID defines */ -#define CONTRIB_CORE1 0x001 -#define CONTRIB_CORE2 0x002 - -/* Gleichmann Electronics device ID defines */ -#define GLEICHMANN_CUSTOM 0x001 -#define GLEICHMANN_GEOLCD01 0x002 -#define GLEICHMANN_DAC 0x003 -#define GLEICHMANN_HPI 0x004 -#define GLEICHMANN_SPI 0x005 -#define GLEICHMANN_HIFC 0x006 -#define GLEICHMANN_ADCDAC 0x007 -#define GLEICHMANN_SPIOC 0x008 -#define GLEICHMANN_AC97 0x009 - -/* Sun Microsystems device ID defines */ -#define SUN_T1 0x001 -#define SUN_S1 0x011 - -/* Orbita device ID defines */ -#define ORBITA_1553B 0x001 -#define ORBITA_429 0x002 -#define ORBITA_SPI 0x003 -#define ORBITA_I2C 0x004 -#define ORBITA_SMARTCARD 0x064 -#define ORBITA_SDCARD 0x065 -#define ORBITA_UART16550 0x066 -#define ORBITA_CRYPTO 0x067 -#define ORBITA_SYSIF 0x068 -#define ORBITA_PIO 0x069 -#define ORBITA_RTC 0x0c8 -#define ORBITA_COLORLCD 0x12c -#define ORBITA_PCI 0x190 -#define ORBITA_DSP 0x1f4 -#define ORBITA_USBHOST 0x258 -#define ORBITA_USBDEV 0x2bc - -/* NASA device ID defines */ -#define NASA_EP32 0x001 - -/* CAL device ID defines */ -#define CAL_DDRCTRL 0x188 - -/* Actel Corporation device ID defines */ -#define ACTEL_COREMP7 0x001 - -/* AppleCore device ID defines */ -#define APPLECORE_UTLEON3 0x001 -#define APPLECORE_UTLEON3DSU 0x002 - -/* Opencores device id's */ -#define OPENCORES_PCIBR 0x4 -#define OPENCORES_ETHMAC 0x5 - -#endif diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 5b356dd..1a77c98 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -110,6 +110,12 @@ typedef struct global_data { } gd_t; #endif +#ifdef CONFIG_BOARD_TYPES +#define gd_board_type() gd->board_type +#else +#define gd_board_type() 0 +#endif + /* * Global Data Flags - the top 16 bits are reserved for arch-specific flags */ diff --git a/include/common.h b/include/common.h index fbbc2cb..83e4037 100644 --- a/include/common.h +++ b/include/common.h @@ -76,9 +76,6 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_4xx #include <asm/ppc4xx.h> #endif -#ifdef CONFIG_BLACKFIN -#include <asm/blackfin.h> -#endif #ifdef CONFIG_SOC_DA8XX #include <asm/arch/hardware.h> #endif @@ -206,14 +203,28 @@ typedef void (interrupt_handler_t)(void *); */ int dram_init(void); +/** + * dram_init_banksize() - Set up DRAM bank sizes + * + * This can be implemented by boards to set up the DRAM bank information in + * gd->bd->bi_dram(). It is called just before relocation, after dram_init() + * is called. + * + * If this is not provided, a default implementation will try to set up a + * single bank. It will do this if CONFIG_NR_DRAM_BANKS and + * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of + * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to + * get_effective_memsize(). + * + * @return 0 if OK, -ve on error + */ +int dram_init_banksize(void); + void hang (void) __attribute__ ((noreturn)); int timer_init(void); int cpu_init(void); -/* */ -phys_size_t initdram (int); - #include <display_options.h> /* common/main.c */ @@ -288,6 +299,22 @@ int print_cpuinfo(void); int update_flash_size(int flash_size); int arch_early_init_r(void); +/* + * setup_board_extra() - Fill in extra details in the bd_t structure + * + * @return 0 if OK, -ve on error + */ +int setup_board_extra(void); + +/** + * arch_fsp_init() - perform firmware support package init + * + * Where U-Boot relies on binary blobs to handle part of the system init, this + * function can be used to set up the blobs. This is used on some Intel + * platforms. + */ +int arch_fsp_init(void); + /** * arch_cpu_init_dm() - init CPU after driver model is available * @@ -497,6 +524,7 @@ extern ssize_t spi_write (uchar *, int, uchar *, int); /* $(BOARD)/$(BOARD).c */ int board_early_init_f (void); +int board_fix_fdt (void *rw_fdt_blob); /* manipulate the U-Boot fdt before its relocation */ int board_late_init (void); int board_postclk_init (void); /* after clocks/timebase, before env/serial */ int board_early_init_r (void); @@ -630,12 +658,7 @@ int serial_stub_tstc(struct stdio_dev *sdev); /* $(CPU)/speed.c */ int get_clocks (void); -int get_clocks_866 (void); -int sdram_adjust_866 (void); -int adjust_sdram_tbs_8xx (void); -#if defined(CONFIG_MPC8260) -int prt_8260_clks (void); -#elif defined(CONFIG_MPC5xxx) +#if defined(CONFIG_MPC5xxx) int prt_mpc5xxx_clks (void); #endif #ifdef CONFIG_4xx @@ -706,11 +729,6 @@ ulong cpu_init_f(void); #endif int cpu_init_r (void); -#if defined(CONFIG_MPC8260) -int prt_8260_rsr (void); -#elif defined(CONFIG_MPC83xx) -int prt_83xx_rsr (void); -#endif /* $(CPU)/interrupts.c */ int interrupt_init (void); @@ -776,7 +794,6 @@ void wait_ticks (unsigned long); /* arch/$(ARCH)/lib/time.c */ ulong usec2ticks (unsigned long usec); ulong ticks2usec (unsigned long ticks); -int init_timebase (void); /* lib/gunzip.c */ int gunzip(void *, int, unsigned char *, unsigned long *); diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index 53a45b2..30dd9e5 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -230,7 +230,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_CMDLINE_EDITING -#define CONFIG_STACKSIZE (128 * 1024) /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 2712687..fc8a08f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -17,7 +17,6 @@ #define __CONFIG_AM335X_EVM_H #include <configs/ti_am335x_common.h> -#include <environment/ti/dfu.h> #ifndef CONFIG_SPL_BUILD # define CONFIG_TIMESTAMP @@ -96,6 +95,9 @@ #include <config_distro_bootcmd.h> #ifndef CONFIG_SPL_BUILD +#include <environment/ti/dfu.h> +#include <environment/ti/mmc.h> + #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ @@ -138,8 +140,14 @@ "setenv fdtfile am335x-bone.dtb; fi; " \ "if test $board_name = A335BNLT; then " \ "setenv fdtfile am335x-boneblack.dtb; fi; " \ + "if test $board_name = BBBW; then " \ + "setenv fdtfile am335x-boneblack-wireless.dtb; fi; " \ "if test $board_name = BBG1; then " \ "setenv fdtfile am335x-bonegreen.dtb; fi; " \ + "if test $board_name = BBGW; then " \ + "setenv fdtfile am335x-bonegreen-wireless.dtb; fi; " \ + "if test $board_name = BBBL; then " \ + "setenv fdtfile am335x-boneblue.dtb; fi; " \ "if test $board_name = A33515BB; then " \ "setenv fdtfile am335x-evm.dtb; fi; " \ "if test $board_name = A335X_SK; then " \ diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h index 2b61405..7ee8ea7 100644 --- a/include/configs/am335x_igep0033.h +++ b/include/configs/am335x_igep0033.h @@ -117,9 +117,6 @@ "1m(uboot),256k(environment),"\ "-(filesystem)" -/* Unsupported features */ -#undef CONFIG_USE_IRQ - /* SPL */ #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds" diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 1d622ef..1feb946 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -13,14 +13,13 @@ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ -#include <environment/ti/dfu.h> #include <asm/arch/omap.h> /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_CLK 48000000 -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) +#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) +#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #endif /* I2C Configuration */ @@ -111,9 +110,6 @@ * DM support in SPL */ #ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_MMC -#undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH #undef CONFIG_TIMER #endif @@ -165,6 +161,9 @@ #define CONFIG_TI_EDMA3 #ifndef CONFIG_SPL_BUILD +#include <environment/ti/dfu.h> +#include <environment/ti/mmc.h> + #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index d545e1b..dc7a370 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -102,10 +102,6 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) -/* EEPROM */ -#define CONFIG_EEPROM_CHIP_ADDRESS 0x50 -#define CONFIG_EEPROM_BUS_ADDRESS 0 - /* * Default to using SPI for environment, etc. * 0x000000 - 0x040000 : QSPI.SPL (256KiB) @@ -120,11 +116,6 @@ #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH -#endif - /* SPI SPL */ #define CONFIG_TI_EDMA3 #define CONFIG_SPL_SPI_LOAD diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h new file mode 100644 index 0000000..84652de --- /dev/null +++ b/include/configs/apalis-tk1.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2017 Toradex, Inc. + * + * Configuration settings for the Toradex Apalis TK1 modules. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/sizes.h> + +/* enable PMIC */ +#define CONFIG_AS3722_POWER + +#include "tegra124-common.h" + +#define CONFIG_ARCH_MISC_INIT + +/* High-level configuration options */ +#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA + +/* SD/MMC support */ +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ + CONFIG_TDX_CFG_BLOCK_OFFSET) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 1 + +/* USB host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA + +/* PCI host support */ +#undef CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI + +/* PCI networking support */ +#define CONFIG_E1000_NO_NVM + +/* General networking support */ +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 16352 +#define CONFIG_TFTP_TSIZE + +/* Miscellaneous commands */ +#define CONFIG_FAT_WRITE + +#undef CONFIG_IPADDR +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#undef CONFIG_SERVERIP +#define CONFIG_SERVERIP 192.168.10.1 + +#define CONFIG_BOOTCOMMAND \ + "run emmcboot; setenv fdtfile ${soc}-apalis-${fdt_board}.dtb && " \ + "run distro_bootcmd" + +#define DFU_ALT_EMMC_INFO "apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \ + "boot part 0 1 mmcpart 0; " \ + "rootfs part 0 2 mmcpart 0; " \ + "uImage fat 0 1 mmcpart 0; " \ + "tegra124-apalis-eval.dtb fat 0 1 mmcpart 0" + +#define EMMC_BOOTCMD \ + "emmcargs=ip=off root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait\0" \ + "emmcboot=run setup; setenv bootargs ${defargs} ${emmcargs} " \ + "${setupargs} ${vidargs}; echo Booting from internal eMMC " \ + "chip...; run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \ + "${boot_file} && run fdt_fixup && " \ + "bootm ${kernel_addr_r} - ${dtbparam}\0" \ + "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \ + "${soc}-apalis-${fdt_board}.dtb && " \ + "setenv dtbparam ${fdt_addr_r}\0" + +#define NFS_BOOTCMD \ + "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ + "nfsboot=pci enum; run setup; setenv bootargs ${defargs} ${nfsargs} " \ + "${setupargs} ${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ + "run nfsdtbload; dhcp ${kernel_addr_r} " \ + "&& run fdt_fixup && bootm ${kernel_addr_r} - ${dtbparam}\0" \ + "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} " \ + "${soc}-apalis-${fdt_board}.dtb " \ + "&& setenv dtbparam ${fdt_addr_r}\0" + +#define SD_BOOTCMD \ + "sdargs=ip=off root=/dev/mmcblk1p2 rw rootfstype=ext3 rootwait\0" \ + "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${setupargs} " \ + "${vidargs}; echo Booting from SD card in 8bit slot...; " \ + "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \ + "${boot_file} && run fdt_fixup && " \ + "bootm ${kernel_addr_r} - ${dtbparam}\0" \ + "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \ + "${soc}-apalis-${fdt_board}.dtb " \ + "&& setenv dtbparam ${fdt_addr_r}\0" + +#define USB_BOOTCMD \ + "usbargs=ip=off root=/dev/sda2 rw rootfstype=ext3 rootwait\0" \ + "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \ + "${usbargs} ${vidargs}; echo Booting from USB stick...; " \ + "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \ + "${boot_file} && run fdt_fixup && " \ + "bootm ${kernel_addr_r} - ${dtbparam}\0" \ + "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \ + "${soc}-apalis-${fdt_board}.dtb " \ + "&& setenv dtbparam ${fdt_addr_r}\0" + +#define BOARD_EXTRA_ENV_SETTINGS \ + "boot_file=uImage\0" \ + "console=ttyS0\0" \ + "defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \ + "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0\0" \ + "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ + EMMC_BOOTCMD \ + "fdt_board=eval\0" \ + "fdt_fixup=;\0" \ + NFS_BOOTCMD \ + SD_BOOTCMD \ + "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ + "00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \ + "flash_eth.img && source ${loadaddr}\0" \ + "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \ + "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \ + "|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1 " \ + "${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "setup=setenv setupargs igb_mac=${ethaddr} " \ + "consoleblank=0 no_console_suspend=1 console=tty1 " \ + "console=${console},${baudrate}n8 debug_uartport=lsport,0 " \ + "${memargs}\0" \ + "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ + "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ + "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + USB_BOOTCMD \ + "vidargs=video=tegrafb0:640x480-16@60 fbcon=map:1\0" + +/* Increase console I/O buffer size */ +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 + +/* Increase arguments buffer size */ +#undef CONFIG_SYS_BARGSIZE +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Increase print buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Increase maximum number of arguments */ +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 32 + +#define CONFIG_CMD_TIME + +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SYS_BOOT_RAMDISK_HIGH + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +/* Reserve top 1M for secure RAM */ +#define CONFIG_ARMV7_SECURE_BASE 0xfff00000 +#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index 030f01c..5c27055 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -148,8 +148,6 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 -#define CONFIG_STACKSIZE (128 * 1024) - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 708f032..4c27225 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -52,8 +52,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_STACKSIZE (2048) - #define CONFIG_BOOTARGS \ "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2" #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index aa30848..64d7c45 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -71,8 +71,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_STACKSIZE (2048) - #define CONFIG_BOOTARGS \ "root=mtd:main rootfstype=jffs2" #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 771a35a..3c03ed3 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -69,8 +69,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_STACKSIZE (2048) - #define CONFIG_BOOTARGS \ "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1" diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index d60db65..768e8fb 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -11,8 +11,6 @@ /* * CPU configuration */ -#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ - #define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 #define ARC_APB_PERIPHERAL_BASE 0xF0000000 #define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000) diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h index 65e9e32..77d6e6a 100644 --- a/include/configs/bcm23550_w1d.h +++ b/include/configs/bcm23550_w1d.h @@ -25,7 +25,6 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */ -#define CONFIG_STACKSIZE SZ_256K /* GPIO Driver */ #define CONFIG_KONA_GPIO diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h index 2d9b0a8..03f4ca0 100644 --- a/include/configs/bcm28155_ap.h +++ b/include/configs/bcm28155_ap.h @@ -24,7 +24,6 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */ -#define CONFIG_STACKSIZE SZ_256K /* GPIO Driver */ #define CONFIG_KONA_GPIO diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h index 868b0a8..c187df2 100644 --- a/include/configs/bcm_ep_board.h +++ b/include/configs/bcm_ep_board.h @@ -28,7 +28,6 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) -#define CONFIG_STACKSIZE (256 * 1024) /* Some commands use this as the default load address */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE diff --git a/include/configs/bcm_northstar2.h b/include/configs/bcm_northstar2.h new file mode 100644 index 0000000..ec2ce3f --- /dev/null +++ b/include/configs/bcm_northstar2.h @@ -0,0 +1,55 @@ +/* + * Configuration for Broadcom NS2. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BCM_NORTHSTAR2_H +#define __BCM_NORTHSTAR2_H + +#include <linux/sizes.h> + +#define CONFIG_HOSTNAME northstar2 + +/* Physical Memory Map */ +#define V2M_BASE 0x80000000 +#define PHYS_SDRAM_1 V2M_BASE + +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1_SIZE (4UL * SZ_1G) +#define PHYS_SDRAM_2_SIZE (4UL * SZ_1G) +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* define text_base for U-boot image */ +#define CONFIG_SYS_TEXT_BASE 0x85000000 +#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x7ff00) +#define CONFIG_SYS_LOAD_ADDR 0x90000000 +#define CONFIG_SYS_MALLOC_LEN SZ_16M + +/* Serial Configuration */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 25000000 +#define CONFIG_SYS_NS16550_COM1 0x66100000 +#define CONFIG_SYS_NS16550_COM2 0x66110000 +#define CONFIG_SYS_NS16550_COM3 0x66120000 +#define CONFIG_SYS_NS16550_COM4 0x66130000 +#define CONFIG_CONS_INDEX 4 +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_NOWHERE + +/* console configuration */ +#define CONFIG_SYS_CBSIZE SZ_1K +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* version string, parser, etc */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_COMMAND_HISTORY +#define CONFIG_SYS_LONGHELP + +#endif /* __BCM_NORTHSTAR2_H */ diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h deleted file mode 100644 index b965803..0000000 --- a/include/configs/bct-brettl2.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * U-Boot - Configuration file for BF536 brettl2 board - */ - -#ifndef __CONFIG_BCT_BRETTL2_H__ -#define __CONFIG_BCT_BRETTL2_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf536-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 16384000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 24 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 3 -#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -/* - * SDRAM Settings - */ -#define CONFIG_EBIU_SDRRC_VAL 0x07f6 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC 1 -#define CONFIG_NETCONSOLE 1 -#define CONFIG_HOSTNAME brettl2 -#define CONFIG_IPADDR 192.168.233.224 -#define CONFIG_GATEWAYIP 192.168.233.1 -#define CONFIG_SERVERIP 192.168.233.53 -#define CONFIG_ROOTPATH "/romfs/brettl2" -#endif - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x12000 - -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#else -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif - -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Misc Settings - */ -#define CONFIG_LOADADDR 0x800000 -#define CONFIG_MISC_INIT_R -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -/* disable unnecessary features */ -#undef CONFIG_BOOTM_RTEMS -#undef CONFIG_BZIP2 -#undef CONFIG_KALLSYMS - -#endif diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h deleted file mode 100644 index b517af3..0000000 --- a/include/configs/bf506f-ezkit.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * U-Boot - Configuration file for BF506F EZ-Kit board - */ - -#ifndef __CONFIG_BF506F_EZKIT_H__ -#define __CONFIG_BF506F_EZKIT_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf506-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 16 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_SIZE 0 - -#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 -#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2 - -#define CONFIG_SYS_MONITOR_BASE (L1_DATA_A_SRAM_END) -#define CONFIG_SYS_MONITOR_LEN (4 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024) - -/* - * Flash Settings - */ -/* -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 -#define CONFIG_MONITOR_IS_IN_RAM -*/ - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x400 - -/* - * Misc Settings - */ -#define CONFIG_ICACHE_OFF -#define CONFIG_DCACHE_OFF -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BFIN_SERIAL - -#undef CONFIG_GZIP -#undef CONFIG_ZLIB -#undef CONFIG_BOOTM_RTEMS -#undef CONFIG_BOOTM_LINUX - -#endif diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h deleted file mode 100644 index e3c2286..0000000 --- a/include/configs/bf518f-ezbrd.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * U-Boot - Configuration file for BF518F EZBrd board - */ - -#ifndef __CONFIG_BF518F_EZBRD_H__ -#define __CONFIG_BF518F_EZBRD_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf518-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 16 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -/* This board has a 64meg MT48H32M16 */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x0096 -#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) - -#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) - -/* - * Network Settings - */ -#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__) -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_BFIN_MAC_PINS \ - { \ - P_MII0_ETxD0, \ - P_MII0_ETxD1, \ - P_MII0_ETxD2, \ - P_MII0_ETxD3, \ - P_MII0_ETxEN, \ - P_MII0_TxCLK, \ - P_MII0_PHYINT, \ - P_MII0_COL, \ - P_MII0_ERxD0, \ - P_MII0_ERxD1, \ - P_MII0_ERxD2, \ - P_MII0_ERxD3, \ - P_MII0_ERxDV, \ - P_MII0_ERxCLK, \ - P_MII0_CRS, \ - P_MII0_MDC, \ - P_MII0_MDIO, \ - 0 } -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME bf518f-ezbrd -#define CONFIG_PHY_ADDR 3 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#endif -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * SDH Settings - */ -#if !defined(__ADSPBF512__) -#define CONFIG_BFIN_SDH -#endif - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h deleted file mode 100644 index 1c1a08f..0000000 --- a/include/configs/bf525-ucr2.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * U-Boot - Configuration file for bf525-ucr2 board - * The board includes ADSP-BF525 rev. 0.2, - * 32-bit SDRAM (SAMSUNG K4S561632H-UC75), - * USB 2.0 High Speed OTG USB WIFI, - * SPI flash (cFeon EN25Q128 16 MB), - * Support PPI and ITU-R656, - * See http://www.ucrobotics.com/?q=cn/ucr2 - */ - -#ifndef __CONFIG_BF525_UCR2_H__ -#define __CONFIG_BF525_UCR2_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf525-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 24000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -/* - * SDRAM reference page - * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram - */ -#define CONFIG_EBIU_SDRRC_VAL 0x3f8 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (320 * 1024) -#define CONFIG_SYS_MALLOC_LEN (320 * 1024) - -/* support for serial flash */ -#define CONFIG_BFIN_SPI -#define CONFIG_SF_DEFAULT_HZ 30000000 - -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 - -#define CONFIG_BFIN_SERIAL -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" -#define CONFIG_BOOTCOMMAND "run sfboot" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "sfboot=sf probe 1;" \ - "sf read 0x1000000 0x20000 0x300000;" \ - "bootm 0x1000000\0" - -#endif diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h deleted file mode 100644 index 7d75e73..0000000 --- a/include/configs/bf526-ezbrd.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * U-Boot - Configuration file for BF526 EZBrd board - */ - -#ifndef __CONFIG_BF526_EZBRD_H__ -#define __CONFIG_BF526_EZBRD_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf526-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 16 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -/* This board has a 64meg MT48H32M16 */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x0267 -#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_2 | PASR_ALL | TRAS_6 | TRP_4 | TRCD_2 | TWR_2 | PSS) - -#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - -/* - * NAND Settings - * (can't be used same time as ethernet) - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -# define CONFIG_BFIN_NFC -# define CONFIG_BFIN_NFC_BOOTROM_ECC -#endif -#ifdef CONFIG_BFIN_NFC -#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 -#define CONFIG_DRIVER_NAND_BFIN -#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND -#endif - -/* - * Network Settings - */ -#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \ - !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC) -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_RMII -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME bf526-ezbrd - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#endif -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * USB Settings - */ -#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) -#define CONFIG_USB_MUSB_HCD -#define CONFIG_USB_BLACKFIN -#define CONFIG_USB_MUSB_TIMEOUT 100000 -#endif - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 1 - -/* define to enable run status via led */ - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h deleted file mode 100644 index e433aaa..0000000 --- a/include/configs/bf527-ad7160-eval.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * U-Boot - Configuration file for BF527 AD7160-EVAL board - */ - -#ifndef __CONFIG_BF527_AD7160_EVAL_H__ -#define __CONFIG_BF527_AD7160_EVAL_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf527-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 24000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 25 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x03F6 -#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) - -#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (640 * 1024) - -/* - * NAND Settings - * (can't be used same time as ethernet) - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -# define CONFIG_BFIN_NFC -# define CONFIG_BFIN_NFC_BOOTROM_ECC -#endif -#ifdef CONFIG_BFIN_NFC -#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 -#define CONFIG_DRIVER_NAND_BFIN -#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 259 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SIZE 0x20000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * SPI_MMC Settings - */ -#define CONFIG_MMC_SPI - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_UART_CONSOLE 0 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h deleted file mode 100644 index d945b8d..0000000 --- a/include/configs/bf527-ezkit.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * U-Boot - Configuration file for BF537 STAMP board - */ - -#ifndef __CONFIG_BF527_EZKIT_H__ -#define __CONFIG_BF527_EZKIT_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf527-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 21 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x03F6 -#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) - -#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (640 * 1024) - -/* - * NAND Settings - * (can't be used same time as ethernet) - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -# define CONFIG_BFIN_NFC -# define CONFIG_BFIN_NFC_BOOTROM_ECC -#endif -#ifdef CONFIG_BFIN_NFC -#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 -#define CONFIG_DRIVER_NAND_BFIN -#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif - -/* - * Network Settings - */ -#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \ - !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC) -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_RMII -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME bf527-ezkit - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 259 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SIZE 0x20000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * USB Settings - */ -#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) -#define CONFIG_USB_MUSB_HCD -#define CONFIG_USB_BLACKFIN -#define CONFIG_USB_MUSB_TIMEOUT 100000 -#endif - -/* Don't waste time transferring a logo over the UART */ - -/* - * Video Settings - */ -#ifdef CONFIG_VIDEO -#ifdef CONFIG_BF527_EZKIT_REV_2_1 -# define CONFIG_LQ035Q1_SPI_BUS 0 -# define CONFIG_LQ035Q1_SPI_CS 7 -# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI -#else -# define CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI -#endif - -#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI -# define EASYLOGO_HEADER <asm/bfin_logo_rgb565_230x230_lzma.h> -#else -# define EASYLOGO_HEADER <asm/bfin_logo_230x230_lzma.h> -#endif -#endif /* CONFIG_VIDEO */ - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 1 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h deleted file mode 100644 index 6b7d19e..0000000 --- a/include/configs/bf527-sdp.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * U-Boot - Configuration file for BF527 SDP board - */ - -#ifndef __CONFIG_BF527_SDP_H__ -#define __CONFIG_BF527_SDP_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf527-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 24000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 25 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -#define CONFIG_PLL_LOCKCNT_VAL 0x0200 -#define CONFIG_PLL_CTL_VAL 0x2a00 -#define CONFIG_VR_CTL_VAL 0x7090 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL 0x00FE -#define CONFIG_EBIU_SDGCTL_VAL 0x8011998d - -#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (640 * 1024) - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 259 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_ALL - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_UART_CONSOLE 0 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h deleted file mode 100644 index e154812..0000000 --- a/include/configs/bf533-ezkit.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * U-Boot - Configuration file for BF533 EZKIT board - */ - -#ifndef __CONFIG_BF533_EZKIT_H__ -#define __CONFIG_BF533_EZKIT_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf533-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 27000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 22 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_SIZE 32 -/* Early EZKITs had 32megs, but later have 64megs */ -#if (CONFIG_MEM_SIZE == 64) -# define CONFIG_MEM_ADD_WDTH 10 -#else -# define CONFIG_MEM_ADD_WDTH 9 -#endif - -#define CONFIG_EBIU_SDRRC_VAL 0x398 -#define CONFIG_EBIU_SDGCTL_VAL 0x91118d - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20310300 -#define SMC91111_EEPROM_INIT() \ - do { \ - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \ - bfin_write_FIO_FLAG_C(PF1); \ - bfin_write_FIO_FLAG_S(PF0); \ - SSYNC(); \ - } while (0) -#define CONFIG_HOSTNAME bf533-ezkit - -/* - * Flash Settings - */ -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 3 -#define CONFIG_SYS_MAX_FLASH_SECT 40 -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR 0x20030000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define FLASH_TOT_SECT 40 - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C_SOFT -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C -#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0 -#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1 -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h deleted file mode 100644 index 516fe2d..0000000 --- a/include/configs/bf533-stamp.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * U-Boot - Configuration file for BF533 STAMP board - */ - -#ifndef __CONFIG_BF533_STAMP_H__ -#define __CONFIG_BF533_STAMP_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf533-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 11059200 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 45 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */ - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 11 -#define CONFIG_MEM_SIZE 128 - -#define CONFIG_EBIU_SDRRC_VAL 0x268 -#define CONFIG_EBIU_SDGCTL_VAL 0x911109 - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3 -#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983 - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20300300 -#define SMC91111_EEPROM_INIT() \ - do { \ - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \ - bfin_write_FIO_FLAG_C(PF1); \ - bfin_write_FIO_FLAG_S(PF0); \ - SSYNC(); \ - } while (0) -#define CONFIG_HOSTNAME bf533-stamp - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0 -/* - * Software (bit-bang) I2C driver configuration - */ -#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3 -#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_CFI_AMD_RESET -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 67 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -/* -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_ALL -*/ - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#endif -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#else -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C_SOFT -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C -#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3 -#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0 -#endif - -/* - * Compact Flash / IDE / ATA Settings - */ - -/* Enabled below option for CF support */ -/* #define CONFIG_STAMP_CF */ -#if defined(CONFIG_STAMP_CF) -#define CONFIG_MISC_INIT_R -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1) - -#define CONFIG_SYS_ATA_BASE_ADDR 0x20200000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */ - -#define CONFIG_SYS_ATA_STRIDE 2 - -#undef CONFIG_EBIU_AMBCTL1_VAL -#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2 -#endif - -/* - * Misc Settings - */ -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 - -/* FLASH/ETHERNET uses the same async bank */ -#define SHARED_RESOURCES 1 - -/* define to enable boot progress via leds */ -/* #define CONFIG_SHOW_BOOT_PROGRESS */ - -/* define to enable run status via led */ - -/* define to enable splash screen support */ - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h deleted file mode 100644 index 5d57b80..0000000 --- a/include/configs/bf537-minotaur.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * U-Boot - Configuration file for CSP Minotaur board - * - * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch> - * Minotaur config, brushed up for official uClinux dist. - * Parallel flash support disabled, SPI flash boot command - * added ('run flashboot'). - * - * Flash image map: - * - * 0x00000000 u-boot bootstrap - * 0x00010000 environment - * 0x00020000 u-boot code - * 0x00030000 uImage.initramfs - * - */ - -#ifndef __CONFIG_BF537_MINOTAUR_H__ -#define __CONFIG_BF537_MINOTAUR_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_SIZE 32 -#define CONFIG_MEM_ADD_WDTH 9 - -#define CONFIG_EBIU_SDRRC_VAL 0x306 -#define CONFIG_EBIU_SDGCTL_VAL 0x91114d - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (128 << 10) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define CONFIG_BFIN_MAC -#define CONFIG_NETCONSOLE 1 -#endif -#ifdef CONFIG_BFIN_MAC -#define CONFIG_IPADDR 192.168.0.15 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_HOSTNAME bf537-minotaur -#endif - -#define CONFIG_SYS_AUTOLOAD "no" -#define CONFIG_ROOTPATH "/romfs" - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 - -/* - * Misc Settings - */ -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_ENV_OVERWRITE 1 - -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BFIN_SERIAL - -#define CONFIG_PANIC_HANG 1 -#define CONFIG_RTC_BFIN 1 -#define CONFIG_BOOT_RETRY_TIME -1 -#define CONFIG_LOADS_ECHO 1 - -#define CONFIG_CMD_BOOTLDR -#define CONFIG_CMD_DATE - -#define CONFIG_BOOTCOMMAND "run ramboot" -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" - -#define BOOT_ENV_SETTINGS \ - "update=tftpboot $(loadaddr) u-boot.ldr;" \ - "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \ - "sf erase 0 0x30000;" \ - "sf write $(loadaddr) 0 $(filesize)" \ - "flashboot=sf read 0x1000000 0x30000 0x320000;" \ - "bootm 0x1000000\0" -#ifdef CONFIG_BFIN_MAC -# define NETWORK_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):eth0:off\0" \ - "ramboot=tftpboot $(loadaddr) linux;" \ - "run ramargs;run addip;bootelf\0" \ - "nfsboot=tftpboot $(loadaddr) linux;" \ - "run nfsargs;run addip;bootelf\0" -#else -# define NETWORK_ENV_SETTINGS -#endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - NETWORK_ENV_SETTINGS \ - "ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \ - BOOT_ENV_SETTINGS - -#endif diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h deleted file mode 100644 index 6d80592..0000000 --- a/include/configs/bf537-pnav.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * U-Boot - Configuration file for BF537 PNAV board - */ - -#ifndef __CONFIG_BF537_PNAV_H__ -#define __CONFIG_BF537_PNAV_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 24576000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x3b7 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_RMII -#endif -#define CONFIG_HOSTNAME bf537-pnav - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#else -#define ENV_IS_EMBEDDED -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x20004000 -#define CONFIG_ENV_OFFSET 0x4000 -#endif -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * NAND Settings - */ -#define CONFIG_NAND_PLAT - -#define CONFIG_SYS_NAND_BASE 0x20100000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_WRITE(addr, cmd) \ - do { \ - bfin_write8(addr, cmd); \ - SSYNC(); \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12 - -/* - * I2C settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Misc Settings - */ -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 - -/* JFFS Partition offset set */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 -/* 512k reserved for u-boot */ -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15 - -#define CONFIG_BOOTCOMMAND "run nandboot" -#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs" - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h deleted file mode 100644 index 3b69e58..0000000 --- a/include/configs/bf537-srv1.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * U-Boot - Configuration file for CSP Minotaur board - * - * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch> - * Minotaur config, brushed up for official uClinux dist. - * Parallel flash support disabled, SPI flash boot command - * added ('run flashboot'). - * - * Flash image map: - * - * 0x00000000 u-boot bootstrap - * 0x00010000 environment - * 0x00020000 u-boot code - * 0x00030000 uImage.initramfs - * - */ - -#ifndef __CONFIG_BF537_SRV1_H__ -#define __CONFIG_BF537_SRV1_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 22118400 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_SIZE 32 -#define CONFIG_MEM_ADD_WDTH 9 - -#define CONFIG_EBIU_SDRRC_VAL 0x2ac -#define CONFIG_EBIU_SDGCTL_VAL 0x91110d - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (384 << 10) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define CONFIG_BFIN_MAC -#define CONFIG_NETCONSOLE 1 -#endif -#ifdef CONFIG_BFIN_MAC -#define CONFIG_IPADDR 192.168.0.15 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_HOSTNAME bf537-srv1 -#endif - -#define CONFIG_SYS_AUTOLOAD "no" -#define CONFIG_ROOTPATH "/romfs" - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 - -/* - * Misc Settings - */ -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_ENV_OVERWRITE 1 - -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BFIN_SERIAL - -#define CONFIG_PANIC_HANG 1 -#define CONFIG_RTC_BFIN 1 -#define CONFIG_BOOT_RETRY_TIME -1 -#define CONFIG_LOADS_ECHO 1 - -#define CONFIG_CMD_BOOTLDR -#define CONFIG_CMD_DATE - -#define CONFIG_BOOTCOMMAND "run flashboot" -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" - -#define BOOT_ENV_SETTINGS \ - "update=tftpboot $(loadaddr) u-boot.ldr;" \ - "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \ - "sf erase 0 0x30000;" \ - "sf write $(loadaddr) 0 $(filesize)" \ - "flashboot=sf read 0x1000000 0x30000 0x320000;" \ - "bootm 0x1000000\0" -#ifdef CONFIG_BFIN_MAC -# define NETWORK_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):eth0:off\0" \ - "ramboot=tftpboot $(loadaddr) linux;" \ - "run ramargs;run addip;bootelf\0" \ - "nfsboot=tftpboot $(loadaddr) linux;" \ - "run nfsargs;run addip;bootelf\0" -#else -# define NETWORK_ENV_SETTINGS -#endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - NETWORK_ENV_SETTINGS \ - "ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \ - BOOT_ENV_SETTINGS - -#endif diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h deleted file mode 100644 index 6858153..0000000 --- a/include/configs/bf537-stamp.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * U-Boot - Configuration file for BF537 STAMP board - */ - -#ifndef __CONFIG_BF537_STAMP_H__ -#define __CONFIG_BF537_STAMP_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x306 -#define CONFIG_EBIU_SDGCTL_VAL 0x91114d - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME bf537-stamp - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_ALL - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#endif -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#else -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * SPI_MMC Settings - */ -#define CONFIG_MMC_SPI - -/* - * NAND Settings - */ -/* #define CONFIG_NAND_PLAT */ -#ifdef CONFIG_NAND_PLAT -#define CONFIG_SYS_NAND_BASE 0x20212000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_WRITE(addr, cmd) \ - do { \ - bfin_write8(addr, cmd); \ - SSYNC(); \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3 -#endif /* CONFIG_NAND_PLAT */ - -/* - * CF-CARD IDE-HDD Support - */ - -/* - * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card) - * Strange address mapping Blackfin A13 connects to CF_A0 - */ - -/* #define CONFIG_BFIN_TRUE_IDE */ - -/* - * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card) - * This should be the preferred mode - */ - -/* #define CONFIG_BFIN_CF_IDE */ - -/* - * Add IDE Disk Drive (HDD) support - * See example interface here: - * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin - */ - -/* #define CONFIG_BFIN_HDD_IDE */ - -#if defined(CONFIG_BFIN_CF_IDE) || \ - defined(CONFIG_BFIN_HDD_IDE) || \ - defined(CONFIG_BFIN_TRUE_IDE) -# define CONFIG_BFIN_IDE 1 -# define CONFIG_CMD_IDE -#endif - -#if defined(CONFIG_BFIN_IDE) - -/* - * IDE/ATA stuff - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1) - -#undef CONFIG_EBIU_AMBCTL1_VAL -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3 - -#define CONFIG_CF_ATASEL_DIS 0x20311800 -#define CONFIG_CF_ATASEL_ENA 0x20311802 - -#if defined(CONFIG_BFIN_TRUE_IDE) -/* - * Note that these settings aren't for the most part used in include/ata.h - * when all of the ATA registers are setup - */ -#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */ - -#elif defined(CONFIG_BFIN_CF_IDE) -#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */ - -#elif defined(CONFIG_BFIN_HDD_IDE) -#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */ -#undef CONFIG_SCLK_DIV -#define CONFIG_SCLK_DIV 8 -#endif - -#endif - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 - -/* Define if want to do post memory test */ -#undef CONFIG_POST -#ifdef CONFIG_POST -#define CONFIG_SYS_POST_HOTKEYS_GPIO GPIO_PF5 -#define CONFIG_POST_BSPEC1_GPIO_LEDS \ - GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, -#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \ - GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2, -#define CONFIG_POST_BSPEC2_GPIO_NAMES \ - 10, 11, 12, 13, -#define CONFIG_SYS_POST_FLASH_START 11 -#define CONFIG_SYS_POST_FLASH_END 71 -#endif - -/* These are for board tests */ -#if 0 -#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100" -#endif - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h deleted file mode 100644 index a6d039c..0000000 --- a/include/configs/bf538f-ezkit.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * U-Boot - Configuration file for BF538F EZ-Kit Lite board - */ - -#ifndef __CONFIG_BF538F_EZKIT_H__ -#define __CONFIG_BF538F_EZKIT_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf538-0.4 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 21 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL (0x03F6) -#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3) - -#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | AMBEN_ALL | AMCKEN) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20310300 -#define CONFIG_HOSTNAME bf538f-ezkit - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -/* -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_ALL -*/ - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#endif -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#else -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Misc Settings - */ -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h deleted file mode 100644 index 35cbebd..0000000 --- a/include/configs/bf548-ezkit.h +++ /dev/null @@ -1,190 +0,0 @@ -/* - * U-Boot - Configuration file for BF548 STAMP board - */ - -#ifndef __CONFIG_BF548_EZKIT_H__ -#define __CONFIG_BF548_EZKIT_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf548-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 21 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE -#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222 -#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021 - -/* Default EZ-Kit bank mapping: - * Async Bank 0 - 32MB Burst Flash - * Async Bank 1 - Ethernet - * Async Bank 2 - Nothing - * Async Bank 3 - Nothing - */ -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 -#define CONFIG_EBIU_FCTL_VAL (BCLK_4) -#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH) - -#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SYS_MALLOC_LEN (768 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE 0x24000000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_HOSTNAME bf548-ezkit - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 259 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_SIZE 0x20000 -#else -/* The BF548-EZKIT uses a top boot flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_OFFSET (0x1000000 - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SECT_SIZE 0x8000 -#endif - -/* - * NAND Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 -#define CONFIG_BFIN_NFC_BOOTROM_ECC -#define CONFIG_DRIVER_NAND_BFIN -#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * SATA - */ -#if !defined(__ADSPBF544__) -#define CONFIG_LIBATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_LBA48 -#define CONFIG_PATA_BFIN -#define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800 -#define CONFIG_BFIN_ATA_MODE XFER_PIO_4 -#endif - -/* - * SDH Settings - */ -#if !defined(__ADSPBF544__) -#define CONFIG_BFIN_SDH -#endif - -/* - * USB Settings - */ -#if !defined(__ADSPBF544__) -#define CONFIG_USB_MUSB_HCD -#define CONFIG_USB_BLACKFIN -#define CONFIG_USB_MUSB_TIMEOUT 100000 -#endif - -/* - * Misc Settings - */ -#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 )) -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 1 -#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000 - -#define CONFIG_ADI_GPIO2 - -#ifdef CONFIG_VIDEO -#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h > -#define CONFIG_DEB_DMA_URGENT -#endif - -/* Define if want to do post memory test */ -#undef CONFIG_POST -#ifdef CONFIG_POST -#define CONFIG_POST_BSPEC1_GPIO_LEDS \ - GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11, -#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \ - GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11 -#define CONFIG_POST_BSPEC2_GPIO_NAMES \ - 13, 12, 11, 10, -#define CONFIG_SYS_POST_FLASH_START 10 -#define CONFIG_SYS_POST_FLASH_END 127 -#endif - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h deleted file mode 100644 index bf2d7b6..0000000 --- a/include/configs/bf561-acvilon.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * U-Boot - Configuration file for BF561 Acvilon System On Module - * For more information please go to http://www.niistt.ru/ - */ - -#ifndef __CONFIG_BF561_ACVILON_H__ -#define __CONFIG_BF561_ACVILON_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf561-0.5 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 12000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 50 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 128 - -#define CONFIG_EBIU_SDRRC_VAL 0x300 -#define CONFIG_EBIU_SDGCTL_VAL 0x00B11189 - -#define CONFIG_EBIU_AMGCTL_VAL 0x4e -#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 -#define CONFIG_EBIU_AMBCTL1_VAL 0x99b35554 - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * RTC Settings - */ -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_I2C_DTT_ADDR 0x49 -/*#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3*/ - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DTT - -#if defined(CONFIG_CMD_NET) - -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_32_BIT -/* #define CONFIG_SMC911X_16_BIT */ -#define CONFIG_SMC911X_BASE 0x28000000 - -#endif /* (CONFIG_CMD_NET) */ - -#define CONFIG_HOSTNAME bf561-acvilon - -/* - * I2C Settings - */ -#define CONFIG_HARD_I2C -/* Use 300kHz speed by default */ -#define CONFIG_SYS_I2C_SPEED 0x00 -#define CONFIG_PCA9564_I2C -#define CONFIG_PCA9564_BASE 0x2c000000 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_SF_DEFAULT_SPEED 10000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SECT_SIZE (1056 * 8) -#define CONFIG_ENV_OFFSET ((16 + 256) * 1056) -#define CONFIG_ENV_SIZE (8 * 1056) - -/* - * NAND Settings - * We're using NAND_PLAT driver to make things simplier - */ -#define CONFIG_NAND_PLAT -#define CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x24000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3)) -#define BFIN_NAND_WRITE(addr, cmd) \ - do { \ - bfin_write8(addr, cmd); \ - SSYNC(); \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10 - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif /* __CONFIG_BF561_ACVILON_H__ */ diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h deleted file mode 100644 index 2fefe98..0000000 --- a/include/configs/bf561-ezkit.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * U-Boot - Configuration file for BF561 EZKIT board - */ - -#ifndef __CONFIG_BF561_EZKIT_H__ -#define __CONFIG_BF561_EZKIT_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf561-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 30000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 6 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x306 -#define CONFIG_EBIU_SDGCTL_VAL 0x91114d - -#define CONFIG_EBIU_AMGCTL_VAL 0x3F -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x2C010300 -#define CONFIG_SMC_USE_32_BIT 1 -#define CONFIG_HOSTNAME bf561-ezkit - -/* - * Flash Settings - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_AMD_RESET -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 -/* The BF561-EZKIT uses a top boot flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET (0x800000 - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SECT_SIZE 0x2000 - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C_SOFT -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C -#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0 -#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0 -#endif - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 - -/* - * Run core 1 from L1 SRAM start address when init uboot on core 0 - */ -/* #define CONFIG_CORE1_RUN 1 */ - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h deleted file mode 100644 index 5791810..0000000 --- a/include/configs/bf609-ezkit.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * U-Boot - Configuration file for BF609 EZ-Kit board - */ - -#ifndef __CONFIG_BF609_EZKIT_H__ -#define __CONFIG_BF609_EZKIT_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf609-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* For ez-board version 1.0, else undef this */ -#define CONFIG_BFIN_BOARD_VERSION_1_0 - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SYSCLK_DIV - * SCLK0 = SCLK / SCLK0_DIV - * SCLK1 = SCLK / SCLK1_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ (25000000) -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF (0) - -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-127 (where 0 means 128) */ -#define CONFIG_VCO_MULT (20) - -/* CCLK_DIV controls the core clock divider */ -/* Values can range from 0-31 (where 0 means 32) */ -#define CONFIG_CCLK_DIV (1) -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 0-31 (where 0 means 32) */ -#define CONFIG_SCLK_DIV (4) -/* Values can range from 0-7 (where 0 means 8) */ -#define CONFIG_SCLK0_DIV (1) -#define CONFIG_SCLK1_DIV (1) -/* DCLK_DIV controls the DDR clock divider */ -/* Values can range from 0-31 (where 0 means 32) */ -#define CONFIG_DCLK_DIV (2) -/* OCLK_DIV controls the output clock divider */ -/* Values can range from 0-127 (where 0 means 128) */ -#define CONFIG_OCLK_DIV (16) - -/* - * Memory Settings - */ -#define CONFIG_MEM_SIZE 128 - -#define CONFIG_SMC_GCTL_VAL 0x00000010 -#define CONFIG_SMC_B0CTL_VAL 0x01007011 -#define CONFIG_SMC_B0TIM_VAL 0x08170977 -#define CONFIG_SMC_B0ETIM_VAL 0x00092231 - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - -#define CONFIG_HW_WATCHDOG -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK -#define CONFIG_NETCONSOLE -#define CONFIG_HOSTNAME "bf609-ezkit" -#define CONFIG_PHY_ADDR 1 -#define CONFIG_DW_PORTS 1 -#define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_MII - -/* i2c Settings */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Flash Settings - */ -#undef CONFIG_CMD_JFFS2 -#define CONFIG_SYS_FLASH_CFI_WIDTH 2 -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0xb0000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 131 -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI6XX -#define CONFIG_ENV_SPI_MAX_HZ 25000000 -#define CONFIG_SF_DEFAULT_SPEED 25000000 -#define CONFIG_SPI_FLASH_ALL - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_SIZE 0x20000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_SECT_SIZE 0x8000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif - -#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0xB0100000\0" - -/* - * SDH Settings - */ -#define CONFIG_BFIN_SDH - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 - -#define CONFIG_CMD_SOFTSWITCH - -#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4) -#define CONFIG_BFIN_SOFT_SWITCH - -#define CONFIG_ADI_GPIO2 - -#if 0 -#define CONFIG_UART_MEM 1024 -#undef CONFIG_UART_CONSOLE -#undef CONFIG_JTAG_CONSOLE -#undef CONFIG_UART_CONSOLE_IS_JTAG -#endif - -#define CONFIG_BOARD_SIZE_LIMIT $$((512 * 1024)) - -/* - * Run core 1 from L1 SRAM start address when init uboot on core 0 - */ -/* #define CONFIG_CORE1_RUN 1 */ - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> -#endif diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h deleted file mode 100644 index a915b1a..0000000 --- a/include/configs/bfin_adi_common.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * U-Boot - Common settings for Analog Devices boards - */ - -#ifndef __CONFIG_BFIN_ADI_COMMON_H__ -#define __CONFIG_BFIN_ADI_COMMON_H__ - -/* - * Command Settings - */ -#ifndef _CONFIG_CMD_DEFAULT_H -# ifdef ADI_CMDS_NETWORK -# define CONFIG_BOOTP_SUBNETMASK -# define CONFIG_BOOTP_GATEWAY -# define CONFIG_BOOTP_DNS -# define CONFIG_BOOTP_NTPSERVER -# define CONFIG_BOOTP_RANDOM_DELAY -# define CONFIG_KEEP_SERVERADDR -# ifdef CONFIG_BFIN_MAC -# endif -# endif -# ifdef CONFIG_LIBATA -# define CONFIG_CMD_SATA -# endif -# ifdef CONFIG_MMC -# define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 -# endif -# ifdef CONFIG_MMC_SPI -# define CONFIG_CMD_MMC_SPI -# endif -# ifdef CONFIG_USB -# define CONFIG_CMD_USB_STORAGE -# endif -# if defined(CONFIG_NAND_PLAT) || defined(CONFIG_DRIVER_NAND_BFIN) -# define CONFIG_CMD_NAND -# define CONFIG_CMD_NAND_LOCK_UNLOCK -# endif -# ifdef CONFIG_POST -# define CONFIG_CMD_DIAG -# endif -# ifdef CONFIG_RTC_BFIN -# define CONFIG_CMD_DATE -# ifdef ADI_CMDS_NETWORK -# endif -# endif -# ifdef CONFIG_SPI -# define CONFIG_CMD_EEPROM -# endif -# if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT) -# define CONFIG_SOFT_I2C_READ_REPEATED_START -# endif -# ifdef CONFIG_MTD_NOR_FLASH -# define CONFIG_CMD_JFFS2 -# endif -# ifdef CONFIG_CMD_JFFS2 -# define CONFIG_JFFS2_SUMMARY -# endif -# define CONFIG_CMD_BOOTLDR -# define CONFIG_CMD_CPLBINFO -# define CONFIG_CMD_KGDB -# define CONFIG_CMD_LDRINFO -# define CONFIG_CMD_REGINFO -# define CONFIG_CMD_STRINGS -# if defined(__ADSPBF51x__) || defined(__ADSPBF52x__) || defined(__ADSPBF54x__) -# define CONFIG_CMD_OTP -# define CONFIG_CMD_SPIBOOTLDR -# endif -#endif - -/* - * Console Settings - */ -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_JTAG_CONSOLE -#ifdef CONFIG_UART_CONSOLE -# define CONFIG_BFIN_SERIAL -#endif - -/* - * Debug Settings - */ -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_DEBUG_DUMP 1 -#define CONFIG_KALLSYMS 1 -#define CONFIG_PANIC_HANG 1 - -/* - * Env Settings - */ -#ifndef CONFIG_BOOTCOMMAND -# define CONFIG_BOOTCOMMAND "run ramboot" -#endif -#ifdef CONFIG_VIDEO -# define CONFIG_BOOTARGS_VIDEO "console=tty0 " -#else -# define CONFIG_BOOTARGS_VIDEO "" -#endif -#ifndef CONFIG_BOOTARGS_ROOT -# define CONFIG_BOOTARGS_ROOT "/dev/mtdblock0 rw" -#endif -#ifndef FLASHBOOT_ENV_SETTINGS -# define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20100000\0" -#endif -#define CONFIG_BOOTARGS \ - "root=" CONFIG_BOOTARGS_ROOT " " \ - "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \ - "earlyprintk=" \ - "serial," \ - "uart" __stringify(CONFIG_UART_CONSOLE) "," \ - __stringify(CONFIG_BAUDRATE) " " \ - CONFIG_BOOTARGS_VIDEO \ - "console=ttyBF" __stringify(CONFIG_UART_CONSOLE) "," \ - __stringify(CONFIG_BAUDRATE) -#if defined(CONFIG_CMD_NAND) -# define NAND_ENV_SETTINGS \ - "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \ - "nandboot=" \ - "nand read $(loadaddr) 0x20000 0x100000;" \ - "run nandargs;" \ - "bootm" \ - "\0" -#else -# define NAND_ENV_SETTINGS -#endif -#if defined(CONFIG_CMD_NET) -# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -# define UBOOT_ENV_FILE "u-boot.bin" -# else -# define UBOOT_ENV_FILE "u-boot.ldr" -# endif -# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -# ifdef CONFIG_SPI -# define UBOOT_ENV_UPDATE \ - "eeprom write $(loadaddr) 0x0 $(filesize)" -# else -# ifndef CONFIG_BFIN_SPI_IMG_SIZE -# define CONFIG_BFIN_SPI_IMG_SIZE 0x40000 -# endif -# define UBOOT_ENV_UPDATE \ - "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \ - "sf erase 0 " __stringify(CONFIG_BFIN_SPI_IMG_SIZE) ";" \ - "sf write $(loadaddr) 0 $(filesize)" -# endif -# elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -# define UBOOT_ENV_UPDATE \ - "nand unlock 0 0x40000;" \ - "nand erase 0 0x40000;" \ - "nand write $(loadaddr) 0 0x40000" -# else -# ifndef UBOOT_ENV_UPDATE -# define UBOOT_ENV_UPDATE \ - "protect off 0x20000000 +$(filesize);" \ - "erase 0x20000000 +$(filesize);" \ - "cp.b $(loadaddr) 0x20000000 $(filesize)" -# endif -# endif -# ifdef CONFIG_NETCONSOLE -# define NETCONSOLE_ENV \ - "nc=" \ - "set ncip ${serverip};" \ - "set stdin nc;" \ - "set stdout nc;" \ - "set stderr nc" \ - "\0" -# else -# define NETCONSOLE_ENV -# endif -# define NETWORK_ENV_SETTINGS \ - NETCONSOLE_ENV \ - \ - "ubootfile=" UBOOT_ENV_FILE "\0" \ - "update=" \ - "tftp $(loadaddr) $(ubootfile);" \ - UBOOT_ENV_UPDATE \ - "\0" \ - "addip=set bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \ - "$(hostname):eth0:off" \ - "\0" \ - \ - "ramfile=uImage\0" \ - "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \ - "ramboot=" \ - "tftp $(loadaddr) $(ramfile);" \ - "run ramargs;" \ - "run addip;" \ - "bootm" \ - "\0" \ - \ - "nfsfile=vmImage\0" \ - "nfsargs=set bootargs " \ - "root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \ - "\0" \ - "nfsboot=" \ - "tftp $(loadaddr) $(nfsfile);" \ - "run nfsargs;" \ - "run addip;" \ - "bootm" \ - "\0" -#else -# define NETWORK_ENV_SETTINGS -#endif -#ifndef BOARD_ENV_SETTINGS -# define BOARD_ENV_SETTINGS -#endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - NAND_ENV_SETTINGS \ - NETWORK_ENV_SETTINGS \ - FLASHBOOT_ENV_SETTINGS \ - BOARD_ENV_SETTINGS - -/* - * Network Settings - */ -#ifdef CONFIG_CMD_NET -# define CONFIG_NETMASK 255.255.255.0 -# ifndef CONFIG_IPADDR -# define CONFIG_IPADDR 192.168.0.15 -# define CONFIG_GATEWAYIP 192.168.0.1 -# define CONFIG_SERVERIP 192.168.0.2 -# endif -# ifndef CONFIG_ROOTPATH -# define CONFIG_ROOTPATH "/romfs" -# endif -# ifdef CONFIG_CMD_DHCP -# ifndef CONFIG_SYS_AUTOLOAD -# define CONFIG_SYS_AUTOLOAD "no" -# endif -# endif -# define CONFIG_IP_DEFRAG -# define CONFIG_NET_RETRY_COUNT 20 -#endif - -/* - * Flash Settings - */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 - -/* - * SPI Settings - */ -#ifdef CONFIG_SPI_FLASH_ALL -#endif - -/* - * I2C Settings - */ -#if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT) -# ifndef CONFIG_SYS_I2C_SPEED -# define CONFIG_SYS_I2C_SPEED 50000 -# endif -# ifndef CONFIG_SYS_I2C_SLAVE -# define CONFIG_SYS_I2C_SLAVE 0 -# endif -#endif - -/* - * Misc Settings - */ -#ifndef CONFIG_BOARD_SIZE_LIMIT -# define CONFIG_BOARD_SIZE_LIMIT $$(( 256 * 1024 )) -#endif -#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */ -#define CONFIG_LZMA -#define CONFIG_MONITOR_IS_IN_RAM -#ifdef CONFIG_HW_WATCHDOG -# define CONFIG_BFIN_WATCHDOG -# ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS -# define CONFIG_WATCHDOG_TIMEOUT_MSECS 5000 -# endif -#endif -#ifndef CONFIG_ADI_GPIO2 -# define CONFIG_ADI_GPIO1 -#endif -#endif diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h deleted file mode 100644 index 4f65a1d..0000000 --- a/include/configs/blackstamp.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * U-Boot - Configuration file for BlackStamp board - * Configuration by Ben Matthews for UR LLE using bf533-stamp.h - * as a template - * See http://blackfin.uclinux.org/gf/project/blackstamp/ - */ - -#ifndef __CONFIG_BLACKSTAMP_H__ -#define __CONFIG_BLACKSTAMP_H__ - -#include <asm/config-pre.h> - -/* - * Debugging: Set these options if you're having problems - */ -/* - * #define CONFIG_DEBUG_EARLY_SERIAL - * #define DEBUG - * #define CONFIG_DEBUG_DUMP - * #define CONFIG_DEBUG_DUMP_SYMS -*/ -#define CONFIG_PANIC_HANG 0 - -/* CPU Options - * Be sure to set the Silicon Revision Correctly - */ -#define CONFIG_BFIN_CPU bf532-0.5 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Board settings - */ -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20300300 - -/* FLASH/ETHERNET uses the same address range - * Depending on what you have the CPLD doing - * this probably isn't needed - */ -#define SHARED_RESOURCES 1 - -/* Is I2C bit-banged? */ - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 16 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 3 - -/* - * Network settings - */ - -#ifdef CONFIG_SMC91111 -#define CONFIG_IPADDR 192.168.0.15 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_HOSTNAME blackstamp -#define CONFIG_ROOTPATH "/checkout/uClinux-dist/romfs" -#define CONFIG_SYS_AUTOLOAD "no" -#endif - -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x40000 - -/* - * SDRAM settings & memory map - */ - -#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (384 << 10) - -/* - * Command settings - */ - -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_ENV_OVERWRITE 1 - -#define CONFIG_CMD_BOOTLDR -#define CONFIG_CMD_CPLBINFO -#define CONFIG_CMD_DATE - -#define CONFIG_BOOTCOMMAND "run ramboot" -#define CONFIG_BOOTARGS \ - "root=/dev/mtdblock0 rw " \ - "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \ - "earlyprintk=" \ - "serial," \ - "uart" __stringify(CONFIG_UART_CONSOLE) "," \ - __stringify(CONFIG_BAUDRATE) " " \ - "console=ttyBF0," __stringify(CONFIG_BAUDRATE) - -#if defined(CONFIG_CMD_NET) -# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -# define UBOOT_ENV_FILE "u-boot.bin" -# else -# define UBOOT_ENV_FILE "u-boot.ldr" -# endif -# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -# ifdef CONFIG_SPI -# define UBOOT_ENV_UPDATE \ - "eeprom write $(loadaddr) 0x0 $(filesize)" -# else -# define UBOOT_ENV_UPDATE \ - "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \ - "sf erase 0 0x40000;" \ - "sf write $(loadaddr) 0 $(filesize)" -# endif -# else -# define UBOOT_ENV_UPDATE \ - "protect off 0x20000000 0x2003FFFF;" \ - "erase 0x20000000 0x2003FFFF;" \ - "cp.b $(loadaddr) 0x20000000 $(filesize)" -# endif -# define NETWORK_ENV_SETTINGS \ - "ubootfile=" UBOOT_ENV_FILE "\0" \ - "update=" \ - "tftp $(loadaddr) $(ubootfile);" \ - UBOOT_ENV_UPDATE \ - "\0" \ - "addip=set bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \ - "$(hostname):eth0:off" \ - "\0" \ - "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \ - "ramboot=" \ - "tftp $(loadaddr) uImage;" \ - "run ramargs;" \ - "run addip;" \ - "bootm" \ - "\0" \ - "nfsargs=set bootargs " \ - "root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \ - "\0" \ - "nfsboot=" \ - "tftp $(loadaddr) vmImage;" \ - "run nfsargs;" \ - "run addip;" \ - "bootm" \ - "\0" -#else -# define NETWORK_ENV_SETTINGS -#endif - -/* - * Console settings - */ -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BFIN_SERIAL - -/* - * I2C settings - * By default PF2 is used as SDA and PF3 as SCL on the Stamp board - * Located on the expansion connector on pins 86/85 - * Note these pins are arbitrarily chosen because we aren't using - * them yet. You can (and probably should) change these values! - */ -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF9 -#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF8 -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_RTC_BFIN 1 - -/* - * Serial Flash Infomation - */ -#define CONFIG_BFIN_SPI -/* For the M25P64 SCK Should be Kept < 15Mhz */ -#define CONFIG_ENV_SPI_MAX_HZ 15000000 -#define CONFIG_SF_DEFAULT_SPEED 15000000 - -/* - * FLASH organization and environment definitions - */ - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3 -#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983 -#define CONFIG_EBIU_SDRRC_VAL 0x268 -#define CONFIG_EBIU_SDGCTL_VAL 0x911109 - -#undef CONFIG_CMD_JFFS2 - -#endif diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h deleted file mode 100644 index fe823ba..0000000 --- a/include/configs/blackvme.h +++ /dev/null @@ -1,222 +0,0 @@ -/* U-Boot for BlackVME. (C) Wojtek Skulski 2010. - * The board includes ADSP-BF561 rev. 0.5, - * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG), - * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell), - * SPI boot flash on PF2 (M25P64 8MB, or M25P128 16 MB), - * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB), - * Spartan6-LX150 (memory-mapped; both PPIs also connected). - * See http://www.skutek.com - */ - -#ifndef __CONFIG_BLACKVME_H__ -#define __CONFIG_BLACKVME_H__ - -#include <asm/config-pre.h> - -/* Debugging: Set these options if you're having problems - * #define CONFIG_DEBUG_EARLY_SERIAL - * #define DEBUG - * #define CONFIG_DEBUG_DUMP - * #define CONFIG_DEBUG_DUMP_SYMS - * CONFIG_PANIC_HANG means that the board will not auto-reboot - */ -#define CONFIG_PANIC_HANG 0 - -/* CPU Options */ -#define CONFIG_BFIN_CPU bf561-0.5 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * CLOCK SETTINGS CAVEAT - * You CANNOT just change the clock settings, esp. the SCLK. - * The SDRAM timing, SPI baud, and the serial UART baud - * use SCLK frequency to set their own frequencies. Therefore, - * if you change the SCLK_DIV, you may also have to adjust - * SDRAM refresh and other timings. - * -------------------------------------------------------------- - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * 25 * 8 / 1 = 200 MHz - * 25 * 16 / 1 = 400 MHz - * 25 * 24 / 1 = 600 MHz - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - * 25 * 8 / 2 = 100 MHz - * 25 * 24 / 6 = 100 MHz - * 25 * 24 / 5 = 120 MHz - * 25 * 16 / 3 = 133 MHz - * 25 MHz because the oscillator also feeds the ether chip. - * CONFIG_CLKIN_HZ is 25 MHz written in Hz - * CLKIN_HALF controls the DF bit in PLL_CTL - * 0 = CLKIN 1 = CLKIN / 2 - * PLL_BYPASS controls the BYPASS bit in PLL_CTL - * 0 = do not bypass 1 = bypass PLL - * VCO_MULT = MSEL (multiplier) in PLL_CTL - * Values can range from 0-63 (where 0 means 64) - * CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY) - * SCLK_DIV = system clock divider, 1 to 15 - */ -#define CONFIG_CLKIN_HZ 25000000 -#define CONFIG_CLKIN_HALF 0 -#define CONFIG_PLL_BYPASS 0 -#define CONFIG_VCO_MULT 8 -#define CONFIG_CCLK_DIV 1 -#define CONFIG_SCLK_DIV 2 - -/* - * Ether chip in async memory space AMS3, same as BF561-EZ-KIT. - * Used in 32-bit mode. 16-bit mode not supported. - * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180 - */ -/* - * Network settings using a dedicated 2nd ether card in PC - * Windows will automatically acquire IP of that card - * Then use the dedicated card IP + 1 for the board - * http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network - */ -#define CONFIG_DRIVER_AX88180 1 -#define AX88180_BASE 0x2c000000 - -#define CONFIG_HOSTNAME blackvme /* Bfin board */ -#define CONFIG_IPADDR 169.254.144.145 /* Bfin board */ -#define CONFIG_GATEWAYIP 169.254.144.144 /* dedic card */ -#define CONFIG_SERVERIP 169.254.144.144 /* tftp server */ -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_ROOTPATH "/export/uClinux-dist/romfs" /*NFS*/ -#define CFG_AUTOLOAD "no" - -/* - * SDRAM settings & memory map - */ - -#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ -/* - * SDRAM reference page - * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram - * NOTE: BlackVME populates only SDRAM bank 0 - */ -/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */ -#define CONFIG_EBIU_SDGCTL_VAL 0x91114d /* global control */ -#define CONFIG_EBIU_SDRRC_VAL 0x306 /* refresh rate */ - -/* Async memory global settings. (ASRAM, not SDRAM) - * HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1 - * CLKOUT enabled, all async banks enabled, core has priority - * bank 0&1 16 bit (FPGA) - * bank 2&3 32 bit (ether and USB chips) - */ -#define CONFIG_EBIU_AMGCTL_VAL 0x3F /* ASRAM setup */ - -/* Async mem timing: BF561 HRM page 16-12 and 16-15. - * Default values 0xFFC2 FFC2 are the slowest supported. - * Example settings of CONFIG_EBIU_AMBCTL1_VAL - * 1. EZ-KIT settings: 0xFFC2 7BB0 - * 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx - * See the following page: - * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180 - * 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz: - * AX88180 WEN = 5 clocks REN 6 clocks @ SCLK = 100 MHz - * One extra clock needed because AX88180 is asynchronous to CPU. - */ - /* bank 1 0 */ -#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2 - /* bank 3 2 */ -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2 - -/* memory layout */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (384 << 10) - -/* - * Serial SPI Flash - * For the M25P64 SCK should be kept < 15 MHz - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x40000 - -#define CONFIG_ENV_SPI_MAX_HZ 15000000 -#define CONFIG_SF_DEFAULT_SPEED 15000000 - -/* - * Interactive command settings - */ - -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE 1 - -#define CONFIG_CMD_BOOTLDR -#define CONFIG_CMD_CPLBINFO - -/* - * Default: boot from SPI flash. - * "sfboot" is a composite command defined in extra settings - */ -#define CONFIG_BOOTCOMMAND "run sfboot" - -/* - * Console settings - */ -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BFIN_SERIAL - -/* - * U-Boot environment variables. Use "printenv" to examine. - * http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env - */ -#define CONFIG_BOOTARGS \ - "root=/dev/mtdblock0 rw " \ - "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \ - "earlyprintk=serial,uart0," \ - __stringify(CONFIG_BAUDRATE) " " \ - "console=ttyBF0," __stringify(CONFIG_BAUDRATE) " " - -/* Convenience env variables & commands. - * Reserve kernstart = 0x20000 = 128 kB for U-Boot. - * Reserve kernarea = 0x500000 = 5 MB for kernel (reasonable size). - * U-Boot image is saved at flash offset=0. - * Kernel image is saved at flash offset=$kernstart. - * Instructions. Ksave takes about a minute to complete. - * 1. Update U-Boot: run uget; run usave - * 2. Update kernel: run kget; run ksave - * After updating U-Boot also update the kernel per above instructions - * to make the saved environment consistent with the flash. - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernstart=0x20000\0" \ - "kernarea=0x500000\0" \ - "uget=tftp u-boot.ldr\0" \ - "kget=tftp uImage\0" \ - "usave=sf probe 2; " \ - "sf erase 0 $(kernstart); " \ - "sf write $(fileaddr) 0 $(filesize)\0" \ - "ksave=sf probe 2; " \ - "saveenv; " \ - "echo Now patiently wait for the prompt...; " \ - "sf erase $(kernstart) $(kernarea); " \ - "sf write $(fileaddr) $(kernstart) $(filesize)\0" \ - "sfboot=sf probe 2; " \ - "sf read $(loadaddr) $(kernstart) $(filesize); " \ - "run addip; bootm\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):eth0:off\0" - -/* - * Soft I2C settings (BF561 does not have hard I2C) - * PF12,13 on SPI connector 0. - */ -#ifdef CONFIG_SYS_I2C_SOFT -# define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF12 -# define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF13 -# define CONFIG_SYS_I2C_SPEED 50000 -# define CONFIG_SYS_I2C_SLAVE 0xFE -#endif - -#undef CONFIG_CMD_JFFS2 - -#endif diff --git a/include/configs/br4.h b/include/configs/br4.h deleted file mode 100644 index 8a7a359..0000000 --- a/include/configs/br4.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * U-Boot - Configuration file for BR4 Appliance - * - * based on bf537-stamp.h - * Copyright (c) Switchfin Org. <dpn@switchfin.org> - */ - -#ifndef __CONFIG_BR4_H__ -#define __CONFIG_BR4_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 24 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x306 -#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_NETCONSOLE -#endif -#define CONFIG_HOSTNAME br4 -#define CONFIG_TFTP_BLOCKSIZE 4404 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * NAND Settings - */ -#define CONFIG_NAND_PLAT -#define CONFIG_SYS_NAND_BASE 0x20000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_WRITE(addr, cmd) \ - do { \ - bfin_write8(addr, cmd); \ - SSYNC(); \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_GPIO_DEV_READY GPIO_PF9 - -/* - * Misc Settings - */ -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run nandboot" -#define CONFIG_LOADADDR 0x2000000 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -/* - * Overwrite some settings defined in bfin_adi_common.h - */ -#undef NAND_ENV_SETTINGS -#define NAND_ENV_SETTINGS \ - "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \ - "nandboot=" \ - "nand read $(loadaddr) 0x0 0x900000;" \ - "run nandargs;" \ - "bootm" \ - "\0" - -#endif diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h deleted file mode 100644 index 3b6f9ba..0000000 --- a/include/configs/cm-bf527.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * U-Boot - Configuration file for CM-BF527 board - */ - -#ifndef __CONFIG_CM_BF527_H__ -#define __CONFIG_CM_BF527_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf527-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 21 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* Decrease core voltage */ -#define CONFIG_VR_CTL_VAL (VLEV_120 | CLKBUFOE | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL 0x3f8 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * NAND Settings - * (can't be used sametime as ethernet) - */ -/* #define CONFIG_BFIN_NFC */ -#ifdef CONFIG_BFIN_NFC -#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 -#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND -#endif - -/* - * Network Settings - */ -#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \ - !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC) -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_RMII -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME cm-bf527 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 67 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x20008000 -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_SECT_SIZE 0x8000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS \ - "flashboot=flread 20040000 1000000 300000;" \ - "bootm 0x1000000\0" - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h deleted file mode 100644 index 01a3579..0000000 --- a/include/configs/cm-bf533.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * U-Boot - Configuration file for CM-BF533 board - */ - -#ifndef __CONFIG_CM_BF533_H__ -#define __CONFIG_CM_BF533_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf533-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 22 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* Decrease core voltage */ -#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 8192) - (7 + 2)) -#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3) - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20200300 -#define CONFIG_HOSTNAME cm-bf533 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 16 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x10000 - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h deleted file mode 100644 index d9f91b5..0000000 --- a/include/configs/cm-bf537e.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * U-Boot - Configuration file for CM-BF537E board - */ - -#ifndef __CONFIG_CM_BF537E_H__ -#define __CONFIG_CM_BF537E_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 21 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* Decrease core voltage */ -#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL 0x3f8 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE 0x20308000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME cm-bf537e - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 35 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SECT_SIZE 0x8000 -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#endif -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * SPI_MMC Settings - */ -#define CONFIG_MMC_SPI - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS \ - "flashboot=flread 20040000 1000000 3c0000;" \ - "bootm 0x1000000\0" -#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024)) - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h deleted file mode 100644 index af11ebe..0000000 --- a/include/configs/cm-bf537u.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * U-Boot - Configuration file for CM-BF537U board - */ - -#ifndef __CONFIG_CM_BF537U_H__ -#define __CONFIG_CM_BF537U_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 30000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 18 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 -/* Core voltage */ -#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL 0x3f8 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE 0x20308000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME cm-bf537u - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 35 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SECT_SIZE 0x8000 -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#endif -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * SPI_MMC Settings - */ -#define CONFIG_MMC_SPI - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS \ - "flashboot=flread 20040000 1000000 300000;" \ - "bootm 0x1000000\0" -#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024)) - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h deleted file mode 100644 index 10e8efd..0000000 --- a/include/configs/cm-bf548.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * U-Boot - Configuration file for cm-bf548 board - */ - -#ifndef __CONFIG_CM_BF548_H__ -#define __CONFIG_CM_BF548_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf548-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 21 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* Decrease core voltage */ -#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE -#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222 -#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021 - -/* Default bank mapping: - * Async Bank 0 - 32MB Burst Flash - * Async Bank 1 - Ethernet - * Async Bank 2 - Nothing - * Async Bank 3 - Nothing - */ -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 -#define CONFIG_EBIU_FCTL_VAL (BCLK_4) -#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH) - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (640 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE 0x24000000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_HOSTNAME cm-bf548 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 259 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x20008000 -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Misc Settings - */ -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 1 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" - -#define CONFIG_ADI_GPIO2 - -#ifndef __ADSPBF542__ -/* Don't waste time transferring a logo over the UART */ -# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) -# define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h> -# endif -# define CONFIG_DEB_DMA_URGENT -#endif - -/* Define if want to do post memory test */ -#undef CONFIG_POST -#ifdef CONFIG_POST -#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ -#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ -#endif - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h deleted file mode 100644 index ac1646c..0000000 --- a/include/configs/cm-bf561.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * U-Boot - Configuration file for CM-BF561 board - */ - -#ifndef __CONFIG_CM_BF561_H__ -#define __CONFIG_CM_BF561_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf561-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* Decrease core voltage */ -#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 4096) - (7 + 2)) -#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3) - -#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | B3_PEN | B2_PEN | B1_PEN | B0_PEN | AMBEN_ALL | AMCKEN) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE 0x24008000 /* AMS1 */ -#define CONFIG_SMC911X_16_BIT -#define CONFIG_HOSTNAME cm-bf561 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 67 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 45511be..14b25d4 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -237,7 +237,6 @@ #define CONFIG_SERIAL_TAG /* misc */ -#define CONFIG_STACKSIZE (128 * 1024) #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) #define CONFIG_MISC_INIT_R diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 2c9c014..87d2012 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -136,8 +136,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 -#define CONFIG_STACKSIZE SZ_128K - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 888899e..73b43bd 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -150,12 +150,6 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING -/* - * Stack sizes - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ - /* Physical memory map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM (0x80000000) diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h new file mode 100644 index 0000000..add5f90 --- /dev/null +++ b/include/configs/controlcenterdc.h @@ -0,0 +1,228 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_CONTROLCENTERDC_H +#define _CONFIG_CONTROLCENTERDC_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_CUSTOMER_BOARD_SUPPORT + +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_LAST_STAGE_INIT +#define CONFIG_SPL_BOARD_INIT + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TEXT_BASE 0x00800000 + +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +#define CONFIG_LOADADDR 1000000 + +/* + * Commands configuration + */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_SPI + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 + +/* + * SDIO/MMC Card Configuration + */ +#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE + +/* + * SATA/SCSI/AHCI configuration + */ +#define CONFIG_LIBATA +#define CONFIG_SCSI +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* Additional FS support/configuration */ +#define CONFIG_SUPPORT_VFAT + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 1 +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI +#define CONFIG_PCI_MVEBU +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define CONFIG_SYS_ALT_MEMTEST + +/* + * Software (bit-bang) MII driver configuration + */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +#define CONFIG_BITBANGMII_MULTI + +/* SPL */ +/* + * Select the boot device here + * + * Currently supported are: + * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash + * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) + */ +#define SPL_BOOT_SPI_NOR_FLASH 1 +#define SPL_BOOT_SDIO_MMC_CARD 2 +#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH + +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_SIZE (160 << 10) + +#if defined(CONFIG_SECURED_MODE_IMAGE) +#define CONFIG_SPL_TEXT_BASE 0x40002614 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614) +#else +#define CONFIG_SPL_TEXT_BASE 0x40000030 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30) +#endif + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT + +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH +/* SPL related SPI defines */ +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000 +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS +#endif + +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD +/* SPL related MMC defines */ +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 +#define CONFIG_SYS_MMC_U_BOOT_OFFS (168 << 10) +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ +#endif +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_HOSTNAME ccdc +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "ccdc.img" + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth1\0" \ + "consoledev=ttyS1\0" \ + "u-boot=u-boot.bin\0" \ + "bootfile_addr=1000000\0" \ + "keyprogram_addr=3000000\0" \ + "keyprogram_file=keyprogram.img\0" \ + "fdtfile=controlcenterdc.dtb\0" \ + "load=tftpboot ${loadaddr} ${u-boot}\0" \ + "mmcdev=0:2\0" \ + "update=sf probe 1:0;" \ + " sf erase 0 +${filesize};" \ + " sf write ${fileaddr} 0 ${filesize}\0" \ + "upd=run load update\0" \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" \ + "loadkeyprogram=tpm flush_keys;" \ + " mmc rescan;" \ + " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\ + " source ${keyprogram_addr}:script@1\0" \ + "gpio1=gpio@22_25\0" \ + "gpio2=A29\0" \ + "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \ + "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \ + "bootfail=for i in ${blinkseq}; do" \ + " if test $i -eq 0; then" \ + " gpio clear ${gpio1}; gpio set ${gpio2};" \ + " elif test $i -eq 1; then" \ + " gpio clear ${gpio1}; gpio clear ${gpio2};" \ + " elif test $i -eq 2; then" \ + " gpio set ${gpio1}; gpio set ${gpio2};" \ + " else;" \ + " gpio clear ${gpio1}; gpio set ${gpio2};" \ + " fi; sleep 0.12; done\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \ + "console=${consoledev},${baudrate} ${othbootargs}; " \ + "tftpboot ${bootfile_addr} ${bootfile}; " \ + "bootm ${bootfile_addr}" + +#define CONFIG_MMCBOOTCOMMAND \ + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ + "console=${consoledev},${baudrate} ${othbootargs}; " \ + "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \ + "bootm ${bootfile_addr}" + +#define CONFIG_BOOTCOMMAND \ + "if env exists keyprogram; then;" \ + " setenv keyprogram; run nfsboot;" \ + " fi;" \ + " run dobootfail" + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#endif /* _CONFIG_CONTROLCENTERDC_H */ diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h deleted file mode 100644 index 1690dda..0000000 --- a/include/configs/dnp5370.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * U-Boot - Configuration file for SSV DNP5370 board - */ - -#ifndef __CONFIG_DNP5370_H__ -#define __CONFIG_DNP5370_H__ - -/* this must come first */ -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -#define CONFIG_CLKIN_HZ 25000000 -#define CONFIG_CLKIN_HALF 0 -#define CONFIG_PLL_BYPASS 0 -#define CONFIG_VCO_MULT 24 -#define CONFIG_CCLK_DIV 1 -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL 0x03a0 -#define CONFIG_EBIU_SDBCTL_VAL 0x0013 -#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d - -#define CONFIG_EBIU_AMGCTL_VAL 0xF7 -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define CONFIG_ROOTPATH "/romfs" - -#define CONFIG_BFIN_MAC 1 -#define CONFIG_PHY_ADDR 0 -#define CONFIG_RMII 1 - -#endif - -/* - * Flash Settings - * - * Only 3 MB of the 4 MB NOR flash are addressable. - * But limiting the flash size does not seem to work. - * It seems the CFI detection has precedence. - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* (M29W320EB) */ - -/* 512k reserved for u-boot */ -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x20004000 -#define CONFIG_ENV_SIZE 0x00002000 -#define CONFIG_ENV_SECT_SIZE 0x00002000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET 0x00004000 /* (CONFIG_ENV_ADDR - CONFIG_FLASH_BASE) */ - -#define ENV_IS_EMBEDDED -#define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); - -/* - * Misc Settings - */ -#define CONFIG_CMD_STRINGS -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_SYS_LONGHELP - -/* This disables the hardware watchdog (not inside the bfin) */ -#define CONFIG_DNP5370_EXT_WD_DISABLE 1 - -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BFIN_SERIAL -#define CONFIG_BOOTCOMMAND "bootm 0x20030000" -#define CONFIG_BOOTARGS "console=ttyBF0,115200 root=/dev/mtdblock3 rootfstype=ext2" - -/* Convenience commands to update Linux in NOR flash */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fetchme=tftpboot 0x01000000 uImage;" \ - "iminfo\0" \ - "flashme=protect off 0x20030000 0x2003ffff;" \ - "erase 0x20030000 0x202effff;" \ - "cp.b 0x01000000 0x20030000 0x2c0000\0" \ - "runme=bootm 0x01000000\0" - -#endif diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 43e74a2..7d6f7ff 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -122,11 +122,6 @@ #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_QSPI_QUAD_SUPPORT -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH -#endif - /* * Default to using SPI for environment, etc. * 0x000000 - 0x040000 : QSPI.SPL (256KiB) @@ -260,8 +255,4 @@ #endif #endif /* NOR support */ -/* EEPROM */ -#define CONFIG_EEPROM_CHIP_ADDRESS 0x50 -#define CONFIG_EEPROM_BUS_ADDRESS 0 - #endif /* __CONFIG_DRA7XX_EVM_H */ diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h index 99f0dae..f012af5 100644 --- a/include/configs/edb93xx.h +++ b/include/configs/edb93xx.h @@ -74,7 +74,6 @@ #define CONFIG_EP93XX 1 /* This is a Cirrus Logic 93xx SoC */ #define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ -#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */ /* Monitor configuration */ #undef CONFIG_CMD_DATE @@ -161,12 +160,6 @@ /* Run-time memory allocatons */ #define CONFIG_SYS_GBL_DATA_SIZE 128 -#define CONFIG_STACKSIZE (128 * 1024) - -#if defined(CONFIG_USE_IRQ) -#define CONFIG_STACKSIZE_IRQ (4 * 1024) -#define CONFIG_STACKSIZE_FIQ (4 * 1024) -#endif #define CONFIG_SYS_MALLOC_LEN (512 * 1024) diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index afb5b73..0848397 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -99,8 +99,6 @@ #define CONFIG_SYS_MEMTEST_END 0x10800000 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 -#define CONFIG_STACKSIZE (128 * 1024) - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 48c9e0b..658f4d9 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -76,8 +76,6 @@ #define CONFIG_SYS_MEMTEST_END 0x10010000 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 -#define CONFIG_STACKSIZE (128 * 1024) - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/evb_rk3288.h b/include/configs/evb_rk3288.h index 6a068bb..bbd54a1 100644 --- a/include/configs/evb_rk3288.h +++ b/include/configs/evb_rk3288.h @@ -11,7 +11,7 @@ #include <configs/rk3288_common.h> #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_WHITE_ON_BLACK diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index b4f7530..ade66a4 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -23,7 +23,7 @@ /* input clock of PLL: 24MHz input clock */ #define CONFIG_SYS_CLK_FREQ 24000000 -#define CONFIG_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG diff --git a/include/configs/fennec_rk3288.h b/include/configs/fennec_rk3288.h index 6a068bb..bbd54a1 100644 --- a/include/configs/fennec_rk3288.h +++ b/include/configs/fennec_rk3288.h @@ -11,7 +11,7 @@ #include <configs/rk3288_common.h> #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_WHITE_ON_BLACK diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index f86e20c..43b1fb0 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -260,7 +260,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_CMDLINE_EDITING -#define CONFIG_STACKSIZE (128 * 1024) /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h deleted file mode 100644 index 2c8adab..0000000 --- a/include/configs/gr_cpci_ax2000.h +++ /dev/null @@ -1,339 +0,0 @@ -/* Configuration header file for Gaisler GR-CPCI-AX2000 - * AX board. Note that since the AX is removable the configuration - * for this board must be edited below. - * - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2008 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H__ -#define __CONFIG_H__ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_CPCI_AX2000 1 /* ... on GR-CPCI-AX2000 board */ - -#define CONFIG_LEON_RAM_SRAM 1 -#define CONFIG_LEON_RAM_SDRAM 2 -#define CONFIG_LEON_RAM_SDRAM_NOSRAM 3 - -/* Select Memory to run from - * - * SRAM - UBoot is run in SRAM, SRAM-0x40000000, SDRAM-0x60000000 - * SDRAM - UBoot is run in SDRAM, SRAM-0x40000000 and SDRAM-0x60000000 - * SDRAM_NOSRAM - UBoot is run in SDRAM, SRAM not available, SDRAM at 0x40000000 - * - * Note, if Linux is to be used, SDRAM or SDRAM_NOSRAM is required since - * it doesn't fit into the 4Mb SRAM. - * - * SRAM is default since it will work for all systems, however will not - * be able to boot linux. - */ -#define CONFIG_LEON_RAM_SELECT CONFIG_LEON_RAM_SRAM - -/* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 20000000 /* 20MHz */ - -/* - * Serial console configuration - */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* Partitions */ - -/* - * Supported commands - */ -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_IRQ - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS_BASE \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "getkernel=tftpboot $(scratch) $(bootfile)\0" \ - "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.206:192.168.0.20:192.168.0.1:255.255.255.0:ax2000:eth0\0" - -#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SRAM -#define CONFIG_EXTRA_ENV_SETTINGS_SELECT \ - "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \ - "scratch=40200000\0" \ - "" -#elif CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM -#define CONFIG_EXTRA_ENV_SETTINGS_SELECT \ - "net_nfs=tftp 60000000 ${bootfile};run nfsargs addip;bootm\0" \ - "scratch=60800000\0" \ - "" -#else -/* More than 4Mb is assumed when running from SDRAM */ -#define CONFIG_EXTRA_ENV_SETTINGS_SELECT \ - "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \ - "scratch=40800000\0" \ - "" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_SETTINGS_BASE CONFIG_EXTRA_ENV_SETTINGS_SELECT - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.20 -#define CONFIG_IPADDR 192.168.0.206 -#define CONFIG_ROOTPATH "/export/rootfs" -#define CONFIG_HOSTNAME ax2000 -#define CONFIG_BOOTFILE "/uImage" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* Memory MAP - * - * Flash: - * |--------------------------------| - * | 0x00000000 Text & Data & BSS | * - * | for Monitor | * - * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| * - * | UNUSED / Growth | * 256kb - * |--------------------------------| - * | 0x00050000 Base custom area | * - * | kernel / FS | * - * | | * Rest of Flash - * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| - * | END-0x00008000 Environment | * 32kb - * |--------------------------------| - * - * - * - * Main Memory (4Mb SRAM or XMb SDRAM): - * |--------------------------------| - * | UNUSED / scratch area | - * | | - * | | - * | | - * | | - * |--------------------------------| - * | Monitor .Text / .DATA / .BSS | * 256kb - * | Relocated! | * - * |--------------------------------| - * | Monitor Malloc | * 128kb (contains relocated environment) - * |--------------------------------| - * | Monitor/kernel STACK | * 64kb - * |--------------------------------| - * | Page Table for MMU systems | * 2k - * |--------------------------------| - * | PROM Code accessed from Linux | * 6kb-128b - * |--------------------------------| - * | Global data (avail from kernel)| * 128b - * |--------------------------------| - * - */ - -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFC000000 for 64 MB - * 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB - */ -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x00800000 - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ -#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -/*** CFI CONFIG ***/ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -/* Bypass cache when reading regs from flash memory */ -#define CONFIG_SYS_FLASH_CFI_BYPASS_READ -/* Buffered writes (32byte/go) instead of single accesses */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* - * Environment settings - */ -/*#define CONFIG_ENV_IS_NOWHERE 1*/ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* CONFIG_ENV_ADDR need to be at sector boundary */ -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - * - * Always 4Mb SRAM available - * SDRAM module may be available on 0x60000000, SDRAM - * is configured as if a 128Mb SDRAM module is available. - */ - -#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#else -#define CONFIG_SYS_SDRAM_BASE 0x60000000 -#endif - -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE) - -/* 4Mb SRAM available */ -#if CONFIG_LEON_RAM_SELECT != CONFIG_LEON_RAM_SDRAM_NOSRAM -#define CONFIG_SYS_SRAM_BASE 0x40000000 -#define CONFIG_SYS_SRAM_SIZE 0x400000 -#define CONFIG_SYS_SRAM_END (CONFIG_SYS_SRAM_BASE+CONFIG_SYS_SRAM_SIZE) -#endif - -/* Select RAM used to run U-BOOT from... */ -#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SRAM -#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SRAM_BASE -#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SRAM_SIZE -#define CONFIG_SYS_RAM_END CONFIG_SYS_SRAM_END -#else -#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE -#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END -#endif - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32) -#define CONFIG_SYS_STACK_SIZE (0x10000-32) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE) -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN) - -/* relocated monitor area */ -#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE -#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN) - -/* make un relocated address from relocated address */ -#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE)) - -/* - * Ethernet configuration uses on board SMC91C111 - */ -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */ -#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ -#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ -/*#define CONFIG_SHOW_ACTIVITY*/ -#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ - -#define CONFIG_PHY_ADDR 0x00 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Various low-level settings - */ - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00005000 - -/***** Gaisler GRLIB IP-Cores Config ********/ - -#define CONFIG_SYS_GRLIB_SDRAM 0 - -/* No SDRAM Configuration */ -#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1 - -/* See, GRLIB Docs (grip.pdf) on how to set up - * These the memory controller registers. - */ -#define CONFIG_SYS_GRLIB_ESA_MCTRL1 -#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11)) -#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM -#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x82206000 -#else -#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x82205260 -#endif -#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x0809a000 - -/* GRLIB FT-MCTRL configuration */ -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1 -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11)) -#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x82206000 -#else -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x82205260 -#endif -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x0809a000 - -/* no DDR controller */ -#undef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1 - -/* no DDR2 Controller */ -#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1 - -/* default kernel command line */ -#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h deleted file mode 100644 index 2edb1b0..0000000 --- a/include/configs/gr_ep2s60.h +++ /dev/null @@ -1,304 +0,0 @@ -/* Configuration header file for Gaisler Research AB's Template - * design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS - * Development board Stratix II edition, with the FPGA device - * EP2S60. - * - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2008 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H__ -#define __CONFIG_H__ - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* Altera NIOS Development board, Stratix II board */ -#define CONFIG_GR_EP2S60 1 - -/* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */ - -/* Define this is the GR-2S60-MEZZ mezzanine is available and you - * want to use the USB and GRETH functionality of the board - */ -#undef GR_2S60_MEZZ - -#ifdef GR_2S60_MEZZ -#define USE_GRETH 1 -#define USE_GRUSB 1 -#endif - -/* - * Serial console configuration - */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* Partitions */ - -/* - * Supported commands - */ -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_IRQ - -/* USB support */ -#if USE_GRUSB -#define CONFIG_USB_UHCI -/* Enable needed helper functions */ -#endif - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \ - "scratch=40800000\0" \ - "getkernel=tftpboot $(scratch) $(bootfile)\0" \ - "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \ - "" - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.20 -#define CONFIG_IPADDR 192.168.0.207 -#define CONFIG_ROOTPATH "/export/rootfs" -#define CONFIG_HOSTNAME ml401 -#define CONFIG_BOOTFILE "/uImage" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* Memory MAP - * - * Flash: - * |--------------------------------| - * | 0x00000000 Text & Data & BSS | * - * | for Monitor | * - * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| * - * | UNUSED / Growth | * 256kb - * |--------------------------------| - * | 0x00050000 Base custom area | * - * | kernel / FS | * - * | | * Rest of Flash - * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| - * | END-0x00008000 Environment | * 32kb - * |--------------------------------| - * - * - * - * Main Memory: - * |--------------------------------| - * | UNUSED / scratch area | - * | | - * | | - * | | - * | | - * |--------------------------------| - * | Monitor .Text / .DATA / .BSS | * 512kb - * | Relocated! | * - * |--------------------------------| - * | Monitor Malloc | * 128kb (contains relocated environment) - * |--------------------------------| - * | Monitor/kernel STACK | * 64kb - * |--------------------------------| - * | Page Table for MMU systems | * 2k - * |--------------------------------| - * | PROM Code accessed from Linux | * 6kb-128b - * |--------------------------------| - * | Global data (avail from kernel)| * 128b - * |--------------------------------| - * - */ - -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFC000000 for 64 MB - * 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB - */ -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */ - -#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ -#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -/*** CFI CONFIG ***/ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -/* Bypass cache when reading regs from flash memory */ -#define CONFIG_SYS_FLASH_CFI_BYPASS_READ -/* Buffered writes (32byte/go) instead of single accesses */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* - * Environment settings - */ -/*#define CONFIG_ENV_IS_NOWHERE 1*/ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* CONFIG_ENV_ADDR need to be at sector boundary */ -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 0x02000000 -#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE) - -/* no SRAM available */ -#undef CONFIG_SYS_SRAM_BASE -#undef CONFIG_SYS_SRAM_SIZE - -#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE -#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32) -#define CONFIG_SYS_STACK_SIZE (0x10000-32) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE) -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN) - -/* relocated monitor area */ -#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE -#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN) - -/* make un relocated address from relocated address */ -#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE)) - -/* - * Ethernet configuration uses on board SMC91C111, however if a mezzanine - * with a PHY is attached the GRETH can be used on this board. - * Define USE_GRETH in order to use the mezzanine provided PHY with the - * onchip GRETH network MAC, note that this is not supported by the - * template design. - */ -#ifndef USE_GRETH - -/* USE SMC91C111 MAC */ -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */ -#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ -#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ -/*#define CONFIG_SHOW_ACTIVITY*/ -#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ - -#else - -/* USE GRETH Ethernet Driver */ -#define CONFIG_GRETH 1 -#endif - -#define CONFIG_PHY_ADDR 0x00 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00005000 - -/***** Gaisler GRLIB IP-Cores Config ********/ - -#define CONFIG_SYS_GRLIB_SDRAM 0 - -/* No SDRAM Configuration */ -#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1 - -/* See, GRLIB Docs (grip.pdf) on how to set up - * These the memory controller registers. - */ -#define CONFIG_SYS_GRLIB_ESA_MCTRL1 -#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11)) -#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x00000000 -#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00000000 - -/* GRLIB FT-MCTRL configuration */ -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1 -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11)) -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x00000000 -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00000000 - -/* DDR controller */ -#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1 -#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL 0xa900830a - -/* no DDR2 Controller */ -#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1 - -/* default kernel command line */ -#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h deleted file mode 100644 index b8ac7d1..0000000 --- a/include/configs/gr_xc3s_1500.h +++ /dev/null @@ -1,271 +0,0 @@ -/* Configuration header file for Gaisler GR-XC3S-1500 - * spartan board. - * - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H__ -#define __CONFIG_H__ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_GRXC3S1500 1 /* ... on GR-XC3S-1500 board */ - -/* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ - -/* - * Serial console configuration - */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* Partitions */ - -/* - * Supported commands - */ -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_IRQ - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \ - "scratch=40200000\0" \ - "getkernel=tftpboot $(scratch) $(bootfile)\0" \ - "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.206:192.168.0.20:192.168.0.1:255.255.255.0:grxc3s1500_daniel:eth0\0" \ - "" - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.20 -#define CONFIG_IPADDR 192.168.0.206 -#define CONFIG_ROOTPATH "/export/rootfs" -#define CONFIG_HOSTNAME grxc3s1500 -#define CONFIG_BOOTFILE "/uImage" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* Memory MAP - * - * Flash: - * |--------------------------------| - * | 0x00000000 Text & Data & BSS | * - * | for Monitor | * - * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| * - * | UNUSED / Growth | * 256kb - * |--------------------------------| - * | 0x00050000 Base custom area | * - * | kernel / FS | * - * | | * Rest of Flash - * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| - * | END-0x00008000 Environment | * 32kb - * |--------------------------------| - * - * - * - * Main Memory: - * |--------------------------------| - * | UNUSED / scratch area | - * | | - * | | - * | | - * | | - * |--------------------------------| - * | Monitor .Text / .DATA / .BSS | * 256kb - * | Relocated! | * - * |--------------------------------| - * | Monitor Malloc | * 128kb (contains relocated environment) - * |--------------------------------| - * | Monitor/kernel STACK | * 64kb - * |--------------------------------| - * | Page Table for MMU systems | * 2k - * |--------------------------------| - * | PROM Code accessed from Linux | * 6kb-128b - * |--------------------------------| - * | Global data (avail from kernel)| * 128b - * |--------------------------------| - * - */ - -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFC000000 for 64 MB - * 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB - */ -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x00800000 - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ -#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -/*** CFI CONFIG ***/ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -/* Bypass cache when reading regs from flash memory */ -#define CONFIG_SYS_FLASH_CFI_BYPASS_READ -/* Buffered writes (32byte/go) instead of single accesses */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* - * Environment settings - */ -/*#define CONFIG_ENV_IS_NOWHERE 1*/ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* CONFIG_ENV_ADDR need to be at sector boundary */ -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 0x4000000 -#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE) - -/* no SRAM available */ -#undef CONFIG_SYS_SRAM_BASE -#undef CONFIG_SYS_SRAM_SIZE - -/* Always Run U-Boot from SDRAM */ -#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE -#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32) -#define CONFIG_SYS_STACK_SIZE (0x10000-32) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE) -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN) - -/* relocated monitor area */ -#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE -#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN) - -/* make un relocated address from relocated address */ -#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE)) - -/* - * Ethernet configuration - */ -#define CONFIG_GRETH 1 - -#define CONFIG_PHY_ADDR 0x00 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Various low-level settings - */ - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00005000 - -/***** Gaisler GRLIB IP-Cores Config ********/ - -#define CONFIG_SYS_GRLIB_SDRAM 0 - -/* No SDRAM Configuration */ -#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1 - -/* See, GRLIB Docs (grip.pdf) on how to set up - * These the memory controller registers. - */ -#define CONFIG_SYS_GRLIB_ESA_MCTRL1 -#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x000000ff | (1<<11)) -#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x82206000 -#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00136000 - -/* GRLIB FT-MCTRL configuration */ -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1 -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x000000ff | (1<<11)) -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x82206000 -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00136000 - -/* no DDR controller */ -#undef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1 - -/* no DDR2 Controller */ -#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1 - -/* default kernel command line */ -#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h index d7b9c18..abc4214 100644 --- a/include/configs/grasshopper.h +++ b/include/configs/grasshopper.h @@ -69,9 +69,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_STACKSIZE (2048) - - /* * After booting the board for the first time, new ethernet addresses * should be generated and assigned to the environment variables diff --git a/include/configs/grsim.h b/include/configs/grsim.h deleted file mode 100644 index 4594b13..0000000 --- a/include/configs/grsim.h +++ /dev/null @@ -1,313 +0,0 @@ -/* Configuration header file for LEON3 GRSIM, trying to be similar - * to Gaisler's GR-XC3S-1500 board. - * - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H__ -#define __CONFIG_H__ - -/* - * High Level Configuration Options - * (easy to change) - * - * Select between TSIM or GRSIM by setting CONFIG_GRSIM or CONFIG_TSIM to 1. - * - * TSIM command: - * $ tsim-leon3 -sdram 32768 -ram 4096 -rom 2048 -mmu -cas - * - * In the evaluation version of TSIM, the -sdram/-ram/-rom arguments are - * hard-coded to these values and need not be specified. (see below) - * - * Get TSIM from http://www.gaisler.com/index.php/downloads/simulators - */ - -#define CONFIG_GRSIM 0 /* ... not running on GRSIM */ -#define CONFIG_TSIM 1 /* ... running on TSIM */ - -/* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ - -/* - * Serial console configuration - */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* Partitions */ - -/* - * Supported commands - */ -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_REGINFO - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/export/roofs\0" \ - "scratch=40000000\0" \ - "getkernel=tftpboot $(scratch) $(bootfile)\0" \ - "bootargs=console=ttyS0,38400" \ - "" -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.81 -#define CONFIG_IPADDR 192.168.0.80 -#define CONFIG_ROOTPATH "/export/rootfs" -#define CONFIG_HOSTNAME grxc3s1500 -#define CONFIG_BOOTFILE "/uImage" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* Memory MAP - * - * Flash: - * |--------------------------------| - * | 0x00000000 Text & Data & BSS | * - * | for Monitor | * - * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| * - * | UNUSED / Growth | * 256kb - * |--------------------------------| - * | 0x00050000 Base custom area | * - * | kernel / FS | * - * | | * Rest of Flash - * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| - * | END-0x00008000 Environment | * 32kb - * |--------------------------------| - * - * - * - * Main Memory: - * |--------------------------------| - * | UNUSED / scratch area | - * | | - * | | - * | | - * | | - * |--------------------------------| - * | Monitor .Text / .DATA / .BSS | * 256kb - * | Relocated! | * - * |--------------------------------| - * | Monitor Malloc | * 128kb (contains relocated environment) - * |--------------------------------| - * | Monitor/kernel STACK | * 64kb - * |--------------------------------| - * | Page Table for MMU systems | * 2k - * |--------------------------------| - * | PROM Code accessed from Linux | * 6kb-128b - * |--------------------------------| - * | Global data (avail from kernel)| * 128b - * |--------------------------------| - * - */ - -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFC000000 for 64 MB - * 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB - */ -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x00800000 -#define CONFIG_ENV_SIZE 0x8000 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SIZE) - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ - -#ifdef ENABLE_FLASH_SUPPORT -/* For use with grsim FLASH emulation extension */ -#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -#undef CONFIG_FLASH_8BIT /* Flash is 32-bit */ - -/*** CFI CONFIG ***/ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#endif - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_NOWHERE 1 -/*#define CONFIG_ENV_IS_IN_FLASH*/ -/*#define CONFIG_ENV_SIZE 0x8000*/ -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_SDRAM_BASE 0x60000000 -#define CONFIG_SYS_SDRAM_SIZE 0x02000000 /* 32MiB SDRAM */ -#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE) - -#define CONFIG_SYS_SRAM_BASE 0x40000000 -#define CONFIG_SYS_SRAM_SIZE 0x00400000 /* 4MiB SRAM */ -#define CONFIG_SYS_SRAM_END (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE) - -/* Always Run U-Boot from SDRAM */ -#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE -#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32) -#define CONFIG_SYS_STACK_SIZE (0x10000-32) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE) -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN) - -/* relocated monitor area */ -#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE -#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN) - -/* make un relocated address from relocated address */ -#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE)) - -#ifdef CONFIG_CMD_NET -/* - * Ethernet configuration - */ -#define CONFIG_GRETH 1 - -/* - * Define CONFIG_GRETH_10MBIT to force GRETH at 10Mb/s - */ -/* #define CONFIG_GRETH_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -#endif /* CONFIG_CMD_NET */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/***** Gaisler GRLIB IP-Cores Config ********/ - -#define CONFIG_SYS_GRLIB_SDRAM 0 - -#define CONFIG_SYS_GRLIB_MEMCFG1 (0x000000ff | (1<<11)) - -/* No SDRAM Configuration */ -#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1 - -/* LEON2 MCTRL configuration */ -#define CONFIG_SYS_GRLIB_ESA_MCTRL1 -#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x000000ff | (1<<11)) -#if CONFIG_GRSIM -/* GRSIM configuration */ -#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x82206000 -#else -/* TSIM configuration */ -#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x81805220 -#endif -#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00136000 - -/* GRLIB FT-MCTRL configuration */ -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1 -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x000000ff | (1<<11)) -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x82206000 -#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00136000 - -/* no DDR controller */ -#undef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1 - -/* no DDR2 Controller */ -#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1 - -/* default kernel command line */ -#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0" - -/* TSIM command: - * $ ./tsim-leon3 -mmu -cas - * - * This TSIM evaluation version will expire 2015-04-02 - * - * - * TSIM/LEON3 SPARC simulator, version 2.0.35 (evaluation version) - * - * Copyright (C) 2014, Aeroflex Gaisler - all rights reserved. - * This software may only be used with a valid license. - * For latest updates, go to http://www.gaisler.com/ - * Comments or bug-reports to support@gaisler.com - * - * serial port A on stdin/stdout - * allocated 4096 K SRAM memory, in 1 bank - * allocated 32 M SDRAM memory, in 1 bank - * allocated 2048 K ROM memory - * icache: 1 * 4 kbytes, 16 bytes/line (4 kbytes total) - * dcache: 1 * 4 kbytes, 16 bytes/line (4 kbytes total) - * tsim> leon - * 0x80000000 Memory configuration register 1 0x000002ff - * 0x80000004 Memory configuration register 2 0x81805220 - * 0x80000008 Memory configuration register 3 0x00000000 - */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h deleted file mode 100644 index ea9e3e8..0000000 --- a/include/configs/grsim_leon2.h +++ /dev/null @@ -1,283 +0,0 @@ -/* Configuration header file for LEON2 GRSIM. - * - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007, 2015 - * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H__ -#define __CONFIG_H__ - -/* - * High Level Configuration Options - * (easy to change) - * - * Select between TSIM or GRSIM by setting CONFIG_GRSIM or CONFIG_TSIM to 1. - * - * TSIM command - * tsim-leon -sdram 0 -ram 32000 -rom 8192 -mmu - * - */ - -#define CONFIG_GRSIM 0 /* ... not running on GRSIM */ -#define CONFIG_TSIM 1 /* ... running on TSIM */ - -/* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ - -/* - * Serial console configuration - */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* Partitions */ - -/* - * Supported commands - */ -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_REGINFO - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/export/roofs\0" \ - "scratch=40000000\0" \ - "getkernel=tftpboot $(scratch) $(bootfile)\0" \ - "bootargs=console=ttyS0,38400" \ - "" -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.81 -#define CONFIG_IPADDR 192.168.0.80 -#define CONFIG_ROOTPATH "/export/rootfs" -#define CONFIG_HOSTNAME grxc3s1500 -#define CONFIG_BOOTFILE "/uImage" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* Memory MAP - * - * Flash: - * |--------------------------------| - * | 0x00000000 Text & Data & BSS | * - * | for Monitor | * - * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| * - * | UNUSED / Growth | * 256kb - * |--------------------------------| - * | 0x00050000 Base custom area | * - * | kernel / FS | * - * | | * Rest of Flash - * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| - * | END-0x00008000 Environment | * 32kb - * |--------------------------------| - * - * - * - * Main Memory: - * |--------------------------------| - * | UNUSED / scratch area | - * | | - * | | - * | | - * | | - * |--------------------------------| - * | Monitor .Text / .DATA / .BSS | * 256kb - * | Relocated! | * - * |--------------------------------| - * | Monitor Malloc | * 128kb (contains relocated environment) - * |--------------------------------| - * | Monitor/kernel STACK | * 64kb - * |--------------------------------| - * | Page Table for MMU systems | * 2k - * |--------------------------------| - * | PROM Code accessed from Linux | * 6kb-128b - * |--------------------------------| - * | Global data (avail from kernel)| * 128b - * |--------------------------------| - * - */ - -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFC000000 for 64 MB - * 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB - */ -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x00800000 -#define CONFIG_ENV_SIZE 0x8000 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SIZE) - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ - -#ifdef ENABLE_FLASH_SUPPORT -/* For use with grsim FLASH emulation extension */ -#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -#undef CONFIG_FLASH_8BIT /* Flash is 32-bit */ - -/*** CFI CONFIG ***/ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#endif - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_NOWHERE 1 -/*#define CONFIG_ENV_IS_IN_FLASH*/ -/*#define CONFIG_ENV_SIZE 0x8000*/ -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 0x00800000 -#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE) - -/* no SRAM available */ -#undef CONFIG_SYS_SRAM_BASE -#undef CONFIG_SYS_SRAM_SIZE - -/* Always Run U-Boot from SDRAM */ -#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE -#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32) -#define CONFIG_SYS_STACK_SIZE (0x10000-32) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE) -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN) - -/* relocated monitor area */ -#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE -#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN) - -/* make un relocated address from relocated address */ -#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE)) - -/* - * Ethernet configuration - */ -/*#define CONFIG_GRETH 1*/ - -/* - * Define CONFIG_GRETH_10MBIT to force GRETH at 10Mb/s - */ -/* #define CONFIG_GRETH_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/***** Gaisler GRLIB IP-Cores Config ********/ - -#define CONFIG_SYS_GRLIB_SDRAM 0 -#define CONFIG_SYS_GRLIB_MEMCFG1 (0x000000ff | (1<<11)) -#if CONFIG_GRSIM -#define CONFIG_SYS_GRLIB_MEMCFG2 0x82206000 -#else -#define CONFIG_SYS_GRLIB_MEMCFG2 0x00001820 -#endif -#define CONFIG_SYS_GRLIB_MEMCFG3 0x00136000 - -/*** LEON2 UART 1 ***/ - -/* UART1 Define to 1 or 0 */ -#define LEON2_UART1_LOOPBACK_ENABLE 0 -#define LEON2_UART1_FLOWCTRL_ENABLE 0 -#define LEON2_UART1_PARITY_ENABLE 0 -#define LEON2_UART1_ODDPAR_ENABLE 0 - -/*** LEON2 UART 2 ***/ - -/* UART2 Define to 1 or 0 */ -#define LEON2_UART2_LOOPBACK_ENABLE 0 -#define LEON2_UART2_FLOWCTRL_ENABLE 0 -#define LEON2_UART2_PARITY_ENABLE 0 -#define LEON2_UART2_ODDPAR_ENABLE 0 - -#define LEON_CONSOLE_UART1 1 -#define LEON_CONSOLE_UART2 2 - -/* Use UART2 as console */ -#define LEON2_CONSOLE_SELECT LEON_CONSOLE_UART1 - -/* LEON2 I/O Port */ -/*#define LEON2_IO_PORT_DIR 0x0000aa00*/ - -/* default kernel command line */ -#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h deleted file mode 100644 index 4cd0f77..0000000 --- a/include/configs/ibf-dsp561.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * U-Boot - Configuration file for IBF-DSP561 board - */ - -#ifndef __CONFIG_IBF_DSP561__H__ -#define __CONFIG_IBF_DSP561__H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf561-0.5 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 24 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x377 -#define CONFIG_EBIU_SDGCTL_VAL 0x91998d -#define CONFIG_EBIU_SDBCTL_VAL 0x15 - -#define CONFIG_EBIU_AMGCTL_VAL 0x3F -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_DRIVER_AX88180 1 -#define AX88180_BASE 0x2c000000 -#define CONFIG_HOSTNAME ibf-dsp561 - -/* - * Flash Settings - */ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI_AMD_RESET -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ -/* The BF561-EZKIT uses a top boot flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x12000 /* Total Size of Environment Sector */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#else -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0 -#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1 - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index bb95dd8..175ddc4 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -130,8 +130,6 @@ #define CONFIG_SYS_MEMTEST_END 0x10010000 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 -#define CONFIG_STACKSIZE (128 * 1024) - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/ip04.h b/include/configs/ip04.h deleted file mode 100644 index 1531feb..0000000 --- a/include/configs/ip04.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * U-Boot - Configuration file for IP04 board (having BF532 processor) - * - * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com - * - * Copyright (c) 2005-2010 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __CONFIG_IP04_H__ -#define __CONFIG_IP04_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf532-0.5 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 10000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 40 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 3 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x408 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 -#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2 - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_HOSTNAME IP04 - -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_NO_SROM -#define CONFIG_DM9000_BASE 0x20100000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 2) - -/* - * Flash Settings - */ -#define CONFIG_ENV_OVERWRITE 1 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_PREBOOT "echo starting from spi flash" -#define CONFIG_ENV_OFFSET 0x30000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 - -/* - * NAND Settings - */ -#define CONFIG_NAND_PLAT -#define CONFIG_SYS_NAND_BASE 0x20000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_WRITE(addr, cmd) \ - do { \ - bfin_write8(addr, cmd); \ - SSYNC(); \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10 - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 - -#undef CONFIG_SHOW_BOOT_PROGRESS -/* Enable this if bootretry required; currently it's disabled */ -#define CONFIG_BOOT_RETRY_TIME -1 -#define CONFIG_BOOTCOMMAND "run nandboot" - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 777f225..3a7993e 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -10,6 +10,8 @@ #ifndef __CONFIG_K2E_EVM_H #define __CONFIG_K2E_EVM_H +#include <environment/ti/spi.h> + /* Platform type */ #define CONFIG_SOC_K2E @@ -30,6 +32,9 @@ /* SPL SPI Loader Configuration */ #define CONFIG_SPL_TEXT_BASE 0x0c100000 + +#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS + /* NAND Configuration */ #define CONFIG_SYS_NAND_PAGE_2K diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index bd25231..bee1be7 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -10,6 +10,9 @@ #ifndef __CONFIG_K2G_EVM_H #define __CONFIG_K2G_EVM_H +#include <environment/ti/mmc.h> +#include <environment/ti/spi.h> + /* Platform type */ #define CONFIG_SOC_K2G @@ -76,4 +79,5 @@ #define CONFIG_BOUNCE_BUFFER #endif +#define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS #endif /* __CONFIG_K2G_EVM_H */ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 4adb119..202167b 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -10,6 +10,8 @@ #ifndef __CONFIG_K2HK_EVM_H #define __CONFIG_K2HK_EVM_H +#include <environment/ti/spi.h> + /* Platform type */ #define CONFIG_SOC_K2HK @@ -30,6 +32,8 @@ /* SPL SPI Loader Configuration */ #define CONFIG_SPL_TEXT_BASE 0x0c200000 +#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS + /* NAND Configuration */ #define CONFIG_SYS_NAND_PAGE_2K diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 9bdd565..a7ccdd1 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -10,6 +10,8 @@ #ifndef __CONFIG_K2L_EVM_H #define __CONFIG_K2L_EVM_H +#include <environment/ti/spi.h> + /* Platform type */ #define CONFIG_SOC_K2L @@ -30,6 +32,8 @@ /* SPL SPI Loader Configuration */ #define CONFIG_SPL_TEXT_BASE 0x0c100000 +#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS + /* NAND Configuration */ #define CONFIG_SYS_NAND_PAGE_4K diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 2ce39ff..258fd3a 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -113,7 +113,6 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING -#define CONFIG_STACKSIZE SZ_128K /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index af07672..1a0c7f8 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -11,6 +11,7 @@ #define CONFIG_GICV2 #include <asm/arch/config.h> +#include <asm/arch/stream_id_lsch2.h> #define CONFIG_SUPPORT_RAW_INITRD diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index db29fa2b..d8bbc80 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -36,11 +36,6 @@ #define CONFIG_CMD_EXT2 #endif -/* - * Generic Timer Definitions - */ -#define GENERIC_TIMER_CLK 12500000 - #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 @@ -243,7 +238,7 @@ #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_TIMER_CLK_FREQ 12500000 +#define COUNTER_FREQUENCY 12500000 #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 @@ -274,12 +269,6 @@ #define CONFIG_LS102XA_STREAM_ID -/* - * Stack sizes - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (30 * 1024) - #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR \ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 4fb8b0c..b349b36 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -27,11 +27,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE -/* - * Generic Timer Definitions - */ -#define GENERIC_TIMER_CLK 12500000 - #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); @@ -500,7 +495,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_TIMER_CLK_FREQ 12500000 +#define COUNTER_FREQUENCY 12500000 #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 @@ -542,12 +537,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_LS102XA_STREAM_ID -/* - * Stack sizes - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (30 * 1024) - #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index c6438d5..fcf035b 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -56,11 +56,6 @@ #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif -/* - * Generic Timer Definitions - */ -#define GENERIC_TIMER_CLK 12500000 - #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 @@ -370,7 +365,7 @@ #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_TIMER_CLK_FREQ 12500000 +#define COUNTER_FREQUENCY 12500000 #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 @@ -408,12 +403,6 @@ #define CONFIG_LS102XA_STREAM_ID -/* - * Stack sizes - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (30 * 1024) - #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR \ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 5a5f951..46d54a0 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -13,6 +13,7 @@ #define CONFIG_MP #define CONFIG_GICV2 +#include <asm/arch/stream_id_lsch2.h> #include <asm/arch/config.h> /* Link Definitions */ @@ -187,12 +188,14 @@ #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ "5m(kernel),1m(dtb),9m(file_system)" #else -#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ - "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ - "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ - "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ - "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ - "40m(nor_bank4_fit);7e800000.flash:" \ +#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \ + "2m@0x100000(nor_bank0_uboot),"\ + "40m@0x1100000(nor_bank0_fit)," \ + "7m(nor_bank0_user)," \ + "2m@0x4100000(nor_bank4_uboot)," \ + "40m@0x5100000(nor_bank4_fit),"\ + "-(nor_bank4_user);" \ + "7e800000.flash:" \ "1m(nand_uboot),1m(nand_uboot_env)," \ "20m(nand_fit);spi0.0:1m(uboot)," \ "5m(kernel),1m(dtb),9m(file_system)" diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 6a345c0..b14e944 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -396,12 +396,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_HZ 1000 -/* - * Stack sizes - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (30 * 1024) - #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 1ed7517..cb79296 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -13,6 +13,7 @@ #define CONFIG_GICV2 #include <asm/arch/config.h> +#include <asm/arch/stream_id_lsch2.h> /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 4b3b21e..0cf6010 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -434,12 +434,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_HZ 1000 -/* - * Stack sizes - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (30 * 1024) - #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) @@ -485,12 +479,14 @@ unsigned long get_board_ddr_clk(void); #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \ "14m(free)" #else -#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ - "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ - "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ - "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ - "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ - "40m(nor_bank4_fit);7e800000.flash:" \ +#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \ + "2m@0x100000(nor_bank0_uboot),"\ + "40m@0x1100000(nor_bank0_fit)," \ + "7m(nor_bank0_user)," \ + "2m@0x4100000(nor_bank4_uboot)," \ + "40m@0x5100000(nor_bank4_fit),"\ + "-(nor_bank4_user);" \ + "7e800000.flash:" \ "4m(nand_uboot),36m(nand_kernel)," \ "472m(nand_free);spi0.0:2m(uboot)," \ "14m(free)" diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 5072e20..427f623 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -13,7 +13,7 @@ #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 -#include <asm/arch/ls2080a_stream_id.h> +#include <asm/arch/stream_id_lsch3.h> #include <asm/arch/config.h> /* Link Definitions */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 08d1586..beacb99 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -368,6 +368,7 @@ unsigned long get_board_ddr_clk(void); "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ + "mcmemsize=0x40000000\0" \ "mcinitcmd=esbc_validate 0x580c80000;" \ "esbc_validate 0x580cc0000;" \ "fsl_mc start mc 0x580300000" \ @@ -384,6 +385,7 @@ unsigned long get_board_ddr_clk(void); "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ + "mcmemsize=0x40000000\0" \ "mcinitcmd=fsl_mc start mc 0x580300000" \ " 0x580800000 \0" #endif /* CONFIG_SECURE_BOOT */ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 408140f..2155a89 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -339,6 +339,7 @@ unsigned long get_board_sys_clk(void); "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ + "mcmemsize=0x40000000\0" \ "fdtfile=fsl-ls2080a-rdb.dtb\0" \ "mcinitcmd=esbc_validate 0x580c80000;" \ "esbc_validate 0x580cc0000;" \ @@ -362,6 +363,7 @@ unsigned long get_board_sys_clk(void); "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ + "mcmemsize=0x40000000\0" \ "fdtfile=fsl-ls2080a-rdb.dtb\0" \ "mcinitcmd=fsl_mc start mc 0x580300000" \ " 0x580800000 \0" \ diff --git a/include/configs/miqi_rk3288.h b/include/configs/miqi_rk3288.h new file mode 100644 index 0000000..f686042 --- /dev/null +++ b/include/configs/miqi_rk3288.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3288_common.h> + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_SYS_WHITE_ON_BLACK + +#endif diff --git a/include/configs/mvebu_db-88f3720.h b/include/configs/mvebu_armada-37xx.h index 6bb78e0..5408490 100644 --- a/include/configs/mvebu_db-88f3720.h +++ b/include/configs/mvebu_armada-37xx.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _CONFIG_MVEBU_DB_88F3720_H -#define _CONFIG_MVEBU_DB_88F3720_H +#ifndef _CONFIG_MVEBU_ARMADA_37XX_H +#define _CONFIG_MVEBU_ARMADA_37XX_H /* * High Level Configuration Options (easy to change) @@ -92,6 +92,7 @@ #define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ #define CONFIG_ARP_TIMEOUT 200 #define CONFIG_NET_RETRY_COUNT 50 +#define CONFIG_PHY_MARVELL /* USB 2.0 */ #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 @@ -126,4 +127,4 @@ #define CONFIG_SUPPORT_VFAT -#endif /* _CONFIG_MVEBU_DB_88F3720_H */ +#endif /* _CONFIG_MVEBU_ARMADA_37XX_H */ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index a8a9d15..8ee5f27 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -81,6 +81,14 @@ #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ +/* + * Ethernet Driver configuration + */ +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ +#define CONFIG_ARP_TIMEOUT 200 +#define CONFIG_NET_RETRY_COUNT 50 + /* USB 2.0 */ #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index a2ab77a..c04ae96 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -180,8 +180,6 @@ #define CONFIG_SYS_MEMTEST_END 0x10010000 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 -#define CONFIG_STACKSIZE (128 * 1024) - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index f5af65d..2fff799 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -120,8 +120,6 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M) -#define CONFIG_STACKSIZE SZ_128K - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 8215e63..62159a1 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -113,8 +113,6 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M) -#define CONFIG_STACKSIZE SZ_128K - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 0742b4b..971f6c2 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -95,8 +95,6 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) -#define CONFIG_STACKSIZE SZ_128K - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -182,7 +180,4 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/ #endif -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } - #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index aff7a24..e63da43 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -123,8 +123,6 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) -#define CONFIG_STACKSIZE SZ_128K - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 71c22ff..f466c62 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -150,7 +150,6 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING -#define CONFIG_STACKSIZE SZ_128K /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index c65a9e5..5bc26aa 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -137,8 +137,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 -#define CONFIG_STACKSIZE SZ_128K - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 5bf8ad7..e2b05ca 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -21,7 +21,7 @@ #define CONFIG_MXC_GPT_HCLK #define CONFIG_SYSCOUNTER_TIMER #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ -#define CONFIG_TIMER_CLK_FREQ CONFIG_SC_TIMER_CLK +#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK #define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_BOOTM_LEN 0x1000000 diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 81d769f..9807ace 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -178,8 +178,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 -#define CONFIG_STACKSIZE SZ_128K - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index f6e4b3b..37f365d 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -88,7 +88,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_CMDLINE_EDITING -#define CONFIG_STACKSIZE SZ_8K /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 6b128df..e99968c 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -48,7 +48,6 @@ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R #define CONFIG_SKIP_LOWLEVEL_INIT /* X-Loader set everything up */ @@ -381,13 +380,6 @@ int rx51_kp_getc(struct stdio_dev *sdev); #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ - -/* * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 diff --git a/include/configs/nsim.h b/include/configs/nsim.h index 0cc55b7..d6d26c7 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -10,11 +10,6 @@ #include <linux/sizes.h> /* - * CPU configuration - */ -#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ - -/* * Memory configuration */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 6700073..9d90e46 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -48,7 +48,6 @@ #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define CONFIG_STACKSIZE (256*1024) /* regular stack */ #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ @@ -261,30 +260,27 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_REVISION_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS "console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off" #define CONFIG_BOOTCOMMAND \ - "if mmc rescan; then " \ - "run mmcboot; " \ - "else " \ - "run spiboot; " \ - "fi" -#define CONFIG_EXTRA_ENV_SETTINGS \ + "run envboot; " \ + "run mmcboot; " + +#define DEFAULT_LINUX_BOOT_ENV \ + "loadaddr=0xc0700000\0" \ "fdtaddr=0xc0600000\0" \ + "scriptaddr=0xc0600000\0" + +#include <environment/ti/mmc.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ "fdtfile=da850-lcdk.dtb\0" \ - "fdtboot=bootz 0xc0700000 - ${fdtaddr};\0" \ - "mmcboot=" \ - "if fatload mmc 0 0xc0600000 boot.scr; then " \ - "source 0xc0600000; " \ - "else " \ - "fatload mmc 0 0xc0700000 " \ - __stringify(CONFIG_BOOTFILE) "; " \ - "fatload mmc 0 ${fdtaddr} ${fdtfile}; " \ - "run fdtboot; " \ - "fi;\0" \ - "spiboot=" \ - "sf probe 0; " \ - "sf read 0xc0700000 0x80000 0x220000; " \ - "bootz 0xc0700000;\0" + "boot_fdt=yes\0" \ + "boot_fit=0\0" \ + "console=ttyS2,115200n8\0" /* * U-Boot commands diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h deleted file mode 100644 index 549b33c..0000000 --- a/include/configs/openrisc-generic.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2011, Stefan Kristiansson, stefan.kristianssons@saunalahti.fi - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * BOARD/CPU - */ -#define CONFIG_SYS_CLK_FREQ 50000000 -#define CONFIG_SYS_RESET_ADDR 0x00000100 - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 0x02000000 - -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define CONFIG_SYS_UART_BASE 0x90000000 -#define CONFIG_SYS_UART_FREQ CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_UART_BAUD 115200 - -#define CONFIG_BOARD_NAME "OpenRISC Generic" - -#define CONFIG_SYS_MAX_FLASH_SECT 0 - -/* - * SERIAL - */ -# define CONFIG_SYS_NS16550_SERIAL -# define CONFIG_SYS_NS16550_REG_SIZE 1 -# define CONFIG_CONS_INDEX 1 -# define CONFIG_SYS_NS16550_COM1 (0x90000000) -# define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ - -#define CONFIG_SYS_BAUDRATE_TABLE {CONFIG_BAUDRATE} -#define CONSOLE_ARG "console=console=ttyS0,115200\0" - -/* - * Ethernet - */ -#define CONFIG_SYS_ETHOC_BASE 0x92000000 - -#define CONFIG_BOOTFILE "boot.img" -#define CONFIG_LOADADDR 0x100000 /* 1MB mark */ - -/* - * TIMER - */ -#define CONFIG_SYS_OPENRISC_TMR_HZ 100 - -/* - * Memory organisation: - * - * RAM start --------------------------- - * | ... | - * --------------------------- - * | Stack | - * --------------------------- - * | Global data | - * --------------------------- - * | Environment | - * --------------------------- - * | Monitor | - * RAM end --------------------------- - */ -/* We're running in RAM */ -#define CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_SDRAM_SIZE - \ - CONFIG_SYS_MONITOR_LEN) - -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment, 128KB */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) - -/* - * Global data object and stack pointer - */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_ENV_ADDR \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_GBL_DATA_ADDR CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_STACK_LENGTH 0x10000 /* 64KB */ -#define CONFIG_SYS_MALLOC_LEN 0x400000 /* 4MB */ -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_INIT_SP_OFFSET \ - - CONFIG_SYS_STACK_LENGTH \ - - CONFIG_SYS_MALLOC_LEN) -/* - * MISC - */ -#define CONFIG_SYS_LONGHELP /* Provide extended help */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ -#define CONFIG_SYS_MAXARGS 16 /* Max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + \ - 16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x2000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP_ADDR - 0x20000) -#define CONFIG_CMDLINE_EDITING - -/* - * Command line configuration. - */ -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_BSP - -#define CONFIG_LMB - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -#endif /* __CONFIG_H */ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 286598d..f506c9c 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -226,12 +226,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* - * Stack sizes - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ - /* Physical memory map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM (0x80000000) diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index dacb78a..9042dc2 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -37,7 +37,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x88000000 #define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN (4 << 10) -#define CONFIG_STACKSIZE (4 << 10) /* regular stack */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (192 << 10) diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 8ad7fa6..26b1b11 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -117,7 +117,6 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING -#define CONFIG_STACKSIZE SZ_128K /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/popmetal_rk3288.h b/include/configs/popmetal_rk3288.h index 6a068bb..bbd54a1 100644 --- a/include/configs/popmetal_rk3288.h +++ b/include/configs/popmetal_rk3288.h @@ -11,7 +11,7 @@ #include <configs/rk3288_common.h> #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_WHITE_ON_BLACK diff --git a/include/configs/pr1.h b/include/configs/pr1.h deleted file mode 100644 index d3fba0d..0000000 --- a/include/configs/pr1.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * U-Boot - Configuration file for PR1 Appliance - * - * based on bf537-stamp.h - * Copyright (c) Switchfin Org. <dpn@switchfin.org> - */ - -#ifndef __CONFIG_PR1_H__ -#define __CONFIG_PR1_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 24 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 11 -#define CONFIG_MEM_SIZE 128 - -#define CONFIG_EBIU_SDRRC_VAL 0x306 -#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_NETCONSOLE -#endif -#define CONFIG_HOSTNAME pr1 -#define CONFIG_TFTP_BLOCKSIZE 4404 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * NAND Settings - */ -#define CONFIG_NAND_PLAT -#define CONFIG_SYS_NAND_BASE 0x20000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_WRITE(addr, cmd) \ - do { \ - bfin_write8(addr, cmd); \ - SSYNC(); \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_GPIO_DEV_READY GPIO_PF9 - -/* - * Misc Settings - */ -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run nandboot" -#define CONFIG_LOADADDR 0x2000000 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -/* - * Overwrite some settings defined in bfin_adi_common.h - */ -#undef NAND_ENV_SETTINGS -#define NAND_ENV_SETTINGS \ - "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \ - "nandboot=" \ - "nand read $(loadaddr) 0x0 0x900000;" \ - "run nandargs;" \ - "bootm" \ - "\0" - -#endif diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index d7e96ec..c5e508e 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -18,7 +18,6 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) #define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */ diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 4ba81ac..9d22e0c 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -17,17 +17,17 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_DRIVERS_MISC_SUPPORT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#define COUNTER_FREQUENCY 24000000 + #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_TEXT_BASE 0x00200000 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff8effff -#define CONFIG_SPL_TEXT_BASE 0xff8c2008 +#define CONFIG_SPL_TEXT_BASE 0xff8c2000 #define CONFIG_SPL_MAX_SIZE 0x30000 /* BSS setup */ #define CONFIG_SPL_BSS_START_ADDR 0xff8e0000 @@ -52,8 +52,6 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SPI_FLASH -#define CONFIG_SPI #define CONFIG_SF_DEFAULT_SPEED 20000000 #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/rock.h b/include/configs/rock.h new file mode 100644 index 0000000..de5291c --- /dev/null +++ b/include/configs/rock.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include <configs/rk3188_common.h> + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +/* SPL @ 32k for 34k + * u-boot directly after @ 68k for 400k or so + * ENV @ 992k + */ +#define CONFIG_ENV_OFFSET ((1024-32) * 1024) +#else +/* SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) +#endif + +#endif diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h index 0b12bf3..398b3aa 100644 --- a/include/configs/s32v234evb.h +++ b/include/configs/s32v234evb.h @@ -199,12 +199,6 @@ #define CONFIG_SYS_MALLOC_BASE (DDR_BASE_ADDR) #endif -/* - * Stack sizes - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ - #if 0 /* Configure PXE */ #define CONFIG_BOOTP_PXE diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 6b3cd18..4c112cc 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -25,12 +25,6 @@ #define CONFIG_SYS_TIMER_RATE 1000000 #endif -/* - * Number of bits in a C 'long' on this architecture. Set this to 32 when - * building on a 32-bit machine. - */ -#define CONFIG_SANDBOX_BITS_PER_LONG 64 - #define CONFIG_LMB #define CONFIG_ANDROID_BOOT_IMAGE @@ -199,4 +193,6 @@ #define CONFIG_SYS_SYSTEMACE_WIDTH 16 #define CONFIG_SYS_SYSTEMACE_BASE 0 +#define CONFIG_MISC_INIT_F + #endif diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 5a9ec02..d69f513 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -228,9 +228,6 @@ # define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ #endif /* SPI support */ -/* Unsupported features */ -#undef CONFIG_USE_IRQ - #define CONFIG_DRIVER_TI_CPSW #define CONFIG_MII #define CONFIG_PHY_GIGE diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index a456e45..8609f2a 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -66,8 +66,6 @@ #define CONFIG_SYS_MALLOC_LEN (2 << 20) -#define CONFIG_STACKSIZE (64 << 10) - #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 55280f2..de3d661 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -12,9 +12,6 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x20050000 #define CONFIG_SYS_TEXT_BASE 0x08000000 -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF - /* * Configuration of the external SDRAM memory */ @@ -58,7 +55,6 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_STACKSIZE (256 * 1024) #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" @@ -79,4 +75,5 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_CMD_MEM +#define CONFIG_CMD_CACHE #endif /* __CONFIG_H */ diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h index 3e5708b..1b7bfb6 100644 --- a/include/configs/sun50i.h +++ b/include/configs/sun50i.h @@ -18,7 +18,6 @@ #define CONFIG_SUNXI_USB_PHYS 1 -#define COUNTER_FREQUENCY CONFIG_TIMER_CLK_FREQ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 05ea172..1d475b1 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -46,7 +46,7 @@ #endif /* CPU */ -#define CONFIG_TIMER_CLK_FREQ 24000000 +#define COUNTER_FREQUENCY 24000000 /* * The DRAM Base differs between some models. We cannot use macros for the @@ -79,7 +79,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ -#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I) +#ifdef CONFIG_SUNXI_HIGH_SRAM /* * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is * slightly bigger. Note that it is possible to map the first 32 KiB of the @@ -125,6 +125,9 @@ #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_MAX_NAND_DEVICE 8 + +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS #endif #ifdef CONFIG_SPL_SPI_SUNXI @@ -134,9 +137,13 @@ /* mmc config */ #ifdef CONFIG_MMC #define CONFIG_MMC_SUNXI_SLOT 0 -#define CONFIG_ENV_IS_IN_MMC +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ #define CONFIG_SYS_MMC_MAX_DEVICE 4 +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE (128 << 10) #endif /* 64MB of malloc() pool */ @@ -155,18 +162,10 @@ /* standalone support */ #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR -/* baudrate */ - -/* The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ - /* FLASH and environment organization */ #define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */ -#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - #define CONFIG_FAT_WRITE /* enable write access */ #define CONFIG_SPL_FRAMEWORK @@ -175,32 +174,24 @@ #define CONFIG_SPL_BOARD_LOAD_IMAGE #endif -#if defined(CONFIG_MACH_SUN9I) +#ifdef CONFIG_SUNXI_HIGH_SRAM #define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */ -#define CONFIG_SPL_MAX_SIZE 0x5fc0 /* ? KiB on sun9i */ -#elif defined(CONFIG_MACH_SUN50I) -#define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */ -#define CONFIG_SPL_MAX_SIZE 0x7fc0 /* 32 KiB on sun50i */ +#define CONFIG_SPL_MAX_SIZE 0x7fc0 /* 32 KiB */ +#define LOW_LEVEL_SRAM_STACK 0x00018000 #else #define CONFIG_SPL_TEXT_BASE 0x40 /* sram start+header */ #define CONFIG_SPL_MAX_SIZE 0x5fc0 /* 24KB on sun4i/sun7i */ +#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ #endif +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + #ifndef CONFIG_ARM64 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" #endif #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ -#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I) -/* FIXME: 40 KiB instead of 32 KiB ? */ -#define LOW_LEVEL_SRAM_STACK 0x00018000 -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK -#else -/* end of 32 KiB in sram */ -#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK -#endif /* I2C */ #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ @@ -338,13 +329,6 @@ extern int soft_i2c_gpio_scl; #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE #endif -#if !defined CONFIG_ENV_IS_IN_MMC && \ - !defined CONFIG_ENV_IS_IN_NAND && \ - !defined CONFIG_ENV_IS_IN_FAT && \ - !defined CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_IS_NOWHERE -#endif - #define CONFIG_MISC_INIT_R #ifndef CONFIG_SPL_BUILD @@ -474,6 +458,20 @@ extern int soft_i2c_gpio_scl; "stderr=serial\0" #endif +#ifdef CONFIG_MTDIDS_DEFAULT +#define SUNXI_MTDIDS_DEFAULT \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" +#else +#define SUNXI_MTDIDS_DEFAULT +#endif + +#ifdef CONFIG_MTDPARTS_DEFAULT +#define SUNXI_MTDPARTS_DEFAULT \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" +#else +#define SUNXI_MTDPARTS_DEFAULT +#endif + #define CONSOLE_ENV_SETTINGS \ CONSOLE_STDIN_SETTINGS \ CONSOLE_STDOUT_SETTINGS @@ -484,6 +482,8 @@ extern int soft_i2c_gpio_scl; DFU_ALT_INFO_RAM \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "console=ttyS0,115200\0" \ + SUNXI_MTDIDS_DEFAULT \ + SUNXI_MTDPARTS_DEFAULT \ BOOTCMD_SUNXI_COMPAT \ BOOTENV diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 035a932..3f2da57 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -196,13 +196,6 @@ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ - -/* * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ diff --git a/include/configs/tb100.h b/include/configs/tb100.h index b719943..115b3b3 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -10,11 +10,6 @@ #include <linux/sizes.h> /* - * CPU configuration - */ -#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ - -/* * Memory configuration */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h deleted file mode 100644 index 7924c8e..0000000 --- a/include/configs/tcm-bf518.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * U-Boot - Configuration file for Bluetechnix TCM-BF518 board - */ - -#ifndef __CONFIG_TCM_BF518_H__ -#define __CONFIG_TCM_BF518_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf518-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 16 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* - * Memory Settings - */ -/* This board has a 32meg MT48H16M16 */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL 0x3f8 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) - -/* - * Network Settings - */ -#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__) -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME tcm-bf518 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 19 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x8000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Misc Settings - */ -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h deleted file mode 100644 index f9d9f84..0000000 --- a/include/configs/tcm-bf537.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * U-Boot - Configuration file for TCM-BF537 board - */ - -#ifndef __CONFIG_TCM_BF537_H__ -#define __CONFIG_TCM_BF537_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 21 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* Decrease core voltage */ -#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL 0x3f8 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE 0x20308000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME tcm-bf537 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 67 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_SECT_SIZE 0x8000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#endif -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * SPI_MMC Settings - */ -#define CONFIG_MMC_SPI - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS \ - "flashboot=flread 20040000 1000000 300000;" \ - "bootm 0x1000000\0" -#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024)) - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 319279e..baf818b 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -179,9 +179,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif -/* Unsupported features */ -#undef CONFIG_USE_IRQ - /* Ethernet */ #define CONFIG_DRIVER_TI_CPSW #define CONFIG_MII diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 2840467..b5af700 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -137,7 +137,4 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif -/* Unsupported features */ -#undef CONFIG_USE_IRQ - #endif diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index a4ec4ce..1561d54 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -51,74 +51,12 @@ "bootm_size=0x10000000\0" \ "boot_fdt=try\0" -#define DEFAULT_MMC_TI_ARGS \ - "mmcdev=0\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "finduuid=part uuid mmc ${bootpart} uuid\0" \ - "args_mmc=run finduuid;setenv bootargs console=${console} " \ - "${optargs} " \ - "root=PARTUUID=${uuid} rw " \ - "rootfstype=${mmcrootfstype}\0" \ - "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ - "source ${loadaddr}\0" \ - "bootenvfile=uEnv.txt\0" \ - "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \ - "loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "envboot=mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootscript; then " \ - "run bootscript;" \ - "else " \ - "if run loadbootenv; then " \ - "echo Loaded env from ${bootenvfile};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "fi;" \ - "fi;\0" \ - "mmcloados=run args_mmc; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdtaddr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "mmcboot=mmc dev ${mmcdev}; " \ - "setenv devnum ${mmcdev}; " \ - "setenv devtype mmc; " \ - "if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadimage; then " \ - "if test ${boot_fit} -eq 1; then " \ - "run loadfit; " \ - "else " \ - "run mmcloados;" \ - "fi;" \ - "fi;" \ - "fi;\0" \ - #define DEFAULT_FIT_TI_ARGS \ "boot_fit=0\0" \ "fit_loadaddr=0x88000000\0" \ - "fit_bootfile=fitImage.itb\0" \ + "fit_bootfile=fitImage\0" \ "update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}\0" \ - "args_fit=setenv bootargs console=${console} \0" \ - "loadfit=run args_fit; bootm ${loadaddr}#${fdtfile};\0" \ + "loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};\0" \ /* * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 5d4ef58..5d2a7ab 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -28,7 +28,6 @@ #define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ -#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \ GENERATED_GBL_DATA_SIZE) @@ -55,6 +54,13 @@ #define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO +/* SRAM scratch space entries */ +#define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8 + +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR) +#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) +#define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) + /* UART Configuration */ #define CONFIG_SYS_NS16550_MEM32 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) @@ -213,6 +219,10 @@ /* EDMA3 */ #define CONFIG_TI_EDMA3 +#define KERNEL_MTD_PARTS \ + "mtdparts=" \ + SPI_MTD_PARTS + #define DEFAULT_FW_INITRAMFS_BOOT_ENV \ "name_fw_rd=k2-fw-initrd.cpio.gz\0" \ "set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0" \ @@ -269,7 +279,8 @@ "sf write ${loadaddr} 0 ${filesize}\0" \ "burn_uboot_nand=nand erase 0 0x100000; " \ "nand write ${loadaddr} 0 ${filesize}\0" \ - "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ + "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1 " \ + KERNEL_MTD_PARTS \ "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ "${nfs_options} ip=dhcp\0" \ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index d07cb9f..b85db50 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -104,6 +104,7 @@ "run distro_bootcmd" #include <config_distro_bootcmd.h> +#include <environment/ti/mmc.h> #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 7fb1bb6..d45baab 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -42,7 +42,7 @@ * Hardware drivers */ #define CONFIG_SYS_NS16550_CLK 48000000 -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) +#if !defined(CONFIG_DM_SERIAL) #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #endif @@ -58,6 +58,8 @@ #define DFUARGS #endif +#include <environment/ti/mmc.h> + #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ @@ -160,14 +162,8 @@ #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ #endif -/* - * Disable MMC DM for SPL build and can be re-enabled after adding - * DM support in SPL - */ #ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_MMC #undef CONFIG_TIMER -#undef CONFIG_DM_ETH #endif #endif /* __CONFIG_TI_OMAP5_COMMON_H */ diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h index c398e07..5228528 100644 --- a/include/configs/tinker_rk3288.h +++ b/include/configs/tinker_rk3288.h @@ -16,7 +16,7 @@ func(MMC, mmc, 1) #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SYS_WHITE_ON_BLACK diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index e72332c..1bfc438 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -349,8 +349,6 @@ "panicboot=echo No boot device !!! reset\0" \ TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ -#define CONFIG_STACKSIZE (128u * SZ_1K) - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 1d737cc..c6f39c3 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -69,7 +69,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) -#define CONFIG_STACKSIZE SZ_128K /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index ee90045..3e7dc9b 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -209,12 +209,6 @@ #define CONFIG_SYS_MEMTEST_START 0x80010000 #define CONFIG_SYS_MEMTEST_END 0x87C00000 -/* - * Stack sizes - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ - /* Physical memory map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM (0x80000000) diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index ade5c27..9a517a9 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -33,8 +33,6 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) -#define CONFIG_STACKSIZE SZ_128K - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/warp.h b/include/configs/warp.h index 865f2ac..5274b27 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -35,8 +35,6 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_256M) -#define CONFIG_STACKSIZE SZ_128K - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/warp7.h b/include/configs/warp7.h index b3e1f2e..23b6eae 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -85,8 +85,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 -#define CONFIG_STACKSIZE SZ_128K - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 3f837e8..f546c38 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -119,13 +119,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ - -/* * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index f7796cf..d69e609 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -16,7 +16,6 @@ * (easy to change) */ #define CONFIG_SHOW_BOOT_PROGRESS -#define CONFIG_ZBOOT_32 #define CONFIG_PHYSMEM #define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_LAST_STAGE_INIT diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 5169504..b1aa579 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -66,7 +66,6 @@ # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ #endif -#define CONFIG_SYS_STACKSIZE (512 << 10) /* stack 512KB */ #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */ /* Linux boot param area in RAM (used only when booting linux) */ @@ -110,7 +109,6 @@ /* U-Boot general configuration */ /*==============================*/ -#undef CONFIG_USE_IRQ /* Keep it simple, poll only */ #define CONFIG_BOARD_POSTCLK_INIT #define CONFIG_MISC_INIT_R diff --git a/include/debug_uart.h b/include/debug_uart.h index 0d640b9..2980ae6 100644 --- a/include/debug_uart.h +++ b/include/debug_uart.h @@ -115,17 +115,23 @@ void printhex8(uint value); * Now define some functions - this should be inserted into the serial driver */ #define DEBUG_UART_FUNCS \ - void printch(int ch) \ +\ + static inline void _printch(int ch) \ { \ if (ch == '\n') \ _debug_uart_putc('\r'); \ _debug_uart_putc(ch); \ } \ \ + void printch(int ch) \ + { \ + _printch(ch); \ + } \ +\ void printascii(const char *str) \ { \ while (*str) \ - printch(*str++); \ + _printch(*str++); \ } \ \ static inline void printhex1(uint digit) \ diff --git a/include/div64.h b/include/div64.h index d833144..cecb232 100644 --- a/include/div64.h +++ b/include/div64.h @@ -4,13 +4,16 @@ * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com> * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h * + * Optimization for constant divisors on 32-bit machines: + * Copyright (C) 2006-2015 Nicolas Pitre + * * The semantics of do_div() are: * * uint32_t do_div(uint64_t *n, uint32_t base) * { - * uint32_t remainder = *n % base; - * *n = *n / base; - * return remainder; + * uint32_t remainder = *n % base; + * *n = *n / base; + * return remainder; * } * * NOTE: macro parameter n is evaluated multiple times, @@ -18,8 +21,182 @@ */ #include <linux/types.h> +#include <linux/compiler.h> + +#if BITS_PER_LONG == 64 + +# define do_div(n,base) ({ \ + uint32_t __base = (base); \ + uint32_t __rem; \ + __rem = ((uint64_t)(n)) % __base; \ + (n) = ((uint64_t)(n)) / __base; \ + __rem; \ + }) + +#elif BITS_PER_LONG == 32 + +#include <linux/log2.h> + +/* + * If the divisor happens to be constant, we determine the appropriate + * inverse at compile time to turn the division into a few inline + * multiplications which ought to be much faster. And yet only if compiling + * with a sufficiently recent gcc version to perform proper 64-bit constant + * propagation. + * + * (It is unfortunate that gcc doesn't perform all this internally.) + */ + +#ifndef __div64_const32_is_OK +#define __div64_const32_is_OK (__GNUC__ >= 4) +#endif + +#define __div64_const32(n, ___b) \ +({ \ + /* \ + * Multiplication by reciprocal of b: n / b = n * (p / b) / p \ + * \ + * We rely on the fact that most of this code gets optimized \ + * away at compile time due to constant propagation and only \ + * a few multiplication instructions should remain. \ + * Hence this monstrous macro (static inline doesn't always \ + * do the trick here). \ + */ \ + uint64_t ___res, ___x, ___t, ___m, ___n = (n); \ + uint32_t ___p, ___bias; \ + \ + /* determine MSB of b */ \ + ___p = 1 << ilog2(___b); \ + \ + /* compute m = ((p << 64) + b - 1) / b */ \ + ___m = (~0ULL / ___b) * ___p; \ + ___m += (((~0ULL % ___b + 1) * ___p) + ___b - 1) / ___b; \ + \ + /* one less than the dividend with highest result */ \ + ___x = ~0ULL / ___b * ___b - 1; \ + \ + /* test our ___m with res = m * x / (p << 64) */ \ + ___res = ((___m & 0xffffffff) * (___x & 0xffffffff)) >> 32; \ + ___t = ___res += (___m & 0xffffffff) * (___x >> 32); \ + ___res += (___x & 0xffffffff) * (___m >> 32); \ + ___t = (___res < ___t) ? (1ULL << 32) : 0; \ + ___res = (___res >> 32) + ___t; \ + ___res += (___m >> 32) * (___x >> 32); \ + ___res /= ___p; \ + \ + /* Now sanitize and optimize what we've got. */ \ + if (~0ULL % (___b / (___b & -___b)) == 0) { \ + /* special case, can be simplified to ... */ \ + ___n /= (___b & -___b); \ + ___m = ~0ULL / (___b / (___b & -___b)); \ + ___p = 1; \ + ___bias = 1; \ + } else if (___res != ___x / ___b) { \ + /* \ + * We can't get away without a bias to compensate \ + * for bit truncation errors. To avoid it we'd need an \ + * additional bit to represent m which would overflow \ + * a 64-bit variable. \ + * \ + * Instead we do m = p / b and n / b = (n * m + m) / p. \ + */ \ + ___bias = 1; \ + /* Compute m = (p << 64) / b */ \ + ___m = (~0ULL / ___b) * ___p; \ + ___m += ((~0ULL % ___b + 1) * ___p) / ___b; \ + } else { \ + /* \ + * Reduce m / p, and try to clear bit 31 of m when \ + * possible, otherwise that'll need extra overflow \ + * handling later. \ + */ \ + uint32_t ___bits = -(___m & -___m); \ + ___bits |= ___m >> 32; \ + ___bits = (~___bits) << 1; \ + /* \ + * If ___bits == 0 then setting bit 31 is unavoidable. \ + * Simply apply the maximum possible reduction in that \ + * case. Otherwise the MSB of ___bits indicates the \ + * best reduction we should apply. \ + */ \ + if (!___bits) { \ + ___p /= (___m & -___m); \ + ___m /= (___m & -___m); \ + } else { \ + ___p >>= ilog2(___bits); \ + ___m >>= ilog2(___bits); \ + } \ + /* No bias needed. */ \ + ___bias = 0; \ + } \ + \ + /* \ + * Now we have a combination of 2 conditions: \ + * \ + * 1) whether or not we need to apply a bias, and \ + * \ + * 2) whether or not there might be an overflow in the cross \ + * product determined by (___m & ((1 << 63) | (1 << 31))). \ + * \ + * Select the best way to do (m_bias + m * n) / (1 << 64). \ + * From now on there will be actual runtime code generated. \ + */ \ + ___res = __arch_xprod_64(___m, ___n, ___bias); \ + \ + ___res /= ___p; \ +}) + +#ifndef __arch_xprod_64 +/* + * Default C implementation for __arch_xprod_64() + * + * Prototype: uint64_t __arch_xprod_64(const uint64_t m, uint64_t n, bool bias) + * Semantic: retval = ((bias ? m : 0) + m * n) >> 64 + * + * The product is a 128-bit value, scaled down to 64 bits. + * Assuming constant propagation to optimize away unused conditional code. + * Architectures may provide their own optimized assembly implementation. + */ +static inline uint64_t __arch_xprod_64(const uint64_t m, uint64_t n, bool bias) +{ + uint32_t m_lo = m; + uint32_t m_hi = m >> 32; + uint32_t n_lo = n; + uint32_t n_hi = n >> 32; + uint64_t res, tmp; + + if (!bias) { + res = ((uint64_t)m_lo * n_lo) >> 32; + } else if (!(m & ((1ULL << 63) | (1ULL << 31)))) { + /* there can't be any overflow here */ + res = (m + (uint64_t)m_lo * n_lo) >> 32; + } else { + res = m + (uint64_t)m_lo * n_lo; + tmp = (res < m) ? (1ULL << 32) : 0; + res = (res >> 32) + tmp; + } + + if (!(m & ((1ULL << 63) | (1ULL << 31)))) { + /* there can't be any overflow here */ + res += (uint64_t)m_lo * n_hi; + res += (uint64_t)m_hi * n_lo; + res >>= 32; + } else { + tmp = res += (uint64_t)m_lo * n_hi; + res += (uint64_t)m_hi * n_lo; + tmp = (res < tmp) ? (1ULL << 32) : 0; + res = (res >> 32) + tmp; + } + res += (uint64_t)m_hi * n_hi; + + return res; +} +#endif + +#ifndef __div64_32 extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor); +#endif /* The unnecessary pointer compare is there * to check for type safety (n must be 64bit) @@ -28,14 +205,32 @@ extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor); uint32_t __base = (base); \ uint32_t __rem; \ (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \ - if (((n) >> 32) == 0) { \ + if (__builtin_constant_p(__base) && \ + is_power_of_2(__base)) { \ + __rem = (n) & (__base - 1); \ + (n) >>= ilog2(__base); \ + } else if (__div64_const32_is_OK && \ + __builtin_constant_p(__base) && \ + __base != 0) { \ + uint32_t __res_lo, __n_lo = (n); \ + (n) = __div64_const32(n, __base); \ + /* the remainder can be computed with 32-bit regs */ \ + __res_lo = (n); \ + __rem = __n_lo - __res_lo * __base; \ + } else if (likely(((n) >> 32) == 0)) { \ __rem = (uint32_t)(n) % __base; \ (n) = (uint32_t)(n) / __base; \ - } else \ + } else \ __rem = __div64_32(&(n), __base); \ __rem; \ }) +#else /* BITS_PER_LONG == ?? */ + +# error do_div() does not yet support the C64 + +#endif /* BITS_PER_LONG */ + /* Wrapper for do_div(). Doesn't modify dividend and returns * the result, not reminder. */ diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index 0bf8707..2cabc87 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -96,12 +96,13 @@ int device_probe(struct udevice *dev); * children are deactivated first. * * @dev: Pointer to device to remove + * @flags: Flags for selective device removal * @return 0 if OK, -ve on error (an error here is normally a very bad thing) */ #if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE) -int device_remove(struct udevice *dev); +int device_remove(struct udevice *dev, uint flags); #else -static inline int device_remove(struct udevice *dev) { return 0; } +static inline int device_remove(struct udevice *dev, uint flags) { return 0; } #endif /** diff --git a/include/dm/device.h b/include/dm/device.h index 4e95fb7..079ec57 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -46,6 +46,32 @@ struct driver_info; #define DM_FLAG_OF_PLATDATA (1 << 8) +/* + * Call driver remove function to stop currently active DMA transfers or + * give DMA buffers back to the HW / controller. This may be needed for + * some drivers to do some final stage cleanup before the OS is called + * (U-Boot exit) + */ +#define DM_FLAG_ACTIVE_DMA (1 << 9) + +/* + * One or multiple of these flags are passed to device_remove() so that + * a selective device removal as specified by the remove-stage and the + * driver flags can be done. + */ +enum { + /* Normal remove, remove all devices */ + DM_REMOVE_NORMAL = 1 << 0, + + /* Remove devices with active DMA */ + DM_REMOVE_ACTIVE_DMA = DM_FLAG_ACTIVE_DMA, + + /* Add more use cases here */ + + /* Remove devices with any active flag */ + DM_REMOVE_ACTIVE_ALL = DM_REMOVE_ACTIVE_DMA, +}; + /** * struct udevice - An instance of a driver * diff --git a/include/dm/root.h b/include/dm/root.h index 3cf730d..058eb98 100644 --- a/include/dm/root.h +++ b/include/dm/root.h @@ -115,4 +115,20 @@ int dm_init(void); */ int dm_uninit(void); +#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE) +/** + * dm_remove_devices_flags - Call remove function of all drivers with + * specific removal flags set to selectively + * remove drivers + * + * All devices with the matching flags set will be removed + * + * @flags: Flags for selective device removal + * @return 0 if OK, -ve on error + */ +int dm_remove_devices_flags(uint flags); +#else +static inline int dm_remove_devices_flags(uint flags) { return 0; } +#endif + #endif diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h new file mode 100644 index 0000000..902abd4 --- /dev/null +++ b/include/dw_hdmi.h @@ -0,0 +1,486 @@ +/* + * Copyright (c) 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DW_HDMI_H +#define _DW_HDMI_H + +#include <edid.h> + +#define HDMI_EDID_BLOCK_SIZE 128 + +/* Identification Registers */ +#define HDMI_DESIGN_ID 0x0000 +#define HDMI_REVISION_ID 0x0001 +#define HDMI_PRODUCT_ID0 0x0002 +#define HDMI_PRODUCT_ID1 0x0003 +#define HDMI_CONFIG0_ID 0x0004 +#define HDMI_CONFIG1_ID 0x0005 +#define HDMI_CONFIG2_ID 0x0006 +#define HDMI_CONFIG3_ID 0x0007 + +/* Interrupt Registers */ +#define HDMI_IH_FC_STAT0 0x0100 +#define HDMI_IH_FC_STAT1 0x0101 +#define HDMI_IH_FC_STAT2 0x0102 +#define HDMI_IH_AS_STAT0 0x0103 +#define HDMI_IH_PHY_STAT0 0x0104 +#define HDMI_IH_I2CM_STAT0 0x0105 +#define HDMI_IH_CEC_STAT0 0x0106 +#define HDMI_IH_VP_STAT0 0x0107 +#define HDMI_IH_I2CMPHY_STAT0 0x0108 +#define HDMI_IH_AHBDMAAUD_STAT0 0x0109 + +#define HDMI_IH_MUTE_FC_STAT0 0x0180 +#define HDMI_IH_MUTE_FC_STAT1 0x0181 +#define HDMI_IH_MUTE_FC_STAT2 0x0182 +#define HDMI_IH_MUTE_AS_STAT0 0x0183 +#define HDMI_IH_MUTE_PHY_STAT0 0x0184 +#define HDMI_IH_MUTE_I2CM_STAT0 0x0185 +#define HDMI_IH_MUTE_CEC_STAT0 0x0186 +#define HDMI_IH_MUTE_VP_STAT0 0x0187 +#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188 +#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189 +#define HDMI_IH_MUTE 0x01FF + +/* Video Sample Registers */ +#define HDMI_TX_INVID0 0x0200 +#define HDMI_TX_INSTUFFING 0x0201 +#define HDMI_TX_GYDATA0 0x0202 +#define HDMI_TX_GYDATA1 0x0203 +#define HDMI_TX_RCRDATA0 0x0204 +#define HDMI_TX_RCRDATA1 0x0205 +#define HDMI_TX_BCBDATA0 0x0206 +#define HDMI_TX_BCBDATA1 0x0207 + +/* Video Packetizer Registers */ +#define HDMI_VP_STATUS 0x0800 +#define HDMI_VP_PR_CD 0x0801 +#define HDMI_VP_STUFF 0x0802 +#define HDMI_VP_REMAP 0x0803 +#define HDMI_VP_CONF 0x0804 +#define HDMI_VP_STAT 0x0805 +#define HDMI_VP_INT 0x0806 +#define HDMI_VP_MASK 0x0807 +#define HDMI_VP_POL 0x0808 + +/* Frame Composer Registers */ +#define HDMI_FC_INVIDCONF 0x1000 +#define HDMI_FC_INHACTV0 0x1001 +#define HDMI_FC_INHACTV1 0x1002 +#define HDMI_FC_INHBLANK0 0x1003 +#define HDMI_FC_INHBLANK1 0x1004 +#define HDMI_FC_INVACTV0 0x1005 +#define HDMI_FC_INVACTV1 0x1006 +#define HDMI_FC_INVBLANK 0x1007 +#define HDMI_FC_HSYNCINDELAY0 0x1008 +#define HDMI_FC_HSYNCINDELAY1 0x1009 +#define HDMI_FC_HSYNCINWIDTH0 0x100A +#define HDMI_FC_HSYNCINWIDTH1 0x100B +#define HDMI_FC_VSYNCINDELAY 0x100C +#define HDMI_FC_VSYNCINWIDTH 0x100D +#define HDMI_FC_INFREQ0 0x100E +#define HDMI_FC_INFREQ1 0x100F +#define HDMI_FC_INFREQ2 0x1010 +#define HDMI_FC_CTRLDUR 0x1011 +#define HDMI_FC_EXCTRLDUR 0x1012 +#define HDMI_FC_EXCTRLSPAC 0x1013 +#define HDMI_FC_CH0PREAM 0x1014 +#define HDMI_FC_CH1PREAM 0x1015 +#define HDMI_FC_CH2PREAM 0x1016 +#define HDMI_FC_AVICONF3 0x1017 +#define HDMI_FC_GCP 0x1018 +#define HDMI_FC_AVICONF0 0x1019 +#define HDMI_FC_AVICONF1 0x101A +#define HDMI_FC_AVICONF2 0x101B +#define HDMI_FC_AVIVID 0x101C +#define HDMI_FC_AVIETB0 0x101D +#define HDMI_FC_AVIETB1 0x101E +#define HDMI_FC_AVISBB0 0x101F +#define HDMI_FC_AVISBB1 0x1020 +#define HDMI_FC_AVIELB0 0x1021 +#define HDMI_FC_AVIELB1 0x1022 +#define HDMI_FC_AVISRB0 0x1023 +#define HDMI_FC_AVISRB1 0x1024 +#define HDMI_FC_AUDICONF0 0x1025 +#define HDMI_FC_AUDICONF1 0x1026 +#define HDMI_FC_AUDICONF2 0x1027 +#define HDMI_FC_AUDICONF3 0x1028 +#define HDMI_FC_VSDIEEEID0 0x1029 +#define HDMI_FC_VSDSIZE 0x102A + +/* HDMI Source PHY Registers */ +#define HDMI_PHY_CONF0 0x3000 +#define HDMI_PHY_TST0 0x3001 +#define HDMI_PHY_TST1 0x3002 +#define HDMI_PHY_TST2 0x3003 +#define HDMI_PHY_STAT0 0x3004 +#define HDMI_PHY_INT0 0x3005 +#define HDMI_PHY_MASK0 0x3006 +#define HDMI_PHY_POL0 0x3007 + +/* HDMI Master PHY Registers */ +#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020 +#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021 +#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022 +#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023 +#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024 +#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025 +#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026 +#define HDMI_PHY_I2CM_INT_ADDR 0x3027 +#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028 +#define HDMI_PHY_I2CM_DIV_ADDR 0x3029 +#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a +#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b +#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c +#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d +#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e +#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f +#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030 +#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031 +#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032 + +/* Audio Sampler Registers */ +#define HDMI_AUD_CONF0 0x3100 +#define HDMI_AUD_CONF1 0x3101 +#define HDMI_AUD_INT 0x3102 +#define HDMI_AUD_CONF2 0x3103 +#define HDMI_AUD_INT1 0x3104 +#define HDMI_AUD_N1 0x3200 +#define HDMI_AUD_N2 0x3201 +#define HDMI_AUD_N3 0x3202 +#define HDMI_AUD_CTS1 0x3203 +#define HDMI_AUD_CTS2 0x3204 +#define HDMI_AUD_CTS3 0x3205 +#define HDMI_AUD_INPUTCLKFS 0x3206 +#define HDMI_AUD_SPDIFINT 0x3302 +#define HDMI_AUD_CONF0_HBR 0x3400 +#define HDMI_AUD_HBR_STATUS 0x3401 +#define HDMI_AUD_HBR_INT 0x3402 +#define HDMI_AUD_HBR_POL 0x3403 +#define HDMI_AUD_HBR_MASK 0x3404 + +/* Main Controller Registers */ +#define HDMI_MC_SFRDIV 0x4000 +#define HDMI_MC_CLKDIS 0x4001 +#define HDMI_MC_SWRSTZ 0x4002 +#define HDMI_MC_OPCTRL 0x4003 +#define HDMI_MC_FLOWCTRL 0x4004 +#define HDMI_MC_PHYRSTZ 0x4005 +#define HDMI_MC_LOCKONCLOCK 0x4006 +#define HDMI_MC_HEACPHY_RST 0x4007 + +/* I2C Master Registers (E-DDC) */ +#define HDMI_I2CM_SLAVE 0x7E00 +#define HDMI_I2CM_ADDRESS 0x7E01 +#define HDMI_I2CM_DATAO 0x7E02 +#define HDMI_I2CM_DATAI 0x7E03 +#define HDMI_I2CM_OPERATION 0x7E04 +#define HDMI_I2CM_INT 0x7E05 +#define HDMI_I2CM_CTLINT 0x7E06 +#define HDMI_I2CM_DIV 0x7E07 +#define HDMI_I2CM_SEGADDR 0x7E08 +#define HDMI_I2CM_SOFTRSTZ 0x7E09 +#define HDMI_I2CM_SEGPTR 0x7E0A +#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B +#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C +#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D +#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E +#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F +#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10 +#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11 +#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 +#define HDMI_I2CM_BUF0 0x7E20 + +enum { + /* HDMI PHY registers define */ + PHY_OPMODE_PLLCFG = 0x06, + PHY_CKCALCTRL = 0x05, + PHY_CKSYMTXCTRL = 0x09, + PHY_VLEVCTRL = 0x0e, + PHY_PLLCURRCTRL = 0x10, + PHY_PLLPHBYCTRL = 0x13, + PHY_PLLGMPCTRL = 0x15, + PHY_PLLCLKBISTPHASE = 0x17, + PHY_TXTERM = 0x19, + + /* ih_phy_stat0 field values */ + HDMI_IH_PHY_STAT0_HPD = 0x1, + + /* ih_mute field values */ + HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, + HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, + + /* tx_invid0 field values */ + HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, + HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f, + HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, + + /* tx_instuffing field values */ + HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, + HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, + + /* vp_pr_cd field values */ + HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0, + HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f, + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, + + /* vp_stuff field values */ + HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, + HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, + HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, + HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, + HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, + + /* vp_conf field values */ + HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, + HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, + HDMI_VP_CONF_PP_EN_ENMASK = 0x20, + HDMI_VP_CONF_PP_EN_DISABLE = 0x00, + HDMI_VP_CONF_PR_EN_MASK = 0x10, + HDMI_VP_CONF_PR_EN_DISABLE = 0x00, + HDMI_VP_CONF_YCC422_EN_MASK = 0x8, + HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, + HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, + HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, + HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, + HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, + + /* vp_remap field values */ + HDMI_VP_REMAP_YCC422_16BIT = 0x0, + + /* fc_invidconf field values */ + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, + HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, + HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, + HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, + HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, + HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, + + + /* fc_aviconf0-fc_aviconf3 field values */ + HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, + HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, + HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, + HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, + HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, + HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, + HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, + HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c, + HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, + HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, + HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, + HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c, + HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, + HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, + HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, + HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, + + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, + HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0, + HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, + HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, + HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, + HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0, + + HDMI_FC_AVICONF2_SCALING_MASK = 0x03, + HDMI_FC_AVICONF2_SCALING_NONE = 0x00, + HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, + HDMI_FC_AVICONF2_SCALING_VERT = 0x02, + HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03, + HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c, + HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, + HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, + HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, + HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, + HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, + HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, + + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, + HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c, + HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, + HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, + + /* fc_gcp field values*/ + HDMI_FC_GCP_SET_AVMUTE = 0x02, + HDMI_FC_GCP_CLEAR_AVMUTE = 0x01, + + /* phy_conf0 field values */ + HDMI_PHY_CONF0_PDZ_MASK = 0x80, + HDMI_PHY_CONF0_PDZ_OFFSET = 7, + HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, + HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, + HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20, + HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5, + HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, + HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, + HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, + HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, + HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, + HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, + HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, + + /* phy_tst0 field values */ + HDMI_PHY_TST0_TSTCLR_MASK = 0x20, + HDMI_PHY_TST0_TSTCLR_OFFSET = 5, + + /* phy_stat0 field values */ + HDMI_PHY_HPD = 0x02, + HDMI_PHY_TX_PHY_LOCK = 0x01, + + /* phy_i2cm_slave_addr field values */ + HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, + + /* phy_i2cm_operation_addr field values */ + HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, + + /* hdmi_phy_i2cm_int_addr */ + HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, + + /* hdmi_phy_i2cm_ctlint_addr */ + HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, + + /* aud_conf0 field values */ + HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80, + HDMI_AUD_CONF0_I2S_SELECT = 0x20, + HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01, + HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02, + HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04, + HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08, + + /* aud_conf0 field values */ + HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0, + HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10, + + /* aud_n3 field values */ + HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80, + HDMI_AUD_N3_AUDN19_16_MASK = 0x0f, + + /* aud_cts3 field values */ + HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, + HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, + HDMI_AUD_CTS3_N_SHIFT_1 = 0, + HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, + HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, + HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, + HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, + HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, + HDMI_AUD_CTS3_CTS_MANUAL = 0x10, + HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, + + /* aud_inputclkfs filed values */ + HDMI_AUD_INPUTCLKFS_128 = 0x0, + + /* mc_clkdis field values */ + HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, + HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, + HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, + + /* mc_swrstz field values */ + HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08, + HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, + + /* mc_flowctrl field values */ + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, + + /* mc_phyrstz field values */ + HDMI_MC_PHYRSTZ_ASSERT = 0x0, + HDMI_MC_PHYRSTZ_DEASSERT = 0x1, + + /* mc_heacphy_rst field values */ + HDMI_MC_HEACPHY_RST_ASSERT = 0x1, + + /* i2cm filed values */ + HDMI_I2CM_SLAVE_DDC_ADDR = 0x50, + HDMI_I2CM_SEGADDR_DDC = 0x30, + HDMI_I2CM_OP_RD8_EXT = 0x2, + HDMI_I2CM_OP_RD8 = 0x1, + HDMI_I2CM_DIV_FAST_STD_MODE = 0x8, + HDMI_I2CM_DIV_FAST_MODE = 0x8, + HDMI_I2CM_DIV_STD_MODE = 0x0, + HDMI_I2CM_SOFTRSTZ_MASK = 0x1, +}; + +struct hdmi_mpll_config { + u64 mpixelclock; + /* Mode of Operation and PLL Dividers Control Register */ + u32 cpce; + /* PLL Gmp Control Register */ + u32 gmp; + /* PLL Current Control Register */ + u32 curr; +}; + +struct hdmi_phy_config { + u64 mpixelclock; + u32 sym_ctr; /* clock symbol and transmitter control */ + u32 term; /* transmission termination value */ + u32 vlev_ctr; /* voltage level control */ +}; + +struct dw_hdmi { + ulong ioaddr; + const struct hdmi_mpll_config *mpll_cfg; + const struct hdmi_phy_config *phy_cfg; + u8 i2c_clk_high; + u8 i2c_clk_low; + u8 reg_io_width; + + int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); +}; + +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock); +int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi); +void dw_hdmi_phy_init(struct dw_hdmi *hdmi); + +int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid); +int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size); +void dw_hdmi_init(struct dw_hdmi *hdmi); + +#endif diff --git a/include/environment.h b/include/environment.h index b602e8a..6f94986 100644 --- a/include/environment.h +++ b/include/environment.h @@ -8,6 +8,8 @@ #ifndef _ENVIRONMENT_H_ #define _ENVIRONMENT_H_ +#include <linux/kconfig.h> + /************************************************************************** * * The "environment" is stored as a list of '\0' terminated diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h new file mode 100644 index 0000000..b987f71 --- /dev/null +++ b/include/environment/ti/mmc.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com + * + * Environment variable definitions for MMC/SD on TI boards. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define DEFAULT_MMC_TI_ARGS \ + "mmcdev=0\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "finduuid=part uuid mmc ${bootpart} uuid\0" \ + "args_mmc=run finduuid;setenv bootargs console=${console} " \ + "${optargs} " \ + "root=PARTUUID=${uuid} rw " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "bootenvfile=uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \ + "loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "envboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootscript; then " \ + "run bootscript;" \ + "else " \ + "if run loadbootenv; then " \ + "echo Loaded env from ${bootenvfile};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "fi;" \ + "fi;\0" \ + "mmcloados=run args_mmc; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "setenv devnum ${mmcdev}; " \ + "setenv devtype mmc; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadimage; then " \ + "if test ${boot_fit} -eq 1; then " \ + "run loadfit; " \ + "else " \ + "run mmcloados;" \ + "fi;" \ + "fi;" \ + "fi;\0" diff --git a/include/environment/ti/spi.h b/include/environment/ti/spi.h new file mode 100644 index 0000000..18c857c --- /dev/null +++ b/include/environment/ti/spi.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com + * + * Environment variable definitions for SPI on TI boards. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TI_SPI_H +#define __TI_SPI_H + +#define KEYSTONE_SPI0_MTD_PARTS "spi0.0:1m(u-boot-spl)ro,-(misc);\0" +#define KEYSTONE_SPI1_MTD_PARTS "spi1.0:1m(u-boot-spl)ro,-(misc);\0" + +#endif diff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h index 6dc159d..8ae0fc0 100644 --- a/include/fsl-mc/ldpaa_wriop.h +++ b/include/fsl-mc/ldpaa_wriop.h @@ -68,4 +68,5 @@ phy_interface_t wriop_get_enet_if(int); void wriop_dpmac_disable(int); void wriop_dpmac_enable(int); phy_interface_t wriop_dpmac_enet_if(int, int); +void wriop_init_dpmac_qsgmii(int, int); #endif /* __LDPAA_WRIOP_H */ diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index b8de46b..6a1f04b 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -477,4 +477,12 @@ typedef struct fixed_ddr_parm{ int max_freq; fsl_ddr_cfg_regs_t *ddr_settings; } fixed_ddr_parm_t; + +/** + * fsl_initdram() - Set up the SDRAM + * + * @return 0 if OK, -ve on error + */ +int fsl_initdram(void); + #endif diff --git a/include/fsl_validate.h b/include/fsl_validate.h index c350938..452c6df 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -40,8 +40,8 @@ struct fsl_secboot_img_hdr { u8 num_srk; u8 srk_sel; u8 reserve; - u8 ie_flag; } len_kr; + u8 ie_flag; u32 uid_flag; @@ -69,6 +69,11 @@ struct fsl_secboot_img_hdr { #define MAX_KEY_ENTRIES 8 #endif +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#define IE_FLAG_MASK 0x1 +#define SCRATCH_IE_LOW_ADR 13 +#define SCRATCH_IE_HIGH_ADR 14 +#endif #else /* CONFIG_ESBC_HDR_LS */ @@ -150,6 +155,10 @@ struct fsl_secboot_img_hdr { #define MAX_KEY_ENTRIES 4 #endif +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#define IE_FLAG_MASK 0xFFFFFFFF +#endif + #endif /* CONFIG_ESBC_HDR_LS */ @@ -202,6 +211,17 @@ struct fsl_secboot_sg_table { }; #endif +/* ESBC global structure. + * Data to be used across verification of different images. + * Stores follwoing Data: + * IE Table + */ +struct fsl_secboot_glb { +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + uintptr_t ie_addr; + struct ie_key_info ie_tbl; +#endif +}; /* * ESBC private structure. * Private structure used by ESBC to store following fields @@ -213,7 +233,7 @@ struct fsl_secboot_sg_table { */ struct fsl_secboot_img_priv { uint32_t hdr_location; - u32 ie_addr; + uintptr_t ie_addr; u32 key_len; struct fsl_secboot_img_hdr hdr; diff --git a/include/grlib/apbuart.h b/include/grlib/apbuart.h deleted file mode 100644 index 1e1eb9a..0000000 --- a/include/grlib/apbuart.h +++ /dev/null @@ -1,47 +0,0 @@ -/* GRLIB APBUART definitions - * - * (C) Copyright 2010, 2015 - * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __GRLIB_APBUART_H__ -#define __GRLIB_APBUART_H__ - -/* APBUART Register map */ -typedef struct { - volatile unsigned int data; - volatile unsigned int status; - volatile unsigned int ctrl; - volatile unsigned int scaler; -} ambapp_dev_apbuart; - -/* - * The following defines the bits in the LEON UART Status Registers. - */ - -#define APBUART_STATUS_DR 0x00000001 /* Data Ready */ -#define APBUART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ -#define APBUART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ -#define APBUART_STATUS_BR 0x00000008 /* Break Error */ -#define APBUART_STATUS_OE 0x00000010 /* RX Overrun Error */ -#define APBUART_STATUS_PE 0x00000020 /* RX Parity Error */ -#define APBUART_STATUS_FE 0x00000040 /* RX Framing Error */ -#define APBUART_STATUS_ERR 0x00000078 /* Error Mask */ - -/* - * The following defines the bits in the LEON UART Ctrl Registers. - */ - -#define APBUART_CTRL_RE 0x00000001 /* Receiver enable */ -#define APBUART_CTRL_TE 0x00000002 /* Transmitter enable */ -#define APBUART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ -#define APBUART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ -#define APBUART_CTRL_PS 0x00000010 /* Parity select */ -#define APBUART_CTRL_PE 0x00000020 /* Parity enable */ -#define APBUART_CTRL_FL 0x00000040 /* Flow control enable */ -#define APBUART_CTRL_LB 0x00000080 /* Loop Back enable */ -#define APBUART_CTRL_DBG (1<<11) /* Debug Bit used by GRMON */ - -#endif diff --git a/include/grlib/gptimer.h b/include/grlib/gptimer.h deleted file mode 100644 index 8b2b165..0000000 --- a/include/grlib/gptimer.h +++ /dev/null @@ -1,34 +0,0 @@ -/* GRLIB GPTIMER (General Purpose Timer) definitions - * - * (C) Copyright 2010, 2015 - * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __GRLIB_GPTIMER_H__ -#define __GRLIB_GPTIMER_H__ - -typedef struct { - volatile unsigned int val; - volatile unsigned int rld; - volatile unsigned int ctrl; - volatile unsigned int unused; -} ambapp_dev_gptimer_element; - -#define GPTIMER_CTRL_EN 0x1 /* Timer enable */ -#define GPTIMER_CTRL_RS 0x2 /* Timer reStart */ -#define GPTIMER_CTRL_LD 0x4 /* Timer reLoad */ -#define GPTIMER_CTRL_IE 0x8 /* interrupt enable */ -#define GPTIMER_CTRL_IP 0x10 /* interrupt flag/pending */ -#define GPTIMER_CTRL_CH 0x20 /* Chain with previous timer */ - -typedef struct { - volatile unsigned int scalar; - volatile unsigned int scalar_reload; - volatile unsigned int config; - volatile unsigned int unused; - volatile ambapp_dev_gptimer_element e[8]; -} ambapp_dev_gptimer; - -#endif diff --git a/include/grlib/greth.h b/include/grlib/greth.h deleted file mode 100644 index 89c1e49..0000000 --- a/include/grlib/greth.h +++ /dev/null @@ -1,87 +0,0 @@ -/* Gaisler.com GRETH 10/100/1000 Ethernet MAC definitions - * - * (C) Copyright 2010, 2015 - * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __GRLIB_GRETH_H__ -#define __GRLIB_GRETH_H__ - -#define GRETH_FD 0x10 -#define GRETH_RESET 0x40 -#define GRETH_MII_BUSY 0x8 -#define GRETH_MII_NVALID 0x10 - -/* MII registers */ -#define GRETH_MII_EXTADV_1000FD 0x00000200 -#define GRETH_MII_EXTADV_1000HD 0x00000100 -#define GRETH_MII_EXTPRT_1000FD 0x00000800 -#define GRETH_MII_EXTPRT_1000HD 0x00000400 - -#define GRETH_MII_100T4 0x00000200 -#define GRETH_MII_100TXFD 0x00000100 -#define GRETH_MII_100TXHD 0x00000080 -#define GRETH_MII_10FD 0x00000040 -#define GRETH_MII_10HD 0x00000020 - -#define GRETH_BD_EN 0x800 -#define GRETH_BD_WR 0x1000 -#define GRETH_BD_IE 0x2000 -#define GRETH_BD_LEN 0x7FF - -#define GRETH_TXEN 0x1 -#define GRETH_INT_TX 0x8 -#define GRETH_TXI 0x4 -#define GRETH_TXBD_STATUS 0x0001C000 -#define GRETH_TXBD_MORE 0x20000 -#define GRETH_TXBD_IPCS 0x40000 -#define GRETH_TXBD_TCPCS 0x80000 -#define GRETH_TXBD_UDPCS 0x100000 -#define GRETH_TXBD_ERR_LC 0x10000 -#define GRETH_TXBD_ERR_UE 0x4000 -#define GRETH_TXBD_ERR_AL 0x8000 -#define GRETH_TXBD_NUM 128 -#define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1) -#define GRETH_TX_BUF_SIZE 2048 - -#define GRETH_INT_RX 0x4 -#define GRETH_RXEN 0x2 -#define GRETH_RXI 0x8 -#define GRETH_RXBD_STATUS 0xFFFFC000 -#define GRETH_RXBD_ERR_AE 0x4000 -#define GRETH_RXBD_ERR_FT 0x8000 -#define GRETH_RXBD_ERR_CRC 0x10000 -#define GRETH_RXBD_ERR_OE 0x20000 -#define GRETH_RXBD_ERR_LE 0x40000 -#define GRETH_RXBD_IP_DEC 0x80000 -#define GRETH_RXBD_IP_CSERR 0x100000 -#define GRETH_RXBD_UDP_DEC 0x200000 -#define GRETH_RXBD_UDP_CSERR 0x400000 -#define GRETH_RXBD_TCP_DEC 0x800000 -#define GRETH_RXBD_TCP_CSERR 0x1000000 - -#define GRETH_RXBD_NUM 128 -#define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1) -#define GRETH_RX_BUF_SIZE 2048 - -/* Ethernet configuration registers */ -typedef struct _greth_regs { - volatile unsigned int control; - volatile unsigned int status; - volatile unsigned int esa_msb; - volatile unsigned int esa_lsb; - volatile unsigned int mdio; - volatile unsigned int tx_desc_p; - volatile unsigned int rx_desc_p; - volatile unsigned int edcl_ip; -} greth_regs; - -/* Ethernet buffer descriptor */ -typedef struct _greth_bd { - volatile unsigned int stat; - unsigned int addr; /* Buffer address not changed by HW */ -} greth_bd; - -#endif diff --git a/include/grlib/irqmp.h b/include/grlib/irqmp.h deleted file mode 100644 index 0354d5c..0000000 --- a/include/grlib/irqmp.h +++ /dev/null @@ -1,23 +0,0 @@ -/* GRLIB IRQMP (IRQ Multi-processor controller) definitions - * - * (C) Copyright 2010, 2015 - * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __GRLIB_IRQMP_H__ -#define __GRLIB_IRQMP_H__ - -typedef struct { - volatile unsigned int ilevel; - volatile unsigned int ipend; - volatile unsigned int iforce; - volatile unsigned int iclear; - volatile unsigned int mstatus; - volatile unsigned int notused[11]; - volatile unsigned int cpu_mask[16]; - volatile unsigned int cpu_force[16]; -} ambapp_dev_irqmp; - -#endif diff --git a/include/i2c.h b/include/i2c.h index d500445..cd7f61e 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -791,21 +791,6 @@ unsigned int i2c_set_bus_speed(unsigned int speed); unsigned int i2c_get_bus_speed(void); -/* - * i2c_reloc_fixup: - * - * Adjusts I2C pointers after U-Boot is relocated to DRAM - */ -void i2c_reloc_fixup(void); -#if defined(CONFIG_SYS_I2C_SOFT) -void i2c_soft_init(void); -void i2c_soft_active(void); -void i2c_soft_tristate(void); -int i2c_soft_read(void); -void i2c_soft_sda(int bit); -void i2c_soft_scl(int bit); -void i2c_soft_delay(void); -#endif #else /* @@ -945,13 +930,6 @@ enum { I2C_8, I2C_9, I2C_10, }; -/* Multi I2C busses handling */ -#ifdef CONFIG_SOFT_I2C_MULTI_BUS -extern int get_multi_scl_pin(void); -extern int get_multi_sda_pin(void); -extern int multi_i2c_init(void); -#endif - /** * Get FDT values for i2c bus. * diff --git a/include/image.h b/include/image.h index 2372518..3f26f9b 100644 --- a/include/image.h +++ b/include/image.h @@ -1256,7 +1256,8 @@ void android_print_contents(const struct andr_img_hdr *hdr); */ int board_fit_config_name_match(const char *name); -#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS +#if defined(CONFIG_SPL_FIT_IMAGE_POST_PROCESS) || \ + defined(CONFIG_FIT_IMAGE_POST_PROCESS) /** * board_fit_image_post_process() - Do any post-process on FIT binary data * diff --git a/include/init_helpers.h b/include/init_helpers.h new file mode 100644 index 0000000..3efcfdd --- /dev/null +++ b/include/init_helpers.h @@ -0,0 +1,18 @@ +/* + * (C) Copyright 2011 + * Graeme Russ, <graeme.russ@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _INIT_HELPERS_H_ +#define _INIT_HELPERS_H_ + +/** + * init_cache_f_r() - Turn on the cache in preparation for relocation + * + * @return 0 if OK, -ve on error + */ +int init_cache_f_r(void); + +#endif /* _INIT_HELPERS_H_ */ diff --git a/include/initcall.h b/include/initcall.h index 65f67dc..fe7e903 100644 --- a/include/initcall.h +++ b/include/initcall.h @@ -4,6 +4,11 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __INITCALL_H +#define __INITCALL_H + typedef int (*init_fnc_t)(void); int initcall_run_list(const init_fnc_t init_sequence[]); + +#endif diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 1b2e491..576b15d 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -2,6 +2,7 @@ #define _LINUX_BITOPS_H #include <asm/types.h> +#include <asm-generic/bitsperlong.h> #include <linux/compiler.h> #define BIT(nr) (1UL << (nr)) diff --git a/include/linux/math64.h b/include/linux/math64.h index 6d760d7..08584c8 100644 --- a/include/linux/math64.h +++ b/include/linux/math64.h @@ -1,10 +1,15 @@ #ifndef _LINUX_MATH64_H #define _LINUX_MATH64_H +#include <div64.h> +#include <linux/bitops.h> #include <linux/types.h> #if BITS_PER_LONG == 64 +#define div64_long(x, y) div64_s64((x), (y)) +#define div64_ul(x, y) div64_u64((x), (y)) + /** * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder * @@ -27,6 +32,15 @@ static inline s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder) } /** + * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder + */ +static inline u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder) +{ + *remainder = dividend % divisor; + return dividend / divisor; +} + +/** * div64_u64 - unsigned 64bit divide with 64bit divisor */ static inline u64 div64_u64(u64 dividend, u64 divisor) @@ -34,8 +48,19 @@ static inline u64 div64_u64(u64 dividend, u64 divisor) return dividend / divisor; } +/** + * div64_s64 - signed 64bit divide with 64bit divisor + */ +static inline s64 div64_s64(s64 dividend, s64 divisor) +{ + return dividend / divisor; +} + #elif BITS_PER_LONG == 32 +#define div64_long(x, y) div_s64((x), (y)) +#define div64_ul(x, y) div_u64((x), (y)) + #ifndef div_u64_rem static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder) { @@ -48,10 +73,18 @@ static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder) extern s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder); #endif +#ifndef div64_u64_rem +extern u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder); +#endif + #ifndef div64_u64 extern u64 div64_u64(u64 dividend, u64 divisor); #endif +#ifndef div64_s64 +extern s64 div64_s64(s64 dividend, s64 divisor); +#endif + #endif /* BITS_PER_LONG */ /** @@ -82,4 +115,143 @@ static inline s64 div_s64(s64 dividend, s32 divisor) u32 iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder); +static __always_inline u32 +__iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder) +{ + u32 ret = 0; + + while (dividend >= divisor) { + /* The following asm() prevents the compiler from + optimising this loop into a modulo operation. */ + asm("" : "+rm"(dividend)); + + dividend -= divisor; + ret++; + } + + *remainder = dividend; + + return ret; +} + +#ifndef mul_u32_u32 +/* + * Many a GCC version messes this up and generates a 64x64 mult :-( + */ +static inline u64 mul_u32_u32(u32 a, u32 b) +{ + return (u64)a * b; +} +#endif + +#if defined(CONFIG_ARCH_SUPPORTS_INT128) && defined(__SIZEOF_INT128__) + +#ifndef mul_u64_u32_shr +static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift) +{ + return (u64)(((unsigned __int128)a * mul) >> shift); +} +#endif /* mul_u64_u32_shr */ + +#ifndef mul_u64_u64_shr +static inline u64 mul_u64_u64_shr(u64 a, u64 mul, unsigned int shift) +{ + return (u64)(((unsigned __int128)a * mul) >> shift); +} +#endif /* mul_u64_u64_shr */ + +#else + +#ifndef mul_u64_u32_shr +static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift) +{ + u32 ah, al; + u64 ret; + + al = a; + ah = a >> 32; + + ret = mul_u32_u32(al, mul) >> shift; + if (ah) + ret += mul_u32_u32(ah, mul) << (32 - shift); + + return ret; +} +#endif /* mul_u64_u32_shr */ + +#ifndef mul_u64_u64_shr +static inline u64 mul_u64_u64_shr(u64 a, u64 b, unsigned int shift) +{ + union { + u64 ll; + struct { +#ifdef __BIG_ENDIAN + u32 high, low; +#else + u32 low, high; +#endif + } l; + } rl, rm, rn, rh, a0, b0; + u64 c; + + a0.ll = a; + b0.ll = b; + + rl.ll = mul_u32_u32(a0.l.low, b0.l.low); + rm.ll = mul_u32_u32(a0.l.low, b0.l.high); + rn.ll = mul_u32_u32(a0.l.high, b0.l.low); + rh.ll = mul_u32_u32(a0.l.high, b0.l.high); + + /* + * Each of these lines computes a 64-bit intermediate result into "c", + * starting at bits 32-95. The low 32-bits go into the result of the + * multiplication, the high 32-bits are carried into the next step. + */ + rl.l.high = c = (u64)rl.l.high + rm.l.low + rn.l.low; + rh.l.low = c = (c >> 32) + rm.l.high + rn.l.high + rh.l.low; + rh.l.high = (c >> 32) + rh.l.high; + + /* + * The 128-bit result of the multiplication is in rl.ll and rh.ll, + * shift it right and throw away the high part of the result. + */ + if (shift == 0) + return rl.ll; + if (shift < 64) + return (rl.ll >> shift) | (rh.ll << (64 - shift)); + return rh.ll >> (shift & 63); +} +#endif /* mul_u64_u64_shr */ + +#endif + +#ifndef mul_u64_u32_div +static inline u64 mul_u64_u32_div(u64 a, u32 mul, u32 divisor) +{ + union { + u64 ll; + struct { +#ifdef __BIG_ENDIAN + u32 high, low; +#else + u32 low, high; +#endif + } l; + } u, rl, rh; + + u.ll = a; + rl.ll = mul_u32_u32(u.l.low, mul); + rh.ll = mul_u32_u32(u.l.high, mul) + rl.l.high; + + /* Bits 32-63 of the result will be in rh.l.low. */ + rl.l.high = do_div(rh.ll, divisor); + + /* Bits 0-31 of the result will be in rl.l.low. */ + do_div(rl.ll, divisor); + + rl.l.high = rh.l.low; + return rl.ll; +} +#endif /* mul_u64_u32_div */ + #endif /* _LINUX_MATH64_H */ diff --git a/include/linux/usb/musb.h b/include/linux/usb/musb.h index 075d222..e1fdab0 100644 --- a/include/linux/usb/musb.h +++ b/include/linux/usb/musb.h @@ -91,14 +91,6 @@ struct musb_hdrc_config { u8 ram_bits; /* ram address size */ struct musb_hdrc_eps_bits *eps_bits __deprecated; -#ifdef CONFIG_BLACKFIN - /* A GPIO controlling VRSEL in Blackfin */ - unsigned int gpio_vrsel; - unsigned int gpio_vrsel_active; - /* musb CLKIN in Blackfin in MHZ */ - unsigned char clkin; -#endif - }; struct musb_hdrc_platform_data { diff --git a/include/nand.h b/include/nand.h index b6eb223..a865528 100644 --- a/include/nand.h +++ b/include/nand.h @@ -28,6 +28,7 @@ #endif extern void nand_init(void); +unsigned long nand_size(void); #include <linux/compat.h> #include <linux/mtd/mtd.h> diff --git a/include/netdev.h b/include/netdev.h index 7a211bc..8eb8b46 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -50,7 +50,6 @@ int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr); int ftgmac100_initialize(bd_t *bits); int ftmac100_initialize(bd_t *bits); int ftmac110_initialize(bd_t *bits); -int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); int ks8851_mll_initialize(u8 dev_num, int base_addr); int lan91c96_initialize(u8 dev_num, int base_addr); diff --git a/include/phy.h b/include/phy.h index 5477496..4f2094b 100644 --- a/include/phy.h +++ b/include/phy.h @@ -15,6 +15,8 @@ #include <linux/ethtool.h> #include <linux/mdio.h> +#define PHY_FIXED_ID 0xa5a55a5a + #define PHY_MAX_ADDR 32 #define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */ @@ -61,6 +63,9 @@ typedef enum { PHY_INTERFACE_MODE_RGMII_TXID, PHY_INTERFACE_MODE_RTBI, PHY_INTERFACE_MODE_XGMII, + PHY_INTERFACE_MODE_XAUI, + PHY_INTERFACE_MODE_RXAUI, + PHY_INTERFACE_MODE_SFI, PHY_INTERFACE_MODE_NONE, /* Must be last */ PHY_INTERFACE_MODE_COUNT, @@ -80,6 +85,9 @@ static const char *phy_interface_strings[] = { [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", [PHY_INTERFACE_MODE_RTBI] = "rtbi", [PHY_INTERFACE_MODE_XGMII] = "xgmii", + [PHY_INTERFACE_MODE_XAUI] = "xaui", + [PHY_INTERFACE_MODE_RXAUI] = "rxaui", + [PHY_INTERFACE_MODE_SFI] = "sfi", [PHY_INTERFACE_MODE_NONE] = "", }; @@ -267,6 +275,7 @@ int phy_ti_init(void); int phy_vitesse_init(void); int phy_xilinx_init(void); int phy_mscc_init(void); +int phy_fixed_init(void); int board_phy_config(struct phy_device *phydev); int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); diff --git a/include/relocate.h b/include/relocate.h new file mode 100644 index 0000000..0d4b27a --- /dev/null +++ b/include/relocate.h @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2011 + * Graeme Russ, <graeme.russ@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _RELOCATE_H_ +#define _RELOCATE_H_ + +#include <common.h> + +/** + * copy_uboot_to_ram() - Copy U-Boot to its new relocated position + * + * @return 0 if OK, -ve on error + */ +int copy_uboot_to_ram(void); + +/** + * clear_bss() - Clear the BSS (Blocked Start by Symbol) segment + * + * This clears the memory used by global variables + * + * @return 0 if OK, -ve on error + */ +int clear_bss(void); + +/** + * do_elf_reloc_fixups() - Fix up ELF relocations in the relocated code + * + * This processes the relocation tables to ensure that the code can run in its + * new location. + * + * @return 0 if OK, -ve on error + */ +int do_elf_reloc_fixups(void); + +#endif /* _RELOCATE_H_ */ diff --git a/include/rtc.h b/include/rtc.h index 69fe8d4..49142b6 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -128,6 +128,26 @@ int rtc_read8(struct udevice *dev, unsigned int reg); int rtc_write8(struct udevice *dev, unsigned int reg, int val); /** + * rtc_read16() - Read a 16-bit value from the RTC + * + * @dev: Device to read from + * @reg: Offset to start reading from + * @valuep: Place to put the value that is read + * @return 0 if OK, -ve on error + */ +int rtc_read16(struct udevice *dev, unsigned int reg, u16 *valuep); + +/** + * rtc_write16() - Write a 16-bit value to the RTC + * + * @dev: Device to write to + * @reg: Register to start writing to + * @value: Value to write + * @return 0 if OK, -ve on error + */ +int rtc_write16(struct udevice *dev, unsigned int reg, u16 value); + +/** * rtc_read32() - Read a 32-bit value from the RTC * * @dev: Device to read from diff --git a/include/tpm.h b/include/tpm.h index 800f29c..f88388f 100644 --- a/include/tpm.h +++ b/include/tpm.h @@ -639,4 +639,16 @@ uint32_t tpm_get_permissions(uint32_t index, uint32_t *perm); */ uint32_t tpm_flush_specific(uint32_t key_handle, uint32_t resource_type); +#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1 +/** + * Search for a key by usage AuthData and the hash of the parent's pub key. + * + * @param auth Usage auth of the key to search for + * @param pubkey_digest SHA1 hash of the pub key structure of the key + * @param[out] handle The handle of the key (Non-null iff found) + * @return 0 if key was found in TPM; != 0 if not. + */ +uint32_t tpm_find_key_sha1(const uint8_t auth[20], const uint8_t + pubkey_digest[20], uint32_t *handle); +#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */ #endif /* __TPM_H */ diff --git a/include/aes.h b/include/uboot_aes.h index 6315c02..6315c02 100644 --- a/include/aes.h +++ b/include/uboot_aes.h diff --git a/include/xyzModem.h b/include/xyzModem.h index 0eddbbc..4b667f7 100644 --- a/include/xyzModem.h +++ b/include/xyzModem.h @@ -44,9 +44,6 @@ #define xyzModem_abort 2 -#ifdef REDBOOT -extern getc_io_funcs_t xyzModem_io; -#else #define CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT #define CYGACC_CALL_IF_SET_CONSOLE_COMM(x) @@ -60,12 +57,8 @@ typedef struct { char *filename; int mode; int chan; -#ifdef CYGPKG_REDBOOT_NETWORKING - struct sockaddr_in *server; -#endif } connection_info_t; -#endif int xyzModem_stream_open(connection_info_t *info, int *err); |