From f71cbfe3ca5d2ad20159871700e8e248c8818ba8 Mon Sep 17 00:00:00 2001 From: Nitin Garg Date: Wed, 2 Apr 2014 08:55:01 -0500 Subject: ARM: Add workaround for Cortex-A9 errata 794072 A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions. Signed-off-by: Nitin Garg Acked-by: Dirk Behme diff --git a/README b/README index 216f0c7..00127a7 100644 --- a/README +++ b/README @@ -566,6 +566,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 + CONFIG_ARM_ERRATA_794072 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index ac1e55a..f3830c8 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -205,7 +205,7 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c1, c0, 0 @ write system control register #endif -#ifdef CONFIG_ARM_ERRATA_742230 +#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072)) mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register orr r0, r0, #1 << 4 @ set bit #4 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register -- cgit v0.10.2 From b7588e3bdcdb2ee073a6a66a4c882b23feaaa0e6 Mon Sep 17 00:00:00 2001 From: Nitin Garg Date: Wed, 2 Apr 2014 08:55:02 -0500 Subject: ARM: Add workaround for Cortex-A9 errata 761320 Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions. Signed-off-by: Nitin Garg Acked-by: Fabio Estevam diff --git a/README b/README index 00127a7..da85c89 100644 --- a/README +++ b/README @@ -567,6 +567,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 CONFIG_ARM_ERRATA_794072 + CONFIG_ARM_ERRATA_761320 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index f3830c8..27be451 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 11 @ set bit #11 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_761320 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 21 @ set bit #21 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15) -- cgit v0.10.2 From 68659d649debc9fb3d8ce21ce4dcfe3a66b63e3a Mon Sep 17 00:00:00 2001 From: Nitin Garg Date: Wed, 2 Apr 2014 08:55:03 -0500 Subject: MX6: Enable ARM errata workaround 794072 and 761320 Since MX6 is Cortex-A9 r2p10, enable software workaround for errata 794072 and 761320. Signed-off-by: Nitin Garg diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index eb107d3..8a8920f 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -20,6 +20,8 @@ #define CONFIG_ARM_ERRATA_742230 #define CONFIG_ARM_ERRATA_743622 #define CONFIG_ARM_ERRATA_751472 +#define CONFIG_ARM_ERRATA_794072 +#define CONFIG_ARM_ERRATA_761320 #define CONFIG_BOARD_POSTCLK_INIT #ifndef CONFIG_SYS_L2CACHE_OFF -- cgit v0.10.2