From 58fab4cd9ceb9556eaa7c18a2390b321c35d05aa Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 10:54:08 +0200 Subject: ARM: zynq: Add interrupt-controller property to gpio nodes GPIO driver supports an input interrupt that's why gpio node itself can be labeled as interrupt controller. Reported-by: John Linn Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 2d786f0..a352bc8 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -96,8 +96,10 @@ gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; + #interrupt-cells = <2>; clocks = <&clkc 42>; gpio-controller; + interrupt-controller; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; -- cgit v0.10.2 From 4c987271b388cb14a57a1bbc7068b18eebf7967a Mon Sep 17 00:00:00 2001 From: Moritz Fischer Date: Thu, 30 Jul 2015 18:13:55 -0700 Subject: ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller. Signed-off-by: Moritz Fischer Signed-off-by: Olof Johansson Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index a352bc8..55eae61 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -272,6 +272,13 @@ reg = <0x100 0x100>; }; + rstc: rstc@200 { + compatible = "xlnx,zynq-reset"; + reg = <0x200 0x48>; + #reset-cells = <1>; + syscon = <&slcr>; + }; + pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; -- cgit v0.10.2 From 20fe3f1791fa836de8c0e9991dde40362350b1a0 Mon Sep 17 00:00:00 2001 From: Moritz Fischer Date: Mon, 22 Jun 2015 23:18:44 -0700 Subject: ARM: dts: Updated devicetree bindings for Zynq 7000 platform Added addtional bindings required for FPGA Manager operation of the Xilinx Zynq Devc configuration interface. Signed-off-by: Moritz Fischer Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 55eae61..aff65f2 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -307,6 +307,7 @@ devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; reg = <0xf8007000 0x100>; + syscon = <&slcr>; }; global_timer: timer@f8f00200 { -- cgit v0.10.2 From 77bb73decb2bdf948a8a5f98273a7504c452baee Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 11:00:37 +0200 Subject: ARM: zynq: Align devcfg node - Have compatible string as the first property - Sync with Linux kernel dtsi - Add missing interrupt properties Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index aff65f2..a327557 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -306,7 +306,11 @@ devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; + interrupt-parent = <&intc>; + interrupts = <0 8 4>; reg = <0xf8007000 0x100>; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; -- cgit v0.10.2 From 936bbc5d161923283135dcc84e6af1fcd31f848a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 11:15:00 +0200 Subject: ARM: zynq: Fix bootargs in board dtsi - Sync with Linux kernel - Remove rootfs - Remove earlyprintk Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 528cd27..eba7037 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -27,7 +27,7 @@ }; chosen { - bootargs = "earlyprintk"; + bootargs = ""; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 1610520..bf996ad 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -27,7 +27,7 @@ }; chosen { - bootargs = "earlyprintk"; + bootargs = ""; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index b6982c0..6dc7c89 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -21,7 +21,7 @@ }; chosen { - bootargs = "root=/dev/ram rw earlyprintk"; + bootargs = ""; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 4fed221..858d0e2 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -18,7 +18,7 @@ }; chosen { - bootargs = "root=/dev/ram rw earlyprintk"; + bootargs = ""; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 8d69f0e..6cab832 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -20,7 +20,7 @@ }; chosen { - bootargs = "root=/dev/ram rw earlyprintk"; + bootargs = ""; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 77fdfcc..40a3601 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -20,7 +20,7 @@ }; chosen { - bootargs = "root=/dev/ram rw earlyprintk"; + bootargs = ""; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index ec9b2f7..b262d83 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -26,7 +26,7 @@ }; chosen { - bootargs = "earlyprintk"; + bootargs = ""; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index d04e962..acc6e42 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -26,7 +26,7 @@ }; chosen { - bootargs = "earlyprintk"; + bootargs = ""; stdout-path = "serial0:115200n8"; }; -- cgit v0.10.2 From c9132b1e4489b394a87555d17c059b4d681ed0cf Mon Sep 17 00:00:00 2001 From: Punnaiah Choudary Kalluri Date: Wed, 3 Feb 2016 15:27:18 +0530 Subject: ARM: zynq: DT: Add ethernet phy reset information Added phy reset gpio information for gem0. Signed-off-by: Punnaiah Choudary Kalluri Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index eba7037..ee050aa 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -91,6 +91,8 @@ phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; + phy-reset-gpio = <&gpio0 11 0>; + phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; -- cgit v0.10.2 From 169050e4f59000c5c169bbf3855d8c013b161a6b Mon Sep 17 00:00:00 2001 From: Christian Kohn Date: Thu, 12 Nov 2015 15:53:35 -0800 Subject: ARM: zynq: zc702: Add adv7511 on i2c bus Add bindings for adv7511. Signed-off-by: Christian Kohn Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index ee050aa..8ad1db2 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -130,6 +130,21 @@ }; }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + adv7511: hdmi-tx@39 { + compatible = "adi,adv7511"; + reg = <0x39>; + adi,input-depth = <8>; + adi,input-colorspace = "yuv422"; + adi,input-clock = "1x"; + adi,input-style = <3>; + adi,input-justification = "right"; + }; + }; + i2c@2 { #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From ac2c40749037acbeafcc5329194e6776450e870b Mon Sep 17 00:00:00 2001 From: Christian Kohn Date: Thu, 12 Nov 2015 15:53:36 -0800 Subject: ARM: zynq: zc706: Add adv7511 on i2c bus Add missing adv7511 and configure to match Base TRD. Signed-off-by: Christian Kohn Reviewed-by: Nathan Rossi Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index bf996ad..cefee25 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -84,6 +84,21 @@ }; }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + adv7511: hdmi-tx@39 { + compatible = "adi,adv7511"; + reg = <0x39>; + adi,input-depth = <8>; + adi,input-colorspace = "yuv422"; + adi,input-clock = "1x"; + adi,input-style = <3>; + adi,input-justification = "evenly"; + }; + }; + i2c@2 { #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From a95d54b49074985e2429f2af42c6d746c63285c0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 13:04:15 +0200 Subject: ARM: zynq: Align spi and qspi node locations Keep nodes alphabelitally sorted. Signed-off-by: Michal Simek Reviewed-by: Nathan Rossi diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 8ad1db2..6585010 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -387,6 +387,11 @@ }; }; +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; +}; + &sdhci0 { u-boot,dm-pre-reloc; status = "okay"; @@ -401,11 +406,6 @@ pinctrl-0 = <&pinctrl_uart1_default>; }; -&qspi { - u-boot,dm-pre-reloc; - status = "okay"; -}; - &usb0 { status = "okay"; dr_mode = "host"; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index cefee25..d04880a 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -306,6 +306,11 @@ }; }; +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; +}; + &sdhci0 { u-boot,dm-pre-reloc; status = "okay"; @@ -320,11 +325,6 @@ pinctrl-0 = <&pinctrl_uart1_default>; }; -&qspi { - u-boot,dm-pre-reloc; - status = "okay"; -}; - &usb0 { status = "okay"; dr_mode = "host"; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 6dc7c89..33524cb 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -36,27 +36,6 @@ }; }; -&spi1 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; - flash@0 { - compatible = "sst25wf080"; - reg = <1>; - spi-max-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - partition@test { - label = "spi-flash"; - reg = <0x0 0x100000>; - }; - }; -}; - -&qspi { - status = "okay"; -}; - &can0 { status = "okay"; }; @@ -82,10 +61,31 @@ }; +&qspi { + status = "okay"; +}; + &sdhci0 { status = "okay"; }; +&spi1 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + flash@0 { + compatible = "sst25wf080"; + reg = <1>; + spi-max-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@test { + label = "spi-flash"; + reg = <0x0 0x100000>; + }; + }; +}; + &uart1 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index b262d83..4363a4f 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -50,17 +50,17 @@ }; }; -&sdhci0 { +&qspi { u-boot,dm-pre-reloc; status = "okay"; }; -&uart1 { +&sdhci0 { u-boot,dm-pre-reloc; status = "okay"; }; -&qspi { +&uart1 { u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index acc6e42..f32923f 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -51,17 +51,17 @@ }; }; -&sdhci0 { +&qspi { u-boot,dm-pre-reloc; status = "okay"; }; -&uart1 { +&sdhci0 { u-boot,dm-pre-reloc; status = "okay"; }; -&qspi { +&uart1 { u-boot,dm-pre-reloc; status = "okay"; }; -- cgit v0.10.2 From b347c14426d63f7172c870b10af3db35760ae280 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 15:24:08 +0200 Subject: ARM: zynq: Create empty line below headers Sync with others zynq DTS files. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 858d0e2..463b14b 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -7,6 +7,7 @@ */ /dts-v1/; #include "zynq-7000.dtsi" + / { compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; model = "Xilinx Zynq"; -- cgit v0.10.2 From 74720dc39532d743b24a1ddd6ead94b66d0a29b0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 13:08:35 +0200 Subject: ARM: zynq: Add missing qspi for xm013 Add missing qspi node and make qspi as spi0. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 40a3601..d5bb4ef 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -16,7 +16,8 @@ ethernet0 = &gem1; i2c0 = &i2c1; serial0 = &uart0; - spi0 = &spi0; + spi0 = &qspi; + spi1 = &spi0; }; chosen { @@ -58,6 +59,10 @@ }; }; +&qspi { + status = "okay"; +}; + &spi0 { status = "okay"; num-cs = <4>; -- cgit v0.10.2 From 371fc580d244aa81dd315c3bf16bca6c3607cae6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 12 Jan 2016 08:06:36 +0100 Subject: ARM: zynq: Extend microzed board support Add missing DT nodes and enable USB. Signed-off-by: Michal Simek Reviewed-by: Nathan Rossi diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index 793ab44..cb238cd 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -1,7 +1,7 @@ /* * Xilinx MicroZED board DTS * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2013 - 2016 Xilinx, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,12 +15,27 @@ aliases { serial0 = &uart1; spi0 = &qspi; + mmc0 = &sdhci0; }; memory { device_type = "memory"; reg = <0 0x40000000>; }; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; }; &qspi { @@ -32,3 +47,24 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&sdhci0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 1d70e43..bd261c1 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -21,3 +21,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_ZYNQ_GEM=y CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h index e66088d..ec7bb1c 100644 --- a/include/configs/zynq_microzed.h +++ b/include/configs/zynq_microzed.h @@ -12,6 +12,8 @@ #define CONFIG_SYS_NO_FLASH +#define CONFIG_ZYNQ_USB + #include #endif /* __CONFIG_ZYNQ_MICROZED_H */ -- cgit v0.10.2 From a195ed335978d31121c4c41d1164ffab62abad49 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 14:42:53 +0200 Subject: ARM: zynq: Fix usb phy node for Zybo Compatible property should be the first. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index f32923f..f8dcf1d 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -31,8 +31,8 @@ }; usb_phy0: phy0 { - #phy-cells = <0>; compatible = "usb-nop-xceiv"; + #phy-cells = <0>; reset-gpios = <&gpio0 46 1>; }; }; -- cgit v0.10.2 From c1584e2a2190756d73d1f96e0e431da30870d208 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 1 Apr 2016 16:04:14 +0200 Subject: ARM: zynq: Use memory initialization based on DTS file Remove hardcoded memory sizes. Use information from DT memory node. Signed-off-by: Michal Simek diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index d8e3fa4..aac1e2b 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -278,14 +278,14 @@ #define CONFIG_SYS_TEXT_BASE 0x4000000 #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) +#define CONFIG_SYS_MEMTEST_START 0 +#define CONFIG_SYS_MEMTEST_END 0x1000 #define CONFIG_SYS_MALLOC_LEN 0x1400000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN + +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -- cgit v0.10.2 From 758f29d0f805ccd6ca1354a9562dab3bacf52310 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 1 Apr 2016 15:56:33 +0200 Subject: ARM: zynq: Support systems with more memory banks This is example how to change u-boot to support more memory banks read from DT. Signed-off-by: Michal Simek diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 4c20450..183f642 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -111,26 +111,134 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) return 0; } +#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) +/* + * fdt_get_reg - Fill buffer by information from DT + */ +static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf, + const u32 *cell, int n) +{ + int i = 0, b, banks; + int parent_offset = fdt_parent_offset(fdt, nodeoffset); + int address_cells = fdt_address_cells(fdt, parent_offset); + int size_cells = fdt_size_cells(fdt, parent_offset); + char *p = buf; + u64 val; + u64 vals; + + debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n", + __func__, address_cells, size_cells, buf, cell); + + /* Check memory bank setup */ + banks = n % (address_cells + size_cells); + if (banks) + panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n", + n, address_cells, size_cells); + + banks = n / (address_cells + size_cells); + + for (b = 0; b < banks; b++) { + debug("%s: Bank #%d:\n", __func__, b); + if (address_cells == 2) { + val = cell[i + 1]; + val <<= 32; + val |= cell[i]; + val = fdt64_to_cpu(val); + debug("%s: addr64=%llx, ptr=%p, cell=%p\n", + __func__, val, p, &cell[i]); + *(phys_addr_t *)p = val; + } else { + debug("%s: addr32=%x, ptr=%p\n", + __func__, fdt32_to_cpu(cell[i]), p); + *(phys_addr_t *)p = fdt32_to_cpu(cell[i]); + } + p += sizeof(phys_addr_t); + i += address_cells; + + debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i, + sizeof(phys_addr_t)); + + if (size_cells == 2) { + vals = cell[i + 1]; + vals <<= 32; + vals |= cell[i]; + vals = fdt64_to_cpu(vals); + + debug("%s: size64=%llx, ptr=%p, cell=%p\n", + __func__, vals, p, &cell[i]); + *(phys_size_t *)p = vals; + } else { + debug("%s: size32=%x, ptr=%p\n", + __func__, fdt32_to_cpu(cell[i]), p); + *(phys_size_t *)p = fdt32_to_cpu(cell[i]); + } + p += sizeof(phys_size_t); + i += size_cells; + + debug("%s: ps=%p, i=%x, size=%zu\n", + __func__, p, i, sizeof(phys_size_t)); + } + + /* Return the first address size */ + return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t)); +} + +#define FDT_REG_SIZE sizeof(u32) +/* Temp location for sharing data for storing */ +/* Up to 64-bit address + 64-bit size */ +static u8 tmp[CONFIG_NR_DRAM_BANKS * 16]; + +void dram_init_banksize(void) +{ + int bank; + + memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp)); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + debug("Bank #%d: start %llx\n", bank, + (unsigned long long)gd->bd->bi_dram[bank].start); + debug("Bank #%d: size %llx\n", bank, + (unsigned long long)gd->bd->bi_dram[bank].size); + } +} + int dram_init(void) { - int node; - fdt_addr_t addr; - fdt_size_t size; + int node, len; const void *blob = gd->fdt_blob; + const u32 *cell; - node = fdt_node_offset_by_prop_value(blob, -1, "device_type", - "memory", 7); - if (node == -FDT_ERR_NOTFOUND) { - debug("ZYNQ DRAM: Can't get memory node\n"); - return -1; + memset(&tmp, 0, sizeof(tmp)); + + /* find or create "/memory" node. */ + node = fdt_subnode_offset(blob, 0, "memory"); + if (node < 0) { + printf("%s: Can't get memory node\n", __func__); + return node; } - addr = fdtdec_get_addr_size(blob, node, "reg", &size); - if (addr == FDT_ADDR_T_NONE || size == 0) { - debug("ZYNQ DRAM: Can't get base address or size\n"); + + /* Get pointer to cells and lenght of it */ + cell = fdt_getprop(blob, node, "reg", &len); + if (!cell) { + printf("%s: Can't get reg property\n", __func__); return -1; } - gd->ram_size = size; + + gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE); + + debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size); + + zynq_ddrc_init(); + + return 0; +} +#else +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + zynq_ddrc_init(); return 0; } +#endif diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index aac1e2b..2d941a7 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -277,7 +277,9 @@ /* Physical Memory map */ #define CONFIG_SYS_TEXT_BASE 0x4000000 -#define CONFIG_NR_DRAM_BANKS 1 +#ifndef CONFIG_NR_DRAM_BANKS +# define CONFIG_NR_DRAM_BANKS 1 +#endif #define CONFIG_SYS_MEMTEST_START 0 #define CONFIG_SYS_MEMTEST_END 0x1000 -- cgit v0.10.2 From 1e8d3830f38e7782bf7ece63003beea29a1d1cab Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 18:55:11 +0200 Subject: ARM: zynq: Do not perform reset at the end of thor Setup reset off for lthor. Signed-off-by: Michal Simek diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 2d941a7..c96b9c5 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -114,6 +114,7 @@ # define CONFIG_USB_CABLE_CHECK # define CONFIG_CMD_DFU # define CONFIG_CMD_THOR_DOWNLOAD +# define CONFIG_THOR_RESET_OFF # define CONFIG_USB_FUNCTION_THOR # define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ -- cgit v0.10.2 From 407b76f9704f9e01d1a5c0fb4c28dd81992019ec Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 2 Nov 2015 19:45:35 +0530 Subject: ARM64: zynqmp: Move kernel and fdt offsets and sizes to board config file Move kernel and fdt offsets and sizes to board config file as the flash size varies across boards Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 8cea610..a603255 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -165,8 +165,7 @@ "kernel_addr=0x80000\0" \ "fdt_addr=0x7000000\0" \ "fdt_high=0x10000000\0" \ - "kernel_size=0x2000000\0" \ - "fdt_size=0x80000\0" \ + CONFIG_KERNEL_FDT_OFST_SIZE \ "sdbootdev=0\0"\ "sdboot=mmc dev $sdbootdev && mmcinfo && load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \ "load mmc $sdbootdev:$partid $kernel_addr Image && " \ diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index aa58b62..4a83eee 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -24,6 +24,13 @@ #define COUNTER_FREQUENCY 4000000 +#define CONFIG_KERNEL_FDT_OFST_SIZE \ + "kernel_offset=0x400000\0" \ + "fdt_offset=0x2400000\0" \ + "kernel_size=0x2000000\0" \ + "fdt_size=0x80000\0" \ + "board=ep108\0" + #include #endif /* __CONFIG_ZYNQMP_EP_H */ -- cgit v0.10.2 From 02e782c6cdc74928b021282aea4273ceba5c9f4b Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Thu, 25 Feb 2016 09:30:03 -0800 Subject: ARM64: zynqmp: Use C pre-processor for includes in dts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change the dtsi include code to use the C pre-processor #include instead of the device tree /include/. This brings all ZynqMP device trees inline with each other. Signed-off-by: Alistair Francis Reviewed-by: Sören Brinkmann Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index 754604e..d952de1 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -10,8 +10,8 @@ /dts-v1/; -/include/ "zynqmp.dtsi" -/include/ "zynqmp-ep108-clk.dtsi" +#include "zynqmp.dtsi" +#include "zynqmp-ep108-clk.dtsi" / { model = "ZynqMP EP108"; -- cgit v0.10.2 From beaf7955b7fbac721fb7428109fbdcb400f18daa Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Feb 2016 09:30:15 +0100 Subject: ARM64: zynqmp: Add missing mmc aliases Add missing mmc aliases. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index d952de1..f34555a 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -17,6 +17,8 @@ model = "ZynqMP EP108"; aliases { + mmc0 = &sdhci0; + mmc1 = &sdhci1; serial0 = &uart0; spi0 = &qspi; spi1 = &spi0; -- cgit v0.10.2 From eaae2b5d0cf87bb6d1ec61288331a0a6e5853e27 Mon Sep 17 00:00:00 2001 From: Ranjit Waghmode Date: Wed, 2 Dec 2015 10:06:58 +0530 Subject: ARM64: zynqmp: dt: Change qspi node compatible string This patch makes compatible string as "m25p80" for qspi node in ep108 device tree file Signed-off-by: Ranjit Waghmode Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index f34555a..b6d30e8 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -74,7 +74,7 @@ &qspi { status = "okay"; flash@0 { - compatible = "n25q512a11"; + compatible = "m25p80"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; -- cgit v0.10.2 From b8bf55399273a7aba597b5687ef2180ec1d24122 Mon Sep 17 00:00:00 2001 From: P L Sai Krishna Date: Thu, 7 Jan 2016 14:57:27 +0530 Subject: ARM64: zynqmp: Add 8-bit bus width property. This patch add 8-bit bus width property to eMMC node. Signed-off-by: P L Sai Krishna Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index b6d30e8..ee9d0fe 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -107,6 +107,7 @@ &sdhci0 { status = "okay"; + bus-width = <8>; }; &sdhci1 { -- cgit v0.10.2 From 88a85aac9fe71b5fdcd2bba4ee38829bdc53e4cc Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Thu, 26 Nov 2015 14:12:19 +0100 Subject: ARM64: zynqmp: Correct IRQ nr for the SMMU Signed-off-by: Edgar E. Iglesias Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 8733604..4cfecec 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -454,11 +454,11 @@ reg = <0x0 0xfd800000 0x20000>; #global-interrupts = <1>; interrupt-parent = <&gic>; - interrupts = <0 157 4>, - <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, - <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, - <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, - <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>; + interrupts = <0 155 4>, + <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, + <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, + <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, + <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { -- cgit v0.10.2 From 7f1d7d974bf6a969447212c2c9bc65d77dcf7d67 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Thu, 26 Nov 2015 14:12:20 +0100 Subject: ARM64: zynqmp: Hook up the GEMs to the SMMU Signed-off-by: Edgar E. Iglesias Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 4cfecec..66abe6f 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -310,6 +310,7 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; jumbo-max-len = <10240>; jumbo-supported; }; @@ -323,6 +324,7 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; jumbo-max-len = <10240>; jumbo-supported; }; @@ -336,6 +338,7 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; jumbo-max-len = <10240>; jumbo-supported; }; @@ -349,6 +352,7 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; jumbo-max-len = <10240>; jumbo-supported; }; @@ -459,6 +463,10 @@ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; + mmu-masters = < &gem0 0x874 + &gem1 0x875 + &gem2 0x876 + &gem3 0x877 >; }; spi0: spi@ff040000 { -- cgit v0.10.2 From da2ad7843cedc1b9d2d056b1eb7a67a153b76cc4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 11 Feb 2016 15:26:46 +0100 Subject: ARM64: zynqmp: Sync GEM nodes with Linux Remove jumbo properties which are handled in the driver directly and use mainline compatible string which is already handled by the driver. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 66abe6f..7ac21f2 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -302,7 +302,7 @@ }; gem0: ethernet@ff0b0000 { - compatible = "cdns,gem"; + compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; @@ -311,12 +311,10 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; - jumbo-max-len = <10240>; - jumbo-supported; }; gem1: ethernet@ff0c0000 { - compatible = "cdns,gem"; + compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; @@ -325,12 +323,10 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; - jumbo-max-len = <10240>; - jumbo-supported; }; gem2: ethernet@ff0d0000 { - compatible = "cdns,gem"; + compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; @@ -339,12 +335,10 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; - jumbo-max-len = <10240>; - jumbo-supported; }; gem3: ethernet@ff0e0000 { - compatible = "cdns,gem"; + compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; @@ -353,8 +347,6 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; - jumbo-max-len = <10240>; - jumbo-supported; }; gpio: gpio@ff0a0000 { -- cgit v0.10.2 From bd750e7a6c515c081b72d4ef108a2bfa691a3fd1 Mon Sep 17 00:00:00 2001 From: P L Sai Krishna Date: Tue, 19 Jan 2016 19:01:10 +0530 Subject: ARM64: zynqmp: Added broken-tuning property to SD, eMMC nodes This patch adds broken-tuning property to SD and eMMC nodes. Signed-off-by: P L Sai Krishna Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 7ac21f2..0e6d404 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -434,6 +434,7 @@ interrupts = <0 48 4>; reg = <0x0 0xff160000 0x1000>; clock-names = "clk_xin", "clk_ahb"; + broken-tuning; }; sdhci1: sdhci@ff170000 { @@ -443,6 +444,7 @@ interrupts = <0 49 4>; reg = <0x0 0xff170000 0x1000>; clock-names = "clk_xin", "clk_ahb"; + broken-tuning; }; smmu: smmu@fd800000 { -- cgit v0.10.2 From 8f4e3972a01a2ac47154fbd737b63b386900315c Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Mon, 11 Jan 2016 15:34:42 -0800 Subject: ARM64: zynqmp: DT: Add power domains Add power-domains to the DT and attach devices to them. The power-domains are all logical domains as understood by firmware. Each PD is identified by a unique identifier that the platform firmware understands. Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 0e6d404..9a53ad6 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -45,6 +45,176 @@ }; }; + power-domains { + compatible = "xlnx,zynqmp-genpd"; + + pd_usb0: pd-usb0 { + #power-domain-cells = <0x0>; + pd-id = <0x16>; + }; + + pd_usb1: pd-usb1 { + #power-domain-cells = <0x0>; + pd-id = <0x17>; + }; + + pd_sata: pd-sata { + #power-domain-cells = <0x0>; + pd-id = <0x1c>; + }; + + pd_spi0: pd-spi0 { + #power-domain-cells = <0x0>; + pd-id = <0x23>; + }; + + pd_spi1: pd-spi1 { + #power-domain-cells = <0x0>; + pd-id = <0x24>; + }; + + pd_uart0: pd-uart0 { + #power-domain-cells = <0x0>; + pd-id = <0x21>; + }; + + pd_uart1: pd-uart1 { + #power-domain-cells = <0x0>; + pd-id = <0x22>; + }; + + pd_eth0: pd-eth0 { + #power-domain-cells = <0x0>; + pd-id = <0x1d>; + }; + + pd_eth1: pd-eth1 { + #power-domain-cells = <0x0>; + pd-id = <0x1e>; + }; + + pd_eth2: pd-eth2 { + #power-domain-cells = <0x0>; + pd-id = <0x1f>; + }; + + pd_eth3: pd-eth3 { + #power-domain-cells = <0x0>; + pd-id = <0x20>; + }; + + pd_i2c0: pd-i2c0 { + #power-domain-cells = <0x0>; + pd-id = <0x25>; + }; + + pd_i2c1: pd-i2c1 { + #power-domain-cells = <0x0>; + pd-id = <0x26>; + }; + + pd_dp: pd-dp { + /* fixme: what to attach to */ + #power-domain-cells = <0x0>; + pd-id = <0x29>; + }; + + pd_gdma: pd-gdma { + #power-domain-cells = <0x0>; + pd-id = <0x2a>; + }; + + pd_adma: pd-adma { + #power-domain-cells = <0x0>; + pd-id = <0x2b>; + }; + + pd_ttc0: pd-ttc0 { + #power-domain-cells = <0x0>; + pd-id = <0x18>; + }; + + pd_ttc1: pd-ttc1 { + #power-domain-cells = <0x0>; + pd-id = <0x19>; + }; + + pd_ttc2: pd-ttc2 { + #power-domain-cells = <0x0>; + pd-id = <0x1a>; + }; + + pd_ttc3: pd-ttc3 { + #power-domain-cells = <0x0>; + pd-id = <0x1b>; + }; + + pd_sd0: pd-sd0 { + #power-domain-cells = <0x0>; + pd-id = <0x27>; + }; + + pd_sd1: pd-sd1 { + #power-domain-cells = <0x0>; + pd-id = <0x28>; + }; + + pd_nand: pd-nand { + #power-domain-cells = <0x0>; + pd-id = <0x2c>; + }; + + pd_qspi: pd-qspi { + #power-domain-cells = <0x0>; + pd-id = <0x2d>; + }; + + pd_gpio: pd-gpio { + #power-domain-cells = <0x0>; + pd-id = <0x2e>; + }; + + pd_can0: pd-can0 { + #power-domain-cells = <0x0>; + pd-id = <0x2f>; + }; + + pd_can1: pd-can1 { + #power-domain-cells = <0x0>; + pd-id = <0x30>; + }; + + pd_ddr: pd-ddr { + #power-domain-cells = <0x0>; + pd-id = <0x37>; + }; + + pd_apll: pd-apll { + #power-domain-cells = <0x0>; + pd-id = <0x32>; + }; + + pd_vpll: pd-vpll { + #power-domain-cells = <0x0>; + pd-id = <0x33>; + }; + + pd_dpll: pd-dpll { + #power-domain-cells = <0x0>; + pd-id = <0x34>; + }; + + pd_rpll: pd-rpll { + #power-domain-cells = <0x0>; + pd-id = <0x35>; + }; + + pd_iopll: pd-iopll { + #power-domain-cells = <0x0>; + pd-id = <0x36>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0 143 4>, @@ -106,6 +276,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + power-domains = <&pd_can0>; }; can1: can@ff070000 { @@ -117,6 +288,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + power-domains = <&pd_can1>; }; /* GDMA */ @@ -128,6 +300,7 @@ interrupts = <0 124 4>; xlnx,id = <0>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { @@ -138,6 +311,7 @@ interrupts = <0 125 4>; xlnx,id = <1>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { @@ -148,6 +322,7 @@ interrupts = <0 126 4>; xlnx,id = <2>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { @@ -158,6 +333,7 @@ interrupts = <0 127 4>; xlnx,id = <3>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { @@ -168,6 +344,7 @@ interrupts = <0 128 4>; xlnx,id = <4>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { @@ -178,6 +355,7 @@ interrupts = <0 129 4>; xlnx,id = <5>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { @@ -188,6 +366,7 @@ interrupts = <0 130 4>; xlnx,id = <6>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { @@ -198,6 +377,7 @@ interrupts = <0 131 4>; xlnx,id = <7>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { @@ -218,6 +398,7 @@ interrupts = <0 77 4>; xlnx,id = <0>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { @@ -228,6 +409,7 @@ interrupts = <0 78 4>; xlnx,id = <1>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { @@ -238,6 +420,7 @@ interrupts = <0 79 4>; xlnx,id = <2>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { @@ -248,6 +431,7 @@ interrupts = <0 80 4>; xlnx,id = <3>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { @@ -258,6 +442,7 @@ interrupts = <0 81 4>; xlnx,id = <4>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { @@ -268,6 +453,7 @@ interrupts = <0 82 4>; xlnx,id = <5>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { @@ -278,6 +464,7 @@ interrupts = <0 83 4>; xlnx,id = <6>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { @@ -288,6 +475,7 @@ interrupts = <0 84 4>; xlnx,id = <7>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; }; nand0: nand@ff100000 { @@ -299,6 +487,7 @@ interrupts = <0 14 4>; #address-cells = <2>; #size-cells = <1>; + power-domains = <&pd_nand>; }; gem0: ethernet@ff0b0000 { @@ -311,6 +500,7 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; + power-domains = <&pd_eth0>; }; gem1: ethernet@ff0c0000 { @@ -323,6 +513,7 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; + power-domains = <&pd_eth1>; }; gem2: ethernet@ff0d0000 { @@ -335,6 +526,7 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; + power-domains = <&pd_eth2>; }; gem3: ethernet@ff0e0000 { @@ -347,6 +539,7 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; + power-domains = <&pd_eth3>; }; gpio: gpio@ff0a0000 { @@ -356,6 +549,7 @@ interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff0a0000 0x1000>; + power-domains = <&pd_gpio>; }; i2c0: i2c@ff020000 { @@ -366,6 +560,7 @@ reg = <0x0 0xff020000 0x1000>; #address-cells = <1>; #size-cells = <0>; + power-domains = <&pd_i2c0>; }; i2c1: i2c@ff030000 { @@ -376,6 +571,7 @@ reg = <0x0 0xff030000 0x1000>; #address-cells = <1>; #size-cells = <0>; + power-domains = <&pd_i2c1>; }; pcie: pcie@fd0e0000 { @@ -408,6 +604,7 @@ reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>; #address-cells = <1>; #size-cells = <0>; + power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { @@ -425,6 +622,7 @@ reg = <0x0 0xfd0c0000 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; + power-domains = <&pd_sata>; }; sdhci0: sdhci@ff160000 { @@ -435,6 +633,7 @@ reg = <0x0 0xff160000 0x1000>; clock-names = "clk_xin", "clk_ahb"; broken-tuning; + power-domains = <&pd_sd0>; }; sdhci1: sdhci@ff170000 { @@ -445,6 +644,7 @@ reg = <0x0 0xff170000 0x1000>; clock-names = "clk_xin", "clk_ahb"; broken-tuning; + power-domains = <&pd_sd1>; }; smmu: smmu@fd800000 { @@ -472,6 +672,7 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; + power-domains = <&pd_spi0>; }; spi1: spi@ff050000 { @@ -483,6 +684,7 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; + power-domains = <&pd_spi1>; }; ttc0: timer@ff110000 { @@ -492,6 +694,7 @@ interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x1000>; timer-width = <32>; + power-domains = <&pd_ttc0>; }; ttc1: timer@ff120000 { @@ -501,6 +704,7 @@ interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x1000>; timer-width = <32>; + power-domains = <&pd_ttc1>; }; ttc2: timer@ff130000 { @@ -510,6 +714,7 @@ interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x1000>; timer-width = <32>; + power-domains = <&pd_ttc2>; }; ttc3: timer@ff140000 { @@ -519,6 +724,7 @@ interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x1000>; timer-width = <32>; + power-domains = <&pd_ttc3>; }; uart0: serial@ff000000 { @@ -528,6 +734,7 @@ interrupts = <0 21 4>; reg = <0x0 0xff000000 0x1000>; clock-names = "uart_clk", "pclk"; + power-domains = <&pd_uart0>; }; uart1: serial@ff010000 { @@ -537,6 +744,7 @@ interrupts = <0 22 4>; reg = <0x0 0xff010000 0x1000>; clock-names = "uart_clk", "pclk"; + power-domains = <&pd_uart1>; }; usb0: usb@fe200000 { @@ -546,6 +754,7 @@ interrupts = <0 65 4>; reg = <0x0 0xfe200000 0x40000>; clock-names = "clk_xin", "clk_ahb"; + power-domains = <&pd_usb0>; }; usb1: usb@fe300000 { @@ -555,6 +764,7 @@ interrupts = <0 70 4>; reg = <0x0 0xfe300000 0x40000>; clock-names = "clk_xin", "clk_ahb"; + power-domains = <&pd_usb1>; }; watchdog0: watchdog@fd4d0000 { -- cgit v0.10.2 From 14cd9eabb871b693b2f6ca30f2f594baa5e99884 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 15:28:33 +0200 Subject: ARM64: zynqmp: Add missing interrupt-parent to PMU node ZynqMP is not using global interrupt-parent setting that's why it has to be listed in every node separately. PMU node missed it and this patch is adding it. Reported-by: John Linn Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 9a53ad6..a09bbbf 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -217,6 +217,7 @@ pmu { compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, -- cgit v0.10.2 From ff50d21bd23b4d8a579100a790f5db81498e2d07 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2015 11:21:25 +0100 Subject: ARM64: zynqmp: Add CCI-400 node Add CCI-400 node to DTSI. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index a09bbbf..48505fa 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -292,6 +292,25 @@ power-domains = <&pd_can1>; }; + cci: cci@fd6e0000 { + compatible = "arm,cci-400"; + reg = <0x0 0xfd6e0000 0x9000>; + ranges = <0x0 0x0 0xfd6e0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupt-parent = <&gic>; + interrupts = <0 123 4>, + <0 123 4>, + <0 123 4>, + <0 123 4>, + <0 123 4>; + }; + }; + /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; -- cgit v0.10.2 From b34d11de188186e8ca39de6b4f7453823ab20820 Mon Sep 17 00:00:00 2001 From: VNSL Durga Date: Thu, 24 Mar 2016 22:45:12 +0530 Subject: ARM64: zynqmp: Added clocks to DT ZynqMP DMA's main clock and apb clock are added in zynqmp DT. Signed-off-by: VNSL Durga Signed-off-by: Michal Simek Acked-by: Punnaiah Choudary Kalluri diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 48505fa..4520930 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -318,6 +318,7 @@ reg = <0x0 0xfd500000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <0>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -329,6 +330,7 @@ reg = <0x0 0xfd510000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <1>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -340,6 +342,7 @@ reg = <0x0 0xfd520000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <2>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -351,6 +354,7 @@ reg = <0x0 0xfd530000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <3>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -362,6 +366,7 @@ reg = <0x0 0xfd540000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <4>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -373,6 +378,7 @@ reg = <0x0 0xfd550000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <5>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -384,6 +390,7 @@ reg = <0x0 0xfd560000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <6>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -395,6 +402,7 @@ reg = <0x0 0xfd570000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <7>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; -- cgit v0.10.2 From 908690098c1836055ee98bde045308ca2ae5d56e Mon Sep 17 00:00:00 2001 From: Naga Sureshkumar Relli Date: Fri, 11 Mar 2016 13:10:26 +0530 Subject: ARM64: zynqmp: Add ddrc node in dts This patch adds ddrc memory controller node in dts. size mentioned in dts is 0x30000, because we need to access DDR_QOS INTR registers located at fd090208 from this driver. Signed-off-by: Naga Sureshkumar Relli Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 4520930..b68fb1a 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -506,6 +506,13 @@ power-domains = <&pd_adma>; }; + mc: memory-controller@fd070000 { + compatible = "xlnx,zynqmp-ddrc-2.40a"; + reg = <0x0 0xfd070000 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 112 4>; + }; + nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; -- cgit v0.10.2 From 7c38ca36cbfd149e6b9c970c0c6fd39b73ee24a6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 23 Nov 2015 13:26:15 +0100 Subject: ARM64: zynqmp: Add interrupt-controller property to gpio nodes GPIO driver supports an input interrupt that's why gpio node itself can be labeled as interrupt controller. Reported-by: John Linn Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index b68fb1a..4850608 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -581,6 +581,8 @@ compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; + #interrupt-cells = <2>; + interrupt-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff0a0000 0x1000>; -- cgit v0.10.2 From 33aec51742702e3a141973f485905a0f008c3dc6 Mon Sep 17 00:00:00 2001 From: Bharat Kumar Gogada Date: Mon, 15 Feb 2016 21:18:58 +0530 Subject: ARM64: zynqmp: Extend pcie node to support legacy interrupts Modifying device tree node to support legacy interrupts. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Ravi Kiran Gummaluri Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 4850608..ec6fc6a 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -629,6 +629,16 @@ <0x0 0xe0000000 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; }; qspi: spi@ff0f0000 { -- cgit v0.10.2 From 91a8b0ee69bde3a97e299bfa12828e4005512074 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 20 Jan 2016 12:59:23 +0100 Subject: ARM64: zynqmp: Fix coding style for pcie Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index ec6fc6a..98c07dc 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -619,10 +619,10 @@ #interrupt-cells = <1>; device_type = "pci"; interrupt-parent = <&gic>; - interrupts = < 0 118 4>, - < 0 116 4>, - < 0 115 4>, /* MSI_1 [63...32] */ - < 0 114 4 >; /* MSI_0 [31...0] */ + interrupts = <0 118 4>, + <0 116 4>, + <0 115 4>, /* MSI_1 [63...32] */ + <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "intx", "msi_1", "msi_0"; reg = <0x0 0xfd0e0000 0x1000>, <0x0 0xfd480000 0x1000>, -- cgit v0.10.2 From ca2f5878d6e6333fb78783662e004032e77f5577 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 27 Nov 2015 13:22:58 +0100 Subject: ARM64: zynqmp: Add backward compatible string for uart Mainline kernel has no r1p12 compatible string that's why console stops to work with the latest DTS files. Append generic compatible string. Keep in your mind that using this generic compatible string not all uart features will be available. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 98c07dc..f9249aa 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -775,7 +775,7 @@ }; uart0: serial@ff000000 { - compatible = "cdns,uart-r1p12"; + compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; @@ -785,7 +785,7 @@ }; uart1: serial@ff010000 { - compatible = "cdns,uart-r1p12"; + compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; -- cgit v0.10.2 From 4e31d27b9c2904144c5af6ed1975a8a1a31d93d3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 27 Jan 2016 19:04:56 +0100 Subject: ARM64: zynqmp: Align node address with parent node for dpdma Use right addresses for channel names Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index f9249aa..2690aa2 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -904,22 +904,22 @@ clock-names = "axi_clk"; dma-channels = <6>; #dma-cells = <1>; - dma-video0channel@43c10000 { + dma-video0channel@fd4c0000 { compatible = "xlnx,video0"; }; - dma-video1channel@43c10000 { + dma-video1channel@fd4c0000 { compatible = "xlnx,video1"; }; - dma-video2channel@43c10000 { + dma-video2channel@fd4c0000 { compatible = "xlnx,video2"; }; - dma-graphicschannel@43c10000 { + dma-graphicschannel@fd4c0000 { compatible = "xlnx,graphics"; }; - dma-audio0channel@43c10000 { + dma-audio0channel@fd4c0000 { compatible = "xlnx,audio0"; }; - dma-audio1channel@43c10000 { + dma-audio1channel@fd4c0000 { compatible = "xlnx,audio1"; }; }; -- cgit v0.10.2 From 695d75a122e48b95f4ccfffcbc39cb14be382b10 Mon Sep 17 00:00:00 2001 From: Hyun Kwon Date: Mon, 23 Nov 2015 17:12:54 -0800 Subject: ARM64: zynqmp: Use correct addresses in node names Reflect actual silicon addresses in DT node names. Signed-off-by: Hyun Kwon Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 2690aa2..5001ccc 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -842,7 +842,7 @@ }; }; - xlnx_dp: dp@43c00000 { + xlnx_dp: dp@fd4a0000 { compatible = "xlnx,v-dp"; status = "disabled"; reg = <0x0 0xfd4a0000 0x1000>; @@ -887,7 +887,7 @@ dma-names = "tx"; }; - xlnx_dp_sub: dp_sub@43c0a000 { + xlnx_dp_sub: dp_sub@fd4aa000 { compatible = "xlnx,dp-sub"; status = "disabled"; reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>; -- cgit v0.10.2 From 939cfeafec767ce0708ac10c1eaaa8e4227fcaa5 Mon Sep 17 00:00:00 2001 From: Hyun Kwon Date: Mon, 23 Nov 2015 17:12:55 -0800 Subject: ARM64: zynqmp: dp: Add default properties to zynqmp.dtsi Add some default properties to zynqmp.dtsi. Signed-off-by: Hyun Kwon Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 5001ccc..a1804b8 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -858,6 +858,7 @@ xlnx,bpc = <8>; xlnx,audio-chan = <2>; xlnx,dp-sub = <&xlnx_dp_sub>; + xlnx,max-pclock-frequency = <300000>; }; xlnx_dp_snd_card: dp_snd_card { @@ -893,6 +894,8 @@ reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>; reg-names = "blend", "av_buf", "aud"; xlnx,output-fmt = "rgb"; + xlnx,vid-fmt = "yuyv"; + xlnx,gfx-fmt = "rgb565"; }; xlnx_dpdma: dma@fd4c0000 { -- cgit v0.10.2 From c588d1544405cba91572583621f5faaa1d56f49a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 15:01:33 +0200 Subject: ARM64: zynqmp: Align register description Separate register space and put it on more lines. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index a1804b8..e2f7b53 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -648,7 +648,8 @@ interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; - reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>; + reg = <0x0 0xff0f0000 0x1000>, + <0x0 0xc0000000 0x8000000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_qspi>; @@ -891,7 +892,9 @@ xlnx_dp_sub: dp_sub@fd4aa000 { compatible = "xlnx,dp-sub"; status = "disabled"; - reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>; + reg = <0x0 0xfd4aa000 0x1000>, + <0x0 0xfd4ab000 0x1000>, + <0x0 0xfd4ac000 0x1000>; reg-names = "blend", "av_buf", "aud"; xlnx,output-fmt = "rgb"; xlnx,vid-fmt = "yuyv"; -- cgit v0.10.2 From 786db82bd5bf09cc8f78c8b14445e843d7566b1c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 27 Jan 2016 19:02:37 +0100 Subject: ARM64: zynqmp: Add serdes address space dp driver For run time serdes adjustment. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index e2f7b53..324d71b 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -846,7 +846,8 @@ xlnx_dp: dp@fd4a0000 { compatible = "xlnx,v-dp"; status = "disabled"; - reg = <0x0 0xfd4a0000 0x1000>; + reg = <0x0 0xfd4a0000 0x1000>, + <0x0 0xfd400000 0x20000>; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk"; -- cgit v0.10.2 From a84de48e7585cd4ebf8f353fb5b81d252be6e2e6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 15:06:07 +0200 Subject: ARM64: zynqmp: Fix DWC3 binding with the kernel Use the same binding as is used in mainline Linux kernel. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index ee9d0fe..1928b0b 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -23,6 +23,8 @@ spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; + usb0 = &usb0; + usb1 = &usb1; }; chosen { @@ -154,12 +156,20 @@ &usb0 { status = "okay"; +}; + +&dwc3_0 { + status = "okay"; dr_mode = "peripheral"; maximum-speed = "high-speed"; }; &usb1 { status = "okay"; +}; + +&dwc3_1 { + status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; }; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 324d71b..8413f16 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -796,23 +796,45 @@ }; usb0: usb@fe200000 { - compatible = "snps,dwc3"; + #address-cells = <2>; + #size-cells = <1>; status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 65 4>; - reg = <0x0 0xfe200000 0x40000>; - clock-names = "clk_xin", "clk_ahb"; + compatible = "xlnx,zynqmp-dwc3"; + clock-names = "bus_clk", "ref_clk"; + clocks = <&clk125>, <&clk125>; power-domains = <&pd_usb0>; + ranges; + + dwc3_0: dwc3@fe200000 { + compatible = "snps,dwc3"; + status = "disabled"; + reg = <0x0 0xfe200000 0x40000>; + interrupt-parent = <&gic>; + interrupts = <0 65 4>; + /* snps,quirk-frame-length-adjustment = <0x20>; */ + snps,refclk_fladj; + }; }; usb1: usb@fe300000 { - compatible = "snps,dwc3"; + #address-cells = <2>; + #size-cells = <1>; status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 70 4>; - reg = <0x0 0xfe300000 0x40000>; - clock-names = "clk_xin", "clk_ahb"; + compatible = "xlnx,zynqmp-dwc3"; + clock-names = "bus_clk", "ref_clk"; + clocks = <&clk125>, <&clk125>; power-domains = <&pd_usb1>; + ranges; + + dwc3_1: dwc3@fe300000 { + compatible = "snps,dwc3"; + status = "disabled"; + reg = <0x0 0xfe300000 0x40000>; + interrupt-parent = <&gic>; + interrupts = <0 70 4>; + /* snps,quirk-frame-length-adjustment = <0x20>; */ + snps,refclk_fladj; + }; }; watchdog0: watchdog@fd4d0000 { -- cgit v0.10.2 From 85d1142eb6cf1bc7f89fdbf67ba228896e158e0d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 15:07:38 +0200 Subject: ARM64: zynqmp: Use 64bit size cell format for memory node Enable option to support more then 4GB memories in single size block. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index 1928b0b..7fa0694 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -33,7 +33,7 @@ memory { device_type = "memory"; - reg = <0x0 0x0 0x40000000>; + reg = <0x0 0x0 0x0 0x40000000>; }; }; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 8413f16..fb95b48 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -10,7 +10,7 @@ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; - #size-cells = <1>; + #size-cells = <2>; cpus { #address-cells = <1>; @@ -247,7 +247,7 @@ compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; - ranges; + ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; @@ -266,7 +266,7 @@ compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; - ranges; + ranges = <0 0 0 0 0xffffffff>; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; -- cgit v0.10.2 From ac8f6913c4269663f3d61e1a4b9b52b2d9b1bb31 Mon Sep 17 00:00:00 2001 From: Anurag Kumar Vulisha Date: Thu, 5 Nov 2015 17:21:37 +0530 Subject: ARM64: zynqmp: Added OOB timing settings in zynqmp-ep108.dts This patch adds the sata port phy OOB timing values in the sata device-tree node. Signed-off-by: Anurag Kumar Vulisha Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index 7fa0694..e48a360 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -105,6 +105,15 @@ &sata { status = "okay"; ceva,broken-gen2; + /* SATA Phy OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; + ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; + ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>; + ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; + ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; + ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; }; &sdhci0 { -- cgit v0.10.2 From 4521202760d78533025fe3df4c7580f8bc97ae40 Mon Sep 17 00:00:00 2001 From: Punnaiah Choudary Kalluri Date: Thu, 5 Nov 2015 22:21:14 +0530 Subject: ARM64: zynqmp: Add missing nand node for ep108 Add missing nand node for ep108. Signed-off-by: Punnaiah Choudary Kalluri Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi index f864526..48bb426 100644 --- a/arch/arm/dts/zynqmp-ep108-clk.dtsi +++ b/arch/arm/dts/zynqmp-ep108-clk.dtsi @@ -62,6 +62,10 @@ clocks = <&i2c_clk>; }; +&nand0 { + clocks = <&misc_clk &misc_clk>; +}; + &qspi { clocks = <&misc_clk &misc_clk>; }; diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index e48a360..0bbf9a7 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -73,6 +73,37 @@ }; }; +&nand0 { + status = "okay"; + arasan,has-mdma; + num-cs = <1>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1C00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xFCC00000>; + }; +}; + &qspi { status = "okay"; flash@0 { -- cgit v0.10.2 From 885581a56bcf508cca87e3d6afe8987010fdcb6b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 4 Apr 2016 15:32:20 +0200 Subject: ARM64: zynqmp: Do not setup DM_ETH/GPIO/MMC by default for all boards There are mini configurations which need to be fit to OCM that's why these options shouldn't be enabled by default. Signed-off-by: Michal Simek diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f18dbe6..c8e0337 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -591,8 +591,6 @@ config ARCH_ZYNQMP select ARM64 select DM select OF_CONTROL - select DM_ETH - select DM_MMC select DM_SERIAL config TEGRA diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 91ae10a..c6e75d4 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -26,8 +26,10 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y CONFIG_NAND_ARASAN=y +CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y CONFIG_USB=y CONFIG_USB_GADGET=y -- cgit v0.10.2 From aa5b52f56c9fcafb485c930319a36f68692af30d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 22 Feb 2016 10:01:27 +0100 Subject: ARM64: zynqmp: Extend early malloc space to be able to run DM drivers DM drivers need more malloc space for early DM models allocation. Use 4k instead of 1k. Signed-off-by: Michal Simek diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index c6e75d4..9f72aba 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep" CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ZYNQMP_USB=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" -- cgit v0.10.2 From 658b3a563983281b6617f57b6bf2aee2c92a2101 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 1 Apr 2016 15:55:47 +0200 Subject: ARM64: zynqmp: Make DDR detection code work on 32bit system Define u64 types to be usable on 32bit system because of 64bit address and size cells and 32bit shifts in the code. Signed-off-by: Michal Simek diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 087578c..529476b 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -63,8 +63,8 @@ static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf, int address_cells = fdt_address_cells(fdt, parent_offset); int size_cells = fdt_size_cells(fdt, parent_offset); char *p = buf; - phys_addr_t val; - phys_size_t vals; + u64 val; + u64 vals; debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n", __func__, address_cells, size_cells, buf, cell); @@ -166,7 +166,7 @@ int dram_init(void) gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE); - debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size); + debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size); return 0; } -- cgit v0.10.2 From 52be5c05a06fc533655f63f1d1dd37b3b9e71231 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 11 Apr 2016 11:44:40 +0200 Subject: ARM64: zynqmp: Remove netdev.h from board file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Including netdev.h is causing compilation warning: + int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)); + ^ w+In file included from ../board/xilinx/zynqmp/zynqmp.c:9:0: w+../include/netdev.h:204:41: warning: ‘struct eth_device’ declared inside parameter list [enabled by default] w+../include/netdev.h:204:41: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default] This patch removes it. Signed-off-by: Michal Simek diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 529476b..132d724 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include -- cgit v0.10.2 From 1f4f3d33c7ba6b3d3f2d806b37e0f86cadf35885 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 15:58:23 +0200 Subject: ARM64: zynqmp: Add support for ZCU102 platform Add new board support. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 01cf030..da3be70 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -81,7 +81,9 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ - zynqmp-ep108.dtb + zynqmp-ep108.dtb \ + zynqmp-zcu102.dtb \ + zynqmp-zcu102-revB.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi new file mode 100644 index 0000000..3418909 --- /dev/null +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -0,0 +1,202 @@ +/* + * Clock specification for Xilinx ZynqMP + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +&amba { + clk100: clk100 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk125: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk200: clk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + clk250: clk250 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + clk300: clk300 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; + + clk600: clk600 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; + + dp_aclk: clock0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-accuracy = <100>; + }; + + dp_aud_clk: clock1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + clock-accuracy = <100>; + }; + + dpdma_clk: dpdma_clk { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <533000000>; + }; + + drm_clock: drm_clock { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <262750000>; + clock-accuracy = <0x64>; + }; +}; + +&can0 { + clocks = <&clk100 &clk100>; +}; + +&can1 { + clocks = <&clk100 &clk100>; +}; + +&fpd_dma_chan1 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan2 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan3 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan4 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan5 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan6 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan7 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan8 { + clocks = <&clk600>, <&clk100>; +}; + +&nand0 { + clocks = <&clk100 &clk100>; +}; + +&gem0 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gem1 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gem2 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gem3 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gpio { + clocks = <&clk100>; +}; + +&i2c0 { + clocks = <&clk100>; +}; + +&i2c1 { + clocks = <&clk100>; +}; + +&qspi { + clocks = <&clk300 &clk300>; +}; + +&sata { + clocks = <&clk250>; +}; + +&sdhci0 { + clocks = <&clk200 &clk200>; +}; + +&sdhci1 { + clocks = <&clk200 &clk200>; +}; + +&spi0 { + clocks = <&clk200 &clk200>; +}; + +&spi1 { + clocks = <&clk200 &clk200>; +}; + +&uart0 { + clocks = <&clk100 &clk100>; +}; + +&uart1 { + clocks = <&clk100 &clk100>; +}; + +&usb0 { + clocks = <&clk250>, <&clk250>; +}; + +&usb1 { + clocks = <&clk250>, <&clk250>; +}; + +&xilinx_drm { + clocks = <&drm_clock>; +}; + +&xlnx_dp { + clocks = <&dp_aclk>, <&dp_aud_clk>; +}; + +&xlnx_dpdma { + clocks = <&dpdma_clk>; +}; + +&xlnx_dp_snd_codec0 { + clocks = <&dp_aud_clk>; +}; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts new file mode 100644 index 0000000..765108e --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -0,0 +1,42 @@ +/* + * dts file for Xilinx ZynqMP ZCU102 RevB + * + * (C) Copyright 2016, Xilinx, Inc. + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "zynqmp-zcu102.dts" + +/ { + model = "ZynqMP ZCU102 RevB"; +}; + +&gem3 { + phy-handle = <&phyc>; + phyc: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; + /* Cleanup from RevA */ + /delete-node/ phy@21; +}; + +/* Different qspi 512Mbit version */ + +/* Fix collision with u61 */ +&i2c0 { + i2cswitch@75 { + i2c@2 { + max15303@1b { /* u8 */ + compatible = "max15303"; + reg = <0x1b>; + }; + /delete-node/ max15303@20; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-zcu102.dts b/arch/arm/dts/zynqmp-zcu102.dts new file mode 100644 index 0000000..de99602 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu102.dts @@ -0,0 +1,631 @@ +/* + * dts file for Xilinx ZynqMP ZCU102 + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP ZCU102 RevA"; + compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ + xlnx,overfetch; /* for testing purpose */ + xlnx,ratectrl = <0>; /* for testing purpose */ + xlnx,src-issue = <31>; +}; + +&fpd_dma_chan2 { + status = "okay"; + xlnx,ratectrl = <100>; /* for testing purpose */ + xlnx,src-issue = <4>; /* for testing purpose */ +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&gem3 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 90]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@21 { + reg = <21>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u97: gpio@20 { + /* + * Enable all GTs to out from U-Boot + * i2c mw 20 6 0 - setup IO to output + * i2c mw 20 2 ef - setup output values on pins 0-7 + * i2c mw 20 3 ff - setup output values on pins 10-17 + */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - PS_GTR_LAN_SEL0 + * 1 - PS_GTR_LAN_SEL1 + * 2 - PS_GTR_LAN_SEL2 + * 3 - PS_GTR_LAN_SEL3 + * 4 - PCI_CLK_DIR_SEL + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 7, 10 - 17 - not connected + */ + + gtr_sel0 { + gpio-hog; + gpios = <0 0>; + output-high; /* PCIE = 0, DP = 1 */ + line-name = "sel0"; + }; + gtr_sel1 { + gpio-hog; + gpios = <1 0>; + output-high; /* PCIE = 0, DP = 1 */ + line-name = "sel1"; + }; + gtr_sel2 { + gpio-hog; + gpios = <2 0>; + output-high; /* PCIE = 0, USB0 = 1 */ + line-name = "sel2"; + }; + gtr_sel3 { + gpio-hog; + gpios = <3 0>; + output-high; /* PCIE = 0, SATA = 1 */ + line-name = "sel3"; + }; + }; + + tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - VCCPSPLL_EN + * 1 - MGTRAVCC_EN + * 2 - MGTRAVTT_EN + * 3 - VCCPSDDRPLL_EN + * 4 - MIO26_PMU_INPUT_LS + * 5 - PL_PMBUS_ALERT + * 6 - PS_PMBUS_ALERT + * 7 - MAXIM_PMBUS_ALERT + * 10 - PL_DDR4_VTERM_EN + * 11 - PL_DDR4_VPP_2V5_EN + * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON + * 13 - PS_DIMM_SUSPEND_EN + * 14 - PS_DDR4_VTERM_EN + * 15 - PS_DDR4_VPP_2V5_EN + * 16 - 17 - not connected + */ + }; + + i2cswitch@75 { /* u60 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { /* i2c mw 75 0 1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + ina226@40 { /* u76 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + ina226@41 { /* u77 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u78 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u87 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@44 { /* u85 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u86 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u93 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + ina226@47 { /* u88 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + ina226@4a { /* u15 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + ina226@4b { /* u92 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { /* i2c mw 75 0 1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* PL_PMBUS */ + ina226@40 { /* u79 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + ina226@41 { /* u81 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u80 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u84 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@44 { /* u16 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u74 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + ina226@47 { /* u75 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { /* i2c mw 75 0 1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* MAXIM_PMBUS - 00 */ + max15301@a { /* u46 */ + compatible = "max15301"; + reg = <0xa>; + }; + max15303@b { /* u4 */ + compatible = "max15303"; + reg = <0xb>; + }; + max15303@10 { /* u13 */ + compatible = "max15303"; + reg = <0x10>; + }; + max15301@13 { /* u47 */ + compatible = "max15301"; + reg = <0x13>; + }; + max15303@14 { /* u7 */ + compatible = "max15303"; + reg = <0x14>; + }; + max15303@15 { /* u6 */ + compatible = "max15303"; + reg = <0x15>; + }; + max15303@16 { /* u10 */ + compatible = "max15303"; + reg = <0x16>; + }; + max15303@17 { /* u9 */ + compatible = "max15303"; + reg = <0x17>; + }; + max15301@18 { /* u63 */ + compatible = "max15301"; + reg = <0x18>; + }; + max15303@1a { /* u49 */ + compatible = "max15303"; + reg = <0x1a>; + }; + max15303@1d { /* u18 */ + compatible = "max15303"; + reg = <0x1d>; + }; + max15303@20 { /* u8 */ + compatible = "max15303"; + status = "disabled"; /* unreachable */ + reg = <0x20>; + }; + +/* drivers/hwmon/pmbus/Kconfig:86: be called max20751. +drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o +*/ + max20751@72 { /* u95 FIXME - not detected */ + compatible = "max20751"; + reg = <0x72>; + }; + max20751@73 { /* u96 FIXME - not detected */ + compatible = "max20751"; + reg = <0x73>; + }; + }; + /* Bus 3 is not connected */ + }; + + /* FIXME PL connection - u55 , PMOD - j160 */ + /* FIXME MSP430F - u41 - not detected */ +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + /* FIXME PL i2c via PCA9306 - u45 */ + /* FIXME MSP430 - u41 - not detected */ + i2cswitch@74 { /* u34 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { /* i2c mw 74 0 1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom@54 { /* u23 */ + compatible = "at,24c08"; + reg = <0x54>; + }; + }; + i2c@1 { /* i2c mw 74 0 2 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si5341: clock-generator1@36 { /* SI5341 - u69 */ + compatible = "si5341"; + reg = <0x36>; + }; + + }; + i2c@2 { /* i2c mw 74 0 4 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator2@5d { /* USER SI570 - u42 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + }; + }; + i2c@3 { /* i2c mw 74 0 8 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; /* copy from zc702 */ + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + i2c@4 { /* i2c mw 74 0 10 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si5328: clock-generator4@69 {/* SI5328 - u20 */ + compatible = "silabs,si5328"; + reg = <0x69>; + }; + }; + /* 5 - 7 unconnected */ + }; + + i2cswitch@75 { + compatible = "nxp,pca9548"; /* u135 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* HPC0_IIC */ + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* HPC1_IIC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { /* i2c mw 75 0 8 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + dev@19 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x19>; + }; + dev@30 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x30>; + }; + dev@35 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x35>; + }; + dev@36 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x36>; + }; + dev@51 { /* u-boot detection - maybe SPD */ + compatible = "xxx"; + reg = <0x51>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SEP 3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SEP 2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SEP 1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SEP 0 */ + }; + }; +}; + +&pcie { +/* status = "okay"; */ +}; + +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; /* for 1.0 silicon */ +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&xilinx_drm { + status = "okay"; + clocks = <&si570_1>; +}; + +&xlnx_dp { + status = "okay"; +}; + +&xlnx_dp_sub { + status = "okay"; + xlnx,vid-clk-pl; +}; + +&xlnx_dp_snd_pcm0 { + status = "okay"; +}; + +&xlnx_dp_snd_pcm1 { + status = "okay"; +}; + +&xlnx_dp_snd_card { + status = "okay"; +}; + +&xlnx_dp_snd_codec0 { + status = "okay"; +}; + +&xlnx_dpdma { + status = "okay"; +}; diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig new file mode 100644 index 0000000..50a957c --- /dev/null +++ b/configs/xilinx_zynqmp_zcu102_defconfig @@ -0,0 +1,34 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102" +CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_GPIO=y +CONFIG_ZYNQMP_USB=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_MMC=y +CONFIG_ZYNQ_SDHCI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_ZYNQ_GEM=y +CONFIG_USB=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h new file mode 100644 index 0000000..4f58020 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zcu102.h @@ -0,0 +1,56 @@ +/* + * Configuration for Xilinx ZynqMP zcu102 + * + * (C) Copyright 2015 Xilinx, Inc. + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZCU102_H +#define __CONFIG_ZYNQMP_ZCU102_H + +#define CONFIG_ZYNQ_SDHCI1 +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_ZYNQ_I2C1 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 18 +#define CONFIG_SYS_I2C_BUSES { \ + {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \ + {1, {I2C_NULL_HOP} }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ + } + +#define CONFIG_SYS_I2C_ZYNQ +#define CONFIG_AHCI +#define CONFIG_SATA_CEVA + +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} + +#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZCU102" + +#define CONFIG_KERNEL_FDT_OFST_SIZE \ + "kernel_offset=0x180000\0" \ + "fdt_offset=0x100000\0" \ + "kernel_size=0x1e00000\0" \ + "fdt_size=0x80000\0" \ + "board=zcu102\0" + +#include + +#endif /* __CONFIG_ZYNQMP_ZCU102_H */ -- cgit v0.10.2 From da81db61d562e473765bbe902f5ba21f1fd4806b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 11 Apr 2016 08:07:07 +0200 Subject: ARM64: zynqmp: Add defconfig for zcu102 revB board Support natively revB board. Till now support for revB was done via zcu102 defconfig where device-tree was changed to revB. This patch is adding direct defconfig for RevB. Signed-off-by: Michal Simek diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig new file mode 100644 index 0000000..5bd8248 --- /dev/null +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -0,0 +1,34 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102" +CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_GPIO=y +CONFIG_ZYNQMP_USB=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_MMC=y +CONFIG_ZYNQ_SDHCI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_ZYNQ_GEM=y +CONFIG_USB=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y -- cgit v0.10.2 From 6c0c958de8259d1163afd5f3b20206a0b6f61c54 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 16:00:11 +0200 Subject: ARM64: zynqmp: Add support for zc1751 with DC cards Support ZynqMP zc1751 with DC cards. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index da3be70..54a318a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -83,7 +83,10 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-ep108.dtb \ zynqmp-zcu102.dtb \ - zynqmp-zcu102-revB.dtb + zynqmp-zcu102-revB.dtb \ + zynqmp-zc1751-xm015-dc1.dtb \ + zynqmp-zc1751-xm016-dc2.dtb \ + zynqmp-zc1751-xm019-dc5.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts new file mode 100644 index 0000000..c68a41b --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -0,0 +1,211 @@ +/* + * dts file for Xilinx ZynqMP zc1751-xm015-dc1 + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP zc1751-xm015-dc1 RevA"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ + xlnx,overfetch; /* for testing purpose */ + xlnx,ratectrl = <0>; /* for testing purpose */ + xlnx,src-issue = <31>; +}; + +&fpd_dma_chan2 { + status = "okay"; + xlnx,ratectrl = <100>; /* for testing purpose */ + xlnx,src-issue = <4>; /* for testing purpose */ +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&gem3 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 90]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@0 { + reg = <0>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + eeprom@55 { + compatible = "at,24c64"; /* 24AA64 */ + reg = <0x55>; + }; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA phy OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +}; + +/* eMMC */ +&sdhci0 { + status = "okay"; + bus-width = <8>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; /* for 1.0 silicon */ +}; + +&uart0 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&xilinx_drm { + status = "okay"; +}; + +&xlnx_dp { + status = "okay"; +}; + +&xlnx_dp_sub { + status = "okay"; + xlnx,vid-clk-pl; +}; + +&xlnx_dp_snd_pcm0 { + status = "okay"; +}; + +&xlnx_dp_snd_pcm1 { + status = "okay"; +}; + +&xlnx_dp_snd_card { + status = "okay"; +}; + +&xlnx_dp_snd_codec0 { + status = "okay"; +}; + +&xlnx_dpdma { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts new file mode 100644 index 0000000..3fdfcc8 --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -0,0 +1,236 @@ +/* + * dts file for Xilinx ZynqMP zc1751-xm016-dc2 + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP zc1751-xm016-dc2 RevA"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + can0 = &can0; + can1 = &can1; + ethernet0 = &gem2; + gpio0 = &gpio; + i2c0 = &i2c0; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + spi0 = &spi0; + spi1 = &spi1; + usb0 = &usb1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ + xlnx,overfetch; /* for testing purpose */ + xlnx,ratectrl = <0>; /* for testing purpose */ + xlnx,src-issue = <31>; +}; + +&fpd_dma_chan2 { + status = "okay"; + xlnx,ratectrl = <100>; /* for testing purpose */ + xlnx,src-issue = <4>; /* for testing purpose */ +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&gem2 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 90]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@5 { + reg = <5>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u26: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + /* IRQ not connected */ + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&nand0 { + status = "okay"; + arasan,has-mdma; + num-cs = <2>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1C00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xFCC00000>; + }; + + partition@6 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; + reg = <0x1 0x0 0x400000>; + }; + partition@7 { /* for testing purpose */ + label = "nand1-linux"; + reg = <0x1 0x400000 0x1400000>; + }; + partition@8 { /* for testing purpose */ + label = "nand1-device-tree"; + reg = <0x1 0x1800000 0x400000>; + }; + partition@9 { /* for testing purpose */ + label = "nand1-rootfs"; + reg = <0x1 0x1C00000 0x1400000>; + }; + partition@10 { /* for testing purpose */ + label = "nand1-bitstream"; + reg = <0x1 0x3000000 0x400000>; + }; + partition@11 { /* for testing purpose */ + label = "nand1-misc"; + reg = <0x1 0x3400000 0xFCC00000>; + }; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; + num-cs = <1>; + spi0_flash0: spi0_flash0@0 { + compatible = "m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + spi0_flash0@00000000 { + label = "spi0_flash0"; + reg = <0x0 0x100000>; + }; + }; +}; + +&spi1 { + status = "okay"; + num-cs = <1>; + spi1_flash0: spi1_flash0@0 { + compatible = "mtd_dataflash"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + + spi1_flash0@00000000 { + label = "spi1_flash0"; + reg = <0x0 0x84000>; + }; + }; +}; + +/* ULPI SMSC USB3320 */ +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts new file mode 100644 index 0000000..d754f9f --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -0,0 +1,121 @@ +/* + * dts file for Xilinx ZynqMP zc1751-xm019-dc5 + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Siva Durga Prasad + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" +/ { + model = "ZynqMP zc1751-xm019-dc5 RevA"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem1; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + bootargs = "earlycon=cdns,mmio,0xff000000,115200n8"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ + xlnx,overfetch; /* for testing purpose */ + xlnx,ratectrl = <0>; /* for testing purpose */ + xlnx,src-issue = <31>; +}; + +&fpd_dma_chan2 { + status = "okay"; + xlnx,ratectrl = <100>; /* for testing purpose */ + xlnx,src-issue = <4>; /* for testing purpose */ +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&gem1 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 90]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@0 { + reg = <0>; + }; +}; + +&gpio { + status = "okay"; +}; + +/* FIXME: Add device */ +&i2c0 { + status = "okay"; +}; + +/* FIXME: Add device */ +&i2c1 { + status = "okay"; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig new file mode 100644 index 0000000..4a62a86 --- /dev/null +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -0,0 +1,34 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1" +CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_GPIO=y +CONFIG_ZYNQMP_USB=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_MMC=y +CONFIG_ZYNQ_SDHCI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_ZYNQ_GEM=y +CONFIG_USB=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig new file mode 100644 index 0000000..c4da7b1 --- /dev/null +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -0,0 +1,32 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2" +CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_GPIO=y +CONFIG_ZYNQMP_USB=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_MMC=y +CONFIG_NAND_ARASAN=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SST=y +CONFIG_DM_ETH=y +CONFIG_ZYNQ_GEM=y +CONFIG_USB=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig new file mode 100644 index 0000000..8bbee1b --- /dev/null +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5" +CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_GPIO=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y +CONFIG_DM_MMC=y +CONFIG_ZYNQ_SDHCI=y +CONFIG_DM_ETH=y diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h new file mode 100644 index 0000000..7aa9936 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h @@ -0,0 +1,31 @@ +/* + * Configuration for Xilinx ZynqMP zc1751 XM015 DC1 + * + * (C) Copyright 2015 Xilinx, Inc. + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H +#define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H + +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_SDHCI1 +#define CONFIG_ZYNQ_I2C1 +#define CONFIG_SYS_I2C_ZYNQ +#define CONFIG_AHCI +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} + +#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm015 dc1" + +#define CONFIG_KERNEL_FDT_OFST_SIZE \ + "kernel_offset=0x400000\0" \ + "fdt_offset=0x2400000\0" \ + "kernel_size=0x2000000\0" \ + "fdt_size=0x80000\0" \ + "board=zc1751-dc1\0" + +#include + +#endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */ diff --git a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h new file mode 100644 index 0000000..2727dc6 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h @@ -0,0 +1,28 @@ +/* + * Configuration for Xilinx ZynqMP zc1751 XM016 DC2 + * + * (C) Copyright 2015 Xilinx, Inc. + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H +#define __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H + +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_SYS_I2C_ZYNQ +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB1_XHCI_BASEADDR} + +#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm016 dc2" + +#define CONFIG_KERNEL_FDT_OFST_SIZE \ + "kernel_offset=0x400000\0" \ + "fdt_offset=0x2400000\0" \ + "kernel_size=0x2000000\0" \ + "fdt_size=0x80000\0" \ + "board=zc1751-dc2\0" + +#include + +#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */ diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h new file mode 100644 index 0000000..d9409ba --- /dev/null +++ b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h @@ -0,0 +1,30 @@ +/* + * Configuration for Xilinx ZynqMP zc1751 XM019 DC5 + * + * (C) Copyright 2015 Xilinx, Inc. + * Siva Durga Prasad + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H +#define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H + +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_ZYNQ_I2C1 +#define CONFIG_SYS_I2C_ZYNQ + +#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm019 dc5" + +#define CONFIG_KERNEL_FDT_OFST_SIZE \ + "kernel_offset=0x400000\0" \ + "fdt_offset=0x2400000\0" \ + "kernel_size=0x2000000\0" \ + "fdt_size=0x80000\0" \ + "board=zc1751-dc5\0" + +#include + +#endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */ -- cgit v0.10.2 From 08afaf1b4068772fd30ac50e570d6e490fdb3619 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 16:25:35 +0200 Subject: ARM64: zynqmp: Clean header after moving stuff to Kconfig Moving stuff to Kconfig by script is keep some empty lines or comment in the file. Remove them. Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index a603255..f7b4643 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -17,7 +17,6 @@ #define CONFIG_SYS_NO_FLASH - /* Generic Interrupt Controller Definitions */ #define CONFIG_GICV2 #define GICD_BASE 0xF9010000 @@ -44,8 +43,6 @@ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -/* Flat Device Tree Definitions */ - /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ #if !defined(COUNTER_FREQUENCY) # define COUNTER_FREQUENCY 100000000 -- cgit v0.10.2 From 68c7026e8d410295bc281128d8c14edef291461d Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 10 Mar 2016 16:27:38 +0530 Subject: gpio: zynq: Convert Zynq GPIO to driver model Convert Zynq GPIO driver to driver model Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 83a2c46..92c9f0e 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -14,6 +14,17 @@ #include #include +#ifdef CONFIG_DM_GPIO +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct zynq_gpio_privdata { + phys_addr_t base; +}; +#endif + /** * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank * for a given pin in the GPIO device @@ -68,6 +79,7 @@ static int check_gpio(unsigned gpio) return 0; } +#ifndef CONFIG_DM_GPIO /** * gpio_get_value - Get the state of the specified pin of GPIO device * @gpio: gpio pin number within the device @@ -218,3 +230,142 @@ int gpio_free(unsigned gpio) { return 0; } +#else +static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio) +{ + u32 data; + unsigned int bank_num, bank_pin_num; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + if (check_gpio(gpio) < 0) + return -1; + + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + + data = readl(priv->base + + ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); + + return (data >> bank_pin_num) & 1; +} + +static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value) +{ + unsigned int reg_offset, bank_num, bank_pin_num; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + if (check_gpio(gpio) < 0) + return -1; + + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + + if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { + /* only 16 data bits in bit maskable reg */ + bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; + reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); + } else { + reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); + } + + /* + * get the 32 bit value to be written to the mask/data register where + * the upper 16 bits is the mask and lower 16 bits is the data + */ + value = !!value; + value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & + ((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK); + + writel(value, priv->base + reg_offset); + + return 0; +} + +static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio) +{ + u32 reg; + unsigned int bank_num, bank_pin_num; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + if (check_gpio(gpio) < 0) + return -1; + + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + + /* bank 0 pins 7 and 8 are special and cannot be used as inputs */ + if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8)) + return -1; + + /* clear the bit in direction mode reg to set the pin as input */ + reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + reg &= ~BIT(bank_pin_num); + writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + + return 0; +} + +static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio, + int value) +{ + u32 reg; + unsigned int bank_num, bank_pin_num; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + if (check_gpio(gpio) < 0) + return -1; + + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + + /* set the GPIO pin as output */ + reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + reg |= BIT(bank_pin_num); + writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + + /* configure the output enable reg for the pin */ + reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); + reg |= BIT(bank_pin_num); + writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); + + /* set the state of the pin */ + gpio_set_value(gpio, value); + return 0; +} + +static const struct dm_gpio_ops gpio_zynq_ops = { + .direction_input = zynq_gpio_direction_input, + .direction_output = zynq_gpio_direction_output, + .get_value = zynq_gpio_get_value, + .set_value = zynq_gpio_set_value, +}; + +static int zynq_gpio_probe(struct udevice *dev) +{ + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + priv->base = dev_get_addr(dev); + + return 0; +} + +static int zynq_gpio_ofdata_to_platdata(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->gpio_count = ZYNQ_GPIO_NR_GPIOS; + + return 0; +} + +static const struct udevice_id zynq_gpio_ids[] = { + { .compatible = "xlnx,zynq-gpio-1.0" }, + { } +}; + +U_BOOT_DRIVER(gpio_zynq) = { + .name = "gpio_zynq", + .id = UCLASS_GPIO, + .ops = &gpio_zynq_ops, + .of_match = zynq_gpio_ids, + .ofdata_to_platdata = zynq_gpio_ofdata_to_platdata, + .probe = zynq_gpio_probe, + .priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata), +}; +#endif -- cgit v0.10.2 From 2978ae23fa252659ccfae9c794105a5d7e1ffc76 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 10 Mar 2016 16:27:39 +0530 Subject: gpio: Kconfig: Enable Zynq GPIO driver using kconfig Enable DM GPIO and ZYNQ GPIO using kconfig instead of the board config file. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c8e0337..802d3b4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -579,6 +579,7 @@ config ARCH_ZYNQ select SPL_OF_CONTROL if SPL select DM select DM_ETH + select DM_GPIO select SPL_DM if SPL select DM_MMC select DM_SPI diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f56a606..4d2cc50 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -136,4 +136,11 @@ config MVEBU_GPIO help Say yes here to support Marvell MVEBU (Armada XP/38x) GPIOs. +config ZYNQ_GPIO + bool "Zynq GPIO driver" + depends on DM_GPIO && ARCH_ZYNQ + default y + help + Supports GPIO access on Zynq SoC. + endmenu diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index c96b9c5..49d9fd0 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -39,8 +39,6 @@ #define CONFIG_ARM_DCC #define CONFIG_ZYNQ_SERIAL -#define CONFIG_ZYNQ_GPIO - /* Ethernet driver */ #if defined(CONFIG_ZYNQ_GEM) # define CONFIG_MII -- cgit v0.10.2 From de77a03bf22431297e968fd276a27e753ee2a603 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 10 Mar 2016 16:27:40 +0530 Subject: gpio: zynq: Remove non driver model code Remove non driver model support as it moved to driver model. Dont need non driver model anymore. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/arch/arm/mach-zynq/include/mach/gpio.h b/arch/arm/mach-zynq/include/mach/gpio.h index 0789c49..956492b 100644 --- a/arch/arm/mach-zynq/include/mach/gpio.h +++ b/arch/arm/mach-zynq/include/mach/gpio.h @@ -8,8 +8,6 @@ #ifndef _ZYNQ_GPIO_H #define _ZYNQ_GPIO_H -#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000 - /* Maximum banks */ #define ZYNQ_GPIO_MAX_BANK 4 diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 92c9f0e..07c2eb5 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -13,8 +13,6 @@ #include #include #include - -#ifdef CONFIG_DM_GPIO #include #include @@ -23,7 +21,6 @@ DECLARE_GLOBAL_DATA_PTR; struct zynq_gpio_privdata { phys_addr_t base; }; -#endif /** * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank @@ -65,7 +62,7 @@ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, } } -int gpio_is_valid(unsigned gpio) +static int gpio_is_valid(unsigned gpio) { return (gpio >= 0) && (gpio < ZYNQ_GPIO_NR_GPIOS); } @@ -79,158 +76,6 @@ static int check_gpio(unsigned gpio) return 0; } -#ifndef CONFIG_DM_GPIO -/** - * gpio_get_value - Get the state of the specified pin of GPIO device - * @gpio: gpio pin number within the device - * - * This function reads the state of the specified pin of the GPIO device. - * - * Return: 0 if the pin is low, 1 if pin is high. - */ -int gpio_get_value(unsigned gpio) -{ - u32 data; - unsigned int bank_num, bank_pin_num; - - if (check_gpio(gpio) < 0) - return -1; - - zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); - - data = readl(ZYNQ_GPIO_BASE_ADDRESS + - ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); - - return (data >> bank_pin_num) & 1; -} - -/** - * gpio_set_value - Modify the value of the pin with specified value - * @gpio: gpio pin number within the device - * @value: value used to modify the value of the specified pin - * - * This function calculates the register offset (i.e to lower 16 bits or - * upper 16 bits) based on the given pin number and sets the value of a - * gpio pin to the specified value. The value is either 0 or non-zero. - */ -int gpio_set_value(unsigned gpio, int value) -{ - unsigned int reg_offset, bank_num, bank_pin_num; - - if (check_gpio(gpio) < 0) - return -1; - - zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); - - if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { - /* only 16 data bits in bit maskable reg */ - bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; - reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); - } else { - reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); - } - - /* - * get the 32 bit value to be written to the mask/data register where - * the upper 16 bits is the mask and lower 16 bits is the data - */ - value = !!value; - value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & - ((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK); - - writel(value, ZYNQ_GPIO_BASE_ADDRESS + reg_offset); - - return 0; -} - -/** - * gpio_direction_input - Set the direction of the specified GPIO pin as input - * @gpio: gpio pin number within the device - * - * This function uses the read-modify-write sequence to set the direction of - * the gpio pin as input. - * - * Return: -1 if invalid gpio specified, 0 if successul - */ -int gpio_direction_input(unsigned gpio) -{ - u32 reg; - unsigned int bank_num, bank_pin_num; - - if (check_gpio(gpio) < 0) - return -1; - - zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); - - /* bank 0 pins 7 and 8 are special and cannot be used as inputs */ - if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8)) - return -1; - - /* clear the bit in direction mode reg to set the pin as input */ - reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); - reg &= ~BIT(bank_pin_num); - writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); - - return 0; -} - -/** - * gpio_direction_output - Set the direction of the specified GPIO pin as output - * @gpio: gpio pin number within the device - * @value: value to be written to specified pin - * - * This function sets the direction of specified GPIO pin as output, configures - * the Output Enable register for the pin and uses zynq_gpio_set to set - * the value of the pin to the value specified. - * - * Return: 0 always - */ -int gpio_direction_output(unsigned gpio, int value) -{ - u32 reg; - unsigned int bank_num, bank_pin_num; - - if (check_gpio(gpio) < 0) - return -1; - - zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); - - /* set the GPIO pin as output */ - reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); - reg |= BIT(bank_pin_num); - writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); - - /* configure the output enable reg for the pin */ - reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); - reg |= BIT(bank_pin_num); - writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); - - /* set the state of the pin */ - gpio_set_value(gpio, value); - return 0; -} - -/** - * Request a gpio before using it. - * - * NOTE: Argument 'label' is unused. - */ -int gpio_request(unsigned gpio, const char *label) -{ - if (check_gpio(gpio) < 0) - return -1; - - return 0; -} - -/** - * Reset and free the gpio after using it. - */ -int gpio_free(unsigned gpio) -{ - return 0; -} -#else static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio) { u32 data; @@ -368,4 +213,3 @@ U_BOOT_DRIVER(gpio_zynq) = { .probe = zynq_gpio_probe, .priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata), }; -#endif -- cgit v0.10.2 From f17abcaedb8f2ed37b7e9361d4171f03ba25279a Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 10 Mar 2016 16:27:42 +0530 Subject: gpio: zynq: Move the definitions to driver file Move all the gpio definitions to driver file as there is no use of them in other files. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/arch/arm/mach-zynq/include/mach/gpio.h b/arch/arm/mach-zynq/include/mach/gpio.h index 956492b..f3dfd65 100644 --- a/arch/arm/mach-zynq/include/mach/gpio.h +++ b/arch/arm/mach-zynq/include/mach/gpio.h @@ -8,65 +8,4 @@ #ifndef _ZYNQ_GPIO_H #define _ZYNQ_GPIO_H -/* Maximum banks */ -#define ZYNQ_GPIO_MAX_BANK 4 - -#define ZYNQ_GPIO_BANK0_NGPIO 32 -#define ZYNQ_GPIO_BANK1_NGPIO 22 -#define ZYNQ_GPIO_BANK2_NGPIO 32 -#define ZYNQ_GPIO_BANK3_NGPIO 32 - -#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \ - ZYNQ_GPIO_BANK1_NGPIO + \ - ZYNQ_GPIO_BANK2_NGPIO + \ - ZYNQ_GPIO_BANK3_NGPIO) - -#define ZYNQ_GPIO_BANK0_PIN_MIN 0 -#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \ - ZYNQ_GPIO_BANK0_NGPIO - 1) -#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \ - ZYNQ_GPIO_BANK1_NGPIO - 1) -#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \ - ZYNQ_GPIO_BANK2_NGPIO - 1) -#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \ - ZYNQ_GPIO_BANK3_NGPIO - 1) - -/* Register offsets for the GPIO device */ -/* LSW Mask & Data -WO */ -#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) -/* MSW Mask & Data -WO */ -#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) -/* Data Register-RW */ -#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) -/* Direction mode reg-RW */ -#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) -/* Output enable reg-RW */ -#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) -/* Interrupt mask reg-RO */ -#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) -/* Interrupt enable reg-WO */ -#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) -/* Interrupt disable reg-WO */ -#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) -/* Interrupt status reg-RO */ -#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) -/* Interrupt type reg-RW */ -#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) -/* Interrupt polarity reg-RW */ -#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) -/* Interrupt on any, reg-RW */ -#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) - -/* Disable all interrupts mask */ -#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF - -/* Mid pin number of a bank */ -#define ZYNQ_GPIO_MID_PIN_NUM 16 - -/* GPIO upper 16 bit mask */ -#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 - #endif /* _ZYNQ_GPIO_H */ diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 07c2eb5..05de9c5 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -18,6 +18,67 @@ DECLARE_GLOBAL_DATA_PTR; +/* Maximum banks */ +#define ZYNQ_GPIO_MAX_BANK 4 + +#define ZYNQ_GPIO_BANK0_NGPIO 32 +#define ZYNQ_GPIO_BANK1_NGPIO 22 +#define ZYNQ_GPIO_BANK2_NGPIO 32 +#define ZYNQ_GPIO_BANK3_NGPIO 32 + +#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \ + ZYNQ_GPIO_BANK1_NGPIO + \ + ZYNQ_GPIO_BANK2_NGPIO + \ + ZYNQ_GPIO_BANK3_NGPIO) + +#define ZYNQ_GPIO_BANK0_PIN_MIN 0 +#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \ + ZYNQ_GPIO_BANK0_NGPIO - 1) +#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1) +#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \ + ZYNQ_GPIO_BANK1_NGPIO - 1) +#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1) +#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \ + ZYNQ_GPIO_BANK2_NGPIO - 1) +#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1) +#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \ + ZYNQ_GPIO_BANK3_NGPIO - 1) + +/* Register offsets for the GPIO device */ +/* LSW Mask & Data -WO */ +#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) +/* MSW Mask & Data -WO */ +#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) +/* Data Register-RW */ +#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) +/* Direction mode reg-RW */ +#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) +/* Output enable reg-RW */ +#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) +/* Interrupt mask reg-RO */ +#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) +/* Interrupt enable reg-WO */ +#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) +/* Interrupt disable reg-WO */ +#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) +/* Interrupt status reg-RO */ +#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) +/* Interrupt type reg-RW */ +#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) +/* Interrupt polarity reg-RW */ +#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) +/* Interrupt on any, reg-RW */ +#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) + +/* Disable all interrupts mask */ +#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF + +/* Mid pin number of a bank */ +#define ZYNQ_GPIO_MID_PIN_NUM 16 + +/* GPIO upper 16 bit mask */ +#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 + struct zynq_gpio_privdata { phys_addr_t base; }; -- cgit v0.10.2 From 404a00c7c9fff1ef2ba5e33c585ff3c950757f34 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 10 Mar 2016 16:27:43 +0530 Subject: gpio: zynqmp: Add GPIO driver support for ZynqMP Add GPIO driver support for ZynqMP platform Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 05de9c5..3a995f6 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -31,18 +31,35 @@ DECLARE_GLOBAL_DATA_PTR; ZYNQ_GPIO_BANK2_NGPIO + \ ZYNQ_GPIO_BANK3_NGPIO) -#define ZYNQ_GPIO_BANK0_PIN_MIN 0 -#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \ - ZYNQ_GPIO_BANK0_NGPIO - 1) -#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \ - ZYNQ_GPIO_BANK1_NGPIO - 1) -#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \ - ZYNQ_GPIO_BANK2_NGPIO - 1) -#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \ - ZYNQ_GPIO_BANK3_NGPIO - 1) +#define ZYNQMP_GPIO_MAX_BANK 6 + +#define ZYNQMP_GPIO_BANK0_NGPIO 26 +#define ZYNQMP_GPIO_BANK1_NGPIO 26 +#define ZYNQMP_GPIO_BANK2_NGPIO 26 +#define ZYNQMP_GPIO_BANK3_NGPIO 32 +#define ZYNQMP_GPIO_BANK4_NGPIO 32 +#define ZYNQMP_GPIO_BANK5_NGPIO 32 + +#define ZYNQMP_GPIO_NR_GPIOS 174 + +#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0 +#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK0_NGPIO - 1) +#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK1_NGPIO - 1) +#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK2_NGPIO - 1) +#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK3_NGPIO - 1) +#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK4_NGPIO - 1) +#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK5_NGPIO - 1) /* Register offsets for the GPIO device */ /* LSW Mask & Data -WO */ @@ -81,6 +98,55 @@ DECLARE_GLOBAL_DATA_PTR; struct zynq_gpio_privdata { phys_addr_t base; + const struct zynq_platform_data *p_data; +}; + +/** + * struct zynq_platform_data - zynq gpio platform data structure + * @label: string to store in gpio->label + * @ngpio: max number of gpio pins + * @max_bank: maximum number of gpio banks + * @bank_min: this array represents bank's min pin + * @bank_max: this array represents bank's max pin + */ +struct zynq_platform_data { + const char *label; + u16 ngpio; + int max_bank; + int bank_min[ZYNQMP_GPIO_MAX_BANK]; + int bank_max[ZYNQMP_GPIO_MAX_BANK]; +}; + +static const struct zynq_platform_data zynqmp_gpio_def = { + .label = "zynqmp_gpio", + .ngpio = ZYNQMP_GPIO_NR_GPIOS, + .max_bank = ZYNQMP_GPIO_MAX_BANK, + .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), + .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP), + .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP), + .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP), + .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP), + .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP), + .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP), + .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP), + .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP), + .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP), + .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP), + .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP), +}; + +static const struct zynq_platform_data zynq_gpio_def = { + .label = "zynq_gpio", + .ngpio = ZYNQ_GPIO_NR_GPIOS, + .max_bank = ZYNQ_GPIO_MAX_BANK, + .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), + .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(), + .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(), + .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(), + .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(), + .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(), + .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(), + .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(), }; /** @@ -96,41 +162,39 @@ struct zynq_gpio_privdata { */ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, unsigned int *bank_num, - unsigned int *bank_pin_num) + unsigned int *bank_pin_num, + struct udevice *dev) { - switch (pin_num) { - case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX: - *bank_num = 0; - *bank_pin_num = pin_num; - break; - case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX: - *bank_num = 1; - *bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN; - break; - case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX: - *bank_num = 2; - *bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN; - break; - case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX: - *bank_num = 3; - *bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN; - break; - default: - printf("invalid GPIO pin number: %u\n", pin_num); + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + int bank; + + for (bank = 0; bank < priv->p_data->max_bank; bank++) { + if ((pin_num >= priv->p_data->bank_min[bank]) && + (pin_num <= priv->p_data->bank_max[bank])) { + *bank_num = bank; + *bank_pin_num = pin_num - + priv->p_data->bank_min[bank]; + return; + } + } + + if (bank >= priv->p_data->max_bank) { + printf("Inavlid bank and pin num\n"); *bank_num = 0; *bank_pin_num = 0; - break; } } -static int gpio_is_valid(unsigned gpio) +static int gpio_is_valid(unsigned gpio, struct udevice *dev) { - return (gpio >= 0) && (gpio < ZYNQ_GPIO_NR_GPIOS); + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + return (gpio >= 0) && (gpio < priv->p_data->ngpio); } -static int check_gpio(unsigned gpio) +static int check_gpio(unsigned gpio, struct udevice *dev) { - if (!gpio_is_valid(gpio)) { + if (!gpio_is_valid(gpio, dev)) { printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); return -1; } @@ -143,10 +207,10 @@ static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio) unsigned int bank_num, bank_pin_num; struct zynq_gpio_privdata *priv = dev_get_priv(dev); - if (check_gpio(gpio) < 0) + if (check_gpio(gpio, dev) < 0) return -1; - zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); data = readl(priv->base + ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); @@ -159,10 +223,10 @@ static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value) unsigned int reg_offset, bank_num, bank_pin_num; struct zynq_gpio_privdata *priv = dev_get_priv(dev); - if (check_gpio(gpio) < 0) + if (check_gpio(gpio, dev) < 0) return -1; - zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { /* only 16 data bits in bit maskable reg */ @@ -191,10 +255,10 @@ static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio) unsigned int bank_num, bank_pin_num; struct zynq_gpio_privdata *priv = dev_get_priv(dev); - if (check_gpio(gpio) < 0) + if (check_gpio(gpio, dev) < 0) return -1; - zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); /* bank 0 pins 7 and 8 are special and cannot be used as inputs */ if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8)) @@ -215,10 +279,10 @@ static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio, unsigned int bank_num, bank_pin_num; struct zynq_gpio_privdata *priv = dev_get_priv(dev); - if (check_gpio(gpio) < 0) + if (check_gpio(gpio, dev) < 0) return -1; - zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); /* set the GPIO pin as output */ reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); @@ -242,29 +306,59 @@ static const struct dm_gpio_ops gpio_zynq_ops = { .set_value = zynq_gpio_set_value, }; +static const struct udevice_id zynq_gpio_ids[] = { + { .compatible = "xlnx,zynq-gpio-1.0", + .data = (ulong)&zynq_gpio_def}, + { .compatible = "xlnx,zynqmp-gpio-1.0", + .data = (ulong)&zynqmp_gpio_def}, + { } +}; + +static void zynq_gpio_getplat_data(struct udevice *dev) +{ + const struct udevice_id *of_match = zynq_gpio_ids; + int ret; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + while (of_match->compatible) { + ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, + of_match->compatible); + if (ret >= 0) { + priv->p_data = + (struct zynq_platform_data *)of_match->data; + break; + } else { + of_match++; + continue; + } + } + + if (!priv->p_data) + printf("No Platform data found\n"); +} + static int zynq_gpio_probe(struct udevice *dev) { struct zynq_gpio_privdata *priv = dev_get_priv(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - priv->base = dev_get_addr(dev); + zynq_gpio_getplat_data(dev); + + if (priv->p_data) + uc_priv->gpio_count = priv->p_data->ngpio; return 0; } static int zynq_gpio_ofdata_to_platdata(struct udevice *dev) { - struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct zynq_gpio_privdata *priv = dev_get_priv(dev); - uc_priv->gpio_count = ZYNQ_GPIO_NR_GPIOS; + priv->base = dev_get_addr(dev); return 0; } -static const struct udevice_id zynq_gpio_ids[] = { - { .compatible = "xlnx,zynq-gpio-1.0" }, - { } -}; - U_BOOT_DRIVER(gpio_zynq) = { .name = "gpio_zynq", .id = UCLASS_GPIO, -- cgit v0.10.2 From 251ab06d26da25bb003117df219288f8e57cabac Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 10 Mar 2016 16:27:44 +0530 Subject: zynqmp: Kconfig: Enable ZYNQ_GPIO for ZynqMP Enable ZYNQ_GPIO for ZynqMP using Kconfig. It enables the GPIO driver support for ZynqMP. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 4d2cc50..2b4624d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -138,7 +138,7 @@ config MVEBU_GPIO config ZYNQ_GPIO bool "Zynq GPIO driver" - depends on DM_GPIO && ARCH_ZYNQ + depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP) default y help Supports GPIO access on Zynq SoC. -- cgit v0.10.2 From f746b4cfd0aa6ccf7fd2c821d6813eed3f88d427 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 11 Apr 2016 11:33:26 +0200 Subject: ARM64: zynqmp: Enable CMD_GPIO and DM_GPIO for ep108 Enable missing GPIO options. Signed-off-by: Michal Simek diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 9f72aba..b45c7f2 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_DM_GPIO=y CONFIG_ZYNQMP_USB=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" @@ -17,6 +18,7 @@ CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y -- cgit v0.10.2 From 01b2a69907a259642be2ff625008b5b9a65a9996 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 11 Apr 2016 13:51:26 +0200 Subject: GPIO: pca953x: Remove compilation warnings on arm64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Warnings: w+../drivers/gpio/pca953x.c: In function ‘do_pca953x’: w+../drivers/gpio/pca953x.c:220:5: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] w+../drivers/gpio/pca953x.c:233:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] Signed-off-by: Michal Simek diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index 932dfe9..238e028 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -217,7 +217,7 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* All commands but "device" require 'maxargs' arguments */ if (!c || !((argc == (c->maxargs)) || - (((int)c->cmd == PCA953X_CMD_DEVICE) && + (((long)c->cmd == PCA953X_CMD_DEVICE) && (argc == (c->maxargs - 1))))) { return CMD_RET_USAGE; } @@ -230,7 +230,7 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc > 3) ul_arg3 = simple_strtoul(argv[3], NULL, 16) & 0x1; - switch ((int)c->cmd) { + switch ((long)c->cmd) { #ifdef CONFIG_CMD_PCA953X_INFO case PCA953X_CMD_INFO: ret = pca953x_info(chip); -- cgit v0.10.2 From ff9bd8e9cadd4a8362684fabea6e6a0b4fed63a5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 11 Apr 2016 13:48:32 +0200 Subject: ARM64: zynqmp: Enable pca953x driver for zcu102 zcu102 has two pca953x on i2c bus 0. Chips 0x20 and 0x21. Enable option to work with these two chips. Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h index 4f58020..30db2e4 100644 --- a/include/configs/xilinx_zynqmp_zcu102.h +++ b/include/configs/xilinx_zynqmp_zcu102.h @@ -37,6 +37,10 @@ } #define CONFIG_SYS_I2C_ZYNQ +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO + #define CONFIG_AHCI #define CONFIG_SATA_CEVA -- cgit v0.10.2 From 17573c2791a76acd71fa82db513f31e965aa641b Mon Sep 17 00:00:00 2001 From: Moritz Fischer Date: Mon, 28 Dec 2015 09:47:10 -0800 Subject: i2c: Describe Cadence I2C devicetree bindings Signed-off-by: Moritz Fischer Reviewed-by: Heiko Schocher Signed-off-by: Michal Simek diff --git a/doc/device-tree-bindings/i2c/i2c-cdns.txt b/doc/device-tree-bindings/i2c/i2c-cdns.txt new file mode 100644 index 0000000..202e0b7 --- /dev/null +++ b/doc/device-tree-bindings/i2c/i2c-cdns.txt @@ -0,0 +1,20 @@ +Cadence I2C controller Device Tree Bindings +------------------------------------------- + +Required properties: +- compatible : Should be "cdns,i2c-r1p10" or "xlnx,zynq-spi-r1p10". +- reg : Physical base address and size of I2C registers map. +- interrupts : Property with a value describing the interrupt + number. +- interrupt-parent : Must be core interrupt controller +- clocks : Clock phandles (see clock bindings for details). + +Example: + i2c0: i2c@e0004000 { + compatible = "cdns,i2c-r1p10"; + reg = <0xe0004000 0x1000>; + clocks = <&clkc 38>; + interrupts = <0 25 4>; + interrupt-parent = <&intc>; + status = "disabled"; + }; -- cgit v0.10.2 From fdec2d21ef8e27dbb01177da53b2bf5167a3dd97 Mon Sep 17 00:00:00 2001 From: Moritz Fischer Date: Mon, 28 Dec 2015 09:47:11 -0800 Subject: dm: i2c: Add driver for Cadence I2C IP This is a possible drop in replacement for drivers/i2c/zynq-i2c.c Since this is cadence IP it has been renamed to cdns-i2c, to make sense with the compatible string. Signed-off-by: Moritz Fischer Reviewed-by: Heiko Schocher Signed-off-by: Michal Simek diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 46b83e7..9324c6c 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -58,6 +58,13 @@ config DM_I2C_GPIO bindings are supported. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt +config SYS_I2C_CADENCE + tristate "Cadence I2C Controller" + depends on DM_I2C && (ARCH_ZYNQ || ARM64) + help + Say yes here to select Cadence I2C Host Controller. This controller is + e.g. used by Xilinx Zynq. + config SYS_I2C_INTEL bool "Intel I2C/SMBUS driver" depends on DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index c75c579..167424d 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c new file mode 100644 index 0000000..909cea2 --- /dev/null +++ b/drivers/i2c/i2c-cdns.c @@ -0,0 +1,335 @@ +/* + * Copyright (C) 2015 Moritz Fischer + * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2) + * + * This file is based on: drivers/i2c/zynq_i2c.c, + * with added driver-model support and code cleanup. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* i2c register set */ +struct cdns_i2c_regs { + u32 control; + u32 status; + u32 address; + u32 data; + u32 interrupt_status; + u32 transfer_size; + u32 slave_mon_pause; + u32 time_out; + u32 interrupt_mask; + u32 interrupt_enable; + u32 interrupt_disable; +}; + +/* Control register fields */ +#define CDNS_I2C_CONTROL_RW 0x00000001 +#define CDNS_I2C_CONTROL_MS 0x00000002 +#define CDNS_I2C_CONTROL_NEA 0x00000004 +#define CDNS_I2C_CONTROL_ACKEN 0x00000008 +#define CDNS_I2C_CONTROL_HOLD 0x00000010 +#define CDNS_I2C_CONTROL_SLVMON 0x00000020 +#define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040 +#define CDNS_I2C_CONTROL_DIV_B_SHIFT 8 +#define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00 +#define CDNS_I2C_CONTROL_DIV_A_SHIFT 14 +#define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000 + +/* Status register values */ +#define CDNS_I2C_STATUS_RXDV 0x00000020 +#define CDNS_I2C_STATUS_TXDV 0x00000040 +#define CDNS_I2C_STATUS_RXOVF 0x00000080 +#define CDNS_I2C_STATUS_BA 0x00000100 + +/* Interrupt register fields */ +#define CDNS_I2C_INTERRUPT_COMP 0x00000001 +#define CDNS_I2C_INTERRUPT_DATA 0x00000002 +#define CDNS_I2C_INTERRUPT_NACK 0x00000004 +#define CDNS_I2C_INTERRUPT_TO 0x00000008 +#define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010 +#define CDNS_I2C_INTERRUPT_RXOVF 0x00000020 +#define CDNS_I2C_INTERRUPT_TXOVF 0x00000040 +#define CDNS_I2C_INTERRUPT_RXUNF 0x00000080 +#define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200 + +#define CDNS_I2C_FIFO_DEPTH 16 +#define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */ + +#ifdef DEBUG +static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c) +{ + int int_status; + int status; + int_status = readl(&cdns_i2c->interrupt_status); + + status = readl(&cdns_i2c->status); + if (int_status || status) { + debug("Status: "); + if (int_status & CDNS_I2C_INTERRUPT_COMP) + debug("COMP "); + if (int_status & CDNS_I2C_INTERRUPT_DATA) + debug("DATA "); + if (int_status & CDNS_I2C_INTERRUPT_NACK) + debug("NACK "); + if (int_status & CDNS_I2C_INTERRUPT_TO) + debug("TO "); + if (int_status & CDNS_I2C_INTERRUPT_SLVRDY) + debug("SLVRDY "); + if (int_status & CDNS_I2C_INTERRUPT_RXOVF) + debug("RXOVF "); + if (int_status & CDNS_I2C_INTERRUPT_TXOVF) + debug("TXOVF "); + if (int_status & CDNS_I2C_INTERRUPT_RXUNF) + debug("RXUNF "); + if (int_status & CDNS_I2C_INTERRUPT_ARBLOST) + debug("ARBLOST "); + if (status & CDNS_I2C_STATUS_RXDV) + debug("RXDV "); + if (status & CDNS_I2C_STATUS_TXDV) + debug("TXDV "); + if (status & CDNS_I2C_STATUS_RXOVF) + debug("RXOVF "); + if (status & CDNS_I2C_STATUS_BA) + debug("BA "); + debug("TS%d ", readl(&cdns_i2c->transfer_size)); + debug("\n"); + } +} +#endif + +struct i2c_cdns_bus { + int id; + struct cdns_i2c_regs __iomem *regs; /* register base */ +}; + + +/** cdns_i2c_probe() - Probe method + * @dev: udevice pointer + * + * DM callback called when device is probed + */ +static int cdns_i2c_probe(struct udevice *dev) +{ + struct i2c_cdns_bus *bus = dev_get_priv(dev); + + bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev); + if (!bus->regs) + return -ENOMEM; + + /* TODO: Calculate dividers based on CPU_CLK_1X */ + /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */ + writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) | + (2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control); + + /* Enable master mode, ack, and 7-bit addressing */ + setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS | + CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA); + + debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs); + + return 0; +} + +static int cdns_i2c_remove(struct udevice *dev) +{ + struct i2c_cdns_bus *bus = dev_get_priv(dev); + + debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs); + + unmap_sysmem(bus->regs); + + return 0; +} + +/* Wait for an interrupt */ +static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask) +{ + int timeout, int_status; + + for (timeout = 0; timeout < 100; timeout++) { + udelay(100); + int_status = readl(&cdns_i2c->interrupt_status); + if (int_status & mask) + break; + } + + /* Clear interrupt status flags */ + writel(int_status & mask, &cdns_i2c->interrupt_status); + + return int_status & mask; +} + +static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) +{ + if (speed != 100000) { + printf("%s, failed to set clock speed to %u\n", __func__, + speed); + return -EINVAL; + } + + return 0; +} + +/* Probe to see if a chip is present. */ +static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) +{ + struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus); + struct cdns_i2c_regs *regs = i2c_bus->regs; + + /* Attempt to read a byte */ + setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | + CDNS_I2C_CONTROL_RW); + clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); + writel(0xFF, ®s->interrupt_status); + writel(chip_addr, ®s->address); + writel(1, ®s->transfer_size); + + return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | + CDNS_I2C_INTERRUPT_NACK) & + CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT; +} + +static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, + u32 len, bool next_is_read) +{ + u8 *cur_data = data; + + struct cdns_i2c_regs *regs = i2c_bus->regs; + + setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | + CDNS_I2C_CONTROL_HOLD); + + /* if next is a read, we need to clear HOLD, doesn't work */ + if (next_is_read) + clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); + + clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW); + + writel(0xFF, ®s->interrupt_status); + writel(addr, ®s->address); + + while (len--) { + writel(*(cur_data++), ®s->data); + if (readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) { + if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) { + /* Release the bus */ + clrbits_le32(®s->control, + CDNS_I2C_CONTROL_HOLD); + return -ETIMEDOUT; + } + } + } + + /* All done... release the bus */ + clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); + /* Wait for the address and data to be sent */ + if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) + return -ETIMEDOUT; + return 0; +} + +static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, + u32 len) +{ + u32 status; + u32 i = 0; + u8 *cur_data = data; + + /* TODO: Fix this */ + struct cdns_i2c_regs *regs = i2c_bus->regs; + + /* Check the hardware can handle the requested bytes */ + if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX)) + return -EINVAL; + + setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | + CDNS_I2C_CONTROL_RW); + + /* Start reading data */ + writel(addr, ®s->address); + writel(len, ®s->transfer_size); + + /* Wait for data */ + do { + status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | + CDNS_I2C_INTERRUPT_DATA); + if (!status) { + /* Release the bus */ + clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); + return -ETIMEDOUT; + } + debug("Read %d bytes\n", + len - readl(®s->transfer_size)); + for (; i < len - readl(®s->transfer_size); i++) + *(cur_data++) = readl(®s->data); + } while (readl(®s->transfer_size) != 0); + /* All done... release the bus */ + clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); + +#ifdef DEBUG + cdns_i2c_debug_status(regs); +#endif + return 0; +} + +static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, + int nmsgs) +{ + struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); + int ret; + + debug("i2c_xfer: %d messages\n", nmsgs); + for (; nmsgs > 0; nmsgs--, msg++) { + bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); + + debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); + if (msg->flags & I2C_M_RD) { + ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf, + msg->len); + } else { + ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf, + msg->len, next_is_read); + } + if (ret) { + debug("i2c_write: error sending\n"); + return -EREMOTEIO; + } + } + + return 0; +} + +static const struct dm_i2c_ops cdns_i2c_ops = { + .xfer = cdns_i2c_xfer, + .probe_chip = cdns_i2c_probe_chip, + .set_bus_speed = cdns_i2c_set_bus_speed, +}; + +static const struct udevice_id cdns_i2c_of_match[] = { + { .compatible = "cdns,i2c-r1p10" }, + { /* end of table */ } +}; + +U_BOOT_DRIVER(cdns_i2c) = { + .name = "i2c-cdns", + .id = UCLASS_I2C, + .of_match = cdns_i2c_of_match, + .probe = cdns_i2c_probe, + .remove = cdns_i2c_remove, + .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus), + .ops = &cdns_i2c_ops, +}; -- cgit v0.10.2 From 58ed7f66939cbfb6e48656b3925aefd9f180a1a3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 13 Apr 2016 08:49:03 +0200 Subject: ARM64: zynqmp: Use i2c cadence DM driver Use i2c cadence DM driver for all zynqmp targets except ZCU102 because I2C muxes and PCA953x are not supported in the tree yet. Signed-off-by: Michal Simek Reviewed-by: Heiko Schocher diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index b45c7f2..daafb61 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_DM_I2C=y CONFIG_DM_GPIO=y CONFIG_ZYNQMP_USB=y CONFIG_SYS_TEXT_BASE=0x8000000 @@ -17,6 +18,7 @@ CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_ENV_EXISTS is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set +CONFIG_CMD_I2C=y # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_ITEST is not set @@ -29,6 +31,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y CONFIG_NAND_ARASAN=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 4a62a86..366aba2 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1" CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_I2C=y CONFIG_DM_GPIO=y CONFIG_ZYNQMP_USB=y CONFIG_SYS_TEXT_BASE=0x8000000 @@ -11,6 +12,7 @@ CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y CONFIG_CMD_GPIO=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_DHCP=y @@ -19,6 +21,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index c4da7b1..6197ad5 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2" CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_I2C=y CONFIG_DM_GPIO=y CONFIG_ZYNQMP_USB=y CONFIG_SYS_TEXT_BASE=0x8000000 @@ -11,6 +12,7 @@ CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y CONFIG_CMD_GPIO=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_DHCP=y @@ -19,6 +21,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_NAND_ARASAN=y CONFIG_SPI_FLASH=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index 8bbee1b..a9b68de 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5" CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_I2C=y CONFIG_DM_GPIO=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5" @@ -10,12 +11,14 @@ CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_OF_EMBED=y +CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y CONFIG_DM_ETH=y diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index 4a83eee..9506355 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -15,8 +15,6 @@ #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9) -#define CONFIG_ZYNQ_I2C0 -#define CONFIG_SYS_I2C_ZYNQ #define CONFIG_ZYNQ_EEPROM #define CONFIG_AHCI #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h index 7aa9936..3c0ba88 100644 --- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h +++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h @@ -12,8 +12,6 @@ #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_SDHCI1 -#define CONFIG_ZYNQ_I2C1 -#define CONFIG_SYS_I2C_ZYNQ #define CONFIG_AHCI #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} diff --git a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h index 2727dc6..83ea624 100644 --- a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h +++ b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H #define __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H -#define CONFIG_ZYNQ_I2C0 -#define CONFIG_SYS_I2C_ZYNQ #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB1_XHCI_BASEADDR} #define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm016 dc2" diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h index d9409ba..4f8f5c1 100644 --- a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h +++ b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h @@ -12,9 +12,6 @@ #define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H #define CONFIG_ZYNQ_SDHCI0 -#define CONFIG_ZYNQ_I2C0 -#define CONFIG_ZYNQ_I2C1 -#define CONFIG_SYS_I2C_ZYNQ #define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm019 dc5" -- cgit v0.10.2