From 8eecbaf303f4472f9cb925e8694a90fb2812e187 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 15 Dec 2014 23:26:27 +0900 Subject: mpc8260: remove gw8260 board support This board is still a non-generic board. Signed-off-by: Masahiro Yamada Cc: Oliver Brown diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig index 56b79ac..59e2bed 100644 --- a/arch/powerpc/cpu/mpc8260/Kconfig +++ b/arch/powerpc/cpu/mpc8260/Kconfig @@ -19,9 +19,6 @@ config TARGET_CPU87 config TARGET_EP82XXM bool "Support ep82xxm" -config TARGET_GW8260 - bool "Support gw8260" - config TARGET_KM82XX bool "Support km82xx" @@ -31,7 +28,6 @@ source "board/atc/Kconfig" source "board/cpu86/Kconfig" source "board/cpu87/Kconfig" source "board/ep82xxm/Kconfig" -source "board/gw8260/Kconfig" source "board/keymile/km82xx/Kconfig" endmenu diff --git a/board/gw8260/Kconfig b/board/gw8260/Kconfig deleted file mode 100644 index 1d6aa80..0000000 --- a/board/gw8260/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_GW8260 - -config SYS_BOARD - default "gw8260" - -config SYS_CONFIG_NAME - default "gw8260" - -endif diff --git a/board/gw8260/MAINTAINERS b/board/gw8260/MAINTAINERS deleted file mode 100644 index 5268d19..0000000 --- a/board/gw8260/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -GW8260 BOARD -M: Oliver Brown -S: Maintained -F: board/gw8260/ -F: include/configs/gw8260.h -F: configs/gw8260_defconfig diff --git a/board/gw8260/Makefile b/board/gw8260/Makefile deleted file mode 100644 index 2e23f39..0000000 --- a/board/gw8260/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := gw8260.o flash.o diff --git a/board/gw8260/flash.c b/board/gw8260/flash.c deleted file mode 100644 index 0c4a943..0000000 --- a/board/gw8260/flash.c +++ /dev/null @@ -1,502 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Oliver Brown - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*********************************************************************/ -/* DESCRIPTION: - * This file contains the flash routines for the GW8260 board. - * - * - * - * MODULE DEPENDENCY: - * None - * - * - * RESTRICTIONS/LIMITATIONS: - * - * Only supports the following flash devices: - * AMD 29F080B - * AMD 29F016D - * - * Copyright (c) 2001, Advent Networks, Inc. - * - */ -/*********************************************************************/ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*********************************************************************/ -/* functions */ -/*********************************************************************/ - -/* - * NAME: flash_init() - initializes flash banks - * - * DESCRIPTION: - * This function initializes the flash bank(s). - * - * RETURNS: - * The size in bytes of the flash - * - * RESTRICTIONS/LIMITATIONS: - * - * - */ -unsigned long flash_init(void) -{ - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* for now, only support the 4 MB Flash SIMM */ - (void)flash_get_size((vu_long *) CONFIG_SYS_FLASH0_BASE, - &flash_info[0]); - /* - * protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -#ifndef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return CONFIG_SYS_FLASH0_SIZE * 1024 * 1024; /*size */ -} - -/*********************************************************************/ -/* NAME: flash_print_info() - prints flash imformation */ -/* */ -/* DESCRIPTION: */ -/* This function prints the flash information. */ -/* */ -/* INPUTS: */ -/* flash_info_t *info - flash information structure */ -/* */ -/* OUTPUTS: */ -/* Displays flash information to console */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - case AMD_ID_F080B: - printf ("AM29F080B (8 Mbit)\n"); - break; - case AMD_ID_F016D: - printf ("AM29F016D (16 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*********************************************************************/ -/* The following code cannot be run from FLASH! */ -/*********************************************************************/ - -/*********************************************************************/ -/* NAME: flash_get_size() - detects the flash size */ -/* */ -/* DESCRIPTION: */ -/* 1) Reads vendor ID and devices ID from the flash devices. */ -/* 2) Initializes flash info struct. */ -/* 3) Return the flash size */ -/* */ -/* INPUTS: */ -/* vu_long *addr - pointer to start of flash */ -/* flash_info_t *info - flash information structure */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* Size of the flash in bytes, or 0 if device id is unknown. */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Only supports the following devices: */ -/* AM29F080D */ -/* AM29F016D */ -/* */ -/*********************************************************************/ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - vu_long vendor, devid; - ulong base = (ulong)addr; - - /*printf("addr = %08lx\n", (unsigned long)addr); */ - - /* Reset and Write auto select command: read Manufacturer ID */ - addr[0x0000] = 0xf0f0f0f0; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - udelay (1000); - - vendor = addr[0]; - /*printf("vendor = %08lx\n", vendor); */ - if (vendor != 0x01010101) { - info->size = 0; - goto out; - } - - devid = addr[1]; - /*printf("devid = %08lx\n", devid); */ - - if ((devid & 0xff) == AMD_ID_F080B) { - info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F080B; - /* we have 16 sectors with 64KB each x 4 */ - info->sector_count = 16; - info->size = 4 * info->sector_count * 64*1024; - } else if ((devid & 0xff) == AMD_ID_F016D){ - info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F016D; - /* we have 32 sectors with 64KB each x 4 */ - info->sector_count = 32; - info->size = 4 * info->sector_count * 64*1024; - } else { - info->size = 0; - goto out; - } - /*printf("sector count = %08x\n", info->sector_count); */ - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* reset command */ - addr = (vu_long *)info->start[0]; - - out: - addr[0] = 0xf0f0f0f0; - - /*printf("size = %08x\n", info->size); */ - return info->size; -} - -/*********************************************************************/ -/* NAME: flash_erase() - erases flash by sector */ -/* */ -/* DESCRIPTION: */ -/* This function erases flash sectors starting for s_first to */ -/* s_last. */ -/* */ -/* INPUTS: */ -/* flash_info_t *info - flash information structure */ -/* int s_first - first sector to erase */ -/* int s_last - last sector to erase */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* Returns 0 for success, 1 for failure. */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/*********************************************************************/ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - udelay (100); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*********************************************************************/ -/* NAME: write_buff() - writes a buffer to flash */ -/* */ -/* DESCRIPTION: */ -/* This function copies a buffer, *src, to flash. */ -/* */ -/* INPUTS: */ -/* flash_info_t *info - flash information structure */ -/* uchar *src - pointer to buffer to write to flash */ -/* ulong addr - address to start write at */ -/* ulong cnt - number of bytes to write to flash */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - OK */ -/* 1 - write timeout */ -/* 2 - Flash not erased */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/*********************************************************************/ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; (i < 4) && (cnt > 0); ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; (cnt == 0) && (i < 4); ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; (i < 4) && (cnt > 0); ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; (i < 4); ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*********************************************************************/ -/* NAME: write_word() - writes a word to flash */ -/* */ -/* DESCRIPTION: */ -/* This writes a single word to flash. */ -/* */ -/* INPUTS: */ -/* flash_info_t *info - flash information structure */ -/* ulong dest - address to write */ -/* ulong data - data to write */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - OK */ -/* 1 - write timeout */ -/* 2 - Flash not erased */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/*********************************************************************/ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} -/*********************************************************************/ -/* End of flash.c */ -/*********************************************************************/ diff --git a/board/gw8260/gw8260.c b/board/gw8260/gw8260.c deleted file mode 100644 index bbae0a8..0000000 --- a/board/gw8260/gw8260.c +++ /dev/null @@ -1,639 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Oliver Brown - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*********************************************************************/ -/* DESCRIPTION: - * This file contains the board routines for the GW8260 board. - * - * MODULE DEPENDENCY: - * None - * - * RESTRICTIONS/LIMITATIONS: - * None - * - * Copyright (c) 2001, Advent Networks, Inc. - */ -/*********************************************************************/ - -#include -#include -#include - -/* - * I/O Port configuration table - * - */ -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* TP14 */ - /* PA30 */ { 1, 1, 1, 1, 0, 0 }, /* US_RTS */ - /* PA29 */ { 1, 0, 0, 1, 0, 1 }, /* LSSI_DATA */ - /* PA28 */ { 1, 0, 0, 1, 0, 1 }, /* LSSI_CLK */ - /* PA27 */ { 1, 0, 0, 1, 0, 0 }, /* TP12 */ - /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* IO_STATUS */ - /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* IO_CLOCK */ - /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* IO_CONFIG */ - /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* IO_DONE */ - /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* IO_DATA */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD3 */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD2 */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD1 */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD0 */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD0 */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD1 */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD2 */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD3 */ - /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE7 */ - /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE6 */ - /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE5 */ - /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE4 */ - /* PA9 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE3 */ - /* PA8 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE2 */ - /* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* LSSI_IN */ - /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE0 */ - /* PA5 */ { 1, 0, 0, 1, 0, 0 }, /* DEMOD_RESET_ */ - /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* MOD_RESET_ */ - /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* IO_RESET */ - /* PA2 */ { 1, 0, 0, 1, 0, 0 }, /* TX_ENABLE */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* RX_LOCK */ - /* PA0 */ { 1, 0, 0, 1, 0, 1 } /* MPC_RESET_ */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FETH0_TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD3 */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD2 */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD1 */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD0 */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD0 */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD1 */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD2 */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD3 */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_DV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_ER */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TX_ER */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD3 */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD2 */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD1 */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD0 */ - /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD0 */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD1 */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD2 */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD3 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 1, 0, 0, 1, 0, 1 }, /* FAST_RESET_ */ - /* PC30 */ { 1, 0, 0, 1, 0, 1 }, /* FAST_PAUSE_ */ - /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* FAST_SLEW1 */ - /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* FAST_SLEW0 */ - /* PC27 */ { 1, 0, 0, 1, 0, 0 }, /* TP13 */ - /* PC26 */ { 1, 0, 0, 0, 0, 0 }, /* RXDECDFLG */ - /* PC25 */ { 1, 0, 0, 0, 0, 0 }, /* RXACQFAIL */ - /* PC24 */ { 1, 0, 0, 0, 0, 0 }, /* RXACQFLG */ - /* PC23 */ { 1, 0, 0, 1, 0, 0 }, /* WD_TCL */ - /* PC22 */ { 1, 0, 0, 1, 0, 0 }, /* WD_EN */ - /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* US_TXCLK */ - /* PC20 */ { 1, 0, 0, 0, 0, 0 }, /* DS_RXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_TX_CLK */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_CLK */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_TX_CLK */ - /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* TX_SHUTDOWN_ */ - /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* RS_232_DTR_ */ - /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* TXERR */ - /* PC12 */ { 1, 0, 0, 1, 0, 1 }, /* FETH1_MDDIS */ - /* PC11 */ { 1, 0, 0, 1, 0, 1 }, /* FETH0_MDDIS */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* MDC */ - /* PC9 */ { 1, 0, 0, 1, 1, 1 }, /* MDIO */ - /* PC8 */ { 1, 0, 0, 1, 1, 1 }, /* SER_NUM */ - /* PC7 */ { 1, 1, 0, 0, 0, 0 }, /* US_CTS */ - /* PC6 */ { 1, 1, 0, 0, 0, 0 }, /* DS_CD_ */ - /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* FETH1_PWRDWN */ - /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* FETH0_PWRDWN */ - /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED3 */ - /* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED2 */ - /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED1 */ - /* PC0 */ { 1, 0, 0, 1, 0, 1 }, /* MPULED0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ - /* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ - /* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ - /* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ - /* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* SDRAM_SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* SDRAM_SCL */ - /* PD13 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED7 */ - /* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED6 */ - /* PD11 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED5 */ - /* PD10 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED4 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* RS232_TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* RD232_RXD */ - /* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/*********************************************************************/ -/* NAME: checkboard() - Displays the board type and serial number */ -/* */ -/* OUTPUTS: */ -/* Displays the board type and serial number */ -/* */ -/* RETURNS: */ -/* Always returns 1 */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: Advent Networks gw8260\n"); - - if (i > 0) { - printf("SN: %s\n", buf); - } - return 0; -} - - -#if defined (CONFIG_SYS_DRAM_TEST) -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ - return; -} - - -#if defined (CONFIG_SYS_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL, -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_SDRAM_BASE; - unsigned long long temp64 = 0; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_DATA */ - -#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *) CONFIG_SYS_SDRAM_BASE; - const unsigned int size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) { - pmem[i] = i; - } - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ - -#if defined (CONFIG_SYS_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp = 0; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *) &(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *) &(base[i])); - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *) CONFIG_SYS_SDRAM_BASE; - const unsigned long size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - } - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - int rundata, runaddress, runwalk; - - rundata = getenv_yesno("testdramdata") == 1; - runaddress = getenv_yesno("testdramaddress") == 1; - runwalk = getenv_yesno("testdramwalk") == 1; - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM ... "); - } -#ifdef CONFIG_SYS_DRAM_TEST_DATA - if (rundata == 1) { - if (mem_test_data () == 1) { - return 1; - } - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS - if (runaddress == 1) { - if (mem_test_address () == 1) { - return 1; - } - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_WALK - if (runwalk == 1) { - if (mem_test_walk () == 1) { - return 1; - } - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("passed"); - } - return 0; - -} -#endif /* CONFIG_SYS_DRAM_TEST */ - -/*********************************************************************/ -/* NAME: initdram() - initializes SDRAM controller */ -/* */ -/* DESCRIPTION: */ -/* Initializes the MPC8260's SDRAM controller. */ -/* */ -/* INPUTS: */ -/* CONFIG_SYS_IMMR - MPC8260 Internal memory map */ -/* CONFIG_SYS_SDRAM_BASE - Physical start address of SDRAM */ -/* CONFIG_SYS_PSDMR - SDRAM mode register */ -/* CONFIG_SYS_MPTPR - Memory refresh timer prescaler register */ -/* CONFIG_SYS_SDRAM0_SIZE - SDRAM size */ -/* */ -/* RETURNS: */ -/* SDRAM size in bytes */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8); - ulong psdmr = CONFIG_SYS_PSDMR; - int i; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) { - *ramaddr = c; - } - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - /* return total ram size */ - return (CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024); -} - -/*********************************************************************/ -/* End of gw8260.c */ -/*********************************************************************/ diff --git a/configs/gw8260_defconfig b/configs/gw8260_defconfig deleted file mode 100644 index a59ec3a..0000000 --- a/configs/gw8260_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_GW8260=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index af4b00c..0c47ebd 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +gw8260 powerpc mpc8260 - - Oliver Brown IPHASE4539 powerpc mpc8260 - - Wolfgang Grandegger muas3001 powerpc mpc8260 - - Heiko Schocher PM825 powerpc mpc8260 - - Wolfgang Denk diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h deleted file mode 100644 index 262c9e9..0000000 --- a/include/configs/gw8260.h +++ /dev/null @@ -1,800 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Oliver Brown - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*********************************************************************/ -/* DESCRIPTION: - * This file contains the board configuartion for the GW8260 board. - * - * MODULE DEPENDENCY: - * None - * - * RESTRICTIONS/LIMITATIONS: - * None - * - * Copyright (c) 2001, Advent Networks, Inc. - */ -/*********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -/* Enable debug prints */ -#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN (66 * 1000 * 1000) - -/*----------------------------------------------------------------------- - * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual - *----------------------------------------------------------------------- - * What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Here are some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 - * ------- ---------- --- --- ---- ----- ----- ----- - * 0x5 0x5 66 133 133 Open Close Open - * 0x5 0x6 66 133 166 Open Open Close - * 0x5 0x7 66 133 200 Open Open Open - * 0x6 0x0 66 133 233 Close Close Close - * 0x6 0x1 66 133 266 Close Close Open - * 0x6 0x2 66 133 300 Close Open Close - */ -#define CONFIG_SYS_SBC_MODCK_H 0x05 - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -#define CONFIG_SYS_SBC_BOOT_LOW 1 - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE. - * The main FLASH is whichever is connected to *CS0. U-Boot expects - * this to be the SIMM. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH0_SIZE 8 - -/* Define CONFIG_SYS_FLASH_CHECKSUM to enable flash checksum during boot. - * Note: the 'flashchecksum' environment variable must also be set to 'y'. - */ -#define CONFIG_SYS_FLASH_CHECKSUM - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? - */ -#define CONFIG_SYS_SDRAM0_BASE 0x00000000 -#define CONFIG_SYS_SDRAM0_SIZE 64 - -/* - * DRAM tests - * CONFIG_SYS_DRAM_TEST - enables the following tests. - * - * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CONFIG_SYS_DRAM_TEST -#if defined(CONFIG_SYS_DRAM_TEST) -#define CONFIG_SYS_DRAM_TEST_DATA -#define CONFIG_SYS_DRAM_TEST_ADDRESS -#define CONFIG_SYS_DRAM_TEST_WALK -#endif /* CONFIG_SYS_DRAM_TEST */ - -/* - * GW8260 with 16 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x00F5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x00F5 FFB0 Board Info Data - * 0x00F6 0000 Malloc Arena - * : CONFIG_ENV_SECT_SIZE, 256k - * : CONFIG_SYS_MALLOC_LEN, 128k - * 0x00FC 0000 RAM Copy of Monitor Code - * : CONFIG_SYS_MONITOR_LEN, 256k - * 0x00FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 - */ - -/* - * GW8260 with 64 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x03F5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x03F5 FFB0 Board Info Data - * 0x03F6 0000 Malloc Arena - * : CONFIG_ENV_SECT_SIZE, 256k - * : CONFIG_SYS_MALLOC_LEN, 128k - * 0x03FC 0000 RAM Copy of Monitor Code - * : CONFIG_SYS_MONITOR_LEN, 256k - * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 - */ - - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ - -#undef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_ON_FCC -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ - -#ifdef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#endif /* CONFIG_ETHER_ON_SCC */ - -#ifdef CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * Port pins used for bit-banged MII communictions (if applicable). - */ -#define MDIO_PORT 2 /* Port C */ - -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) -#endif /* CONFIG_ETHER_ON_FCC */ - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -/* Define this to reserve an entire FLASH sector (256 KB) for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CONFIG_ENV_IN_OWN_SECT - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* What should the console's baud rate be? */ -#define CONFIG_BAUDRATE 115200 - -/* Ethernet MAC address - This is set to all zeros to force an - * an error if we use BOOTP without setting - * the MAC address - */ -#define CONFIG_ETHADDR 00:00:00:00:00:00 - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Autobooting in %d seconds, press \" \" to stop\n", bootdelay -#define CONFIG_AUTOBOOT_STOP_STR " " -#undef CONFIG_AUTOBOOT_DELAY_STR -#define DEBUG_BOOTKEYS 0 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS - -/* undef this to save memory */ -#define CONFIG_SYS_LONGHELP - -/* Monitor Command Prompt */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII - -#undef CONFIG_CMD_KGDB - - -/* Where do the internal registers live? */ -#define CONFIG_SYS_IMMR 0xf0000000 - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#endif - -/* What is the address of IO controller */ -#define CONFIG_SYS_IO_BASE 0xe0000000 - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_GW8260 1 /* on an GW8260 Board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* - * Miscellaneous configurable options - */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_MAXARGS 8 /* max number of command args */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* Convert clocks to MHZ when passing board info to kernel. - * This must be defined for eariler 2.4 kernels (~2.4.4). - */ -#define CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - - -/* memtest works from the end of the exception vector table - * to the end of the DRAM less monitor and malloc area - */ -#define CONFIG_SYS_MEMTEST_START 0x2000 - -#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ - -#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ - + CONFIG_SYS_MALLOC_LEN \ - + CONFIG_ENV_SECT_SIZE \ - + CONFIG_SYS_STACK_USAGE ) - -#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \ - - CONFIG_SYS_MEM_END_USAGE ) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ -#if defined(CONFIG_SYS_SBC_BOOT_LOW) -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ - -/* get the HRCW ISB field from CONFIG_SYS_IMMR */ -#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \ - ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \ - ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) - -#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS11 | \ - HRCW_DPPC11 | \ - CONFIG_SYS_SBC_HRCW_IMMR | \ - HRCW_MMR00 | \ - HRCW_LBPC11 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \ - CONFIG_SYS_SBC_HRCW_BOOT_FLAGS ) - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -#ifdef CONFIG_ENV_IN_OWN_SECT -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + (256 * 1024)) -# define CONFIG_ENV_SECT_SIZE (256 * 1024) -#else -# define CONFIG_ENV_SIZE (16 * 1024)/* Size of Environment Sector */ -# define CONFIG_ENV_ADD ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SIZE) -# define CONFIG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size */ -#endif /* CONFIG_ENV_IN_OWN_SECT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_ETM) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\ - SIUMCR_L2CPC00 |\ - SIUMCR_APPC10 |\ - SIUMCR_MMR00) - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Initialize Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH (SIMM - 4MB) - * 1 60x GPCM 32 bit unused - * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB) - * 3 60x SDRAM 64 bit unused - * 4 Local GPCM 8 bit IO (on board - 64k) - * 5 60x GPCM 8 bit unused - * 6 60x GPCM 8 bit unused - * 7 60x GPCM 8 bit unused - * - */ - -/*----------------------------------------------------------------------- - * BR0 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR0 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 0,1 - FLASH SIMM - * - * This expects the FLASH SIMM to be connected to *CS0 - * It consists of 4 AM29F016D parts. - * - * Note: For the 8 MB SIMM, *CS1 is unused. - */ - -/* BR0 is configured as follows: - * - * - Base address of 0x40000000 - * - 32 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR0 is configured as follows: - * - * - 8 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - -/*----------------------------------------------------------------------- - * BR2 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR2 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* Bank 2 - SDRAM DIMM - * - * 16MB DIMM: P/N - * 64MB DIMM: P/N 1W-8864X8-4-P1-EST or - * MT4LSDT864AG-10EB1 (Micron) - * - * Note: *CS3 is unused for this DIMM - */ - -/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows: - * - * - Base address of 0x00000000 - * - 64 bit port size (60x bus only) - * - Data errors checking is disabled - * - Read and write access - * - SDRAM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -/* With a 16 MB DIMM, the OR2 is configured as follows: - * - * - 16 MB - * - 2 internal banks per device - * - Row start address bit is A9 with PSDMR[PBI] = 0 - * - 11 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CONFIG_SYS_SDRAM0_SIZE == 16) -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ - ORxS_BPD_2 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_11) - -/* With a 16 MB DIMM, the PSDMR is configured as follows: - * - * - Page Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A16-A18 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A16_A18 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#endif /* (CONFIG_SYS_SDRAM0_SIZE == 16) */ - -/* With a 64 MB DIMM, the OR2 is configured as follows: - * - * - 64 MB - * - 4 internal banks per device - * - Row start address bit is A8 with PSDMR[PBI] = 0 - * - 12 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CONFIG_SYS_SDRAM0_SIZE == 64) -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12) - -/* With a 64 MB DIMM, the PSDMR is configured as follows: - * - * - Page Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A14-A16 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#endif /* (CONFIG_SYS_SDRAM0_SIZE == 64) */ - -#define CONFIG_SYS_PSRT 0x0e -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 - - -/*----------------------------------------------------------------------- - * BR4 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR4 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ -/* Bank 4 - Onboard Memory Mapped IO controller - * - * This expects the onboard IO controller to connected to *CS4 and - * the local bus. - * - Base address of 0xe0000000 - * - 8 bit port size (local bus only) - * - Read and write access - * - GPCM local bus - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - * - extended hold time - * - 11 wait states - */ - -#ifdef CONFIG_SYS_IO_BASE -# define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_L |\ - BRx_V) - -# define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\ - ORxG_SCY_11_CLK |\ - ORxG_EHTR) -#endif /* CONFIG_SYS_IO_BASE */ -#endif /* __CONFIG_H */ -- cgit v0.10.2