From bec6a126ba150701868e553ab709a7aab5d20d85 Mon Sep 17 00:00:00 2001
From: Calvin Johnson <calvin.johnson@nxp.com>
Date: Tue, 16 Jan 2018 11:18:57 +0530
Subject: armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC

1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces
to bufferable.
2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces.
3. Disable ECC detection for PFE.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>

Changes in v2:
-Improved commit message to provide more description
-Replaced magic numbers with proper definitions

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 69e091a..a9adb0a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -569,6 +569,29 @@ int setup_chip_volt(void)
 	return 0;
 }
 
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	u32 ecccr2;
+
+	out_be32(&scfg->pfeasbcr,
+		 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
+	out_be32(&scfg->pfebsbcr,
+		 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
+
+	/* CCI-400 QoS settings for PFE */
+	out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
+		 | SCFG_WR_QOS1_PFE2_QOS));
+	out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
+		 | SCFG_RD_QOS1_PFE2_QOS));
+
+	ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
+	out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
+		 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
+}
+#endif
+
 void fsl_lsch2_early_init_f(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index e1a57de..11cf35c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -205,6 +205,8 @@ struct sys_info {
 
 /* Device Configuration and Pin Control */
 #define DCFG_DCSR_PORCR1		0x0
+#define DCFG_DCSR_ECCCR2		0x524
+#define DISABLE_PFE_ECC			BIT(13)
 
 struct ccsr_gur {
 	u32     porsr1;         /* POR status 1 */
@@ -402,7 +404,7 @@ struct ccsr_gur {
 #define SCFG_RGMIIPCR_SETSP_10M		(0x00000002)
 #define SCFG_RGMIIPCR_SETFD		(0x00000001)
 
-/*PFEASBCR bit definitions */
+/* PFEASBCR bit definitions */
 #define SCFG_PFEASBCR_ARCACHE0		(0x80000000)
 #define SCFG_PFEASBCR_AWCACHE0		(0x40000000)
 #define SCFG_PFEASBCR_ARCACHE1		(0x20000000)
@@ -410,6 +412,14 @@ struct ccsr_gur {
 #define SCFG_PFEASBCR_ARSNP		(0x08000000)
 #define SCFG_PFEASBCR_AWSNP		(0x04000000)
 
+/* WR_QoS1 PFE bit definitions */
+#define SCFG_WR_QOS1_PFE1_QOS		GENMASK(27, 24)
+#define SCFG_WR_QOS1_PFE2_QOS		GENMASK(23, 20)
+
+/* RD_QoS1 PFE bit definitions */
+#define SCFG_RD_QOS1_PFE1_QOS		GENMASK(27, 24)
+#define SCFG_RD_QOS1_PFE2_QOS		GENMASK(23, 20)
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
 	u8 res_000[0x100-0x000];
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 09f64e7..0ff109d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -124,6 +124,9 @@ void fsl_lsch2_early_init_f(void);
 int setup_chip_volt(void);
 /* Setup core vdd in unit mV */
 int board_setup_core_volt(u32 vdd);
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void);
+#endif
 #endif
 
 void cpu_name(char *name);
-- 
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