From 29b7042addcad3512c9e597bf4c805df7b9d2757 Mon Sep 17 00:00:00 2001 From: Sanjeev Premi Date: Wed, 16 Nov 2011 10:20:47 -0500 Subject: part_efi: Fix compile errors Fix errors noticed after enabling CONFIG_EFI_PARTITION for the OMAP3 EVM board: part_efi.c: In function 'print_part_efi': part_efi.c:133:5: warning: passing argument 3 of 'is_gpt_valid' from incompatible pointer type part_efi.c:95:12: note: expected 'struct gpt_header *' but arg ument is of type 'struct gpt_header **' part_efi.c: In function 'get_partition_info_efi': part_efi.c:173:4: warning: passing argument 3 of 'is_gpt_valid ' from incompatible pointer type part_efi.c:95:12: note: expected 'struct gpt_header *' but arg ument is of type 'struct gpt_header **' part_efi.c: In function 'alloc_read_gpt_entries': part_efi.c:384:18: error: 'CONFIG_SYS_CACHELINE_SIZE' undeclare d (first use in this function) Signed-off-by: Sanjeev Premi Cc: Tom Rini Cc: Anton staaf Signed-off-by: Sandeep Paulraj diff --git a/disk/part_efi.c b/disk/part_efi.c index ddf80a7..b6cda57 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -380,7 +380,7 @@ static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc, /* Allocate memory for PTE, remember to FREE */ if (count != 0) { - pte = memalign(CONFIG_SYS_CACHELINE_SIZE, count); + pte = memalign(ARCH_DMA_MINALIGN, count); } if (count == 0 || pte == NULL) { -- cgit v0.10.2 From 35e3f6d7693fe11718850511ef729bf692c6260b Mon Sep 17 00:00:00 2001 From: Sanjeev Premi Date: Wed, 16 Nov 2011 10:20:50 -0500 Subject: omap3evm: Add support for EFI partitions Defines CONFIG_EFI_PARTITION for OMAP3 EVM. Signed-off-by: Sanjeev Premi Cc: Sandeep Paulraj Cc: Tom Rini Signed-off-by: Sandeep Paulraj diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 47ec39f..9228ef1 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -84,6 +84,7 @@ #define CONFIG_GENERIC_MMC #define CONFIG_OMAP_HSMMC #define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION /* USB * -- cgit v0.10.2 From 0bfb66b6d1497046aac9c4d61f4478a403659f5a Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Tue, 8 Nov 2011 11:31:14 +0000 Subject: netspace_v2: Read Ethernet MAC address from EEPROM Signed-off-by: Simon Guinot diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 7c4b15e..6938a43 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -89,6 +90,48 @@ int board_init(void) return 0; } +int misc_init_r(void) +{ +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) + if (!getenv("ethaddr")) { + ushort version; + uchar mac[6]; + int ret; + + /* I2C-0 for on-board EEPROM */ + i2c_set_bus_num(0); + + /* Check layout version for EEPROM data */ + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (uchar *) &version, 2); + if (ret != 0) { + printf("Error: failed to read I2C EEPROM @%02x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return ret; + } + version = be16_to_cpu(version); + if (version < 1 || version > 3) { + printf("Error: unknown version %d for EEPROM data\n", + version); + return -1; + } + + /* Read Ethernet MAC address from EEPROM */ + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac, 6); + if (ret != 0) { + printf("Error: failed to read I2C EEPROM @%02x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return ret; + } + eth_setenv_enetaddr("ethaddr", mac); + } +#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */ + + return 0; +} + void mv_phy_88e1116_init(char *name) { u16 reg; diff --git a/include/configs/netspace_v2.h b/include/configs/netspace_v2.h index bb27ed7..1ddf4b4 100644 --- a/include/configs/netspace_v2.h +++ b/include/configs/netspace_v2.h @@ -87,6 +87,7 @@ * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET +#define CONFIG_MISC_INIT_R /* Call misc_init_r() to initialize MAC address */ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_NETCONSOLE #endif -- cgit v0.10.2 From 2cb4fade0ef00ebf485db05d6aab4acd8897ecf9 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Mon, 21 Nov 2011 19:25:46 +0530 Subject: mvsata: fix ide_preinit for missing disks Consider that ide_preinit() succeed if at least one port is successfully initialized. This allows to iniatialize IDE support on a board with two SATA ports but a single hard disk available. Signed-off-by: Simon Guinot diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index 1be395f..a88d0f7 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -150,23 +150,25 @@ static int mvsata_ide_initialize_port(struct mvsata_port_registers *port) int ide_preinit(void) { + int ret = MVSATA_STATUS_TIMEOUT; int status; + /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE0_OFFSET) status = mvsata_ide_initialize_port( (struct mvsata_port_registers *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET)); - if (status) - return status; + if (status == MVSATA_STATUS_OK) + ret = MVSATA_STATUS_OK; #endif /* Enable ATA port 1 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE1_OFFSET) status = mvsata_ide_initialize_port( (struct mvsata_port_registers *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET)); - if (status) - return status; + if (status == MVSATA_STATUS_OK) + ret = MVSATA_STATUS_OK; #endif - /* return success if all ports initializations succeeded */ - return MVSATA_STATUS_OK; + /* Return success if at least one port initialization succeeded */ + return ret; } -- cgit v0.10.2 From 5628fb75d10764c377bd7eef9dfb4476f2398ff7 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Mon, 21 Nov 2011 19:25:46 +0530 Subject: ARM: add support for LaCie 2Big Network v2 This patch adds support for the LaCie 2Big Network v2 board, based on the Marvell Kirkwood 6281 SoC. Additional information is available at: http://lacie-nas.org/doku.php?id=2big_network_v2 Signed-off-by: Simon Guinot diff --git a/MAINTAINERS b/MAINTAINERS index 0c0b4ee..3a6d29c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -651,6 +651,7 @@ Simon Guinot inetspace_v2 ARM926EJS (Kirkwood SoC) netspace_v2 ARM926EJS (Kirkwood SoC) netspace_max_v2 ARM926EJS (Kirkwood SoC) + net2big_v2 ARM926EJS (Kirkwood SoC) Igor Grinberg diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile new file mode 100644 index 0000000..4bacef4 --- /dev/null +++ b/board/LaCie/net2big_v2/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2011 Simon Guinot +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := net2big_v2.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/LaCie/net2big_v2/kwbimage.cfg b/board/LaCie/net2big_v2/kwbimage.cfg new file mode 100644 index 0000000..8d9f153 --- /dev/null +++ b/board/LaCie/net2big_v2/kwbimage.cfg @@ -0,0 +1,162 @@ +# +# Copyright (C) 2011 Simon Guinot +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1B1B1B9B + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000C30 # DDR Configuration register +# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x38743000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000A32 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x0000CCCC # DDR Address Control +# bit1-0: 01, Cs0width=x16 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs2width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000662 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000044 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strenght reduced +# bit2: 1, DDR ODT control lsd enabled +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, enabled +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 1 , D2P Latency enabled +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 +# bit11-10:1, DQ_ODTSel. ODT select turned on + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c new file mode 100644 index 0000000..16d1405 --- /dev/null +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2011 Simon Guinot + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "net2big_v2.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* GPIO configuration */ + kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH, + NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* Request power-off */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP13_GPIO, /* Rear power switch (on|auto) */ + MPP14_GPIO, /* USB fuse alarm */ + MPP15_GPIO, /* Rear power switch (auto|off) */ + MPP16_GPIO, /* SATA HDD1 power */ + MPP17_GPIO, /* SATA HDD2 power */ + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP24_GPIO, /* USB mode select */ + MPP26_GPIO, /* USB device vbus */ + MPP28_GPIO, /* USB enable host vbus */ + MPP29_GPIO, /* GPIO extension ALE */ + MPP34_GPIO, /* Rear Push button 0=on 1=off */ + MPP35_GPIO, /* Inhibit switch power-off */ + MPP36_GPIO, /* SATA HDD1 presence */ + MPP37_GPIO, /* SATA HDD2 presence */ + MPP40_GPIO, /* eSATA presence */ + MPP44_GPIO, /* GPIO extension (data 0) */ + MPP45_GPIO, /* GPIO extension (data 1) */ + MPP46_GPIO, /* GPIO extension (data 2) */ + MPP47_GPIO, /* GPIO extension (addr 0) */ + MPP48_GPIO, /* GPIO extension (addr 1) */ + MPP49_GPIO, /* GPIO extension (addr 2) */ + 0 + }; + + kirkwood_mpp_conf(kwmpp_config); + + return 0; +} + +int board_init(void) +{ + /* Machine number */ + gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2; + + /* Boot parameters address */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_I2C + if (!getenv("ethaddr")) { + ushort version; + uchar mac[6]; + int ret; + + /* I2C-0 for on-board EEPROM */ + i2c_set_bus_num(0); + + /* Check layout version for EEPROM data */ + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (uchar *) &version, 2); + if (ret != 0) { + printf("Error: failed to read I2C EEPROM @%02x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return ret; + } + version = be16_to_cpu(version); + if (version < 1 || version > 3) { + printf("Error: unknown version %d for EEPROM data\n", + version); + return -1; + } + + /* Read Ethernet MAC address from EEPROM */ + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac, 6); + if (ret != 0) { + printf("Error: failed to read I2C EEPROM @%02x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return ret; + } + eth_setenv_enetaddr("ethaddr", mac); + } +#endif /* CONFIG_CMD_I2C */ + + return 0; +} + +void mv_phy_88e1116_init(char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..(%s) could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + if (miiphy_read(name, devadr, MII_BMCR, ®) != 0) { + printf("Err..(%s) PHY status read failed\n", __func__); + return; + } + if (miiphy_write(name, devadr, MII_BMCR, reg | 0x8000) != 0) { + printf("Err..(%s) PHY reset failed\n", __func__); + return; + } + + debug("88E1116 Initialized on %s\n", name); +} + +/* Configure and initialize PHY */ +void reset_phy(void) +{ + mv_phy_88e1116_init("egiga0"); +} + +/* Return GPIO push button status */ +static int +do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON); +} + +U_BOOT_CMD(button, 1, 1, do_read_push_button, + "Return GPIO push button status 0=off 1=on", ""); diff --git a/board/LaCie/net2big_v2/net2big_v2.h b/board/LaCie/net2big_v2/net2big_v2.h new file mode 100644 index 0000000..bbe67af --- /dev/null +++ b/board/LaCie/net2big_v2/net2big_v2.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2011 Simon Guinot + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef NET2BIG_V2_H +#define NET2BIG_V2_H + +/* GPIO configuration */ +#define NET2BIG_V2_OE_LOW 0x0600E000 +#define NET2BIG_V2_OE_HIGH 0x00000134 +#define NET2BIG_V2_OE_VAL_LOW 0x10030000 +#define NET2BIG_V2_OE_VAL_HIGH 0x00000000 + +/* Buttons */ +#define NET2BIG_V2_GPIO_PUSH_BUTTON 34 + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* NET2BIG_V2_H */ diff --git a/boards.cfg b/boards.cfg index d9021aa..d16789b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -141,6 +141,7 @@ km_kirkwood_pci arm arm926ejs km_arm keymile mgcoge3un arm arm926ejs km_arm keymile kirkwood portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:INETSPACE_V2 +net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:NETSPACE_V2 netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:NETSPACE_MAX_V2 dreamplug arm arm926ejs - Marvell kirkwood diff --git a/include/configs/net2big_v2.h b/include/configs/net2big_v2.h new file mode 100644 index 0000000..9cf76d0 --- /dev/null +++ b/include/configs/net2big_v2.h @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2011 Simon Guinot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CONFIG_NET2BIG_V2_H +#define _CONFIG_NET2BIG_V2_H + +/* + * Machine number information + */ +#define CONFIG_IDENT_STRING " 2Big v2" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_MACH_NET2BIG_V2 /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include +#define CONFIG_CMD_ENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_USB + +/* + * Core clock definition. + */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#define CONFIG_NR_DRAM_BANKS 2 +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_RBTREE +#undef CONFIG_ENV_SPI_MAX_HZ +#undef CONFIG_SYS_IDE_MAXBUS +#undef CONFIG_SYS_IDE_MAXDEVICE +#undef CONFIG_SYS_PROMPT +#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 +#define CONFIG_SYS_PROMPT "2big2> " + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MISC_INIT_R /* Call misc_init_r() to initialize MAC address */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_NETCONSOLE +#endif + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif + +/* + * Enable GPI0 support + */ +#define CONFIG_KIRKWOOD_GPIO + +/* + * Enable I2C support + */ +#ifdef CONFIG_CMD_I2C +/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ +#endif /* CONFIG_CMD_I2C */ + +/* + * File systems support + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Console configuration + */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + +/* + * Environment variables configurations + */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */ +#define CONFIG_ENV_SIZE 0x1000 /* 4KB */ +#define CONFIG_ENV_ADDR 0x70000 +#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTARGS "console=ttyS0,115200" + +#define CONFIG_BOOTCOMMAND \ + "dhcp && run netconsole; " \ + "if run usbload || run diskload; then bootm; fi" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "bootfile=uImage\0" \ + "loadaddr=0x800000\0" \ + "autoload=no\0" \ + "netconsole=" \ + "set stdin $stdin,nc; " \ + "set stdout $stdout,nc; " \ + "set stderr $stderr,nc;\0" \ + "diskload=ide reset && " \ + "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ + "usbload=usb start && " \ + "fatload usb 0:1 $loadaddr /boot/$bootfile\0" + +#endif /* _CONFIG_NET2BIG_V2_H */ -- cgit v0.10.2 From 77ea071fefbda70ed21a6f0e7bd34ec215e70d39 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Mon, 21 Nov 2011 19:25:47 +0530 Subject: ARM: remove duplicated code for LaCie boards This patch groups together all the common functions for LaCie boards: Ethernet PHY and MAC address initializations. Moreover the configurations for LaCie Kirkwood boards are merged into a single file: include/configs/lacie_kw.h Signed-off-by: Simon Guinot diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c new file mode 100644 index 0000000..dc5350d --- /dev/null +++ b/board/LaCie/common/common.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2011 Simon Guinot + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include +#include +#include + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) + +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +void mv_phy_88e1116_init(const char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..(%s) could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) +int lacie_read_mac_address(uchar *mac_addr) +{ + int ret; + ushort version; + + /* I2C-0 for on-board EEPROM */ + i2c_set_bus_num(0); + + /* Check layout version for EEPROM data */ + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (uchar *) &version, 2); + if (ret != 0) { + printf("Error: failed to read I2C EEPROM @%02x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return ret; + } + version = be16_to_cpu(version); + if (version < 1 || version > 3) { + printf("Error: unknown version %d for EEPROM data\n", + version); + return -1; + } + + /* Read Ethernet MAC address from EEPROM */ + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6); + if (ret != 0) + printf("Error: failed to read I2C EEPROM @%02x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return ret; +} +#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */ diff --git a/board/LaCie/common/common.h b/board/LaCie/common/common.h new file mode 100644 index 0000000..82a9522 --- /dev/null +++ b/board/LaCie/common/common.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011 Simon Guinot + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef _LACIE_COMMON_H +#define _LACIE_COMMON_H + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +void mv_phy_88e1116_init(const char *name); +#endif +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) +int lacie_read_mac_address(uchar *mac); +#endif + +#endif /* _LACIE_COMMON_H */ diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile index 00a255d..c8d45f4 100644 --- a/board/LaCie/edminiv2/Makefile +++ b/board/LaCie/edminiv2/Makefile @@ -26,10 +26,13 @@ # include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).o -COBJS := edminiv2.o +COBJS := edminiv2.o ../common/common.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index ee26893..c1a01bc 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -27,7 +27,6 @@ #include #include #include -#include "edminiv2.h" DECLARE_GLOBAL_DATA_PTR; @@ -96,33 +95,6 @@ int board_init(void) /* Configure and enable MV88E1116 PHY */ void reset_phy(void) { - u16 reg; - u16 devadr; - char *name = "egiga0"; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..%s could not read PHY dev address\n", - __func__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); - - printf("88E1116 Initialized on %s\n", name); + mv_phy_88e1116_init("egiga0"); } #endif /* CONFIG_RESET_PHY_R */ diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/edminiv2/edminiv2.h deleted file mode 100644 index 88e62b2..0000000 --- a/board/LaCie/edminiv2/edminiv2.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2009 - * Net Insight - * Written-by: Simon Kagstrom - * - * Based on sheevaplug.h: - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __EDMINIV2_BASE_H -#define __EDMINIV2_BASE_H - -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -#endif /* __EDMINIV2_BASE_H */ diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile index 4bacef4..fbae48e 100644 --- a/board/LaCie/net2big_v2/Makefile +++ b/board/LaCie/net2big_v2/Makefile @@ -21,10 +21,13 @@ # include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).o -COBJS := net2big_v2.o +COBJS := $(BOARD).o ../common/common.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 16d1405..d0b4adf 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -21,15 +21,14 @@ */ #include -#include -#include #include -#include #include #include #include #include + #include "net2big_v2.h" +#include "../common/common.h" DECLARE_GLOBAL_DATA_PTR; @@ -92,91 +91,29 @@ int board_init(void) return 0; } +#if defined(CONFIG_MISC_INIT_R) int misc_init_r(void) { -#ifdef CONFIG_CMD_I2C +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) if (!getenv("ethaddr")) { - ushort version; uchar mac[6]; - int ret; - - /* I2C-0 for on-board EEPROM */ - i2c_set_bus_num(0); - - /* Check layout version for EEPROM data */ - ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (uchar *) &version, 2); - if (ret != 0) { - printf("Error: failed to read I2C EEPROM @%02x\n", - CONFIG_SYS_I2C_EEPROM_ADDR); - return ret; - } - version = be16_to_cpu(version); - if (version < 1 || version > 3) { - printf("Error: unknown version %d for EEPROM data\n", - version); - return -1; - } - - /* Read Ethernet MAC address from EEPROM */ - ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac, 6); - if (ret != 0) { - printf("Error: failed to read I2C EEPROM @%02x\n", - CONFIG_SYS_I2C_EEPROM_ADDR); - return ret; - } - eth_setenv_enetaddr("ethaddr", mac); + if (lacie_read_mac_address(mac) == 0) + eth_setenv_enetaddr("ethaddr", mac); } -#endif /* CONFIG_CMD_I2C */ - +#endif return 0; } +#endif -void mv_phy_88e1116_init(char *name) -{ - u16 reg; - u16 devadr; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..(%s) could not read PHY dev address\n", __func__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - if (miiphy_read(name, devadr, MII_BMCR, ®) != 0) { - printf("Err..(%s) PHY status read failed\n", __func__); - return; - } - if (miiphy_write(name, devadr, MII_BMCR, reg | 0x8000) != 0) { - printf("Err..(%s) PHY reset failed\n", __func__); - return; - } - - debug("88E1116 Initialized on %s\n", name); -} - +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) /* Configure and initialize PHY */ void reset_phy(void) { mv_phy_88e1116_init("egiga0"); } +#endif +#if defined(CONFIG_KIRKWOOD_GPIO) /* Return GPIO push button status */ static int do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -186,3 +123,4 @@ do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD(button, 1, 1, do_read_push_button, "Return GPIO push button status 0=off 1=on", ""); +#endif diff --git a/board/LaCie/net2big_v2/net2big_v2.h b/board/LaCie/net2big_v2/net2big_v2.h index bbe67af..f9778f4 100644 --- a/board/LaCie/net2big_v2/net2big_v2.h +++ b/board/LaCie/net2big_v2/net2big_v2.h @@ -32,12 +32,4 @@ /* Buttons */ #define NET2BIG_V2_GPIO_PUSH_BUTTON 34 -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - #endif /* NET2BIG_V2_H */ diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile index d4a613f..b43c3d3 100644 --- a/board/LaCie/netspace_v2/Makefile +++ b/board/LaCie/netspace_v2/Makefile @@ -21,10 +21,13 @@ # include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).o -COBJS := netspace_v2.o +COBJS := $(BOARD).o ../common/common.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 6938a43..fbf020f 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -21,15 +21,14 @@ */ #include -#include -#include #include -#include #include #include #include #include + #include "netspace_v2.h" +#include "../common/common.h" DECLARE_GLOBAL_DATA_PTR; @@ -90,91 +89,29 @@ int board_init(void) return 0; } +#if defined(CONFIG_MISC_INIT_R) int misc_init_r(void) { #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) if (!getenv("ethaddr")) { - ushort version; uchar mac[6]; - int ret; - - /* I2C-0 for on-board EEPROM */ - i2c_set_bus_num(0); - - /* Check layout version for EEPROM data */ - ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (uchar *) &version, 2); - if (ret != 0) { - printf("Error: failed to read I2C EEPROM @%02x\n", - CONFIG_SYS_I2C_EEPROM_ADDR); - return ret; - } - version = be16_to_cpu(version); - if (version < 1 || version > 3) { - printf("Error: unknown version %d for EEPROM data\n", - version); - return -1; - } - - /* Read Ethernet MAC address from EEPROM */ - ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac, 6); - if (ret != 0) { - printf("Error: failed to read I2C EEPROM @%02x\n", - CONFIG_SYS_I2C_EEPROM_ADDR); - return ret; - } - eth_setenv_enetaddr("ethaddr", mac); + if (lacie_read_mac_address(mac) == 0) + eth_setenv_enetaddr("ethaddr", mac); } -#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */ - +#endif return 0; } +#endif -void mv_phy_88e1116_init(char *name) -{ - u16 reg; - u16 devadr; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..(%s) could not read PHY dev address\n", __func__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - if (miiphy_read(name, devadr, MII_BMCR, ®) != 0) { - printf("Err..(%s) PHY status read failed\n", __func__); - return; - } - if (miiphy_write(name, devadr, MII_BMCR, reg | 0x8000) != 0) { - printf("Err..(%s) PHY reset failed\n", __func__); - return; - } - - debug("88E1116 Initialized on %s\n", name); -} - +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) /* Configure and initialize PHY */ void reset_phy(void) { mv_phy_88e1116_init("egiga0"); } +#endif +#if defined(CONFIG_KIRKWOOD_GPIO) /* Return GPIO button status */ static int do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -184,3 +121,4 @@ do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD(button, 1, 1, do_read_button, "Return GPIO button status 0=off 1=on", ""); +#endif diff --git a/board/LaCie/netspace_v2/netspace_v2.h b/board/LaCie/netspace_v2/netspace_v2.h index 3f3d51c..34e492c 100644 --- a/board/LaCie/netspace_v2/netspace_v2.h +++ b/board/LaCie/netspace_v2/netspace_v2.h @@ -31,12 +31,4 @@ #define NETSPACE_V2_GPIO_BUTTON 32 -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - #endif /* NETSPACE_V2_H */ diff --git a/boards.cfg b/boards.cfg index d16789b..9869dd6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -140,10 +140,10 @@ km_kirkwood arm arm926ejs km_arm keymile km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_RECONFIG_XLX mgcoge3un arm arm926ejs km_arm keymile kirkwood portl2 arm arm926ejs km_arm keymile kirkwood -inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:INETSPACE_V2 -net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood -netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:NETSPACE_V2 -netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:NETSPACE_MAX_V2 +inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 +net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2 +netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2 +netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2 dreamplug arm arm926ejs - Marvell kirkwood guruplug arm arm926ejs - Marvell kirkwood mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h new file mode 100644 index 0000000..6cbc752 --- /dev/null +++ b/include/configs/lacie_kw.h @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2011 Simon Guinot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CONFIG_LACIE_KW_H +#define _CONFIG_LACIE_KW_H + +/* + * Machine number definition + */ +#if defined(CONFIG_INETSPACE_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2 +#define CONFIG_IDENT_STRING " IS v2" +#elif defined(CONFIG_NETSPACE_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2 +#define CONFIG_IDENT_STRING " NS v2" +#elif defined(CONFIG_NETSPACE_MAX_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 +#define CONFIG_IDENT_STRING " NS Max v2" +#elif defined(CONFIG_NET2BIG_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2 +#define CONFIG_IDENT_STRING " 2Big v2" +#else +#error "Unknown board" +#endif + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include +#define CONFIG_CMD_ENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_USB + +/* + * Core clock definition + */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +/* + * SDRAM configuration + */ +#if defined(CONFIG_NET2BIG_V2) +#define CONFIG_NR_DRAM_BANKS 2 +#else +#define CONFIG_NR_DRAM_BANKS 1 +#endif + +#ifdef CONFIG_INETSPACE_V2 +/* Different SDRAM configuration and size for Internet Space v2 */ +#define CONFIG_SYS_KWD_CONFIG ($(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg) +#endif + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_RBTREE +#undef CONFIG_ENV_SPI_MAX_HZ +#undef CONFIG_SYS_IDE_MAXBUS +#undef CONFIG_SYS_IDE_MAXDEVICE +#undef CONFIG_SYS_PROMPT +#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 +#if defined(CONFIG_NET2BIG_V2) +#define CONFIG_SYS_PROMPT "2big2> " +#else +#define CONFIG_SYS_PROMPT "ns2> " +#endif + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MISC_INIT_R /* Call misc_init_r() to initialize MAC address */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_NETCONSOLE +#endif + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_NET2BIG_V2) +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif +#endif /* CONFIG_MVSATA_IDE */ + +/* + * Enable GPI0 support + */ +#define CONFIG_KIRKWOOD_GPIO + +/* + * Enable I2C support + */ +#ifdef CONFIG_CMD_I2C +/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ +#endif /* CONFIG_CMD_I2C */ + +/* + * File systems support + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Console configuration + */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + +/* + * Environment variables configurations + */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */ +#define CONFIG_ENV_SIZE 0x1000 /* 4KB */ +#define CONFIG_ENV_ADDR 0x70000 +#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTARGS "console=ttyS0,115200" + +#define CONFIG_BOOTCOMMAND \ + "dhcp && run netconsole; " \ + "if run usbload || run diskload; then bootm; fi" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "bootfile=uImage\0" \ + "loadaddr=0x800000\0" \ + "autoload=no\0" \ + "netconsole=" \ + "set stdin $stdin,nc; " \ + "set stdout $stdout,nc; " \ + "set stderr $stderr,nc;\0" \ + "diskload=ide reset && " \ + "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ + "usbload=usb start && " \ + "fatload usb 0:1 $loadaddr /boot/$bootfile\0" + +#endif /* _CONFIG_LACIE_KW_H */ diff --git a/include/configs/net2big_v2.h b/include/configs/net2big_v2.h deleted file mode 100644 index 9cf76d0..0000000 --- a/include/configs/net2big_v2.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (C) 2011 Simon Guinot - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _CONFIG_NET2BIG_V2_H -#define _CONFIG_NET2BIG_V2_H - -/* - * Machine number information - */ -#define CONFIG_IDENT_STRING " 2Big v2" - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD /* SOC Family Name */ -#define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_MACH_NET2BIG_V2 /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#include -#define CONFIG_CMD_ENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_SF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_USB - -/* - * Core clock definition. - */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#define CONFIG_NR_DRAM_BANKS 2 -#include "mv-common.h" - -/* Remove or override few declarations from mv-common.h */ -#undef CONFIG_RBTREE -#undef CONFIG_ENV_SPI_MAX_HZ -#undef CONFIG_SYS_IDE_MAXBUS -#undef CONFIG_SYS_IDE_MAXDEVICE -#undef CONFIG_SYS_PROMPT -#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 -#define CONFIG_SYS_PROMPT "2big2> " - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MISC_INIT_R /* Call misc_init_r() to initialize MAC address */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_NETCONSOLE -#endif - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif - -/* - * Enable GPI0 support - */ -#define CONFIG_KIRKWOOD_GPIO - -/* - * Enable I2C support - */ -#ifdef CONFIG_CMD_I2C -/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ -#define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ -#endif /* CONFIG_CMD_I2C */ - -/* - * File systems support - */ -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - -/* - * Use the HUSH parser - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -/* - * Console configuration - */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -/* - * Enable device tree support - */ -#define CONFIG_OF_LIBFDT - -/* - * Environment variables configurations - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */ -#define CONFIG_ENV_SIZE 0x1000 /* 4KB */ -#define CONFIG_ENV_ADDR 0x70000 -#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTARGS "console=ttyS0,115200" - -#define CONFIG_BOOTCOMMAND \ - "dhcp && run netconsole; " \ - "if run usbload || run diskload; then bootm; fi" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "bootfile=uImage\0" \ - "loadaddr=0x800000\0" \ - "autoload=no\0" \ - "netconsole=" \ - "set stdin $stdin,nc; " \ - "set stdout $stdout,nc; " \ - "set stderr $stderr,nc;\0" \ - "diskload=ide reset && " \ - "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ - "usbload=usb start && " \ - "fatload usb 0:1 $loadaddr /boot/$bootfile\0" - -#endif /* _CONFIG_NET2BIG_V2_H */ diff --git a/include/configs/netspace_v2.h b/include/configs/netspace_v2.h deleted file mode 100644 index 1ddf4b4..0000000 --- a/include/configs/netspace_v2.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (C) 2011 Simon Guinot - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _CONFIG_NETSPACE_V2_H -#define _CONFIG_NETSPACE_V2_H - -/* - * Machine number definition - */ -#if defined(CONFIG_INETSPACE_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2 -#define CONFIG_IDENT_STRING " IS v2" -#elif defined(CONFIG_NETSPACE_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2 -#define CONFIG_IDENT_STRING " NS v2" -#elif defined(CONFIG_NETSPACE_MAX_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 -#define CONFIG_IDENT_STRING " NS Max v2" -#else -#error "Unknown board" -#endif - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD /* SOC Family Name */ -#define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#include -#define CONFIG_CMD_ENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_SF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_USB - -/* - * Core clock definition. - */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ - -#define CONFIG_NR_DRAM_BANKS 1 -#ifdef CONFIG_INETSPACE_V2 -/* Different SDRAM configuration and size for Internet Space v2 */ -#define CONFIG_SYS_KWD_CONFIG ($(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg) -#endif - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* Remove or override few declarations from mv-common.h */ -#undef CONFIG_RBTREE -#undef CONFIG_ENV_SPI_MAX_HZ -#undef CONFIG_SYS_IDE_MAXBUS -#undef CONFIG_SYS_IDE_MAXDEVICE -#undef CONFIG_SYS_PROMPT -#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 -#define CONFIG_SYS_PROMPT "ns2> " - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MISC_INIT_R /* Call misc_init_r() to initialize MAC address */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_NETCONSOLE -#endif - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -/* Network Space Max v2 use 2 SATA ports */ -#ifdef CONFIG_NETSPACE_MAX_V2 -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif -#endif - -/* - * Enable GPI0 support - */ -#define CONFIG_KIRKWOOD_GPIO - -/* - * Enable I2C support - */ -#ifdef CONFIG_CMD_I2C -/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ -#define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ -#endif /* CONFIG_CMD_I2C */ - -/* - * File systems support - */ -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - -/* - * Use the HUSH parser - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -/* - * Console configuration - */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -/* - * Enable device tree support - */ -#define CONFIG_OF_LIBFDT - -/* - * Environment variables configurations - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */ -#define CONFIG_ENV_SIZE 0x1000 /* 4KB */ -#define CONFIG_ENV_ADDR 0x70000 -#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTARGS "console=ttyS0,115200" - -#define CONFIG_BOOTCOMMAND \ - "dhcp && run netconsole; " \ - "if run usbload || run diskload; then bootm; fi" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "bootfile=uImage\0" \ - "loadaddr=0x800000\0" \ - "autoload=no\0" \ - "netconsole=" \ - "set stdin $stdin,nc; " \ - "set stdout $stdout,nc; " \ - "set stderr $stderr,nc;\0" \ - "diskload=ide reset && " \ - "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ - "usbload=usb start && " \ - "fatload usb 0:1 $loadaddr /boot/$bootfile\0" - -#endif /* _CONFIG_NETSPACE_V2_H */ -- cgit v0.10.2 From 28cb465f78027c2e7eb6678a61bf5c71e6b2cdeb Mon Sep 17 00:00:00 2001 From: Ajay Bhargav Date: Mon, 31 Oct 2011 01:19:37 +0000 Subject: net: Armada100: Fix compilation warnings This patch fix compilation warnings for Armada100 FEC driver Ref: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Ajay Bhargav Acked-by: Anatolij Gustschin diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c index fbf9763..1a54362 100644 --- a/drivers/net/armada100_fec.c +++ b/drivers/net/armada100_fec.c @@ -440,6 +440,7 @@ static int armdfec_init(struct eth_device *dev, bd_t *bd) struct armdfec_device *darmdfec = to_darmdfec(dev); struct armdfec_reg *regs = darmdfec->regs; int phy_adr; + u32 temp; armdfec_init_rx_desc_ring(darmdfec); @@ -479,9 +480,12 @@ static int armdfec_init(struct eth_device *dev, bd_t *bd) update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr); /* Update TX and RX queue descriptor register */ - writel((u32)darmdfec->p_txdesc, ®s->txcdp[TXQ]); - writel((u32)darmdfec->p_rxdesc, ®s->rxfdp[RXQ]); - writel((u32)darmdfec->p_rxdesc_curr, ®s->rxcdp[RXQ]); + temp = (u32)®s->txcdp[TXQ]; + writel((u32)darmdfec->p_txdesc, temp); + temp = (u32)®s->rxfdp[RXQ]; + writel((u32)darmdfec->p_rxdesc, temp); + temp = (u32)®s->rxcdp[RXQ]; + writel((u32)darmdfec->p_rxdesc_curr, temp); /* Enable Interrupts */ writel(ALL_INTS, ®s->im); @@ -614,6 +618,7 @@ static int armdfec_recv(struct eth_device *dev) struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr; u32 cmd_sts; u32 timeout = 0; + u32 temp; /* wait untill rx packet available or timeout */ do { @@ -667,7 +672,8 @@ static int armdfec_recv(struct eth_device *dev) p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; p_rxdesc_curr->byte_cnt = 0; - writel((u32)p_rxdesc_curr->nxtdesc_p, (u32)&darmdfec->p_rxdesc_curr); + temp = (u32)&darmdfec->p_rxdesc_curr; + writel((u32)p_rxdesc_curr->nxtdesc_p, temp); return 0; } -- cgit v0.10.2 From 14c326149739b784bbb8b57f5bbec61f1723efab Mon Sep 17 00:00:00 2001 From: Tim Schendekehl Date: Tue, 1 Nov 2011 23:55:01 +0000 Subject: Ethernut 5 board support Add support for the Ethernut 5 open hardware design, based on Atmel's AT91SAM9XE512 SoC. V4 - Fix several coding style issues. - Move machine type to config file. - Remove use of CONFIG_ATMEL_LEGACY. Signed-off-by: Tim Schendekehl diff --git a/MAINTAINERS b/MAINTAINERS index 3a6d29c..4aa54d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -142,6 +142,10 @@ Phil Edworthy rsk7264 SH7264 +egnite GmbH + + ethernut5 ARM926EJS (AT91SAM9XE SoC) + Dirk Eibach devconcenter PPC460EX diff --git a/board/egnite/ethernut5/Makefile b/board/egnite/ethernut5/Makefile new file mode 100644 index 0000000..8dc85d2 --- /dev/null +++ b/board/egnite/ethernut5/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2010 +# egnite GmbH +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += $(BOARD)_pwrman.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c new file mode 100644 index 0000000..e42e91e --- /dev/null +++ b/board/egnite/ethernut5/ethernut5.c @@ -0,0 +1,270 @@ +/* + * (C) Copyright 2011 + * egnite GmbH + * + * (C) Copyright 2010 + * Ole Reinhardt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ethernut 5 general board support + * + * Ethernut is an open source hardware and software project for + * embedded Ethernet devices. Hardware layouts and CAD files are + * freely available under BSD-like license. + * + * Ethernut 5 is the first member of the Ethernut board family + * with U-Boot and Linux support. This implementation is based + * on the original work done by Ole Reinhardt, but heavily modified + * to support additional features and the latest board revision 5.0F. + * + * Main board components are by default: + * + * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash + * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM + * 512 MBytes Micron MT29F4G08ABADA NAND Flash + * 4 MBytes Atmel AT45DB321D DataFlash + * SMSC LAN8710 Ethernet PHY + * Atmel ATmega168 MCU used for power management + * Linear Technology LTC4411 PoE controller + * + * U-Boot relevant board interfaces are: + * + * 100 Mbit Ethernet with IEEE 802.3af PoE + * RS-232 serial port + * USB host and device + * MMC/SD-Card slot + * Expansion port with I2C, SPI and more... + * + * Typically the U-Boot image is loaded from serial DataFlash into + * SDRAM by the samboot boot loader, which is located in internal + * NOR Flash and provides all essential initializations like CPU + * and peripheral clocks and, of course, the SDRAM configuration. + * + * For testing purposes it is also possibly to directly transfer + * the image into SDRAM via JTAG. A tested configuration exists + * for the Turtelizer 2 hardware dongle and the OpenOCD software. + * In this case the latter will do the basic hardware configuration + * via its reset-init script. + * + * For additional information visit the project home page at + * http://www.ethernut.de/ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ethernut5_pwrman.h" + +DECLARE_GLOBAL_DATA_PTR; + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0} +}; + +/* + * In fact we have 7 partitions, but u-boot supports 5 only. This is + * no big deal, because the first partition is reserved for applications + * and the last one is used by Nut/OS. Both need not to be visible here. + */ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + { 0x00021000, 0x00041FFF, FLAG_PROTECT_SET, 0, "setup" }, + { 0x00042000, 0x000C5FFF, FLAG_PROTECT_SET, 0, "uboot" }, + { 0x000C6000, 0x00359FFF, FLAG_PROTECT_SET, 0, "kernel" }, + { 0x0035A000, 0x003DDFFF, FLAG_PROTECT_SET, 0, "nutos" }, + { 0x003DE000, 0x003FEFFF, FLAG_PROTECT_CLEAR, 0, "env" } +}; + +/* + * This is called last during early initialization. Most of the basic + * hardware interfaces are up and running. + * + * The SDRAM hardware has been configured by the first stage boot loader. + * We only need to announce its size, using u-boot's memory check. + */ +int dram_init(void) +{ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_CMD_NAND +static void ethernut5_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + +#ifdef CONFIG_SYS_NAND_READY_PIN + /* Ready pin is optional. */ + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); +#endif + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +/* + * This is called first during late initialization. + */ +int board_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC), + &pmc->pcer); + /* Set adress of boot parameters. */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + /* Initialize UARTs and power management. */ + at91_seriald_hw_init(); + ethernut5_power_init(); +#ifdef CONFIG_CMD_NAND + ethernut5_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91_spi0_hw_init(1 << 0); +#endif + return 0; +} + +#ifdef CONFIG_MACB +/* + * This is optionally called last during late initialization. + */ +int board_eth_init(bd_t *bis) +{ + const char *devname; + unsigned short mode; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable on-chip EMAC clock. */ + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + /* Need to reset PHY via power management. */ + ethernut5_phy_reset(); + /* Set peripheral pins. */ + at91_macb_hw_init(); + /* Basic EMAC initialization. */ + if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID)) + return -1; + /* + * Early board revisions have a pull-down at the PHY's MODE0 + * strap pin, which forces the PHY into power down. Here we + * switch to all-capable mode. + */ + devname = miiphy_get_current_dev(); + if (miiphy_read(devname, 0, 18, &mode) == 0) { + /* Set mode[2:0] to 0b111. */ + mode |= 0x00E0; + miiphy_write(devname, 0, 18, mode); + /* Soft reset overrides strap pins. */ + miiphy_write(devname, 0, MII_BMCR, BMCR_RESET); + } + /* Sync environment with network devices, needed for nfsroot. */ + return eth_init(gd->bd); +} +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bd) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable MCI clock. */ + writel(1 << ATMEL_ID_MCI, &pmc->pcer); + /* Initialize MCI hardware. */ + at91_mci_hw_init(); + /* Register the device. */ + return atmel_mci_init((void *)ATMEL_BASE_MCI); +} + +int board_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + *cd = at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN) ? 1 : 0; + return 0; +} +#endif + +#ifdef CONFIG_ATMEL_SPI +/* + * Note, that u-boot uses different code for SPI bus access. While + * memory routines use automatic chip select control, the serial + * flash support requires 'manual' GPIO control. Thus, we switch + * modes. + */ +void spi_cs_activate(struct spi_slave *slave) +{ + /* Enable NPCS0 in GPIO mode. This disables peripheral control. */ + at91_set_pio_output(AT91_PIO_PORTA, 3, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* Disable NPCS0 in GPIO mode. */ + at91_set_pio_output(AT91_PIO_PORTA, 3, 1); + /* Switch back to peripheral chip select control. */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 1); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} +#endif diff --git a/board/egnite/ethernut5/ethernut5_pwrman.c b/board/egnite/ethernut5/ethernut5_pwrman.c new file mode 100644 index 0000000..4b00038 --- /dev/null +++ b/board/egnite/ethernut5/ethernut5_pwrman.c @@ -0,0 +1,338 @@ +/* + * (C) Copyright 2011 + * egnite GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ethernut 5 power management support + * + * This board may be supplied via USB, IEEE 802.3af PoE or an + * auxiliary DC input. An on-board ATmega168 microcontroller, + * the so called power management controller or PMC, is used + * to select the supply source and to switch on and off certain + * energy consuming board components. This allows to reduce the + * total stand-by consumption to less than 70mW. + * + * The main CPU communicates with the PMC via I2C. When + * CONFIG_CMD_BSP is defined in the board configuration file, + * then the board specific command 'pwrman' becomes available, + * which allows to manually deal with the PMC. + * + * Two distinct registers are provided by the PMC for enabling + * and disabling specific features. This avoids the often seen + * read-modify-write cycle or shadow register requirement. + * Additional registers are available to query the board + * status and temperature, the auxiliary voltage and to control + * the green user LED that is integrated in the reset switch. + * + * Note, that the AVR firmware of the PMC is released under BSDL. + * + * For additional information visit the project home page at + * http://www.ethernut.de/ + */ +#include +#include +#include +#include +#include +#include + +#include "ethernut5_pwrman.h" + +/* PMC firmware version */ +static int pwrman_major; +static int pwrman_minor; + +/* + * Enable Ethernut 5 power management. + * + * This function must be called during board initialization. + * While we are using u-boot's I2C subsystem, it may be required + * to enable the serial port before calling this function, + * in particular when debugging is enabled. + * + * If board specific commands are not available, we will activate + * all board components. + */ +void ethernut5_power_init(void) +{ + pwrman_minor = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VERS); + pwrman_major = pwrman_minor >> 4; + pwrman_minor &= 15; + +#ifndef CONFIG_CMD_BSP + /* Do not modify anything, if we do not have a known version. */ + if (pwrman_major == 2) { + /* Without board specific commands we enable all features. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, ~PWRMAN_ETHRST); + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); + } +#endif +} + +/* + * Reset Ethernet PHY. + * + * This function allows the re-configure the PHY after + * changing its strap pins. + */ +void ethernut5_phy_reset(void) +{ + /* Do not modify anything, if we do not have a known version. */ + if (pwrman_major != 2) + return; + + /* + * Make sure that the Ethernet clock is enabled and the PHY reset + * is disabled for at least 100 us. + */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHCLK); + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); + udelay(100); + + /* + * LAN8710 strap pins are + * PA14 => PHY MODE0 + * PA15 => PHY MODE1 + * PA17 => PHY MODE2 => 111b all capable + * PA18 => PHY ADDR0 => 0b + */ + at91_set_pio_input(AT91_PIO_PORTA, 14, 1); + at91_set_pio_input(AT91_PIO_PORTA, 15, 1); + at91_set_pio_input(AT91_PIO_PORTA, 17, 1); + at91_set_pio_input(AT91_PIO_PORTA, 18, 0); + + /* Activate PHY reset for 100 us. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHRST); + udelay(100); + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); + + at91_set_pio_input(AT91_PIO_PORTA, 14, 1); +} + +/* + * Output the firmware version we got during initialization. + */ +void ethernut5_print_version(void) +{ + printf("%u.%u\n", pwrman_major, pwrman_minor); +} + +/* + * All code below this point is optional and implements + * the 'pwrman' command. + */ +#ifdef CONFIG_CMD_BSP + +/* Human readable names of PMC features */ +char *pwrman_feat[8] = { + "board", "vbin", "vbout", "mmc", + "rs232", "ethclk", "ethrst", "wakeup" +}; + +/* + * Print all feature names, that have its related flags enabled. + */ +static void print_flagged_features(u8 flags) +{ + int i; + + for (i = 0; i < 8; i++) { + if (flags & (1 << i)) + printf("%s ", pwrman_feat[i]); + } +} + +/* + * Return flags of a given list of feature names. + * + * The function stops at the first unknown list entry and + * returns the number of detected names as a function result. + */ +static int feature_flags(char * const names[], int num, u8 *flags) +{ + int i, j; + + *flags = 0; + for (i = 0; i < num; i++) { + for (j = 0; j < 8; j++) { + if (strcmp(pwrman_feat[j], names[i]) == 0) { + *flags |= 1 << j; + break; + } + } + if (j > 7) + break; + } + return i; +} + +void ethernut5_print_power(void) +{ + u8 flags; + int i; + + flags = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA); + for (i = 0; i < 2; i++) { + if (flags) { + print_flagged_features(flags); + printf("%s\n", i ? "off" : "on"); + } + flags = ~flags; + } +} + +void ethernut5_print_celsius(void) +{ + int val; + + /* Read ADC value from LM50 and return Celsius degrees. */ + val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_TEMP); + val *= 5000; /* 100mV/degree with 5V reference */ + val += 128; /* 8 bit resolution */ + val /= 256; + val -= 450; /* Celsius offset, still x10 */ + /* Output full degrees. */ + printf("%d\n", (val + 5) / 10); +} + +void ethernut5_print_voltage(void) +{ + int val; + + /* Read ADC value from divider and return voltage. */ + val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VAUX); + /* Resistors are 100k and 12.1k */ + val += 5; + val *= 180948; + val /= 100000; + val++; + /* Calculation was done in 0.1V units. */ + printf("%d\n", (val + 5) / 10); +} + +/* + * Process the board specific 'pwrman' command. + */ +int do_pwrman(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u8 val; + int i; + + if (argc == 1) { + ethernut5_print_power(); + } else if (argc == 2 && strcmp(argv[1], "reset") == 0) { + at91_set_pio_output(AT91_PIO_PORTB, 8, 1); + udelay(100); + at91_set_pio_output(AT91_PIO_PORTB, 8, 0); + udelay(100000); + } else if (argc == 2 && strcmp(argv[1], "temp") == 0) { + ethernut5_print_celsius(); + } else if (argc == 2 && strcmp(argv[1], "vaux") == 0) { + ethernut5_print_voltage(); + } else if (argc == 2 && strcmp(argv[1], "version") == 0) { + ethernut5_print_version(); + } else if (strcmp(argv[1], "led") == 0) { + /* Control the green status LED. Blink frequency unit + ** is 0.1s, very roughly. */ + if (argc == 2) { + /* No more arguments, output current settings. */ + val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL); + printf("led %u %u\n", val >> 4, val & 15); + } else { + /* First argument specifies the on-time. */ + val = (u8) simple_strtoul(argv[2], NULL, 0); + val <<= 4; + if (argc > 3) { + /* Second argument specifies the off-time. */ + val |= (u8) (simple_strtoul(argv[3], NULL, 0) + & 15); + } + /* Update the LED control register. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL, val); + } + } else { + /* We expect a list of features followed an optional status. */ + argc--; + i = feature_flags(&argv[1], argc, &val); + if (argc == i) { + /* We got a list only, print status. */ + val &= i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_STA); + if (val) { + if (i > 1) + print_flagged_features(val); + printf("active\n"); + } else { + printf("inactive\n"); + } + } else { + /* More arguments. */ + if (i == 0) { + /* No given feature, use despensibles. */ + val = PWRMAN_DISPENSIBLE; + } + if (strcmp(argv[i + 1], "on") == 0) { + /* Enable features. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, + val); + } else if (strcmp(argv[i + 1], "off") == 0) { + /* Disable features. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, + val); + } else { + printf("Bad parameter %s\n", argv[i + 1]); + return 1; + } + } + } + return 0; +} + +U_BOOT_CMD( + pwrman, CONFIG_SYS_MAXARGS, 1, do_pwrman, + "power management", + "- print settings\n" + "pwrman feature ...\n" + " - print status\n" + "pwrman [feature ...] on|off\n" + " - enable/disable specified or all dispensible features\n" + "pwrman led [on-time [off-time]]\n" + " - print or set led blink timer\n" + "pwrman temp\n" + " - print board temperature (Celsius)\n" + "pwrman vaux\n" + " - print auxiliary input voltage\n" + "pwrman reset\n" + " - reset power management controller\n" + "pwrman version\n" + " - print firmware version\n" + "\n" + " features, (*)=dispensible:\n" + " board - 1.8V and 3.3V supply\n" + " vbin - supply via USB device connector\n" + " vbout - USB host connector supply(*)\n" + " mmc - MMC slot supply(*)\n" + " rs232 - RS232 driver\n" + " ethclk - Ethernet PHY clock(*)\n" + " ethrst - Ethernet PHY reset\n" + " wakeup - RTC alarm" +); +#endif /* CONFIG_CMD_BSP */ diff --git a/board/egnite/ethernut5/ethernut5_pwrman.h b/board/egnite/ethernut5/ethernut5_pwrman.h new file mode 100644 index 0000000..0541884 --- /dev/null +++ b/board/egnite/ethernut5/ethernut5_pwrman.h @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2011 + * egnite GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ethernut 5 power management support + * + * For additional information visit the project home page at + * http://www.ethernut.de/ + */ + +/* I2C address of the PMC */ +#define PWRMAN_I2C_ADDR 0x22 + +/* PMC registers */ +#define PWRMAN_REG_VERS 0 /* Version register */ +#define PWRMAN_REG_STA 1 /* Feature status register */ +#define PWRMAN_REG_ENA 2 /* Feature enable register */ +#define PWRMAN_REG_DIS 3 /* Feature disable register */ +#define PWRMAN_REG_TEMP 4 /* Board temperature */ +#define PWRMAN_REG_VAUX 6 /* Auxiliary input voltage */ +#define PWRMAN_REG_LEDCTL 8 /* LED blinking timer. */ + +/* Feature flags used in status, enable and disable registers */ +#define PWRMAN_BOARD 0x01 /* 1.8V and 3.3V supply */ +#define PWRMAN_VBIN 0x02 /* VBUS input at device connector */ +#define PWRMAN_VBOUT 0x04 /* VBUS output at host connector */ +#define PWRMAN_MMC 0x08 /* Memory card supply */ +#define PWRMAN_RS232 0x10 /* RS-232 driver shutdown */ +#define PWRMAN_ETHCLK 0x20 /* Ethernet clock enable */ +#define PWRMAN_ETHRST 0x40 /* Ethernet PHY reset */ +#define PWRMAN_WAKEUP 0x80 /* RTC wake-up */ + +/* Features, which are not essential to keep u-boot alive */ +#define PWRMAN_DISPENSIBLE (PWRMAN_VBOUT | PWRMAN_MMC | PWRMAN_ETHCLK) + +/* Enable Ethernut 5 power management. */ +extern void ethernut5_power_init(void); + +/* Reset Ethernet PHY. */ +extern void ethernut5_phy_reset(void); + +extern void ethernut5_print_version(void); + +#ifdef CONFIG_CMD_BSP +extern void ethernut5_print_power(void); +extern void ethernut5_print_celsius(void); +extern void ethernut5_print_voltage(void); +#endif diff --git a/boards.cfg b/boards.cfg index 9869dd6..8280cb9 100644 --- a/boards.cfg +++ b/boards.cfg @@ -110,6 +110,7 @@ cpu9G20 arm arm926ejs cpu9260 eukrea cpu9G20_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,NANDBOOT cpu9G20_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,CPU9G20_128M cpu9G20_nand_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT +ethernut5 arm arm926ejs ethernut5 egnite at91 ethernut5:AT91SAM9XE top9000eval_xe arm arm926ejs top9000 emk at91 top9000:EVAL9000 top9000su_xe arm arm926ejs top9000 emk at91 top9000:SU9000 meesc arm arm926ejs meesc esd at91 meesc:AT91SAM9263,SYS_USE_NANDFLASH diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h new file mode 100644 index 0000000..f878665 --- /dev/null +++ b/include/configs/ethernut5.h @@ -0,0 +1,287 @@ +/* + * (C) Copyright 2011 + * egnite GmbH + * + * Configuation settings for Ethernut 5 with AT91SAM9XE. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* The first stage boot loader expects u-boot running at this address. */ +#define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */ + +/* The first stage boot loader takes care of low level initialization. */ +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Set our official architecture number. */ +#define MACH_TYPE_ETHERNUT5 1971 +#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 + +/* CPU information */ +#define CONFIG_ARM926EJS +#define CONFIG_AT91FAMILY +#define CONFIG_DISPLAY_CPUINFO /* Display at console. */ +#define CONFIG_ARCH_CPU_INIT + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ +#define CONFIG_SYS_HZ 1000 +#undef CONFIG_USE_IRQ /* Running w/o interrupts */ + +/* 32kB internal SRAM */ +#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ +#define CONFIG_SRAM_SIZE (32 << 10) +#define CONFIG_STACKSIZE (CONFIG_SRAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_STACKSIZE) + +/* 128MB SDRAM in 1 bank */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE (128 << 20) +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \ + - CONFIG_SYS_MALLOC_LEN) + +/* 512kB on-chip NOR flash */ +# define CONFIG_SYS_MAX_FLASH_BANKS 1 +# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ +# define CONFIG_AT91_EFLASH +# define CONFIG_SYS_MAX_FLASH_SECT 32 +# define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */ +# define CONFIG_EFLASH_PROTSECTORS 1 + +/* 512kB DataFlash at NPCS0 */ +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_HAS_DATAFLASH +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x3DE000 +#define CONFIG_ENV_SECT_SIZE (132 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \ + + CONFIG_ENV_OFFSET) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \ + + 0x042000) + +/* SPI */ +#define CONFIG_ATMEL_SPI +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +#define AT91_SPI_CLK 15000000 + +/* Serial port */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART3 /* USART 3 is DBGU */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS + +/* Misc. hardware drivers */ +#define CONFIG_AT91_GPIO + +/* Command line configuration */ +#include +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS + +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_SPI + +#ifdef MINIMAL_LOADER +#undef CONFIG_CMD_CONSOLE +#undef CONFIG_CMD_EDITENV +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_ITEST +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG +#else +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BSP +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_CDP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DNS +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_RARP +#define CONFIG_CMD_REISER +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_SF +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_UNZIP +#define CONFIG_CMD_USB +#endif + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 +#define CONFIG_NAND_ATMEL +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 +#endif + +/* JFFS2 */ +#ifdef CONFIG_CMD_JFFS2 +#define CONFIG_MTD_NAND_ECC_JFFS2 +#define CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_NAND +#endif + +/* Ethernet */ +#define CONFIG_NET_MULTI +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_PHY_ID 0 +#define CONFIG_MACB_SEARCH_PHY + +/* MMC */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#endif + +/* RTC */ +#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) +#define CONFIG_RTC_PCF8563 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#endif + +/* I2C */ +#define CONFIG_SYS_MAX_I2C_BUS 1 +#define CONFIG_SYS_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SOFT_I2C +#define I2C_SOFT_DECLARATIONS + +#define GPIO_I2C_SCL AT91_PIO_PORTA, 24 +#define GPIO_I2C_SDA AT91_PIO_PORTA, 23 + +#define I2C_INIT { \ + at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \ + at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ + at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \ + at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \ + at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ +} + +#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0) +#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0) +#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) +#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) +#define I2C_DELAY udelay(100) +#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) + +/* DHCP/BOOTP options */ +#ifdef CONFIG_CMD_DHCP +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_SYS_AUTOLOAD "n" +#endif + +/* File systems */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND) +#define MTDIDS_DEFAULT "nand0=atmel_nand" +#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)" +#endif +#if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \ + defined(CONFIG_CMD_USB) || defined(CONFIG_MMC) +#define CONFIG_DOS_PARTITION +#endif +#define CONFIG_LZO +#define CONFIG_RBTREE + +/* Boot command */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm" +#if defined(CONFIG_CMD_NAND) +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + MTDPARTS_DEFAULT \ + " rw rootfstype=jffs2" +#endif + +/* Misc. u-boot settings */ +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \ + + sizeof(CONFIG_SYS_PROMPT)) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING + +#endif -- cgit v0.10.2 From 82645f816fe25b8ff1cda8cf509dfb4f3059c975 Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Mon, 31 Oct 2011 06:34:44 +0000 Subject: nand: Add common functions to linux/mtd/nand.h Functions often used in SPL are now part of linux/mtd/nand.h. Static modifiers are removed from these functions in drivers/mtd/nand/nand_base.c. Signed-off-by: Simon Schwarz Cc: scottwood@freescale.com Cc: s-paulraj@ti.com Cc: albert.u.boot@aribaud.net Acked-by: Scott Wood diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 6aac6a2..27f6c77 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -133,7 +133,7 @@ static void nand_release_device (struct mtd_info *mtd) * * Default read function for 8bit buswith */ -static uint8_t nand_read_byte(struct mtd_info *mtd) +uint8_t nand_read_byte(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; return readb(chip->IO_ADDR_R); @@ -196,7 +196,7 @@ static void nand_select_chip(struct mtd_info *mtd, int chipnr) * * Default write function for 8bit buswith */ -static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) { int i; struct nand_chip *chip = mtd->priv; @@ -249,7 +249,7 @@ static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) * * Default write function for 16bit buswith */ -static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) +void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) { int i; struct nand_chip *chip = mtd->priv; diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 987a2ec..1cdc7ae 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -623,4 +623,11 @@ struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) return chip->priv; } +/* Standard NAND functions from nand_base.c */ +void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); +void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); +void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); +void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); +uint8_t nand_read_byte(struct mtd_info *mtd); + #endif /* __LINUX_MTD_NAND_H */ diff --git a/include/nand.h b/include/nand.h index b4140794..d444ddc 100644 --- a/include/nand.h +++ b/include/nand.h @@ -135,9 +135,6 @@ int nand_get_lock_status(nand_info_t *meminfo, loff_t offset); int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst); void nand_deselect(void); -void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); -void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); - #ifdef CONFIG_SYS_NAND_SELECT_DEVICE void board_nand_select_device(struct nand_chip *nand, int chip); #endif -- cgit v0.10.2 From 56c91bc3b6be0551113df0eb1f0c8b1a597b9da1 Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Mon, 31 Oct 2011 06:34:45 +0000 Subject: Fix regression in SMDK6400 s3c64xx.c implemented its own nand_read_byte, nand_write_buf and nand_read_buf functions. This provoked a regression when these functions were made public by patch 55f429bb39614a16b1bacc9a8bea9ac01a60bfc8. This deletes these duplicated functions from s3c64xx.c and adds the generic implementations in nand_base.c to the spl Makefile. It also adds -ffcuntion-sections and -gc-sections to the compilation flags of the SPL to avoid errors originating from unused functions in nand_base.c. Description of the regression: http://article.gmane.org/gmane.comp.boot-loaders.u-boot/108873 Signed-off-by: Simon Schwarz Cc: scottwood@freescale.com Cc: s-paulraj@ti.com Cc: albert.u.boot@aribaud.net diff --git a/drivers/mtd/nand/s3c64xx.c b/drivers/mtd/nand/s3c64xx.c index 084e475..87f0341 100644 --- a/drivers/mtd/nand/s3c64xx.c +++ b/drivers/mtd/nand/s3c64xx.c @@ -28,6 +28,8 @@ #include #include +#include + #include #include @@ -60,32 +62,6 @@ static void print_oob(const char *header, struct mtd_info *mtd) } #endif /* S3C_NAND_DEBUG */ -#ifdef CONFIG_NAND_SPL -static u_char nand_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - return readb(this->IO_ADDR_R); -} - -static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - int i; - struct nand_chip *this = mtd->priv; - - for (i = 0; i < len; i++) - writeb(buf[i], this->IO_ADDR_W); -} - -static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - int i; - struct nand_chip *this = mtd->priv; - - for (i = 0; i < len; i++) - buf[i] = readb(this->IO_ADDR_R); -} -#endif - static void s3c_nand_select_chip(struct mtd_info *mtd, int chip) { int ctrl = readl(NFCONT); diff --git a/nand_spl/board/samsung/smdk6400/Makefile b/nand_spl/board/samsung/smdk6400/Makefile index 2f9c307..c9e75ba 100644 --- a/nand_spl/board/samsung/smdk6400/Makefile +++ b/nand_spl/board/samsung/smdk6400/Makefile @@ -33,12 +33,12 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) + $(LDFLAGS_FINAL) -gc-sections AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL -ffunction-sections SOBJS = start.o cpu_init.o lowlevel_init.o -COBJS = nand_boot.o nand_ecc.o s3c64xx.o smdk6400_nand_spl.o +COBJS = nand_boot.o nand_ecc.o s3c64xx.o smdk6400_nand_spl.o nand_base.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -98,6 +98,9 @@ $(obj)smdk6400_nand_spl.c: @rm -f $@ @ln -s $(TOPDIR)/board/samsung/smdk6400/smdk6400_nand_spl.c $@ +$(obj)nand_base.c: + @rm -f $@ + @ln -s $(TOPDIR)/drivers/mtd/nand/nand_base.c $@ ######################################################################### $(obj)%.o: $(obj)%.S -- cgit v0.10.2 From f13eba66fdbc19bd1a4725cb1a6c0a37b0445a36 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 20 Nov 2011 05:18:28 +0100 Subject: PXA: Drop CERF250 board The board is unmaintained and maintainer doesn't respond. Signed-off-by: Marek Vasut Cc: Simon Glass Cc: Anatolij Gustschin diff --git a/MAINTAINERS b/MAINTAINERS index 4aa54d7..7a5407c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -712,10 +712,6 @@ Sergey Kubushyn SONATA ARM926EJS SCHMOOGIE ARM926EJS -Prakash Kumar - - cerf250 xscale/pxa - Vipin Kumar spear300 ARM926EJS (spear300 Soc) diff --git a/board/cerf250/Makefile b/board/cerf250/Makefile deleted file mode 100644 index cf4742e..0000000 --- a/board/cerf250/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := cerf250.o flash.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/cerf250/cerf250.c b/board/cerf250/cerf250.c deleted file mode 100644 index 043afea..0000000 --- a/board/cerf250/cerf250.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of cerf PXA Board */ - gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/cerf250/flash.c b/board/cerf250/flash.c deleted file mode 100644 index e1e7807..0000000 --- a/board/cerf250/flash.c +++ /dev/null @@ -1,429 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/boards.cfg b/boards.cfg index 8280cb9..82c705d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -216,7 +216,6 @@ actux3 arm ixp actux4 arm ixp dvlhost arm ixp balloon3 arm pxa -cerf250 arm pxa colibri_pxa270 arm pxa cradle arm pxa lubbock arm pxa diff --git a/doc/README.scrapyard b/doc/README.scrapyard index d37dbcf..732d92d 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +cerf250 arm pxa a3f1241 2011-25-11 Prakash Kumar mpq101 powerpc mpc85xx - 2011-10-23 Alex Dubov ixdpg425 arm ixp 0ca8eb7 2011-09-22 Stefan Roese ixdp425 arm ixp 0ca8eb7 2011-09-22 Kyle Harris diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h deleted file mode 100644 index 70427da..0000000 --- a/include/configs/cerf250.h +++ /dev/null @@ -1,229 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the CERF250 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ -#define CONFIG_CERF250 1 /* on Cerf PXA Board */ -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_BAUDRATE 38400 -#define CONFIG_SYS_TEXT_BASE 0x0 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE 0x04000300 -#define CONFIG_SMC_USE_32_BIT - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 /* we use FFUART on CERF PXA */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ETHADDR 00:D0:CA:F1:3C:D2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.0.5 -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_BOOTCOMMAND "bootm 0xC0000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400" -#define CONFIG_CMDLINE_TAG - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "uboot$ " /* Monitor Command Prompt */ -#else -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) - -/* - * GPIO settings - */ - - -#define CONFIG_SYS_GPSR0_VAL 0x00408030 -#define CONFIG_SYS_GPSR1_VAL 0x00BFA882 -#define CONFIG_SYS_GPSR2_VAL 0x0001C000 -#define CONFIG_SYS_GPCR0_VAL 0xC0031100 -#define CONFIG_SYS_GPCR1_VAL 0xFC400300 -#define CONFIG_SYS_GPCR2_VAL 0x00003FFF -#define CONFIG_SYS_GPDR0_VAL 0xC0439330 -#define CONFIG_SYS_GPDR1_VAL 0xFCFFAB82 -#define CONFIG_SYS_GPDR2_VAL 0x0001FFFF -#define CONFIG_SYS_GAFR0_L_VAL 0x80000000 -#define CONFIG_SYS_GAFR0_U_VAL 0xA5000010 -#define CONFIG_SYS_GAFR1_L_VAL 0x60008018 -#define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA -#define CONFIG_SYS_GAFR2_L_VAL 0xAAA0000A -#define CONFIG_SYS_GAFR2_U_VAL 0x00000002 - -#define CONFIG_SYS_PSSR_VAL 0x20 - -#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 -#define CONFIG_SYS_CKEN 0x0 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x12447FF0 -#define CONFIG_SYS_MSC1_VAL 0x12BC5554 -#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1 -#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9 -#define CONFIG_SYS_MDREFR_VAL 0x03CDC017 -#define CONFIG_SYS_MDMRS_VAL 0x00000000 -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00010504 -#define CONFIG_SYS_MCMEM1_VAL 0x00010504 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00010504 -#define CONFIG_SYS_MCIO0_VAL 0x00004715 -#define CONFIG_SYS_MCIO1_VAL 0x00004715 - -#define _LED 0x08000010 /*check this */ -#define LED_BLANK 0x08000040 -#define LED_GPIO 0x10 - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* 256 KiB */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ - - -#endif /* __CONFIG_H */ -- cgit v0.10.2 From 00c4acaa97b3446eb771ce5539f4a188b25618ff Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 21 Nov 2011 23:32:36 +0100 Subject: PXA: Drop CRADLE board The board is unmaintained and maintainer doesn't respond. Signed-off-by: Marek Vasut Cc: Simon Glass Cc: Anatolij Gustschin diff --git a/MAINTAINERS b/MAINTAINERS index 7a5407c..7d6c97e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -905,7 +905,6 @@ Sughosh Ganu Unknown / orphaned boards: Board CPU Last known maintainer / Comment ......................................................................... - cradle xscale/pxa Kyle Harris / dead address lubbock xscale/pxa Kyle Harris / dead address imx31_phycore_eet i.MX31 Guennadi Liakhovetski / resigned diff --git a/board/cradle/Makefile b/board/cradle/Makefile deleted file mode 100644 index bdc91d8..0000000 --- a/board/cradle/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := cradle.o flash.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c deleted file mode 100644 index 2bbf2d5..0000000 --- a/board/cradle/cradle.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - - -/* local prototypes */ -void set_led (int led, int color); -void error_code_halt (int code); -int init_sio (int led, unsigned long base); -inline void cradle_outb (unsigned short val, unsigned long base, - unsigned long reg); -inline unsigned char cradle_inb (unsigned long base, unsigned long reg); -inline void sleep (int i); - -inline void -/**********************************************************/ -sleep (int i) -/**********************************************************/ -{ - while (i--) { - udelay (1000000); - } -} - -void -/**********************************************************/ -error_code_halt (int code) -/**********************************************************/ -{ - while (1) { - led_code (code, RED); - sleep (1); - led_code (0, OFF); - sleep (1); - } -} - -void -/**********************************************************/ -led_code (int code, int color) -/**********************************************************/ -{ - int i; - - code &= 0xf; /* only 4 leds */ - - for (i = 0; i < 4; i++) { - if (code & (1 << i)) { - set_led (i, color); - } else { - set_led (i, OFF); - } - } -} - -void -/**********************************************************/ -set_led (int led, int color) -/**********************************************************/ -{ - int shift = led * 2; - unsigned long mask = 0x3 << shift; - - writel(mask, GPCR2); /* clear bits */ - writel((color << shift), GPSR2); /* set bits */ - udelay (5000); -} - -inline void -/**********************************************************/ -cradle_outb (unsigned short val, unsigned long base, unsigned long reg) -/**********************************************************/ -{ - *(volatile unsigned short *) (base + (reg * 2)) = val; -} - -inline unsigned char -/**********************************************************/ -cradle_inb (unsigned long base, unsigned long reg) -/**********************************************************/ -{ - unsigned short val; - - val = *(volatile unsigned short *) (base + (reg * 2)); - return (val & 0xff); -} - -int -/**********************************************************/ -init_sio (int led, unsigned long base) -/**********************************************************/ -{ - unsigned char val; - - set_led (led, YELLOW); - val = cradle_inb (base, CRADLE_SIO_INDEX); - val = cradle_inb (base, CRADLE_SIO_INDEX); - if (val != 0) { - set_led (led, RED); - return -1; - } - - /* map SCC2 to COM1 */ - cradle_outb (0x01, base, CRADLE_SIO_INDEX); - cradle_outb (0x00, base, CRADLE_SIO_DATA); - - /* enable SCC2 extended regs */ - cradle_outb (0x40, base, CRADLE_SIO_INDEX); - cradle_outb (0xa0, base, CRADLE_SIO_DATA); - - /* enable SCC2 clock multiplier */ - cradle_outb (0x51, base, CRADLE_SIO_INDEX); - cradle_outb (0x04, base, CRADLE_SIO_DATA); - - /* enable SCC2 */ - cradle_outb (0x00, base, CRADLE_SIO_INDEX); - cradle_outb (0x04, base, CRADLE_SIO_DATA); - - /* map SCC2 DMA to channel 0 */ - cradle_outb (0x4f, base, CRADLE_SIO_INDEX); - cradle_outb (0x09, base, CRADLE_SIO_DATA); - - /* read ID from SIO to check operation */ - cradle_outb (0xe4, base, 0x3f8 + 0x3); - val = cradle_inb (base, 0x3f8 + 0x0); - if ((val & 0xf0) != 0x20) { - set_led (led, RED); - /* disable SCC2 */ - cradle_outb (0, base, CRADLE_SIO_INDEX); - cradle_outb (0, base, CRADLE_SIO_DATA); - return -1; - } - /* set back to bank 0 */ - cradle_outb (0, base, 0x3f8 + 0x3); - set_led (led, GREEN); - return 0; -} - -/* - * Miscelaneous platform dependent initialisations - */ - -int -/**********************************************************/ -board_late_init (void) -/**********************************************************/ -{ - return (0); -} - -int -/**********************************************************/ -board_init (void) -/**********************************************************/ -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - led_code (0xf, YELLOW); - - /* arch number of HHP Cradle */ - gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* Init SIOs to enable SCC2 */ - udelay (100000); /* delay makes it look neat */ - init_sio (0, CRADLE_SIO1_PHYS); - udelay (100000); - init_sio (1, CRADLE_SIO2_PHYS); - udelay (100000); - init_sio (2, CRADLE_SIO3_PHYS); - udelay (100000); - set_led (3, GREEN); - - return 1; -} - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/cradle/flash.c b/board/cradle/flash.c deleted file mode 100644 index 1601782..0000000 --- a/board/cradle/flash.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#define FLASH_BANK_SIZE 0x400000 -#define MAIN_SECT_SIZE 0x20000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F128J3 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - switch (i) { - case 0: - flashbase = PHYS_FLASH_1; - break; - case 1: - flashbase = PHYS_FLASH_2; - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = - flashbase + j * MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i, j; - - for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) { - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F320J3A & FLASH_TYPEMASK): - printf ("28F320J3A (32Mbit)\n"); - break; - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): - printf ("28F128J3 (128Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - info++; - } - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - ulong start; - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (INTEL_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - *addr = 0x20; /* erase setup */ - *addr = 0xD0; /* erase confirm */ - - while ((*addr & 0x80) != 0x80) { - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = 0xB0; /* suspend erase */ - *addr = 0xFF; /* reset to read mode */ - rc = ERR_TIMOUT; - goto outahere; - } - } - - /* clear status register command */ - *addr = 0x50; - /* reset to read mode */ - *addr = 0xFF; - } - printf ("ok.\n"); - } - if (ctrlc ()) - printf ("User Interrupt!\n"); - -outahere: - - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (flag) - enable_interrupts (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest, val; - int rc = ERR_OK; - int flag; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* clear status register command */ - *addr = 0x50; - - /* program set-up command */ - *addr = 0x40; - - /* latch address/data */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((val = *addr) & 0x80) != 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - rc = ERR_TIMOUT; - /* suspend program command */ - *addr = 0xB0; - goto outahere; - } - } - - if (val & 0x1A) { /* check for error */ - printf ("\nFlash write error %02x at address %08lx\n", - (int) val, (unsigned long) dest); - if (val & (1 << 3)) { - printf ("Voltage range error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - if (val & (1 << 1)) { - printf ("Device protect error.\n"); - rc = ERR_PROTECTED; - goto outahere; - } - if (val & (1 << 4)) { - printf ("Programming error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - rc = ERR_PROG_ERROR; - goto outahere; - } - -outahere: - /* read array command */ - *addr = 0xFF; - - if (flag) - enable_interrupts (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_word (info, wp, data); -} diff --git a/boards.cfg b/boards.cfg index 82c705d..f649ae9 100644 --- a/boards.cfg +++ b/boards.cfg @@ -217,7 +217,6 @@ actux4 arm ixp dvlhost arm ixp balloon3 arm pxa colibri_pxa270 arm pxa -cradle arm pxa lubbock arm pxa palmld arm pxa palmtc arm pxa diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 732d92d..3e7f113 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +cradle arm pxa 4e24f8a 2011-25-11 Kyle Harris cerf250 arm pxa a3f1241 2011-25-11 Prakash Kumar mpq101 powerpc mpc85xx - 2011-10-23 Alex Dubov ixdpg425 arm ixp 0ca8eb7 2011-09-22 Stefan Roese diff --git a/include/configs/cradle.h b/include/configs/cradle.h deleted file mode 100644 index 25be616..0000000 --- a/include/configs/cradle.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ -#define CONFIG_HHP_CRADLE 1 /* on an Cradle Board */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF -#define CONFIG_SYS_TEXT_BASE 0x0 -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE 0x10000300 -#define CONFIG_SMC91111_EXT_PHY -#define CONFIG_SMC_USE_32_BIT - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200" -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.0.21 -#define CONFIG_SERVERIP 192.168.0.250 -#define CONFIG_BOOTCOMMAND "bootm 40000" -#define CONFIG_CMDLINE_TAG - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ - - /* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x00020000 /* absolute address for now */ -#define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */ - -/****************************************************************************** - * - * CPU specific defines - * - ******************************************************************************/ - -/* - * GPIO settings - * - * GPIO pin assignments - * GPIO Name Dir Out AF - * 0 NC - * 1 NC - * 2 SIRQ1 I - * 3 SIRQ2 I - * 4 SIRQ3 I - * 5 DMAACK1 O 0 - * 6 DMAACK2 O 0 - * 7 DMAACK3 O 0 - * 8 TC1 O 0 - * 9 TC2 O 0 - * 10 TC3 O 0 - * 11 nDMAEN O 1 - * 12 AENCTRL O 0 - * 13 PLDTC O 0 - * 14 ETHIRQ I - * 15 NC - * 16 NC - * 17 NC - * 18 RDY I - * 19 DMASIO I - * 20 ETHIRQ NC - * 21 NC - * 22 PGMEN O 1 FIXME for debug only enable flash - * 23 NC - * 24 NC - * 25 NC - * 26 NC - * 27 NC - * 28 NC - * 29 NC - * 30 NC - * 31 NC - * 32 NC - * 33 NC - * 34 FFRXD I 01 - * 35 FFCTS I 01 - * 36 FFDCD I 01 - * 37 FFDSR I 01 - * 38 FFRI I 01 - * 39 FFTXD O 1 10 - * 40 FFDTR O 0 10 - * 41 FFRTS O 0 10 - * 42 RS232FOFF O 0 00 - * 43 NC - * 44 NC - * 45 IRSL0 O 0 - * 46 IRRX0 I 01 - * 47 IRTX0 O 0 10 - * 48 NC - * 49 nIOWE O 0 - * 50 NC - * 51 NC - * 52 NC - * 53 NC - * 54 NC - * 55 NC - * 56 NC - * 57 NC - * 58 DKDIRQ I - * 59 NC - * 60 NC - * 61 NC - * 62 NC - * 63 NC - * 64 COMLED O 0 - * 65 COMLED O 0 - * 66 COMLED O 0 - * 67 COMLED O 0 - * 68 COMLED O 0 - * 69 COMLED O 0 - * 70 COMLED O 0 - * 71 COMLED O 0 - * 72 NC - * 73 NC - * 74 NC - * 75 NC - * 76 NC - * 77 NC - * 78 CSIO O 1 - * 79 NC - * 80 CSETH O 1 - * - * NOTE: All NC's are defined to be outputs - * - */ -/* Pin direction control */ -/* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */ -#define CONFIG_SYS_GPDR0_VAL 0xfff3bf02 -#define CONFIG_SYS_GPDR1_VAL 0xfbffbf83 -#define CONFIG_SYS_GPDR2_VAL 0x0001ffff -/* Set and Clear registers */ -#define CONFIG_SYS_GPSR0_VAL 0x00400800 -#define CONFIG_SYS_GPSR1_VAL 0x00000480 -#define CONFIG_SYS_GPSR2_VAL 0x00014000 -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -/* Edge detect registers (these are set by the kernel) */ -#define CONFIG_SYS_GRER0_VAL 0x00000000 -#define CONFIG_SYS_GRER1_VAL 0x00000000 -#define CONFIG_SYS_GRER2_VAL 0x00000000 -#define CONFIG_SYS_GFER0_VAL 0x00000000 -#define CONFIG_SYS_GFER1_VAL 0x00000000 -#define CONFIG_SYS_GFER2_VAL 0x00000000 -/* Alternate function registers */ -#define CONFIG_SYS_GAFR0_L_VAL 0x00000000 -#define CONFIG_SYS_GAFR0_U_VAL 0x00000010 -#define CONFIG_SYS_GAFR1_L_VAL 0x900a9550 -#define CONFIG_SYS_GAFR1_U_VAL 0x00000008 -#define CONFIG_SYS_GAFR2_L_VAL 0x20000000 -#define CONFIG_SYS_GAFR2_U_VAL 0x00000002 - -/* - * Clocks, power control and interrupts - */ -#define CONFIG_SYS_PSSR_VAL 0x00000020 -#define CONFIG_SYS_CCCR 0x00000141 /* 100 MHz memory, 200 MHz CPU */ -#define CONFIG_SYS_CKEN 0x00000060 /* FFUART and STUART enabled */ -#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ - -/* FIXME - * - * RTC settings - * Watchdog - * - */ - -/* - * Memory settings - * - * FIXME Can ethernet be burst read and/or write?? This is set for lubbock - * Verify timings on all - */ -#define CONFIG_SYS_MSC0_VAL 0x000023FA /* flash bank (cs0) */ -/*#define CONFIG_SYS_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */ -#define CONFIG_SYS_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */ -#define CONFIG_SYS_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */ -#ifdef REDBOOT_WAY -#define CONFIG_SYS_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ -#define CONFIG_SYS_MDMRS_VAL 0x00000000 -#define CONFIG_SYS_MDREFR_VAL 0x00018018 -#else -#define CONFIG_SYS_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ -#define CONFIG_SYS_MDMRS_VAL 0x00000000 -#define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */ -#endif -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00010504 -#define CONFIG_SYS_MCMEM1_VAL 0x00010504 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00010504 -#define CONFIG_SYS_MCIO0_VAL 0x00004715 -#define CONFIG_SYS_MCIO1_VAL 0x00004715 - -/* Board specific defines */ - -/* LED defines */ -#define YELLOW 0x03 -#define RED 0x02 -#define GREEN 0x01 -#define OFF 0x00 -#define LED_IRDA0 0 -#define LED_IRDA1 2 -#define LED_IRDA2 4 -#define LED_IRDA3 6 - -/* SuperIO defines */ -#define CRADLE_SIO_INDEX 0x2e -#define CRADLE_SIO_DATA 0x2f - -/* IO defines */ -#define CRADLE_CPLD_PHYS 0x08000000 -#define CRADLE_SIO1_PHYS 0x08100000 -#define CRADLE_SIO2_PHYS 0x08200000 -#define CRADLE_SIO3_PHYS 0x08300000 -#define CRADLE_ETH_PHYS 0x10000000 - -#ifndef __ASSEMBLY__ - -/* global prototypes */ -void led_code(int code, int color); - -#endif - -#endif /* __CONFIG_H */ -- cgit v0.10.2 From d299173139f030386f9d55117775cca050936706 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 21 Nov 2011 23:31:25 +0100 Subject: PXA: Drop PLEB2 board The board is unmaintained and maintainer doesn't respond. Signed-off-by: Marek Vasut Cc: Simon Glass Cc: Anatolij Gustschin diff --git a/board/pleb2/Makefile b/board/pleb2/Makefile deleted file mode 100644 index bc29610..0000000 --- a/board/pleb2/Makefile +++ /dev/null @@ -1,44 +0,0 @@ - -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := pleb2.o flash.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/pleb2/flash.c b/board/pleb2/flash.c deleted file mode 100644 index 2406c5f..0000000 --- a/board/pleb2/flash.c +++ /dev/null @@ -1,814 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -/* environment.h defines the various CONFIG_ENV_... values in terms - * of whichever ones are given in the configuration file. - */ -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPWV * addr, flash_info_t * info); -static void flash_reset (flash_info_t * info); -static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data); -static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -#ifdef CONFIG_SYS_FLASH_PROTECTION -static void flash_sync_real_protect (flash_info_t * info); -#endif - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size_b; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b; - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n", - size_b); - } - - /* Do this again (was done already in flast_get_size), just - * in case we move it when remap the FLASH. - */ - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#ifdef CONFIG_SYS_FLASH_PROTECTION - /* read the hardware protection status (if any) into the - * protection array in flash_info. - */ - flash_sync_real_protect (&flash_info[0]); -#endif - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_ADDR - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - return (size_b); -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset (flash_info_t * info) -{ - FPWV *base = (FPWV *) (info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW) 0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW) 0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof (FPW) / 2); - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set up sector start address table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sect_size); - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set up sector start address table (top boot sector type) */ - for (i = 0; i < info->sector_count - 3; i++) - info->start[i] = base + (i * sect_size); - i = info->sector_count - 1; - info->start[i--] = - base + (info->size - 0x00004000) * (sizeof (FPW) / 2); - info->start[i--] = - base + (info->size - 0x00006000) * (sizeof (FPW) / 2); - info->start[i--] = - base + (info->size - 0x00008000) * (sizeof (FPW) / 2); - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t * info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_BM: - printf ("BRIGHT MICRO "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("STM "); - break; - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - fmt = "29LV800B%s (8 Mbit, %s)\n"; - break; - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV * addr, flash_info_t * info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ - addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ - addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[0] & 0xff) { - - case (uchar) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) - switch (addr[1]) { - - case (FPW) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MiB */ - - case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets ((ulong) addr, info); - - /* Put FLASH back in read mode */ - flash_reset (info); - - return (info->size); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ - -static void flash_sync_real_protect (flash_info_t * info) -{ - FPWV *addr = (FPWV *) (info->start[0]); - FPWV *sect; - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - /* check for protected sectors */ - *addr = (FPW) 0x00900090; - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but mixed protected and unprotected devices - * within a sector should never happen. - */ - sect = (FPWV *) (info->start[i]); - info->protect[i] = - (sect[2] & (FPW) (0x00010001)) ? 1 : 0; - } - - /* Put FLASH back in read mode */ - flash_reset (info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - break; - } -} -#endif - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - case FLASH_AM800T: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - start = get_timer(0); - last = 0; - - addr = (FPWV *) (info->start[sect]); - if (intel) { - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - } else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *) (info->start[0]); - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00800080; /* erase mode */ - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - *addr = (FPW) 0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = - get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - } - - flash_reset (info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((now - last) > 1 * CONFIG_SYS_HZ) { /* every second */ - putc ('.'); - last = now; - } - } - - flash_reset (info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof (data), left -= sizeof (data) - bytes) { - - bytes = addr & (sizeof (data) - 1); - addr &= ~(sizeof (data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ -#ifdef CONFIG_SYS_LITTLE_ENDIAN - for (i = 0; i < sizeof (data); i++) { - data >>= 8; - if (i < bytes || i - bytes >= left) - data += (*((uchar *) addr + i)) << 24; - else - data += (*src++) << 24; - } -#else - for (i = 0; i < sizeof (data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left) - data += *((uchar *) addr + i); - else - data += *src++; - } -#endif - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd (info, (FPWV *) addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel (info, (FPWV *) addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) -{ - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *) (info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer(0); - - /* data polling for D7 */ - while (res == 0 - && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) -{ - int flag; - int res = 0; /* result, assume success */ - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - *dest = (FPW) 0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer(0); - - while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW) 0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - - return (res); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - flash_reset (info); /* make sure in read mode */ - *addr = (FPW) 0x00600060L; /* lock command setup */ - if (prot) - *addr = (FPW) 0x00010001L; /* lock sector */ - else - *addr = (FPW) 0x00D000D0L; /* unlock sector */ - flash_reset (info); /* reset to read mode */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) 0x00900090; - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) 0x00010001; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) 0x00010001) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect (info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif diff --git a/board/pleb2/pleb2.c b/board/pleb2/pleb2.c deleted file mode 100644 index 5a16cc7..0000000 --- a/board/pleb2/pleb2.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of Lubbock-Board */ - gd->bd->bi_arch_number = MACH_TYPE_PLEB2; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} diff --git a/boards.cfg b/boards.cfg index f649ae9..35ef5f3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -220,7 +220,6 @@ colibri_pxa270 arm pxa lubbock arm pxa palmld arm pxa palmtc arm pxa -pleb2 arm pxa polaris arm pxa trizepsiv - - trizepsiv:POLARIS pxa255_idp arm pxa trizepsiv arm pxa diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 3e7f113..68bbfee 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +pleb2 arm pxa b185a1c 2011-25-11 cradle arm pxa 4e24f8a 2011-25-11 Kyle Harris cerf250 arm pxa a3f1241 2011-25-11 Prakash Kumar mpq101 powerpc mpc85xx - 2011-10-23 Alex Dubov diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h deleted file mode 100644 index 2aeb7fb..0000000 --- a/include/configs/pleb2.h +++ /dev/null @@ -1,266 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuration settings for the PLEB 2 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA255 CPU */ -#define CONFIG_PLEB2 1 /* on an PLEB2 Board */ -#undef CONFIG_LCD -#undef CONFIG_MMC -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_SYS_TEXT_BASE 0x0 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ - -/* None - PLEB 2 doesn't have any of this. - #define CONFIG_LAN91C96 - #define CONFIG_LAN91C96_BASE 0x0C000000 - */ - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 /* we use FFUART on PLEB 2 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.0.21 -#define CONFIG_SERVERIP 192.168.0.250 -#define CONFIG_BOOTCOMMAND "bootm 40000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 prompt_ramdisk=0 load_ramdisk=1 console=ttyS0,115200" - -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ -#else -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ - - /* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#ifdef CONFIG_MMC -#define CONFIG_PXA_MMC -#define CONFIG_CMD_MMC -#endif - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x00800000 /* 4 MB */ - -/* Not entirely sure about this - DS/CHC */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */ - -#define CONFIG_SYS_DRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x00000000 /* Don't set anything */ -#define CONFIG_SYS_GPSR1_VAL 0x00000080 -#define CONFIG_SYS_GPSR2_VAL 0x00000000 - -#define CONFIG_SYS_GPCR0_VAL 0x00000000 /* Don't clear anything */ -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 - -#define CONFIG_SYS_GPDR0_VAL 0x00000000 -#define CONFIG_SYS_GPDR1_VAL 0x000007C3 -#define CONFIG_SYS_GPDR2_VAL 0x00000000 - -/* Edge detect registers (these are set by the kernel) */ -#define CONFIG_SYS_GRER0_VAL 0x00000000 -#define CONFIG_SYS_GRER1_VAL 0x00000000 -#define CONFIG_SYS_GRER2_VAL 0x00000000 -#define CONFIG_SYS_GFER0_VAL 0x00000000 -#define CONFIG_SYS_GFER1_VAL 0x00000000 -#define CONFIG_SYS_GFER2_VAL 0x00000000 - -#define CONFIG_SYS_GAFR0_L_VAL 0x00000000 -#define CONFIG_SYS_GAFR0_U_VAL 0x00000000 -#define CONFIG_SYS_GAFR1_L_VAL 0x00008010 /* Use FF UART Send and Receive */ -#define CONFIG_SYS_GAFR1_U_VAL 0x00000000 -#define CONFIG_SYS_GAFR2_L_VAL 0x00000000 -#define CONFIG_SYS_GAFR2_U_VAL 0x00000000 - -#define CONFIG_SYS_PSSR_VAL 0x20 -#define CONFIG_SYS_CCCR 0x00000141 /* 100 MHz memory, 200 MHz CPU */ -#define CONFIG_SYS_CKEN 0x00000060 /* FFUART and STUART enabled */ -#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x00007FF0 /* Not properly calculated - FIXME (DS) */ -#define CONFIG_SYS_MSC1_VAL 0x00000000 -#define CONFIG_SYS_MSC2_VAL 0x00000000 - -#define CONFIG_SYS_MDCNFG_VAL 0x00000aC9 /* Memory timings for the SDRAM. - tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */ - -#define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual */ - /* bits set in lowlevel_init.S */ -#define CONFIG_SYS_MDMRS_VAL 0x00000000 - -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 /* Hangover from Lubbock. - Needs calculating. (DS/CHC) */ -#define CONFIG_SYS_MCMEM0_VAL 0x00010504 -#define CONFIG_SYS_MCMEM1_VAL 0x00010504 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00010504 -#define CONFIG_SYS_MCIO0_VAL 0x00004715 -#define CONFIG_SYS_MCIO1_VAL 0x00004715 - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -/* FIXME */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* Flash protection */ -#define CONFIG_SYS_FLASH_PROTECTION 1 - -/* FIXME */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3C000) /* Addr of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 - -/* Option added to get around byte ordering issues in the flash driver */ -#define CONFIG_SYS_LITTLE_ENDIAN 1 - -#endif /* __CONFIG_H */ -- cgit v0.10.2 From c477d72c04916b10efb32deb112905d2680ad4a2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 21 Nov 2011 23:40:23 +0100 Subject: PXA: Drop XM250 board The board is unmaintained and maintainer doesn't respond. Signed-off-by: Marek Vasut Cc: Simon Glass Cc: Anatolij Gustschin diff --git a/board/xm250/Makefile b/board/xm250/Makefile deleted file mode 100644 index 6a0cca0..0000000 --- a/board/xm250/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := xm250.o flash.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/xm250/flash.c b/board/xm250/flash.c deleted file mode 100644 index e825aba..0000000 --- a/board/xm250/flash.c +++ /dev/null @@ -1,535 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -/* Intel-compatible flash ID */ -#define INTEL_COMPAT 0x00890089 -#define INTEL_ALT 0x00B000B0 - -/* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x00100010 -#define INTEL_ERASE 0x00200020 -#define INTEL_CLEAR 0x00500050 -#define INTEL_LOCKBIT 0x00600060 -#define INTEL_PROTECT 0x00010001 -#define INTEL_STATUS 0x00700070 -#define INTEL_READID 0x00900090 -#define INTEL_CONFIRM 0x00D000D0 -#define INTEL_RESET 0xFFFFFFFF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x00800080 -#define INTEL_OK 0x00800080 - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured to many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - - case FLASH_28F640J3A: - printf ("28F640J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 32 MB */ - - case (FPW) INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} - -/*----------------------------------------------------------------------- - * Set/Clear sector's lock bit, returns: - * 0 - OK - * 1 - Error (timeout, voltage problems, etc.) - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int i; - int rc = 0; - vu_long *addr = (vu_long *)(info->start[sector]); - int flag = disable_interrupts(); - ulong start; - - *addr = INTEL_CLEAR; /* Clear status register */ - if (prot) { /* Set sector lock bit */ - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - } - else { /* Clear sector lock bit */ - *addr = INTEL_LOCKBIT; /* All sectors lock bits */ - *addr = INTEL_CONFIRM; /* clear */ - } - - start = get_timer(0); - - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - - if (*addr != INTEL_OK) { - printf("Flash lock bit operation failed at %08X, CSR=%08X\n", - (uint)addr, (uint)*addr); - rc = 1; - } - - if (!rc) - info->protect[sector] = prot; - - /* - * Clear lock bit command clears all sectors lock bits, so - * we have to restore lock bits of protected sectors. - */ - if (!prot) - { - for (i = 0; i < info->sector_count; i++) - { - if (info->protect[i]) - { - start = get_timer(0); - addr = (vu_long *)(info->start[i]); - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) - { - if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) - { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - } - } - } - - if (flag) - enable_interrupts(); - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c deleted file mode 100644 index 3188cf2..0000000 --- a/board/xm250/xm250.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -/* local prototypes */ - -inline void sleep (int i); - -inline void -/**********************************************************/ -sleep (int i) -/**********************************************************/ -{ - while (i--) { - udelay (1000000); - } -} - -/* - * Miscelaneous platform dependent initialisations - */ - -int -/**********************************************************/ -board_init (void) -/**********************************************************/ -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of MicroSys XM250 */ - gd->bd->bi_arch_number = MACH_TYPE_XM250; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/boards.cfg b/boards.cfg index 35ef5f3..3fe96ad 100644 --- a/boards.cfg +++ b/boards.cfg @@ -227,7 +227,6 @@ vpac270_nor_128 arm pxa vpac270 - vpac270_nor_256 arm pxa vpac270 - - vpac270:NOR,RAM_256M vpac270_ond_256 arm pxa vpac270 - - vpac270:ONENAND,RAM_256M xaeniax arm pxa -xm250 arm pxa zipitz2 arm pxa jornada arm sa1100 atngw100 avr32 at32ap - atmel at32ap700x diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 68bbfee..07f0024 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +xm250 arm pxa c746cdd 2011-25-11 pleb2 arm pxa b185a1c 2011-25-11 cradle arm pxa 4e24f8a 2011-25-11 Kyle Harris cerf250 arm pxa a3f1241 2011-25-11 Prakash Kumar diff --git a/include/configs/xm250.h b/include/configs/xm250.h deleted file mode 100644 index a35bce3..0000000 --- a/include/configs/xm250.h +++ /dev/null @@ -1,369 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ -#define CONFIG_XM250 1 /* on a MicroSys XM250 Board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_SYS_TEXT_BASE 0x0 - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* - * Size of malloc() pool; this lives below the uppermost 128 KiB which are - * used for the RAM copy of the uboot code - * - */ -#define CONFIG_SYS_MALLOC_LEN (256*1024) - -/* - * Hardware drivers - */ -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE 0x04000300 -#undef CONFIG_SMC91111_EXT_PHY -#define CONFIG_SMC_USE_32_BIT -#undef CONFIG_SHOW_ACTIVITY -#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ - -/* - * I2C bus - */ -#define CONFIG_I2C_MV 1 -#define CONFIG_MV_I2C_REG 0x40301680 -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0xfe - -#define CONFIG_RTC_PCF8563 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* A0 = 0 (hardwired) */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 4 bits = 16 octets */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* length of address */ -#define CONFIG_SYS_EEPROM_SIZE 2048 /* size in bytes */ -#undef CONFIG_SYS_I2C_INIT_BOARD /* board has no own init */ - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 /* we use FFUART */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C - - -#define CONFIG_BOOTDELAY 3 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */ - - /* valid baudrates */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Definitions related to passing arguments to kernel. - */ -#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ -#define CONFIG_INITRD_TAG 1 /* do not send initrd params */ - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ -#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ -#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Set Lock Bit */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Clear Lock Bits */ -#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ -#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */ - -/****************************************************************************** - * - * CPU specific defines - * - ******************************************************************************/ - -/* - * GPIO settings - * - * GPIO pin assignments - * GPIO Name Dir Out AF - * 0 NC - * 1 NC - * 2 SIRQ1 I - * 3 SIRQ2 I - * 4 SIRQ3 I - * 5 DMAACK1 O 0 - * 6 DMAACK2 O 0 - * 7 DMAACK3 O 0 - * 8 TC1 O 0 - * 9 TC2 O 0 - * 10 TC3 O 0 - * 11 nDMAEN O 1 - * 12 AENCTRL O 0 - * 13 PLDTC O 0 - * 14 ETHIRQ I - * 15 NC - * 16 NC - * 17 NC - * 18 RDY I - * 19 DMASIO I - * 20 ETHIRQ NC - * 21 NC - * 22 PGMEN O 1 FIXME for debug only enable flash - * 23 NC - * 24 NC - * 25 NC - * 26 NC - * 27 NC - * 28 NC - * 29 NC - * 30 NC - * 31 NC - * 32 NC - * 33 NC - * 34 FFRXD I 01 - * 35 FFCTS I 01 - * 36 FFDCD I 01 - * 37 FFDSR I 01 - * 38 FFRI I 01 - * 39 FFTXD O 1 10 - * 40 FFDTR O 0 10 - * 41 FFRTS O 0 10 - * 42 RS232FOFF O 0 00 - * 43 NC - * 44 NC - * 45 IRSL0 O 0 - * 46 IRRX0 I 01 - * 47 IRTX0 O 0 10 - * 48 NC - * 49 nIOWE O 0 - * 50 NC - * 51 NC - * 52 NC - * 53 NC - * 54 NC - * 55 NC - * 56 NC - * 57 NC - * 58 DKDIRQ I - * 59 NC - * 60 NC - * 61 NC - * 62 NC - * 63 NC - * 64 COMLED O 0 - * 65 COMLED O 0 - * 66 COMLED O 0 - * 67 COMLED O 0 - * 68 COMLED O 0 - * 69 COMLED O 0 - * 70 COMLED O 0 - * 71 COMLED O 0 - * 72 NC - * 73 NC - * 74 NC - * 75 NC - * 76 NC - * 77 NC - * 78 CSIO O 1 - * 79 NC - * 80 CSETH O 1 - * - * NOTE: All NC's are defined to be outputs - * - */ -/* Pin direction control */ -#define CONFIG_SYS_GPDR0_VAL 0xd3808000 -#define CONFIG_SYS_GPDR1_VAL 0xfcffab83 -#define CONFIG_SYS_GPDR2_VAL 0x0001ffff -/* Set and Clear registers */ -#define CONFIG_SYS_GPSR0_VAL 0x00008000 -#define CONFIG_SYS_GPSR1_VAL 0x00ff0002 -#define CONFIG_SYS_GPSR2_VAL 0x0001c000 -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -/* Edge detect registers (these are set by the kernel) */ -#define CONFIG_SYS_GRER0_VAL 0x00002180 -#define CONFIG_SYS_GRER1_VAL 0x00000000 -#define CONFIG_SYS_GRER2_VAL 0x00000000 -#define CONFIG_SYS_GFER0_VAL 0x000043e0 -#define CONFIG_SYS_GFER1_VAL 0x00000000 -#define CONFIG_SYS_GFER2_VAL 0x00000000 -/* Alternate function registers */ -#define CONFIG_SYS_GAFR0_L_VAL 0x80000004 -#define CONFIG_SYS_GAFR0_U_VAL 0x595a8010 -#define CONFIG_SYS_GAFR1_L_VAL 0x699a9559 -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aaaa -#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x00000002 - -/* - * Clocks, power control and interrupts - */ -#define CONFIG_SYS_PSSR_VAL 0x00000030 -#define CONFIG_SYS_CCCR 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */ -#define CONFIG_SYS_CKEN 0x000141ec /* FFUART and STUART enabled */ -#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ - -/* FIXME - * - * RTC settings - * Watchdog - * - */ - -/* - * Memory settings - * - */ -#define CONFIG_SYS_MSC0_VAL 0x122423f0 /* FLASH / LAN (cs0)/(cS1) */ -#define CONFIG_SYS_MSC1_VAL 0x35f4aa4c /* USB / ST3+ST5 (cs2)/(cS3) */ -#define CONFIG_SYS_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */ -#define CONFIG_SYS_MDCNFG_VAL 0x000009c9 -#define CONFIG_SYS_MDMRS_VAL 0x00220022 -#define CONFIG_SYS_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */ -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00010504 -#define CONFIG_SYS_MCMEM1_VAL 0x00010504 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00010504 -#define CONFIG_SYS_MCIO0_VAL 0x00004715 -#define CONFIG_SYS_MCIO1_VAL 0x00004715 - -/* Board specific defines */ - -#ifndef __ASSEMBLY__ - -/* global prototypes */ -void led_code(int code, int color); - -#endif - -#endif /* __CONFIG_H */ -- cgit v0.10.2 From 20f7b1b745f1dff6e7a02b2160c688e5276b52e4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 31 Oct 2011 14:12:39 +0100 Subject: PXA: Rework start.S to be closer to other ARMs The start.S on PXA was very obscure. This reworks it back to be close to arm1136 start.S and others. Signed-off-by: Marek Vasut Cc: Albert ARIBAUD V2: Don't compile in relocation support if building SPL diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c index df351c7..c48b2ef 100644 --- a/arch/arm/cpu/pxa/cpu.c +++ b/arch/arm/cpu/pxa/cpu.c @@ -328,3 +328,19 @@ void i2c_clk_enable(void) writel(readl(CKEN) | CKEN14_I2C, CKEN); #endif } + +void reset_cpu(ulong ignored) __attribute__((noreturn)); + +void reset_cpu(ulong ignored) +{ + uint32_t tmp; + + setbits_le32(OWER, OWER_WME); + + tmp = readl(OSCR); + tmp += 0x1000; + writel(tmp, OSMR3); + + for (;;) + ; +} diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 6191a73..88a4cc2 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -1,14 +1,20 @@ /* - * armboot - Startup Code for XScale + * armboot - Startup Code for XScale CPU-core * * Copyright (C) 1998 Dan Malek * Copyright (C) 1999 Magnus Damm * Copyright (C) 2000 Wolfgang Denk * Copyright (C) 2001 Alex Zuepke + * Copyright (C) 2001 Marius Groger + * Copyright (C) 2002 Alex Zupke + * Copyright (C) 2002 Gary Jennejohn * Copyright (C) 2002 Kyle Harris - * Copyright (C) 2003 Robert Schwebel * Copyright (C) 2003 Kai-Uwe Bloem - * Copyright (c) 2010 Marek Vasut + * Copyright (C) 2003 Kshitij + * Copyright (C) 2003 Richard Woodruff + * Copyright (C) 2003 Robert Schwebel + * Copyright (C) 2004 Texas Instruments + * Copyright (C) 2010 Marek Vasut * * See file CREDITS for list of people who contributed to this * project. @@ -32,15 +38,6 @@ #include #include #include -#include - -/* takes care the CP15 update has taken place */ -.macro CPWAIT reg -mrc p15,0,\reg,c2,c0,0 -mov \reg,\reg -sub pc,pc,#4 -.endm - .globl _start _start: b reset #ifdef CONFIG_SPL_BUILD @@ -77,26 +74,38 @@ _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq +_pad: .word 0x12345678 /* now 16*4=64 */ #endif /* CONFIG_SPL_BUILD */ +.global _end_vect +_end_vect: .balignl 16,0xdeadbeef - - /* + ************************************************************************* + * * Startup Code (reset vector) * - * do important init only if we don't start from RAM! - * - relocate armboot to RAM - * - setup stack - * - jump to second stage + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* */ .globl _TEXT_BASE _TEXT_BASE: +#ifdef CONFIG_SPL_BUILD + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. + * Subtracting _start from them lets the linker put their + * relative position in the executable instead of leaving + * them null. */ .globl _bss_start_ofs _bss_start_ofs: @@ -120,9 +129,8 @@ IRQ_STACK_START: .globl FIQ_STACK_START FIQ_STACK_START: .word 0x0badc0de -#endif /* CONFIG_USE_IRQ */ +#endif -#ifndef CONFIG_SPL_BUILD /* IRQ stack memory (calculated at run-time) + 8 bytes */ .globl IRQ_STACK_START_IN IRQ_STACK_START_IN: @@ -141,95 +149,19 @@ reset: orr r0,r0,#0xd3 msr cpsr,r0 - /* - * Enable MMU to use DCache as DRAM - */ - /* Domain access -- enable for all CPs */ - ldr r0, =0x0000ffff - mcr p15, 0, r0, c3, c0, 0 - - /* Point TTBR to MMU table */ - ldr r0, =mmu_table - adr r2, _start - orr r0, r2 - mcr p15, 0, r0, c2, c0, 0 - -/* !!! Hereby, check if the code is running from SRAM !!! */ -/* If the code is running from SRAM, alias SRAM to 0x0 to simulate NOR. The code - * is linked to 0x0 too, so this makes things easier. */ - cmp r2, #0x5c000000 - - ldreq r1, [r0] - orreq r1, r2 - streq r1, [r0] - - /* Kick in MMU, ICache, DCache, BTB */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, #0x1b00 - bic r0, #0x0087 - orr r0, #0x1800 - orr r0, #0x0005 - mcr p15, 0, r0, c1, c0, 0 - CPWAIT r0 - - /* Unlock Icache, Dcache */ - mcr p15, 0, r0, c9, c1, 1 - mcr p15, 0, r0, c9, c2, 1 - - /* Flush Icache, Dcache, BTB */ - mcr p15, 0, r0, c7, c7, 0 - - /* Unlock I-TLB, D-TLB */ - mcr p15, 0, r0, c10, c4, 1 - mcr p15, 0, r0, c10, c8, 1 - - /* Flush TLB */ - mcr p15, 0, r0, c8, c7, 0 - /* Allocate 4096 bytes of Dcache as RAM */ - - /* Drain pending loads and stores */ - mcr p15, 0, r0, c7, c10, 4 - - mov r4, #0x00 - mov r5, #0x00 - mov r2, #0x01 - mcr p15, 0, r0, c9, c2, 0 - CPWAIT r0 - - /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ - mov r0, #128 - mov r1, #0xa0000000 -alloc: - mcr p15, 0, r1, c7, c2, 5 - /* Drain pending loads and stores */ - mcr p15, 0, r0, c7, c10, 4 - strd r4, [r1], #8 - strd r4, [r1], #8 - strd r4, [r1], #8 - strd r4, [r1], #8 - subs r0, #0x01 - bne alloc - /* Drain pending loads and stores */ - mcr p15, 0, r0, c7, c10, 4 - mov r2, #0x00 - mcr p15, 0, r2, c9, c2, 0 - CPWAIT r0 - - /* Jump to 0x0 ( + offset) if running from SRAM */ - adr r0, zerojmp - bic r0, #0x5c000000 - mov pc, r0 -zerojmp: +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif /* Set stackpointer in internal RAM to call board_init_f */ call_board_init_f: ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 + ldr r0, =0x00000000 bl board_init_f /*------------------------------------------------------------------------------*/ - +#ifndef CONFIG_SPL_BUILD /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -254,13 +186,11 @@ stack_setup: ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ - stmfd sp!, {r0-r12} copy_loop: - ldmia r0!, {r3-r5, r7-r11} /* copy from source address [r0] */ - stmia r1!, {r3-r5, r7-r11} /* copy to target address [r1] */ + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r1!, {r9-r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop - ldmfd sp!, {r0-r12} #ifndef CONFIG_SPL_BUILD /* @@ -275,13 +205,13 @@ copy_loop: ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ fixloop: - ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ - add r0, r9 /* r0 <- location to fix up in RAM */ + ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ + add r0, r0, r9 /* r0 <- location to fix up in RAM */ ldr r1, [r2, #4] and r7, r1, #0xff - cmp r7, #23 /* relative fixup? */ + cmp r7, #23 /* relative fixup? */ beq fixrel - cmp r7, #2 /* absolute fixup? */ + cmp r7, #2 /* absolute fixup? */ beq fixabs /* ignore unknown type of fixup */ b fixnext @@ -298,10 +228,10 @@ fixrel: add r1, r1, r9 fixnext: str r1, [r0] - add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ + add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop -#endif /* #ifndef CONFIG_SPL_BUILD */ +#endif clear_bss: #ifndef CONFIG_SPL_BUILD @@ -322,15 +252,16 @@ clbss_l:str r2, [r0] /* clear loop... */ * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ -#ifdef CONFIG_ONENAND_IPL - ldr r0, _start_oneboot_ofs +#ifdef CONFIG_ONENAND_SPL + ldr r0, _onenand_boot_ofs mov pc, r0 -_start_oneboot_ofs - : .word start_oneboot +_onenand_boot_ofs: + .word onenand_boot #else +jump_2_ram: ldr r0, _board_init_r_ofs - adr r1, _start + ldr r1, _TEXT_BASE add lr, r0, r1 add lr, lr, r9 /* setup parameters for board_init_r */ @@ -341,7 +272,7 @@ _start_oneboot_ofs _board_init_r_ofs: .word board_init_r - _start -#endif /* CONFIG_ONENAND_IPL */ +#endif _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -349,43 +280,50 @@ _rel_dyn_end_ofs: .word __rel_dyn_end - _start _dynsym_start_ofs: .word __dynsym_start - _start - -#else /* CONFIG_SPL_BUILD */ - -/****************************************************************************/ -/* */ -/* the actual reset code for OneNAND IPL */ -/* */ -/****************************************************************************/ - -#ifndef CONFIG_PXA27X -#error OneNAND IPL is not supported on PXA25x and 26x due to lack of SRAM #endif +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ + mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ -reset: - /* Set CPU to SVC32 mode */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0x13 - msr cpsr,r0 - - /* Point stack at the end of SRAM and leave 32 words for abort-stack */ - ldr sp, =0x5c03ff80 - - /* Start OneNAND IPL */ - ldr pc, =start_oneboot + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) + orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + mcr p15, 0, r0, c1, c0, 0 -#endif /* CONFIG_SPL_BUILD */ + mov pc, lr /* back to my caller */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ #ifndef CONFIG_SPL_BUILD -/****************************************************************************/ -/* */ -/* Interrupt handling */ -/* */ -/****************************************************************************/ - -/* IRQ stack frame */ - +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ +@ +@ IRQ stack frame. +@ #define S_FRAME_SIZE 72 #define S_OLD_R0 68 @@ -409,37 +347,36 @@ reset: #define S_R0 0 #define MODE_SVC 0x13 +#define I_BIT 0x80 - /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC + sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ - add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ + ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack + ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack add r5, sp, #S_SP mov r1, lr - stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ - mov r0, sp + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 (param register) .endm - - /* use irq_save_user_regs / irq_restore_user_regs for */ - /* IRQ/FIQ handling */ - .macro irq_save_user_regs sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ /* Calling SP, LR */ - str lr, [r8, #0] /* Save calling PC */ + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC mrs r6, spsr - str r6, [r8, #4] /* Save CPSR */ - str r0, [r8, #8] /* Save OLD_R0 */ + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 mov r0, sp .endm @@ -452,16 +389,28 @@ reset: .endm .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack + ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] + str lr, [r13] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of saved stack mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & switch modes. + .endm + + .macro get_bad_stack_swi + sub r13, r13, #4 @ space on current stack for scratch reg. + str r0, [r13] @ save R0's value. + ldr r0, IRQ_STACK_START_IN @ get data regions start + str lr, [r0] @ save caller lr in position 0 of saved stack + mrs r0, spsr @ get the spsr + str lr, [r0, #4] @ save spsr in position 1 of saved stack + ldr r0, [r13] @ restore r0 + add r13, r13, #4 @ pop stack entry .endm .macro get_irq_stack @ setup IRQ stack @@ -471,21 +420,17 @@ reset: .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm -#endif /* CONFIG_SPL_BUILD - - -/****************************************************************************/ -/* */ -/* exception handlers */ -/* */ -/****************************************************************************/ +#endif /* CONFIG_SPL_BUILD */ +/* + * exception handlers + */ #ifdef CONFIG_SPL_BUILD .align 5 do_hang: - ldr sp, _TEXT_BASE /* use 32 words abort stack */ + ldr sp, _TEXT_BASE /* use 32 words about stack */ bl hang /* hang and never return */ -#else +#else /* !CONFIG_SPL_BUILD */ .align 5 undefined_instruction: get_bad_stack @@ -494,7 +439,7 @@ undefined_instruction: .align 5 software_interrupt: - get_bad_stack + get_bad_stack_swi bad_save_user_regs bl do_software_interrupt @@ -528,11 +473,12 @@ irq: .align 5 fiq: get_fiq_stack - irq_save_user_regs /* someone ought to write a more */ - bl do_fiq /* effiction fiq_save_user_regs */ + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq irq_restore_user_regs -#else /* !CONFIG_USE_IRQ */ +#else .align 5 irq: @@ -545,63 +491,7 @@ fiq: get_bad_stack bad_save_user_regs bl do_fiq -#endif /* CONFIG_SPL_BUILD */ -#endif /* CONFIG_USE_IRQ */ - -/****************************************************************************/ -/* */ -/* Reset function: the PXA250 doesn't have a reset function, so we have to */ -/* perform a watchdog timeout for a soft reset. */ -/* */ -/****************************************************************************/ -/* Operating System Timer */ -.align 5 -.globl reset_cpu - - /* FIXME: this code is PXA250 specific. How is this handled on */ - /* other XScale processors? */ - -reset_cpu: - - /* We set OWE:WME (watchdog enable) and wait until timeout happens */ - ldr r0, =OWER - ldr r1, [r0] - orr r1, r1, #0x0001 /* bit0: WME */ - str r1, [r0] - - /* OS timer does only wrap every 1165 seconds, so we have to set */ - /* the match register as well. */ - - ldr r0, =OSCR - ldr r1, [r0] /* read OS timer */ - add r1, r1, #0x800 /* let OSMR3 match after */ - add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */ - ldr r0, =OSMR3 - str r1, [r0] - -reset_endless: - - b reset_endless - -#ifndef CONFIG_SPL_BUILD -.section .mmudata, "a" - .align 14 - .globl mmu_table -mmu_table: - /* 0x00000000 - 0xa0000000 : 1:1, uncached mapping */ - .set __base, 0 - .rept 0xa00 - .word (__base << 20) | 0xc12 - .set __base, __base + 1 - .endr - - /* 0xa0000000 - 0xa0100000 : 1:1, cached mapping */ - .word (0xa00 << 20) | 0x1c1e - - .set __base, 0xa01 - .rept 0x1000 - 0xa01 - .word (__base << 20) | 0xc12 - .set __base, __base + 1 - .endr +#endif + .align 5 #endif /* CONFIG_SPL_BUILD */ -- cgit v0.10.2 From 7f4cfcf40d04b03091400c85fd4815335feec401 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Nov 2011 19:26:47 +0100 Subject: PXA: Re-add the Dcache locking as RAM for pxa250 Signed-off-by: Marek Vasut Cc: Stefan Herbrechtsmeier Cc: Albert ARIBAUD diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 88a4cc2..6504819 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -38,6 +38,13 @@ #include #include #include + +#ifdef CONFIG_PXA25X +#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) +#error "Init SP address must be set to 0xfffff800 for PXA250" +#endif +#endif + .globl _start _start: b reset #ifdef CONFIG_SPL_BUILD @@ -153,6 +160,10 @@ reset: bl cpu_init_crit #endif +#ifdef CONFIG_PXA250 + bl lock_cache_for_stack +#endif + /* Set stackpointer in internal RAM to call board_init_f */ call_board_init_f: ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) @@ -179,6 +190,11 @@ relocate_code: stack_setup: mov sp, r4 +/* Disable the Dcache RAM lock for stack now */ +#ifdef CONFIG_PXA250 + bl cpu_init_crit +#endif + adr r0, _start cmp r0, r6 beq clear_bss /* skip relocation */ @@ -291,7 +307,7 @@ _dynsym_start_ofs: * ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_PXA250) cpu_init_crit: /* * flush v4 I/D caches @@ -311,7 +327,7 @@ cpu_init_crit: mcr p15, 0, r0, c1, c0, 0 mov pc, lr /* back to my caller */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_PXA250 */ #ifndef CONFIG_SPL_BUILD /* @@ -495,3 +511,95 @@ fiq: #endif .align 5 #endif /* CONFIG_SPL_BUILD */ + + +/* + * Enable MMU to use DCache as DRAM. + * + * This is useful on PXA25x and PXA26x in early bootstages, where there is no + * other possible memory available to hold stack. + */ +#ifdef CONFIG_PXA250 +.macro CPWAIT reg + mrc p15, 0, \reg, c2, c0, 0 + mov \reg, \reg + sub pc, pc, #4 +.endm +lock_cache_for_stack: + /* Domain access -- enable for all CPs */ + ldr r0, =0x0000ffff + mcr p15, 0, r0, c3, c0, 0 + + /* Point TTBR to MMU table */ + ldr r0, =mmutable + mcr p15, 0, r0, c2, c0, 0 + + /* Kick in MMU, ICache, DCache, BTB */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, #0x1b00 + bic r0, #0x0087 + orr r0, #0x1800 + orr r0, #0x0005 + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + /* Unlock Icache, Dcache */ + mcr p15, 0, r0, c9, c1, 1 + mcr p15, 0, r0, c9, c2, 1 + + /* Flush Icache, Dcache, BTB */ + mcr p15, 0, r0, c7, c7, 0 + + /* Unlock I-TLB, D-TLB */ + mcr p15, 0, r0, c10, c4, 1 + mcr p15, 0, r0, c10, c8, 1 + + /* Flush TLB */ + mcr p15, 0, r0, c8, c7, 0 + + /* Allocate 4096 bytes of Dcache as RAM */ + + /* Drain pending loads and stores */ + mcr p15, 0, r0, c7, c10, 4 + + mov r4, #0x00 + mov r5, #0x00 + mov r2, #0x01 + mcr p15, 0, r0, c9, c2, 0 + CPWAIT r0 + + /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ + mov r0, #128 + ldr r1, =0xfffff000 + +alloc: + mcr p15, 0, r1, c7, c2, 5 + /* Drain pending loads and stores */ + mcr p15, 0, r0, c7, c10, 4 + strd r4, [r1], #8 + strd r4, [r1], #8 + strd r4, [r1], #8 + strd r4, [r1], #8 + subs r0, #0x01 + bne alloc + /* Drain pending loads and stores */ + mcr p15, 0, r0, c7, c10, 4 + mov r2, #0x00 + mcr p15, 0, r2, c9, c2, 0 + CPWAIT r0 + + mov pc, lr + +.section .mmutable, "a" +mmutable: + .align 14 + /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ + .set __base, 0 + .rept 0xfff + .word (__base << 20) | 0xc12 + .set __base, __base + 1 + .endr + + /* 0xfff00000 : 1:1, cached mapping */ + .word (0xfff << 20) | 0x1c1e +#endif /* CONFIG_PXA250 */ diff --git a/arch/arm/cpu/pxa/u-boot.lds b/arch/arm/cpu/pxa/u-boot.lds index e163369..e86e781 100644 --- a/arch/arm/cpu/pxa/u-boot.lds +++ b/arch/arm/cpu/pxa/u-boot.lds @@ -63,6 +63,12 @@ SECTIONS *(.dynsym) } + . = ALIGN(4096); + + .mmutable : { + *(.mmutable) + } + _end = .; .bss __rel_dyn_start (OVERLAY) : { -- cgit v0.10.2 From 00d5ec937d4ba782c034d0c31bcd1b0055fdf441 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Nov 2011 12:04:11 +0100 Subject: PXA: Fixup PXA25x boards after start.S update Signed-off-by: Marek Vasut diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 90c5bf8..07bc895 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -175,7 +175,7 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 #define FPGA_REGS_BASE_PHYSICAL 0x08000000 diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index bdb5f57..026e183 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -157,7 +157,7 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 /* * NOR FLASH diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 620d270..c208a25 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -291,7 +291,7 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 /* * GPIO settings diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 6dce8ae..5c59ac7 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -168,7 +168,7 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 /* * FLASH and environment organization -- cgit v0.10.2 From 496471df9e8a4216386d4e43b95e531f0ca7f140 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 31 Oct 2011 13:11:48 +0100 Subject: PXA: Drop Voipac PXA270 OneNAND IPL This OneNAND IPL will be replaced by OneNAND SPL. Signed-off-by: Marek Vasut Cc: Albert ARIBAUD diff --git a/onenand_ipl/board/vpac270/Makefile b/onenand_ipl/board/vpac270/Makefile deleted file mode 100644 index f850ddd..0000000 --- a/onenand_ipl/board/vpac270/Makefile +++ /dev/null @@ -1,79 +0,0 @@ - -include $(TOPDIR)/config.mk -include $(TOPDIR)/board/$(BOARDDIR)/config.mk - -LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds -LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS) -AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL -CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL -OBJCFLAGS += --gap-fill=0x00 - -SOBJS += start.o -COBJS := vpac270.o -COBJS += onenand_read.o -COBJS += onenand_boot.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR) - -onenandobj := $(OBJTREE)/onenand_ipl/ - -ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin - -all: $(obj).depend $(ALL) - -$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x0800 -O binary $< $@ - -$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(onenandobj)onenand-ipl: $(OBJS) $(onenandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ - -Map $@.map -o $@ - -$(onenandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links from common files - -# from cpu directory -$(obj)start.S: - @rm -f $@ - ln -s $(SRCTREE)/$(CPUDIR)/start.S $@ - -# from onenand_ipl directory -$(obj)onenand_ipl.h: - @rm -f $@ - ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $@ - -$(obj)onenand_boot.c: $(obj)onenand_ipl.h - @rm -f $@ - ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $@ - -$(obj)onenand_read.c: $(obj)onenand_ipl.h - @rm -f $@ - ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)vpac270.c: - @rm -f $@ - ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/vpac270.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)$.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/onenand_ipl/board/vpac270/config.mk b/onenand_ipl/board/vpac270/config.mk deleted file mode 100644 index 752836d..0000000 --- a/onenand_ipl/board/vpac270/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x5c03fc00 diff --git a/onenand_ipl/board/vpac270/u-boot.onenand.lds b/onenand_ipl/board/vpac270/u-boot.onenand.lds deleted file mode 100644 index b5b2646..0000000 --- a/onenand_ipl/board/vpac270/u-boot.onenand.lds +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) . = ALIGN(4); } - __bss_end__ = .; -} diff --git a/onenand_ipl/board/vpac270/vpac270.c b/onenand_ipl/board/vpac270/vpac270.c deleted file mode 100644 index a1eb331..0000000 --- a/onenand_ipl/board/vpac270/vpac270.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * (C) Copyright 2004 - * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -int board_init (void) -{ - return 0; -} - -int s_init(int skip) -{ - return 0; -} -- cgit v0.10.2 From 411b9eaf554225c12ca253473002d0381cfec4ff Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 31 Oct 2011 14:17:21 +0100 Subject: PXA: Adapt Voipac PXA270 to OneNAND SPL Signed-off-by: Marek Vasut Cc: Albert ARIBAUD V2: Add missing u-boot-spl.lds, convert bitshifts to division, convert to spl_onenand_load_image() diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile index b5c60fd..5967055 100644 --- a/board/vpac270/Makefile +++ b/board/vpac270/Makefile @@ -23,7 +23,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +ifndef CONFIG_SPL_BUILD COBJS := vpac270.o +else +COBJS := onenand.o +endif SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/vpac270/onenand.c b/board/vpac270/onenand.c new file mode 100644 index 0000000..6a0a37b --- /dev/null +++ b/board/vpac270/onenand.c @@ -0,0 +1,66 @@ +/* + * Voipac PXA270 OneNAND SPL + * + * Copyright (C) 2011 Marek Vasut + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +extern void pxa_dram_init(void); + +void board_init_f(unsigned long unused) +{ + extern uint32_t _end; + uint32_t tmp; + + asm volatile("mov %0, pc" : "=r"(tmp)); + tmp >>= 24; + + /* The code runs from OneNAND RAM, copy SPL to SRAM and execute it. */ + if (tmp == 0) { + tmp = (uint32_t)&_end - CONFIG_SPL_TEXT_BASE; + onenand_spl_load_image(0, tmp, (void *)CONFIG_SPL_TEXT_BASE); + asm volatile("mov pc, %0" : : "r"(CONFIG_SPL_TEXT_BASE)); + } + + /* Hereby, the code runs from (S)RAM, copy U-Boot and execute it. */ + arch_cpu_init(); + pxa_dram_init(); + onenand_spl_load_image(CONFIG_SPL_ONENAND_LOAD_ADDR, + CONFIG_SPL_ONENAND_LOAD_SIZE, + (void *)CONFIG_SYS_TEXT_BASE); + asm volatile("mov pc, %0" : : "r"(CONFIG_SYS_TEXT_BASE)); + + for (;;) + ; +} + +void __attribute__((noreturn)) hang(void) +{ + for (;;) + ; +} + +void icache_disable(void) {} +void dcache_disable(void) {} diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds new file mode 100644 index 0000000..1958c2f --- /dev/null +++ b/board/vpac270/u-boot-spl.lds @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = CONFIG_SPL_TEXT_BASE; + .text.0 : + { + arch/arm/cpu/pxa/start.o (.text*) + board/vpac270/libvpac270.o (.text*) + drivers/mtd/onenand/libonenand.o (.text*) + } + + + /* Start of the rest of the SPL */ + . = CONFIG_SPL_TEXT_BASE + 0x800; + + .text.1 : + { + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data) + } + + . = ALIGN(4); + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + . = ALIGN(0x800); + + _end = .; + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end__ = .; + } + + /DISCARD/ : { *(.bss*) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index cf8e7b6..d90a859 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -57,7 +57,9 @@ struct serial_device *default_serial_console(void) extern void pxa_dram_init(void); int dram_init(void) { +#ifndef CONFIG_ONENAND pxa_dram_init(); +#endif gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index dd68c66..8accebf 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -27,7 +27,17 @@ */ #define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ #define CONFIG_VPAC270 1 /* Voipac PXA270 board */ -#define CONFIG_SYS_TEXT_BASE 0x0 +#define CONFIG_SYS_TEXT_BASE 0xa0000000 + +#ifdef CONFIG_ONENAND +#define CONFIG_SPL +#define CONFIG_SPL_ONENAND_SUPPORT +#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x2000 +#define CONFIG_SPL_ONENAND_LOAD_SIZE \ + (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR) +#define CONFIG_SPL_TEXT_BASE 0x5c000000 +#define CONFIG_SPL_LDSCRIPT "board/vpac270/u-boot-spl.lds" +#endif /* * Environment settings @@ -46,12 +56,19 @@ "bootm 0xa4000000; " \ "fi; " \ "bootm 0x60000;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "update_onenand=" \ + "onenand erase 0x0 0x80000 ; " \ + "onenand write 0xa0000000 0x0 0x80000" + #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" #define CONFIG_TIMESTAMP #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_LZMA /* LZMA compression support */ +#define CONFIG_OF_LIBFDT /* * Serial Console Configuration @@ -180,16 +197,14 @@ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 -#define CONFIG_SYS_IPL_LOAD_ADDR (0x5c000000) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR \ - (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048) +#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 /* * NOR FLASH */ #define CONFIG_SYS_MONITOR_BASE 0x0 -#define CONFIG_SYS_MONITOR_LEN 0x40000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 #define CONFIG_ENV_ADDR \ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_SIZE 0x4000 -- cgit v0.10.2 From 7c7204db357eedc93b3b0ff1b760f58263b6c789 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 12 Nov 2011 03:35:50 +0100 Subject: PXA: Enable command line editing for vpac270 Signed-off-by: Marek Vasut diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 8accebf..41f8a6b 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -158,6 +158,8 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_DEVICE_NULLDEV 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE 1 /* * Clock Configuration -- cgit v0.10.2 From 3e43c749f2c9c22e0841294c304639907b444608 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 13 Nov 2011 01:40:46 +0100 Subject: PXA: Unify vpac270 environment size Signed-off-by: Marek Vasut Cc: Albert Aribaud diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 41f8a6b..e78b83a 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -209,7 +209,8 @@ #define CONFIG_SYS_MONITOR_LEN 0x80000 #define CONFIG_ENV_ADDR \ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 #if defined(CONFIG_CMD_FLASH) /* NOR */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ @@ -238,22 +239,11 @@ #define CONFIG_ENV_IS_IN_FLASH 1 -/* - * The first four sectors of the NOR flash are 0x8000 bytes big, the rest of the - * flash consists of 0x20000 bytes big sectors. - */ -#if (CONFIG_ENV_ADDR <= 0x18000) -#define CONFIG_ENV_SECT_SIZE 0x8000 -#else -#define CONFIG_ENV_SECT_SIZE 0x20000 -#endif - #elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_ONENAND_BASE 0x00000000 #define CONFIG_ENV_IS_IN_ONENAND 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 #else /* No flash */ #define CONFIG_SYS_NO_FLASH -- cgit v0.10.2 From abc20aba1834c321a638b367c18dcce1bb4e232d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Nov 2011 07:20:07 +0100 Subject: PXA: Rename CONFIG_PXA2[57]X to CONFIG_CPU_PXA2[57]X Signed-off-by: Marek Vasut diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c index c48b2ef..7727554 100644 --- a/arch/arm/cpu/pxa/cpu.c +++ b/arch/arm/cpu/pxa/cpu.c @@ -234,21 +234,21 @@ void pxa_gpio_setup(void) writel(CONFIG_SYS_GPSR0_VAL, GPSR0); writel(CONFIG_SYS_GPSR1_VAL, GPSR1); writel(CONFIG_SYS_GPSR2_VAL, GPSR2); -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) writel(CONFIG_SYS_GPSR3_VAL, GPSR3); #endif writel(CONFIG_SYS_GPCR0_VAL, GPCR0); writel(CONFIG_SYS_GPCR1_VAL, GPCR1); writel(CONFIG_SYS_GPCR2_VAL, GPCR2); -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) writel(CONFIG_SYS_GPCR3_VAL, GPCR3); #endif writel(CONFIG_SYS_GPDR0_VAL, GPDR0); writel(CONFIG_SYS_GPDR1_VAL, GPDR1); writel(CONFIG_SYS_GPDR2_VAL, GPDR2); -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) writel(CONFIG_SYS_GPDR3_VAL, GPDR3); #endif @@ -258,7 +258,7 @@ void pxa_gpio_setup(void) writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U); writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L); writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U); -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L); writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U); #endif @@ -270,7 +270,7 @@ void pxa_interrupt_setup(void) { writel(0, ICLR); writel(0, ICMR); -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) writel(0, ICLR2); writel(0, ICMR2); #endif diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 6504819..ba0de8f 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -39,7 +39,7 @@ #include #include -#ifdef CONFIG_PXA25X +#ifdef CONFIG_CPU_PXA25X #if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) #error "Init SP address must be set to 0xfffff800 for PXA250" #endif @@ -160,7 +160,7 @@ reset: bl cpu_init_crit #endif -#ifdef CONFIG_PXA250 +#ifdef CONFIG_CPU_PXA25X bl lock_cache_for_stack #endif @@ -191,7 +191,7 @@ stack_setup: mov sp, r4 /* Disable the Dcache RAM lock for stack now */ -#ifdef CONFIG_PXA250 +#ifdef CONFIG_CPU_PXA25X bl cpu_init_crit #endif @@ -307,7 +307,7 @@ _dynsym_start_ofs: * ************************************************************************* */ -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_PXA250) +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) cpu_init_crit: /* * flush v4 I/D caches @@ -327,7 +327,7 @@ cpu_init_crit: mcr p15, 0, r0, c1, c0, 0 mov pc, lr /* back to my caller */ -#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_PXA250 */ +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ #ifndef CONFIG_SPL_BUILD /* @@ -519,7 +519,7 @@ fiq: * This is useful on PXA25x and PXA26x in early bootstages, where there is no * other possible memory available to hold stack. */ -#ifdef CONFIG_PXA250 +#ifdef CONFIG_CPU_PXA25X .macro CPWAIT reg mrc p15, 0, \reg, c2, c0, 0 mov \reg, \reg @@ -602,4 +602,4 @@ mmutable: /* 0xfff00000 : 1:1, cached mapping */ .word (0xfff << 20) | 0x1c1e -#endif /* CONFIG_PXA250 */ +#endif /* CONFIG_CPU_PXA25X */ diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c index 2866745..0ad64dd 100644 --- a/arch/arm/cpu/pxa/timer.c +++ b/arch/arm/cpu/pxa/timer.c @@ -35,9 +35,9 @@ #error: interrupts not implemented yet #endif -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define TIMER_FREQ_HZ 3250000 -#elif defined(CONFIG_PXA250) +#elif defined(CONFIG_CPU_PXA25X) #define TIMER_FREQ_HZ 3686400 #else #error "Timer frequency unknown - please config PXA CPU type" diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c index 0311d5e..83022e2 100644 --- a/arch/arm/cpu/pxa/usb.c +++ b/arch/arm/cpu/pxa/usb.c @@ -24,7 +24,7 @@ #include #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) -# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) +# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) #include #include @@ -37,7 +37,7 @@ int usb_cpu_init(void) writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA); udelay(100); #endif -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) /* Enable USB host clock. */ writel(readl(CKEN) | CKEN10_USBHOST, CKEN); #endif @@ -58,7 +58,7 @@ int usb_cpu_init(void) #if defined(CONFIG_CPU_MONAHANS) writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); #endif -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR); #endif writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR); @@ -78,7 +78,7 @@ int usb_cpu_stop(void) #if defined(CONFIG_CPU_MONAHANS) writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR); #endif -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR); #endif writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR); @@ -88,7 +88,7 @@ int usb_cpu_stop(void) writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA); udelay(100); #endif -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) /* Disable USB host clock. */ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); #endif @@ -101,5 +101,5 @@ int usb_cpu_init_fail(void) return usb_cpu_stop(); } -# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */ +# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */ #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index 52c79a9..8527c68 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -109,7 +109,7 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */ #define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */ #define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */ #define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */ #define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */ @@ -126,7 +126,7 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */ #define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */ #define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ #define DCSR(x) (0x40000000 | ((x) << 2)) @@ -134,7 +134,7 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ -#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ @@ -438,7 +438,7 @@ typedef void (*ExcpHndlr) (void) ; /* * USB Device Controller */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define UDCCR 0x40600000 /* UDC Control Register */ #define UDCCR_UDE (1 << 0) /* UDC enable */ @@ -797,9 +797,9 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) #define UDC_BCR_MASK (0x3ff) -#endif /* CONFIG_PXA27X */ +#endif /* CONFIG_CPU_PXA27X */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) /******************************************************************************/ /* @@ -870,7 +870,7 @@ typedef void (*ExcpHndlr) (void) ; #define UP2OCR_CPVPE (1<<1) #define UP2OCR_CPVEN (1<<0) -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ /******************************************************************************/ /* @@ -923,7 +923,7 @@ typedef void (*ExcpHndlr) (void) ; #define OWER 0x40A00018 /* OS Timer Watchdog Enable Register */ #define OIER 0x40A0001C /* OS Timer Interrupt Enable Register */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define OSCR4 0x40A00040 /* OS Timer Counter Register 4 */ #define OSCR5 0x40A00044 /* OS Timer Counter Register 5 */ #define OSCR6 0x40A00048 /* OS Timer Counter Register 6 */ @@ -951,7 +951,7 @@ typedef void (*ExcpHndlr) (void) ; #define OMCR10 0x40A000D8 /* OS Match Control Register 10 */ #define OMCR11 0x40A000DC /* OS Match Control Register 11 */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ #define OSSR_M4 (1 << 4) /* Match status channel 4 */ #define OSSR_M3 (1 << 3) /* Match status channel 3 */ @@ -1052,7 +1052,7 @@ typedef void (*ExcpHndlr) (void) ; #define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#if !defined(CONFIG_PXA27X) +#if !defined(CONFIG_CPU_PXA27X) #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ #endif #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ @@ -1071,7 +1071,7 @@ typedef void (*ExcpHndlr) (void) ; #define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ #define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ #define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ #define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ #endif @@ -1087,7 +1087,7 @@ typedef void (*ExcpHndlr) (void) ; #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ -#if !defined(CONFIG_PXA27X) +#if !defined(CONFIG_CPU_PXA27X) #define CCCR_L09 (0x1F) #define CCCR_L27 (0x1) #define CCCR_L32 (0x2) @@ -1120,7 +1120,7 @@ typedef void (*ExcpHndlr) (void) ; #define PWM_PWDUTY1 0x40C00004 /* PWM 1 Duty Cycle Register */ #define PWM_PERVAL1 0x40C00008 /* PWM 1 Period Control Register */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define PWM_CTRL2 0x40B00010 /* PWM 2 Control Register */ #define PWM_PWDUTY2 0x40B00014 /* PWM 2 Duty Cycle Register */ #define PWM_PERVAL2 0x40B00018 /* PWM 2 Period Control Register */ @@ -1128,7 +1128,7 @@ typedef void (*ExcpHndlr) (void) ; #define PWM_CTRL3 0x40C00010 /* PWM 3 Control Register */ #define PWM_PWDUTY3 0x40C00014 /* PWM 3 Duty Cycle Register */ #define PWM_PERVAL3 0x40C00018 /* PWM 3 Period Control Register */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ /* * Interrupt Controller @@ -1140,14 +1140,14 @@ typedef void (*ExcpHndlr) (void) ; #define ICPR 0x40D00010 /* Interrupt Controller Pending Register */ #define ICCR 0x40D00014 /* Interrupt Controller Control Register */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define ICHP 0x40D00018 /* Interrupt Controller Highest Priority Register */ #define ICIP2 0x40D0009C /* Interrupt Controller IRQ Pending Register 2 */ #define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */ #define ICLR2 0x40D000A4 /* Interrupt Controller Level Register 2 */ #define ICFP2 0x40D000A8 /* Interrupt Controller FIQ Pending Register 2 */ #define ICPR2 0x40D000AC /* Interrupt Controller Pending Register 2 */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ /******************************************************************************/ /* @@ -1188,7 +1188,7 @@ typedef void (*ExcpHndlr) (void) ; #define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */ #define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */ #define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */ #define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */ @@ -1198,7 +1198,7 @@ typedef void (*ExcpHndlr) (void) ; #define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */ #define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */ #define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ #ifdef CONFIG_CPU_MONAHANS #define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */ @@ -1244,7 +1244,7 @@ typedef void (*ExcpHndlr) (void) ; #define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3)) #define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2)) -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)) #define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)) #define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)) @@ -2123,7 +2123,7 @@ typedef void (*ExcpHndlr) (void) ; #define LCCR0_PDD_S 12 #define LCCR0_BM (1 << 20) /* Branch mask */ #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define LCCR0_LCDT (1 << 22) /* LCD Panel Type */ #define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */ #define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */ @@ -2249,7 +2249,7 @@ typedef void (*ExcpHndlr) (void) ; #define LCSR1_IU6 (1 << 29) #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define LDCMD_SOFINT (1 << 22) #define LDCMD_EOFINT (1 << 21) #endif @@ -2480,7 +2480,7 @@ typedef void (*ExcpHndlr) (void) ; #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define ARB_CNTRL 0x48000048 /* Arbiter Control Register */ @@ -2494,7 +2494,7 @@ typedef void (*ExcpHndlr) (void) ; #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ -#endif /* CONFIG_PXA27X */ +#endif /* CONFIG_CPU_PXA27X */ /* LCD registers */ #define LCCR4 0x44000010 /* LCD Controller Control Register 4 */ @@ -2628,6 +2628,6 @@ typedef void (*ExcpHndlr) (void) ; #define OSCR4 0x40A00040 /* OS Timer Counter Register */ #define OMCR4 0x40A000C0 /* */ -#endif /* CONFIG_PXA27X */ +#endif /* CONFIG_CPU_PXA27X */ #endif /* _PXA_REGS_H_ */ diff --git a/common/lcd.c b/common/lcd.c index 6313ec0..bf1a6a9 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -41,7 +41,9 @@ #include #include -#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS +#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ + defined(CONFIG_CPU_MONAHANS) +#define CONFIG_CPU_PXA #include #endif @@ -512,7 +514,7 @@ void bitmap_plot (int x, int y) uchar *bmap; uchar *fb; ushort *fb16; -#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS +#if defined(CONFIG_CPU_PXA) struct pxafb_info *fbi = &panel_info.pxa; #elif defined(CONFIG_MPC823) volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; @@ -528,7 +530,7 @@ void bitmap_plot (int x, int y) if (NBITS(panel_info.vl_bpix) < 12) { /* Leave room for default color map */ -#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS +#if defined(CONFIG_CPU_PXA) cmap = (ushort *)fbi->palette; #elif defined(CONFIG_MPC823) cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]); @@ -623,7 +625,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) unsigned long width, height, byte_width; unsigned long pwidth = panel_info.vl_col; unsigned colors, bpix, bmp_bpix; -#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS +#if defined(CONFIG_CPU_PXA) struct pxafb_info *fbi = &panel_info.pxa; #elif defined(CONFIG_MPC823) volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; @@ -663,7 +665,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) #if !defined(CONFIG_MCC200) /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */ if (bmp_bpix == 8) { -#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS +#if defined(CONFIG_CPU_PXA) cmap = (ushort *)fbi->palette; #elif defined(CONFIG_MPC823) cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]); @@ -752,7 +754,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) WATCHDOG_RESET(); for (j = 0; j < width; j++) { if (bpix != 16) { -#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS || defined(CONFIG_ATMEL_LCD) +#if defined(CONFIG_CPU_PXA) || defined(CONFIG_ATMEL_LCD) *(fb++) = *(bmap++); #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200) *(fb++) = 255 - *(bmap++); diff --git a/drivers/mmc/pxa_mmc.c b/drivers/mmc/pxa_mmc.c index 3c2905c..2b58a98 100644 --- a/drivers/mmc/pxa_mmc.c +++ b/drivers/mmc/pxa_mmc.c @@ -129,7 +129,7 @@ mmc_block_read(uchar * dst, uint32_t src, int len) writel(~MMC_I_MASK_RXFIFO_RD_REQ, MMC_I_MASK); while (len) { if (readl(MMC_I_REG) & MMC_I_REG_RXFIFO_RD_REQ) { -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) int i; for (i = min(len, 32); i; i--) { *dst++ = readb(MMC_RXFIFO); @@ -560,7 +560,8 @@ mmc_legacy_init(int verbose) /* Reset device interface type */ mmc_dev.if_type = IF_TYPE_UNKNOWN; -#if defined (CONFIG_LUBBOCK) || (defined (CONFIG_GUMSTIX) && !defined(CONFIG_PXA27X)) +#if defined(CONFIG_LUBBOCK) || \ + (defined(CONFIG_GUMSTIX) && !defined(CONFIG_CPU_PXA27X)) set_GPIO_mode(GPIO6_MMCCLK_MD); set_GPIO_mode(GPIO8_MMCCS0_MD); #endif @@ -633,7 +634,7 @@ mmc_legacy_init(int verbose) writel(0, MMC_CLKRT); /* 20 MHz */ resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1); -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) if (IF_TYPE_SD == mmc_dev.if_type) { resp = mmc_cmd(MMC_CMD_APP_CMD, rca, 0, MMC_CMDAT_R1); resp = mmc_cmd(SD_CMD_APP_SET_BUS_WIDTH, 0, 2, MMC_CMDAT_R1); diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c index 28e37b4..4a7c67a 100644 --- a/drivers/mmc/pxa_mmc_gen.c +++ b/drivers/mmc/pxa_mmc_gen.c @@ -30,12 +30,12 @@ #include /* PXAMMC Generic default config for various CPUs */ -#if defined(CONFIG_PXA250) +#if defined(CONFIG_CPU_PXA25X) #define PXAMMC_FIFO_SIZE 1 #define PXAMMC_MIN_SPEED 312500 #define PXAMMC_MAX_SPEED 20000000 #define PXAMMC_HOST_CAPS (0) -#elif defined(CONFIG_PXA27X) +#elif defined(CONFIG_CPU_PXA27X) #define PXAMMC_CRC_SKIP #define PXAMMC_FIFO_SIZE 32 #define PXAMMC_MIN_SPEED 304000 diff --git a/drivers/net/lan91c96.h b/drivers/net/lan91c96.h index 6fbb0e3..bef1522 100644 --- a/drivers/net/lan91c96.h +++ b/drivers/net/lan91c96.h @@ -68,7 +68,7 @@ typedef unsigned long int dword; #define SMC_IO_EXTENT 16 -#ifdef CONFIG_PXA250 +#ifdef CONFIG_CPU_PXA25X #ifdef CONFIG_LUBBOCK #define SMC_IO_SHIFT 2 @@ -146,7 +146,7 @@ typedef unsigned long int dword; }; \ }) -#else /* if not CONFIG_PXA250 */ +#else /* if not CONFIG_CPU_PXA25X */ /* * We have only 16 Bit PCMCIA access on Socket 0 diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index 895c749..d70c66f 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -78,7 +78,7 @@ struct smc91111_priv{ #define SMC_IO_EXTENT 16 -#ifdef CONFIG_PXA250 +#ifdef CONFIG_CPU_PXA25X #ifdef CONFIG_XSENGINE #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1)))) @@ -180,7 +180,7 @@ struct smc91111_priv{ }; \ }) -#elif defined(CONFIG_LEON) /* if not CONFIG_PXA250 */ +#elif defined(CONFIG_LEON) /* if not CONFIG_CPU_PXA25X */ #define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); }) @@ -249,7 +249,7 @@ struct smc91111_priv{ }; \ }while(0) -#else /* if not CONFIG_PXA250 and not CONFIG_LEON */ +#else /* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */ #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ /* diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c index 84bb17c..a9976d7 100644 --- a/drivers/serial/serial_pxa.c +++ b/drivers/serial/serial_pxa.c @@ -49,7 +49,7 @@ DECLARE_GLOBAL_DATA_PTR; #define BTUART_INDEX 0 #define FFUART_INDEX 1 #define STUART_INDEX 2 -#elif CONFIG_PXA250 +#elif CONFIG_CPU_PXA25X #define UART_CLK_BASE (1 << 4) /* HWUART */ #define UART_CLK_REG CKEN #define HWUART_INDEX 0 @@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR; * Only PXA250 has HWUART, to avoid poluting the code with more macros, * artificially introduce this. */ -#ifndef CONFIG_PXA250 +#ifndef CONFIG_CPU_PXA25X #define HWUART_INDEX 0xff #endif diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index 14961c1..e449cd7 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -31,7 +31,7 @@ #include #elif defined(CONFIG_MUSB_UDC) #include -#elif defined(CONFIG_PXA27X) +#elif defined(CONFIG_CPU_PXA27X) #include #elif defined(CONFIG_SPEAR3XX) || defined(CONFIG_SPEAR600) #include diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 7d5b504..5e72713 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -37,7 +37,7 @@ COBJS-y += ep0.o COBJS-$(CONFIG_OMAP1510) += omap1510_udc.o COBJS-$(CONFIG_OMAP1610) += omap1510_udc.o COBJS-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o -COBJS-$(CONFIG_PXA27X) += pxa27x_udc.o +COBJS-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o COBJS-$(CONFIG_SPEARUDC) += spr_udc.o endif endif diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h index b604b52..a5ec224 100644 --- a/include/configs/balloon3.h +++ b/include/configs/balloon3.h @@ -25,7 +25,7 @@ /* * High Level Board Configuration Options */ -#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ #define CONFIG_BALLOON3 1 /* Balloon3 board */ /* diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 8a3446e..819c5d0 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -25,7 +25,7 @@ /* * High Level Board Configuration Options */ -#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ #define CONFIG_VPAC270 1 /* Toradex Colibri PXA270 board */ #undef CONFIG_BOARD_LATE_INIT diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 07bc895..361ffc5 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -34,7 +34,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */ #define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */ #define CONFIG_LCD 1 #ifdef CONFIG_LCD diff --git a/include/configs/palmld.h b/include/configs/palmld.h index 514bcaa..88f4bfb 100644 --- a/include/configs/palmld.h +++ b/include/configs/palmld.h @@ -25,7 +25,7 @@ /* * High Level Board Configuration Options */ -#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ #define CONFIG_PALMLD 1 /* Palm LifeDrive board */ /* diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index 026e183..d1fef25 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -27,7 +27,7 @@ /* * High Level Board Configuration Options */ -#define CONFIG_PXA250 1 /* Intel PXA255 CPU */ +#define CONFIG_CPU_PXA25X 1 /* Intel PXA255 CPU */ #define CONFIG_PALMTC 1 /* Palm Tungsten|C board */ /* diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index c208a25..0666f7b 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -55,7 +55,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */ #undef CONFIG_LCD #ifdef CONFIG_LCD diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index 2d55044..af464e1 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -40,7 +40,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ +#define CONFIG_CPU_PXA27X 1 /* This is an PXA27x CPU */ #define CONFIG_MMC 1 #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index e78b83a..7802f44 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -25,7 +25,7 @@ /* * High Level Board Configuration Options */ -#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ #define CONFIG_VPAC270 1 /* Voipac PXA270 board */ #define CONFIG_SYS_TEXT_BASE 0xa0000000 diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 5c59ac7..941f80c 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -40,7 +40,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA250 1 /* This is an PXA255 CPU */ +#define CONFIG_CPU_PXA25X 1 /* This is an PXA255 CPU */ #define CONFIG_XAENIAX 1 /* on a xaeniax board */ #define CONFIG_SYS_TEXT_BASE 0x0 diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index 9505007..26204af 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -25,7 +25,7 @@ /* * High Level Board Configuration Options */ -#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ #define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */ #define CONFIG_SYS_TEXT_BASE 0x0 diff --git a/include/lcd.h b/include/lcd.h index 83b50f4..d95feeb 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -87,7 +87,8 @@ typedef struct vidinfo { u_char vl_wbf; /* Wait between frames */ } vidinfo_t; -#elif defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS +#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ + defined CONFIG_CPU_MONAHANS /* * PXA LCD DMA descriptor */ @@ -195,7 +196,7 @@ typedef struct vidinfo { void *priv; /* Pointer to driver-specific data */ } vidinfo_t; -#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */ +#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */ extern vidinfo_t panel_info; -- cgit v0.10.2 From d10237d275300562bbfecbbe2f59a97cfb9dc180 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Nov 2011 07:32:24 +0100 Subject: PXA: Separate PXA2xx CPU init Signed-off-by: Marek Vasut diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile index e8b59a3..29dc637 100644 --- a/arch/arm/cpu/pxa/Makefile +++ b/arch/arm/cpu/pxa/Makefile @@ -27,7 +27,10 @@ LIB = $(obj)lib$(CPU).o START = start.o -COBJS += cpu.o +COBJS-$(CONFIG_CPU_PXA25X) = pxa2xx.o +COBJS-$(CONFIG_CPU_PXA27X) = pxa2xx.o + +COBJS = $(COBJS-y) COBJS += pxafb.o COBJS += timer.o COBJS += usb.o diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c deleted file mode 100644 index 7727554..0000000 --- a/arch/arm/cpu/pxa/cpu.c +++ /dev/null @@ -1,346 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include -#include -#include -#include -#include - -static void cache_flush(void); - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * just disable everything that can disturb booting linux - */ - - disable_interrupts (); - - /* turn off I-cache */ - icache_disable(); - dcache_disable(); - - /* flush I-cache */ - cache_flush(); - - return (0); -} - -/* flush I/D-cache */ -static void cache_flush (void) -{ - unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); -} - -#ifndef CONFIG_CPU_MONAHANS -void set_GPIO_mode(int gpio_mode) -{ - int gpio = gpio_mode & GPIO_MD_MASK_NR; - int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; - int val; - - /* This below changes direction setting of GPIO "gpio" */ - val = readl(GPDR(gpio)); - - if (gpio_mode & GPIO_MD_MASK_DIR) - val |= GPIO_bit(gpio); - else - val &= ~GPIO_bit(gpio); - - writel(val, GPDR(gpio)); - - /* This below updates only AF of GPIO "gpio" */ - val = readl(GAFR(gpio)); - val &= ~(0x3 << (((gpio) & 0xf) * 2)); - val |= fn << (((gpio) & 0xf) * 2); - writel(val, GAFR(gpio)); -} -#endif /* CONFIG_CPU_MONAHANS */ - -void pxa_wait_ticks(int ticks) -{ - writel(0, OSCR); - while (readl(OSCR) < ticks) - asm volatile("":::"memory"); -} - -inline void writelrb(uint32_t val, uint32_t addr) -{ - writel(val, addr); - asm volatile("":::"memory"); - readl(addr); - asm volatile("":::"memory"); -} - -void pxa_dram_init(void) -{ - uint32_t tmp; - int i; - /* - * 1) Initialize Asynchronous static memory controller - */ - - writelrb(CONFIG_SYS_MSC0_VAL, MSC0); - writelrb(CONFIG_SYS_MSC1_VAL, MSC1); - writelrb(CONFIG_SYS_MSC2_VAL, MSC2); - /* - * 2) Initialize Card Interface - */ - - /* MECR: Memory Expansion Card Register */ - writelrb(CONFIG_SYS_MECR_VAL, MECR); - /* MCMEM0: Card Interface slot 0 timing */ - writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0); - /* MCMEM1: Card Interface slot 1 timing */ - writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1); - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0); - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1); - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0); - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1); - - /* - * 3) Configure Fly-By DMA register - */ - - writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG); - - /* - * 4) Initialize Timing for Sync Memory (SDCLK0) - */ - - /* - * Before accessing MDREFR we need a valid DRI field, so we set - * this to power on defaults + DRI field. - */ - - /* Read current MDREFR config and zero out DRI */ - tmp = readl(MDREFR) & ~0xfff; - /* Add user-specified DRI */ - tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff; - /* Configure important bits */ - tmp |= MDREFR_K0RUN | MDREFR_SLFRSH; - tmp &= ~(MDREFR_APD | MDREFR_E1PIN); - - /* Write MDREFR back */ - writelrb(tmp, MDREFR); - - /* - * 5) Initialize Synchronous Static Memory (Flash/Peripherals) - */ - - /* Initialize SXCNFG register. Assert the enable bits. - * - * Write SXMRS to cause an MRS command to all enabled banks of - * synchronous static memory. Note that SXLCR need not be written - * at this time. - */ - writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG); - - /* - * 6) Initialize SDRAM - */ - - writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR); - writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR); - - /* - * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure - * but not enable each SDRAM partition pair. - */ - - writelrb(CONFIG_SYS_MDCNFG_VAL & - ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG); - /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */ - pxa_wait_ticks(0x300); - - /* - * 8) Trigger a number (usually 8) refresh cycles by attempting - * non-burst read or write accesses to disabled SDRAM, as commonly - * specified in the power up sequence documented in SDRAM data - * sheets. The address(es) used for this purpose must not be - * cacheable. - */ - for (i = 9; i >= 0; i--) { - writel(i, 0xa0000000); - asm volatile("":::"memory"); - } - /* - * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). - */ - - tmp = CONFIG_SYS_MDCNFG_VAL & - (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3); - tmp |= readl(MDCNFG); - writelrb(tmp, MDCNFG); - - /* - * 10) Write MDMRS. - */ - - writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS); - - /* - * 11) Enable APD - */ - - if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) { - tmp = readl(MDREFR); - tmp |= MDREFR_APD; - writelrb(tmp, MDREFR); - } -} - -void pxa_gpio_setup(void) -{ - writel(CONFIG_SYS_GPSR0_VAL, GPSR0); - writel(CONFIG_SYS_GPSR1_VAL, GPSR1); - writel(CONFIG_SYS_GPSR2_VAL, GPSR2); -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) - writel(CONFIG_SYS_GPSR3_VAL, GPSR3); -#endif - - writel(CONFIG_SYS_GPCR0_VAL, GPCR0); - writel(CONFIG_SYS_GPCR1_VAL, GPCR1); - writel(CONFIG_SYS_GPCR2_VAL, GPCR2); -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) - writel(CONFIG_SYS_GPCR3_VAL, GPCR3); -#endif - - writel(CONFIG_SYS_GPDR0_VAL, GPDR0); - writel(CONFIG_SYS_GPDR1_VAL, GPDR1); - writel(CONFIG_SYS_GPDR2_VAL, GPDR2); -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) - writel(CONFIG_SYS_GPDR3_VAL, GPDR3); -#endif - - writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L); - writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U); - writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L); - writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U); - writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L); - writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U); -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) - writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L); - writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U); -#endif - - writel(CONFIG_SYS_PSSR_VAL, PSSR); -} - -void pxa_interrupt_setup(void) -{ - writel(0, ICLR); - writel(0, ICMR); -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) - writel(0, ICLR2); - writel(0, ICMR2); -#endif -} - -void pxa_clock_setup(void) -{ -#ifndef CONFIG_CPU_MONAHANS - writel(CONFIG_SYS_CKEN, CKEN); - writel(CONFIG_SYS_CCCR, CCCR); - asm volatile("mcr p14, 0, %0, c6, c0, 0"::"r"(2)); -#else -/* Set CKENA/CKENB/ACCR for MH */ -#endif - - /* enable the 32Khz oscillator for RTC and PowerManager */ - writel(OSCC_OON, OSCC); - while(!(readl(OSCC) & OSCC_OOK)) - asm volatile("":::"memory"); -} - -void pxa_wakeup(void) -{ - uint32_t rcsr; - - rcsr = readl(RCSR); - writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR); - - /* Wakeup */ - if (rcsr & RCSR_SMR) { - writel(PSSR_PH, PSSR); - pxa_dram_init(); - icache_disable(); - dcache_disable(); - asm volatile("mov pc, %0"::"r"(readl(PSPR))); - } -} - -int arch_cpu_init(void) -{ - pxa_gpio_setup(); -/* pxa_wait_ticks(0x8000); */ - pxa_wakeup(); - pxa_interrupt_setup(); - pxa_clock_setup(); - return 0; -} - -void i2c_clk_enable(void) -{ - /* set the global I2C clock on */ -#ifdef CONFIG_CPU_MONAHANS - writel(readl(CKENB) | (CKENB_4_I2C), CKENB); -#else - writel(readl(CKEN) | CKEN14_I2C, CKEN); -#endif -} - -void reset_cpu(ulong ignored) __attribute__((noreturn)); - -void reset_cpu(ulong ignored) -{ - uint32_t tmp; - - setbits_le32(OWER, OWER_WME); - - tmp = readl(OSCR); - tmp += 0x1000; - writel(tmp, OSMR3); - - for (;;) - ; -} diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c new file mode 100644 index 0000000..e7b475d --- /dev/null +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -0,0 +1,301 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/* Flush I/D-cache */ +static void cache_flush(void) +{ + unsigned long i = 0; + + asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i)); +} + +int cleanup_before_linux(void) +{ + /* + * This function is called just before we call Linux. It prepares + * the processor for Linux by just disabling everything that can + * disturb booting Linux. + */ + + disable_interrupts(); + icache_disable(); + dcache_disable(); + cache_flush(); + + return 0; +} + +void pxa_wait_ticks(int ticks) +{ + writel(0, OSCR); + while (readl(OSCR) < ticks) + asm volatile("" : : : "memory"); +} + +inline void writelrb(uint32_t val, uint32_t addr) +{ + writel(val, addr); + asm volatile("" : : : "memory"); + readl(addr); + asm volatile("" : : : "memory"); +} + +void pxa_dram_init(void) +{ + uint32_t tmp; + int i; + /* + * 1) Initialize Asynchronous static memory controller + */ + + writelrb(CONFIG_SYS_MSC0_VAL, MSC0); + writelrb(CONFIG_SYS_MSC1_VAL, MSC1); + writelrb(CONFIG_SYS_MSC2_VAL, MSC2); + /* + * 2) Initialize Card Interface + */ + + /* MECR: Memory Expansion Card Register */ + writelrb(CONFIG_SYS_MECR_VAL, MECR); + /* MCMEM0: Card Interface slot 0 timing */ + writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0); + /* MCMEM1: Card Interface slot 1 timing */ + writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1); + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0); + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1); + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0); + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1); + + /* + * 3) Configure Fly-By DMA register + */ + + writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG); + + /* + * 4) Initialize Timing for Sync Memory (SDCLK0) + */ + + /* + * Before accessing MDREFR we need a valid DRI field, so we set + * this to power on defaults + DRI field. + */ + + /* Read current MDREFR config and zero out DRI */ + tmp = readl(MDREFR) & ~0xfff; + /* Add user-specified DRI */ + tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff; + /* Configure important bits */ + tmp |= MDREFR_K0RUN | MDREFR_SLFRSH; + tmp &= ~(MDREFR_APD | MDREFR_E1PIN); + + /* Write MDREFR back */ + writelrb(tmp, MDREFR); + + /* + * 5) Initialize Synchronous Static Memory (Flash/Peripherals) + */ + + /* Initialize SXCNFG register. Assert the enable bits. + * + * Write SXMRS to cause an MRS command to all enabled banks of + * synchronous static memory. Note that SXLCR need not be written + * at this time. + */ + writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG); + + /* + * 6) Initialize SDRAM + */ + + writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR); + writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR); + + /* + * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure + * but not enable each SDRAM partition pair. + */ + + writelrb(CONFIG_SYS_MDCNFG_VAL & + ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG); + /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */ + pxa_wait_ticks(0x300); + + /* + * 8) Trigger a number (usually 8) refresh cycles by attempting + * non-burst read or write accesses to disabled SDRAM, as commonly + * specified in the power up sequence documented in SDRAM data + * sheets. The address(es) used for this purpose must not be + * cacheable. + */ + for (i = 9; i >= 0; i--) { + writel(i, 0xa0000000); + asm volatile("" : : : "memory"); + } + /* + * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). + */ + + tmp = CONFIG_SYS_MDCNFG_VAL & + (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3); + tmp |= readl(MDCNFG); + writelrb(tmp, MDCNFG); + + /* + * 10) Write MDMRS. + */ + + writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS); + + /* + * 11) Enable APD + */ + + if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) { + tmp = readl(MDREFR); + tmp |= MDREFR_APD; + writelrb(tmp, MDREFR); + } +} + +void pxa_gpio_setup(void) +{ + writel(CONFIG_SYS_GPSR0_VAL, GPSR0); + writel(CONFIG_SYS_GPSR1_VAL, GPSR1); + writel(CONFIG_SYS_GPSR2_VAL, GPSR2); +#if defined(CONFIG_CPU_PXA27X) + writel(CONFIG_SYS_GPSR3_VAL, GPSR3); +#endif + + writel(CONFIG_SYS_GPCR0_VAL, GPCR0); + writel(CONFIG_SYS_GPCR1_VAL, GPCR1); + writel(CONFIG_SYS_GPCR2_VAL, GPCR2); +#if defined(CONFIG_CPU_PXA27X) + writel(CONFIG_SYS_GPCR3_VAL, GPCR3); +#endif + + writel(CONFIG_SYS_GPDR0_VAL, GPDR0); + writel(CONFIG_SYS_GPDR1_VAL, GPDR1); + writel(CONFIG_SYS_GPDR2_VAL, GPDR2); +#if defined(CONFIG_CPU_PXA27X) + writel(CONFIG_SYS_GPDR3_VAL, GPDR3); +#endif + + writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L); + writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U); + writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L); + writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U); + writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L); + writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U); +#if defined(CONFIG_CPU_PXA27X) + writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L); + writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U); +#endif + + writel(CONFIG_SYS_PSSR_VAL, PSSR); +} + +void pxa_interrupt_setup(void) +{ + writel(0, ICLR); + writel(0, ICMR); +#if defined(CONFIG_CPU_PXA27X) + writel(0, ICLR2); + writel(0, ICMR2); +#endif +} + +void pxa_clock_setup(void) +{ + writel(CONFIG_SYS_CKEN, CKEN); + writel(CONFIG_SYS_CCCR, CCCR); + asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(2)); + + /* enable the 32Khz oscillator for RTC and PowerManager */ + writel(OSCC_OON, OSCC); + while (!(readl(OSCC) & OSCC_OOK)) + asm volatile("" : : : "memory"); +} + +void pxa_wakeup(void) +{ + uint32_t rcsr; + + rcsr = readl(RCSR); + writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR); + + /* Wakeup */ + if (rcsr & RCSR_SMR) { + writel(PSSR_PH, PSSR); + pxa_dram_init(); + icache_disable(); + dcache_disable(); + asm volatile("mov pc, %0" : : "r"(readl(PSPR))); + } +} + +int arch_cpu_init(void) +{ + pxa_gpio_setup(); + pxa_wakeup(); + pxa_interrupt_setup(); + pxa_clock_setup(); + return 0; +} + +void i2c_clk_enable(void) +{ + /* Set the global I2C clock on */ + writel(readl(CKEN) | CKEN14_I2C, CKEN); +} + +void reset_cpu(ulong ignored) __attribute__((noreturn)); + +void reset_cpu(ulong ignored) +{ + uint32_t tmp; + + setbits_le32(OWER, OWER_WME); + + tmp = readl(OSCR); + tmp += 0x1000; + writel(tmp, OSMR3); + + for (;;) + ; +} -- cgit v0.10.2 From e8de0fa89656a03d1ecc90cbee4b8a897d268c7e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Nov 2011 08:11:32 +0100 Subject: PXA: Add cpuinfo display for PXA2xx Signed-off-by: Marek Vasut diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile index 29dc637..e088832 100644 --- a/arch/arm/cpu/pxa/Makefile +++ b/arch/arm/cpu/pxa/Makefile @@ -30,6 +30,8 @@ START = start.o COBJS-$(CONFIG_CPU_PXA25X) = pxa2xx.o COBJS-$(CONFIG_CPU_PXA27X) = pxa2xx.o +COBJS-y += cpuinfo.o + COBJS = $(COBJS-y) COBJS += pxafb.o COBJS += timer.o diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c new file mode 100644 index 0000000..f1cdd40 --- /dev/null +++ b/arch/arm/cpu/pxa/cpuinfo.c @@ -0,0 +1,132 @@ +/* + * PXA CPU information display + * + * Copyright (C) 2011 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define CPU_MASK_PXA_REVID 0x00f + +#define CPU_MASK_PXA_PRODID 0x3f0 +#define CPU_VALUE_PXA25X 0x100 +#define CPU_VALUE_PXA27X 0x110 + +static uint32_t pxa_get_cpuid(void) +{ + uint32_t cpuid; + asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid)); + return cpuid; +} + +int cpu_is_pxa25x(void) +{ + uint32_t id = pxa_get_cpuid(); + id &= CPU_MASK_PXA_PRODID; + return id == CPU_VALUE_PXA25X; +} + +int cpu_is_pxa27x(void) +{ + uint32_t id = pxa_get_cpuid(); + id &= CPU_MASK_PXA_PRODID; + return id == CPU_VALUE_PXA27X; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +static const char *pxa25x_get_revision(void) +{ + static __maybe_unused const char * const revs_25x[] = { "A0" }; + static __maybe_unused const char * const revs_26x[] = { + "A0", "B0", "B1" + }; + static const char *unknown = "Unknown"; + uint32_t id; + + if (!cpu_is_pxa25x()) + return unknown; + + id = pxa_get_cpuid() & CPU_MASK_PXA_REVID; + +/* PXA26x is a sick special case as it can't be told apart from PXA25x :-( */ +#ifdef CONFIG_CPU_PXA26X + switch (id) { + case 3: return revs_26x[0]; + case 5: return revs_26x[1]; + case 6: return revs_26x[2]; + } +#else + if (id == 6) + return revs_25x[0]; +#endif + return unknown; +} + +static const char *pxa27x_get_revision(void) +{ + static const char *const rev[] = { "A0", "A1", "B0", "B1", "C0", "C5" }; + static const char *unknown = "Unknown"; + uint32_t id; + + if (!cpu_is_pxa27x()) + return unknown; + + id = pxa_get_cpuid() & CPU_MASK_PXA_REVID; + + if ((id == 5) || (id == 6) || (id > 7)) + return unknown; + + /* Cap the special PXA270 C5 case. */ + if (id == 7) + id = 5; + + return rev[id]; +} + +static int print_cpuinfo_pxa2xx(void) +{ + if (cpu_is_pxa25x()) { + puts("Marvell PXA25x rev. "); + puts(pxa25x_get_revision()); + } else if (cpu_is_pxa27x()) { + puts("Marvell PXA27x rev. "); + puts(pxa27x_get_revision()); + } else + return -EINVAL; + + puts("\n"); + + return 0; +} + +int print_cpuinfo(void) +{ + int ret; + + puts("CPU: "); + + ret = print_cpuinfo_pxa2xx(); + if (!ret) + return ret; + + return ret; +} +#endif -- cgit v0.10.2 From d1bb9443f06740ab4a7a4a5c37f90e3acf5a1c5c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Nov 2011 10:02:41 +0100 Subject: PXA: Replace timer driver This new timer driver shall conform to new Timer API. Signed-off-by: Marek Vasut diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c index 0ad64dd..b7b0da9 100644 --- a/arch/arm/cpu/pxa/timer.c +++ b/arch/arm/cpu/pxa/timer.c @@ -1,11 +1,7 @@ /* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger + * Marvell PXA2xx/3xx timer driver * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke + * Copyright (C) 2011 Marek Vasut * * See file CREDITS for list of people who contributed to this * project. @@ -31,55 +27,63 @@ #include #include -#ifdef CONFIG_USE_IRQ -#error: interrupts not implemented yet -#endif +DECLARE_GLOBAL_DATA_PTR; + +#define TIMER_LOAD_VAL 0xffffffff + +#define timestamp (gd->tbl) +#define lastinc (gd->lastinc) #if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define TIMER_FREQ_HZ 3250000 +#define TIMER_FREQ_HZ 3250000 #elif defined(CONFIG_CPU_PXA25X) -#define TIMER_FREQ_HZ 3686400 +#define TIMER_FREQ_HZ 3686400 #else #error "Timer frequency unknown - please config PXA CPU type" #endif -static inline unsigned long long tick_to_time(unsigned long long tick) +static unsigned long long tick_to_time(unsigned long long tick) { - tick *= CONFIG_SYS_HZ; - do_div(tick, TIMER_FREQ_HZ); - return tick; + return tick * CONFIG_SYS_HZ / TIMER_FREQ_HZ; } -static inline unsigned long long us_to_tick(unsigned long long us) +static unsigned long long us_to_tick(unsigned long long us) { - us = us * TIMER_FREQ_HZ + 999999; - do_div(us, 1000000); - return us; + return (us * TIMER_FREQ_HZ) / 1000000; } -int timer_init (void) +int timer_init(void) { writel(0, OSCR); - return 0; } -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void __udelay (unsigned long usec) +unsigned long long get_ticks(void) { - udelay_masked (usec); + /* Current tick value */ + uint32_t now = readl(OSCR); + + if (now >= lastinc) { + /* + * Normal mode (non roll) + * Move stamp forward with absolute diff ticks + */ + timestamp += (now - lastinc); + } else { + /* We have rollover of incrementer */ + timestamp += (TIMER_LOAD_VAL - lastinc) + now; + } + + lastinc = now; + return timestamp; } -ulong get_timer_masked (void) +ulong get_timer(ulong base) { - return tick_to_time(get_ticks()); + return tick_to_time(get_ticks()) - base; } -void udelay_masked (unsigned long usec) +void __udelay(unsigned long usec) { unsigned long long tmp; ulong tmo; @@ -89,25 +93,4 @@ void udelay_masked (unsigned long usec) while (get_ticks() < tmp) /* loop till event */ /*NOP*/; - -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return readl(OSCR); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - tbclk = TIMER_FREQ_HZ; - return tbclk; } -- cgit v0.10.2 From f9f5486c743db65e7e6583db39dd72e14d8d0f22 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Nov 2011 07:15:36 +0100 Subject: PXA: Cleanup Colibri PXA270 Signed-off-by: Marek Vasut diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c index 191fb33..42b541c 100644 --- a/board/colibri_pxa270/colibri_pxa270.c +++ b/board/colibri_pxa270/colibri_pxa270.c @@ -21,26 +21,19 @@ #include #include +#include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations - */ -extern struct serial_device serial_ffuart_device; -extern struct serial_device serial_btuart_device; -extern struct serial_device serial_stuart_device; - -struct serial_device *default_serial_console (void) +struct serial_device *default_serial_console(void) { return &serial_ffuart_device; } -int board_init (void) +int board_init(void) { /* We have RAM, disable cache */ dcache_disable(); @@ -63,12 +56,6 @@ int dram_init(void) return 0; } -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - #ifdef CONFIG_CMD_USB int usb_board_init(void) { @@ -78,7 +65,8 @@ int usb_board_init(void) writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - while (UHCHR & UHCHR_FSBIR); + while (UHCHR & UHCHR_FSBIR) + ; writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); @@ -126,3 +114,11 @@ int board_eth_init(bd_t *bis) return dm9000_initialize(bis); } #endif + +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 819c5d0..cde84ec 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -26,20 +26,16 @@ * High Level Board Configuration Options */ #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ -#define CONFIG_VPAC270 1 /* Toradex Colibri PXA270 board */ +#define CONFIG_SYS_TEXT_BASE 0x0 -#undef CONFIG_BOARD_LATE_INIT -#undef CONFIG_USE_IRQ -#undef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_DISPLAY_CPUINFO /* * Environment settings */ -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) -#define CONFIG_SYS_TEXT_BASE 0x0 -#define CONFIG_ENV_OVERWRITE /* override default environment */ - +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) +#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ "if mmc init && fatload mmc 0 0xa0000000 uImage; then " \ "bootm 0xa0000000; " \ @@ -53,8 +49,8 @@ #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS - #define CONFIG_LZMA /* LZMA compression support */ +#define CONFIG_OF_LIBFDT /* * Serial Console Configuration @@ -101,9 +97,11 @@ */ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC -#define CONFIG_PXA_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC #define CONFIG_SYS_MMC_BASE 0xF0000000 #define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 #define CONFIG_DOS_PARTITION #endif @@ -121,34 +119,37 @@ #define CONFIG_SYS_HUSH_PARSER 1 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LONGHELP #ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "$ " #else -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "=> " #endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_DEVICE_NULLDEV 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE 1 + /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ -#define CONFIG_SYS_CPUSPEED 0x290 /* 520 MHz */ +#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ /* * Stack sizes * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ #endif /* @@ -164,10 +165,9 @@ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR (0xa1000000) - +#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 /* * NOR FLASH @@ -182,8 +182,8 @@ #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) #define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 #define CONFIG_SYS_FLASH_PROTECTION 1 @@ -195,14 +195,15 @@ #define CONFIG_SYS_ENV_IS_NOWHERE #endif -#define CONFIG_SYS_MONITOR_BASE 0x000000 -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#define CONFIG_SYS_MONITOR_BASE 0x0 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x40000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) /* * GPIO settings -- cgit v0.10.2 From 77b04c578c161840c9fd696ef66cf84f165838f8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Nov 2011 11:17:09 +0100 Subject: PXA: Export cpu_is_ and pxa_dram_init functions Signed-off-by: Marek Vasut diff --git a/arch/arm/include/asm/arch-pxa/pxa.h b/arch/arm/include/asm/arch-pxa/pxa.h new file mode 100644 index 0000000..050b3cd --- /dev/null +++ b/arch/arm/include/asm/arch-pxa/pxa.h @@ -0,0 +1,29 @@ +/* + * PXA common functions + * + * Copyright (C) 2011 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __PXA_H__ +#define __PXA_H__ + +int cpu_is_pxa25x(void); +int cpu_is_pxa27x(void); +void pxa_dram_init(void); + +#endif /* __PXA_H__ */ -- cgit v0.10.2 From 4438a45f4d6abd4b65998dd76528c4705b93b4b5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Nov 2011 11:17:32 +0100 Subject: PXA: Squash extern pxa_dram_init() Signed-off-by: Marek Vasut diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c index 26e34e9..ebee5e1 100644 --- a/board/balloon3/balloon3.c +++ b/board/balloon3/balloon3.c @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -57,7 +58,6 @@ struct serial_device *default_serial_console(void) return &serial_stuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { pxa_dram_init(); diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c index 42b541c..06f970b 100644 --- a/board/colibri_pxa270/colibri_pxa270.c +++ b/board/colibri_pxa270/colibri_pxa270.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -48,7 +49,6 @@ int board_init(void) return 0; } -extern void pxa_dram_init(void); int dram_init(void) { pxa_dram_init(); diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c index f791c5b..e9e6bda 100644 --- a/board/lubbock/lubbock.c +++ b/board/lubbock/lubbock.c @@ -27,6 +27,7 @@ #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -56,7 +57,6 @@ int board_late_init(void) return 0; } -extern void pxa_dram_init(void); int dram_init(void) { pxa_dram_init(); diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c index 5588fe7..65bde83 100644 --- a/board/palmld/palmld.c +++ b/board/palmld/palmld.c @@ -23,6 +23,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -56,7 +57,6 @@ struct serial_device *default_serial_console(void) return &serial_ffuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { pxa_dram_init(); diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c index 25186ae..414562b 100644 --- a/board/palmtc/palmtc.c +++ b/board/palmtc/palmtc.c @@ -23,6 +23,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -55,7 +56,6 @@ struct serial_device *default_serial_console(void) return &serial_ffuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { pxa_dram_init(); diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c index 804d09c..7b975f6 100644 --- a/board/pxa255_idp/pxa_idp.c +++ b/board/pxa255_idp/pxa_idp.c @@ -34,6 +34,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -83,7 +84,6 @@ int board_late_init(void) return 0; } -extern void pxa_dram_init(void); int dram_init(void) { pxa_dram_init(); diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c index 99f665b..008cdd8 100644 --- a/board/trizepsiv/conxs.c +++ b/board/trizepsiv/conxs.c @@ -33,6 +33,7 @@ #include #include +#include #include #include @@ -139,7 +140,6 @@ struct serial_device *default_serial_console (void) return &serial_ffuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { pxa_dram_init(); diff --git a/board/vpac270/onenand.c b/board/vpac270/onenand.c index 6a0a37b..dceb5b7 100644 --- a/board/vpac270/onenand.c +++ b/board/vpac270/onenand.c @@ -26,8 +26,7 @@ #include #include #include - -extern void pxa_dram_init(void); +#include void board_init_f(unsigned long unused) { diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index d90a859..bd2f241 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -54,7 +55,6 @@ struct serial_device *default_serial_console(void) return &serial_ffuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { #ifndef CONFIG_ONENAND diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c index 40b0f3b..9cc64bb 100644 --- a/board/xaeniax/xaeniax.c +++ b/board/xaeniax/xaeniax.c @@ -30,6 +30,7 @@ #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -59,7 +60,6 @@ int board_late_init(void) return 0; } -extern void pxa_dram_init(void); int dram_init(void) { pxa_dram_init(); diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c index 9e6a0d5..e72a5d9 100644 --- a/board/zipitz2/zipitz2.c +++ b/board/zipitz2/zipitz2.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -65,7 +66,6 @@ struct serial_device *default_serial_console (void) return &serial_stuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { pxa_dram_init(); -- cgit v0.10.2 From f68d2a222f0c37e281d28888add34ae263be6777 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Nov 2011 11:18:57 +0100 Subject: PXA: Rename pxa_dram_init to pxa2xx_dram_init Signed-off-by: Marek Vasut diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index e7b475d..09e8177 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -71,7 +71,7 @@ inline void writelrb(uint32_t val, uint32_t addr) asm volatile("" : : : "memory"); } -void pxa_dram_init(void) +void pxa2xx_dram_init(void) { uint32_t tmp; int i; @@ -262,7 +262,7 @@ void pxa_wakeup(void) /* Wakeup */ if (rcsr & RCSR_SMR) { writel(PSSR_PH, PSSR); - pxa_dram_init(); + pxa2xx_dram_init(); icache_disable(); dcache_disable(); asm volatile("mov pc, %0" : : "r"(readl(PSPR))); diff --git a/arch/arm/include/asm/arch-pxa/pxa.h b/arch/arm/include/asm/arch-pxa/pxa.h index 050b3cd..49c6552 100644 --- a/arch/arm/include/asm/arch-pxa/pxa.h +++ b/arch/arm/include/asm/arch-pxa/pxa.h @@ -24,6 +24,6 @@ int cpu_is_pxa25x(void); int cpu_is_pxa27x(void); -void pxa_dram_init(void); +void pxa2xx_dram_init(void); #endif /* __PXA_H__ */ diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c index ebee5e1..f360323 100644 --- a/board/balloon3/balloon3.c +++ b/board/balloon3/balloon3.c @@ -60,7 +60,7 @@ struct serial_device *default_serial_console(void) int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c index 06f970b..d72e5d6 100644 --- a/board/colibri_pxa270/colibri_pxa270.c +++ b/board/colibri_pxa270/colibri_pxa270.c @@ -51,7 +51,7 @@ int board_init(void) int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c index e9e6bda..437f944 100644 --- a/board/lubbock/lubbock.c +++ b/board/lubbock/lubbock.c @@ -59,7 +59,7 @@ int board_late_init(void) int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c index 65bde83..2f1ad20 100644 --- a/board/palmld/palmld.c +++ b/board/palmld/palmld.c @@ -59,7 +59,7 @@ struct serial_device *default_serial_console(void) int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c index 414562b..4adf152 100644 --- a/board/palmtc/palmtc.c +++ b/board/palmtc/palmtc.c @@ -58,7 +58,7 @@ struct serial_device *default_serial_console(void) int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c index 7b975f6..877e8d9 100644 --- a/board/pxa255_idp/pxa_idp.c +++ b/board/pxa255_idp/pxa_idp.c @@ -86,7 +86,7 @@ int board_late_init(void) int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c index 008cdd8..1291195 100644 --- a/board/trizepsiv/conxs.c +++ b/board/trizepsiv/conxs.c @@ -142,7 +142,7 @@ struct serial_device *default_serial_console (void) int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/vpac270/onenand.c b/board/vpac270/onenand.c index dceb5b7..c2ae9a7 100644 --- a/board/vpac270/onenand.c +++ b/board/vpac270/onenand.c @@ -45,7 +45,7 @@ void board_init_f(unsigned long unused) /* Hereby, the code runs from (S)RAM, copy U-Boot and execute it. */ arch_cpu_init(); - pxa_dram_init(); + pxa2xx_dram_init(); onenand_spl_load_image(CONFIG_SPL_ONENAND_LOAD_ADDR, CONFIG_SPL_ONENAND_LOAD_SIZE, (void *)CONFIG_SYS_TEXT_BASE); diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index bd2f241..dfdab9b 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -58,7 +58,7 @@ struct serial_device *default_serial_console(void) int dram_init(void) { #ifndef CONFIG_ONENAND - pxa_dram_init(); + pxa2xx_dram_init(); #endif gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c index 9cc64bb..a4acf6c 100644 --- a/board/xaeniax/xaeniax.c +++ b/board/xaeniax/xaeniax.c @@ -62,7 +62,7 @@ int board_late_init(void) int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c index e72a5d9..b093c2f 100644 --- a/board/zipitz2/zipitz2.c +++ b/board/zipitz2/zipitz2.c @@ -68,7 +68,7 @@ struct serial_device *default_serial_console (void) int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } -- cgit v0.10.2 From cd0f3d2eb8abdd475cbc8a0d3ddfd2403b92af30 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Nov 2011 11:27:30 +0100 Subject: PXA: Introduce common configuration header for PXA Signed-off-by: Marek Vasut diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h new file mode 100644 index 0000000..e8ddda6 --- /dev/null +++ b/include/configs/pxa-common.h @@ -0,0 +1,60 @@ +/* + * Toradex Colibri PXA270 configuration file + * + * Copyright (C) 2010 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_PXA_COMMON_H__ +#define __CONFIG_PXA_COMMON_H__ + +#define CONFIG_DISPLAY_CPUINFO + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 +#define CONFIG_KGDB_SER_INDEX 2 +#endif + +/* + * MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#endif + +/* + * OHCI USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_BOARD_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4c000000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "pxa-ohci" +#define CONFIG_USB_STORAGE +#endif + +#endif /* __CONFIG_PXA_COMMON_H__ */ -- cgit v0.10.2 From 67a1f00c7c4bd485b28041c9cc1289af0a9f1df7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Nov 2011 11:27:50 +0100 Subject: PXA: Flip colibri_pxa27x to pxa-common.h Signed-off-by: Marek Vasut diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index cde84ec..7691fb3 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -28,8 +28,6 @@ #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ #define CONFIG_SYS_TEXT_BASE 0x0 -#define CONFIG_DISPLAY_CPUINFO - /* * Environment settings */ @@ -93,27 +91,6 @@ #endif /* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_DOS_PARTITION -#endif - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* * HUSH Shell Configuration */ #define CONFIG_SYS_HUSH_PARSER 1 @@ -263,17 +240,6 @@ #define CONFIG_SYS_MCIO0_VAL 0x0001430f #define CONFIG_SYS_MCIO1_VAL 0x0001430f -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "tdex270" -#define CONFIG_USB_STORAGE -#endif +#include "pxa-common.h" #endif /* __CONFIG_H */ -- cgit v0.10.2 From ef426d45cc94678eab90ebaf1b62fe0f4f0e4691 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Nov 2011 11:29:36 +0100 Subject: PXA: Move colibri_pxa270 to board/toradex/ Signed-off-by: Marek Vasut diff --git a/board/colibri_pxa270/Makefile b/board/colibri_pxa270/Makefile deleted file mode 100644 index 854b19b..0000000 --- a/board/colibri_pxa270/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# Toradex Colibri PXA270 Support -# -# Copyright (C) 2010 Marek Vasut -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := colibri_pxa270.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c deleted file mode 100644 index d72e5d6..0000000 --- a/board/colibri_pxa270/colibri_pxa270.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Toradex Colibri PXA270 Support - * - * Copyright (C) 2010 Marek Vasut - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -struct serial_device *default_serial_console(void) -{ - return &serial_ffuart_device; -} - -int board_init(void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of vpac270 */ - gd->bd->bi_arch_number = MACH_TYPE_COLIBRI; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -#ifdef CONFIG_CMD_USB -int usb_board_init(void) -{ - writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), - UHCHR); - - writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - - while (UHCHR & UHCHR_FSBIR) - ; - - writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); - writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); - - /* Clear any OTG Pin Hold */ - if (readl(PSSR) & PSSR_OTGPH) - writel(readl(PSSR) | PSSR_OTGPH, PSSR); - - writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); - writel(readl(UHCRHDA) | 0x100, UHCRHDA); - - /* Set port power control mask bits, only 3 ports. */ - writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); - - /* enable port 2 */ - writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | - UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); - - return 0; -} - -void usb_board_init_fail(void) -{ - return; -} - -void usb_board_stop(void) -{ - writel(readl(UHCHR) | UHCHR_FHR, UHCHR); - udelay(11); - writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - - writel(readl(UHCCOMS) | 1, UHCCOMS); - udelay(10); - - writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); - - return; -} -#endif - -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(bd_t *bis) -{ - return dm9000_initialize(bis); -} -#endif - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bis) -{ - pxa_mmc_register(0); - return 0; -} -#endif diff --git a/board/toradex/colibri_pxa270/Makefile b/board/toradex/colibri_pxa270/Makefile new file mode 100644 index 0000000..854b19b --- /dev/null +++ b/board/toradex/colibri_pxa270/Makefile @@ -0,0 +1,41 @@ +# +# Toradex Colibri PXA270 Support +# +# Copyright (C) 2010 Marek Vasut +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := colibri_pxa270.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c new file mode 100644 index 0000000..d72e5d6 --- /dev/null +++ b/board/toradex/colibri_pxa270/colibri_pxa270.c @@ -0,0 +1,124 @@ +/* + * Toradex Colibri PXA270 Support + * + * Copyright (C) 2010 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct serial_device *default_serial_console(void) +{ + return &serial_ffuart_device; +} + +int board_init(void) +{ + /* We have RAM, disable cache */ + dcache_disable(); + icache_disable(); + + /* arch number of vpac270 */ + gd->bd->bi_arch_number = MACH_TYPE_COLIBRI; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int dram_init(void) +{ + pxa2xx_dram_init(); + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +#ifdef CONFIG_CMD_USB +int usb_board_init(void) +{ + writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), + UHCHR); + + writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); + + while (UHCHR & UHCHR_FSBIR) + ; + + writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); + writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); + + /* Clear any OTG Pin Hold */ + if (readl(PSSR) & PSSR_OTGPH) + writel(readl(PSSR) | PSSR_OTGPH, PSSR); + + writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); + writel(readl(UHCRHDA) | 0x100, UHCRHDA); + + /* Set port power control mask bits, only 3 ports. */ + writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); + + /* enable port 2 */ + writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | + UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); + + return 0; +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); + udelay(11); + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); + + writel(readl(UHCCOMS) | 1, UHCCOMS); + udelay(10); + + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); + + return; +} +#endif + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif + +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif diff --git a/boards.cfg b/boards.cfg index 3fe96ad..77dc560 100644 --- a/boards.cfg +++ b/boards.cfg @@ -216,7 +216,7 @@ actux3 arm ixp actux4 arm ixp dvlhost arm ixp balloon3 arm pxa -colibri_pxa270 arm pxa +colibri_pxa270 arm pxa - toradex lubbock arm pxa palmld arm pxa palmtc arm pxa -- cgit v0.10.2 From 8f1da53508c78789ebeea98a92a3f55c3f84dc5d Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Wed, 30 Nov 2011 22:27:37 +0000 Subject: arm, arm926ejs: Fix clear bss loop for zero length bss This patch fixes the clear bss loop for bss sections that have zero length, i.e., where __bss_start == __bss_end__. Signed-off-by: Christian Riesch Cc: Albert Aribaud diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 339c5ed..bb4d00b 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -301,10 +301,12 @@ clear_bss: #endif mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - bne clbss_l + b clbss_l +clbss_e: #ifndef CONFIG_SPL_BUILD bl coloured_LED_init -- cgit v0.10.2 From dc7100f4080952798413fb63bb4134b22c57623a Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Mon, 21 Nov 2011 23:33:58 +0000 Subject: armv7: disable L2 cache in cleanup_before_linux() We were not disabling external caches before jumping to kernel. We were flushing all caches including external caches and disabling caches globally in CP15 System Control register. Apparently this is not enough. The bootstrap loader in Linux kernel that does decompression enables data-caches again, flush them after use and disable them before jumping to kernel proper. However, it's not aware of the external caches. Since we have left external cache enabled, external cache will get used once caches are enabled globally, but it's not flushed because decompressor is not aware of external caches. When it jumps to kernel with caches disabled globally, we have stale data in the external cache and a coherency problem. This was breaking the boot for OMAP4 with latest mainline kernel. The solution is to disable external caches in cleanup_before_linux(). With this fix kernel is booting again. Cc: Albert Aribaud Signed-off-by: Aneesh V diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index 091e3e0..662c496 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -65,6 +65,7 @@ int cleanup_before_linux(void) * dcache_disable() in turn flushes the d-cache and disables MMU */ dcache_disable(); + v7_outer_cache_disable(); /* * After D-cache is flushed and before it is disabled there may -- cgit v0.10.2 From 87d3da7b01ee083447f9fcc62f35427d5fde2e2f Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Mon, 21 Nov 2011 23:33:59 +0000 Subject: armv7: include armv7/cpu.c in SPL build This allows SPL to have default implementation of save_boot_params(), useful for SoCs that do not intend to override this default implementation Cc: Albert Aribaud Signed-off-by: Aneesh V diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 92a5a96..f97fa3d 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -29,10 +29,10 @@ START := start.o ifndef CONFIG_SPL_BUILD COBJS += cache_v7.o -COBJS += cpu.o endif -COBJS += syslib.o +COBJS += cpu.o +COBJS += syslib.o SRCS := $(START:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -- cgit v0.10.2 From a8c686399f01c359713447c2adaecf94f3a4445b Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Mon, 21 Nov 2011 23:34:00 +0000 Subject: armv7: setup vector The vector is not correctly setup in armv7 except for OMAP3. Correcting this. Cc: Albert Aribaud Signed-off-by: Aneesh V diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index db8e9d2..f17763f 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -32,6 +32,7 @@ #include #include #include +#include .globl _start _start: b reset @@ -143,6 +144,22 @@ reset: orr r0, r0, #0xd3 msr cpsr,r0 +/* + * Setup vector: + * (OMAP4 spl TEXT_BASE is not 32 byte aligned. + * Continue to use ROM code vector only in OMAP4 spl) + */ +#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) + /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ + mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register + bic r0, #CR_V @ V = 0 + mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register + + /* Set vector address in CP15 VBAR register */ + ldr r0, =_start + mcr p15, 0, r0, c12, c0, 0 @Set VBAR +#endif + #if defined(CONFIG_OMAP34XX) /* Copy vectors to mask ROM indirect addr */ adr r0, _start @ r0 <- current position of code -- cgit v0.10.2 From e4fce34e7a5f484de2ca557fd43a198fd14894b7 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Mon, 21 Nov 2011 23:34:01 +0000 Subject: start.S: remove omap3 specific code from start.S Cc: Tom Rini Cc: Albert Aribaud Signed-off-by: Aneesh V Acked-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index a308ebd..2f6930b 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -216,6 +216,14 @@ lowlevel_init: ldr sp, SRAM_STACK str ip, [sp] /* stash old link register */ mov ip, lr /* save link reg across call */ +#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) +/* + * No need to copy/exec the clock code - DPLL adjust already done + * in NAND/oneNAND Boot. + */ + ldr r1, =SRAM_CLK_CODE + bl cpy_clk_code +#endif /* NAND Boot */ bl s_init /* go setup pll, mux, memory */ ldr ip, [sp] /* restore save ip */ mov lr, ip /* restore link reg */ diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index f17763f..d23dc9d 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -160,29 +160,6 @@ reset: mcr p15, 0, r0, c12, c0, 0 @Set VBAR #endif -#if defined(CONFIG_OMAP34XX) - /* Copy vectors to mask ROM indirect addr */ - adr r0, _start @ r0 <- current position of code - add r0, r0, #4 @ skip reset vector - mov r2, #64 @ r2 <- size to copy - add r2, r0, r2 @ r2 <- source end address - mov r1, #SRAM_OFFSET0 @ build vect addr - mov r3, #SRAM_OFFSET1 - add r1, r1, r3 - mov r3, #SRAM_OFFSET2 - add r1, r1, r3 -next: - ldmia r0!, {r3 - r10} @ copy from source address [r0] - stmia r1!, {r3 - r10} @ copy to target address [r1] - cmp r0, r2 @ until source end address [r2] - bne next @ loop until equal */ -#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) - /* No need to copy/exec the clock code - DPLL adjust already done - * in NAND/oneNAND Boot. - */ - bl cpy_clk_code @ put dpll adjust code behind vectors -#endif /* NAND Boot */ -#endif /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 02eb865..2b5e9ae 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -153,6 +153,7 @@ struct gpio { #define SRAM_OFFSET2 0x0000F800 #define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \ SRAM_OFFSET2) +#define SRAM_CLK_CODE (SRAM_VECT_CODE + 64) #define OMAP3_PUBLIC_SRAM_BASE 0x40208000 /* Works for GP & EMU */ #define OMAP3_PUBLIC_SRAM_END 0x40210000 -- cgit v0.10.2 From 28a181ff81826bfa53f42c9790cc7397ef9a2dc9 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Mon, 21 Nov 2011 23:38:57 +0000 Subject: omap: Improve PLL parameter calculation tool Improve the tool that finds multiplier and divider for PLLs: The previous algorithm could get stuck on local maxima and required the user to specify the tolerance. Improve the algorithm to go through the entire search space and find the optimal solution. Signed-off-by: Aneesh V diff --git a/tools/omap/clocks_get_m_n.c b/tools/omap/clocks_get_m_n.c index cfc1760..c27577b 100644 --- a/tools/omap/clocks_get_m_n.c +++ b/tools/omap/clocks_get_m_n.c @@ -63,45 +63,41 @@ typedef unsigned int u32; * $ gcc clocks_get_m_n.c * $ ./a.out */ -int get_m_n_optimized(u32 target_freq_khz, u32 ref_freq_khz, u32 *m, u32 *n, - u32 tolerance_khz) +int get_m_n_optimized(u32 target_freq_khz, u32 ref_freq_khz, u32 *M, u32 *N) { - u32 min_freq = target_freq_khz - tolerance_khz; - u32 max_freq = target_freq_khz; - u32 freq, freq_old; - *n = 1; + u32 freq = target_freq_khz; + u32 m_optimal, n_optimal, freq_optimal = 0, freq_old; + u32 m, n; + n = 1; while (1) { - *m = min_freq / ref_freq_khz / 2 * (*n) ; + m = target_freq_khz / ref_freq_khz / 2 * n; freq_old = 0; while (1) { - freq = ref_freq_khz * 2 * (*m) / (*n); - if (abs(target_freq_khz - freq_old) <= - abs(target_freq_khz - freq)) { + freq = ref_freq_khz * 2 * m / n; + if (freq > target_freq_khz) { freq = freq_old; - (*m)--; + m--; break; } - (*m)++; + m++; freq_old = freq; } - if (freq >= min_freq && freq <= max_freq) + if (freq > freq_optimal) { + freq_optimal = freq; + m_optimal = m; + n_optimal = n; + } + n++; + if ((freq_optimal == target_freq_khz) || + ((ref_freq_khz / n) < 1000)) { break; - (*n)++; - if ((*n) > MAX_N + 1) { - printf("ref %d m %d n %d target %d : ", - ref_freq_khz, *m, *n, target_freq_khz); - printf("can not find m & n - please consider" - " increasing tolerance\n"); - return -1; } } - (*n)--; - printf("ref %d m %d n %d target %d locked %d\n", - ref_freq_khz, *m, *n, target_freq_khz, freq); - if ((ref_freq_khz / (*n + 1)) < 1000) { - printf("\tREFCLK - CLKINP/(N+1) is less than 1 MHz - less than" - " ideal, locking time will be high!\n"); - } + n--; + *M = m_optimal; + *N = n_optimal - 1; + printf("ref %d m %d n %d target %d locked %d\n", ref_freq_khz, + m_optimal, n_optimal - 1, target_freq_khz, freq_optimal); return 0; } @@ -109,89 +105,98 @@ void main(void) { u32 m, n; printf("\nMPU - 2000000\n"); - get_m_n_optimized(2000000, 12000, &m, &n, 0); - get_m_n_optimized(2000000, 13000, &m, &n, 0); - get_m_n_optimized(2000000, 16800, &m, &n, 800); - get_m_n_optimized(2000000, 19200, &m, &n, 0); - get_m_n_optimized(2000000, 26000, &m, &n, 0); - get_m_n_optimized(2000000, 27000, &m, &n, 0); - get_m_n_optimized(2000000, 38400, &m, &n, 0); + get_m_n_optimized(2000000, 12000, &m, &n); + get_m_n_optimized(2000000, 13000, &m, &n); + get_m_n_optimized(2000000, 16800, &m, &n); + get_m_n_optimized(2000000, 19200, &m, &n); + get_m_n_optimized(2000000, 26000, &m, &n); + get_m_n_optimized(2000000, 27000, &m, &n); + get_m_n_optimized(2000000, 38400, &m, &n); printf("\nMPU - 1200000\n"); - get_m_n_optimized(1200000, 12000, &m, &n, 0); - get_m_n_optimized(1200000, 13000, &m, &n, 0); - get_m_n_optimized(1200000, 16800, &m, &n, 800); - get_m_n_optimized(1200000, 19200, &m, &n, 0); - get_m_n_optimized(1200000, 26000, &m, &n, 0); - get_m_n_optimized(1200000, 27000, &m, &n, 0); - get_m_n_optimized(1200000, 38400, &m, &n, 0); + get_m_n_optimized(1200000, 12000, &m, &n); + get_m_n_optimized(1200000, 13000, &m, &n); + get_m_n_optimized(1200000, 16800, &m, &n); + get_m_n_optimized(1200000, 19200, &m, &n); + get_m_n_optimized(1200000, 26000, &m, &n); + get_m_n_optimized(1200000, 27000, &m, &n); + get_m_n_optimized(1200000, 38400, &m, &n); printf("\nMPU - 1584000\n"); - get_m_n_optimized(1584000, 12000, &m, &n, 0); - get_m_n_optimized(1584000, 13000, &m, &n, 0); - get_m_n_optimized(1584000, 16800, &m, &n, 400); - get_m_n_optimized(1584000, 19200, &m, &n, 0); - get_m_n_optimized(1584000, 26000, &m, &n, 0); - get_m_n_optimized(1584000, 27000, &m, &n, 0); - get_m_n_optimized(1584000, 38400, &m, &n, 0); + get_m_n_optimized(1584000, 12000, &m, &n); + get_m_n_optimized(1584000, 13000, &m, &n); + get_m_n_optimized(1584000, 16800, &m, &n); + get_m_n_optimized(1584000, 19200, &m, &n); + get_m_n_optimized(1584000, 26000, &m, &n); + get_m_n_optimized(1584000, 27000, &m, &n); + get_m_n_optimized(1584000, 38400, &m, &n); printf("\nCore 1600000\n"); - get_m_n_optimized(1600000, 12000, &m, &n, 0); - get_m_n_optimized(1600000, 13000, &m, &n, 0); - get_m_n_optimized(1600000, 16800, &m, &n, 200); - get_m_n_optimized(1600000, 19200, &m, &n, 0); - get_m_n_optimized(1600000, 26000, &m, &n, 0); - get_m_n_optimized(1600000, 27000, &m, &n, 0); - get_m_n_optimized(1600000, 38400, &m, &n, 0); + get_m_n_optimized(1600000, 12000, &m, &n); + get_m_n_optimized(1600000, 13000, &m, &n); + get_m_n_optimized(1600000, 16800, &m, &n); + get_m_n_optimized(1600000, 19200, &m, &n); + get_m_n_optimized(1600000, 26000, &m, &n); + get_m_n_optimized(1600000, 27000, &m, &n); + get_m_n_optimized(1600000, 38400, &m, &n); printf("\nPER 1536000\n"); - get_m_n_optimized(1536000, 12000, &m, &n, 0); - get_m_n_optimized(1536000, 13000, &m, &n, 0); - get_m_n_optimized(1536000, 16800, &m, &n, 0); - get_m_n_optimized(1536000, 19200, &m, &n, 0); - get_m_n_optimized(1536000, 26000, &m, &n, 0); - get_m_n_optimized(1536000, 27000, &m, &n, 0); - get_m_n_optimized(1536000, 38400, &m, &n, 0); + get_m_n_optimized(1536000, 12000, &m, &n); + get_m_n_optimized(1536000, 13000, &m, &n); + get_m_n_optimized(1536000, 16800, &m, &n); + get_m_n_optimized(1536000, 19200, &m, &n); + get_m_n_optimized(1536000, 26000, &m, &n); + get_m_n_optimized(1536000, 27000, &m, &n); + get_m_n_optimized(1536000, 38400, &m, &n); printf("\nIVA 1862000\n"); - get_m_n_optimized(1862000, 12000, &m, &n, 0); - get_m_n_optimized(1862000, 13000, &m, &n, 0); - get_m_n_optimized(1862000, 16800, &m, &n, 0); - get_m_n_optimized(1862000, 19200, &m, &n, 900); - get_m_n_optimized(1862000, 26000, &m, &n, 0); - get_m_n_optimized(1862000, 27000, &m, &n, 0); - get_m_n_optimized(1862000, 38400, &m, &n, 800); + get_m_n_optimized(1862000, 12000, &m, &n); + get_m_n_optimized(1862000, 13000, &m, &n); + get_m_n_optimized(1862000, 16800, &m, &n); + get_m_n_optimized(1862000, 19200, &m, &n); + get_m_n_optimized(1862000, 26000, &m, &n); + get_m_n_optimized(1862000, 27000, &m, &n); + get_m_n_optimized(1862000, 38400, &m, &n); + + printf("\nIVA Nitro - 1290000\n"); + get_m_n_optimized(1290000, 12000, &m, &n); + get_m_n_optimized(1290000, 13000, &m, &n); + get_m_n_optimized(1290000, 16800, &m, &n); + get_m_n_optimized(1290000, 19200, &m, &n); + get_m_n_optimized(1290000, 26000, &m, &n); + get_m_n_optimized(1290000, 27000, &m, &n); + get_m_n_optimized(1290000, 38400, &m, &n); printf("\nABE 196608 sys clk\n"); - get_m_n_optimized(196608, 12000, &m, &n, 700); - get_m_n_optimized(196608, 13000, &m, &n, 200); - get_m_n_optimized(196608, 16800, &m, &n, 700); - get_m_n_optimized(196608, 19200, &m, &n, 400); - get_m_n_optimized(196608, 26000, &m, &n, 200); - get_m_n_optimized(196608, 27000, &m, &n, 900); - get_m_n_optimized(196608, 38400, &m, &n, 0); + get_m_n_optimized(196608, 12000, &m, &n); + get_m_n_optimized(196608, 13000, &m, &n); + get_m_n_optimized(196608, 16800, &m, &n); + get_m_n_optimized(196608, 19200, &m, &n); + get_m_n_optimized(196608, 26000, &m, &n); + get_m_n_optimized(196608, 27000, &m, &n); + get_m_n_optimized(196608, 38400, &m, &n); printf("\nABE 196608 32K\n"); - get_m_n_optimized(196608000/4, 32768, &m, &n, 0); + get_m_n_optimized(196608000/4, 32768, &m, &n); printf("\nUSB 1920000\n"); - get_m_n_optimized(1920000, 12000, &m, &n, 0); - get_m_n_optimized(1920000, 13000, &m, &n, 0); - get_m_n_optimized(1920000, 16800, &m, &n, 0); - get_m_n_optimized(1920000, 19200, &m, &n, 0); - get_m_n_optimized(1920000, 26000, &m, &n, 0); - get_m_n_optimized(1920000, 27000, &m, &n, 0); - get_m_n_optimized(1920000, 38400, &m, &n, 0); + get_m_n_optimized(1920000, 12000, &m, &n); + get_m_n_optimized(1920000, 13000, &m, &n); + get_m_n_optimized(1920000, 16800, &m, &n); + get_m_n_optimized(1920000, 19200, &m, &n); + get_m_n_optimized(1920000, 26000, &m, &n); + get_m_n_optimized(1920000, 27000, &m, &n); + get_m_n_optimized(1920000, 38400, &m, &n); printf("\nCore ES1 1523712\n"); - get_m_n_optimized(1524000, 12000, &m, &n, 100); - get_m_n_optimized(1524000, 13000, &m, &n, 0); - get_m_n_optimized(1524000, 16800, &m, &n, 0); - get_m_n_optimized(1524000, 19200, &m, &n, 0); - get_m_n_optimized(1524000, 26000, &m, &n, 0); - get_m_n_optimized(1524000, 27000, &m, &n, 0); + get_m_n_optimized(1524000, 12000, &m, &n); + get_m_n_optimized(1524000, 13000, &m, &n); + get_m_n_optimized(1524000, 16800, &m, &n); + get_m_n_optimized(1524000, 19200, &m, &n); + get_m_n_optimized(1524000, 26000, &m, &n); + get_m_n_optimized(1524000, 27000, &m, &n); /* exact recommendation for SDPs */ - get_m_n_optimized(1523712, 38400, &m, &n, 0); + get_m_n_optimized(1523712, 38400, &m, &n); } -- cgit v0.10.2 From d71a4916d6ed3a60c254d800b992fc039a04c762 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Mon, 21 Nov 2011 23:38:58 +0000 Subject: omap4: ttyO2 instead of ttyS2 in default bootargs Set console=ttyO2 instead of ttyS2 in default bootargs according to latest kernel config Signed-off-by: Aneesh V diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 42a8f10..a058700 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -150,7 +150,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ - "console=ttyS2,115200n8\0" \ + "console=ttyO2,115200n8\0" \ "usbtty=cdc_acm\0" \ "vram=16M\0" \ "mmcdev=0\0" \ -- cgit v0.10.2 From 8e40852f0d60ab0b1381d43e38b31a6b3bcd6549 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Mon, 21 Nov 2011 23:38:59 +0000 Subject: omap: fix cache line size for omap3/omap4 boards Acked-by: Tom Rini Signed-off-by: Aneesh V Signed-off-by: Tom Rini diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 15e40c5..a73c8af 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -390,4 +390,6 @@ #define CONFIG_OMAP3_SPI +#define CONFIG_SYS_CACHELINE_SIZE 64 + #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 54aa7a7..e6921c5 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -289,4 +289,6 @@ /* Uncomment to define the board revision statically */ /* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + #endif /* __OMAP3_EVM_COMMON_H */ diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index a0252a2..7df75f5 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -310,4 +310,6 @@ #define CONFIG_OMAP3_SPI +#define CONFIG_SYS_CACHELINE_SIZE 64 + #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index afdefd9..b628fef 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -307,4 +307,6 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_CACHELINE_SIZE 64 + #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 3c2793e..af2bf80 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -278,4 +278,6 @@ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET +#define CONFIG_SYS_CACHELINE_SIZE 64 + #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 35472bb..8e9ac53 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -358,4 +358,6 @@ * - rest for filesystem */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index fbac222..a01dc74 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -303,4 +303,6 @@ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET +#define CONFIG_SYS_CACHELINE_SIZE 64 + #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 8de3d31..c4b6552 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -269,4 +269,6 @@ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET +#define CONFIG_SYS_CACHELINE_SIZE 64 + #endif /* __CONFIG_H */ diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index a058700..613aef2 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -239,6 +239,7 @@ #define CONFIG_SYS_L2_PL310 1 #define CONFIG_SYS_PL310_BASE 0x48242000 #endif +#define CONFIG_SYS_CACHELINE_SIZE 32 /* Defines for SDRAM init */ #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -- cgit v0.10.2 From cd5847ac3a2d561e9d02926c768fd547f418c24d Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Mon, 21 Nov 2011 23:39:00 +0000 Subject: omap4460: fix TPS initialization TPS power IC is controlled using a GPIO (gpio_wk7). This GPIO should be maintained at logic 1 always. As such an internal pull-up on this pin will do the job, driving the GPIO outuput is not needed. This will avoid the need of using GPIO library in SPL and also may save some power. Signed-off-by: Aneesh V diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index f64a10b..1e7e20e 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -359,14 +359,6 @@ void do_scale_tps62361(u32 reg, u32 volt_mv) step = volt_mv - TPS62361_BASE_VOLT_MV; step /= 10; - /* - * Select SET1 in TPS62361: - * VSEL1 is grounded on board. So the following selects - * VSEL1 = 0 and VSEL0 = 1 - */ - gpio_direction_output(TPS62361_VSEL0_GPIO, 0); - gpio_set_value(TPS62361_VSEL0_GPIO, 1); - temp = TPS62361_I2C_SLAVE_ADDR | (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) | diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index c05170e..2970ccd 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -76,7 +76,7 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { -{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7, TPS */ +{PAD1_FREF_CLK4_REQ, (PTU | M7)}, /* gpio_wk7 for TPS: safe mode + pull up */ }; diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index e1b853c..9ae9e2c 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -96,6 +96,13 @@ void set_muxconf_regs_non_essential(void) do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, sizeof(wkup_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); + + if (omap_revision() < OMAP4460_ES1_0) { + do_set_mux(CONTROL_PADCONF_WKUP, + wkup_padconf_array_non_essential_4430, + sizeof(wkup_padconf_array_non_essential_4430) / + sizeof(struct pad_conf_entry)); + } } #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 1c6e0ee..0a20968 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -67,7 +67,7 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { -{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7, TPS */ +{PAD1_FREF_CLK4_REQ, (PTU | M7)}, /* gpio_wk7 for TPS: safe mode + pull up */ }; @@ -275,4 +275,8 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = { {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ }; +const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { + {PAD1_FREF_CLK4_REQ, (M3)} /* gpio_wk7 - Debug led-2 */ +}; + #endif /* _SDP4430_MUX_DATA_H */ -- cgit v0.10.2 From 473673a5c89cfa24aee92ec5fbae30e2d5557d32 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Mon, 21 Nov 2011 23:39:01 +0000 Subject: omap: remove I2C from SPL Due to some recent changes I2C is no longer required in SPL. Remove the i2c_init() call to save some space Signed-off-by: Aneesh V diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index d6d7d65..f72d389 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -115,7 +115,6 @@ void board_init_r(gd_t *id, ulong dummy) CONFIG_SYS_SPL_MALLOC_SIZE); timer_init(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); boot_device = omap_boot_device(); debug("boot device - %d\n", boot_device); -- cgit v0.10.2 From 4324c118a03d8b957ef249e33313b6eafb580b41 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Mon, 21 Nov 2011 23:39:02 +0000 Subject: omap4: emif: fix error in driver There was a typo in the EMIF driver. It went un-noticed because it affected only when automatic detection is enabled and even then half the memory was configured and identified properly. Reported-by: Rockefeller Signed-off-by: Aneesh V diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index ce03b5c..62678ff 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -903,9 +903,9 @@ static void do_sdram_init(u32 base) */ struct lpddr2_device_details cs0_dev_details, cs1_dev_details; emif_reset_phy(base); - dev_details.cs0_device_details = emif_get_device_details(base, CS0, + dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, &cs0_dev_details); - dev_details.cs1_device_details = emif_get_device_details(base, CS1, + dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, &cs1_dev_details); emif_reset_phy(base); -- cgit v0.10.2 From 9404758e9baf0472d6958efaa7df1aa757b237d8 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Mon, 21 Nov 2011 23:39:03 +0000 Subject: omap4460: add ES1.1 identification Signed-off-by: Aneesh V diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 52c9b19..cd1451a 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -146,7 +146,15 @@ void init_omap_revision(void) *omap4_revision = OMAP4430_ES2_3; break; case MIDR_CORTEX_A9_R2P10: - *omap4_revision = OMAP4460_ES1_0; + switch (readl(CONTROL_ID_CODE)) { + case OMAP4460_CONTROL_ID_CODE_ES1_1: + *omap4_revision = OMAP4460_ES1_1; + break; + case OMAP4460_CONTROL_ID_CODE_ES1_0: + default: + *omap4_revision = OMAP4460_ES1_0; + break; + } break; default: *omap4_revision = OMAP4430_SILICON_ID_INVALID; diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index e994257..4d8c89f 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -63,6 +63,8 @@ #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F +#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F +#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F /* UART */ #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index f1562ea..913231b 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -108,6 +108,7 @@ void spl_mmc_load_image(void); #define OMAP4430_ES2_2 0x44300220 #define OMAP4430_ES2_3 0x44300230 #define OMAP4460_ES1_0 0x44600100 +#define OMAP4460_ES1_1 0x44600110 /* omap5 */ #define OMAP5430_SILICON_ID_INVALID 0 -- cgit v0.10.2 From f6ddfdd3a92e2906c87c521deae46e509bd0bf3d Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Mon, 21 Nov 2011 23:39:04 +0000 Subject: omap4+: streamline CONFIG_SYS_TEXT_BASE and other SDRAM addresses Change the CONFIG_SYS_TEXT_BASE and the addresses of SDRAM buffers used by SPL(heap and BSS) keeping in mind the following requirements: 1. Make sure that SPL's heap and BSS doesn't come in the way of Linux kernel, which is typically loaded at 0x80008000. This will be important when SPL directly loads kernel. 2. Align the CONFIG_SYS_TEXT_BASE between TI internal U-Boot and mainline U-Boot. This avoids a lot of confusion and allows for the inter-operability of x-loader, SPL, internal U-Boot, mainline U-Boot etc. The internal U-Boot's address can not be changed to that of mainline U-Boot as internal U-Boot doesn't have relocation and 0x80100000 used by mainline U-Boot will clash with kernel 3. Assume only a minimum amount of memory that may be available on any practical OMAP4/5 board in future too. We are assuming a minimum of 128 MB of memory Signed-off-by: Aneesh V diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 613aef2..a989721 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -255,18 +255,21 @@ #define CONFIG_SPL_MAX_SIZE (38 * 1024) #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ /* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any + * header. That is 80E7FFC0--0x80E80000 should not be used for any * other needs. */ -#define CONFIG_SYS_TEXT_BASE 0x80100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_TEXT_BASE 0x80E80000 +/* + * BSS and malloc area 64MB into memory to allow enough + * space for the kernel at the beginning of memory + */ +#define CONFIG_SPL_BSS_START_ADDR 0x84000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index b763f01..d3d5263 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -254,9 +254,6 @@ #define CONFIG_SPL_MAX_SIZE 0x1E000 /* 120K */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 @@ -272,13 +269,19 @@ #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" /* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any + * header. That is 80E7FFC0--0x80E80000 should not be used for any * other needs. */ -#define CONFIG_SYS_TEXT_BASE 0x80100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_TEXT_BASE 0x80E80000 + +/* + * BSS and malloc area 64MB into memory to allow enough + * space for the kernel at the beginning of memory + */ +#define CONFIG_SPL_BSS_START_ADDR 0x84000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ #endif /* __CONFIG_H */ -- cgit v0.10.2 From 23e9f0723e48615332119de4f4ec7a833a282628 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Mon, 21 Nov 2011 23:39:05 +0000 Subject: omap4: fix IO setting The value from TRIM is not working for some 4430 silicons. So, override with hw team recommended value. However, for 4460 TRIM value shall be used as long as the part is trimmed This fixes boot problem on some OMAP4430 ES2.0 Panda boards out there. Cc: Steve Sakoman Signed-off-by: Aneesh V diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index cd1451a..37a86b4 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -105,7 +105,12 @@ void do_io_settings(void) &ctrl->control_ldosram_core_voltage_ctrl); } - if (!readl(&ctrl->control_efuse_1)) + /* + * Over-ride the register + * i. unconditionally for all 4430 + * ii. only if un-trimmed for 4460 + */ + if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_1)) writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1); if (!readl(&ctrl->control_efuse_2)) -- cgit v0.10.2 From 8152c6f6f538c0c3b61a9e0cd6e1c67f1bcc687a Mon Sep 17 00:00:00 2001 From: Thomas Weber Date: Sat, 26 Nov 2011 10:30:55 +0000 Subject: ARM: OMAP3: Remove unused define CONFIG_OMAP3430 This patch removes the CONFIG_OMAP3430, because it is unused. Acked-by: Enric Balletbo i Serra Acked-by: Tom Rini Acked-by: Igor Grinberg Signed-off-by: Thomas Weber Acked-by: Luca Ceresoli diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 026d222..eca7dec 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -38,7 +38,6 @@ */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_CM_T3X 1 /* working with CM-T35 and CM-T3730 */ #define CONFIG_SYS_TEXT_BASE 0x80008000 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index e1743dc..353e09f 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -34,7 +34,6 @@ /* High Level Configuration Options */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ #define CONFIG_SYS_TEXT_BASE 0x80008000 diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 9baf415..749be7e 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -45,7 +45,6 @@ */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ -#define CONFIG_OMAP3430 /* which is in a 3430 */ #define CONFIG_SYS_TEXT_BASE 0x80008000 diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h index 279a9d2..a3b58cf 100644 --- a/include/configs/igep0020.h +++ b/include/configs/igep0020.h @@ -27,7 +27,6 @@ */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_IGEP0020 1 /* working with IGEP0020 */ #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/igep0030.h b/include/configs/igep0030.h index d85e5ae..96b366b 100644 --- a/include/configs/igep0030.h +++ b/include/configs/igep0030.h @@ -27,7 +27,6 @@ */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_IGEP0030 1 /* working with IGEP0030 */ #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index a73c8af..13af584 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -33,7 +33,6 @@ */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index e6921c5..c459f94 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -22,7 +22,6 @@ */ #define CONFIG_OMAP /* This is TI OMAP core */ #define CONFIG_OMAP34XX /* belonging to 34XX family */ -#define CONFIG_OMAP3430 /* which is in a 3430 */ #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 7df75f5..f2c5309 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -37,7 +37,6 @@ #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */ #define CONFIG_MACH_TYPE MACH_TYPE_MVBLX diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index b628fef..9f01fc4 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -25,7 +25,6 @@ */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_OVERO 1 /* working with overo */ #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index af2bf80..e2fda26 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -28,7 +28,6 @@ */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 8e9ac53..d3d25ab 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -38,7 +38,6 @@ */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */ #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index a01dc74..1224c48 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -34,7 +34,6 @@ */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */ #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index c4b6552..8432ae3 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -35,7 +35,6 @@ */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */ #define CONFIG_SDRC /* The chip has SDRC controller */ -- cgit v0.10.2 From 0997561de956783ef1ac2f0acf649a0793882a3a Mon Sep 17 00:00:00 2001 From: Thomas Weber Date: Sat, 26 Nov 2011 10:30:56 +0000 Subject: ARM: OMAP3: Remove unused define SDRC_R_C_B This patch removes the unused definition of SDRC_R_C_B from the config files. Acked-by: Enric Balletbo i Serra Acked-by: Igor Grinberg Signed-off-by: Thomas Weber Acked-by: Luca Ceresoli Acked-by: Tom Rini diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 8842a18..25ce2da 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -277,9 +277,6 @@ #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - /*----------------------------------------------------------------------- * FLASH and environment organization */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 1c70b9d..87dd00f 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -276,9 +276,6 @@ #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - /*----------------------------------------------------------------------- * FLASH and environment organization */ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index eca7dec..2cba7fd 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -295,9 +295,6 @@ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - /*----------------------------------------------------------------------- * FLASH and environment organization */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 353e09f..e27e282 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -286,9 +286,6 @@ #define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - /* NAND and environment organization */ #define PISMO1_NAND_SIZE GPMC_SIZE_128M diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 749be7e..42aab27 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -281,9 +281,6 @@ #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - /*----------------------------------------------------------------------- * FLASH and environment organization */ diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h index a3b58cf..56fd6de 100644 --- a/include/configs/igep0020.h +++ b/include/configs/igep0020.h @@ -237,9 +237,6 @@ #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - /* * FLASH and environment organization */ diff --git a/include/configs/igep0030.h b/include/configs/igep0030.h index 96b366b..3634618 100644 --- a/include/configs/igep0030.h +++ b/include/configs/igep0030.h @@ -235,9 +235,6 @@ #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - /* * FLASH and environment organization */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 13af584..d280451 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -349,9 +349,6 @@ #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - /*----------------------------------------------------------------------- * FLASH and environment organization */ diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index c459f94..d11de5a 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -73,9 +73,6 @@ #define PHYS_SDRAM_1_SIZE (32 << 20) #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C - /* Limits for memtest */ #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index f2c5309..04b683e 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -269,9 +269,6 @@ #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - #define CONFIG_ENV_IS_NOWHERE 1 /*---------------------------------------------------------------------------- diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 9f01fc4..ae2247f 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -256,9 +256,6 @@ #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - /*----------------------------------------------------------------------- * FLASH and environment organization */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index e2fda26..5589342 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -240,9 +240,6 @@ #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - #define CONFIG_SYS_TEXT_BASE 0x80008000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index d3d25ab..5500ede 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -322,9 +322,6 @@ #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - /*--------------------------------------------------------------------------*/ /* diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 1224c48..fcfdfda 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -271,9 +271,6 @@ #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - /*----------------------------------------------------------------------- * FLASH and environment organization */ diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 8432ae3..3f71dca 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -239,9 +239,6 @@ #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - /*----------------------------------------------------------------------- * FLASH and environment organization */ -- cgit v0.10.2 From 81dcf8bb117db89cbdeba3b2c2a289f52c162dca Mon Sep 17 00:00:00 2001 From: Thomas Weber Date: Sat, 26 Nov 2011 10:30:57 +0000 Subject: ARM: OMAP: Remove STACKSIZE for IRQ and FIQ if unused This patch removes the definition of stack sizes for irq and fiq if the CONFIG_USE_IRQ is undefined before. Acked-by: Enric Balletbo i Serra Acked-by: Tom Rini Acked-by: Igor Grinberg Signed-off-by: Thomas Weber Acked-by: Luca Ceresoli diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 25ce2da..0a62e36 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -264,10 +264,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ -#endif /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 87dd00f..dfe186c 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -263,10 +263,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ -#endif /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/apollon.h b/include/configs/apollon.h index 46595d9..7fcf437 100644 --- a/include/configs/apollon.h +++ b/include/configs/apollon.h @@ -211,10 +211,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE SZ_128K /* regular stack */ -#ifdef CONFIG_USE_IRQ -# define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -# define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ -#endif /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 2cba7fd..a06a89d 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -283,10 +283,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ -#endif /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index e27e282..3ea4532 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -275,10 +275,6 @@ /* The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ -#endif /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index d280451..7bb56a3 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -336,10 +336,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ -#endif /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index d11de5a..d62d2ab 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -58,11 +58,6 @@ */ #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ -#endif - /* * Physical Memory Map * Note 1: CS1 may or may not be populated diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 04b683e..eb51ea9 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -256,10 +256,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ -#endif /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index ae2247f..0874716 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -243,10 +243,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ -#endif /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 5589342..1a30454 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -227,10 +227,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ -#endif /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 5500ede..90f4b90 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -303,10 +303,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128 << 10) /* Regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */ -#endif #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index fcfdfda..b0e10c7 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -258,10 +258,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ -#endif /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 3f71dca..8a37ebf 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -226,10 +226,6 @@ * The stack sizes are set up in start.S using these settings */ #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ -#endif /*----------------------------------------------------------------------- * Physical Memory Map -- cgit v0.10.2 From 10e2568d0362a813013e934456c9bed2e7e8299b Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Sun, 27 Nov 2011 10:16:07 +0000 Subject: ARM: davinci_dm6467Tevm: Fix build breakage Fix: arch/arm/cpu/arm926ejs/davinci/libdavinci.o: In function `timer_init': /work/agust/git/u-boot/arch/arm/cpu/arm926ejs/davinci/timer.c:62: undefined reference to `davinci_arm_clk_get' drivers/i2c/libi2c.o: In function `i2c_init': /work/agust/git/u-boot/drivers/i2c/davinci_i2c.c:102: undefined reference to `davinci_arm_clk_get' Signed-off-by: Anatolij Gustschin Cc: Sandeep Paulraj diff --git a/include/configs/davinci_dm6467Tevm.h b/include/configs/davinci_dm6467Tevm.h index f7c994e..b3a4e44 100644 --- a/include/configs/davinci_dm6467Tevm.h +++ b/include/configs/davinci_dm6467Tevm.h @@ -23,6 +23,7 @@ /* Spectrum Digital TMS320DM6467T EVM board */ #define DAVINCI_DM6467EVM #define DAVINCI_DM6467TEVM +#define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_USE_NAND #define CONFIG_SYS_NAND_SMALLPAGE -- cgit v0.10.2 From 27b8c8f267e260b10450a53b14843eed58cebeff Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Sun, 27 Nov 2011 03:51:06 +0000 Subject: BeagleBoard: config: Really switch to ttyO2 The previous commit changed it to "zero two" instead of the proper "Oh two". This was completely broken! Signed-off-by: Koen Kooi Acked-by: Tom Rini diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 7bb56a3..a33aa41 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -214,7 +214,7 @@ "rdaddr=0x81000000\0" \ "usbtty=cdc_acm\0" \ "bootfile=uImage.beagle\0" \ - "console=tty02,115200n8\0" \ + "console=ttyO2,115200n8\0" \ "mpurate=auto\0" \ "buddy=none "\ "optargs=\0" \ -- cgit v0.10.2 From 7c587d320d110e41008bc7b658655d22485d05a6 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:29 +0000 Subject: davinci_emac: move arch-independent defines to separate header DaVinci EMAC is found not only on DaVinci SoCs but on some OMAP3 SoCs also. This patch moves common defines from arch-davinci/emac_defs.h to drivers/net/davinci_emac.h DaVinci specific PHY drivers hacked to include the new header. We might want to switch to phylib in future. Signed-off-by: Ilya Yanok diff --git a/arch/arm/cpu/arm926ejs/davinci/dp83848.c b/arch/arm/cpu/arm926ejs/davinci/dp83848.c index c71c685..d435e4b 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dp83848.c +++ b/arch/arm/cpu/arm926ejs/davinci/dp83848.c @@ -29,6 +29,7 @@ #include #include #include +#include "../../../../../drivers/net/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/arch/arm/cpu/arm926ejs/davinci/et1011c.c b/arch/arm/cpu/arm926ejs/davinci/et1011c.c index df35e44..68650e5 100644 --- a/arch/arm/cpu/arm926ejs/davinci/et1011c.c +++ b/arch/arm/cpu/arm926ejs/davinci/et1011c.c @@ -22,6 +22,7 @@ #include #include #include +#include "../../../../../drivers/net/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/arch/arm/cpu/arm926ejs/davinci/ksz8873.c b/arch/arm/cpu/arm926ejs/davinci/ksz8873.c index 634eda0..3546e7f 100644 --- a/arch/arm/cpu/arm926ejs/davinci/ksz8873.c +++ b/arch/arm/cpu/arm926ejs/davinci/ksz8873.c @@ -36,6 +36,7 @@ #include #include #include +#include "../../../../../drivers/net/davinci_emac.h" int ksz8873_is_phy_connected(int phy_addr) { diff --git a/arch/arm/cpu/arm926ejs/davinci/lxt972.c b/arch/arm/cpu/arm926ejs/davinci/lxt972.c index 733d413..cce1fe4 100644 --- a/arch/arm/cpu/arm926ejs/davinci/lxt972.c +++ b/arch/arm/cpu/arm926ejs/davinci/lxt972.c @@ -30,6 +30,7 @@ #include #include #include +#include "../../../../../drivers/net/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/arch/arm/include/asm/arch-davinci/emac_defs.h b/arch/arm/include/asm/arch-davinci/emac_defs.h index ea52888..8a17de9 100644 --- a/arch/arm/include/asm/arch-davinci/emac_defs.h +++ b/arch/arm/include/asm/arch-davinci/emac_defs.h @@ -84,295 +84,6 @@ #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ #endif -/* Ethernet Min/Max packet size */ -#define EMAC_MIN_ETHERNET_PKT_SIZE 60 -#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 -#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ - -/* Number of RX packet buffers - * NOTE: Only 1 buffer supported as of now - */ -#define EMAC_MAX_RX_BUFFERS 10 - - -/*********************************************** - ******** Internally used macros *************** - ***********************************************/ - -#define EMAC_CH_TX 1 -#define EMAC_CH_RX 0 - -/* Each descriptor occupies 4 words, lets start RX desc's at 0 and - * reserve space for 64 descriptors max - */ -#define EMAC_RX_DESC_BASE 0x0 -#define EMAC_TX_DESC_BASE 0x1000 - -/* EMAC Teardown value */ -#define EMAC_TEARDOWN_VALUE 0xfffffffc - -/* MII Status Register */ -#define MII_STATUS_REG 1 - -/* Number of statistics registers */ -#define EMAC_NUM_STATS 36 - - -/* EMAC Descriptor */ -typedef volatile struct _emac_desc -{ - u_int32_t next; /* Pointer to next descriptor in chain */ - u_int8_t *buffer; /* Pointer to data buffer */ - u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ - u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ -} emac_desc; - -/* CPPI bit positions */ -#define EMAC_CPPI_SOP_BIT (0x80000000) -#define EMAC_CPPI_EOP_BIT (0x40000000) -#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) -#define EMAC_CPPI_EOQ_BIT (0x10000000) -#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) -#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) - -#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) - -#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) -#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) -#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) -#define EMAC_MACCONTROL_GIGFORCE (1 << 17) -#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) - -#define EMAC_MAC_ADDR_MATCH (1 << 19) -#define EMAC_MAC_ADDR_IS_VALID (1 << 20) - -#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) -#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) - - -#define MDIO_CONTROL_IDLE (0x80000000) -#define MDIO_CONTROL_ENABLE (0x40000000) -#define MDIO_CONTROL_FAULT_ENABLE (0x40000) -#define MDIO_CONTROL_FAULT (0x80000) -#define MDIO_USERACCESS0_GO (0x80000000) -#define MDIO_USERACCESS0_WRITE_READ (0x0) -#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) -#define MDIO_USERACCESS0_ACK (0x20000000) - -/* Ethernet MAC Registers Structure */ -typedef struct { - dv_reg TXIDVER; - dv_reg TXCONTROL; - dv_reg TXTEARDOWN; - u_int8_t RSVD0[4]; - dv_reg RXIDVER; - dv_reg RXCONTROL; - dv_reg RXTEARDOWN; - u_int8_t RSVD1[100]; - dv_reg TXINTSTATRAW; - dv_reg TXINTSTATMASKED; - dv_reg TXINTMASKSET; - dv_reg TXINTMASKCLEAR; - dv_reg MACINVECTOR; - u_int8_t RSVD2[12]; - dv_reg RXINTSTATRAW; - dv_reg RXINTSTATMASKED; - dv_reg RXINTMASKSET; - dv_reg RXINTMASKCLEAR; - dv_reg MACINTSTATRAW; - dv_reg MACINTSTATMASKED; - dv_reg MACINTMASKSET; - dv_reg MACINTMASKCLEAR; - u_int8_t RSVD3[64]; - dv_reg RXMBPENABLE; - dv_reg RXUNICASTSET; - dv_reg RXUNICASTCLEAR; - dv_reg RXMAXLEN; - dv_reg RXBUFFEROFFSET; - dv_reg RXFILTERLOWTHRESH; - u_int8_t RSVD4[8]; - dv_reg RX0FLOWTHRESH; - dv_reg RX1FLOWTHRESH; - dv_reg RX2FLOWTHRESH; - dv_reg RX3FLOWTHRESH; - dv_reg RX4FLOWTHRESH; - dv_reg RX5FLOWTHRESH; - dv_reg RX6FLOWTHRESH; - dv_reg RX7FLOWTHRESH; - dv_reg RX0FREEBUFFER; - dv_reg RX1FREEBUFFER; - dv_reg RX2FREEBUFFER; - dv_reg RX3FREEBUFFER; - dv_reg RX4FREEBUFFER; - dv_reg RX5FREEBUFFER; - dv_reg RX6FREEBUFFER; - dv_reg RX7FREEBUFFER; - dv_reg MACCONTROL; - dv_reg MACSTATUS; - dv_reg EMCONTROL; - dv_reg FIFOCONTROL; - dv_reg MACCONFIG; - dv_reg SOFTRESET; - u_int8_t RSVD5[88]; - dv_reg MACSRCADDRLO; - dv_reg MACSRCADDRHI; - dv_reg MACHASH1; - dv_reg MACHASH2; - dv_reg BOFFTEST; - dv_reg TPACETEST; - dv_reg RXPAUSE; - dv_reg TXPAUSE; - u_int8_t RSVD6[16]; - dv_reg RXGOODFRAMES; - dv_reg RXBCASTFRAMES; - dv_reg RXMCASTFRAMES; - dv_reg RXPAUSEFRAMES; - dv_reg RXCRCERRORS; - dv_reg RXALIGNCODEERRORS; - dv_reg RXOVERSIZED; - dv_reg RXJABBER; - dv_reg RXUNDERSIZED; - dv_reg RXFRAGMENTS; - dv_reg RXFILTERED; - dv_reg RXQOSFILTERED; - dv_reg RXOCTETS; - dv_reg TXGOODFRAMES; - dv_reg TXBCASTFRAMES; - dv_reg TXMCASTFRAMES; - dv_reg TXPAUSEFRAMES; - dv_reg TXDEFERRED; - dv_reg TXCOLLISION; - dv_reg TXSINGLECOLL; - dv_reg TXMULTICOLL; - dv_reg TXEXCESSIVECOLL; - dv_reg TXLATECOLL; - dv_reg TXUNDERRUN; - dv_reg TXCARRIERSENSE; - dv_reg TXOCTETS; - dv_reg FRAME64; - dv_reg FRAME65T127; - dv_reg FRAME128T255; - dv_reg FRAME256T511; - dv_reg FRAME512T1023; - dv_reg FRAME1024TUP; - dv_reg NETOCTETS; - dv_reg RXSOFOVERRUNS; - dv_reg RXMOFOVERRUNS; - dv_reg RXDMAOVERRUNS; - u_int8_t RSVD7[624]; - dv_reg MACADDRLO; - dv_reg MACADDRHI; - dv_reg MACINDEX; - u_int8_t RSVD8[244]; - dv_reg TX0HDP; - dv_reg TX1HDP; - dv_reg TX2HDP; - dv_reg TX3HDP; - dv_reg TX4HDP; - dv_reg TX5HDP; - dv_reg TX6HDP; - dv_reg TX7HDP; - dv_reg RX0HDP; - dv_reg RX1HDP; - dv_reg RX2HDP; - dv_reg RX3HDP; - dv_reg RX4HDP; - dv_reg RX5HDP; - dv_reg RX6HDP; - dv_reg RX7HDP; - dv_reg TX0CP; - dv_reg TX1CP; - dv_reg TX2CP; - dv_reg TX3CP; - dv_reg TX4CP; - dv_reg TX5CP; - dv_reg TX6CP; - dv_reg TX7CP; - dv_reg RX0CP; - dv_reg RX1CP; - dv_reg RX2CP; - dv_reg RX3CP; - dv_reg RX4CP; - dv_reg RX5CP; - dv_reg RX6CP; - dv_reg RX7CP; -} emac_regs; - -/* EMAC Wrapper Registers Structure */ -typedef struct { -#ifdef DAVINCI_EMAC_VERSION2 - dv_reg idver; - dv_reg softrst; - dv_reg emctrl; - dv_reg c0rxthreshen; - dv_reg c0rxen; - dv_reg c0txen; - dv_reg c0miscen; - dv_reg c1rxthreshen; - dv_reg c1rxen; - dv_reg c1txen; - dv_reg c1miscen; - dv_reg c2rxthreshen; - dv_reg c2rxen; - dv_reg c2txen; - dv_reg c2miscen; - dv_reg c0rxthreshstat; - dv_reg c0rxstat; - dv_reg c0txstat; - dv_reg c0miscstat; - dv_reg c1rxthreshstat; - dv_reg c1rxstat; - dv_reg c1txstat; - dv_reg c1miscstat; - dv_reg c2rxthreshstat; - dv_reg c2rxstat; - dv_reg c2txstat; - dv_reg c2miscstat; - dv_reg c0rximax; - dv_reg c0tximax; - dv_reg c1rximax; - dv_reg c1tximax; - dv_reg c2rximax; - dv_reg c2tximax; -#else - u_int8_t RSVD0[4100]; - dv_reg EWCTL; - dv_reg EWINTTCNT; -#endif -} ewrap_regs; - -/* EMAC MDIO Registers Structure */ -typedef struct { - dv_reg VERSION; - dv_reg CONTROL; - dv_reg ALIVE; - dv_reg LINK; - dv_reg LINKINTRAW; - dv_reg LINKINTMASKED; - u_int8_t RSVD0[8]; - dv_reg USERINTRAW; - dv_reg USERINTMASKED; - dv_reg USERINTMASKSET; - dv_reg USERINTMASKCLEAR; - u_int8_t RSVD1[80]; - dv_reg USERACCESS0; - dv_reg USERPHYSEL0; - dv_reg USERACCESS1; - dv_reg USERPHYSEL1; -} mdio_regs; - -int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); -int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); - -typedef struct -{ - char name[64]; - int (*init)(int phy_addr); - int (*is_phy_connected)(int phy_addr); - int (*get_link_speed)(int phy_addr); - int (*auto_negotiate)(int phy_addr); -} phy_t; - #define PHY_KSZ8873 (0x00221450) int ksz8873_is_phy_connected(int phy_addr); int ksz8873_get_link_speed(int phy_addr); diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 36c33af..43c4373 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -43,6 +43,7 @@ #include #include #include +#include "davinci_emac.h" unsigned int emac_dbg = 0; #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) diff --git a/drivers/net/davinci_emac.h b/drivers/net/davinci_emac.h new file mode 100644 index 0000000..a42c93a --- /dev/null +++ b/drivers/net/davinci_emac.h @@ -0,0 +1,314 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on: mach-davinci/emac_defs.h + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _DAVINCI_EMAC_H_ +#define _DAVINCI_EMAC_H_ +/* Ethernet Min/Max packet size */ +#define EMAC_MIN_ETHERNET_PKT_SIZE 60 +#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 +/* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ +#define EMAC_PKT_ALIGN 18 + +/* Number of RX packet buffers + * NOTE: Only 1 buffer supported as of now + */ +#define EMAC_MAX_RX_BUFFERS 10 + + +/*********************************************** + ******** Internally used macros *************** + ***********************************************/ + +#define EMAC_CH_TX 1 +#define EMAC_CH_RX 0 + +/* Each descriptor occupies 4 words, lets start RX desc's at 0 and + * reserve space for 64 descriptors max + */ +#define EMAC_RX_DESC_BASE 0x0 +#define EMAC_TX_DESC_BASE 0x1000 + +/* EMAC Teardown value */ +#define EMAC_TEARDOWN_VALUE 0xfffffffc + +/* MII Status Register */ +#define MII_STATUS_REG 1 + +/* Number of statistics registers */ +#define EMAC_NUM_STATS 36 + + +/* EMAC Descriptor */ +typedef volatile struct _emac_desc +{ + u_int32_t next; /* Pointer to next descriptor + in chain */ + u_int8_t *buffer; /* Pointer to data buffer */ + u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ + u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ +} emac_desc; + +/* CPPI bit positions */ +#define EMAC_CPPI_SOP_BIT (0x80000000) +#define EMAC_CPPI_EOP_BIT (0x40000000) +#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) +#define EMAC_CPPI_EOQ_BIT (0x10000000) +#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) +#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) + +#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) + +#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) +#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) +#define EMAC_MACCONTROL_GIGFORCE (1 << 17) +#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) + +#define EMAC_MAC_ADDR_MATCH (1 << 19) +#define EMAC_MAC_ADDR_IS_VALID (1 << 20) + +#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) +#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) + + +#define MDIO_CONTROL_IDLE (0x80000000) +#define MDIO_CONTROL_ENABLE (0x40000000) +#define MDIO_CONTROL_FAULT_ENABLE (0x40000) +#define MDIO_CONTROL_FAULT (0x80000) +#define MDIO_USERACCESS0_GO (0x80000000) +#define MDIO_USERACCESS0_WRITE_READ (0x0) +#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) +#define MDIO_USERACCESS0_ACK (0x20000000) + +/* Ethernet MAC Registers Structure */ +typedef struct { + dv_reg TXIDVER; + dv_reg TXCONTROL; + dv_reg TXTEARDOWN; + u_int8_t RSVD0[4]; + dv_reg RXIDVER; + dv_reg RXCONTROL; + dv_reg RXTEARDOWN; + u_int8_t RSVD1[100]; + dv_reg TXINTSTATRAW; + dv_reg TXINTSTATMASKED; + dv_reg TXINTMASKSET; + dv_reg TXINTMASKCLEAR; + dv_reg MACINVECTOR; + u_int8_t RSVD2[12]; + dv_reg RXINTSTATRAW; + dv_reg RXINTSTATMASKED; + dv_reg RXINTMASKSET; + dv_reg RXINTMASKCLEAR; + dv_reg MACINTSTATRAW; + dv_reg MACINTSTATMASKED; + dv_reg MACINTMASKSET; + dv_reg MACINTMASKCLEAR; + u_int8_t RSVD3[64]; + dv_reg RXMBPENABLE; + dv_reg RXUNICASTSET; + dv_reg RXUNICASTCLEAR; + dv_reg RXMAXLEN; + dv_reg RXBUFFEROFFSET; + dv_reg RXFILTERLOWTHRESH; + u_int8_t RSVD4[8]; + dv_reg RX0FLOWTHRESH; + dv_reg RX1FLOWTHRESH; + dv_reg RX2FLOWTHRESH; + dv_reg RX3FLOWTHRESH; + dv_reg RX4FLOWTHRESH; + dv_reg RX5FLOWTHRESH; + dv_reg RX6FLOWTHRESH; + dv_reg RX7FLOWTHRESH; + dv_reg RX0FREEBUFFER; + dv_reg RX1FREEBUFFER; + dv_reg RX2FREEBUFFER; + dv_reg RX3FREEBUFFER; + dv_reg RX4FREEBUFFER; + dv_reg RX5FREEBUFFER; + dv_reg RX6FREEBUFFER; + dv_reg RX7FREEBUFFER; + dv_reg MACCONTROL; + dv_reg MACSTATUS; + dv_reg EMCONTROL; + dv_reg FIFOCONTROL; + dv_reg MACCONFIG; + dv_reg SOFTRESET; + u_int8_t RSVD5[88]; + dv_reg MACSRCADDRLO; + dv_reg MACSRCADDRHI; + dv_reg MACHASH1; + dv_reg MACHASH2; + dv_reg BOFFTEST; + dv_reg TPACETEST; + dv_reg RXPAUSE; + dv_reg TXPAUSE; + u_int8_t RSVD6[16]; + dv_reg RXGOODFRAMES; + dv_reg RXBCASTFRAMES; + dv_reg RXMCASTFRAMES; + dv_reg RXPAUSEFRAMES; + dv_reg RXCRCERRORS; + dv_reg RXALIGNCODEERRORS; + dv_reg RXOVERSIZED; + dv_reg RXJABBER; + dv_reg RXUNDERSIZED; + dv_reg RXFRAGMENTS; + dv_reg RXFILTERED; + dv_reg RXQOSFILTERED; + dv_reg RXOCTETS; + dv_reg TXGOODFRAMES; + dv_reg TXBCASTFRAMES; + dv_reg TXMCASTFRAMES; + dv_reg TXPAUSEFRAMES; + dv_reg TXDEFERRED; + dv_reg TXCOLLISION; + dv_reg TXSINGLECOLL; + dv_reg TXMULTICOLL; + dv_reg TXEXCESSIVECOLL; + dv_reg TXLATECOLL; + dv_reg TXUNDERRUN; + dv_reg TXCARRIERSENSE; + dv_reg TXOCTETS; + dv_reg FRAME64; + dv_reg FRAME65T127; + dv_reg FRAME128T255; + dv_reg FRAME256T511; + dv_reg FRAME512T1023; + dv_reg FRAME1024TUP; + dv_reg NETOCTETS; + dv_reg RXSOFOVERRUNS; + dv_reg RXMOFOVERRUNS; + dv_reg RXDMAOVERRUNS; + u_int8_t RSVD7[624]; + dv_reg MACADDRLO; + dv_reg MACADDRHI; + dv_reg MACINDEX; + u_int8_t RSVD8[244]; + dv_reg TX0HDP; + dv_reg TX1HDP; + dv_reg TX2HDP; + dv_reg TX3HDP; + dv_reg TX4HDP; + dv_reg TX5HDP; + dv_reg TX6HDP; + dv_reg TX7HDP; + dv_reg RX0HDP; + dv_reg RX1HDP; + dv_reg RX2HDP; + dv_reg RX3HDP; + dv_reg RX4HDP; + dv_reg RX5HDP; + dv_reg RX6HDP; + dv_reg RX7HDP; + dv_reg TX0CP; + dv_reg TX1CP; + dv_reg TX2CP; + dv_reg TX3CP; + dv_reg TX4CP; + dv_reg TX5CP; + dv_reg TX6CP; + dv_reg TX7CP; + dv_reg RX0CP; + dv_reg RX1CP; + dv_reg RX2CP; + dv_reg RX3CP; + dv_reg RX4CP; + dv_reg RX5CP; + dv_reg RX6CP; + dv_reg RX7CP; +} emac_regs; + +/* EMAC Wrapper Registers Structure */ +typedef struct { +#ifdef DAVINCI_EMAC_VERSION2 + dv_reg idver; + dv_reg softrst; + dv_reg emctrl; + dv_reg c0rxthreshen; + dv_reg c0rxen; + dv_reg c0txen; + dv_reg c0miscen; + dv_reg c1rxthreshen; + dv_reg c1rxen; + dv_reg c1txen; + dv_reg c1miscen; + dv_reg c2rxthreshen; + dv_reg c2rxen; + dv_reg c2txen; + dv_reg c2miscen; + dv_reg c0rxthreshstat; + dv_reg c0rxstat; + dv_reg c0txstat; + dv_reg c0miscstat; + dv_reg c1rxthreshstat; + dv_reg c1rxstat; + dv_reg c1txstat; + dv_reg c1miscstat; + dv_reg c2rxthreshstat; + dv_reg c2rxstat; + dv_reg c2txstat; + dv_reg c2miscstat; + dv_reg c0rximax; + dv_reg c0tximax; + dv_reg c1rximax; + dv_reg c1tximax; + dv_reg c2rximax; + dv_reg c2tximax; +#else + u_int8_t RSVD0[4100]; + dv_reg EWCTL; + dv_reg EWINTTCNT; +#endif +} ewrap_regs; + +/* EMAC MDIO Registers Structure */ +typedef struct { + dv_reg VERSION; + dv_reg CONTROL; + dv_reg ALIVE; + dv_reg LINK; + dv_reg LINKINTRAW; + dv_reg LINKINTMASKED; + u_int8_t RSVD0[8]; + dv_reg USERINTRAW; + dv_reg USERINTMASKED; + dv_reg USERINTMASKSET; + dv_reg USERINTMASKCLEAR; + u_int8_t RSVD1[80]; + dv_reg USERACCESS0; + dv_reg USERPHYSEL0; + dv_reg USERACCESS1; + dv_reg USERPHYSEL1; +} mdio_regs; + +int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); +int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); + +typedef struct { + char name[64]; + int (*init)(int phy_addr); + int (*is_phy_connected)(int phy_addr); + int (*get_link_speed)(int phy_addr); + int (*auto_negotiate)(int phy_addr); +} phy_t; + +#endif /* _DAVINCI_EMAC_H_ */ -- cgit v0.10.2 From 82b772178d0f3d7f3cb246138197028795edf004 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:30 +0000 Subject: davinci_emac: use internal addresses in buffer descriptors On AM35xx CPPI RAM had different addresses when accessed from the CPU and from the EMAC. We need to account this to deal with the buffer descriptors correctly. Signed-off-by: Ilya Yanok diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 43c4373..2ac6874 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -48,6 +48,27 @@ unsigned int emac_dbg = 0; #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) +#ifdef EMAC_HW_RAM_ADDR +static inline unsigned long BD_TO_HW(unsigned long x) +{ + if (x == 0) + return 0; + + return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR; +} + +static inline unsigned long HW_TO_BD(unsigned long x) +{ + if (x == 0) + return 0; + + return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR; +} +#else +#define BD_TO_HW(x) (x) +#define HW_TO_BD(x) (x) +#endif + #ifdef DAVINCI_EMAC_GIG_ENABLE #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) #else @@ -448,7 +469,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) /* Create RX queue and set receive process in place */ emac_rx_active_head = emac_rx_desc; for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { - rx_desc->next = (u_int32_t)(rx_desc + 1); + rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1)); rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; @@ -501,7 +522,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) emac_gigabit_enable(active_phy_addr[index]); /* Start receive process */ - writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP); + writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP); debug_emac("- emac_open\n"); @@ -619,7 +640,7 @@ static int davinci_eth_send_packet (struct eth_device *dev, EMAC_CPPI_OWNERSHIP_BIT | EMAC_CPPI_EOP_BIT); /* Send the packet */ - writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP); + writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP); /* Wait for packet to complete or link down */ while (1) { @@ -663,14 +684,14 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) } /* Ack received packet descriptor */ - writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP); + writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP); curr_desc = rx_curr_desc; emac_rx_active_head = - (volatile emac_desc *) rx_curr_desc->next; + (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next)); if (status & EMAC_CPPI_EOQ_BIT) { if (emac_rx_active_head) { - writel((unsigned long)emac_rx_active_head, + writel(BD_TO_HW((ulong)emac_rx_active_head), &adap_emac->RX0HDP); } else { emac_rx_queue_active = 0; @@ -688,7 +709,7 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) emac_rx_active_head = curr_desc; emac_rx_active_tail = curr_desc; if (emac_rx_queue_active != 0) { - writel((unsigned long)emac_rx_active_head, + writel(BD_TO_HW((ulong)emac_rx_active_head), &adap_emac->RX0HDP); printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); emac_rx_queue_active = 1; @@ -696,10 +717,10 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) } else { tail_desc = emac_rx_active_tail; emac_rx_active_tail = curr_desc; - tail_desc->next = (unsigned int) curr_desc; + tail_desc->next = BD_TO_HW((ulong) curr_desc); status = tail_desc->pkt_flag_len; if (status & EMAC_CPPI_EOQ_BIT) { - writel((unsigned long)curr_desc, + writel(BD_TO_HW((ulong)curr_desc), &adap_emac->RX0HDP); status &= ~EMAC_CPPI_EOQ_BIT; tail_desc->pkt_flag_len = status; -- cgit v0.10.2 From 918588cfd380cdd93c796f9217283737b45887c6 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:31 +0000 Subject: davinci_emac: conditionally compile specific PHY support Signed-off-by: Ilya Yanok diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 2ac6874..4f9ed2f 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -803,6 +803,7 @@ int davinci_emac_initialize(void) phy_id |= tmp & 0x0000ffff; switch (phy_id) { +#ifdef PHY_KSZ8873 case PHY_KSZ8873: sprintf(phy[i].name, "KSZ8873 @ 0x%02x", active_phy_addr[i]); @@ -811,6 +812,8 @@ int davinci_emac_initialize(void) phy[i].get_link_speed = ksz8873_get_link_speed; phy[i].auto_negotiate = ksz8873_auto_negotiate; break; +#endif +#ifdef PHY_LXT972 case PHY_LXT972: sprintf(phy[i].name, "LXT972 @ 0x%02x", active_phy_addr[i]); @@ -819,6 +822,8 @@ int davinci_emac_initialize(void) phy[i].get_link_speed = lxt972_get_link_speed; phy[i].auto_negotiate = lxt972_auto_negotiate; break; +#endif +#ifdef PHY_DP83848 case PHY_DP83848: sprintf(phy[i].name, "DP83848 @ 0x%02x", active_phy_addr[i]); @@ -827,6 +832,8 @@ int davinci_emac_initialize(void) phy[i].get_link_speed = dp83848_get_link_speed; phy[i].auto_negotiate = dp83848_auto_negotiate; break; +#endif +#ifdef PHY_ET1011C case PHY_ET1011C: sprintf(phy[i].name, "ET1011C @ 0x%02x", active_phy_addr[i]); @@ -835,6 +842,7 @@ int davinci_emac_initialize(void) phy[i].get_link_speed = et1011c_get_link_speed; phy[i].auto_negotiate = gen_auto_negotiate; break; +#endif default: sprintf(phy[i].name, "GENERIC @ 0x%02x", active_phy_addr[i]); -- cgit v0.10.2 From 2f3427ccb915c6f6774f0bcebb67c648dc25dcfd Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:32 +0000 Subject: arm926ejs: add noop implementation for dcache ops Added noop implementation for dcache operations that will buzz about missing real implementation and disable the dcache. This fixes compilation of DaVinci EMAC driver on arm926ejs. Signed-off-by: Ilya Yanok diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index a56ff08..5923e65 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).o START = start.o -COBJS = cpu.o +COBJS = cpu.o cache.o ifdef CONFIG_SPL_BUILD ifdef CONFIG_SPL_NO_CPU_SUPPORT_CODE diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c new file mode 100644 index 0000000..4415642 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2011 + * Ilya Yanok, EmCraft Systems + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include +#include + +#ifndef CONFIG_SYS_DCACHE_OFF +static inline void dcache_noop(void) +{ + if (dcache_status()) { + puts("WARNING: cache operations are not implemented!\n" + "WARNING: disabling D-Cache now, you can re-enable it" + "later with 'dcache on' command\n"); + dcache_disable(); + } +} + +void invalidate_dcache_all(void) +{ + dcache_noop(); +} + +void flush_dcache_all(void) +{ + dcache_noop(); +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + dcache_noop(); +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + dcache_noop(); +} +#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ +void invalidate_dcache_all(void) +{ +} + +void flush_dcache_all(void) +{ +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_cache(unsigned long start, unsigned long size) +{ +} +#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ -- cgit v0.10.2 From 2aa8720257beadde8f798bd30096ca4c9007c8e0 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:33 +0000 Subject: davinci_emac: fix for running with dcache enabled DaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache enabled by default. So we have to take care and flush/invalidate the cache before/after the DMA operations. Please note that the receive buffer alignment to 32 byte boundary comes from the old driver version I don't know if it is really needed or alignment to cache line size is enough. Signed-off-by: Ilya Yanok diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 4f9ed2f..4760390 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include #include "davinci_emac.h" @@ -105,7 +106,8 @@ static volatile emac_desc *emac_rx_active_tail = 0; static int emac_rx_queue_active = 0; /* Receive packet buffers */ -static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; +static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE] + __aligned(ARCH_DMA_MINALIGN); #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3 @@ -119,6 +121,26 @@ static u_int8_t num_phy; phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; +static inline void davinci_flush_rx_descs(void) +{ + /* flush the whole RX descs area */ + flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, + EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); +} + +static inline void davinci_invalidate_rx_descs(void) +{ + /* invalidate the whole RX descs area */ + invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, + EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); +} + +static inline void davinci_flush_desc(emac_desc *desc) +{ + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + sizeof(*desc)); +} + static int davinci_eth_set_mac_addr(struct eth_device *dev) { unsigned long mac_hi; @@ -470,7 +492,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) emac_rx_active_head = emac_rx_desc; for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1)); - rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; + rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE]; rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; rx_desc++; @@ -482,6 +504,8 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) emac_rx_active_tail = rx_desc; emac_rx_queue_active = 1; + davinci_flush_rx_descs(); + /* Enable TX/RX */ writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); writel(0, &adap_emac->RXBUFFEROFFSET); @@ -639,6 +663,11 @@ static int davinci_eth_send_packet (struct eth_device *dev, EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT | EMAC_CPPI_EOP_BIT); + + flush_dcache_range((unsigned long)packet, + (unsigned long)packet + length); + davinci_flush_desc(emac_tx_desc); + /* Send the packet */ writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP); @@ -671,6 +700,8 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) volatile emac_desc *tail_desc; int status, ret = -1; + davinci_invalidate_rx_descs(); + rx_curr_desc = emac_rx_active_head; status = rx_curr_desc->pkt_flag_len; if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { @@ -678,6 +709,9 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) /* Error in packet - discard it and requeue desc */ printf ("WARN: emac_rcv_pkt: Error in packet\n"); } else { + unsigned long tmp = (unsigned long)rx_curr_desc->buffer; + + invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE); NetReceive (rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xffff)); ret = rx_curr_desc->buff_off_len & 0xffff; @@ -703,6 +737,7 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; rx_curr_desc->next = 0; + davinci_flush_desc(rx_curr_desc); if (emac_rx_active_head == 0) { printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); @@ -720,11 +755,13 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) tail_desc->next = BD_TO_HW((ulong) curr_desc); status = tail_desc->pkt_flag_len; if (status & EMAC_CPPI_EOQ_BIT) { + davinci_flush_desc(tail_desc); writel(BD_TO_HW((ulong)curr_desc), &adap_emac->RX0HDP); status &= ~EMAC_CPPI_EOQ_BIT; tail_desc->pkt_flag_len = status; } + davinci_flush_desc(tail_desc); } return (ret); } diff --git a/drivers/net/davinci_emac.h b/drivers/net/davinci_emac.h index a42c93a..37c841c 100644 --- a/drivers/net/davinci_emac.h +++ b/drivers/net/davinci_emac.h @@ -24,8 +24,9 @@ /* Ethernet Min/Max packet size */ #define EMAC_MIN_ETHERNET_PKT_SIZE 60 #define EMAC_MAX_ETHERNET_PKT_SIZE 1518 -/* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ -#define EMAC_PKT_ALIGN 18 +/* Buffer size (should be aligned on 32 byte and cache line) */ +#define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\ + ARCH_DMA_MINALIGN) /* Number of RX packet buffers * NOTE: Only 1 buffer supported as of now -- cgit v0.10.2 From 80deda5d8e02c7e58dd4e037d754d72a8e1a99ae Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:34 +0000 Subject: davinci_emac: hardcode 100Mbps for AM35xx and RMII For some reason code setting the speed based on the PHY feedback causes troubles on AM3517 so hardcode 100Mbps for now. Signed-off-by: Ilya Yanok diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 4760390..d6c4e63 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -520,7 +520,8 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) writel(1, &adap_emac->RXUNICASTSET); /* Enable MII interface and Full duplex mode */ -#ifdef CONFIG_SOC_DA8XX +#if defined(CONFIG_SOC_DA8XX) || \ + (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII)) writel((EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE | EMAC_MACCONTROL_RMIISPEED_100), -- cgit v0.10.2 From b9e65a797bea224c786e3dcd936a9ffc08d24aef Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:35 +0000 Subject: AM35xx: add EMAC support AM35xx has DaVinci-compatible EMAC. Signed-off-by: Ilya Yanok diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 8e85891..6ebfd32 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -32,6 +32,7 @@ COBJS += clock.o COBJS += mem.o COBJS += sys_info.o +COBJS-$(CONFIG_DRIVER_TI_EMAC) += emac.o COBJS-$(CONFIG_EMIF4) += emif4.o COBJS-$(CONFIG_SDRC) += sdrc.o diff --git a/arch/arm/cpu/armv7/omap3/emac.c b/arch/arm/cpu/armv7/omap3/emac.c new file mode 100644 index 0000000..14667f1 --- /dev/null +++ b/arch/arm/cpu/armv7/omap3/emac.c @@ -0,0 +1,44 @@ +/* + * + * DaVinci EMAC initialization. + * + * (C) Copyright 2011, Ilya Yanok, Emcraft Systems + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include +#include +#include +#include + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ + u32 reset; + + /* ensure that the module is out of reset */ + reset = readl(&am35x_scm_general_regs->ip_sw_reset); + reset &= ~CPGMACSS_SW_RST; + writel(reset, &am35x_scm_general_regs->ip_sw_reset); + + return davinci_emac_initialize(); +} diff --git a/arch/arm/include/asm/arch-omap3/am35x_def.h b/arch/arm/include/asm/arch-omap3/am35x_def.h index 81942a8..bbaf1bc 100644 --- a/arch/arm/include/asm/arch-omap3/am35x_def.h +++ b/arch/arm/include/asm/arch-omap3/am35x_def.h @@ -32,6 +32,9 @@ #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ +/* IP_SW_RESET bits */ +#define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */ + /* General register mappings of system control module */ #define AM35X_SCM_GEN_BASE 0x48002270 struct am35x_scm_general { diff --git a/arch/arm/include/asm/arch-omap3/emac_defs.h b/arch/arm/include/asm/arch-omap3/emac_defs.h new file mode 100644 index 0000000..8506c55 --- /dev/null +++ b/arch/arm/include/asm/arch-omap3/emac_defs.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Based on: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.h + * + * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + + * Modifications: + * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. + * + */ + +#ifndef _AM3517_EMAC_H_ +#define _AM3517_EMAC_H_ + +#define EMAC_BASE_ADDR 0x5C010000 +#define EMAC_WRAPPER_BASE_ADDR 0x5C000000 +#define EMAC_WRAPPER_RAM_ADDR 0x5C020000 +#define EMAC_MDIO_BASE_ADDR 0x5C030000 +#define EMAC_HW_RAM_ADDR 0x01E20000 + +#define EMAC_MDIO_BUS_FREQ 166000000 /* 166 MHZ check */ +#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 2.0 MHz */ + +/* SOFTRESET macro definition interferes with emac_regs structure definition */ +#undef SOFTRESET + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int *dv_reg_p; + +#define DAVINCI_EMAC_VERSION2 + +#endif /* _AM3517_EMAC_H_ */ -- cgit v0.10.2 From ad2a7909a1430321224ea25c808494b4df8d1140 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:36 +0000 Subject: AM3517: move AM3517 specific mux defines to generic header AM3517 specific CONTROL_PADCONF_* defines moved from board-specific files to Signed-off-by: Ilya Yanok diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h index 0c01c73..6daef49 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h @@ -404,6 +404,47 @@ #define CONTROL_PADCONF_SDRC_CKE0 0x0262 #define CONTROL_PADCONF_SDRC_CKE1 0x0264 +/* AM3517 specific mux configuration */ +#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 +/* CCDC */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 +#define CONTROL_PADCONF_CCDC_HD 0x01E8 +#define CONTROL_PADCONF_CCDC_VD 0x01EA +#define CONTROL_PADCONF_CCDC_WEN 0x01EC +#define CONTROL_PADCONF_CCDC_DATA0 0x01EE +#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 +#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 +#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 +#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 +#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 +#define CONTROL_PADCONF_CCDC_DATA6 0x01FA +#define CONTROL_PADCONF_CCDC_DATA7 0x01FC +/* RMII */ +#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE +#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 +#define CONTROL_PADCONF_RMII_RXD0 0x0202 +#define CONTROL_PADCONF_RMII_RXD1 0x0204 +#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 +#define CONTROL_PADCONF_RMII_RXER 0x0208 +#define CONTROL_PADCONF_RMII_TXD0 0x020A +#define CONTROL_PADCONF_RMII_TXD1 0x020C +#define CONTROL_PADCONF_RMII_TXEN 0x020E +#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 +#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 +/* CAN */ +#define CONTROL_PADCONF_HECC1_TXD 0x0214 +#define CONTROL_PADCONF_HECC1_RXD 0x0216 + +#define CONTROL_PADCONF_SYS_BOOT7 0x0218 +#define CONTROL_PADCONF_SDRC_DQS0N 0x021A +#define CONTROL_PADCONF_SDRC_DQS1N 0x021C +#define CONTROL_PADCONF_SDRC_DQS2N 0x021E +#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 +#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 +#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 +#define CONTROL_PADCONF_SYS_BOOT8 0x0226 + #define MUX_VAL(OFFSET,VALUE)\ writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h index 3d74ef1..68d746c 100644 --- a/board/logicpd/am3517evm/am3517evm.h +++ b/board/logicpd/am3517evm/am3517evm.h @@ -31,46 +31,6 @@ const omap3_sysinfo sysinfo = { "AM3517EVM Board", "NAND", }; -/* AM3517 specific mux configuration */ -#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 -/* CCDC */ -#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 -#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 -#define CONTROL_PADCONF_CCDC_HD 0x01E8 -#define CONTROL_PADCONF_CCDC_VD 0x01EA -#define CONTROL_PADCONF_CCDC_WEN 0x01EC -#define CONTROL_PADCONF_CCDC_DATA0 0x01EE -#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 -#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 -#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 -#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 -#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 -#define CONTROL_PADCONF_CCDC_DATA6 0x01FA -#define CONTROL_PADCONF_CCDC_DATA7 0x01FC -/* RMII */ -#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE -#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 -#define CONTROL_PADCONF_RMII_RXD0 0x0202 -#define CONTROL_PADCONF_RMII_RXD1 0x0204 -#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 -#define CONTROL_PADCONF_RMII_RXER 0x0208 -#define CONTROL_PADCONF_RMII_TXD0 0x020A -#define CONTROL_PADCONF_RMII_TXD1 0x020C -#define CONTROL_PADCONF_RMII_TXEN 0x020E -#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 -#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 -/* CAN */ -#define CONTROL_PADCONF_HECC1_TXD 0x0214 -#define CONTROL_PADCONF_HECC1_RXD 0x0216 - -#define CONTROL_PADCONF_SYS_BOOT7 0x0218 -#define CONTROL_PADCONF_SDRC_DQS0N 0x021A -#define CONTROL_PADCONF_SDRC_DQS1N 0x021C -#define CONTROL_PADCONF_SDRC_DQS2N 0x021E -#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 -#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 -#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 -#define CONTROL_PADCONF_SYS_BOOT8 0x0226 /* * IEN - Input Enable diff --git a/board/ti/am3517crane/am3517crane.h b/board/ti/am3517crane/am3517crane.h index 41db972..71335a3 100644 --- a/board/ti/am3517crane/am3517crane.h +++ b/board/ti/am3517crane/am3517crane.h @@ -30,45 +30,6 @@ const omap3_sysinfo sysinfo = { "CraneBoard", "NAND", }; -/* AM3517 specific mux configuration */ -#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 -/* CCDC */ -#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 -#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 -#define CONTROL_PADCONF_CCDC_HD 0x01E8 -#define CONTROL_PADCONF_CCDC_VD 0x01EA -#define CONTROL_PADCONF_CCDC_WEN 0x01EC -#define CONTROL_PADCONF_CCDC_DATA0 0x01EE -#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 -#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 -#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 -#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 -#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 -#define CONTROL_PADCONF_CCDC_DATA6 0x01FA -#define CONTROL_PADCONF_CCDC_DATA7 0x01FC -/* RMII */ -#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE -#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 -#define CONTROL_PADCONF_RMII_RXD0 0x0202 -#define CONTROL_PADCONF_RMII_RXD1 0x0204 -#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 -#define CONTROL_PADCONF_RMII_RXER 0x0208 -#define CONTROL_PADCONF_RMII_TXD0 0x020A -#define CONTROL_PADCONF_RMII_TXD1 0x020C -#define CONTROL_PADCONF_RMII_TXEN 0x020E -#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 -#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 -/* CAN */ -#define CONTROL_PADCONF_HECC1_TXD 0x0214 -#define CONTROL_PADCONF_HECC1_RXD 0x0216 -#define CONTROL_PADCONF_SYS_BOOT7 0x0218 -#define CONTROL_PADCONF_SDRC_DQS0N 0x021A -#define CONTROL_PADCONF_SDRC_DQS1N 0x021C -#define CONTROL_PADCONF_SDRC_DQS2N 0x021E -#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 -#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 -#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 -#define CONTROL_PADCONF_SYS_BOOT8 0x0226 /* * IEN - Input Enable -- cgit v0.10.2 From 1df308e5be76ec42ade8fb21f623f36ba09217bd Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:37 +0000 Subject: nand_spl_simple: add support for software ECC This patch adds support for software ECC to the nand_spl_simple driver. To enable this one have to define CONFIG_SPL_NAND_SOFTECC. Tested on OMAP3. Signed-off-by: Ilya Yanok Acked-by: Scott Wood diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c index 52bc916..81f0e08 100644 --- a/drivers/mtd/nand/nand_ecc.c +++ b/drivers/mtd/nand/nand_ecc.c @@ -50,7 +50,7 @@ * only nand_correct_data() is needed */ -#ifndef CONFIG_NAND_SPL +#if !defined(CONFIG_NAND_SPL) || defined(CONFIG_SPL_NAND_SOFTECC) /* * Pre-calculated 256-way 1 byte column parity */ diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c index e5003e6..ed821f2 100644 --- a/drivers/mtd/nand/nand_spl_simple.c +++ b/drivers/mtd/nand/nand_spl_simple.c @@ -21,6 +21,7 @@ #include #include #include +#include static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; static nand_info_t mtd; @@ -204,7 +205,8 @@ static int nand_read_page(int block, int page, void *dst) oob_data = ecc_calc + 0x200; for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - this->ecc.hwctl(&mtd, NAND_ECC_READ); + if (this->ecc.mode != NAND_ECC_SOFT) + this->ecc.hwctl(&mtd, NAND_ECC_READ); this->read_buf(&mtd, p, eccsize); this->ecc.calculate(&mtd, p, &ecc_calc[i]); } @@ -274,6 +276,13 @@ void nand_init(void) (void __iomem *)CONFIG_SYS_NAND_BASE; board_nand_init(&nand_chip); +#ifdef CONFIG_SPL_NAND_SOFTECC + if (nand_chip.ecc.mode == NAND_ECC_SOFT) { + nand_chip.ecc.calculate = nand_calculate_ecc; + nand_chip.ecc.correct = nand_correct_data; + } +#endif + if (nand_chip.select_chip) nand_chip.select_chip(&mtd, 0); } -- cgit v0.10.2 From ff62fb4c6a01866310b0b5f43ea097e9e5220a27 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:38 +0000 Subject: omap_gpmc: use SOFTECC in SPL if it's enabled Use software ECC for the SPL build if support for software ECC in SPL is enabled. Signed-off-by: Ilya Yanok Acked-by: Scott Wood diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 5bbec48..1dfe074 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -348,7 +348,7 @@ int board_nand_init(struct nand_chip *nand) nand->chip_delay = 100; /* Default ECC mode */ -#ifndef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC) nand->ecc.mode = NAND_ECC_SOFT; #else nand->ecc.mode = NAND_ECC_HW; @@ -359,7 +359,9 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.correct = omap_correct_data; nand->ecc.calculate = omap_calculate_ecc; omap_hwecc_init(nand); +#endif +#ifdef CONFIG_SPL_BUILD if (nand->options & NAND_BUSWIDTH_16) nand->read_buf = nand_read_buf16; else -- cgit v0.10.2 From ca4b55800ed74207c35271bf7335a092d4955416 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 9 Nov 2011 20:06:23 +0000 Subject: arm, arm926ejs: always do cpu critical inits always do the cpu critical inits in cpu_init_crit, and only jump to lowlevel_init, if CONFIG_SKIP_LOWLEVEL_INIT is not defined. Signed-off-by: Heiko Schocher Cc: Albert ARIBAUD Cc: Wolfgang Denk Cc: Sandeep Paulraj Cc: Tom Rini Cc: Christian Riesch diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index bb4d00b..6a09c02 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -194,9 +194,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit -#endif /* Set stackpointer in internal RAM to call board_init_f */ call_board_init_f: @@ -355,7 +353,6 @@ _dynsym_start_ofs: * ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: /* * flush v4 I/D caches @@ -374,14 +371,15 @@ cpu_init_crit: orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0 +#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* * Go setup Memory and board specific bits prior to relocation. */ mov ip, lr /* perserve link reg across call */ bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ - mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + mov pc, lr /* back to my caller */ #ifndef CONFIG_SPL_BUILD /* -- cgit v0.10.2 From 964930bcfdc67112ea76727163f3408bcf40f614 Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Mon, 28 Nov 2011 23:46:14 +0000 Subject: arm, davinci: Move pinmux functions from board to arch tree Signed-off-by: Christian Riesch Cc: Sandeep Paulraj Cc: Heiko Schocher Cc: Sudhakar Rajashekhara Cc: Syed Mohammed Khasim Cc: Sughosh Ganu Cc: Nick Thompson Cc: Stefano Babic Acked-by: Heiko Schocher Acked-by: Nick Thompson diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index aeb058a..2105ec5 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS-y += cpu.o timer.o psc.o +COBJS-y += cpu.o timer.o psc.o pinmux.o COBJS-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM365) += dm365.o diff --git a/arch/arm/cpu/arm926ejs/davinci/pinmux.c b/arch/arm/cpu/arm926ejs/davinci/pinmux.c new file mode 100644 index 0000000..ce58f71 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/pinmux.c @@ -0,0 +1,105 @@ +/* + * DaVinci pinmux functions. + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, + * Copyright (C) 2007 Sergey Kubushyn + * Copyright (C) 2008 Lyrtech + * Copyright (C) 2004 Texas Instruments. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +/* + * Change the setting of a pin multiplexer field. + * + * Takes an array of pinmux settings similar to: + * + * struct pinmux_config uart_pins[] = { + * { &davinci_syscfg_regs->pinmux[8], 2, 7 }, + * { &davinci_syscfg_regs->pinmux[9], 2, 0 } + * }; + * + * Stepping through the array, each pinmux[n] register has the given value + * set in the pin mux field specified. + * + * The number of pins in the array must be passed (ARRAY_SIZE can provide + * this value conveniently). + * + * Returns 0 if all field numbers and values are in the correct range, + * else returns -1. + */ +int davinci_configure_pin_mux(const struct pinmux_config *pins, + const int n_pins) +{ + int i; + + /* check for invalid pinmux values */ + for (i = 0; i < n_pins; i++) { + if (pins[i].field >= PIN_MUX_NUM_FIELDS || + (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0) + return -1; + } + + /* configure the pinmuxes */ + for (i = 0; i < n_pins; i++) { + const int offset = pins[i].field * PIN_MUX_FIELD_SIZE; + const unsigned int value = pins[i].value << offset; + const unsigned int mask = PIN_MUX_FIELD_MASK << offset; + const dv_reg *mux = pins[i].mux; + + writel(value | (readl(mux) & (~mask)), mux); + } + + return 0; +} + +/* + * Configure multiple pinmux resources. + * + * Takes an pinmux_resource array of pinmux_config and pin counts: + * + * const struct pinmux_resource pinmuxes[] = { + * PINMUX_ITEM(uart_pins), + * PINMUX_ITEM(i2c_pins), + * }; + * + * The number of items in the array must be passed (ARRAY_SIZE can provide + * this value conveniently). + * + * Each item entry is configured in the defined order. If configuration + * of any item fails, -1 is returned and none of the following items are + * configured. On success, 0 is returned. + */ +int davinci_configure_pin_mux_items(const struct pinmux_resource *item, + const int n_items) +{ + int i; + + for (i = 0; i < n_items; i++) { + if (davinci_configure_pin_mux(item[i].pins, + item[i].n_pins) != 0) + return -1; + } + + return 0; +} diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 3e9a3b6..06819a6 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -480,6 +480,8 @@ struct davinci_syscfg_regs { #define davinci_syscfg_regs \ ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE) +#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) + /* Emulation suspend bits */ #define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5) #define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16) diff --git a/board/davinci/common/Makefile b/board/davinci/common/Makefile index 9d7b164..bc99da3 100644 --- a/board/davinci/common/Makefile +++ b/board/davinci/common/Makefile @@ -29,7 +29,7 @@ endif LIB = $(obj)lib$(VENDOR).o -COBJS := misc.o davinci_pinmux.o +COBJS := misc.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/davinci/common/davinci_pinmux.c b/board/davinci/common/davinci_pinmux.c deleted file mode 100644 index ce58f71..0000000 --- a/board/davinci/common/davinci_pinmux.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * DaVinci pinmux functions. - * - * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, - * Copyright (C) 2007 Sergey Kubushyn - * Copyright (C) 2008 Lyrtech - * Copyright (C) 2004 Texas Instruments. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include - -/* - * Change the setting of a pin multiplexer field. - * - * Takes an array of pinmux settings similar to: - * - * struct pinmux_config uart_pins[] = { - * { &davinci_syscfg_regs->pinmux[8], 2, 7 }, - * { &davinci_syscfg_regs->pinmux[9], 2, 0 } - * }; - * - * Stepping through the array, each pinmux[n] register has the given value - * set in the pin mux field specified. - * - * The number of pins in the array must be passed (ARRAY_SIZE can provide - * this value conveniently). - * - * Returns 0 if all field numbers and values are in the correct range, - * else returns -1. - */ -int davinci_configure_pin_mux(const struct pinmux_config *pins, - const int n_pins) -{ - int i; - - /* check for invalid pinmux values */ - for (i = 0; i < n_pins; i++) { - if (pins[i].field >= PIN_MUX_NUM_FIELDS || - (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0) - return -1; - } - - /* configure the pinmuxes */ - for (i = 0; i < n_pins; i++) { - const int offset = pins[i].field * PIN_MUX_FIELD_SIZE; - const unsigned int value = pins[i].value << offset; - const unsigned int mask = PIN_MUX_FIELD_MASK << offset; - const dv_reg *mux = pins[i].mux; - - writel(value | (readl(mux) & (~mask)), mux); - } - - return 0; -} - -/* - * Configure multiple pinmux resources. - * - * Takes an pinmux_resource array of pinmux_config and pin counts: - * - * const struct pinmux_resource pinmuxes[] = { - * PINMUX_ITEM(uart_pins), - * PINMUX_ITEM(i2c_pins), - * }; - * - * The number of items in the array must be passed (ARRAY_SIZE can provide - * this value conveniently). - * - * Each item entry is configured in the defined order. If configuration - * of any item fails, -1 is returned and none of the following items are - * configured. On success, 0 is returned. - */ -int davinci_configure_pin_mux_items(const struct pinmux_resource *item, - const int n_items) -{ - int i; - - for (i = 0; i < n_items; i++) { - if (davinci_configure_pin_mux(item[i].pins, - item[i].n_pins) != 0) - return -1; - } - - return 0; -} diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c index 2021e73..c45c94b 100644 --- a/board/davinci/da8xxevm/da830evm.c +++ b/board/davinci/da8xxevm/da830evm.c @@ -46,8 +46,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) - /* SPI0 pin muxer settings */ static const struct pinmux_config spi0_pins[] = { { pinmux(7), 1, 3 }, diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index e0a3bbe..844e585 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -34,8 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) - /* SPI0 pin muxer settings */ static const struct pinmux_config spi1_pins[] = { { pinmux(5), 1, 1 }, diff --git a/board/davinci/da8xxevm/hawkboard_nand_spl.c b/board/davinci/da8xxevm/hawkboard_nand_spl.c index 32b17ce..0fdccac 100644 --- a/board/davinci/da8xxevm/hawkboard_nand_spl.c +++ b/board/davinci/da8xxevm/hawkboard_nand_spl.c @@ -32,8 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) - static const struct pinmux_config mii_pins[] = { { pinmux(2), 8, 1 }, { pinmux(2), 8, 2 }, diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index 720a360..9b6c4c0 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -40,8 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) - static const struct da8xx_panel lcd_panel = { /* Casio COM57H531x */ .name = "Casio_COM57H531x", diff --git a/nand_spl/board/davinci/da8xxevm/Makefile b/nand_spl/board/davinci/da8xxevm/Makefile index accf716..7b06cd2 100644 --- a/nand_spl/board/davinci/da8xxevm/Makefile +++ b/nand_spl/board/davinci/da8xxevm/Makefile @@ -42,7 +42,7 @@ SOBJS = _divsi3.o \ COBJS = cpu.o \ davinci_nand.o \ - davinci_pinmux.o \ + pinmux.o \ div0.o \ hawkboard_nand_spl.o \ memsize.o \ @@ -78,9 +78,9 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # create symbolic links for common files # from board directory -$(obj)davinci_pinmux.c: +$(obj)pinmux.c: @rm -f $@ - @ln -s $(TOPDIR)/board/davinci/common/davinci_pinmux.c $@ + @ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/pinmux.c $@ # from drivers/mtd/nand directory $(obj)davinci_nand.c: -- cgit v0.10.2 From e5b9aa9e9c0bdd536177e8ab8071be30d2a0e7d9 Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Mon, 28 Nov 2011 23:46:15 +0000 Subject: arm, hawkboard: Remove obsolete struct pinmux_config i2c_pins The configuration in struct pinmux_config i2c_pins does not configure the pins for i2c but for uart. Since this function is already configured by struct pinmux_config uart2_pins the i2c_pins struct is obsolete. Signed-off-by: Christian Riesch Cc: Heiko Schocher Cc: Syed Mohammed Khasim Cc: Sughosh Ganu Cc: Sandeep Paulraj Acked-by: Heiko Schocher diff --git a/board/davinci/da8xxevm/hawkboard_nand_spl.c b/board/davinci/da8xxevm/hawkboard_nand_spl.c index 0fdccac..fd130fa 100644 --- a/board/davinci/da8xxevm/hawkboard_nand_spl.c +++ b/board/davinci/da8xxevm/hawkboard_nand_spl.c @@ -71,15 +71,9 @@ static const struct pinmux_config uart2_pins[] = { { pinmux(4), 2, 5 } }; -static const struct pinmux_config i2c_pins[] = { - { pinmux(4), 2, 4 }, - { pinmux(4), 2, 5 } -}; - static const struct pinmux_resource pinmuxes[] = { PINMUX_ITEM(mii_pins), PINMUX_ITEM(mdio_pins), - PINMUX_ITEM(i2c_pins), PINMUX_ITEM(nand_pins), PINMUX_ITEM(uart2_pins), }; -- cgit v0.10.2 From 591d8019a13f1104f87257071ee9d934a7f4a4fe Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Mon, 28 Nov 2011 23:46:16 +0000 Subject: arm, da850evm: Do pinmux configuration for EMAC together with other pinmuxes Pinmux configuration for the EMAC was done in a separate call of davinci_configure_pin_mux(). This patch moves all the pinmux configuration that is done for this board to a common place. Signed-off-by: Christian Riesch Cc: Heiko Schocher Cc: Sandeep Paulraj Cc: Sudhakar Rajashekhara Acked-by: Heiko Schocher diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 844e585..9b68c5c 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -223,6 +223,9 @@ int misc_init_r(void) } static const struct pinmux_resource pinmuxes[] = { +#ifdef CONFIG_DRIVER_TI_EMAC + PINMUX_ITEM(emac_pins), +#endif #ifdef CONFIG_SPI_FLASH PINMUX_ITEM(spi1_pins), #endif @@ -344,9 +347,6 @@ int board_init(void) #endif #ifdef CONFIG_DRIVER_TI_EMAC - if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) - return 1; - davinci_emac_mii_mode_sel(HAS_RMII); #endif /* CONFIG_DRIVER_TI_EMAC */ -- cgit v0.10.2 From 516fb1c4c02d4e103a382dd9b0e1ada02fd389cd Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Mon, 28 Nov 2011 23:46:17 +0000 Subject: arm, da850: Add pinmux configurations to the arch tree Up to now nearly every davinci board has separate code for the definition of pinmux configurations. This patch adds pinmux configurations for the DA850 SoCs to the arch tree which may later be used for all DA850 based boards. Signed-off-by: Christian Riesch Cc: Sandeep Paulraj Cc: Heiko Schocher Cc: Mike Frysinger Acked-by: Heiko Schocher diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index 2105ec5..4ac187a 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM365) += dm365.o COBJS-$(CONFIG_SOC_DM644X) += dm644x.o COBJS-$(CONFIG_SOC_DM646X) += dm646x.o +COBJS-$(CONFIG_SOC_DA850) += da850_pinmux.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c new file mode 100644 index 0000000..a3472ea --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c @@ -0,0 +1,166 @@ +/* + * Pinmux configurations for the DA850 SoCs + * + * Copyright (C) 2011 OMICRON electronics GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +/* SPI pin muxer settings */ +const struct pinmux_config spi1_pins_base[] = { + { pinmux(5), 1, 2 }, /* SPI1_CLK */ + { pinmux(5), 1, 4 }, /* SPI1_SOMI */ + { pinmux(5), 1, 5 }, /* SPI1_SIMO */ +}; + +const struct pinmux_config spi1_pins_scs0[] = { + { pinmux(5), 1, 1 }, /* SPI1_SCS[0] */ +}; + +/* UART pin muxer settings */ +const struct pinmux_config uart2_pins_txrx[] = { + { pinmux(4), 2, 4 }, /* UART2_RXD */ + { pinmux(4), 2, 5 }, /* UART2_TXD */ +}; + +const struct pinmux_config uart2_pins_rtscts[] = { + { pinmux(0), 4, 6 }, /* UART2_RTS */ + { pinmux(0), 4, 7 }, /* UART2_CTS */ +}; + +/* EMAC pin muxer settings*/ +const struct pinmux_config emac_pins_rmii[] = { + { pinmux(14), 8, 2 }, /* RMII_TXD[1] */ + { pinmux(14), 8, 3 }, /* RMII_TXD[0] */ + { pinmux(14), 8, 4 }, /* RMII_TXEN */ + { pinmux(14), 8, 5 }, /* RMII_RXD[1] */ + { pinmux(14), 8, 6 }, /* RMII_RXD[0] */ + { pinmux(14), 8, 7 }, /* RMII_RXER */ + { pinmux(15), 8, 1 }, /* RMII_CRS_DV */ +}; + +const struct pinmux_config emac_pins_mii[] = { + { pinmux(2), 8, 1 }, /* MII_TXEN */ + { pinmux(2), 8, 2 }, /* MII_TXCLK */ + { pinmux(2), 8, 3 }, /* MII_COL */ + { pinmux(2), 8, 4 }, /* MII_TXD[3] */ + { pinmux(2), 8, 5 }, /* MII_TXD[2] */ + { pinmux(2), 8, 6 }, /* MII_TXD[1] */ + { pinmux(2), 8, 7 }, /* MII_TXD[0] */ + { pinmux(3), 8, 0 }, /* MII_RXCLK */ + { pinmux(3), 8, 1 }, /* MII_RXDV */ + { pinmux(3), 8, 2 }, /* MII_RXER */ + { pinmux(3), 8, 3 }, /* MII_CRS */ + { pinmux(3), 8, 4 }, /* MII_RXD[3] */ + { pinmux(3), 8, 5 }, /* MII_RXD[2] */ + { pinmux(3), 8, 6 }, /* MII_RXD[1] */ + { pinmux(3), 8, 7 }, /* MII_RXD[0] */ +}; + +const struct pinmux_config emac_pins_mdio[] = { + { pinmux(4), 8, 0 }, /* MDIO_CLK */ + { pinmux(4), 8, 1 }, /* MDIO_D */ +}; + +/* I2C pin muxer settings */ +const struct pinmux_config i2c0_pins[] = { + { pinmux(4), 2, 2 }, /* I2C0_SCL */ + { pinmux(4), 2, 3 }, /* I2C0_SDA */ +}; + +const struct pinmux_config i2c1_pins[] = { + { pinmux(4), 4, 4 }, /* I2C1_SCL */ + { pinmux(4), 4, 5 }, /* I2C1_SDA */ +}; + +/* EMIFA pin muxer settings */ +const struct pinmux_config emifa_pins_cs2[] = { + { pinmux(7), 1, 0 }, /* EMA_CS2 */ +}; + +const struct pinmux_config emifa_pins_cs3[] = { + { pinmux(7), 1, 1 }, /* EMA_CS[3] */ +}; + +const struct pinmux_config emifa_pins_cs4[] = { + { pinmux(7), 1, 2 }, /* EMA_CS[4] */ +}; + +const struct pinmux_config emifa_pins_nand[] = { + { pinmux(7), 1, 4 }, /* EMA_WE */ + { pinmux(7), 1, 5 }, /* EMA_OE */ + { pinmux(9), 1, 0 }, /* EMA_D[7] */ + { pinmux(9), 1, 1 }, /* EMA_D[6] */ + { pinmux(9), 1, 2 }, /* EMA_D[5] */ + { pinmux(9), 1, 3 }, /* EMA_D[4] */ + { pinmux(9), 1, 4 }, /* EMA_D[3] */ + { pinmux(9), 1, 5 }, /* EMA_D[2] */ + { pinmux(9), 1, 6 }, /* EMA_D[1] */ + { pinmux(9), 1, 7 }, /* EMA_D[0] */ + { pinmux(12), 1, 5 }, /* EMA_A[2] */ + { pinmux(12), 1, 6 }, /* EMA_A[1] */ +}; + +/* NOR pin muxer settings */ +const struct pinmux_config emifa_pins_nor[] = { + { pinmux(5), 1, 6 }, /* EMA_BA[1] */ + { pinmux(6), 1, 6 }, /* EMA_WAIT[1] */ + { pinmux(7), 1, 4 }, /* EMA_WE */ + { pinmux(7), 1, 5 }, /* EMA_OE */ + { pinmux(8), 1, 0 }, /* EMA_D[15] */ + { pinmux(8), 1, 1 }, /* EMA_D[14] */ + { pinmux(8), 1, 2 }, /* EMA_D[13] */ + { pinmux(8), 1, 3 }, /* EMA_D[12] */ + { pinmux(8), 1, 4 }, /* EMA_D[11] */ + { pinmux(8), 1, 5 }, /* EMA_D[10] */ + { pinmux(8), 1, 6 }, /* EMA_D[9] */ + { pinmux(8), 1, 7 }, /* EMA_D[8] */ + { pinmux(9), 1, 0 }, /* EMA_D[7] */ + { pinmux(9), 1, 1 }, /* EMA_D[6] */ + { pinmux(9), 1, 2 }, /* EMA_D[5] */ + { pinmux(9), 1, 3 }, /* EMA_D[4] */ + { pinmux(9), 1, 4 }, /* EMA_D[3] */ + { pinmux(9), 1, 5 }, /* EMA_D[2] */ + { pinmux(9), 1, 6 }, /* EMA_D[1] */ + { pinmux(9), 1, 7 }, /* EMA_D[0] */ + { pinmux(10), 1, 1 }, /* EMA_A[22] */ + { pinmux(10), 1, 2 }, /* EMA_A[21] */ + { pinmux(10), 1, 3 }, /* EMA_A[20] */ + { pinmux(10), 1, 4 }, /* EMA_A[19] */ + { pinmux(10), 1, 5 }, /* EMA_A[18] */ + { pinmux(10), 1, 6 }, /* EMA_A[17] */ + { pinmux(10), 1, 7 }, /* EMA_A[16] */ + { pinmux(11), 1, 0 }, /* EMA_A[15] */ + { pinmux(11), 1, 1 }, /* EMA_A[14] */ + { pinmux(11), 1, 2 }, /* EMA_A[13] */ + { pinmux(11), 1, 3 }, /* EMA_A[12] */ + { pinmux(11), 1, 4 }, /* EMA_A[11] */ + { pinmux(11), 1, 5 }, /* EMA_A[10] */ + { pinmux(11), 1, 6 }, /* EMA_A[9] */ + { pinmux(11), 1, 7 }, /* EMA_A[8] */ + { pinmux(12), 1, 0 }, /* EMA_A[7] */ + { pinmux(12), 1, 1 }, /* EMA_A[6] */ + { pinmux(12), 1, 2 }, /* EMA_A[5] */ + { pinmux(12), 1, 3 }, /* EMA_A[4] */ + { pinmux(12), 1, 4 }, /* EMA_A[3] */ + { pinmux(12), 1, 5 }, /* EMA_A[2] */ + { pinmux(12), 1, 6 }, /* EMA_A[1] */ + { pinmux(12), 1, 7 }, /* EMA_A[0] */ +}; diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/include/asm/arch-davinci/pinmux_defs.h new file mode 100644 index 0000000..191494b --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h @@ -0,0 +1,50 @@ +/* + * Pinmux configurations for the DAxxx SoCs + * + * Copyright (C) 2011 OMICRON electronics GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_PINMUX_DEFS_H +#define __ASM_ARCH_PINMUX_DEFS_H + +#include + +/* SPI pin muxer settings */ +extern const struct pinmux_config spi1_pins_base[3]; +extern const struct pinmux_config spi1_pins_scs0[1]; + +/* UART pin muxer settings */ +extern const struct pinmux_config uart2_pins_txrx[2]; +extern const struct pinmux_config uart2_pins_rtscts[2]; + +/* EMAC pin muxer settings*/ +extern const struct pinmux_config emac_pins_rmii[7]; +extern const struct pinmux_config emac_pins_mii[15]; +extern const struct pinmux_config emac_pins_mdio[2]; + +/* I2C pin muxer settings */ +extern const struct pinmux_config i2c0_pins[2]; +extern const struct pinmux_config i2c1_pins[2]; + +/* EMIFA pin muxer settings */ +extern const struct pinmux_config emifa_pins_cs2[1]; +extern const struct pinmux_config emifa_pins_cs3[1]; +extern const struct pinmux_config emifa_pins_cs4[1]; +extern const struct pinmux_config emifa_pins_nand[12]; +extern const struct pinmux_config emifa_pins_nor[43]; + +#endif -- cgit v0.10.2 From 52b0f877a271c0e5b43cc0753c25b2b944ea7dcd Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Mon, 28 Nov 2011 23:46:18 +0000 Subject: arm, da850evm: Use the pinmux configurations defined in the arch tree The boards in board/davinci/da8xxevm/ define pinmux_config[] vectors that contain pinmux configurations for emac, uarts, memory controllers... In an earlier patch such pinmux configurations were added to the arch tree. This patch makes the da850evm use these definitions instead of defining its own. Signed-off-by: Christian Riesch Cc: Sandeep Paulraj Cc: Heiko Schocher Cc: Sudhakar Rajashekhara Cc: Mike Frysinger Acked-by: Heiko Schocher diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 9b68c5c..e827256 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -28,135 +28,14 @@ #include #include #include +#include #include #include #include DECLARE_GLOBAL_DATA_PTR; -/* SPI0 pin muxer settings */ -static const struct pinmux_config spi1_pins[] = { - { pinmux(5), 1, 1 }, - { pinmux(5), 1, 2 }, - { pinmux(5), 1, 4 }, - { pinmux(5), 1, 5 } -}; - -/* UART pin muxer settings */ -static const struct pinmux_config uart_pins[] = { - { pinmux(0), 4, 6 }, - { pinmux(0), 4, 7 }, - { pinmux(4), 2, 4 }, - { pinmux(4), 2, 5 } -}; - #ifdef CONFIG_DRIVER_TI_EMAC -static const struct pinmux_config emac_pins[] = { -#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII - { pinmux(14), 8, 2 }, - { pinmux(14), 8, 3 }, - { pinmux(14), 8, 4 }, - { pinmux(14), 8, 5 }, - { pinmux(14), 8, 6 }, - { pinmux(14), 8, 7 }, - { pinmux(15), 8, 1 }, -#else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */ - { pinmux(2), 8, 1 }, - { pinmux(2), 8, 2 }, - { pinmux(2), 8, 3 }, - { pinmux(2), 8, 4 }, - { pinmux(2), 8, 5 }, - { pinmux(2), 8, 6 }, - { pinmux(2), 8, 7 }, - { pinmux(3), 8, 0 }, - { pinmux(3), 8, 1 }, - { pinmux(3), 8, 2 }, - { pinmux(3), 8, 3 }, - { pinmux(3), 8, 4 }, - { pinmux(3), 8, 5 }, - { pinmux(3), 8, 6 }, - { pinmux(3), 8, 7 }, -#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ - { pinmux(4), 8, 0 }, - { pinmux(4), 8, 1 } -}; - -/* I2C pin muxer settings */ -static const struct pinmux_config i2c_pins[] = { - { pinmux(4), 2, 2 }, - { pinmux(4), 2, 3 } -}; - -#ifdef CONFIG_NAND_DAVINCI -const struct pinmux_config nand_pins[] = { - { pinmux(7), 1, 1 }, - { pinmux(7), 1, 2 }, - { pinmux(7), 1, 4 }, - { pinmux(7), 1, 5 }, - { pinmux(9), 1, 0 }, - { pinmux(9), 1, 1 }, - { pinmux(9), 1, 2 }, - { pinmux(9), 1, 3 }, - { pinmux(9), 1, 4 }, - { pinmux(9), 1, 5 }, - { pinmux(9), 1, 6 }, - { pinmux(9), 1, 7 }, - { pinmux(12), 1, 5 }, - { pinmux(12), 1, 6 } -}; -#elif defined(CONFIG_USE_NOR) -/* NOR pin muxer settings */ -const struct pinmux_config nor_pins[] = { - /* GP0[11] is required for NOR to work on Rev 3 EVMs */ - { pinmux(0), 8, 4 }, /* GP0[11] */ - { pinmux(5), 1, 6 }, - { pinmux(6), 1, 6 }, - { pinmux(7), 1, 0 }, - { pinmux(7), 1, 4 }, - { pinmux(7), 1, 5 }, - { pinmux(8), 1, 0 }, - { pinmux(8), 1, 1 }, - { pinmux(8), 1, 2 }, - { pinmux(8), 1, 3 }, - { pinmux(8), 1, 4 }, - { pinmux(8), 1, 5 }, - { pinmux(8), 1, 6 }, - { pinmux(8), 1, 7 }, - { pinmux(9), 1, 0 }, - { pinmux(9), 1, 1 }, - { pinmux(9), 1, 2 }, - { pinmux(9), 1, 3 }, - { pinmux(9), 1, 4 }, - { pinmux(9), 1, 5 }, - { pinmux(9), 1, 6 }, - { pinmux(9), 1, 7 }, - { pinmux(10), 1, 0 }, - { pinmux(10), 1, 1 }, - { pinmux(10), 1, 2 }, - { pinmux(10), 1, 3 }, - { pinmux(10), 1, 4 }, - { pinmux(10), 1, 5 }, - { pinmux(10), 1, 6 }, - { pinmux(10), 1, 7 }, - { pinmux(11), 1, 0 }, - { pinmux(11), 1, 1 }, - { pinmux(11), 1, 2 }, - { pinmux(11), 1, 3 }, - { pinmux(11), 1, 4 }, - { pinmux(11), 1, 5 }, - { pinmux(11), 1, 6 }, - { pinmux(11), 1, 7 }, - { pinmux(12), 1, 0 }, - { pinmux(12), 1, 1 }, - { pinmux(12), 1, 2 }, - { pinmux(12), 1, 3 }, - { pinmux(12), 1, 4 }, - { pinmux(12), 1, 5 }, - { pinmux(12), 1, 6 }, - { pinmux(12), 1, 7 } -}; -#endif - #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII #define HAS_RMII 1 #else @@ -222,20 +101,38 @@ int misc_init_r(void) return 0; } +static const struct pinmux_config gpio_pins[] = { +#ifdef CONFIG_USE_NOR + /* GP0[11] is required for NOR to work on Rev 3 EVMs */ + { pinmux(0), 8, 4 }, /* GP0[11] */ +#endif +}; + static const struct pinmux_resource pinmuxes[] = { #ifdef CONFIG_DRIVER_TI_EMAC - PINMUX_ITEM(emac_pins), + PINMUX_ITEM(emac_pins_mdio), +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII + PINMUX_ITEM(emac_pins_rmii), +#else + PINMUX_ITEM(emac_pins_mii), +#endif #endif #ifdef CONFIG_SPI_FLASH - PINMUX_ITEM(spi1_pins), + PINMUX_ITEM(spi1_pins_base), + PINMUX_ITEM(spi1_pins_scs0), #endif - PINMUX_ITEM(uart_pins), - PINMUX_ITEM(i2c_pins), + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(uart2_pins_rtscts), + PINMUX_ITEM(i2c0_pins), #ifdef CONFIG_NAND_DAVINCI - PINMUX_ITEM(nand_pins), + PINMUX_ITEM(emifa_pins_cs3), + PINMUX_ITEM(emifa_pins_cs4), + PINMUX_ITEM(emifa_pins_nand), #elif defined(CONFIG_USE_NOR) - PINMUX_ITEM(nor_pins), + PINMUX_ITEM(emifa_pins_cs2), + PINMUX_ITEM(emifa_pins_nor), #endif + PINMUX_ITEM(gpio_pins), }; static const struct lpsc_resource lpsc[] = { diff --git a/include/configs/da850_am18xxevm.h b/include/configs/da850_am18xxevm.h index 92b83ff..2885ece 100644 --- a/include/configs/da850_am18xxevm.h +++ b/include/configs/da850_am18xxevm.h @@ -36,6 +36,7 @@ #define CONFIG_MACH_DAVINCI_DA850_EVM #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 4c14370..2e2aa19 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -36,6 +36,7 @@ #define CONFIG_MACH_DAVINCI_DA850_EVM #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -- cgit v0.10.2 From e8c856d28814a4ee52c84f3c7a92bb8c561a9b4c Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Mon, 28 Nov 2011 23:46:19 +0000 Subject: arm, hawkboard: Use the pinmux configurations defined in the arch tree The boards in board/davinci/da8xxevm/ define pinmux_config[] vectors that contain pinmux configurations for emac, uarts, memory controllers... In an earlier patch such pinmux configurations were added to the arch tree. This patch makes the hawkboard use these definitions instead of defining its own. Signed-off-by: Christian Riesch Cc: Sandeep Paulraj Cc: Heiko Schocher Cc: Syed Mohammed Khasim Cc: Sughosh Ganu Cc: Mike Frysinger Acked-by: Heiko Schocher diff --git a/board/davinci/da8xxevm/hawkboard_nand_spl.c b/board/davinci/da8xxevm/hawkboard_nand_spl.c index fd130fa..df97963 100644 --- a/board/davinci/da8xxevm/hawkboard_nand_spl.c +++ b/board/davinci/da8xxevm/hawkboard_nand_spl.c @@ -27,55 +27,20 @@ #include #include #include +#include #include #include DECLARE_GLOBAL_DATA_PTR; -static const struct pinmux_config mii_pins[] = { - { pinmux(2), 8, 1 }, - { pinmux(2), 8, 2 }, - { pinmux(2), 8, 3 }, - { pinmux(2), 8, 4 }, - { pinmux(2), 8, 5 }, - { pinmux(2), 8, 6 }, - { pinmux(2), 8, 7 } -}; - -static const struct pinmux_config mdio_pins[] = { - { pinmux(4), 8, 0 }, - { pinmux(4), 8, 1 } -}; - -static const struct pinmux_config nand_pins[] = { - { pinmux(7), 1, 1 }, - { pinmux(7), 1, 2 }, - { pinmux(7), 1, 4 }, - { pinmux(7), 1, 5 }, - { pinmux(9), 1, 0 }, - { pinmux(9), 1, 1 }, - { pinmux(9), 1, 2 }, - { pinmux(9), 1, 3 }, - { pinmux(9), 1, 4 }, - { pinmux(9), 1, 5 }, - { pinmux(9), 1, 6 }, - { pinmux(9), 1, 7 }, - { pinmux(12), 1, 5 }, - { pinmux(12), 1, 6 } -}; - -static const struct pinmux_config uart2_pins[] = { - { pinmux(0), 4, 6 }, - { pinmux(0), 4, 7 }, - { pinmux(4), 2, 4 }, - { pinmux(4), 2, 5 } -}; - static const struct pinmux_resource pinmuxes[] = { - PINMUX_ITEM(mii_pins), - PINMUX_ITEM(mdio_pins), - PINMUX_ITEM(nand_pins), - PINMUX_ITEM(uart2_pins), + PINMUX_ITEM(emac_pins_mii), + PINMUX_ITEM(emac_pins_mdio), + PINMUX_ITEM(emifa_pins_cs3), + PINMUX_ITEM(emifa_pins_cs4), + PINMUX_ITEM(emifa_pins_nand), + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(uart2_pins_rtscts), }; static const struct lpsc_resource lpsc[] = { diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h index 638643a..12acb27 100644 --- a/include/configs/hawkboard.h +++ b/include/configs/hawkboard.h @@ -34,6 +34,7 @@ #define CONFIG_MACH_DAVINCI_HAWK #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE diff --git a/nand_spl/board/davinci/da8xxevm/Makefile b/nand_spl/board/davinci/da8xxevm/Makefile index 7b06cd2..616e6f1 100644 --- a/nand_spl/board/davinci/da8xxevm/Makefile +++ b/nand_spl/board/davinci/da8xxevm/Makefile @@ -43,6 +43,7 @@ SOBJS = _divsi3.o \ COBJS = cpu.o \ davinci_nand.o \ pinmux.o \ + da850_pinmux.o \ div0.o \ hawkboard_nand_spl.o \ memsize.o \ @@ -82,6 +83,10 @@ $(obj)pinmux.c: @rm -f $@ @ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/pinmux.c $@ +$(obj)da850_pinmux.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c $@ + # from drivers/mtd/nand directory $(obj)davinci_nand.c: @rm -f $@ -- cgit v0.10.2 From 65204715bda949543278cf994c7ffdb7fe909f6f Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Mon, 28 Nov 2011 23:46:20 +0000 Subject: arm, davinci: Remove duplication of pinmux configuration code This patch replaces the pinmux configuration code in arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c by the code from arch/arm/cpu/arm926ejs/davinci/pinmux.c. Signed-off-by: Christian Riesch Cc: Sandeep Paulraj Acked-by: Heiko Schocher diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c index c7ec70f..a532f8a 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -235,19 +236,16 @@ int da850_ddr_setup(void) return 0; } -void da850_pinmux_ctl(unsigned long offset, unsigned long mask, - unsigned long value) -{ - clrbits_le32(&davinci_syscfg_regs->pinmux[offset], mask); - setbits_le32(&davinci_syscfg_regs->pinmux[offset], (mask & value)); -} - __attribute__((weak)) void board_gpio_init(void) { return; } +/* pinmux_resource[] vector is defined in the board specific file */ +extern const struct pinmux_resource pinmuxes[]; +extern const int pinmuxes_size; + int arch_cpu_init(void) { /* Unlock kick registers */ @@ -257,27 +255,9 @@ int arch_cpu_init(void) dv_maskbits(&davinci_syscfg_regs->suspsrc, CONFIG_SYS_DA850_SYSCFG_SUSPSRC); - /* Setup Pinmux */ - da850_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX0); - da850_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX1); - da850_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX2); - da850_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX3); - da850_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX4); - da850_pinmux_ctl(5, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX5); - da850_pinmux_ctl(6, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX6); - da850_pinmux_ctl(7, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX7); - da850_pinmux_ctl(8, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX8); - da850_pinmux_ctl(9, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX9); - da850_pinmux_ctl(10, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX10); - da850_pinmux_ctl(11, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX11); - da850_pinmux_ctl(12, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX12); - da850_pinmux_ctl(13, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX13); - da850_pinmux_ctl(14, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX14); - da850_pinmux_ctl(15, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX15); - da850_pinmux_ctl(16, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX16); - da850_pinmux_ctl(17, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX17); - da850_pinmux_ctl(18, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX18); - da850_pinmux_ctl(19, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX19); + /* configure pinmux settings */ + if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size)) + return 1; /* PLL setup */ da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM); -- cgit v0.10.2 From b5ce18a235b9b7064575a817576a8aa2c64f30ac Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 29 Nov 2011 02:33:43 +0000 Subject: arm, davinci: move davinci_rtc struct to hardware.h move struct davinci_rtc to arch/arm/include/asm/arch-davinci/hardware.h and add RTC_KICK0R_WE, RTC_KICK1R_WE defines, so they are global useable. Signed-off-by: Heiko Schocher Cc: Sandeep Paulraj diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 06819a6..dd89e84 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -588,4 +588,43 @@ static inline int get_async3_src(void) #include #include #endif + +struct davinci_rtc { + dv_reg second; + dv_reg minutes; + dv_reg hours; + dv_reg day; + dv_reg month; /* 0x10 */ + dv_reg year; + dv_reg dotw; + dv_reg resv1; + dv_reg alarmsecond; /* 0x20 */ + dv_reg alarmminute; + dv_reg alarmhour; + dv_reg alarmday; + dv_reg alarmmonth; /* 0x30 */ + dv_reg alarmyear; + dv_reg resv2[2]; + dv_reg ctrl; /* 0x40 */ + dv_reg status; + dv_reg irq; + dv_reg complsb; + dv_reg compmsb; /* 0x50 */ + dv_reg osc; + dv_reg resv3[2]; + dv_reg scratch0; /* 0x60 */ + dv_reg scratch1; + dv_reg scratch2; + dv_reg kick0r; + dv_reg kick1r; /* 0x70 */ +}; + +#define RTC_STATE_BUSY 0x01 +#define RTC_STATE_RUN 0x02 + +#define RTC_KICK0R_WE 0x130be783 +#define RTC_KICK1R_WE 0xe0f1a495 + +#define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE) + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c index 8436cbf..5cafff4 100644 --- a/drivers/rtc/davinci.c +++ b/drivers/rtc/davinci.c @@ -27,32 +27,6 @@ #include #if defined(CONFIG_CMD_DATE) -struct davinci_rtc { - u_int32_t second; - u_int32_t minutes; - u_int32_t hours; - u_int32_t day; - u_int32_t month; /* 0x10 */ - u_int32_t year; - u_int32_t dotw; - u_int32_t resv1; - u_int32_t alarmsecond; /* 0x20 */ - u_int32_t alarmminute; - u_int32_t alarmhour; - u_int32_t alarmday; - u_int32_t alarmmonth; /* 0x30 */ - u_int32_t alarmyear; - u_int32_t resv2[2]; - u_int32_t ctrl; /* 0x40 */ - u_int32_t status; - u_int32_t irq; -}; - -#define RTC_STATE_BUSY 0x01 -#define RTC_STATE_RUN 0x02 - -#define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE) - int rtc_get(struct rtc_time *tmp) { struct davinci_rtc *rtc = davinci_rtc_base; -- cgit v0.10.2 From 7f34b1163a4b5be319d5b87a8027bdab7c765e93 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 29 Nov 2011 02:33:44 +0000 Subject: arm, davinci, da850: add uart1 tx rx pinmux config Signed-off-by: Heiko Schocher Acked-by: Tom Rini Cc: Sandeep Paulraj Cc: Tom Rini Cc: Albert ARIBAUD Cc: Christian Riesch diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c index a3472ea..fa07fb5 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c @@ -35,6 +35,11 @@ const struct pinmux_config spi1_pins_scs0[] = { }; /* UART pin muxer settings */ +const struct pinmux_config uart1_pins_txrx[] = { + { pinmux(4), 2, 6 }, /* UART1_RXD */ + { pinmux(4), 2, 7 }, /* UART1_TXD */ +}; + const struct pinmux_config uart2_pins_txrx[] = { { pinmux(4), 2, 4 }, /* UART2_RXD */ { pinmux(4), 2, 5 }, /* UART2_TXD */ diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/include/asm/arch-davinci/pinmux_defs.h index 191494b..07aceaa 100644 --- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h +++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h @@ -28,6 +28,7 @@ extern const struct pinmux_config spi1_pins_base[3]; extern const struct pinmux_config spi1_pins_scs0[1]; /* UART pin muxer settings */ +extern const struct pinmux_config uart1_pins_txrx[2]; extern const struct pinmux_config uart2_pins_txrx[2]; extern const struct pinmux_config uart2_pins_rtscts[2]; -- cgit v0.10.2 From 8a73e561fe7a357d51f00e86eb9853d7e7f803dc Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 29 Nov 2011 02:33:45 +0000 Subject: arm, board/davinci/common/misc.c: Codingstyle cleanup Signed-off-by: Heiko Schocher Cc: Sandeep Paulraj Cc: Tom Rini Cc: Albert ARIBAUD Cc: Christian Riesch diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c index 5aa7605..5f510b6 100644 --- a/board/davinci/common/misc.c +++ b/board/davinci/common/misc.c @@ -51,16 +51,16 @@ void dram_init_banksize(void) #endif #ifdef CONFIG_DRIVER_TI_EMAC - -/* Read ethernet MAC address from EEPROM for DVEVM compatible boards. +/* + * Read ethernet MAC address from EEPROM for DVEVM compatible boards. * Returns 1 if found, 0 otherwise. */ int dvevm_read_mac_address(uint8_t *buf) { #ifdef CONFIG_SYS_I2C_EEPROM_ADDR /* Read MAC address. */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (uint8_t *) &buf[0], 6)) + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6)) goto i2cerr; /* Check that MAC address is valid. */ @@ -70,7 +70,8 @@ int dvevm_read_mac_address(uint8_t *buf) return 1; /* Found */ i2cerr: - printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR); + printf("Read from EEPROM @ 0x%02x failed\n", + CONFIG_SYS_I2C_EEPROM_ADDR); err: #endif /* CONFIG_SYS_I2C_EEPROM_ADDR */ @@ -103,15 +104,16 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { - /* There is no MAC address in the environment, so we initialize - * it from the value in the EEPROM. */ + /* + * There is no MAC address in the environment, so we + * initialize it from the value in the EEPROM. + */ debug("### Setting environment from EEPROM MAC address = " "\"%pM\"\n", env_enetaddr); eth_setenv_enetaddr("ethaddr", rom_enetaddr); } } - #endif /* CONFIG_DRIVER_TI_EMAC */ #if defined(CONFIG_SOC_DA8XX) @@ -122,7 +124,6 @@ void irq_init(void) * Mask all IRQs by clearing the global enable and setting * the enable clear for all the 90 interrupts. */ - writel(0, &davinci_aintc_regs->ger); writel(0, &davinci_aintc_regs->hier); -- cgit v0.10.2 From 5b51e7f3ca36f1ba445f9079835bf66304e16562 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 29 Nov 2011 02:33:46 +0000 Subject: arm, davinci: move misc function in arch tree move the board/davinci/common/misc.c file to arch/arm/cpu/arm926ejs/davinci/misc.c, so all davinci boards can use this functions. Signed-off-by: Heiko Schocher Cc: Sandeep Paulraj Cc: Tom Rini Cc: Albert ARIBAUD Cc: Christian Riesch diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index 4ac187a..5ae89df 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS-y += cpu.o timer.o psc.o pinmux.o +COBJS-y += cpu.o misc.o timer.o psc.o pinmux.o COBJS-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM365) += dm365.o diff --git a/arch/arm/cpu/arm926ejs/davinci/misc.c b/arch/arm/cpu/arm926ejs/davinci/misc.c new file mode 100644 index 0000000..5f510b6 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/misc.c @@ -0,0 +1,150 @@ +/* + * Miscelaneous DaVinci functions. + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, + * Copyright (C) 2007 Sergey Kubushyn + * Copyright (C) 2008 Lyrtech + * Copyright (C) 2004 Texas Instruments. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SPL_BUILD +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_RAM_BANK_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} +#endif + +#ifdef CONFIG_DRIVER_TI_EMAC +/* + * Read ethernet MAC address from EEPROM for DVEVM compatible boards. + * Returns 1 if found, 0 otherwise. + */ +int dvevm_read_mac_address(uint8_t *buf) +{ +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR + /* Read MAC address. */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6)) + goto i2cerr; + + /* Check that MAC address is valid. */ + if (!is_valid_ether_addr(buf)) + goto err; + + return 1; /* Found */ + +i2cerr: + printf("Read from EEPROM @ 0x%02x failed\n", + CONFIG_SYS_I2C_EEPROM_ADDR); +err: +#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */ + + return 0; +} + +/* + * Set the mii mode as MII or RMII + */ +#if defined(CONFIG_SOC_DA8XX) +void davinci_emac_mii_mode_sel(int mode_sel) +{ + int val; + + val = readl(&davinci_syscfg_regs->cfgchip3); + if (mode_sel == 0) + val &= ~(1 << 8); + else + val |= (1 << 8); + writel(val, &davinci_syscfg_regs->cfgchip3); +} +#endif +/* + * If there is no MAC address in the environment, then it will be initialized + * (silently) from the value in the EEPROM. + */ +void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) +{ + uint8_t env_enetaddr[6]; + + eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); + if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { + /* + * There is no MAC address in the environment, so we + * initialize it from the value in the EEPROM. + */ + debug("### Setting environment from EEPROM MAC address = " + "\"%pM\"\n", + env_enetaddr); + eth_setenv_enetaddr("ethaddr", rom_enetaddr); + } +} +#endif /* CONFIG_DRIVER_TI_EMAC */ + +#if defined(CONFIG_SOC_DA8XX) +#ifndef CONFIG_USE_IRQ +void irq_init(void) +{ + /* + * Mask all IRQs by clearing the global enable and setting + * the enable clear for all the 90 interrupts. + */ + writel(0, &davinci_aintc_regs->ger); + + writel(0, &davinci_aintc_regs->hier); + + writel(0xffffffff, &davinci_aintc_regs->ecr1); + writel(0xffffffff, &davinci_aintc_regs->ecr2); + writel(0xffffffff, &davinci_aintc_regs->ecr3); +} +#endif + +/* + * Enable PSC for various peripherals. + */ +int da8xx_configure_lpsc_items(const struct lpsc_resource *item, + const int n_items) +{ + int i; + + for (i = 0; i < n_items; i++) + lpsc_on(item[i].lpsc_no); + + return 0; +} +#endif diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c index 1351358..f438c15 100644 --- a/board/ait/cam_enc_4xx/cam_enc_4xx.c +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -36,21 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SPL_BUILD -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; -} - static struct davinci_timer *timer = (struct davinci_timer *)DAVINCI_TIMER3_BASE; diff --git a/board/davinci/common/Makefile b/board/davinci/common/Makefile deleted file mode 100644 index bc99da3..0000000 --- a/board/davinci/common/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)board/$(VENDOR)/common) -endif - -LIB = $(obj)lib$(VENDOR).o - -COBJS := misc.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c deleted file mode 100644 index 5f510b6..0000000 --- a/board/davinci/common/misc.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Miscelaneous DaVinci functions. - * - * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, - * Copyright (C) 2007 Sergey Kubushyn - * Copyright (C) 2008 Lyrtech - * Copyright (C) 2004 Texas Instruments. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SPL_BUILD -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; -} -#endif - -#ifdef CONFIG_DRIVER_TI_EMAC -/* - * Read ethernet MAC address from EEPROM for DVEVM compatible boards. - * Returns 1 if found, 0 otherwise. - */ -int dvevm_read_mac_address(uint8_t *buf) -{ -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR - /* Read MAC address. */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6)) - goto i2cerr; - - /* Check that MAC address is valid. */ - if (!is_valid_ether_addr(buf)) - goto err; - - return 1; /* Found */ - -i2cerr: - printf("Read from EEPROM @ 0x%02x failed\n", - CONFIG_SYS_I2C_EEPROM_ADDR); -err: -#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */ - - return 0; -} - -/* - * Set the mii mode as MII or RMII - */ -#if defined(CONFIG_SOC_DA8XX) -void davinci_emac_mii_mode_sel(int mode_sel) -{ - int val; - - val = readl(&davinci_syscfg_regs->cfgchip3); - if (mode_sel == 0) - val &= ~(1 << 8); - else - val |= (1 << 8); - writel(val, &davinci_syscfg_regs->cfgchip3); -} -#endif -/* - * If there is no MAC address in the environment, then it will be initialized - * (silently) from the value in the EEPROM. - */ -void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) -{ - uint8_t env_enetaddr[6]; - - eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); - if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { - /* - * There is no MAC address in the environment, so we - * initialize it from the value in the EEPROM. - */ - debug("### Setting environment from EEPROM MAC address = " - "\"%pM\"\n", - env_enetaddr); - eth_setenv_enetaddr("ethaddr", rom_enetaddr); - } -} -#endif /* CONFIG_DRIVER_TI_EMAC */ - -#if defined(CONFIG_SOC_DA8XX) -#ifndef CONFIG_USE_IRQ -void irq_init(void) -{ - /* - * Mask all IRQs by clearing the global enable and setting - * the enable clear for all the 90 interrupts. - */ - writel(0, &davinci_aintc_regs->ger); - - writel(0, &davinci_aintc_regs->hier); - - writel(0xffffffff, &davinci_aintc_regs->ecr1); - writel(0xffffffff, &davinci_aintc_regs->ecr2); - writel(0xffffffff, &davinci_aintc_regs->ecr3); -} -#endif - -/* - * Enable PSC for various peripherals. - */ -int da8xx_configure_lpsc_items(const struct lpsc_resource *item, - const int n_items) -{ - int i; - - for (i = 0; i < n_items; i++) - lpsc_on(item[i].lpsc_no); - - return 0; -} -#endif diff --git a/nand_spl/board/davinci/da8xxevm/Makefile b/nand_spl/board/davinci/da8xxevm/Makefile index 616e6f1..3783c18 100644 --- a/nand_spl/board/davinci/da8xxevm/Makefile +++ b/nand_spl/board/davinci/da8xxevm/Makefile @@ -127,15 +127,14 @@ $(obj)cpu.c: @rm -f $@ @ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/cpu.c $@ -# from board directory -$(obj)hawkboard_nand_spl.c: +$(obj)misc.c: @rm -f $@ - ln -s $(TOPDIR)/board/davinci/da8xxevm/hawkboard_nand_spl.c $@ + ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/misc.c $@ # from board directory -$(obj)misc.c: +$(obj)hawkboard_nand_spl.c: @rm -f $@ - ln -s $(TOPDIR)/board/davinci/common/misc.c $@ + ln -s $(TOPDIR)/board/davinci/da8xxevm/hawkboard_nand_spl.c $@ $(obj)psc.c: @rm -f $@ -- cgit v0.10.2 From f7264c36cde2d9423798fd7a93cd20698f426b44 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 29 Nov 2011 02:33:47 +0000 Subject: arm, davinci: add support for am1808 based enbw_cmc board - booting from NOR Flash with direct boot method - POST support - LOGBUF support Signed-off-by: Heiko Schocher Cc: Paulraj Sandeep Cc: Albert ARIBAUD Cc: Igor Grinberg Cc: Christian Riesch diff --git a/MAINTAINERS b/MAINTAINERS index 7d6c97e..2ecc664 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -812,6 +812,7 @@ Jens Scharsig Heiko Schocher + enbw_cmc ARM926EJS (AM1808 SoC) magnesium i.MX27 mgcoge3un ARM926EJS (Kirkwood SoC) diff --git a/board/enbw/enbw_cmc/Makefile b/board/enbw/enbw_cmc/Makefile new file mode 100644 index 0000000..cd1f0d4 --- /dev/null +++ b/board/enbw/enbw_cmc/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c new file mode 100644 index 0000000..5cd5357 --- /dev/null +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -0,0 +1,607 @@ +/* + * (C) Copyright 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on da830evm.c. Original Copyrights follow: + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct lpsc_resource lpsc[] = { + { DAVINCI_LPSC_AEMIF }, + { DAVINCI_LPSC_SPI1 }, + { DAVINCI_LPSC_ARM_RAM_ROM }, + { DAVINCI_LPSC_UART0 }, + { DAVINCI_LPSC_EMAC }, + { DAVINCI_LPSC_UART0 }, + { DAVINCI_LPSC_GPIO }, + { DAVINCI_LPSC_DDR_EMIF }, + { DAVINCI_LPSC_UART1 }, + { DAVINCI_LPSC_UART2 }, + { DAVINCI_LPSC_MMC_SD1 }, + { DAVINCI_LPSC_USB20 }, + { DAVINCI_LPSC_USB11 }, +}; + +static const struct pinmux_config enbw_pins[] = { + { pinmux(0), 8, 0 }, + { pinmux(0), 8, 1 }, + { pinmux(0), 8, 2 }, + { pinmux(0), 8, 3 }, + { pinmux(0), 8, 4 }, + { pinmux(0), 8, 5 }, + { pinmux(1), 4, 0 }, + { pinmux(1), 8, 1 }, + { pinmux(1), 8, 2 }, + { pinmux(1), 8, 3 }, + { pinmux(1), 8, 4 }, + { pinmux(1), 8, 5 }, + { pinmux(1), 8, 6 }, + { pinmux(1), 4, 7 }, + { pinmux(2), 8, 0 }, + { pinmux(5), 1, 0 }, + { pinmux(5), 1, 3 }, + { pinmux(5), 1, 7 }, + { pinmux(6), 1, 0 }, + { pinmux(6), 1, 1 }, + { pinmux(6), 8, 2 }, + { pinmux(6), 8, 3 }, + { pinmux(6), 1, 4 }, + { pinmux(6), 8, 5 }, + { pinmux(6), 1, 7 }, + { pinmux(7), 8, 2 }, + { pinmux(7), 1, 3 }, + { pinmux(7), 1, 6 }, + { pinmux(7), 1, 7 }, + { pinmux(13), 8, 2 }, + { pinmux(13), 8, 3 }, + { pinmux(13), 8, 4 }, + { pinmux(13), 8, 5 }, + { pinmux(13), 8, 6 }, + { pinmux(13), 8, 7 }, + { pinmux(14), 8, 0 }, + { pinmux(14), 8, 1 }, + { pinmux(16), 8, 1 }, + { pinmux(16), 8, 2 }, + { pinmux(16), 8, 3 }, + { pinmux(16), 8, 4 }, + { pinmux(16), 8, 5 }, + { pinmux(16), 8, 6 }, + { pinmux(16), 8, 7 }, + { pinmux(17), 1, 0 }, + { pinmux(17), 1, 1 }, + { pinmux(17), 1, 2 }, + { pinmux(17), 8, 3 }, + { pinmux(17), 8, 4 }, + { pinmux(17), 8, 5 }, + { pinmux(17), 8, 6 }, + { pinmux(17), 8, 7 }, + { pinmux(18), 8, 0 }, + { pinmux(18), 8, 1 }, + { pinmux(18), 2, 2 }, + { pinmux(18), 2, 3 }, + { pinmux(18), 2, 4 }, + { pinmux(18), 8, 6 }, + { pinmux(18), 8, 7 }, + { pinmux(19), 8, 0 }, + { pinmux(19), 2, 1 }, + { pinmux(19), 2, 2 }, + { pinmux(19), 2, 3 }, + { pinmux(19), 2, 4 }, + { pinmux(19), 8, 5 }, + { pinmux(19), 8, 6 }, +}; + +const struct pinmux_resource pinmuxes[] = { + PINMUX_ITEM(emac_pins_mii), + PINMUX_ITEM(emac_pins_mdio), + PINMUX_ITEM(i2c0_pins), + PINMUX_ITEM(emifa_pins_cs2), + PINMUX_ITEM(emifa_pins_cs3), + PINMUX_ITEM(emifa_pins_cs4), + PINMUX_ITEM(emifa_pins_nand), + PINMUX_ITEM(emifa_pins_nor), + PINMUX_ITEM(spi1_pins_base), + PINMUX_ITEM(spi1_pins_scs0), + PINMUX_ITEM(uart1_pins_txrx), + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(uart2_pins_rtscts), + PINMUX_ITEM(enbw_pins), +}; + +const int pinmuxes_size = ARRAY_SIZE(pinmuxes); + +struct gpio_config { + char name[GPIO_NAME_SIZE]; + unsigned char bank; + unsigned char gpio; + unsigned char out; + unsigned char value; +}; + +static const struct gpio_config enbw_gpio_config[] = { + { "RS485 enable", 8, 11, 1, 0 }, + { "RS485 iso", 8, 10, 1, 0 }, + { "W2HUT RS485 Rx ena", 8, 9, 1, 0 }, + { "W2HUT RS485 iso", 8, 8, 1, 0 }, + { "LAN reset", 7, 15, 1, 1 }, + { "ena 11V PLC", 7, 14, 1, 0 }, + { "ena 1.5V PLC", 7, 13, 1, 0 }, + { "disable VBUS", 7, 12, 1, 1 }, + { "PLC reset", 6, 13, 1, 1 }, + { "LCM RS", 6, 12, 1, 0 }, + { "LCM R/W", 6, 11, 1, 0 }, + { "PLC pairing", 6, 10, 1, 1 }, + { "PLC MDIO CLK", 6, 9, 1, 0 }, + { "HK218", 6, 8, 1, 0 }, + { "HK218 Rx", 6, 1, 1, 1 }, + { "TPM reset", 6, 0, 1, 1 }, + { "LCM E", 2, 2, 1, 1 }, + { "PV-IF RxD ena", 0, 15, 1, 1 }, + { "LED1", 1, 15, 1, 1 }, + { "LED2", 0, 1, 1, 1 }, + { "LED3", 0, 2, 1, 1 }, + { "LED4", 0, 3, 1, 1 }, + { "LED5", 0, 4, 1, 1 }, + { "LED6", 0, 5, 1, 0 }, + { "LED7", 0, 6, 1, 0 }, + { "LED8", 0, 14, 1, 0 }, + { "USER1", 0, 12, 0, 0 }, + { "USER2", 0, 13, 0, 0 }, +}; + +#define PHY_POWER 0x0800 + +static void enbw_cmc_switch(int port, int on) +{ + const char *devname; + unsigned char phyaddr = 3; + unsigned char reg = 0; + unsigned short data; + + if (port == 1) + phyaddr = 2; + + devname = miiphy_get_current_dev(); + if (!devname) { + printf("Error: no mii device\n"); + return; + } + if (miiphy_read(devname, phyaddr, reg, &data) != 0) { + printf("Error reading from the PHY addr=%02x reg=%02x\n", + phyaddr, reg); + return; + } + + if (on) + data &= ~PHY_POWER; + else + data |= PHY_POWER; + + if (miiphy_write(devname, phyaddr, reg, data) != 0) { + printf("Error writing to the PHY addr=%02x reg=%02x\n", + phyaddr, reg); + return; + } +} + +int board_init(void) +{ + int i, ret; + +#ifndef CONFIG_USE_IRQ + irq_init(); +#endif + /* address of boot parameters, not used as booting with DTT */ + gd->bd->bi_boot_params = 0; + + for (i = 0; i < ARRAY_SIZE(enbw_gpio_config); i++) { + int gpio = enbw_gpio_config[i].bank * 16 + + enbw_gpio_config[i].gpio; + + ret = gpio_request(gpio, enbw_gpio_config[i].name); + if (ret) { + printf("%s: Could not get %s gpio\n", __func__, + enbw_gpio_config[i].name); + return -1; + } + + if (enbw_gpio_config[i].out) + gpio_direction_output(gpio, + enbw_gpio_config[i].value); + else + gpio_direction_input(gpio); + } + + /* setup the SUSPSRC for ARM to control emulation suspend */ + clrbits_le32(&davinci_syscfg_regs->suspsrc, + (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | + DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | + DAVINCI_SYSCFG_SUSPSRC_UART2)); + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_EMAC +/* + * Initializes on-board ethernet controllers. + */ +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_DRIVER_TI_EMAC + davinci_emac_mii_mode_sel(0); +#endif /* CONFIG_DRIVER_TI_EMAC */ + + if (!davinci_emac_initialize()) { + printf("Error: Ethernet init failed!\n"); + return -1; + } + + if (hwconfig_subarg_cmp("switch", "lan", "on")) + /* Switch port lan on */ + enbw_cmc_switch(1, 1); + else + enbw_cmc_switch(1, 0); + + if (hwconfig_subarg_cmp("switch", "pwl", "on")) + /* Switch port pwl on */ + enbw_cmc_switch(2, 1); + else + enbw_cmc_switch(2, 0); + + return 0; +} +#endif /* CONFIG_DRIVER_TI_EMAC */ + +#ifdef CONFIG_PREBOOT +static uchar kbd_magic_prefix[] = "key_magic_"; +static uchar kbd_command_prefix[] = "key_cmd_"; + +struct kbd_data_t { + char s1; +}; + +struct kbd_data_t *get_keys(struct kbd_data_t *kbd_data) +{ + /* read SW1 + SW2 */ + kbd_data->s1 = gpio_get_value(12) + + (gpio_get_value(13) << 1); + return kbd_data; +} + +static int compare_magic(const struct kbd_data_t *kbd_data, char *str) +{ + char s1 = str[0]; + + if (s1 >= '0' && s1 <= '9') + s1 -= '0'; + else if (s1 >= 'a' && s1 <= 'f') + s1 = s1 - 'a' + 10; + else if (s1 >= 'A' && s1 <= 'F') + s1 = s1 - 'A' + 10; + else + return -1; + + if (s1 != kbd_data->s1) + return -1; + + return 0; +} + +static char *key_match(const struct kbd_data_t *kbd_data) +{ + char magic[sizeof(kbd_magic_prefix) + 1]; + char *suffix; + char *kbd_magic_keys; + + /* + * The following string defines the characters that can be appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + kbd_magic_keys = getenv("magic_keys"); + if (kbd_magic_keys == NULL) + kbd_magic_keys = ""; + + /* + * loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix = kbd_magic_keys; *suffix || + suffix == kbd_magic_keys; ++suffix) { + sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); + + if (compare_magic(kbd_data, getenv(magic)) == 0) { + char cmd_name[sizeof(kbd_command_prefix) + 1]; + char *cmd; + + sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); + cmd = getenv(cmd_name); + + return cmd; + } + } + + return NULL; +} +#endif /* CONFIG_PREBOOT */ + +int misc_init_r(void) +{ + char *s, buf[32]; +#ifdef CONFIG_PREBOOT + struct kbd_data_t kbd_data; + /* Decode keys */ + char *str = strdup(key_match(get_keys(&kbd_data))); + /* Set or delete definition */ + setenv("preboot", str); + free(str); +#endif /* CONFIG_PREBOOT */ + + /* count all restarts, and save this in an environment var */ + s = getenv("restartcount"); + + if (s) + sprintf(buf, "%ld", simple_strtoul(s, NULL, 10) + 1); + else + strcpy(buf, "1"); + + setenv("restartcount", buf); + saveenv(); + +#ifdef CONFIG_HW_WATCHDOG + davinci_hw_watchdog_enable(); +#endif + + return 0; +} + +struct cmc_led { + char name[20]; + unsigned char bank; + unsigned char gpio; +}; + +struct cmc_led led_table[] = { + {"led1", 1, 15}, + {"led2", 0, 1}, + {"led3", 0, 2}, + {"led4", 0, 3}, + {"led5", 0, 4}, + {"led6", 0, 5}, + {"led7", 0, 6}, + {"led8", 0, 14}, +}; + +static int cmc_get_led_state(struct cmc_led *led) +{ + int value; + int gpio = led->bank * 16 + led->gpio; + + value = gpio_get_value(gpio); + + return value; +} + +static int cmc_set_led_state(struct cmc_led *led, int state) +{ + int gpio = led->bank * 16 + led->gpio; + + gpio_set_value(gpio, state); + return 0; +} + +static int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + struct cmc_led *led; + int found = 0; + int i = 0; + int only_print = 0; + int len = ARRAY_SIZE(led_table); + + if (argc < 2) + return cmd_usage(cmdtp); + + if (argc < 3) + only_print = 1; + + led = led_table; + while ((!found) && (i < len)) { + if (strcmp(argv[1], led->name) == 0) { + found = 1; + } else { + led++; + i++; + } + } + if (!found) + return cmd_usage(cmdtp); + + if (only_print) { + if (cmc_get_led_state(led)) + printf("on\n"); + else + printf("off\n"); + + return 0; + } + if (strcmp(argv[2], "on") == 0) + cmc_set_led_state(led, 1); + else + cmc_set_led_state(led, 0); + + return 0; +} + +U_BOOT_CMD(led, 3, 1, do_led, + "switch on/off board led", + "[name] [on/off]" +); + +#ifdef CONFIG_HW_WATCHDOG +void hw_watchdog_reset(void) +{ + davinci_hw_watchdog_reset(); +} +#endif + +#if defined(CONFIG_POST) +void arch_memory_failure_handle(void) +{ + struct davinci_gpio *gpio = davinci_gpio_bank01; + int state = 1; + + /* + * if memor< failure blink with the LED 1,2 and 3 + * as we running from flash, we cannot use the gpio + * api here, so access the gpio pin direct through + * the gpio register. + */ + while (1) { + if (state) { + clrbits_le32(&gpio->out_data, 0x80000006); + state = 0; + } else { + setbits_le32(&gpio->out_data, 0x80000006); + state = 1; + } + udelay(500); + } +} +#endif + +#if defined(CONFIG_BOOTCOUNT_LIMIT) +void bootcount_store(ulong a) +{ + struct davinci_rtc *reg = + (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; + + /* + * write RTC kick register to enable write + * for RTC Scratch registers. Cratch0 and 1 are + * used for bootcount values. + */ + out_be32(®->kick0r, RTC_KICK0R_WE); + out_be32(®->kick1r, RTC_KICK1R_WE); + out_be32(®->scratch0, a); + out_be32(®->scratch1, BOOTCOUNT_MAGIC); +} + +ulong bootcount_load(void) +{ + struct davinci_rtc *reg = + (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; + + if (in_be32(®->scratch1) != BOOTCOUNT_MAGIC) + return 0; + else + return in_be32(®->scratch0); +} +#endif + +void board_gpio_init(void) +{ + struct davinci_gpio *gpio = davinci_gpio_bank01; + + /* + * Power on required peripherals + * ARM does not have access by default to PSC0 and PSC1 + * assuming here that the DSP bootloader has set the IOPU + * such that PSC access is available to ARM + */ + if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) + return; + + /* + * set LED (gpio Interface not usable here) + * set LED pins to output and state 0 + */ + clrbits_le32(&gpio->dir, 0x8000407e); + clrbits_le32(&gpio->out_data, 0x8000407e); + /* set LED 1 - 5 to state on */ + setbits_le32(&gpio->out_data, 0x8000001e); +} + +int board_late_init(void) +{ + cmc_set_led_state(&led_table[4], 0); + + return 0; +} + +void show_boot_progress(int val) +{ + switch (val) { + case 1: + cmc_set_led_state(&led_table[4], 1); + break; + case 4: + cmc_set_led_state(&led_table[4], 0); + break; + case 15: + cmc_set_led_state(&led_table[4], 1); + break; + } +} + +#ifdef CONFIG_DAVINCI_MMC +static struct davinci_mmc mmc_sd1 = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE, + .input_clk = 228000000, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .version = MMC_CTLR_VERSION_2, +}; + +int board_mmc_init(bd_t *bis) +{ + mmc_sd1.input_clk = clk_get(DAVINCI_MMC_CLKID); + /* Add slot-0 to mmc subsystem */ + return davinci_mmc_init(bis, &mmc_sd1); +} +#endif diff --git a/boards.cfg b/boards.cfg index 77dc560..b678547 100644 --- a/boards.cfg +++ b/boards.cfg @@ -137,6 +137,7 @@ davinci_dvevm arm arm926ejs dvevm davinci davinci_schmoogie arm arm926ejs schmoogie davinci davinci davinci_sffsdr arm arm926ejs sffsdr davinci davinci davinci_sonata arm arm926ejs sonata davinci davinci +enbw_cmc arm arm926ejs enbw_cmc enbw davinci km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_RECONFIG_XLX mgcoge3un arm arm926ejs km_arm keymile kirkwood diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h new file mode 100644 index 0000000..c427dc7 --- /dev/null +++ b/include/configs/enbw_cmc.h @@ -0,0 +1,451 @@ +/* + * (C) Copyright 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on davinci_dvevm.h. Original Copyrights follow: + * + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Board + */ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7 +#define CONFIG_USE_NAND + +/* + * SoC Configuration + */ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SOC_DA850 /* TI DA850 SoC */ +#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) +#define CONFIG_SYS_OSCIN_FREQ 24000000 +#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_DA850_LOWLEVEL +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DA8XX_GPIO +#define CONFIG_HOSTNAME enbw_cmc +#define CONFIG_DISPLAY_CPUINFO + +#define MACH_TYPE_ENBW_CMC 3585 +#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC + +/* + * Memory Info + */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ +#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ +#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ + +/* memtest start addr */ +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) + +/* memtest will be run on 16MB */ +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) + +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ + +/* + * Serial Driver info + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ +#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2 +/* + * I2C Configuration + */ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CONFIG_SYS_I2C_SPEED 80000 +#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 +#define CONFIG_CMD_I2C + +#define CONFIG_CMD_DTT +#define CONFIG_DTT_LM75 +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3 + +/* + * Flash & Environment + */ +#ifdef CONFIG_USE_NAND +#define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_SYS_NAND_CS 3 +#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CONFIG_SYS_CLE_MASK 0x10 +#define CONFIG_SYS_ALE_MASK 0x8 +#undef CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 + +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1" +#define MTDPARTS_DEFAULT \ + "mtdparts=" \ + "physmap-flash.0:" \ + "512k(U-Boot)," \ + "64k(env1)," \ + "64k(env2)," \ + "-(rest);" \ + "davinci_nand.1:" \ + "128k(dtb)," \ + "3m(kernel)," \ + "4m(rootfs)," \ + "-(userfs)" + + +#define CONFIG_CMD_MTDPARTS + +#endif + +/* + * Network & Ethernet Configuration + */ +#ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#endif + +/* + * Flash configuration + */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_SIZE 0x01000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_FLASH_16BIT /* Flash is 16-bit */ + +#define CONFIG_CMD_FLASH + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE (64 << 10) +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#undef CONFIG_ENV_IS_IN_NAND +#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \ + CONFIG_ENV_SECT_SIZE) + +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "u-boot_addr_r=c0000000\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ + "update=protect off " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};"\ + "erase " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ + "cp.b ${u-boot_addr_r} " xstr(CONFIG_SYS_FLASH_BASE) \ + " ${filesize};" \ + "protect on " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\ + "netdev=eth0\0" \ + "rootpath=/opt/eldk-arm/arm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "kernel_addr_r=c0700000\0" \ + "fdt_addr_r=c0600000\0" \ + "ramdisk_addr_r=c0b00000\0" \ + "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \ + xstr(CONFIG_HOSTNAME) ".dtb\0" \ + "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \ + "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0" \ + "nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0" \ + "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0" \ + "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \ + "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \ + "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \ + "addcon=setenv bootargs ${bootargs} console=ttyS2," \ + "${baudrate}n8\0" \ + "net_nfs=run load_fdt load_kernel; " \ + "run nfsargs addip addcon addmtd addmisc;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\ + "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ + "bootcmd=run net_nfs\0" \ + "machid=e01\0" \ + "key_cmd_0=echo key: 0\0" \ + "key_cmd_1=echo key: 1\0" \ + "key_cmd_2=echo key: 2\0" \ + "key_cmd_3=echo key: 3\0" \ + "key_magic_0=0\0" \ + "key_magic_1=1\0" \ + "key_magic_2=2\0" \ + "key_magic_3=3\0" \ + "magic_keys=0123\0" \ + "hwconfig=switch:lan=on,pwl=off\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs} davinci_mmc.use_dma=0\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "logversion=2\0" \ + "\0" + +/* + * U-Boot general configuration + */ +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "=> " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +#define CONFIG_BOOTDELAY 3 +#define CONFIG_HWCONFIG +#define CONFIG_SHOW_BOOT_PROGRESS +#define CONFIG_BOARD_LATE_INIT + +/* + * U-Boot commands + */ +#include +#define CONFIG_CMD_ENV +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_CACHE + +#ifndef CONFIG_DRIVER_TI_EMAC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_PING +#endif + +#ifdef CONFIG_USE_NAND +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_NAND + +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_LZO +#define CONFIG_RBTREE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#endif + +#if !defined(CONFIG_USE_NAND) && \ + !defined(CONFIG_USE_NOR) && \ + !defined(CONFIG_USE_SPIFLASH) +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_SIZE (16 << 10) +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_ENV +#endif + +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00) + +#define CONFIG_VERSION_VARIABLE +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo" +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMC_RESET_PIN 0x04000000 +#define CONFIG_CMC_RESET_TIMEOUT 3 + +#define CONFIG_HW_WATCHDOG +#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE +#define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000 +#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0 + +#define CONFIG_CMD_DATE +#define CONFIG_RTC_DAVINCI + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DAVINCI_MMC +#define CONFIG_MMC_MBLOCK +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MMC + + +/* FDT support */ +#define CONFIG_OF_LIBFDT + +/* LowLevel Init */ +/* PLL */ +#define CONFIG_SYS_DV_CLKMODE 0 +#define CONFIG_SYS_DA850_PLL0_POSTDIV 0 +#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 +#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 +#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 /* 150MHz */ +#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 +#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 +#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 +#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 + +#define CONFIG_SYS_DA850_PLL1_POSTDIV 1 +#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 +#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 +#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 + +#define CONFIG_SYS_DA850_PLL0_PLLM 18 /* PLL0 -> 456 MHz */ +#define CONFIG_SYS_DA850_PLL1_PLLM 24 /* PLL1 -> 300 MHz */ + +/* DDR RAM */ +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ + DV_DDR_PHY_EXT_STRBEN | \ + (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \ + (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \ + (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ + (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ + (0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \ + (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ + (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \ + (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ + (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ + (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ + (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */ + +/* + * freq = 150MHz -> t = 7ns + */ +#define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \ + (0x0d << DV_DDR_SDTMR1_RFC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ + (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ + (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ + (7 << DV_DDR_SDTMR1_RC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ + (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \ + ((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT)) + +/* + * freq = 150MHz -> t=7ns + */ +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \ + (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \ + (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ + (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ + (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ + (15 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ + (27 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ + (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ + (2 << DV_DDR_SDTMR2_CKE_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000407 +#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 +#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ + DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ + DAVINCI_SYSCFG_SUSPSRC_UART2 | \ + DAVINCI_SYSCFG_SUSPSRC_EMAC |\ + DAVINCI_SYSCFG_SUSPSRC_I2C) + +#define CONFIG_SYS_DA850_CS2CFG (DAVINCI_ABCR_WSETUP(2) | \ + DAVINCI_ABCR_WSTROBE(6) | \ + DAVINCI_ABCR_WHOLD(1) | \ + DAVINCI_ABCR_RSETUP(2) | \ + DAVINCI_ABCR_RSTROBE(6) | \ + DAVINCI_ABCR_RHOLD(1) | \ + DAVINCI_ABCR_ASIZE_16BIT) + +#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \ + DAVINCI_ABCR_WSTROBE(2) | \ + DAVINCI_ABCR_WHOLD(1) | \ + DAVINCI_ABCR_RSETUP(1) | \ + DAVINCI_ABCR_RSTROBE(6) | \ + DAVINCI_ABCR_RHOLD(1) | \ + DAVINCI_ABCR_ASIZE_8BIT) + +/* + * NOR Bootconfiguration word: + * Method: Direc boot + * EMIFA access mode: 16 Bit + */ +#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) + +#define CONFIG_POST (CONFIG_SYS_POST_MEMORY) +#define CONFIG_SYS_POST_WORD_ADDR 0x8001FFF0 +#define CONFIG_LOGBUFFER +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE + +#define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#endif /* __CONFIG_H */ -- cgit v0.10.2 From 5cb939fb04a3d5f2ca1174a367a3fc27aed30c6a Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Tue, 29 Nov 2011 00:11:03 +0000 Subject: arm: printf() is not available in some SPL configurations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch avoids build breakage for SPLs that do not support printf. Signed-off-by: Christian Riesch Cc: Wolfgang Denk Cc: Albert Aribaud Acked-by: Tom Rini Acked-by: Andreas Bießmann diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c index eb3e26d..e1b87be 100644 --- a/arch/arm/lib/eabi_compat.c +++ b/arch/arm/lib/eabi_compat.c @@ -13,7 +13,9 @@ int raise (int signum) { +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("raise: Signal # %d caught\n", signum); +#endif return 0; } -- cgit v0.10.2 From b609009801b8a00644926f49b7d0d0cc0d3d8797 Mon Sep 17 00:00:00 2001 From: Prabhakar Lad Date: Thu, 17 Nov 2011 02:53:23 +0000 Subject: ARM: davici_emac: Fix condition for number of phy detects Fix the condition for number of phys in davinci_eth_phy_detect() function. CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT indicates number of phys. From this commit id dc02badab480563b0bf9d3908046ea9d6b22ae63 davinci emac initilazed one less than the number of phy count. Signed-off-by: Prabhakar Lad Acked-by: Heiko Schocher diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index d6c4e63..fbd0f1b 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -220,7 +220,7 @@ static int davinci_eth_phy_detect(void) for (i = 0, j = 0; i < 32; i++) if (phy_act_state & (1 << i)) { count++; - if (count < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) { + if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) { active_phy_addr[j++] = i; } else { printf("%s: to many PHYs detected.\n", -- cgit v0.10.2 From b7eb9e7895bf481d979d58d5d7a53033c3ad9a8f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:47:58 +0000 Subject: omap3: mem: Comment enable_gpmc_cs_config more Expand the "enable the config" comment to explain what the bit shifts are and define out two of the magic numbers. Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c index a01c303..2f1efea 100644 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ b/arch/arm/cpu/armv7/omap3/mem.c @@ -105,9 +105,15 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, writel(gpmc_config[3], &cs->config4); writel(gpmc_config[4], &cs->config5); writel(gpmc_config[5], &cs->config6); - /* Enable the config */ - writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | - (1 << 6)), &cs->config7); + + /* + * Enable the config. size is the CS size and goes in + * bits 11:8. We set bit 6 to enable this CS and the base + * address goes into bits 5:0. + */ + writel((size << 8) | (GPMC_CS_ENABLE << 6) | + ((base >> 24) & GPMC_BASEADDR_MASK), + &cs->config7); sdelay(2000); } diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index db6a696..abf4e82 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -259,6 +259,10 @@ enum { #define GPMC_SIZE_32M 0xE #define GPMC_SIZE_16M 0xF +#define GPMC_BASEADDR_MASK 0x3F + +#define GPMC_CS_ENABLE 0x1 + #define SMNAND_GPMC_CONFIG1 0x00000800 #define SMNAND_GPMC_CONFIG2 0x00141400 #define SMNAND_GPMC_CONFIG3 0x00141400 -- cgit v0.10.2 From 5f862b7179f61b4ca826fe8b20d8ca3c7e267153 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:47:59 +0000 Subject: OMAP3: Update SDRC dram_init to always call make_cs1_contiguous() We update the comment in make_cs1_contiguous() to be a little bit more clear (it's been copy/pasted from other silicons) and then explain in dram_init() why we need to always try this. Note that in the previous behavior we were always calling this on boards that never had cs1 populated anyhow so making sure we do this always is fine and will correct things like omap3evm detecting an invalid amount of memory (384MB). Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 0dd1955..66ce33f 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -58,10 +58,9 @@ u32 is_mem_sdr(void) /* * make_cs1_contiguous - - * - For es2 and above remap cs1 behind cs0 to allow command line - * mem=xyz use all memory with out discontinuous support compiled in. - * Could do it at the ATAG, but there really is two banks... - * - Called as part of 2nd phase DDR init. + * - When we have CS1 populated we want to have it mapped after cs0 to allow + * command line mem=xyz use all memory with out discontinuous support + * compiled in. We could do it in the ATAG, but there really is two banks... */ void make_cs1_contiguous(void) { @@ -207,16 +206,16 @@ int dram_init(void) size0 = get_sdr_cs_size(CS0); /* - * If a second bank of DDR is attached to CS1 this is - * where it can be started. Early init code will init - * memory on CS0. + * We always need to have cs_cfg point at where the second + * bank would be, if present. Failure to do so can lead to + * strange situations where memory isn't detected and + * configured correctly. CS0 will already have been setup + * at this point. */ - if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) { - do_sdrc_init(CS1, NOT_EARLY); - make_cs1_contiguous(); + make_cs1_contiguous(); + do_sdrc_init(CS1, NOT_EARLY); + size1 = get_sdr_cs_size(CS1); - size1 = get_sdr_cs_size(CS1); - } gd->ram_size = size0 + size1; return 0; -- cgit v0.10.2 From 2a04e85870de089018e40828a5238cc413089007 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:00 +0000 Subject: OMAP3: Add a helper function to set timings in SDRC Since we go through the sequence to setup the SDRC timings more than once, break this logic out into its own function and have that function call mem_ok() to make sure the memory is usable. Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 66ce33f..2756024 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -108,14 +108,45 @@ u32 get_sdr_cs_offset(u32 cs) } /* + * write_sdrc_timings - + * - Takes CS and associated timings and initalize SDRAM + * - Test CS to make sure it's OK for use + */ +static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, + u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr) +{ + /* Setup timings we got from the board. */ + writel(mcfg, &sdrc_base->cs[cs].mcfg); + writel(ctrla, &sdrc_actim_base->ctrla); + writel(ctrlb, &sdrc_actim_base->ctrlb); + writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); + writel(CMD_NOP, &sdrc_base->cs[cs].manual); + writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + writel(mr, &sdrc_base->cs[cs].mr); + + /* + * Test ram in this bank + * Disable if bad or not present + */ + if (!mem_ok(cs)) + writel(0, &sdrc_base->cs[cs].mcfg); +} + +/* * do_sdrc_init - - * - Initialize the SDRAM for use. - * - code called once in C-Stack only context for CS0 and a possible 2nd - * time depending on memory configuration from stack+global context + * - Code called once in C-Stack only context for CS0 and with early being + * true and a possible 2nd time depending on memory configuration from + * stack+global context. */ void do_sdrc_init(u32 cs, u32 early) { struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1; + u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr; + + sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; + sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; if (early) { /* reset sdrc controller */ @@ -127,73 +158,48 @@ void do_sdrc_init(u32 cs, u32 early) /* setup sdrc to ball mux */ writel(SDRC_SHARING, &sdrc_base->sharing); - /* Disable Power Down of CKE cuz of 1 CKE on combo part */ + /* Disable Power Down of CKE because of 1 CKE on combo part */ writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power); writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); - } - /* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need * to prevent this to be build in non-SPL build */ #ifdef CONFIG_SPL_BUILD - /* If we use a SPL there is no x-loader nor config header so we have - * to do the job ourselfs - */ - if (cs == CS0) { - sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; - - /* General SDRC config */ - writel(V_MCFG, &sdrc_base->cs[cs].mcfg); - writel(V_RFR_CTRL, &sdrc_base->cs[cs].rfr_ctrl); - - /* AC timings */ - writel(V_ACTIMA_165, &sdrc_actim_base0->ctrla); - writel(V_ACTIMB_165, &sdrc_actim_base0->ctrlb); - - /* Initialize */ - writel(CMD_NOP, &sdrc_base->cs[cs].manual); - writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + /* + * If we use a SPL there is no x-loader nor config header so + * we have to do the job ourselfs + */ + + mcfg = V_MCFG; + ctrla = V_ACTIMA_165; + ctrlb = V_ACTIMB_165; + rfr_ctrl = V_RFR_CTRL; + mr = V_MR; + + write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb, + rfr_ctrl, mr); +#endif - writel(V_MR, &sdrc_base->cs[cs].mr); } -#endif /* - * SDRC timings are set up by x-load or config header - * We don't need to redo them here. - * Older x-loads configure only CS0 - * configure CS1 to handle this ommission + * If we aren't using SPL we have been loaded by some + * other means which may not have correctly initialized + * both CS0 and CS1 (such as some older versions of x-loader) + * so we may be asked now to setup CS1. */ if (cs == CS1) { - sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; - sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; - writel(readl(&sdrc_base->cs[CS0].mcfg), - &sdrc_base->cs[CS1].mcfg); - writel(readl(&sdrc_base->cs[CS0].rfr_ctrl), - &sdrc_base->cs[CS1].rfr_ctrl); - writel(readl(&sdrc_actim_base0->ctrla), - &sdrc_actim_base1->ctrla); - writel(readl(&sdrc_actim_base0->ctrlb), - &sdrc_actim_base1->ctrlb); - - writel(CMD_NOP, &sdrc_base->cs[cs].manual); - writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(readl(&sdrc_base->cs[CS0].mr), - &sdrc_base->cs[CS1].mr); - } + mcfg = readl(&sdrc_base->cs[CS0].mcfg), + rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); + ctrla = readl(&sdrc_actim_base0->ctrla), + ctrlb = readl(&sdrc_actim_base0->ctrlb); + mr = readl(&sdrc_base->cs[CS0].mr); + write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb, + rfr_ctrl, mr); - /* - * Test ram in this bank - * Disable if bad or not present - */ - if (!mem_ok(cs)) - writel(0, &sdrc_base->cs[cs].mcfg); + } } /* -- cgit v0.10.2 From 3bd8437dcce211bba51b306a9b71f9eec4a474c2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:01 +0000 Subject: OMAP3: Change mem_ok to clear again after reading back It's possible to need to call this function on the same banks multiple times so we want to be sure that 'pos A' is cleared out again at the end. Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c index 2f1efea..2fe5ac7 100644 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ b/arch/arm/cpu/armv7/omap3/mem.c @@ -86,6 +86,7 @@ u32 mem_ok(u32 cs) writel(0x0, addr + 4); /* remove pattern off the bus */ val1 = readl(addr + 0x400); /* get pos A value */ val2 = readl(addr); /* get val2 */ + writel(0x0, addr + 0x400); /* clear pos A */ if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ return 0; -- cgit v0.10.2 From 50e7ff0369fc2720eb72feb50cce41d54dd1b2d8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:02 +0000 Subject: OMAP3: Remove get_mem_type prototype This function doesn't exist for omap3 Signed-off-by: Tom Rini diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 995e7cb..9e64410 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -49,7 +49,6 @@ void set_muxconf_regs(void); u32 get_cpu_family(void); u32 get_cpu_rev(void); u32 get_sku_id(void); -u32 get_mem_type(void); u32 get_sysboot_value(void); u32 is_gpmc_muxed(void); u32 get_gpmc0_type(void); -- cgit v0.10.2 From 14ca3dee80718b5f8fd06e39e78a4e7757826bbf Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:03 +0000 Subject: omap3: mem: Add MCFG helper macro This adds an MCFG macro to calculate the correct value, similar to the ACTIMA/ACTIMB macros and adds a comment that all of the potential values here are documented in the TRM. Then we convert the Micron value to use this macro. Signed-off-by: Tom Rini diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index abf4e82..12ff3b0 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -39,6 +39,12 @@ enum { #define EARLY_INIT 1 +/* + * For a full explanation of these registers and values please see + * the Technical Reference Manual (TRM) for any of the processors in + * this family. + */ + /* Slower full frequency range default timings for x32 operation*/ #define SDRC_SHARING 0x00000100 #define SDRC_MR_0_SDR 0x00000031 @@ -86,6 +92,27 @@ enum { ACTIM_CTRLB_TXP(b) | \ ACTIM_CTRLB_TXSR(d) +/* + * Values used in the MCFG register. Only values we use today + * are defined and the rest can be found in the TRM. Unless otherwise + * noted all fields are one bit. + */ +#define V_MCFG_RAMTYPE_DDR (0x1) +#define V_MCFG_DEEPPD_EN (0x1 << 3) +#define V_MCFG_B32NOT16_32 (0x1 << 4) +#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */ +#define V_MCFG_RAMSIZE(a) ((((a)/(1024*1024))/2) << 8) /* 8:17 */ +#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19) +#define V_MCFG_CASWIDTH_10B (0x5 << 20) /* 20:22 */ +#define V_MCFG_RASWIDTH(a) ((a) << 24) /* 24:26 */ + +/* Macro to construct MCFG */ +#define MCFG(a, b) \ + V_MCFG_RASWIDTH(b) | V_MCFG_CASWIDTH_10B | \ + V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(a) | \ + V_MCFG_BANKALLOCATION_RBC | \ + V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR + /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ /* 15/6 + 18/6 = 5.5 -> 6 */ @@ -138,21 +165,8 @@ enum { ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ MICRON_TXP_165, MICRON_XSR_165) -#define MICRON_RAMTYPE 0x1 -#define MICRON_DDRTYPE 0x0 -#define MICRON_DEEPPD 0x1 -#define MICRON_B32NOT16 0x1 -#define MICRON_BANKALLOCATION 0x2 -#define MICRON_RAMSIZE ((PHYS_SDRAM_1_SIZE/(1024*1024))/2) -#define MICRON_ADDRMUXLEGACY 0x1 -#define MICRON_CASWIDTH 0x5 -#define MICRON_RASWIDTH 0x2 -#define MICRON_LOCKSTATUS 0x0 -#define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \ - (MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \ - (MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \ - (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \ - (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE)) +#define MICRON_RASWIDTH 0x2 +#define MICRON_V_MCFG(size) MCFG((size), MICRON_RASWIDTH) #define MICRON_ARCV 2030 #define MICRON_ARE 0x1 @@ -199,7 +213,7 @@ enum { #ifdef CONFIG_OMAP3_MICRON_DDR #define V_ACTIMA_165 MICRON_V_ACTIMA_165 #define V_ACTIMB_165 MICRON_V_ACTIMB_165 -#define V_MCFG MICRON_V_MCFG +#define V_MCFG MICRON_V_MCFG(PHYS_SDRAM_1_SIZE) #define V_RFR_CTRL MICRON_V_RFR_CTRL #define V_MR MICRON_V_MR #endif -- cgit v0.10.2 From 1be1433b834aaf7aef7c92275f92d4729f6bd62e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:04 +0000 Subject: OMAP3: Add optimal SDRC autorefresh control values This adds the optimal SDRC autorefresh control register values for 100Mhz, 133MHz, 165MHz and 200MHz clocks. We switch to using this to provide the default 165MHz value. Signed-off-by: Tom Rini diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 12ff3b0..912c737 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -49,6 +49,16 @@ enum { #define SDRC_SHARING 0x00000100 #define SDRC_MR_0_SDR 0x00000031 +/* + * SDRC autorefresh control values. This register consists of autorefresh + * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The + * counter is a result of ( tREFI / tCK ) - 50. + */ +#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ +#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ +#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ + #define DLL_OFFSET 0 #define DLL_WRITEDDRCLKX2DIS 1 #define DLL_ENADLL 1 @@ -168,10 +178,6 @@ enum { #define MICRON_RASWIDTH 0x2 #define MICRON_V_MCFG(size) MCFG((size), MICRON_RASWIDTH) -#define MICRON_ARCV 2030 -#define MICRON_ARE 0x1 -#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE)) - #define MICRON_BL 0x2 #define MICRON_SIL 0x0 #define MICRON_CASL 0x3 @@ -214,7 +220,7 @@ enum { #define V_ACTIMA_165 MICRON_V_ACTIMA_165 #define V_ACTIMB_165 MICRON_V_ACTIMB_165 #define V_MCFG MICRON_V_MCFG(PHYS_SDRAM_1_SIZE) -#define V_RFR_CTRL MICRON_V_RFR_CTRL +#define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz #define V_MR MICRON_V_MR #endif -- cgit v0.10.2 From fc41ba1e2b4271bef197bfbf89d49458368319ce Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:05 +0000 Subject: OMAP3: Suffix all Micron memory timing parts with their speed Signed-off-by: Tom Rini diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 912c737..4f996d9 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -175,15 +175,16 @@ enum { ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ MICRON_TXP_165, MICRON_XSR_165) -#define MICRON_RASWIDTH 0x2 -#define MICRON_V_MCFG(size) MCFG((size), MICRON_RASWIDTH) +#define MICRON_RASWIDTH_165 0x2 +#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165) -#define MICRON_BL 0x2 -#define MICRON_SIL 0x0 -#define MICRON_CASL 0x3 -#define MICRON_WBST 0x0 -#define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \ - (MICRON_SIL << 3) | (MICRON_BL)) +#define MICRON_BL_165 0x2 +#define MICRON_SIL_165 0x0 +#define MICRON_CASL_165 0x3 +#define MICRON_WBST_165 0x0 +#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \ + (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ + (MICRON_BL_165)) /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ @@ -219,9 +220,9 @@ enum { #ifdef CONFIG_OMAP3_MICRON_DDR #define V_ACTIMA_165 MICRON_V_ACTIMA_165 #define V_ACTIMB_165 MICRON_V_ACTIMB_165 -#define V_MCFG MICRON_V_MCFG(PHYS_SDRAM_1_SIZE) +#define V_MCFG MICRON_V_MCFG_165(PHYS_SDRAM_1_SIZE) #define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz -#define V_MR MICRON_V_MR +#define V_MR MICRON_V_MR_165 #endif #ifdef CONFIG_OMAP3_NUMONYX_DDR -- cgit v0.10.2 From 9ae0d550741db45e933dc73e7135d1861e3a9b62 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:06 +0000 Subject: OMAP3 SPL: Rework memory initalization and devkit8000 support This changes to making the board be responsible for providing the memory initialization timings in SPL and converts the devkit8000 to this framework. In SPL we try and initialize both CS0 and CS1. Cc: Frederik Kriewitz Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 2756024..a27b4b1 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -148,6 +148,18 @@ void do_sdrc_init(u32 cs, u32 early) sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; + /* + * When called in the early context this may be SPL and we will + * need to set all of the timings. This ends up being board + * specific so we call a helper function to take care of this + * for us. Otherwise, to be safe, we need to copy the settings + * from the first bank to the second. We will setup CS0, + * then set cs_cfg to the appropriate value then try and + * setup CS1. + */ +#ifdef CONFIG_SPL_BUILD + get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr); +#endif if (early) { /* reset sdrc controller */ writel(SOFTRESET, &sdrc_base->sysconfig); @@ -164,22 +176,12 @@ void do_sdrc_init(u32 cs, u32 early) writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); -/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need - * to prevent this to be build in non-SPL build */ #ifdef CONFIG_SPL_BUILD - /* - * If we use a SPL there is no x-loader nor config header so - * we have to do the job ourselfs - */ - - mcfg = V_MCFG; - ctrla = V_ACTIMA_165; - ctrlb = V_ACTIMB_165; - rfr_ctrl = V_RFR_CTRL; - mr = V_MR; - write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb, rfr_ctrl, mr); + make_cs1_contiguous(); + write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb, + rfr_ctrl, mr); #endif } diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 4f996d9..09f5872 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -212,32 +212,6 @@ enum { ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ NUMONYX_TXP_165, NUMONYX_XSR_165) -#ifdef CONFIG_OMAP3_INFINEON_DDR -#define V_ACTIMA_165 INFINEON_V_ACTIMA_165 -#define V_ACTIMB_165 INFINEON_V_ACTIMB_165 -#endif - -#ifdef CONFIG_OMAP3_MICRON_DDR -#define V_ACTIMA_165 MICRON_V_ACTIMA_165 -#define V_ACTIMB_165 MICRON_V_ACTIMB_165 -#define V_MCFG MICRON_V_MCFG_165(PHYS_SDRAM_1_SIZE) -#define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz -#define V_MR MICRON_V_MR_165 -#endif - -#ifdef CONFIG_OMAP3_NUMONYX_DDR -#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 -#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 -#endif - -#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) -#error "Please choose the right DDR type in config header" -#endif - -#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL)) -#error "Please choose the right DDR type in config header" -#endif - /* * GPMC settings - * Definitions is as per the following format diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 9e64410..80e167b 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -38,6 +38,8 @@ void per_clocks_enable(void); void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr); void emif4_init(void); void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index fee0dff..b06aab6 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -138,3 +138,24 @@ int board_eth_init(bd_t *bis) return dm9000_initialize(bis); } #endif + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. We have either one or two banks of 128MB DDR. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + /* General SDRC config */ + *mcfg = MICRON_V_MCFG_165(128 << 20); + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + + /* AC timings */ + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + + *mr = MICRON_V_MR_165; +} diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 3ea4532..4b58dc3 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -67,10 +67,6 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) /* Hardware drivers */ - -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* DM9000 */ #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_DRIVER_DM9000 1 @@ -279,7 +275,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* NAND and environment organization */ -- cgit v0.10.2 From 4e647e12074c11a5bcfc5291c44c3b52531795fa Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:07 +0000 Subject: OMAP3 SPL: Add identify_nand_chip function A number of boards are populated with a PoP chip for both DDR and NAND memory. Other boards may simply use this as an easy way to identify board revs. So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND. Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 6ebfd32..ac597be 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -31,6 +31,9 @@ COBJS += board.o COBJS += clock.o COBJS += mem.o COBJS += sys_info.o +ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o +endif COBJS-$(CONFIG_DRIVER_TI_EMAC) += emac.o COBJS-$(CONFIG_EMIF4) += emif4.o diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c new file mode 100644 index 0000000..0871fc9 --- /dev/null +++ b/arch/arm/cpu/armv7/omap3/spl_id_nand.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2011 + * Texas Instruments, + * + * Author : + * Tom Rini + * + * Initial Code from: + * Richard Woodruff + * Jian Zhang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE; + +/* nand_command: Send a flash command to the flash chip */ +static void nand_command(u8 command) +{ + writeb(command, &gpmc_config->cs[0].nand_cmd); + + if (command == NAND_CMD_RESET) { + unsigned char ret_val; + writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd); + do { + /* Wait until ready */ + ret_val = readl(&gpmc_config->cs[0].nand_dat); + } while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY); + } +} + +/* + * Many boards will want to know the results of the NAND_CMD_READID command + * in order to decide what to do about DDR initialization. This function + * allows us to do that very early and to pass those results back to the + * board so it can make whatever decisions need to be made. + */ +void identify_nand_chip(int *mfr, int *id) +{ + /* Make sure that we have setup GPMC for NAND correctly. */ + writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1); + writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2); + writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3); + writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4); + writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5); + writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6); + + /* + * Enable the config. The CS size goes in bits 11:8. We set + * bit 6 to enable the CS and the base address goes into bits 5:0. + */ + writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) | + ((NAND_BASE >> 24) & GPMC_BASEADDR_MASK), + &gpmc_config->cs[0].config7); + + sdelay(2000); + + /* Issue a RESET and then READID */ + nand_command(NAND_CMD_RESET); + nand_command(NAND_CMD_READID); + + /* Set the address to read to 0x0 */ + writeb(0x0, &gpmc_config->cs[0].nand_adr); + + /* Read off the manufacturer and device id. */ + *mfr = readb(&gpmc_config->cs[0].nand_dat); + *id = readb(&gpmc_config->cs[0].nand_dat); +} diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 80e167b..e5031d5 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -40,6 +40,7 @@ void sdrc_init(void); void do_sdrc_init(u32, u32); void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, u32 *mr); +void identify_nand_chip(int *mfr, int *id); void emif4_init(void); void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, -- cgit v0.10.2 From 75c57a3570ec0904c14394db08ef436a8b49dda4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:08 +0000 Subject: OMAP3: Add SPL support to Beagleboard This introduces 200MHz Micron parts timing information based on x-loader to and Numonyx MCFG calculation. The memory init logic is also based on what x-loader does in these cases. Note that while previously u-boot would be flashed in with SW ECC in this case it now must be flashed with HW ECC. We also change CONFIG_SYS_TEXT_BASE to 0x80100000. Cc: Dirk Behme Beagleboard rev C5, xM rev A: Tested-by: Tom Rini Beagleboard xM rev C: Tested-by: Matt Ranostay Beagleboard rev B7, C2, xM rev B: Tested-by: Matt Porter Signed-off-by: Tom Rini diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 09f5872..4ea5f74 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -186,6 +186,32 @@ enum { (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ (MICRON_BL_165)) +/* Micron part (200MHz optimized) 5 ns */ +#define MICRON_TDAL_200 6 +#define MICRON_TDPL_200 3 +#define MICRON_TRRD_200 2 +#define MICRON_TRCD_200 3 +#define MICRON_TRP_200 3 +#define MICRON_TRAS_200 8 +#define MICRON_TRC_200 11 +#define MICRON_TRFC_200 15 +#define MICRON_V_ACTIMA_200 \ + ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \ + MICRON_TRAS_200, MICRON_TRP_200, \ + MICRON_TRCD_200, MICRON_TRRD_200, \ + MICRON_TDPL_200, MICRON_TDAL_200) + +#define MICRON_TWTR_200 2 +#define MICRON_TCKE_200 4 +#define MICRON_TXP_200 2 +#define MICRON_XSR_200 23 +#define MICRON_V_ACTIMB_200 \ + ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \ + MICRON_TXP_200, MICRON_XSR_200) + +#define MICRON_RASWIDTH_200 0x3 +#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200) + /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ /* 15/6 + 18/6 = 5.5 -> 6 */ @@ -212,6 +238,9 @@ enum { ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ NUMONYX_TXP_165, NUMONYX_XSR_165) +#define NUMONYX_RASWIDTH_165 0x4 +#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165) + /* * GPMC settings - * Definitions is as per the following format diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 9482c5e..6a457cb 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2008 + * (C) Copyright 2004-2011 * Texas Instruments, * * Author : @@ -34,9 +34,11 @@ #include #endif #include +#include #include #include #include +#include #include #include #include @@ -135,6 +137,69 @@ int get_board_revision(void) return revision; } +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + int pop_mfr, pop_id; + + /* + * We need to identify what PoP memory is on the board so that + * we know what timings to use. If we can't identify it then + * we know it's an xM. To map the ID values please see nand_ids.c + */ + identify_nand_chip(&pop_mfr, &pop_id); + + *mr = MICRON_V_MR_165; + switch (get_board_revision()) { + case REVISION_C4: + if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) { + /* 512MB DDR */ + *mcfg = NUMONYX_V_MCFG_165(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) { + /* Beagleboard Rev C5, 256MB DDR */ + *mcfg = MICRON_V_MCFG_200(256 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + break; + } + case REVISION_XM_A: + case REVISION_XM_B: + case REVISION_XM_C: + if (pop_mfr == 0) { + /* 256MB DDR */ + *mcfg = MICRON_V_MCFG_200(256 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } else { + /* 512MB DDR */ + *mcfg = NUMONYX_V_MCFG_165(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } + break; + default: + /* Assume 128MB and Micron/165MHz timings to be safe */ + *mcfg = MICRON_V_MCFG_165(128 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } +} +#endif + /* * Routine: get_expansion_id * Description: This function checks for expansion board by checking I2C @@ -367,7 +432,7 @@ void set_muxconf_regs(void) MUX_BEAGLE(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); @@ -476,6 +541,7 @@ int ehci_hcd_init(void) #endif /* CONFIG_USB_EHCI */ +#ifndef CONFIG_SPL_BUILD /* * This command returns the status of the user button on beagle xM * Input - none @@ -528,3 +594,4 @@ U_BOOT_CMD( "Return the status of the BeagleBoard USER button", "" ); +#endif diff --git a/board/ti/beagle/config.mk b/board/ti/beagle/config.mk deleted file mode 100644 index cf055db..0000000 --- a/board/ti/beagle/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, -# -# Beagle Board uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index a33aa41..91af8a0 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -110,9 +110,6 @@ #define STATUS_LED_BOOT STATUS_LED_BIT #define STATUS_LED_GREEN STATUS_LED_BIT1 -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* Enable Multi Bus support for I2C */ #define CONFIG_I2C_MULTI_BUS 1 @@ -342,7 +339,6 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /*----------------------------------------------------------------------- @@ -384,4 +380,59 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (45 * 1024) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_OMAP3_ID_NAND +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #endif /* __CONFIG_H */ -- cgit v0.10.2 From 673283f3fc2583a56b3be995cd341159428734ba Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:09 +0000 Subject: OMAP3: Add SPL support to omap3_evm Add Hynix 200MHz timing information to . This also changes CONFIG_SYS_TEXT_BASE to 0x80100000. Signed-off-by: Tom Rini diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 4ea5f74..5fd02d4 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -123,6 +123,32 @@ enum { V_MCFG_BANKALLOCATION_RBC | \ V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR +/* Hynix part of AM/DM37xEVM (200MHz optimized) */ +#define HYNIX_TDAL_200 6 +#define HYNIX_TDPL_200 3 +#define HYNIX_TRRD_200 2 +#define HYNIX_TRCD_200 4 +#define HYNIX_TRP_200 3 +#define HYNIX_TRAS_200 8 +#define HYNIX_TRC_200 11 +#define HYNIX_TRFC_200 18 +#define HYNIX_V_ACTIMA_200 \ + ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \ + HYNIX_TRAS_200, HYNIX_TRP_200, \ + HYNIX_TRCD_200, HYNIX_TRRD_200, \ + HYNIX_TDPL_200, HYNIX_TDAL_200) + +#define HYNIX_TWTR_200 2 +#define HYNIX_TCKE_200 1 +#define HYNIX_TXP_200 1 +#define HYNIX_XSR_200 28 +#define HYNIX_V_ACTIMB_200 \ + ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \ + HYNIX_TXP_200, HYNIX_XSR_200) + +#define HYNIX_RASWIDTH_200 0x3 +#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200) + /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ /* 15/6 + 18/6 = 5.5 -> 6 */ diff --git a/board/ti/evm/config.mk b/board/ti/evm/config.mk deleted file mode 100644 index d173eef..0000000 --- a/board/ti/evm/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 - 2008 -# Texas Instruments, -# -# EVM uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 8c43463..8497aee 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2008 + * (C) Copyright 2004-2011 * Texas Instruments, * * Author : @@ -37,6 +37,7 @@ #include #include #include +#include #include "evm.h" #define OMAP3EVM_GPIO_ETH_RST_GEN1 64 @@ -119,6 +120,42 @@ int board_init(void) return 0; } +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + int pop_mfr, pop_id; + + /* + * We need to identify what PoP memory is on the board so that + * we know what timings to use. To map the ID values please see + * nand_ids.c + */ + identify_nand_chip(&pop_mfr, &pop_id); + + if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { + /* 256MB DDR */ + *mcfg = HYNIX_V_MCFG_200(256 << 20); + *ctrla = HYNIX_V_ACTIMA_200; + *ctrlb = HYNIX_V_ACTIMB_200; + } else { + /* 128MB DDR */ + *mcfg = MICRON_V_MCFG_165(128 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + } + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + *mr = MICRON_V_MR_165; +} +#endif + /* * Routine: misc_init_r * Description: Init ethernet (done here so udelay works) @@ -238,7 +275,7 @@ int board_eth_init(bd_t *bis) } #endif /* CONFIG_CMD_NET */ -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 9228ef1..2ce3959 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -83,8 +83,21 @@ #define CONFIG_MMC #define CONFIG_GENERIC_MMC #define CONFIG_OMAP_HSMMC -#define CONFIG_DOS_PARTITION + +/* SPL */ +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +/* Partition tables */ +/* Only need DOS partition support for SPL, currently */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_EFI_PARTITION +#endif +#define CONFIG_DOS_PARTITION /* USB * @@ -95,6 +108,26 @@ #define CONFIG_MUSB_HCD /* #define CONFIG_MUSB_UDC */ +/* NAND SPL */ +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + /* ----------------------------------------------------------------------------- * Include common board configuration * ----------------------------------------------------------------------------- diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index d62d2ab..b256317 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -26,7 +26,6 @@ #define CONFIG_SDRC /* The chip has SDRC controller */ #define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */ -#define CONFIG_OMAP3_MICRON_DDR /* with MICRON DDR part */ #define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */ #undef CONFIG_USE_IRQ /* no support for IRQs */ @@ -65,7 +64,6 @@ */ #define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* Limits for memtest */ @@ -282,4 +280,32 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (45 * 1024) /* 45 KB */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_OMAP3_ID_NAND +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #endif /* __OMAP3_EVM_COMMON_H */ diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h index 691e4c2..912da7d 100644 --- a/include/configs/omap3_evm_quick_mmc.h +++ b/include/configs/omap3_evm_quick_mmc.h @@ -88,4 +88,14 @@ "root=/dev/mmcblk0p2 rw " \ "rootfstype=ext3 rootwait" +/* + * SPL + */ +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + #endif /* __OMAP3_EVM_QUICK_MMC_H */ diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h index 2d18314..2f879c0 100644 --- a/include/configs/omap3_evm_quick_nand.h +++ b/include/configs/omap3_evm_quick_nand.h @@ -76,4 +76,26 @@ "root=/dev/mtdblock4 rw " \ "rootfstype=jffs2 " +/* + * SPL + */ +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + #endif /* __OMAP3_EVM_QUICK_NAND_H */ -- cgit v0.10.2 From 5059a2a471beb920c11a4f2150d060458a6885a8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:10 +0000 Subject: AM3517: Add SPL support The only change of note is that we move from 0x80008000 to 0x80100000 for CONFIG_SYS_TEXT_BASE Cc: Vaibhav Hiremath Signed-off-by: Tom Rini diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index c0a006a..0a105bf 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -76,7 +76,7 @@ void set_muxconf_regs(void) MUX_AM3517EVM(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/board/logicpd/am3517evm/config.mk b/board/logicpd/am3517evm/config.mk deleted file mode 100644 index 71ec5d0..0000000 --- a/board/logicpd/am3517evm/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# Author: Vaibhav Hiremath -# -# Based on ti/evm/config.mk -# -# Copyright (C) 2010 -# Texas Instruments Incorporated - http://www.ti.com/ -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index dfe186c..d44eeec 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -63,7 +63,6 @@ /* * DDR related */ -#define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */ #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) /* @@ -269,7 +268,6 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /*----------------------------------------------------------------------- @@ -324,4 +322,59 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (45 * 1024) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #endif /* __CONFIG_H */ -- cgit v0.10.2 From d067cc464fd10f9473bcedef94805a167d0525cb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:11 +0000 Subject: AM3517 CraneBoard: Add SPL support The only change of note is that we move from 0x80008000 to 0x80100000 for CONFIG_SYS_TEXT_BASE Cc: Nagendra T S Tested-by: Koen Kooi Signed-off-by: Tom Rini diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index cd5683d..436645a 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -75,7 +75,7 @@ void set_muxconf_regs(void) MUX_AM3517CRANE(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/board/ti/am3517crane/config.mk b/board/ti/am3517crane/config.mk deleted file mode 100644 index c6a18b5..0000000 --- a/board/ti/am3517crane/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# Author: Srinath R -# -# Based on logicpd/am3517evm/config.mk -# -# Copyright (C) 2011 Mistral Solutions Pvt Ltd -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 0a62e36..0a0c261 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -64,7 +64,6 @@ /* * DDR related */ -#define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */ #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) /* @@ -270,7 +269,6 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /*----------------------------------------------------------------------- @@ -323,4 +321,59 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (45 * 1024) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #endif /* __CONFIG_H */ -- cgit v0.10.2 From ee08a8260a3a7f6ef2001cfa3e7b6137b485f40a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 23 Nov 2011 05:13:06 +0000 Subject: OMAP3: Add SPL_BOARD_INIT hook Add an SPL_BOARD_INIT hook and for OMAP3 have it turn on i2c. OMAP4 doesn't need i2c enabled in SPL. Enable SPL_BOARD_INIT on devkit8000. Cc: Frederik Kriewitz Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index f72d389..25f04ed 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -116,6 +116,10 @@ void board_init_r(gd_t *id, ulong dummy) timer_init(); +#ifdef CONFIG_SPL_BOARD_INIT + spl_board_init(); +#endif + boot_device = omap_boot_device(); debug("boot device - %d\n", boot_device); switch (boot_device) { diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index cdf452d..1f33c63 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -40,6 +40,7 @@ #include #include #include +#include /* Declarations */ extern omap3_sysinfo sysinfo; @@ -89,6 +90,10 @@ u32 omap_boot_device(void) return omap3_boot_device; } +void spl_board_init(void) +{ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +} #endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 913231b..1ec651b 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -94,6 +94,10 @@ void spl_nand_load_image(void); /* MMC SPL functions */ void spl_mmc_load_image(void); +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void); +#endif + /* * silicon revisions. * Moving this to common, so that most of code can be moved to common, diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 4b58dc3..c090d2b 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -304,6 +304,7 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT -- cgit v0.10.2 From 73128aad5847cceef7adf691a66e56260f7747ea Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 15 Nov 2011 05:51:29 +0000 Subject: mx53loco: Configure the pins as GPIOs prior to using gpio_get_value Configure the pins as GPIO prior to using gpio_get_value. Cc: Jason Liu Signed-off-by: Fabio Estevam Acked-by: Jason Liu diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index b4c7f33..3cf4195 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -140,6 +140,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) *cd = gpio_get_value(77); /*GPIO3_13*/ else -- cgit v0.10.2 From d59c33a1f32c1b440cce6ebee46967cbc1be48ae Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 15 Nov 2011 05:51:30 +0000 Subject: mx53ard: Configure the pins as GPIOs prior to using gpio_get_value Configure the pins as GPIO prior to using gpio_get_value. Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index be32aee..e5a1142 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -87,6 +87,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1); + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) *cd = gpio_get_value(1); /*GPIO1_1*/ else -- cgit v0.10.2 From a146dca5c2c422309669c99f04eca90ad810e264 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 15 Nov 2011 05:51:31 +0000 Subject: mx53evk: Configure the pins as GPIOs prior to using gpio_get_value Configure the pins as GPIO prior to using gpio_get_value. Cc: Jason Liu Signed-off-by: Fabio Estevam Acked-by: Jason Liu diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index 335661f..aa4a2c9 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -212,6 +212,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) *cd = gpio_get_value(77); /*GPIO3_13*/ else -- cgit v0.10.2 From 3ee3729e95da0f12126fe26c0c05f34405061920 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 15 Nov 2011 05:51:32 +0000 Subject: mx53smd: Configure the pins as GPIOs prior to using gpio_get_value Configure the pins as GPIO prior to using gpio_get_value. Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index 87fa7fa..55af4e4 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -134,6 +134,7 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = { int board_mmc_getcd(u8 *cd, struct mmc *mmc) { + mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); *cd = gpio_get_value(77); /*GPIO3_13*/ return 0; -- cgit v0.10.2 From 58aef72d891ab46e3fbf775a43782143817354ba Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 15 Nov 2011 05:51:33 +0000 Subject: mx51evk: Configure the pins as GPIOs prior to using gpio_get_value Configure the pins as GPIO prior to using gpio_get_value. Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 37e6e4d..e5b0929 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -265,6 +265,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) *cd = gpio_get_value(0); else -- cgit v0.10.2 From 761e83a9a9a2c024f02c746da03b8c6d938fa4a7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 28 Sep 2011 02:07:26 +0000 Subject: MC13892: Add REGMODE0 bits definitions Signed-off-by: Marek Vasut Cc: Stefano Babic diff --git a/include/mc13892.h b/include/mc13892.h index 8138bb7..ea41272 100644 --- a/include/mc13892.h +++ b/include/mc13892.h @@ -139,6 +139,22 @@ #define VCAM_3_0 (3 << 16) #define VCAM_MASK (3 << 16) +/* Reg Mode 0 */ +#define VGEN1EN (1 << 0) +#define VGEN1STBY (1 << 1) +#define VGEN1MODE (1 << 2) +#define VIOHIEN (1 << 3) +#define VIOHISTBY (1 << 4) +#define VDIGEN (1 << 9) +#define VDIGSTBY (1 << 10) +#define VGEN2EN (1 << 12) +#define VGEN2STBY (1 << 13) +#define VGEN2MODE (1 << 14) +#define VPLLEN (1 << 15) +#define VPLLSTBY (1 << 16) +#define VUSBEN (1 << 18) +#define VUSBSTBY (1 << 19) + /* Reg Mode 1 */ #define VGEN3EN (1 << 0) #define VGEN3STBY (1 << 1) -- cgit v0.10.2 From 5acc90729488328665ebee7bc7ae2fb6c9e08c3a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 5 Nov 2011 04:25:22 +0000 Subject: mx5: Correct a warning in clock.c This corects the warning below, obtained with my gcc 4.6 compiler. arch/arm/cpu/armv7/mx5/libmx5.o: In function `decode_pll': arch/arm/cpu/armv7/mx5/clock.c:94: undefined reference to `__aeabi_uldivmod' I am not able to test this on MX5x hardware, but it does improve the MAKEALL output for me. You may already have a similar patch, but I cannot see it on the list. Signed-off-by: Simon Glass diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 0769a64..933ce05 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -91,7 +91,7 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq) if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN) refclk *= 2; - refclk /= pdf + 1; + do_div(refclk, pdf + 1); temp = refclk * mfn_abs; do_div(temp, mfd + 1); ret = refclk * mfi; -- cgit v0.10.2 From 55723954829f30cf148924ee55d10b1662551edc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 28 Sep 2011 02:19:57 +0000 Subject: Efika: Configure additional regulators for HDMI output Signed-off-by: Marek Vasut Cc: Stefano Babic diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c index b78bf6c..3d2cc1a 100644 --- a/board/efikamx/efikamx.c +++ b/board/efikamx/efikamx.c @@ -226,7 +226,7 @@ static void power_init(void) /* Set core voltage to 1.1V */ pmic_reg_read(p, REG_SW_0, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; + val = (val & ~SWx_VOLT_MASK) | SWx_1_200V; pmic_reg_write(p, REG_SW_0, val); /* Setup VCC (SW2) to 1.25 */ @@ -260,18 +260,23 @@ static void power_init(void) (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); pmic_reg_write(p, REG_SW_5, val); - /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */ + /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */ pmic_reg_read(p, REG_SETTING_0, &val); val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); - val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6; + val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6; pmic_reg_write(p, REG_SETTING_0, val); /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ pmic_reg_read(p, REG_SETTING_1, &val); val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); - val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775; + val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15; pmic_reg_write(p, REG_SETTING_1, val); + /* Enable VGEN1, VGEN2, VDIG, VPLL */ + pmic_reg_read(p, REG_MODE_0, &val); + val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN; + pmic_reg_write(p, REG_MODE_0, val); + /* Configure VGEN3 and VCAM regulators to use external PNP */ val = VGEN3CONFIG | VCAMCONFIG; pmic_reg_write(p, REG_MODE_1, val); @@ -279,7 +284,7 @@ static void power_init(void) /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | - VVIDEOEN | VAUDIOEN | VSDEN; + VVIDEOEN | VAUDIOEN | VSDEN; pmic_reg_write(p, REG_MODE_1, val); pmic_reg_read(p, REG_POWER_CTL2, &val); -- cgit v0.10.2 From 12dab4ce85a7dc2cb2e4d813696ed47ed44fb24e Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 18 Nov 2011 01:17:44 +0000 Subject: apbh_dma: return error value on timeout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When a timeout occurs, the return value is prepared but never returned. Fix that. Signed-off-by: Uwe Kleine-König Signed-off-by: Wolfram Sang Cc: Marek Vasut Acked-by: Stefano Babic diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index 69a1042..4000974 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -606,7 +606,7 @@ int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan) mxs_dma_reset(chan); } - return 0; + return ret; } /* -- cgit v0.10.2 From aa72e43bb77353f8f33f4f5c7484a48084495e50 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 23 Nov 2011 10:59:13 +0000 Subject: MXS: Add static annotations to dma driver Some functions were internal to the apbh dma driver, so annotate them static. Some of the functions weren't used at all so drop them. This makes the U-Boot binary smaller by about 1500 bytes. Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Wolfgang Denk Acked-by: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx28/dma.h b/arch/arm/include/asm/arch-mx28/dma.h index 7061e7c..52747e2 100644 --- a/arch/arm/include/asm/arch-mx28/dma.h +++ b/arch/arm/include/asm/arch-mx28/dma.h @@ -135,36 +135,11 @@ struct mxs_dma_chan { struct list_head done; }; -/* Hardware management ops */ -int mxs_dma_enable(int channel); -int mxs_dma_disable(int channel); -int mxs_dma_reset(int channel); -int mxs_dma_freeze(int channel); -int mxs_dma_unfreeze(int channel); -int mxs_dma_read_semaphore(int channel); -int mxs_dma_enable_irq(int channel, int enable); -int mxs_dma_irq_is_pending(int channel); -int mxs_dma_ack_irq(int channel); - -/* Channel management ops */ -int mxs_dma_request(int channel); -int mxs_dma_release(int channel); - -/* Descriptor management ops */ struct mxs_dma_desc *mxs_dma_desc_alloc(void); void mxs_dma_desc_free(struct mxs_dma_desc *); - -unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc); -int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc); - int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); -int mxs_dma_get_finished(int channel, struct list_head *head); -int mxs_dma_finish(int channel, struct list_head *head); - -int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan); int mxs_dma_go(int chan); - int mxs_dma_init(void); #endif /* __DMA_H__ */ diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index 4000974..e85f5fe 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -53,6 +53,47 @@ int mxs_dma_validate_chan(int channel) } /* + * Return the address of the command within a descriptor. + */ +static unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc) +{ + return desc->address + offsetof(struct mxs_dma_desc, cmd); +} + +/* + * Read a DMA channel's hardware semaphore. + * + * As used by the MXS platform's DMA software, the DMA channel's hardware + * semaphore reflects the number of DMA commands the hardware will process, but + * has not yet finished. This is a volatile value read directly from hardware, + * so it must be be viewed as immediately stale. + * + * If the channel is not marked busy, or has finished processing all its + * commands, this value should be zero. + * + * See mxs_dma_append() for details on how DMA command blocks must be configured + * to maintain the expected behavior of the semaphore's value. + */ +static int mxs_dma_read_semaphore(int channel) +{ + struct mx28_apbh_regs *apbh_regs = + (struct mx28_apbh_regs *)MXS_APBH_BASE; + uint32_t tmp; + int ret; + + ret = mxs_dma_validate_chan(channel); + if (ret) + return ret; + + tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema); + + tmp &= APBH_CHn_SEMA_PHORE_MASK; + tmp >>= APBH_CHn_SEMA_PHORE_OFFSET; + + return tmp; +} + +/* * Enable a DMA channel. * * If the given channel has any DMA descriptors on its active list, this @@ -61,7 +102,7 @@ int mxs_dma_validate_chan(int channel) * This function marks the DMA channel as "busy," whether or not there are any * descriptors to process. */ -int mxs_dma_enable(int channel) +static int mxs_dma_enable(int channel) { struct mx28_apbh_regs *apbh_regs = (struct mx28_apbh_regs *)MXS_APBH_BASE; @@ -132,7 +173,7 @@ int mxs_dma_enable(int channel) * state. It is unwise to call this function if there is ANY chance the hardware * is still processing a command. */ -int mxs_dma_disable(int channel) +static int mxs_dma_disable(int channel) { struct mxs_dma_chan *pchan; struct mx28_apbh_regs *apbh_regs = @@ -162,7 +203,7 @@ int mxs_dma_disable(int channel) /* * Resets the DMA channel hardware. */ -int mxs_dma_reset(int channel) +static int mxs_dma_reset(int channel) { struct mx28_apbh_regs *apbh_regs = (struct mx28_apbh_regs *)MXS_APBH_BASE; @@ -179,90 +220,11 @@ int mxs_dma_reset(int channel) } /* - * Freeze a DMA channel. - * - * This function causes the channel to continuously fail arbitration for bus - * access, which halts all forward progress without losing any state. A call to - * mxs_dma_unfreeze() will cause the channel to continue its current operation - * with no ill effect. - */ -int mxs_dma_freeze(int channel) -{ - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - int ret; - - ret = mxs_dma_validate_chan(channel); - if (ret) - return ret; - - writel(1 << (channel + APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET), - &apbh_regs->hw_apbh_channel_ctrl_set); - - return 0; -} - -/* - * Unfreeze a DMA channel. - * - * This function reverses the effect of mxs_dma_freeze(), enabling the DMA - * channel to continue from where it was frozen. - */ -int mxs_dma_unfreeze(int channel) -{ - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - int ret; - - ret = mxs_dma_validate_chan(channel); - if (ret) - return ret; - - writel(1 << (channel + APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET), - &apbh_regs->hw_apbh_channel_ctrl_clr); - - return 0; -} - -/* - * Read a DMA channel's hardware semaphore. - * - * As used by the MXS platform's DMA software, the DMA channel's hardware - * semaphore reflects the number of DMA commands the hardware will process, but - * has not yet finished. This is a volatile value read directly from hardware, - * so it must be be viewed as immediately stale. - * - * If the channel is not marked busy, or has finished processing all its - * commands, this value should be zero. - * - * See mxs_dma_append() for details on how DMA command blocks must be configured - * to maintain the expected behavior of the semaphore's value. - */ -int mxs_dma_read_semaphore(int channel) -{ - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - uint32_t tmp; - int ret; - - ret = mxs_dma_validate_chan(channel); - if (ret) - return ret; - - tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema); - - tmp &= APBH_CHn_SEMA_PHORE_MASK; - tmp >>= APBH_CHn_SEMA_PHORE_OFFSET; - - return tmp; -} - -/* * Enable or disable DMA interrupt. * * This function enables the given DMA channel to interrupt the CPU. */ -int mxs_dma_enable_irq(int channel, int enable) +static int mxs_dma_enable_irq(int channel, int enable) { struct mx28_apbh_regs *apbh_regs = (struct mx28_apbh_regs *)MXS_APBH_BASE; @@ -283,32 +245,12 @@ int mxs_dma_enable_irq(int channel, int enable) } /* - * Check if a DMA interrupt is pending. - */ -int mxs_dma_irq_is_pending(int channel) -{ - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - uint32_t tmp; - int ret; - - ret = mxs_dma_validate_chan(channel); - if (ret) - return ret; - - tmp = readl(&apbh_regs->hw_apbh_ctrl1); - tmp |= readl(&apbh_regs->hw_apbh_ctrl2); - - return (tmp >> channel) & 1; -} - -/* * Clear DMA interrupt. * * The software that is using the DMA channel must register to receive its * interrupts and, when they arrive, must call this function to clear them. */ -int mxs_dma_ack_irq(int channel) +static int mxs_dma_ack_irq(int channel) { struct mx28_apbh_regs *apbh_regs = (struct mx28_apbh_regs *)MXS_APBH_BASE; @@ -327,7 +269,7 @@ int mxs_dma_ack_irq(int channel) /* * Request to reserve a DMA channel */ -int mxs_dma_request(int channel) +static int mxs_dma_request(int channel) { struct mxs_dma_chan *pchan; @@ -359,7 +301,7 @@ int mxs_dma_request(int channel) * The channel will NOT be released if it's marked "busy" (see * mxs_dma_enable()). */ -int mxs_dma_release(int channel) +static int mxs_dma_release(int channel) { struct mxs_dma_chan *pchan; int ret; @@ -411,32 +353,6 @@ void mxs_dma_desc_free(struct mxs_dma_desc *pdesc) } /* - * Return the address of the command within a descriptor. - */ -unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc) -{ - return desc->address + offsetof(struct mxs_dma_desc, cmd); -} - -/* - * Check if descriptor is on a channel's active list. - * - * This function returns the state of a descriptor's "ready" flag. This flag is - * usually set only if the descriptor appears on a channel's active list. The - * descriptor may or may not have already been processed by the hardware. - * - * The "ready" flag is set when the descriptor is submitted to a channel by a - * call to mxs_dma_append() or mxs_dma_append_list(). The "ready" flag is - * cleared when a processed descriptor is moved off the active list by a call - * to mxs_dma_finish(). The "ready" flag is NOT cleared if the descriptor is - * aborted by a call to mxs_dma_disable(). - */ -int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc) -{ - return pdesc->flags & MXS_DMA_DESC_READY; -} - -/* * Add a DMA descriptor to a channel. * * If the descriptor list for this channel is not empty, this function sets the @@ -509,31 +425,6 @@ int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc) } /* - * Retrieve processed DMA descriptors. - * - * This function moves all the descriptors from the DMA channel's "done" list to - * the head of the given list. - */ -int mxs_dma_get_finished(int channel, struct list_head *head) -{ - struct mxs_dma_chan *pchan; - int ret; - - ret = mxs_dma_validate_chan(channel); - if (ret) - return ret; - - if (head == NULL) - return 0; - - pchan = mxs_dma_channels + channel; - - list_splice(&pchan->done, head); - - return 0; -} - -/* * Clean up processed DMA descriptors. * * This function removes processed DMA descriptors from the "active" list. Pass @@ -544,7 +435,7 @@ int mxs_dma_get_finished(int channel, struct list_head *head) * This function marks the DMA channel as "not busy" if no unprocessed * descriptors remain on the "active" list. */ -int mxs_dma_finish(int channel, struct list_head *head) +static int mxs_dma_finish(int channel, struct list_head *head) { int sem; struct mxs_dma_chan *pchan; @@ -590,7 +481,7 @@ int mxs_dma_finish(int channel, struct list_head *head) /* * Wait for DMA channel to complete */ -int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan) +static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan) { struct mx28_apbh_regs *apbh_regs = (struct mx28_apbh_regs *)MXS_APBH_BASE; -- cgit v0.10.2 From 5a42cd33d5600e90245fe4fa979d888753b081de Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20Deli=C3=ABn?= Date: Tue, 22 Nov 2011 04:14:22 +0000 Subject: M28: Fix OB1 bug in GPIO driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch fixes a small off-by-one bug in the GPIO driver for the mxs platform that allowed the selection gpio pins of one bank more than the SoC actually has. Signed-off-by: Robert Deliën Acked-by: Marek Vasut Acked-by: Marek Vasut diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index b7e9591..539738b 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -120,7 +120,7 @@ int gpio_direction_output(int gp, int value) int gpio_request(int gp, const char *label) { - if (PAD_BANK(gp) > PINCTRL_BANKS) + if (PAD_BANK(gp) >= PINCTRL_BANKS) return -EINVAL; return 0; -- cgit v0.10.2 From 40f6fffee5917930597bfcc07de1cd879d4994f6 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 22 Nov 2011 15:22:39 +0100 Subject: MX: serial_mxc: cleanup removing nasty #ifdef The serial driver for iMX SOCs is continuosly changed if a new SOC or not yet used port is used. CONFIG_SYS__ defines were used only to find the base address for the selected UART. Instead of that, move the base address to the board configuration file and drop all #ifdef from driver. Signed-off-by: Stefano Babic CC: Marek Vasut CC: Wolfgang Denk CC: Fabio Estevam CC: Helmut Raiger CC: John Rigby CC: Matthias Weisser CC: Jason Liu Acked-by: Jason Liu diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c index b42dac3..2ebee2e 100644 --- a/arch/arm/cpu/arm1136/mx31/devices.c +++ b/arch/arm/cpu/arm1136/mx31/devices.c @@ -27,7 +27,6 @@ #include #include -#ifdef CONFIG_SYS_MX31_UART1 void mx31_uart1_hw_init(void) { /* setup pins for UART1 */ @@ -36,9 +35,7 @@ void mx31_uart1_hw_init(void) mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); } -#endif -#ifdef CONFIG_SYS_MX31_UART2 void mx31_uart2_hw_init(void) { /* setup pins for UART2 */ @@ -47,7 +44,6 @@ void mx31_uart2_hw_init(void) mx31_gpio_mux(MUX_RTS2__UART2_RTS_B); mx31_gpio_mux(MUX_CTS2__UART2_CTS_B); } -#endif #ifdef CONFIG_MXC_SPI /* diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index eece138..7f9449b 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -180,8 +180,8 @@ struct aips_regs { #define IMX_I2C3_BASE (0x43F84000) #define IMX_CAN1_BASE (0x43F88000) #define IMX_CAN2_BASE (0x43F8C000) -#define IMX_UART1_BASE (0x43F90000) -#define IMX_UART2_BASE (0x43F94000) +#define UART1_BASE (0x43F90000) +#define UART2_BASE (0x43F94000) #define IMX_I2C2_BASE (0x43F98000) #define IMX_OWIRE_BASE (0x43F9C000) #define IMX_CSPI1_BASE (0x43FA4000) @@ -197,15 +197,15 @@ struct aips_regs { /* SPBA */ #define IMX_SPBA_BASE (0x50000000) #define IMX_CSPI3_BASE (0x50004000) -#define IMX_UART4_BASE (0x50008000) -#define IMX_UART3_BASE (0x5000C000) +#define UART4_BASE (0x50008000) +#define UART3_BASE (0x5000C000) #define IMX_CSPI2_BASE (0x50010000) #define IMX_SSI2_BASE (0x50014000) #define IMX_ESAI_BASE (0x50018000) #define IMX_ATA_DMA_BASE (0x50020000) #define IMX_SIM1_BASE (0x50024000) #define IMX_SIM2_BASE (0x50028000) -#define IMX_UART5_BASE (0x5002C000) +#define UART5_BASE (0x5002C000) #define IMX_TSC_BASE (0x50030000) #define IMX_SSI1_BASE (0x50034000) #define IMX_FEC_BASE (0x50038000) diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index 83ab216..ced5b2a 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -224,10 +224,10 @@ struct fuse_bank0_regs { #define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) #define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) #define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) -#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) -#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) -#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) -#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) +#define UART1_BASE (0x0a000 + IMX_IO_BASE) +#define UART2_BASE (0x0b000 + IMX_IO_BASE) +#define UART3_BASE (0x0c000 + IMX_IO_BASE) +#define UART4_BASE (0x0d000 + IMX_IO_BASE) #define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE) #define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) #define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 0147920..6a517dd 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -600,6 +600,12 @@ struct esdc_regs { #define WEIM_ESDCFG1 0xB800100C #define WEIM_ESDMISC 0xB8001010 +#define UART1_BASE 0x43F90000 +#define UART2_BASE 0x43F94000 +#define UART3_BASE 0x5000C000 +#define UART4_BASE 0x43FB0000 +#define UART5_BASE 0x43FB4000 + #define ESDCTL_SDE (1 << 31) #define ESDCTL_CMD_RW (0 << 28) #define ESDCTL_CMD_PRECHARGE (1 << 28) diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index 25c324e..df74508 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -42,8 +42,8 @@ #define I2C_BASE_ADDR 0x43F80000 #define I2C3_BASE_ADDR 0x43F84000 #define ATA_BASE_ADDR 0x43F8C000 -#define UART1_BASE_ADDR 0x43F90000 -#define UART2_BASE_ADDR 0x43F94000 +#define UART1_BASE 0x43F90000 +#define UART2_BASE 0x43F94000 #define I2C2_BASE_ADDR 0x43F98000 #define CSPI1_BASE_ADDR 0x43FA4000 #define IOMUXC_BASE_ADDR 0x43FAC000 @@ -52,7 +52,7 @@ * SPBA */ #define SPBA_BASE_ADDR 0x50000000 -#define UART3_BASE_ADDR 0x5000C000 +#define UART3_BASE 0x5000C000 #define CSPI2_BASE_ADDR 0x50010000 #define ATA_DMA_BASE_ADDR 0x50020000 #define FEC_BASE_ADDR 0x50038000 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index d069209..0ee88d2 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -54,7 +54,7 @@ */ #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) -#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) +#define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000) #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) @@ -83,8 +83,8 @@ #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) -#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) -#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) +#define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000) +#define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000) #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index dcb4bd1..af00b9c 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -24,41 +24,12 @@ #define __REG(x) (*((volatile u32 *)(x))) -#if defined(CONFIG_SYS_MX31_UART1) || defined(CONFIG_SYS_MX25_UART1) -#define UART_PHYS 0x43f90000 -#elif defined(CONFIG_SYS_MX31_UART2) || defined(CONFIG_SYS_MX25_UART2) -#define UART_PHYS 0x43f94000 -#elif defined(CONFIG_SYS_MX31_UART3) || defined(CONFIG_SYS_MX25_UART3) -#define UART_PHYS 0x5000c000 -#elif defined(CONFIG_SYS_MX31_UART4) || defined(CONFIG_SYS_MX25_UART4) -#define UART_PHYS 0x43fb0000 -#elif defined(CONFIG_SYS_MX31_UART5) || defined(CONFIG_SYS_MX25_UART5) -#define UART_PHYS 0x43fb4000 -#elif defined(CONFIG_SYS_MX27_UART1) -#define UART_PHYS 0x1000a000 -#elif defined(CONFIG_SYS_MX27_UART2) -#define UART_PHYS 0x1000b000 -#elif defined(CONFIG_SYS_MX27_UART3) -#define UART_PHYS 0x1000c000 -#elif defined(CONFIG_SYS_MX27_UART4) -#define UART_PHYS 0x1000d000 -#elif defined(CONFIG_SYS_MX27_UART5) -#define UART_PHYS 0x1001b000 -#elif defined(CONFIG_SYS_MX27_UART6) -#define UART_PHYS 0x1001c000 -#elif defined(CONFIG_SYS_MX35_UART1) || defined(CONFIG_SYS_MX51_UART1) || \ - defined(CONFIG_SYS_MX53_UART1) -#define UART_PHYS UART1_BASE_ADDR -#elif defined(CONFIG_SYS_MX35_UART2) || defined(CONFIG_SYS_MX51_UART2) || \ - defined(CONFIG_SYS_MX53_UART2) -#define UART_PHYS UART2_BASE_ADDR -#elif defined(CONFIG_SYS_MX35_UART3) || defined(CONFIG_SYS_MX51_UART3) || \ - defined(CONFIG_SYS_MX53_UART3) -#define UART_PHYS UART3_BASE_ADDR -#else -#error "define CONFIG_SYS_MXxx_UARTx to use the MXC UART driver" +#ifndef CONFIG_MXC_UART_BASE +#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver" #endif +#define UART_PHYS CONFIG_MXC_UART_BASE + #ifdef CONFIG_SERIAL_MULTI #warning "MXC driver does not support MULTI serials." #endif diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h index a07c8b5..2b069d6 100644 --- a/include/configs/efikamx.h +++ b/include/configs/efikamx.h @@ -85,7 +85,7 @@ * Hardware drivers */ #define CONFIG_MXC_UART -#define CONFIG_SYS_MX51_UART1 +#define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/flea3.h b/include/configs/flea3.h index d88c578..20100c2 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -77,7 +77,7 @@ * UART (console) */ #define CONFIG_MXC_UART -#define CONFIG_SYS_MX35_UART3 +#define CONFIG_MXC_UART_BASE UART3_BASE /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 6953a80..2af4e7a 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -102,7 +102,7 @@ * Serial Driver info */ #define CONFIG_MXC_UART -#define CONFIG_SYS_MX27_UART1 +#define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 1455ea2..bbcbce1 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -63,8 +63,8 @@ * Hardware drivers */ -#define CONFIG_MXC_UART 1 -#define CONFIG_SYS_MX31_UART1 1 +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_MXC_GPIO #define CONFIG_HARD_SPI 1 diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 1b75197..3153eb5 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -59,7 +59,7 @@ #define CONFIG_SYS_I2C_SLAVE 0xfe #define CONFIG_MXC_UART -#define CONFIG_SYS_MX31_UART1 +#define CONFIG_MXC_UART_BASE UART1_BASE /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index 8414376..d1ba02b 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -54,7 +54,7 @@ /* Serial Info */ #define CONFIG_MXC_UART -#define CONFIG_SYS_MX25_UART1 +#define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 7e011ae..87638a4 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -60,8 +60,8 @@ * Hardware drivers */ -#define CONFIG_MXC_UART 1 -#define CONFIG_SYS_MX31_UART1 1 +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 4253c3e..4da6020 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -61,7 +61,7 @@ */ #define CONFIG_MXC_UART -#define CONFIG_SYS_MX31_UART1 +#define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_HW_WATCHDOG #define CONFIG_MXC_GPIO diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 32ed609..0c62b9f 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -85,7 +85,7 @@ * UART (console) */ #define CONFIG_MXC_UART -#define CONFIG_SYS_MX35_UART1 +#define CONFIG_MXC_UART_BASE UART1_BASE /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 7c7544f..dd53f48 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -59,7 +59,7 @@ * Hardware drivers */ #define CONFIG_MXC_UART -#define CONFIG_SYS_MX51_UART1 +#define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_MXC_GPIO /* diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 15dfcb4..f48a41e 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -44,7 +44,7 @@ #define CONFIG_MXC_GPIO #define CONFIG_MXC_UART -#define CONFIG_SYS_MX53_UART1 +#define CONFIG_MXC_UART_BASE UART1_BASE /* I2C Configs */ #define CONFIG_CMD_I2C diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 7c49136..11fe6ef 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -47,7 +47,7 @@ #define CONFIG_MXC_GPIO #define CONFIG_MXC_UART -#define CONFIG_SYS_MX53_UART1 +#define CONFIG_MXC_UART_BASE UART1_BASE /* I2C Configs */ #define CONFIG_CMD_I2C diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index d699010..537649e 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -45,7 +45,7 @@ #define CONFIG_MXC_GPIO #define CONFIG_MXC_UART -#define CONFIG_SYS_MX53_UART1 +#define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #define CONFIG_FSL_ESDHC diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index 48b32dd..032f722 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -44,7 +44,7 @@ #define CONFIG_MXC_GPIO #define CONFIG_MXC_UART -#define CONFIG_SYS_MX53_UART1 +#define CONFIG_MXC_UART_BASE UART1_BASE /* I2C Configs */ #define CONFIG_CMD_I2C diff --git a/include/configs/qong.h b/include/configs/qong.h index 3346802..3e36bb0 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -49,8 +49,8 @@ * Hardware drivers */ -#define CONFIG_MXC_UART 1 -#define CONFIG_SYS_MX31_UART1 1 +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_MXC_GPIO #define CONFIG_HW_WATCHDOG diff --git a/include/configs/tt01.h b/include/configs/tt01.h index 6ef25cd..a553712 100644 --- a/include/configs/tt01.h +++ b/include/configs/tt01.h @@ -148,7 +148,7 @@ * make sure that the transceiver is enabled during PL=1 for testing! */ #define CONFIG_MXC_UART -#define CONFIG_SYS_MX31_UART2 +#define CONFIG_MXC_UART_BASE UART2_BASE #define CONFIG_MXC_SPI #define CONFIG_MXC_GPIO diff --git a/include/configs/tx25.h b/include/configs/tx25.h index f77c546..87bd8a6 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -90,7 +90,7 @@ * Serial Info */ #define CONFIG_MXC_UART -#define CONFIG_SYS_MX25_UART1 +#define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/vision2.h b/include/configs/vision2.h index f321ad2..35b71f7 100644 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@ -54,7 +54,7 @@ * Hardware drivers */ #define CONFIG_MXC_UART -#define CONFIG_SYS_MX51_UART3 +#define CONFIG_MXC_UART_BASE UART3_BASE #define CONFIG_MXC_GPIO #define CONFIG_MXC_SPI #define CONFIG_HW_WATCHDOG diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 9a7a27a..599d5bb 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -66,7 +66,7 @@ * Serial */ #define CONFIG_MXC_UART -#define CONFIG_SYS_MX25_UART2 +#define CONFIG_MXC_UART_BASE UART2_BASE #define CONFIG_CONS_INDEX 1 /* use UART2 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -- cgit v0.10.2 From fda241d59d12381493f31e38f94a2057a955ec94 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 25 Nov 2011 09:08:36 +0100 Subject: MX35: flea3: changes due to hardware revision B Revision B of the board uses CSD0 for the DRAM, as usual for MX3 boards. The patch fixes also some values in the U-Boot environment. Signed-off-by: Stefano Babic diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c index 64f4b57..34ede87 100644 --- a/board/CarMediaLab/flea3/flea3.c +++ b/board/CarMediaLab/flea3/flea3.c @@ -160,7 +160,7 @@ static void board_setup_sdram(void) writel(0x2000, &esdc->esdctl0); writel(0x2000, &esdc->esdctl1); - board_setup_sdram_bank(CSD1_BASE_ADDR); + board_setup_sdram_bank(CSD0_BASE_ADDR); } static void setup_iomux_uart3(void) @@ -229,7 +229,7 @@ int board_early_init_f(void) (struct ccm_regs *)IMX_CCM_BASE; /* setup GPIO3_1 to set HighVCore signal */ - mxc_request_iomux(MX35_PIN_ATA_DATA1, MUX_CONFIG_ALT5); + mxc_request_iomux(MX35_PIN_ATA_DA1, MUX_CONFIG_ALT5); gpio_direction_output(65, 1); /* initialize PLL and clock configuration */ diff --git a/include/configs/flea3.h b/include/configs/flea3.h index 20100c2..aac3930 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -107,7 +107,7 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ +#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ /* @@ -162,10 +162,10 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD1_BASE_ADDR +#define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE CSD1_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ @@ -181,10 +181,14 @@ #define CONFIG_FLASH_CFI_MTD #define CONFIG_MTD_PARTITIONS #define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0" -#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:196m(root1)," \ - "196m(root2),-(user);" \ +#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:50m(root1)," \ + "32m(rootfb)," \ + "64m(pcache)," \ + "64m(app1)," \ + "10m(app2),-(spool);" \ "physmap-flash.0:512k(u-boot),64k(env1)," \ "64k(env2),3776k(kernel1),3776k(kernel2)" + /* * FLASH and environment organization */ @@ -249,10 +253,10 @@ "else run addip_sta;fi\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ + " console=ttymxc2,${baudrate}\0" \ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ - "loadaddr=90800000\0" \ - "kernel_addr_r=90800000\0" \ + "loadaddr=80800000\0" \ + "kernel_addr_r=80800000\0" \ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \ -- cgit v0.10.2 From b0a86a27ee4133aba2e275a7b680f6cedad7311a Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Sat, 3 Dec 2011 06:46:13 +0000 Subject: arch/arm/cpu/armv7/omap-common/spl.c: Fix GCC 4.2 warnings Fix: spl.c: In function 'jump_to_image_no_args': spl.c:103: warning: assignment makes pointer from integer without a cast spl.c:105: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Anatolij Gustschin Cc: sricharan Cc: Tom Rini Acked-by: Marek Vasut Acked-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index 25f04ed..9c35a09 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -100,9 +100,10 @@ static void jump_to_image_no_args(void) debug("image entry point: 0x%X\n", spl_image.entry_point); /* Pass the saved boot_params from rom code */ #if defined(CONFIG_VIRTIO) || defined(CONFIG_ZEBU) - image_entry = 0x80100000; + image_entry = (image_entry_noargs_t)0x80100000; #endif - image_entry((u32 *)&boot_params_ptr); + u32 boot_params_ptr_addr = (u32)&boot_params_ptr; + image_entry((u32 *)boot_params_ptr_addr); } void jump_to_image_no_args(void) __attribute__ ((noreturn)); -- cgit v0.10.2 From 164a75078917ab83d29a02cd282ee49878b4a349 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Sat, 3 Dec 2011 06:46:14 +0000 Subject: arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix GCC 4.6 warnings Fix: clocks-common.c: In function 'setup_dplls': clocks-common.c:256:6: warning: variable 'sysclk_ind' set but not used [-Wunused-but-set-variable] clocks-common.c: In function 'setup_non_essential_dplls': clocks-common.c:292:6: warning: variable 'sysclk_ind' set but not used [-Wunused-but-set-variable] Signed-off-by: Anatolij Gustschin Cc: sricharan Cc: Tom Rini Acked-by: Marek Vasut Acked-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 1e7e20e..1da90a4 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -253,11 +253,10 @@ void configure_mpu_dpll(void) static void setup_dplls(void) { - u32 sysclk_ind, temp; + u32 temp; const struct dpll_params *params; - debug("setup_dplls\n"); - sysclk_ind = get_sys_clk_index(); + debug("setup_dplls\n"); /* CORE dpll */ params = get_core_dpll_params(); /* default - safest */ @@ -289,10 +288,9 @@ static void setup_dplls(void) static void setup_non_essential_dplls(void) { u32 sys_clk_khz, abe_ref_clk; - u32 sysclk_ind, sd_div, num, den; + u32 sd_div, num, den; const struct dpll_params *params; - sysclk_ind = get_sys_clk_index(); sys_clk_khz = get_sys_clk_freq() / 1000; /* IVA */ -- cgit v0.10.2 From e8f473548a6a0a7321fb4e05bcc77337d5eca710 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Sat, 3 Dec 2011 06:46:15 +0000 Subject: arch/arm/include/asm/arch-omap5/clocks.h: Fix GCC 4.2 warnings Fix: clocks.c: In function 'setup_post_dividers': clocks.c:175: warning: comparison is always true due to limited range of data type clocks.c:177: warning: comparison is always true due to limited range of data type clocks.c:179: warning: comparison is always true due to limited range of data type clocks.c:181: warning: comparison is always true due to limited range of data type clocks.c:183: warning: comparison is always true due to limited range of data type clocks.c:185: warning: comparison is always true due to limited range of data type clocks.c:187: warning: comparison is always true due to limited range of data type clocks.c:189: warning: comparison is always true due to limited range of data type Signed-off-by: Anatolij Gustschin Cc: sricharan Cc: Tom Rini diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index fa99f65..d0e6dd6 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -686,14 +686,14 @@ struct dpll_regs { struct dpll_params { u32 m; u32 n; - u8 m2; - u8 m3; - u8 h11; - u8 h12; - u8 h13; - u8 h14; - u8 h22; - u8 h23; + s8 m2; + s8 m3; + s8 h11; + s8 h12; + s8 h13; + s8 h14; + s8 h22; + s8 h23; }; extern struct omap5_prcm_regs *const prcm; -- cgit v0.10.2 From 754f8cb68978efd31ddea73fa731e4e511bdd873 Mon Sep 17 00:00:00 2001 From: Manjunath Hadli Date: Mon, 10 Oct 2011 21:06:38 +0000 Subject: da850evm: pass board revision info to kernel there are two boards based on da850 SOC - OMAP-L138 and AM18x. In order to differentiate between these two boards, revision id is passed to kernel via second byte of ATAG_REVISION. Signed-off-by: Manjunathappa, Prakash Signed-off-by: Manjunath Hadli diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index e827256..9c0eade 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -147,6 +147,8 @@ static const struct lpsc_resource lpsc[] = { #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 #endif +#define REV_AM18X_EVM 0x100 + /* * get_board_rev() - setup to pass kernel board revision information * Returns: @@ -172,7 +174,9 @@ u32 get_board_rev(void) rev = 2; else if (maxcpuclk >= 372000000) rev = 1; - +#ifdef CONFIG_DA850_AM18X_EVM + rev |= REV_AM18X_EVM; +#endif return rev; } diff --git a/include/configs/da850_am18xxevm.h b/include/configs/da850_am18xxevm.h index 2885ece..9b7bf1e 100644 --- a/include/configs/da850_am18xxevm.h +++ b/include/configs/da850_am18xxevm.h @@ -44,7 +44,7 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_TEXT_BASE 0xc1080000 - +#define CONFIG_DA850_AM18X_EVM /* * Memory Info */ -- cgit v0.10.2 From 5183b7ec48cb6b47df2cb2ac0b7cb3e0c706d392 Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Mon, 5 Dec 2011 23:16:28 +0000 Subject: devkit8000: Move CONFIG_SYS_TEXT_BASE out of bss This moves CONFIG_SYS_TEXT_BASE one MB after beginning of SD-RAM. Move CONFIG_SYS_SPL_MALLOC_START to have one MB of free space for the u-boot image. CONFIG_SYS_TEXT_BASE was in the middle of the bss-section. This was the reason for the problems with MMC boot described here: http://article.gmane.org/gmane.comp.boot-loaders.u-boot/118711 Signed-off-by: Simon Schwarz Tested-by: Thomas Weber Signed-off-by: Tom Rini diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index c090d2b..758326b 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -36,7 +36,13 @@ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ -#define CONFIG_SYS_TEXT_BASE 0x80008000 +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 #define CONFIG_SDRC /* The chip has SDRC controller */ @@ -347,7 +353,7 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80108000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ #endif /* __CONFIG_H */ -- cgit v0.10.2 From 15422043c4a213dc5d7d59a337be1ab34c9b2e7f Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Tue, 6 Dec 2011 03:45:28 +0000 Subject: davinci: Remove unwanted memsize.c from hawkboard's nand spl build dram_init function in board/davinci/common/misc.c does not get compiled for spl builds, thus rendering inclusion of memsize.c useless. Signed-off-by: Sughosh Ganu diff --git a/nand_spl/board/davinci/da8xxevm/Makefile b/nand_spl/board/davinci/da8xxevm/Makefile index 3783c18..7746e41 100644 --- a/nand_spl/board/davinci/da8xxevm/Makefile +++ b/nand_spl/board/davinci/da8xxevm/Makefile @@ -46,7 +46,6 @@ COBJS = cpu.o \ da850_pinmux.o \ div0.o \ hawkboard_nand_spl.o \ - memsize.o \ misc.o \ nand_boot.o \ ns16550.o \ @@ -140,11 +139,6 @@ $(obj)psc.c: @rm -f $@ ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/psc.c $@ -# from common directory -$(obj)memsize.c: - @rm -f $@ - ln -s $(TOPDIR)/common/memsize.c $@ - ######################################################################### $(obj)%.o: $(obj)%.S -- cgit v0.10.2