From da6dafeb26b827d753e027920d14a287f678d659 Mon Sep 17 00:00:00 2001 From: Joris van Vossen Date: Mon, 9 Apr 2018 16:04:47 +0200 Subject: LSDK-18.03 Grapeboard initial support diff --git a/Makefile b/Makefile index 67f01ad..ff6a9cd 100644 --- a/Makefile +++ b/Makefile @@ -767,6 +767,8 @@ endif # Always append ALL so that arch config.mk's can add custom ones ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map binary_size_check +ALL-$(CONFIG_CONCAT_PBL_UBOOT_IMAGE) += u-boot-with-pbl.bin + ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin ifeq ($(CONFIG_SPL_FSL_PBL),y) ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin @@ -1210,6 +1212,14 @@ OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl $(UBOOT_BINLOAD) FORCE $(call if_changed,pad_cat) + + +#Concatenate PBL and U-boot binaries automatically +OBJCOPYFLAGS_u-boot-with-pbl.bin := -I binary -O binary --pad-to=$(CONFIG_UBOOT_TEXT_OFFSET) \ + --gap-fill=0xff + +u-boot-with-pbl.bin: $(srctree)/$(CONFIG_PBL_BINARY_SRC:"%"=%) u-boot.bin FORCE + $(call if_changed,pad_cat) # PPC4xx needs the SPL at the end of the image, since the reset vector # is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d77bc6e..2108ece 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -940,6 +940,13 @@ config TARGET_LS1012AFRDM development platform that supports the QorIQ LS1012A Layerscape Architecture processor. +config TARGET_GRAPEBOARD + bool "Support grapeboard" + select ARCH_LS1012A + select ARM64 + help + Support for Scalys LS1012A based Grapeboard platform. + config TARGET_LS1088ARDB bool "Support ls1088ardb" select ARCH_LS1088A @@ -1255,6 +1262,7 @@ source "board/freescale/ls1046ardb/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" +source "board/scalys/grapeboard/Kconfig" source "board/freescale/mx23evk/Kconfig" source "board/freescale/mx28evk/Kconfig" source "board/freescale/mx31ads/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 3a0e129..4bb64e4 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -91,6 +91,7 @@ config PSCI_RESET !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \ !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \ + !TARGET_GRAPEBOARD && \ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ !TARGET_LS2081ARDB && \ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c index ff0903c..56f1174 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c @@ -18,6 +18,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x0008, {NONE, NONE, NONE, SATA1} }, {0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} }, {0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} }, + {0x3308, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, SATA1} }, {0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} }, {0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} }, {0x9508, {TX_CLK, PCIE1, NONE, SATA1} }, diff --git a/arch/arm/dts/grapeboard.dts b/arch/arm/dts/grapeboard.dts new file mode 100644 index 0000000..3331285 --- /dev/null +++ b/arch/arm/dts/grapeboard.dts @@ -0,0 +1,15 @@ +/* + * Copyright 2017 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "grapeboard.dtsi" + +/ { + chosen { + stdout-path = &duart0; + }; +}; diff --git a/arch/arm/dts/grapeboard.dtsi b/arch/arm/dts/grapeboard.dtsi new file mode 100644 index 0000000..5389b30 --- /dev/null +++ b/arch/arm/dts/grapeboard.dtsi @@ -0,0 +1,66 @@ +/* + * Copyright 2017 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "fsl-ls1012a.dtsi" + +/ { + model = "LS1012A Grape Board"; + aliases { + spi0 = &qspi; + spi1 = &dspi0; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fl128s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "disabled"; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "disabled"; +}; + +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "disabled"; +}; + +&usb0 { + status = "disabled"; +}; + +&usb1 { + status = "okay"; +}; \ No newline at end of file diff --git a/board/scalys/grapeboard/Kconfig b/board/scalys/grapeboard/Kconfig new file mode 100644 index 0000000..99ece55 --- /dev/null +++ b/board/scalys/grapeboard/Kconfig @@ -0,0 +1,57 @@ +if TARGET_GRAPEBOARD + +config SYS_BOARD + default "grapeboard" + +config SYS_VENDOR + default "scalys" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "grapeboard" + +menu "Grapeboard configuration options" + depends on TARGET_GRAPEBOARD + +choice + prompt "U-boot environment configuration" + default STANDARD_UBOOT_CONFIG + +config STANDARD_UBOOT_CONFIG + bool + prompt "Standard flash target" + +config RESCUE_UBOOT_CONFIG + bool + prompt "Rescue flash target" + +endchoice + +config CONCAT_PBL_UBOOT_IMAGE + bool + default y + prompt "Concat PBL and U-boot.bin" + help + Enable concatenation of PBL binary 'PBL_BINARY_SRC' and 'u-boot.bin' with offset 'UBOOT_TEXT_OFFSET' into a single binary 'u-boot-with-pbl.bin'. + +config UBOOT_TEXT_OFFSET + string + depends on CONCAT_PBL_UBOOT_IMAGE + default 0x1000 + prompt "Concatenation offset for U-boot.bin to PBL binary" + help + See CONCAT_PBL_UBOOT_IMAGE help. Make sure this matches the offset used in the PBI command of the PBL binary and the SYS_TEXT_BASE define. + +config PBL_BINARY_SRC + string + depends on CONCAT_PBL_UBOOT_IMAGE + default "board/scalys/grapeboard/PBL_0x33_0x05_800_250_1000.bin" + prompt "See CONCAT_PBL_UBOOT_IMAGE" + help + See CONCAT_PBL_UBOOT_IMAGE help. + +endmenu + +endif diff --git a/board/scalys/grapeboard/Makefile b/board/scalys/grapeboard/Makefile new file mode 100644 index 0000000..a8632b6 --- /dev/null +++ b/board/scalys/grapeboard/Makefile @@ -0,0 +1,15 @@ +# +# Copyright 2018 Scalys B.V. +# opensource@scalys.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += grapeboard.o +obj-y += eth.o +obj-y += usb_grapeboard.o +obj-y += board_configuration_data.o + +obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ../../freescale/common/ns_access.o + + diff --git a/board/scalys/grapeboard/PBL_0x33_0x05_800_250_1000.bin b/board/scalys/grapeboard/PBL_0x33_0x05_800_250_1000.bin new file mode 100644 index 0000000..03bde04 Binary files /dev/null and b/board/scalys/grapeboard/PBL_0x33_0x05_800_250_1000.bin differ diff --git a/board/scalys/grapeboard/PBL_0x33_0x08_800_250_1000.bin b/board/scalys/grapeboard/PBL_0x33_0x08_800_250_1000.bin new file mode 100644 index 0000000..97eaade Binary files /dev/null and b/board/scalys/grapeboard/PBL_0x33_0x08_800_250_1000.bin differ diff --git a/board/scalys/grapeboard/PBL_0x35_0x08_800_250_1000.bin b/board/scalys/grapeboard/PBL_0x35_0x08_800_250_1000.bin new file mode 100644 index 0000000..f2d6425 Binary files /dev/null and b/board/scalys/grapeboard/PBL_0x35_0x08_800_250_1000.bin differ diff --git a/board/scalys/grapeboard/board_configuration_data.c b/board/scalys/grapeboard/board_configuration_data.c new file mode 100644 index 0000000..d277454 --- /dev/null +++ b/board/scalys/grapeboard/board_configuration_data.c @@ -0,0 +1,443 @@ +/* + * Copyright 2018 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include <../../../include/generated/autoconf.h> +#include "board_configuration_data.h" +#include "gpio_grapeboard.h" + +DECLARE_GLOBAL_DATA_PTR; + +int add_mac_addressess_to_env(const void* blob) +{ + const char *propname; + const void *value; + int prop_offset, len; + int count = 0; + char mac_string[19], eth_string[10]; + uint8_t mac_address[6]; + + if (fdt_check_header(blob) != 0) { + printf( "Board Configuration Data FDT corrupt\n"); + return -1; + } + + int nodeoff = fdt_path_offset(blob, "/network"); + + if (nodeoff < 0) { + printf("Network node not found\n"); + return -1; + } + for (prop_offset = fdt_first_property_offset(blob, nodeoff); + prop_offset > 0; + prop_offset = fdt_next_property_offset(blob, prop_offset)) { + value = fdt_getprop_by_offset(blob, prop_offset, + &propname, &len); + if (!value) { + return -EINVAL; + } + + memcpy(mac_address, value, 6); + + if (count) { + snprintf(eth_string, sizeof(eth_string), "eth%iaddr", count); + } + else { + snprintf(eth_string, sizeof(eth_string), "ethaddr"); + } + + snprintf(mac_string, sizeof(mac_string), + "%02x:%02x:%02x:%02x:%02x:%02x", + mac_address[0], mac_address[1], mac_address[2], + mac_address[3], mac_address[4], mac_address[5] + ); + + printf("%s : [ %s ]\n", propname, mac_string ); + + env_set( eth_string, mac_string); + + count++; + + } + printf("Done reading BCD\n"); + + return 0; +} + +struct udevice* sel_rescue_qspi_flash(bool sel_rescue) { + struct ccsr_gpio *pgpio = (void *)(CONFIG_SYS_GPIO2); + struct udevice *rescue_flash_dev,*bus_dev; + int ret = 0; + unsigned int bus = 0; + unsigned int cs = 0; + unsigned int speed = 0; + unsigned int mode = 0; + + /* Remove previous DM device */ + ret = spi_find_bus_and_cs(bus, cs, &bus_dev, &rescue_flash_dev); + if (!ret) { + device_remove(rescue_flash_dev, DM_REMOVE_NORMAL); + } + + setbits_be32(&pgpio->gpdir, QSPI_MUX_N_MASK); + if (sel_rescue == true) { + /* Change chip select to rescue QSPI NOR flash */ + setbits_be32(&pgpio->gpdat, QSPI_MUX_N_MASK); + } else { + /* Revert chip select muxing to standard QSPI flash */ + clrbits_be32(&pgpio->gpdat, QSPI_MUX_N_MASK); + /* Delay required (to meet RC time for button debouncing) before probing flash again. + * May be removed but the primary flash is only available after delay */ + udelay(75000); + } + + /* Probe new flash */ + ret = spi_flash_probe_bus_cs(bus, cs, speed, mode, &rescue_flash_dev); + if (ret != 0) { + printf("probe failed\n"); + return NULL; + } + + return rescue_flash_dev; + +} + + + +const void* get_boardinfo_rescue_flash(void) +{ + struct udevice *rescue_flash_dev; + uint32_t bcd_data_length; + uint8_t *bcd_data = NULL; + uint32_t calculated_crc, received_crc; + int dtb_length; + int ret = 0; + + /* Select and probe rescue flash */ + rescue_flash_dev = sel_rescue_qspi_flash(true); + + if (rescue_flash_dev == NULL) + goto err_no_free; + + /* Read the last 4 bytes to determine the length of the DTB data */ + ret = spi_flash_read_dm(rescue_flash_dev, (BCD_FLASH_SIZE-4), 4, (uint8_t*) &bcd_data_length); + if (ret != 0) { + printf("Error reading bcd length\n"); + errno = -ENODEV; + goto err_no_free; + } + + /* Convert length from big endianess to architecture endianess */ + bcd_data_length = ntohl(bcd_data_length); + printf("bcd_data_length = %i\n", bcd_data_length ); + + if (bcd_data_length > BCD_FLASH_SIZE ) { + debug("BCD data length error %02x %02x %02x %02x\n", + ( (uint8_t*) &bcd_data_length)[0], + ( (uint8_t*) &bcd_data_length)[1], + ( (uint8_t*) &bcd_data_length)[2], + ( (uint8_t*) &bcd_data_length)[3] ); + errno = -EMSGSIZE; + goto err_no_free; + } + + /* Allocate, and verify memory for the BCD data */ + bcd_data = (uint8_t*) malloc(bcd_data_length); + if (bcd_data == NULL) { + printf("Error locating memory for BCD data\n"); + goto err_no_free; + } + debug("Allocated memory for BCD data\n"); + + /* Read the DTB BCD data to memory */ + ret = spi_flash_read_dm(rescue_flash_dev, (BCD_FLASH_SIZE-bcd_data_length), bcd_data_length, (uint8_t*) bcd_data); + debug("Read data from QSPI bus\n"); + + if (ret != 0) { + printf("Error reading complete BCD data from EEPROM\n"); + errno = -ENOMEM; + goto err_free; + } + dtb_length = bcd_data_length - BCD_LENGTH_SIZE - BCD_HASH_SIZE; + + /* Calculate CRC on read DTB data */ + calculated_crc = crc32( 0, bcd_data, dtb_length); + + /* Received CRC is packed after the DTB data */ + received_crc = *((uint32_t*) &bcd_data[dtb_length]); + + /* Convert CRC from big endianess to architecture endianess */ + received_crc = ntohl(received_crc); + + if (calculated_crc != received_crc) { + printf("Checksum error. expected %08x, got %08x\n", + calculated_crc, received_crc); + errno = -EBADMSG; + goto err_free; + } + + /* Select and probe normal flash */ + rescue_flash_dev = sel_rescue_qspi_flash(false); + + /* Everything checked out, return the BCD data. + * The caller is expected to free this data */ + return bcd_data; + +err_free: + /* free the allocated buffer */ + free(bcd_data); + +err_no_free: + + /* Select and probe normal flash */ + rescue_flash_dev = sel_rescue_qspi_flash(false); + return NULL; +} + +#ifndef CONFIG_SPL_BUILD + +#ifndef CONFIG_CMD_FDT_MAX_DUMP +#define CONFIG_CMD_FDT_MAX_DUMP 64 +#endif + +/* + * Heuristic to guess if this is a string or concatenated strings. + */ + +static int is_printable_string(const void *data, int len) +{ + const char *s = data; + + /* zero length is not */ + if (len == 0) + return 0; + + /* must terminate with zero or '\n' */ + if (s[len - 1] != '\0' && s[len - 1] != '\n') + return 0; + + /* printable or a null byte (concatenated strings) */ + while (((*s == '\0') || isprint(*s) || isspace(*s)) && (len > 0)) { + /* + * If we see a null, there are three possibilities: + * 1) If len == 1, it is the end of the string, printable + * 2) Next character also a null, not printable. + * 3) Next character not a null, continue to check. + */ + if (s[0] == '\0') { + if (len == 1) + return 1; + if (s[1] == '\0') + return 0; + } + s++; + len--; + } + + /* Not the null termination, or not done yet: not printable */ + if (*s != '\0' || (len != 0)) + return 0; + + return 1; +} + +/* + * Print the property in the best format, a heuristic guess. Print as + * a string, concatenated strings, a byte, word, double word, or (if all + * else fails) it is printed as a stream of bytes. + */ +static void print_data(const void *data, int len) +{ + int j; + + /* no data, don't print */ + if (len == 0) + return; + + /* + * It is a string, but it may have multiple strings (embedded '\0's). + */ + if (is_printable_string(data, len)) { + puts("\""); + j = 0; + while (j < len) { + if (j > 0) + puts("\", \""); + puts(data); + j += strlen(data) + 1; + data += strlen(data) + 1; + } + puts("\""); + return; + } + + if ((len %4) == 0) { + if (len > CONFIG_CMD_FDT_MAX_DUMP) + printf("* 0x%p [0x%08x]", data, len); + else { + const __be32 *p; + + printf("<"); + for (j = 0, p = data; j < len/4; j++) + printf("0x%08x%s", fdt32_to_cpu(p[j]), + j < (len/4 - 1) ? " " : ""); + printf(">"); + } + } else { /* anything else... hexdump */ + if (len > CONFIG_CMD_FDT_MAX_DUMP) + printf("* 0x%p [0x%08x]", data, len); + else { + const u8 *s; + + printf("["); + for (j = 0, s = data; j < len; j++) + printf("%02x%s", s[j], j < len - 1 ? " " : ""); + printf("]"); + } + } +} + +/* + * Recursively print (a portion of) the working_fdt. The depth parameter + * determines how deeply nested the fdt is printed. + */ +#define MAX_LEVEL 4 +static int bcd_fdt_print(const void* address, int depth) +{ + static char tabs[MAX_LEVEL+1] = + "\t\t\t\t\t"; + const void *nodep; /* property node pointer */ + int nodeoffset; /* node offset from libfdt */ + int nextoffset; /* next node offset from libfdt */ + uint32_t tag; /* tag */ + int len; /* length of the property */ + int level = 0; /* keep track of nesting level */ + const struct fdt_property *fdt_prop; + const char *pathp; + + nodeoffset = fdt_path_offset (address, "/"); + if (nodeoffset < 0) { + /* + * Not found or something else bad happened. + */ + printf ("libfdt fdt_path_offset() returned %s\n", + fdt_strerror(nodeoffset)); + return 1; + } + + /* + * The user passed in a node path and no property, + * print the node and all subnodes. + */ + while(level >= 0) { + tag = fdt_next_tag(address, nodeoffset, &nextoffset); + switch(tag) { + case FDT_BEGIN_NODE: + pathp = fdt_get_name(address, nodeoffset, NULL); + if (level <= depth) { + if (pathp == NULL) + pathp = "/* NULL pointer error */"; + if (*pathp == '\0') + pathp = "/"; /* root is nameless */ + printf("%s%s {\n", + &tabs[MAX_LEVEL - level], pathp); + } + level++; + if (level >= MAX_LEVEL) { + printf("Nested too deep, aborting.\n"); + return 1; + } + break; + case FDT_END_NODE: + level--; + if (level <= depth) + printf("%s};\n", &tabs[MAX_LEVEL - level]); + if (level == 0) { + level = -1; /* exit the loop */ + } + break; + case FDT_PROP: + fdt_prop = fdt_offset_ptr(address, nodeoffset, + sizeof(*fdt_prop)); + pathp = fdt_string(address, + fdt32_to_cpu(fdt_prop->nameoff)); + len = fdt32_to_cpu(fdt_prop->len); + nodep = fdt_prop->data; + if (len < 0) { + printf ("libfdt fdt_getprop(): %s\n", + fdt_strerror(len)); + return 1; + } else if (len == 0) { + /* the property has no value */ + if (level <= depth) + printf("%s%s;\n", + &tabs[MAX_LEVEL - level], + pathp); + } else { + if (level <= depth) { + printf("%s%s = ", + &tabs[MAX_LEVEL - level], + pathp); + print_data (nodep, len); + printf(";\n"); + } + } + break; + case FDT_NOP: + printf("%s/* NOP */\n", &tabs[MAX_LEVEL - level]); + break; + case FDT_END: + return 1; + default: + if (level <= depth) + printf("Unknown tag 0x%08X\n", tag); + return 1; + } + nodeoffset = nextoffset; + } + return 0; +} + +int do_bcdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const void* bcd_dtc_blob; + int ret = 0; + + bcd_dtc_blob = get_boardinfo_rescue_flash(); + + if (bcd_dtc_blob != NULL) { + bcd_fdt_print(bcd_dtc_blob, 4); + } + + return ret; +} + +/* U_BOOT_CMD(name,maxargs,repeatable,command,"usage","help") */ +U_BOOT_CMD( + bcdinfo, + 1, + 1, + do_bcdinfo, + "Show the Board Configuration Data (stored in rescue flash)", + "" +); +#endif diff --git a/board/scalys/grapeboard/board_configuration_data.h b/board/scalys/grapeboard/board_configuration_data.h new file mode 100644 index 0000000..f08eea8 --- /dev/null +++ b/board/scalys/grapeboard/board_configuration_data.h @@ -0,0 +1,20 @@ +/* + * Copyright 2018 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BCD_H +#define _BCD_H + +#define BCD_LENGTH_SIZE 4 + +#define BCD_FLASH_SIZE 0x100000 /* 1 MBytes */ + +#define BCD_HASH_SIZE 4 + +const void* get_boardinfo_rescue_flash(void); +int add_mac_addressess_to_env(const void* blob); + +#endif /* _BCD_H */ diff --git a/board/scalys/grapeboard/eth.c b/board/scalys/grapeboard/eth.c new file mode 100644 index 0000000..43b3e92 --- /dev/null +++ b/board/scalys/grapeboard/eth.c @@ -0,0 +1,86 @@ +/* + * Copyright 2018 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" +#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" + + +void reset_phy(void) +{ + /* No PHY reset control from LS1012A */ +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FSL_PFE + struct mii_dev *bus; + struct mdio_info mac1_mdio_info; + struct mdio_info mac2_mdio_info; + + reset_phy(); + + init_pfe_scfg_dcfg_regs(); + + /* Initialize SGMIIA on MDIO1 */ + mac1_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; + mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME; + + bus = pfe_mdio_init(&mac1_mdio_info); + if (!bus) { + printf("Failed to register mdio 1\n"); + return -1; + } + + /* Initialize SGMIIB on MDIO2 */ + mac2_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; + mac2_mdio_info.name = DEFAULT_PFE_MDIO1_NAME; + + bus = pfe_mdio_init(&mac2_mdio_info); + if (!bus) { + printf("Failed to register mdio 2\n"); + return -1; + } + + /* Initialize PHYs on MDIO1 */ + pfe_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); + pfe_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII); + + pfe_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); + pfe_set_phy_address_mode(1, EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_SGMII); + + /* Initialize TI DP83867CS PHY LEDs as: + * LED_3 = 0x0: Link established (not connected) + * LED_2 = 0x0: Link established (not connected) + * LED_1 = 0xB: Link established, blink for activity (green LED) + * LED_0 = 0x8: 10/100BT link established (orange LED) + */ + miiphy_write(DEFAULT_PFE_MDIO_NAME,EMAC1_PHY_ADDR,0x18,0x00B8); + miiphy_write(DEFAULT_PFE_MDIO_NAME,EMAC2_PHY_ADDR,0x18,0x00B8); + + /* Enable PHY Power save mode */ + miiphy_write(DEFAULT_PFE_MDIO_NAME,EMAC1_PHY_ADDR,0x10,0x0200); + miiphy_write(DEFAULT_PFE_MDIO_NAME,EMAC2_PHY_ADDR,0x10,0x0200); + + cpu_eth_init(bis); +#endif + return pci_eth_init(bis); +} \ No newline at end of file diff --git a/board/scalys/grapeboard/gpio_grapeboard.h b/board/scalys/grapeboard/gpio_grapeboard.h new file mode 100644 index 0000000..1792013 --- /dev/null +++ b/board/scalys/grapeboard/gpio_grapeboard.h @@ -0,0 +1,63 @@ +/* + * Copyright 2018 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef GPIO_GRAPEBOARD_H_ +#define GPIO_GRAPEBOARD_H_ + +/* GPIO1 and GPIO2 registers */ +#define CONFIG_SYS_GPIO1 0x2300000 +#define CONFIG_SYS_GPIO2 0x2310000 +#define GPIO_PIN_MASK(shift) (0x80000000 >> shift) + +/* ===================================================== + * Grapeboard ExPI mapping (*pin name at ls1012a side) + * Note: The secondary options require modified RCW. + * ===================================================== + * 3V3 -| 1 2|- 5V0 + * I2C_SDA -| 3 4|- 5V0 + * I2C_SCL -| 5 6|- GND + * CLK0_25MHZ -| 7 8|- UART_TXD + * GND -| 9 10|- UART_RXD + * SPI_CE2/GPIO1_27* -|11 12|- GPIO2_04* + * GPIO2_05* -|13 14|- GND + * GPIO2_06* -|15 16|- GPIO2_07* + * 3V3 -|17 18|- GPIO2_09* + * SPI_MOSI/GPIO1_24* -|19 20|- GND + * SPI_MISO/GPIO1_28* -|21 22|- GPIO2_10* + * SPI_CLK/GPIO1_29* -|23 24|- SPI_CE0/GPIO1_25* + * GND -|25 26|- SPI_CE1/GPIO1_26* + */ + +/* ExPI gpios */ +#define gpio1_24 GPIO_PIN_MASK(24) /* ExPI pin 19 */ +#define gpio1_25 GPIO_PIN_MASK(25) /* ExPI pin 24 */ +#define gpio1_26 GPIO_PIN_MASK(26) /* ExPI pin 26 */ +#define gpio1_27 GPIO_PIN_MASK(27) /* ExPI pin 11 */ +#define gpio1_28 GPIO_PIN_MASK(28) /* ExPI pin 21 */ +#define gpio1_29 GPIO_PIN_MASK(29) /* ExPI pin 23 */ + +#define gpio2_04 GPIO_PIN_MASK(4) /* ExPI pin 12 */ +#define gpio2_05 GPIO_PIN_MASK(5) /* ExPI pin 13 */ +#define gpio2_06 GPIO_PIN_MASK(6) /* ExPI pin 15 */ +#define gpio2_07 GPIO_PIN_MASK(7) /* ExPI pin 16 */ +#define gpio2_09 GPIO_PIN_MASK(9) /* ExPI pin 18 */ +#define gpio2_10 GPIO_PIN_MASK(10) /* ExPI pin 22 */ + +/* M.2 gpios */ +#define gpio1_22 GPIO_PIN_MASK(22) +#define gpio2_00 GPIO_PIN_MASK(0) +#define gpio2_01 GPIO_PIN_MASK(1) +#define gpio2_02 GPIO_PIN_MASK(2) +#define M2_CFG1 GPIO_PIN_MASK(11) /* gpio2_11 */ +#define M2_CFG0 GPIO_PIN_MASK(12) /* gpio2_12 */ +#define M2_CFG2 GPIO_PIN_MASK(13) /* gpio2_13 */ +#define M2_CFG3 GPIO_PIN_MASK(14) /* gpio2_14 */ + +/* Misc gpios */ +#define QSPI_MUX_N_MASK GPIO_PIN_MASK(3) /* gpio2_03 */ + +#endif /* GPIO_GRAPEBOARD_H_ */ diff --git a/board/scalys/grapeboard/grapeboard.c b/board/scalys/grapeboard/grapeboard.c new file mode 100644 index 0000000..72d9510 --- /dev/null +++ b/board/scalys/grapeboard/grapeboard.c @@ -0,0 +1,181 @@ +/* + * Copyright 2018 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#ifdef CONFIG_FSL_LS_PPA +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "usb_grapeboard.h" +#include <../../../include/generated/autoconf.h> +#include +#include "gpio_grapeboard.h" +#include "board_configuration_data.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct ccsr_gpio *pgpio = (void *)(CONFIG_SYS_GPIO2); + + int m2_config = 0; + int serdes_cfg = get_serdes_protocol(); + + puts("Board: Grape board\n"); + + /* set QSPI chip select muxing to 0 */ + setbits_be32(&pgpio->gpdir, QSPI_MUX_N_MASK); + clrbits_be32(&pgpio->gpdat, QSPI_MUX_N_MASK); + + /* Configure USB hub */ + usb_hx3_hub_init(); + + /* Check for an M.2 module */ + clrbits_be32(&pgpio->gpdir, (M2_CFG0 | M2_CFG1 | M2_CFG2 | M2_CFG3)); + m2_config = (in_be32(&pgpio->gpdat) & (M2_CFG0 | M2_CFG1 | M2_CFG2 | M2_CFG3)); + + switch(m2_config) { + case 0: + printf("M.2: SATA SSD module found\n"); + if (serdes_cfg & 0x5) + printf("Warning: SERDES has not been configured in RCW for SATA!\n"); + break; + case M2_CFG1: + printf("M.2: PCIe SSD module found\n"); + if (serdes_cfg & 0x8) + printf("Warning: SERDES has not been configured in RCW for PCIe!\n"); + break; + case (M2_CFG0 | M2_CFG1 | M2_CFG2 | M2_CFG3): + printf("M.2: No module detected\n"); + break; + default: + printf("M.2: A module has been detected (TODO: support new module type)\n"); + break; + } + + return 0; +} + +int misc_init_r(void) +{ + const void* bcd_dtc_blob; + int ret; + + bcd_dtc_blob = get_boardinfo_rescue_flash(); + if (bcd_dtc_blob != NULL) { + /* Board Configuration Data is intact, ready for parsing */ + ret = add_mac_addressess_to_env(bcd_dtc_blob); + if (ret != 0) { + printf("Error adding BCD data to environment\n"); + } + } + + return 0; +} + +int dram_init(void) +{ + static const struct fsl_mmdc_info mparam = { + 0x05180000, /* mdctl */ + 0x00030035, /* mdpdc */ + 0x12554000, /* mdotc */ + 0xbabf7954, /* mdcfg0 */ + 0xdb328f64, /* mdcfg1 */ + 0x01ff00db, /* mdcfg2 */ + 0x00001680, /* mdmisc */ + 0x0f3c8000, /* mdref */ + 0x00002000, /* mdrwd */ + 0x00bf1023, /* mdor */ + 0x0000003f, /* mdasp */ + 0x0000022a, /* mpodtctrl */ + 0xa1390003, /* mpzqhwctrl */ + }; + + mmdc_init(&mparam); + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif + + return 0; +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); + /* + * Set CCI-400 control override register to enable barrier + * transaction + */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + return 0; +} + +int esdhc_status_fixup(void *blob, const char *compat) +{ + char esdhc0_path[] = "/soc/esdhc@1560000"; + + do_fixup_by_path(blob, esdhc0_path, "status", "okay", + sizeof("okay"), 1); + + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} + +void scsi_init(void) { + printf("\r"); /* SCSI init already completed in board_late_init, so skip message */ +} + diff --git a/board/scalys/grapeboard/usb_grapeboard.c b/board/scalys/grapeboard/usb_grapeboard.c new file mode 100644 index 0000000..6ed1889 --- /dev/null +++ b/board/scalys/grapeboard/usb_grapeboard.c @@ -0,0 +1,103 @@ +/* + * Copyright 2018 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define MIN(X,Y) ((X) < (Y) ? (X) : (Y)) + +#define I2C_ADDRESS_USB_HUB 0x60 +#define MAX_I2C_ATTEMPTS 10 + +#define HX3_SETTINGS_SIZE 192 + +/* Cypress HX3 hub settings blob */ +const uint8_t hx3_settings[5 + HX3_SETTINGS_SIZE] = { + 'C', 'Y', /* Cypress magic signature */ + 0x30, /* I2C speed : 100kHz */ + 0xd4, /* Image type: Only settings, no firmware */ + HX3_SETTINGS_SIZE, /* payload size (192) */ + 0xb4, 0x04, /* VID */ + 0x04, 0x65, /* PID */ + 10, 50, /* DID */ + 0x00, /* Reserved */ + 0x07, /* DS4 has no SuperSpeed port */ + 0x32, /* bPwrOn2PwrGood : 100 ms */ + 0x7f, /* 4 Downstream ports : DS4 is non-removable (MCU) */ + 0x11, /* Ganged power switching */ + 0x20, /* suspend indicator disabled, power switch control is active high */ + 0x11, /* BC v1.2 and ghost charging enabled */ + 0xf0, /* cdp enabled */ + 0xf8, /* embedded hub, overcurrent input is active high */ + 0x00, /* reserved */ + 0x08, /* USB String descriptors enabled (0x08) / disabled (0x00) */ + 0x00, 0x00, + 0x12, 0x00, 0x2c, + 0x66, 0x66, /* USB3.0 TX driver de-emphasis */ + 0x69, 0x29, 0x29, 0x29, 0x29, /* TX amplitude */ + 0x00, /* Reserved */ + 0x06, 0x65, /* USB 2.0 PID */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Reserved */ + 0x04, 0x03, 0x09, 0x04, /* LangID = 0x0409 US English */ + 0x18, 0x03, /* Manufacturer string descriptor */ + 0x32, 0x00, 0x30, 0x00, 0x31, 0x00, 0x37, 0x00, + 0x20, 0x00, 0x53, 0x00, 0x63, 0x00, 0x61, 0x00, + 0x6c, 0x00, 0x79, 0x00, 0x73, 0x00, + 0x2c, 0x03, /* Product string descriptor */ + 0x47, 0x00, 0x72, 0x00, 0x61, 0x00, 0x70, 0x00, + 0x65, 0x00, 0x62, 0x00, 0x6f, 0x00, 0x61, 0x00, + 0x72, 0x00, 0x64, 0x00, 0x20, 0x00, 0x43, 0x00, + 0x59, 0x00, 0x2d, 0x00, 0x48, 0x00, 0x58, 0x00, + 0x33, 0x00, 0x20, 0x00, 0x48, 0x00, 0x55, 0x00, + 0x42, 0x00, + 0x1a, 0x03, /* Serial string descriptor */ + 0x47, 0x00, 0x72, 0x00, 0x61, 0x00, 0x70, 0x00, + 0x65, 0x00, 0x62, 0x00, 0x6f, 0x00, 0x61, 0x00, + 0x72, 0x00, 0x64, 0x00, 0x20, 0x00, 0x31, 0x00, + 0x39, 0x00, 0x41, 0x00, + 0x00 +}; + +int usb_hx3_hub_init(void) { + int length, index = 0, i2c_attempts = 0; + const int settings_size = sizeof(hx3_settings); + uint8_t *data = (uint8_t *)hx3_settings; + + /* + * Configure USB hub slave + * + * The Hx3 starts in an i2c slave bootloader mode until sufficient and correct data is written to it over I2C. + * If transferred data is incorrect then the device will hang until it has been reset. + */ + puts("USB: configuring hub...."); + + while(index <= settings_size - 1){ + length = MIN(64, (settings_size - index)); + + if(i2c_write(I2C_ADDRESS_USB_HUB, index, 2, data, length)) { + if(i2c_attempts < 1) + printf("\nWARNING: I2C error during configuring USB hub slave. retrying...\n"); + if(++i2c_attempts >= MAX_I2C_ATTEMPTS){ + printf("ERROR: Maximum USB hub configuration attempts reached. Exiting now\n"); + return 1; + } + continue; + } + i2c_attempts = 0; /* reset error count */ + index += length; + data += length; + } + + puts("Done!\n"); + return 0; +} + +int usb_hx3_hub_reset(void) { + /* USB hub cannot be reset in software without resetting the ls1012a */ + return 1; +} diff --git a/board/scalys/grapeboard/usb_grapeboard.h b/board/scalys/grapeboard/usb_grapeboard.h new file mode 100644 index 0000000..fbd1fcc --- /dev/null +++ b/board/scalys/grapeboard/usb_grapeboard.h @@ -0,0 +1,14 @@ +/* + * Copyright 2018 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef USB_GRAPEBOARD_H_ +#define USB_GRAPEBOARD_H_ + +int usb_hx3_hub_init(void); +int usb_hx3_hub_reset(void); + +#endif /* USB_GRAPEBOARD_H_ */ diff --git a/configs/grapeboard_pcie_qspi_defconfig b/configs/grapeboard_pcie_qspi_defconfig new file mode 100644 index 0000000..26f33a4 --- /dev/null +++ b/configs/grapeboard_pcie_qspi_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_TARGET_GRAPEBOARD=y +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_DEFAULT_DEVICE_TREE="grapeboard" +CONFIG_STANDARD_UBOOT_CONFIG=y +CONFIG_SYS_LS_PPA_FW_ADDR=0x40240000 +CONFIG_CONCAT_PBL_UBOOT_IMAGE=y +CONFIG_PBL_BINARY_SRC="board/scalys/grapeboard/PBL_0x33_0x05_800_250_1000.bin" + +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=2 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000 noinitrd root=/dev/mmcblk0p1 rootfstype=ext4 rw rootwait" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +# CONFIG_BLK is not set +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_FSL_PFE=y +CONFIG_PHYLIB=y +CONFIG_PHY_TI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_DISTRO_DEFAULTS=y \ No newline at end of file diff --git a/configs/grapeboard_qspi_rescue_defconfig b/configs/grapeboard_qspi_rescue_defconfig new file mode 100644 index 0000000..5649f3f --- /dev/null +++ b/configs/grapeboard_qspi_rescue_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_TARGET_GRAPEBOARD=y +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_DEFAULT_DEVICE_TREE="grapeboard" +CONFIG_RESCUE_UBOOT_CONFIG=y +CONFICONFIG_SYS_LS_PPA_FW_ADDR=0x400a0000 +CONFIG_SYS_LS_PFE_FW_ADDR=0x400c0000 +CONFIG_PBL_BINARY_SRC="board/scalys/grapeboard/PBL_0x33_0x05_800_250_1000.bin" + +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=10 +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +# CONFIG_BLK is not set +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_FSL_PFE=y +CONFIG_PHYLIB=y +CONFIG_PHY_TI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_DISTRO_DEFAULTS=y + diff --git a/configs/grapeboard_sata_qspi_defconfig b/configs/grapeboard_sata_qspi_defconfig new file mode 100644 index 0000000..47eb0f2 --- /dev/null +++ b/configs/grapeboard_sata_qspi_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_TARGET_GRAPEBOARD=y +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_DEFAULT_DEVICE_TREE="grapeboard" +CONFIG_STANDARD_UBOOT_CONFIG=y +CONFIG_SYS_LS_PPA_FW_ADDR=0x40240000 +CONFIG_CONCAT_PBL_UBOOT_IMAGE=y +CONFIG_PBL_BINARY_SRC="board/scalys/grapeboard/PBL_0x33_0x08_800_250_1000.bin" + +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=2 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000 noinitrd root=/dev/mmcblk0p1 rootfstype=ext4 rw rootwait" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +# CONFIG_BLK is not set +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_FSL_PFE=y +CONFIG_PHYLIB=y +CONFIG_PHY_TI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_DISTRO_DEFAULTS=y \ No newline at end of file diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index d0fd7ea..5b836f4 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -104,6 +104,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"s25fs256s_64k", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, {"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) }, {"s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, RD_FULL | WR_QPP | ADDR_4B) }, + {"s25fs064s", INFO6(0x010217, 0x4d0181, 64 * 1024, 128, RD_FULL | WR_QPP | ADDR_4B) }, {"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP) }, {"s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP) }, {"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP) }, diff --git a/include/configs/grapeboard.h b/include/configs/grapeboard.h new file mode 100644 index 0000000..e148e65 --- /dev/null +++ b/include/configs/grapeboard.h @@ -0,0 +1,325 @@ +/* + * Copyright 2018 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __GRAPEBOARD_H__ +#define __GRAPEBOARD_H__ + +#define CONFIG_FSL_LAYERSCAPE +#define CONFIG_GICV2 + +#include +#include +#include +#include <../../../include/generated/autoconf.h> + +#define CONFIG_SUPPORT_RAW_INITRD + +#define CONFIG_BOARD_LATE_INIT /* scsi/sata init */ +#define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_MISC_INIT_R + +#define CONFIG_SYS_TEXT_BASE 0x40001000 /* QSPI0_AMBA_BASE + CONFIG_UBOOT_TEXT_OFFSET */ + +#define CONFIG_SYS_CLK_FREQ 125000000 /* 125MHz */ + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + +/* DDR */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +/* CSU */ +#define CONFIG_LAYERSCAPE_NS_ACCESS + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (0x40000 + 128 * 1024) + +/* QSPI */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 1000000 +#define CONFIG_ENV_SPI_MODE 0x03 +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_FSL_SPI_INTERFACE +#define CONFIG_SF_DATAFLASH +#define CONFIG_FSL_QSPI +#define QSPI0_AMBA_BASE 0x40000000 +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_SST +#define FSL_QSPI_FLASH_SIZE SZ_64M +#define FSL_QSPI_FLASH_NUM 1 + +/* QSPI Environment */ +#define CONFIG_ENV_SIZE 0x40000 /* 256KB */ + +#if CONFIG_RESCUE_UBOOT_CONFIG +/* Rescue flash size is at minimum 1MBytes. + * I.e. PBL/U-boot/PPA/PFE/BCD must fit within 0x100000. */ +#define CONFIG_ENV_IS_NOWHERE +#else +#define CONFIG_ENV_OVERWRITE +/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/ +#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 +#endif +#endif /* CONFIG_QSPI_BOOT */ + +/* SPI */ +#define CONFIG_FSL_DSPI1 +#define CONFIG_DEFAULT_SPI_BUS 0 +#define CONFIG_CMD_SPI +#define MMAP_DSPI DSPI1_BASE_ADDR +#define CONFIG_SYS_DSPI_CTAR0 1 +#define CONFIG_SYS_DSPI_CTAR1 1 +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 + +/* UART */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* Command line configuration */ +#undef CONFIG_CMD_IMLS + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#include +#include + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_PANIC_HANG +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* PFE Ethernet */ +#ifdef CONFIG_FSL_PFE +#define EMAC1_PHY_ADDR 0x1 +#define EMAC2_PHY_ADDR 0x2 +#define CONFIG_SYS_LS_PFE_FW_ADDR 0x40280000 +#endif + +/* MMC */ +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#endif + +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_SYS_SATA AHCI_BASE_ADDR +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) + +/* PCIE */ +#define CONFIG_PCIE1 +#define CONFIG_NET_MULTI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI + +/* Mtdparts configuration */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_USE_SPIFLASH +#define CONFIG_SPI_FLASH_MTD + +#define MTDIDS_DEFAULT \ + "nor0=qspi@40000000.0" + +#define MTDPARTS_DEFAULT \ + "mtdparts=qspi@40000000.0:" \ + "2M@0x0(u-boot)," \ + "256k(env)," \ + "256k(ppa)," \ + "256k(pfe)," \ + "-(rootfs)" + +/* Default environment variables */ +#define COMMON_UBOOT_CONFIG \ + "verify=no\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "kernelheader_addr=0x800000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "console=ttyS0,115200\0" \ + "ethprime=pfe_eth0\0" \ + "ethaddr=02:00:00:ba:be:01\0" \ + "eth1addr=02:00:00:ba:be:02\0" \ + "update_files_path=.\0" \ + "update_source_file_system=ext4\0" \ + "autoload=no\0" \ + "update_tftp_uboot_qspi_nor=" \ + "dhcp;" \ + "tftp $load_addr $update_files_path/u-boot-with-pbl.bin;" \ + "if test $? = \"0\"; then " \ + "sf probe 0:0;" \ + "sf erase u-boot 200000;" \ + "sf write $load_addr u-boot $filesize;" \ + "fi\0" \ + "update_tftp_ppa_qspi_nor=" \ + "dhcp;" \ + "tftp $load_addr $update_files_path/ppa.itb;" \ + "if test $? = \"0\"; then " \ + "sf probe 0:0;" \ + "sf erase ppa 40000;" \ + "sf write $load_addr ppa $filesize;" \ + "fi\0" \ + "update_tftp_pfe_qspi_nor=" \ + "dhcp;" \ + "tftp $load_addr $update_files_path/pfe_fw_sbl.itb;" \ + "if test $? = \"0\"; then " \ + "sf probe 0:0;" \ + "sf erase pfe 40000;" \ + "sf write $load_addr pfe $filesize;" \ + "fi\0" \ + "update_usb_uboot_qspi_nor=" \ + "usb start;" \ + "fatload usb 0:1 $load_addr $update_files_path/u-boot-with-pbl.bin;" \ + "if test $? = \"0\"; then " \ + "sf probe 0:0;" \ + "sf erase u-boot 200000;" \ + "sf write $load_addr u-boot $filesize;" \ + "fi\0" \ + "update_usb_ppa_qspi_nor=" \ + "usb start;" \ + "fatload usb 0:1 $load_addr $update_files_path/ppa.itb;" \ + "if test $? = \"0\"; then " \ + "sf probe 0:0;" \ + "sf erase ppa 40000;" \ + "sf write $load_addr ppa $filesize;" \ + "fi\0" \ + "update_usb_pfe_qspi_nor=" \ + "usb start;" \ + "fatload usb 0:1 $load_addr $update_files_path/pfe_fw_sbl.itb;" \ + "if test $? = \"0\"; then " \ + "sf probe 0:0;" \ + "sf erase pfe 40000;" \ + "sf write $load_addr pfe $filesize;" \ + "fi\0" \ + "update_mmc_uboot_qspi_nor=" \ + "mmc rescan;" \ + "ext4load mmc 0:1 $load_addr $update_files_path/u-boot-with-pbl.bin;" \ + "if test $? = \"0\"; then " \ + "sf probe 0:0;" \ + "sf erase u-boot 200000;" \ + "sf write $load_addr u-boot $filesize;" \ + "fi\0" \ + "update_mmc_ppa_qspi_nor=" \ + "mmc rescan;" \ + "ext4load mmc 0:1 $load_addr $update_files_path/ppa.itb;" \ + "if test $? = \"0\"; then " \ + "sf probe 0:0;" \ + "sf erase ppa 40000;" \ + "sf write $load_addr ppa $filesize;" \ + "fi\0" \ + "update_mmc_pfe_qspi_nor=" \ + "mmc rescan;" \ + "ext4load mmc 0:1 $load_addr $update_files_path/pfe_fw_sbl.itb;" \ + "if test $? = \"0\"; then " \ + "sf probe 0:0;" \ + "sf erase pfe 40000;" \ + "sf write $load_addr pfe $filesize;" \ + "fi\0" \ + +/* Default flash specific environment variables */ +#if CONFIG_RESCUE_UBOOT_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_UBOOT_CONFIG +#undef CONFIG_BOOTCOMMAND +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +/* recover from sd card */ +#define CONFIG_BOOTCOMMAND "run update_mmc_uboot_pbl_qspi_nor; run update_mmc_pfe_qspi_nor; run update_mmc_ppa_qspi_nor" +#endif + +#else /* if CONFIG_STANDARD_UBOOT_CONFIG */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_UBOOT_CONFIG \ + "mmcboot=" \ + "ext4load mmc 0:1 $fdt_addr_r /boot/grapeboard.dtb;" \ + "ext4load mmc 0:1 $kernel_addr_r /boot/uImage;" \ + "if test $? = \"0\"; then " \ + "pfe stop;" \ + "bootm $kernel_addr_r - $fdt_addr_r;" \ + "fi\0" \ + "scsiboot=" \ + "ext4load scsi 0:1 $fdt_addr_r /boot/grapeboard.dtb;" \ + "ext4load scsi 0:1 $kernel_addr_r /boot/uImage;" \ + "if test $? = \"0\"; then " \ + "pfe stop;" \ + "bootm $kernel_addr_r - $fdt_addr_r;" \ + "fi\0" \ + "netboot=" \ + "dhcp;" \ + "tftp $fdt_addr_r $tftp_path/grapeboard.dtb;" \ + "tftp $kernel_addr_r $tftp_path/uImage;" \ + "if test $? = \"0\"; then " \ + "pfe stop;" \ + "bootm $kernel_addr_r - $fdt_addr_r;" \ + "fi\0" + +#undef CONFIG_BOOTCOMMAND +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_BOOTCOMMAND "run mmcboot" +#endif +#endif + +#include + +#endif /* __GRAPEBOARD_H__ */ -- cgit v0.10.2