From 02c41535b6a4744e28e89938584d8db230ac014f Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 7 Aug 2012 14:59:18 +0530 Subject: ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index dfa3760..8e7411d 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -418,55 +418,6 @@ static void setup_dplls(void) #endif } -#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL -static void setup_non_essential_dplls(void) -{ - u32 abe_ref_clk; - const struct dpll_params *params; - - /* IVA */ - clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva, - CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); - - params = get_iva_dpll_params(*dplls_data); - do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); - - /* Configure ABE dpll */ - params = get_abe_dpll_params(*dplls_data); -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; - - if (omap_revision() == DRA752_ES1_0) - /* Select the sys clk for dpll_abe */ - clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel, - CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK, - CM_ABE_PLL_SYS_CLKSEL_SYSCLK2); -#else - abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; - /* - * We need to enable some additional options to achieve - * 196.608MHz from 32768 Hz - */ - setbits_le32((*prcm)->cm_clkmode_dpll_abe, - CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| - CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| - CM_CLKMODE_DPLL_LPMODE_EN_MASK| - CM_CLKMODE_DPLL_REGM4XEN_MASK); - /* Spend 4 REFCLK cycles at each stage */ - clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe, - CM_CLKMODE_DPLL_RAMP_RATE_MASK, - 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); -#endif - - /* Select the right reference clk */ - clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel, - CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, - abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); - /* Lock the dpll */ - do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe"); -} -#endif - u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic) { u32 offset_code; @@ -760,10 +711,6 @@ void prcm_init(void) timer_init(); scale_vcores(*omap_vcores); setup_dplls(); -#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL - setup_non_essential_dplls(); - enable_non_essential_clocks(); -#endif setup_warmreset_time(); break; default: diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 1b2f439..4dec73e 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -399,91 +399,6 @@ void enable_basic_uboot_clocks(void) 1); } -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 const clk_domains_non_essential[] = { - (*prcm)->cm_mpu_m3_clkstctrl, - (*prcm)->cm_ivahd_clkstctrl, - (*prcm)->cm_dsp_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sgx_clkstctrl, - (*prcm)->cm1_abe_clkstctrl, - (*prcm)->cm_c2c_clkstctrl, - (*prcm)->cm_cam_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sdma_clkstctrl, - 0 - }; - - u32 const clk_modules_hw_auto_non_essential[] = { - (*prcm)->cm_l3instr_l3_3_clkctrl, - (*prcm)->cm_l3instr_l3_instr_clkctrl, - (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, - (*prcm)->cm_l3init_hsi_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_non_essential[] = { - (*prcm)->cm1_abe_aess_clkctrl, - (*prcm)->cm1_abe_pdm_clkctrl, - (*prcm)->cm1_abe_dmic_clkctrl, - (*prcm)->cm1_abe_mcasp_clkctrl, - (*prcm)->cm1_abe_mcbsp1_clkctrl, - (*prcm)->cm1_abe_mcbsp2_clkctrl, - (*prcm)->cm1_abe_mcbsp3_clkctrl, - (*prcm)->cm1_abe_slimbus_clkctrl, - (*prcm)->cm1_abe_timer5_clkctrl, - (*prcm)->cm1_abe_timer6_clkctrl, - (*prcm)->cm1_abe_timer7_clkctrl, - (*prcm)->cm1_abe_timer8_clkctrl, - (*prcm)->cm1_abe_wdt3_clkctrl, - (*prcm)->cm_l4per_gptimer9_clkctrl, - (*prcm)->cm_l4per_gptimer10_clkctrl, - (*prcm)->cm_l4per_gptimer11_clkctrl, - (*prcm)->cm_l4per_gptimer3_clkctrl, - (*prcm)->cm_l4per_gptimer4_clkctrl, - (*prcm)->cm_l4per_hdq1w_clkctrl, - (*prcm)->cm_l4per_mcbsp4_clkctrl, - (*prcm)->cm_l4per_mcspi2_clkctrl, - (*prcm)->cm_l4per_mcspi3_clkctrl, - (*prcm)->cm_l4per_mcspi4_clkctrl, - (*prcm)->cm_l4per_mmcsd3_clkctrl, - (*prcm)->cm_l4per_mmcsd4_clkctrl, - (*prcm)->cm_l4per_mmcsd5_clkctrl, - (*prcm)->cm_l4per_uart1_clkctrl, - (*prcm)->cm_l4per_uart2_clkctrl, - (*prcm)->cm_l4per_uart4_clkctrl, - (*prcm)->cm_wkup_keyboard_clkctrl, - (*prcm)->cm_wkup_wdtimer2_clkctrl, - (*prcm)->cm_cam_iss_clkctrl, - (*prcm)->cm_cam_fdif_clkctrl, - (*prcm)->cm_dss_dss_clkctrl, - (*prcm)->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32((*prcm)->cm_cam_clkstctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} - void hw_data_init(void) { u32 omap_rev = omap_revision(); diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 5268a1f..32998aa 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -486,94 +486,6 @@ void enable_basic_uboot_clocks(void) 1); } -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 const clk_domains_non_essential[] = { - (*prcm)->cm_mpu_m3_clkstctrl, - (*prcm)->cm_ivahd_clkstctrl, - (*prcm)->cm_dsp_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sgx_clkstctrl, - (*prcm)->cm1_abe_clkstctrl, - (*prcm)->cm_c2c_clkstctrl, - (*prcm)->cm_cam_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sdma_clkstctrl, - 0 - }; - - u32 const clk_modules_hw_auto_non_essential[] = { - (*prcm)->cm_mpu_m3_mpu_m3_clkctrl, - (*prcm)->cm_ivahd_ivahd_clkctrl, - (*prcm)->cm_ivahd_sl2_clkctrl, - (*prcm)->cm_dsp_dsp_clkctrl, - (*prcm)->cm_l3instr_l3_3_clkctrl, - (*prcm)->cm_l3instr_l3_instr_clkctrl, - (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, - (*prcm)->cm_l3init_hsi_clkctrl, - (*prcm)->cm_l4per_hdq1w_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_non_essential[] = { - (*prcm)->cm1_abe_aess_clkctrl, - (*prcm)->cm1_abe_pdm_clkctrl, - (*prcm)->cm1_abe_dmic_clkctrl, - (*prcm)->cm1_abe_mcasp_clkctrl, - (*prcm)->cm1_abe_mcbsp1_clkctrl, - (*prcm)->cm1_abe_mcbsp2_clkctrl, - (*prcm)->cm1_abe_mcbsp3_clkctrl, - (*prcm)->cm1_abe_slimbus_clkctrl, - (*prcm)->cm1_abe_timer5_clkctrl, - (*prcm)->cm1_abe_timer6_clkctrl, - (*prcm)->cm1_abe_timer7_clkctrl, - (*prcm)->cm1_abe_timer8_clkctrl, - (*prcm)->cm1_abe_wdt3_clkctrl, - (*prcm)->cm_l4per_gptimer9_clkctrl, - (*prcm)->cm_l4per_gptimer10_clkctrl, - (*prcm)->cm_l4per_gptimer11_clkctrl, - (*prcm)->cm_l4per_gptimer3_clkctrl, - (*prcm)->cm_l4per_gptimer4_clkctrl, - (*prcm)->cm_l4per_mcspi2_clkctrl, - (*prcm)->cm_l4per_mcspi3_clkctrl, - (*prcm)->cm_l4per_mcspi4_clkctrl, - (*prcm)->cm_l4per_mmcsd3_clkctrl, - (*prcm)->cm_l4per_mmcsd4_clkctrl, - (*prcm)->cm_l4per_mmcsd5_clkctrl, - (*prcm)->cm_l4per_uart1_clkctrl, - (*prcm)->cm_l4per_uart2_clkctrl, - (*prcm)->cm_l4per_uart4_clkctrl, - (*prcm)->cm_wkup_keyboard_clkctrl, - (*prcm)->cm_wkup_wdtimer2_clkctrl, - (*prcm)->cm_cam_iss_clkctrl, - (*prcm)->cm_cam_fdif_clkctrl, - (*prcm)->cm_dss_dss_clkctrl, - (*prcm)->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32((*prcm)->cm_cam_clkstctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} - const struct ctrl_ioregs ioregs_omap5430 = { .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index a78f990..4efc89e 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -567,7 +567,6 @@ u32 omap_ddr_clk(void); u32 get_sys_clk_index(void); void enable_basic_clocks(void); void enable_basic_uboot_clocks(void); -void enable_non_essential_clocks(void); void scale_vcores(struct vcores_data const *); u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); -- cgit v0.10.2 From e81f63f0d2acb130df68da52e711f9178592a012 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 7 Aug 2012 14:59:52 +0530 Subject: ARM: OMAP4/5: Remove dead code against CONFIG_SYS_ENABLE_PADS_ALL The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 85d3754..bf29510 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -43,16 +43,10 @@ static void set_mux_conf_regs(void) set_muxconf_regs_essential(); break; case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: -#ifdef CONFIG_SYS_ENABLE_PADS_ALL - set_muxconf_regs_non_essential(); -#endif break; case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: set_muxconf_regs_essential(); -#ifdef CONFIG_SYS_ENABLE_PADS_ALL - set_muxconf_regs_non_essential(); -#endif break; } } diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index ce8217f..fc94725 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -30,7 +30,6 @@ void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); -void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 9e70d48..43011a4 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -31,7 +31,6 @@ void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); -void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index af854da..b549d72 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -157,19 +157,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/omap5_uevm/mux_data.h b/board/ti/omap5_uevm/mux_data.h index 31ce363..de7ce9f 100644 --- a/board/ti/omap5_uevm/mux_data.h +++ b/board/ti/omap5_uevm/mux_data.h @@ -55,238 +55,4 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - - {C2C_DATAIN0, (IEN | M0)}, /* C2C_DATAIN0 */ - {C2C_DATAIN1, (IEN | M0)}, /* C2C_DATAIN1 */ - {C2C_DATAIN2, (IEN | M0)}, /* C2C_DATAIN2 */ - {C2C_DATAIN3, (IEN | M0)}, /* C2C_DATAIN3 */ - {C2C_DATAIN4, (IEN | M0)}, /* C2C_DATAIN4 */ - {C2C_DATAIN5, (IEN | M0)}, /* C2C_DATAIN5 */ - {C2C_DATAIN6, (IEN | M0)}, /* C2C_DATAIN6 */ - {C2C_DATAIN7, (IEN | M0)}, /* C2C_DATAIN7 */ - {C2C_CLKIN1, (IEN | M0)}, /* C2C_CLKIN1 */ - {C2C_CLKIN0, (IEN | M0)}, /* C2C_CLKIN0 */ - {C2C_CLKOUT0, (M0)}, /* C2C_CLKOUT0 */ - {C2C_CLKOUT1, (M0)}, /* C2C_CLKOUT1 */ - {C2C_DATAOUT0, (M0)}, /* C2C_DATAOUT0 */ - {C2C_DATAOUT1, (M0)}, /* C2C_DATAOUT1 */ - {C2C_DATAOUT2, (M0)}, /* C2C_DATAOUT2 */ - {C2C_DATAOUT3, (M0)}, /* C2C_DATAOUT3 */ - {C2C_DATAOUT4, (M0)}, /* C2C_DATAOUT4 */ - {C2C_DATAOUT5, (M0)}, /* C2C_DATAOUT5 */ - {C2C_DATAOUT6, (M0)}, /* C2C_DATAOUT6 */ - {C2C_DATAOUT7, (M0)}, /* C2C_DATAOUT7 */ - {C2C_DATA8, (IEN | M0)}, /* C2C_DATA8 */ - {C2C_DATA9, (IEN | M0)}, /* C2C_DATA9 */ - {C2C_DATA10, (IEN | M0)}, /* C2C_DATA10 */ - {C2C_DATA11, (IEN | M0)}, /* C2C_DATA11 */ - {C2C_DATA12, (IEN | M0)}, /* C2C_DATA12 */ - {C2C_DATA13, (IEN | M0)}, /* C2C_DATA13 */ - {C2C_DATA14, (IEN | M0)}, /* C2C_DATA14 */ - {C2C_DATA15, (IEN | M0)}, /* C2C_DATA15 */ - {LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 */ - {LLIA_WAKEREQOUT, (M1)}, /* C2C_WAKEREQOUT */ - {HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 */ - {HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 */ - {HSI1_ACWAKE, (PTD | IEN | M6)}, /* GPIO3_66 */ - {HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 */ - {HSI1_ACFLAG, (PTD | IEN | M6)}, /* GPIO3_68 */ - {HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 */ - {HSI1_CAFLAG, (M6)}, /* GPIO3_70 */ - {HSI1_CADATA, (M6)}, /* GPIO3_71 */ - {UART1_TX, (M0)}, /* UART1_TX */ - {UART1_CTS, (PTU | IEN | M0)}, /* UART1_CTS */ - {UART1_RX, (PTU | IEN | M0)}, /* UART1_RX */ - {UART1_RTS, (M0)}, /* UART1_RTS */ - {HSI2_CAREADY, (IEN | M0)}, /* HSI2_CAREADY */ - {HSI2_ACREADY, (OFF_EN | M0)}, /* HSI2_ACREADY */ - {HSI2_CAWAKE, (IEN | PTD | M0)}, /* HSI2_CAWAKE */ - {HSI2_ACWAKE, (M0)}, /* HSI2_ACWAKE */ - {HSI2_CAFLAG, (IEN | PTD | M0)}, /* HSI2_CAFLAG */ - {HSI2_CADATA, (IEN | PTD | M0)}, /* HSI2_CADATA */ - {HSI2_ACFLAG, (M0)}, /* HSI2_ACFLAG */ - {HSI2_ACDATA, (M0)}, /* HSI2_ACDATA */ - {UART2_RTS, (IEN | M1)}, /* MCSPI3_SOMI */ - {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */ - {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */ - {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */ - {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */ - {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */ - {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */ - {DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y */ - {DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X */ - {DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y */ - {DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X */ - {DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y */ - {DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X */ - {DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y */ - {DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X */ - {DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y */ - {TIMER9_PWM_EVT, (IEN | M0)}, /* TIMER9_PWM_EVT */ - {DSIPORTC_TE0, (IEN | M0)}, /* DSIPORTC_TE0 */ - {DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X */ - {DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y */ - {DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X */ - {DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y */ - {DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X */ - {DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y */ - {DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X */ - {DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y */ - {DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X */ - {DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y */ - {RFBI_HSYNC0, (M4)}, /* KBD_COL5 */ - {RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 */ - {RFBI_RE, (M4)}, /* KBD_COL4 */ - {RFBI_A0, (PTD | IEN | M6)}, /* GPIO6_165 */ - {RFBI_DATA8, (M4)}, /* KBD_COL3 */ - {RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 */ - {RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 */ - {RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 */ - {RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 */ - {RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 */ - {RFBI_DATA14, (M4)}, /* KBD_COL7 */ - {RFBI_DATA15, (M4)}, /* KBD_COL6 */ - {GPIO6_182, (M6)}, /* GPIO6_182 */ - {GPIO6_183, (PTD | M6)}, /* GPIO6_183 */ - {GPIO6_184, (M4)}, /* KBD_COL2 */ - {GPIO6_185, (PTD | IEN | M6)}, /* GPIO6_185 */ - {GPIO6_186, (PTD | M6)}, /* GPIO6_186 */ - {GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 */ - {RFBI_DATA0, (PTD | M6)}, /* GPIO6_166 */ - {RFBI_DATA1, (PTD | M6)}, /* GPIO6_167 */ - {RFBI_DATA2, (PTD | M6)}, /* GPIO6_168 */ - {RFBI_DATA3, (PTD | IEN | M6)}, /* GPIO6_169 */ - {RFBI_DATA4, (IEN | M6)}, /* GPIO6_170 */ - {RFBI_DATA5, (IEN | M6)}, /* GPIO6_171 */ - {RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 */ - {RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 */ - {RFBI_CS0, (PTD | IEN | M6)}, /* GPIO6_163 */ - {RFBI_WE, (PTD | M6)}, /* GPIO6_162 */ - {MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 */ - {MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK */ - {MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO*/ - {MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI*/ - {I2C4_SCL, (IEN | M0)}, /* I2C4_SCL */ - {I2C4_SDA, (IEN | M0)}, /* I2C4_SDA */ - {HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */ - {HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */ - {HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */ - {HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */ - {CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */ - {CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */ - {CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */ - {CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */ - {CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */ - {CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */ - {CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */ - {CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */ - {CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */ - {CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */ - {CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */ - {CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */ - {CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */ - {CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */ - {CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */ - {CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */ - {CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */ - {CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */ - {CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */ - {CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */ - {CAM_SHUTTER, (M0)}, /* CAM_SHUTTER */ - {CAM_STROBE, (M0)}, /* CAM_STROBE */ - {CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET */ - {TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 */ - {TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 */ - {TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 */ - {TIMER8_PWM_EVT, (PTU | M6)}, /* GPIO8_230 */ - {I2C3_SCL, (IEN | M0)}, /* I2C3_SCL */ - {I2C3_SDA, (IEN | M0)}, /* I2C3_SDA */ - {GPIO8_233, (IEN | M2)}, /* TIMER8_PWM_EVT */ - {ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */ - {ABEDMIC_DIN1, (IEN | M0)}, /* ABEDMIC_DIN1 */ - {ABEDMIC_DIN2, (IEN | M0)}, /* ABEDMIC_DIN2 */ - {ABEDMIC_DIN3, (IEN | M0)}, /* ABEDMIC_DIN3 */ - {ABEDMIC_CLK1, (M0)}, /* ABEDMIC_CLK1 */ - {ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX */ - {ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX */ - {ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX */ - {ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR */ - {ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR */ - {ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX */ - {ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX */ - {ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX */ - {ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */ - {ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */ - {ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */ - {ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */ - {WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */ - {WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */ - {WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0*/ - {WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1*/ - {WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2*/ - {WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3*/ - {UART5_RX, (PTU | IEN | M0)}, /* UART5_RX */ - {UART5_TX, (M0)}, /* UART5_TX */ - {UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS */ - {UART5_RTS, (M0)}, /* UART5_RTS */ - {I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */ - {I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */ - {MCSPI1_CLK, (M6)}, /* GPIO5_140 */ - {MCSPI1_SOMI, (IEN | M6)}, /* GPIO5_141 */ - {MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 */ - {MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 */ - {MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 */ - {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ - {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ - {PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 */ - {PERSLIMBUS2_DATA, (PTD | IEN | M6)}, /* GPIO5_146 */ - {UART6_TX, (PTU | IEN | M6)}, /* GPIO5_149 */ - {UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 */ - {UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 */ - {UART6_RTS, (PTU | M0)}, /* UART6_RTS */ - {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */ - {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */ - {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ - {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ - -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - -/* - * This pad keeps C2C Module always enabled. - * Putting this in safe mode do not cause the issue. - * C2C driver could enable this mux setting if needed. - */ - {LLIA_WAKEREQIN, (M7)}, /* SAFE MODE */ - {LLIB_WAKEREQIN, (M7)}, /* SAFE MODE */ - {DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */ - {DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */ - {JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */ - {JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */ - {JTAG_RTCK, (M0)}, /* JTAG_RTCK */ - {JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */ - {JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */ - {JTAG_TDO, (M0)}, /* JTAG_TDO */ - {FREF_CLK_IOREQ, (IEN | M0)}, /* FREF_CLK_IOREQ */ - {FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */ - {FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */ - {FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */ - {FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 */ - {FREF_CLK1_REQ, (PTD | IEN | M6)}, /* GPIO1_WK8 */ - {SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */ - {SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */ - {SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */ - {SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */ - {SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */ - {SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */ - {SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */ - {SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */ - {SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */ - -}; - #endif /* _EVM4430_MUX_DATA_H */ diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index cda09a9..5ab6db9 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -284,36 +284,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential_4430, - sizeof(core_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); - else - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential_4460, - sizeof(core_padconf_array_non_essential_4460) / - sizeof(struct pad_conf_entry)); - - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential_4430, - sizeof(wkup_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index fb83eac..53c7080 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -84,190 +84,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ - {GPMC_A16, (M3)}, /* gpio_40 */ - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ - {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (M3)}, /* gpio_46 */ - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ - {GPMC_NCS0, (M3)}, /* gpio_50 */ - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ - {GPMC_NWP, (M3)}, /* gpio_54 */ - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ - {C2C_DATA14, (M1)}, /* dsi2_te0 */ - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ - {HDMI_HPD, (M0)}, /* hdmi_hpd */ - {HDMI_CEC, (M0)}, /* hdmi_cec */ - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | M0)}, /* abe_mcbsp1_clkx */ - {ABE_MCBSP1_DR, (IEN | M0)}, /* abe_mcbsp1_dr */ - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ - {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */ - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M7)}, /* uart2_cts */ - {UART2_RTS, (M7)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M7)}, /* uart2_rx */ - {UART2_TX, (M7)}, /* uart2_tx */ - {HDQ_SIO, (M3)}, /* gpio_127 */ - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ - {UART4_RX, (IEN | M0)}, /* uart4_rx */ - {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ - {SYS_BOOT1, (M3)}, /* gpio_185 */ - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (M3)}, /* gpio_187 */ - {SYS_BOOT4, (M3)}, /* gpio_188 */ - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M3)}, /* gpio_27 */ - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ -}; - -const struct pad_conf_entry core_padconf_array_non_essential_4430[] = { - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ -}; - -const struct pad_conf_entry core_padconf_array_non_essential_4460[] = { - {ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ - {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { - {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */ -}; - #endif /* _PANDA_MUX_DATA_H_ */ diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 79270a9..1e9ef9e 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -73,26 +73,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) { - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential_4430, - sizeof(wkup_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); - } -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 4394dba..9a9efe7 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -65,201 +65,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ - {GPMC_A16, (M3)}, /* gpio_40 */ - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ - {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ - {GPMC_NCS0, (M3)}, /* gpio_50 */ - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ - {GPMC_NWP, (M3)}, /* gpio_54 */ - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (M1)}, /* dsi1_te0 */ - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ - {C2C_DATA14, (M1)}, /* dsi2_te0 */ - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ - {HDMI_HPD, (M0)}, /* hdmi_hpd */ - {HDMI_CEC, (M0)}, /* hdmi_cec */ - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ - {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ - {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ - {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ - {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ - {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ - {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ - {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ - {UART2_RTS, (M0)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ - {UART2_TX, (M0)}, /* uart2_tx */ - {HDQ_SIO, (M3)}, /* gpio_127 */ - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ - {UART4_RX, (IEN | M0)}, /* uart4_rx */ - {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ - {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ - {SYS_BOOT1, (M3)}, /* gpio_185 */ - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ - {SYS_BOOT4, (M3)}, /* gpio_188 */ - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M3)}, /* gpio_27 */ - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ - {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ - {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */ - -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 - Debug led-1 */ - {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 - Debug led-3 */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { - {PAD1_FREF_CLK4_REQ, (M3)} /* gpio_wk7 - Debug led-2 */ -}; - #endif /* _SDP4430_MUX_DATA_H */ -- cgit v0.10.2 From ce3ca05d77a0b7e80afa111080b16d9d61a88a59 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 24 Jan 2014 11:01:56 -0500 Subject: feature-removal-schedule.txt: Drop CONFIG_SYS_ENABLE_PADS_ALL/CLOCKS_ENABLE_ALL Signed-off-by: Tom Rini diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt index 1c79c14..16819c7 100644 --- a/doc/feature-removal-schedule.txt +++ b/doc/feature-removal-schedule.txt @@ -19,22 +19,6 @@ Who: Tom Rini --------------------------- -What: Remove CONFIG_SYS_ENABLE_PADS_ALL and CONFIG_SYS_CLOCKS_ENABLE_ALL -When: Release v2013.07 - -Why: When set these options enable "all" of the pads and clocks found - on OMAP4/5 platforms, so that the Linux Kernel does not have to. - It has been agreed that this goes against the U-Boot design - philosophy and since f3f98bb0 we have not enabled more than is - used in U-Boot. The kernel has been updating drivers to enable - rather than assume pads/clocks have been enabled already. Our - expectation is that by v2013.07 a suitable kernel shall exist that - does not need these options set for a reasonable I/O set to function. - -Who: Tom Rini and Sricharan R - ---------------------------- - What: Users of the legacy miiphy_* code When: undetermined -- cgit v0.10.2 From 6c0a032a3280daf96924b689f47e62bd09472260 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Enric=20Balletb=C3=B2=20i=20Serra?= Date: Fri, 6 Dec 2013 21:30:18 +0100 Subject: ARM: OMAP4: Rename to ti_omap4_common.h Follow the pattern ti__common.h used by other TI processors to be coherent. So just rename omap4_common.h to ti_omap4_common.h. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Lokesh Vutla diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h deleted file mode 100644 index d099bfd..0000000 --- a/include/configs/omap4_common.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments Incorporated. - * Aneesh V - * Steve Sakoman - * - * TI OMAP4 common configuration settings - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_OMAP4_COMMON_H -#define __CONFIG_OMAP4_COMMON_H - -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP44XX 1 /* which is a 44XX */ -#define CONFIG_OMAP4430 1 /* which is in a 4430 */ -#define CONFIG_MISC_INIT_R -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_SYS_THUMB_BUILD - -#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 1 -#define CONFIG_SYS_PL310_BASE 0x48242000 -#endif -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* Get CPU defs */ -#include -#include - -/* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE - -/* - * Total Size Environment - 128k - */ -#define CONFIG_ENV_SIZE (128 << 10) - -/* - * For the DDR timing information we can either dynamically determine - * the timings to use or use pre-determined timings (based on using the - * dynamic method. Default to the static timing infomation. - */ -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - -#include - -/* - * Hardware drivers - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 UART3_BASE - -/* TWL6030 */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_TWL6030_POWER 1 -#endif - -/* USB */ -#define CONFIG_MUSB_UDC 1 -#define CONFIG_USB_OMAP3 1 - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 - -/* Per-Soc commands */ -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - -/* - * Environment setup - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyO2,115200n8\0" \ - "fdt_high=0xffffffff\0" \ - "fdtaddr=0x80f80000\0" \ - "fdtfile=undefined\0" \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "usbtty=cdc_acm\0" \ - "vram=16M\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "vram=${vram} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ - "source ${loadaddr}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ - "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "mmcboot=echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "findfdt="\ - "if test $board_name = sdp4430; then " \ - "setenv fdtfile omap4-sdp.dtb; fi; " \ - "if test $board_name = panda; then " \ - "setenv fdtfile omap4-panda.dtb; fi;" \ - "if test $board_name = panda-a4; then " \ - "setenv fdtfile omap4-panda-a4.dtb; fi;" \ - "if test $board_name = panda-es; then " \ - "setenv fdtfile omap4-panda-es.dtb; fi;" \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" \ - "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "run findfdt; " \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadbootenv; then " \ - "run importbootenv; " \ - "fi;" \ - "if test -n ${uenvcmd}; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "fi;" \ - "if run loadimage; then " \ - "run loadfdt;" \ - "run mmcboot; " \ - "fi; " \ - "fi" - -/* - * Defines for SPL - * It is known that this will break HS devices. Since the current size of - * SPL is overlapped with public stack and breaking non HS devices to boot. - * So moving TEXT_BASE down to non-HS limit. - */ -#define CONFIG_SPL_TEXT_BASE 0x40300000 -#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_DISPLAY_PRINT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" - -#endif /* __CONFIG_OMAP4_COMMON_H */ diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index 73dc088..7378acd 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -4,7 +4,7 @@ * Steve Sakoman * * Configuration settings for the TI OMAP4 Panda board. - * See omap4_common.h for OMAP4 common part + * See ti_omap4_common.h for OMAP4 common part * * SPDX-License-Identifier: GPL-2.0+ */ @@ -36,7 +36,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP -#include +#include #define CONFIG_CMD_NET /* GPIO */ diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index b352511..a837974 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -5,7 +5,7 @@ * Steve Sakoman * * Configuration settings for the TI SDP4430 board. - * See omap4_common.h for OMAP4 common part + * See ti_omap4_common.h for OMAP4 common part * * SPDX-License-Identifier: GPL-2.0+ */ @@ -19,7 +19,7 @@ #define CONFIG_4430SDP 1 /* working with SDP */ #define CONFIG_MACH_TYPE MACH_TYPE_OMAP_4430SDP -#include +#include /* Battery Charger */ #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h new file mode 100644 index 0000000..b625c49 --- /dev/null +++ b/include/configs/ti_omap4_common.h @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated. + * Aneesh V + * Steve Sakoman + * + * TI OMAP4 common configuration settings + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_TI_OMAP4_COMMON_H +#define __CONFIG_TI_OMAP4_COMMON_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP44XX 1 /* which is a 44XX */ +#define CONFIG_OMAP4430 1 /* which is in a 4430 */ +#define CONFIG_MISC_INIT_R +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +#define CONFIG_SYS_THUMB_BUILD + +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 1 +#define CONFIG_SYS_PL310_BASE 0x48242000 +#endif +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* Get CPU defs */ +#include +#include + +/* Use General purpose timer 1 */ +#define CONFIG_SYS_TIMERBASE GPT2_BASE + +/* + * Total Size Environment - 128k + */ +#define CONFIG_ENV_SIZE (128 << 10) + +/* + * For the DDR timing information we can either dynamically determine + * the timings to use or use pre-determined timings (based on using the + * dynamic method. Default to the static timing infomation. + */ +#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +#endif + +#include + +/* + * Hardware drivers + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 UART3_BASE + +/* TWL6030 */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_TWL6030_POWER 1 +#endif + +/* USB */ +#define CONFIG_MUSB_UDC 1 +#define CONFIG_USB_OMAP3 1 + +/* USB device configuration */ +#define CONFIG_USB_DEVICE 1 +#define CONFIG_USB_TTY 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +/* Per-Soc commands */ +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +/* + * Environment setup + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "fdt_high=0xffffffff\0" \ + "fdtaddr=0x80f80000\0" \ + "fdtfile=undefined\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "usbtty=cdc_acm\0" \ + "vram=16M\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "vram=${vram} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "mmcboot=echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "findfdt="\ + "if test $board_name = sdp4430; then " \ + "setenv fdtfile omap4-sdp.dtb; fi; " \ + "if test $board_name = panda; then " \ + "setenv fdtfile omap4-panda.dtb; fi;" \ + "if test $board_name = panda-a4; then " \ + "setenv fdtfile omap4-panda-a4.dtb; fi;" \ + "if test $board_name = panda-es; then " \ + "setenv fdtfile omap4-panda-es.dtb; fi;" \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadbootenv; then " \ + "run importbootenv; " \ + "fi;" \ + "if test -n ${uenvcmd}; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt;" \ + "run mmcboot; " \ + "fi; " \ + "fi" + +/* + * Defines for SPL + * It is known that this will break HS devices. Since the current size of + * SPL is overlapped with public stack and breaking non HS devices to boot. + * So moving TEXT_BASE down to non-HS limit. + */ +#define CONFIG_SPL_TEXT_BASE 0x40300000 +#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_DISPLAY_PRINT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#endif /* __CONFIG_TI_OMAP4_COMMON_H */ -- cgit v0.10.2 From 3d657a05a9cba0415fa028ac3d5acc5ec883bf00 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Enric=20Balletb=C3=B2=20i=20Serra?= Date: Fri, 6 Dec 2013 21:30:19 +0100 Subject: ARM: OMAP5: Rename to ti_omap5_common.h Follow the pattern ti__common.h used by other TI processors to be coherent. So just rename omap5_common.h to ti_omap5_common.h. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Lokesh Vutla diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index f210ed8..04ae3ca 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -4,7 +4,7 @@ * Lokesh Vutla * * Configuration settings for the TI DRA7XX board. - * See omap5_common.h for omap5 common settings. + * See ti_omap5_common.h for omap5 common settings. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -34,7 +34,7 @@ #define CONFIG_SYS_OMAP_ABE_SYSCK -#include +#include /* CPSW Ethernet */ #define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h deleted file mode 100644 index c7fa37e..0000000 --- a/include/configs/omap5_common.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2013 - * Texas Instruments Incorporated. - * Sricharan R - * - * Derived from OMAP4 done by: - * Aneesh V - * - * TI OMAP5 AND DRA7XX common configuration settings - * - * SPDX-License-Identifier: GPL-2.0+ - * - * For more details, please see the technical documents listed at - * http://www.ti.com/product/omap5432 - */ - -#ifndef __CONFIG_OMAP5_COMMON_H -#define __CONFIG_OMAP5_COMMON_H - -#define CONFIG_OMAP54XX -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_MISC_INIT_R -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_SYS_CACHELINE_SIZE 64 - -/* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE - -/* - * For the DDR timing information we can either dynamically determine - * the timings to use or use pre-determined timings (based on using the - * dynamic method. Default to the static timing infomation. - */ -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PALMAS_POWER -#endif - -#include -#include - -#define CONFIG_ENV_SIZE (128 << 10) - -#include - -/* - * Hardware drivers - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 - -/* Per-SoC commands */ -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - -/* - * Environment setup - */ -#ifndef PARTS_DEFAULT -#define PARTS_DEFAULT -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "fdtaddr=0x80F80000\0" \ - "fdt_high=0xffffffff\0" \ - "rdaddr=0x81000000\0" \ - "console=" CONSOLEDEV ",115200n8\0" \ - "fdtfile=undefined\0" \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "usbtty=cdc_acm\0" \ - "vram=16M\0" \ - "partitions=" PARTS_DEFAULT "\0" \ - "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk1p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "vram=${vram} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ - "source ${loadaddr}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ - "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "mmcboot=mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loadimage; then " \ - "run loadfdt; " \ - "echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr}; " \ - "fi;" \ - "fi;\0" \ - "findfdt="\ - "if test $board_name = omap5_uevm; then " \ - "setenv fdtfile omap5-uevm.dtb; fi; " \ - "if test $board_name = dra7xx; then " \ - "setenv fdtfile dra7-evm.dtb; fi;" \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" \ - "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \ - -#define CONFIG_BOOTCOMMAND \ - "run findfdt; " \ - "run mmcboot;" \ - "setenv mmcdev 1; " \ - "setenv bootpart 1:2; " \ - "setenv mmcroot /dev/mmcblk0p2 rw; " \ - "run mmcboot;" \ - - -/* - * SPL related defines. The Public RAM memory map the ROM defines the - * area between 0x40300000 and 0x4031E000 as a download area for OMAP5 - * (dra7xx is larger, but we do not need to be larger at this time). We - * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and - * print some information. - */ -#define CONFIG_SPL_TEXT_BASE 0x40300000 -#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_DISPLAY_PRINT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" - -#endif /* __CONFIG_OMAP5_COMMON_H */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 76c5106..51dff23 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -4,7 +4,7 @@ * Sricharan R * * Configuration settings for the TI EVM5430 board. - * See omap5_common.h for omap5 common settings. + * See ti_omap5_common.h for omap5 common settings. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -17,7 +17,7 @@ "uuid_disk=${uuid_gpt_disk};" \ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" -#include +#include #define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 UART3_BASE diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h new file mode 100644 index 0000000..4f34dcf --- /dev/null +++ b/include/configs/ti_omap5_common.h @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated. + * Sricharan R + * + * Derived from OMAP4 done by: + * Aneesh V + * + * TI OMAP5 AND DRA7XX common configuration settings + * + * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the technical documents listed at + * http://www.ti.com/product/omap5432 + */ + +#ifndef __CONFIG_TI_OMAP5_COMMON_H +#define __CONFIG_TI_OMAP5_COMMON_H + +#define CONFIG_OMAP54XX +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_MISC_INIT_R +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* Use General purpose timer 1 */ +#define CONFIG_SYS_TIMERBASE GPT2_BASE + +/* + * For the DDR timing information we can either dynamically determine + * the timings to use or use pre-determined timings (based on using the + * dynamic method. Default to the static timing infomation. + */ +#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +#endif + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PALMAS_POWER +#endif + +#include +#include + +#define CONFIG_ENV_SIZE (128 << 10) + +#include + +/* + * Hardware drivers + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 + +/* Per-SoC commands */ +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +/* + * Environment setup + */ +#ifndef PARTS_DEFAULT +#define PARTS_DEFAULT +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x80F80000\0" \ + "fdt_high=0xffffffff\0" \ + "rdaddr=0x81000000\0" \ + "console=" CONSOLEDEV ",115200n8\0" \ + "fdtfile=undefined\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "usbtty=cdc_acm\0" \ + "vram=16M\0" \ + "partitions=" PARTS_DEFAULT "\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk1p2 rw\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "vram=${vram} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt; " \ + "echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi;" \ + "fi;\0" \ + "findfdt="\ + "if test $board_name = omap5_uevm; then " \ + "setenv fdtfile omap5-uevm.dtb; fi; " \ + "if test $board_name = dra7xx; then " \ + "setenv fdtfile dra7-evm.dtb; fi;" \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \ + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run mmcboot;" \ + "setenv mmcdev 1; " \ + "setenv bootpart 1:2; " \ + "setenv mmcroot /dev/mmcblk0p2 rw; " \ + "run mmcboot;" \ + + +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x40300000 and 0x4031E000 as a download area for OMAP5 + * (dra7xx is larger, but we do not need to be larger at this time). We + * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and + * print some information. + */ +#define CONFIG_SPL_TEXT_BASE 0x40300000 +#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_DISPLAY_PRINT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#endif /* __CONFIG_TI_OMAP5_COMMON_H */ -- cgit v0.10.2 From 70e71b61bca9c44708a449461f0dc5a51d7cf622 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Enric=20Balletb=C3=B2=20i=20Serra?= Date: Fri, 6 Dec 2013 21:30:20 +0100 Subject: TI: armv7: Move ELM support to SoC configuration file. The ELM hardware engine wihich is used for ECC error detections is not present on OMAP3 SoC, so move the CONFIG_SPL_NAND_AM33XX_BCH from ti_armv7_common.h to SoC configuration file. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Lokesh Vutla diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 4364eef..91f97dd 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -73,6 +73,10 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ +#endif + /* Now bring in the rest of the common code. */ #include diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 99b60fc..f4e42ef 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -237,7 +237,6 @@ #define CONFIG_SPL_BOARD_INIT #ifdef CONFIG_NAND -#define CONFIG_SPL_NAND_AM33XX_BCH /* OMAP4 and later ELM support */ #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index b625c49..2f0e4c0 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -159,4 +159,8 @@ #define CONFIG_SPL_DISPLAY_PRINT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ +#endif + #endif /* __CONFIG_TI_OMAP4_COMMON_H */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 4f34dcf..7b10fbd 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -146,4 +146,8 @@ #define CONFIG_SPL_DISPLAY_PRINT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ +#endif + #endif /* __CONFIG_TI_OMAP5_COMMON_H */ -- cgit v0.10.2 From c6a7fce1138596b9e91727c32da2c2faa3bb481f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Enric=20Balletb=C3=B2=20i=20Serra?= Date: Fri, 6 Dec 2013 21:30:21 +0100 Subject: TI: armv7: Do not define the number DRAM banks if is already defined. If CONFIG_NR_DRAM_BANKS is not defined, we say (for simplicity) that we have 1 bank, but for some boards should be interesting that we can define CONFIG_NR_DRAM_BANKS. To handle this possibility just define the number of DRAM banks if is not already defined. This is useful for some OMAP3 boards where the DRAM initialitzation is only at u-boot level. Signed-off-by: Enric Balletbo i Serra diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index f4e42ef..69d69a5 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -45,11 +45,15 @@ #define CONFIG_BOOTDELAY 1 /* - * DDR information. We say (for simplicity) that we have 1 bank, - * always, even when we have more. We always start at 0x80000000, - * and we place the initial stack pointer in our SRAM. + * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, + * we say (for simplicity) that we have 1 bank, always, even when + * we have more. We always start at 0x80000000, and we place the + * initial stack pointer in our SRAM. Otherwise, we can define + * CONFIG_NR_DRAM_BANKS before including this file. */ +#ifndef CONFIG_NR_DRAM_BANKS #define CONFIG_NR_DRAM_BANKS 1 +#endif #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ GENERATED_GBL_DATA_SIZE) -- cgit v0.10.2 From ac02aa97636b3df25dc10022fd328208deafbfee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Enric=20Balletb=C3=B2=20i=20Serra?= Date: Fri, 6 Dec 2013 21:30:22 +0100 Subject: ARM: OMAP3: Rename OMAP3_PUBLIC_SRAM_* to NON_SECURE_SRAM_* Other TI processors like am33xx, omap4 and omap5 have called these variables as NON_SECURE_SRAM_*, shouldn't be a big problem rename these variables to be coherent. One reason more to rename these variables is to have the possibility of any OMAP3 board to use the ti_armv7_common.h include as the NON_SECURE_SRAM_END is used to define the CONFIG_SYS_INIT_SP_ADDR variable. Signed-off-by: Enric Balletbo i Serra diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 65a5995..194b93b 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -140,13 +140,13 @@ struct gpio { SRAM_OFFSET2) #define SRAM_CLK_CODE (SRAM_VECT_CODE + 64) -#define OMAP3_PUBLIC_SRAM_BASE 0x40208000 /* Works for GP & EMU */ -#define OMAP3_PUBLIC_SRAM_END 0x40210000 +#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */ +#define NON_SECURE_SRAM_END 0x40210000 #define LOW_LEVEL_SRAM_STACK 0x4020FFFC /* scratch area - accessible on both EMU and GP */ -#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA OMAP3_PUBLIC_SRAM_BASE +#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START #define DEBUG_LED1 149 /* gpio */ #define DEBUG_LED2 150 /* gpio */ -- cgit v0.10.2 From c7964f86c28da4e4cf5a7cc4430461ea17218d80 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Enric=20Balletb=C3=B2=20i=20Serra?= Date: Fri, 6 Dec 2013 21:30:23 +0100 Subject: TI: OMAP3: Create common config files for TI OMAP3 platforms. Create a new file, include/configs/ti_omap3_common.h, for everything common to the OMAP3 SoC leaving just the board specific part to board configuration file. Signed-off-by: Enric Balletbo i Serra diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h new file mode 100644 index 0000000..854cb78 --- /dev/null +++ b/include/configs/ti_omap3_common.h @@ -0,0 +1,73 @@ +/* + * ti_omap3_common.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the technical documents listed at + * http://www.ti.com/product/omap3530 + * http://www.ti.com/product/omap3630 + * http://www.ti.com/product/dm3730 + */ + +#ifndef __CONFIG_TI_OMAP3_COMMON_H__ +#define __CONFIG_TI_OMAP3_COMMON_H__ + +#define CONFIG_OMAP34XX + +#include +#include + +/* The chip has SDRC controller */ +#define CONFIG_SDRC + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +/* NS16550 Configuration */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ + 115200} + +/* Select serial console configuration */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) + +/* TWL4030 */ +#define CONFIG_TWL4030_POWER 1 + +/* SPL */ +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (54 * 1024) +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_POWER_SUPPORT + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_SIMPLE +#endif + +/* Now bring in the rest of the common code. */ +#include + +#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ -- cgit v0.10.2 From e37e954eba3edb5015a0a02880d57517f57425d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Enric=20Balletb=C3=B2=20i=20Serra?= Date: Fri, 6 Dec 2013 21:30:24 +0100 Subject: OMAP3: igep00x0: Convert to ti_omap3_common.h. To reduce code duplication update omap3_igep00x0.h to use ti_omap3_common.h. Signed-off-by: Enric Balletbo i Serra diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 71062a6..20fbbec 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -10,20 +10,13 @@ #ifndef __IGEP00X0_H #define __IGEP00X0_H -#include - -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON +#ifdef CONFIG_BOOT_NAND +#define CONFIG_NAND +#endif -#define CONFIG_SDRC /* The chip has SDRC controller */ +#define CONFIG_NR_DRAM_BANKS 2 -#include -#include +#include #include /* @@ -32,47 +25,12 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - #define CONFIG_MISC_INIT_R -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ #define CONFIG_SUPPORT_RAW_INITRD -/* - * NS16550 Configuration - */ - -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* select serial console configuration */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ - 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - /* define to enable boot progress via leds */ #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) @@ -95,21 +53,10 @@ #define CONFIG_USBD_MANUFACTURER "Texas Instruments" #define CONFIG_USBD_PRODUCT_NAME "IGEP" -/* commands to include */ -#include - #define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ #ifdef CONFIG_BOOT_ONENAND #define CONFIG_CMD_ONENAND /* ONENAND support */ #endif -#ifdef CONFIG_BOOT_NAND -#define CONFIG_CMD_NAND -#endif #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ @@ -117,24 +64,8 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_NFS /* NFS support */ -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ -#define CONFIG_MTD_DEVICE - -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#undef CONFIG_CMD_IMLS /* List all found images */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_OMAP34XX -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER 1 - -#define CONFIG_BOOTDELAY 3 +/*#undef CONFIG_ENV_IS_NOWHERE*/ #define CONFIG_EXTRA_ENV_SETTINGS \ "usbtty=cdc_acm\0" \ @@ -205,48 +136,6 @@ "fi;" \ "run nandboot;" \ -#define CONFIG_AUTO_COMPLETE 1 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "U-Boot # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ - /* works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* - * Physical Memory Map - * - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - /* * FLASH and environment organization */ @@ -263,24 +152,16 @@ #define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET #endif -#ifdef CONFIG_BOOT_NAND +#ifdef CONFIG_NAND #define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */ -#define CONFIG_NAND_OMAP_GPMC -#define CONFIG_SYS_NAND_BASE NAND_BASE #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ #define CONFIG_ENV_ADDR NAND_ENV_OFFSET -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #endif /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -/* * SMSC911x Ethernet */ #if defined(CONFIG_CMD_NET) @@ -289,54 +170,9 @@ #define CONFIG_SMC911X_BASE 0x2C000000 #endif /* (CONFIG_CMD_NET) */ -/* - * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader - * and older u-boot.bin with the new U-Boot SPL. - */ -#define CONFIG_SYS_TEXT_BASE 0x80008000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (54 * 1024) -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -/* move malloc and bss high to prevent clashing with the main image */ -#define CONFIG_SYS_SPL_MALLOC_START 0x87000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -/* MMC boot config */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT - -#define CONFIG_SPL_POWER_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" - +/* OneNAND boot config */ #ifdef CONFIG_BOOT_ONENAND #define CONFIG_SPL_ONENAND_SUPPORT - -/* OneNAND boot config */ #define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000 #define CONFIG_SYS_ONENAND_PAGE_SIZE 2048 #define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000 @@ -345,13 +181,8 @@ #endif -#ifdef CONFIG_BOOT_NAND -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC - /* NAND boot config */ +#ifdef CONFIG_NAND #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 @@ -363,8 +194,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #endif #endif /* __IGEP00X0_H */ -- cgit v0.10.2 From 0df8afdf107268198e706ce84b71820db3572936 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 19 Dec 2013 10:00:28 +0530 Subject: ARM: AM43xx: Enable DDR dynamic IO power down for DDR3 This patch enables dynamically powering down the IO receiver when not performing a read on DDR3 board. This optimizes both active and standby power consumption. This is derived from a patch that is done on AM335x[1] [1] http://arago-project.org/git/projects/?p=u-boot-am33x.git;a=commit;h=6a9ee4bc72ece53fabf01825605fba3d71d5feb2 Signed-off-by: Lokesh Vutla diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index ed87cd9..4e6846a 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -188,7 +188,7 @@ const struct ctrl_ioregs ioregs_ddr3 = { .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, - .emif_sdram_config_ext = 0x0043, + .emif_sdram_config_ext = 0x0143, }; const struct emif_regs ddr3_emif_regs_400Mhz = { -- cgit v0.10.2 From e9b13ce0b6f58f9d1c9d2a4f3e2927b671503a9e Mon Sep 17 00:00:00 2001 From: "Satyanarayana, Sandhya" Date: Thu, 19 Dec 2013 10:00:29 +0530 Subject: ARM: AM335x: Enable DDR dynamic IO power down This patch enables dynamically powering down the IO receiver when not performing a read on boards using DDR3. This optimizes both active and standby power consumption. This bit is not set on EVM SK and EVM 1.5 and later boards. Setting the same. This has been tested on PG2.0 EVM1.5, EVM1.2, EVM-SK, BBB. Signed-off-by: Lokesh Vutla Signed-off-by: Satyanarayana, Sandhya diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index c1777df..fbe599d 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -43,7 +43,7 @@ #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B /* Micron MT41J128M16JT-125 */ -#define MT41J128MJT125_EMIF_READ_LATENCY 0x06 +#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006 #define MT41J128MJT125_EMIF_TIM1 0x0888A39B #define MT41J128MJT125_EMIF_TIM2 0x26337FDA #define MT41J128MJT125_EMIF_TIM3 0x501F830F @@ -65,7 +65,7 @@ #define MT41J256MJT125_EMIF_SDCFG 0x61C04B32 /* Micron MT41J256M8HX-15E */ -#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06 +#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F @@ -97,7 +97,7 @@ #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B /* Micron MT41J512M8RH-125 on EVM v1.5 */ -#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06 +#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF @@ -113,7 +113,7 @@ #define MT41J512M8RH125_IOCTRL_VALUE 0x18B /* Samsung K4B2G1646E-BIH9 */ -#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x07 +#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007 #define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B #define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA #define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF -- cgit v0.10.2 From 3ac8c0bf65759a1725e5dfc24a6e0214d6b37a4a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 14 Jan 2014 10:54:42 -0600 Subject: DRA7: Add support for ES1.1 silicon ID code ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support for ES1.1 IDCODE change. Signed-off-by: Nishanth Menon Reviewed-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index cd6289b..429c4be 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -179,8 +179,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) writel(regs->temp_alert_config, &emif->emif_temp_alert_config); writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); - if ((omap_revision() >= OMAP5430_ES1_0) || - (omap_revision() == DRA752_ES1_0)) { + if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) { writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); } else if (omap_revision() >= OMAP4460_ES1_0) { @@ -309,7 +308,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) * The same sequence should work on OMAP5432 as well. But strange that * it is not working */ - if (omap_revision() == DRA752_ES1_0) { + if (is_dra7xx()) { do_ext_phy_settings(base, regs); writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); writel(regs->sdram_config_init, &emif->emif_sdram_config); diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 32998aa..ad97132 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -551,6 +551,7 @@ void hw_data_init(void) break; case DRA752_ES1_0: + case DRA752_ES1_1: *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; *omap_vcores = &dra752_volts; @@ -578,6 +579,7 @@ void get_ioregs(const struct ctrl_ioregs **regs) *regs = &ioregs_omap5432_es2; break; case DRA752_ES1_0: + case DRA752_ES1_1: *regs = &ioregs_dra7xx_es1; break; diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 5386ae0..737d23c 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -333,6 +333,9 @@ void init_omap_revision(void) case DRA752_CONTROL_ID_CODE_ES1_0: *omap_si_rev = DRA752_ES1_0; break; + case DRA752_CONTROL_ID_CODE_ES1_1: + *omap_si_rev = DRA752_ES1_1; + break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; } diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 2e18706..16a91f9 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -245,6 +245,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_ddr3_532_mhz_1cs_es2; break; case DRA752_ES1_0: + case DRA752_ES1_1: switch (emif_nr) { case 1: *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; @@ -273,6 +274,7 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; break; case DRA752_ES1_0: + case DRA752_ES1_1: default: *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2; } @@ -460,6 +462,7 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2); break; case DRA752_ES1_0: + case DRA752_ES1_1: if (emif_nr == 1) { *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; *size = @@ -626,6 +629,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations) sizeof(omap5_bug_00339_regs[0]); break; case DRA752_ES1_0: + case DRA752_ES1_1: bug_00339_regs_ptr = dra_bug_00339_regs; *iterations = sizeof(dra_bug_00339_regs)/ sizeof(dra_bug_00339_regs[0]); diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 590235b..34f6fc5 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -44,6 +44,7 @@ #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F +#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F /* UART */ #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 4efc89e..04925bc 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -642,6 +642,7 @@ static inline u8 is_dra7xx(void) /* DRA7XX */ #define DRA752_ES1_0 0x07520100 +#define DRA752_ES1_1 0x07520110 /* * SRAM scratch space entries -- cgit v0.10.2 From 194dd74ad919e57026f385aaab7f89acf7ea79ef Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 14 Jan 2014 12:27:29 -0600 Subject: DRA7: add ABB setup for MPU voltage domain Patch adds modification to shared omap5 abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain at OPP_NOM. Signed-off-by: Nishanth Menon Reviewed-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap5/abb.c b/arch/arm/cpu/armv7/omap5/abb.c index 31b6795..3bf8897 100644 --- a/arch/arm/cpu/armv7/omap5/abb.c +++ b/arch/arm/cpu/armv7/omap5/abb.c @@ -28,18 +28,25 @@ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) { u32 vset; + u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK; + u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK; + if (!is_omap54xx()) { + /* DRA7 */ + fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK; + fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK; + } /* * ABB parameters must be properly fused * otherwise ABB should be disabled */ vset = readl(fuse); - if (!(vset & OMAP5_ABB_FUSE_ENABLE_MASK)) + if (!(vset & fuse_enable_mask)) return -1; /* prepare VSET value for LDOVBB mux register */ - vset &= OMAP5_ABB_FUSE_VSET_MASK; - vset >>= ffs(OMAP5_ABB_FUSE_VSET_MASK) - 1; + vset &= fuse_vset_mask; + vset >>= ffs(fuse_vset_mask) - 1; vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1; vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK; diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 77c428b..ff32807 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -432,11 +432,13 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_srcomp_code_latch = 0x4A002E84, .control_ddr_control_ext_0 = 0x4A002E88, .control_padconf_core_base = 0x4A003400, + .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B24, .control_port_emif1_sdram_config = 0x4AE0C110, .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, .control_port_emif2_sdram_config = 0x4AE0C118, .control_emif1_sdram_config_ext = 0x4AE0C144, .control_emif2_sdram_config_ext = 0x4AE0C148, + .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C158, .control_padconf_mode = 0x4AE0C5A0, .control_xtal_oscillator = 0x4AE0C5A4, .control_i2c_2 = 0x4AE0C5A8, @@ -807,6 +809,9 @@ struct prcm_regs const dra7xx_prcm = { .cm_dsp_clkstctrl = 0x4a005400, .cm_dsp_dsp_clkctrl = 0x4a005420, + /* prm irqstatus regs */ + .prm_irqstatus_mpu_2 = 0x4ae06014, + /* cm2.ckgen */ .cm_clksel_usb_60mhz = 0x4a008104, .cm_clkmode_dpll_per = 0x4a008140, @@ -967,4 +972,7 @@ struct prcm_regs const dra7xx_prcm = { .prm_vc_val_bypass = 0x4ae07da0, .prm_vc_cfg_i2c_mode = 0x4ae07db4, .prm_vc_cfg_i2c_clk = 0x4ae07db8, + + .prm_abbldo_mpu_setup = 0x4AE07DDC, + .prm_abbldo_mpu_ctrl = 0x4AE07DE0, }; diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 34f6fc5..19fdece 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -205,6 +205,8 @@ struct s32ktimer { /* ABB efuse masks */ #define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) #define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) +#define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) +#define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) -- cgit v0.10.2 From b1cde7e21f950e05d18c102976c3b7d232b65e13 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 20 Jan 2014 08:40:07 -0500 Subject: am43xx_evm.h: Correct SPL max size Upon further inspection of relevant parts of the architecture, the maximum SPL binary size is 220KiB. Cc: Lokesh Vutla Signed-off-by: Tom Rini diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 4de495a..83431a4 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -34,7 +34,7 @@ /* SPL defines. */ #define CONFIG_SPL_TEXT_BASE 0x40300350 -#define CONFIG_SPL_MAX_SIZE (0x40337C00 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */ #define CONFIG_SPL_YMODEM_SUPPORT /* Enabling L2 Cache */ -- cgit v0.10.2