From 54652991caedc39b2ec2e5b49e750669bfcd1e2e Mon Sep 17 00:00:00 2001 From: Philippe De Muyter Date: Tue, 17 Aug 2010 18:40:25 +0200 Subject: Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips. I have "ported" U-boot to a in house made board with Numonyx Axcell P33/P30 256-Mbit 65nm flash chips. After some time :( searching for bugs in our board or soft, we have discovered that those chips have a small but annoying bug, documented in "Numonyx Axcell P33/P30 256-Mbit Specification Update" It states : When customer uses [...] block unlock, the block lock status might be altered inadvertently. Lock status might be set to either 01h or 03h unexpectedly (00h as expected data), which leads to program/erase failure on certain blocks. A working workaround is given, which I have applied and tested with success : Workaround: If the interval between 60h and its subsequent command can be guaranteed within 20us, Option I is recommended, otherwise Option II (involves hardware) should be selected. Option I: The table below lists the detail command sequences: Command Data bus Address bus Remarks Sequence 1 90h Block Address Read Lock Status 2 Read Block Address + 02h (2)(3) (1) 3 60h Block Address (2)(3) (1) Lock/Unlock/RCR Configuration 4 D0h/01h/03h Block Address Notes: (1) Block Address refers to RCR configuration data only when the 60h command sequence is used to set RCR register combined with 03h subsequent command. (2) For the third and fourth command sequences, the Block Address must be the same. (3) The interval between 60h command and its subsequent D0h/01h/2Fh/03h commands should be less than 20us. And here is a log comparison of a simple (destructive) flash test without and with the workaround. diff without-numonyx-workaround.log with-numonyx-workaround.log -U-Boot 2010.06-00696-g22b002c-dirty (Aug 16 2010 - 15:07:47) +U-Boot 2010.06-00696-g22b002c-dirty (Aug 16 2010 - 15:25:19) CPU: Freescale MCF5484 CPU CLK 200 MHz BUS CLK 100 MHz Board: Macq Electronique ME2060 I2C: ready DRAM: 64 MiB FLASH: 32 MiB In: serial Out: serial Err: serial Net: FEC0, FEC1 -> flinfo Bank # 1: CFI conformant FLASH (16 x 16) Size: 32 MB in 259 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x8922 Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes Sector Start Addresses: FE000000 RO FE008000 RO FE010000 RO FE018000 RO FE020000 RO FE040000 RO FE060000 RO FE080000 RO FE0A0000 RO FE0C0000 RO ... FFF80000 RO FFFA0000 RO FFFC0000 RO FFFE0000 RO -> protect off all Un-Protect Flash Bank # 1 ................... done -> erase all Erase Flash Bank # 1 ................... done -> cp.b 1000000 fe000000 2000000 -Copy to Flash... Flash not Erased +Copy to Flash... done -> Signed-off-by: Philippe De Muyter Signed-off-by: Stefan Roese diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 1191ef0..44ebb9d 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1355,15 +1355,32 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: - flash_write_cmd (info, sector, 0, - FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); - if (prot) - flash_write_cmd (info, sector, 0, - FLASH_CMD_PROTECT_SET); - else + /* + * see errata called + * "Numonyx Axcell P33/P30 Specification Update" :) + */ + flash_write_cmd (info, sector, 0, FLASH_CMD_READ_ID); + if (!flash_isequal (info, sector, FLASH_OFFSET_PROTECT, + prot)) { + /* + * cmd must come before FLASH_CMD_PROTECT + 20us + * Disable interrupts which might cause a timeout here. + */ + int flag = disable_interrupts (); + unsigned short cmd; + + if (prot) + cmd = FLASH_CMD_PROTECT_SET; + else + cmd = FLASH_CMD_PROTECT_CLEAR; + flash_write_cmd (info, sector, 0, - FLASH_CMD_PROTECT_CLEAR); + FLASH_CMD_PROTECT); + flash_write_cmd (info, sector, 0, cmd); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + } break; case CFI_CMDSET_AMD_EXTENDED: case CFI_CMDSET_AMD_STANDARD: -- cgit v0.10.2 From 680c613a5cc7be59a9123765c51287bc306df02f Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 9 Aug 2010 18:39:57 -0500 Subject: powerpc/8xxx: share PIC defines among 85xx and 86xx fixes breakeage introduced by commit a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query feature reporting register for num cores on unknown cpus" Reported-by: Wolfgang Denk Signed-off-by: Kim Phillips Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index f15d43c..3f80700 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -74,7 +74,7 @@ int checkcpu (void) puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2c3be6d..27236a0 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -179,7 +179,7 @@ static void corenet_tb_init(void) volatile ccsr_rcpm_t *rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); volatile ccsr_pic_t *pic = - (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); u32 whoami = in_be32(&pic->whoami); /* Enable the timebase register for this core */ diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index ac8c01a..a62b031 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -35,7 +35,7 @@ int interrupt_init_cpu(unsigned int *decrementer_count) { - ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR; + ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; out_be32(&pic->gcr, MPC85xx_PICGCR_RST); while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index e05257c..603baef 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -38,7 +38,7 @@ u32 get_my_id() int cpu_reset(int nr) { - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); out_be32(&pic->pir, 1 << nr); /* the dummy read works around an errata on early 85xx MP PICs */ (void)in_be32(&pic->pir); @@ -207,7 +207,7 @@ static void plat_mp_up(unsigned long bootpg) gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); - pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1; @@ -272,7 +272,7 @@ static void plat_mp_up(unsigned long bootpg) volatile u32 bpcr; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); u32 devdisr; int timeout = 10; diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index 7e96664..7800717 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -288,7 +288,7 @@ UnknownException(struct pt_regs *regs) void ExtIntException(struct pt_regs *regs) { - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); uint vect; diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 97a94f4..5b30fbd 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -110,13 +110,15 @@ struct cpu_type *identify_cpu(u32 ver) } int cpu_numcores() { - ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR; + ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; struct cpu_type *cpu = gd->cpu; /* better to query feature reporting register than just assume 1 */ +#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00 +#define MPC8xxx_PICFRR_NCPU_SHIFT 8 if (cpu == &cpu_type_unknown) - return ((in_be32(&pic->frr) & MPC85xx_PICFRR_NCPU_MASK) >> - MPC85xx_PICFRR_NCPU_SHIFT) + 1; + return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >> + MPC8xxx_PICFRR_NCPU_SHIFT) + 1; return cpu->num_cores; } diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index c1382c8..e5a02c3 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -760,8 +760,6 @@ typedef struct ccsr_pic { u32 eoi; /* End Of IRQ */ u8 res9[3916]; u32 frr; /* Feature Reporting */ -#define MPC85xx_PICFRR_NCPU_MASK 0x00001f00 -#define MPC85xx_PICFRR_NCPU_SHIFT 8 u8 res10[28]; u32 gcr; /* Global Configuration */ #define MPC85xx_PICGCR_RST 0x80000000 @@ -2301,7 +2299,7 @@ typedef struct ccsr_pme { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) -#define CONFIG_SYS_MPC85xx_PIC_ADDR \ +#define CONFIG_SYS_MPC8xxx_PIC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) #define CONFIG_SYS_MPC85xx_CPM_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index 4bebb68..4e60cbb 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -1250,12 +1250,15 @@ typedef struct immap { extern immap_t *immr; -#define CONFIG_SYS_MPC86xx_DDR_OFFSET (0x2000) +#define CONFIG_SYS_MPC86xx_DDR_OFFSET 0x2000 #define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET) -#define CONFIG_SYS_MPC86xx_DDR2_OFFSET (0x6000) +#define CONFIG_SYS_MPC86xx_DDR2_OFFSET 0x6000 #define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000) +#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET) +#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000 +#define CONFIG_SYS_MPC8xxx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET) + #define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000 #ifdef CONFIG_MPC8610 -- cgit v0.10.2 From ed062e0f6c7ee8c56eb096fdd3e01712c53fc2e4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 17 Aug 2010 23:12:37 -0500 Subject: powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs Official docs call it the Job Ring not Job Queue for the p4080 security block. Match the docs to reduce confusion. Signed-off-by: Kim Phillips Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index 3861146..a6cfaa5 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -81,10 +81,10 @@ struct liodn_id_table fman2_liodn_tbl[] = { #endif struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JQ_LIODN_ENTRY(0, 146, 154), - SET_SEC_JQ_LIODN_ENTRY(1, 147, 155), - SET_SEC_JQ_LIODN_ENTRY(2, 178, 186), - SET_SEC_JQ_LIODN_ENTRY(3, 179, 187), + SET_SEC_JR_LIODN_ENTRY(0, 146, 154), + SET_SEC_JR_LIODN_ENTRY(1, 147, 155), + SET_SEC_JR_LIODN_ENTRY(2, 178, 186), + SET_SEC_JR_LIODN_ENTRY(3, 179, 187), SET_SEC_RTIC_LIODN_ENTRY(a, 144), SET_SEC_RTIC_LIODN_ENTRY(b, 145), SET_SEC_RTIC_LIODN_ENTRY(c, 176), diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index acdc99a..4c17fe2 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -115,11 +115,11 @@ extern void fdt_fixup_liodn(void *blob); FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ -#define SET_SEC_JQ_LIODN_ENTRY(jqNum, liodnA, liodnB) \ - SET_LIODN_ENTRY_2("fsl,sec4.0-job-queue", liodnA, liodnB,\ - offsetof(ccsr_sec_t, jqliodnr[jqNum].ls) + \ +#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \ + SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\ + offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jqNum) + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum) /* This is a bit evil since we treat rtic param as both a string & hex value */ #define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index e5a02c3..3dd2b7f 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2063,7 +2063,7 @@ typedef struct ccsr_sec { struct { u32 ms; /* Job Ring LIODN Register, MS */ u32 ls; /* Job Ring LIODN Register, LS */ - } jqliodnr[4]; + } jrliodnr[4]; u8 res2[0x30]; struct { u32 ms; /* RTIC LIODN Register, MS */ @@ -2108,8 +2108,8 @@ typedef struct ccsr_sec { #define SEC_CTPR_MS_AXI_LIODN 0x08000000 #define SEC_CTPR_MS_QI 0x02000000 #define SEC_RVID_MA 0x0f000000 -#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000 -#define SEC_CHANUM_MS_JQNUM_SHIFT 28 +#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 +#define SEC_CHANUM_MS_JRNUM_SHIFT 28 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 #define SEC_CHANUM_MS_DECONUM_SHIFT 24 #endif -- cgit v0.10.2 From 90870d9846e6a302823712acf6d40f947e60ed75 Mon Sep 17 00:00:00 2001 From: york Date: Fri, 2 Jul 2010 22:25:59 +0000 Subject: powerpc/8xxx: Fix quad-rank DIMMs support on corenet_ds board. The board specific parameters associated with quad rank dimms where missing. This fixes it so the board will function if quad rank dimms are placed in it. Signed-off-by: York Sun Signed-off-by: Kumar Gala diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 82b2b4f..18adf2f 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -66,11 +66,19 @@ typedef struct { * seem reliable, but errors will appear when memory intensive * program is run. */ /* XXX: Single rank at 800 MHz is OK. */ -const board_specific_parameters_t board_specific_parameters[][20] = { +const board_specific_parameters_t board_specific_parameters[][30] = { { /* memory controller 0 */ /* lo| hi| num| clk| cpo|wrdata|2T */ /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 4, 6, 7, 3, 0}, + {334, 400, 4, 6, 9, 3, 0}, + {401, 549, 4, 6, 11, 3, 0}, + {550, 680, 4, 1, 10, 5, 0}, + {681, 850, 4, 1, 12, 5, 0}, + {851, 1050, 4, 1, 12, 5, 0}, + {1051, 1250, 4, 1, 15, 4, 0}, + {1251, 1350, 4, 1, 15, 4, 0}, { 0, 333, 2, 6, 7, 3, 0}, {334, 400, 2, 6, 9, 3, 0}, {401, 549, 2, 6, 11, 3, 0}, @@ -90,6 +98,14 @@ const board_specific_parameters_t board_specific_parameters[][20] = { /* memory controller 1 */ /* lo| hi| num| clk| cpo|wrdata|2T */ /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 4, 6, 7, 3, 0}, + {334, 400, 4, 6, 9, 3, 0}, + {401, 549, 4, 6, 11, 3, 0}, + {550, 680, 4, 1, 10, 5, 0}, + {681, 850, 4, 1, 12, 5, 0}, + {851, 1050, 4, 1, 12, 5, 0}, + {1051, 1250, 4, 1, 15, 4, 0}, + {1251, 1350, 4, 1, 15, 4, 0}, { 0, 333, 2, 6, 7, 3, 0}, {334, 400, 2, 6, 9, 3, 0}, {401, 549, 2, 6, 11, 3, 0}, diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index dd609da..3dcee85 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -124,7 +124,7 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD #define CONFIG_FSL_DDR3 -- cgit v0.10.2 From 0e159024ea0bc1c7ee2c31e98c5e45b08d42b4e7 Mon Sep 17 00:00:00 2001 From: Lian Minghuan Date: Wed, 18 Aug 2010 16:33:47 +0800 Subject: powerpc/85xx: Fix SRIO LAW setup on corenet_ds boards In function board_early_init_r(), serdes will not be initialize yet. Thus sRIO was always considered disabled. Move the check for sRIO into misc_init_r() which is called after fsl_serdes_init(). Also, fixed warning associated with gur variable possibly not being used. Signed-off-by: Roy Zang Signed-off-by: Lian Minghuan Signed-off-by: Kumar Gala diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 3cdefb3..48d95d6 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -120,28 +121,6 @@ int board_early_init_r(void) set_liodns(); setup_portals(); -#ifdef CONFIG_SRIO1 - if (is_serdes_configured(SRIO1)) { - set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_1); - } else { - printf (" SRIO1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ -#endif - -#ifdef CONFIG_SRIO2 - if (is_serdes_configured(SRIO2)) { - set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_2); - } else { - printf (" SRIO2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ -#endif - return 0; } @@ -164,10 +143,34 @@ static const char *serdes_clock_to_string(u32 clock) int misc_init_r(void) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + __maybe_unused ccsr_gur_t *gur; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw3; + gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_SRIO1 + if (is_serdes_configured(SRIO1)) { + set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_RIO_1); + } else { + printf (" SRIO1: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ +#endif + +#ifdef CONFIG_SRIO2 + if (is_serdes_configured(SRIO2)) { + set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_RIO_2); + } else { + printf (" SRIO2: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ +#endif + /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. -- cgit v0.10.2 From a2243b84bf5aa1f789a19e12f03849702d418986 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Aug 2010 01:48:14 -0500 Subject: powerpc/83xx: Fix build issue with ve8313 board due to lbus changes We get two build errors: fsl_elbc_nand.c: In function 'fsl_elbc_run_command': fsl_elbc_nand.c:231: error: 'fsl_lbc_t' has no member named 'lsor' make[1]: *** [/work/wd/tmp-ppc/drivers/mtd/nand/fsl_elbc_nand.o] Error 1 and ve8313.c: In function 'initdram': ve8313.c:104: error: expected '=', ',', ';', 'asm' or '__attribute__' before '*' token ve8313.c:104: error: 'lbc' undeclared (first use in this function) ve8313.c:104: error: (Each undeclared identifier is reported only once ve8313.c:104: error: for each function it appears in.) ve8313.c:104: error: 'immap_t' has no member named 'lbus' make[1]: *** [ve8313.o] Error 1 make: *** [board/ve8313/libve8313.a] Error 2 Due to changes to unifiy local bus struct definitions. Reported-by: Wolfgang Denk Signed-off-by: Kumar Gala diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index 8ba1b19..2272ff0 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -101,7 +101,7 @@ static long fixed_sdram(void) phys_size_t initdram(int board_type) { volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc = &im->lbus; + volatile fsl_lbc_t *lbc = &im->im_lbc; u32 msize; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 1589913..56d24f9 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -39,6 +39,7 @@ #define CONFIG_VE8313 1 #define CONFIG_PCI 1 +#define CONFIG_FSL_ELBC 1 #define CONFIG_BOARD_EARLY_INIT_F 1 -- cgit v0.10.2 From 62a05573822fc253a1ad5037482511347d6abaa5 Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Fri, 30 Jul 2010 14:12:12 +0800 Subject: nios2: fix bootm error on fdt args We should check argv[3] only if there are enough args. Otherwise, it might cause invalid memory access fault. Signed-off-by: Thomas Chou Signed-off-by: Scott McNutt diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index e25a113..40a4d15 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -42,7 +42,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima if (boot_get_fdt(flag, argc, argv, images, &of_flat_tree, &of_size)) return 1; #endif - if (!of_flat_tree) + if (!of_flat_tree && argc > 3) of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16); if (of_flat_tree) initrd_end = (ulong)of_flat_tree; -- cgit v0.10.2 From 7a6a7d10e6b96ab4a5c0d8852802ec52be2b582e Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Mon, 16 Aug 2010 10:49:44 +0800 Subject: nios2: fix out of reach case for do_reset There is a limitation (or bug?) of nios2 toolchain. The nios2 gcc didn't generate correct code when the reset vector is passed as a constant. It just generated a direct "call", which was wrong when the reset vector was not located in the same 256MB span as u-boot. The "Nios II Processor Reference Handbook" said, "call can transfer execution anywhere within the 256 MByte range determined by PC31..28. The Nios II GNU linker does not automatically handle cases in which the address is out of this range." So we have to use registered "callr" instruction to do the job. Signed-off-by: Thomas Chou Signed-off-by: Scott McNutt diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 6379534..d9c6544 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -40,11 +40,10 @@ int checkcpu (void) return (0); } - -int do_reset (void) +int do_reset(void) { - void (*rst)(void) = (void(*)(void))CONFIG_SYS_RESET_ADDR; - disable_interrupts (); - rst(); - return(0); + disable_interrupts(); + /* indirect call to go beyond 256MB limitation of toolchain */ + nios2_callr(CONFIG_SYS_RESET_ADDR); + return 0; } diff --git a/arch/nios2/include/asm/system.h b/arch/nios2/include/asm/system.h index bb03ca5..086d92b 100644 --- a/arch/nios2/include/asm/system.h +++ b/arch/nios2/include/asm/system.h @@ -56,4 +56,9 @@ ((flags & NIOS2_STATUS_PIE_MSK) == 0x0); \ }) +/* indirect call to go beyond 256MB limitation of toolchain */ +#define nios2_callr(addr) __asm__ __volatile__ ( \ + "callr %0" \ + : : "r" (addr)) + #endif /* __ASM_NIOS2_SYSTEM_H */ -- cgit v0.10.2 From b80d30546e88c70985094d81297d449b2bc59033 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Thu, 19 Aug 2010 13:57:48 -0500 Subject: mpx85xx/fdt: Add cpu-release-addr for all cores We currently do not add a cpu-release-addr for core 0, this is needed when we want to reset core 0 and later restart it from Linux Signed-off-by: Matthew McClintock Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 8e7b827..4540364 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -54,18 +54,19 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); if (reg) { + u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; + val = cpu_to_fdt32(val); if (*reg == id) { - fdt_setprop_string(blob, off, "status", "okay"); + fdt_setprop_string(blob, off, "status", + "okay"); } else { - u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; - val = cpu_to_fdt32(val); fdt_setprop_string(blob, off, "status", "disabled"); - fdt_setprop_string(blob, off, "enable-method", - "spin-table"); - fdt_setprop(blob, off, "cpu-release-addr", - &val, sizeof(val)); } + fdt_setprop_string(blob, off, "enable-method", + "spin-table"); + fdt_setprop(blob, off, "cpu-release-addr", + &val, sizeof(val)); } else { printf ("cpu NULL\n"); } -- cgit v0.10.2 From 6395f318e9ddf26817a01f0b3877af0e3e47d056 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Thu, 12 Aug 2010 18:37:39 -0500 Subject: fdt: call fdt_parent_offset fewer times while translating addresses fdt_parent_offset() is an expensive operation, so we'd like to reduce unnecessary calls to it. Further, the practice of iterating up to the root if address/size cells aren't found was apparently done for Linux for compatibility with certain buggy Open Firmware implementations, and U-Boot inherited the code. The compliant behavior is to treat a missing #address-cells as 2, and a missing #size-cells as 1 -- never looking anywhere but the immediate parent of the node of interest. Signed-off-by: Scott Wood Signed-off-by: Kumar Gala diff --git a/common/fdt_support.c b/common/fdt_support.c index 33336be..aef4fe2 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -874,35 +874,6 @@ static inline u64 of_read_number(const __be32 *cell, int size) return r; } -static int of_n_cells(const void *blob, int nodeoffset, const char *name) -{ - int np; - const int *ip; - - do { - np = fdt_parent_offset(blob, nodeoffset); - - if (np >= 0) - nodeoffset = np; - ip = (int *)fdt_getprop(blob, nodeoffset, name, NULL); - if (ip) - return be32_to_cpup(ip); - } while (np >= 0); - - /* No #-cells property for the root node */ - return 1; -} - -int of_n_addr_cells(const void *blob, int nodeoffset) -{ - return of_n_cells(blob, nodeoffset, "#address-cells"); -} - -int of_n_size_cells(const void *blob, int nodeoffset) -{ - return of_n_cells(blob, nodeoffset, "#size-cells"); -} - #define PRu64 "%llx" /* Max address size we deal with */ @@ -928,7 +899,7 @@ static void of_dump_addr(const char *s, const u32 *addr, int na) { } struct of_bus { const char *name; const char *addresses; - void (*count_cells)(void *blob, int offset, + void (*count_cells)(void *blob, int parentoffset, int *addrc, int *sizec); u64 (*map)(u32 *addr, const u32 *range, int na, int ns, int pna); @@ -936,13 +907,26 @@ struct of_bus { }; /* Default translator (generic bus) */ -static void of_bus_default_count_cells(void *blob, int offset, +static void of_bus_default_count_cells(void *blob, int parentoffset, int *addrc, int *sizec) { - if (addrc) - *addrc = of_n_addr_cells(blob, offset); - if (sizec) - *sizec = of_n_size_cells(blob, offset); + const u32 *prop; + + if (addrc) { + prop = fdt_getprop(blob, parentoffset, "#address-cells", NULL); + if (prop) + *addrc = be32_to_cpup(prop); + else + *addrc = 2; + } + + if (sizec) { + prop = fdt_getprop(blob, parentoffset, "#size-cells", NULL); + if (prop) + *sizec = be32_to_cpup(prop); + else + *sizec = 1; + } } static u64 of_bus_default_map(u32 *addr, const u32 *range, @@ -1068,7 +1052,7 @@ u64 __of_translate_address(void *blob, int node_offset, const u32 *in_addr, bus = &of_busses[0]; /* Cound address cells & copy address locally */ - bus->count_cells(blob, node_offset, &na, &ns); + bus->count_cells(blob, parent, &na, &ns); if (!OF_CHECK_COUNTS(na, ns)) { printf("%s: Bad cell count for %s\n", __FUNCTION__, fdt_get_name(blob, node_offset, NULL)); @@ -1095,7 +1079,7 @@ u64 __of_translate_address(void *blob, int node_offset, const u32 *in_addr, /* Get new parent bus and counts */ pbus = &of_busses[0]; - pbus->count_cells(blob, node_offset, &pna, &pns); + pbus->count_cells(blob, parent, &pna, &pns); if (!OF_CHECK_COUNTS(pna, pns)) { printf("%s: Bad cell count for %s\n", __FUNCTION__, fdt_get_name(blob, node_offset, NULL)); -- cgit v0.10.2 From 07cf5e207ecd7e82f08ec9f2d35d0df1dceaeadd Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 18 Aug 2010 19:39:07 -0500 Subject: i2c: omap2+: change header guard to be generic Make the header guard to be generic to stop conflicting with omap2 i2c header file arch/arm/include/asm/arch-omap24xx/i2c.h Cc: Steve Sakoman Cc: Heiko Cc: Sandeep Paulraj Cc: Wolfang Denk Signed-off-by: Nishanth Menon Acked-by: Steve Sakoman diff --git a/drivers/i2c/omap24xx_i2c.h b/drivers/i2c/omap24xx_i2c.h index 650e33a..1f38c23 100644 --- a/drivers/i2c/omap24xx_i2c.h +++ b/drivers/i2c/omap24xx_i2c.h @@ -20,8 +20,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef _OMAP24XX_I2C_H_ -#define _OMAP24XX_I2C_H_ +#ifndef _OMAP2PLUS_I2C_H_ +#define _OMAP2PLUS_I2C_H_ /* I2C masks */ -- cgit v0.10.2 From 46d8ece4e8fd2c4b92c99f7139332f49c368384e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 18 Aug 2010 19:39:08 -0500 Subject: omap2: i2c: add syss offset OMAP2420 ES2.3 trm defines syss register offset as 0x10. Add it. Cc: Steve Sakoman Cc: Heiko Cc: Sandeep Paulraj Cc: Wolfang Denk Signed-off-by: Nishanth Menon Acked-by: Steve Sakoman diff --git a/arch/arm/include/asm/arch-omap24xx/i2c.h b/arch/arm/include/asm/arch-omap24xx/i2c.h index 19046aa..418a432 100644 --- a/arch/arm/include/asm/arch-omap24xx/i2c.h +++ b/arch/arm/include/asm/arch-omap24xx/i2c.h @@ -36,7 +36,9 @@ struct i2c { unsigned short stat; /* 0x08 */ unsigned short res3; unsigned short iv; /* 0x0C */ - unsigned short res4[3]; + unsigned short res4; + unsigned short syss; /* 0x10 */ + unsigned short res4p1; unsigned short buf; /* 0x14 */ unsigned short res5; unsigned short cnt; /* 0x18 */ -- cgit v0.10.2 From a947f4b68b04fa73d8c862185b8cb7e61abda211 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 18 Aug 2010 19:39:09 -0500 Subject: omap2: i2c: remove redundant header definitions Remove the register offset and common defines which are already present in drivers/i2c/omap24xx.h. All of these defines carry the same value even. Cc: Steve Sakoman Cc: Heiko Cc: Sandeep Paulraj Cc: Wolfang Denk Signed-off-by: Nishanth Menon Acked-by: Steve Sakoman diff --git a/arch/arm/include/asm/arch-omap24xx/i2c.h b/arch/arm/include/asm/arch-omap24xx/i2c.h index 418a432..6f64519 100644 --- a/arch/arm/include/asm/arch-omap24xx/i2c.h +++ b/arch/arm/include/asm/arch-omap24xx/i2c.h @@ -65,110 +65,4 @@ struct i2c { #define I2C_BUS_MAX 2 -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ -#define I2C_IE_GC_IE (1 << 5) -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_GC (1 << 5) -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ - -/* I2C Buffer Configuration Register (I2C_BUF): */ - -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ - -/* I2C System Test Register (I2C_SYSTEST): */ - -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ - -/* These values were copied from omap3, include/asm-arm/arch-omap3/i2c.h. */ -#define OMAP_I2C_STANDARD 100000 -#define OMAP_I2C_FAST_MODE 400000 -#define OMAP_I2C_HIGH_SPEED 3400000 - -#define SYSTEM_CLOCK_12 12000000 -#define SYSTEM_CLOCK_13 13000000 -#define SYSTEM_CLOCK_192 19200000 -#define SYSTEM_CLOCK_96 96000000 - -#ifndef I2C_IP_CLK -#define I2C_IP_CLK SYSTEM_CLOCK_96 -#endif - -#ifndef I2C_INTERNAL_SAMPLING_CLK -#define I2C_INTERNAL_SAMPLING_CLK 19200000 -#endif - -/* These are the trim values for standard and fast speed */ -#ifndef I2C_FASTSPEED_SCLL_TRIM -#define I2C_FASTSPEED_SCLL_TRIM 6 -#endif -#ifndef I2C_FASTSPEED_SCLH_TRIM -#define I2C_FASTSPEED_SCLH_TRIM 6 -#endif - -/* These are the trim values for high speed */ -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM -#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM -#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM -#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM -#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM -#endif - -#define I2C_PSC_MAX 0x0f -#define I2C_PSC_MIN 0x00 - - #endif -- cgit v0.10.2 From 7a92e53cd0d8164d518216bebd52679603d6ffe9 Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Wed, 25 Aug 2010 14:41:16 +0200 Subject: CMD_I2C: make alen=0 work Signed-off-by: Reinhard Meyer diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 371e022..1283c82 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -152,7 +152,7 @@ int i2c_set_bus_speed(unsigned int) /* * get_alen: small parser helper function to get address length - * returns the address length,or 0 on error + * returns the address length */ static uint get_alen(char *arg) { @@ -163,9 +163,6 @@ static uint get_alen(char *arg) for (j = 0; j < 8; j++) { if (arg[j] == '.') { alen = arg[j+1] - '0'; - if (alen > 3) { - return 0; - } break; } else if (arg[j] == '\0') break; @@ -198,7 +195,7 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv */ devaddr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) + if (alen > 3) return cmd_usage(cmdtp); /* @@ -255,7 +252,7 @@ static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) + if (alen > 3) return cmd_usage(cmdtp); /* @@ -337,7 +334,7 @@ static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) + if (alen > 3) return cmd_usage(cmdtp); /* @@ -399,7 +396,7 @@ static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) + if (alen > 3) return cmd_usage(cmdtp); /* @@ -477,7 +474,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) + if (alen > 3) return cmd_usage(cmdtp); } @@ -621,7 +618,7 @@ static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) + if (alen > 3) return cmd_usage(cmdtp); /* -- cgit v0.10.2 From ed56fb1d775bb872c976eb6768a2cd739abea435 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Jul 2010 11:19:17 +0900 Subject: sh: Update lowlevel_init.S of rsk7203 Update data address size and fix typo of register. Signed-off-by: Nobuhiro Iwamatsu diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index 7b9ecd8..30ef5ab 100644 --- a/board/renesas/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -73,7 +73,7 @@ init_bsc_cs0: write32 CMNCR_A, CMNCR_D - write32 SC0BCR_A, SC0BCR_D + write32 CS0BCR_A, CS0BCR_D write32 CS0WCR_A, CS0WCR_D @@ -122,63 +122,82 @@ repeat0: CCR1_A: .long CCR1 CCR1_D: .long 0x0000090B PCCRL4_A: .long 0xFFFE3910 -PCCRL4_D0: .long 0x00000000 +PCCRL4_D0: .word 0x0000 +.align 2 PECRL4_A: .long 0xFFFE3A10 -PECRL4_D0: .long 0x00000000 +PECRL4_D0: .word 0x0000 +.align 2 PECRL3_A: .long 0xFFFE3A12 -PECRL3_D: .long 0x00000000 +PECRL3_D: .word 0x0000 +.align 2 PEIORL_A: .long 0xFFFE3A06 -PEIORL_D0: .long 0x00001C00 -PEIORL_D1: .long 0x00001C02 +PEIORL_D0: .word 0x1C00 +PEIORL_D1: .word 0x1C02 PCIORL_A: .long 0xFFFE3906 -PCIORL_D: .long 0x00004000 +PCIORL_D: .word 0x4000 +.align 2 PFCRH2_A: .long 0xFFFE3A8C -PFCRH2_D: .long 0x00000000 +PFCRH2_D: .word 0x0000 +.align 2 PFCRH3_A: .long 0xFFFE3A8A -PFCRH3_D: .long 0x00000000 +PFCRH3_D: .word 0x0000 +.align 2 PFCRH1_A: .long 0xFFFE3A8E -PFCRH1_D: .long 0x00000000 +PFCRH1_D: .word 0x0000 +.align 2 PFIORH_A: .long 0xFFFE3A84 -PFIORH_D: .long 0x00000729 +PFIORH_D: .word 0x0729 +.align 2 PECRL1_A: .long 0xFFFE3A16 -PECRL1_D0: .long 0x00000033 +PECRL1_D0: .word 0x0033 +.align 2 WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .long 0x0000A518 -WTCSR_D1: .long 0x0000A51D +WTCSR_D0: .word 0xA518 +WTCSR_D1: .word 0xA51D WTCNT_A: .long 0xFFFE0002 -WTCNT_D: .long 0x00005A84 +WTCNT_D: .word 0x5A84 +.align 2 FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .long 0x00000104 +FRQCR_D: .word 0x0104 +.align 2 -PCCRL4_D1: .long 0x00000010 -PECRL1_D1: .long 0x00000133 +PCCRL4_D1: .word 0x0010 +PECRL1_D1: .word 0x0133 CMNCR_A: .long 0xFFFC0000 CMNCR_D: .long 0x00001810 -SC0BCR_A: .long 0xFFFC0004 -SC0BCR_D: .long 0x10000400 +CS0BCR_A: .long 0xFFFC0004 +CS0BCR_D: .long 0x10000400 CS0WCR_A: .long 0xFFFC0028 CS0WCR_D: .long 0x00000B41 -PECRL4_D1: .long 0x00000100 +PECRL4_D1: .word 0x0100 +.align 2 CS1WCR_A: .long 0xFFFC002C CS1WCR_D: .long 0x00000B01 -PCCRL4_D2: .long 0x00000011 +PCCRL4_D2: .word 0x0011 +.align 2 PCCRL3_A: .long 0xFFFE3912 -PCCRL3_D: .long 0x00000011 +PCCRL3_D: .word 0x0011 +.align 2 PCCRL2_A: .long 0xFFFE3914 -PCCRL2_D: .long 0x00001111 +PCCRL2_D: .word 0x1111 +.align 2 PCCRL1_A: .long 0xFFFE3916 -PCCRL1_D: .long 0x00001010 +PCCRL1_D: .word 0x1010 PDCRL4_A: .long 0xFFFE3990 -PDCRL4_D: .long 0x00000011 +PDCRL4_D: .word 0x0011 +.align 2 PDCRL3_A: .long 0xFFFE3992 -PDCRL3_D: .long 0x00000011 +PDCRL3_D: .word 0x00011 +.align 2 PDCRL2_A: .long 0xFFFE3994 -PDCRL2_D: .long 0x00001111 +PDCRL2_D: .word 0x1111 +.align 2 PDCRL1_A: .long 0xFFFE3996 -PDCRL1_D: .long 0x00001000 +PDCRL1_D: .word 0x1000 +.align 2 CS3BCR_A: .long 0xFFFC0010 CS3BCR_D: .long 0x00004400 CS3WCR_A: .long 0xFFFC0034 @@ -190,13 +209,5 @@ RTCOR_D: .long 0xA55A0041 RTCSR_A: .long 0xFFFC0050 RTCSR_D: .long 0xa55a0010 -STBCR3_A: .long 0xFFFE0408 -STBCR3_D: .long 0x00000000 -STBCR4_A: .long 0xFFFE040C -STBCR4_D: .long 0x00000008 -STBCR5_A: .long 0xFFFE0410 -STBCR5_D: .long 0x00000000 -STBCR6_A: .long 0xFFFE0414 -STBCR6_D: .long 0x00000002 SDRAM_MODE: .long 0xFFFC5040 REPEAT_D: .long 0x00009C40 -- cgit v0.10.2 From 20962771fa0e7eac668245d7fc7a97d48e36d01b Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Jul 2010 15:14:35 +0900 Subject: sh: Update lowlevel_init.S of sh7785lcr Fix data size. Signed-off-by: Nobuhiro Iwamatsu diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S index 40d9b08..86f6783 100644 --- a/board/renesas/sh7785lcr/lowlevel_init.S +++ b/board/renesas/sh7785lcr/lowlevel_init.S @@ -68,22 +68,22 @@ lowlevel_init: wait_timer WAIT_200US /*------- GPIO -------*/ - write16 PACR_A, PACR_D - write16 PBCR_A, PBCR_D - write16 PCCR_A, PCCR_D - write16 PDCR_A, PDCR_D - write16 PECR_A, PECR_D - write16 PFCR_A, PFCR_D - write16 PGCR_A, PGCR_D + write16 PACR_A, PXCR_D + write16 PBCR_A, PXCR_D + write16 PCCR_A, PXCR_D + write16 PDCR_A, PXCR_D + write16 PECR_A, PXCR_D + write16 PFCR_A, PXCR_D + write16 PGCR_A, PXCR_D write16 PHCR_A, PHCR_D write16 PJCR_A, PJCR_D write16 PKCR_A, PKCR_D - write16 PLCR_A, PLCR_D + write16 PLCR_A, PXCR_D write16 PMCR_A, PMCR_D write16 PNCR_A, PNCR_D - write16 PPCR_A, PPCR_D - write16 PQCR_A, PQCR_D - write16 PRCR_A, PRCR_D + write16 PPCR_A, PXCR_D + write16 PQCR_A, PXCR_D + write16 PRCR_A, PXCR_D write8 PEPUPR_A, PEPUPR_D write8 PHPUPR_A, PHPUPR_D @@ -179,22 +179,14 @@ lbsc_end: .align 4 /*------- GPIO -------*/ -PACR_D: .long 0x0000 -PBCR_D: .long 0x0000 -PCCR_D: .long 0x0000 -PDCR_D: .long 0x0000 -PECR_D: .long 0x0000 -PFCR_D: .long 0x0000 -PGCR_D: .long 0x0000 -PHCR_D: .long 0x00c0 -PJCR_D: .long 0xc3fc -PKCR_D: .long 0x03ff -PLCR_D: .long 0x0000 -PMCR_D: .long 0xffff -PNCR_D: .long 0xf0c3 -PPCR_D: .long 0x0000 -PQCR_D: .long 0x0000 -PRCR_D: .long 0x0000 +/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */ +PXCR_D: .word 0x0000 + +PHCR_D: .word 0x00c0 +PJCR_D: .word 0xc3fc +PKCR_D: .word 0x03ff +PMCR_D: .word 0xffff +PNCR_D: .word 0xf0c3 PEPUPR_D: .long 0xff PHPUPR_D: .long 0x00 @@ -203,10 +195,10 @@ PKPUPR_D: .long 0x00 PLPUPR_D: .long 0x00 PMPUPR_D: .long 0xfc PNPUPR_D: .long 0x00 -PPUPR1_D: .long 0xffbf -PPUPR2_D: .long 0xff00 -P1MSELR_D: .long 0x3780 -P2MSELR_D: .long 0x0000 +PPUPR1_D: .word 0xffbf +PPUPR2_D: .word 0xff00 +P1MSELR_D: .word 0x3780 +P2MSELR_D: .word 0x0000 #define GPIO_BASE 0xffe70000 PACR_A: .long GPIO_BASE + 0x00 -- cgit v0.10.2 From e77ff552037a5eddaa2a38d6dd88f3707041f80b Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Jul 2010 15:22:10 +0900 Subject: sh: Update lowlevel_init.S of MigoR Fix data size. Signed-off-by: Nobuhiro Iwamatsu diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S index 0daf25a..d8b2bc7 100644 --- a/board/renesas/ap325rxa/lowlevel_init.S +++ b/board/renesas/ap325rxa/lowlevel_init.S @@ -119,15 +119,15 @@ lowlevel_init: DRVCRA_A: .long DRVCRA DRVCRB_A: .long DRVCRB -DRVCRA_D: .long 0x4555 -DRVCRB_D: .long 0x0005 +DRVCRA_D: .word 0x4555 +DRVCRB_D: .word 0x0005 RWTCSR_A: .long RWTCSR RWTCNT_A: .long RWTCNT FRQCR_A: .long FRQCR -RWTCSR_D1: .long 0xa507 -RWTCSR_D2: .long 0xa504 -RWTCNT_D: .long 0x5a00 +RWTCSR_D1: .word 0xa507 +RWTCSR_D2: .word 0xa504 +RWTCNT_D: .word 0x5a00 FRQCR_D: .long 0x0b04474a SBSC_SDCR_A: .long SBSC_SDCR -- cgit v0.10.2 From 3106732180c7f79109df5dfc633063a24dc41ea2 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Jul 2010 15:29:10 +0900 Subject: sh: Update lowlevel_init.S of sh7763rdp Fix data size. Signed-off-by: Nobuhiro Iwamatsu diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S index 3747bf6..5b18200 100644 --- a/board/renesas/sh7763rdp/lowlevel_init.S +++ b/board/renesas/sh7763rdp/lowlevel_init.S @@ -266,8 +266,8 @@ SDR4_D: .long 0x00000300 SDMR00308_D: .long 0x00000000 SDMR00B08_D: .long 0x00000000 SDMR02000_D: .long 0x00000000 -PSEL0_D: .long 0x00000001 -PSEL1_D: .long 0x00000244 +PSEL0_D: .word 0x00000001 +PSEL1_D: .word 0x00000244 SR_MASK_D: .long 0xEFFFFF0F WDTST_D: .long 0x5A000FFF WDTCSR_D: .long 0xA5000000 -- cgit v0.10.2 From 45c710dd40c00796244fb3df495a4282038ffd79 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Jul 2010 15:33:47 +0900 Subject: sh: Update lowlevel_init.S of espt-giga Fix data size. Signed-off-by: Nobuhiro Iwamatsu diff --git a/board/espt/lowlevel_init.S b/board/espt/lowlevel_init.S index 7f0686c..1a11eee 100644 --- a/board/espt/lowlevel_init.S +++ b/board/espt/lowlevel_init.S @@ -206,26 +206,31 @@ PKDR_A: .long 0xFFEF0034 /* GPIO Set data */ PADR_D: .long 0x00000000 -PACR_D: .long 0x00001400 +PACR_D: .word 0x1400 +.align 2 PBDR_D: .long 0x00000000 -PBCR_D: .long 0x0000555A +PBCR_D: .word 0x555A +.align 2 PCDR_D: .long 0x00000000 -PCCR_D: .long 0x00005555 +PCCR_D: .word 0x5555 +.align 2 PDDR_D: .long 0x00000000 -PDCR_D: .long 0x00000155 -PECR_D: .long 0x00000000 -PFCR_D: .long 0x00000000 -PGCR_D: .long 0x00000000 -PHCR_D: .long 0x00000000 -PICR_D: .long 0x00000800 +PDCR_D: .word 0x0155 +PECR_D: .word 0x0000 +PFCR_D: .word 0x0000 +PGCR_D: .word 0x0000 +PHCR_D: .word 0x0000 +PICR_D: .word 0x0800 PJDR_D: .long 0x00000006 -PJCR_D: .long 0x00005A57 +PJCR_D: .word 0x5A57 +.align 2 PKDR_D: .long 0x00000000 -PKCR_D: .long 0x0000FFF9 -PLCR_D: .long 0x0000C330 -PMCR_D: .long 0x0000FFFF -PNCR_D: .long 0x00000242 -POCR_D: .long 0x00000000 +PKCR_D: .word 0xFFF9 +.align 2 +PLCR_D: .word 0xC330 +PMCR_D: .word 0xFFFF +PNCR_D: .word 0x0242 +POCR_D: .word 0x0000 /* Pin Select */ PSEL0_A: .long 0xFFEF0070 @@ -233,11 +238,12 @@ PSEL1_A: .long 0xFFEF0072 PSEL2_A: .long 0xFFEF0074 PSEL3_A: .long 0xFFEF0076 PSEL4_A: .long 0xFFEF0078 -PSEL0_D: .long 0x0001 -PSEL1_D: .long 0x2400 -PSEL2_D: .long 0x0000 -PSEL3_D: .long 0x2421 -PSEL4_D: .long 0x0000 +PSEL0_D: .word 0x0001 +PSEL1_D: .word 0x2400 +PSEL2_D: .word 0x0000 +PSEL3_D: .word 0x2421 +PSEL4_D: .word 0x0000 +.align 2 MMSEL_A: .long 0xFE600020 BCR_A: .long 0xFF801000 -- cgit v0.10.2 From edb3205a8d3cbdf465942ec7f32976bd7289cbfa Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Jul 2010 15:41:49 +0900 Subject: sh: Update lowlevel_init.S of r2dplus Fix data size. Signed-off-by: Nobuhiro Iwamatsu diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index 76d3cfc..f3392f0 100644 --- a/board/renesas/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -94,11 +94,14 @@ WCR3_D: .long 0x07777707 LED_A: .long 0x04000036 /* LED Address */ LED_D: .long 0xFF /* LED Data */ RTCNT_A: .long RTCNT /* RTCNT Address */ -RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ +RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ +.align 2 RTCOR_A: .long RTCOR /* RTCOR Address */ -RTCOR_D: .long 0xA534 /* RTCOR Write Code */ +RTCOR_D: .word 0xA534 /* RTCOR Write Code */ +.align 2 RTCSR_A: .long RTCSR /* RTCSR Address */ -RTCSR_D: .long 0xA510 /* RTCSR Write Code */ +RTCSR_D: .word 0xA510 /* RTCSR Write Code */ +.align 2 SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ SDMR3_D0: .long 0x55 SDMR3_D1: .long 0x00 -- cgit v0.10.2 From 72d5cdb71ac53e60d8fb15fb50247b30edbbdc05 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Jul 2010 16:04:08 +0900 Subject: sh: Update lowlevel_init.S of ap325rxa Fix data size. Signed-off-by: Nobuhiro Iwamatsu diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S index d8b2bc7..04cfef1 100644 --- a/board/renesas/ap325rxa/lowlevel_init.S +++ b/board/renesas/ap325rxa/lowlevel_init.S @@ -128,6 +128,7 @@ FRQCR_A: .long FRQCR RWTCSR_D1: .word 0xa507 RWTCSR_D2: .word 0xa504 RWTCNT_D: .word 0x5a00 +.align 2 FRQCR_D: .long 0x0b04474a SBSC_SDCR_A: .long SBSC_SDCR -- cgit v0.10.2 From ebd0d062acdf4dcd26ee0e6a47e16032e1eba75b Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Jul 2010 16:05:32 +0900 Subject: sh: Add support do_bdinfo function SH did not support do_bdinfo fuction. This code based avr32 stuff. Signed-off-by: Nobuhiro Iwamatsu diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index fbe73f1..d43867f 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -348,6 +348,25 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#elif defined(CONFIG_SH) + +int do_bdinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + bd_t *bd = gd->bd; + print_num ("mem start ", (ulong)bd->bi_memstart); + print_lnum ("mem size ", (u64)bd->bi_memsize); + print_num ("flash start ", (ulong)bd->bi_flashstart); + print_num ("flash size ", (ulong)bd->bi_flashsize); + print_num ("flash offset ", (ulong)bd->bi_flashoffset); + +#if defined(CONFIG_CMD_NET) + print_eth(0); + printf ("ip_addr = %pI4\n", &bd->bi_ip_addr); +#endif + printf ("baudrate = %ld bps\n", (ulong)bd->bi_baudrate); + return 0; +} + #else #error "a case for this architecture does not exist!" #endif -- cgit v0.10.2 From fc0db1325af535cff3cd8783e8af6d0a6ad5379d Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Jul 2010 16:14:54 +0900 Subject: sh: Update lowlevel_init.S of ms7720se Fix data size. Signed-off-by: Nobuhiro Iwamatsu diff --git a/board/ms7720se/lowlevel_init.S b/board/ms7720se/lowlevel_init.S index 7593811..3df25b6 100644 --- a/board/ms7720se/lowlevel_init.S +++ b/board/ms7720se/lowlevel_init.S @@ -114,10 +114,10 @@ FRQCR_A: .long 0xA415FF80 /* FRQCR Address */ WTCNT_A: .long 0xA415FF84 WTCSR_A: .long 0xA415FF86 UCLKCR_A: .long 0xA40A0008 -FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */ -WTCNT_D: .long 0x5A00 -WTCSR_D: .long 0xA506 -UCLKCR_D: .long 0xA5C0 +FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */ +WTCNT_D: .word 0x5A00 +WTCSR_D: .word 0xA506 +UCLKCR_D: .word 0xA5C0 #define BSC_BASE 0xA4FD0000 CMNCR_A: .long BSC_BASE @@ -164,7 +164,8 @@ SDCR_D1: .long 0x00000011 RTCSR_D: .long 0xA55A0010 RTCNT_D: .long 0xA55A001F RTCOR_D: .long 0xA55A001F -SDMR3_D: .long 0x0000 +SDMR3_D: .word 0x0000 +.align 2 SDCR_D2: .long 0x00000811 #define PFC_BASE 0xA4050100 @@ -178,15 +179,16 @@ PTCR_A: .long PFC_BASE + 0x1E PVCR_A: .long PFC_BASE + 0x22 PSELA_A: .long PFC_BASE + 0x24 -PCCR_D: .long 0x0000 -PDCR_D: .long 0x0000 -PECR_D: .long 0x0000 -PGCR_D: .long 0x0000 -PHCR_D: .long 0x0000 -PPCR_D: .long 0x00AA -PTCR_D: .long 0x0280 -PVCR_D: .long 0x0000 -PSELA_D: .long 0x0000 +PCCR_D: .word 0x0000 +PDCR_D: .word 0x0000 +PECR_D: .word 0x0000 +PGCR_D: .word 0x0000 +PHCR_D: .word 0x0000 +PPCR_D: .word 0x00AA +PTCR_D: .word 0x0280 +PVCR_D: .word 0x0000 +PSELA_D: .word 0x0000 +.align 2 CCR_A: .long 0xFFFFFFEC !CCR_D: .long 0x0000000D -- cgit v0.10.2 From 339719373a784166b5e46903470cd1f3d6ed544d Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Jul 2010 16:18:22 +0900 Subject: sh: Update lowlevel_init.S of ms7750se Fix data size. Signed-off-by: Nobuhiro Iwamatsu diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S index 5e09a39..3041e64 100644 --- a/board/ms7750se/lowlevel_init.S +++ b/board/ms7750se/lowlevel_init.S @@ -120,13 +120,14 @@ CCR_D_DISABLE: .long 0x0808 FRQCR_A: .long FRQCR FRQCR_D: #ifdef CONFIG_CPU_TYPE_R - .long 0x00000e1a /* 12:3:3 */ + .word 0x0e1a /* 12:3:3 */ #else /* CONFIG_CPU_TYPE_R */ #ifdef CONFIG_GOOD_SESH4 - .long 0x00000e13 /* 6:2:1 */ + .word 0x00e13 /* 6:2:1 */ #else - .long 0x00000e23 /* 6:1:1 */ + .word 0x00e23 /* 6:1:1 */ #endif +.align 2 #endif /* CONFIG_CPU_TYPE_R */ BCR1_A: .long BCR1 @@ -140,15 +141,19 @@ WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ WCR3_A: .long WCR3 WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ RTCSR_A: .long RTCSR -RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */ +RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */ +.align 2 RTCNT_A: .long RTCNT -RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ +RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ +.align 2 RTCOR_A: .long RTCOR -RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */ +RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */ +.align 2 SDMR3_A: .long SDMR3_ADDRESS SDMR3_D: .long 0x00 MCR_A: .long MCR MCR_D1: .long MCR_D1_VALUE MCR_D2: .long MCR_D2_VALUE RFCR_A: .long RFCR -RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ +RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */ +.align 2 -- cgit v0.10.2 From 3594f1987cca0cb0ea3ad64c6364389950ff3d48 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Jul 2010 16:20:08 +0900 Subject: sh: Update lowlevel_init.S of mpr2 Fix data size. Signed-off-by: Nobuhiro Iwamatsu diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S index 5f02bd4..0f7a892 100644 --- a/board/mpr2/lowlevel_init.S +++ b/board/mpr2/lowlevel_init.S @@ -82,10 +82,10 @@ lowlevel_init: /* * PLL Settings */ -FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */ -WTCNT_D: .long 0x5A00 /* start counting at zero */ -WTCSR_D: .long 0xA507 /* divide by 4096 */ - +FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */ +WTCNT_D: .word 0x5A00 /* start counting at zero */ +WTCSR_D: .word 0xA507 /* divide by 4096 */ +.align 2 /* * Spansion S29GL256N11 @ 48 MHz */ -- cgit v0.10.2 From 2fefa2ae868d3508ff432ba73a0db53356035c71 Mon Sep 17 00:00:00 2001 From: Albert Aribaud Date: Fri, 27 Aug 2010 18:26:03 +0200 Subject: suen3: remove CONFIG_HARD_I2C and related defines These are not used on this board, which uses soft I2C instead. Signed-off-by: Albert Aribaud Acked-by: Prafulla Wadaskar Acked-by: Heiko Schocher diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 6519c90..1617e69 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -142,16 +142,8 @@ /* * I2C related stuff */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SOFT_I2C /* I2C bit-banged */ -#if defined(CONFIG_HARD_I2C) -#define CONFIG_I2C_KIRKWOOD -#define CONFIG_I2C_KW_REG_BASE KW_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - #define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */ #if defined(CONFIG_SOFT_I2C) #ifndef __ASSEMBLY__ -- cgit v0.10.2 From 01ec99d9693929fc56e630c10499b1bfce3e3693 Mon Sep 17 00:00:00 2001 From: Albert Aribaud Date: Fri, 27 Aug 2010 18:26:04 +0200 Subject: i2c: rename kirkwood_i2c to mvtwsi This driver is not kirkwood-specific and can also be used e.g. by orion5x. Rename to a SoC-neutral name. Signed-off-by: Albert Aribaud Acked-by: Prafulla Wadaskar Acked-by: Heiko Schocher diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index d2c2515..8921ff9 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -28,7 +28,7 @@ LIB := $(obj)libi2c.a COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o -COBJS-$(CONFIG_I2C_KIRKWOOD) += kirkwood_i2c.o +COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o diff --git a/drivers/i2c/kirkwood_i2c.c b/drivers/i2c/kirkwood_i2c.c deleted file mode 100644 index a4409be..0000000 --- a/drivers/i2c/kirkwood_i2c.c +++ /dev/null @@ -1,496 +0,0 @@ -/* - * Driver for the i2c controller on the Marvell line of host bridges - * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, Orion SoC family), - * and Kirkwood family. - * - * Based on: - * Author: Mark A. Greer - * 2005 (c) MontaVista, Software, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * ported from Linux to u-boot - * (C) Copyright 2009 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0; -#if defined(CONFIG_I2C_MUX) -static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0; -#endif - -/* Register defines */ -#define KW_I2C_REG_SLAVE_ADDR 0x00 -#define KW_I2C_REG_DATA 0x04 -#define KW_I2C_REG_CONTROL 0x08 -#define KW_I2C_REG_STATUS 0x0c -#define KW_I2C_REG_BAUD 0x0c -#define KW_I2C_REG_EXT_SLAVE_ADDR 0x10 -#define KW_I2C_REG_SOFT_RESET 0x1c - -#define KW_I2C_REG_CONTROL_ACK 0x00000004 -#define KW_I2C_REG_CONTROL_IFLG 0x00000008 -#define KW_I2C_REG_CONTROL_STOP 0x00000010 -#define KW_I2C_REG_CONTROL_START 0x00000020 -#define KW_I2C_REG_CONTROL_TWSIEN 0x00000040 -#define KW_I2C_REG_CONTROL_INTEN 0x00000080 - -/* Ctlr status values */ -#define KW_I2C_STATUS_BUS_ERR 0x00 -#define KW_I2C_STATUS_MAST_START 0x08 -#define KW_I2C_STATUS_MAST_REPEAT_START 0x10 -#define KW_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 -#define KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 -#define KW_I2C_STATUS_MAST_WR_ACK 0x28 -#define KW_I2C_STATUS_MAST_WR_NO_ACK 0x30 -#define KW_I2C_STATUS_MAST_LOST_ARB 0x38 -#define KW_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 -#define KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 -#define KW_I2C_STATUS_MAST_RD_DATA_ACK 0x50 -#define KW_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 -#define KW_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 -#define KW_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 -#define KW_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 -#define KW_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 -#define KW_I2C_STATUS_NO_STATUS 0xf8 - -/* Driver states */ -enum { - KW_I2C_STATE_INVALID, - KW_I2C_STATE_IDLE, - KW_I2C_STATE_WAITING_FOR_START_COND, - KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK, - KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK, - KW_I2C_STATE_WAITING_FOR_SLAVE_ACK, - KW_I2C_STATE_WAITING_FOR_SLAVE_DATA, -}; - -/* Driver actions */ -enum { - KW_I2C_ACTION_INVALID, - KW_I2C_ACTION_CONTINUE, - KW_I2C_ACTION_SEND_START, - KW_I2C_ACTION_SEND_ADDR_1, - KW_I2C_ACTION_SEND_ADDR_2, - KW_I2C_ACTION_SEND_DATA, - KW_I2C_ACTION_RCV_DATA, - KW_I2C_ACTION_RCV_DATA_STOP, - KW_I2C_ACTION_SEND_STOP, -}; - -/* defines to get compatible with Linux driver */ -#define IRQ_NONE 0x0 -#define IRQ_HANDLED 0x01 - -#define I2C_M_TEN 0x01 -#define I2C_M_RD 0x02 -#define I2C_M_REV_DIR_ADDR 0x04; - -struct i2c_msg { - u32 addr; - u32 flags; - u8 *buf; - u32 len; -}; - -struct kirkwood_i2c_data { - int irq; - u32 state; - u32 action; - u32 aborting; - u32 cntl_bits; - void *reg_base; - u32 reg_base_p; - u32 reg_size; - u32 addr1; - u32 addr2; - u32 bytes_left; - u32 byte_posn; - u32 block; - int rc; - u32 freq_m; - u32 freq_n; - struct i2c_msg *msg; -}; - -static struct kirkwood_i2c_data __drv_data __attribute__ ((section (".data"))); -static struct kirkwood_i2c_data *drv_data = &__drv_data; -static struct i2c_msg __i2c_msg __attribute__ ((section (".data"))); -static struct i2c_msg *kirkwood_i2c_msg = &__i2c_msg; - -/* - ***************************************************************************** - * - * Finite State Machine & Interrupt Routines - * - ***************************************************************************** - */ - -static inline int abs(int n) -{ - if(n >= 0) - return n; - else - return n * -1; -} - -static void kirkwood_calculate_speed(int speed) -{ - int calcspeed; - int diff; - int best_diff = CONFIG_SYS_TCLK; - int best_speed = 0; - int m, n; - int tmp[8] = {2, 4, 8, 16, 32, 64, 128, 256}; - - for (n = 0; n < 8; n++) { - for (m = 0; m < 16; m++) { - calcspeed = CONFIG_SYS_TCLK / (10 * (m + 1) * tmp[n]); - diff = abs((speed - calcspeed)); - if ( diff < best_diff) { - best_diff = diff; - best_speed = calcspeed; - drv_data->freq_m = m; - drv_data->freq_n = n; - } - } - } -} - -/* Reset hardware and initialize FSM */ -static void -kirkwood_i2c_hw_init(int speed, int slaveadd) -{ - drv_data->state = KW_I2C_STATE_IDLE; - - kirkwood_calculate_speed(speed); - writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SOFT_RESET); - writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)), - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_BAUD); - writel(slaveadd, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SLAVE_ADDR); - writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_EXT_SLAVE_ADDR); - writel(KW_I2C_REG_CONTROL_TWSIEN | KW_I2C_REG_CONTROL_STOP, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); -} - -static void -kirkwood_i2c_fsm(u32 status) -{ - /* - * If state is idle, then this is likely the remnants of an old - * operation that driver has given up on or the user has killed. - * If so, issue the stop condition and go to idle. - */ - if (drv_data->state == KW_I2C_STATE_IDLE) { - drv_data->action = KW_I2C_ACTION_SEND_STOP; - return; - } - - /* The status from the ctlr [mostly] tells us what to do next */ - switch (status) { - /* Start condition interrupt */ - case KW_I2C_STATUS_MAST_START: /* 0x08 */ - case KW_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */ - drv_data->action = KW_I2C_ACTION_SEND_ADDR_1; - drv_data->state = KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK; - break; - - /* Performing a write */ - case KW_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */ - if (drv_data->msg->flags & I2C_M_TEN) { - drv_data->action = KW_I2C_ACTION_SEND_ADDR_2; - drv_data->state = - KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK; - break; - } - /* FALLTHRU */ - case KW_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */ - case KW_I2C_STATUS_MAST_WR_ACK: /* 0x28 */ - if ((drv_data->bytes_left == 0) - || (drv_data->aborting - && (drv_data->byte_posn != 0))) { - drv_data->action = KW_I2C_ACTION_SEND_STOP; - drv_data->state = KW_I2C_STATE_IDLE; - } else { - drv_data->action = KW_I2C_ACTION_SEND_DATA; - drv_data->state = - KW_I2C_STATE_WAITING_FOR_SLAVE_ACK; - drv_data->bytes_left--; - } - break; - - /* Performing a read */ - case KW_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */ - if (drv_data->msg->flags & I2C_M_TEN) { - drv_data->action = KW_I2C_ACTION_SEND_ADDR_2; - drv_data->state = - KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK; - break; - } - /* FALLTHRU */ - case KW_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */ - if (drv_data->bytes_left == 0) { - drv_data->action = KW_I2C_ACTION_SEND_STOP; - drv_data->state = KW_I2C_STATE_IDLE; - break; - } - /* FALLTHRU */ - case KW_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */ - if (status != KW_I2C_STATUS_MAST_RD_DATA_ACK) - drv_data->action = KW_I2C_ACTION_CONTINUE; - else { - drv_data->action = KW_I2C_ACTION_RCV_DATA; - drv_data->bytes_left--; - } - drv_data->state = KW_I2C_STATE_WAITING_FOR_SLAVE_DATA; - - if ((drv_data->bytes_left == 1) || drv_data->aborting) - drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_ACK; - break; - - case KW_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */ - drv_data->action = KW_I2C_ACTION_RCV_DATA_STOP; - drv_data->state = KW_I2C_STATE_IDLE; - break; - - case KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ - case KW_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ - case KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ - /* Doesn't seem to be a device at other end */ - drv_data->action = KW_I2C_ACTION_SEND_STOP; - drv_data->state = KW_I2C_STATE_IDLE; - drv_data->rc = -ENODEV; - break; - - default: - printf("kirkwood_i2c_fsm: Ctlr Error -- state: 0x%x, " - "status: 0x%x, addr: 0x%x, flags: 0x%x\n", - drv_data->state, status, drv_data->msg->addr, - drv_data->msg->flags); - drv_data->action = KW_I2C_ACTION_SEND_STOP; - kirkwood_i2c_hw_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - drv_data->rc = -EIO; - } -} - -static void -kirkwood_i2c_do_action(void) -{ - switch(drv_data->action) { - case KW_I2C_ACTION_CONTINUE: - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_SEND_START: - writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_START, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_SEND_ADDR_1: - writel(drv_data->addr1, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_SEND_ADDR_2: - writel(drv_data->addr2, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_SEND_DATA: - writel(drv_data->msg->buf[drv_data->byte_posn++], - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_RCV_DATA: - drv_data->msg->buf[drv_data->byte_posn++] = - readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_RCV_DATA_STOP: - drv_data->msg->buf[drv_data->byte_posn++] = - readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN; - writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - drv_data->block = 0; - break; - - case KW_I2C_ACTION_INVALID: - default: - printf("kirkwood_i2c_do_action: Invalid action: %d\n", - drv_data->action); - drv_data->rc = -EIO; - /* FALLTHRU */ - case KW_I2C_ACTION_SEND_STOP: - drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN; - writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - drv_data->block = 0; - break; - } -} - -static int -kirkwood_i2c_intr(void) -{ - u32 status; - u32 ctrl; - int rc = IRQ_NONE; - - ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - while ((ctrl & KW_I2C_REG_CONTROL_IFLG) && - (drv_data->rc == 0)) { - status = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_STATUS); - kirkwood_i2c_fsm(status); - kirkwood_i2c_do_action(); - rc = IRQ_HANDLED; - ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - udelay(1000); - } - return rc; -} - -static void -kirkwood_i2c_doio(struct i2c_msg *msg) -{ - int ret; - - while ((drv_data->rc == 0) && (drv_data->state != KW_I2C_STATE_IDLE)) { - /* poll Status register */ - ret = kirkwood_i2c_intr(); - if (ret == IRQ_NONE) - udelay(10); - } -} - -static void -kirkwood_i2c_prepare_for_io(struct i2c_msg *msg) -{ - u32 dir = 0; - - drv_data->msg = msg; - drv_data->byte_posn = 0; - drv_data->bytes_left = msg->len; - drv_data->aborting = 0; - drv_data->rc = 0; - /* in u-boot we use no IRQs */ - drv_data->cntl_bits = KW_I2C_REG_CONTROL_ACK | KW_I2C_REG_CONTROL_TWSIEN; - - if (msg->flags & I2C_M_RD) - dir = 1; - if (msg->flags & I2C_M_TEN) { - drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; - drv_data->addr2 = (u32)msg->addr & 0xff; - } else { - drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir; - drv_data->addr2 = 0; - } - /* OK, no start it (from kirkwood_i2c_execute_msg())*/ - drv_data->action = KW_I2C_ACTION_SEND_START; - drv_data->state = KW_I2C_STATE_WAITING_FOR_START_COND; - drv_data->block = 1; - kirkwood_i2c_do_action(); -} - -void -i2c_init(int speed, int slaveadd) -{ - kirkwood_i2c_hw_init(speed, slaveadd); -} - -int -i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) -{ - kirkwood_i2c_msg->buf = data; - kirkwood_i2c_msg->len = length; - kirkwood_i2c_msg->addr = dev; - kirkwood_i2c_msg->flags = I2C_M_RD; - - kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg); - kirkwood_i2c_doio(kirkwood_i2c_msg); - return drv_data->rc; -} - -int -i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) -{ - kirkwood_i2c_msg->buf = data; - kirkwood_i2c_msg->len = length; - kirkwood_i2c_msg->addr = dev; - kirkwood_i2c_msg->flags = 0; - - kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg); - kirkwood_i2c_doio(kirkwood_i2c_msg); - return drv_data->rc; -} - -int -i2c_probe(uchar chip) -{ - return i2c_read(chip, 0, 0, NULL, 0); -} - -int i2c_set_bus_num(unsigned int bus) -{ -#if defined(CONFIG_I2C_MUX) - if (bus < CONFIG_SYS_MAX_I2C_BUS) { - i2c_bus_num = bus; - } else { - int ret; - - ret = i2x_mux_select_mux(bus); - if (ret) - return ret; - i2c_bus_num = 0; - } - i2c_bus_num_mux = bus; -#else - if (bus > 0) { - return -1; - } - - i2c_bus_num = bus; -#endif - return 0; -} - -unsigned int i2c_get_bus_num(void) -{ -#if defined(CONFIG_I2C_MUX) - return i2c_bus_num_mux; -#else - return i2c_bus_num; -#endif -} diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c new file mode 100644 index 0000000..a4409be --- /dev/null +++ b/drivers/i2c/mvtwsi.c @@ -0,0 +1,496 @@ +/* + * Driver for the i2c controller on the Marvell line of host bridges + * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, Orion SoC family), + * and Kirkwood family. + * + * Based on: + * Author: Mark A. Greer + * 2005 (c) MontaVista, Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * ported from Linux to u-boot + * (C) Copyright 2009 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + */ +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0; +#if defined(CONFIG_I2C_MUX) +static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0; +#endif + +/* Register defines */ +#define KW_I2C_REG_SLAVE_ADDR 0x00 +#define KW_I2C_REG_DATA 0x04 +#define KW_I2C_REG_CONTROL 0x08 +#define KW_I2C_REG_STATUS 0x0c +#define KW_I2C_REG_BAUD 0x0c +#define KW_I2C_REG_EXT_SLAVE_ADDR 0x10 +#define KW_I2C_REG_SOFT_RESET 0x1c + +#define KW_I2C_REG_CONTROL_ACK 0x00000004 +#define KW_I2C_REG_CONTROL_IFLG 0x00000008 +#define KW_I2C_REG_CONTROL_STOP 0x00000010 +#define KW_I2C_REG_CONTROL_START 0x00000020 +#define KW_I2C_REG_CONTROL_TWSIEN 0x00000040 +#define KW_I2C_REG_CONTROL_INTEN 0x00000080 + +/* Ctlr status values */ +#define KW_I2C_STATUS_BUS_ERR 0x00 +#define KW_I2C_STATUS_MAST_START 0x08 +#define KW_I2C_STATUS_MAST_REPEAT_START 0x10 +#define KW_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 +#define KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 +#define KW_I2C_STATUS_MAST_WR_ACK 0x28 +#define KW_I2C_STATUS_MAST_WR_NO_ACK 0x30 +#define KW_I2C_STATUS_MAST_LOST_ARB 0x38 +#define KW_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 +#define KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 +#define KW_I2C_STATUS_MAST_RD_DATA_ACK 0x50 +#define KW_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 +#define KW_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 +#define KW_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 +#define KW_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 +#define KW_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 +#define KW_I2C_STATUS_NO_STATUS 0xf8 + +/* Driver states */ +enum { + KW_I2C_STATE_INVALID, + KW_I2C_STATE_IDLE, + KW_I2C_STATE_WAITING_FOR_START_COND, + KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK, + KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK, + KW_I2C_STATE_WAITING_FOR_SLAVE_ACK, + KW_I2C_STATE_WAITING_FOR_SLAVE_DATA, +}; + +/* Driver actions */ +enum { + KW_I2C_ACTION_INVALID, + KW_I2C_ACTION_CONTINUE, + KW_I2C_ACTION_SEND_START, + KW_I2C_ACTION_SEND_ADDR_1, + KW_I2C_ACTION_SEND_ADDR_2, + KW_I2C_ACTION_SEND_DATA, + KW_I2C_ACTION_RCV_DATA, + KW_I2C_ACTION_RCV_DATA_STOP, + KW_I2C_ACTION_SEND_STOP, +}; + +/* defines to get compatible with Linux driver */ +#define IRQ_NONE 0x0 +#define IRQ_HANDLED 0x01 + +#define I2C_M_TEN 0x01 +#define I2C_M_RD 0x02 +#define I2C_M_REV_DIR_ADDR 0x04; + +struct i2c_msg { + u32 addr; + u32 flags; + u8 *buf; + u32 len; +}; + +struct kirkwood_i2c_data { + int irq; + u32 state; + u32 action; + u32 aborting; + u32 cntl_bits; + void *reg_base; + u32 reg_base_p; + u32 reg_size; + u32 addr1; + u32 addr2; + u32 bytes_left; + u32 byte_posn; + u32 block; + int rc; + u32 freq_m; + u32 freq_n; + struct i2c_msg *msg; +}; + +static struct kirkwood_i2c_data __drv_data __attribute__ ((section (".data"))); +static struct kirkwood_i2c_data *drv_data = &__drv_data; +static struct i2c_msg __i2c_msg __attribute__ ((section (".data"))); +static struct i2c_msg *kirkwood_i2c_msg = &__i2c_msg; + +/* + ***************************************************************************** + * + * Finite State Machine & Interrupt Routines + * + ***************************************************************************** + */ + +static inline int abs(int n) +{ + if(n >= 0) + return n; + else + return n * -1; +} + +static void kirkwood_calculate_speed(int speed) +{ + int calcspeed; + int diff; + int best_diff = CONFIG_SYS_TCLK; + int best_speed = 0; + int m, n; + int tmp[8] = {2, 4, 8, 16, 32, 64, 128, 256}; + + for (n = 0; n < 8; n++) { + for (m = 0; m < 16; m++) { + calcspeed = CONFIG_SYS_TCLK / (10 * (m + 1) * tmp[n]); + diff = abs((speed - calcspeed)); + if ( diff < best_diff) { + best_diff = diff; + best_speed = calcspeed; + drv_data->freq_m = m; + drv_data->freq_n = n; + } + } + } +} + +/* Reset hardware and initialize FSM */ +static void +kirkwood_i2c_hw_init(int speed, int slaveadd) +{ + drv_data->state = KW_I2C_STATE_IDLE; + + kirkwood_calculate_speed(speed); + writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SOFT_RESET); + writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)), + CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_BAUD); + writel(slaveadd, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SLAVE_ADDR); + writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_EXT_SLAVE_ADDR); + writel(KW_I2C_REG_CONTROL_TWSIEN | KW_I2C_REG_CONTROL_STOP, + CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); +} + +static void +kirkwood_i2c_fsm(u32 status) +{ + /* + * If state is idle, then this is likely the remnants of an old + * operation that driver has given up on or the user has killed. + * If so, issue the stop condition and go to idle. + */ + if (drv_data->state == KW_I2C_STATE_IDLE) { + drv_data->action = KW_I2C_ACTION_SEND_STOP; + return; + } + + /* The status from the ctlr [mostly] tells us what to do next */ + switch (status) { + /* Start condition interrupt */ + case KW_I2C_STATUS_MAST_START: /* 0x08 */ + case KW_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */ + drv_data->action = KW_I2C_ACTION_SEND_ADDR_1; + drv_data->state = KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK; + break; + + /* Performing a write */ + case KW_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */ + if (drv_data->msg->flags & I2C_M_TEN) { + drv_data->action = KW_I2C_ACTION_SEND_ADDR_2; + drv_data->state = + KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK; + break; + } + /* FALLTHRU */ + case KW_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */ + case KW_I2C_STATUS_MAST_WR_ACK: /* 0x28 */ + if ((drv_data->bytes_left == 0) + || (drv_data->aborting + && (drv_data->byte_posn != 0))) { + drv_data->action = KW_I2C_ACTION_SEND_STOP; + drv_data->state = KW_I2C_STATE_IDLE; + } else { + drv_data->action = KW_I2C_ACTION_SEND_DATA; + drv_data->state = + KW_I2C_STATE_WAITING_FOR_SLAVE_ACK; + drv_data->bytes_left--; + } + break; + + /* Performing a read */ + case KW_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */ + if (drv_data->msg->flags & I2C_M_TEN) { + drv_data->action = KW_I2C_ACTION_SEND_ADDR_2; + drv_data->state = + KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK; + break; + } + /* FALLTHRU */ + case KW_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */ + if (drv_data->bytes_left == 0) { + drv_data->action = KW_I2C_ACTION_SEND_STOP; + drv_data->state = KW_I2C_STATE_IDLE; + break; + } + /* FALLTHRU */ + case KW_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */ + if (status != KW_I2C_STATUS_MAST_RD_DATA_ACK) + drv_data->action = KW_I2C_ACTION_CONTINUE; + else { + drv_data->action = KW_I2C_ACTION_RCV_DATA; + drv_data->bytes_left--; + } + drv_data->state = KW_I2C_STATE_WAITING_FOR_SLAVE_DATA; + + if ((drv_data->bytes_left == 1) || drv_data->aborting) + drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_ACK; + break; + + case KW_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */ + drv_data->action = KW_I2C_ACTION_RCV_DATA_STOP; + drv_data->state = KW_I2C_STATE_IDLE; + break; + + case KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ + case KW_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ + case KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ + /* Doesn't seem to be a device at other end */ + drv_data->action = KW_I2C_ACTION_SEND_STOP; + drv_data->state = KW_I2C_STATE_IDLE; + drv_data->rc = -ENODEV; + break; + + default: + printf("kirkwood_i2c_fsm: Ctlr Error -- state: 0x%x, " + "status: 0x%x, addr: 0x%x, flags: 0x%x\n", + drv_data->state, status, drv_data->msg->addr, + drv_data->msg->flags); + drv_data->action = KW_I2C_ACTION_SEND_STOP; + kirkwood_i2c_hw_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + drv_data->rc = -EIO; + } +} + +static void +kirkwood_i2c_do_action(void) +{ + switch(drv_data->action) { + case KW_I2C_ACTION_CONTINUE: + writel(drv_data->cntl_bits, + CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); + break; + + case KW_I2C_ACTION_SEND_START: + writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_START, + CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); + break; + + case KW_I2C_ACTION_SEND_ADDR_1: + writel(drv_data->addr1, + CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); + writel(drv_data->cntl_bits, + CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); + break; + + case KW_I2C_ACTION_SEND_ADDR_2: + writel(drv_data->addr2, + CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); + writel(drv_data->cntl_bits, + CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); + break; + + case KW_I2C_ACTION_SEND_DATA: + writel(drv_data->msg->buf[drv_data->byte_posn++], + CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); + writel(drv_data->cntl_bits, + CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); + break; + + case KW_I2C_ACTION_RCV_DATA: + drv_data->msg->buf[drv_data->byte_posn++] = + readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); + writel(drv_data->cntl_bits, + CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); + break; + + case KW_I2C_ACTION_RCV_DATA_STOP: + drv_data->msg->buf[drv_data->byte_posn++] = + readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); + drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN; + writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP, + CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); + drv_data->block = 0; + break; + + case KW_I2C_ACTION_INVALID: + default: + printf("kirkwood_i2c_do_action: Invalid action: %d\n", + drv_data->action); + drv_data->rc = -EIO; + /* FALLTHRU */ + case KW_I2C_ACTION_SEND_STOP: + drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN; + writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP, + CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); + drv_data->block = 0; + break; + } +} + +static int +kirkwood_i2c_intr(void) +{ + u32 status; + u32 ctrl; + int rc = IRQ_NONE; + + ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); + while ((ctrl & KW_I2C_REG_CONTROL_IFLG) && + (drv_data->rc == 0)) { + status = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_STATUS); + kirkwood_i2c_fsm(status); + kirkwood_i2c_do_action(); + rc = IRQ_HANDLED; + ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); + udelay(1000); + } + return rc; +} + +static void +kirkwood_i2c_doio(struct i2c_msg *msg) +{ + int ret; + + while ((drv_data->rc == 0) && (drv_data->state != KW_I2C_STATE_IDLE)) { + /* poll Status register */ + ret = kirkwood_i2c_intr(); + if (ret == IRQ_NONE) + udelay(10); + } +} + +static void +kirkwood_i2c_prepare_for_io(struct i2c_msg *msg) +{ + u32 dir = 0; + + drv_data->msg = msg; + drv_data->byte_posn = 0; + drv_data->bytes_left = msg->len; + drv_data->aborting = 0; + drv_data->rc = 0; + /* in u-boot we use no IRQs */ + drv_data->cntl_bits = KW_I2C_REG_CONTROL_ACK | KW_I2C_REG_CONTROL_TWSIEN; + + if (msg->flags & I2C_M_RD) + dir = 1; + if (msg->flags & I2C_M_TEN) { + drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; + drv_data->addr2 = (u32)msg->addr & 0xff; + } else { + drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir; + drv_data->addr2 = 0; + } + /* OK, no start it (from kirkwood_i2c_execute_msg())*/ + drv_data->action = KW_I2C_ACTION_SEND_START; + drv_data->state = KW_I2C_STATE_WAITING_FOR_START_COND; + drv_data->block = 1; + kirkwood_i2c_do_action(); +} + +void +i2c_init(int speed, int slaveadd) +{ + kirkwood_i2c_hw_init(speed, slaveadd); +} + +int +i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) +{ + kirkwood_i2c_msg->buf = data; + kirkwood_i2c_msg->len = length; + kirkwood_i2c_msg->addr = dev; + kirkwood_i2c_msg->flags = I2C_M_RD; + + kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg); + kirkwood_i2c_doio(kirkwood_i2c_msg); + return drv_data->rc; +} + +int +i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) +{ + kirkwood_i2c_msg->buf = data; + kirkwood_i2c_msg->len = length; + kirkwood_i2c_msg->addr = dev; + kirkwood_i2c_msg->flags = 0; + + kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg); + kirkwood_i2c_doio(kirkwood_i2c_msg); + return drv_data->rc; +} + +int +i2c_probe(uchar chip) +{ + return i2c_read(chip, 0, 0, NULL, 0); +} + +int i2c_set_bus_num(unsigned int bus) +{ +#if defined(CONFIG_I2C_MUX) + if (bus < CONFIG_SYS_MAX_I2C_BUS) { + i2c_bus_num = bus; + } else { + int ret; + + ret = i2x_mux_select_mux(bus); + if (ret) + return ret; + i2c_bus_num = 0; + } + i2c_bus_num_mux = bus; +#else + if (bus > 0) { + return -1; + } + + i2c_bus_num = bus; +#endif + return 0; +} + +unsigned int i2c_get_bus_num(void) +{ +#if defined(CONFIG_I2C_MUX) + return i2c_bus_num_mux; +#else + return i2c_bus_num; +#endif +} -- cgit v0.10.2 From 306563a773f1111c6beff8d1855d5b2a2137aebd Mon Sep 17 00:00:00 2001 From: Albert Aribaud Date: Fri, 27 Aug 2010 18:26:05 +0200 Subject: i2c: rewrite mvtwsi, support orion5x and kirkwood This rewrite of the mvtwsi driver is 25% smaller and much faster and simpler than the previous code. Signed-off-by: Albert Aribaud Acked-by: Prafulla Wadaskar Acked-by: Heiko Schocher diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index a4409be..16a536f 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -1,11 +1,9 @@ /* - * Driver for the i2c controller on the Marvell line of host bridges - * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, Orion SoC family), - * and Kirkwood family. + * Driver for the TWSI (i2c) controller found on the Marvell + * orion5x and kirkwood SoC families. * - * Based on: - * Author: Mark A. Greer - * 2005 (c) MontaVista, Software, Inc. + * Author: Albert Aribaud + * Copyright (c) 2010 Albert Aribaud. * * See file CREDITS for list of people who contributed to this * project. @@ -24,473 +22,407 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, * MA 02110-1301 USA - * - * ported from Linux to u-boot - * (C) Copyright 2009 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ + #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; +/* + * include a file that will provide CONFIG_I2C_MVTWSI_BASE + * and possibly other settings + */ -static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0; -#if defined(CONFIG_I2C_MUX) -static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0; +#if defined(CONFIG_ORION5X) +#include +#elif defined(CONFIG_KIRKWOOD) +#include +#else +#error Driver mvtwsi not supported by SoC or board #endif -/* Register defines */ -#define KW_I2C_REG_SLAVE_ADDR 0x00 -#define KW_I2C_REG_DATA 0x04 -#define KW_I2C_REG_CONTROL 0x08 -#define KW_I2C_REG_STATUS 0x0c -#define KW_I2C_REG_BAUD 0x0c -#define KW_I2C_REG_EXT_SLAVE_ADDR 0x10 -#define KW_I2C_REG_SOFT_RESET 0x1c - -#define KW_I2C_REG_CONTROL_ACK 0x00000004 -#define KW_I2C_REG_CONTROL_IFLG 0x00000008 -#define KW_I2C_REG_CONTROL_STOP 0x00000010 -#define KW_I2C_REG_CONTROL_START 0x00000020 -#define KW_I2C_REG_CONTROL_TWSIEN 0x00000040 -#define KW_I2C_REG_CONTROL_INTEN 0x00000080 - -/* Ctlr status values */ -#define KW_I2C_STATUS_BUS_ERR 0x00 -#define KW_I2C_STATUS_MAST_START 0x08 -#define KW_I2C_STATUS_MAST_REPEAT_START 0x10 -#define KW_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 -#define KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 -#define KW_I2C_STATUS_MAST_WR_ACK 0x28 -#define KW_I2C_STATUS_MAST_WR_NO_ACK 0x30 -#define KW_I2C_STATUS_MAST_LOST_ARB 0x38 -#define KW_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 -#define KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 -#define KW_I2C_STATUS_MAST_RD_DATA_ACK 0x50 -#define KW_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 -#define KW_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 -#define KW_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 -#define KW_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 -#define KW_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 -#define KW_I2C_STATUS_NO_STATUS 0xf8 - -/* Driver states */ -enum { - KW_I2C_STATE_INVALID, - KW_I2C_STATE_IDLE, - KW_I2C_STATE_WAITING_FOR_START_COND, - KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK, - KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK, - KW_I2C_STATE_WAITING_FOR_SLAVE_ACK, - KW_I2C_STATE_WAITING_FOR_SLAVE_DATA, -}; +/* + * TWSI register structure + */ -/* Driver actions */ -enum { - KW_I2C_ACTION_INVALID, - KW_I2C_ACTION_CONTINUE, - KW_I2C_ACTION_SEND_START, - KW_I2C_ACTION_SEND_ADDR_1, - KW_I2C_ACTION_SEND_ADDR_2, - KW_I2C_ACTION_SEND_DATA, - KW_I2C_ACTION_RCV_DATA, - KW_I2C_ACTION_RCV_DATA_STOP, - KW_I2C_ACTION_SEND_STOP, +struct mvtwsi_registers { + u32 slave_address; + u32 data; + u32 control; + union { + u32 status; /* when reading */ + u32 baudrate; /* when writing */ + }; + u32 xtnd_slave_addr; + u32 reserved[2]; + u32 soft_reset; }; -/* defines to get compatible with Linux driver */ -#define IRQ_NONE 0x0 -#define IRQ_HANDLED 0x01 +/* + * Control register fields + */ -#define I2C_M_TEN 0x01 -#define I2C_M_RD 0x02 -#define I2C_M_REV_DIR_ADDR 0x04; +#define MVTWSI_CONTROL_ACK 0x00000004 +#define MVTWSI_CONTROL_IFLG 0x00000008 +#define MVTWSI_CONTROL_STOP 0x00000010 +#define MVTWSI_CONTROL_START 0x00000020 +#define MVTWSI_CONTROL_TWSIEN 0x00000040 +#define MVTWSI_CONTROL_INTEN 0x00000080 -struct i2c_msg { - u32 addr; - u32 flags; - u8 *buf; - u32 len; -}; +/* + * Status register values -- only those expected in normal master + * operation on non-10-bit-address devices; whatever status we don't + * expect in nominal conditions (bus errors, arbitration losses, + * missing ACKs...) we just pass back to the caller as an error + * code. + */ -struct kirkwood_i2c_data { - int irq; - u32 state; - u32 action; - u32 aborting; - u32 cntl_bits; - void *reg_base; - u32 reg_base_p; - u32 reg_size; - u32 addr1; - u32 addr2; - u32 bytes_left; - u32 byte_posn; - u32 block; - int rc; - u32 freq_m; - u32 freq_n; - struct i2c_msg *msg; -}; +#define MVTWSI_STATUS_START 0x08 +#define MVTWSI_STATUS_REPEATED_START 0x10 +#define MVTWSI_STATUS_ADDR_W_ACK 0x18 +#define MVTWSI_STATUS_DATA_W_ACK 0x28 +#define MVTWSI_STATUS_ADDR_R_ACK 0x40 +#define MVTWSI_STATUS_ADDR_R_NAK 0x48 +#define MVTWSI_STATUS_DATA_R_ACK 0x50 +#define MVTWSI_STATUS_DATA_R_NAK 0x58 +#define MVTWSI_STATUS_IDLE 0xF8 + +/* + * The single instance of the controller we'll be dealing with + */ -static struct kirkwood_i2c_data __drv_data __attribute__ ((section (".data"))); -static struct kirkwood_i2c_data *drv_data = &__drv_data; -static struct i2c_msg __i2c_msg __attribute__ ((section (".data"))); -static struct i2c_msg *kirkwood_i2c_msg = &__i2c_msg; +static struct mvtwsi_registers *twsi = + (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE; /* - ***************************************************************************** - * - * Finite State Machine & Interrupt Routines - * - ***************************************************************************** + * Returned statuses are 0 for success and nonzero otherwise. + * Currently, cmd_i2c and cmd_eeprom do not interpret an error status. + * Thus to ease debugging, the return status contains some debug info: + * - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'. + * - bits 23..16 are the last value of the control register. + * - bits 15..8 are the last value of the status register. + * - bits 7..0 are the expected value of the status register. */ -static inline int abs(int n) -{ - if(n >= 0) - return n; - else - return n * -1; -} +#define MVTWSI_ERROR_WRONG_STATUS 0x01 +#define MVTWSI_ERROR_TIMEOUT 0x02 -static void kirkwood_calculate_speed(int speed) -{ - int calcspeed; - int diff; - int best_diff = CONFIG_SYS_TCLK; - int best_speed = 0; - int m, n; - int tmp[8] = {2, 4, 8, 16, 32, 64, 128, 256}; +#define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) | \ + ((lc << 16) & 0x00FF0000) | ((ls<<8) & 0x0000FF00) | (es & 0xFF)) - for (n = 0; n < 8; n++) { - for (m = 0; m < 16; m++) { - calcspeed = CONFIG_SYS_TCLK / (10 * (m + 1) * tmp[n]); - diff = abs((speed - calcspeed)); - if ( diff < best_diff) { - best_diff = diff; - best_speed = calcspeed; - drv_data->freq_m = m; - drv_data->freq_n = n; - } +/* + * Wait for IFLG to raise, or return 'timeout'; then if status is as expected, + * return 0 (ok) or return 'wrong status'. + */ +static int twsi_wait(int expected_status) +{ + int control, status; + int timeout = 1000; + + do { + control = readl(&twsi->control); + if (control & MVTWSI_CONTROL_IFLG) { + status = readl(&twsi->status); + if (status == expected_status) + return 0; + else + return MVTWSI_ERROR( + MVTWSI_ERROR_WRONG_STATUS, + control, status, expected_status); } - } + udelay(10); /* one clock cycle at 100 kHz */ + } while (timeout--); + status = readl(&twsi->status); + return MVTWSI_ERROR( + MVTWSI_ERROR_TIMEOUT, control, status, expected_status); } -/* Reset hardware and initialize FSM */ -static void -kirkwood_i2c_hw_init(int speed, int slaveadd) +/* + * These flags are ORed to any write to the control register + * They allow global setting of TWSIEN and ACK. + * By default none are set. + * twsi_start() sets TWSIEN (in case the controller was disabled) + * twsi_recv() sets ACK or resets it depending on expected status. + */ +static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN; + +/* + * Assert the START condition, either in a single I2C transaction + * or inside back-to-back ones (repeated starts). + */ +static int twsi_start(int expected_status) { - drv_data->state = KW_I2C_STATE_IDLE; - - kirkwood_calculate_speed(speed); - writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SOFT_RESET); - writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)), - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_BAUD); - writel(slaveadd, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SLAVE_ADDR); - writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_EXT_SLAVE_ADDR); - writel(KW_I2C_REG_CONTROL_TWSIEN | KW_I2C_REG_CONTROL_STOP, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); + /* globally set TWSIEN in case it was not */ + twsi_control_flags |= MVTWSI_CONTROL_TWSIEN; + /* assert START */ + writel(twsi_control_flags | MVTWSI_CONTROL_START, &twsi->control); + /* wait for controller to process START */ + return twsi_wait(expected_status); } -static void -kirkwood_i2c_fsm(u32 status) +/* + * Send a byte (i2c address or data). + */ +static int twsi_send(u8 byte, int expected_status) { - /* - * If state is idle, then this is likely the remnants of an old - * operation that driver has given up on or the user has killed. - * If so, issue the stop condition and go to idle. - */ - if (drv_data->state == KW_I2C_STATE_IDLE) { - drv_data->action = KW_I2C_ACTION_SEND_STOP; - return; - } - - /* The status from the ctlr [mostly] tells us what to do next */ - switch (status) { - /* Start condition interrupt */ - case KW_I2C_STATUS_MAST_START: /* 0x08 */ - case KW_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */ - drv_data->action = KW_I2C_ACTION_SEND_ADDR_1; - drv_data->state = KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK; - break; - - /* Performing a write */ - case KW_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */ - if (drv_data->msg->flags & I2C_M_TEN) { - drv_data->action = KW_I2C_ACTION_SEND_ADDR_2; - drv_data->state = - KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK; - break; - } - /* FALLTHRU */ - case KW_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */ - case KW_I2C_STATUS_MAST_WR_ACK: /* 0x28 */ - if ((drv_data->bytes_left == 0) - || (drv_data->aborting - && (drv_data->byte_posn != 0))) { - drv_data->action = KW_I2C_ACTION_SEND_STOP; - drv_data->state = KW_I2C_STATE_IDLE; - } else { - drv_data->action = KW_I2C_ACTION_SEND_DATA; - drv_data->state = - KW_I2C_STATE_WAITING_FOR_SLAVE_ACK; - drv_data->bytes_left--; - } - break; - - /* Performing a read */ - case KW_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */ - if (drv_data->msg->flags & I2C_M_TEN) { - drv_data->action = KW_I2C_ACTION_SEND_ADDR_2; - drv_data->state = - KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK; - break; - } - /* FALLTHRU */ - case KW_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */ - if (drv_data->bytes_left == 0) { - drv_data->action = KW_I2C_ACTION_SEND_STOP; - drv_data->state = KW_I2C_STATE_IDLE; - break; - } - /* FALLTHRU */ - case KW_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */ - if (status != KW_I2C_STATUS_MAST_RD_DATA_ACK) - drv_data->action = KW_I2C_ACTION_CONTINUE; - else { - drv_data->action = KW_I2C_ACTION_RCV_DATA; - drv_data->bytes_left--; - } - drv_data->state = KW_I2C_STATE_WAITING_FOR_SLAVE_DATA; - - if ((drv_data->bytes_left == 1) || drv_data->aborting) - drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_ACK; - break; - - case KW_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */ - drv_data->action = KW_I2C_ACTION_RCV_DATA_STOP; - drv_data->state = KW_I2C_STATE_IDLE; - break; - - case KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ - case KW_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ - case KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ - /* Doesn't seem to be a device at other end */ - drv_data->action = KW_I2C_ACTION_SEND_STOP; - drv_data->state = KW_I2C_STATE_IDLE; - drv_data->rc = -ENODEV; - break; - - default: - printf("kirkwood_i2c_fsm: Ctlr Error -- state: 0x%x, " - "status: 0x%x, addr: 0x%x, flags: 0x%x\n", - drv_data->state, status, drv_data->msg->addr, - drv_data->msg->flags); - drv_data->action = KW_I2C_ACTION_SEND_STOP; - kirkwood_i2c_hw_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - drv_data->rc = -EIO; - } + /* put byte in data register for sending */ + writel(byte, &twsi->data); + /* clear any pending interrupt -- that'll cause sending */ + writel(twsi_control_flags, &twsi->control); + /* wait for controller to receive byte and check ACK */ + return twsi_wait(expected_status); } -static void -kirkwood_i2c_do_action(void) +/* + * Receive a byte. + * Global mvtwsi_control_flags variable says if we should ack or nak. + */ +static int twsi_recv(u8 *byte) { - switch(drv_data->action) { - case KW_I2C_ACTION_CONTINUE: - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_SEND_START: - writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_START, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_SEND_ADDR_1: - writel(drv_data->addr1, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_SEND_ADDR_2: - writel(drv_data->addr2, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_SEND_DATA: - writel(drv_data->msg->buf[drv_data->byte_posn++], - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_RCV_DATA: - drv_data->msg->buf[drv_data->byte_posn++] = - readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_RCV_DATA_STOP: - drv_data->msg->buf[drv_data->byte_posn++] = - readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN; - writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - drv_data->block = 0; - break; - - case KW_I2C_ACTION_INVALID: - default: - printf("kirkwood_i2c_do_action: Invalid action: %d\n", - drv_data->action); - drv_data->rc = -EIO; - /* FALLTHRU */ - case KW_I2C_ACTION_SEND_STOP: - drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN; - writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - drv_data->block = 0; - break; - } + int expected_status, status; + + /* compute expected status based on ACK bit in global control flags */ + if (twsi_control_flags & MVTWSI_CONTROL_ACK) + expected_status = MVTWSI_STATUS_DATA_R_ACK; + else + expected_status = MVTWSI_STATUS_DATA_R_NAK; + /* acknowledge *previous state* and launch receive */ + writel(twsi_control_flags, &twsi->control); + /* wait for controller to receive byte and assert ACK or NAK */ + status = twsi_wait(expected_status); + /* if we did receive expected byte then store it */ + if (status == 0) + *byte = readl(&twsi->data); + /* return status */ + return status; } -static int -kirkwood_i2c_intr(void) +/* + * Assert the STOP condition. + * This is also used to force the bus back in idle (SDA=SCL=1). + */ +static int twsi_stop(int status) { - u32 status; - u32 ctrl; - int rc = IRQ_NONE; - - ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - while ((ctrl & KW_I2C_REG_CONTROL_IFLG) && - (drv_data->rc == 0)) { - status = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_STATUS); - kirkwood_i2c_fsm(status); - kirkwood_i2c_do_action(); - rc = IRQ_HANDLED; - ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - udelay(1000); - } - return rc; + int control, stop_status; + int timeout = 1000; + + /* assert STOP */ + control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP; + writel(control, &twsi->control); + /* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */ + do { + stop_status = readl(&twsi->status); + if (stop_status == MVTWSI_STATUS_IDLE) + break; + udelay(10); /* one clock cycle at 100 kHz */ + } while (timeout--); + control = readl(&twsi->control); + if (stop_status != MVTWSI_STATUS_IDLE) + if (status == 0) + status = MVTWSI_ERROR( + MVTWSI_ERROR_TIMEOUT, + control, status, MVTWSI_STATUS_IDLE); + return status; } -static void -kirkwood_i2c_doio(struct i2c_msg *msg) -{ - int ret; +/* + * Ugly formula to convert m and n values to a frequency comes from + * TWSI specifications + */ - while ((drv_data->rc == 0) && (drv_data->state != KW_I2C_STATE_IDLE)) { - /* poll Status register */ - ret = kirkwood_i2c_intr(); - if (ret == IRQ_NONE) - udelay(10); - } +#define TWSI_FREQUENCY(m, n) \ + ((u8) (CONFIG_SYS_TCLK / (10 * (m + 1) * 2 * (1 << n)))) + +/* + * These are required to be reprogrammed before enabling the controller + * because a reset loses them. + * Default values come from the spec, but a twsi_reset will change them. + * twsi_slave_address left uninitialized lest checkpatch.pl complains. + */ + +/* Baudrate generator: m (bits 7..4) =4, n (bits 3..0) =4 */ +static u8 twsi_baud_rate = 0x44; /* baudrate at controller reset */ +/* Default frequency corresponding to default m=4, n=4 */ +static u8 twsi_actual_speed = TWSI_FREQUENCY(4, 4); +/* Default slave address is 0 (so is an uninitialized static) */ +static u8 twsi_slave_address; + +/* + * Reset controller. + * Called at end of i2c_init unsuccessful i2c transactions. + * Controller reset also resets the baud rate and slave address, so + * re-establish them. + */ +static void twsi_reset(void) +{ + /* ensure controller will be enabled by any twsi*() function */ + twsi_control_flags = MVTWSI_CONTROL_TWSIEN; + /* reset controller */ + writel(0, &twsi->soft_reset); + /* wait 2 ms -- this is what the Marvell LSP does */ + udelay(20000); + /* set baud rate */ + writel(twsi_baud_rate, &twsi->baudrate); + /* set slave address even though we don't use it */ + writel(twsi_slave_address, &twsi->slave_address); + writel(0, &twsi->xtnd_slave_addr); + /* assert STOP but don't care for the result */ + (void) twsi_stop(0); } -static void -kirkwood_i2c_prepare_for_io(struct i2c_msg *msg) +/* + * I2C init called by cmd_i2c when doing 'i2c reset'. + * Sets baud to the highest possible value not exceeding requested one. + */ +void i2c_init(int requested_speed, int slaveadd) { - u32 dir = 0; - - drv_data->msg = msg; - drv_data->byte_posn = 0; - drv_data->bytes_left = msg->len; - drv_data->aborting = 0; - drv_data->rc = 0; - /* in u-boot we use no IRQs */ - drv_data->cntl_bits = KW_I2C_REG_CONTROL_ACK | KW_I2C_REG_CONTROL_TWSIEN; - - if (msg->flags & I2C_M_RD) - dir = 1; - if (msg->flags & I2C_M_TEN) { - drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; - drv_data->addr2 = (u32)msg->addr & 0xff; - } else { - drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir; - drv_data->addr2 = 0; + int tmp_speed, highest_speed, n, m; + int baud = 0x44; /* baudrate at controller reset */ + + /* use actual speed to collect progressively higher values */ + highest_speed = 0; + /* compute m, n setting for highest speed not above requested speed */ + for (n = 0; n < 8; n++) { + for (m = 0; m < 16; m++) { + tmp_speed = TWSI_FREQUENCY(m, n); + if ((tmp_speed <= requested_speed) + && (tmp_speed > highest_speed)) { + highest_speed = tmp_speed; + baud = (m << 3) | n; + } + } } - /* OK, no start it (from kirkwood_i2c_execute_msg())*/ - drv_data->action = KW_I2C_ACTION_SEND_START; - drv_data->state = KW_I2C_STATE_WAITING_FOR_START_COND; - drv_data->block = 1; - kirkwood_i2c_do_action(); + /* save baud rate and slave for later calls to twsi_reset */ + twsi_baud_rate = baud; + twsi_actual_speed = highest_speed; + twsi_slave_address = slaveadd; + /* reset controller */ + twsi_reset(); } -void -i2c_init(int speed, int slaveadd) +/* + * Begin I2C transaction with expected start status, at given address. + * Common to i2c_probe, i2c_read and i2c_write. + * Expected address status will derive from direction bit (bit 0) in addr. + */ +static int i2c_begin(int expected_start_status, u8 addr) { - kirkwood_i2c_hw_init(speed, slaveadd); + int status, expected_addr_status; + + /* compute expected address status from direction bit in addr */ + if (addr & 1) /* reading */ + expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK; + else /* writing */ + expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK; + /* assert START */ + status = twsi_start(expected_start_status); + /* send out the address if the start went well */ + if (status == 0) + status = twsi_send(addr, expected_addr_status); + /* return ok or status of first failure to caller */ + return status; } -int -i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) +/* + * I2C probe called by cmd_i2c when doing 'i2c probe'. + * Begin read, nak data byte, end. + */ +int i2c_probe(uchar chip) { - kirkwood_i2c_msg->buf = data; - kirkwood_i2c_msg->len = length; - kirkwood_i2c_msg->addr = dev; - kirkwood_i2c_msg->flags = I2C_M_RD; - - kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg); - kirkwood_i2c_doio(kirkwood_i2c_msg); - return drv_data->rc; + u8 dummy_byte; + int status; + + /* begin i2c read */ + status = i2c_begin(MVTWSI_STATUS_START, (chip << 1) | 1); + /* dummy read was accepted: receive byte but NAK it. */ + if (status == 0) + status = twsi_recv(&dummy_byte); + /* Stop transaction */ + twsi_stop(0); + /* return 0 or status of first failure */ + return status; } -int -i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) +/* + * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c + * Begin write, send address byte(s), begin read, receive data bytes, end. + * + * NOTE: some EEPROMS want a stop right before the second start, while + * some will choke if it is there. Deciding which we should do is eeprom + * stuff, not i2c, but at the moment the APIs won't let us put it in + * cmd_eeprom, so we have to choose here, and for the moment that'll be + * a repeated start without a preceding stop. + */ +int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) { - kirkwood_i2c_msg->buf = data; - kirkwood_i2c_msg->len = length; - kirkwood_i2c_msg->addr = dev; - kirkwood_i2c_msg->flags = 0; - - kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg); - kirkwood_i2c_doio(kirkwood_i2c_msg); - return drv_data->rc; + int status; + + /* begin i2c write to send the address bytes */ + status = i2c_begin(MVTWSI_STATUS_START, (dev << 1)); + /* send addr bytes */ + while ((status == 0) && alen--) + status = twsi_send(addr >> (8*alen), + MVTWSI_STATUS_DATA_W_ACK); + /* begin i2c read to receive eeprom data bytes */ + if (status == 0) + status = i2c_begin( + MVTWSI_STATUS_REPEATED_START, (dev << 1) | 1); + /* prepare ACK if at least one byte must be received */ + if (length > 0) + twsi_control_flags |= MVTWSI_CONTROL_ACK; + /* now receive actual bytes */ + while ((status == 0) && length--) { + /* reset NAK if we if no more to read now */ + if (length == 0) + twsi_control_flags &= ~MVTWSI_CONTROL_ACK; + /* read current byte */ + status = twsi_recv(data++); + } + /* Stop transaction */ + status = twsi_stop(status); + /* return 0 or status of first failure */ + return status; } -int -i2c_probe(uchar chip) +/* + * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c + * Begin write, send address byte(s), send data bytes, end. + */ +int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) { - return i2c_read(chip, 0, 0, NULL, 0); + int status; + + /* begin i2c write to send the eeprom adress bytes then data bytes */ + status = i2c_begin(MVTWSI_STATUS_START, (dev << 1)); + /* send addr bytes */ + while ((status == 0) && alen--) + status = twsi_send(addr >> (8*alen), + MVTWSI_STATUS_DATA_W_ACK); + /* send data bytes */ + while ((status == 0) && (length-- > 0)) + status = twsi_send(*(data++), MVTWSI_STATUS_DATA_W_ACK); + /* Stop transaction */ + status = twsi_stop(status); + /* return 0 or status of first failure */ + return status; } +/* + * Bus set routine: we only support bus 0. + */ int i2c_set_bus_num(unsigned int bus) { -#if defined(CONFIG_I2C_MUX) - if (bus < CONFIG_SYS_MAX_I2C_BUS) { - i2c_bus_num = bus; - } else { - int ret; - - ret = i2x_mux_select_mux(bus); - if (ret) - return ret; - i2c_bus_num = 0; - } - i2c_bus_num_mux = bus; -#else if (bus > 0) { return -1; } - - i2c_bus_num = bus; -#endif return 0; } +/* + * Bus get routine: hard-return bus 0. + */ unsigned int i2c_get_bus_num(void) { -#if defined(CONFIG_I2C_MUX) - return i2c_bus_num_mux; -#else - return i2c_bus_num; -#endif + return 0; } -- cgit v0.10.2 From c2ca44c24b77e8f65bd5c564576d8eee1a78b4f5 Mon Sep 17 00:00:00 2001 From: Albert Aribaud Date: Fri, 27 Aug 2010 18:26:06 +0200 Subject: edminiv2: add I2C support using mvtwsi driver Signed-off-by: Albert Aribaud Acked-by: Prafulla Wadaskar Acked-by: Heiko Schocher diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 57dd165..ccfc660 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -132,6 +132,7 @@ */ #include #define CONFIG_CMD_IDE +#define CONFIG_CMD_I2C /* * Network @@ -182,6 +183,16 @@ #endif /* CMD_IDE */ /* + * I2C related stuff + */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* * Environment variables configurations */ #define CONFIG_ENV_IS_IN_FLASH 1 -- cgit v0.10.2 From 8d9207c79223497666580c51be7c4f9e2d7a4d1f Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 27 Aug 2010 16:25:56 -0500 Subject: Fix parameters to support RDIMM for P2020DS Signed-off-by: York Sun Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index dccb7aa..e82082e 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -613,6 +613,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, #if defined(CONFIG_FSL_DDR3) md_en = popts->mirrored_dimm; #endif + rcw_en = popts->registered_dimm_en; qd_en = popts->quad_rank_present ? 1 : 0; ddr->ddr_sdram_cfg_2 = (0 | ((frc_sr & 0x1) << 31) diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index 30d640f..9a1b075 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -68,7 +68,7 @@ const board_specific_parameters_t board_specific_parameters[][20] = { {550, 680, 1, 4, 0x1f, 3, 0}, {681, 850, 1, 4, 0x1f, 4, 0} #else - { 0, 850, 2, 4, 0x1f, 4, 0}, + { 0, 850, 2, 6, 0x1f, 4, 0}, { 0, 850, 1, 4, 0x1f, 4, 0} #endif }, @@ -120,7 +120,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, /* Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xa; - popts->wrlvl_start = 0x7; + popts->wrlvl_start = 0x8; /* Rtt and Rtt_WR override */ popts->rtt_override = 1; popts->rtt_override_value = DDR3_RTT_120_OHM; -- cgit v0.10.2 From 359ec4931944adb885882deb9b781e4095eabc94 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 27 Aug 2010 16:25:50 -0500 Subject: powerpc/8xxx: Fix dma for 36bit addressing Use more bits to support 36-bit addressing Signed-off-by: York Sun Signed-off-by: Kumar Gala diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index df33e7a..09c18c1 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -114,8 +114,12 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) { while (count) { xfer_size = MIN(FSL_DMA_MAX_SIZE, count); - out_dma32(&dma->dar, (uint) dest); - out_dma32(&dma->sar, (uint) src); + out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF)); + out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF)); + out_dma32(&dma->satr, + in_dma32(&dma->satr) | (u32)((u64)src >> 32)); + out_dma32(&dma->datr, + in_dma32(&dma->datr) | (u32)((u64)dest >> 32)); out_dma32(&dma->bcr, xfer_size); dma_sync(); -- cgit v0.10.2 From 38570b2ff3b618892b7b7f2d4c80f5b79d49018f Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Wed, 25 Aug 2010 17:02:28 +0200 Subject: ppc4xx: Fix APC405 board support Opps, after a long time I tested recent u-boot on our APC405 board. This simple fix makes networking work again. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 20849bc..a7724ad 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -104,6 +104,7 @@ #define CONFIG_NET_MULTI 1 #undef CONFIG_HAS_ETH1 +#define CONFIG_PPC4xx_EMAC #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 -- cgit v0.10.2 From c1ab75c7d4e5d080c630335b78681c50aa3569a5 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 26 Aug 2010 17:14:51 +0200 Subject: ppc4xx: Fix 440EPx bug in reconfigure_pll() This patch fixes a bug in reconfigure_pll(), where the detection of the current bootstrap option is wrong. The ICS bits where incorrectly shifted. This bug was found on the lwmon5 board, which uses bootstrap option H (I2C bootstrap EEPROM). Additionally a bit of code was moved into the if statement, since its only used after later on. No need to run this code all the time. Also, a few empty lines are added to make the code better readable. Signed-off-by: Stefan Roese Cc: Rupjyoti Sarmah Cc: Victor Gallardo diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index c04eede..b31bd0b 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -142,22 +142,28 @@ void reconfigure_pll(u32 new_cpu_freq) * modify it. */ if (temp == 1) { - mfcpr(CPR0_PLLD, reg); - /* Get current value of fbdv. */ - temp = (reg & PLLD_FBDV_MASK) >> 24; - fbdv = temp ? temp : 32; - /* Get current value of lfbdv. */ - temp = (reg & PLLD_LFBDV_MASK); - lfbdv = temp ? temp : 64; /* * Load register that contains current boot strapping option. */ mfcpr(CPR0_ICFG, reg); - /* Shift strapping option into low 3 bits.*/ - reg = (reg >> 28); + /* + * Strapping option bits (ICS) are already in correct position, + * only masking needed. + */ + reg &= CPR0_ICFG_ICS_MASK; if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) || (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) { + mfcpr(CPR0_PLLD, reg); + + /* Get current value of fbdv. */ + temp = (reg & PLLD_FBDV_MASK) >> 24; + fbdv = temp ? temp : 32; + + /* Get current value of lfbdv. */ + temp = (reg & PLLD_LFBDV_MASK); + lfbdv = temp ? temp : 64; + /* * Get current value of FWDVA. Assign current FWDVA to * new FWDVB. @@ -165,12 +171,14 @@ void reconfigure_pll(u32 new_cpu_freq) mfcpr(CPR0_PLLD, reg); target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16; fwdvb = target_fwdvb ? target_fwdvb : 8; + /* * Get current value of FWDVB. Assign current FWDVB to * new FWDVA. */ target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8; fwdva = target_fwdva ? target_fwdva : 16; + /* * Update CPR0_PLLD with switched FWDVA and FWDVB. */ @@ -181,6 +189,7 @@ void reconfigure_pll(u32 new_cpu_freq) ((fbdv == 32 ? 0 : fbdv) << 24) | (lfbdv == 64 ? 0 : lfbdv); mtcpr(CPR0_PLLD, reg); + /* Acknowledge that a reset is required. */ reset_needed = 1; } diff --git a/include/ppc440.h b/include/ppc440.h index c807dda..6727753 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1711,6 +1711,7 @@ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define CPR0_ICFG_RLI_MASK 0x80000000 +#define CPR0_ICFG_ICS_MASK 0x00000007 #define CPR0_SPCID_SPCIDV0_MASK 0x03000000 #define CPR0_SPCID_SPCIDV0_DIV1 0x01000000 #define CPR0_SPCID_SPCIDV0_DIV2 0x02000000 -- cgit v0.10.2 From f3cac5384074f3c20b5bcbbdbccbe1e2e25ffc76 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 31 Aug 2010 11:27:14 +0200 Subject: ppc4xx: Invalidate d-cache when used as init-ram We need to invalidate the data cache after it has been used as init-ram. This problem was detected on the lwmon5 update. Signed-off-by: Stefan Roese diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 5296dad..4bad32f 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -1459,6 +1459,11 @@ relocate_code: mtspr SPRN_DTV3,r6 msync isync + + /* Invalidate data cache, now no longer our stack */ + dccci 0,0 + sync + isync #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ /* -- cgit v0.10.2 From 40930316071b9062cae3f01f00876e2fc90940ca Mon Sep 17 00:00:00 2001 From: Xiangfu Liu Date: Mon, 9 Aug 2010 23:13:43 +0800 Subject: MIPS: update the MIPS u-boot.lds From the document, if set all arguments in "OUTPUT_FORMAT" to "tradbigmips", then even add "-EL" to gcc we still get EB format. pb1x00 is only used in Little-endian, so its default endian should be set to LE. Signed-off-by: Xiangfu Liu Signed-off-by: Shinya Kuribayashi diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds index 9a6cd1b..3c4fbe3 100644 --- a/board/dbau1x00/u-boot.lds +++ b/board/dbau1x00/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds index e6eee9b..aeb0fcc 100644 --- a/board/gth2/u-boot.lds +++ b/board/gth2/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds index 9a6cd1b..3c4fbe3 100644 --- a/board/incaip/u-boot.lds +++ b/board/incaip/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds index 9a6cd1b..358cc54 100644 --- a/board/pb1x00/u-boot.lds +++ b/board/pb1x00/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds index 1881e65..542601a 100644 --- a/board/purple/u-boot.lds +++ b/board/purple/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds index ad058ca..bd16786 100644 --- a/board/qemu-mips/u-boot.lds +++ b/board/qemu-mips/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/examples/standalone/mips.lds b/examples/standalone/mips.lds index 717b201..63a1c92 100644 --- a/examples/standalone/mips.lds +++ b/examples/standalone/mips.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) SECTIONS { -- cgit v0.10.2