From feae34243f63fc319b40db7b92070a0718dc31a6 Mon Sep 17 00:00:00 2001
From: York Sun <yorksun@freescale.com>
Date: Mon, 7 May 2012 07:39:53 +0000
Subject: powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E

Fix SVR checking for commit acf3f8da.

Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 36c79d3..1860684 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -171,15 +171,12 @@ __secondary_start_page:
 
 #ifdef CONFIG_BACKSIDE_L2_CACHE
 	/* skip L2 setup on P2040/P2040E as they have no L2 */
-	mfspr	r2,SPRN_SVR
+	mfspr	r3,SPRN_SVR
+	rlwinm	r6,r3,24,~0x800		/* clear E bit of SVR */
+
 	lis	r3,SVR_P2040@h
 	ori	r3,r3,SVR_P2040@l
-	cmpw	r2,r3
-	beq 3f
-
-	lis	r3,SVR_P2040_E@h
-	ori	r3,r3,SVR_P2040_E@l
-	cmpw	r2,r3
+	cmpw	r6,r3
 	beq 3f
 
 	/* Enable/invalidate the L2 cache */
-- 
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