From c8c845cfdc6d0217135c1d5927eebd2b133a3314 Mon Sep 17 00:00:00 2001 From: Ben Warren Date: Sat, 5 Jul 2008 00:08:48 -0700 Subject: Moved initialization of AVR32 Ethernet controllers to board_eth_init() Renamed initialization functions for atngw100 and atstk1000. Removed initializations for these boards from net/eth.c Signed-off-by: Ben Warren Signed-off-by: Haavard Skinnemoen diff --git a/board/atmel/atngw100/Makefile b/board/atmel/atngw100/Makefile index 1b5c635..9f3849f 100644 --- a/board/atmel/atngw100/Makefile +++ b/board/atmel/atngw100/Makefile @@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(BOARD).a -COBJS := $(BOARD).o eth.o +COBJS := $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c index f2c3e79..52c70f7 100644 --- a/board/atmel/atngw100/atngw100.c +++ b/board/atmel/atngw100/atngw100.c @@ -93,6 +93,17 @@ void board_init_info(void) gd->bd->bi_phy_id[1] = 0x03; } +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bi) +{ + macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); + macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]); + return 0; +} +#endif + /* SPI chip select control */ #ifdef CONFIG_ATMEL_SPI #include diff --git a/board/atmel/atngw100/eth.c b/board/atmel/atngw100/eth.c deleted file mode 100644 index d1d57bb..0000000 --- a/board/atmel/atngw100/eth.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * Ethernet initialization for the AVR32 Network Gateway - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include - -#include - -extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); - -#ifdef CONFIG_CMD_NET -void atngw100_eth_initialize(bd_t *bi) -{ - macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); - macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]); -} -#endif diff --git a/board/atmel/atstk1000/Makefile b/board/atmel/atstk1000/Makefile index 8a15713..155d46a 100644 --- a/board/atmel/atstk1000/Makefile +++ b/board/atmel/atstk1000/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(BOARD).a -COBJS := $(BOARD).o flash.o eth.o +COBJS := $(BOARD).o flash.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c index 6371e2d..496c6a8 100644 --- a/board/atmel/atstk1000/atstk1000.c +++ b/board/atmel/atstk1000/atstk1000.c @@ -115,3 +115,14 @@ void board_init_info(void) gd->bd->bi_phy_id[0] = 0x10; gd->bd->bi_phy_id[1] = 0x11; } + +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bi) +{ + macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); + macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]); + return 0; +} +#endif diff --git a/board/atmel/atstk1000/eth.c b/board/atmel/atstk1000/eth.c deleted file mode 100644 index b2b1a12..0000000 --- a/board/atmel/atstk1000/eth.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * Ethernet initialization for the ATSTK1000 starterkit - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include - -#include - -extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); - -#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET) -void atstk1000_eth_initialize(bd_t *bi) -{ - int id = 0; - - macb_eth_initialize(id++, (void *)MACB0_BASE, bi->bi_phy_id[0]); - macb_eth_initialize(id++, (void *)MACB1_BASE, bi->bi_phy_id[1]); -} -#endif diff --git a/net/eth.c b/net/eth.c index 38979aa..8e83b66 100644 --- a/net/eth.c +++ b/net/eth.c @@ -69,9 +69,7 @@ extern int uli526x_initialize(bd_t *); extern int npe_initialize(bd_t *); extern int uec_initialize(int); extern int bfin_EMAC_initialize(bd_t *); -extern int atstk1000_eth_initialize(bd_t *); extern int greth_initialize(bd_t *); -extern int atngw100_eth_initialize(bd_t *); extern int mcffec_initialize(bd_t*); extern int mcdmafec_initialize(bd_t*); extern int at91sam9_eth_initialize(bd_t *); @@ -271,15 +269,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_BF537) bfin_EMAC_initialize(bis); #endif -#if defined(CONFIG_ATSTK1000) - atstk1000_eth_initialize(bis); -#endif #if defined(CONFIG_GRETH) greth_initialize(bis); #endif -#if defined(CONFIG_ATNGW100) - atngw100_eth_initialize(bis); -#endif #if defined(CONFIG_MCFFEC) mcffec_initialize(bis); #endif -- cgit v0.10.2 From 5c374c9ee16fee2bf68533cc4010b3c0df21f783 Mon Sep 17 00:00:00 2001 From: Julien May Date: Mon, 23 Jun 2008 13:57:52 +0200 Subject: Add support for the hammerhead (AVR32) board The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. It offers versatile peripherals, such as ethernet, usb device, usb host etc. The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered Device (PD). Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. For more information see: http:///www.miromico.com/hammerhead Signed-off-by: Julien May [haavard.skinnemoen@atmel.com: various small fixes and adaptions] Signed-off-by: Haavard Skinnemoen diff --git a/MAINTAINERS b/MAINTAINERS index cbe5c47..bcac300 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -709,6 +709,11 @@ Haavard Skinnemoen ATSTK1006 AT32AP7000 ATNGW100 AT32AP7000 +Alex Raimondi +Julien May + + HAMMERHEAD AT32AP7000 + ######################################################################### # SuperH Systems: # # # diff --git a/MAKEALL b/MAKEALL index ee83cca..d14cb79 100755 --- a/MAKEALL +++ b/MAKEALL @@ -714,6 +714,7 @@ LIST_avr32=" \ atstk1004 \ atstk1006 \ atngw100 \ + hammerhead \ " ######################################################################### diff --git a/Makefile b/Makefile index b104617..acc36f4 100644 --- a/Makefile +++ b/Makefile @@ -2911,6 +2911,9 @@ atstk1004_config : unconfig atstk1006_config : unconfig @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x +hammerhead_config : unconfig + @$(MKCONFIG) $(@:_config=) avr32 at32ap hammerhead miromico at32ap700x + #======================================================================== # SH3 (SuperH) #======================================================================== diff --git a/board/miromico/hammerhead/Makefile b/board/miromico/hammerhead/Makefile new file mode 100644 index 0000000..4b74d16 --- /dev/null +++ b/board/miromico/hammerhead/Makefile @@ -0,0 +1,40 @@ +# +# Copyright (C) 2008 Miromico AG +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/miromico/hammerhead/config.mk b/board/miromico/hammerhead/config.mk new file mode 100644 index 0000000..9a794e5 --- /dev/null +++ b/board/miromico/hammerhead/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE = 0x00000000 +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_LDFLAGS += --gc-sections diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c new file mode 100644 index 0000000..738ece2 --- /dev/null +++ b/board/miromico/hammerhead/hammerhead.c @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2008 Miromico AG + * + * Mostly copied form atmel ATNGW100 sources + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "../cpu/at32ap/at32ap700x/sm.h" + +#include + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct sdram_config sdram_config = { + .data_bits = SDRAM_DATA_32BIT, + .row_bits = 13, + .col_bits = 9, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 5, + .txsr = 5, + /* 7.81 us */ + .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, +}; + +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + return macb_eth_initialize(0, (void *)MACB0_BASE, bis->bi_phy_id[0]); +} +#endif + +int board_early_init_f(void) +{ + /* Enable SDRAM in the EBI mux */ + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); + + gpio_enable_ebi(); + gpio_enable_usart1(); + +#if defined(CONFIG_MACB) + gpio_enable_macb0(); +#endif +#if defined(CONFIG_MMC) + gpio_enable_mmci(); +#endif + return 0; +} + +phys_size_t initdram(int board_type) +{ + unsigned long expected_size; + unsigned long actual_size; + void *sdram_base; + + sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + + expected_size = sdram_init(sdram_base, &sdram_config); + actual_size = get_ram_size(sdram_base, expected_size); + + unmap_physmem(sdram_base, EBI_SDRAM_SIZE); + + if (expected_size != actual_size) + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return actual_size; +} + +void board_init_info(void) +{ + gd->bd->bi_phy_id[0] = 0x01; +} + +void gclk_init(void) +{ + /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */ + + /* Select GCLK3 peripheral function */ + gpio_select_periph_A(GPIO_PIN_PB29, 0); + + /* Enable GCLK3 with no input divider, from OSC0 (crystal) */ + sm_writel(PM_GCCTRL(3), SM_BIT(CEN)); +} diff --git a/board/miromico/hammerhead/u-boot.lds b/board/miromico/hammerhead/u-boot.lds new file mode 100644 index 0000000..e736adf --- /dev/null +++ b/board/miromico/hammerhead/u-boot.lds @@ -0,0 +1,73 @@ +/* -*- Fundamental -*- + * + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = 0; + _text = .; + .text : { + *(.exception.text) + *(.text) + *(.text.*) + } + _etext = .; + + .rodata : { + *(.rodata) + *(.rodata.*) + } + + . = ALIGN(8); + _data = .; + .data : { + *(.data) + *(.data.*) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { + KEEP(*(.u_boot_cmd)) + } + __u_boot_cmd_end = .; + + . = ALIGN(4); + _got = .; + .got : { + *(.got) + } + _egot = .; + + . = ALIGN(8); + _edata = .; + + .bss : { + *(.bss) + *(.bss.*) + } + . = ALIGN(8); + _end = .; +} diff --git a/cpu/at32ap/at32ap700x/sm.h b/cpu/at32ap/at32ap700x/sm.h index 6492c8e..b6e4409 100644 --- a/cpu/at32ap/at32ap700x/sm.h +++ b/cpu/at32ap/at32ap700x/sm.h @@ -21,7 +21,7 @@ #define SM_PM_IMR 0x0048 #define SM_PM_ISR 0x004c #define SM_PM_ICR 0x0050 -#define SM_PM_GCCTRL 0x0060 +#define SM_PM_GCCTRL(x) (0x0060 + 4 * x) #define SM_RTC_CTRL 0x0080 #define SM_RTC_VAL 0x0084 #define SM_RTC_TOP 0x0088 diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c index 0ba8361..1a13702 100644 --- a/cpu/at32ap/cpu.c +++ b/cpu/at32ap/cpu.c @@ -65,6 +65,9 @@ int cpu_init(void) sysreg_write(EVBA, (unsigned long)&_evba); asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET)); + if(gclk_init) + gclk_init(); + return 0; } diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index a9d8431..e9a4fe4 100644 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -82,6 +82,7 @@ static inline unsigned long get_spi_clk_rate(unsigned int dev_id) #endif extern void clk_init(void); +extern void gclk_init(void) __attribute__((weak)); /* Board code may need the SDRAM base clock as a compile-time constant */ #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB) diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h new file mode 100644 index 0000000..ab13d2e --- /dev/null +++ b/include/configs/hammerhead.h @@ -0,0 +1,172 @@ +/* + * Copyright (C) 2008 Miromico AG + * + * Configuration settings for the Miromico Hammerhead AVR32 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_HAMMERHEAD 1 + +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 125 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency + * and the PBA bus to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 25000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 5 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +#define CFG_CLKDIV_CPU 0 +#define CFG_CLKDIV_HSB 1 +#define CFG_CLKDIV_PBA 2 +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#define CONFIG_USART1 1 + +#define CONFIG_HOSTNAME hammerhead + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=mtd1 rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm" + +/* + * Only interrupt autoboot if is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * After booting the board for the first time, new ethernet address + * should be generated and assigned to the environment variables + * "ethaddr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP/DHCP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE 0x24000000 +#define CFG_INTRAM_SIZE 0x8000 + +#define CFG_SDRAM_BASE 0x10000000 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) + +#define CFG_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "Hammerhead> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000) + +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From 0eb5717a85b6cba3f67c11fa89bdde38dcd081b5 Mon Sep 17 00:00:00 2001 From: Hans-Christian Egtvedt Date: Wed, 6 Aug 2008 14:42:13 +0200 Subject: avr32: add support for EarthLCD Favr-32 board This patch adds support for the Favr-32 board made by EarthLCD. This kit, which is also called ezLCD-101 when running with EarthLCD firmware, has a 10.4" touch screen LCD panel, 16 MB 32-bit SDRAM, 8 MB parallel flash, Ethernet, audio out, USB device, SD-card slot, USART and various other connectors for cennecting stuff to SPI, I2C, GPIO, etc. Signed-off-by: Hans-Christian Egtvedt Signed-off-by: Haavard Skinnemoen diff --git a/MAINTAINERS b/MAINTAINERS index cbe5c47..0ff2add 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -709,6 +709,10 @@ Haavard Skinnemoen ATSTK1006 AT32AP7000 ATNGW100 AT32AP7000 +Hans-Christian Egtvedt + + FAVR-32-EZKIT AT32AP7000 + ######################################################################### # SuperH Systems: # # # diff --git a/MAKEALL b/MAKEALL index ee83cca..76dd334 100755 --- a/MAKEALL +++ b/MAKEALL @@ -714,6 +714,7 @@ LIST_avr32=" \ atstk1004 \ atstk1006 \ atngw100 \ + favr-32-ezkit \ " ######################################################################### diff --git a/Makefile b/Makefile index 3179c67..ebbf2bc 100644 --- a/Makefile +++ b/Makefile @@ -2911,6 +2911,9 @@ atstk1004_config : unconfig atstk1006_config : unconfig @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x +favr-32-ezkit_config : unconfig + @$(MKCONFIG) $(@:_config=) avr32 at32ap favr-32-ezkit earthlcd at32ap700x + #======================================================================== # SH3 (SuperH) #======================================================================== diff --git a/board/earthlcd/favr-32-ezkit/Makefile b/board/earthlcd/favr-32-ezkit/Makefile new file mode 100644 index 0000000..3e67a65 --- /dev/null +++ b/board/earthlcd/favr-32-ezkit/Makefile @@ -0,0 +1,42 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2008 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) any later +# version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +# details. +# +# You should have received a copy of the GNU General Public License along with +# this program; if not, write to the Free Software Foundation, Inc., 59 Temple +# Place, Suite 330, Boston, MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o flash.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/earthlcd/favr-32-ezkit/config.mk b/board/earthlcd/favr-32-ezkit/config.mk new file mode 100644 index 0000000..2337d62 --- /dev/null +++ b/board/earthlcd/favr-32-ezkit/config.mk @@ -0,0 +1,4 @@ +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_LDFLAGS += --gc-sections +TEXT_BASE = 0x00000000 +LDSCRIPT = $(obj)board/earthlcd/favr-32-ezkit/u-boot.lds diff --git a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c new file mode 100644 index 0000000..22b6981 --- /dev/null +++ b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple + * Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct sdram_config sdram_config = { + /* MT48LC4M32B2P-6 (16 MB) */ + .data_bits = SDRAM_DATA_32BIT, + .row_bits = 12, + .col_bits = 8, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 5, + .txsr = 5, + /* 15.6 us */ + .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000, +}; + +int board_early_init_f(void) +{ + /* Enable SDRAM in the EBI mux */ + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); + + gpio_enable_ebi(); + gpio_enable_usart3(); +#if defined(CONFIG_MACB) + gpio_enable_macb0(); +#endif +#if defined(CONFIG_MMC) + gpio_enable_mmci(); +#endif + + return 0; +} + +phys_size_t initdram(int board_type) +{ + unsigned long expected_size; + unsigned long actual_size; + void *sdram_base; + + sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + + expected_size = sdram_init(sdram_base, &sdram_config); + actual_size = get_ram_size(sdram_base, expected_size); + + unmap_physmem(sdram_base, EBI_SDRAM_SIZE); + + if (expected_size != actual_size) + printf("Warning: Only %u of %u MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return actual_size; +} + +void board_init_info(void) +{ + gd->bd->bi_phy_id[0] = 0x01; +} + +#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET) +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); + +int board_eth_init(bd_t *bi) +{ + return macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); +} +#endif diff --git a/board/earthlcd/favr-32-ezkit/flash.c b/board/earthlcd/favr-32-ezkit/flash.c new file mode 100644 index 0000000..49a715a --- /dev/null +++ b/board/earthlcd/favr-32-ezkit/flash.c @@ -0,0 +1,230 @@ +/* + * Copyright (C) 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple + * Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include + +#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +flash_info_t flash_info[1]; + +static void flash_identify(uint16_t *flash, flash_info_t *info) +{ + unsigned long flags; + + flags = disable_interrupts(); + + dcache_flush_unlocked(); + + writew(0xaa, flash + 0x555); + writew(0x55, flash + 0xaaa); + writew(0x90, flash + 0x555); + info->flash_id = readl(flash); + writew(0xff, flash); + + readw(flash); + + if (flags) + enable_interrupts(); +} + +unsigned long flash_init(void) +{ + unsigned long addr; + unsigned int i; + + flash_info[0].size = CFG_FLASH_SIZE; + flash_info[0].sector_count = 135; + + flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]); + + for (i = 0, addr = 0; i < 8; i++, addr += 0x2000) + flash_info[0].start[i] = addr; + for (; i < flash_info[0].sector_count; i++, addr += 0x10000) + flash_info[0].start[i] = addr; + + return CFG_FLASH_SIZE; +} + +void flash_print_info(flash_info_t *info) +{ + printf("Flash: Vendor ID: 0x%02x, Product ID: 0x%02x\n", + info->flash_id >> 16, info->flash_id & 0xffff); + printf("Size: %ld MB in %d sectors\n", + info->size >> 10, info->sector_count); +} + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + unsigned long flags; + unsigned long start_time; + uint16_t *fb, *sb; + unsigned int i; + int ret; + uint16_t status; + + if ((s_first < 0) || (s_first > s_last) + || (s_last >= info->sector_count)) { + puts("Error: first and/or last sector out of range\n"); + return ERR_INVAL; + } + + for (i = s_first; i < s_last; i++) + if (info->protect[i]) { + printf("Error: sector %d is protected\n", i); + return ERR_PROTECTED; + } + + fb = (uint16_t *)uncached(info->start[0]); + + dcache_flush_unlocked(); + + for (i = s_first; (i <= s_last) && !ctrlc(); i++) { + printf("Erasing sector %3d...", i); + + sb = (uint16_t *)uncached(info->start[i]); + + flags = disable_interrupts(); + + start_time = get_timer(0); + + /* Unlock sector */ + writew(0xaa, fb + 0x555); + writew(0x70, sb); + + /* Erase sector */ + writew(0xaa, fb + 0x555); + writew(0x55, fb + 0xaaa); + writew(0x80, fb + 0x555); + writew(0xaa, fb + 0x555); + writew(0x55, fb + 0xaaa); + writew(0x30, sb); + + /* Wait for completion */ + ret = ERR_OK; + do { + /* TODO: Timeout */ + status = readw(sb); + } while ((status != 0xffff) && !(status & 0x28)); + + writew(0xf0, fb); + + /* + * Make sure the command actually makes it to the bus + * before we re-enable interrupts. + */ + readw(fb); + + if (flags) + enable_interrupts(); + + if (status != 0xffff) { + printf("Flash erase error at address 0x%p: 0x%02x\n", + sb, status); + ret = ERR_PROG_ERROR; + break; + } + } + + if (ctrlc()) + printf("User interrupt!\n"); + + return ERR_OK; +} + +int write_buff(flash_info_t *info, uchar *src, + ulong addr, ulong count) +{ + unsigned long flags; + uint16_t *base, *p, *s, *end; + uint16_t word, status, status1; + int ret = ERR_OK; + + if (addr < info->start[0] + || (addr + count) > (info->start[0] + info->size) + || (addr + count) < addr) { + puts("Error: invalid address range\n"); + return ERR_INVAL; + } + + if (addr & 1 || count & 1 || (unsigned int)src & 1) { + puts("Error: misaligned source, destination or count\n"); + return ERR_ALIGN; + } + + base = (uint16_t *)uncached(info->start[0]); + end = (uint16_t *)uncached(addr + count); + + flags = disable_interrupts(); + + dcache_flush_unlocked(); + sync_write_buffer(); + + for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src; + p < end && !ctrlc(); p++, s++) { + word = *s; + + writew(0xaa, base + 0x555); + writew(0x55, base + 0xaaa); + writew(0xa0, base + 0x555); + writew(word, p); + + sync_write_buffer(); + + /* Wait for completion */ + status1 = readw(p); + do { + /* TODO: Timeout */ + status = status1; + status1 = readw(p); + } while (((status ^ status1) & 0x40) /* toggled */ + && !(status1 & 0x28)); /* error bits */ + + /* + * We'll need to check once again for toggle bit + * because the toggle bit may stop toggling as I/O5 + * changes to "1" (ref at49bv642.pdf p9) + */ + status1 = readw(p); + status = readw(p); + if ((status ^ status1) & 0x40) { + printf("Flash write error at address 0x%p: " + "0x%02x != 0x%02x\n", + p, status,word); + ret = ERR_PROG_ERROR; + writew(0xf0, base); + readw(base); + break; + } + + writew(0xf0, base); + readw(base); + } + + if (flags) + enable_interrupts(); + + return ret; +} + +#endif /* CONFIG_FAVR32_EZKIT_EXT_FLASH */ diff --git a/board/earthlcd/favr-32-ezkit/u-boot.lds b/board/earthlcd/favr-32-ezkit/u-boot.lds new file mode 100644 index 0000000..ad056b3 --- /dev/null +++ b/board/earthlcd/favr-32-ezkit/u-boot.lds @@ -0,0 +1,71 @@ +/* -*- Fundamental -*- + * + * Copyright (C) 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple + * Place, Suite 330, Boston, MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = 0; + _text = .; + .text : { + *(.exception.text) + *(.text) + *(.text.*) + } + _etext = .; + + .rodata : { + *(.rodata) + *(.rodata.*) + } + + . = ALIGN(8); + _data = .; + .data : { + *(.data) + *(.data.*) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { + KEEP(*(.u_boot_cmd)) + } + __u_boot_cmd_end = .; + + . = ALIGN(4); + _got = .; + .got : { + *(.got) + } + _egot = .; + + . = ALIGN(8); + _edata = .; + + .bss (NOLOAD) : { + *(.bss) + *(.bss.*) + } + . = ALIGN(8); + _end = .; +} diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h new file mode 100644 index 0000000..6f77c25 --- /dev/null +++ b/include/configs/favr-32-ezkit.h @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2008 Atmel Corporation + * + * Configuration settings for the Favr-32 EarthLCD LCD kit. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple + * Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_FAVR32_EZKIT 1 + +#define CONFIG_FAVR32_EZKIT_EXT_FLASH 1 + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the + * PLL frequency. + * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 20000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 7 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +/* + * Set the CPU running at: + * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz + */ +#define CFG_CLKDIV_CPU 0 +/* + * Set the HSB running at: + * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz + */ +#define CFG_CLKDIV_HSB 1 +/* + * Set the PBA running at: + * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz + */ +#define CFG_CLKDIV_PBA 2 +/* + * Set the PBB running at: + * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz + */ +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "root=/dev/mtdblock1 rootfstype=jffs fbmem=1800k" + +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm $(fileaddr)" + +/* + * Only interrupt autoboot if is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * After booting the board for the first time, new ethernet addresses + * should be generated and assigned to the environment variables + * "ethaddr" and "eth1addr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC + +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +/* External flash on Favr-32 */ +#if 0 +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#endif + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) +#define CFG_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START EBI_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From 13b50fe3bc065c48911fa373231421280855a9d6 Mon Sep 17 00:00:00 2001 From: Mark Jackson Date: Wed, 30 Jul 2008 13:07:27 +0100 Subject: avr32: Add MIMC200 board The MIMC200 board is based on Atmel's NGW100 dev kit, but with an extra 8MByte FLASH and 128KByte FRAM. Signed-off-by: Mark Jackson Signed-off-by: Haavard Skinnemoen diff --git a/CREDITS b/CREDITS index 2b0dab7..5010c78 100644 --- a/CREDITS +++ b/CREDITS @@ -217,6 +217,10 @@ H: Rich Ireland E: r.ireland@computer.org D: FPGA device configuration driver +H: Mark Jackson +E: mpfj@mimc.co.uk +D: Port to MIMC200 board + N: Gary Jennejohn E: garyj@jennejohn.org, gj@denx.de D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB" diff --git a/MAINTAINERS b/MAINTAINERS index cbe5c47..1716055 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -700,6 +700,10 @@ Hayden Fraser # Board CPU # ######################################################################### +Mark Jackson + + MIMC200 AT32AP7000 + Haavard Skinnemoen ATSTK1000 AT32AP7xxx diff --git a/MAKEALL b/MAKEALL index ee83cca..fcd9310 100755 --- a/MAKEALL +++ b/MAKEALL @@ -714,6 +714,7 @@ LIST_avr32=" \ atstk1004 \ atstk1006 \ atngw100 \ + mimc200 \ " ######################################################################### diff --git a/Makefile b/Makefile index 3179c67..a74f33b 100644 --- a/Makefile +++ b/Makefile @@ -2911,6 +2911,9 @@ atstk1004_config : unconfig atstk1006_config : unconfig @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x +mimc200_config : unconfig + @$(MKCONFIG) $(@:_config=) avr32 at32ap mimc200 mimc at32ap700x + #======================================================================== # SH3 (SuperH) #======================================================================== diff --git a/board/mimc/mimc200/Makefile b/board/mimc/mimc200/Makefile new file mode 100644 index 0000000..9f3849f --- /dev/null +++ b/board/mimc/mimc200/Makefile @@ -0,0 +1,40 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mimc/mimc200/config.mk b/board/mimc/mimc200/config.mk new file mode 100644 index 0000000..9a794e5 --- /dev/null +++ b/board/mimc/mimc200/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE = 0x00000000 +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_LDFLAGS += --gc-sections diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c new file mode 100644 index 0000000..4ece11a --- /dev/null +++ b/board/mimc/mimc200/mimc200.c @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include +#include +#include +#include +#include + +#define SM_PM_GCCTRL 0x0060 + +DECLARE_GLOBAL_DATA_PTR; + +static const struct sdram_config sdram_config = { + .data_bits = SDRAM_DATA_16BIT, + .row_bits = 13, + .col_bits = 9, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 6, + .trp = 2, + .trcd = 2, + .tras = 6, + .txsr = 6, + /* 15.6 us */ + .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000, +}; + +int board_early_init_f(void) +{ + /* Enable SDRAM in the EBI mux */ + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); + + gpio_enable_ebi(); + gpio_enable_usart1(); + + /* enable higher address lines for larger flash devices */ + gpio_select_periph_A(GPIO_PIN_PE16, 0); /* ADDR23 */ + gpio_select_periph_A(GPIO_PIN_PE17, 0); /* ADDR24 */ + gpio_select_periph_A(GPIO_PIN_PE18, 0); /* ADDR25 */ + + /* enable data flash chip select */ + gpio_select_periph_A(GPIO_PIN_PE25, 0); /* NCS2 */ + + /* de-assert "force sys reset" pin */ + gpio_set_value(GPIO_PIN_PD15, 1); /* FORCE RESET */ + gpio_select_pio(GPIO_PIN_PD15, GPIOF_OUTPUT); + + /* init custom i/o */ + /* cpu type inputs */ + gpio_select_pio(GPIO_PIN_PE19, 0); + gpio_select_pio(GPIO_PIN_PE20, 0); + gpio_select_pio(GPIO_PIN_PE23, 0); + /* main board type inputs */ + gpio_select_pio(GPIO_PIN_PB19, 0); + gpio_select_pio(GPIO_PIN_PB29, 0); + /* DEBUG input (use weak pullup) */ + gpio_select_pio(GPIO_PIN_PE21, GPIOF_PULLUP); + + /* are we suppressing the console ? */ + if (gpio_get_value(GPIO_PIN_PE21) == 1) + gd->flags |= GD_FLG_SILENT; + + /* reset phys */ + gpio_select_pio(GPIO_PIN_PE24, 0); + gpio_set_value(GPIO_PIN_PC18, 1); /* PHY RESET */ + gpio_select_pio(GPIO_PIN_PC18, GPIOF_OUTPUT); + + /* GCLK0 - 10MHz clock */ + writel(0x00000004, (void *)SM_BASE + SM_PM_GCCTRL); + gpio_select_periph_A(GPIO_PIN_PA30, 0); + + udelay(5000); + + /* release phys reset */ + gpio_set_value(GPIO_PIN_PC18, 0); /* PHY RESET (Release) */ + +#if defined(CONFIG_MACB) + /* init macb0 pins */ + gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */ + gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */ + gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */ + gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */ + gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */ + gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */ + gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */ + gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */ + gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */ + gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */ +#if !defined(CONFIG_RMII) + gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */ + gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */ + gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */ + gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */ + gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */ + gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */ + gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */ + gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */ +#endif + + /* init macb1 pins */ + gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */ + gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */ + gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */ + gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */ + gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */ + gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */ + gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */ + gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */ + gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */ + gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */ +#if !defined(CONFIG_RMII) + gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */ + gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */ + gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */ + gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */ + gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */ + gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */ + gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */ + gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */ +#endif +#endif + +#if defined(CONFIG_MMC) + gpio_enable_mmci(); +#endif + + return 0; +} + +phys_size_t initdram(int board_type) +{ + unsigned long expected_size; + unsigned long actual_size; + void *sdram_base; + + sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + + expected_size = sdram_init(sdram_base, &sdram_config); + actual_size = get_ram_size(sdram_base, expected_size); + + unmap_physmem(sdram_base, EBI_SDRAM_SIZE); + + if (expected_size != actual_size) + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return actual_size; +} + +void board_init_info(void) +{ + gd->bd->bi_phy_id[0] = 0x01; + gd->bd->bi_phy_id[1] = 0x03; +} + +/* SPI chip select control */ +#ifdef CONFIG_ATMEL_SPI +#include + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return (bus == 0) && (cs == 0); +} + +void spi_cs_activate(struct spi_slave *slave) +{ +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ +} +#endif /* CONFIG_ATMEL_SPI */ + +#ifdef CONFIG_CMD_NET +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); + +int board_eth_init(bd_t *bi) +{ + macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); + macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]); + + return 0; +} +#endif diff --git a/board/mimc/mimc200/u-boot.lds b/board/mimc/mimc200/u-boot.lds new file mode 100644 index 0000000..e736adf --- /dev/null +++ b/board/mimc/mimc200/u-boot.lds @@ -0,0 +1,73 @@ +/* -*- Fundamental -*- + * + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = 0; + _text = .; + .text : { + *(.exception.text) + *(.text) + *(.text.*) + } + _etext = .; + + .rodata : { + *(.rodata) + *(.rodata.*) + } + + . = ALIGN(8); + _data = .; + .data : { + *(.data) + *(.data.*) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { + KEEP(*(.u_boot_cmd)) + } + __u_boot_cmd_end = .; + + . = ALIGN(4); + _got = .; + .got : { + *(.got) + } + _egot = .; + + . = ALIGN(8); + _edata = .; + + .bss : { + *(.bss) + *(.bss.*) + } + . = ALIGN(8); + _end = .; +} diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h new file mode 100644 index 0000000..3486be0 --- /dev/null +++ b/include/configs/mimc200.h @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * Configuration settings for the AVR32 Network Gateway + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_MIMC200 1 + +#define CONFIG_MIMC200_EXT_FLASH 1 + +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency + * and the PBA bus to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 10000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 15 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +#define CFG_CLKDIV_CPU 0 +#define CFG_CLKDIV_HSB 1 +#define CFG_CLKDIV_PBA 2 +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#define CONFIG_USART1 1 +#define CONFIG_MIMC200_DBGLINK 1 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=/dev/mtdblock1 fbmem=600k rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm" + +#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ +#define CONFIG_SILENT_CONSOLE_INPUT 1 /* disable console inputs */ +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +/* + * Only interrupt autoboot if is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 0 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 +#define CONFIG_AUTOBOOT 1 + +/* + * After booting the board for the first time, new ethernet addresses + * should be generated and assigned to the environment variables + * "ethaddr" and "eth1addr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP/DHCP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + +#define CONFIG_DOS_PARTITION 1 + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE + +#define CFG_FRAM_BASE 0x08000000 +#define CFG_FRAM_SIZE 0x20000 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (1024*1024) +#define CFG_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START EBI_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000) + +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From 462da25e89b0b58bf4c66346c1fcb3087c61b4b8 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Fri, 15 Aug 2008 12:04:25 +0200 Subject: MAINTAINERS: Sort avr32 section alphabetically The rest of the MAINTAINERS file appears to be sorted almost-alphabetically, but entries for the newly added AVR32 boards were added somewhat randomly. This patch sorts the list alphabetically again. Also update my e-mail address. The old one still works, but it may not work forever. Signed-off-by: Haavard Skinnemoen diff --git a/MAINTAINERS b/MAINTAINERS index 7fe89ff..4f7c97c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -700,27 +700,27 @@ Hayden Fraser # Board CPU # ######################################################################### -Mark Jackson +Hans-Christian Egtvedt - MIMC200 AT32AP7000 + FAVR-32-EZKIT AT32AP7000 -Haavard Skinnemoen +Mark Jackson - ATSTK1000 AT32AP7xxx - ATSTK1002 AT32AP7000 - ATSTK1003 AT32AP7001 - ATSTK1004 AT32AP7002 - ATSTK1006 AT32AP7000 - ATNGW100 AT32AP7000 + MIMC200 AT32AP7000 Alex Raimondi Julien May HAMMERHEAD AT32AP7000 -Hans-Christian Egtvedt +Haavard Skinnemoen - FAVR-32-EZKIT AT32AP7000 + ATSTK1000 AT32AP7xxx + ATSTK1002 AT32AP7000 + ATSTK1003 AT32AP7001 + ATSTK1004 AT32AP7002 + ATSTK1006 AT32AP7000 + ATNGW100 AT32AP7000 ######################################################################### # SuperH Systems: # -- cgit v0.10.2 From 25da0b84195fdda89a943b2d25757db5afeef5b8 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Wed, 20 Aug 2008 09:27:37 +0200 Subject: favr-32-ezkit: Fix printf format warnings Signed-off-by: Haavard Skinnemoen diff --git a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c index 22b6981..da69e75 100644 --- a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c +++ b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c @@ -75,7 +75,7 @@ phys_size_t initdram(int board_type) unmap_physmem(sdram_base, EBI_SDRAM_SIZE); if (expected_size != actual_size) - printf("Warning: Only %u of %u MiB SDRAM is working\n", + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", actual_size >> 20, expected_size >> 20); return actual_size; diff --git a/board/earthlcd/favr-32-ezkit/flash.c b/board/earthlcd/favr-32-ezkit/flash.c index 49a715a..2aa9415 100644 --- a/board/earthlcd/favr-32-ezkit/flash.c +++ b/board/earthlcd/favr-32-ezkit/flash.c @@ -68,7 +68,7 @@ unsigned long flash_init(void) void flash_print_info(flash_info_t *info) { - printf("Flash: Vendor ID: 0x%02x, Product ID: 0x%02x\n", + printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n", info->flash_id >> 16, info->flash_id & 0xffff); printf("Size: %ld MB in %d sectors\n", info->size >> 10, info->sector_count); diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h index 6f77c25..a27c02a 100644 --- a/include/configs/favr-32-ezkit.h +++ b/include/configs/favr-32-ezkit.h @@ -108,7 +108,7 @@ #define CONFIG_AUTOBOOT 1 #define CONFIG_AUTOBOOT_KEYED 1 #define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n" + "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " -- cgit v0.10.2 From 33eac2b3d946fc998a09245dfe54d017079b9056 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Wed, 20 Aug 2008 09:28:36 +0200 Subject: hammerhead: Add missing printf parameter to CONFIG_AUTOBOOT_PROMPT Signed-off-by: Haavard Skinnemoen diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h index ab13d2e..8e83daa 100644 --- a/include/configs/hammerhead.h +++ b/include/configs/hammerhead.h @@ -83,7 +83,7 @@ #define CONFIG_AUTOBOOT 1 #define CONFIG_AUTOBOOT_KEYED 1 #define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n" + "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " -- cgit v0.10.2