From 46d0a9913c2874521ea63e50b6c7593629b7e7d0 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 17 Aug 2015 18:38:06 +0530 Subject: spi: Add zynq qspi controller driver Added zynq qspi controller driver for Xilinx Zynq APSOC, this driver is driver-model driven with devicetree support. => sf probe SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 16 MiB => mw.b 0x100 0xCC 0x1000000 => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 59.842s, speed 289262 B/s => sf read 0x3000000 0x0 0x1000000 device 0 whole chip SF: 16777216 bytes @ 0x0 Read: OK => cmp.b 0x3000000 0x100 0x1000000 Total of 16777216 byte(s) were the same Signed-off-by: Jagan Teki Reviewed-by: Simon Glass Cc: Michal Simek Acked-by: Siva Durga Prasad Paladugu Tested-by: Jagan Teki diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index de241be..637fea8 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -49,3 +49,4 @@ obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o +obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c new file mode 100644 index 0000000..0ce6127 --- /dev/null +++ b/drivers/spi/zynq_qspi.c @@ -0,0 +1,622 @@ +/* + * (C) Copyright 2013 Xilinx, Inc. + * (C) Copyright 2015 Jagan Teki + * + * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* zynq qspi register bit masks ZYNQ_QSPI___MASK */ +#define ZYNQ_QSPI_CR_IFMODE_MASK (1 << 31) /* Flash intrface mode*/ +#define ZYNQ_QSPI_CR_MSA_MASK (1 << 15) /* Manual start enb */ +#define ZYNQ_QSPI_CR_MCS_MASK (1 << 14) /* Manual chip select */ +#define ZYNQ_QSPI_CR_PCS_MASK (1 << 10) /* Peri chip select */ +#define ZYNQ_QSPI_CR_FW_MASK (0x3 << 6) /* FIFO width */ +#define ZYNQ_QSPI_CR_SS_MASK (0xF << 10) /* Slave Select */ +#define ZYNQ_QSPI_CR_BAUD_MASK (0x7 << 3) /* Baud rate div */ +#define ZYNQ_QSPI_CR_CPHA_MASK (1 << 2) /* Clock phase */ +#define ZYNQ_QSPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */ +#define ZYNQ_QSPI_CR_MSTREN_MASK (1 << 0) /* Mode select */ +#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK (1 << 4) /* RX_FIFO_not_empty */ +#define ZYNQ_QSPI_IXR_TXOW_MASK (1 << 2) /* TX_FIFO_not_full */ +#define ZYNQ_QSPI_IXR_ALL_MASK 0x7F /* All IXR bits */ +#define ZYNQ_QSPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */ + +/* zynq qspi Transmit Data Register */ +#define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */ +#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */ +#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */ +#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */ + +#define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/ +#define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */ + +#define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */ +#define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */ +#define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */ + +#define ZYNQ_QSPI_FIFO_DEPTH 63 +#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT +#define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ +#endif + +/* zynq qspi register set */ +struct zynq_qspi_regs { + u32 cr; /* 0x00 */ + u32 isr; /* 0x04 */ + u32 ier; /* 0x08 */ + u32 idr; /* 0x0C */ + u32 imr; /* 0x10 */ + u32 enr; /* 0x14 */ + u32 dr; /* 0x18 */ + u32 txd0r; /* 0x1C */ + u32 drxr; /* 0x20 */ + u32 sicr; /* 0x24 */ + u32 txftr; /* 0x28 */ + u32 rxftr; /* 0x2C */ + u32 gpior; /* 0x30 */ + u32 reserved0[19]; + u32 txd1r; /* 0x80 */ + u32 txd2r; /* 0x84 */ + u32 txd3r; /* 0x88 */ +}; + +/* zynq qspi platform data */ +struct zynq_qspi_platdata { + struct zynq_qspi_regs *regs; + u32 frequency; /* input frequency */ + u32 speed_hz; +}; + +/* zynq qspi priv */ +struct zynq_qspi_priv { + struct zynq_qspi_regs *regs; + u8 cs; + u8 mode; + u8 fifo_depth; + u32 freq; /* required frequency */ + const void *tx_buf; + void *rx_buf; + unsigned len; + int bytes_to_transfer; + int bytes_to_receive; + unsigned int is_inst; + unsigned cs_change:1; +}; + +static int zynq_qspi_ofdata_to_platdata(struct udevice *bus) +{ + struct zynq_qspi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + + plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob, + node, "reg"); + + /* FIXME: Use 166MHz as a suitable default */ + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", + 166666666); + plat->speed_hz = plat->frequency / 2; + + debug("%s: regs=%p max-frequency=%d\n", __func__, + plat->regs, plat->frequency); + + return 0; +} + +static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) +{ + struct zynq_qspi_regs *regs = priv->regs; + u32 confr; + + /* Disable QSPI */ + writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); + + /* Disable Interrupts */ + writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr); + + /* Clear the TX and RX threshold reg */ + writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, ®s->txftr); + writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr); + + /* Clear the RX FIFO */ + while (readl(®s->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK) + readl(®s->drxr); + + /* Clear Interrupts */ + writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->isr); + + /* Manual slave select and Auto start */ + confr = readl(®s->cr); + confr &= ~ZYNQ_QSPI_CR_MSA_MASK; + confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK | + ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK | + ZYNQ_QSPI_CR_MSTREN_MASK; + writel(confr, ®s->cr); + + /* Enable SPI */ + writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); +} + +static int zynq_qspi_probe(struct udevice *bus) +{ + struct zynq_qspi_platdata *plat = dev_get_platdata(bus); + struct zynq_qspi_priv *priv = dev_get_priv(bus); + + priv->regs = plat->regs; + priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH; + + /* init the zynq spi hw */ + zynq_qspi_init_hw(priv); + + return 0; +} + +/* + * zynq_qspi_read_data - Copy data to RX buffer + * @zqspi: Pointer to the zynq_qspi structure + * @data: The 32 bit variable where data is stored + * @size: Number of bytes to be copied from data to RX buffer + */ +static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size) +{ + u8 byte3; + + debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ , + data, (unsigned)(priv->rx_buf), size); + + if (priv->rx_buf) { + switch (size) { + case 1: + *((u8 *)priv->rx_buf) = data; + priv->rx_buf += 1; + break; + case 2: + *((u16 *)priv->rx_buf) = data; + priv->rx_buf += 2; + break; + case 3: + *((u16 *)priv->rx_buf) = data; + priv->rx_buf += 2; + byte3 = (u8)(data >> 16); + *((u8 *)priv->rx_buf) = byte3; + priv->rx_buf += 1; + break; + case 4: + /* Can not assume word aligned buffer */ + memcpy(priv->rx_buf, &data, size); + priv->rx_buf += 4; + break; + default: + /* This will never execute */ + break; + } + } + priv->bytes_to_receive -= size; + if (priv->bytes_to_receive < 0) + priv->bytes_to_receive = 0; +} + +/* + * zynq_qspi_write_data - Copy data from TX buffer + * @zqspi: Pointer to the zynq_qspi structure + * @data: Pointer to the 32 bit variable where data is to be copied + * @size: Number of bytes to be copied from TX buffer to data + */ +static void zynq_qspi_write_data(struct zynq_qspi_priv *priv, + u32 *data, u8 size) +{ + if (priv->tx_buf) { + switch (size) { + case 1: + *data = *((u8 *)priv->tx_buf); + priv->tx_buf += 1; + *data |= 0xFFFFFF00; + break; + case 2: + *data = *((u16 *)priv->tx_buf); + priv->tx_buf += 2; + *data |= 0xFFFF0000; + break; + case 3: + *data = *((u16 *)priv->tx_buf); + priv->tx_buf += 2; + *data |= (*((u8 *)priv->tx_buf) << 16); + priv->tx_buf += 1; + *data |= 0xFF000000; + break; + case 4: + /* Can not assume word aligned buffer */ + memcpy(data, priv->tx_buf, size); + priv->tx_buf += 4; + break; + default: + /* This will never execute */ + break; + } + } else { + *data = 0; + } + + debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__, + *data, (u32)priv->tx_buf, size); + + priv->bytes_to_transfer -= size; + if (priv->bytes_to_transfer < 0) + priv->bytes_to_transfer = 0; +} + +static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on) +{ + u32 confr; + struct zynq_qspi_regs *regs = priv->regs; + + confr = readl(®s->cr); + + if (is_on) { + /* Select the slave */ + confr &= ~ZYNQ_QSPI_CR_SS_MASK; + confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) & + ZYNQ_QSPI_CR_SS_MASK; + } else + /* Deselect the slave */ + confr |= ZYNQ_QSPI_CR_SS_MASK; + + writel(confr, ®s->cr); +} + +/* + * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible + * @zqspi: Pointer to the zynq_qspi structure + */ +static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size) +{ + u32 data = 0; + u32 fifocount = 0; + unsigned len, offset; + struct zynq_qspi_regs *regs = priv->regs; + static const unsigned offsets[4] = { + ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET, + ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET }; + + while ((fifocount < size) && + (priv->bytes_to_transfer > 0)) { + if (priv->bytes_to_transfer >= 4) { + if (priv->tx_buf) { + memcpy(&data, priv->tx_buf, 4); + priv->tx_buf += 4; + } else { + data = 0; + } + writel(data, ®s->txd0r); + priv->bytes_to_transfer -= 4; + fifocount++; + } else { + /* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */ + if (!(readl(®s->isr) + & ZYNQ_QSPI_IXR_TXOW_MASK) && + !priv->rx_buf) + return; + len = priv->bytes_to_transfer; + zynq_qspi_write_data(priv, &data, len); + offset = (priv->rx_buf) ? offsets[0] : offsets[len]; + writel(data, ®s->cr + (offset / 4)); + } + } +} + +/* + * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller + * @zqspi: Pointer to the zynq_qspi structure + * + * This function handles TX empty and Mode Fault interrupts only. + * On TX empty interrupt this function reads the received data from RX FIFO and + * fills the TX FIFO if there is any data remaining to be transferred. + * On Mode Fault interrupt this function indicates that transfer is completed, + * the SPI subsystem will identify the error as the remaining bytes to be + * transferred is non-zero. + * + * returns: 0 for poll timeout + * 1 transfer operation complete + */ +static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv) +{ + struct zynq_qspi_regs *regs = priv->regs; + u32 rxindex = 0; + u32 rxcount; + u32 status, timeout; + + /* Poll until any of the interrupt status bits are set */ + timeout = get_timer(0); + do { + status = readl(®s->isr); + } while ((status == 0) && + (get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT)); + + if (status == 0) { + printf("zynq_qspi_irq_poll: Timeout!\n"); + return -ETIMEDOUT; + } + + writel(status, ®s->isr); + + /* Disable all interrupts */ + writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr); + if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) || + (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) { + /* + * This bit is set when Tx FIFO has < THRESHOLD entries. We have + * the THRESHOLD value set to 1, so this bit indicates Tx FIFO + * is empty + */ + rxcount = priv->bytes_to_receive - priv->bytes_to_transfer; + rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4); + while ((rxindex < rxcount) && + (rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) { + /* Read out the data from the RX FIFO */ + u32 data; + data = readl(®s->drxr); + + if (priv->bytes_to_receive >= 4) { + if (priv->rx_buf) { + memcpy(priv->rx_buf, &data, 4); + priv->rx_buf += 4; + } + priv->bytes_to_receive -= 4; + } else { + zynq_qspi_read_data(priv, data, + priv->bytes_to_receive); + } + rxindex++; + } + + if (priv->bytes_to_transfer) { + /* There is more data to send */ + zynq_qspi_fill_tx_fifo(priv, + ZYNQ_QSPI_RXFIFO_THRESHOLD); + + writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier); + } else { + /* + * If transfer and receive is completed then only send + * complete signal + */ + if (!priv->bytes_to_receive) { + /* return operation complete */ + writel(ZYNQ_QSPI_IXR_ALL_MASK, + ®s->idr); + return 1; + } + } + } + + return 0; +} + +/* + * zynq_qspi_start_transfer - Initiates the QSPI transfer + * @qspi: Pointer to the spi_device structure + * @transfer: Pointer to the spi_transfer structure which provide information + * about next transfer parameters + * + * This function fills the TX FIFO, starts the QSPI transfer, and waits for the + * transfer to be completed. + * + * returns: Number of bytes transferred in the last transfer + */ +static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv) +{ + u32 data = 0; + struct zynq_qspi_regs *regs = priv->regs; + + debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__, + (u32)priv, (u32)priv, priv->len); + + priv->bytes_to_transfer = priv->len; + priv->bytes_to_receive = priv->len; + + if (priv->len < 4) + zynq_qspi_fill_tx_fifo(priv, priv->len); + else + zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth); + + writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier); + /* Start the transfer by enabling manual start bit */ + + /* wait for completion */ + do { + data = zynq_qspi_irq_poll(priv); + } while (data == 0); + + return (priv->len) - (priv->bytes_to_transfer); +} + +static int zynq_qspi_transfer(struct zynq_qspi_priv *priv) +{ + unsigned cs_change = 1; + int status = 0; + + while (1) { + /* Select the chip if required */ + if (cs_change) + zynq_qspi_chipselect(priv, 1); + + cs_change = priv->cs_change; + + if (!priv->tx_buf && !priv->rx_buf && priv->len) { + status = -1; + break; + } + + /* Request the transfer */ + if (priv->len) { + status = zynq_qspi_start_transfer(priv); + priv->is_inst = 0; + } + + if (status != priv->len) { + if (status > 0) + status = -EMSGSIZE; + debug("zynq_qspi_transfer:%d len:%d\n", + status, priv->len); + break; + } + status = 0; + + if (cs_change) + /* Deselect the chip */ + zynq_qspi_chipselect(priv, 0); + + break; + } + + return 0; +} + +static int zynq_qspi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct zynq_qspi_priv *priv = dev_get_priv(bus); + struct zynq_qspi_regs *regs = priv->regs; + + writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); + + return 0; +} + +static int zynq_qspi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct zynq_qspi_priv *priv = dev_get_priv(bus); + struct zynq_qspi_regs *regs = priv->regs; + + writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); + + return 0; +} + +static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct zynq_qspi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + + priv->cs = slave_plat->cs; + priv->tx_buf = dout; + priv->rx_buf = din; + priv->len = bitlen / 8; + + debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n", + bus->seq, slave_plat->cs, bitlen, priv->len, flags); + + /* + * Festering sore. + * Assume that the beginning of a transfer with bits to + * transmit must contain a device command. + */ + if (dout && flags & SPI_XFER_BEGIN) + priv->is_inst = 1; + else + priv->is_inst = 0; + + if (flags & SPI_XFER_END) + priv->cs_change = 1; + else + priv->cs_change = 0; + + zynq_qspi_transfer(priv); + + return 0; +} + +static int zynq_qspi_set_speed(struct udevice *bus, uint speed) +{ + struct zynq_qspi_platdata *plat = bus->platdata; + struct zynq_qspi_priv *priv = dev_get_priv(bus); + struct zynq_qspi_regs *regs = priv->regs; + uint32_t confr; + u8 baud_rate_val = 0; + + if (speed > plat->frequency) + speed = plat->frequency; + + /* Set the clock frequency */ + confr = readl(®s->cr); + if (speed == 0) { + /* Set baudrate x8, if the freq is 0 */ + baud_rate_val = 0x2; + } else if (plat->speed_hz != speed) { + while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) && + ((plat->frequency / + (2 << baud_rate_val)) > speed)) + baud_rate_val++; + + plat->speed_hz = speed / (2 << baud_rate_val); + } + confr &= ~ZYNQ_QSPI_CR_BAUD_MASK; + confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT); + + writel(confr, ®s->cr); + priv->freq = speed; + + debug("zynq_spi_set_speed: regs=%p, mode=%d\n", priv->regs, priv->freq); + + return 0; +} + +static int zynq_qspi_set_mode(struct udevice *bus, uint mode) +{ + struct zynq_qspi_priv *priv = dev_get_priv(bus); + struct zynq_qspi_regs *regs = priv->regs; + uint32_t confr; + + /* Set the SPI Clock phase and polarities */ + confr = readl(®s->cr); + confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK); + + if (priv->mode & SPI_CPHA) + confr |= ZYNQ_QSPI_CR_CPHA_MASK; + if (priv->mode & SPI_CPOL) + confr |= ZYNQ_QSPI_CR_CPOL_MASK; + + writel(confr, ®s->cr); + priv->mode = mode; + + debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode); + + return 0; +} + +static const struct dm_spi_ops zynq_qspi_ops = { + .claim_bus = zynq_qspi_claim_bus, + .release_bus = zynq_qspi_release_bus, + .xfer = zynq_qspi_xfer, + .set_speed = zynq_qspi_set_speed, + .set_mode = zynq_qspi_set_mode, +}; + +static const struct udevice_id zynq_qspi_ids[] = { + { .compatible = "xlnx,zynq-qspi-1.0" }, + { } +}; + +U_BOOT_DRIVER(zynq_qspi) = { + .name = "zynq_qspi", + .id = UCLASS_SPI, + .of_match = zynq_qspi_ids, + .ops = &zynq_qspi_ops, + .ofdata_to_platdata = zynq_qspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct zynq_qspi_platdata), + .priv_auto_alloc_size = sizeof(struct zynq_qspi_priv), + .probe = zynq_qspi_probe, +}; -- cgit v0.10.2 From 70676cb3b503bea970eb4e1dd7ea902ec8ac2ea1 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 15 Aug 2015 23:02:31 +0530 Subject: dts: zynq: Add zynq qspi controller nodes This patch adds zynq qspi controller nodes in zynq-7000.dtsi. Signed-off-by: Jagan Teki Cc: Simon Glass Cc: Siva Durga Prasad Paladugu Acked-by: Michal Simek Tested-by: Jagan Teki diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 0b62cb0..84c15b5 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -191,6 +191,18 @@ #size-cells = <0>; }; + qspi: spi@e000d000 { + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,zynq-qspi-1.0"; + status = "disabled"; + interrupt-parent = <&intc>; + interrupts = <0 19 4>; + reg = <0xe000d000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; -- cgit v0.10.2 From e5e7c747a0d591116f3418b071d2bb3629eafe56 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 15 Aug 2015 23:06:56 +0530 Subject: doc: device-tree-bindings: spi: Add zynq qspi info Added device-tree-binding information for zynq qspi controller driver. Signed-off-by: Jagan Teki Cc: Simon Glass Cc: Siva Durga Prasad Paladugu Acked-by: Michal Simek Tested-by: Jagan Teki diff --git a/doc/device-tree-bindings/spi/spi-zynq-qspi.txt b/doc/device-tree-bindings/spi/spi-zynq-qspi.txt new file mode 100644 index 0000000..47472fd --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-zynq-qspi.txt @@ -0,0 +1,26 @@ +Xilinx Zynq QSPI controller Device Tree Bindings +------------------------------------------------- + +Required properties: +- compatible : Should be "xlnx,zynq-qspi-1.0". +- reg : Physical base address and size of QSPI registers map. +- interrupts : Property with a value describing the interrupt + number. +- interrupt-parent : Must be core interrupt controller +- clock-names : List of input clock names - "ref_clk", "pclk" + (See clock bindings for details). +- clocks : Clock phandles (see clock bindings for details). + +Optional properties: +- num-cs : Number of chip selects used. + +Example: + qspi@e000d000 { + compatible = "xlnx,zynq-qspi-1.0"; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 10>, <&clkc 43>; + interrupt-parent = <&intc>; + interrupts = <0 19 4>; + num-cs = <1>; + reg = <0xe000d000 0x1000>; + } ; -- cgit v0.10.2 From 659cc156306561a6115d583e82b49e42ce3af9b2 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 15 Aug 2015 23:08:51 +0530 Subject: dts: microzed: Enable zynq qspi controller node Enabled zynq qspi controller node for microzed board, verified the same on spansion spi-nor flash. Signed-off-by: Jagan Teki Cc: Simon Glass Cc: Siva Durga Prasad Paladugu Acked-by: Michal Simek Tested-by: Jagan Teki diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index c373a2c..d5e0050 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -14,6 +14,7 @@ aliases { serial0 = &uart1; + spi0 = &qspi; }; memory { @@ -21,3 +22,7 @@ reg = <0 0x40000000>; }; }; + +&qspi { + status = "okay"; +}; -- cgit v0.10.2 From e9cf6ec5160d457af1423ffe9ce254754b4cdde5 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 15 Aug 2015 23:15:21 +0530 Subject: dts: zc702: Enable zynq qspi controller node Enabled zynq qspi controller node for zc702 board. Signed-off-by: Jagan Teki Cc: Simon Glass Cc: Siva Durga Prasad Paladugu Acked-by: Michal Simek diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 6691a8d..4d86960 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -17,6 +17,7 @@ ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; }; memory { @@ -380,6 +381,10 @@ pinctrl-0 = <&pinctrl_uart1_default>; }; +&qspi { + status = "okay"; +}; + &usb0 { status = "okay"; dr_mode = "host"; -- cgit v0.10.2 From e94c71c0755531a99ae5950002717878833979b0 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 15 Aug 2015 23:16:21 +0530 Subject: dts: zc706: Enable zynq qspi controller node Enabled zynq qspi controller node for zc706 board. Signed-off-by: Jagan Teki Cc: Simon Glass Cc: Siva Durga Prasad Paladugu Acked-by: Michal Simek diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index cf7bce4..fc336ea 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -17,6 +17,7 @@ ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; }; memory { @@ -301,6 +302,10 @@ pinctrl-0 = <&pinctrl_uart1_default>; }; +&qspi { + status = "okay"; +}; + &usb0 { status = "okay"; dr_mode = "host"; -- cgit v0.10.2 From 7b0d3459818f0823783d286d52ec523a293756ab Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 4 Sep 2015 12:49:49 +0530 Subject: dts: zc770-xm010: Enable zynq qspi controller node Enabled zynq qspi controller node for zc770-xm010 board. => sf probe 0 -- bus1 for selecting qspi controller => sf probe 1 -- bus0 for selecting spi controller Signed-off-by: Jagan Teki Cc: Simon Glass Cc: Siva Durga Prasad Paladugu Acked-by: Michal Simek diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 680f24c..cf56ac8 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -16,7 +16,8 @@ ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; - spi0 = &spi1; + spi0 = &qspi; + spi1 = &spi1; }; chosen { @@ -53,6 +54,10 @@ }; }; +&qspi { + status = "okay"; +}; + &can0 { status = "okay"; }; -- cgit v0.10.2 From 976dfb0fd884fa13e4e64c7ded4322ffd9967df4 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 15 Aug 2015 23:19:05 +0530 Subject: dts: zed: Enable zynq qspi controller node Enabled zynq qspi controller node for zed board. Signed-off-by: Jagan Teki Cc: Simon Glass Cc: Siva Durga Prasad Paladugu Acked-by: Michal Simek diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 5762576..3630490 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -16,6 +16,7 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; }; memory { @@ -56,6 +57,10 @@ status = "okay"; }; +&qspi { + status = "okay"; +}; + &usb0 { status = "okay"; dr_mode = "host"; -- cgit v0.10.2 From 73193b01c5d7222d4be84091d105a10f58d02549 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Aug 2015 17:36:03 +0530 Subject: configs: Enable legacy SPI flash interface support Enable legacy spi-flash interface support for boards which supports qspi controller with connected spi-nor flash. Signed-off-by: Jagan Teki Cc: Simon Glass Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Tested-by: Jagan Teki diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index e9c3209..130851e 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -11,3 +11,4 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPI_FLASH=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 0abb7a8..db2e92c 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -10,3 +10,4 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPI_FLASH=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index d67f507..87158ab 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -11,3 +11,4 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPI_FLASH=y diff --git a/configs/zynq_zc70x_defconfig b/configs/zynq_zc70x_defconfig index 37c249f..4f10c8a 100644 --- a/configs/zynq_zc70x_defconfig +++ b/configs/zynq_zc70x_defconfig @@ -11,3 +11,4 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPI_FLASH=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 886b4a5..0f99975 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -11,3 +11,4 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPI_FLASH=y -- cgit v0.10.2 From a241d4ecab6f6e10336e91bbd317feeb0ff73941 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 17 Aug 2015 18:55:02 +0530 Subject: zynq-common: Enable zynq qspi controller support This patch adds support for zynq qspi controller driver on zynq-common.h Signed-off-by: Jagan Teki Cc: Simon Glass Cc: Siva Durga Prasad Paladugu Acked-by: Michal Simek Tested-by: Jagan Teki diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 66b1e69..3910ae9 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -72,6 +72,15 @@ # define CONFIG_CMD_SF #endif +/* QSPI */ +#ifdef CONFIG_ZYNQ_QSPI +# define CONFIG_SF_DEFAULT_SPEED 30000000 +# define CONFIG_SPI_FLASH_SPANSION +# define CONFIG_SPI_FLASH_STMICRO +# define CONFIG_SPI_FLASH_WINBOND +# define CONFIG_CMD_SF +#endif + /* NOR */ #ifndef CONFIG_SYS_NO_FLASH # define CONFIG_SYS_FLASH_BASE 0xE2000000 -- cgit v0.10.2 From 9a7620916d6234da29e766446b35a019615dc767 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 17 Aug 2015 18:56:38 +0530 Subject: zynq-common: Enable Bank/Extended address register support Enabled SPI flash Bank/Extended address register support. Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. Signed-off-by: Jagan Teki diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 3910ae9..cac76d2 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -78,6 +78,7 @@ # define CONFIG_SPI_FLASH_SPANSION # define CONFIG_SPI_FLASH_STMICRO # define CONFIG_SPI_FLASH_WINBOND +# define CONFIG_SPI_FLASH_BAR # define CONFIG_CMD_SF #endif -- cgit v0.10.2 From 38a41675db949d86bfde2299a3eaebb4e105d8c1 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Aug 2015 17:38:40 +0530 Subject: configs: zynq: Enable zynq qspi controller Enable zynq qspi controller driver on respective zynq boards. Signed-off-by: Jagan Teki Cc: Simon Glass Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Tested-by: Jagan Teki diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 130851e..9cb2ca1 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -12,3 +12,4 @@ CONFIG_FIT_SIGNATURE=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index db2e92c..c4922f3 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -11,3 +11,4 @@ CONFIG_FIT_SIGNATURE=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 87158ab..b4c076c 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -12,3 +12,4 @@ CONFIG_FIT_SIGNATURE=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc70x_defconfig b/configs/zynq_zc70x_defconfig index 4f10c8a..97f8a5d 100644 --- a/configs/zynq_zc70x_defconfig +++ b/configs/zynq_zc70x_defconfig @@ -12,3 +12,4 @@ CONFIG_FIT_SIGNATURE=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 0e826bb..61106df 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -13,3 +13,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 0f99975..5e128fb 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -12,3 +12,4 @@ CONFIG_FIT_SIGNATURE=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_ZYNQ_QSPI=y -- cgit v0.10.2 From 78a025ace8124a36e475251916d46cbdd029c5bb Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sun, 16 Aug 2015 00:19:38 +0530 Subject: spi: Kconfig: Add Zynq QSPI controller entry Add Zynq QSPI controller Kconfig entry. Signed-off-by: Jagan Teki Reviewed-by: Simon Glass Acked-by: Michal Simek Cc: Siva Durga Prasad Paladugu diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2f8cf19..7d7a9d0 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -139,6 +139,15 @@ config ZYNQ_SPI access the SPI NOR flash on platforms embedding this Zynq SPI IP core. +config ZYNQ_QSPI + bool "Zynq QSPI driver" + depends on ARCH_ZYNQ + help + Enable the Zynq Quad-SPI (QSPI) driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Zynq QSPI IP core. This IP is used to connect the flash in + 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. + endif # if DM_SPI config FSL_ESPI -- cgit v0.10.2 From 46ab8a6a13bdc18f64d745e829d75f61e8625c2c Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 17 Aug 2015 18:25:03 +0530 Subject: spi: zynq_spi: Add config reg shift named macros Update the numerical values for baudrate and chipselect with config reg shift named macro's Signed-off-by: Jagan Teki diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index d370e49..293499c 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -32,6 +32,10 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ #define ZYNQ_SPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */ +#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */ +#define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */ +#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */ + #define ZYNQ_SPI_FIFO_DEPTH 128 #ifndef CONFIG_SYS_ZYNQ_SPI_WAIT #define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ @@ -143,7 +147,7 @@ static void spi_cs_activate(struct udevice *dev, uint cs) * xx01 - cs1 * x011 - cs2 */ - cr |= (~(0x1 << cs) << 10) & ZYNQ_SPI_CR_CS_MASK; + cr |= (~(0x1 << cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; writel(cr, ®s->cr); } @@ -260,14 +264,14 @@ static int zynq_spi_set_speed(struct udevice *bus, uint speed) /* Set baudrate x8, if the freq is 0 */ baud_rate_val = 0x2; } else if (plat->speed_hz != speed) { - while ((baud_rate_val < 8) && + while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) && ((plat->frequency / (2 << baud_rate_val)) > speed)) baud_rate_val++; plat->speed_hz = speed / (2 << baud_rate_val); } confr &= ~ZYNQ_SPI_CR_BRD_MASK; - confr |= (baud_rate_val << 3); + confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT); writel(confr, ®s->cr); priv->freq = speed; -- cgit v0.10.2 From dda6241a1dc7fafd878e016acff9f1fb019c4f6e Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 17 Aug 2015 18:27:47 +0530 Subject: spi: zynq_spi: Rename baudrate divisor mask name Rename ZYNQ_SPI_CR_BRD_MASK to ZYNQ_SPI_CR_BAUD_MASK for more readable. Signed-off-by: Jagan Teki diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 293499c..04d4b71 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_SPI_CR_MSA_MASK (1 << 15) /* Manual start enb */ #define ZYNQ_SPI_CR_MCS_MASK (1 << 14) /* Manual chip select */ #define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */ -#define ZYNQ_SPI_CR_BRD_MASK (0x7 << 3) /* Baud rate div */ +#define ZYNQ_SPI_CR_BAUD_MASK (0x7 << 3) /* Baud rate div */ #define ZYNQ_SPI_CR_CPHA_MASK (1 << 2) /* Clock phase */ #define ZYNQ_SPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */ #define ZYNQ_SPI_CR_MSTREN_MASK (1 << 0) /* Mode select */ @@ -270,7 +270,7 @@ static int zynq_spi_set_speed(struct udevice *bus, uint speed) baud_rate_val++; plat->speed_hz = speed / (2 << baud_rate_val); } - confr &= ~ZYNQ_SPI_CR_BRD_MASK; + confr &= ~ZYNQ_SPI_CR_BAUD_MASK; confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT); writel(confr, ®s->cr); -- cgit v0.10.2 From 191269987c3c9ee4943ffa29d078999362342966 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 17 Aug 2015 18:31:39 +0530 Subject: spi: zynq_spi: Store cs value into private data Store cs value into private data and use it while activating chipselect instead of passing through function. Signed-off-by: Jagan Teki diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 04d4b71..65a9633 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -65,6 +65,7 @@ struct zynq_spi_platdata { /* zynq spi priv */ struct zynq_spi_priv { struct zynq_spi_regs *regs; + u8 cs; u8 mode; u8 fifo_depth; u32 freq; /* required frequency */ @@ -132,7 +133,7 @@ static int zynq_spi_probe(struct udevice *bus) return 0; } -static void spi_cs_activate(struct udevice *dev, uint cs) +static void spi_cs_activate(struct udevice *dev) { struct udevice *bus = dev->parent; struct zynq_spi_priv *priv = dev_get_priv(bus); @@ -147,7 +148,7 @@ static void spi_cs_activate(struct udevice *dev, uint cs) * xx01 - cs1 * x011 - cs2 */ - cr |= (~(0x1 << cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; + cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; writel(cr, ®s->cr); } @@ -203,8 +204,9 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen, return -1; } + priv->cs = slave_plat->cs; if (flags & SPI_XFER_BEGIN) - spi_cs_activate(dev, slave_plat->cs); + spi_cs_activate(dev); while (rx_len > 0) { /* Write the data into TX FIFO - tx threshold is fifo_depth */ -- cgit v0.10.2 From 24ea6ac892b98e5093402f863cd70aa4985298a1 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 4 Sep 2015 18:25:45 +0530 Subject: sf: params: Add IS25LP032 part support Added support for IS25LP032 flash part. Signed-off-by: Jagan Teki Cc: Siva Durga Prasad Paladugu Cc: Michal Simek diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 8f5bdda..43fb555 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -35,6 +35,9 @@ const struct spi_flash_params spi_flash_params_table[] = { {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, #endif +#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ + {"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, RD_NORM, 0}, +#endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0}, {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0}, -- cgit v0.10.2 From 65a75b6f7a96e3db962005f9e29e6f847e5c64c0 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 4 Sep 2015 18:27:58 +0530 Subject: sf: params: Add IS25LP064 part support Added support for IS25LP064 flash part. Signed-off-by: Jagan Teki Cc: Siva Durga Prasad Paladugu Cc: Michal Simek diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 43fb555..44863ac 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -37,6 +37,7 @@ const struct spi_flash_params spi_flash_params_table[] = { #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ {"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, RD_NORM, 0}, + {"IS25LP064", 0x9d6017, 0x0, 64 * 1024, 128, RD_NORM, 0}, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0}, -- cgit v0.10.2 From 720e5e54ebc81ddbee171dbd1bab4e394b97fb81 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 4 Sep 2015 18:29:12 +0530 Subject: sf: params: Add IS25LP128 part support Added support for IS25LP128 flash part. Signed-off-by: Jagan Teki Cc: Siva Durga Prasad Paladugu Cc: Michal Simek diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 44863ac..4f37e33 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -38,6 +38,7 @@ const struct spi_flash_params spi_flash_params_table[] = { #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ {"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, RD_NORM, 0}, {"IS25LP064", 0x9d6017, 0x0, 64 * 1024, 128, RD_NORM, 0}, + {"IS25LP128", 0x9d6018, 0x0, 64 * 1024, 256, RD_NORM, 0}, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0}, -- cgit v0.10.2 From 232a8e4ecc21c8ee4c500900c26f706cab60150d Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 4 Sep 2015 18:30:34 +0530 Subject: zynq-common: Enable ISSI SPI-NOR flash support This patch enabled CONFIG_SPI_FLASH_ISSI for qspi on zynq boards. Signed-off-by: Jagan Teki Cc: Siva Durga Prasad Paladugu Cc: Michal Simek diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index cac76d2..acb8670 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -75,6 +75,7 @@ /* QSPI */ #ifdef CONFIG_ZYNQ_QSPI # define CONFIG_SF_DEFAULT_SPEED 30000000 +# define CONFIG_SPI_FLASH_ISSI # define CONFIG_SPI_FLASH_SPANSION # define CONFIG_SPI_FLASH_STMICRO # define CONFIG_SPI_FLASH_WINBOND -- cgit v0.10.2 From 2775e91835638031d1134176d536ac2946fc5e6b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 8 Sep 2015 01:39:44 +0530 Subject: spi: zynq_qspi: Fix to configure CPOL, CPHA mask priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 0ce6127..8aa61d7 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -569,7 +569,8 @@ static int zynq_qspi_set_speed(struct udevice *bus, uint speed) writel(confr, ®s->cr); priv->freq = speed; - debug("zynq_spi_set_speed: regs=%p, mode=%d\n", priv->regs, priv->freq); + debug("zynq_spi_set_speed: regs=%p, speed=%d\n", + priv->regs, priv->freq); return 0; } @@ -584,9 +585,9 @@ static int zynq_qspi_set_mode(struct udevice *bus, uint mode) confr = readl(®s->cr); confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK); - if (priv->mode & SPI_CPHA) + if (mode & SPI_CPHA) confr |= ZYNQ_QSPI_CR_CPHA_MASK; - if (priv->mode & SPI_CPOL) + if (mode & SPI_CPOL) confr |= ZYNQ_QSPI_CR_CPOL_MASK; writel(confr, ®s->cr); -- cgit v0.10.2 From 8e0e01d330e76ec2b8db4da3fa5cb425603507f9 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 14 Sep 2015 12:59:08 +0530 Subject: zynq-common: Add SPL SPI offset, size configs Define CONFIG_SYS_SPI_ARGS_OFFS, CONFIG_SYS_SPI_ARGS_SIZE and CONFIG_SYS_SPI_KERNEL_OFFS which will be used in SPL spi mode. These macros defines the device tree offset, size and the kernel image offset in flash respectively. Signed-off-by: Siva Durga Prasad Paladugu Reviewed-by: Jagan Teki diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index acb8670..ca5ef04 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -355,6 +355,10 @@ #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 +#define CONFIG_SYS_SPI_ARGS_OFFS 0x200000 +#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 +#define CONFIG_SYS_SPI_KERNEL_OFFS (CONFIG_SYS_SPI_ARGS_OFFS + \ + CONFIG_SYS_SPI_ARGS_SIZE) #endif /* for booting directly linux */ -- cgit v0.10.2 From 86e99b98614258de2b46bc6d58fbbf8c64a0900f Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 2 Sep 2015 11:39:45 +0530 Subject: spi: zynq_spi: Remove unneeded headers - Removed unneeded inclusion of header files - Add "Xilinx" on license text Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Signed-off-by: Jagan Teki diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 65a9633..33a13bf 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013 Inc. + * (C) Copyright 2013 Xilinx, Inc. * (C) Copyright 2015 Jagan Teki * * Xilinx Zynq PS SPI controller driver (master mode only) @@ -7,15 +7,11 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include -#include #include #include -#include #include -#include DECLARE_GLOBAL_DATA_PTR; -- cgit v0.10.2 From 3c75ade2b38ea987b79b7ef74d64301b49aa306d Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 2 Sep 2015 11:39:46 +0530 Subject: sf: Return bank_sel, if flash->bank_curr == bank_sel If computed bank_sel is same as flash->bank_curr which is computed at probe time, then return the bank_sel instead of zero. Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Signed-off-by: Jagan Teki diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 900ec1f..b33fe5a 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -102,7 +102,7 @@ static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) if (flash->bank_curr == bank_sel) { debug("SF: not require to enable bank%d\n", bank_sel); - return 0; + return bank_sel; } cmd = flash->bank_write_cmd; -- cgit v0.10.2 From 234a9e1c605c45748c7a9503e4424c405738fb0c Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 2 Sep 2015 11:39:47 +0530 Subject: sf: Add spi_flash_read_bar Add spi_flash_read_bar function for reading bar and discovering bar commands at probe time. Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Signed-off-by: Jagan Teki diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 954376d..f17ec17 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -99,6 +99,37 @@ static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0) } } +#ifdef CONFIG_SPI_FLASH_BAR +static int spi_flash_read_bank(struct spi_flash *flash, u8 idcode0) +{ + u8 curr_bank = 0; + int ret; + + if (flash->size <= SPI_FLASH_16MB_BOUN) + goto bank_end; + + switch (idcode0) { + case SPI_FLASH_CFI_MFR_SPANSION: + flash->bank_read_cmd = CMD_BANKADDR_BRRD; + flash->bank_write_cmd = CMD_BANKADDR_BRWR; + default: + flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; + flash->bank_write_cmd = CMD_EXTNADDR_WREAR; + } + + ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1, + &curr_bank, 1); + if (ret) { + debug("SF: fail to read bank addr register\n"); + return ret; + } + +bank_end: + flash->bank_curr = curr_bank; + return 0; +} +#endif + static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, struct spi_flash *flash) { @@ -235,25 +266,9 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, /* Configure the BAR - discover bank cmds and read current bank */ #ifdef CONFIG_SPI_FLASH_BAR - u8 curr_bank = 0; - if (flash->size > SPI_FLASH_16MB_BOUN) { - int ret; - - flash->bank_read_cmd = (idcode[0] == 0x01) ? - CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR; - flash->bank_write_cmd = (idcode[0] == 0x01) ? - CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR; - - ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1, - &curr_bank, 1); - if (ret) { - debug("SF: fail to read bank addr register\n"); - return ret; - } - flash->bank_curr = curr_bank; - } else { - flash->bank_curr = curr_bank; - } + int ret = spi_flash_read_bank(flash, idcode[0]); + if (ret < 0) + return ret; #endif /* Flash powers up read-only, so clear BP# bits */ -- cgit v0.10.2 From 70ccf5940650a2c37cc9d70ce3c866abe97e9eb5 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 2 Sep 2015 11:39:48 +0530 Subject: sf: Optimize BAR write code Optimized spi-flash bar writing code and also removed unnecessary bank_sel in read_ops. Cc: Simon Glass Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Signed-off-by: Jagan Teki diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index b33fe5a..6e457ec 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -95,15 +95,14 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc) #endif #ifdef CONFIG_SPI_FLASH_BAR -static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) +static int spi_flash_write_bank(struct spi_flash *flash, u32 offset) { - u8 cmd; + u8 cmd, bank_sel; int ret; - if (flash->bank_curr == bank_sel) { - debug("SF: not require to enable bank%d\n", bank_sel); - return bank_sel; - } + bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); + if (bank_sel == flash->bank_curr) + goto bar_end; cmd = flash->bank_write_cmd; ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); @@ -111,25 +110,10 @@ static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) debug("SF: fail to write bank register\n"); return ret; } - flash->bank_curr = bank_sel; - - return 0; -} - -static int spi_flash_bank(struct spi_flash *flash, u32 offset) -{ - u8 bank_sel; - int ret; - - bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); - - ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); - if (ret) { - debug("SF: fail to set bank%d\n", bank_sel); - return ret; - } - return bank_sel; +bar_end: + flash->bank_curr = bank_sel; + return flash->bank_curr; } #endif @@ -285,7 +269,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) spi_flash_dual_flash(flash, &erase_addr); #endif #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_bank(flash, erase_addr); + ret = spi_flash_write_bank(flash, erase_addr); if (ret < 0) return ret; #endif @@ -327,7 +311,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, spi_flash_dual_flash(flash, &write_addr); #endif #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_bank(flash, write_addr); + ret = spi_flash_write_bank(flash, write_addr); if (ret < 0) return ret; #endif @@ -422,9 +406,10 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, spi_flash_dual_flash(flash, &read_addr); #endif #ifdef CONFIG_SPI_FLASH_BAR - bank_sel = spi_flash_bank(flash, read_addr); - if (bank_sel < 0) + ret = spi_flash_write_bank(flash, read_addr); + if (ret < 0) return ret; + bank_sel = flash->bank_curr; #endif remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * (bank_sel + 1)) - offset; -- cgit v0.10.2 From 1fabefddfce1bc79a3d704501efdaa053442b8c1 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Sep 2015 11:17:02 +0530 Subject: sf: Make flash->flags use for generic usage Use the flash->flags for generic usage, not only for dm-spi-flash, this will be used for future flag additions. [Correct the spi flash flags detect logic] Signed-off-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Jagan Teki diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 9c95d56..53998fc 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -51,6 +51,10 @@ enum { #define SST_WR (SST_BP | SST_WP) +enum spi_nor_option_flags { + SNOR_F_SST_WR = (1 << 0), +}; + #define SPI_FLASH_3B_ADDR_LEN 3 #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) #define SPI_FLASH_16MB_BOUN 0x1000000 diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index f17ec17..2634e90 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -163,15 +163,15 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, flash->name = params->name; flash->memory_map = spi->memory_map; flash->dual_flash = flash->spi->option; -#ifdef CONFIG_DM_SPI_FLASH - flash->flags = params->flags; -#endif /* Assign spi_flash ops */ #ifndef CONFIG_DM_SPI_FLASH flash->write = spi_flash_cmd_write_ops; #if defined(CONFIG_SPI_FLASH_SST) - if (params->flags & SST_WR) { + if (params->flags & SST_WR) + flash->flags |= SNOR_F_SST_WR; + + if (params->flags & SNOR_F_SST_WR) { if (flash->spi->op_mode_tx & SPI_OPM_TX_BP) flash->write = sst_write_bp; else @@ -466,7 +466,7 @@ int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len, struct spi_flash *flash = dev_get_uclass_priv(dev); #if defined(CONFIG_SPI_FLASH_SST) - if (flash->flags & SST_WR) { + if (flash->flags & SNOR_F_SST_WR) { if (flash->spi->op_mode_tx & SPI_OPM_TX_BP) return sst_write_bp(flash, offset, len, buf); else diff --git a/include/spi_flash.h b/include/spi_flash.h index 3b2d555..8d85468 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -38,10 +38,10 @@ struct spi_slave; * * @spi: SPI slave * @dev: SPI flash device - * @flags: Indication of spi flash flags * @name: Name of SPI flash * @dual_flash: Indicates dual flash memories - dual stacked, parallel * @shift: Flash shift useful in dual parallel + * @flags: Indication of spi flash flags * @size: Total flash size * @page_size: Write (page) size * @sector_size: Sector size @@ -67,11 +67,11 @@ struct spi_flash { struct spi_slave *spi; #ifdef CONFIG_DM_SPI_FLASH struct udevice *dev; - u16 flags; #endif const char *name; u8 dual_flash; u8 shift; + u16 flags; u32 size; u32 page_size; -- cgit v0.10.2 From 4efad20a175119f1a82b58d3197df4c20ae85934 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 2 Sep 2015 11:39:50 +0530 Subject: sf: Update status reg check in spi_flash_cmd_wait_ready Current flash wait_ready logic is not modular to add new register status check, hence updated the status check for adding few more register checks in future. Below are the sf speed runs with 'sf update' on whole flash, 16MiB. => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 59.564s, speed 289262 B/s => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 62.549s, speed 275036 B/s => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 61.276s, speed 284359 B/s Cc: Simon Glass Cc: Marek Vasut Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Cc: Stefan Roese Cc: Tom Warren Cc: Tom Rini Tested-by: Jagan Teki Signed-off-by: Jagan Teki Tested-by: Bin Meng diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 6e457ec..c820d48 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -139,72 +139,27 @@ static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr) } #endif -static int spi_flash_poll_status(struct spi_slave *spi, unsigned long timeout, - u8 cmd, u8 poll_bit) -{ - unsigned long timebase; - unsigned long flags = SPI_XFER_BEGIN; - int ret; - u8 status; - u8 check_status = 0x0; - - if (cmd == CMD_FLAG_STATUS) - check_status = poll_bit; - -#ifdef CONFIG_SF_DUAL_FLASH - if (spi->flags & SPI_XFER_U_PAGE) - flags |= SPI_XFER_U_PAGE; -#endif - ret = spi_xfer(spi, 8, &cmd, NULL, flags); - if (ret) { - debug("SF: fail to read %s status register\n", - cmd == CMD_READ_STATUS ? "read" : "flag"); - return ret; - } - - timebase = get_timer(0); - do { - WATCHDOG_RESET(); - - ret = spi_xfer(spi, 8, NULL, &status, 0); - if (ret) - return -1; - - if ((status & poll_bit) == check_status) - break; - - } while (get_timer(timebase) < timeout); - - spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); - - if ((status & poll_bit) == check_status) - return 0; - - /* Timed out */ - debug("SF: time out!\n"); - return -1; -} - int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) { - struct spi_slave *spi = flash->spi; - int ret; - u8 poll_bit = STATUS_WIP; - u8 cmd = CMD_READ_STATUS; + u8 sr; + int timebase, ret; - ret = spi_flash_poll_status(spi, timeout, cmd, poll_bit); - if (ret < 0) - return ret; + timebase = get_timer(0); - if (flash->poll_cmd == CMD_FLAG_STATUS) { - poll_bit = STATUS_PEC; - cmd = CMD_FLAG_STATUS; - ret = spi_flash_poll_status(spi, timeout, cmd, poll_bit); + while (get_timer(timebase) < timeout) { + ret = spi_flash_cmd_read_status(flash, &sr); if (ret < 0) return ret; + + if (!(sr & STATUS_WIP)) + return 0; + else + break; } - return 0; + printf("SF: Timeout!\n"); + + return -ETIMEDOUT; } int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, -- cgit v0.10.2 From baaaa7539c7511e7e90453ecf0f20d8eaeeb70c6 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Sep 2015 16:54:31 +0530 Subject: sf: Add FSR support to spi_flash_cmd_wait_ready This patch adds flag status register reading support to spi_flash_cmd_wait_ready. Cc: Simon Glass Cc: Marek Vasut Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Cc: Stefan Roese Cc: Tom Warren Cc: Tom Rini Cc: Hou Zhiqiang Tested-by: Jagan Teki Tested-by: Bin Meng Signed-off-by: Jagan Teki diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 53998fc..8a3e5ec 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -53,6 +53,7 @@ enum { enum spi_nor_option_flags { SNOR_F_SST_WR = (1 << 0), + SNOR_F_USE_FSR = (1 << 1), }; #define SPI_FLASH_3B_ADDR_LEN 3 diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index c820d48..f2a9244 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -41,6 +41,20 @@ int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs) return 0; } +static int read_fsr(struct spi_flash *flash, u8 *fsr) +{ + int ret; + const u8 cmd = CMD_FLAG_STATUS; + + ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1); + if (ret < 0) { + debug("SF: fail to read flag status register\n"); + return ret; + } + + return 0; +} + int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws) { u8 cmd; @@ -139,22 +153,60 @@ static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr) } #endif -int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) +static int spi_flash_sr_ready(struct spi_flash *flash) { u8 sr; + int ret; + + ret = spi_flash_cmd_read_status(flash, &sr); + if (ret < 0) + return ret; + + return !(sr & STATUS_WIP); +} + +static int spi_flash_fsr_ready(struct spi_flash *flash) +{ + u8 fsr; + int ret; + + ret = read_fsr(flash, &fsr); + if (ret < 0) + return ret; + + return fsr & STATUS_PEC; +} + +static int spi_flash_ready(struct spi_flash *flash) +{ + int sr, fsr; + + sr = spi_flash_sr_ready(flash); + if (sr < 0) + return sr; + + fsr = 1; + if (flash->flags & SNOR_F_USE_FSR) { + fsr = spi_flash_fsr_ready(flash); + if (fsr < 0) + return fsr; + } + + return sr && fsr; +} + +int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) +{ int timebase, ret; timebase = get_timer(0); while (get_timer(timebase) < timeout) { - ret = spi_flash_cmd_read_status(flash, &sr); + ret = spi_flash_ready(flash); if (ret < 0) return ret; - - if (!(sr & STATUS_WIP)) + if (ret) return 0; - else - break; } printf("SF: Timeout!\n"); diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 2634e90..f591ab1 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -257,11 +257,9 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, flash->dummy_byte = 1; } - /* Poll cmd selection */ - flash->poll_cmd = CMD_READ_STATUS; #ifdef CONFIG_SPI_FLASH_STMICRO if (params->flags & E_FSR) - flash->poll_cmd = CMD_FLAG_STATUS; + flash->flags |= SNOR_F_USE_FSR; #endif /* Configure the BAR - discover bank cmds and read current bank */ diff --git a/include/spi_flash.h b/include/spi_flash.h index 8d85468..4312d3d 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -49,7 +49,6 @@ struct spi_slave; * @bank_read_cmd: Bank read cmd * @bank_write_cmd: Bank write cmd * @bank_curr: Current flash bank - * @poll_cmd: Poll cmd - for flash erase/program * @erase_cmd: Erase cmd 4K, 32K, 64K * @read_cmd: Read cmd - Array Fast, Extn read and quad read. * @write_cmd: Write cmd - page and quad program. @@ -82,7 +81,6 @@ struct spi_flash { u8 bank_write_cmd; u8 bank_curr; #endif - u8 poll_cmd; u8 erase_cmd; u8 read_cmd; u8 write_cmd; -- cgit v0.10.2 From e5e0d68f27eaf1986e4049ff4621e822c281ff79 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sun, 25 Oct 2015 09:31:54 +0530 Subject: spi: zynq_qspi: Minor cleanups - Use __func__ on debug - Removed unnecessary comment - Fix function name in debug as zynq_qspi_xfer instead of spi_xfer Signed-off-by: Jagan Teki diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 8aa61d7..6963c13 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -430,7 +430,6 @@ static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv) zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth); writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier); - /* Start the transfer by enabling manual start bit */ /* wait for completion */ do { @@ -516,7 +515,7 @@ static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen, priv->rx_buf = din; priv->len = bitlen / 8; - debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n", + debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n", bus->seq, slave_plat->cs, bitlen, priv->len, flags); /* @@ -569,8 +568,7 @@ static int zynq_qspi_set_speed(struct udevice *bus, uint speed) writel(confr, ®s->cr); priv->freq = speed; - debug("zynq_spi_set_speed: regs=%p, speed=%d\n", - priv->regs, priv->freq); + debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); return 0; } @@ -593,7 +591,7 @@ static int zynq_qspi_set_mode(struct udevice *bus, uint mode) writel(confr, ®s->cr); priv->mode = mode; - debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode); + debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); return 0; } -- cgit v0.10.2 From 736b4df15d603325f97663a7a4f26f7abf454dcf Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 22 Oct 2015 20:40:16 +0530 Subject: spi: zynq_[q]spi: Use BIT macro Used BIT macro on zynq_spi.c and zynq_qspi.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Michal Simek Acked-by: Siva Durga Prasad Paladugu Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 6963c13..241a363 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -16,20 +16,20 @@ DECLARE_GLOBAL_DATA_PTR; /* zynq qspi register bit masks ZYNQ_QSPI___MASK */ -#define ZYNQ_QSPI_CR_IFMODE_MASK (1 << 31) /* Flash intrface mode*/ -#define ZYNQ_QSPI_CR_MSA_MASK (1 << 15) /* Manual start enb */ -#define ZYNQ_QSPI_CR_MCS_MASK (1 << 14) /* Manual chip select */ -#define ZYNQ_QSPI_CR_PCS_MASK (1 << 10) /* Peri chip select */ +#define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/ +#define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */ +#define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */ +#define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */ #define ZYNQ_QSPI_CR_FW_MASK (0x3 << 6) /* FIFO width */ #define ZYNQ_QSPI_CR_SS_MASK (0xF << 10) /* Slave Select */ #define ZYNQ_QSPI_CR_BAUD_MASK (0x7 << 3) /* Baud rate div */ -#define ZYNQ_QSPI_CR_CPHA_MASK (1 << 2) /* Clock phase */ -#define ZYNQ_QSPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */ -#define ZYNQ_QSPI_CR_MSTREN_MASK (1 << 0) /* Mode select */ -#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK (1 << 4) /* RX_FIFO_not_empty */ -#define ZYNQ_QSPI_IXR_TXOW_MASK (1 << 2) /* TX_FIFO_not_full */ +#define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */ +#define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ +#define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */ +#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ +#define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ #define ZYNQ_QSPI_IXR_ALL_MASK 0x7F /* All IXR bits */ -#define ZYNQ_QSPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */ +#define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ /* zynq qspi Transmit Data Register */ #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */ diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 33a13bf..ce8acb4 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -16,17 +16,17 @@ DECLARE_GLOBAL_DATA_PTR; /* zynq spi register bit masks ZYNQ_SPI___MASK */ -#define ZYNQ_SPI_CR_MSA_MASK (1 << 15) /* Manual start enb */ -#define ZYNQ_SPI_CR_MCS_MASK (1 << 14) /* Manual chip select */ +#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */ +#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */ #define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */ #define ZYNQ_SPI_CR_BAUD_MASK (0x7 << 3) /* Baud rate div */ -#define ZYNQ_SPI_CR_CPHA_MASK (1 << 2) /* Clock phase */ -#define ZYNQ_SPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */ -#define ZYNQ_SPI_CR_MSTREN_MASK (1 << 0) /* Mode select */ -#define ZYNQ_SPI_IXR_RXNEMPTY_MASK (1 << 4) /* RX_FIFO_not_empty */ -#define ZYNQ_SPI_IXR_TXOW_MASK (1 << 2) /* TX_FIFO_not_full */ +#define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */ +#define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ +#define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */ +#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ +#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ #define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ -#define ZYNQ_SPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */ +#define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ #define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */ #define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */ -- cgit v0.10.2 From 9cf2ffb3c3721c28f8d6473df0fa8693f5bead7d Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 22 Oct 2015 21:06:37 +0530 Subject: spi: zynq_[q]spi: Use GENMASK macro GENMASK macro used on zynq_spi.c and zynq_qspi.c GENMASK is used to create a contiguous bitmask([hi:lo]). Ex: (0x7 << 3) => GENMASK(5, 3) Cc: Michal Simek Acked-by: Siva Durga Prasad Paladugu Signed-off-by: Jagan Teki diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 241a363..5825c6d 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -20,15 +20,15 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */ #define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */ #define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */ -#define ZYNQ_QSPI_CR_FW_MASK (0x3 << 6) /* FIFO width */ -#define ZYNQ_QSPI_CR_SS_MASK (0xF << 10) /* Slave Select */ -#define ZYNQ_QSPI_CR_BAUD_MASK (0x7 << 3) /* Baud rate div */ +#define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */ +#define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */ +#define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */ #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */ #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ #define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */ #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ -#define ZYNQ_QSPI_IXR_ALL_MASK 0x7F /* All IXR bits */ +#define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ /* zynq qspi Transmit Data Register */ diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index ce8acb4..6ed2165 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -18,14 +18,14 @@ DECLARE_GLOBAL_DATA_PTR; /* zynq spi register bit masks ZYNQ_SPI___MASK */ #define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */ #define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */ -#define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */ -#define ZYNQ_SPI_CR_BAUD_MASK (0x7 << 3) /* Baud rate div */ +#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */ +#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */ #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */ #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ #define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */ #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ -#define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ +#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ #define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ #define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */ -- cgit v0.10.2 From a48c4eb6a720d21aae995a6c60903763950fda46 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:35:26 +0530 Subject: spi: atmel_spi: Use BIT macro Replace numerical bit shift with BIT macro in atmel_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Bo Shen Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h index 1538a23..5b892d2 100644 --- a/drivers/spi/atmel_spi.h +++ b/drivers/spi/atmel_spi.h @@ -15,19 +15,19 @@ #define ATMEL_SPI_VERSION 0x00fc /* Bits in CR */ -#define ATMEL_SPI_CR_SPIEN (1 << 0) -#define ATMEL_SPI_CR_SPIDIS (1 << 1) -#define ATMEL_SPI_CR_SWRST (1 << 7) -#define ATMEL_SPI_CR_LASTXFER (1 << 24) +#define ATMEL_SPI_CR_SPIEN BIT(0) +#define ATMEL_SPI_CR_SPIDIS BIT(1) +#define ATMEL_SPI_CR_SWRST BIT(7) +#define ATMEL_SPI_CR_LASTXFER BIT(24) /* Bits in MR */ -#define ATMEL_SPI_MR_MSTR (1 << 0) -#define ATMEL_SPI_MR_PS (1 << 1) -#define ATMEL_SPI_MR_PCSDEC (1 << 2) -#define ATMEL_SPI_MR_FDIV (1 << 3) -#define ATMEL_SPI_MR_MODFDIS (1 << 4) -#define ATMEL_SPI_MR_WDRBT (1 << 5) -#define ATMEL_SPI_MR_LLB (1 << 7) +#define ATMEL_SPI_MR_MSTR BIT(0) +#define ATMEL_SPI_MR_PS BIT(1) +#define ATMEL_SPI_MR_PCSDEC BIT(2) +#define ATMEL_SPI_MR_FDIV BIT(3) +#define ATMEL_SPI_MR_MODFDIS BIT(4) +#define ATMEL_SPI_MR_WDRBT BIT(5) +#define ATMEL_SPI_MR_LLB BIT(7) #define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16) #define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24) @@ -38,25 +38,25 @@ /* Bits in TDR */ #define ATMEL_SPI_TDR_TD(x) (x) #define ATMEL_SPI_TDR_PCS(x) ((x) << 16) -#define ATMEL_SPI_TDR_LASTXFER (1 << 24) +#define ATMEL_SPI_TDR_LASTXFER BIT(24) /* Bits in SR/IER/IDR/IMR */ -#define ATMEL_SPI_SR_RDRF (1 << 0) -#define ATMEL_SPI_SR_TDRE (1 << 1) -#define ATMEL_SPI_SR_MODF (1 << 2) -#define ATMEL_SPI_SR_OVRES (1 << 3) -#define ATMEL_SPI_SR_ENDRX (1 << 4) -#define ATMEL_SPI_SR_ENDTX (1 << 5) -#define ATMEL_SPI_SR_RXBUFF (1 << 6) -#define ATMEL_SPI_SR_TXBUFE (1 << 7) -#define ATMEL_SPI_SR_NSSR (1 << 8) -#define ATMEL_SPI_SR_TXEMPTY (1 << 9) -#define ATMEL_SPI_SR_SPIENS (1 << 16) +#define ATMEL_SPI_SR_RDRF BIT(0) +#define ATMEL_SPI_SR_TDRE BIT(1) +#define ATMEL_SPI_SR_MODF BIT(2) +#define ATMEL_SPI_SR_OVRES BIT(3) +#define ATMEL_SPI_SR_ENDRX BIT(4) +#define ATMEL_SPI_SR_ENDTX BIT(5) +#define ATMEL_SPI_SR_RXBUFF BIT(6) +#define ATMEL_SPI_SR_TXBUFE BIT(7) +#define ATMEL_SPI_SR_NSSR BIT(8) +#define ATMEL_SPI_SR_TXEMPTY BIT(9) +#define ATMEL_SPI_SR_SPIENS BIT(16) /* Bits in CSRx */ -#define ATMEL_SPI_CSRx_CPOL (1 << 0) -#define ATMEL_SPI_CSRx_NCPHA (1 << 1) -#define ATMEL_SPI_CSRx_CSAAT (1 << 3) +#define ATMEL_SPI_CSRx_CPOL BIT(0) +#define ATMEL_SPI_CSRx_NCPHA BIT(1) +#define ATMEL_SPI_CSRx_CSAAT BIT(3) #define ATMEL_SPI_CSRx_BITS(x) ((x) << 4) #define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8) #define ATMEL_SPI_CSRx_SCBR_MAX 0xff -- cgit v0.10.2 From c0d1ea4acd53304f9f749790424586f52547a99a Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:35:47 +0530 Subject: spi: bfin_spi6xx: Use BIT macro Replace numerical bit shift with BIT macro in bfin_spi6xx :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c index eba01d1..8359d76 100644 --- a/drivers/spi/bfin_spi6xx.c +++ b/drivers/spi/bfin_spi6xx.c @@ -63,9 +63,9 @@ void spi_cs_activate(struct spi_slave *slave) ssel = bfin_read32(&bss->regs->ssel); ssel |= 1 << slave->cs; if (bss->cs_pol) - ssel |= (1 << 8) << slave->cs; + ssel |= BIT(8) << slave->cs; else - ssel &= ~((1 << 8) << slave->cs); + ssel &= ~(BIT(8) << slave->cs); bfin_write32(&bss->regs->ssel, ssel); } @@ -83,9 +83,9 @@ void spi_cs_deactivate(struct spi_slave *slave) u32 ssel; ssel = bfin_read32(&bss->regs->ssel); if (bss->cs_pol) - ssel &= ~((1 << 8) << slave->cs); + ssel &= ~(BIT(8) << slave->cs); else - ssel |= (1 << 8) << slave->cs; + ssel |= BIT(8) << slave->cs; /* deassert cs */ bfin_write32(&bss->regs->ssel, ssel); SSYNC(); -- cgit v0.10.2 From b7e83b087c0464b2e52240c2ebb1356125cca93e Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:36:06 +0530 Subject: spi: cadence_qspi_apb: Use BIT macro Replace numerical bit shift with BIT macro in cadence_qspi_apb :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stefan Roese Cc: Marek Vasut Acked-by: Vikas Manocha Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index d053407..7786dd6 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -58,10 +58,10 @@ #define CQSPI_REG_CONFIG 0x00 #define CQSPI_REG_CONFIG_CLK_POL_LSB 1 #define CQSPI_REG_CONFIG_CLK_PHA_LSB 2 -#define CQSPI_REG_CONFIG_ENABLE_MASK (1 << 0) -#define CQSPI_REG_CONFIG_DIRECT_MASK (1 << 7) -#define CQSPI_REG_CONFIG_DECODE_MASK (1 << 9) -#define CQSPI_REG_CONFIG_XIP_IMM_MASK (1 << 18) +#define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) +#define CQSPI_REG_CONFIG_DIRECT_MASK BIT(7) +#define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) +#define CQSPI_REG_CONFIG_XIP_IMM_MASK BIT(18) #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 #define CQSPI_REG_CONFIG_BAUD_LSB 19 #define CQSPI_REG_CONFIG_IDLE_LSB 31 @@ -122,18 +122,18 @@ #define CQSPI_REG_IRQMASK 0x44 #define CQSPI_REG_INDIRECTRD 0x60 -#define CQSPI_REG_INDIRECTRD_START_MASK (1 << 0) -#define CQSPI_REG_INDIRECTRD_CANCEL_MASK (1 << 1) -#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK (1 << 2) -#define CQSPI_REG_INDIRECTRD_DONE_MASK (1 << 5) +#define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) +#define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) +#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK BIT(2) +#define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 #define CQSPI_REG_INDIRECTRDBYTES 0x6C #define CQSPI_REG_CMDCTRL 0x90 -#define CQSPI_REG_CMDCTRL_EXECUTE_MASK (1 << 0) -#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK (1 << 1) +#define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) +#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 @@ -149,10 +149,10 @@ #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF #define CQSPI_REG_INDIRECTWR 0x70 -#define CQSPI_REG_INDIRECTWR_START_MASK (1 << 0) -#define CQSPI_REG_INDIRECTWR_CANCEL_MASK (1 << 1) -#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK (1 << 2) -#define CQSPI_REG_INDIRECTWR_DONE_MASK (1 << 5) +#define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) +#define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) +#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK BIT(2) +#define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 -- cgit v0.10.2 From 431a9f0286dc5041b47520479fab388b7917521b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:36:23 +0530 Subject: spi: designware_spi: Use BIT macro Replace numerical bit shift with BIT macro in designware_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stefan Roese Cc: Marek Vasut Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 86ee90f..7885e46 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -75,13 +75,13 @@ DECLARE_GLOBAL_DATA_PTR; /* Bit fields in SR, 7 bits */ #define SR_MASK 0x7f /* cover 7 bits */ -#define SR_BUSY (1 << 0) -#define SR_TF_NOT_FULL (1 << 1) -#define SR_TF_EMPT (1 << 2) -#define SR_RF_NOT_EMPT (1 << 3) -#define SR_RF_FULL (1 << 4) -#define SR_TX_ERR (1 << 5) -#define SR_DCOL (1 << 6) +#define SR_BUSY BIT(0) +#define SR_TF_NOT_FULL BIT(1) +#define SR_TF_EMPT BIT(2) +#define SR_RF_NOT_EMPT BIT(3) +#define SR_RF_FULL BIT(4) +#define SR_TX_ERR BIT(5) +#define SR_DCOL BIT(6) #define RX_TIMEOUT 1000 /* timeout in ms */ -- cgit v0.10.2 From 29e6abd94b0d879b0b92538d41b80d22b4a28d2c Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:37:18 +0530 Subject: spi: fsl: Use BIT macro Replace numerical bit shift with BIT macro in fsl_*spi.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: York Sun Cc: Haikun Wang Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index 887edd8..c8dcb27 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; /* fsl_dspi_platdata flags */ -#define DSPI_FLAG_REGMAP_ENDIAN_BIG (1 << 0) +#define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) /* idle data value */ #define DSPI_IDLE_VAL 0x0 diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 375dc07..b1586d1 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -32,26 +32,26 @@ struct fsl_spi_slave { #define ESPI_MAX_CS_NUM 4 #define ESPI_FIFO_WIDTH_BIT 32 -#define ESPI_EV_RNE (1 << 9) -#define ESPI_EV_TNF (1 << 8) -#define ESPI_EV_DON (1 << 14) -#define ESPI_EV_TXE (1 << 15) +#define ESPI_EV_RNE BIT(9) +#define ESPI_EV_TNF BIT(8) +#define ESPI_EV_DON BIT(14) +#define ESPI_EV_TXE BIT(15) #define ESPI_EV_RFCNT_SHIFT 24 #define ESPI_EV_RFCNT_MASK (0x3f << ESPI_EV_RFCNT_SHIFT) -#define ESPI_MODE_EN (1 << 31) /* Enable interface */ +#define ESPI_MODE_EN BIT(31) /* Enable interface */ #define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */ #define ESPI_MODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold */ #define ESPI_COM_CS(x) ((x) << 30) #define ESPI_COM_TRANLEN(x) ((x) << 0) -#define ESPI_CSMODE_CI_INACTIVEHIGH (1 << 31) -#define ESPI_CSMODE_CP_BEGIN_EDGCLK (1 << 30) -#define ESPI_CSMODE_REV_MSB_FIRST (1 << 29) -#define ESPI_CSMODE_DIV16 (1 << 28) +#define ESPI_CSMODE_CI_INACTIVEHIGH BIT(31) +#define ESPI_CSMODE_CP_BEGIN_EDGCLK BIT(30) +#define ESPI_CSMODE_REV_MSB_FIRST BIT(29) +#define ESPI_CSMODE_DIV16 BIT(28) #define ESPI_CSMODE_PM(x) ((x) << 24) -#define ESPI_CSMODE_POL_ASSERTED_LOW (1 << 20) +#define ESPI_CSMODE_POL_ASSERTED_LOW BIT(20) #define ESPI_CSMODE_LEN(x) ((x) << 16) #define ESPI_CSMODE_CSBEF(x) ((x) << 12) #define ESPI_CSMODE_CSAFT(x) ((x) << 8) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 868df5f..e1a0ec9 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */ /* fsl_qspi_platdata flags */ -#define QSPI_FLAG_REGMAP_ENDIAN_BIG (1 << 0) +#define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) /* default SCK frequency, unit: HZ */ #define FSL_QSPI_DEFAULT_SCK_FREQ 50000000 @@ -383,7 +383,7 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) /* Enable the module again (enable the DDR too) */ reg |= QSPI_MCR_DDR_EN_MASK; /* Enable bit 29 for imx6sx */ - reg |= (1 << 29); + reg |= BIT(29); qspi_write32(priv->flags, ®s->mcr, reg); } -- cgit v0.10.2 From 69fd4c386cb4ca60fa5d3c8e28d6601b1a48acac Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:37:56 +0530 Subject: spi: ich: Use BIT macro Replace numerical bit shift with BIT macro in ich :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Simon Glass Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index be4c0a3..af327c4 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -692,13 +692,13 @@ static int ich_spi_probe(struct udevice *bus) */ if (plat->use_sbase) { bios_cntl = ich_readb(priv, priv->bcr); - bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */ + bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */ bios_cntl |= 1; /* Write Protect Disable (WPD) */ ich_writeb(priv, bios_cntl, priv->bcr); } else { pci_read_config_byte(plat->dev, 0xdc, &bios_cntl); if (plat->ich_version == 9) - bios_cntl &= ~(1 << 5); + bios_cntl &= ~BIT(5); pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1); } -- cgit v0.10.2 From a048d4bbb1079b4b70bb5fabca4661ba373fbc4b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:38:07 +0530 Subject: spi: mpc8xxx_spi: Use BIT macro Replace numerical bit shift with BIT macro in mpc8xxx_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index 0d59c36..00cbcbf 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -55,7 +55,7 @@ void spi_init(void) * some registers */ spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN; - spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use SYSCLK / 8 + spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8 (16.67MHz typ.) */ spi->event = 0xffffffff; /* Clear all SPI events */ spi->mask = 0x00000000; /* Mask all SPI interrupts */ -- cgit v0.10.2 From 3e1b4dcf1cb6d5edbb6a78824a2f30531ef8ea55 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:38:32 +0530 Subject: spi: omap3_spi: Use BIT macro Replace numerical bit shift with BIT macro in omap3_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Nikita Kiryanov Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h index 4af22c1..fb02ea1 100644 --- a/drivers/spi/omap3_spi.h +++ b/drivers/spi/omap3_spi.h @@ -52,40 +52,40 @@ struct mcspi { /* per-register bitmasks */ #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3) -#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0) -#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1) +#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) +#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) +#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1) -#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0) +#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0) -#define OMAP3_MCSPI_MODULCTRL_SINGLE (1 << 0) -#define OMAP3_MCSPI_MODULCTRL_MS (1 << 2) -#define OMAP3_MCSPI_MODULCTRL_STEST (1 << 3) +#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0) +#define OMAP3_MCSPI_MODULCTRL_MS BIT(2) +#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3) -#define OMAP3_MCSPI_CHCONF_PHA (1 << 0) -#define OMAP3_MCSPI_CHCONF_POL (1 << 1) +#define OMAP3_MCSPI_CHCONF_PHA BIT(0) +#define OMAP3_MCSPI_CHCONF_POL BIT(1) #define OMAP3_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) -#define OMAP3_MCSPI_CHCONF_EPOL (1 << 6) +#define OMAP3_MCSPI_CHCONF_EPOL BIT(6) #define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7) #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12) #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12) #define OMAP3_MCSPI_CHCONF_TRM_MASK (0x03 << 12) -#define OMAP3_MCSPI_CHCONF_DMAW (1 << 14) -#define OMAP3_MCSPI_CHCONF_DMAR (1 << 15) -#define OMAP3_MCSPI_CHCONF_DPE0 (1 << 16) -#define OMAP3_MCSPI_CHCONF_DPE1 (1 << 17) -#define OMAP3_MCSPI_CHCONF_IS (1 << 18) -#define OMAP3_MCSPI_CHCONF_TURBO (1 << 19) -#define OMAP3_MCSPI_CHCONF_FORCE (1 << 20) - -#define OMAP3_MCSPI_CHSTAT_RXS (1 << 0) -#define OMAP3_MCSPI_CHSTAT_TXS (1 << 1) -#define OMAP3_MCSPI_CHSTAT_EOT (1 << 2) - -#define OMAP3_MCSPI_CHCTRL_EN (1 << 0) +#define OMAP3_MCSPI_CHCONF_DMAW BIT(14) +#define OMAP3_MCSPI_CHCONF_DMAR BIT(15) +#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16) +#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17) +#define OMAP3_MCSPI_CHCONF_IS BIT(18) +#define OMAP3_MCSPI_CHCONF_TURBO BIT(19) +#define OMAP3_MCSPI_CHCONF_FORCE BIT(20) + +#define OMAP3_MCSPI_CHSTAT_RXS BIT(0) +#define OMAP3_MCSPI_CHSTAT_TXS BIT(1) +#define OMAP3_MCSPI_CHSTAT_EOT BIT(2) + +#define OMAP3_MCSPI_CHCTRL_EN BIT(0) #define OMAP3_MCSPI_CHCTRL_DIS (0 << 0) -#define OMAP3_MCSPI_WAKEUPENABLE_WKEN (1 << 0) +#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0) struct omap3_spi_slave { struct spi_slave slave; -- cgit v0.10.2 From ccaa9485011b853e7729d1e7315c34563cdabb8e Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:38:47 +0530 Subject: spi: sh_qspi: Use BIT macro Replace numerical bit shift with BIT macro in sh_qspi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Nobuhiro Iwamatsu Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c index 77ede6b..7209e1d 100644 --- a/drivers/spi/sh_qspi.c +++ b/drivers/spi/sh_qspi.c @@ -21,19 +21,19 @@ #define SPPCR_IO3FV 0x04 #define SPPCR_IO2FV 0x02 #define SPPCR_IO1FV 0x01 -#define SPBDCR_RXBC0 (1 << 0) -#define SPCMD_SCKDEN (1 << 15) -#define SPCMD_SLNDEN (1 << 14) -#define SPCMD_SPNDEN (1 << 13) -#define SPCMD_SSLKP (1 << 7) -#define SPCMD_BRDV0 (1 << 2) +#define SPBDCR_RXBC0 BIT(0) +#define SPCMD_SCKDEN BIT(15) +#define SPCMD_SLNDEN BIT(14) +#define SPCMD_SPNDEN BIT(13) +#define SPCMD_SSLKP BIT(7) +#define SPCMD_BRDV0 BIT(2) #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \ SPCMD_SPNDEN | SPCMD_SSLKP | \ SPCMD_BRDV0 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \ SPCMD_BRDV0 -#define SPBFCR_TXRST (1 << 7) -#define SPBFCR_RXRST (1 << 6) +#define SPBFCR_TXRST BIT(7) +#define SPBFCR_RXRST BIT(6) /* SH QSPI register set */ struct sh_qspi_regs { -- cgit v0.10.2 From f692248f9039fb9d933ccb5e919ecfa073b5a130 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:39:06 +0530 Subject: spi: tegra: Use BIT macro Replace numerical bit shift with BIT macro in tegra*.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stephen Warren Cc: Tom Warren Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index a965f80..d9edd11 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -33,54 +33,54 @@ DECLARE_GLOBAL_DATA_PTR; /* COMMAND1 */ -#define SPI_CMD1_GO (1 << 31) -#define SPI_CMD1_M_S (1 << 30) +#define SPI_CMD1_GO BIT(31) +#define SPI_CMD1_M_S BIT(30) #define SPI_CMD1_MODE_MASK 0x3 #define SPI_CMD1_MODE_SHIFT 28 #define SPI_CMD1_CS_SEL_MASK 0x3 #define SPI_CMD1_CS_SEL_SHIFT 26 -#define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25) -#define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24) -#define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23) -#define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22) -#define SPI_CMD1_CS_SW_HW (1 << 21) -#define SPI_CMD1_CS_SW_VAL (1 << 20) +#define SPI_CMD1_CS_POL_INACTIVE3 BIT(25) +#define SPI_CMD1_CS_POL_INACTIVE2 BIT(24) +#define SPI_CMD1_CS_POL_INACTIVE1 BIT(23) +#define SPI_CMD1_CS_POL_INACTIVE0 BIT(22) +#define SPI_CMD1_CS_SW_HW BIT(21) +#define SPI_CMD1_CS_SW_VAL BIT(20) #define SPI_CMD1_IDLE_SDA_MASK 0x3 #define SPI_CMD1_IDLE_SDA_SHIFT 18 -#define SPI_CMD1_BIDIR (1 << 17) -#define SPI_CMD1_LSBI_FE (1 << 16) -#define SPI_CMD1_LSBY_FE (1 << 15) -#define SPI_CMD1_BOTH_EN_BIT (1 << 14) -#define SPI_CMD1_BOTH_EN_BYTE (1 << 13) -#define SPI_CMD1_RX_EN (1 << 12) -#define SPI_CMD1_TX_EN (1 << 11) -#define SPI_CMD1_PACKED (1 << 5) +#define SPI_CMD1_BIDIR BIT(17) +#define SPI_CMD1_LSBI_FE BIT(16) +#define SPI_CMD1_LSBY_FE BIT(15) +#define SPI_CMD1_BOTH_EN_BIT BIT(14) +#define SPI_CMD1_BOTH_EN_BYTE BIT(13) +#define SPI_CMD1_RX_EN BIT(12) +#define SPI_CMD1_TX_EN BIT(11) +#define SPI_CMD1_PACKED BIT(5) #define SPI_CMD1_BIT_LEN_MASK 0x1F #define SPI_CMD1_BIT_LEN_SHIFT 0 /* COMMAND2 */ -#define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6) +#define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6) #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) -#define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0) +#define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0) #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) /* TRANSFER STATUS */ -#define SPI_XFER_STS_RDY (1 << 30) +#define SPI_XFER_STS_RDY BIT(30) /* FIFO STATUS */ -#define SPI_FIFO_STS_CS_INACTIVE (1 << 31) -#define SPI_FIFO_STS_FRAME_END (1 << 30) -#define SPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15) -#define SPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14) -#define SPI_FIFO_STS_ERR (1 << 8) -#define SPI_FIFO_STS_TX_FIFO_OVF (1 << 7) -#define SPI_FIFO_STS_TX_FIFO_UNR (1 << 6) -#define SPI_FIFO_STS_RX_FIFO_OVF (1 << 5) -#define SPI_FIFO_STS_RX_FIFO_UNR (1 << 4) -#define SPI_FIFO_STS_TX_FIFO_FULL (1 << 3) -#define SPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2) -#define SPI_FIFO_STS_RX_FIFO_FULL (1 << 1) -#define SPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0) +#define SPI_FIFO_STS_CS_INACTIVE BIT(31) +#define SPI_FIFO_STS_FRAME_END BIT(30) +#define SPI_FIFO_STS_RX_FIFO_FLUSH BIT(15) +#define SPI_FIFO_STS_TX_FIFO_FLUSH BIT(14) +#define SPI_FIFO_STS_ERR BIT(8) +#define SPI_FIFO_STS_TX_FIFO_OVF BIT(7) +#define SPI_FIFO_STS_TX_FIFO_UNR BIT(6) +#define SPI_FIFO_STS_RX_FIFO_OVF BIT(5) +#define SPI_FIFO_STS_RX_FIFO_UNR BIT(4) +#define SPI_FIFO_STS_TX_FIFO_FULL BIT(3) +#define SPI_FIFO_STS_TX_FIFO_EMPTY BIT(2) +#define SPI_FIFO_STS_RX_FIFO_FULL BIT(1) +#define SPI_FIFO_STS_RX_FIFO_EMPTY BIT(0) #define SPI_TIMEOUT 1000 #define TEGRA_SPI_MAX_FREQ 52000000 diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c index afa0848..5dc196b 100644 --- a/drivers/spi/tegra20_sflash.c +++ b/drivers/spi/tegra20_sflash.c @@ -20,37 +20,37 @@ DECLARE_GLOBAL_DATA_PTR; -#define SPI_CMD_GO (1 << 30) +#define SPI_CMD_GO BIT(30) #define SPI_CMD_ACTIVE_SCLK_SHIFT 26 #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT) -#define SPI_CMD_CK_SDA (1 << 21) +#define SPI_CMD_CK_SDA BIT(21) #define SPI_CMD_ACTIVE_SDA_SHIFT 18 #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT) -#define SPI_CMD_CS_POL (1 << 16) -#define SPI_CMD_TXEN (1 << 15) -#define SPI_CMD_RXEN (1 << 14) -#define SPI_CMD_CS_VAL (1 << 13) -#define SPI_CMD_CS_SOFT (1 << 12) -#define SPI_CMD_CS_DELAY (1 << 9) -#define SPI_CMD_CS3_EN (1 << 8) -#define SPI_CMD_CS2_EN (1 << 7) -#define SPI_CMD_CS1_EN (1 << 6) -#define SPI_CMD_CS0_EN (1 << 5) -#define SPI_CMD_BIT_LENGTH (1 << 4) +#define SPI_CMD_CS_POL BIT(16) +#define SPI_CMD_TXEN BIT(15) +#define SPI_CMD_RXEN BIT(14) +#define SPI_CMD_CS_VAL BIT(13) +#define SPI_CMD_CS_SOFT BIT(12) +#define SPI_CMD_CS_DELAY BIT(9) +#define SPI_CMD_CS3_EN BIT(8) +#define SPI_CMD_CS2_EN BIT(7) +#define SPI_CMD_CS1_EN BIT(6) +#define SPI_CMD_CS0_EN BIT(5) +#define SPI_CMD_BIT_LENGTH BIT(4) #define SPI_CMD_BIT_LENGTH_MASK 0x0000001F -#define SPI_STAT_BSY (1 << 31) -#define SPI_STAT_RDY (1 << 30) -#define SPI_STAT_RXF_FLUSH (1 << 29) -#define SPI_STAT_TXF_FLUSH (1 << 28) -#define SPI_STAT_RXF_UNR (1 << 27) -#define SPI_STAT_TXF_OVF (1 << 26) -#define SPI_STAT_RXF_EMPTY (1 << 25) -#define SPI_STAT_RXF_FULL (1 << 24) -#define SPI_STAT_TXF_EMPTY (1 << 23) -#define SPI_STAT_TXF_FULL (1 << 22) -#define SPI_STAT_SEL_TXRX_N (1 << 16) -#define SPI_STAT_CUR_BLKCNT (1 << 15) +#define SPI_STAT_BSY BIT(31) +#define SPI_STAT_RDY BIT(30) +#define SPI_STAT_RXF_FLUSH BIT(29) +#define SPI_STAT_TXF_FLUSH BIT(28) +#define SPI_STAT_RXF_UNR BIT(27) +#define SPI_STAT_TXF_OVF BIT(26) +#define SPI_STAT_RXF_EMPTY BIT(25) +#define SPI_STAT_RXF_FULL BIT(24) +#define SPI_STAT_TXF_EMPTY BIT(23) +#define SPI_STAT_TXF_FULL BIT(22) +#define SPI_STAT_SEL_TXRX_N BIT(16) +#define SPI_STAT_CUR_BLKCNT BIT(15) #define SPI_TIMEOUT 1000 #define TEGRA_SPI_MAX_FREQ 52000000 diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index 144716f..d1abac2 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -33,45 +33,45 @@ DECLARE_GLOBAL_DATA_PTR; /* COMMAND */ -#define SLINK_CMD_ENB (1 << 31) -#define SLINK_CMD_GO (1 << 30) -#define SLINK_CMD_M_S (1 << 28) +#define SLINK_CMD_ENB BIT(31) +#define SLINK_CMD_GO BIT(30) +#define SLINK_CMD_M_S BIT(28) #define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24) -#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH (1 << 24) +#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH BIT(24) #define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24) #define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24) #define SLINK_CMD_IDLE_SCLK_MASK (3 << 24) -#define SLINK_CMD_CK_SDA (1 << 21) -#define SLINK_CMD_CS_POL (1 << 13) -#define SLINK_CMD_CS_VAL (1 << 12) -#define SLINK_CMD_CS_SOFT (1 << 11) -#define SLINK_CMD_BIT_LENGTH (1 << 4) +#define SLINK_CMD_CK_SDA BIT(21) +#define SLINK_CMD_CS_POL BIT(13) +#define SLINK_CMD_CS_VAL BIT(12) +#define SLINK_CMD_CS_SOFT BIT(11) +#define SLINK_CMD_BIT_LENGTH BIT(4) #define SLINK_CMD_BIT_LENGTH_MASK 0x0000001F /* COMMAND2 */ -#define SLINK_CMD2_TXEN (1 << 30) -#define SLINK_CMD2_RXEN (1 << 31) -#define SLINK_CMD2_SS_EN (1 << 18) +#define SLINK_CMD2_TXEN BIT(30) +#define SLINK_CMD2_RXEN BIT(31) +#define SLINK_CMD2_SS_EN BIT(18) #define SLINK_CMD2_SS_EN_SHIFT 18 #define SLINK_CMD2_SS_EN_MASK 0x000C0000 -#define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 << 17) +#define SLINK_CMD2_CS_ACTIVE_BETWEEN BIT(17) /* STATUS */ -#define SLINK_STAT_BSY (1 << 31) -#define SLINK_STAT_RDY (1 << 30) -#define SLINK_STAT_ERR (1 << 29) -#define SLINK_STAT_RXF_FLUSH (1 << 27) -#define SLINK_STAT_TXF_FLUSH (1 << 26) -#define SLINK_STAT_RXF_OVF (1 << 25) -#define SLINK_STAT_TXF_UNR (1 << 24) -#define SLINK_STAT_RXF_EMPTY (1 << 23) -#define SLINK_STAT_RXF_FULL (1 << 22) -#define SLINK_STAT_TXF_EMPTY (1 << 21) -#define SLINK_STAT_TXF_FULL (1 << 20) -#define SLINK_STAT_TXF_OVF (1 << 19) -#define SLINK_STAT_RXF_UNR (1 << 18) -#define SLINK_STAT_CUR_BLKCNT (1 << 15) +#define SLINK_STAT_BSY BIT(31) +#define SLINK_STAT_RDY BIT(30) +#define SLINK_STAT_ERR BIT(29) +#define SLINK_STAT_RXF_FLUSH BIT(27) +#define SLINK_STAT_TXF_FLUSH BIT(26) +#define SLINK_STAT_RXF_OVF BIT(25) +#define SLINK_STAT_TXF_UNR BIT(24) +#define SLINK_STAT_RXF_EMPTY BIT(23) +#define SLINK_STAT_RXF_FULL BIT(22) +#define SLINK_STAT_TXF_EMPTY BIT(21) +#define SLINK_STAT_TXF_FULL BIT(20) +#define SLINK_STAT_TXF_OVF BIT(19) +#define SLINK_STAT_RXF_UNR BIT(18) +#define SLINK_STAT_CUR_BLKCNT BIT(15) /* STATUS2 */ -#define SLINK_STAT2_RXF_FULL_CNT (1 << 16) -#define SLINK_STAT2_TXF_FULL_CNT (1 << 0) +#define SLINK_STAT2_RXF_FULL_CNT BIT(16) +#define SLINK_STAT2_TXF_FULL_CNT BIT(0) #define SPI_TIMEOUT 1000 #define TEGRA_SPI_MAX_FREQ 52000000 -- cgit v0.10.2 From 847720c4e143130e372aabd0c39d19e8ae9885a3 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:39:20 +0530 Subject: spi: ti_qspi: Use BIT macro Replace numerical bit shift with BIT macro in ti_qspi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Vignesh R Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index bd63db8..ecd9d78 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -20,13 +20,13 @@ #define QSPI_TIMEOUT 2000000 #define QSPI_FCLK 192000000 /* clock control */ -#define QSPI_CLK_EN (1 << 31) +#define QSPI_CLK_EN BIT(31) #define QSPI_CLK_DIV_MAX 0xffff /* command */ #define QSPI_EN_CS(n) (n << 28) #define QSPI_WLEN(n) ((n-1) << 19) -#define QSPI_3_PIN (1 << 18) -#define QSPI_RD_SNGL (1 << 16) +#define QSPI_3_PIN BIT(18) +#define QSPI_RD_SNGL BIT(16) #define QSPI_WR_SNGL (2 << 16) #define QSPI_INVAL (4 << 16) #define QSPI_RD_QUAD (7 << 16) @@ -36,8 +36,8 @@ #define QSPI_CSPOL(n) (1 << (1 + n*8)) #define QSPI_CKPOL(n) (1 << (n*8)) /* status */ -#define QSPI_WC (1 << 1) -#define QSPI_BUSY (1 << 0) +#define QSPI_WC BIT(1) +#define QSPI_BUSY BIT(0) #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY) #define QSPI_XFER_DONE QSPI_WC #define MM_SWITCH 0x01 -- cgit v0.10.2 From 5ea392d43bd15c652aac01750ed363c7d3d144e4 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:39:31 +0530 Subject: spi: xilinx_spi: Use BIT macro Replace numerical bit shift with BIT macro in xilinx_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Michal Simek Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 8ccc578..7620163 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -32,24 +32,24 @@ */ /* SPI Control Register (spicr), [1] p9, [2] p8 */ -#define SPICR_LSB_FIRST (1 << 9) -#define SPICR_MASTER_INHIBIT (1 << 8) -#define SPICR_MANUAL_SS (1 << 7) -#define SPICR_RXFIFO_RESEST (1 << 6) -#define SPICR_TXFIFO_RESEST (1 << 5) -#define SPICR_CPHA (1 << 4) -#define SPICR_CPOL (1 << 3) -#define SPICR_MASTER_MODE (1 << 2) -#define SPICR_SPE (1 << 1) -#define SPICR_LOOP (1 << 0) +#define SPICR_LSB_FIRST BIT(9) +#define SPICR_MASTER_INHIBIT BIT(8) +#define SPICR_MANUAL_SS BIT(7) +#define SPICR_RXFIFO_RESEST BIT(6) +#define SPICR_TXFIFO_RESEST BIT(5) +#define SPICR_CPHA BIT(4) +#define SPICR_CPOL BIT(3) +#define SPICR_MASTER_MODE BIT(2) +#define SPICR_SPE BIT(1) +#define SPICR_LOOP BIT(0) /* SPI Status Register (spisr), [1] p11, [2] p10 */ -#define SPISR_SLAVE_MODE_SELECT (1 << 5) -#define SPISR_MODF (1 << 4) -#define SPISR_TX_FULL (1 << 3) -#define SPISR_TX_EMPTY (1 << 2) -#define SPISR_RX_FULL (1 << 1) -#define SPISR_RX_EMPTY (1 << 0) +#define SPISR_SLAVE_MODE_SELECT BIT(5) +#define SPISR_MODF BIT(4) +#define SPISR_TX_FULL BIT(3) +#define SPISR_TX_EMPTY BIT(2) +#define SPISR_RX_FULL BIT(1) +#define SPISR_RX_EMPTY BIT(0) /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */ #define SPIDTR_8BIT_MASK (0xff << 0) -- cgit v0.10.2 From a9d3b780232907206c7930edae8a0a7cc8fd7e24 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 00:59:00 +0530 Subject: spi: atmel_spi: Use GENMASK Replace numeric mask hexcodes with GENMASK macro in atmel_spi Cc: Bo Shen Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h index 5b892d2..76b8556 100644 --- a/drivers/spi/atmel_spi.h +++ b/drivers/spi/atmel_spi.h @@ -59,7 +59,7 @@ #define ATMEL_SPI_CSRx_CSAAT BIT(3) #define ATMEL_SPI_CSRx_BITS(x) ((x) << 4) #define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8) -#define ATMEL_SPI_CSRx_SCBR_MAX 0xff +#define ATMEL_SPI_CSRx_SCBR_MAX GENMASK(7, 0) #define ATMEL_SPI_CSRx_DLYBS(x) ((x) << 16) #define ATMEL_SPI_CSRx_DLYBCT(x) ((x) << 24) -- cgit v0.10.2 From 95e77d904ea10512cdf882357352c40e54877601 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:01:36 +0530 Subject: spi: designware_spi: Use GENMASK Replace numeric mask hexcodes with GENMASK macro in designware_spi Cc: Stefan Roese Cc: Marek Vasut Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 7885e46..24a6e98 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -74,7 +74,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_CFS_OFFSET 12 /* Bit fields in SR, 7 bits */ -#define SR_MASK 0x7f /* cover 7 bits */ +#define SR_MASK GENMASK(6, 0) /* cover 7 bits */ #define SR_BUSY BIT(0) #define SR_TF_NOT_FULL BIT(1) #define SR_TF_EMPT BIT(2) -- cgit v0.10.2 From bad490a24212c068c5b718b9189f47ea4075d078 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:02:04 +0530 Subject: spi: fsl_qspi: Use GENMASK Replace numeric mask hexcodes with GENMASK macro in fsl_qspi Cc: York Sun Cc: Haikun Wang Signed-off-by: Jagan Teki diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index e1a0ec9..10733df 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; #define TX_BUFFER_SIZE 0x40 #endif -#define OFFSET_BITS_MASK 0x00ffffff +#define OFFSET_BITS_MASK GENMASK(24, 0) #define FLASH_STATUS_WEL 0x02 -- cgit v0.10.2 From 0ebc0ec6200907588881b3c7347af74dbcf9cb65 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:02:49 +0530 Subject: spi: omap3_spi: Use GENMASK Replace numeric mask hexcodes with GENMASK macro in omap3_spi Cc: Nikita Kiryanov Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h index fb02ea1..6a07c6d 100644 --- a/drivers/spi/omap3_spi.h +++ b/drivers/spi/omap3_spi.h @@ -64,12 +64,12 @@ struct mcspi { #define OMAP3_MCSPI_CHCONF_PHA BIT(0) #define OMAP3_MCSPI_CHCONF_POL BIT(1) -#define OMAP3_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) +#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2) #define OMAP3_MCSPI_CHCONF_EPOL BIT(6) -#define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7) -#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12) -#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12) -#define OMAP3_MCSPI_CHCONF_TRM_MASK (0x03 << 12) +#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7) +#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) +#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) +#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12) #define OMAP3_MCSPI_CHCONF_DMAW BIT(14) #define OMAP3_MCSPI_CHCONF_DMAR BIT(15) #define OMAP3_MCSPI_CHCONF_DPE0 BIT(16) -- cgit v0.10.2 From 76538ec64804155c5361aeac9d38291feef01c50 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:03:10 +0530 Subject: spi: tegra: Use GENMASK Replace numeric mask hexcodes with GENMASK macro in tegra*.c Cc: Stephen Warren Cc: Tom Warren Signed-off-by: Jagan Teki diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index d9edd11..98a062c 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -35,9 +35,9 @@ DECLARE_GLOBAL_DATA_PTR; /* COMMAND1 */ #define SPI_CMD1_GO BIT(31) #define SPI_CMD1_M_S BIT(30) -#define SPI_CMD1_MODE_MASK 0x3 +#define SPI_CMD1_MODE_MASK GENMASK(1, 0) #define SPI_CMD1_MODE_SHIFT 28 -#define SPI_CMD1_CS_SEL_MASK 0x3 +#define SPI_CMD1_CS_SEL_MASK GENMASK(1, 0) #define SPI_CMD1_CS_SEL_SHIFT 26 #define SPI_CMD1_CS_POL_INACTIVE3 BIT(25) #define SPI_CMD1_CS_POL_INACTIVE2 BIT(24) @@ -45,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_CMD1_CS_POL_INACTIVE0 BIT(22) #define SPI_CMD1_CS_SW_HW BIT(21) #define SPI_CMD1_CS_SW_VAL BIT(20) -#define SPI_CMD1_IDLE_SDA_MASK 0x3 +#define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0) #define SPI_CMD1_IDLE_SDA_SHIFT 18 #define SPI_CMD1_BIDIR BIT(17) #define SPI_CMD1_LSBI_FE BIT(16) @@ -55,14 +55,14 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_CMD1_RX_EN BIT(12) #define SPI_CMD1_TX_EN BIT(11) #define SPI_CMD1_PACKED BIT(5) -#define SPI_CMD1_BIT_LEN_MASK 0x1F +#define SPI_CMD1_BIT_LEN_MASK GENMASK(4, 0) #define SPI_CMD1_BIT_LEN_SHIFT 0 /* COMMAND2 */ #define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6) -#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) +#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6) #define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0) -#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) +#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0) /* TRANSFER STATUS */ #define SPI_XFER_STS_RDY BIT(30) diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c index 5dc196b..6888a96 100644 --- a/drivers/spi/tegra20_sflash.c +++ b/drivers/spi/tegra20_sflash.c @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_CMD_CS1_EN BIT(6) #define SPI_CMD_CS0_EN BIT(5) #define SPI_CMD_BIT_LENGTH BIT(4) -#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F +#define SPI_CMD_BIT_LENGTH_MASK GENMASK(4, 0) #define SPI_STAT_BSY BIT(31) #define SPI_STAT_RDY BIT(30) diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index d1abac2..43054f1 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -46,13 +46,13 @@ DECLARE_GLOBAL_DATA_PTR; #define SLINK_CMD_CS_VAL BIT(12) #define SLINK_CMD_CS_SOFT BIT(11) #define SLINK_CMD_BIT_LENGTH BIT(4) -#define SLINK_CMD_BIT_LENGTH_MASK 0x0000001F +#define SLINK_CMD_BIT_LENGTH_MASK GENMASK(4, 0) /* COMMAND2 */ #define SLINK_CMD2_TXEN BIT(30) #define SLINK_CMD2_RXEN BIT(31) #define SLINK_CMD2_SS_EN BIT(18) #define SLINK_CMD2_SS_EN_SHIFT 18 -#define SLINK_CMD2_SS_EN_MASK 0x000C0000 +#define SLINK_CMD2_SS_EN_MASK GENMASK(19, 18) #define SLINK_CMD2_CS_ACTIVE_BETWEEN BIT(17) /* STATUS */ #define SLINK_STAT_BSY BIT(31) -- cgit v0.10.2 From d2436301c52a823f0f0b3c2ef4b966a5bced489c Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2015 01:03:44 +0530 Subject: spi: xilinx_spi: Use GENMASK Replace numeric mask hexcodes with GENMASK macro in xilinx_spi Cc: Michal Simek Signed-off-by: Jagan Teki diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 7620163..0713714 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -52,14 +52,14 @@ #define SPISR_RX_EMPTY BIT(0) /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */ -#define SPIDTR_8BIT_MASK (0xff << 0) -#define SPIDTR_16BIT_MASK (0xffff << 0) -#define SPIDTR_32BIT_MASK (0xffffffff << 0) +#define SPIDTR_8BIT_MASK GENMASK(7, 0) +#define SPIDTR_16BIT_MASK GENMASK(15, 0) +#define SPIDTR_32BIT_MASK GENMASK(31, 0) /* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */ -#define SPIDRR_8BIT_MASK (0xff << 0) -#define SPIDRR_16BIT_MASK (0xffff << 0) -#define SPIDRR_32BIT_MASK (0xffffffff << 0) +#define SPIDRR_8BIT_MASK GENMASK(7, 0) +#define SPIDRR_16BIT_MASK GENMASK(15, 0) +#define SPIDRR_32BIT_MASK GENMASK(31, 0) /* SPI Slave Select Register (spissr), [1] p13, [2] p13 */ #define SPISSR_MASK(cs) (1 << (cs)) @@ -75,7 +75,7 @@ #define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS) #ifndef CONFIG_XILINX_SPI_IDLE_VAL -#define CONFIG_XILINX_SPI_IDLE_VAL 0xff +#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0) #endif #ifndef CONFIG_SYS_XILINX_SPI_LIST -- cgit v0.10.2 From 9c63d44e92e3c90080491ba4e61e36e39a20aea8 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 27 Oct 2015 23:09:56 +0530 Subject: spi: altera_spi: Use BIT macro Replace numerical bit shift with BIT macro in altera_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Marek Vasut Acked-by: Thomas Chou Reviewed-by: Tom Rini Signed-off-by: Jagan Teki diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index ff3512a..3dbcfaa 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -38,8 +38,8 @@ struct altera_spi_priv { struct altera_spi_regs *regs; }; -#define ALTERA_SPI_STATUS_RRDY_MSK (1 << 7) -#define ALTERA_SPI_CONTROL_SSO_MSK (1 << 10) +#define ALTERA_SPI_STATUS_RRDY_MSK BIT(7) +#define ALTERA_SPI_CONTROL_SSO_MSK BIT(10) static void spi_cs_activate(struct udevice *dev, uint cs) { -- cgit v0.10.2 From bef87adf95e7ca923f866e27bbcccb2dad85df9f Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 27 Oct 2015 23:11:11 +0530 Subject: spi: altera_spi: Minor cleanup - Moved macro definitions to top - Give tab space to CONFIG_ALTERA_SPI_IDLE_VAL value - Re-arrange header includes ascending order Acked-by: Thomas Chou Signed-off-by: Jagan Teki diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index 3dbcfaa..e49949b 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -11,14 +11,17 @@ #include #include #include -#include #include +#include #include DECLARE_GLOBAL_DATA_PTR; +#define ALTERA_SPI_STATUS_RRDY_MSK BIT(7) +#define ALTERA_SPI_CONTROL_SSO_MSK BIT(10) + #ifndef CONFIG_ALTERA_SPI_IDLE_VAL -#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff +#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff #endif struct altera_spi_regs { @@ -38,9 +41,6 @@ struct altera_spi_priv { struct altera_spi_regs *regs; }; -#define ALTERA_SPI_STATUS_RRDY_MSK BIT(7) -#define ALTERA_SPI_CONTROL_SSO_MSK BIT(10) - static void spi_cs_activate(struct udevice *dev, uint cs) { struct udevice *bus = dev->parent; -- cgit v0.10.2