From 7428f55c94ac51214038a3882630ddb89520e42e Mon Sep 17 00:00:00 2001
From: Peng Fan <Peng.Fan@freescale.com>
Date: Tue, 27 Jan 2015 10:14:03 +0800
Subject: pmic:pfuze implement pmic_mode_init

This patch is to implement pmic_mode_init function, and add prototype
in header file.

This function is to set switching mode for pmic buck regulators to
improve system efficiency.

Mode:
OFF: The regulator is switched off and the output voltage is discharged.
PFM: In this mode, the regulator is always in PFM mode, which
     is useful at light loads for optimized efficiency.
PWM: In this mode, the regulator is always in PWM mode operation
     regardless of load conditions.
APS: In this mode, the regulator moves automatically between
     pulse skipping mode and PWM mode depending on load conditions.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>

diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
index 2cd1794..4980bf7 100644
--- a/board/freescale/common/pfuze.c
+++ b/board/freescale/common/pfuze.c
@@ -5,9 +5,47 @@
  */
 
 #include <common.h>
+#include <errno.h>
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 
+int pfuze_mode_init(struct pmic *p, u32 mode)
+{
+	unsigned char offset, i, switch_num;
+	u32 id, ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
+	id = id & 0xf;
+
+	if (id == 0) {
+		switch_num = 6;
+		offset = PFUZE100_SW1CMODE;
+	} else if (id == 1) {
+		switch_num = 4;
+		offset = PFUZE100_SW2MODE;
+	} else {
+		printf("Not supported, id=%d\n", id);
+		return -EINVAL;
+	}
+
+	ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
+	if (ret < 0) {
+		printf("Set SW1AB mode error!\n");
+		return ret;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
+		if (ret < 0) {
+			printf("Set switch 0x%x mode error!\n",
+			       offset + i * SWITCH_SIZE);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
 struct pmic *pfuze_common_init(unsigned char i2cbus)
 {
 	struct pmic *p;
diff --git a/board/freescale/common/pfuze.h b/board/freescale/common/pfuze.h
index 7a4126c..53cfc99 100644
--- a/board/freescale/common/pfuze.h
+++ b/board/freescale/common/pfuze.h
@@ -8,5 +8,6 @@
 #define __PFUZE_BOARD_HELPER__
 
 struct pmic *pfuze_common_init(unsigned char i2cbus);
+int pfuze_mode_init(struct pmic *p, u32 mode);
 
 #endif
-- 
cgit v0.10.2


From a4f7d098319a6521588d32ec21ac143c73b0899d Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Wed, 11 Feb 2015 12:35:46 +0100
Subject: pmic: fix missing SWITCH_SIZE

Applying ccbb18713b279f1326479cc10664d247206e9e76,
the define disappeared. Fix it.

Signed-off-by: Stefano Babic <sbabic@denx.de>

diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
index d304658..07199b4 100644
--- a/include/power/pfuze100_pmic.h
+++ b/include/power/pfuze100_pmic.h
@@ -232,5 +232,7 @@ enum {
 #define APS_PFM		0xc
 #define PWM_PFM		0xd
 
+#define SWITCH_SIZE	0x7
+
 int power_pfuze100_init(unsigned char bus);
 #endif
-- 
cgit v0.10.2


From 258c98f8d36ef35d7cb7604847ba73e64d702c2a Mon Sep 17 00:00:00 2001
From: Peng Fan <Peng.Fan@freescale.com>
Date: Tue, 27 Jan 2015 10:14:04 +0800
Subject: imx:mx6 set normal APS and standby PFM mode

To normal mode, use APS switching mode.
To standy mode, use PFM switching mode.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>

diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index a90360f..b76e4eb 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -29,6 +29,7 @@
 #include <asm/arch/crm_regs.h>
 #include <pca953x.h>
 #include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -494,11 +495,16 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
 int power_init_board(void)
 {
 	struct pmic *p;
+	unsigned int ret;
 
 	p = pfuze_common_init(I2C_PMIC);
 	if (!p)
 		return -ENODEV;
 
+	ret = pfuze_mode_init(p, APS_PFM);
+	if (ret < 0)
+		return ret;
+
 	return 0;
 }
 
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 2f7198d..bb2dd96 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -631,12 +631,16 @@ int board_init(void)
 int power_init_board(void)
 {
 	struct pmic *p;
-	unsigned int reg;
+	unsigned int reg, ret;
 
 	p = pfuze_common_init(I2C_PMIC);
 	if (!p)
 		return -ENODEV;
 
+	ret = pfuze_mode_init(p, APS_PFM);
+	if (ret < 0)
+		return ret;
+
 	/* Increase VGEN3 from 2.5 to 2.8V */
 	pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
 	reg &= ~LDO_VOL_MASK;
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index a2c9aae..2ff960e 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -199,12 +199,16 @@ static struct i2c_pads_info i2c_pad_info1 = {
 int power_init_board(void)
 {
 	struct pmic *p;
-	unsigned int reg;
+	unsigned int reg, ret;
 
 	p = pfuze_common_init(I2C_PMIC);
 	if (!p)
 		return -ENODEV;
 
+	ret = pfuze_mode_init(p, APS_PFM);
+	if (ret < 0)
+		return ret;
+
 	/* Enable power of VGEN5 3V3, needed for SD3 */
 	pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
 	reg &= ~LDO_VOL_MASK;
-- 
cgit v0.10.2


From 1f516faa45611aedc8c2e3f303b3866f615d481e Mon Sep 17 00:00:00 2001
From: Peng Fan <Peng.Fan@freescale.com>
Date: Thu, 15 Jan 2015 14:22:32 +0800
Subject: ARM: imx6: disable bandgap self-bias after boot

The self-bias circuit is used by the bandgap during startup.
Once the bandgap has stabilized, the self-bias circuit should
be disabled for best noise performance of analog blocks.
Also this bit should be disabled before the chip enters STOP mode or
when ever the regular bandgap is disabled.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index e599a12..df4e824 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -255,6 +255,23 @@ static void clear_mmdc_ch_mask(void)
 	writel(0, &mxc_ccm->ccdr);
 }
 
+static void init_bandgap(void)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	/*
+	 * Ensure the bandgap has stabilized.
+	 */
+	while (!(readl(&anatop->ana_misc0) & 0x80))
+		;
+	/*
+	 * For best noise performance of the analog blocks using the
+	 * outputs of the bandgap, the reftop_selfbiasoff bit should
+	 * be set.
+	 */
+	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
+}
+
+
 #ifdef CONFIG_MX6SL
 static void set_preclk_from_osc(void)
 {
@@ -275,6 +292,13 @@ int arch_cpu_init(void)
 	clear_mmdc_ch_mask();
 
 	/*
+	 * Disable self-bias circuit in the analog bandap.
+	 * The self-bias circuit is used by the bandgap during startup.
+	 * This bit should be set after the bandgap has initialized.
+	 */
+	init_bandgap();
+
+	/*
 	 * When low freq boot is enabled, ROM will not set AHB
 	 * freq, so we need to ensure AHB freq is 132MHz in such
 	 * scenario.
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 39f3c07..0592ce0 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -1063,4 +1063,6 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
 	(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
 
+#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
+
 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
-- 
cgit v0.10.2


From 83dd1dd91c71c75c943714ef93b5cbd8ccb7e1c9 Mon Sep 17 00:00:00 2001
From: Peng Fan <Peng.Fan@freescale.com>
Date: Thu, 15 Jan 2015 14:22:33 +0800
Subject: ARM: imx6 Add WDOG3 for i.MX6SX

There are three wdogs for i.MX 6SoloX. Add wdog3 support
in function imx_set_wdog_powerdown.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index df4e824..ef02972 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -230,6 +230,11 @@ static void imx_set_wdog_powerdown(bool enable)
 	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 
+#ifdef CONFIG_MX6SX
+	struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
+	writew(enable, &wdog3->wmcr);
+#endif
+
 	/* Write to the PDE (Power Down Enable) bit */
 	writew(enable, &wdog1->wmcr);
 	writew(enable, &wdog2->wmcr);
-- 
cgit v0.10.2


From 189d257b7ad9c6c9c84941be27de8e31a6e87e86 Mon Sep 17 00:00:00 2001
From: Christian Gmeiner <christian.gmeiner@gmail.com>
Date: Wed, 11 Feb 2015 15:19:31 +0100
Subject: cmd_eeprom: make it possible to define the used i2c bus

A SoC like the i.MX6 supports more then one i2c bus. In oder to be
able to use the eeprom command add a new define to specify the
i2c bus to use. If CONFIG_SYS_I2C_EEPROM_BUS is not defined there
is no functional change, else a call to i2c_set_bus_num(..) is
done before calling i2c_read(..) and i2c_write(..).

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>

diff --git a/README b/README
index ba57dc5..f38ab15 100644
--- a/README
+++ b/README
@@ -4341,6 +4341,9 @@ to save the current settings.
 	  If defined, specified the chip address of the EEPROM device.
 	  The default address is zero.
 
+	- CONFIG_SYS_I2C_EEPROM_BUS:
+	  If defined, specified the i2c bus of the EEPROM device.
+
 	- CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
 	  If defined, the number of bits used to address bytes in a
 	  single page in the EEPROM device.  A 64 byte page, for example
diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c
index 29f0f1f..e9904cd 100644
--- a/common/cmd_eeprom.c
+++ b/common/cmd_eeprom.c
@@ -161,6 +161,9 @@ int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt
 #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
 		spi_read (addr, alen, buffer, len);
 #else
+#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
+		i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
+#endif
 		if (i2c_read(addr[0], offset, alen - 1, buffer, len))
 			rcode = 1;
 #endif
@@ -339,6 +342,9 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn
 		/* Write is enabled ... now write eeprom value.
 		 */
 #endif
+#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
+		i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
+#endif
 		if (i2c_write(addr[0], offset, alen - 1, buffer, len))
 			rcode = 1;
 
-- 
cgit v0.10.2


From fb2589b3307bcbb1c763b2039a50b5e8198af048 Mon Sep 17 00:00:00 2001
From: Christian Gmeiner <christian.gmeiner@gmail.com>
Date: Wed, 11 Feb 2015 15:20:25 +0100
Subject: ot1200: add eeprom command to non-SPL build

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>

diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index c061e93..3c60b4f 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -131,6 +131,16 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
+#ifndef CONFIG_SPL
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_BUS             1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#endif
+
 /* Miscellaneous commands */
 #define CONFIG_CMD_BMODE
 #define CONFIG_CMD_SETEXPR
-- 
cgit v0.10.2


From 11c2e505c4505a8c709cfa65675ba07aedec4e76 Mon Sep 17 00:00:00 2001
From: Eric Nelson <eric.nelson@boundarydevices.com>
Date: Sun, 15 Feb 2015 14:37:21 -0700
Subject: ARM: i.MX: provide access to reset cause through
 get_imx_reset_cause()

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 28ccd29..067d08f 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -24,13 +24,16 @@
 #include <fsl_esdhc.h>
 #endif
 
-char *get_reset_cause(void)
+static u32 reset_cause = -1;
+
+static char *get_reset_cause(void)
 {
 	u32 cause;
 	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 
 	cause = readl(&src_regs->srsr);
 	writel(cause, &src_regs->srsr);
+	reset_cause = cause;
 
 	switch (cause) {
 	case 0x00001:
@@ -53,6 +56,11 @@ char *get_reset_cause(void)
 	}
 }
 
+u32 get_imx_reset_cause(void)
+{
+	return reset_cause;
+}
+
 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
 #if defined(CONFIG_MX53)
 #define MEMCTL_BASE	ESDCTL_BASE_ADDR
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 254136e..4715f4e 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -17,3 +17,5 @@
 #define CS0_64M_CS1_64M				1
 #define CS0_64M_CS1_32M_CS2_32M			2
 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M		3
+
+u32 get_imx_reset_cause(void);
-- 
cgit v0.10.2


From d9f43c8f5c1d7ed27c99a06be85a4bb64b2c73fb Mon Sep 17 00:00:00 2001
From: Eric Nelson <eric.nelson@boundarydevices.com>
Date: Sun, 15 Feb 2015 14:37:22 -0700
Subject: nitrogen6x: set environment variable reset_cause

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>

diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index e8ea256..d46b8db 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -1018,5 +1018,6 @@ int misc_init_r(void)
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
+	setenv_hex("reset_cause", get_imx_reset_cause());
 	return 0;
 }
-- 
cgit v0.10.2


From 5df3d19b1925ea63075664878fad84eeef28ea3e Mon Sep 17 00:00:00 2001
From: Soeren Moch <smoch@web.de>
Date: Fri, 23 Jan 2015 19:03:37 +0100
Subject: board: tbs2910: Gate clock when switching async clock muxes

According to the i.MX6Q Reference Manual, clocks must be gated when
switching input clocks of async clock muxes. So use clock gates. Avoid
ldb_di0_ipu clock, because there is no clock gate for this signal.

There have never been any complaints about problems with the old code,
but the new approach is in line with the recommendations in the manual.

Signed-off-by: Soeren Moch <smoch@web.de>

diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index dfa430e..42b166d 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -326,21 +326,25 @@ static void setup_display(void)
 	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 	writel(reg, &ccm->analog_pll_video);
 
-	/* select video pll for ldb_di0_clk */
-	reg = readl(&ccm->cs2cdr);
-	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
-	writel(reg, &ccm->cs2cdr);
+	/* gate ipu1_di0_clk */
+	reg = readl(&ccm->CCGR3);
+	reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &ccm->CCGR3);
 
-	/* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */
-	reg = readl(&ccm->cscmr2);
-	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
-	writel(reg, &ccm->cscmr2);
-
-	/* select ldb_di0_ipu_clk for ipu1_di0_clk -> 65MHz pixclock */
+	/* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
 	reg = readl(&ccm->chsccdr);
-	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
+		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
+		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
+	       (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
+	       (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 	writel(reg, &ccm->chsccdr);
+
+	/* enable ipu1_di0_clk */
+	reg = readl(&ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &ccm->CCGR3);
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 
-- 
cgit v0.10.2


From 9c3de876a1082b0390c7ddea9b5eda48d2dd7392 Mon Sep 17 00:00:00 2001
From: Peng Fan <Peng.Fan@freescale.com>
Date: Thu, 12 Feb 2015 09:36:27 +0800
Subject: imx:mx6sl add I2c pad settings

A few pad settings are I2C1

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 9ded3d8..0475203 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -58,5 +58,10 @@ enum {
 
 	MX6_PAD_KEY_COL4__USB_USBOTG1_PWR			= IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0),
 	MX6_PAD_KEY_COL5__USB_USBOTG2_PWR			= IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0),
+
+	MX6_PAD_I2C1_SDA__I2C1_SDA				= IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
+	MX6_PAD_I2C1_SDA__GPIO_3_13				= IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0),
+	MX6_PAD_I2C1_SCL__I2C1_SCL				= IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
+	MX6_PAD_I2C1_SCL__GPIO_3_12				= IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0),
 };
 #endif	/* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
-- 
cgit v0.10.2


From c82009058bd9d3fd9774cab36e9d89434f9563f4 Mon Sep 17 00:00:00 2001
From: Peng Fan <Peng.Fan@freescale.com>
Date: Thu, 12 Feb 2015 09:36:28 +0800
Subject: imx:mx6slevk add pmic and i2c configuration

Add pmic and i2c configuration in board header file.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index c567d9d..1221418 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -48,6 +48,18 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
-- 
cgit v0.10.2


From af38bf6b38eab53343afda2ad124682b27d82e64 Mon Sep 17 00:00:00 2001
From: Peng Fan <Peng.Fan@freescale.com>
Date: Thu, 12 Feb 2015 09:36:29 +0800
Subject: imx:mx6slevk implement power init board

Implement power_init_board and related I2C interface configuration.

After adding this, uboot can successfully detect and configure pmic.

"
U-Boot 2015.01-00281-ge29eddf (Feb 12 2015 - 09:24:01)

CPU:   Freescale i.MX6SL rev1.0 at 396 MHz
Reset cause: POR
Board: MX6SLEVK
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
"

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 838ea6c..c65f72b 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -13,13 +13,18 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
 #include <asm/imx-common/spi.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
 #include <fsl_esdhc.h>
+#include <i2c.h>
 #include <mmc.h>
 #include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
 #include <usb.h>
 #include <usb/ehci-fsl.h>
 
@@ -40,6 +45,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
 		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+		      PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
+		      PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
+		      PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
 #define ETH_PHY_RESET	IMX_GPIO_NR(4, 21)
 
 int dram_init(void)
@@ -221,6 +231,34 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC	MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info1 = {
+	.sda = {
+		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
+		.gp = IMX_GPIO_NR(3, 13),
+	},
+	.scl = {
+		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
+		.gp = IMX_GPIO_NR(3, 12),
+	},
+};
+
+int power_init_board(void)
+{
+	struct pmic *p;
+
+	p = pfuze_common_init(I2C_PMIC);
+	if (!p)
+		return -ENODEV;
+
+	return pfuze_mode_init(p, APS_PFM);
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
 int board_eth_init(bd_t *bis)
 {
@@ -297,6 +335,10 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_SYS_I2C_MXC
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
 #ifdef	CONFIG_FEC_MXC
 	setup_fec();
 #endif
-- 
cgit v0.10.2


From f022d36e8a4517b2a9d25ff2d75bd2459d0c68b1 Mon Sep 17 00:00:00 2001
From: Otavio Salvador <otavio@ossystems.com.br>
Date: Tue, 17 Feb 2015 10:42:43 -0200
Subject: mmc: fsl_esdhc: Add CMD11 support to switch to 1.8V

This adds support to switch to 1.8V in case CMD11 succeeds.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Marek Vasut <marex@denx.de>

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c55eb28..6a3e147 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -54,19 +54,21 @@ struct fsl_esdhc {
 	uint    fevt;		/* Force event register */
 	uint    admaes;		/* ADMA error status register */
 	uint    adsaddr;	/* ADMA system address register */
-	char    reserved2[160];	/* reserved */
+	char    reserved2[100];	/* reserved */
+	uint    vendorspec;	/* Vendor Specific register */
+	char    reserved3[59];	/* reserved */
 	uint    hostver;	/* Host controller version register */
-	char    reserved3[4];	/* reserved */
-	uint    dmaerraddr;	/* DMA error address register */
 	char    reserved4[4];	/* reserved */
-	uint    dmaerrattr;	/* DMA error attribute register */
+	uint    dmaerraddr;	/* DMA error address register */
 	char    reserved5[4];	/* reserved */
+	uint    dmaerrattr;	/* DMA error attribute register */
+	char    reserved6[4];	/* reserved */
 	uint    hostcapblt2;	/* Host controller capabilities register 2 */
-	char    reserved6[8];	/* reserved */
+	char    reserved7[8];	/* reserved */
 	uint    tcr;		/* Tuning control register */
-	char    reserved7[28];	/* reserved */
+	char    reserved8[28];	/* reserved */
 	uint    sddirctl;	/* SD direction control register */
-	char    reserved8[712];	/* reserved */
+	char    reserved9[712];	/* reserved */
 	uint    scr;		/* eSDHC control register */
 };
 
@@ -341,6 +343,15 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 		goto out;
 	}
 
+	/* Switch voltage to 1.8V if CMD11 succeeded */
+	if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
+		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+
+		printf("Run CMD11 1.8V switch\n");
+		/* Sleep for 5 ms - max time for card to switch to 1.8V */
+		udelay(5000);
+	}
+
 	/* Workaround for ESDHC errata ENGcm03648 */
 	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
 		int timeout = 2500;
@@ -413,6 +424,10 @@ out:
 			while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
 				;
 		}
+
+		/* If this was CMD11, then notify that power cycle is needed */
+		if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
+			printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
 	}
 
 	esdhc_write32(&regs->irqstat, -1);
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index c1b6648..e3d6581 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -154,6 +154,8 @@
 #define ESDHC_HOSTCAPBLT_DMAS	0x00400000
 #define ESDHC_HOSTCAPBLT_HSS	0x00200000
 
+#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
+
 struct fsl_esdhc_cfg {
 	u32	esdhc_base;
 	u32	sdhc_clk;
diff --git a/include/mmc.h b/include/mmc.h
index 56d97bb..e4b071e 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -88,6 +88,7 @@
 #define SD_CMD_SEND_RELATIVE_ADDR	3
 #define SD_CMD_SWITCH_FUNC		6
 #define SD_CMD_SEND_IF_COND		8
+#define SD_CMD_SWITCH_UHS18V		11
 
 #define SD_CMD_APP_SET_BUS_WIDTH	6
 #define SD_CMD_ERASE_WR_BLK_START	32
-- 
cgit v0.10.2


From ee0c538951018759eff4038db75e61b1cd040307 Mon Sep 17 00:00:00 2001
From: Otavio Salvador <otavio@ossystems.com.br>
Date: Tue, 17 Feb 2015 10:42:44 -0200
Subject: mmc: fsl_esdhc: Add support to force VSELECT set

Some boards cannot do voltage negotiation but need to set the VSELECT
bit forcely to ensure it to work at 1.8V.

This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc
index b70f271..619c6b2 100644
--- a/doc/README.fsl-esdhc
+++ b/doc/README.fsl-esdhc
@@ -1,5 +1,6 @@
 CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode.
 CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode.
+CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.
 
 Accessing ESDHC registers can be determined by ESDHC IP's endian
 mode or processor's endian mode.
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 6a3e147..67ee179 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -523,6 +523,10 @@ static int esdhc_init(struct mmc *mmc)
 	/* Set timout to the maximum value */
 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 
+#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
+	esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+#endif
+
 	return 0;
 }
 
-- 
cgit v0.10.2


From 8359318b5e99446513a003e1f2fde7188ea21009 Mon Sep 17 00:00:00 2001
From: Otavio Salvador <otavio@ossystems.com.br>
Date: Tue, 17 Feb 2015 10:42:45 -0200
Subject: imx: mx6sl: Extend USDHC SD2 pins to support 8-wire use

This adds the DATA[4-7] and RST pin definitions.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 0475203..6ba1034 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -31,7 +31,12 @@ enum {
 	MX6_PAD_SD2_DAT1__USDHC2_DAT1				= IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
 	MX6_PAD_SD2_DAT2__USDHC2_DAT2				= IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
 	MX6_PAD_SD2_DAT3__USDHC2_DAT3				= IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT4__USDHC2_DAT4				= IOMUX_PAD(0X0574, 0X026C, 0, 0X0000, 0, 0),
+	MX6_PAD_SD2_DAT5__USDHC2_DAT5				= IOMUX_PAD(0X0578, 0X0270, 0, 0X0000, 0, 0),
+	MX6_PAD_SD2_DAT6__USDHC2_DAT6				= IOMUX_PAD(0X057C, 0X0274, 0, 0X0000, 0, 0),
+	MX6_PAD_SD2_DAT7__USDHC2_DAT7				= IOMUX_PAD(0X0580, 0X0278, 0, 0X0000, 0, 0),
 	MX6_PAD_SD2_DAT7__GPIO_5_0					= IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0),
+	MX6_PAD_SD2_RST__USDHC2_RST				= IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, 0),
 	MX6_PAD_SD3_CLK__USDHC3_CLK					= IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0),
 	MX6_PAD_SD3_CMD__USDHC3_CMD					= IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0),
 	MX6_PAD_SD3_DAT0__USDHC3_DAT0				= IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0),
-- 
cgit v0.10.2


From 4579dc37c3cce36d9521c26c6e82881393ec769e Mon Sep 17 00:00:00 2001
From: Otavio Salvador <otavio@ossystems.com.br>
Date: Tue, 17 Feb 2015 10:42:46 -0200
Subject: warp: Add initial WaRP Board support

The WaRP Board is a Wearable Reference Plaform. The board features:

 - Freescale i.MX6 SoloLite processor with 512MB of RAM
 - Freescale FXOS8700CQ 6-axis Xtrinsic sensor
 - Freescale Kinetis KL16 MCU
 - Freescale Xtrinsic MMA955xL intelligent motion sensing platform

The board implements a hybrid architecture to address the evolving
needs of the wearables market. The platform consists of a main board
and an example daughtercard with the ability to add additional
daughtercards for different usage models.

For more information about the project, visit:

 http://www.warpboard.org/

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f1ccad..a3eb876 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -608,6 +608,10 @@ config TARGET_WANDBOARD
 	bool "Support wandboard"
 	select CPU_V7
 
+config TARGET_WARP
+	bool "Support WaRP"
+	select CPU_V7
+
 config TARGET_TITANIUM
 	bool "Support titanium"
 	select CPU_V7
@@ -1013,6 +1017,7 @@ source "board/ttcontrol/vision2/Kconfig"
 source "board/udoo/Kconfig"
 source "board/vpac270/Kconfig"
 source "board/wandboard/Kconfig"
+source "board/warp/Kconfig"
 source "board/woodburn/Kconfig"
 source "board/xaeniax/Kconfig"
 source "board/zipitz2/Kconfig"
diff --git a/board/warp/Kconfig b/board/warp/Kconfig
new file mode 100644
index 0000000..7b569cc
--- /dev/null
+++ b/board/warp/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_WARP
+
+config SYS_BOARD
+	default "warp"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "warp"
+
+endif
diff --git a/board/warp/MAINTAINERS b/board/warp/MAINTAINERS
new file mode 100644
index 0000000..ee2114d
--- /dev/null
+++ b/board/warp/MAINTAINERS
@@ -0,0 +1,6 @@
+WaRP BOARD
+M:	Otavio Salvador <otavio@ossystems.com.br>
+S:	Maintained
+F:	board/warp/
+F:	include/configs/warp.h
+F:	configs/warp_defconfig
diff --git a/board/warp/Makefile b/board/warp/Makefile
new file mode 100644
index 0000000..c555f87
--- /dev/null
+++ b/board/warp/Makefile
@@ -0,0 +1,8 @@
+# Copyright (C) 2014 O.S. Systems Software LTDA.
+# Copyright (C) 2014 Kynetics LLC.
+# Copyright (C) 2014 Revolution Robotics, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := warp.o
diff --git a/board/warp/warp.c b/board/warp/warp.c
new file mode 100644
index 0000000..3b275c2
--- /dev/null
+++ b/board/warp/warp.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2014, 2015 O.S. Systems Software LTDA.
+ * Copyright (C) 2014 Kynetics LLC.
+ * Copyright (C) 2014 Revolution Robotics, Inc.
+ *
+ * Author: Otavio Salvador <otavio@ossystems.com.br>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <watchdog.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS | \
+	PAD_CTL_LVE)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS | \
+	PAD_CTL_LVE)
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	static iomux_v3_cfg_t const uart1_pads[] = {
+		MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+		MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;	/* Assume boot SD always present */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	static iomux_v3_cfg_t const usdhc2_pads[] = {
+		MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_RST__USDHC2_RST | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+	hw_watchdog_init();
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: WaRP Board\n");
+
+	return 0;
+}
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
new file mode 100644
index 0000000..624a8af
--- /dev/null
+++ b/configs/warp_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
+CONFIG_ARM=y
+CONFIG_TARGET_WARP=y
diff --git a/include/configs/warp.h b/include/configs/warp.h
new file mode 100644
index 0000000..82036e4
--- /dev/null
+++ b/include/configs/warp.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (C) 2014 O.S. Systems Software LTDA.
+ * Copyright (C) 2014 Kynetics LLC.
+ * Copyright (C) 2014 Revolution Robotics, Inc.
+ *
+ * Author: Otavio Salvador <otavio@ossystems.com.br>
+ *
+ * Configuration settings for the WaRP Board
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_IPS_BASE_ADDR
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+/* Command definition */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_LOADADDR			0x82000000
+#define CONFIG_SYS_TEXT_BASE		0x87800000
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256
+
+/* Watchdog */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 /* 30s */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + SZ_256M)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE		SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			SZ_512M
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OFFSET		(6 * SZ_64K)
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+/* VDD voltage 1.65 - 1.95 */
+#define CONFIG_SYS_SD_VOLTAGE		0x00000080
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx6sl-warp.dtb\0" \
+	"fdt_addr=0x88000000\0" \
+	"initrd_addr=0x83800000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+#endif				/* __CONFIG_H */
-- 
cgit v0.10.2


From bcc5ea24c4b48c4bea6a02b179c4a2bac8377bdc Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Sat, 21 Feb 2015 17:22:49 -0200
Subject: mc34704: Add the definition of ONOFFA bit

ONOFFA is the bit 3 of the GENERAL2 register.

Add its definition.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/include/mc34704.h b/include/mc34704.h
index 53716e0..482d51a 100644
--- a/include/mc34704.h
+++ b/include/mc34704.h
@@ -40,6 +40,7 @@ enum {
 /* GENERAL2 register fields */
 #define ONOFFE		(1 << 0)
 #define ONOFFD		(1 << 1)
+#define ONOFFA		(1 << 3)
 #define ALLOFF		(1 << 4)
 
 #endif /* __MC34704_H__ */
-- 
cgit v0.10.2


From 86a390d30526ac96ae161fb389c7f151a136208f Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Sat, 21 Feb 2015 17:22:50 -0200
Subject: mx25pdk: Turn on the LCD supply

Currently there is no support for MC34704 PMIC in the mainline kernel.

Turn on the LCD supply via bootloader for the time being, so that we could
use the LCD in the kernel.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c
index 71a395c..01dac72 100644
--- a/board/freescale/mx25pdk/mx25pdk.c
+++ b/board/freescale/mx25pdk/mx25pdk.c
@@ -146,8 +146,8 @@ int board_late_init(void)
 	if (!p)
 		return -ENODEV;
 
-	/* Turn on Ethernet PHY supply */
-	pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
+	/* Turn on Ethernet PHY and LCD supplies */
+	pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE | ONOFFA);
 
 	return 0;
 }
-- 
cgit v0.10.2


From fe021777c7fd0171c00a73d2114c2e795519ad4e Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Mon, 23 Feb 2015 09:09:08 -0300
Subject: mx31: Fix boot hang by avoiding vector relocation

Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") mx31
does not boot anymore.

Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX31 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.

This allows mx31 to boot again.

Cc: Anatolij Gustschin <agust@denx.de>
Cc: Magnus Lilja <lilja.magnus@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/arch/arm/cpu/arm1136/mx31/Makefile b/arch/arm/cpu/arm1136/mx31/Makefile
index 9670ed9..dcbd570 100644
--- a/arch/arm/cpu/arm1136/mx31/Makefile
+++ b/arch/arm/cpu/arm1136/mx31/Makefile
@@ -8,3 +8,7 @@
 obj-y	+= generic.o
 obj-y	+= timer.o
 obj-y	+= devices.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y  += relocate.o
+endif
diff --git a/arch/arm/cpu/arm1136/mx31/relocate.S b/arch/arm/cpu/arm1136/mx31/relocate.S
new file mode 100644
index 0000000..1c556df
--- /dev/null
+++ b/arch/arm/cpu/arm1136/mx31/relocate.S
@@ -0,0 +1,23 @@
+/*
+ *  relocate - i.MX31-specific vector relocation
+ *
+ *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The i.MX31 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+	.section	.text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+	bx	lr
+
+ENDPROC(relocate_vectors)
-- 
cgit v0.10.2


From 26688b216d6c72e958e389174bc077e4a7cd96d2 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Mon, 23 Feb 2015 09:09:09 -0300
Subject: mx35: Fix boot hang by avoiding vector relocation

Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") mx35
does not boot anymore.

Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX35 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.

This allows mx35 to boot again.

Cc: Sebastian Priebe <sebastian.priebe@cadcon.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile
index c533215..796db9c 100644
--- a/arch/arm/cpu/arm1136/mx35/Makefile
+++ b/arch/arm/cpu/arm1136/mx35/Makefile
@@ -10,3 +10,7 @@
 obj-y	+= generic.o
 obj-y	+= timer.o
 obj-y	+= mx35_sdram.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y  += relocate.o
+endif
diff --git a/arch/arm/cpu/arm1136/mx35/relocate.S b/arch/arm/cpu/arm1136/mx35/relocate.S
new file mode 100644
index 0000000..43003f8
--- /dev/null
+++ b/arch/arm/cpu/arm1136/mx35/relocate.S
@@ -0,0 +1,23 @@
+/*
+ *  relocate - i.MX35-specific vector relocation
+ *
+ *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The i.MX35 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+	.section	.text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+	bx	lr
+
+ENDPROC(relocate_vectors)
-- 
cgit v0.10.2


From 6628aa57e1b61e9b1b829667269fd143c64e5ba2 Mon Sep 17 00:00:00 2001
From: Soeren Moch <smoch@web.de>
Date: Thu, 26 Feb 2015 19:50:02 +0100
Subject: board: tbs2910: Enable USB Mass Storage support

Add USB Mass Storage support. This is useful for flashing the on-board eMMC.

Signed-off-by: Soeren Moch <smoch@web.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index c097b98..7089378 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -165,6 +165,19 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+#ifdef CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW	0
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_G_DNL_VENDOR_NUM		0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER	"TBS"
+#endif /* CONFIG_CMD_USB_MASS_STORAGE */
 #define CONFIG_USB_KEYBOARD
 #ifdef CONFIG_USB_KEYBOARD
 #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
-- 
cgit v0.10.2


From ad8aae82b20ac6addc9683321d38e3c9fb028d52 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Thu, 26 Feb 2015 16:58:55 -0300
Subject: mx6sabre: Enable User Mass Storage

User Mass Storage is very useful for flashing the on-board eMMC.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>

diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 4aa8101..c3f1b35 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -276,4 +276,18 @@
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#define CONFIG_USB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+
+#define CONFIG_G_DNL_VENDOR_NUM		0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER	"FSL"
+
 #endif                         /* __MX6QSABRE_COMMON_CONFIG_H */
-- 
cgit v0.10.2


From b5cd10b911f632f74e1211ef786989781d2a1ca1 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Thu, 26 Feb 2015 16:58:56 -0300
Subject: mx6sabre: Select CMD_EXT4 options

Add EXT4 support.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>

diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index c3f1b35..f0e37f0 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -53,6 +53,8 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
-- 
cgit v0.10.2


From 0200020bc2b8192c31dc57c600865267f51bface Mon Sep 17 00:00:00 2001
From: Raul Cardenas <Ulises.Cardenas@freescale.com>
Date: Fri, 27 Feb 2015 11:22:06 -0600
Subject: imx6: Added DEK blob generator command

Freescale's SEC block has built-in Data Encryption
Key(DEK) Blob Protocol which provides a method for
protecting a DEK for non-secure memory storage.
SEC block protects data in a data structure called
a Secret Key Blob, which provides both confidentiality
and integrity protection.
Every time the blob encapsulation is executed,
a AES-256 key is randomly generated to encrypt the DEK.
This key is encrypted with the OTP Secret key
from SoC. The resulting blob consists of the encrypted
AES-256 key, the encrypted DEK, and a 16-bit MAC.

During decapsulation, the reverse process is performed
to get back the original DEK. A caveat to the blob
decapsulation process,  is that the DEK is decrypted
in secure-memory and can only be read by FSL SEC HW.
The DEK is used to decrypt data during encrypted boot.

Commands added
--------------
  dek_blob - encapsulating DEK as a cryptgraphic blob

Commands Syntax
---------------
  dek_blob src dst len

    Encapsulate and create blob of a len-bits DEK at
    address src and store the result at address dst.

Signed-off-by: Raul Cardenas <Ulises.Cardenas@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>

Signed-off-by: Ulises Cardenas <ulises.cardenas@freescale.com>

Signed-off-by: Ulises Cardenas-B45798 <Ulises.Cardenas@freescale.com>

diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 25a9d4c..606482f 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 endif
 obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
 obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
+obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
 
 quiet_cmd_cpp_cfg = CFGS    $@
       cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $<
diff --git a/arch/arm/imx-common/cmd_dek.c b/arch/arm/imx-common/cmd_dek.c
new file mode 100644
index 0000000..d93d5fb
--- /dev/null
+++ b/arch/arm/imx-common/cmd_dek.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Command for encapsulating DEK blob
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+#include <linux/compiler.h>
+#include <fsl_sec.h>
+#include <asm/arch/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+* blob_dek() - Encapsulate the DEK as a blob using CAM's Key
+* @src: - Address of data to be encapsulated
+* @dst: - Desination address of encapsulated data
+* @len: - Size of data to be encapsulated
+*
+* Returns zero on success,and negative on error.
+*/
+static int blob_encap_dek(const u8 *src, u8 *dst, u32 len)
+{
+	int ret = 0;
+	u32 jr_size = 4;
+
+	u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c);
+	if (out_jr_size != jr_size) {
+		hab_caam_clock_enable(1);
+		sec_init();
+	}
+
+	if (!((len == 128) | (len == 192) | (len == 256))) {
+		debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
+		return -1;
+	}
+
+	len /= 8;
+	ret = blob_dek(src, dst, len);
+
+	return ret;
+}
+
+/**
+ * do_dek_blob() - Handle the "dek_blob" command-line command
+ * @cmdtp:  Command data struct pointer
+ * @flag:   Command flag
+ * @argc:   Command-line argument count
+ * @argv:   Array of command-line arguments
+ *
+ * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
+ * on error.
+ */
+static int do_dek_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	uint32_t src_addr, dst_addr, len;
+	uint8_t *src_ptr, *dst_ptr;
+	int ret = 0;
+
+	if (argc != 4)
+		return CMD_RET_USAGE;
+
+	src_addr = simple_strtoul(argv[1], NULL, 16);
+	dst_addr = simple_strtoul(argv[2], NULL, 16);
+	len = simple_strtoul(argv[3], NULL, 10);
+
+	src_ptr = map_sysmem(src_addr, len/8);
+	dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len/8));
+
+	ret = blob_encap_dek(src_ptr, dst_ptr, len);
+
+	return ret;
+}
+
+/***************************************************/
+static char dek_blob_help_text[] =
+	"src dst len            - Encapsulate and create blob of data\n"
+	"                         $len bits long at address $src and\n"
+	"                         store the result at address $dst.\n";
+
+U_BOOT_CMD(
+	dek_blob, 4, 1, do_dek_blob,
+	"Data Encryption Key blob encapsulation",
+	dek_blob_help_text
+);
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index 65ef60b..e522990 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -176,3 +176,20 @@ ulong get_tbclk(void)
 {
 	return gpt_get_clk();
 }
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long usec)
+{
+	ulong ticks;
+
+	if (usec < 1000)
+		ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+	else
+		ticks = ((usec / 10) * (get_tbclk() / 100000));
+
+	return ticks;
+}
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index ae88b6e..9a4ad8b 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -215,6 +215,10 @@
 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
 #define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
+
+#define CONFIG_SYS_FSL_SEC_ADDR     CAAM_BASE_ADDR
+#define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + 0x1000)
+
 #define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
 #define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
 
diff --git a/doc/README.mxc_hab b/doc/README.mxc_hab
index 43e64a2..e9340dd 100644
--- a/doc/README.mxc_hab
+++ b/doc/README.mxc_hab
@@ -46,3 +46,51 @@ cat u-boot.imx U-Boot_CSF_pad.bin > u-boot-signed.imx
 
 NOTE: U-Boot_CSF.bin needs to be padded to the value specified in
 the imximage.cfg file.
+
+Setup U-Boot Image for Encrypted Boot
+-------------------------------------
+An authenticated U-Boot image is used as starting point for
+Encrypted Boot. The image is encrypted by Freescale's Code
+Signing Tool (CST). The CST replaces only the image data of
+u-boot.imx with the encrypted data. The Initial Vector Table,
+DCD, and Boot data, remains in plaintext.
+
+The image data is encrypted with a Encryption Key (DEK).
+Therefore, this key is needed to decrypt the data during the
+booting process. The DEK is protected by wrapping it in a Blob,
+which needs to be appended to the U-Boot image and specified in
+the CSF file.
+
+The DEK blob is generated by an authenticated U-Boot image with
+the dek_blob cmd enabled. The image used for DEK blob generation
+needs to have the following configurations enabled:
+
+CONFIG_SECURE_BOOT
+CONFIG_SYS_FSL_SEC_COMPAT    4 /* HAB version */
+CONFIG_FSL_CAAM
+CONFIG_CMD_DEKBLOB
+
+Note: The encrypted boot feature is only supported by HABv4 or
+greater.
+
+The dek_blob command then can be used to generate the DEK blob of
+a DEK previously loaded in memory. The command is used as follows:
+
+dek_blob <DEK address> <Output Address> <Key Size in Bits>
+example: dek_blob 0x10800000 0x10801000 192
+
+The resulting DEK blob then is used to construct the encrypted
+U-Boot image. Note that the blob needs to be transferred back
+to the host.Then the following commands are used to construct
+the final image.
+
+objcopy -I binary -O binary --pad-to 0x2000 --gap-fill=0x00 \
+    U-Boot_CSF.bin U-Boot_CSF_pad.bin
+cat u-boot.imx U-Boot_CSF_pad.bin > u-boot-signed.imx
+objcopy -I binary -O binary --pad-to <blob_dst> --gap-fill=0x00 \
+    u-boot-signed.imx u-boot-signed-pad.bin
+cat u-boot-signed-pad.imx DEK_blob.bin > u-boot-encrypted.imx
+
+    NOTE: u-boot-signed.bin needs to be padded to the value
+    equivalent to the address in which the DEK blob is specified
+    in the CSF.
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
index c0cf642..4aa91e4 100644
--- a/drivers/crypto/fsl/Makefile
+++ b/drivers/crypto/fsl/Makefile
@@ -8,5 +8,5 @@
 
 obj-y += sec.o
 obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
-obj-$(CONFIG_CMD_BLOB) += fsl_blob.o
+obj-$(CONFIG_CMD_BLOB)$(CONFIG_CMD_DEKBLOB) += fsl_blob.o
 obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o
diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h
index 504f2b0..18e2ec8 100644
--- a/drivers/crypto/fsl/desc.h
+++ b/drivers/crypto/fsl/desc.h
@@ -12,11 +12,18 @@
 #ifndef DESC_H
 #define DESC_H
 
+#define KEY_BLOB_SIZE		32
+#define MAC_SIZE			16
+
 /* Max size of any CAAM descriptor in 32-bit words, inclusive of header */
 #define MAX_CAAM_DESCSIZE	64
 
+/* Size of DEK Blob  descriptor, inclusive of header */
+#define DEK_BLOB_DESCSIZE	9
+
 /* Block size of any entity covered/uncovered with a KEK/TKEK */
 #define KEK_BLOCKSIZE		16
+
 /*
  * Supported descriptor command types as they show up
  * inside a descriptor command word.
@@ -273,6 +280,13 @@
 #define LDLEN_SET_OFIFO_OFFSET_MASK	(3 << LDLEN_SET_OFIFO_OFFSET_SHIFT)
 
 /*
+ * AAD Definitions
+ */
+#define AES_KEY_SHIFT		8
+#define LD_CCM_MODE		0x66
+#define KEY_AES_SRC		(0x55 << AES_KEY_SHIFT)
+
+/*
  * FIFO_LOAD/FIFO_STORE/SEQ_FIFO_LOAD/SEQ_FIFO_STORE
  * Command Constructs
  */
@@ -418,6 +432,7 @@
 #define OP_PCLID_MASK		(0xff << 16)
 
 /* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */
+#define OP_PCLID_SECMEM		0x08
 #define OP_PCLID_BLOB		(0x0d << OP_PCLID_SHIFT)
 #define OP_PCLID_SECRETKEY	(0x11 << OP_PCLID_SHIFT)
 #define OP_PCLID_PUBLICKEYPAIR	(0x14 << OP_PCLID_SHIFT)
diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c
index 9923bcb..8b25921 100644
--- a/drivers/crypto/fsl/fsl_blob.c
+++ b/drivers/crypto/fsl/fsl_blob.c
@@ -7,6 +7,8 @@
 
 #include <common.h>
 #include <malloc.h>
+#include <fsl_sec.h>
+#include <asm-generic/errno.h>
 #include "jobdesc.h"
 #include "desc.h"
 #include "jr.h"
@@ -59,3 +61,53 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
 	free(desc);
 	return ret;
 }
+
+#ifdef CONFIG_CMD_DEKBLOB
+int blob_dek(const u8 *src, u8 *dst, u8 len)
+{
+	int ret, size, i = 0;
+	u32 *desc;
+
+	int out_sz =  WRP_HDR_SIZE + len + KEY_BLOB_SIZE + MAC_SIZE;
+
+	puts("\nEncapsulating provided DEK to form blob\n");
+	desc = memalign(ARCH_DMA_MINALIGN,
+			sizeof(uint32_t) * DEK_BLOB_DESCSIZE);
+	if (!desc) {
+		debug("Not enough memory for descriptor allocation\n");
+		return -ENOMEM;
+	}
+
+	ret = inline_cnstr_jobdesc_blob_dek(desc, src, dst, len);
+	if (ret) {
+		debug("Error in Job Descriptor Construction:  %d\n", ret);
+	} else {
+		size = roundup(sizeof(uint32_t) * DEK_BLOB_DESCSIZE,
+			      ARCH_DMA_MINALIGN);
+		flush_dcache_range((unsigned long)desc,
+				   (unsigned long)desc + size);
+		size = roundup(sizeof(uint8_t) * out_sz, ARCH_DMA_MINALIGN);
+		flush_dcache_range((unsigned long)dst,
+				   (unsigned long)dst + size);
+
+		ret = run_descriptor_jr(desc);
+	}
+
+	if (ret) {
+		debug("Error in Encapsulation %d\n", ret);
+	   goto err;
+	}
+
+	size = roundup(out_sz, ARCH_DMA_MINALIGN);
+	invalidate_dcache_range((unsigned long)dst, (unsigned long)dst+size);
+
+	puts("DEK Blob\n");
+	for (i = 0; i < out_sz; i++)
+		printf("%02X", ((uint8_t *)dst)[i]);
+	printf("\n");
+
+err:
+	free(desc);
+	return ret;
+}
+#endif
diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c
index cc0dced..5695bef 100644
--- a/drivers/crypto/fsl/jobdesc.c
+++ b/drivers/crypto/fsl/jobdesc.c
@@ -9,12 +9,157 @@
  */
 
 #include <common.h>
+#include <fsl_sec.h>
 #include "desc_constr.h"
 #include "jobdesc.h"
 #include "rsa_caam.h"
 
-#define KEY_BLOB_SIZE			32
-#define MAC_SIZE			16
+#ifdef CONFIG_MX6
+/*!
+ * Secure memory run command
+ *
+ * @param   sec_mem_cmd  Secure memory command register
+ * @return  cmd_status  Secure memory command status register
+ */
+uint32_t secmem_set_cmd(uint32_t sec_mem_cmd)
+{
+	uint32_t temp_reg;
+
+	sec_out32(CAAM_SMCJR0, sec_mem_cmd);
+
+	do {
+		temp_reg = sec_in32(CAAM_SMCSJR0);
+	} while (temp_reg & CMD_COMPLETE);
+
+	return temp_reg;
+}
+
+/*!
+ * CAAM page allocation:
+ * Allocates a partition from secure memory, with the id
+ * equal to partion_num. This will de-allocate the page
+ * if it is already allocated. The partition will have
+ * full access permissions. The permissions are set before,
+ * running a job descriptor. A memory page of secure RAM
+ * is allocated for the partition.
+ *
+ * @param   page  Number of the page to allocate.
+ * @param   partition  Number of the partition to allocate.
+ * @return  0 on success, ERROR_IN_PAGE_ALLOC otherwise
+ */
+int caam_page_alloc(uint8_t page_num, uint8_t partition_num)
+{
+	uint32_t temp_reg;
+
+	/*
+	 * De-Allocate partition_num if already allocated to ARM core
+	 */
+	if (sec_in32(CAAM_SMPO_0) & PARTITION_OWNER(partition_num)) {
+		temp_reg = secmem_set_cmd(PARTITION(partition_num) |
+						CMD_PART_DEALLOC);
+		if (temp_reg & SMCSJR_AERR) {
+			printf("Error: De-allocation status 0x%X\n", temp_reg);
+			return ERROR_IN_PAGE_ALLOC;
+		}
+	}
+
+	/* set the access rights to allow full access */
+	sec_out32(CAAM_SMAG1JR0(partition_num), 0xF);
+	sec_out32(CAAM_SMAG2JR0(partition_num), 0xF);
+	sec_out32(CAAM_SMAPJR0(partition_num), 0xFF);
+
+	/* Now need to allocate partition_num of secure RAM. */
+	/* De-Allocate page_num by starting with a page inquiry command */
+	temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_INQUIRY);
+
+	/* if the page is owned, de-allocate it */
+	if ((temp_reg & SMCSJR_PO) == PAGE_OWNED) {
+		temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_PAGE_DEALLOC);
+		if (temp_reg & SMCSJR_AERR) {
+			printf("Error: Allocation status 0x%X\n", temp_reg);
+			return ERROR_IN_PAGE_ALLOC;
+		}
+	}
+
+	/* Allocate page_num to partition_num */
+	temp_reg = secmem_set_cmd(PAGE(page_num) | PARTITION(partition_num)
+						| CMD_PAGE_ALLOC);
+	if (temp_reg & SMCSJR_AERR) {
+		printf("Error: Allocation status 0x%X\n", temp_reg);
+		return ERROR_IN_PAGE_ALLOC;
+	}
+	/* page inquiry command to ensure that the page was allocated */
+	temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_INQUIRY);
+
+	/* if the page is not owned => problem */
+	if ((temp_reg & SMCSJR_PO) != PAGE_OWNED) {
+		printf("Allocation of page %d in partition %d failed 0x%X\n",
+		       temp_reg, page_num, partition_num);
+
+		return ERROR_IN_PAGE_ALLOC;
+	}
+
+	return 0;
+}
+
+int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,
+				       uint8_t *dek_blob, uint32_t in_sz)
+{
+	uint32_t ret = 0;
+	u32 aad_w1, aad_w2;
+	/* output blob will have 32 bytes key blob in beginning and
+	 * 16 byte HMAC identifier at end of data blob */
+	uint32_t out_sz = in_sz + KEY_BLOB_SIZE + MAC_SIZE;
+	/* Setting HDR for blob */
+	uint8_t wrapped_key_hdr[8] = {HDR_TAG, 0x00, WRP_HDR_SIZE + out_sz,
+			     HDR_PAR, HAB_MOD, HAB_ALG, in_sz, HAB_FLG};
+
+	/* initialize the blob array */
+	memset(dek_blob, 0, out_sz + 8);
+	/* Copy the header into the DEK blob buffer */
+	memcpy(dek_blob, wrapped_key_hdr, sizeof(wrapped_key_hdr));
+
+	/* allocating secure memory */
+	ret = caam_page_alloc(PAGE_1, PARTITION_1);
+	if (ret)
+		return ret;
+
+	/* Write DEK to secure memory */
+	memcpy((uint32_t *)SEC_MEM_PAGE1, (uint32_t *)plain_txt, in_sz);
+
+	unsigned long start = (unsigned long)SEC_MEM_PAGE1 &
+				~(ARCH_DMA_MINALIGN - 1);
+	unsigned long end = ALIGN(start + 0x1000, ARCH_DMA_MINALIGN);
+	flush_dcache_range(start, end);
+
+	/* Now configure the access rights of the partition */
+	sec_out32(CAAM_SMAG1JR0(PARTITION_1), KS_G1); /* set group 1 */
+	sec_out32(CAAM_SMAG2JR0(PARTITION_1), 0);     /* clear group 2 */
+	sec_out32(CAAM_SMAPJR0(PARTITION_1), PERM);   /* set perm & locks */
+
+	/* construct aad for AES */
+	aad_w1 = (in_sz << OP_ALG_ALGSEL_SHIFT) | KEY_AES_SRC | LD_CCM_MODE;
+	aad_w2 = 0x0;
+
+	init_job_desc(desc, 0);
+
+	append_cmd(desc, CMD_LOAD | CLASS_2 | KEY_IMM | KEY_ENC |
+				(0x0c << LDST_OFFSET_SHIFT) | 0x08);
+
+	append_u32(desc, aad_w1);
+
+	append_u32(desc, aad_w2);
+
+	append_cmd_ptr(desc, (dma_addr_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR);
+
+	append_cmd_ptr(desc, (dma_addr_t)dek_blob + 8, out_sz, CMD_SEQ_OUT_PTR);
+
+	append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB |
+						OP_PCLID_SECMEM);
+
+	return ret;
+}
+#endif
 
 void inline_cnstr_jobdesc_hash(uint32_t *desc,
 			  const uint8_t *msg, uint32_t msgsz, uint8_t *digest,
diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h
index 84b3edd..112404c 100644
--- a/drivers/crypto/fsl/jobdesc.h
+++ b/drivers/crypto/fsl/jobdesc.h
@@ -14,6 +14,20 @@
 
 #define KEY_IDNFR_SZ_BYTES		16
 
+#ifdef CONFIG_CMD_DEKBLOB
+/* inline_cnstr_jobdesc_blob_dek:
+ * Intializes and constructs the job descriptor for DEK encapsulation
+ * using the given parameters.
+ * @desc: reference to the job descriptor
+ * @plain_txt: reference to the DEK
+ * @enc_blob: reference where to store the blob
+ * @in_sz: size in bytes of the DEK
+ * @return: 0 on success, ECONSTRJDESC otherwise
+ */
+int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,
+				uint8_t *enc_blob, uint32_t in_sz);
+#endif
+
 void inline_cnstr_jobdesc_hash(uint32_t *desc,
 			  const uint8_t *msg, uint32_t msgsz, uint8_t *digest,
 			  u32 alg_type, uint32_t alg_size, int sg_tbl);
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index f9d4938..f99d594 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -90,11 +90,13 @@ static int jr_init(void)
 	jr.liodn = DEFAULT_JR_LIODN;
 #endif
 	jr.size = JR_SIZE;
-	jr.input_ring = (dma_addr_t *)malloc(JR_SIZE * sizeof(dma_addr_t));
+	jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
+				JR_SIZE * sizeof(dma_addr_t));
 	if (!jr.input_ring)
 		return -1;
 	jr.output_ring =
-	    (struct op_ring *)malloc(JR_SIZE * sizeof(struct op_ring));
+	    (struct op_ring *)memalign(ARCH_DMA_MINALIGN,
+				JR_SIZE * sizeof(struct op_ring));
 	if (!jr.output_ring)
 		return -1;
 
@@ -163,13 +165,23 @@ static int jr_enqueue(uint32_t *desc_addr,
 	    CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
 		return -1;
 
-	jr.input_ring[head] = desc_phys_addr;
 	jr.info[head].desc_phys_addr = desc_phys_addr;
 	jr.info[head].desc_addr = (uint32_t)desc_addr;
 	jr.info[head].callback = (void *)callback;
 	jr.info[head].arg = arg;
 	jr.info[head].op_done = 0;
 
+	unsigned long start = (unsigned long)&jr.info[head] &
+					~(ARCH_DMA_MINALIGN - 1);
+	unsigned long end = ALIGN(start + sizeof(struct jr_info),
+					ARCH_DMA_MINALIGN);
+	flush_dcache_range(start, end);
+
+	jr.input_ring[head] = desc_phys_addr;
+	start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
+	end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
+	flush_dcache_range(start, end);
+
 	jr.head = (head + 1) & (jr.size - 1);
 
 	sec_out32(&regs->irja, 1);
@@ -187,6 +199,13 @@ static int jr_dequeue(void)
 	void *arg = NULL;
 
 	while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
+		unsigned long start = (unsigned long)jr.output_ring &
+					~(ARCH_DMA_MINALIGN - 1);
+		unsigned long end = ALIGN(start +
+					  sizeof(struct op_ring)*JR_SIZE,
+					  ARCH_DMA_MINALIGN);
+		invalidate_dcache_range(start, end);
+
 		found = 0;
 
 		dma_addr_t op_desc = jr.output_ring[jr.tail].desc;
@@ -333,13 +352,17 @@ static int instantiate_rng(void)
 
 	memset(&op, 0, sizeof(struct result));
 
-	desc = malloc(sizeof(int) * 6);
+	desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
 	if (!desc) {
 		printf("cannot allocate RNG init descriptor memory\n");
 		return -1;
 	}
 
 	inline_cnstr_jobdesc_rng_instantiation(desc);
+	int size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
+	flush_dcache_range((unsigned long)desc,
+			   (unsigned long)desc + size);
+
 	ret = run_descriptor_jr(desc);
 
 	if (ret)
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index b6e6f04..dbfae68 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -135,7 +135,7 @@ typedef struct ccsr_sec {
 #define CONFIG_JRSTARTR_JR0		0x00000001
 
 struct jr_regs {
-#ifdef CONFIG_SYS_FSL_SEC_LE
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
 	u32 irba_l;
 	u32 irba_h;
 #else
@@ -148,7 +148,7 @@ struct jr_regs {
 	u32 irsa;
 	u32 rsvd3;
 	u32 irja;
-#ifdef CONFIG_SYS_FSL_SEC_LE
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
 	u32 orba_l;
 	u32 orba_h;
 #else
@@ -180,7 +180,7 @@ struct jr_regs {
  * related information
  */
 struct sg_entry {
-#ifdef CONFIG_SYS_FSL_SEC_LE
+#ifdef defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
 	uint32_t addr_lo;	/* Memory Address - lo */
 	uint16_t addr_hi;	/* Memory Address of start of buffer - hi */
 	uint16_t reserved_zero;
@@ -201,7 +201,79 @@ struct sg_entry {
 #define SG_ENTRY_OFFSET_SHIFT	0
 };
 
+#ifdef CONFIG_MX6
+/* CAAM Job Ring 0 Registers */
+/* Secure Memory Partition Owner register */
+#define SMCSJR_PO		(3 << 6)
+/* JR Allocation Error */
+#define SMCSJR_AERR		(3 << 12)
+/* Secure memory partition 0 page 0 owner register */
+#define CAAM_SMPO_0		CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC
+/* Secure memory command register */
+#define CAAM_SMCJR0		CONFIG_SYS_FSL_SEC_ADDR + 0x10f4
+/* Secure memory command status register */
+#define CAAM_SMCSJR0		CONFIG_SYS_FSL_SEC_ADDR + 0x10fc
+/* Secure memory access permissions register */
+#define CAAM_SMAPJR0(y)	(CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16)
+/* Secure memory access group 2 register */
+#define CAAM_SMAG2JR0(y)	(CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16)
+/* Secure memory access group 1 register */
+#define CAAM_SMAG1JR0(y)	(CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16)
+
+/* Commands and macros for secure memory */
+#define CMD_PAGE_ALLOC		0x1
+#define CMD_PAGE_DEALLOC	0x2
+#define CMD_PART_DEALLOC	0x3
+#define CMD_INQUIRY		0x5
+#define CMD_COMPLETE		(3 << 14)
+#define PAGE_AVAILABLE		0
+#define PAGE_OWNED		(3 << 6)
+#define PAGE(x)			(x << 16)
+#define PARTITION(x)		(x << 8)
+#define PARTITION_OWNER(x)	(0x3 << (x*2))
+
+/* Address of secure 4kbyte pages */
+#define SEC_MEM_PAGE0		CAAM_ARB_BASE_ADDR
+#define SEC_MEM_PAGE1		(CAAM_ARB_BASE_ADDR + 0x1000)
+#define SEC_MEM_PAGE2		(CAAM_ARB_BASE_ADDR + 0x2000)
+#define SEC_MEM_PAGE3		(CAAM_ARB_BASE_ADDR + 0x3000)
+
+#define JR_MID			2               /* Matches ROM configuration */
+#define KS_G1			(1 << JR_MID)   /* CAAM only */
+#define PERM			0x0000B008      /* Clear on release, lock SMAP
+						 * lock SMAG group 1 Blob */
+
+#define BLOB_SIZE(x)       (x + 32 + 16) /* Blob buffer size */
+
+/* HAB WRAPPED KEY header */
+#define WRP_HDR_SIZE		0x08
+#define HDR_TAG			0x81
+#define HDR_PAR			0x41
+/* HAB WRAPPED KEY Data */
+#define HAB_MOD			0x66
+#define HAB_ALG			0x55
+#define HAB_FLG			0x00
+
+/* Partition and Page IDs */
+#define PARTITION_1	1
+#define PAGE_1			1
+
+#define ERROR_IN_PAGE_ALLOC	1
+#define ECONSTRJDESC   -1
+
+#endif
+
 int sec_init(void);
+
+/* blob_dek:
+ * Encapsulates the src in a secure blob and stores it dst
+ * @src: reference to the plaintext
+ * @dst: reference to the output adrress
+ * @len: size in bytes of src
+ * @return: 0 on success, error otherwise
+ */
+int blob_dek(const u8 *src, u8 *dst, u8 len);
+
 #endif
 
 #endif /* __FSL_SEC_H */
-- 
cgit v0.10.2


From 16edd347f0e4e0c77c9a667855e3293b58bb3fda Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Sat, 28 Feb 2015 14:25:46 -0300
Subject: mx6slevk: Provide a proper pad configuration for OTG1_ID pin

Pass the same pad configuration as done in the kernel so that OTG1_ID pin can
properly work in device mode.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index c65f72b..7c18c90 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -50,6 +50,11 @@ DECLARE_GLOBAL_DATA_PTR;
 		      PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
 		      PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
+#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+			PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
+			PAD_CTL_DSE_80ohm | PAD_CTL_HYS |	\
+			PAD_CTL_SRE_FAST)
+
 #define ETH_PHY_RESET	IMX_GPIO_NR(4, 21)
 
 int dram_init(void)
@@ -285,7 +290,7 @@ static int setup_fec(void)
 static iomux_v3_cfg_t const usb_otg_pads[] = {
 	/* OTG1 */
 	MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
 	/* OTG2 */
 	MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
 };
-- 
cgit v0.10.2


From 09ac7b5961396ffb8644e180180b33008e0b6b35 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Sat, 28 Feb 2015 15:16:42 -0300
Subject: warp: Add USB Mass Storage support

With UMS support we are able to flash the eMMC from U-boot, which is very
convenient.

Add UMS support to make the eMMC flashing process easier.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>

diff --git a/board/warp/warp.c b/board/warp/warp.c
index 3b275c2..21ac5e7 100644
--- a/board/warp/warp.c
+++ b/board/warp/warp.c
@@ -21,6 +21,7 @@
 #include <watchdog.h>
 #include <fsl_esdhc.h>
 #include <mmc.h>
+#include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -82,6 +83,11 @@ int board_mmc_init(bd_t *bis)
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 }
 
+int board_usb_phy_mode(int port)
+{
+	return USB_INIT_DEVICE;
+}
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
diff --git a/include/configs/warp.h b/include/configs/warp.h
index 82036e4..22acdca 100644
--- a/include/configs/warp.h
+++ b/include/configs/warp.h
@@ -120,6 +120,32 @@
 #define CONFIG_CMD_CACHE
 #endif
 
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1 /* Only OTG2 port enabled */
+#endif
+
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#define CONFIG_USB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+
+#define CONFIG_G_DNL_VENDOR_NUM		0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER	"FSL"
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
-- 
cgit v0.10.2


From b16c37e46c1993b7d789aa7a1840250369d6944c Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Sat, 28 Feb 2015 15:16:43 -0300
Subject: warp: Select BOUNCE_BUFFER and CMD_EXT options

Add EXT2/EXT4 and BOUNCE_BUFFER support.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>

diff --git a/include/configs/warp.h b/include/configs/warp.h
index 22acdca..bcdd112 100644
--- a/include/configs/warp.h
+++ b/include/configs/warp.h
@@ -46,6 +46,10 @@
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
-- 
cgit v0.10.2


From 32df39c741788e8637cffe6633d73594b26d70fb Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Mon, 2 Mar 2015 10:12:13 +0100
Subject: mx5: fix get_reset_cause

commit d9f43c8f5c1d7ed27c99a06be85a4bb64b2c73fb sets
get_reset_cause() as static, but this conflicts with mx5
where its prototype is in sys_proto.h.

Drop it from sys_proto.h and drop print_cpuinfo from mx53_loco,
factorizing the call for this board.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <jason.hui@linaro.org>

diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
index ac7705b..b06c77f 100644
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -24,6 +24,5 @@ void set_chipselect_size(int const);
 int fecmxc_initialize(bd_t *bis);
 u32 get_ahb_clk(void);
 u32 get_periph_clk(void);
-char *get_reset_cause(void);
 
 #endif
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index efcf4b3..9ece6ec 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -366,22 +366,6 @@ int board_early_init_f(void)
 	return 0;
 }
 
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	u32 cpurev;
-
-	cpurev = get_cpu_rev();
-	printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
-		(cpurev & 0xFF000) >> 12,
-		(cpurev & 0x000F0) >> 4,
-		(cpurev & 0x0000F) >> 0,
-		mxc_get_clock(MXC_ARM_CLK) / 1000000);
-	printf("Reset cause: %s\n", get_reset_cause());
-	return 0;
-}
-#endif
-
 /*
  * Do not overwrite the console
  * Use always serial for U-Boot console
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 42bc3c8..8d8b93c 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -24,6 +24,8 @@
 
 #define CONFIG_SYS_GENERIC_BOARD
 
+#define CONFIG_DISPLAY_CPUINFO
+
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 
-- 
cgit v0.10.2