From 18f66cbeb6515de281325145df92704e6ac80dde Mon Sep 17 00:00:00 2001 From: Vinitha Pillai-B57223 Date: Wed, 2 Aug 2017 14:47:57 +0530 Subject: LS2080ARDB: QSPI boot: Secure Boot image validation Validates the images in the ESBC phase for LS2088ARDB platform and QSPI boot using esbc_validate command. Add images validation in default environment under mcinitcmd prior to MC initialization. Adds header address for PPA to be validated during ESBC phase for ARCH_LS2088 and QSPI_BOOT. Moves sec_init prior to ppa_init as for validation of PPA sec must be initialised before the PPA is initialised. Signed-off-by: Vinitha Pillai-B57223 Signed-off-by: Udit Agarwal diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 45bf3d8..6c2ba4f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -195,6 +195,7 @@ config SYS_LS_PPA_ESBC_ADDR default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A + default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 default 0x680000 if SYS_LS_PPA_FW_IN_MMC default 0x680000 if SYS_LS_PPA_FW_IN_NAND diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index d9a3826..5ebe0cf 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -72,8 +72,13 @@ * DDR memory map */ #ifdef CONFIG_FSL_LSCH3 +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_BS_ADDR_DEVICE 0x20600000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x20640000 +#else /* NOR BOOT */ #define CONFIG_BS_ADDR_DEVICE 0x580600000 #define CONFIG_BS_HDR_ADDR_DEVICE 0x580640000 +#endif /*ifdef CONFIG_QSPI_BOOT */ #define CONFIG_BS_SIZE 0x00001000 #define CONFIG_BS_HDR_SIZE 0x00004000 #define CONFIG_BS_ADDR_RAM 0xa0600000 diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index f332b6f..00d905f 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 NXP Semiconductors + * Copyright 2017 NXP * Copyright 2015 Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ @@ -218,6 +218,10 @@ int board_init(void) #ifdef CONFIG_FSL_QIXIS QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); #endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif @@ -226,9 +230,6 @@ int board_init(void) /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif return 0; } diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 0a4c90c..50a907c 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -363,6 +363,27 @@ unsigned long get_board_sys_clk(void); /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS #ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "scriptaddr=0x80800000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x81000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x89000000\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x21000000\0" \ + "mcmemsize=0x40000000\0" \ + "mcinitcmd=esbc_validate 0x20700000;" \ + "esbc_validate 0x20740000;" \ + "fsl_mc start mc 0x20a00000" \ + " 0x20e00000 \0" \ + BOOTENV +#else /* !(CONFIG_QSPI_BOOT) */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "scriptaddr=0x80800000\0" \ @@ -386,6 +407,7 @@ unsigned long get_board_sys_clk(void); "fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" \ BOOTENV +#endif #else #ifdef CONFIG_QSPI_BOOT #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v0.10.2