From e0ebd4c63c3dc48172d39fb03a1f0e4cdf86a4d3 Mon Sep 17 00:00:00 2001 From: Suresh Gupta Date: Fri, 14 Oct 2016 12:26:24 +0530 Subject: armv8: Add workaround for USB erratum A-008997 USB3 LFPS Peak-Peak Differential Output Voltage Adjustment This patch is adding the erratum for LS1043 and LS2080 SoCs. But miss LS1088A due to code base not support LS1088A yet, need to be added in arch/arm/cpu/armv8/fsl-layerscape/Kconfig in the future. Signed-off-by: Sriram Dash Signed-off-by: Rajesh Bhagat Signed-off-by: yinbo.zhu Signed-off-by: ran.wang diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 465976f..ccc4ed4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -7,6 +7,7 @@ config ARCH_LS1012A select SYS_FSL_MMDC select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A008997 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F @@ -19,6 +20,7 @@ config ARCH_LS1043A select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009660 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009663 @@ -41,6 +43,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008511 select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009801 select SYS_FSL_ERRATUM_A009803 select SYS_FSL_ERRATUM_A009942 @@ -77,6 +80,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A008585 select SYS_FSL_ERRATUM_A009635 select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009801 select SYS_FSL_ERRATUM_A009803 @@ -91,6 +95,7 @@ config FSL_LSCH2 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_BE + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -98,6 +103,7 @@ config FSL_LSCH3 bool select SYS_FSL_SRDS_1 select SYS_HAS_SERDES + select SYS_FSL_ERRATUM_A008997 config FSL_MC_ENET bool "Management Complex network" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index c4aaa1a..e73612a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -45,6 +45,33 @@ scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE); #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ } +static void erratum_a008997(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008997 +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A) + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4); + val &= ~(0x7F << 9); + scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4, + val | (USB_PCSTXSWINGFULL << 9)); + val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4); + val &= ~(0x7F << 9); + scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4, + val | (USB_PCSTXSWINGFULL << 9)); + val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4); + val &= ~(0x7F << 9); + scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4, + val | (USB_PCSTXSWINGFULL << 9)); +#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4); + val &= ~(0x7F << 9); + scfg_out32(scfg + SCFG_USB3PRM2CR / 4, + val | (USB_PCSTXSWINGFULL << 9)); +#endif +#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ +} + bool soc_has_dp_ddr(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -219,6 +246,7 @@ void fsl_lsch3_early_init_f(void) erratum_a008336(); erratum_a009008(); erratum_a009798(); + erratum_a008997(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -495,6 +523,7 @@ void fsl_lsch2_early_init_f(void) erratum_a009660(); erratum_a010539(); erratum_a009798(); + erratum_a008997(); } #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 0cd0d30..4fac487 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -199,8 +199,12 @@ struct ccsr_gur { #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 +#define SCFG_BASE 0x01570000 +#define SCFG_USB3PRM1CR_USB1 0x070 +#define SCFG_USB3PRM2CR_USB1 0x074 #define SCFG_USB3PRM1CR_USB2 0x07C #define SCFG_USB3PRM1CR_USB3 0x088 +#define SCFG_USB3PRM2CR_USB3 0x08c #define USB_TXVREFTUNE 0x9 #define USB_SQRXTUNE 0xFC7FFFFF diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 62113e5..b6be6ab 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -132,9 +132,11 @@ /* Supplemental Configuration */ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 +#define SCFG_USB3PRM2CR 0x004 #define SCFG_USB3PRM1CR_INIT 0x27672b2a #define USB_TXVREFTUNE 0x9 #define USB_SQRXTUNE 0xFC7FFFFF +#define USB_PCSTXSWINGFULL 0x47 #define SCFG_QSPICLKCTLR 0x10 #define TP_ITYP_AV 0x00000001 /* Initiator available */ -- cgit v0.10.2