From 3098e539d6a67df9f2a3c402d62147fa10422150 Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Fri, 14 Apr 2017 16:49:01 +0800
Subject: armv8: ls1046a: enable PCI command tool

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 957ffd3..80f8dc2 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -138,6 +138,16 @@
 #define CONFIG_SYS_I2C_MXC_I2C3
 #define CONFIG_SYS_I2C_MXC_I2C4
 
+/* PCIe */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+#define CONFIG_PCIE3		/* PCIE controller 3 */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#endif
+
 /* Command line configuration */
 #ifndef SPL_NO_ENV
 #define CONFIG_CMD_ENV
-- 
cgit v0.10.2


From 5193405a163aa9bab068680167fdeb0e1008e7b5 Mon Sep 17 00:00:00 2001
From: Priyanka Jain <priyanka.jain@nxp.com>
Date: Tue, 25 Apr 2017 10:12:31 +0530
Subject: board: freescale: ls2080ardb: Enable SD interface for RevF board

LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
which needs to be programmed to enable high speed SD interface
by setting GPIO4_10 output to zero.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 80c421f..59410aa 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -1,6 +1,7 @@
 /*
  * LayerScape Internal Memory Map
  *
+ * Copyright (C) 2017 NXP Semiconductors
  * Copyright 2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -45,6 +46,9 @@
 #define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01010000)
 #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
 #define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)
+#define GPIO4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01330000)
+#define GPIO4_GPDIR_ADDR			(GPIO4_BASE_ADDR + 0x0)
+#define GPIO4_GPDAT_ADDR			(GPIO4_BASE_ADDR + 0x8)
 
 #define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
 #define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02110000)
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index ea05ec6..c2aa101 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2017 NXP Semiconductors
  * Copyright 2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -205,6 +206,23 @@ int board_early_init_f(void)
 
 int misc_init_r(void)
 {
+#ifdef CONFIG_FSL_QIXIS
+	u8 sw;
+
+	sw = QIXIS_READ(arch);
+	/*
+	 * LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
+	 * which needs to be programmed to enable high speed SD interface
+	 * by setting GPIO4_10 output to zero
+	 */
+	if ((sw & 0xf) == 0x5) {
+		out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
+					    in_le32(GPIO4_GPDIR_ADDR)));
+		out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
+					    in_le32(GPIO4_GPDAT_ADDR)));
+	}
+#endif
+
 	if (hwconfig("sdhc"))
 		config_board_mux(MUX_TYPE_SDHC);
 
-- 
cgit v0.10.2


From e9420444f64a0ec3b444204ada20c10a50f93800 Mon Sep 17 00:00:00 2001
From: Suresh Gupta <suresh.gupta@nxp.com>
Date: Tue, 25 Apr 2017 14:51:37 +0530
Subject: armv8: layperscape: remove CONFIG_SPI_FLASH_BAR from some platforms

ls1012ardb, ls1046ardb, ls2080ardb have S25FS512S flash which does
not support Bank Address Register commands.

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 09f890d..0db926f 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -55,7 +55,6 @@
 #define CONFIG_FSL_QSPI
 #define QSPI0_AMBA_BASE		0x40000000
 #define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_BAR
 
 #define FSL_QSPI_FLASH_SIZE		(1 << 24)
 #define FSL_QSPI_FLASH_NUM		2
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 67ee626..66af039 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -208,7 +208,6 @@
 #define CONFIG_SPI_FLASH_SPANSION
 #define FSL_QSPI_FLASH_SIZE		(1 << 26)
 #define FSL_QSPI_FLASH_NUM		2
-#define CONFIG_SPI_FLASH_BAR
 #endif
 #endif
 
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index d0bf552..ec83eb5 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -265,7 +265,6 @@ unsigned long get_board_sys_clk(void);
 /* SPI */
 #ifdef CONFIG_FSL_DSPI
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_BAR
 #define CONFIG_SPI_FLASH_STMICRO
 #endif
 
-- 
cgit v0.10.2


From 5e3f763a4b00b6ca99e3e7e30544c78a8cb05f20 Mon Sep 17 00:00:00 2001
From: Suresh Gupta <suresh.gupta@nxp.com>
Date: Tue, 25 Apr 2017 14:51:38 +0530
Subject: armv8: ls1012a: fix the size of flash for multiple boards

LS1012AFRDM, LS1012ARDB, LS1012AQDS all have S25FS512S flash
of 64MB size.

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 0db926f..861cbc3 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -56,7 +56,7 @@
 #define QSPI0_AMBA_BASE		0x40000000
 #define CONFIG_SPI_FLASH_SPANSION
 
-#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_SIZE		SZ_64M
 #define FSL_QSPI_FLASH_NUM		2
 
 /*
-- 
cgit v0.10.2


From 99b47c25d0e2bdc9ebbd685a87456e175581c695 Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Tue, 25 Apr 2017 08:39:51 -0700
Subject: armv8: ls1046ardb: Make NET independent of FMan

This allows using PCIe NIC without enabling DPAA FMan.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Mingkai Hu <mingkai.hu@nxp.com>
Acked-by: Mingkai Hu <mingkai.hu@nxp.com>

diff --git a/board/freescale/ls1046ardb/Makefile b/board/freescale/ls1046ardb/Makefile
index b92ed0b..4076558 100644
--- a/board/freescale/ls1046ardb/Makefile
+++ b/board/freescale/ls1046ardb/Makefile
@@ -7,6 +7,6 @@
 obj-y += ddr.o
 obj-y += ls1046ardb.o
 ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
+obj-$(CONFIG_NET) += eth.o
 obj-y += cpld.o
 endif
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 66af039..7161ee8 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -178,18 +178,20 @@
 #define CONFIG_ENV_SECT_SIZE		0x40000		/* 256KB */
 #endif
 
+#define AQR105_IRQ_MASK			0x80000000
 /* FMan */
 #ifndef SPL_NO_FMAN
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
+
+#ifdef CONFIG_NET
 #define CONFIG_PHYLIB
-#define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
-
 #define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_AQUANTIA
-#define AQR105_IRQ_MASK			0x80000000
+#endif
 
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHY_AQUANTIA
+#define CONFIG_PHYLIB_10G
 #define RGMII_PHY1_ADDR			0x1
 #define RGMII_PHY2_ADDR			0x2
 
@@ -200,6 +202,7 @@
 
 #define CONFIG_ETHPRIME			"FM1@DTSEC3"
 #endif
+
 #endif
 
 /* QSPI device */
-- 
cgit v0.10.2


From c40e6f916982bfaa38aef642461cbcb5917f2744 Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Tue, 25 Apr 2017 08:39:52 -0700
Subject: armv8: ls1043ardb: Make NET independent of FMan

This allows using PCIe NIC without enabling DPAA FMan.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Mingkai Hu <mingkai.hu@nxp.com>
Acked-by: Mingkai Hu <mingkai.hu@nxp.com>

diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile
index 2a4452e..930c690 100644
--- a/board/freescale/ls1043ardb/Makefile
+++ b/board/freescale/ls1043ardb/Makefile
@@ -7,6 +7,6 @@
 obj-y += ddr.o
 obj-y += ls1043ardb.o
 ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
+obj-$(CONFIG_NET) += eth.o
 obj-y += cpld.o
 endif
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 5e570cd..5e5d1f6 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -250,16 +250,19 @@
 
 /* FMan */
 #ifndef SPL_NO_FMAN
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
+#define AQR105_IRQ_MASK			0x40000000
+
+#ifdef CONFIG_NET
 #define CONFIG_PHYLIB
-#define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
-
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_AQUANTIA
-#define AQR105_IRQ_MASK			0x40000000
 
 #define RGMII_PHY1_ADDR			0x1
 #define RGMII_PHY2_ADDR			0x2
-- 
cgit v0.10.2


From 42e8179007bbfc5f4c0c80cd2131db8138f8546f Mon Sep 17 00:00:00 2001
From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Date: Thu, 27 Apr 2017 10:14:16 +0530
Subject: driver: net: fsl-mc: Update fsl_mc_ldpaa_exit() path

Earlier when MC is loaded but DPL is not deployed results in FDT
fix-up code execution hangs. For this case now print message on
console and return success instead of return -ENODEV. This update
allows fdt fixup to continue execution.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Priyanka Jain <Priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 9f69d75..0a74e3e 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2017 NXP Semiconductors
  * Copyright (C) 2014 Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -1201,6 +1202,7 @@ err:
 int fsl_mc_ldpaa_exit(bd_t *bd)
 {
 	int err = 0;
+	bool is_dpl_apply_status = false;
 
 	if (bd && mc_lazy_dpl_addr && !fsl_mc_ldpaa_exit(NULL)) {
 		mc_apply_dpl(mc_lazy_dpl_addr);
@@ -1211,14 +1213,18 @@ int fsl_mc_ldpaa_exit(bd_t *bd)
 	if (bd && get_mc_boot_status() != 0)
 		return 0;
 
-	if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) {
-		printf("ERROR: fsl-mc: DPL is not applied\n");
-		err = -ENODEV;
-		return err;
-	}
+	/* If DPL is deployed, set is_dpl_apply_status as TRUE. */
+	if (!get_dpl_apply_status())
+		is_dpl_apply_status = true;
 
-	if (bd && !get_mc_boot_status() && !get_dpl_apply_status())
-		return err;
+	/*
+	 * For case MC is loaded but DPL is not deployed, return success and
+	 * print message on console. Else FDT fix-up code execution hanged.
+	 */
+	if (bd && !get_mc_boot_status() && !is_dpl_apply_status) {
+		printf("fsl-mc: DPL not deployed, DPAA2 ethernet not work\n");
+		return 0;
+	}
 
 	err = dpbp_exit();
 	if (err < 0) {
-- 
cgit v0.10.2


From d1418c15c81dfa798b38ee164d6fb6a4a6f3b6d9 Mon Sep 17 00:00:00 2001
From: Priyanka Jain <priyanka.jain@nxp.com>
Date: Fri, 28 Apr 2017 10:41:34 +0530
Subject: board: freescale: ls2080ardb: Update QIXIS code

Update QIXIS related code to be executed only if CONFIG_FSL_QIXIS
flag is enabled. In case QIXIS code is not enabled, use default
sysclk value as 100MHz per board documentation.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index c2aa101..10e8ea4 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -23,8 +23,10 @@
 #include <asm/arch/ppa.h>
 #include <fsl_sec.h>
 
+#ifdef CONFIG_FSL_QIXIS
 #include "../common/qixis.h"
 #include "ls2080ardb_qixis.h"
+#endif
 #include "../common/vid.h"
 
 #define PIN_MUX_SEL_SDHC	0x00
@@ -58,12 +60,15 @@ unsigned long long get_qixis_addr(void)
 
 int checkboard(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 sw;
+#endif
 	char buf[15];
 
 	cpu_name(buf);
 	printf("Board: %s-RDB, ", buf);
 
+#ifdef CONFIG_FSL_QIXIS
 	sw = QIXIS_READ(arch);
 	printf("Board Arch: V%d, ", sw >> 4);
 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
@@ -79,7 +84,7 @@ int checkboard(void)
 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 
 	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
-
+#endif
 	puts("SERDES1 Reference : ");
 	printf("Clock1 = 156.25MHz ");
 	printf("Clock2 = 156.25MHz");
@@ -93,6 +98,7 @@ int checkboard(void)
 
 unsigned long get_board_sys_clk(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 
 	switch (sysclk_conf & 0x0F) {
@@ -111,7 +117,8 @@ unsigned long get_board_sys_clk(void)
 	case QIXIS_SYSCLK_166:
 		return 166666666;
 	}
-	return 66666666;
+#endif
+	return 100000000;
 }
 
 int select_i2c_ch_pca9547(u8 ch)
@@ -134,6 +141,7 @@ int i2c_multiplexer_select_vid_channel(u8 channel)
 
 int config_board_mux(int ctrl_type)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 reg5;
 
 	reg5 = QIXIS_READ(brdcfg[5]);
@@ -151,7 +159,7 @@ int config_board_mux(int ctrl_type)
 	}
 
 	QIXIS_WRITE(brdcfg[5], reg5);
-
+#endif
 	return 0;
 }
 
@@ -181,8 +189,9 @@ int board_init(void)
 #endif
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
+#ifdef CONFIG_FSL_QIXIS
 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
-
+#endif
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
@@ -319,6 +328,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 void qixis_dump_switch(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	int i, nr_of_cfgsw;
 
 	QIXIS_WRITE(cms[0], 0x00);
@@ -329,6 +339,7 @@ void qixis_dump_switch(void)
 		QIXIS_WRITE(cms[0], i);
 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 	}
+#endif
 }
 
 /*
@@ -339,6 +350,7 @@ void update_spd_address(unsigned int ctrl_num,
 			unsigned int slot,
 			unsigned int *addr)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 sw;
 
 	sw = QIXIS_READ(arch);
@@ -348,4 +360,5 @@ void update_spd_address(unsigned int ctrl_num,
 		else if (ctrl_num == 1 && slot == 1)
 			*addr = SPD_EEPROM_ADDRESS3;
 	}
+#endif
 }
-- 
cgit v0.10.2


From 89a168f776cbc15a2ff1f25a0f4e54f9bbaffdec Mon Sep 17 00:00:00 2001
From: Priyanka Jain <priyanka.jain@nxp.com>
Date: Fri, 28 Apr 2017 10:41:35 +0530
Subject: armv8: ls2080ardb: Add QSPI-boot support

QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC.
LS2088ARDB RevF Board has limitation that QIXIS can not be accessed.
CONFIG_FSL_QIXIS is not enabled.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 4c16c4c..998944a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -163,6 +163,7 @@ endchoice
 config SYS_LS_PPA_FW_ADDR
 	hex "Address of PPA firmware loading from"
 	depends on FSL_LS_PPA
+	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
 	default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
 	default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
 	default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a985c5d..a44f158 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -174,7 +174,8 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
 	ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
 	ls1021a-iot-duart.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
-	fsl-ls2080a-rdb.dtb
+	fsl-ls2080a-rdb.dtb \
+	fsl-ls2088a-rdb-qspi.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
 	fsl-ls1043a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
new file mode 100644
index 0000000..3230e7e
--- /dev/null
+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
@@ -0,0 +1,59 @@
+/*
+ * NXP ls2080a RDB board device tree source for QSPI-boot
+ *
+ * Author: Priyanka Jain <priyanka.jain@nxp.com>
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "fsl-ls2080a.dtsi"
+
+/ {
+	model = "Freescale Layerscape 2080a RDB Board";
+	compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
+
+	aliases {
+		spi0 = &qspi;
+		spi1 = &dspi;
+	};
+};
+
+&dspi {
+	bus-num = <0>;
+	status = "okay";
+
+	dflash0: n25q512a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <3000000>;
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fs512s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		reg = <0>;
+	};
+
+	qflash1: s25fs512s@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		reg = <1>;
+	};
+};
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index 759a146..3175ba3 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -7,6 +7,11 @@ F:	include/configs/ls2080ardb.h
 F:	configs/ls2080ardb_defconfig
 F:	configs/ls2080ardb_nand_defconfig
 
+LS2088A_QSPI-boot BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	configs/ls2088ardb_qspi_defconfig
+
 LS2080A_SECURE_BOOT BOARD
 M:	Saksham Jain <saksham.jain@nxp.freescale.com>
 S:	Maintained
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index 0c9c574..873aadf 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -43,6 +43,7 @@ Memory map from core's view
 0x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
 0x00_0100_0000 .. 0x00_0FFF_FFFF	CCSR
 0x00_1800_0000 .. 0x00_181F_FFFF	OCRAM
+0x00_2000_0000 .. 0x00_2FFF_FFFF	QSPI region #1
 0x00_3000_0000 .. 0x00_3FFF_FFFF	IFC region #1
 0x00_8000_0000 .. 0x00_FFFF_FFFF	DDR region #1
 0x05_1000_0000 .. 0x05_FFFF_FFFF	IFC region #2
@@ -68,6 +69,31 @@ Booting Options
 ---------------
 a) NOR boot
 b) NAND boot
+c) QSPI boot
+
+cfg_rcw_src switches needs to be changed for booting from different option.
+Refer to board documentation for correct switch setting.
+
+QSPI boot details
+===================
+Supported only for
+ LS2088ARDB RevF board with LS2088A SoC.
+
+Images needs to be copied to QSPI flash
+as per memory map given below.
+
+Memory map for QSPI flash
+-------------------------
+Image				Flash Offset
+RCW+PBI				0x00000000
+Boot firmware (U-Boot)		0x00100000
+Boot firmware Environment	0x00300000
+PPA firmware			0x00400000
+Cortina PHY firmware		0x00980000
+DPAA2 MC			0x00A00000
+DPAA2 DPL			0x00D00000
+DPAA2 DPC			0x00E00000
+Kernel.itb			0x01000000
 
 Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
 -------------------------------------------------------------------
diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
new file mode 100644
index 0000000..139ff08
--- /dev/null
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -0,0 +1,46 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080ARDB=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_CMD_GREPENV=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 427f623..363bfd4 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright (C) 2014 Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -28,6 +29,12 @@
 #else
 #define CONFIG_SYS_TEXT_BASE		0x30100000
 #endif
+#else
+#define CONFIG_SYS_TEXT_BASE		0x20100000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
+#define CONFIG_ENV_SECT_SIZE		0x10000
 #endif
 
 #define CONFIG_SUPPORT_RAW_INITRD
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index f50ad42..469ef9e 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -262,13 +263,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 
-#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_TEXT_BASE		0x20010000
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
-#define CONFIG_ENV_OFFSET		0x100000        /* 1MB */
-#define CONFIG_ENV_SECT_SIZE		0x10000
-#else
+#ifndef CONFIG_QSPI_BOOT
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index ec83eb5..ef95358 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -12,6 +13,11 @@
 #undef CONFIG_CONS_INDEX
 #define CONFIG_CONS_INDEX       2
 
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#endif
+
 #define I2C_MUX_CH_VOL_MONITOR		0xa
 #define I2C_VOL_MONITOR_ADDR		0x38
 #define CONFIG_VOL_MONITOR_IR36021_READ
@@ -69,6 +75,7 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 						CONFIG_SYS_SCSI_MAX_LUN)
 
+#ifndef CONFIG_FSL_QSPI
 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
 
 #define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
@@ -157,7 +164,6 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_CMD_NAND
 
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
-
 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
 #define QIXIS_LBMAP_SWITCH		0x06
 #define QIXIS_LBMAP_MASK		0x0f
@@ -250,7 +256,7 @@ unsigned long get_board_sys_clk(void);
 /* Debug Server firmware */
 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL
-
+#endif
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
 /*
@@ -263,10 +269,17 @@ unsigned long get_board_sys_clk(void);
 #define I2C_MUX_CH_DEFAULT      0x8
 
 /* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_SPI_FLASH
+#ifdef CONFIG_FSL_QSPI
 #define CONFIG_SPI_FLASH_STMICRO
 #endif
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE		SZ_64M	/* 64MB */
+#define FSL_QSPI_FLASH_NUM		2
+#endif
+#endif
 
 /*
  * RTC configuration
@@ -345,6 +358,25 @@ unsigned long get_board_sys_clk(void);
 	" 0x580800000 \0"                       \
 	BOOTENV
 #else
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"scriptaddr=0x80800000\0"		\
+	"kernel_addr_r=0x81000000\0"		\
+	"pxefile_addr_r=0x81000000\0"		\
+	"fdt_addr_r=0x88000000\0"		\
+	"ramdisk_addr_r=0x89000000\0"		\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x21000000\0"		\
+	"mcmemsize=0x40000000\0"		\
+	"mcinitcmd=fsl_mc start mc 0x20a00000" \
+	" 0x20e00000 \0"                       \
+	BOOTENV
+#else
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
 	"scriptaddr=0x80800000\0"		\
@@ -367,6 +399,7 @@ unsigned long get_board_sys_clk(void);
 	" 0x580800000 \0"                       \
 	BOOTENV
 #endif
+#endif
 
 
 #undef CONFIG_BOOTARGS
@@ -376,11 +409,18 @@ unsigned long get_board_sys_clk(void);
 				" hugepagesz=2m hugepages=256"
 
 #undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_QSPI_BOOT
+/* Try to boot an on-QSPI kernel first, then do normal distro boot */
+#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x20d00000" \
+			   " && bootm $kernel_start" \
+			   " || run distro_bootcmd"
+#else
 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \
 			   " && cp.b $kernel_start $kernel_load $kernel_size" \
 			   " && bootm $kernel_load" \
 			   " || run distro_bootcmd"
+#endif
 
 /* MAC/PHY configuration */
 #ifdef CONFIG_FSL_MC_ENET
@@ -389,7 +429,11 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_PHY_CORTINA
 #define CONFIG_PHYLIB
 #define	CONFIG_SYS_CORTINA_FW_IN_NOR
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_CORTINA_FW_ADDR		0x20980000
+#else
 #define CONFIG_CORTINA_FW_ADDR		0x581000000
+#endif
 #define CONFIG_CORTINA_FW_LENGTH	0x40000
 
 #define CORTINA_PHY_ADDR1	0x10
-- 
cgit v0.10.2


From e809e747996b00acd0ffc833999e97a3a21ddfac Mon Sep 17 00:00:00 2001
From: Priyanka Jain <priyanka.jain@nxp.com>
Date: Thu, 27 Apr 2017 15:08:06 +0530
Subject: armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support

The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index bb02960..cba0095 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -98,7 +99,8 @@ static void fix_pcie_mmu_map(void)
 
 	/* Fix PCIE base and size for LS2088A */
 	if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
-	    (ver == SVR_LS2048A) || (ver == SVR_LS2044A)) {
+	    (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
+	    (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 		for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 			switch (final_map[i].phys) {
 			case CONFIG_SYS_PCIE1_PHYS_ADDR:
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index c7496c0..3ae16ae 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -5,6 +5,7 @@ SoC overview
 	3. LS1012A
 	4. LS1046A
 	5. LS2088A
+	6. LS2081A
 
 LS1043A
 ---------
@@ -227,3 +228,13 @@ LS2088A SoC has 3 more similar SoC personalities
 
 3)LS2044A, few difference w.r.t. LS2084A:
        a) Four 64-bit ARM v8 Cortex-A72 CPUs
+
+LS2081A
+--------
+LS2081A is 40-pin derivative of LS2084A.
+So feature-wise it is same as LS2084A.
+Refer to LS2084A(LS2088A) section above for details.
+
+It has one more similar SoC personality
+1)LS2041A, few difference w.r.t. LS2081A:
+       a) Four 64-bit ARM v8 Cortex-A72 CPUs
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 95c3e2f..d6a273a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015, Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -15,6 +16,8 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
 	CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
 	CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
+	CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
+	CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
 	CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
 	CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
 	CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 426fe8e..cc3b079 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -54,6 +55,8 @@ struct cpu_type {
 #define SVR_LS2084A		0x870910
 #define SVR_LS2048A		0x870920
 #define SVR_LS2044A		0x870930
+#define SVR_LS2081A		0x870919
+#define SVR_LS2041A		0x870915
 
 #define SVR_DEV_LS2080A		0x8701
 
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 1c5a33a..7565e2f 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  *
@@ -170,7 +171,8 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie)
 	/* Fix the pcie memory map for LS2088A series SoCs */
 	svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-	    svr == SVR_LS2048A || svr == SVR_LS2044A) {
+	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
 		if (io)
 			io->phys_start = (io->phys_start &
 					 (PCIE_PHYS_SIZE - 1)) +
@@ -531,7 +533,8 @@ static int ls_pcie_probe(struct udevice *dev)
 	svr = get_svr();
 	svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-	    svr == SVR_LS2048A || svr == SVR_LS2044A) {
+	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
 		pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
 					LS2088A_PCIE_PHYS_SIZE * pcie->idx;
 		pcie->ctrl = pcie->lut + 0x40000;
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index e3324a5..308b073 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  *
@@ -117,6 +118,8 @@
 #define SVR_LS2084A		0x870910
 #define SVR_LS2048A		0x870920
 #define SVR_LS2044A		0x870930
+#define SVR_LS2081A		0x870919
+#define SVR_LS2041A		0x870915
 
 /* LS1021a PCIE space */
 #define LS1021_PCIE_SPACE_OFFSET	0x4000000000ULL
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index d504bbd..ce709bf 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  *
@@ -82,7 +83,8 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-		    svr == SVR_LS2048A || svr == SVR_LS2044A)
+		    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+		    svr == SVR_LS2081A || svr == SVR_LS2041A)
 			compat = "fsl,ls2088a-pcie";
 		else
 			compat = CONFIG_FSL_PCIE_COMPAT;
@@ -217,7 +219,8 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-		    svr == SVR_LS2048A || svr == SVR_LS2044A)
+		    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+		    svr == SVR_LS2081A || svr == SVR_LS2041A)
 			compat = "fsl,ls2088a-pcie";
 		else
 			compat = CONFIG_FSL_PCIE_COMPAT;
-- 
cgit v0.10.2


From 3049a583f343a71ead9d7cb33f0ab6cecfbbaa12 Mon Sep 17 00:00:00 2001
From: Priyanka Jain <priyanka.jain@nxp.com>
Date: Thu, 27 Apr 2017 15:08:07 +0530
Subject: armv8: ls2080ardb: Add LS2081ARDB board support

LS2081ARDB board is similar to LS2080ARDB board with few differences
 It hosts LS2081A SoC
 Default boot source is QSPI-boot
 It does not have IFC interface
 RTC and QSPI flash device are different
 It provides QIXIS access via I2C

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b2d6e80..2db7e3c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -781,6 +781,20 @@ config TARGET_LS2080ARDB
 	  development platform that supports the QorIQ LS2080A
 	  Layerscape Architecture processor.
 
+config TARGET_LS2081ARDB
+	bool "Support ls2081ardb"
+	select ARCH_LS2080A
+	select ARM64
+	select ARMV8_MULTIENTRY
+	select BOARD_LATE_INIT
+	select SUPPORT_SPL
+	select ARCH_MISC_INIT
+	help
+	  Support for Freescale LS2081ARDB platform.
+	  The LS2081A Reference design board (RDB) is a high-performance
+	  development platform that supports the QorIQ LS2081A/LS2041A
+	  Layerscape Architecture processor.
+
 config TARGET_HIKEY
 	bool "Support HiKey 96boards Consumer Edition Platform"
 	select ARM64
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 0188b95..d5b692e 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -91,6 +91,7 @@ config PSCI_RESET
 		   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
 		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
 		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
+		   !TARGET_LS2081ARDB && \
 		   !ARCH_UNIPHIER && !ARCH_SNAPDRAGON && !TARGET_S32V234EVB
 	help
 	  Most armv8 systems have PSCI support enabled in EL3, either through
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a44f158..55f4ae9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -175,6 +175,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
 	ls1021a-iot-duart.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-ls2080a-rdb.dtb \
+	fsl-ls2081a-rdb.dtb \
 	fsl-ls2088a-rdb-qspi.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
diff --git a/arch/arm/dts/fsl-ls2081a-rdb.dts b/arch/arm/dts/fsl-ls2081a-rdb.dts
new file mode 100644
index 0000000..6489362
--- /dev/null
+++ b/arch/arm/dts/fsl-ls2081a-rdb.dts
@@ -0,0 +1,59 @@
+/*
+ * NXP LS2081A RDB board device tree source for QSPI-boot
+ *
+ * Author: Priyanka Jain <priyanka.jain@nxp.com>
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "fsl-ls2080a.dtsi"
+
+/ {
+	model = "Freescale Layerscape 2081a RDB Board";
+	compatible = "fsl,ls2081a-rdb", "fsl,ls2080a";
+
+	aliases {
+		spi0 = &qspi;
+		spi1 = &dspi;
+	};
+};
+
+&dspi {
+	bus-num = <0>;
+	status = "okay";
+
+	dflash0: n25q512a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <3000000>;
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: n25q512a@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		reg = <0>;
+	};
+
+	qflash1: n25q512a@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		reg = <1>;
+	};
+};
diff --git a/board/freescale/ls2080ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig
index 2f0465f..8f64642 100644
--- a/board/freescale/ls2080ardb/Kconfig
+++ b/board/freescale/ls2080ardb/Kconfig
@@ -16,3 +16,21 @@ config SYS_CONFIG_NAME
 source "board/freescale/common/Kconfig"
 
 endif
+
+if TARGET_LS2081ARDB
+
+config SYS_BOARD
+	default "ls2080ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls2080ardb"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index 3175ba3..91f13ea 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -12,6 +12,11 @@ M:	Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	configs/ls2088ardb_qspi_defconfig
 
+LS2081ARDB BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	configs/ls2081ardb_defconfig
+
 LS2080A_SECURE_BOOT BOARD
 M:	Saksham Jain <saksham.jain@nxp.freescale.com>
 S:	Maintained
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index 873aadf..fde143d 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -4,10 +4,14 @@ The LS2080A Reference Design (RDB) is a high-performance computing,
 evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
 Layerscape Architecture processor.
 
-LS2080A, LS2088A SoC Overview
---------------------
+The LS2081A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2081A
+Layerscape Architecture processor.More details in below sections
+
+LS2080A, LS2088A, LS2081A SoC Overview
+--------------------------------------
 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
-LS2088A SoC overview.
+LS2081A, LS2088A SoC overview.
 
  LS2080ARDB board Overview
  -----------------------
@@ -38,6 +42,16 @@ LS2088A SoC overview.
  - UART
  - ARM JTAG support
 
+ LS2081ARDB board Overview
+ -------------------------
+ LS2081ARDB board is similar to LS2080ARDB board
+ with few differences like
+  - Hosts LS2081A SoC
+  - Default boot source is QSPI-boot
+  - Does not have IFC interface
+  - RTC and QSPI flash devices are different
+  - Provides QIXIS access via I2C
+
 Memory map from core's view
 ----------------------------
 0x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 10e8ea4..df2d768 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -68,6 +68,44 @@ int checkboard(void)
 	cpu_name(buf);
 	printf("Board: %s-RDB, ", buf);
 
+#ifdef CONFIG_TARGET_LS2081ARDB
+#ifdef CONFIG_FSL_QIXIS
+	sw = QIXIS_READ(arch);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, ", (sw & 0xf) + 'A');
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
+	switch (sw) {
+	case 0:
+		puts("boot from QSPI DEV#0\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
+		break;
+	case 1:
+		puts("boot from QSPI DEV#1\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
+		break;
+	case 2:
+		puts("boot from QSPI EMU\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
+		break;
+	case 3:
+		puts("boot from QSPI EMU\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
+		break;
+	case 4:
+		puts("boot from QSPI DEV#0\n");
+		puts("QSPI_CSA_1 mapped to QSPI EMU\n");
+		break;
+	default:
+		printf("invalid setting of SW%u\n", sw);
+		break;
+	}
+#endif
+	puts("SERDES1 Reference : ");
+	printf("Clock1 = 100MHz ");
+	printf("Clock2 = 161.13MHz");
+#else
 #ifdef CONFIG_FSL_QIXIS
 	sw = QIXIS_READ(arch);
 	printf("Board Arch: V%d, ", sw >> 4);
@@ -88,6 +126,7 @@ int checkboard(void)
 	puts("SERDES1 Reference : ");
 	printf("Clock1 = 156.25MHz ");
 	printf("Clock2 = 156.25MHz");
+#endif
 
 	puts("\nSERDES2 Reference : ");
 	printf("Clock1 = 100MHz ");
@@ -209,6 +248,9 @@ int board_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+	i2c_early_init_f();
+#endif
 	fsl_lsch3_early_init_f();
 	return 0;
 }
@@ -216,6 +258,11 @@ int board_early_init_f(void)
 int misc_init_r(void)
 {
 #ifdef CONFIG_FSL_QIXIS
+	/*
+	 * LS2081ARDB has smart voltage translator which needs
+	 * to be programmed as below
+	 */
+#ifndef CONFIG_TARGET_LS2081ARDB
 	u8 sw;
 
 	sw = QIXIS_READ(arch);
@@ -225,12 +272,15 @@ int misc_init_r(void)
 	 * by setting GPIO4_10 output to zero
 	 */
 	if ((sw & 0xf) == 0x5) {
+#endif
 		out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
 					    in_le32(GPIO4_GPDIR_ADDR)));
 		out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
 					    in_le32(GPIO4_GPDAT_ADDR)));
+#ifndef CONFIG_TARGET_LS2081ARDB
 	}
 #endif
+#endif
 
 	if (hwconfig("sdhc"))
 		config_board_mux(MUX_TYPE_SDHC);
@@ -350,6 +400,7 @@ void update_spd_address(unsigned int ctrl_num,
 			unsigned int slot,
 			unsigned int *addr)
 {
+#ifndef CONFIG_TARGET_LS2081ARDB
 #ifdef CONFIG_FSL_QIXIS
 	u8 sw;
 
@@ -361,4 +412,5 @@ void update_spd_address(unsigned int ctrl_num,
 			*addr = SPD_EEPROM_ADDRESS3;
 	}
 #endif
+#endif
 }
diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
new file mode 100644
index 0000000..0d1730f
--- /dev/null
+++ b/configs/ls2081ardb_defconfig
@@ -0,0 +1,46 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2081ARDB=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2081a-rdb"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_CMD_GREPENV=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index 798c358..3a16624 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -40,7 +40,8 @@ __weak int __board_usb_init(int index, enum usb_init_type init)
 
 static int erratum_a008751(void)
 {
-#if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB)
+#if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB) ||\
+					defined(CONFIG_TARGET_LS2080AQDS)
 	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
 	writel(SCFG_USB3PRM1CR_INIT, scfg + SCFG_USB3PRM1CR / 4);
 	return 0;
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index ef95358..3774b17 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -14,6 +14,9 @@
 #define CONFIG_CONS_INDEX       2
 
 #ifdef CONFIG_FSL_QSPI
+#ifdef CONFIG_TARGET_LS2081ARDB
+#define CONFIG_QIXIS_I2C_ACCESS
+#endif
 #define CONFIG_SYS_I2C_EARLY_INIT
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 #endif
@@ -259,9 +262,28 @@ unsigned long get_board_sys_clk(void);
 #endif
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
+#ifdef CONFIG_TARGET_LS2081ARDB
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_QMAP_MASK			0x07
+#define QIXIS_QMAP_SHIFT		5
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_QSPI		0x62
+#define QIXIS_LBMAP_ALTBANK		0x20
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_RST_CTL_RESET_EN		0x30
+#endif
+
 /*
  * I2C
  */
+#ifdef CONFIG_TARGET_LS2081ARDB
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#endif
 #define I2C_MUX_PCA_ADDR		0x75
 #define I2C_MUX_PCA_ADDR_PRI		0x75 /* Primary Mux*/
 
@@ -275,7 +297,11 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SPI_FLASH_STMICRO
 #endif
 #ifdef CONFIG_FSL_QSPI
+#ifdef CONFIG_TARGET_LS2081ARDB
+#define CONFIG_SPI_FLASH_STMICRO
+#else
 #define CONFIG_SPI_FLASH_SPANSION
+#endif
 #define FSL_QSPI_FLASH_SIZE		SZ_64M	/* 64MB */
 #define FSL_QSPI_FLASH_NUM		2
 #endif
@@ -285,8 +311,13 @@ unsigned long get_board_sys_clk(void);
  * RTC configuration
  */
 #define RTC
+#ifdef CONFIG_TARGET_LS2081ARDB
+#define CONFIG_RTC_PCF8563		1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x51
+#else
 #define CONFIG_RTC_DS3231               1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#endif
 
 /* EEPROM */
 #define CONFIG_ID_EEPROM
-- 
cgit v0.10.2


From 615bfce5640c1b577f14d95d77f1b46dfd2b500e Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Tue, 16 May 2017 10:45:57 +0800
Subject: arm: ls1021a: Adjust memory mapping for Flash/SD card on
 LS1021AQDS/TWR

This patch is to adjust the memory mapping for FLash/SD card on
LS1021AQDS and LS1021ATWR, such as U-Boot start address on serial
Flash, QE firmware load address and environment address.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 373de40..5fcaf85 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -69,7 +69,7 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #ifdef CONFIG_QSPI_BOOT
-#define CONFIG_SYS_TEXT_BASE		0x40010000
+#define CONFIG_SYS_TEXT_BASE		0x40100000
 #endif
 
 #ifdef CONFIG_NAND_BOOT
@@ -498,7 +498,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_FSL_DEVICE_DISABLE
 
 
-#define CONFIG_SYS_QE_FW_ADDR     0x600c0000
+#define CONFIG_SYS_QE_FW_ADDR     0x60940000
 
 #ifdef CONFIG_LPUART
 #define CONFIG_EXTRA_ENV_SETTINGS       \
@@ -549,14 +549,14 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_OVERWRITE
 
 #if defined(CONFIG_SD_BOOT)
-#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET		0x300000
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SIZE			0x2000
 #elif defined(CONFIG_QSPI_BOOT)
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SIZE			0x2000          /* 8KB */
-#define CONFIG_ENV_OFFSET		0x100000        /* 1MB */
+#define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
 #define CONFIG_ENV_SECT_SIZE		0x10000
 #elif defined(CONFIG_NAND_BOOT)
 #define CONFIG_ENV_IS_IN_NAND
@@ -564,7 +564,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
 #endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 1ff3d9e..2a20dec 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -133,7 +133,7 @@
 #endif
 
 #ifdef CONFIG_QSPI_BOOT
-#define CONFIG_SYS_TEXT_BASE		0x40010000
+#define CONFIG_SYS_TEXT_BASE		0x40100000
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
@@ -409,7 +409,7 @@
 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 #endif
 
-#define CONFIG_SYS_QE_FW_ADDR     0x600c0000
+#define CONFIG_SYS_QE_FW_ADDR     0x60940000
 
 /*
  * Environment
@@ -417,18 +417,18 @@
 #define CONFIG_ENV_OVERWRITE
 
 #if defined(CONFIG_SD_BOOT)
-#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET		0x300000
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SIZE			0x20000
 #elif defined(CONFIG_QSPI_BOOT)
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET		0x300000
 #define CONFIG_ENV_SECT_SIZE		0x10000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
 #define CONFIG_ENV_SIZE			0x20000
 #define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
 #endif
-- 
cgit v0.10.2


From a9a5cef391ed5b2e47ed02a8cecf0ab1a19fc76a Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Tue, 16 May 2017 10:45:58 +0800
Subject: armv8: layerscape: Adjust memory mapping for Flash/SD card on LS1043A

This patch is to adjust the memory mapping for FLash/SD card on
LS1043AQDS and LS1043ARDB, such as PPA firmware load address, FMAN
firmware load address, QE firmware load address, U-Boot start address
on serial flash and environment address.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 998944a..c8ba2d6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -164,11 +164,11 @@ config SYS_LS_PPA_FW_ADDR
 	hex "Address of PPA firmware loading from"
 	depends on FSL_LS_PPA
 	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
-	default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+	default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
 	default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
-	default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
-	default 0x500000 if SYS_LS_PPA_FW_IN_MMC
-	default 0x500000 if SYS_LS_PPA_FW_IN_NAND
+	default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x400000 if SYS_LS_PPA_FW_IN_MMC
+	default 0x400000 if SYS_LS_PPA_FW_IN_NAND
 
 	help
 	  If the PPA firmware locate at XIP flash, such as NOR or
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index e269248..05419fe 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -208,20 +208,20 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
 
 #ifdef CONFIG_NAND_BOOT
-/* Store Fman ucode at offeset 0x160000(11 blocks). */
+/* Store Fman ucode at offeset 0x900000(72 blocks). */
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_FMAN_FW_ADDR		(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR		(72 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SD_BOOT)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 1MB (2040 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
+ * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
+#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x4800)
 #elif defined(CONFIG_QSPI_BOOT)
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_FMAN_FW_ADDR		0x400d0000
+#define CONFIG_SYS_FMAN_FW_ADDR		0x40900000
 #define CONFIG_ENV_SPI_BUS		0
 #define CONFIG_ENV_SPI_CS		0
 #define CONFIG_ENV_SPI_MAX_HZ		1000000
@@ -229,7 +229,7 @@
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 /* FMan fireware Pre-load address */
-#define CONFIG_SYS_FMAN_FW_ADDR		0x60300000
+#define CONFIG_SYS_FMAN_FW_ADDR		0x60900000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index b14e944..04d74ac 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -12,7 +12,7 @@
 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
 #define CONFIG_SYS_TEXT_BASE		0x82000000
 #elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_TEXT_BASE		0x40010000
+#define CONFIG_SYS_TEXT_BASE		0x40100000
 #else
 #define CONFIG_SYS_TEXT_BASE		0x60100000
 #endif
@@ -413,20 +413,20 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET		(24 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SD_BOOT)
-#define CONFIG_ENV_OFFSET		(1024 * 1024)
+#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SIZE			0x2000
 #elif defined(CONFIG_QSPI_BOOT)
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SIZE			0x2000          /* 8KB */
-#define CONFIG_ENV_OFFSET		0x100000        /* 1MB */
+#define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
 #define CONFIG_ENV_SECT_SIZE		0x10000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x20000
 #endif
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 5e5d1f6..2647b15 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -235,15 +235,15 @@
 #if defined(CONFIG_NAND_BOOT)
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET		(24 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SD_BOOT)
-#define CONFIG_ENV_OFFSET		(1024 * 1024)
+#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SIZE			0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x20000
 #endif
@@ -284,7 +284,7 @@
 	!defined(CONFIG_QSPI_BOOT)
 #define CONFIG_U_QE
 #endif
-#define CONFIG_SYS_QE_FW_ADDR     0x60600000
+#define CONFIG_SYS_QE_FW_ADDR     0x60940000
 #endif
 
 /* USB */
-- 
cgit v0.10.2


From 8104deb2d6b77d3793a66016bf993bccd8f6afe2 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Tue, 16 May 2017 10:45:59 +0800
Subject: armv8: layerscape: Adjust memory mapping for Flash/SD card on LS1046A

This patch is to adjust the memory mapping for FLash/SD card on
LS1046AQDS and LS1046ARDB, such as FMAN firmware load address, U-Boot
start address on serial flash and environment address.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README
index 1ef7d47..a38c9d4 100644
--- a/board/freescale/ls1046ardb/README
+++ b/board/freescale/ls1046ardb/README
@@ -59,14 +59,14 @@ Start Address	 End Address	 Description		Size
 QSPI flash map:
 Start Address    End Address     Description		Size
 0x00_4000_0000 - 0x00_400F_FFFF  RCW + PBI		1MB
-0x00_4010_0000 - 0x00_401F_FFFF  U-Boot 		1MB
-0x00_4020_0000 - 0x00_402F_FFFF  U-Boot Env		1MB
-0x00_4030_0000 - 0x00_403F_FFFF  FMan ucode		1MB
-0x00_4040_0000 - 0x00_404F_FFFF  UEFI			1MB
-0x00_4050_0000 - 0x00_406F_FFFF  PPA			2MB
-0x00_4070_0000 - 0x00_408F_FFFF  Secure boot header
-			         + bootscript		2MB
-0x00_4090_0000 - 0x00_40FF_FFFF  Reserved		7MB
+0x00_4010_0000 - 0x00_402F_FFFF  U-Boot 		2MB
+0x00_4030_0000 - 0x00_403F_FFFF  U-Boot Env		1MB
+0x00_4040_0000 - 0x00_405F_FFFF  PPA			2MB
+0x00_4060_0000 - 0x00_408F_FFFF  Secure boot header
+				 + bootscript		3MB
+0x00_4090_0000 - 0x00_4093_FFFF  FMan ucode		256KB
+0x00_4094_0000 - 0x00_4097_FFFF  QE/uQE firmware	256KB
+0x00_4098_0000 - 0x00_40FF_FFFF  Reserved		6MB
 0x00_4100_0000 - 0x00_43FF_FFFF  FIT Image		48MB
 
 Booting Options
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 80f8dc2..47a544c 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -176,23 +176,23 @@
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
+#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x4800)
 #elif defined(CONFIG_QSPI_BOOT)
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_FMAN_FW_ADDR		0x40300000
+#define CONFIG_SYS_FMAN_FW_ADDR		0x40900000
 #define CONFIG_ENV_SPI_BUS		0
 #define CONFIG_ENV_SPI_CS		0
 #define CONFIG_ENV_SPI_MAX_HZ		1000000
 #define CONFIG_ENV_SPI_MODE		0x03
 #elif defined(CONFIG_NAND_BOOT)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_FMAN_FW_ADDR		(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR		(72 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_FMAN_FW_ADDR		0x60300000
+#define CONFIG_SYS_FMAN_FW_ADDR		0x60900000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 0cf6010..5d2e819 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -12,7 +12,7 @@
 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
 #define CONFIG_SYS_TEXT_BASE		0x82000000
 #elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_TEXT_BASE		0x40010000
+#define CONFIG_SYS_TEXT_BASE		0x40100000
 #else
 #define CONFIG_SYS_TEXT_BASE		0x60100000
 #endif
@@ -447,20 +447,20 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET		(24 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SD_BOOT)
-#define CONFIG_ENV_OFFSET		(1024 * 1024)
+#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SIZE			0x2000
 #elif defined(CONFIG_QSPI_BOOT)
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SIZE			0x2000          /* 8KB */
-#define CONFIG_ENV_OFFSET		0x100000        /* 1MB */
+#define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
 #define CONFIG_ENV_SECT_SIZE		0x10000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x20000
 #endif
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 7161ee8..6f649a6 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -169,12 +169,12 @@
 #if defined(CONFIG_SD_BOOT)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0
-#define CONFIG_ENV_OFFSET		(1024 * 1024)
+#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
 #define CONFIG_ENV_SIZE			0x2000
 #else
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SIZE			0x2000		/* 8KB */
-#define CONFIG_ENV_OFFSET		0x200000	/* 2MB */
+#define CONFIG_ENV_OFFSET		0x300000	/* 3MB */
 #define CONFIG_ENV_SECT_SIZE		0x40000		/* 256KB */
 #endif
 
-- 
cgit v0.10.2


From f5bf23d8278b2fdfb9ce41fa36369cebc882ab02 Mon Sep 17 00:00:00 2001
From: Santan Kumar <santan.kumar@nxp.com>
Date: Fri, 28 Apr 2017 12:47:24 +0530
Subject: armv8: ls2080ardb, ls2080aqds: Adjust memory map for NOR-boot

This patch adjusts memory map for images on LS2080ARDB and
LS2080AQDS NOR flash as below

Image				Flash Offset
RCW+PBI				0x00000000
Boot firmware (U-Boot)		0x00100000
Boot firmware Environment	0x00300000
PPA firmware			0x00400000
PHY firmware			0x00980000
DPAA2 MC			0x00A00000
DPAA2 DPL			0x00D00000
DPAA2 DPC			0x00E00000
Kernel.itb			0x01000000

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index c8ba2d6..fa386c6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -165,7 +165,7 @@ config SYS_LS_PPA_FW_ADDR
 	depends on FSL_LS_PPA
 	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
 	default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
-	default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+	default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
 	default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
 	default 0x400000 if SYS_LS_PPA_FW_IN_MMC
 	default 0x400000 if SYS_LS_PPA_FW_IN_NAND
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index 2808bd5..fd0e25a 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -89,6 +89,18 @@ c) NAND boot
 d) SD boot
 e) QSPI boot
 
+Memory map for NOR boot
+-------------------------
+Image				Flash Offset
+RCW+PBI				0x00000000
+Boot firmware (U-Boot)		0x00100000
+Boot firmware Environment	0x00300000
+PPA firmware			0x00400000
+DPAA2 MC			0x00A00000
+DPAA2 DPL			0x00D00000
+DPAA2 DPC			0x00E00000
+Kernel.itb			0x01000000
+
 Environment Variables
 ---------------------
 - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index fde143d..f228d80 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -85,6 +85,19 @@ a) NOR boot
 b) NAND boot
 c) QSPI boot
 
+Memory map for NOR boot
+-------------------------
+Image				Flash Offset
+RCW+PBI				0x00000000
+Boot firmware (U-Boot)		0x00100000
+Boot firmware Environment	0x00300000
+PPA firmware			0x00400000
+Cortina PHY firmware		0x00980000
+DPAA2 MC			0x00A00000
+DPAA2 DPL			0x00D00000
+DPAA2 DPC			0x00E00000
+Kernel.itb			0x01000000
+
 cfg_rcw_src switches needs to be changed for booting from different option.
 Refer to board documentation for correct switch setting.
 
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 363bfd4..7b73139 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -193,18 +193,18 @@ unsigned long long get_qixis_addr(void);
 	"ramdisk_size=0x2000000\0"		\
 	"fdt_high=0xa0000000\0"			\
 	"initrd_high=0xffffffffffffffff\0"	\
-	"kernel_start=0x581200000\0"		\
+	"kernel_start=0x581000000\0"		\
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x2800000\0"		\
 	"console=ttyAMA0,38400n8\0"		\
-	"mcinitcmd=fsl_mc start mc 0x580300000"	\
-	" 0x580800000 \0"
+	"mcinitcmd=fsl_mc start mc 0x580a00000"	\
+	" 0x580e00000 \0"
 
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/ram0 " \
 				"earlycon=uart8250,mmio,0x21c0500 " \
 				"ramdisk_size=0x2000000 default_hugepagesz=2m" \
 				" hugepagesz=2m hugepages=256"
-#define CONFIG_BOOTCOMMAND	"fsl_mc apply dpl 0x580700000 &&" \
+#define CONFIG_BOOTCOMMAND	"fsl_mc apply dpl 0x580d00000 &&" \
 				" cp.b $kernel_start $kernel_load" \
 				" $kernel_size && bootm $kernel_load"
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 469ef9e..4788c15 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -265,7 +265,7 @@ unsigned long get_board_ddr_clk(void);
 
 #ifndef CONFIG_QSPI_BOOT
 #define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x2000
 #endif
@@ -376,12 +376,12 @@ unsigned long get_board_ddr_clk(void);
 	"ramdisk_size=0x2000000\0"		\
 	"fdt_high=0xa0000000\0"			\
 	"initrd_high=0xffffffffffffffff\0"	\
-	"kernel_start=0x581100000\0"		\
+	"kernel_start=0x581000000\0"		\
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x2800000\0"		\
 	"mcmemsize=0x40000000\0"		\
-	"mcinitcmd=fsl_mc start mc 0x580300000" \
-	" 0x580800000 \0"
+	"mcinitcmd=fsl_mc start mc 0x580a00000" \
+	" 0x580e00000 \0"
 #endif /* CONFIG_SECURE_BOOT */
 
 
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 3774b17..0e920f6 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -251,7 +251,7 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 
 #define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x2000
 #endif
@@ -421,13 +421,13 @@ unsigned long get_board_sys_clk(void);
 	"ramdisk_size=0x2000000\0"		\
 	"fdt_high=0xa0000000\0"			\
 	"initrd_high=0xffffffffffffffff\0"	\
-	"kernel_start=0x581100000\0"		\
+	"kernel_start=0x581000000\0"		\
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x2800000\0"		\
 	"mcmemsize=0x40000000\0"		\
 	"fdtfile=fsl-ls2080a-rdb.dtb\0"		\
-	"mcinitcmd=fsl_mc start mc 0x580300000" \
-	" 0x580800000 \0"                       \
+	"mcinitcmd=fsl_mc start mc 0x580a00000" \
+	" 0x580e00000 \0"                       \
 	BOOTENV
 #endif
 #endif
@@ -447,7 +447,7 @@ unsigned long get_board_sys_clk(void);
 			   " || run distro_bootcmd"
 #else
 /* Try to boot an on-NOR kernel first, then do normal distro boot */
-#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \
+#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580d00000" \
 			   " && cp.b $kernel_start $kernel_load $kernel_size" \
 			   " && bootm $kernel_load" \
 			   " || run distro_bootcmd"
@@ -463,7 +463,7 @@ unsigned long get_board_sys_clk(void);
 #ifdef CONFIG_QSPI_BOOT
 #define CONFIG_CORTINA_FW_ADDR		0x20980000
 #else
-#define CONFIG_CORTINA_FW_ADDR		0x581000000
+#define CONFIG_CORTINA_FW_ADDR		0x580980000
 #endif
 #define CONFIG_CORTINA_FW_LENGTH	0x40000
 
-- 
cgit v0.10.2


From 7676074ac756ab9566d52544cc836f7b93f80b37 Mon Sep 17 00:00:00 2001
From: Udit Agarwal <udit.agarwal@nxp.com>
Date: Tue, 2 May 2017 17:43:57 +0530
Subject: armv8: LS2080A: Adjust memory map for secure boot headers for
 NOR-boot

This patch adjusts memory map for secure boot headers on LS2080AQDS
and LS2080ARDB platforms. Secure boot headers are placed on NOR
flash at offset 0x00600000.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index fd0e25a..cad860e 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -96,6 +96,7 @@ RCW+PBI				0x00000000
 Boot firmware (U-Boot)		0x00100000
 Boot firmware Environment	0x00300000
 PPA firmware			0x00400000
+Secure Headers			0x00600000
 DPAA2 MC			0x00A00000
 DPAA2 DPL			0x00D00000
 DPAA2 DPC			0x00E00000
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index f228d80..205c45c 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -92,6 +92,7 @@ RCW+PBI				0x00000000
 Boot firmware (U-Boot)		0x00100000
 Boot firmware Environment	0x00300000
 PPA firmware			0x00400000
+Secure Headers			0x00600000
 Cortina PHY firmware		0x00980000
 DPAA2 MC			0x00A00000
 DPAA2 DPL			0x00D00000
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 4788c15..84e9db2 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -359,14 +359,14 @@ unsigned long get_board_ddr_clk(void);
 	"ramdisk_size=0x2000000\0"		\
 	"fdt_high=0xa0000000\0"			\
 	"initrd_high=0xffffffffffffffff\0"	\
-	"kernel_start=0x581100000\0"		\
+	"kernel_start=0x581000000\0"		\
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x2800000\0"		\
 	"mcmemsize=0x40000000\0"		\
-	"mcinitcmd=esbc_validate 0x580c80000;"  \
-	"esbc_validate 0x580cc0000;"            \
-	"fsl_mc start mc 0x580300000"           \
-	" 0x580800000 \0"
+	"mcinitcmd=esbc_validate 0x580700000;"  \
+	"esbc_validate 0x580740000;"            \
+	"fsl_mc start mc 0x580a00000"           \
+	" 0x580e00000 \0"
 #else
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 0e920f6..c20a7f4 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -378,15 +378,15 @@ unsigned long get_board_sys_clk(void);
 	"ramdisk_size=0x2000000\0"		\
 	"fdt_high=0xa0000000\0"			\
 	"initrd_high=0xffffffffffffffff\0"	\
-	"kernel_start=0x581100000\0"		\
+	"kernel_start=0x581000000\0"		\
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x2800000\0"		\
 	"mcmemsize=0x40000000\0"		\
 	"fdtfile=fsl-ls2080a-rdb.dtb\0"		\
-	"mcinitcmd=esbc_validate 0x580c80000;"  \
-	"esbc_validate 0x580cc0000;"            \
-	"fsl_mc start mc 0x580300000"           \
-	" 0x580800000 \0"                       \
+	"mcinitcmd=esbc_validate 0x580700000;"  \
+	"esbc_validate 0x580740000;"            \
+	"fsl_mc start mc 0x580a00000"           \
+	" 0x580e00000 \0"                       \
 	BOOTENV
 #else
 #ifdef CONFIG_QSPI_BOOT
-- 
cgit v0.10.2