From 3b5b599f171ee66bbb514fddd6361a84f1e198f5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 13:48:08 +0200 Subject: ARM: zynq: Fix sparse warnings in slcr.c Warnings: arch/arm/cpu/armv7/zynq/slcr.c:21:6: warning: symbol 'zynq_slcr_lock' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:27:6: warning: symbol 'zynq_slcr_unlock' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:34:6: warning: symbol 'zynq_slcr_cpu_reset' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:54:6: warning: symbol 'zynq_slcr_gem_clk_setup' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:81:6: warning: symbol 'zynq_slcr_devcfg_disable' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:94:6: warning: symbol 'zynq_slcr_devcfg_enable' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:107:5: warning: symbol 'zynq_slcr_get_boot_mode' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:113:5: warning: symbol 'zynq_slcr_get_idcode' was not declared. Should it be static? Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index d7c1882..c326a4c 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #define SLCR_LOCK_MAGIC 0x767B -- cgit v0.10.2 From ec9638659f5ed9cbb691c09fb72aee12c3426601 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 14:19:00 +0200 Subject: ARM: zynq: Fix sparse warning in ddrc.c Warning: arch/arm/cpu/armv7/zynq/ddrc.c:43:24: warning: Using plain integer as NULL pointer Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index ba6a6ae..302654d 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -40,7 +40,7 @@ void zynq_ddrc_init(void) * first stage bootloader. To get ECC to work all memory has * been initialized by writing any value. */ - memset(0, 0, 1 * 1024 * 1024); + memset((void *)0, 0, 1 * 1024 * 1024); } else { puts("Memory: ECC disabled\n"); } -- cgit v0.10.2 From 5b73caffeb12b0f635693ce4c53177de86dd3b38 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 13:51:17 +0200 Subject: ARM: zynq: Remove sparse warnings Warnings: board/xilinx/zynq/board.c:17:13: warning: symbol 'fpga' was not declared. Should it be static? board/xilinx/zynq/board.c:20:13: warning: symbol 'fpga010' was not declared. Should it be static? board/xilinx/zynq/board.c:21:13: warning: symbol 'fpga015' was not declared. Should it be static? board/xilinx/zynq/board.c:22:13: warning: symbol 'fpga020' was not declared. Should it be static? board/xilinx/zynq/board.c:23:13: warning: symbol 'fpga030' was not declared. Should it be static? board/xilinx/zynq/board.c:24:13: warning: symbol 'fpga045' was not declared. Should it be static? board/xilinx/zynq/board.c:25:13: warning: symbol 'fpga100' was not declared. Should it be static? board/xilinx/zynq/board.c:120:5: warning: symbol 'board_mmc_init' was not declared. Should it be static? Signed-off-by: Michal Simek diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index c8cc2bc..5190938 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -6,6 +6,8 @@ #include #include +#include +#include #include #include #include @@ -14,15 +16,15 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_FPGA -xilinx_desc fpga; +static xilinx_desc fpga; /* It can be done differently */ -xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); -xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); -xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); -xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); -xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); -xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); +static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); +static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); +static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); +static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); +static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif int board_init(void) -- cgit v0.10.2 From 96a2859e54c8f6153ddb429ba730b324ab8ff352 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 29 Nov 2013 19:01:25 +0530 Subject: ARM: zynq: Added efuse status register base address Added efuse status register base address. This register is used for determining whether efuse was blown or not. Also, added the zynq_get_silicon_version() to get the silicon version of the zynq board. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 7626b5c..816d0c5 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -14,6 +14,9 @@ void lowlevel_init(void) { } +#define ZYNQ_SILICON_VER_MASK 0xF0000000 +#define ZYNQ_SILICON_VER_SHIFT 28 + int arch_cpu_init(void) { zynq_slcr_unlock(); @@ -42,6 +45,16 @@ int arch_cpu_init(void) return 0; } +unsigned int zynq_get_silicon_version(void) +{ + unsigned int ver; + + ver = (readl(&devcfg_base->mctrl) & + ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT; + + return ver; +} + void reset_cpu(ulong addr) { zynq_slcr_cpu_reset(); diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 39184da..20f62bf 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -22,6 +22,7 @@ #define ZYNQ_SPI_BASEADDR0 0xE0006000 #define ZYNQ_SPI_BASEADDR1 0xE0007000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 +#define ZYNQ_EFUSE_BASEADDR 0xF800D000 /* Bootmode setting values */ #define ZYNQ_BM_MASK 0xF @@ -130,4 +131,12 @@ struct ddrc_regs { }; #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR) +struct efuse_reg { + u32 reserved1[4]; + u32 status; + u32 reserved2[3]; +}; + +#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR) + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index a68e1b3..2445a04 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -16,6 +16,7 @@ extern void zynq_slcr_devcfg_enable(void); extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); extern void zynq_ddrc_init(void); +extern unsigned int zynq_get_silicon_version(void); /* Driver extern functions */ extern int zynq_sdhci_init(u32 regbase); -- cgit v0.10.2 From 10fa49f428b9425f554f64a74a451868cbbfba3a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 4 Sep 2013 16:51:33 +0200 Subject: ARM: zynq: Do not use half memory size for ECC case Memory size should be specified without ECC place. If you need to have half memory size, please change u-boot configuration. Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index 302654d..e0ed3bf 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -44,7 +44,4 @@ void zynq_ddrc_init(void) } else { puts("Memory: ECC disabled\n"); } - - if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT) - gd->ram_size /= 2; } -- cgit v0.10.2 From 1540fb725bb7067f5cacbcc624f8684ed1471815 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 12:15:40 +0200 Subject: ARM: zynq: Call zynq board_init() in SPL Call board_init() if SPL is configured with CONFIG_SPL_BOARD_INIT. Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c index fcad762..c3ea221 100644 --- a/arch/arm/cpu/armv7/zynq/spl.c +++ b/arch/arm/cpu/armv7/zynq/spl.c @@ -28,6 +28,13 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); } +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + board_init(); +} +#endif + u32 spl_boot_device(void) { u32 mode; diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 731e69b..2080a61 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -235,6 +235,7 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot-spl.lds" -- cgit v0.10.2 From 6e04769caf208a9f2da8ef8a85353def2a170176 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 27 Mar 2014 10:06:43 +0100 Subject: ARM: zynq: slcr: Fix incorrect commentary Fix c&p error in zynq_slcr_devcfg_enable() commentary and extending it with description according to Zynq TRM also in zynq_slcr_devcfg_disable(). Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index c326a4c..1ff1eac 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -83,7 +83,7 @@ void zynq_slcr_devcfg_disable(void) { zynq_slcr_unlock(); - /* Disable AXI interface */ + /* Disable AXI interface by asserting FPGA resets */ writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl); /* Set Level Shifters DT618760 */ @@ -99,7 +99,7 @@ void zynq_slcr_devcfg_enable(void) /* Set Level Shifters DT618760 */ writel(0xF, &slcr_base->lvl_shftr_en); - /* Disable AXI interface */ + /* Enable AXI interface by de-asserting FPGA resets */ writel(0x0, &slcr_base->fpga_rst_ctrl); zynq_slcr_lock(); -- cgit v0.10.2 From 2da7a745b6d24eec7be30e7d11ca456d445e30c3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 30 Aug 2013 07:26:08 +0200 Subject: ARM: zynq: Setup correct slcr_lock value The driver should setup slcr state according to slcr operations. Reported-by: Andrey Filippov Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 1ff1eac..5ba58fa 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -21,14 +21,18 @@ static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ void zynq_slcr_lock(void) { - if (!slcr_lock) + if (!slcr_lock) { writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock); + slcr_lock = 1; + } } void zynq_slcr_unlock(void) { - if (slcr_lock) + if (slcr_lock) { writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock); + slcr_lock = 0; + } } /* Reset the entire system */ -- cgit v0.10.2 From dc4a1a2729f9ccaa473cf017c8bd4be4f242cafe Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Thu, 6 Mar 2014 14:43:36 +0100 Subject: ARM: zynq: Fix bootmode mask Bootmode mask was defined as 0x0F, but documentation mentions 0x07. Experiments show that bit "3" is the JTAG chain configuration. Change the mask to "7" to allow systems with a different chain configuration to boot correctly. Signed-off-by: Mike Looijmans Acked-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 20f62bf..a9d091f 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -25,7 +25,7 @@ #define ZYNQ_EFUSE_BASEADDR 0xF800D000 /* Bootmode setting values */ -#define ZYNQ_BM_MASK 0xF +#define ZYNQ_BM_MASK 0x7 #define ZYNQ_BM_NOR 0x2 #define ZYNQ_BM_SD 0x5 #define ZYNQ_BM_JTAG 0x0 -- cgit v0.10.2 From 0b680206ccf5a4ae6adf759339ba7dc7ce06d284 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 4 Mar 2014 12:41:05 +0100 Subject: ARM: zynq: Fix building SPL without FPGA support When CONFIG_FPGA is defined but CONFIG_SPL_FPGA is not, the build fails: board.c: In function 'board_init': board.c:41:3: error: 'fpga' undeclared (first use in this function) fpga = fpga010; Fix this by expanding the "#if.." around this block to match the other FPGA checks and don't compile this block when buildign for SPL without FPGA support. Tested a bootloader that had CONFIG_FPGA defined without CONFIG_SPL_FPGA, this now compiles without errors and loading FPGA from u-boot works. Signed-off-by: Mike Looijmans Signed-off-by: Michal Simek diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 5190938..258632e 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -15,7 +15,8 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_FPGA +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) static xilinx_desc fpga; /* It can be done differently */ @@ -29,7 +30,8 @@ static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); int board_init(void) { -#ifdef CONFIG_FPGA +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) u32 idcode; idcode = zynq_slcr_get_idcode(); @@ -56,7 +58,8 @@ int board_init(void) } #endif -#ifdef CONFIG_FPGA +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); fpga_add(fpga_xilinx, &fpga); #endif -- cgit v0.10.2 From 3d456eec43c13778738a5b5246a4109282d207a3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 20 Jan 2014 11:29:06 +0100 Subject: ARM: zynq: Extend kernel image size to 60MB Extend max kernel image size. Gunzip is checking this value. If kernel is larger, message below is shown. Uncompressing Kernel Image ... Error: inflate() returned -5 GUNZIP: uncompress, out-of-mem or overwrite error - must RESET board to recover Signed-off-by: Michal Simek diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 2080a61..8ee78e4 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -209,7 +209,7 @@ #define CONFIG_RSA /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (20 * 1024 * 1024) +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) /* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) -- cgit v0.10.2 From 3cc3fa8672705e609ccd25348438453bd8de07fd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 12:21:04 +0200 Subject: ARM: zynq: Add MIO detection code Add run-time MIO pin detection to get actual pin configuration for specific periphery. Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 5ba58fa..51894f9 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -17,6 +17,26 @@ #define SLCR_IDCODE_MASK 0x1F000 #define SLCR_IDCODE_SHIFT 12 +/* + * zynq_slcr_mio_get_status - Get the status of MIO peripheral. + * + * @peri_name: Name of the peripheral for checking MIO status + * @get_pins: Pointer to array of get pin for this peripheral + * @num_pins: Number of pins for this peripheral + * @mask: Mask value + * @check_val: Required check value to get the status of periph + */ +struct zynq_slcr_mio_get_status { + const char *peri_name; + const int *get_pins; + int num_pins; + u32 mask; + u32 check_val; +}; + +static const struct zynq_slcr_mio_get_status mio_periphs[] = { +}; + static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ void zynq_slcr_lock(void) @@ -120,3 +140,33 @@ u32 zynq_slcr_get_idcode(void) return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> SLCR_IDCODE_SHIFT; } + +/* + * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral. + * + * @periph: Name of the peripheral + * + * Returns count to indicate the number of pins configured for the + * given @periph. + */ +int zynq_slcr_get_mio_pin_status(const char *periph) +{ + const struct zynq_slcr_mio_get_status *mio_ptr; + int val, i, j; + int mio = 0; + + for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) { + if (strcmp(periph, mio_periphs[i].peri_name) == 0) { + mio_ptr = &mio_periphs[i]; + for (j = 0; j < mio_ptr->num_pins; j++) { + val = readl(&slcr_base->mio_pin + [mio_ptr->get_pins[j]]); + if ((val & mio_ptr->mask) == mio_ptr->check_val) + mio++; + } + break; + } + } + + return mio; +} diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index 2445a04..53c30ec 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -15,6 +15,7 @@ extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); +extern int zynq_slcr_get_mio_pin_status(const char *periph); extern void zynq_ddrc_init(void); extern unsigned int zynq_get_silicon_version(void); -- cgit v0.10.2 From eb8c54bfaabec7b8ba65a054f6c3e37572288ae9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 12:21:04 +0200 Subject: ARM: zynq: ehci: Added USB host driver support Added USB host driver for zynq. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 51894f9..934ccc3 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -14,6 +14,8 @@ #define SLCR_LOCK_MAGIC 0x767B #define SLCR_UNLOCK_MAGIC 0xDF0D +#define SLCR_USB_L1_SEL 0x04 + #define SLCR_IDCODE_MASK 0x1F000 #define SLCR_IDCODE_SHIFT 12 @@ -34,7 +36,29 @@ struct zynq_slcr_mio_get_status { u32 check_val; }; +static const int usb0_pins[] = { + 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39 +}; + +static const int usb1_pins[] = { + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51 +}; + static const struct zynq_slcr_mio_get_status mio_periphs[] = { + { + "usb0", + usb0_pins, + ARRAY_SIZE(usb0_pins), + SLCR_USB_L1_SEL, + SLCR_USB_L1_SEL, + }, + { + "usb1", + usb1_pins, + ARRAY_SIZE(usb1_pins), + SLCR_USB_L1_SEL, + SLCR_USB_L1_SEL, + }, }; static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index a9d091f..2aede0c 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -23,6 +23,8 @@ #define ZYNQ_SPI_BASEADDR1 0xE0007000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 #define ZYNQ_EFUSE_BASEADDR 0xF800D000 +#define ZYNQ_USB_BASEADDR0 0xE0002000 +#define ZYNQ_USB_BASEADDR1 0xE0003000 /* Bootmode setting values */ #define ZYNQ_BM_MASK 0x7 diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index b301e28..7211c6a 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o +obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o diff --git a/drivers/usb/host/ehci-zynq.c b/drivers/usb/host/ehci-zynq.c new file mode 100644 index 0000000..7770d05 --- /dev/null +++ b/drivers/usb/host/ehci-zynq.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2014, Xilinx, Inc + * + * USB Low level initialization(Specific to zynq) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "ehci.h" + +#define ZYNQ_USB_USBCMD_RST 0x0000002 +#define ZYNQ_USB_USBCMD_STOP 0x0000000 +#define ZYNQ_USB_NUM_MIO 12 + +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, + struct ehci_hcor **hcor) +{ + struct usb_ehci *ehci; + struct ulpi_viewport ulpi_vp; + int ret, mio_usb; + /* Used for writing the ULPI data address */ + struct ulpi_regs *ulpi = (struct ulpi_regs *)0; + + if (!index) { + mio_usb = zynq_slcr_get_mio_pin_status("usb0"); + if (mio_usb != ZYNQ_USB_NUM_MIO) { + printf("usb0 wrong num MIO: %d, Index %d\n", mio_usb, + index); + return -1; + } + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0; + } else { + mio_usb = zynq_slcr_get_mio_pin_status("usb1"); + if (mio_usb != ZYNQ_USB_NUM_MIO) { + printf("usb1 wrong num MIO: %d, Index %d\n", mio_usb, + index); + return -1; + } + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1; + } + + *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); + *hcor = (struct ehci_hcor *)((uint32_t) *hccr + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + + ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; + ulpi_vp.port_num = 0; + + ret = ulpi_init(&ulpi_vp); + if (ret) { + puts("zynq ULPI viewport init failed\n"); + return -1; + } + + /* ULPI set flags */ + ulpi_write(&ulpi_vp, &ulpi->otg_ctrl, + ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN | + ULPI_OTG_EXTVBUSIND); + ulpi_write(&ulpi_vp, &ulpi->function_ctrl, + ULPI_FC_FULL_SPEED | ULPI_FC_OPMODE_NORMAL | + ULPI_FC_SUSPENDM); + ulpi_write(&ulpi_vp, &ulpi->iface_ctrl, 0); + + /* Set VBus */ + ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(int index) +{ + struct usb_ehci *ehci; + + if (!index) + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0; + else + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1; + + /* Stop controller */ + writel(ZYNQ_USB_USBCMD_STOP, &ehci->usbcmd); + udelay(1000); + + /* Initiate controller reset */ + writel(ZYNQ_USB_USBCMD_RST, &ehci->usbcmd); + + return 0; +} -- cgit v0.10.2 From c6024c8edd5e9e27f1099341cca1fc41f77c5ed4 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 20 Feb 2014 10:28:27 +0530 Subject: ARM: zynq: Added USB host support for zynq boards Added configs to support USB host for zynq boards. Also added a command usbboot to boot from usb. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 8ee78e4..bcc476e 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -89,6 +89,18 @@ # define CONFIG_DOS_PARTITION #endif +#ifdef CONFIG_ZYNQ_USB +# define CONFIG_USB_EHCI +# define CONFIG_CMD_USB +# define CONFIG_USB_STORAGE +# define CONFIG_SUPPORT_VFAT +# define CONFIG_USB_EHCI_ZYNQ +# define CONFIG_USB_ULPI_VIEWPORT +# define CONFIG_USB_ULPI +# define CONFIG_EHCI_IS_TDI +# define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + #define CONFIG_SYS_I2C_ZYNQ /* I2C */ #if defined(CONFIG_SYS_I2C_ZYNQ) @@ -150,7 +162,13 @@ "bootm ${load_addr}\0" \ "jtagboot=echo TFTPing FIT to RAM... && " \ "tftpboot ${load_addr} ${fit_image} && " \ - "bootm ${load_addr}\0" + "bootm ${load_addr}\0" \ + "usbboot=if usb start; then " \ + "echo Copying FIT from USB to RAM... && " \ + "fatload usb 0 ${load_addr} ${fit_image} && " \ + "bootm ${load_addr}\0" \ + "fi\0" + #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */ #define CONFIG_SYS_LOAD_ADDR 0 /* default? */ diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index de0e241..291a5fe 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -19,6 +19,7 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_USB #define CONFIG_ZYNQ_I2C0 #define CONFIG_ZYNQ_EEPROM #define CONFIG_ZYNQ_BOOT_FREEBSD diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h index 274140c..ce17d40 100644 --- a/include/configs/zynq_zed.h +++ b/include/configs/zynq_zed.h @@ -18,6 +18,7 @@ #define CONFIG_SYS_NO_FLASH +#define CONFIG_ZYNQ_USB #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_BOOT_FREEBSD #define CONFIG_DEFAULT_DEVICE_TREE zynq-zed -- cgit v0.10.2 From 00cf6b4e229f8537ea2543ccc01e08a310414d09 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Wed, 12 Feb 2014 21:45:51 +0530 Subject: ARM: zynq: Enable the FAT write capability Enable the FAT write capability for SD/MMC write functionality. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index bcc476e..1cfc963 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -86,6 +86,7 @@ # define CONFIG_CMD_FAT # define CONFIG_SUPPORT_VFAT # define CONFIG_CMD_EXT2 +# define CONFIG_FAT_WRITE # define CONFIG_DOS_PARTITION #endif -- cgit v0.10.2 From 47b35a516b60de6c1055fab3a866a1e70bf12f6b Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Wed, 12 Mar 2014 14:52:56 +0530 Subject: ARM: zynq: Move USB/SD/MMC common FAT configs Moved the USB/SD/MMC common FAT configs separately to avoid redefinition warnings. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 1cfc963..0a7d104 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -83,18 +83,12 @@ # define CONFIG_SDHCI # define CONFIG_ZYNQ_SDHCI # define CONFIG_CMD_MMC -# define CONFIG_CMD_FAT -# define CONFIG_SUPPORT_VFAT -# define CONFIG_CMD_EXT2 -# define CONFIG_FAT_WRITE -# define CONFIG_DOS_PARTITION #endif #ifdef CONFIG_ZYNQ_USB # define CONFIG_USB_EHCI # define CONFIG_CMD_USB # define CONFIG_USB_STORAGE -# define CONFIG_SUPPORT_VFAT # define CONFIG_USB_EHCI_ZYNQ # define CONFIG_USB_ULPI_VIEWPORT # define CONFIG_USB_ULPI @@ -102,6 +96,14 @@ # define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif +#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQ_USB) +# define CONFIG_SUPPORT_VFAT +# define CONFIG_CMD_FAT +# define CONFIG_CMD_EXT2 +# define CONFIG_FAT_WRITE +# define CONFIG_DOS_PARTITION +#endif + #define CONFIG_SYS_I2C_ZYNQ /* I2C */ #if defined(CONFIG_SYS_I2C_ZYNQ) -- cgit v0.10.2 From 2e38a9067227ca005e61afc3337c32ae92a4d0c4 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Wed, 12 Mar 2014 14:52:56 +0530 Subject: ARM: zynq: Enable EXT4 configs Enabled the EXT4 configs. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 0a7d104..09d6c55 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -102,6 +102,8 @@ # define CONFIG_CMD_EXT2 # define CONFIG_FAT_WRITE # define CONFIG_DOS_PARTITION +# define CONFIG_CMD_EXT4 +# define CONFIG_CMD_EXT4_WRITE #endif #define CONFIG_SYS_I2C_ZYNQ -- cgit v0.10.2 From 841426ad9f19b7bcf4add8329484ebad672daa9c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 13:33:19 +0200 Subject: ARM: zynq: Extend maximum number of command arguments 15 was too small for variables stored in file on MMC. Signed-off-by: Michal Simek diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 09d6c55..d2149b3 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -188,7 +188,7 @@ #define CONFIG_SYS_LONGHELP #define CONFIG_CLOCKS #define CONFIG_CMD_CLK -#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -- cgit v0.10.2 From f05862d7bdba1912d041df1e1434af82d47e64d2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 8 May 2014 17:13:56 +0900 Subject: zynq: add empty xil_io.h to avoid compile error ps7_init.c exported by hw project has #include "xil_io.h" line but U-Boot does not have "xil_io.h". So we get an error on SPL build: ps7_init.c:12581:20: fatal error: xil_io.h: No such file or directory We can delete the include directive in ps7_init.c to avoid this error. But it is painful to do this every time we export ps7_init.c file. Instead, we can put an empty xil_io.h in the same directory so we can directly copy ps7_init.c as is. Signed-off-by: Masahiro Yamada Acked-by: Tom Rini Signed-off-by: Michal Simek diff --git a/board/xilinx/zynq/xil_io.h b/board/xilinx/zynq/xil_io.h new file mode 100644 index 0000000..e59a977 --- /dev/null +++ b/board/xilinx/zynq/xil_io.h @@ -0,0 +1,13 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H + +/* + * This empty file is here because ps7_init.c exported by hw project + * has #include "xil_io.h" line. + */ + +#endif /* XIL_IO_H */ -- cgit v0.10.2 From 66e6715c5ffe817c70485020508c7b9ec47227b7 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 12 May 2014 12:18:30 +0900 Subject: zynq: treat ps7_init.c/h as external files to ignore them ps7_init.c and ps7_init.h are supposed to be exported by hw project and copied to board/xilinx/zynq/ directory. We want them to be ignored by git. So what we should do is to always treat them as external files rather than replacing ps7_init.c This commit does: - Move a weak function ps7_init() to arch/arm/cpu/armv7/zynq/spl.c and delete board/xilinx/zynq/ps7_init.c - Compile board/xilinx/zynq/ps7_init.c only when it exists - Add .gitignore to ignore ps7_init.c/h Signed-off-by: Masahiro Yamada Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c index c3ea221..d73e5cb 100644 --- a/arch/arm/cpu/armv7/zynq/spl.c +++ b/arch/arm/cpu/armv7/zynq/spl.c @@ -74,3 +74,11 @@ int spl_start_uboot(void) return 0; } #endif + +__weak void ps7_init(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynq/ps7_init.c, if it exists. + */ +} diff --git a/board/xilinx/zynq/.gitignore b/board/xilinx/zynq/.gitignore new file mode 100644 index 0000000..68b8edd --- /dev/null +++ b/board/xilinx/zynq/.gitignore @@ -0,0 +1 @@ +ps7_init.[ch] diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 3f19a1c..fd93f63 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -6,4 +6,7 @@ # obj-y := board.o -obj-$(CONFIG_SPL_BUILD) += ps7_init.o + +# Please copy ps7_init.c/h from hw project to this directory +obj-$(CONFIG_SPL_BUILD) += \ + $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o) diff --git a/board/xilinx/zynq/ps7_init.c b/board/xilinx/zynq/ps7_init.c deleted file mode 100644 index c47da09..0000000 --- a/board/xilinx/zynq/ps7_init.c +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2014 Xilinx, Inc. Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include - -__weak void ps7_init(void) -{ - puts("Please copy ps7_init.c/h from hw project\n"); -} -- cgit v0.10.2 From 2405d09c4c8a1e4cd7744e5f10d1592bd974a939 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 15 May 2014 20:37:51 +0900 Subject: build: support a new image u-boot-dtb.img In SPL framework, SPL uses u-boot.img to load u-boot.bin. Here, u-boot.img = uImage header + u-boot.bin To use OF control with a separate devicetree, u-boot.dtb must be placed right after u-boot.bin. In this case, u-boot-dtb.bin is generally used. Here, u-boot-dtb.bin = u-boot.bin + u-boot.dtb We need u-boot-dtb.img to use both SPL framework and separate OF control at the same time. u-boot-dtb.img = uImage header + u-boot-dtb.bin For example, Zynq boards already define all of - CONFIG_SPL - CONFIG_OF_CONTROL - CONFIG_OF_SEPARATE So, the support of u-boot-dtb.img is urgent. Signed-off-by: Masahiro Yamada Cc: Michal Simek Acked-by: Simon Glass Signed-off-by: Michal Simek diff --git a/Makefile b/Makefile index e82f616..83d1cc6 100644 --- a/Makefile +++ b/Makefile @@ -752,6 +752,9 @@ ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin +ifeq ($(CONFIG_SPL_FRAMEWORK),y) +ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img +endif ALL-$(CONFIG_OF_HOSTFILE) += u-boot.dtb ifneq ($(CONFIG_SPL_TARGET),) ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) @@ -854,6 +857,11 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE $(call if_changed,mkimage) +MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img) + +u-boot-dtb.img: u-boot-dtb.bin FORCE + $(call if_changed,mkimage) + u-boot.sha1: u-boot.bin tools/ubsha1 u-boot.bin -- cgit v0.10.2 From 0dfbcf02de58b2ebf8ea63f57a9971592b5b2277 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 15 May 2014 20:37:52 +0900 Subject: zynq: load u-boot-dtb.img if CONFIG_OF_SEPARATE is defined SPL should load "u-boot-dtb.img" if both CONFIG_OF_CONTROL and CONFIG_OF_SEPARATE are defined. Otherwise, "u-boot.img" should be loaded. Since CONFIG_OF_CONTROL is always undefined for SPL_BUILD, the undef block should be moved below the conditional definition of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME. Signed-off-by: Masahiro Yamada Cc: Michal Simek Signed-off-by: Michal Simek diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index d2149b3..579091d 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -262,13 +262,6 @@ #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot-spl.lds" -/* Disable dcache for SPL just for sure */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_DCACHE_OFF -#undef CONFIG_FPGA -#undef CONFIG_OF_CONTROL -#endif - /* MMC support */ #ifdef CONFIG_ZYNQ_SDHCI0 #define CONFIG_SPL_MMC_SUPPORT @@ -277,7 +270,18 @@ #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_OF_SEPARATE) +# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +#else +# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#endif +#endif + +/* Disable dcache for SPL just for sure */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_DCACHE_OFF +#undef CONFIG_FPGA +#undef CONFIG_OF_CONTROL #endif /* Address in RAM where the parameters must be copied by SPL. */ -- cgit v0.10.2 From 580a54c5d464d9c23b79e249e7ab0979900f9cf4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 15 May 2014 20:37:53 +0900 Subject: zynq: import zynq-7000.dtsi from Linux Kernel Our current motivation is to use OF initialization for RAM and UART. But adding full DTS would be helpful in future, for instance, for OF configuration of Ethernet, MMC, USB, etc. This commit imports arch/arm/boot/dts/zynq-7000.dtsi from Linux 3.15-rc5 and adjusts the license comment block for SPDX. Signed-off-by: Masahiro Yamada Suggested-by: Michal Simek Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index f20b8bd..2d076f1 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -10,4 +10,198 @@ / { compatible = "xlnx,zynq-7000"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + clocks = <&clkc 3>; + clock-latency = <1000>; + operating-points = < + /* kHz uV */ + 666667 1000000 + 333334 1000000 + 222223 1000000 + >; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + clocks = <&clkc 3>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 5 4>, <0 6 4>; + interrupt-parent = <&intc>; + reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + i2c0: zynq-i2c@e0004000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <&clkc 38>; + interrupt-parent = <&intc>; + interrupts = <0 25 4>; + reg = <0xe0004000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: zynq-i2c@e0005000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <&clkc 39>; + interrupt-parent = <&intc>; + interrupts = <0 48 4>; + reg = <0xe0005000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + intc: interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xF8F01000 0x1000>, + <0xF8F00100 0x100>; + }; + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xF8F02000 0x1000>; + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-unified; + cache-level = <2>; + }; + + uart0: uart@e0000000 { + compatible = "xlnx,xuartps"; + status = "disabled"; + clocks = <&clkc 23>, <&clkc 40>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xE0000000 0x1000>; + interrupts = <0 27 4>; + }; + + uart1: uart@e0001000 { + compatible = "xlnx,xuartps"; + status = "disabled"; + clocks = <&clkc 24>, <&clkc 41>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xE0001000 0x1000>; + interrupts = <0 50 4>; + }; + + gem0: ethernet@e000b000 { + compatible = "cdns,gem"; + reg = <0xe000b000 0x4000>; + status = "disabled"; + interrupts = <0 22 4>; + clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; + clock-names = "pclk", "hclk", "tx_clk"; + }; + + gem1: ethernet@e000c000 { + compatible = "cdns,gem"; + reg = <0xe000c000 0x4000>; + status = "disabled"; + interrupts = <0 45 4>; + clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; + clock-names = "pclk", "hclk", "tx_clk"; + }; + + sdhci0: ps7-sdhci@e0100000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 21>, <&clkc 32>; + interrupt-parent = <&intc>; + interrupts = <0 24 4>; + reg = <0xe0100000 0x1000>; + } ; + + sdhci1: ps7-sdhci@e0101000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 22>, <&clkc 33>; + interrupt-parent = <&intc>; + interrupts = <0 47 4>; + reg = <0xe0101000 0x1000>; + } ; + + slcr: slcr@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-slcr", "syscon"; + reg = <0xF8000000 0x1000>; + ranges; + clkc: clkc@100 { + #clock-cells = <1>; + compatible = "xlnx,ps7-clkc"; + ps-clk-frequency = <33333333>; + fclk-enable = <0>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", + "dci", "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", + "dma", "usb0_aper", "usb1_aper", "gem0_aper", + "gem1_aper", "sdio0_aper", "sdio1_aper", + "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", + "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", + "gpio_aper", "lqspi_aper", "smc_aper", "swdt", + "dbg_trc", "dbg_apb"; + reg = <0x100 0x100>; + }; + }; + + global_timer: timer@f8f00200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf8f00200 0x20>; + interrupts = <1 11 0x301>; + interrupt-parent = <&intc>; + clocks = <&clkc 4>; + }; + + ttc0: ttc0@f8001000 { + interrupt-parent = <&intc>; + interrupts = < 0 10 4 0 11 4 0 12 4 >; + compatible = "cdns,ttc"; + clocks = <&clkc 6>; + reg = <0xF8001000 0x1000>; + }; + + ttc1: ttc1@f8002000 { + interrupt-parent = <&intc>; + interrupts = < 0 37 4 0 38 4 0 39 4 >; + compatible = "cdns,ttc"; + clocks = <&clkc 6>; + reg = <0xF8002000 0x1000>; + }; + scutimer: scutimer@f8f00600 { + interrupt-parent = <&intc>; + interrupts = < 1 13 0x301 >; + compatible = "arm,cortex-a9-twd-timer"; + reg = < 0xf8f00600 0x20 >; + clocks = <&clkc 4>; + } ; + }; }; -- cgit v0.10.2 From 7d34c5de72ef2f48ac4d17e4faadd952b897b8b3 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 15 May 2014 20:37:54 +0900 Subject: zynq: add memory nodes to device tree to initialize DRAM with OF Commit 9e0e37ac added OF RAM initialization support but memory nodes are missing in device tree. Signed-off-by: Masahiro Yamada Cc: Michal Simek Tested-by: Masahiro Yamada [on ZC706 board] Tested-by: Michal Simek [on ZC702 board] Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index 6da71c1..842896f 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -11,4 +11,9 @@ / { model = "Zynq MicroZED Board"; compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 667dc28..a94e331 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -11,4 +11,9 @@ / { model = "Zynq ZC702 Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 526fc88..92de947 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -11,4 +11,9 @@ / { model = "Zynq ZC706 Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 8b542a1..8d68208 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -11,4 +11,9 @@ / { model = "Zynq ZC770 XM010 Board"; compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 0379a07..9ebbddf 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -11,4 +11,9 @@ / { model = "Zynq ZC770 XM012 Board"; compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index a4f9e05..b4f7fa2 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -11,4 +11,9 @@ / { model = "Zynq ZC770 XM013 Board"; compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 91a5deb..3488a56 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -11,4 +11,9 @@ / { model = "Zynq ZED Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x20000000>; + }; }; -- cgit v0.10.2 From 9f9d41bad16efe0674257b4efe4db1a399f93643 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 15 May 2014 20:37:55 +0900 Subject: zynq: add UART nodes to device tree to initialize UART with OF Commit c9416b92 added OF UART initialization support but aliases nodes are missing in device tree. Signed-off-by: Masahiro Yamada Cc: Michal Simek Tested-by: Masahiro Yamada [on ZC706 board] Tested-by: Michal Simek [on ZC702 board] Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index 842896f..c373a2c 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -12,6 +12,10 @@ model = "Zynq MicroZED Board"; compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000"; + aliases { + serial0 = &uart1; + }; + memory { device_type = "memory"; reg = <0 0x40000000>; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index a94e331..4fa0b00 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -12,6 +12,10 @@ model = "Zynq ZC702 Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; + aliases { + serial0 = &uart1; + }; + memory { device_type = "memory"; reg = <0 0x40000000>; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 92de947..2a80195 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -12,6 +12,10 @@ model = "Zynq ZC706 Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; + aliases { + serial0 = &uart1; + }; + memory { device_type = "memory"; reg = <0 0x40000000>; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 8d68208..5e661749 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -12,6 +12,10 @@ model = "Zynq ZC770 XM010 Board"; compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; + aliases { + serial0 = &uart1; + }; + memory { device_type = "memory"; reg = <0 0x40000000>; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 9ebbddf..127a661 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -12,6 +12,10 @@ model = "Zynq ZC770 XM012 Board"; compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; + aliases { + serial0 = &uart1; + }; + memory { device_type = "memory"; reg = <0 0x40000000>; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index b4f7fa2..c61c7e7 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -12,6 +12,10 @@ model = "Zynq ZC770 XM013 Board"; compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; + aliases { + serial0 = &uart0; + }; + memory { device_type = "memory"; reg = <0 0x40000000>; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 3488a56..70cc8a6 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -12,6 +12,10 @@ model = "Zynq ZED Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; + aliases { + serial0 = &uart1; + }; + memory { device_type = "memory"; reg = <0 0x20000000>; -- cgit v0.10.2