From 39aba2257d019528a9c05085634ac50981862bc5 Mon Sep 17 00:00:00 2001 From: Suresh Gupta Date: Fri, 14 Oct 2016 12:11:59 +0530 Subject: armv8: Add workaround for USB erratum A-009008 USB High Speed (HS) EYE Height Adjustment This patch is adding the erratum for LS1043 and LS2080 SoCs. But miss LS1088A due to code base not support LS1088A yet, need to be added in arch/arm/cpu/armv8/fsl-layerscape/Kconfig in the future. Signed-off-by: Sriram Dash Signed-off-by: Rajesh Bhagat Signed-off-by: yinbo.zhu Signed-off-by: ran.wang diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 096137c..a14708d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -9,6 +9,7 @@ config ARCH_LS1012A select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_ERRATUM_A009008 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F @@ -30,6 +31,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R @@ -53,6 +55,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A010539 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R @@ -101,6 +104,7 @@ config FSL_LSCH2 select SYS_FSL_SEC_BE select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -110,6 +114,7 @@ config FSL_LSCH3 select SYS_HAS_SERDES select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_ERRATUM_A009008 config FSL_MC_ENET bool "Management Complex network" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index b6408cd..c5ea47d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -26,6 +26,30 @@ DECLARE_GLOBAL_DATA_PTR; +static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008 +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A) +u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; +u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4); +val &= ~(0xF << 6); +scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6)); +val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4); +val &= ~(0xF << 6); +scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6)); +val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4); +val &= ~(0xF << 6); +scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6)); +#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; +u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4); +val &= ~(0xF << 6); +scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6)); +#endif +#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ +} + + static void erratum_a009798(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A009798 @@ -286,6 +310,7 @@ void fsl_lsch3_early_init_f(void) erratum_a008514(); erratum_a008336(); erratum_a009008(); + erratum_a009008(); erratum_a009798(); erratum_a008997(); erratum_a009007(); @@ -564,6 +589,7 @@ void fsl_lsch2_early_init_f(void) erratum_a009929(); erratum_a009660(); erratum_a010539(); + erratum_a009008(); erratum_a009798(); erratum_a008997(); erratum_a009007(); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 8bc4134..2409879 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -142,6 +142,7 @@ #define SCFG_USB3PRM2CR 0x004 #define SCFG_USB3PRM1CR_INIT 0x27672b2a #define USB_TXVREFTUNE 0x9 +#define USB_TXVREFTUNE 0x9 #define USB_SQRXTUNE 0xFC7FFFFF #define USB_PCSTXSWINGFULL 0x47 #define SCFG_QSPICLKCTLR 0x10 -- cgit v0.10.2