From c6d339016064d014f36072898a26a333c7b61719 Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@kernel.crashing.org>
Date: Wed, 31 Aug 2011 09:50:13 -0500
Subject: powerpc/85xx: Refactor some defines out of corenet_ds.h

Move some SoC/board specific defines out of corenet_ds.h and into the
corresponding P3041DS/P4080DS/P5020.h.

We moved CONFIG_MMC, CONFIG_PCIE3, & CONFIG_FSL_NGPIXIS because the P3060
SoC/reference board does not have these devices and it will share the same
board code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
index d9e8f51..e4d1fe5 100644
--- a/include/configs/P3041DS.h
+++ b/include/configs/P3041DS.h
@@ -28,7 +28,12 @@
 #define CONFIG_PHYS_64BIT
 #define CONFIG_PPC_P3041
 
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#define CONFIG_MMC
+#define CONFIG_NAND_FSL_ELBC
 #define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE3
 #define CONFIG_PCIE4
 
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 49f7c53..4a2e475 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -27,6 +27,11 @@
 #define CONFIG_PHYS_64BIT
 #define CONFIG_PPC_P4080
 
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#define CONFIG_MMC
+#define CONFIG_PCIE3
+
 #define CONFIG_ICS307_REFCLK_HZ		33333000  /* ICS307 ref clk freq */
 
 #include "corenet_ds.h"
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
index dd8d442..4d990be 100644
--- a/include/configs/P5020DS.h
+++ b/include/configs/P5020DS.h
@@ -28,7 +28,12 @@
 #define CONFIG_PHYS_64BIT
 #define CONFIG_PPC_P5020
 
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#define CONFIG_MMC
+#define CONFIG_NAND_FSL_ELBC
 #define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE3
 #define CONFIG_PCIE4
 
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index d5fc19b..4bbca88 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -56,7 +56,6 @@
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #define CONFIG_PCIE1			/* PCIE controler 1 */
 #define CONFIG_PCIE2			/* PCIE controler 2 */
-#define CONFIG_PCIE3			/* PCIE controler 3 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
@@ -199,7 +198,6 @@
 	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 #define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
 
-#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
 #define PIXIS_BASE		0xffdf0000	/* PIXIS registers */
 #ifdef CONFIG_PHYS_64BIT
 #define PIXIS_BASE_PHYS		0xfffdf0000ull
@@ -230,8 +228,6 @@
 #endif
 
 /* Nand Flash */
-#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
-#define CONFIG_NAND_FSL_ELBC
 #ifdef CONFIG_NAND_FSL_ELBC
 #define CONFIG_SYS_NAND_BASE		0xffa00000
 #ifdef CONFIG_PHYS_64BIT
@@ -272,11 +268,10 @@
 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #endif
-#endif /* CONFIG_NAND_FSL_ELBC */
 #else
 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#endif
+#endif /* CONFIG_NAND_FSL_ELBC */
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
@@ -587,8 +582,6 @@
 #define CONFIG_CMD_EXT2
 #define CONFIG_HAS_FSL_DR_USB
 
-#define CONFIG_MMC
-
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
-- 
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