From 06ad970b53a3d6aa122685e6142a04908434a8ef Mon Sep 17 00:00:00 2001 From: Darwin Dingel Date: Tue, 25 Oct 2016 09:48:01 +1300 Subject: powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907 Core hang occurs when using L1 stashes. Workaround is to disable L1 stashes so software uses L2 cache for stashes instead. Reviewed-by: Chris Packham Signed-off-by: Darwin Dingel Cc: York Sun [York S: Move SYS_FSL_ERRATUM_A007907 to Kconfig] Reviewed-by: York Sun diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 704f65b..b0f34b6 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -365,6 +365,7 @@ config ARCH_B4860 select SYS_FSL_ERRATUM_A007075 select SYS_FSL_ERRATUM_A007186 select SYS_FSL_ERRATUM_A007212 + select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -830,6 +831,7 @@ config ARCH_T2080 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007186 select SYS_FSL_ERRATUM_A007212 + select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 @@ -891,6 +893,7 @@ config ARCH_T4240 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007186 select SYS_FSL_ERRATUM_A007798 + select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -1081,6 +1084,9 @@ config SYS_FSL_ERRATUM_A007212 config SYS_FSL_ERRATUM_A007798 bool +config SYS_FSL_ERRATUM_A007907 + bool + config SYS_FSL_ERRATUM_A008044 bool diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 54b5b33..822ae72 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -330,7 +330,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 puts("Work-around for Erratum A009663 enabled\n"); #endif - +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907 + puts("Work-around for Erratum A007907 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 822844d..f5bf67c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -777,6 +777,13 @@ int cpu_init_r(void) sync(); } #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907 + flush_dcache(); + mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); + sync(); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 /* * A-005812 workaround sets bit 32 of SPR 976 for SoCs running diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index fbf72bb..81bae6f 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -501,6 +501,7 @@ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ #define L1CSR2_DCWS 0x40000000 /* Data Cache Write Shadow */ +#define L1CSR2_DCSTASHID 0x000003ff /* Data Cache Stash ID */ #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ -- cgit v0.10.2 From 09bfd962bdc97359b916bfbf18a17e2a85396d65 Mon Sep 17 00:00:00 2001 From: Tony O'Brien Date: Fri, 2 Dec 2016 09:22:34 +1300 Subject: mpc85xx: pcie: Implement workaround for Erratum A007815 The read-only-write-enable bit is set by default and must be cleared to prevent overwriting read-only registers. This should be done immediately after resetting the PCI Express controller. Reviewed-by: Hamish Martin Signed-off-by: Tony O'Brien [York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig] Reviewed-by: York Sun diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index b0f34b6..615d7e1 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -831,6 +831,7 @@ config ARCH_T2080 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007186 select SYS_FSL_ERRATUM_A007212 + select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 @@ -893,6 +894,7 @@ config ARCH_T4240 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007186 select SYS_FSL_ERRATUM_A007798 + select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 @@ -1081,6 +1083,9 @@ config SYS_FSL_ERRATUM_A007186 config SYS_FSL_ERRATUM_A007212 bool +config SYS_FSL_ERRATUM_A007815 + bool + config SYS_FSL_ERRATUM_A007798 bool diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 822ae72..b8be596 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -333,6 +333,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A007907 puts("Work-around for Erratum A007907 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + puts("Work-around for Erratum A007815 enabled\n"); +#endif + return 0; } diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 8bee8ca..cad341e 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -79,7 +79,9 @@ typedef struct ccsr_pci { u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ u32 pm_command; /* 0x02c - PCIE PM Command register */ - char res4[3016]; /* (- #xbf8 #x30)3016 */ + char res3[2188]; /* (0x8bc - 0x30 = 2188) */ + u32 dbi_ro_wr_en; /* 0x8bc - DBI read only write enable reg */ + char res4[824]; /* (0xbf8 - 0x8c0 = 824) */ u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 52792dc..af20cf0 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -543,6 +543,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); } +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + /* The Read-Only Write Enable bit defaults to 1 instead of 0. + * Set to 0 to protect the read-only registers. + */ + clrbits_be32(&pci->dbi_ro_wr_en, 0x01); +#endif + /* Use generic setup_device to initialize standard pci regs, * but do not allocate any windows since any BAR found (such * as PCSRBAR) is not in this cpu's memory space. -- cgit v0.10.2 From 76866600f544f00928ee9b5b2799a091ea9b80a7 Mon Sep 17 00:00:00 2001 From: Tony O'Brien Date: Fri, 6 Jan 2017 17:29:45 +1300 Subject: powerpc: Enable flush and invalidate dcache by range for MPC85xx Commit ac337168a unified functions to flush and invalidate dcache by range. These two functions were no-ops for SoCs other than 4xx and MPC86xx. Adding these functions seemed to be correct but introduced issues in some drivers when the dcache was flushed. While the root cause was under investigation, these functions were disabled in Commit cb1629f91a for affected SoCs, including the MPC85xx, to make the various drivers work. On the T208x USB stopped working after v2016.07 was pulled. After re-enabling the dcache functions for the MPC85xx it started working again. The USB and DPPA Ethernet drivers have been seen as operational after this change but other drivers cannot be tested. Reviewed-by: Chris Packham Signed-off-by: Tony O'Brien Cc: Marek Vasut Cc: York Sun Reviewed-by: York Sun diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S index 66cf02d..ad28c7c 100644 --- a/arch/powerpc/lib/ppccache.S +++ b/arch/powerpc/lib/ppccache.S @@ -65,7 +65,7 @@ ppcSync: * flush_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(flush_dcache_range) -#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 @@ -89,7 +89,7 @@ _GLOBAL(flush_dcache_range) * invalidate_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(invalidate_dcache_range) -#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 -- cgit v0.10.2