From 24936ed1c9a19ff855e00a37ee94ecf3941743ee Mon Sep 17 00:00:00 2001
From: Dave Liu <daveliu@freescale.com>
Date: Thu, 28 Nov 2013 14:58:08 +0800
Subject: powerpc/corenet: CPC1 speculation disable

In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
CPC1 speculation and keep it till relocation. Otherwise, speculation
transactions will go to DDR controller, it will cause problem.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 6a81fa7..db84d10 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -886,7 +886,11 @@ delete_ccsr_l2_tlb:
 	erratum_set_dcsr 0xb0008 0x00900000
 	erratum_set_dcsr 0xb0e40 0xe00a0000
 	erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+#ifdef  CONFIG_RAMBOOT_PBL
+	erratum_set_ccsr 0x10f00 0x495e5000
+#else
 	erratum_set_ccsr 0x10f00 0x415e5000
+#endif
 	erratum_set_ccsr 0x11f00 0x415e5000
 
 	/* Make temp mapping uncacheable again, if it was initially */
-- 
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