From 2290fe06421720d1c54523a9acf1052181bc6e87 Mon Sep 17 00:00:00 2001 From: Hannes Schmelzer Date: Wed, 22 Jun 2016 12:36:13 +0200 Subject: board/BuR: rename tseries board to brppt1 Rename B&R tseries board to brppt1 Signed-off-by: Hannes Schmelzer Reviewed-by: Tom Rini diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e9d2fc9..3c2c755 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -309,8 +309,8 @@ config TARGET_KWB select CPU_V7 select SUPPORT_SPL -config TARGET_TSERIES - bool "Support tseries" +config TARGET_BRPPT1 + bool "Support BRPPT1" select CPU_V7 select SUPPORT_SPL @@ -909,7 +909,7 @@ source "arch/arm/imx-common/Kconfig" source "board/bosch/shc/Kconfig" source "board/BuR/kwb/Kconfig" -source "board/BuR/tseries/Kconfig" +source "board/BuR/brppt1/Kconfig" source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" source "board/Marvell/gplugd/Kconfig" diff --git a/board/BuR/brppt1/Kconfig b/board/BuR/brppt1/Kconfig new file mode 100644 index 0000000..e006c80 --- /dev/null +++ b/board/BuR/brppt1/Kconfig @@ -0,0 +1,15 @@ +if TARGET_BRPPT1 + +config SYS_BOARD + default "brppt1" + +config SYS_VENDOR + default "BuR" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "brppt1" + +endif diff --git a/board/BuR/brppt1/MAINTAINERS b/board/BuR/brppt1/MAINTAINERS new file mode 100644 index 0000000..9eddab4 --- /dev/null +++ b/board/BuR/brppt1/MAINTAINERS @@ -0,0 +1,8 @@ +BRPPT1 BOARD +M: Hannes Schmelzer +S: Maintained +F: board/BuR/brppt1/ +F: include/configs/brppt1.h +F: configs/brppt1_mmc_defconfig +F: configs/brppt1_nand_defconfig +F: configs/brppt1_spi_defconfig diff --git a/board/BuR/brppt1/Makefile b/board/BuR/brppt1/Makefile new file mode 100644 index 0000000..43945d2 --- /dev/null +++ b/board/BuR/brppt1/Makefile @@ -0,0 +1,14 @@ +# +# Makefile +# +# Copyright (C) 2013 Hannes Schmelzer +# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SPL_BUILD),y) +obj-y := mux.o +endif +obj-y += ../common/common.o +obj-y += board.o diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c new file mode 100644 index 0000000..a227221 --- /dev/null +++ b/board/BuR/brppt1/board.c @@ -0,0 +1,174 @@ +/* + * board.c + * + * Board functions for B&R BRPPT1 + * + * Copyright (C) 2013 Hannes Schmelzer + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/bur_common.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* --------------------------------------------------------------------------*/ +/* -- defines for GPIO -- */ +#define REPSWITCH (0+20) /* GPIO0_20 */ + +#if defined(CONFIG_SPL_BUILD) +/* TODO: check ram-timing ! */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +static const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +#ifdef CONFIG_SPL_OS_BOOT +/* + * called from spl_nand.c + * return 0 for loading linux, return 1 for loading u-boot + */ +int spl_start_uboot(void) +{ + if (0 == gpio_get_value(REPSWITCH)) { + mdelay(1000); + printf("SPL: entering u-boot instead kernel image.\n"); + return 1; + } + return 0; +} +#endif /* CONFIG_SPL_OS_BOOT */ + +#define OSC (V_OSCK/1000000) +static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; + /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/ + struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; + + /* + * in TRM they write a reset value of 1 (=CLK_M_OSC) for the + * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set + * the source of timer6 clk to CLK_M_OSC + */ + writel(0x01, &cmdpll->clktimer6clk); + + /* enable additional clocks of modules which are accessed later */ + u32 *const clk_domains[] = { + &cmper->lcdcclkstctrl, + 0 + }; + + u32 *const clk_modules_tsspecific[] = { + &cmper->lcdclkctrl, + &cmper->timer5clkctrl, + &cmper->timer6clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_tsspecific, 1); + + /* setup LCD-Pixel Clock */ + writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */ + + /* setup I2C */ + enable_i2c_pin_mux(); + i2c_set_bus_num(0); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + pmicsetup(0); + + gpio_direction_output(64+29, 1); /* switch NAND_RnB to GPMC_WAIT1 */ + gpio_direction_output(64+28, 1); /* switch MII2_CRS to GPMC_WAIT0 */ +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr3; +} + +void sdram_init(void) +{ + config_ddr(400, &ddr3_ioregs, + &ddr3_data, + &ddr3_cmd_ctrl_data, + &ddr3_emif_reg_data, 0); +} +#endif /* CONFIG_SPL_BUILD */ + +/* Basic board specific setup. Pinmux has been handled already. */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#ifdef CONFIG_NAND + gpmc_init(); +#endif + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + if (0 == gpio_get_value(REPSWITCH)) { + lcd_position_cursor(1, 8); + lcd_puts( + "switching to network-console ... "); + setenv("bootcmd", "run netconsole"); + } + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/BuR/brppt1/mux.c b/board/BuR/brppt1/mux.c new file mode 100644 index 0000000..ab3788f --- /dev/null +++ b/board/BuR/brppt1/mux.c @@ -0,0 +1,254 @@ +/* + * mux.c + * + * Pinmux Setting for B&R BRPPT1 Board(s) + * + * Copyright (C) 2013 Hannes Schmelzer + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct module_pin_mux uart0_pin_mux[] = { + /* UART0_RTS */ + {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)}, + /* UART0_CTS */ + {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_RXD */ + {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_TXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; +static struct module_pin_mux uart1_pin_mux[] = { + /* UART1_RTS as I2C2-SCL */ + {OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART1_CTS as I2C2-SDA */ + {OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART1_RXD */ + {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART1_TXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; +#ifdef CONFIG_MMC +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ + {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ + {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ + {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ + + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ + {-1}, +}; +#endif +static struct module_pin_mux i2c0_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux spi0_pin_mux[] = { + /* SPI0_SCLK */ + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_D0 */ + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_D1 */ + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_CS0 */ + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */ + {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */ + {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */ + {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */ + {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */ + {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */ + {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */ + {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */ + {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */ + {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */ + {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */ + {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */ + {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */ + {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)}, + /* + * MII2_CRS is shared with + * NAND_WAIT0 + */ + {OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */ + {-1}, +}; +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; +#endif +static struct module_pin_mux gpIOs[] = { + /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */ + {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */ + {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)}, + /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */ + {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)}, + /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */ + {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */ + {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */ + {OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */ + {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */ + {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */ + {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */ + {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO2_0 (GPMC_nCS3) - DCOK */ + {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ + {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* + * GPIO0_7 (PWW0 OUT) + * DISPLAY_ONOFF (Backlight Enable at LVDS Versions) + */ + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */ + {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO0_20 (DMA_INTR1) - REP-Switch */ + {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)}, + /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */ + {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, + /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */ + {OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, + /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */ + {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) }, + /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */ + {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) }, +#ifndef CONFIG_NAND + /* GPIO2_3 - NAND_OE */ + {OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, + /* GPIO2_4 - NAND_WEN */ + {OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, + /* GPIO2_5 - NAND_BE_CLE */ + {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, +#endif + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ + + {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ + {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ + {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ + {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ + {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ + {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ + {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ + {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ + + {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ + {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ + {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ + {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ + + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mii2_pin_mux); +#ifdef CONFIG_NAND + configure_module_pin_mux(nand_pin_mux); +#elif defined(CONFIG_MMC) + configure_module_pin_mux(mmc1_pin_mux); +#endif + configure_module_pin_mux(spi0_pin_mux); + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(uart1_pin_mux); + configure_module_pin_mux(gpIOs); +} diff --git a/board/BuR/tseries/Kconfig b/board/BuR/tseries/Kconfig deleted file mode 100644 index ed48300..0000000 --- a/board/BuR/tseries/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_TSERIES - -config SYS_BOARD - default "tseries" - -config SYS_VENDOR - default "BuR" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "tseries" - -endif diff --git a/board/BuR/tseries/MAINTAINERS b/board/BuR/tseries/MAINTAINERS deleted file mode 100644 index e2e67e6..0000000 --- a/board/BuR/tseries/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -TSERIES BOARD -M: Hannes Schmelzer -S: Maintained -F: board/BuR/tseries/ -F: include/configs/tseries.h -F: configs/tseries_mmc_defconfig -F: configs/tseries_nand_defconfig -F: configs/tseries_spi_defconfig diff --git a/board/BuR/tseries/Makefile b/board/BuR/tseries/Makefile deleted file mode 100644 index 43945d2..0000000 --- a/board/BuR/tseries/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# Makefile -# -# Copyright (C) 2013 Hannes Schmelzer -# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifeq ($(CONFIG_SPL_BUILD),y) -obj-y := mux.o -endif -obj-y += ../common/common.o -obj-y += board.o diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c deleted file mode 100644 index bc119e6..0000000 --- a/board/BuR/tseries/board.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * board.c - * - * Board functions for B&R LEIT Board - * - * Copyright (C) 2013 Hannes Schmelzer - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com - * - * SPDX-License-Identifier: GPL-2.0+ - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/bur_common.h" -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* --------------------------------------------------------------------------*/ -/* -- defines for GPIO -- */ -#define REPSWITCH (0+20) /* GPIO0_20 */ - -#if defined(CONFIG_SPL_BUILD) -/* TODO: check ram-timing ! */ -static const struct ddr_data ddr3_data = { - .datardsratio0 = MT41K256M16HA125E_RD_DQS, - .datawdsratio0 = MT41K256M16HA125E_WR_DQS, - .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, - .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, -}; - -static const struct cmd_control ddr3_cmd_ctrl_data = { - .cmd0csratio = MT41K256M16HA125E_RATIO, - .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, - - .cmd1csratio = MT41K256M16HA125E_RATIO, - .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, - - .cmd2csratio = MT41K256M16HA125E_RATIO, - .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, -}; - -static struct emif_regs ddr3_emif_reg_data = { - .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, - .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, - .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, - .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, - .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, - .zq_config = MT41K256M16HA125E_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, -}; - -static const struct ctrl_ioregs ddr3_ioregs = { - .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, -}; - -#ifdef CONFIG_SPL_OS_BOOT -/* - * called from spl_nand.c - * return 0 for loading linux, return 1 for loading u-boot - */ -int spl_start_uboot(void) -{ - if (0 == gpio_get_value(REPSWITCH)) { - mdelay(1000); - printf("SPL: entering u-boot instead kernel image.\n"); - return 1; - } - return 0; -} -#endif /* CONFIG_SPL_OS_BOOT */ - -#define OSC (V_OSCK/1000000) -static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; - -void am33xx_spl_board_init(void) -{ - struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; - /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/ - struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; - - /* - * in TRM they write a reset value of 1 (=CLK_M_OSC) for the - * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set - * the source of timer6 clk to CLK_M_OSC - */ - writel(0x01, &cmdpll->clktimer6clk); - - /* enable additional clocks of modules which are accessed later */ - u32 *const clk_domains[] = { - &cmper->lcdcclkstctrl, - 0 - }; - - u32 *const clk_modules_tsspecific[] = { - &cmper->lcdclkctrl, - &cmper->timer5clkctrl, - &cmper->timer6clkctrl, - 0 - }; - do_enable_clocks(clk_domains, clk_modules_tsspecific, 1); - - /* setup LCD-Pixel Clock */ - writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */ - - /* setup I2C */ - enable_i2c_pin_mux(); - i2c_set_bus_num(0); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - pmicsetup(0); - - gpio_direction_output(64+29, 1); /* switch NAND_RnB to GPMC_WAIT1 */ - gpio_direction_output(64+28, 1); /* switch MII2_CRS to GPMC_WAIT0 */ -} - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr3; -} - -void sdram_init(void) -{ - config_ddr(400, &ddr3_ioregs, - &ddr3_data, - &ddr3_cmd_ctrl_data, - &ddr3_emif_reg_data, 0); -} -#endif /* CONFIG_SPL_BUILD */ - -/* Basic board specific setup. Pinmux has been handled already. */ -int board_init(void) -{ -#if defined(CONFIG_HW_WATCHDOG) - hw_watchdog_init(); -#endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -#ifdef CONFIG_NAND - gpmc_init(); -#endif - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - if (0 == gpio_get_value(REPSWITCH)) { - lcd_position_cursor(1, 8); - lcd_puts( - "switching to network-console ... "); - setenv("bootcmd", "run netconsole"); - } - return 0; -} -#endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c deleted file mode 100644 index 349788a..0000000 --- a/board/BuR/tseries/mux.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * mux.c - * - * Pinmux Setting for B&R LEIT Board(s) - * - * Copyright (C) 2013 Hannes Schmelzer - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -static struct module_pin_mux uart0_pin_mux[] = { - /* UART0_RTS */ - {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)}, - /* UART0_CTS */ - {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* UART0_RXD */ - {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* UART0_TXD */ - {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, - {-1}, -}; -static struct module_pin_mux uart1_pin_mux[] = { - /* UART1_RTS as I2C2-SCL */ - {OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* UART1_CTS as I2C2-SDA */ - {OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* UART1_RXD */ - {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* UART1_TXD */ - {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, - {-1}, -}; -#ifdef CONFIG_MMC -static struct module_pin_mux mmc1_pin_mux[] = { - {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ - {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ - {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ - {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ - - {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ - {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ - {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ - {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ - {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ - {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ - {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ - {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ - {-1}, -}; -#endif -static struct module_pin_mux i2c0_pin_mux[] = { - /* I2C_DATA */ - {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, - /* I2C_SCLK */ - {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, - {-1}, -}; - -static struct module_pin_mux spi0_pin_mux[] = { - /* SPI0_SCLK */ - {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, - /* SPI0_D0 */ - {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, - /* SPI0_D1 */ - {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, - /* SPI0_CS0 */ - {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, - {-1}, -}; - -static struct module_pin_mux mii1_pin_mux[] = { - {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ - {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ - {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ - {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ - {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ - {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ - {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ - {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ - {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ - {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ - {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ - {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ - {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ - {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ - {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ - {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ - {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ - {-1}, -}; - -static struct module_pin_mux mii2_pin_mux[] = { - {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */ - {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */ - {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */ - {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */ - {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */ - {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */ - {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */ - {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */ - {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */ - {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */ - {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */ - {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */ - {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */ - {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)}, - /* - * MII2_CRS is shared with - * NAND_WAIT0 - */ - {OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */ - {-1}, -}; -#ifdef CONFIG_NAND -static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ - {OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ - {-1}, -}; -#endif -static struct module_pin_mux gpIOs[] = { - /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */ - {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */ - {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)}, - /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */ - {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)}, - /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */ - {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)}, - /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */ - {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)}, - /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */ - {OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */ - {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */ - {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */ - {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */ - {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* GPIO2_0 (GPMC_nCS3) - DCOK */ - {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, - /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ - {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) }, - /* - * GPIO0_7 (PWW0 OUT) - * DISPLAY_ONOFF (Backlight Enable at LVDS Versions) - */ - {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)}, - /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */ - {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* GPIO0_20 (DMA_INTR1) - REP-Switch */ - {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)}, - /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */ - {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, - /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */ - {OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, - /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */ - {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) }, - /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */ - {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) }, -#ifndef CONFIG_NAND - /* GPIO2_3 - NAND_OE */ - {OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, - /* GPIO2_4 - NAND_WEN */ - {OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, - /* GPIO2_5 - NAND_BE_CLE */ - {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, -#endif - {-1}, -}; - -static struct module_pin_mux lcd_pin_mux[] = { - {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ - {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ - {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ - {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ - {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ - {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ - {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ - {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ - {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ - {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ - {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ - {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ - {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ - {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ - {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ - {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ - - {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ - {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ - {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ - {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ - {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ - {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ - {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ - {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ - - {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ - {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ - {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ - {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ - - {-1}, -}; - -void enable_uart0_pin_mux(void) -{ - configure_module_pin_mux(uart0_pin_mux); -} - -void enable_i2c_pin_mux(void) -{ - configure_module_pin_mux(i2c0_pin_mux); -} - -void enable_board_pin_mux(void) -{ - configure_module_pin_mux(i2c0_pin_mux); - configure_module_pin_mux(mii1_pin_mux); - configure_module_pin_mux(mii2_pin_mux); -#ifdef CONFIG_NAND - configure_module_pin_mux(nand_pin_mux); -#elif defined(CONFIG_MMC) - configure_module_pin_mux(mmc1_pin_mux); -#endif - configure_module_pin_mux(spi0_pin_mux); - configure_module_pin_mux(lcd_pin_mux); - configure_module_pin_mux(uart1_pin_mux); - configure_module_pin_mux(gpIOs); -} diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig new file mode 100644 index 0000000..f8d9de5 --- /dev/null +++ b/configs/brppt1_mmc_defconfig @@ -0,0 +1,37 @@ +CONFIG_ARM=y +CONFIG_TARGET_BRPPT1=y +CONFIG_SPL=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT" +CONFIG_BOOTDELAY=0 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_NETCONSOLE=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig new file mode 100644 index 0000000..85ddbe7 --- /dev/null +++ b/configs/brppt1_nand_defconfig @@ -0,0 +1,37 @@ +CONFIG_ARM=y +CONFIG_TARGET_BRPPT1=y +CONFIG_SPL=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND" +CONFIG_BOOTDELAY=0 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_NAND=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_NETCONSOLE=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig new file mode 100644 index 0000000..37b8bc9 --- /dev/null +++ b/configs/brppt1_spi_defconfig @@ -0,0 +1,42 @@ +CONFIG_ARM=y +CONFIG_TARGET_BRPPT1=y +CONFIG_SPL=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT" +CONFIG_BOOTDELAY=0 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_NETCONSOLE=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y diff --git a/configs/tseries_mmc_defconfig b/configs/tseries_mmc_defconfig deleted file mode 100644 index 337404b..0000000 --- a/configs/tseries_mmc_defconfig +++ /dev/null @@ -1,37 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_TSERIES=y -CONFIG_SPL=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT" -CONFIG_BOOTDELAY=0 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -# CONFIG_CMD_FPGA is not set -CONFIG_CMD_GPIO=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -# CONFIG_CMD_NFS is not set -CONFIG_CMD_PING=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_MUSB_HOST=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/tseries_nand_defconfig b/configs/tseries_nand_defconfig deleted file mode 100644 index 4dc0296..0000000 --- a/configs/tseries_nand_defconfig +++ /dev/null @@ -1,37 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_TSERIES=y -CONFIG_SPL=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND" -CONFIG_BOOTDELAY=0 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -# CONFIG_CMD_FPGA is not set -CONFIG_CMD_GPIO=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -# CONFIG_CMD_NFS is not set -CONFIG_CMD_PING=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_MUSB_HOST=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/tseries_spi_defconfig b/configs/tseries_spi_defconfig deleted file mode 100644 index 5b52bf6..0000000 --- a/configs/tseries_spi_defconfig +++ /dev/null @@ -1,42 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_TSERIES=y -CONFIG_SPL=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT" -CONFIG_BOOTDELAY=0 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -# CONFIG_CMD_FPGA is not set -CONFIG_CMD_GPIO=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -# CONFIG_CMD_NFS is not set -CONFIG_CMD_PING=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_NETCONSOLE=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_MUSB_HOST=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h new file mode 100644 index 0000000..6a239b5 --- /dev/null +++ b/include/configs/brppt1.h @@ -0,0 +1,304 @@ +/* + * brtpp1.h + * + * specific parts for B&R T-Series Motherboard + * + * Copyright (C) 2013 Hannes Schmelzer - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BRPPT1_H__ +#define __CONFIG_BRPPT1_H__ + +#include +#include +/* ------------------------------------------------------------------------- */ +#define CONFIG_AM335X_LCD +#define CONFIG_LCD +#define CONFIG_LCD_ROTATION +#define CONFIG_LCD_DT_SIMPLEFB +#define CONFIG_SYS_WHITE_ON_BLACK +#define LCD_BPP LCD_COLOR32 + +#define CONFIG_HW_WATCHDOG +#define CONFIG_OMAP_WATCHDOG +#define CONFIG_SPL_WATCHDOG_SUPPORT + +#define CONFIG_SPL_GPIO_SUPPORT +/* Bootcount using the RTC block */ +#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000 +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_BOOTCOUNT_AM33XX + +/* memory */ +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_POWER_TPS65217 + +/* Support both device trees and ATAGs. */ +#define CONFIG_USE_FDT /* use fdt within board code */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +/*#define CONFIG_MACH_TYPE 3589*/ +#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/ + +/* MMC/SD IP block */ +#if defined(CONFIG_EMMC_BOOT) + #define CONFIG_MMC + #define CONFIG_GENERIC_MMC + #define CONFIG_OMAP_HSMMC + #define CONFIG_SUPPORT_EMMC_BOOT +/* RAW SD card / eMMC locations. */ + #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */ + #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ + #define CONFIG_SPL_MMC_SUPPORT +#endif /* CONFIG_EMMC_BOOT */ + +/* + * When we have SPI or NAND flash we expect to be making use of mtdparts, + * both for ease of use in U-Boot and for passing information on to + * the Linux kernel. + */ +#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND) +#define CONFIG_MTD_DEVICE /* Required for mtdparts */ +#define CONFIG_CMD_MTDPARTS +#endif /* CONFIG_SPI_BOOT, ... */ + +#undef CONFIG_SPL_OS_BOOT +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 + +/* RAW SD card / eMMC */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ + +/* NAND */ +#ifdef CONFIG_NAND +#define CONFIG_CMD_SPL_NAND_OFS 0x080000 /* end of u-boot */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif /* CONFIG_NAND */ +#endif /* CONFIG_SPL_OS_BOOT */ + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_AM33XX_BCH /* OMAP4 and later ELM support */ +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#endif /* CONFIG_NAND */ + +/* Always 64 KiB env size */ +#define CONFIG_ENV_SIZE (64 << 10) + +#ifdef CONFIG_NAND +#define NANDARGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "${optargs_rot} " \ + "root=mtd6 " \ + "rootfstype=jffs2\0" \ + "kernelsize=0x400000\0" \ + "nandboot=echo booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} kernel ${kernelsize}; " \ + "bootz ${loadaddr} - ${dtbaddr}\0" \ + "defboot=run nandboot\0" \ + "bootlimit=1\0" \ + "simplefb=1\0 " \ + "altbootcmd=run usbscript\0" +#else +#define NANDARGS "" +#endif /* CONFIG_NAND */ + +#ifdef CONFIG_MMC +#define MMCARGS \ +"dtbdev=mmc\0" \ +"dtbpart=0:1\0" \ +"mmcroot0=setenv bootargs ${optargs_rot} ${optargs} console=${console}\0" \ +"mmcroot1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \ + "root=/dev/mmcblk0p2 rootfstype=ext4\0" \ +"mmcboot0=echo booting Updatesystem from mmc (ext4-fs) ...; " \ + "setenv simplefb 1; " \ + "ext4load mmc 0:1 ${loadaddr} /${kernel}; " \ + "ext4load mmc 0:1 ${ramaddr} /${ramdisk}; " \ + "run mmcroot0; bootz ${loadaddr} ${ramaddr} ${dtbaddr};\0" \ +"mmcboot1=echo booting PPT-OS from mmc (ext4-fs) ...; " \ + "setenv simplefb 0; " \ + "ext4load mmc 0:2 ${loadaddr} /boot/${kernel}; " \ + "run mmcroot1; bootz ${loadaddr} - ${dtbaddr};\0" \ +"defboot=ext4load mmc 0:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \ + "ext4load mmc 0:1 ${dtbaddr} /$dtb && run mmcboot0; " \ + "run ramboot; run usbscript;\0" \ +"bootlimit=1\0" \ +"altbootcmd=run mmcboot0;\0" \ +"upduboot=dhcp; " \ + "tftp ${loadaddr} MLO && mmc write ${loadaddr} 100 100; " \ + "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 400;\0" +#else +#define MMCARGS "" +#endif /* CONFIG_MMC */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ +BUR_COMMON_ENV \ +"verify=no\0" \ +"autoload=0\0" \ +"dtb=bur-ppt-ts30.dtb\0" \ +"dtbaddr=0x80100000\0" \ +"loadaddr=0x80200000\0" \ +"ramaddr=0x80A00000\0" \ +"kernel=zImage\0" \ +"ramdisk=rootfs.cpio.uboot\0" \ +"console=ttyO0,115200n8\0" \ +"optargs=consoleblank=0 quiet panic=2\0" \ +"nfsroot=/tftpboot/tseries/rootfs-small\0" \ +"nfsopts=nolock\0" \ +"ramargs=setenv bootargs ${optargs} console=${console} root=/dev/ram0\0" \ +"netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${nfsroot},${nfsopts} rw " \ + "ip=dhcp\0" \ +"netboot=echo Booting from network ...; " \ + "dhcp; " \ + "tftp ${loadaddr} ${kernel}; " \ + "tftp ${dtbaddr} ${dtb}; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${dtbaddr}\0" \ +"ramboot=echo Booting from network into RAM ...; "\ + "if dhcp; then; " \ + "tftp ${loadaddr} ${kernel}; " \ + "tftp ${ramaddr} ${ramdisk}; " \ + "if ext4load ${dtbdev} ${dtbpart} ${dtbaddr} /${dtb}; " \ + "then; else tftp ${dtbaddr} ${dtb}; fi;" \ + "run mmcroot0; " \ + "bootz ${loadaddr} ${ramaddr} ${dtbaddr}; fi;\0" \ +"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \ + "setenv autoload 0; " \ + "dhcp && tftp 0x80000000 updateUBOOT.img && source;\0" \ +NANDARGS \ +MMCARGS +#endif /* !CONFIG_SPL_BUILD*/ + +#define CONFIG_BOOTCOMMAND \ + "run defboot;" + +#ifdef CONFIG_NAND +/* + * GPMC block. We support 1 device and the physical address to + * access CS0 at is 0x8000000. + */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x8000000 +#define CONFIG_NAND_OMAP_GPMC +/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ + "128k(MLO)," \ + "128k(MLO.backup)," \ + "128k(dtb)," \ + "128k(u-boot-env)," \ + "512k(u-boot)," \ + "4m(kernel),"\ + "128m(rootfs),"\ + "-(user)" +#define CONFIG_NAND_OMAP_GPMC_WSCFG 1 +#endif /* CONFIG_NAND */ + +/* USB configuration */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_USB_MUSB_PIO_ONLY +#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_HOST +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#if defined(CONFIG_SPI_BOOT) +/* McSPI IP block */ +#define CONFIG_SPI +#define CONFIG_OMAP3_SPI +#define CONFIG_SF_DEFAULT_SPEED 24000000 + +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ +#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ + +#elif defined(CONFIG_EMMC_BOOT) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#elif defined(CONFIG_NAND) +/* No NAND env support in SPL */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_ENV_IS_NOWHERE +#else +#define CONFIG_ENV_IS_IN_NAND +#endif +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE +#else +#error "no storage for Environment defined!" +#endif +/* + * Common filesystems support. When we have removable storage we + * enabled a number of useful commands and support. + */ +#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE) +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_FS_EXT4 +#define CONFIG_EXT4_WRITE +#endif /* CONFIG_MMC, ... */ + +#endif /* ! __CONFIG_BRPPT1_H__ */ diff --git a/include/configs/tseries.h b/include/configs/tseries.h deleted file mode 100644 index 8ed9eb0..0000000 --- a/include/configs/tseries.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - * tseries.h - * - * specific parts for B&R T-Series Motherboard - * - * Copyright (C) 2013 Hannes Schmelzer - - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_TSERIES_H__ -#define __CONFIG_TSERIES_H__ - -#include -#include -/* ------------------------------------------------------------------------- */ -#define CONFIG_AM335X_LCD -#define CONFIG_LCD -#define CONFIG_LCD_ROTATION -#define CONFIG_LCD_DT_SIMPLEFB -#define CONFIG_SYS_WHITE_ON_BLACK -#define LCD_BPP LCD_COLOR32 - -#define CONFIG_HW_WATCHDOG -#define CONFIG_OMAP_WATCHDOG -#define CONFIG_SPL_WATCHDOG_SUPPORT - -#define CONFIG_SPL_GPIO_SUPPORT -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000 -#define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_BOOTCOUNT_AM33XX - -/* memory */ -#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define CONFIG_POWER_TPS65217 - -/* Support both device trees and ATAGs. */ -#define CONFIG_USE_FDT /* use fdt within board code */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -/*#define CONFIG_MACH_TYPE 3589*/ -#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/ - -/* MMC/SD IP block */ -#if defined(CONFIG_EMMC_BOOT) - #define CONFIG_MMC - #define CONFIG_GENERIC_MMC - #define CONFIG_OMAP_HSMMC - #define CONFIG_SUPPORT_EMMC_BOOT -/* RAW SD card / eMMC locations. */ - #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */ - #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ - #define CONFIG_SPL_MMC_SUPPORT -#endif /* CONFIG_EMMC_BOOT */ - -/* - * When we have SPI or NAND flash we expect to be making use of mtdparts, - * both for ease of use in U-Boot and for passing information on to - * the Linux kernel. - */ -#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND) -#define CONFIG_MTD_DEVICE /* Required for mtdparts */ -#define CONFIG_CMD_MTDPARTS -#endif /* CONFIG_SPI_BOOT, ... */ - -#undef CONFIG_SPL_OS_BOOT -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 - -/* RAW SD card / eMMC */ -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ - -/* NAND */ -#ifdef CONFIG_NAND -#define CONFIG_CMD_SPL_NAND_OFS 0x080000 /* end of u-boot */ -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000 -#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 -#endif /* CONFIG_NAND */ -#endif /* CONFIG_SPL_OS_BOOT */ - -#ifdef CONFIG_NAND -#define CONFIG_SPL_NAND_AM33XX_BCH /* OMAP4 and later ELM support */ -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -#endif /* CONFIG_NAND */ - -/* Always 64 KiB env size */ -#define CONFIG_ENV_SIZE (64 << 10) - -#ifdef CONFIG_NAND -#define NANDARGS \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "${optargs_rot} " \ - "root=mtd6 " \ - "rootfstype=jffs2\0" \ - "kernelsize=0x400000\0" \ - "nandboot=echo booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} kernel ${kernelsize}; " \ - "bootz ${loadaddr} - ${dtbaddr}\0" \ - "defboot=run nandboot\0" \ - "bootlimit=1\0" \ - "simplefb=1\0 " \ - "altbootcmd=run usbscript\0" -#else -#define NANDARGS "" -#endif /* CONFIG_NAND */ - -#ifdef CONFIG_MMC -#define MMCARGS \ -"dtbdev=mmc\0" \ -"dtbpart=0:1\0" \ -"mmcroot0=setenv bootargs ${optargs_rot} ${optargs} console=${console}\0" \ -"mmcroot1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \ - "root=/dev/mmcblk0p2 rootfstype=ext4\0" \ -"mmcboot0=echo booting Updatesystem from mmc (ext4-fs) ...; " \ - "setenv simplefb 1; " \ - "ext4load mmc 0:1 ${loadaddr} /${kernel}; " \ - "ext4load mmc 0:1 ${ramaddr} /${ramdisk}; " \ - "run mmcroot0; bootz ${loadaddr} ${ramaddr} ${dtbaddr};\0" \ -"mmcboot1=echo booting PPT-OS from mmc (ext4-fs) ...; " \ - "setenv simplefb 0; " \ - "ext4load mmc 0:2 ${loadaddr} /boot/${kernel}; " \ - "run mmcroot1; bootz ${loadaddr} - ${dtbaddr};\0" \ -"defboot=ext4load mmc 0:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \ - "ext4load mmc 0:1 ${dtbaddr} /$dtb && run mmcboot0; " \ - "run ramboot; run usbscript;\0" \ -"bootlimit=1\0" \ -"altbootcmd=run mmcboot0;\0" \ -"upduboot=dhcp; " \ - "tftp ${loadaddr} MLO && mmc write ${loadaddr} 100 100; " \ - "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 400;\0" -#else -#define MMCARGS "" -#endif /* CONFIG_MMC */ - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ -BUR_COMMON_ENV \ -"verify=no\0" \ -"autoload=0\0" \ -"dtb=bur-ppt-ts30.dtb\0" \ -"dtbaddr=0x80100000\0" \ -"loadaddr=0x80200000\0" \ -"ramaddr=0x80A00000\0" \ -"kernel=zImage\0" \ -"ramdisk=rootfs.cpio.uboot\0" \ -"console=ttyO0,115200n8\0" \ -"optargs=consoleblank=0 quiet panic=2\0" \ -"nfsroot=/tftpboot/tseries/rootfs-small\0" \ -"nfsopts=nolock\0" \ -"ramargs=setenv bootargs ${optargs} console=${console} root=/dev/ram0\0" \ -"netargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=/dev/nfs " \ - "nfsroot=${serverip}:${nfsroot},${nfsopts} rw " \ - "ip=dhcp\0" \ -"netboot=echo Booting from network ...; " \ - "dhcp; " \ - "tftp ${loadaddr} ${kernel}; " \ - "tftp ${dtbaddr} ${dtb}; " \ - "run netargs; " \ - "bootz ${loadaddr} - ${dtbaddr}\0" \ -"ramboot=echo Booting from network into RAM ...; "\ - "if dhcp; then; " \ - "tftp ${loadaddr} ${kernel}; " \ - "tftp ${ramaddr} ${ramdisk}; " \ - "if ext4load ${dtbdev} ${dtbpart} ${dtbaddr} /${dtb}; " \ - "then; else tftp ${dtbaddr} ${dtb}; fi;" \ - "run mmcroot0; " \ - "bootz ${loadaddr} ${ramaddr} ${dtbaddr}; fi;\0" \ -"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \ - "setenv autoload 0; " \ - "dhcp && tftp 0x80000000 updateUBOOT.img && source;\0" \ -NANDARGS \ -MMCARGS -#endif /* !CONFIG_SPL_BUILD*/ - -#define CONFIG_BOOTCOMMAND \ - "run defboot;" - -#ifdef CONFIG_NAND -/* - * GPMC block. We support 1 device and the physical address to - * access CS0 at is 0x8000000. - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x8000000 -#define CONFIG_NAND_OMAP_GPMC -/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ -#define CONFIG_NAND_OMAP_ELM -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -#define MTDIDS_DEFAULT "nand0=omap2-nand.0" -#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ - "128k(MLO)," \ - "128k(MLO.backup)," \ - "128k(dtb)," \ - "128k(u-boot-env)," \ - "512k(u-boot)," \ - "4m(kernel),"\ - "128m(rootfs),"\ - "-(user)" -#define CONFIG_NAND_OMAP_GPMC_WSCFG 1 -#endif /* CONFIG_NAND */ - -/* USB configuration */ -#define CONFIG_USB_MUSB_DSPS -#define CONFIG_ARCH_MISC_INIT -#define CONFIG_USB_MUSB_PIO_ONLY -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT -#define CONFIG_AM335X_USB0 -#define CONFIG_AM335X_USB0_MODE MUSB_HOST -#define CONFIG_AM335X_USB1 -#define CONFIG_AM335X_USB1_MODE MUSB_HOST - -#if defined(CONFIG_SPI_BOOT) -/* McSPI IP block */ -#define CONFIG_SPI -#define CONFIG_OMAP3_SPI -#define CONFIG_SF_DEFAULT_SPEED 24000000 - -#define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SPL_SPI_FLASH_SUPPORT -#define CONFIG_SPL_SPI_LOAD -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 -#undef CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED -#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ -#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ -#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ - -#elif defined(CONFIG_EMMC_BOOT) -#undef CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 -#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - -#elif defined(CONFIG_NAND) -/* No NAND env support in SPL */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_ENV_IS_NOWHERE -#else -#define CONFIG_ENV_IS_IN_NAND -#endif -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE -#else -#error "no storage for Environment defined!" -#endif -/* - * Common filesystems support. When we have removable storage we - * enabled a number of useful commands and support. - */ -#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE) -#define CONFIG_DOS_PARTITION -#define CONFIG_FAT_WRITE -#define CONFIG_FS_EXT4 -#define CONFIG_EXT4_WRITE -#endif /* CONFIG_MMC, ... */ - -#endif /* ! __CONFIG_TSERIES_H__ */ -- cgit v0.10.2