From 3cd42180a8f691c68d88b9ef428054348c2f0432 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 12 Dec 2016 09:46:09 +0100 Subject: lib: Add WATCHDOG_RESET to wait_bit.h wait_for_bit() is missing reset watchdog in case watchdog is configured. Signed-off-by: Michal Simek Reviewed-by: Tom Rini diff --git a/include/wait_bit.h b/include/wait_bit.h index 066e30c..06ad43a 100644 --- a/include/wait_bit.h +++ b/include/wait_bit.h @@ -11,6 +11,7 @@ #include #include +#include #include #include @@ -59,6 +60,7 @@ static inline int wait_for_bit(const char *prefix, const u32 *reg, } udelay(1); + WATCHDOG_RESET(); } debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", prefix, reg, mask, -- cgit v0.10.2 From b908fcad841a97025dd8c2a79bc53b15b386f292 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 12 Dec 2016 09:47:26 +0100 Subject: net: gem: Use wait_for_bit() instead of private mdio_wait() Using generic wait_for_bit() implementation instead of using private wait function. Signed-off-by: Michal Simek diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index d2e5e7c..95b4d6e 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -183,33 +183,17 @@ struct zynq_gem_priv { struct mii_dev *bus; }; -static inline int mdio_wait(struct zynq_gem_regs *regs) -{ - u32 timeout = 20000; - - /* Wait till MDIO interface is ready to accept a new transaction. */ - while (--timeout) { - if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) - break; - WATCHDOG_RESET(); - } - - if (!timeout) { - printf("%s: Timeout\n", __func__); - return 1; - } - - return 0; -} - static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, u32 op, u16 *data) { u32 mgtcr; struct zynq_gem_regs *regs = priv->iobase; + int err; - if (mdio_wait(regs)) - return 1; + err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, + true, 20000, true); + if (err) + return err; /* Construct mgtcr mask for the operation */ mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | @@ -219,8 +203,10 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, /* Write mgtcr and wait for completion */ writel(mgtcr, ®s->phymntnc); - if (mdio_wait(regs)) - return 1; + err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, + true, 20000, true); + if (err) + return err; if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) *data = readl(®s->phymntnc); -- cgit v0.10.2 From 36458cef1b9b5c06e20eb9ed9c213b7171a63e52 Mon Sep 17 00:00:00 2001 From: Sai Pavan Boddu Date: Tue, 16 Aug 2016 17:12:05 +0530 Subject: microblaze: Make the board configuration name user definable Add a prompt for editing in menuconfig Signed-off-by: Sai Pavan Boddu Signed-off-by: Michal Simek diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig index 02ac65c..6e93a3d 100644 --- a/board/xilinx/microblaze-generic/Kconfig +++ b/board/xilinx/microblaze-generic/Kconfig @@ -7,7 +7,12 @@ config SYS_VENDOR default "xilinx" config SYS_CONFIG_NAME + string "Board configuration name" default "microblaze-generic" + help + This option contains information about board configuration name. + Based on this option include/configs/.h header + will be used for board configuration. config XILINX_MICROBLAZE0_USE_MSR_INSTR int "USE_MSR_INSTR range (0:1)" -- cgit v0.10.2 From a9fb35a8db0bdb8e67f4efbe95f1b8b4d275ba1b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 16 Dec 2016 09:12:10 +0100 Subject: microblaze: Remove hardcoded IP address from config IP addresses shouldn't be hardcoded in board config. This patch removes them. Signed-off-by: Michal Simek diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 7abffdb..6b380f0 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -235,9 +235,6 @@ #define CONFIG_BOOTARGS "root=romfs" #define CONFIG_HOSTNAME XILINX_BOARD_NAME #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" -#define CONFIG_IPADDR 192.168.0.3 -#define CONFIG_SERVERIP 192.168.0.5 -#define CONFIG_GATEWAYIP 192.168.0.1 /* architecture dependent code */ #define CONFIG_SYS_USR_EXCEP /* user exception */ -- cgit v0.10.2 From 2902a9b7a932ada96d74f56eb765f5260ced4888 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 May 2016 13:11:19 +0200 Subject: microblaze: Enable option to overwrite default variables Enable overwriting variables out of main config file. Signed-off-by: Michal Simek diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 6b380f0..36b0a0e 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -241,6 +241,7 @@ #define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" +#ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ "nor0=flash-0\0"\ "mtdparts=mtdparts=flash-0:"\ @@ -250,6 +251,7 @@ "setenv stdin nc\0" \ "serial=setenv stdout serial;"\ "setenv stdin serial\0" +#endif #define CONFIG_CMDLINE_EDITING -- cgit v0.10.2 From 936b03849678f727eae2cf0da91e61d856411501 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 18 Nov 2016 10:27:47 +0530 Subject: ARM64: zynqmp: Increase environment size to 32K Increase environment size to 32K as the current default environment itself is greater than 4K. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 74cbfcf..61cd147 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -133,7 +133,7 @@ /* Do not preserve environment */ #define CONFIG_ENV_IS_NOWHERE 1 -#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SIZE 0x8000 /* Monitor Command Prompt */ /* Console I/O Buffer Size */ -- cgit v0.10.2 From 6f09d3433854571a918d8494758ecf89433dca19 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 18 Nov 2016 10:27:48 +0530 Subject: ARM64: zynqmp: Add support to save env to FAT Add support to save environment as a file of FAT filesystem on to SD card. The file will be saved with name uEnv.txt. This environment will be retrieved during boot. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 61cd147..e0343a3 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -86,6 +86,10 @@ # ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ # define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000 # endif +# define CONFIG_ENV_IS_IN_FAT +# define FAT_ENV_DEVICE_AND_PART "0:auto" +# define FAT_ENV_FILE "uboot.env" +# define FAT_ENV_INTERFACE "mmc" #endif #if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQMP_USB) @@ -132,7 +136,9 @@ #define CONFIG_BOARD_LATE_INIT /* Do not preserve environment */ +#if !defined(CONFIG_ENV_IS_IN_FAT) #define CONFIG_ENV_IS_NOWHERE 1 +#endif #define CONFIG_ENV_SIZE 0x8000 /* Monitor Command Prompt */ -- cgit v0.10.2 From 3d4eb334ecdfec467ecbb7fbd826c3cb397a8ac3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 16 Dec 2016 10:01:45 +0100 Subject: fpga: zynqmp: Remove empty functions Xilinx core files will take care about it. There is no need to have these functions because they do nothing. Signed-off-by: Michal Simek diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index ef889ea..2ff716c 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -38,11 +38,6 @@ #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ #endif -static int zynq_info(xilinx_desc *desc) -{ - return FPGA_SUCCESS; -} - #define DUMMY_WORD 0xffffffff /* Xilinx binary format header */ @@ -481,16 +476,9 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, } #endif -static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) -{ - return FPGA_FAIL; -} - struct xilinx_fpga_op zynq_op = { .load = zynq_load, #if defined(CONFIG_CMD_FPGA_LOADFS) .loadfs = zynq_loadfs, #endif - .dump = zynq_dump, - .info = zynq_info, }; -- cgit v0.10.2 From 6ebf8a4a9d9f77694d3e80a63040a274d16ee098 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 16 Dec 2016 11:57:17 +0100 Subject: ARM: zynq: Move CONFIG_SYS_TEXT_BASE to Kconfig Enable CONFIG_SYS_TEXT_BASE via Kconfig. Signed-off-by: Michal Simek diff --git a/Kconfig b/Kconfig index a44ac91..1fa791c 100644 --- a/Kconfig +++ b/Kconfig @@ -248,7 +248,8 @@ config SYS_EXTRA_OPTIONS config SYS_TEXT_BASE depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \ - (M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS + (M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS || \ + ARCH_ZYNQ depends on !EFI_APP hex "Text Base" help diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index e7b6c0f..3239d99 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="topic" CONFIG_SYS_CONFIG_NAME="topic_miami" CONFIG_ARCH_ZYNQ=y CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt" +CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami" CONFIG_BOOTDELAY=0 CONFIG_SYS_NO_FLASH=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 2141949e..906220c 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="topic" CONFIG_SYS_CONFIG_NAME="topic_miamiplus" CONFIG_ARCH_ZYNQ=y CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt" +CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus" CONFIG_BOOTDELAY=0 CONFIG_SYS_NO_FLASH=y diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 7ec5752..361e3b9 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index d8c76a7..529a9ad 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed" CONFIG_SYS_NO_FLASH=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 4c65231..04e60e8 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="zynq_zc70x" CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 935a9c9..7c2040c 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="zynq_zc70x" CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 16a14ae..a11010c 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 247fb6d..ae7a631 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y # CONFIG_MMC is not set +CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 8e80a90..c01faaa 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y # CONFIG_MMC is not set +CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index 286f0bd..573fc14 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y # CONFIG_MMC is not set +CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 6f8f3a6..25f03b6 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-zed" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 6706324..b69fd2f 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="zynq_zybo" CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 2fe6897..ae87d17 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -247,9 +247,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* Physical Memory map */ -#define CONFIG_SYS_TEXT_BASE 0x4000000 - #ifndef CONFIG_NR_DRAM_BANKS # define CONFIG_NR_DRAM_BANKS 1 #endif -- cgit v0.10.2 From c1d7f29b62021d42c02f56b7ba469009afa3e734 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 27 Jul 2016 14:44:30 +0200 Subject: ARM: zynq: Remove CONFIG_BOOTP_SERVERIP Do the same change which was done in ZynqMP by: "ARM64: zynqmp: Remove CONFIG_BOOTP_SERVERIP" (sha1: a8b6a156c0f7fb99502229e454bc9c3b38645280) Signed-off-by: Michal Simek diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index ae87d17..fd74e80 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -43,7 +43,6 @@ # define CONFIG_PHY_MARVELL # define CONFIG_PHY_REALTEK # define CONFIG_PHY_XILINX -# define CONFIG_BOOTP_SERVERIP # define CONFIG_BOOTP_BOOTPATH # define CONFIG_BOOTP_GATEWAY # define CONFIG_BOOTP_HOSTNAME -- cgit v0.10.2 From 5af46ca71a85c6eb678fd4a06e004e203e31e2be Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 21 Nov 2016 10:43:37 +0100 Subject: ARM: zynq: Remove spi-max-frequency spi-max-frequency for spi bus depends on devices which are connected to it. Remove this parameter from dtsi file. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 668f54e..fa9ee27 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -177,7 +177,6 @@ interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; - spi-max-frequency = <166666700>; #address-cells = <1>; #size-cells = <0>; }; @@ -190,7 +189,6 @@ interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; - spi-max-frequency = <166666700>; #address-cells = <1>; #size-cells = <0>; }; -- cgit v0.10.2 From 085b2b82874f96cd644940754449ce0319f9f043 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 16 Dec 2016 13:16:14 +0100 Subject: ARM: zynq: Setup modeboot variable based on boot mode modeboot variable is used for saving inforation which bootmode is used. Signed-off-by: Michal Simek diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 5cd9bbf..6a3cbe0 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -85,6 +85,12 @@ int board_init(void) int board_late_init(void) { switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { + case ZYNQ_BM_QSPI: + setenv("modeboot", "qspiboot"); + break; + case ZYNQ_BM_NAND: + setenv("modeboot", "nandboot"); + break; case ZYNQ_BM_NOR: setenv("modeboot", "norboot"); break; -- cgit v0.10.2 From a930ca572a142dfccd8dc47286cf8b74e269e017 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Wed, 21 Oct 2015 11:10:16 +0100 Subject: ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Though the keyboard driver for GPIO buttons(gpio-keys) will continue to check for/support the legacy "gpio-key,wakeup" boolean property to enable gpio buttons as wakeup source, "wakeup-source" is the new standard binding. This patch replaces the legacy "gpio-key,wakeup" with the unified "wakeup-source" property in order to avoid any futher copy-paste duplication. Cc: Michal Simek Cc: "Sören Brinkmann" Signed-off-by: Sudeep Holla Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 478e9fd..2696e70 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -40,14 +40,14 @@ label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ - gpio-key,wakeup; + wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; -- cgit v0.10.2 From 14de6c4ea1cad7fca8bc545c4f58b7686927910c Mon Sep 17 00:00:00 2001 From: Shubhrajyoti Datta Date: Fri, 21 Oct 2016 16:12:19 +0530 Subject: ARM64: zynqmp: clk: Add the clock for watchdog The watchdog clock node is missing. Add the same. This solves the below error. cdns-wdt fd4d0000.watchdog: input clock not found cdns-wdt: probe of fd4d0000.watchdog failed with error -2 Signed-off-by: Shubhrajyoti Datta Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi index aa848c8..b64a0a6 100644 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -218,6 +218,10 @@ clocks = <&clk250>, <&clk250>; }; +&watchdog0 { + clocks = <&clk250>; +}; + &xilinx_drm { clocks = <&drm_clock>; }; -- cgit v0.10.2 From 7876dcb5d46057403a715771a75c483add6a64c1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 16 Dec 2016 13:08:55 +0100 Subject: ARM64: zynqmp: Add missing earlycon for ep108 Just sync between version. Others zynqmp boards have this setup. Signed-off-by: Michal Simek Reviewed-by: Simon Glass diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index 2483180..9f6b111 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -28,6 +28,7 @@ }; chosen { + bootargs = "earlycon"; stdout-path = "serial0:115200n8"; }; -- cgit v0.10.2 From 8925e5996db05abca28ad2858e011f3b45724d5a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 5 Apr 2016 12:01:16 +0200 Subject: ARM64: zynqmp: Fix usb nodes for dc1 and dc2 Fix DT binding for usb nodes. Setup correct aliases and enable dwc3 nodes. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index b3f4297..c2a26c1 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -176,6 +176,10 @@ /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; +}; + +&dwc3_0 { + status = "okay"; dr_mode = "host"; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 09a114b..32847e1 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -224,6 +224,10 @@ /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; +}; + +&dwc3_1 { + status = "okay"; dr_mode = "host"; }; -- cgit v0.10.2 From 2e15b071a21ae1fbbf8bf22ab8757cce79d036d5 Mon Sep 17 00:00:00 2001 From: Stefan Krsmanovic Date: Fri, 21 Oct 2016 12:44:56 +0200 Subject: ARM64: zynqmp: Add idle state for ZynqMP Added the idle-states node to describe zynqmp idle states. Only cpu-sleep-0 idle state is added in this patch. References to the idle-states node are added in all CPU nodes. Time values: entry/exit latencies and min-residency, needs to be tuned. arm,psci-suspend-param is selected to comply with PSCIv1.0 and Extended StateID format. Signed-off-by: Stefan Krsmanovic Acked-by: Will Wong Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index de1f160..e2e76d7 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -22,6 +22,7 @@ device_type = "cpu"; enable-method = "psci"; reg = <0x0>; + cpu-idle-states = <&CPU_SLEEP_0>; }; cpu@1 { @@ -29,6 +30,7 @@ device_type = "cpu"; enable-method = "psci"; reg = <0x1>; + cpu-idle-states = <&CPU_SLEEP_0>; }; cpu@2 { @@ -36,6 +38,7 @@ device_type = "cpu"; enable-method = "psci"; reg = <0x2>; + cpu-idle-states = <&CPU_SLEEP_0>; }; cpu@3 { @@ -43,6 +46,20 @@ device_type = "cpu"; enable-method = "psci"; reg = <0x3>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + + idle-states { + entry-mehod = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <600>; + min-residency-us = <800000>; + }; }; }; -- cgit v0.10.2 From 5ce987feb35202bc21b36afdce4eb4bf95cf7a66 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 12 May 2016 10:54:41 +0530 Subject: ARM64: zynqmp: Enable fastboot for first SD/MMC/EMMC device DNL numbers are not changed that's why fastboot needs to be called with -i parameter (Xilinx vendor id). - Show available devices sudo fastboot -i 0x03fd devices xilinx_zynqmp_zcu100 fastboot - Stop fastboot and go back to U-Boot prompt sudo fastboot -i 0x03fd continue - Reboot the board sudo fastboot -i 0x03fd reboot - Get internal variables sudo fastboot -i 0x3fd getvar bootloader-version bootloader-version: U-Boot 2016.07-00026-g19bd53044817 sudo fastboot -i 0x3fd getvar downloadsize downloadsize: 0x06000000 sudo fastboot -i 0x3fd getvar version version: 0.4 (regular variables needs to have fastboot. prefix - there is also serialno variable which should be define as serial#) - Format SD/MMC/EMMC card sudo fastboot -i 0x3fd oem format - Write images to boot and Linux partition sudo fastboot -i 0x3fd flash boot sd.img sudo fastboot -i 0x3fd flash Linux os.img - Creating sd.img or os.img $ dd if=/dev/zero of=sd.img bs=1024 count=1024 $ mkfs.vfat sd.img $ mkdir sd-mount $ mount -o loop sd.img sd-mount $ echo foo > sd-mount/bar $ umount sd-mount partitions setting should be checked by running gpt command. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index e0343a3..ea4761c 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -127,12 +127,36 @@ #define DFU_ALT_INFO \ DFU_ALT_INFO_RAM + +#ifndef CONFIG_SPL_BUILD +# define CONFIG_USB_FUNCTION_FASTBOOT +# define CONFIG_CMD_FASTBOOT +# define CONFIG_ANDROID_BOOT_IMAGE +# define CONFIG_FASTBOOT_BUF_ADDR 0x100000 +# define CONFIG_FASTBOOT_BUF_SIZE 0x6000000 +# define CONFIG_FASTBOOT_FLASH +# ifdef CONFIG_ZYNQ_SDHCI +# define CONFIG_FASTBOOT_FLASH_MMC_DEV 0 +# endif +# define CONFIG_PARTITION_UUIDS +# define CONFIG_CMD_GPT + +# define CONFIG_RANDOM_UUID +# define PARTS_DEFAULT \ + "partitions=uuid_disk=${uuid_gpt_disk};" \ + "name=""boot"",size=16M,uuid=${uuid_gpt_boot};" \ + "name=""Linux"",size=-M,uuid=${uuid_gpt_Linux}\0" +#endif #endif #if !defined(DFU_ALT_INFO) # define DFU_ALT_INFO #endif +#if !defined(PARTS_DEFAULT) +# define PARTS_DEFAULT +#endif + #define CONFIG_BOARD_LATE_INIT /* Do not preserve environment */ -- cgit v0.10.2 From 128ec1fe6f5ee3a753326215732e6030e2c7c4d6 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 15 Nov 2016 16:15:41 +0530 Subject: clk: zynqmp: Add clock driver support for zynqmp Add basic clock driver support for zynqmp which sets the required clock for GEM controller Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek Reviewed-by: Simon Glass diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c05ce2a..335ef9e 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -28,6 +28,13 @@ config CLK_BOSTON help Enable this to support the clocks +config CLK_ZYNQMP + bool "Enable clock driver support for ZynqMP" + depends on ARCH_ZYNQMP + help + This clock driver adds support for clock realted settings for + ZynqMP platform. + source "drivers/clk/tegra/Kconfig" source "drivers/clk/uniphier/Kconfig" source "drivers/clk/exynos/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 40a5e8c..f55348e 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_SANDBOX) += clk_sandbox.o obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o obj-$(CONFIG_MACH_PIC32) += clk_pic32.o +obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o obj-y += tegra/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c new file mode 100644 index 0000000..694274d --- /dev/null +++ b/drivers/clk/clk_zynqmp.c @@ -0,0 +1,241 @@ +/* + * ZynqMP clock driver + * + * Copyright (C) 2016 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define ZYNQMP_GEM0_REF_CTRL 0xFF5E0050 +#define ZYNQMP_IOPLL_CTRL 0xFF5E0020 +#define ZYNQMP_RPLL_CTRL 0xFF5E0030 +#define ZYNQMP_DPLL_CTRL 0xFD1A002C +#define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013 +#define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013 +#define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013 +#define ZYNQMP_SIP_SVC_MMIO_READ 0xC2000014 +#define ZYNQMP_DIV_MAX_VAL 0x3F +#define ZYNQMP_DIV1_SHFT 8 +#define ZYNQMP_DIV1_SHFT 8 +#define ZYNQMP_DIV2_SHFT 16 +#define ZYNQMP_DIV_MASK 0x3F +#define ZYNQMP_PLL_CTRL_FBDIV_MASK 0x7F +#define ZYNQMP_PLL_CTRL_FBDIV_SHFT 8 +#define ZYNQMP_GEM_REF_CTRL_SRC_MASK 0x7 +#define ZYNQMP_GEM0_CLK_ID 45 +#define ZYNQMP_GEM1_CLK_ID 46 +#define ZYNQMP_GEM2_CLK_ID 47 +#define ZYNQMP_GEM3_CLK_ID 48 + +static unsigned long pss_ref_clk; + +static int zynqmp_calculate_divisors(unsigned long req_rate, + unsigned long parent_rate, + u32 *div1, u32 *div2) +{ + u32 req_div = 1; + u32 i; + + /* + * calculate two divisors to get + * required rate and each divisor + * should be less than 63 + */ + req_div = DIV_ROUND_UP(parent_rate, req_rate); + + for (i = 1; i <= req_div; i++) { + if ((req_div % i) == 0) { + *div1 = req_div / i; + *div2 = i; + if ((*div1 < ZYNQMP_DIV_MAX_VAL) && + (*div2 < ZYNQMP_DIV_MAX_VAL)) + return 0; + } + } + + return -1; +} + +static int zynqmp_get_periph_id(unsigned long id) +{ + int periph_id; + + switch (id) { + case ZYNQMP_GEM0_CLK_ID: + periph_id = 0; + break; + case ZYNQMP_GEM1_CLK_ID: + periph_id = 1; + break; + case ZYNQMP_GEM2_CLK_ID: + periph_id = 2; + break; + case ZYNQMP_GEM3_CLK_ID: + periph_id = 3; + break; + default: + printf("%s, Invalid clock id:%ld\n", __func__, id); + return -EINVAL; + } + + return periph_id; +} + +static int zynqmp_set_clk(unsigned long id, u32 div1, u32 div2) +{ + struct pt_regs regs; + ulong reg; + u32 mask, value; + + id = zynqmp_get_periph_id(id); + if (id < 0) + return -EINVAL; + + reg = (ulong)((u32 *)ZYNQMP_GEM0_REF_CTRL + id); + mask = (ZYNQMP_DIV_MASK << ZYNQMP_DIV1_SHFT) | + (ZYNQMP_DIV_MASK << ZYNQMP_DIV2_SHFT); + value = (div1 << ZYNQMP_DIV1_SHFT) | (div2 << ZYNQMP_DIV2_SHFT); + + debug("%s: reg:0x%lx, mask:0x%x, value:0x%x\n", __func__, reg, mask, + value); + + regs.regs[0] = ZYNQMP_SIP_SVC_MMIO_WRITE; + regs.regs[1] = ((u64)mask << 32) | reg; + regs.regs[2] = value; + regs.regs[3] = 0; + + smc_call(®s); + + return regs.regs[0]; +} + +static unsigned long zynqmp_clk_get_rate(struct clk *clk) +{ + struct pt_regs regs; + ulong reg; + unsigned long value; + int id; + + id = zynqmp_get_periph_id(clk->id); + if (id < 0) + return -EINVAL; + + reg = (ulong)((u32 *)ZYNQMP_GEM0_REF_CTRL + id); + + regs.regs[0] = ZYNQMP_SIP_SVC_MMIO_READ; + regs.regs[1] = reg; + regs.regs[2] = 0; + regs.regs[3] = 0; + + smc_call(®s); + + value = upper_32_bits(regs.regs[0]); + + value &= ZYNQMP_GEM_REF_CTRL_SRC_MASK; + + switch (value) { + case 0: + regs.regs[1] = ZYNQMP_IOPLL_CTRL; + break; + case 2: + regs.regs[1] = ZYNQMP_RPLL_CTRL; + break; + case 3: + regs.regs[1] = ZYNQMP_DPLL_CTRL; + break; + default: + return -EINVAL; + } + + regs.regs[0] = ZYNQMP_SIP_SVC_MMIO_READ; + regs.regs[2] = 0; + regs.regs[3] = 0; + + smc_call(®s); + + value = upper_32_bits(regs.regs[0]) & + (ZYNQMP_PLL_CTRL_FBDIV_MASK << + ZYNQMP_PLL_CTRL_FBDIV_SHFT); + value >>= ZYNQMP_PLL_CTRL_FBDIV_SHFT; + value *= pss_ref_clk; + + return value; +} + +static ulong zynqmp_clk_set_rate(struct clk *clk, unsigned long clk_rate) +{ + int ret; + u32 div1 = 0; + u32 div2 = 0; + unsigned long input_clk; + + input_clk = zynqmp_clk_get_rate(clk); + if (IS_ERR_VALUE(input_clk)) { + dev_err(dev, "failed to get input_clk\n"); + return -EINVAL; + } + + debug("%s: i/p CLK %ld, clk_rate:0x%ld\n", __func__, input_clk, + clk_rate); + + ret = zynqmp_calculate_divisors(clk_rate, input_clk, &div1, &div2); + if (ret) { + dev_err(dev, "failed to proper divisors\n"); + return -EINVAL; + } + + debug("%s: Div1:%d, Div2:%d\n", __func__, div1, div2); + + ret = zynqmp_set_clk(clk->id, div1, div2); + if (ret) { + dev_err(dev, "failed to set gem clk\n"); + return -EINVAL; + } + + return 0; +} + +static int zynqmp_clk_probe(struct udevice *dev) +{ + struct clk clk; + int ret; + + debug("%s\n", __func__); + ret = clk_get_by_name(dev, "pss_ref_clk", &clk); + if (ret < 0) { + dev_err(dev, "failed to get pss_ref_clk\n"); + return ret; + } + + pss_ref_clk = clk_get_rate(&clk); + if (IS_ERR_VALUE(pss_ref_clk)) { + dev_err(dev, "failed to get rate pss_ref_clk\n"); + return -EINVAL; + } + + return 0; +} + +static struct clk_ops zynqmp_clk_ops = { + .set_rate = zynqmp_clk_set_rate, + .get_rate = zynqmp_clk_get_rate, +}; + +static const struct udevice_id zynqmp_clk_ids[] = { + { .compatible = "xlnx,zynqmp-clkc" }, + { } +}; + +U_BOOT_DRIVER(zynqmp_clk) = { + .name = "zynqmp-clk", + .id = UCLASS_CLK, + .of_match = zynqmp_clk_ids, + .probe = zynqmp_clk_probe, + .ops = &zynqmp_clk_ops, +}; -- cgit v0.10.2 From a765bdd1cbf576b71502635cf1ebfb28fbad034e Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 15 Nov 2016 16:15:42 +0530 Subject: net: zynq_gem: Use clock driver for ZynqMP Enable and use the clock driver routine defined in clock driver toset required clock appropriately. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 1db2bd6..95fd91d 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -8,10 +8,12 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H +#ifndef CONFIG_CLK_ZYNQMP /* Setup clk for network */ static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) { } +#endif int zynq_slcr_get_mio_pin_status(const char *periph); diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 95b4d6e..6dd87cf 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -9,6 +9,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include @@ -181,6 +182,9 @@ struct zynq_gem_priv { struct phy_device *phydev; int phy_of_handle; struct mii_dev *bus; +#ifdef CONFIG_CLK_ZYNQMP + struct clk clk; +#endif }; static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, @@ -455,8 +459,14 @@ static int zynq_gem_init(struct udevice *dev) /* Change the rclk and clk only not using EMIO interface */ if (!priv->emio) +#ifndef CONFIG_CLK_ZYNQMP zynq_slcr_gem_clk_setup((ulong)priv->iobase != ZYNQ_GEM_BASEADDR0, clk_rate); +#else + ret = clk_set_rate(&priv->clk, clk_rate); + if (IS_ERR_VALUE(ret)) + return -1; +#endif setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); @@ -629,6 +639,14 @@ static int zynq_gem_probe(struct udevice *dev) priv->tx_bd = (struct emac_bd *)bd_space; priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); +#ifdef CONFIG_CLK_ZYNQMP + ret = clk_get_by_name(dev, "tx_clk", &priv->clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return -EINVAL; + } +#endif + priv->bus = mdio_alloc(); priv->bus->read = zynq_gem_miiphy_read; priv->bus->write = zynq_gem_miiphy_write; -- cgit v0.10.2 From 50994ab757c680589685bd29f562b8100b032e65 Mon Sep 17 00:00:00 2001 From: Moritz Fischer Date: Thu, 22 Dec 2016 09:36:10 -0800 Subject: i2c: cdns: Add additional compatible string for r1p14 of the IP. Adding additional compatible string for version 1.4 of the IP block. Signed-off-by: Moritz Fischer Cc: Michal Simek Cc: Heiko Schocher Signed-off-by: Michal Simek diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c index f49f60b..ef85a70 100644 --- a/drivers/i2c/i2c-cdns.c +++ b/drivers/i2c/i2c-cdns.c @@ -366,6 +366,7 @@ static const struct dm_i2c_ops cdns_i2c_ops = { static const struct udevice_id cdns_i2c_of_match[] = { { .compatible = "cdns,i2c-r1p10" }, + { .compatible = "cdns,i2c-r1p14" }, { /* end of table */ } }; -- cgit v0.10.2 From de4914b4e2eadef68c2fd349177a60b2eb0d813e Mon Sep 17 00:00:00 2001 From: Moritz Fischer Date: Thu, 22 Dec 2016 09:36:11 -0800 Subject: ARM64: zynqmp: Fix i2c node's compatible string The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core which fixes some silicon bugs that needed software workarounds in Version 1.0 that was used on Zynq systems. Signed-off-by: Moritz Fischer Cc: Michal Simek Cc: Heiko Schocher Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index e2e76d7..1fd570b 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -637,7 +637,7 @@ }; i2c0: i2c@ff020000 { - compatible = "cdns,i2c-r1p10"; + compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; @@ -648,7 +648,7 @@ }; i2c1: i2c@ff030000 { - compatible = "cdns,i2c-r1p10"; + compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; -- cgit v0.10.2 From ef4cab9d4f0a4a7231c614001f5d1da562104874 Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Tue, 3 Jan 2017 09:47:52 +0100 Subject: ARM: zynqmp: Make SYS_VENDOR configurable Add a string description for SYS_VENDOR to allow configuring boards from other vendors than just "xilinx". Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index e175e6e..499e1dd 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -28,6 +28,7 @@ config SYS_BOARD default "zynqmp" config SYS_VENDOR + string "Vendor name" default "xilinx" config SYS_SOC -- cgit v0.10.2 From 5cf22289aeaf0c84dcb55c629ae4ed72112024cc Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 6 Jan 2017 11:20:54 +0100 Subject: fpga: Use enum for bitstream command types Using enum simplify handling of different bitstream command types. Signed-off-by: Michal Simek diff --git a/cmd/fpga.c b/cmd/fpga.c index 8956eb1..016349f 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -18,15 +18,17 @@ static int fpga_get_op(char *opstr); /* Local defines */ -#define FPGA_NONE -1 -#define FPGA_INFO 0 -#define FPGA_LOAD 1 -#define FPGA_LOADB 2 -#define FPGA_DUMP 3 -#define FPGA_LOADMK 4 -#define FPGA_LOADP 5 -#define FPGA_LOADBP 6 -#define FPGA_LOADFS 7 +enum { + FPGA_NONE = -1, + FPGA_INFO, + FPGA_LOAD, + FPGA_LOADB, + FPGA_DUMP, + FPGA_LOADMK, + FPGA_LOADP, + FPGA_LOADBP, + FPGA_LOADFS, +}; /* ------------------------------------------------------------------------- */ /* command form: -- cgit v0.10.2 From 509d4b9545d82179d5854eddb928c0055702dc67 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 9 Jan 2017 10:05:16 +0100 Subject: ARM64: zynqmp: Generate handoff structure for ATF Xilinx ATF extending options for passing images from BL2(FSBL) to BL31. U-Boot SPL is FSBL replacement that's why it should generate handoff structure the same. Support only one entry which is U-Boot in EL2 itself. When FIT image is adopted structure generate should be data driven. Currently ATF is placing this structure at the beggining of OCM which is rewriting early parts of ATF which should be unused at that time. Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile index be8673a..013f136 100644 --- a/arch/arm/cpu/armv8/zynqmp/Makefile +++ b/arch/arm/cpu/armv8/zynqmp/Makefile @@ -9,4 +9,4 @@ obj-y += clk.o obj-y += cpu.o obj-$(CONFIG_MP) += mp.o obj-y += slcr.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o diff --git a/arch/arm/cpu/armv8/zynqmp/handoff.c b/arch/arm/cpu/armv8/zynqmp/handoff.c new file mode 100644 index 0000000..25d6ef3 --- /dev/null +++ b/arch/arm/cpu/armv8/zynqmp/handoff.c @@ -0,0 +1,87 @@ +/* + * Copyright 2016 - 2017 Xilinx, Inc. + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/* + * atfhandoffparams + * Parameter bitfield encoding + * ----------------------------------------------------------------------------- + * Exec State 0 0 -> Aarch64, 1-> Aarch32 + * endianness 1 0 -> LE, 1 -> BE + * secure (TZ) 2 0 -> Non secure, 1 -> secure + * EL 3:4 00 -> EL0, 01 -> EL1, 10 -> EL2, 11 -> EL3 + * CPU# 5:6 00 -> A53_0, 01 -> A53_1, 10 -> A53_2, 11 -> A53_3 + */ + +#define FSBL_FLAGS_ESTATE_SHIFT 0 +#define FSBL_FLAGS_ESTATE_MASK (1 << FSBL_FLAGS_ESTATE_SHIFT) +#define FSBL_FLAGS_ESTATE_A64 0 +#define FSBL_FLAGS_ESTATE_A32 1 + +#define FSBL_FLAGS_ENDIAN_SHIFT 1 +#define FSBL_FLAGS_ENDIAN_MASK (1 << FSBL_FLAGS_ENDIAN_SHIFT) +#define FSBL_FLAGS_ENDIAN_LE 0 +#define FSBL_FLAGS_ENDIAN_BE 1 + +#define FSBL_FLAGS_TZ_SHIFT 2 +#define FSBL_FLAGS_TZ_MASK (1 << FSBL_FLAGS_TZ_SHIFT) +#define FSBL_FLAGS_NON_SECURE 0 +#define FSBL_FLAGS_SECURE 1 + +#define FSBL_FLAGS_EL_SHIFT 3 +#define FSBL_FLAGS_EL_MASK (3 << FSBL_FLAGS_EL_SHIFT) +#define FSBL_FLAGS_EL0 0 +#define FSBL_FLAGS_EL1 1 +#define FSBL_FLAGS_EL2 2 +#define FSBL_FLAGS_EL3 3 + +#define FSBL_FLAGS_CPU_SHIFT 5 +#define FSBL_FLAGS_CPU_MASK (3 << FSBL_FLAGS_CPU_SHIFT) +#define FSBL_FLAGS_A53_0 0 +#define FSBL_FLAGS_A53_1 1 +#define FSBL_FLAGS_A53_2 2 +#define FSBL_FLAGS_A53_3 3 + +#define FSBL_MAX_PARTITIONS 8 + +/* Structure corresponding to each partition entry */ +struct xfsbl_partition { + uint64_t entry_point; + uint64_t flags; +}; + +/* Structure for handoff parameters to ARM Trusted Firmware (ATF) */ +struct xfsbl_atf_handoff_params { + uint8_t magic[4]; + uint32_t num_entries; + struct xfsbl_partition partition[FSBL_MAX_PARTITIONS]; +}; + +#ifdef CONFIG_SPL_OS_BOOT +void handoff_setup(void) +{ + struct xfsbl_atf_handoff_params *atfhandoffparams; + + atfhandoffparams = (void *)CONFIG_SPL_TEXT_BASE; + atfhandoffparams->magic[0] = 'X'; + atfhandoffparams->magic[1] = 'L'; + atfhandoffparams->magic[2] = 'N'; + atfhandoffparams->magic[3] = 'X'; + + atfhandoffparams->num_entries = 1; + atfhandoffparams->partition[0].entry_point = CONFIG_SYS_TEXT_BASE; + atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 << + FSBL_FLAGS_EL_SHIFT; + + writel(CONFIG_SPL_TEXT_BASE, &pmu_base->gen_storage6); +} +#endif diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index f5f550f..0a5f430 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -128,6 +128,8 @@ __weak void psu_init(void) #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { + handoff_setup(); + return 0; } #endif diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 041b43c..cf187f3 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -144,4 +144,13 @@ struct csu_regs { #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) +#define ZYNQMP_PMU_BASEADDR 0xFFD80000 + +struct pmu_regs { + u32 reserved[18]; + u32 gen_storage6; /* 0x48 */ +}; + +#define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 95fd91d..8c54fce 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -21,4 +21,6 @@ unsigned int zynqmp_get_silicon_version(void); void psu_init(void); +void handoff_setup(void); + #endif /* _ASM_ARCH_SYS_PROTO_H */ -- cgit v0.10.2 From 1e946297575b320e6f6ab8a33467df17d8e38923 Mon Sep 17 00:00:00 2001 From: Kamensky Ivan Date: Tue, 27 Dec 2016 19:12:23 +0300 Subject: xilinx_phy: Pass correct pointer to fdtdec_get_int() This patch fixes incorrect pointer on offset device in device tree blob. When using with the component "Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII" it does not understand what type is XAE_PHY_TYPE_1000BASE_X and trying to change frequency. Signed-off-by: Kamensky Ivan Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c index f3eaf2e..920bfcb 100644 --- a/drivers/net/phy/xilinx_phy.c +++ b/drivers/net/phy/xilinx_phy.c @@ -101,11 +101,11 @@ static int xilinxphy_startup(struct phy_device *phydev) static int xilinxphy_of_init(struct phy_device *phydev) { - struct udevice *dev = (struct udevice *)&phydev->dev; u32 phytype; debug("%s\n", __func__); - phytype = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "phy-type", -1); + phytype = fdtdec_get_int(gd->fdt_blob, phydev->dev->of_offset, + "phy-type", -1); if (phytype == XAE_PHY_TYPE_1000BASE_X) phydev->flags |= XAE_PHY_TYPE_1000BASE_X; -- cgit v0.10.2 From 7364dfe7bfca8632bfe02de5c333a64472812ebe Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 Jan 2017 13:47:52 +0100 Subject: ARM64: zynqmp: Move CONFIG_AHCI from board file Move configuration option from board file to defconfig. Signed-off-by: Michal Simek diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 0663e16..9da0306 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -6,6 +6,7 @@ CONFIG_ZYNQMP_USB=y CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1" CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1" +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h index b19a552..e3797a8 100644 --- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h +++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h @@ -12,7 +12,6 @@ #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_SDHCI1 -#define CONFIG_AHCI #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} #include -- cgit v0.10.2