From 2b792afcc517dcca14c898d3ce444c2bbb7be31a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 24 Sep 2005 21:54:50 +0200 Subject: * Fix PHY address argument passing with mii info command Patch by Andrew Dyer, 28 Dec 2004 * Cleanup: fix broken builds diff --git a/CHANGELOG b/CHANGELOG index 624e449..1f74eba 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,11 @@ Changes for U-Boot 1.1.4: ====================================================================== +* Cleanup: fix broken builds + +* Fix PHY address argument passing with mii info command + Patch by Andrew Dyer, 28 Dec 2004 + * Cleanup (PPC4xx is AMCC now) * esd CPCI2DP board added diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile new file mode 100644 index 0000000..2ca73a9 --- /dev/null +++ b/board/esd/cpci5200/Makefile @@ -0,0 +1,53 @@ + +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +# Objects for Xilinx JTAG programming (CPLD) +# CPLD = ../common/xilinx_jtag/lenval.o \ +# ../common/xilinx_jtag/micro.o \ +# ../common/xilinx_jtag/ports.o + +# OBJS = $(BOARD).o flash.o $(CPLD) +OBJS = $(BOARD).o strataflash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c index 3856a39..cfbfa47 100644 --- a/board/sandburst/karef/karef.c +++ b/board/sandburst/karef/karef.c @@ -242,7 +242,7 @@ int checkboard (void) sys_info_t sysinfo; unsigned char brd_rev, brd_id; unsigned short sernum; - unsigned char scan_rev, scan_id, ofem_rev, ofem_id; + unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0; unsigned char ofem_brd_rev, ofem_brd_id; KAREF_FPGA_REGS_ST *karef_ps; OFEM_FPGA_REGS_ST *ofem_ps; @@ -349,7 +349,6 @@ int misc_init_r (void) char envstr[255]; KAREF_FPGA_REGS_ST *karef_ps; OFEM_FPGA_REGS_ST *ofem_ps; - unsigned char ofem_id; if(NULL != getenv("secondserial")) { puts("secondserial is set, switching to second serial port\n"); diff --git a/common/cmd_mii.c b/common/cmd_mii.c index 3d260ab..722b9f0 100644 --- a/common/cmd_mii.c +++ b/common/cmd_mii.c @@ -414,7 +414,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { char op; unsigned char addrlo, addrhi, reglo, reghi; - unsigned char addr = 0, reg = 0; + unsigned char addr, reg; unsigned short data; int rcode = 0; @@ -456,12 +456,12 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * Look for any and all PHYs. Valid addresses are 0..31. */ if (argc >= 3) { - start = addr; end = addr + 1; + start = addrlo; end = addrhi; } else { - start = 0; end = 32; + start = 0; end = 31; } - for (j = start; j < end; j++) { + for (j = start; j <= end; j++) { if (miiphy_info (j, &oui, &model, &rev) == 0) { printf("PHY 0x%02X: " "OUI = 0x%04X, " @@ -482,8 +482,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) "Error reading from the PHY addr=%02x reg=%02x\n", addr, reg); rcode = 1; - } - else { + } else { if ((addrlo != addrhi) || (reglo != reghi)) printf("addr=%02x reg=%02x data=", (uint)addr, (uint)reg); diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h index 933a42c..e44f1cc 100644 --- a/include/configs/LANTEC.h +++ b/include/configs/LANTEC.h @@ -86,6 +86,7 @@ #define CONFIG_CMD_FULL (CFG_CMD_ALL & ~CFG_CMD_BEDBUG \ & ~CFG_CMD_BMP \ & ~CFG_CMD_BSP \ + & ~CFG_CMD_DISPLAY \ & ~CFG_CMD_DOC \ & ~CFG_CMD_DTT \ & ~CFG_CMD_EEPROM \ diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 9188ae5..98a063a 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -48,7 +48,7 @@ * Figure out if we are booting low via flash HRCW or high via the BCSR. */ #if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */ -# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT 1 #endif @@ -143,7 +143,7 @@ #define CFG_MDIO_PIN 0x00002000 /* PC18 */ #define CFG_MDC_PIN 0x00001000 /* PC19 */ #else -#define CFG_MDIO_PIN 0x00400000 /* PC9 */ +#define CFG_MDIO_PIN 0x00400000 /* PC9 */ #define CFG_MDC_PIN 0x00200000 /* PC10 */ #endif /* CONFIG_ADSTYPE == CFG_8272ADS */ @@ -169,12 +169,12 @@ #define CFG_I2C_SLAVE 0x7F #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR) -#define CONFIG_SPD_ADDR 0x50 +#define CONFIG_SPD_ADDR 0x50 #endif #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ #ifndef CONFIG_SDRAM_PBI -#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ +#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ #endif #ifndef CONFIG_8260_CLKIN @@ -187,16 +187,17 @@ #define CONFIG_BAUDRATE 115200 -#define CFG_EXCLUDE CFG_CMD_BEDBUG | \ +#define CFG_EXCLUDE CFG_CMD_BEDBUG | \ CFG_CMD_BMP | \ CFG_CMD_BSP | \ CFG_CMD_DATE | \ + CFG_CMD_DISPLAY | \ CFG_CMD_DOC | \ CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ CFG_CMD_EXT2 | \ - CFG_CMD_FAT | \ + CFG_CMD_FAT | \ CFG_CMD_FDC | \ CFG_CMD_FDOS | \ CFG_CMD_HWFLOW | \ @@ -205,7 +206,7 @@ CFG_CMD_MMC | \ CFG_CMD_NAND | \ CFG_CMD_PCI | \ - CFG_CMD_PCMCIA | \ + CFG_CMD_PCMCIA | \ CFG_CMD_REISER | \ CFG_CMD_SCSI | \ CFG_CMD_SPI | \ @@ -241,7 +242,7 @@ #endif #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ /* * Miscellaneous configurable options diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index 0a4b04d..4ebbf35 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -31,13 +31,13 @@ */ /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - !! !! + !! !! !! This configuration requires JP3 to be in position 1-2 to work !! - !! To make it work for the default, the TEXT_BASE define in !! + !! To make it work for the default, the TEXT_BASE define in !! !! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !! !! 0xfff00000 !! !! The CFG_HRCW_MASTER define below must also be changed to match !! - !! !! + !! !! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */ @@ -139,23 +139,24 @@ * Definitions for Serial Presence Detect EEPROM address * (to get SDRAM settings) */ -#define SPD_EEPROM_ADDRESS 0x50 +#define SPD_EEPROM_ADDRESS 0x50 #define CONFIG_8260_CLKIN 66000000 /* in Hz */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS ( CFG_CMD_ALL & ~( \ - CFG_CMD_BEDBUG | \ +#define CONFIG_COMMANDS ( CFG_CMD_ALL & ~( \ + CFG_CMD_BEDBUG | \ CFG_CMD_BMP | \ CFG_CMD_BSP | \ CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ + CFG_CMD_DHCP | \ + CFG_CMD_DISPLAY | \ CFG_CMD_DOC | \ CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ CFG_CMD_EXT2 | \ CFG_CMD_FDC | \ CFG_CMD_FDOS | \ @@ -165,7 +166,7 @@ CFG_CMD_KGDB | \ CFG_CMD_MMC | \ CFG_CMD_NAND | \ - CFG_CMD_PCMCIA | \ + CFG_CMD_PCMCIA | \ CFG_CMD_REISER | \ CFG_CMD_SCSI | \ CFG_CMD_SPI | \ @@ -178,8 +179,8 @@ /* Define a command string that is automatically executed when no character * is read on the console interface withing "Boot Delay" after reset. */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ -#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ +#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ +#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ #ifdef CONFIG_BOOT_ROOT_INITRD #define CONFIG_BOOTCOMMAND \ @@ -457,7 +458,7 @@ /*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 + * HIDx - Hardware Implementation-dependent Registers 2-11 *----------------------------------------------------------------------- * HID0 also contains cache control - initially enable both caches and * invalidate contents, then the final state leaves only the instruction @@ -489,7 +490,7 @@ * 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window * 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window * 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory - * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window + * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window * 0xF8000000-0xF8007FFF 32KB BCSR * 0xF8100000-0xF8107FFF 32KB ATM UNI * 0xF8200000-0xF8207FFF 32KB PCI interrupt controller @@ -543,10 +544,10 @@ * in the bridge. */ -#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ -#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ -#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL -#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ +#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ +#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ +#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL +#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ #define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) /* @@ -555,11 +556,11 @@ * in the bridge. */ -#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ -#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ -#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL -#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ -#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) +#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ +#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ +#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL +#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) /* * Master window that allows the CPU to access PCI IO space. @@ -567,11 +568,11 @@ * in the bridge. */ -#define CFG_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */ -#define CFG_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */ -#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL -#define CFG_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */ -#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO) +#define CFG_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */ +#define CFG_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */ +#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL +#define CFG_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */ +#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO) /* * JFFS2 partitions diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index 4d47d3e..dbc3c86 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -97,6 +97,7 @@ #define CONFIG_COMMANDS ( CFG_CMD_ALL & \ ~CFG_CMD_BSP & \ ~CFG_CMD_DATE & \ + ~CFG_CMD_DISPLAY& \ ~CFG_CMD_DTT & \ ~CFG_CMD_EXT2 & \ ~CFG_CMD_FDC & \ diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h index 8b0afd5..e7b0818 100644 --- a/include/configs/ep8260.h +++ b/include/configs/ep8260.h @@ -299,6 +299,7 @@ CFG_CMD_BSP | \ CFG_CMD_DCR | \ CFG_CMD_DHCP | \ + CFG_CMD_DISPLAY | \ CFG_CMD_DOC | \ CFG_CMD_DTT | \ CFG_CMD_EEPROM | \ diff --git a/include/configs/hymod.h b/include/configs/hymod.h index aadb59f..8cad98d 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -177,6 +177,7 @@ #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ CFG_CMD_BEDBUG | \ CFG_CMD_BMP | \ + CFG_CMD_DISPLAY | \ CFG_CMD_DOC | \ CFG_CMD_EXT2 | \ CFG_CMD_FDC | \ -- cgit v0.10.2