From e6bbe53da015285ae67606a4eca1a8996f368aab Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 23 Nov 2011 16:32:16 +0000 Subject: CFB: Fix font rendering on mx5 framebuffer Signed-off-by: Marek Vasut Cc: Anatolij Gustschin Cc: Stefano Babic diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 32e890c..480df64 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -164,7 +164,7 @@ /* * Defines for the i.MX31 driver (mx3fb.c) */ -#ifdef CONFIG_VIDEO_MX3 +#if defined(CONFIG_VIDEO_MX3) || defined(CONFIG_VIDEO_MX5) #define VIDEO_FB_16BPP_WORD_SWAP #endif -- cgit v0.10.2 From d8bf22bb0ee95ac5fd74a3b357a47bc94283336d Mon Sep 17 00:00:00 2001 From: Jerry Huang Date: Tue, 1 Nov 2011 15:16:43 +0000 Subject: DIU: 1080P and 720P support Add the 1920x1080 and 1280x720 resolution support. Signed-off-by: Jerry Huang Acked-by: Timur Tabi CC: Anatolij Gustschin diff --git a/drivers/video/fsl_diu_fb.c b/drivers/video/fsl_diu_fb.c index 350241e..648ffa3 100644 --- a/drivers/video/fsl_diu_fb.c +++ b/drivers/video/fsl_diu_fb.c @@ -106,6 +106,38 @@ static struct fb_videomode fsl_diu_mode_1280_1024 = { .vmode = FB_VMODE_NONINTERLACED }; +static struct fb_videomode fsl_diu_mode_1280_720 = { + .name = "1280x720-60", + .refresh = 60, + .xres = 1280, + .yres = 720, + .pixclock = 13426, + .left_margin = 192, + .right_margin = 64, + .upper_margin = 22, + .lower_margin = 1, + .hsync_len = 136, + .vsync_len = 3, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; + +static struct fb_videomode fsl_diu_mode_1920_1080 = { + .name = "1920x1080-60", + .refresh = 60, + .xres = 1920, + .yres = 1080, + .pixclock = 5787, + .left_margin = 328, + .right_margin = 120, + .upper_margin = 34, + .lower_margin = 1, + .hsync_len = 208, + .vsync_len = 3, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; + /* * These are the fields of area descriptor(in DDR memory) for every plane */ @@ -259,6 +291,12 @@ int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix) case RESOLUTION(1280, 1024): fsl_diu_mode_db = &fsl_diu_mode_1280_1024; break; + case RESOLUTION(1280, 720): + fsl_diu_mode_db = &fsl_diu_mode_1280_720; + break; + case RESOLUTION(1920, 1080): + fsl_diu_mode_db = &fsl_diu_mode_1920_1080; + break; default: printf("DIU: Unsupported resolution %ux%u\n", xres, yres); return -1; -- cgit v0.10.2 From 762e63754b6417126260dd22631d0e3bda12eb70 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Tue, 1 Nov 2011 00:00:39 +0100 Subject: Fix Stelian's email address Change my old email address which is no longer valid. Signed-off-by: Stelian Pop Signed-off-by: Anatolij Gustschin diff --git a/CREDITS b/CREDITS index e8e923a..dead57d 100644 --- a/CREDITS +++ b/CREDITS @@ -376,7 +376,7 @@ D: Support for the Wind River sbc405, sbc8240 board W: http://www.windriver.com N: Stelian Pop -E: stelian.pop@leadtechdesign.com +E: stelian@popies.net D: Atmel AT91CAP9ADK support N: Ricardo Ribalda Delgado diff --git a/MAINTAINERS b/MAINTAINERS index f6f6b72..c68842e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -771,7 +771,7 @@ Dave Peverley omap730p2 ARM926EJS -Stelian Pop +Stelian Pop at91sam9260ek ARM926EJS (AT91SAM9260 SoC) at91sam9261ek ARM926EJS (AT91SAM9261 SoC) diff --git a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c b/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c index 412f502..4caa157 100644 --- a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c +++ b/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c @@ -5,7 +5,7 @@ * Andreas Bießmann * * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c b/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c index 2d878fd..db2ecb8 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * (C) Copyright 2009 diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c index 65b8d51..a4e9f09 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c index edc7972..ae8cd56 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c index 6eb0f30..7191db2 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * (C) Copyright 2009-2011 diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 5ff32e3..f31c364 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c index b0a1687..ca44cf5 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c index 6e59c86..a1bb28d 100644 --- a/arch/arm/cpu/arm926ejs/at91/led.c +++ b/arch/arm/cpu/arm926ejs/at91/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/cpu/arm926ejs/at91/reset.c index 023719a..f6a7cb7 100644 --- a/arch/arm/cpu/arm926ejs/at91/reset.c +++ b/arch/arm/cpu/arm926ejs/at91/reset.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c index a087687..f70ce83 100644 --- a/arch/arm/cpu/arm926ejs/at91/timer.c +++ b/arch/arm/cpu/arm926ejs/at91/timer.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c index 8f38056..75314b9 100644 --- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c +++ b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * (C) Copyright 2010 diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h index 330edd8..8282f46 100644 --- a/arch/arm/include/asm/arch-at91/at91_common.h +++ b/arch/arm/include/asm/arch-at91/at91_common.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/include/asm/arch-at91/at91cap9.h b/arch/arm/include/asm/arch-at91/at91cap9.h index 5af6fdc..7bf363a 100644 --- a/arch/arm/include/asm/arch-at91/at91cap9.h +++ b/arch/arm/include/asm/arch-at91/at91cap9.h @@ -1,7 +1,7 @@ /* * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h] * - * Copyright (C) 2007 Stelian Pop + * Copyright (C) 2007 Stelian Pop * Copyright (C) 2007 Lead Tech Design * Copyright (C) 2007 Atmel Corporation. * diff --git a/arch/arm/include/asm/arch-at91/at91cap9_matrix.h b/arch/arm/include/asm/arch-at91/at91cap9_matrix.h index 22b7e9b..a9b5ae0 100644 --- a/arch/arm/include/asm/arch-at91/at91cap9_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91cap9_matrix.h @@ -1,7 +1,7 @@ /* * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9_matrix.h] * - * Copyright (C) 2007 Stelian Pop + * Copyright (C) 2007 Stelian Pop * Copyright (C) 2007 Lead Tech Design * Copyright (C) 2006 Atmel Corporation. * diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h index f645327..1e8522b 100644 --- a/arch/arm/include/asm/arch-at91/clk.h +++ b/arch/arm/include/asm/arch-at91/clk.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007 - * Stelian Pop + * Stelian Pop * Lead Tech Design * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD * diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h index 36af571..85c2889 100644 --- a/arch/arm/include/asm/arch-at91/hardware.h +++ b/arch/arm/include/asm/arch-at91/hardware.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 501ce0e..5bbb0a0 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/afeb9260/Makefile b/board/afeb9260/Makefile index 9134856..c56bcf8 100644 --- a/board/afeb9260/Makefile +++ b/board/afeb9260/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c index f0e2e80..dda69e0 100644 --- a/board/afeb9260/afeb9260.c +++ b/board/afeb9260/afeb9260.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * (C) Copyright 2008 Sergey Lapin * diff --git a/board/atmel/at91sam9260ek/Makefile b/board/atmel/at91sam9260ek/Makefile index b9ecc88..66706eb 100644 --- a/board/atmel/at91sam9260ek/Makefile +++ b/board/atmel/at91sam9260ek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index b3ed91d..2555672 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9260ek/led.c b/board/atmel/at91sam9260ek/led.c index daf81e8..9bdd385 100644 --- a/board/atmel/at91sam9260ek/led.c +++ b/board/atmel/at91sam9260ek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9261ek/Makefile b/board/atmel/at91sam9261ek/Makefile index 080f289..f44dcdb 100644 --- a/board/atmel/at91sam9261ek/Makefile +++ b/board/atmel/at91sam9261ek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index b6c7d9e..47ab839 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9261ek/led.c b/board/atmel/at91sam9261ek/led.c index 0c2f522..7fa6136 100644 --- a/board/atmel/at91sam9261ek/led.c +++ b/board/atmel/at91sam9261ek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9263ek/Makefile b/board/atmel/at91sam9263ek/Makefile index 8493043..af8726d 100644 --- a/board/atmel/at91sam9263ek/Makefile +++ b/board/atmel/at91sam9263ek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 4d2937d..41ec752 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9263ek/led.c b/board/atmel/at91sam9263ek/led.c index c44455e..ce3cf09 100644 --- a/board/atmel/at91sam9263ek/led.c +++ b/board/atmel/at91sam9263ek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9m10g45ek/Makefile b/board/atmel/at91sam9m10g45ek/Makefile index 6c37827..1915111 100644 --- a/board/atmel/at91sam9m10g45ek/Makefile +++ b/board/atmel/at91sam9m10g45ek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 24a8606..5a04274 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9m10g45ek/led.c b/board/atmel/at91sam9m10g45ek/led.c index dadbd6a..0fd38f6 100644 --- a/board/atmel/at91sam9m10g45ek/led.c +++ b/board/atmel/at91sam9m10g45ek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9rlek/Makefile b/board/atmel/at91sam9rlek/Makefile index 7de8897..36df7af 100644 --- a/board/atmel/at91sam9rlek/Makefile +++ b/board/atmel/at91sam9rlek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index e559084..ef0ddd7 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9rlek/led.c b/board/atmel/at91sam9rlek/led.c index 987e8c0..4a1e8d7 100644 --- a/board/atmel/at91sam9rlek/led.c +++ b/board/atmel/at91sam9rlek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/calao/sbc35_a9g20/Makefile b/board/calao/sbc35_a9g20/Makefile index 7b7cc29..8a0618e 100644 --- a/board/calao/sbc35_a9g20/Makefile +++ b/board/calao/sbc35_a9g20/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c index 5f448d9..4f5cff6 100644 --- a/board/calao/sbc35_a9g20/sbc35_a9g20.c +++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * Copyright (C) 2009 diff --git a/board/calao/tny_a9260/Makefile b/board/calao/tny_a9260/Makefile index 1bf21e1..5a6c6b8 100644 --- a/board/calao/tny_a9260/Makefile +++ b/board/calao/tny_a9260/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/calao/tny_a9260/tny_a9260.c b/board/calao/tny_a9260/tny_a9260.c index ab51a33..24de177 100644 --- a/board/calao/tny_a9260/tny_a9260.c +++ b/board/calao/tny_a9260/tny_a9260.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * Copyright (C) 2009 diff --git a/board/emk/top9000/top9000.c b/board/emk/top9000/top9000.c index 61dee62..6f5662a 100644 --- a/board/emk/top9000/top9000.c +++ b/board/emk/top9000/top9000.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * (C) Copyright 2010 diff --git a/board/esd/meesc/Makefile b/board/esd/meesc/Makefile index 74cfce9..2c95ced 100644 --- a/board/esd/meesc/Makefile +++ b/board/esd/meesc/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index ad43531..4882ffc 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * (C) Copyright 2009-2011 diff --git a/board/esd/otc570/Makefile b/board/esd/otc570/Makefile index 1819292..3e94d19 100644 --- a/board/esd/otc570/Makefile +++ b/board/esd/otc570/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c index 15faa16..5dded41 100644 --- a/board/esd/otc570/otc570.c +++ b/board/esd/otc570/otc570.c @@ -4,7 +4,7 @@ * esd electronic system design gmbh * * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/eukrea/cpu9260/Makefile b/board/eukrea/cpu9260/Makefile index 897fe3e..2ec6338 100644 --- a/board/eukrea/cpu9260/Makefile +++ b/board/eukrea/cpu9260/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop # Ilko Iliev # diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c index 402f19f..ecb0796 100644 --- a/board/eukrea/cpu9260/cpu9260.c +++ b/board/eukrea/cpu9260/cpu9260.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * Ilko Iliev * diff --git a/board/ronetix/pm9261/Makefile b/board/ronetix/pm9261/Makefile index 0abca0d..a288b28 100644 --- a/board/ronetix/pm9261/Makefile +++ b/board/ronetix/pm9261/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # Ilko Iliev # diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c index f659870..1a2a81d 100644 --- a/board/ronetix/pm9261/led.c +++ b/board/ronetix/pm9261/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * Ilko Iliev * diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index b26e33a..c6b582d 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD diff --git a/board/ronetix/pm9263/Makefile b/board/ronetix/pm9263/Makefile index 68baec7..db8de82 100644 --- a/board/ronetix/pm9263/Makefile +++ b/board/ronetix/pm9263/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # Ilko Iliev # diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c index d6eb69f..e6883a3 100644 --- a/board/ronetix/pm9263/led.c +++ b/board/ronetix/pm9263/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * Ilko Iliev * diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 335efba..59cca87 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD diff --git a/board/ronetix/pm9g45/Makefile b/board/ronetix/pm9g45/Makefile index e586964..bebc5b4 100644 --- a/board/ronetix/pm9g45/Makefile +++ b/board/ronetix/pm9g45/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 961d193..d29d076 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -5,7 +5,7 @@ * Ronetix GmbH * * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile index c99252c..a2951a4 100644 --- a/board/syteco/jadecpu/Makefile +++ b/board/syteco/jadecpu/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/doc/README.scrapyard b/doc/README.scrapyard index cb5e4bc..d37dbcf 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -30,7 +30,7 @@ m501sk arm arm920t b1a2bd4 2011-07-17 kb9202 arm arm920t 5bd3814 2011-07-17 csb637 arm arm920t d14af08 2011-07-17 cmc_pu2 arm arm920t 37a9b4d 2011-07-17 -at91cap9adk arm arm926ejs b550834 2011-07-17 Stelian Pop +at91cap9adk arm arm926ejs b550834 2011-07-17 Stelian Pop voiceblue arm arm925t 1b793a4 2011-07-17 smdk2400 arm arm920t ad218a8 2011-07-17 Gary Jennejohn sbc2410x arm arm920t 1f7f0ed 2011-07-17 diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 818d362..de66382 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index c439f3e..db52ee6 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * Configuation settings for the AT91SAM9260EK & AT91SAM9G20EK boards. diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index c8fc9e7..5140b26 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * Configuation settings for the AT91SAM9261EK board. diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index f73d952..8399246 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * Configuation settings for the AT91SAM9263EK board. diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 05575cd..5ef6bd2 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES). diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 3ca09e1..79ea1f2 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * Configuation settings for the AT91SAM9RLEK board. diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h index 0c86d62..8674a35 100644 --- a/include/configs/cpu9260.h +++ b/include/configs/cpu9260.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * Ilko Iliev * diff --git a/include/configs/meesc.h b/include/configs/meesc.h index ea40290..d6197bc 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * (C) Copyright 2009-2011 diff --git a/include/configs/otc570.h b/include/configs/otc570.h index c068aa0..b322c77 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -4,7 +4,7 @@ * esd electronic system design gmbh * * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * Configuation settings for the esd OTC570 board. diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 55455e7..9fbf9af 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * Ilko Iliev * diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 43104a3..374be27 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * Ilko Iliev * diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index d3beaf3..5b08d91 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -5,7 +5,7 @@ * Ronetix GmbH * * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * Configuation settings for the PM9G45 board. diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h index 986aeba..ec8ec18 100644 --- a/include/configs/tny_a9260.h +++ b/include/configs/tny_a9260.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * Copyright (C) 2009 -- cgit v0.10.2 From a67fe5f284c73e5171b80657619ee24d7cc9726b Mon Sep 17 00:00:00 2001 From: Alexander Holler Date: Sat, 18 Dec 2010 13:24:20 +0100 Subject: OMAP3: Use sdelay from arch/arm/cpu/armv7/syslib.c instead of cloning that. There is no need to have such a function twice. Signed-off-by: Alexander Holler Acked-by: Dirk Behme Signed-off-by: Anatolij Gustschin diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index a9fdb4f..cdf452d 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -93,16 +93,6 @@ u32 omap_boot_device(void) /****************************************************************************** - * Routine: delay - * Description: spinning delay to use before udelay works - *****************************************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -/****************************************************************************** * Routine: secure_unlock * Description: Setup security registers for access * (GP Device only) @@ -227,7 +217,7 @@ void s_init(void) #endif set_muxconf_regs(); - delay(100); + sdelay(100); prcm_init(); -- cgit v0.10.2 From 641483af40915dabdfe7764bb22d7e5103cb636b Mon Sep 17 00:00:00 2001 From: Yan-Pai Chen Date: Mon, 7 Nov 2011 19:40:25 +0000 Subject: arm: a320evb: define mach-type in board config file MACH_TYPE_FARADAY was dropped from mach-types.h. Add it back to board config file. Signed-off-by: Yan-Pai Chen Acked-by: Igor Grinberg diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c index 2578be4..dfd186b 100644 --- a/board/faraday/a320evb/a320evb.c +++ b/board/faraday/a320evb/a320evb.c @@ -31,7 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_FARADAY; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; ftsmc020_init(); /* initialize Flash */ diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h index 45a7c53..1fafbed 100644 --- a/include/configs/a320evb.h +++ b/include/configs/a320evb.h @@ -25,6 +25,12 @@ #include /* + * mach-type definition + */ +#define MACH_TYPE_FARADAY 758 +#define CONFIG_MACH_TYPE MACH_TYPE_FARADAY + +/* * Linux kernel tagged list */ #define CONFIG_CMDLINE_TAG -- cgit v0.10.2 From ece91e30265764fe4edd61d8c1852d2248e566be Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Sat, 19 Nov 2011 00:45:42 +0000 Subject: davinci_schmoogie: define CONFIG_MACH_TYPE for davinci_schmoogie board This patch fixes the build breakage for the davinci_schmoogie board. Signed-off-by: Christian Riesch Cc: Sergey Kubushyn Cc: Sandeep Paulraj diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c index 8b615a9..52d00e4 100644 --- a/board/davinci/schmoogie/schmoogie.c +++ b/board/davinci/schmoogie/schmoogie.c @@ -33,9 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE; - /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 5eaa198..f4ddbeac 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -27,6 +27,9 @@ #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_USE_NAND #define CONFIG_DISPLAY_CPUINFO +#define MACH_TYPE_SCHMOOGIE 1255 +#define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE + /*===================*/ /* SoC Configuration */ /*===================*/ -- cgit v0.10.2 From f880fe57948907815cccbcbb6cb2f1984254da0d Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Sat, 19 Nov 2011 00:45:43 +0000 Subject: davinci_sonata: define CONFIG_MACH_TYPE for davinci_sonata board This patch fixes the build breakage for the davinci_sonata board. Signed-off-by: Christian Riesch Cc: Sergey Kubushyn Cc: Sandeep Paulraj diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index c194290..55110fb 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -34,9 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_SONATA; - /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 74530e8..fc4d8ec 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -52,6 +52,8 @@ #define CONFIG_SYS_NAND_SMALLPAGE #define CONFIG_SYS_USE_NOR #define CONFIG_DISPLAY_CPUINFO +#define MACH_TYPE_SONATA 1254 +#define CONFIG_MACH_TYPE MACH_TYPE_SONATA /*===================*/ /* SoC Configuration */ /*===================*/ -- cgit v0.10.2 From e722d5d076539309e4dc6ff718a2d3ba0341a046 Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Sat, 19 Nov 2011 00:45:44 +0000 Subject: hawkboard: Replace HAWKBOARD_KICK{0, 1}_UNLOCK defines This patch replaces the HAWKBOARD_KICK{0,1}_UNLOCK defines by DV_SYSCFG_KICK{0,1}_UNLOCK. The kick register values are not hawkboard specific but may be used for all davinci boards. In commit f3c149d6c6e5ba8dd72baa86fe527837e4fb0e9a new defines for these values wer introduced. Signed-off-by: Christian Riesch Cc: Syed Mohammed Khasim Cc: Sughosh Ganu Cc: Sandeep Paulraj diff --git a/arch/arm/include/asm/arch-davinci/davinci_misc.h b/arch/arm/include/asm/arch-davinci/davinci_misc.h index 211b769..cbac803 100644 --- a/arch/arm/include/asm/arch-davinci/davinci_misc.h +++ b/arch/arm/include/asm/arch-davinci/davinci_misc.h @@ -45,9 +45,6 @@ struct pinmux_resource { .n_pins = ARRAY_SIZE(item) \ } -#define HAWKBOARD_KICK0_UNLOCK 0x83e70b13 -#define HAWKBOARD_KICK1_UNLOCK 0x95a4f1e0 - struct lpsc_resource { const int lpsc_no; }; diff --git a/board/davinci/da8xxevm/hawkboard.c b/board/davinci/da8xxevm/hawkboard.c index f34830e..9d4e238 100644 --- a/board/davinci/da8xxevm/hawkboard.c +++ b/board/davinci/da8xxevm/hawkboard.c @@ -47,8 +47,8 @@ int board_early_init_f(void) /* * Kick Registers need to be set to allow access to Pin Mux registers */ - writel(HAWKBOARD_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); - writel(HAWKBOARD_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); + writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); + writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); /* set cfgchip3 to select mii */ writel(readl(&davinci_syscfg_regs->cfgchip3) & diff --git a/board/davinci/da8xxevm/hawkboard_nand_spl.c b/board/davinci/da8xxevm/hawkboard_nand_spl.c index e5e65e5..32b17ce 100644 --- a/board/davinci/da8xxevm/hawkboard_nand_spl.c +++ b/board/davinci/da8xxevm/hawkboard_nand_spl.c @@ -99,8 +99,8 @@ void board_init_f(ulong bootflag) /* * Kick Registers need to be set to allow access to Pin Mux registers */ - writel(HAWKBOARD_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); - writel(HAWKBOARD_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); + writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); + writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); /* setup the SUSPSRC for ARM to control emulation suspend */ writel(readl(&davinci_syscfg_regs->suspsrc) & -- cgit v0.10.2 From 85be1e21fcec4f9c1010c4f61e050ae9b0df2bbc Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Sat, 26 Nov 2011 23:06:46 +0000 Subject: dataflash: fix parameters order in write_dataflash() Fix parameters order in write_dataflash() function extern declaration in the header file. Parameters order, as in function definition, should be: addr_dest, addr_src, size. Signed-off-by: Igor Grinberg diff --git a/include/dataflash.h b/include/dataflash.h index 056e18b..94f86b3 100644 --- a/include/dataflash.h +++ b/include/dataflash.h @@ -207,7 +207,8 @@ extern int addr2ram(ulong addr); extern int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr); extern int addr_dataflash (unsigned long addr); extern int read_dataflash (unsigned long addr, unsigned long size, char *result); -extern int write_dataflash (unsigned long addr, unsigned long dest, unsigned long size); +extern int write_dataflash(unsigned long addr_dest, unsigned long addr_src, + unsigned long size); extern int AT91F_DataflashInit(void); extern void dataflash_print_info (void); -- cgit v0.10.2 From 623e03256e222b42fb86fd81fafe508e3cb569a4 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 17 Nov 2011 23:16:14 +0000 Subject: MAKEALL: drop obsolete mx31pdk_nand target The mx31pdk can boot only from NAND and the target was already updated in boards.cfg. mx31pdk_nand is obsolete and is dropped. Signed-off-by: Stefano Babic diff --git a/MAKEALL b/MAKEALL index 95b7cd3..2a77857 100755 --- a/MAKEALL +++ b/MAKEALL @@ -316,7 +316,6 @@ LIST_ARM11="$(boards_by_cpu arm1136) \ imx31_phycore \ imx31_phycore_eet \ mx31pdk \ - mx31pdk_nand \ smdk6400 \ " -- cgit v0.10.2 From a63d9652757605ec5f7104addc5d38bf10ba8671 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 28 Nov 2011 20:19:41 +0100 Subject: menu.c: use puts() instead of printf() where possible common/menu.c used printf() in a number of places to print user provided, constant strings (like the "title" string). printf() is dangerous here for example in case the user unwittingly embeds some '%' caracters that printf() would interpret as formatting and then pick up random arguments. Use puts() instead. We also omit the trailing ':' in the title line - if a user wants this, he can provide it as part of the title string. Signed-off-by: Wolfgang Denk diff --git a/common/menu.c b/common/menu.c index f004823..ca1baef 100644 --- a/common/menu.c +++ b/common/menu.c @@ -87,10 +87,12 @@ static inline void *menu_item_print(struct menu *m, struct menu_item *item, void *extra) { - if (!m->item_data_print) - printf("%s\n", item->key); - else + if (!m->item_data_print) { + putc(item->key); + putc('\n'); + } else { m->item_data_print(item->data); + } return NULL; } @@ -117,8 +119,10 @@ static inline void *menu_item_destroy(struct menu *m, */ static inline void menu_display(struct menu *m) { - if (m->title) - printf("%s:\n", m->title); + if (m->title) { + puts(m->title); + putc('\n'); + } menu_items_iter(m, menu_item_print, NULL); } @@ -226,7 +230,7 @@ static inline int menu_interactive_choice(struct menu *m, void **choice) if (!choice_item) printf("%s not found\n", cbuf); } else { - printf("^C\n"); + puts("^C\n"); return -EINTR; } } -- cgit v0.10.2 From 6d7404c4c18ba2be711504909a67b2717ef55ac8 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:12 +0000 Subject: x86: Call hang() on unrecoverable exception Signed-off-by: Graeme Russ diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index c6e72ea..89f39d2 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -255,7 +255,7 @@ void irq_llsr(struct irq_regs *regs) case 0x00: printf("Divide Error (Division by zero)\n"); dump_regs(regs); - while(1); + hang(); break; case 0x01: printf("Debug Interrupt (Single step)\n"); @@ -272,32 +272,32 @@ void irq_llsr(struct irq_regs *regs) case 0x04: printf("Overflow\n"); dump_regs(regs); - while(1); + hang(); break; case 0x05: printf("BOUND Range Exceeded\n"); dump_regs(regs); - while(1); + hang(); break; case 0x06: printf("Invalid Opcode (UnDefined Opcode)\n"); dump_regs(regs); - while(1); + hang(); break; case 0x07: printf("Device Not Available (No Math Coprocessor)\n"); dump_regs(regs); - while(1); + hang(); break; case 0x08: printf("Double fault\n"); dump_regs(regs); - while(1); + hang(); break; case 0x09: printf("Co-processor segment overrun\n"); dump_regs(regs); - while(1); + hang(); break; case 0x0a: printf("Invalid TSS\n"); @@ -306,12 +306,12 @@ void irq_llsr(struct irq_regs *regs) case 0x0b: printf("Segment Not Present\n"); dump_regs(regs); - while(1); + hang(); break; case 0x0c: printf("Stack Segment Fault\n"); dump_regs(regs); - while(1); + hang(); break; case 0x0d: printf("General Protection\n"); @@ -320,7 +320,7 @@ void irq_llsr(struct irq_regs *regs) case 0x0e: printf("Page fault\n"); dump_regs(regs); - while(1); + hang(); break; case 0x0f: printf("Floating-Point Error (Math Fault)\n"); -- cgit v0.10.2 From 717979fdd752b80e031001c871a4fa2f84b3e3f6 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:13 +0000 Subject: cosmetic: checkpatch cleanup of arch/x86/cpu/*.c Signed-off-by: Graeme Russ diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index cac12c0..48d2f7a 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -52,7 +52,7 @@ struct gdt_ptr { u16 len; u32 ptr; -} __attribute__((packed)); +} __packed; static void reload_gdt(void) { @@ -115,14 +115,14 @@ int x86_cpu_init_r(void) reload_gdt(); /* Initialize core interrupt and exception functionality of CPU */ - cpu_init_interrupts (); + cpu_init_interrupts(); return 0; } int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - printf ("resetting ...\n"); + printf("resetting ...\n"); /* wait 50 ms */ udelay(50000); @@ -133,7 +133,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -void flush_cache (unsigned long dummy1, unsigned long dummy2) +void flush_cache(unsigned long dummy1, unsigned long dummy2) { asm("wbinvd\n"); } @@ -142,16 +142,16 @@ void __attribute__ ((regparm(0))) generate_gpf(void); /* segment 0x70 is an arbitrary segment which does not exist */ asm(".globl generate_gpf\n" - ".hidden generate_gpf\n" - ".type generate_gpf, @function\n" - "generate_gpf:\n" - "ljmp $0x70, $0x47114711\n"); + ".hidden generate_gpf\n" + ".type generate_gpf, @function\n" + "generate_gpf:\n" + "ljmp $0x70, $0x47114711\n"); void __reset_cpu(ulong addr) { printf("Resetting using x86 Triple Fault\n"); - set_vector(13, generate_gpf); /* general protection fault handler */ - set_vector(8, generate_gpf); /* double fault handler */ - generate_gpf(); /* start the show */ + set_vector(13, generate_gpf); /* general protection fault handler */ + set_vector(8, generate_gpf); /* double fault handler */ + generate_gpf(); /* start the show */ } void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu"))); diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index 89f39d2..e007511 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -31,6 +31,7 @@ #include #include #include +#include #define DECLARE_INTERRUPT(x) \ ".globl irq_"#x"\n" \ @@ -83,22 +84,22 @@ static inline unsigned long get_debugreg(int regno) switch (regno) { case 0: - asm("mov %%db0, %0" :"=r" (val)); + asm("mov %%db0, %0" : "=r" (val)); break; case 1: - asm("mov %%db1, %0" :"=r" (val)); + asm("mov %%db1, %0" : "=r" (val)); break; case 2: - asm("mov %%db2, %0" :"=r" (val)); + asm("mov %%db2, %0" : "=r" (val)); break; case 3: - asm("mov %%db3, %0" :"=r" (val)); + asm("mov %%db3, %0" : "=r" (val)); break; case 6: - asm("mov %%db6, %0" :"=r" (val)); + asm("mov %%db6, %0" : "=r" (val)); break; case 7: - asm("mov %%db7, %0" :"=r" (val)); + asm("mov %%db7, %0" : "=r" (val)); break; default: val = 0; @@ -120,7 +121,8 @@ void dump_regs(struct irq_regs *regs) printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n", regs->esi, regs->edi, regs->ebp, regs->esp); printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n", - (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, (u16)regs->xgs, (u16)regs->xss); + (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, + (u16)regs->xgs, (u16)regs->xss); cr0 = read_cr0(); cr2 = read_cr2(); @@ -164,13 +166,13 @@ struct idt_entry { u8 res; u8 access; u16 base_high; -} __attribute__ ((packed)); +} __packed; struct desc_ptr { unsigned short size; unsigned long address; unsigned short segment; -} __attribute__((packed)); +} __packed; struct idt_entry idt[256]; @@ -178,7 +180,7 @@ struct desc_ptr idt_ptr; static inline void load_idt(const struct desc_ptr *dtr) { - asm volatile("cs lidt %0"::"m" (*dtr)); + asm volatile("cs lidt %0" : : "m" (*dtr)); } void set_vector(u8 intnum, void *routine) @@ -187,6 +189,11 @@ void set_vector(u8 intnum, void *routine) idt[intnum].base_low = (u16)((u32)(routine) & 0xffff); } +/* + * Ideally these would be defined static to avoid a checkpatch warning, but + * the compiler cannot see them in the inline asm and complains that they + * aren't defined + */ void irq_0(void); void irq_1(void); @@ -201,7 +208,7 @@ int cpu_init_interrupts(void) disable_interrupts(); /* Setup the IDT */ - for (i=0;i<256;i++) { + for (i = 0; i < 256; i++) { idt[i].access = 0x8e; idt[i].res = 0; idt[i].selector = 0x10; @@ -238,7 +245,7 @@ int disable_interrupts(void) asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : ); - return flags & X86_EFLAGS_IF; /* IE flags is bit 9 */ + return flags & X86_EFLAGS_IF; } /* IRQ Low-Level Service Routine */ -- cgit v0.10.2 From 01a0f5a1ebba7eeccf13fc5992ed59e8614fd58a Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:14 +0000 Subject: cosmetic: checkpatch cleanup of arch/x86/cpu/sc520/*.c Signed-off-by: Graeme Russ diff --git a/arch/x86/cpu/sc520/sc520.c b/arch/x86/cpu/sc520/sc520.c index 4892c01..3fe85e7 100644 --- a/arch/x86/cpu/sc520/sc520.c +++ b/arch/x86/cpu/sc520/sc520.c @@ -49,7 +49,7 @@ int cpu_init_f(void) asm("movl $0x2000, %%ecx\n" "0: pushl %%ecx\n" "popl %%ecx\n" - "loop 0b\n": : : "ecx"); + "loop 0b\n" : : : "ecx"); return x86_cpu_init_f(); } diff --git a/arch/x86/cpu/sc520/sc520_pci.c b/arch/x86/cpu/sc520/sc520_pci.c index e26793a..a13798f 100644 --- a/arch/x86/cpu/sc520/sc520_pci.c +++ b/arch/x86/cpu/sc520/sc520_pci.c @@ -70,26 +70,28 @@ int pci_sc520_set_irq(int pci_pin, int irq) debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); - if (irq < 0 || irq > 15) { + if (irq < 0 || irq > 15) return -1; /* illegal irq */ - } - if (pci_pin < 0 || pci_pin > 15) { + if (pci_pin < 0 || pci_pin > 15) return -1; /* illegal pci int pin */ - } /* first disable any non-pci interrupt source that use * this level */ /* PCI interrupt mapping (A through D)*/ - for (i=0; i<=3 ;i++) { - if (readb(&sc520_mmcr->pci_int_map[i]) == sc520_irq[irq].priority) + for (i = 0; i <= 3 ; i++) { + tmpb = readb(&sc520_mmcr->pci_int_map[i]); + + if (tmpb == sc520_irq[irq].priority) writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]); } /* GP IRQ interrupt mapping */ - for (i=0; i<=10 ;i++) { - if (readb(&sc520_mmcr->gp_int_map[i]) == sc520_irq[irq].priority) + for (i = 0; i <= 10 ; i++) { + tmpb = readb(&sc520_mmcr->gp_int_map[i]); + + if (tmpb == sc520_irq[irq].priority) writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]); } @@ -102,10 +104,12 @@ int pci_sc520_set_irq(int pci_pin, int irq) if (pci_pin < 4) { /* PCI INTA-INTD */ /* route the interrupt */ - writeb(sc520_irq[irq].priority, &sc520_mmcr->pci_int_map[pci_pin]); + writeb(sc520_irq[irq].priority, + &sc520_mmcr->pci_int_map[pci_pin]); } else { /* GPIRQ0-GPIRQ10 used for additional PCI INTS */ - writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin - 4]); + writeb(sc520_irq[irq].priority, + &sc520_mmcr->gp_int_map[pci_pin - 4]); /* also set the polarity in this case */ tmpw = readw(&sc520_mmcr->intpinpol); diff --git a/arch/x86/cpu/sc520/sc520_sdram.c b/arch/x86/cpu/sc520/sc520_sdram.c index 57e4e7d..9dc1334 100644 --- a/arch/x86/cpu/sc520/sc520_sdram.c +++ b/arch/x86/cpu/sc520/sc520_sdram.c @@ -40,9 +40,6 @@ static void sc520_set_dram_timing(void); static void sc520_set_dram_refresh_rate(void); static void sc520_enable_dram_refresh(void); static void sc520_enable_sdram(void); -#if CONFIG_SYS_SDRAM_ECC_ENABLE -static void sc520_enable_ecc(void) -#endif int dram_init_f(void) { @@ -51,9 +48,6 @@ int dram_init_f(void) sc520_set_dram_refresh_rate(); sc520_enable_dram_refresh(); sc520_enable_sdram(); -#if CONFIG_SYS_SDRAM_ECC_ENABLE - sc520_enable_ecc(); -#endif return 0; } @@ -426,53 +420,6 @@ static void sc520_sizemem(void) writel(0x00000000, &sc520_mmcr->par[4]); } -#if CONFIG_SYS_SDRAM_ECC_ENABLE -static void sc520_enable_ecc(void) - - /* A nominal memory test: just a byte at each address line */ - movl %eax, %ecx - shrl $0x1, %ecx - movl $0x1, %edi -memtest0: - movb $0xa5, (%edi) - cmpb $0xa5, (%edi) - jne out - shrl $0x1, %ecx - andl %ecx, %ecx - jz set_ecc - shll $0x1, %edi - jmp memtest0 - -set_ecc: - /* clear all ram with a memset */ - movl %eax, %ecx - xorl %esi, %esi - xorl %edi, %edi - xorl %eax, %eax - shrl $0x2, %ecx - cld - rep stosl - - /* enable read, write buffers */ - movb $0x11, %al - movl $DBCTL, %edi - movb %al, (%edi) - - /* enable NMI mapping for ECC */ - movl $ECCINT, %edi - movb $0x10, %al - movb %al, (%edi) - - /* Turn on ECC */ - movl $ECCCTL, %edi - movb $0x05, %al - movb %al,(%edi) - -out: - jmp init_ecc_ret -} -#endif - int dram_init(void) { ulong dram_ctrl; diff --git a/arch/x86/cpu/sc520/sc520_ssi.c b/arch/x86/cpu/sc520/sc520_ssi.c index 3a6a858..cc601e5 100644 --- a/arch/x86/cpu/sc520/sc520_ssi.c +++ b/arch/x86/cpu/sc520/sc520_ssi.c @@ -28,37 +28,33 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) { - u8 temp=0; + u8 temp = 0; - if (freq >= 8192) { + if (freq >= 8192) temp |= CTL_CLK_SEL_4; - } else if (freq >= 4096) { + else if (freq >= 4096) temp |= CTL_CLK_SEL_8; - } else if (freq >= 2048) { + else if (freq >= 2048) temp |= CTL_CLK_SEL_16; - } else if (freq >= 1024) { + else if (freq >= 1024) temp |= CTL_CLK_SEL_32; - } else if (freq >= 512) { + else if (freq >= 512) temp |= CTL_CLK_SEL_64; - } else if (freq >= 256) { + else if (freq >= 256) temp |= CTL_CLK_SEL_128; - } else if (freq >= 128) { + else if (freq >= 128) temp |= CTL_CLK_SEL_256; - } else { + else temp |= CTL_CLK_SEL_512; - } - if (!lsb_first) { + if (!lsb_first) temp |= MSBF_ENB; - } - if (inv_clock) { + if (inv_clock) temp |= CLK_INV_ENB; - } - if (inv_phase) { + if (inv_phase) temp |= PHS_INV_ENB; - } writeb(temp, &sc520_mmcr->ssictl); @@ -68,9 +64,11 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) u8 ssi_txrx_byte(u8 data) { writeb(data, &sc520_mmcr->ssixmit); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; return readb(&sc520_mmcr->ssircv); } @@ -78,15 +76,18 @@ u8 ssi_txrx_byte(u8 data) void ssi_tx_byte(u8 data) { writeb(data, &sc520_mmcr->ssixmit); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd); } u8 ssi_rx_byte(void) { - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; return readb(&sc520_mmcr->ssircv); } diff --git a/arch/x86/cpu/sc520/sc520_timer.c b/arch/x86/cpu/sc520/sc520_timer.c index 05bc9c1..495a694 100644 --- a/arch/x86/cpu/sc520/sc520_timer.c +++ b/arch/x86/cpu/sc520/sc520_timer.c @@ -38,7 +38,7 @@ void sc520_timer_isr(void) int timer_init(void) { /* Register the SC520 specific timer interrupt handler */ - register_timer_isr (sc520_timer_isr); + register_timer_isr(sc520_timer_isr); /* Install interrupt handler for GP Timer 1 */ irq_install_handler (0, timer_isr, NULL); @@ -62,7 +62,7 @@ int timer_init(void) writew(100, &sc520_mmcr->gptmr1maxcmpa); writew(0xe009, &sc520_mmcr->gptmr1ctl); - unmask_irq (0); + unmask_irq(0); /* Clear the GP Timer 1 status register to get the show rolling*/ writeb(0x02, &sc520_mmcr->gptmrsta); -- cgit v0.10.2 From 83088afbba0c142fda5313866abd1e679d0f9e78 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:15 +0000 Subject: cosmetic: checkpatch cleanup of arch/x86/lib/*.c Signed-off-by: Graeme Russ diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 85f60d7..c09078e 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -26,6 +26,9 @@ #ifndef _PCI_I386_H_ #define _PCI_I386_H_ 1 +#define DEFINE_PCI_DEVICE_TABLE(_table) \ + const struct pci_device_id _table[] + void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); int pci_enable_legacy_video_ports(struct pci_controller* hose); int pci_shadow_rom(pci_dev_t dev, unsigned char *dest); diff --git a/arch/x86/include/asm/realmode.h b/arch/x86/include/asm/realmode.h index c62310e..0f12a89 100644 --- a/arch/x86/include/asm/realmode.h +++ b/arch/x86/include/asm/realmode.h @@ -25,6 +25,10 @@ #define __ASM_REALMODE_H_ #include +extern ulong __realmode_start; +extern ulong __realmode_size; +extern char realmode_enter; + int bios_setup(void); int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out); int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out); diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index d3e2f4c..755f88a 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -24,6 +24,14 @@ #ifndef _U_BOOT_I386_H_ #define _U_BOOT_I386_H_ 1 +/* Exports from the Linker Script */ +extern ulong __text_start; +extern ulong __data_end; +extern ulong __rel_dyn_start; +extern ulong __rel_dyn_end; +extern ulong __bss_start; +extern ulong __bss_end; + /* cpu/.../cpu.c */ int x86_cpu_init_r(void); int cpu_init_r(void); diff --git a/arch/x86/lib/bios.h b/arch/x86/lib/bios.h index 4a9cdb5..a220983 100644 --- a/arch/x86/lib/bios.h +++ b/arch/x86/lib/bios.h @@ -24,69 +24,150 @@ #ifndef _BIOS_H_ #define _BIOS_H_ -#define OFFS_ES 0 /* 16bit */ -#define OFFS_GS 2 /* 16bit */ -#define OFFS_DS 4 /* 16bit */ -#define OFFS_EDI 6 /* 32bit */ -#define OFFS_DI 6 /* low 16 bits of EDI */ -#define OFFS_ESI 10 /* 32bit */ -#define OFFS_SI 10 /* low 16 bits of ESI */ -#define OFFS_EBP 14 /* 32bit */ -#define OFFS_BP 14 /* low 16 bits of EBP */ -#define OFFS_ESP 18 /* 32bit */ -#define OFFS_SP 18 /* low 16 bits of ESP */ -#define OFFS_EBX 22 /* 32bit */ -#define OFFS_BX 22 /* low 16 bits of EBX */ -#define OFFS_BL 22 /* low 8 bits of BX */ -#define OFFS_BH 23 /* high 8 bits of BX */ -#define OFFS_EDX 26 /* 32bit */ -#define OFFS_DX 26 /* low 16 bits of EBX */ -#define OFFS_DL 26 /* low 8 bits of BX */ -#define OFFS_DH 27 /* high 8 bits of BX */ -#define OFFS_ECX 30 /* 32bit */ -#define OFFS_CX 30 /* low 16 bits of EBX */ -#define OFFS_CL 30 /* low 8 bits of BX */ -#define OFFS_CH 31 /* high 8 bits of BX */ -#define OFFS_EAX 34 /* 32bit */ -#define OFFS_AX 34 /* low 16 bits of EBX */ -#define OFFS_AL 34 /* low 8 bits of BX */ -#define OFFS_AH 35 /* high 8 bits of BX */ -#define OFFS_VECTOR 38 /* 16bit */ -#define OFFS_IP 40 /* 16bit */ -#define OFFS_CS 42 /* 16bit */ -#define OFFS_FLAGS 44 /* 16bit */ +#define OFFS_ES 0 /* 16bit */ +#define OFFS_GS 2 /* 16bit */ +#define OFFS_DS 4 /* 16bit */ +#define OFFS_EDI 6 /* 32bit */ +#define OFFS_DI 6 /* low 16 bits of EDI */ +#define OFFS_ESI 10 /* 32bit */ +#define OFFS_SI 10 /* low 16 bits of ESI */ +#define OFFS_EBP 14 /* 32bit */ +#define OFFS_BP 14 /* low 16 bits of EBP */ +#define OFFS_ESP 18 /* 32bit */ +#define OFFS_SP 18 /* low 16 bits of ESP */ +#define OFFS_EBX 22 /* 32bit */ +#define OFFS_BX 22 /* low 16 bits of EBX */ +#define OFFS_BL 22 /* low 8 bits of BX */ +#define OFFS_BH 23 /* high 8 bits of BX */ +#define OFFS_EDX 26 /* 32bit */ +#define OFFS_DX 26 /* low 16 bits of EBX */ +#define OFFS_DL 26 /* low 8 bits of BX */ +#define OFFS_DH 27 /* high 8 bits of BX */ +#define OFFS_ECX 30 /* 32bit */ +#define OFFS_CX 30 /* low 16 bits of EBX */ +#define OFFS_CL 30 /* low 8 bits of BX */ +#define OFFS_CH 31 /* high 8 bits of BX */ +#define OFFS_EAX 34 /* 32bit */ +#define OFFS_AX 34 /* low 16 bits of EBX */ +#define OFFS_AL 34 /* low 8 bits of BX */ +#define OFFS_AH 35 /* high 8 bits of BX */ +#define OFFS_VECTOR 38 /* 16bit */ +#define OFFS_IP 40 /* 16bit */ +#define OFFS_CS 42 /* 16bit */ +#define OFFS_FLAGS 44 /* 16bit */ -#define SEGMENT 0x40 -#define STACK 0x800 /* stack at 0x40:0x800 -> 0x800 */ +/* stack at 0x40:0x800 -> 0x800 */ +#define SEGMENT 0x40 +#define STACK 0x800 -/* save general registers */ -/* save some segments */ -/* save callers stack segment .. */ -/* ... in gs */ - /* setup my segments */ - /* setup BIOS stackpointer */ - -#define MAKE_BIOS_STACK \ - pushal; \ - pushw %ds; \ - pushw %gs; \ - pushw %es; \ - pushw %ss; \ - popw %gs; \ - movw $SEGMENT, %ax; \ - movw %ax, %ds; \ - movw %ax, %es; \ - movw %ax, %ss; \ - movw %sp, %bp; \ +/* + * save general registers + * save some segments + * save callers stack segment + * setup BIOS segments + * setup BIOS stackpointer + */ +#define MAKE_BIOS_STACK \ + pushal; \ + pushw %ds; \ + pushw %gs; \ + pushw %es; \ + pushw %ss; \ + popw %gs; \ + movw $SEGMENT, %ax; \ + movw %ax, %ds; \ + movw %ax, %es; \ + movw %ax, %ss; \ + movw %sp, %bp; \ movw $STACK, %sp -#define RESTORE_CALLERS_STACK \ - pushw %gs; /* restore callers stack segment */ \ - popw %ss; \ - movw %bp, %sp; /* restore stackpointer */ \ - popw %es; /* restore segment selectors */ \ - popw %gs; \ - popw %ds; \ - popal /* restore GP registers */ +/* + * restore callers stack segment + * restore some segments + * restore general registers + */ +#define RESTORE_CALLERS_STACK \ + pushw %gs; \ + popw %ss; \ + movw %bp, %sp; \ + popw %es; \ + popw %gs; \ + popw %ds; \ + popal + +#ifndef __ASSEMBLY__ +#define BIOS_DATA ((char *)0x400) +#define BIOS_DATA_SIZE 256 +#define BIOS_BASE ((char *)0xf0000) +#define BIOS_CS 0xf000 + +extern ulong __bios_start; +extern ulong __bios_size; + +/* these are defined in a 16bit segment and needs + * to be accessed with the RELOC_16_xxxx() macros below + */ +extern u16 ram_in_64kb_chunks; +extern u16 bios_equipment; +extern u8 pci_last_bus; + +extern void *rm_int00; +extern void *rm_int01; +extern void *rm_int02; +extern void *rm_int03; +extern void *rm_int04; +extern void *rm_int05; +extern void *rm_int06; +extern void *rm_int07; +extern void *rm_int08; +extern void *rm_int09; +extern void *rm_int0a; +extern void *rm_int0b; +extern void *rm_int0c; +extern void *rm_int0d; +extern void *rm_int0e; +extern void *rm_int0f; +extern void *rm_int10; +extern void *rm_int11; +extern void *rm_int12; +extern void *rm_int13; +extern void *rm_int14; +extern void *rm_int15; +extern void *rm_int16; +extern void *rm_int17; +extern void *rm_int18; +extern void *rm_int19; +extern void *rm_int1a; +extern void *rm_int1b; +extern void *rm_int1c; +extern void *rm_int1d; +extern void *rm_int1e; +extern void *rm_int1f; +extern void *rm_def_int; + +extern void *realmode_reset; +extern void *realmode_pci_bios_call_entry; + +#define RELOC_16_LONG(seg, off) (*(u32 *)(seg << 4 | (u32)&off)) +#define RELOC_16_WORD(seg, off) (*(u16 *)(seg << 4 | (u32)&off)) +#define RELOC_16_BYTE(seg, off) (*(u8 *)(seg << 4 | (u32)&off)) + +#ifdef PCI_BIOS_DEBUG +extern u32 num_pci_bios_present; +extern u32 num_pci_bios_find_device; +extern u32 num_pci_bios_find_class; +extern u32 num_pci_bios_generate_special_cycle; +extern u32 num_pci_bios_read_cfg_byte; +extern u32 num_pci_bios_read_cfg_word; +extern u32 num_pci_bios_read_cfg_dword; +extern u32 num_pci_bios_write_cfg_byte; +extern u32 num_pci_bios_write_cfg_word; +extern u32 num_pci_bios_write_cfg_dword; +extern u32 num_pci_bios_get_irq_routing; +extern u32 num_pci_bios_set_irq; +extern u32 num_pci_bios_unknown_function; +#endif + +#endif #endif diff --git a/arch/x86/lib/bios_pci.S b/arch/x86/lib/bios_pci.S index 53d2ea0..47c478b 100644 --- a/arch/x86/lib/bios_pci.S +++ b/arch/x86/lib/bios_pci.S @@ -80,11 +80,15 @@ cs incl num_pci_bios_present #endif movl $0x20494350, %eax gs movl %eax, OFFS_EDX(%bp) + + /* We support cfg type 1 version 2.10 */ movb $0x01, %al -gs movb %al, OFFS_AL(%bp) /* We support cfg type 1 */ - movw $0x0210, %ax /* version 2.10 */ +gs movb %al, OFFS_AL(%bp) + movw $0x0210, %ax gs movw %ax, OFFS_BX(%bp) -cs movb pci_last_bus, %al /* last bus number */ + + /* last bus number */ +cs movb pci_last_bus, %al gs movb %al, OFFS_CL(%bp) jmp clear_carry @@ -97,16 +101,22 @@ cs incl num_pci_bios_find_device #endif gs movw OFFS_CX(%bp), %di shll $16, %edi -gs movw OFFS_DX(%bp), %di /* edi now holds device in upper 16 - * bits and vendor in lower 16 bits */ +gs movw OFFS_DX(%bp), %di + /* edi now holds device in upper 16 bits and vendor in lower 16 bits */ + gs movw OFFS_SI(%bp), %si - xorw %bx, %bx /* start at bus 0 dev 0 function 0 */ + + /* start at bus 0 dev 0 function 0 */ + xorw %bx, %bx pfd_loop: - xorw %ax, %ax /* dword 0 is vendor/device */ + /* dword 0 is vendor/device */ + xorw %ax, %ax call __pci_bios_select_register movw $0xcfc, %dx inl %dx, %eax - cmpl %edi, %eax /* our device ? */ + + /* our device ? */ + cmpl %edi, %eax je pfd_found_one pfd_next_dev: /* check for multi function devices */ @@ -120,13 +130,16 @@ pfd_next_dev: andb $0x80, %al jz pfd_not_multi_function pfd_function_not_zero: - incw %bx /* next function, overflows in to - * device number, then bus number */ + /* next function, overflows in to device number, then bus number */ + incw %bx jmp pfd_check_bus pfd_not_multi_function: - andw $0xfff8, %bx /* remove function bits */ - addw $0x0008, %bx /* next device, overflows in to bus number */ + /* remove function bits */ + andw $0xfff8, %bx + + /* next device, overflows in to bus number */ + addw $0x0008, %bx pfd_check_bus: cs movb pci_last_bus, %ah cmpb %ah, %bh @@ -142,7 +155,8 @@ gs movw %bx, OFFS_BX(%bp) jmp clear_carry pfd_not_found: - movb $0x86, %ah /* device not found */ + /* device not found */ + movb $0x86, %ah jmp set_carry /*****************************************************************************/ @@ -152,17 +166,24 @@ pci_bios_find_class: cs incl num_pci_bios_find_class #endif gs movl OFFS_ECX(%bp), %edi - andl $0x00ffffff, %edi /* edi now holds class-code in lower 24 bits */ + + /* edi now holds class-code in lower 24 bits */ + andl $0x00ffffff, %edi gs movw OFFS_SI(%bp), %si - xorw %bx, %bx /* start at bus 0 dev 0 function 0 */ + + /* start at bus 0 dev 0 function 0 */ + xorw %bx, %bx pfc_loop: - movw $8, %ax /* dword 8 is class-code high 24bits */ + /* dword 8 is class-code high 24bits */ + movw $8, %ax call __pci_bios_select_register movw $0xcfc, %dx inl %dx, %eax shrl $8, %eax andl $0x00ffffff, %eax - cmpl %edi, %eax /* our device ? */ + + /* our device ? */ + cmpl %edi, %eax je pfc_found_one pfc_next_dev: /* check for multi function devices */ @@ -175,13 +196,16 @@ pfc_next_dev: andb $0x80, %al jz pfc_not_multi_function pfc_function_not_zero: - incw %bx /* next function, overflows in to - * device number, then bus number */ + /* next function, overflows in to device number, then bus number */ + incw %bx jmp pfc_check_bus pfc_not_multi_function: - andw $0xfff8, %bx /* remove function bits */ - addw $0x0008, %bx /* next device, overflows in to bus number */ + /* remove function bits */ + andw $0xfff8, %bx + + /* next device, overflows in to bus number */ + addw $0x0008, %bx pfc_check_bus: cs movb pci_last_bus, %ah cmpb %ah, %bh @@ -197,7 +221,8 @@ gs movw %bx, OFFS_BX(%bp) jmp clear_carry pfc_not_found: - movb $0x86, %ah /* device not found */ + /* device not found */ + movb $0x86, %ah jmp set_carry /*****************************************************************************/ @@ -206,7 +231,8 @@ pci_bios_generate_special_cycle: #ifdef PCI_BIOS_DEBUG cs incl num_pci_bios_generate_special_cycle #endif - movb $0x81, %ah /* function not supported */ + /* function not supported */ + movb $0x81, %ah jmp set_carry /*****************************************************************************/ @@ -296,7 +322,8 @@ pci_bios_get_irq_routing: #ifdef PCI_BIOS_DEBUG cs incl num_pci_bios_get_irq_routing #endif - movb $0x81, %ah /* function not supported */ + /* function not supported */ + movb $0x81, %ah jmp set_carry /*****************************************************************************/ @@ -305,7 +332,8 @@ pci_bios_set_irq: #ifdef PCI_BIOS_DEBUG cs incl num_pci_bios_set_irq #endif - movb $0x81, %ah /* function not supported */ + /* function not supported */ + movb $0x81, %ah jmp set_carry /*****************************************************************************/ @@ -314,7 +342,8 @@ unknown_function: #ifdef PCI_BIOS_DEBUG cs incl num_pci_bios_unknown_function #endif - movb $0x81, %ah /* function not supported */ + /* function not supported */ + movb $0x81, %ah jmp set_carry /*****************************************************************************/ @@ -323,7 +352,8 @@ pci_bios_select_register: gs movw OFFS_BX(%bp), %bx gs movw OFFS_DI(%bp), %ax /* destroys eax, dx */ -__pci_bios_select_register: /* BX holds device id, AX holds register index */ +__pci_bios_select_register: + /* BX holds device id, AX holds register index */ pushl %ebx andl $0xfc, %eax andl $0xffff, %ebx @@ -338,7 +368,9 @@ __pci_bios_select_register: /* BX holds device id, AX holds regist clear_carry: gs movw OFFS_FLAGS(%bp), %ax - andw $0xfffe, %ax /* clear carry -- function succeeded */ + + /* clear carry -- function succeeded */ + andw $0xfffe, %ax gs movw %ax, OFFS_FLAGS(%bp) xorw %ax, %ax gs movb %ah, OFFS_AH(%bp) @@ -347,7 +379,9 @@ gs movb %ah, OFFS_AH(%bp) set_carry: gs movb %ah, OFFS_AH(%bp) gs movw OFFS_FLAGS(%bp), %ax - orw $1, %ax /* return carry -- function not supported */ + + /* return carry -- function not supported */ + orw $1, %ax gs movw %ax, OFFS_FLAGS(%bp) movw $-1, %ax ret diff --git a/arch/x86/lib/bios_setup.c b/arch/x86/lib/bios_setup.c index 9bf7e58..053280b 100644 --- a/arch/x86/lib/bios_setup.c +++ b/arch/x86/lib/bios_setup.c @@ -34,74 +34,22 @@ #include #include #include +#include "bios.h" DECLARE_GLOBAL_DATA_PTR; #define NUMVECTS 256 -#define BIOS_DATA ((char*)0x400) -#define BIOS_DATA_SIZE 256 -#define BIOS_BASE ((char*)0xf0000) -#define BIOS_CS 0xf000 - -extern ulong __bios_start; -extern ulong __bios_size; - -/* these are defined in a 16bit segment and needs - * to be accessed with the RELOC_16_xxxx() macros below - */ -extern u16 ram_in_64kb_chunks; -extern u16 bios_equipment; -extern u8 pci_last_bus; - -extern void *rm_int00; -extern void *rm_int01; -extern void *rm_int02; -extern void *rm_int03; -extern void *rm_int04; -extern void *rm_int05; -extern void *rm_int06; -extern void *rm_int07; -extern void *rm_int08; -extern void *rm_int09; -extern void *rm_int0a; -extern void *rm_int0b; -extern void *rm_int0c; -extern void *rm_int0d; -extern void *rm_int0e; -extern void *rm_int0f; -extern void *rm_int10; -extern void *rm_int11; -extern void *rm_int12; -extern void *rm_int13; -extern void *rm_int14; -extern void *rm_int15; -extern void *rm_int16; -extern void *rm_int17; -extern void *rm_int18; -extern void *rm_int19; -extern void *rm_int1a; -extern void *rm_int1b; -extern void *rm_int1c; -extern void *rm_int1d; -extern void *rm_int1e; -extern void *rm_int1f; -extern void *rm_def_int; - -extern void *realmode_reset; -extern void *realmode_pci_bios_call_entry; - static int set_jmp_vector(int entry_point, void *target) { - if (entry_point & ~0xffff) { + if (entry_point & ~0xffff) return -1; - } - if (((u32)target-0xf0000) & ~0xffff) { + if (((u32)target - 0xf0000) & ~0xffff) return -1; - } + printf("set_jmp_vector: 0xf000:%04x -> %p\n", - entry_point, target); + entry_point, target); /* jmp opcode */ writeb(0xea, 0xf0000 + entry_point); @@ -115,51 +63,41 @@ static int set_jmp_vector(int entry_point, void *target) return 0; } - -/* - ************************************************************ - * Install an interrupt vector - ************************************************************ - */ - +/* Install an interrupt vector */ static void setvector(int vector, u16 segment, void *handler) { - u16 *ptr = (u16*)(vector*4); - ptr[0] = ((u32)handler - (segment << 4))&0xffff; + u16 *ptr = (u16 *)(vector * 4); + ptr[0] = ((u32)handler - (segment << 4)) & 0xffff; ptr[1] = segment; #if 0 printf("setvector: int%02x -> %04x:%04x\n", - vector, ptr[1], ptr[0]); + vector, ptr[1], ptr[0]); #endif } -#define RELOC_16_LONG(seg, off) *(u32*)(seg << 4 | (u32)&off) -#define RELOC_16_WORD(seg, off) *(u16*)(seg << 4 | (u32)&off) -#define RELOC_16_BYTE(seg, off) *(u8*)(seg << 4 | (u32)&off) - int bios_setup(void) { ulong bios_start = (ulong)&__bios_start + gd->reloc_off; ulong bios_size = (ulong)&__bios_size; - static int done=0; + static int done; int vector; #ifdef CONFIG_PCI struct pci_controller *pri_hose; #endif - if (done) { + if (done) return 0; - } + done = 1; if (bios_size > 65536) { printf("BIOS too large (%ld bytes, max is 65536)\n", - bios_size); + bios_size); return -1; } - memcpy(BIOS_BASE, (void*)bios_start, bios_size); + memcpy(BIOS_BASE, (void *)bios_start, bios_size); /* clear bda */ memset(BIOS_DATA, 0, BIOS_DATA_SIZE); @@ -178,9 +116,8 @@ int bios_setup(void) /* setup realmode interrupt vectors */ - for (vector = 0; vector < NUMVECTS; vector++) { + for (vector = 0; vector < NUMVECTS; vector++) setvector(vector, BIOS_CS, &rm_def_int); - } setvector(0x00, BIOS_CS, &rm_int00); setvector(0x01, BIOS_CS, &rm_int01); diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c index 8963580..e8227b1 100644 --- a/arch/x86/lib/board.c +++ b/arch/x86/lib/board.c @@ -56,15 +56,6 @@ #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); - -/* Exports from the Linker Script */ -extern ulong __text_start; -extern ulong __data_end; -extern ulong __rel_dyn_start; -extern ulong __rel_dyn_end; -extern ulong __bss_start; -extern ulong __bss_end; - /************************************************************************ * Init Utilities * ************************************************************************ @@ -72,48 +63,38 @@ extern ulong __bss_end; * or dropped completely, * but let's get it working (again) first... */ -static int init_baudrate (void) +static int init_baudrate(void) { gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); return 0; } -static int display_banner (void) +static int display_banner(void) { - printf ("\n\n%s\n\n", version_string); -/* - printf ("U-Boot code: %08lX -> %08lX data: %08lX -> %08lX\n" - " BSS: %08lX -> %08lX stack: %08lX -> %08lX\n", - i386boot_start, i386boot_romdata_start-1, - i386boot_romdata_dest, i386boot_romdata_dest+i386boot_romdata_size-1, - i386boot_bss_start, i386boot_bss_start+i386boot_bss_size-1, - i386boot_bss_start+i386boot_bss_size, - i386boot_bss_start+i386boot_bss_size+CONFIG_SYS_STACK_SIZE-1); - -*/ + printf("\n\n%s\n\n", version_string); - return (0); + return 0; } -static int display_dram_config (void) +static int display_dram_config(void) { int i; - puts ("DRAM Configuration:\n"); + puts("DRAM Configuration:\n"); - for (i=0; ibd->bi_dram[i].start); - print_size (gd->bd->bi_dram[i].size, "\n"); + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); + print_size(gd->bd->bi_dram[i].size, "\n"); } - return (0); + return 0; } -static void display_flash_config (ulong size) +static void display_flash_config(ulong size) { - puts ("Flash: "); - print_size (size, "\n"); + puts("Flash: "); + print_size(size, "\n"); } /* @@ -214,7 +195,7 @@ static int clear_bss(void) void *bss_end = &__bss_end; ulong *dst_addr = (ulong *)(bss_start + gd->reloc_off); - ulong *end_addr = (ulong *)(bss_end + gd->reloc_off);; + ulong *end_addr = (ulong *)(bss_end + gd->reloc_off); while (dst_addr < end_addr) *dst_addr++ = 0x00000000; @@ -227,10 +208,23 @@ static int do_elf_reloc_fixups(void) Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start); Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end); + Elf32_Addr *offset_ptr_rom; + Elf32_Addr *offset_ptr_ram; + do { - if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE) - if (*(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) >= CONFIG_SYS_TEXT_BASE) - *(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) += gd->reloc_off; + /* Get the location from the relocation entry */ + offset_ptr_rom = (Elf32_Addr *)re_src->r_offset; + + /* Check that the location of the relocation is in .text */ + if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE) { + + /* Switch to the in-RAM version */ + offset_ptr_ram = offset_ptr_rom + gd->reloc_off; + + /* Check that the target points into .text */ + if (*offset_ptr_ram >= CONFIG_SYS_TEXT_BASE) + *offset_ptr_ram += gd->reloc_off; + } } while (re_src++ < re_end); return 0; @@ -254,7 +248,8 @@ void board_init_f(ulong boot_flags) relocate_code(gd->start_addr_sp, gd, gd->relocaddr); /* NOTREACHED - relocate_code() does not return */ - while(1); + while (1) + ; } void board_init_r(gd_t *id, ulong dest_addr) @@ -272,10 +267,10 @@ void board_init_r(gd_t *id, ulong dest_addr) memcpy(gd, id, sizeof(gd_t)); /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); + __asm__ __volatile__("" : : : "memory"); gd->bd = &bd_data; - memset (gd->bd, 0, sizeof (bd_t)); + memset(gd->bd, 0, sizeof(bd_t)); show_boot_progress(0x22); gd->baudrate = CONFIG_BAUDRATE; @@ -285,7 +280,7 @@ void board_init_r(gd_t *id, ulong dest_addr) for (init_fnc_ptr = init_sequence_r; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) - hang (); + hang(); } show_boot_progress(0x23); @@ -300,13 +295,13 @@ void board_init_r(gd_t *id, ulong dest_addr) show_boot_progress(0x25); /* initialize environment */ - env_relocate (); + env_relocate(); show_boot_progress(0x26); #ifdef CONFIG_CMD_NET /* IP Address */ - bd_data.bi_ip_addr = getenv_IPaddr ("ipaddr"); + bd_data.bi_ip_addr = getenv_IPaddr("ipaddr"); #endif #if defined(CONFIG_PCI) @@ -319,9 +314,9 @@ void board_init_r(gd_t *id, ulong dest_addr) show_boot_progress(0x27); - stdio_init (); + stdio_init(); - jumptable_init (); + jumptable_init(); /* Initialize the console (after the relocation and devices init) */ console_init_r(); @@ -333,7 +328,7 @@ void board_init_r(gd_t *id, ulong dest_addr) #if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE) WATCHDOG_RESET(); - puts ("PCMCIA:"); + puts("PCMCIA:"); pcmcia_init(); #endif @@ -348,7 +343,7 @@ void board_init_r(gd_t *id, ulong dest_addr) show_boot_progress(0x28); #ifdef CONFIG_STATUS_LED - status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); + status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); #endif udelay(20); @@ -356,9 +351,10 @@ void board_init_r(gd_t *id, ulong dest_addr) /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); #if defined(CONFIG_CMD_NET) - if ((s = getenv ("bootfile")) != NULL) { - copy_filename (BootFile, s, sizeof (BootFile)); - } + s = getenv("bootfile"); + + if (s != NULL) + copy_filename(BootFile, s, sizeof(BootFile)); #endif WATCHDOG_RESET(); @@ -390,10 +386,10 @@ void board_init_r(gd_t *id, ulong dest_addr) eth_initialize(gd->bd); #endif -#if ( defined(CONFIG_CMD_NET)) && (0) +#if (defined(CONFIG_CMD_NET)) && (0) WATCHDOG_RESET(); # ifdef DEBUG - puts ("Reset Ethernet PHY\n"); + puts("Reset Ethernet PHY\n"); # endif reset_phy(); #endif @@ -410,27 +406,27 @@ void board_init_r(gd_t *id, ulong dest_addr) #ifdef CONFIG_POST - post_run (NULL, POST_RAM | post_bootmode_get(0)); + post_run(NULL, POST_RAM | post_bootmode_get(0)); #endif - show_boot_progress(0x29); /* main_loop() can return to retry autoboot, if so just run it again. */ - for (;;) { + for (;;) main_loop(); - } /* NOTREACHED - no way out of command loop except booting */ } -void hang (void) +void hang(void) { - puts ("### ERROR ### Please RESET the board ###\n"); - for (;;); + puts("### ERROR ### Please RESET the board ###\n"); + for (;;) + ; } -unsigned long do_go_exec (ulong (*entry)(int, char * const []), int argc, char * const argv[]) +unsigned long do_go_exec(ulong (*entry)(int, char * const []), + int argc, char * const argv[]) { unsigned long ret = 0; char **argv_tmp; diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index a21a21f..836803c 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -32,7 +32,8 @@ #include /*cmd_boot.c*/ -int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images) +int do_bootm_linux(int flag, int argc, char * const argv[], + bootm_headers_t *images) { void *base_ptr; ulong os_data, os_len; @@ -48,41 +49,41 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima if (images->legacy_hdr_valid) { hdr = images->legacy_hdr_os; - if (image_check_type (hdr, IH_TYPE_MULTI)) { + if (image_check_type(hdr, IH_TYPE_MULTI)) { /* if multi-part image, we need to get first subimage */ - image_multi_getimg (hdr, 0, &os_data, &os_len); + image_multi_getimg(hdr, 0, &os_data, &os_len); } else { /* otherwise get image data */ - os_data = image_get_data (hdr); - os_len = image_get_data_size (hdr); + os_data = image_get_data(hdr); + os_len = image_get_data_size(hdr); } #if defined(CONFIG_FIT) } else if (images->fit_uname_os) { - ret = fit_image_get_data (images->fit_hdr_os, + ret = fit_image_get_data(images->fit_hdr_os, images->fit_noffset_os, &data, &len); if (ret) { - puts ("Can't get image data/size!\n"); + puts("Can't get image data/size!\n"); goto error; } os_data = (ulong)data; os_len = (ulong)len; #endif } else { - puts ("Could not find kernel image!\n"); + puts("Could not find kernel image!\n"); goto error; } - base_ptr = load_zimage ((void*)os_data, os_len, + base_ptr = load_zimage((void *)os_data, os_len, images->rd_start, images->rd_end - images->rd_start, 0); if (NULL == base_ptr) { - printf ("## Kernel loading failed ...\n"); + printf("## Kernel loading failed ...\n"); goto error; } #ifdef DEBUG - printf ("## Transferring control to Linux (at address %08x) ...\n", + printf("## Transferring control to Linux (at address %08x) ...\n", (u32)base_ptr); #endif diff --git a/arch/x86/lib/interrupts.c b/arch/x86/lib/interrupts.c index 04a9c79..76fbe9d 100644 --- a/arch/x86/lib/interrupts.c +++ b/arch/x86/lib/interrupts.c @@ -56,8 +56,8 @@ struct irq_action { }; static struct irq_action irq_handlers[CONFIG_SYS_NUM_IRQS] = { {0} }; -static int spurious_irq_cnt = 0; -static int spurious_irq = 0; +static int spurious_irq_cnt; +static int spurious_irq; void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg) { @@ -70,10 +70,10 @@ void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg) if (irq_handlers[irq].handler != NULL) printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n", - (ulong) handler, - (ulong) irq_handlers[irq].handler); + (ulong) handler, + (ulong) irq_handlers[irq].handler); - status = disable_interrupts (); + status = disable_interrupts(); irq_handlers[irq].handler = handler; irq_handlers[irq].arg = arg; @@ -96,7 +96,7 @@ void irq_free_handler(int irq) return; } - status = disable_interrupts (); + status = disable_interrupts(); mask_irq(irq); @@ -141,14 +141,14 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int irq; printf("Spurious IRQ: %u, last unknown IRQ: %d\n", - spurious_irq_cnt, spurious_irq); + spurious_irq_cnt, spurious_irq); - printf ("Interrupt-Information:\n"); - printf ("Nr Routine Arg Count\n"); + printf("Interrupt-Information:\n"); + printf("Nr Routine Arg Count\n"); for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) { if (irq_handlers[irq].handler != NULL) { - printf ("%02d %08lx %08lx %d\n", + printf("%02d %08lx %08lx %d\n", irq, (ulong)irq_handlers[irq].handler, (ulong)irq_handlers[irq].arg, diff --git a/arch/x86/lib/pcat_interrupts.c b/arch/x86/lib/pcat_interrupts.c index 2caae20..5dac498 100644 --- a/arch/x86/lib/pcat_interrupts.c +++ b/arch/x86/lib/pcat_interrupts.c @@ -76,7 +76,7 @@ int interrupt_init(void) * Enable cascaded interrupts by unmasking the cascade IRQ pin of * the master PIC */ - unmask_irq (2); + unmask_irq(2); enable_interrupts(); diff --git a/arch/x86/lib/pcat_timer.c b/arch/x86/lib/pcat_timer.c index f2a5422..6b3db69 100644 --- a/arch/x86/lib/pcat_timer.c +++ b/arch/x86/lib/pcat_timer.c @@ -30,7 +30,7 @@ #define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */ #define TIMER2_VALUE 0x0a8e /* 440Hz */ -static int timer_init_done = 0; +static int timer_init_done; int timer_init(void) { @@ -42,18 +42,18 @@ int timer_init(void) * (to stasrt a beep: write 3 to port 0x61, * to stop it again: write 0) */ - outb (PIT_CMD_CTR0 | PIT_CMD_BOTH | PIT_CMD_MODE2, - PIT_BASE + PIT_COMMAND); - outb (TIMER0_VALUE & 0xff, PIT_BASE + PIT_T0); - outb (TIMER0_VALUE >> 8, PIT_BASE + PIT_T0); + outb(PIT_CMD_CTR0 | PIT_CMD_BOTH | PIT_CMD_MODE2, + PIT_BASE + PIT_COMMAND); + outb(TIMER0_VALUE & 0xff, PIT_BASE + PIT_T0); + outb(TIMER0_VALUE >> 8, PIT_BASE + PIT_T0); - outb (PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3, - PIT_BASE + PIT_COMMAND); - outb (TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2); - outb (TIMER2_VALUE >> 8, PIT_BASE + PIT_T2); + outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3, + PIT_BASE + PIT_COMMAND); + outb(TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2); + outb(TIMER2_VALUE >> 8, PIT_BASE + PIT_T2); - irq_install_handler (0, timer_isr, NULL); - unmask_irq (0); + irq_install_handler(0, timer_isr, NULL); + unmask_irq(0); timer_init_done = 1; @@ -64,21 +64,20 @@ static u16 read_pit(void) { u8 low; - outb (PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND); - low = inb (PIT_BASE + PIT_T0); + outb(PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND); + low = inb(PIT_BASE + PIT_T0); - return ((inb (PIT_BASE + PIT_T0) << 8) | low); + return (inb(PIT_BASE + PIT_T0) << 8) | low; } /* this is not very exact */ -void __udelay (unsigned long usec) +void __udelay(unsigned long usec) { int counter; int wraps; - if (timer_init_done) - { - counter = read_pit (); + if (timer_init_done) { + counter = read_pit(); wraps = usec / 1000; usec = usec % 1000; @@ -92,7 +91,7 @@ void __udelay (unsigned long usec) } while (1) { - int new_count = read_pit (); + int new_count = read_pit(); if (((new_count < usec) && !wraps) || wraps < 0) break; diff --git a/arch/x86/lib/pci.c b/arch/x86/lib/pci.c index 593a7db..f3018b7 100644 --- a/arch/x86/lib/pci.c +++ b/arch/x86/lib/pci.c @@ -42,11 +42,13 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) u16 device; u32 class_code; + u32 pci_data; + hose = pci_bus_to_hose(PCI_BUS(dev)); -#if 0 - printf("pci_shadow_rom() asked to shadow device %x to %x\n", + + debug("pci_shadow_rom() asked to shadow device %x to %x\n", dev, (u32)dest); -#endif + pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); pci_read_config_word(dev, PCI_DEVICE_ID, &device); pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_code); @@ -67,7 +69,7 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) return -1; } - size = (~(addr_reg&PCI_ROM_ADDRESS_MASK))+1; + size = (~(addr_reg&PCI_ROM_ADDRESS_MASK)) + 1; debug("ROM is %d bytes\n", size); @@ -80,27 +82,25 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) |PCI_ROM_ADDRESS_ENABLE); - for (i=rom_addr;i #include -#define cfg_read(val, addr, op) *val = op((int)(addr)) +#define cfg_read(val, addr, op) (*val = op((int)(addr))) #define cfg_write(val, addr, op) op((val), (int)(addr)) #define TYPE1_PCI_OP(rw, size, type, op, mask) \ @@ -42,7 +42,6 @@ type1_##rw##_config_##size(struct pci_controller *hose, \ return 0; \ } - TYPE1_PCI_OP(read, byte, u8 *, inb, 3) TYPE1_PCI_OP(read, word, u16 *, inw, 2) TYPE1_PCI_OP(read, dword, u32 *, inl, 0) @@ -51,7 +50,7 @@ TYPE1_PCI_OP(write, byte, u8, outb, 3) TYPE1_PCI_OP(write, word, u16, outw, 2) TYPE1_PCI_OP(write, dword, u32, outl, 0) -void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) +void pci_setup_type1(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) { pci_set_ops(hose, type1_read_config_byte, @@ -61,6 +60,6 @@ void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) type1_write_config_word, type1_write_config_dword); - hose->cfg_addr = (unsigned int *) cfg_addr; - hose->cfg_data = (unsigned char *) cfg_data; + hose->cfg_addr = (unsigned int *)cfg_addr; + hose->cfg_data = (unsigned char *)cfg_data; } diff --git a/arch/x86/lib/realmode.c b/arch/x86/lib/realmode.c index 6aa0f23..5a525ee 100644 --- a/arch/x86/lib/realmode.c +++ b/arch/x86/lib/realmode.c @@ -26,11 +26,7 @@ #include #include -#define REALMODE_MAILBOX ((char*)0xe00) - -extern ulong __realmode_start; -extern ulong __realmode_size; -extern char realmode_enter; +#define REALMODE_MAILBOX ((char *)0xe00) int realmode_setup(void) { @@ -63,15 +59,14 @@ int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out) in->eip = off; in->xcs = seg; - if (3>(in->esp & 0xffff)) { + if ((in->esp & 0xffff) < 4) printf("Warning: entering realmode with sp < 4 will fail\n"); - } memcpy(REALMODE_MAILBOX, in, sizeof(struct pt_regs)); asm("wbinvd\n"); __asm__ volatile ( - "lcall $0x20,%0\n" : : "i" (&realmode_enter) ); + "lcall $0x20,%0\n" : : "i" (&realmode_enter)); asm("wbinvd\n"); memcpy(out, REALMODE_MAILBOX, sizeof(struct pt_regs)); @@ -79,9 +74,10 @@ int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out) return out->eax; } - -/* This code is supposed to access a realmode interrupt - * it does currently not work for me */ +/* + * This code is supposed to access a realmode interrupt + * it does currently not work for me + */ int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out) { /* place two instructions at 0x700 */ @@ -92,5 +88,5 @@ int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out) enter_realmode(0x00, 0x700, in, out); - return out->eflags&1; + return out->eflags & 0x00000001; } diff --git a/arch/x86/lib/timer.c b/arch/x86/lib/timer.c index 8b1bde7..fd7032e 100644 --- a/arch/x86/lib/timer.c +++ b/arch/x86/lib/timer.c @@ -35,15 +35,15 @@ struct timer_isr_function { timer_fnc_t *isr_func; }; -static struct timer_isr_function *first_timer_isr = NULL; -static volatile unsigned long system_ticks = 0; +static struct timer_isr_function *first_timer_isr; +static unsigned long system_ticks; /* * register_timer_isr() allows multiple architecture and board specific * functions to be called every millisecond. Keep the execution time of * each function as low as possible */ -int register_timer_isr (timer_fnc_t *isr_func) +int register_timer_isr(timer_fnc_t *isr_func) { struct timer_isr_function *new_func; struct timer_isr_function *temp; @@ -61,7 +61,7 @@ int register_timer_isr (timer_fnc_t *isr_func) * Don't allow timer interrupts while the * linked list is being modified */ - flag = disable_interrupts (); + flag = disable_interrupts(); if (first_timer_isr == NULL) { first_timer_isr = new_func; @@ -73,7 +73,7 @@ int register_timer_isr (timer_fnc_t *isr_func) } if (flag) - enable_interrupts (); + enable_interrupts(); return 0; } @@ -89,12 +89,12 @@ void timer_isr(void *unused) /* Execute each registered function */ while (temp != NULL) { - temp->isr_func (); + temp->isr_func(); temp = temp->next; } } -ulong get_timer (ulong base) +ulong get_timer(ulong base) { - return (system_ticks - base); + return system_ticks - base; } diff --git a/arch/x86/lib/video.c b/arch/x86/lib/video.c index 0efcf3f..3d6b24d 100644 --- a/arch/x86/lib/video.c +++ b/arch/x86/lib/video.c @@ -123,7 +123,7 @@ static void __video_putc(const char c, int *x, int *y) static void video_putc(const char c) { - int x,y,pos; + int x, y, pos; x = orig_x; y = orig_y; @@ -142,7 +142,7 @@ static void video_putc(const char c) static void video_puts(const char *s) { - int x,y,pos; + int x, y, pos; char c; x = orig_x; @@ -187,7 +187,7 @@ int video_init(void) printf("pos %x %d %d\n", pos, orig_x, orig_y); #endif if (orig_y > lines) - orig_x = orig_y =0; + orig_x = orig_y = 0; memset(&vga_dev, 0, sizeof(vga_dev)); strcpy(vga_dev.name, "vga"); diff --git a/arch/x86/lib/video_bios.c b/arch/x86/lib/video_bios.c index 7574f77..f89f7d6 100644 --- a/arch/x86/lib/video_bios.c +++ b/arch/x86/lib/video_bios.c @@ -28,86 +28,94 @@ #include #include #include +#include "bios.h" #undef PCI_BIOS_DEBUG #undef VGA_BIOS_DEBUG #ifdef VGA_BIOS_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) +#define PRINTF(fmt, args...) printf(fmt, ##args) #else -#define PRINTF(fmt,args...) +#define PRINTF(fmt, args...) #endif #ifdef CONFIG_PCI #ifdef PCI_BIOS_DEBUG -#define RELOC_16(seg, off) *(u32*)(seg << 4 | (u32)&off) -extern u32 num_pci_bios_present; -extern u32 num_pci_bios_find_device; -extern u32 num_pci_bios_find_class; -extern u32 num_pci_bios_generate_special_cycle; -extern u32 num_pci_bios_read_cfg_byte; -extern u32 num_pci_bios_read_cfg_word; -extern u32 num_pci_bios_read_cfg_dword; -extern u32 num_pci_bios_write_cfg_byte; -extern u32 num_pci_bios_write_cfg_word; -extern u32 num_pci_bios_write_cfg_dword; -extern u32 num_pci_bios_get_irq_routing; -extern u32 num_pci_bios_set_irq; -extern u32 num_pci_bios_unknown_function; - void print_bios_bios_stat(void) { printf("16 bit functions:\n"); - printf("pci_bios_present: %d\n", RELOC_16(0xf000, num_pci_bios_present)); - printf("pci_bios_find_device: %d\n", RELOC_16(0xf000, num_pci_bios_find_device)); - printf("pci_bios_find_class: %d\n", RELOC_16(0xf000, num_pci_bios_find_class)); - printf("pci_bios_generate_special_cycle: %d\n", RELOC_16(0xf000, num_pci_bios_generate_special_cycle)); - printf("pci_bios_read_cfg_byte: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_byte)); - printf("pci_bios_read_cfg_word: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_word)); - printf("pci_bios_read_cfg_dword: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_dword)); - printf("pci_bios_write_cfg_byte: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_byte)); - printf("pci_bios_write_cfg_word: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_word)); - printf("pci_bios_write_cfg_dword: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_dword)); - printf("pci_bios_get_irq_routing: %d\n", RELOC_16(0xf000, num_pci_bios_get_irq_routing)); - printf("pci_bios_set_irq: %d\n", RELOC_16(0xf000, num_pci_bios_set_irq)); - printf("pci_bios_unknown_function: %d\n", RELOC_16(0xf000, num_pci_bios_unknown_function)); + printf("pci_bios_present: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_present)); + printf("pci_bios_find_device: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_find_device)); + printf("pci_bios_find_class: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_find_class)); + printf("pci_bios_generate_special_cycle: %d\n", + RELOC_16_LONG(0xf000, + num_pci_bios_generate_special_cycle)); + printf("pci_bios_read_cfg_byte: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_byte)); + printf("pci_bios_read_cfg_word: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_word)); + printf("pci_bios_read_cfg_dword: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_dword)); + printf("pci_bios_write_cfg_byte: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_byte)); + printf("pci_bios_write_cfg_word: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_word)); + printf("pci_bios_write_cfg_dword: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_dword)); + printf("pci_bios_get_irq_routing: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_get_irq_routing)); + printf("pci_bios_set_irq: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_set_irq)); + printf("pci_bios_unknown_function: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_unknown_function)); } #endif #ifdef CONFIG_VIDEO -#define PCI_CLASS_VIDEO 3 -#define PCI_CLASS_VIDEO_STD 0 -#define PCI_CLASS_VIDEO_PROG_IF_VGA 0 +#define PCI_CLASS_VIDEO 3 +#define PCI_CLASS_VIDEO_STD 0 +#define PCI_CLASS_VIDEO_PROG_IF_VGA 0 -static struct pci_device_id supported[] = { +DEFINE_PCI_DEVICE_TABLE(supported) = { {PCI_VIDEO_VENDOR_ID, PCI_VIDEO_DEVICE_ID}, {} }; static u32 probe_pci_video(void) { - pci_dev_t devbusfn; + struct pci_controller *hose; + pci_dev_t devbusfn = pci_find_devices(supported, 0); - if ((devbusfn = pci_find_devices(supported, 0) != -1)) { + if ((devbusfn != -1)) { u32 old; u32 addr; /* PCI video device detected */ printf("Found PCI VGA device at %02x.%02x.%x\n", - PCI_BUS(devbusfn), PCI_DEV(devbusfn), PCI_FUNC(devbusfn)); + PCI_BUS(devbusfn), + PCI_DEV(devbusfn), + PCI_FUNC(devbusfn)); /* Enable I/O decoding as well, PCI viudeo boards * support I/O accesses, but they provide no * bar register for this since the ports are fixed. */ - pci_write_config_word(devbusfn, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER); + pci_write_config_word(devbusfn, + PCI_COMMAND, + PCI_COMMAND_MEMORY | + PCI_COMMAND_IO | + PCI_COMMAND_MASTER); /* Test the ROM decoder, do the device support a rom? */ pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &old); - pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK); + pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, + (u32)PCI_ROM_ADDRESS_MASK); pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &addr); pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, old); @@ -117,13 +125,14 @@ static u32 probe_pci_video(void) } /* device have a rom */ - if (pci_shadow_rom(devbusfn, (void*)0xc0000)) { + if (pci_shadow_rom(devbusfn, (void *)0xc0000)) { printf("Shadowing of PCI VGA BIOS failed\n"); return 0; } /* Now enable lagacy VGA port access */ - if (pci_enable_legacy_video_ports(pci_bus_to_hose(PCI_BUS(devbusfn)))) { + hose = pci_bus_to_hose(PCI_BUS(devbusfn)); + if (pci_enable_legacy_video_ports(hose)) { printf("PCI VGA enable failed\n"); return 0; } @@ -131,7 +140,7 @@ static u32 probe_pci_video(void) /* return the pci device info, that we'll need later */ return PCI_BUS(devbusfn) << 8 | - PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn)&7); + PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn) & 7); } return 0; @@ -142,13 +151,17 @@ static int probe_isa_video(void) u32 ptr; char *buf; - if (0 == (ptr = isa_map_rom(0xc0000, 0x8000))) { + ptr = isa_map_rom(0xc0000, 0x8000); + + if (!ptr) return -1; - } - if (NULL == (buf=malloc(0x8000))) { + + buf = malloc(0x8000); + if (!buf) { isa_unmap_rom(ptr); return -1; } + if (readw(ptr) != 0xaa55) { free(buf); isa_unmap_rom(ptr); @@ -156,9 +169,9 @@ static int probe_isa_video(void) } /* shadow the rom */ - memcpy(buf, (void*)ptr, 0x8000); + memcpy(buf, (void *)ptr, 0x8000); isa_unmap_rom(ptr); - memcpy((void*)0xc0000, buf, 0x8000); + memcpy((void *)0xc0000, buf, 0x8000); free(buf); @@ -168,35 +181,35 @@ static int probe_isa_video(void) int video_bios_init(void) { struct pt_regs regs; + int size; + int i; + u8 sum; /* clear the video bios area in case we warmbooted */ - memset((void*)0xc0000, 0, 0x8000); + memset((void *)0xc0000, 0, 0x8000); memset(®s, 0, sizeof(struct pt_regs)); - if (probe_isa_video()) { + if (probe_isa_video()) /* No ISA board found, try the PCI bus */ regs.eax = probe_pci_video(); - } /* Did we succeed in mapping any video bios */ if (readw(0xc0000) == 0xaa55) { - int size; - int i; - u8 sum; - PRINTF("Found video bios signature\n"); - size = 512*readb(0xc0002); + size = readb(0xc0002) * 512; PRINTF("size %d\n", size); - sum=0; - for (i=0;iboot_flag) { printf("Error: Invalid Boot Flag (found 0x%04x, expected 0x%04x)\n", - hdr->boot_flag, KERNEL_MAGIC); + hdr->boot_flag, KERNEL_MAGIC); return 0; } else { printf("Valid Boot Flag\n"); @@ -124,43 +123,50 @@ void *load_zimage(char *image, unsigned long kernel_size, printf("Setup Size = 0x%8.8lx\n", (ulong)setup_size); - if (setup_size > SETUP_MAX_SIZE) { + if (setup_size > SETUP_MAX_SIZE) printf("Error: Setup is too large (%d bytes)\n", setup_size); - } /* Determine image type */ - big_image = (bootproto >= 0x0200) && (hdr->loadflags & BIG_KERNEL_FLAG); + big_image = (bootproto >= 0x0200) && + (hdr->loadflags & BIG_KERNEL_FLAG); /* Determine load address */ - load_address = (void*)(big_image ? BZIMAGE_LOAD_ADDR : ZIMAGE_LOAD_ADDR); + load_address = (void *)(big_image ? + BZIMAGE_LOAD_ADDR : + ZIMAGE_LOAD_ADDR); /* load setup */ - printf("Moving Real-Mode Code to 0x%8.8lx (%d bytes)\n", (ulong)setup_base, setup_size); + printf("Moving Real-Mode Code to 0x%8.8lx (%d bytes)\n", + (ulong)setup_base, setup_size); memmove(setup_base, image, setup_size); printf("Using boot protocol version %x.%02x\n", (bootproto & 0xff00) >> 8, bootproto & 0xff); if (bootproto == 0x0100) { + *(u16 *)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC; + *(u16 *)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET; - *(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC; - *(u16*)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET; - - /* A very old kernel MUST have its real-mode code - * loaded at 0x90000 */ - + /* + * A very old kernel MUST have its real-mode code + * loaded at 0x90000 + */ if ((u32)setup_base != 0x90000) { /* Copy the real-mode kernel */ - memmove((void*)0x90000, setup_base, setup_size); + memmove((void *)0x90000, setup_base, setup_size); + /* Copy the command line */ - memmove((void*)0x99000, setup_base+COMMAND_LINE_OFFSET, - COMMAND_LINE_SIZE); + memmove((void *)0x99000, + setup_base + COMMAND_LINE_OFFSET, + COMMAND_LINE_SIZE); - setup_base = (void*)0x90000; /* Relocated */ + /* Relocated */ + setup_base = (void *)0x90000; } /* It is recommended to clear memory up to the 32K mark */ - memset((void*)0x90000 + setup_size, 0, SETUP_MAX_SIZE-setup_size); + memset((void *)0x90000 + setup_size, 0, + SETUP_MAX_SIZE-setup_size); } /* We are now setting up the real-mode version of the header */ @@ -170,8 +176,9 @@ void *load_zimage(char *image, unsigned long kernel_size, hdr->type_of_loader = 8; if (hdr->setup_sects >= 15) - printf("Linux kernel version %s\n", (char *) - (setup_base + (hdr->kernel_version + 0x200))); + printf("Linux kernel version %s\n", + (char *)(setup_base + + (hdr->kernel_version + 0x200))); else printf("Setup Sectors < 15 - Cannot print kernel version.\n"); @@ -193,8 +200,8 @@ void *load_zimage(char *image, unsigned long kernel_size, hdr->cmd_line_ptr = (u32)setup_base + COMMAND_LINE_OFFSET; } else if (bootproto >= 0x0200) { - *(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC; - *(u16*)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET; + *(u16 *)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC; + *(u16 *)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET; hdr->setup_move_size = 0x9100; } @@ -221,8 +228,8 @@ void *load_zimage(char *image, unsigned long kernel_size, /* build command line at COMMAND_LINE_OFFSET */ build_command_line(setup_base + COMMAND_LINE_OFFSET, auto_boot); - printf("Loading %czImage at address 0x%08x (%ld bytes)\n", big_image ? 'b' : ' ', - (u32)load_address, kernel_size); + printf("Loading %czImage at address 0x%08x (%ld bytes)\n", + big_image ? 'b' : ' ', (u32)load_address, kernel_size); memmove(load_address, image + setup_size, kernel_size); @@ -241,10 +248,11 @@ void boot_zimage(void *setup_base) regs.xss = regs.xds; regs.esp = 0x9000; regs.eflags = 0; - enter_realmode(((u32)setup_base+SETUP_START_OFFSET)>>4, 0, ®s, ®s); + enter_realmode(((u32)setup_base+SETUP_START_OFFSET)>>4, 0, ®s, + ®s); } -int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { void *base_ptr; void *bzImage_addr = NULL; @@ -270,12 +278,12 @@ int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) bzImage_size = simple_strtoul(argv[2], NULL, 16); /* Lets look for*/ - base_ptr = load_zimage (bzImage_addr, bzImage_size, 0, 0, 0); + base_ptr = load_zimage(bzImage_addr, bzImage_size, 0, 0, 0); - if (NULL == base_ptr) { - printf ("## Kernel loading failed ...\n"); + if (!base_ptr) { + printf("## Kernel loading failed ...\n"); } else { - printf ("## Transferring control to Linux (at address %08x) ...\n", + printf("## Transferring control to Linux (at address %08x) ...\n", (u32)base_ptr); /* we assume that the kernel is in place */ -- cgit v0.10.2 From 63a90bfb7e2794489acc708835958e1e4a6ea1d6 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:16 +0000 Subject: cosmetic: checkpatch cleanup of board/eNET/*.c Signed-off-by: Graeme Russ diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index c4ed820..429fe1b 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -223,7 +223,7 @@ void setup_pcat_compatibility() * active low polarity on PIC interrupt pins, * active high polarity on all other irq pins */ - writew(0x0000,&sc520_mmcr->intpinpol); + writew(0x0000, &sc520_mmcr->intpinpol); /* * PIT 0 -> IRQ0 @@ -252,7 +252,7 @@ void setup_pcat_compatibility() void enet_timer_isr(void) { - static long enet_ticks = 0; + static long enet_ticks; enet_ticks++; @@ -281,9 +281,9 @@ void hw_watchdog_reset(void) void enet_toggle_run_led(void) { - unsigned char leds_state= inb(LED_LATCH_ADDRESS); + unsigned char leds_state = inb(LED_LATCH_ADDRESS); if (leds_state & LED_RUN_BITMASK) - outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS); + outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS); else outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS); } diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c index 29d13d2..5af4ef7 100644 --- a/board/eNET/eNET_pci.c +++ b/board/eNET/eNET_pci.c @@ -38,7 +38,7 @@ static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev) CONFIG_SYS_THIRD_PCI_IRQ, CONFIG_SYS_FORTH_PCI_IRQ }; - static int next_irq_index=0; + static int next_irq_index; uchar tmp_pin; int pin; @@ -47,9 +47,8 @@ static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev) pin = tmp_pin; pin -= 1; /* PCI config space use 1-based numbering */ - if (pin == -1) { + if (pin == -1) return; /* device use no irq */ - } /* map device number + pin to a pin on the sc520 */ switch (PCI_DEV(dev)) { @@ -69,19 +68,19 @@ static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev) if (sc520_pci_ints[pin] == -1) { /* re-route one interrupt for us */ - if (next_irq_index > 3) { + if (next_irq_index > 3) return; - } - if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { + + if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) return; - } + next_irq_index++; } - if (-1 != sc520_pci_ints[pin]) { - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + if (-1 != sc520_pci_ints[pin]) + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, sc520_pci_ints[pin]); - } + printf("fixup_irq: device %d pin %c irq %d\n", PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); } -- cgit v0.10.2 From facc9e7bf42e3578d7e7cecf1727f31badeee6bd Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:17 +0000 Subject: x86: Punt cold- and warm-boot flags Nobody uses them anyway Signed-off-by: Graeme Russ Acked-by: Mike Frysinger diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 306fb49..1634eb1 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -53,8 +53,6 @@ _x86boot_start: movl %eax, %cr0 wbinvd - /* Tell 32-bit code it is being entered from an in-RAM copy */ - movw $GD_FLG_WARM_BOOT, %bx _start: /* This is the 32-bit cold-reset entry point */ diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index 9dabff2..33e53cd 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -37,9 +37,6 @@ .code16 .globl start16 start16: - /* Set the Cold Boot / Hard Reset flag */ - movl $GD_FLG_COLD_BOOT, %ebx - /* * First we let the BSP do some early initialization * this code have to map the flash to its final position diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index f177a4f..c736549 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -91,8 +91,6 @@ extern gd_t *gd; #define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ #define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ -#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */ -#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */ #if 0 #define DECLARE_GLOBAL_DATA_PTR -- cgit v0.10.2 From 311b1a2b38b5317fdff76a5dad9d16fee3f52c79 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:18 +0000 Subject: sc520: Create arch asm-offsets Signed-off-by: Graeme Russ diff --git a/arch/x86/cpu/sc520/asm-offsets.c b/arch/x86/cpu/sc520/asm-offsets.c new file mode 100644 index 0000000..794f00c --- /dev/null +++ b/arch/x86/cpu/sc520/asm-offsets.c @@ -0,0 +1,45 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include + +#include + +int main(void) +{ + DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off)); + + DEFINE(GENERATED_SC520_PAR0, offsetof(struct sc520_mmcr, par[0])); + DEFINE(GENERATED_SC520_PAR1, offsetof(struct sc520_mmcr, par[1])); + DEFINE(GENERATED_SC520_PAR2, offsetof(struct sc520_mmcr, par[2])); + DEFINE(GENERATED_SC520_PAR3, offsetof(struct sc520_mmcr, par[3])); + DEFINE(GENERATED_SC520_PAR4, offsetof(struct sc520_mmcr, par[4])); + DEFINE(GENERATED_SC520_PAR5, offsetof(struct sc520_mmcr, par[5])); + DEFINE(GENERATED_SC520_PAR6, offsetof(struct sc520_mmcr, par[6])); + DEFINE(GENERATED_SC520_PAR7, offsetof(struct sc520_mmcr, par[7])); + DEFINE(GENERATED_SC520_PAR8, offsetof(struct sc520_mmcr, par[8])); + DEFINE(GENERATED_SC520_PAR9, offsetof(struct sc520_mmcr, par[9])); + DEFINE(GENERATED_SC520_PAR10, offsetof(struct sc520_mmcr, par[10])); + DEFINE(GENERATED_SC520_PAR11, offsetof(struct sc520_mmcr, par[11])); + DEFINE(GENERATED_SC520_PAR12, offsetof(struct sc520_mmcr, par[12])); + DEFINE(GENERATED_SC520_PAR13, offsetof(struct sc520_mmcr, par[13])); + DEFINE(GENERATED_SC520_PAR14, offsetof(struct sc520_mmcr, par[14])); + DEFINE(GENERATED_SC520_PAR15, offsetof(struct sc520_mmcr, par[15])); + + return 0; +} diff --git a/arch/x86/cpu/sc520/sc520_car.S b/arch/x86/cpu/sc520/sc520_car.S index 7cac4d1..c04cc1f 100644 --- a/arch/x86/cpu/sc520/sc520_car.S +++ b/arch/x86/cpu/sc520/sc520_car.S @@ -24,6 +24,7 @@ #include #include #include +#include .section .text @@ -55,7 +56,7 @@ car_init: /* Configure Cache-As-RAM PAR */ movl $CONFIG_SYS_SC520_CAR_PAR, %eax - movl $SC520_PAR2, %edi + movl $(SC520_MMCR_BASE + GENERATED_SC520_PAR2), %edi movl %eax, (%edi) /* Trash the cache then turn it on */ diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 1634eb1..5adb387 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -30,6 +30,7 @@ #include #include #include +#include .section .text .code32 @@ -112,7 +113,7 @@ relocate_code: /* Setup call address of in-RAM copy of board_init_r() */ movl $board_init_r, %ebp - addl (GD_RELOC_OFF * 4)(%edx), %ebp + addl (GENERATED_GD_RELOC_OFF)(%edx), %ebp /* Setup parameters to board_init_r() */ movl %edx, %eax diff --git a/arch/x86/include/asm/arch-sc520/sc520.h b/arch/x86/include/asm/arch-sc520/sc520.h index 5ac9bb8..9dc29d3 100644 --- a/arch/x86/include/asm/arch-sc520/sc520.h +++ b/arch/x86/include/asm/arch-sc520/sc520.h @@ -259,32 +259,6 @@ extern sc520_mmcr_t *sc520_mmcr; /* Memory Mapped Control Registers (MMCR) Base Address */ #define SC520_MMCR_BASE 0xfffef000 -/* MMCR Addresses (required for assembler code) */ -#define SC520_DRCCTL (SC520_MMCR_BASE + 0x010) -#define SC520_DRCTMCTL (SC520_MMCR_BASE + 0x012) -#define SC520_DRCCFG (SC520_MMCR_BASE + 0x014) -#define SC520_DRCBENDADR (SC520_MMCR_BASE + 0x018) -#define SC520_ECCCTL (SC520_MMCR_BASE + 0x020) -#define SC520_DBCTL (SC520_MMCR_BASE + 0x040) -#define SC520_ECCINT (SC520_MMCR_BASE + 0xd18) - -#define SC520_PAR0 (SC520_MMCR_BASE + 0x088) -#define SC520_PAR1 (SC520_PAR0 + (0x04 * 1)) -#define SC520_PAR2 (SC520_PAR0 + (0x04 * 2)) -#define SC520_PAR3 (SC520_PAR0 + (0x04 * 3)) -#define SC520_PAR4 (SC520_PAR0 + (0x04 * 4)) -#define SC520_PAR5 (SC520_PAR0 + (0x04 * 5)) -#define SC520_PAR6 (SC520_PAR0 + (0x04 * 6)) -#define SC520_PAR7 (SC520_PAR0 + (0x04 * 7)) -#define SC520_PAR8 (SC520_PAR0 + (0x04 * 8)) -#define SC520_PAR9 (SC520_PAR0 + (0x04 * 9)) -#define SC520_PAR10 (SC520_PAR0 + (0x04 * 10)) -#define SC520_PAR11 (SC520_PAR0 + (0x04 * 11)) -#define SC520_PAR12 (SC520_PAR0 + (0x04 * 12)) -#define SC520_PAR13 (SC520_PAR0 + (0x04 * 13)) -#define SC520_PAR14 (SC520_PAR0 + (0x04 * 14)) -#define SC520_PAR15 (SC520_PAR0 + (0x04 * 15)) - /* * PARs for maximum allowable 256MB of SDRAM @ 0x00000000 * Two PARs are required due to maximum PAR size of 128MB diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index c736549..05a2139 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -61,25 +61,6 @@ extern gd_t *gd; #endif -/* Word Offsets into Global Data - MUST match struct gd_t */ -#define GD_BD 0 -#define GD_FLAGS 1 -#define GD_BAUDRATE 2 -#define GD_HAVE_CONSOLE 3 -#define GD_RELOC_OFF 4 -#define GD_LOAD_OFF 5 -#define GD_ENV_ADDR 6 -#define GD_ENV_VALID 7 -#define GD_CPU_CLK 8 -#define GD_BUS_CLK 9 -#define GD_RELOC_ADDR 10 -#define GD_START_ADDR_SP 11 -#define GD_RAM_SIZE 12 -#define GD_RESET_STATUS 13 -#define GD_JT 14 - -#define GD_SIZE 15 - /* * Global Data Flags */ diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S index 4241f6e..5e3f44c 100644 --- a/board/eNET/eNET_start16.S +++ b/board/eNET/eNET_start16.S @@ -30,6 +30,7 @@ #include "config.h" #include "hardware.h" #include +#include .text .section .start16, "ax" @@ -46,12 +47,12 @@ board_init16: movw %ax, %ds /* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */ - movl $(SC520_PAR14 - SC520_MMCR_BASE), %edi + movl $GENERATED_SC520_PAR14, %edi movl $CONFIG_SYS_SC520_BOOTCS_PAR, %eax movl %eax, (%di) /* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */ - movl $(SC520_PAR15 - SC520_MMCR_BASE), %edi + movl $GENERATED_SC520_PAR15, %edi movl $CONFIG_SYS_SC520_LLIO_PAR, %eax movl %eax, (%di) -- cgit v0.10.2 From a206cc23431474a9890f0301f02f50ad3dc9b062 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:19 +0000 Subject: x86: Add multiboot header By adding a multiboot header, U-Boot can be loaded by GRUB2. Using GRUB2 to bootstrap U-Boot is useful for using an existing BIOS to get an initial U-Boot port up and running before implementing the low-level reset vector code, SDRAM init, etc. and overwriting the BIOS Signed-off-by: Graeme Russ diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 5adb387..d099fc9 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -129,3 +129,23 @@ die: hlt blank_idt_ptr: .word 0 /* limit */ .long 0 /* base */ + + .p2align 2 /* force 4-byte alignment */ + +multiboot_header: + /* magic */ + .long 0x1BADB002 + /* flags */ + .long (1 << 16) + /* checksum */ + .long -0x1BADB002 - (1 << 16) + /* header addr */ + .long multiboot_header - _x86boot_start + CONFIG_SYS_TEXT_BASE + /* load addr */ + .long CONFIG_SYS_TEXT_BASE + /* load end addr */ + .long 0 + /* bss end addr */ + .long 0 + /* entry addr */ + .long CONFIG_SYS_TEXT_BASE -- cgit v0.10.2 From a76fc70ee190416e0c161efebdb955a5fac904d3 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:20 +0000 Subject: x86: Provide more configuration granularity Planned future ports requires more granularity for some options Signed-off-by: Graeme Russ diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 71e94f7..eb5fa10 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -25,11 +25,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(ARCH).o -SOBJS-y += bios.o -SOBJS-y += bios_pci.o -SOBJS-y += realmode_switch.o +SOBJS-$(CONFIG_SYS_PC_BIOS) += bios.o +SOBJS-$(CONFIG_SYS_PCI_BIOS) += bios_pci.o +SOBJS-$(CONFIG_SYS_X86_REALMODE) += realmode_switch.o -COBJS-y += bios_setup.o +COBJS-$(CONFIG_SYS_PC_BIOS) += bios_setup.o COBJS-y += board.o COBJS-y += bootm.o COBJS-y += interrupts.o @@ -37,11 +37,11 @@ COBJS-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o COBJS-$(CONFIG_SYS_GENERIC_TIMER) += pcat_timer.o COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_PCI) += pci_type1.o -COBJS-y += realmode.o -COBJS-y += timer.o -COBJS-y += video_bios.o -COBJS-y += video.o -COBJS-y += zimage.o +COBJS-$(CONFIG_SYS_X86_REALMODE) += realmode.o +COBJS-$(CONFIG_SYS_X86_ISR_TIMER) += timer.o +COBJS-$(CONFIG_VIDEO) += video_bios.o +COBJS-$(CONFIG_VIDEO) += video.o +COBJS-$(CONFIG_CMD_ZBOOT) += zimage.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c index e8227b1..b445179 100644 --- a/arch/x86/lib/board.c +++ b/arch/x86/lib/board.c @@ -91,11 +91,13 @@ static int display_dram_config(void) return 0; } +#ifndef CONFIG_SYS_NO_FLASH static void display_flash_config(ulong size) { puts("Flash: "); print_size(size, "\n"); } +#endif /* * Breath some life into the board... @@ -254,8 +256,12 @@ void board_init_f(ulong boot_flags) void board_init_r(gd_t *id, ulong dest_addr) { +#if defined(CONFIG_CMD_NET) char *s; +#endif +#ifndef CONFIG_SYS_NO_FLASH ulong size; +#endif static bd_t bd_data; static gd_t gd_data; init_fnc_t **init_fnc_ptr; @@ -287,10 +293,13 @@ void board_init_r(gd_t *id, ulong dest_addr) #ifdef CONFIG_SERIAL_MULTI serial_initialize(); #endif + +#ifndef CONFIG_SYS_NO_FLASH /* configure available FLASH banks */ size = flash_init(); display_flash_config(size); show_boot_progress(0x24); +#endif show_boot_progress(0x25); diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 836803c..bac7b4f 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -35,7 +35,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images) { - void *base_ptr; + void *base_ptr = NULL; ulong os_data, os_len; image_header_t *hdr; @@ -73,8 +73,10 @@ int do_bootm_linux(int flag, int argc, char * const argv[], goto error; } +#ifdef CONFIG_CMD_ZBOOT base_ptr = load_zimage((void *)os_data, os_len, images->rd_start, images->rd_end - images->rd_start, 0); +#endif if (NULL == base_ptr) { printf("## Kernel loading failed ...\n"); diff --git a/arch/x86/lib/pci.c b/arch/x86/lib/pci.c index f3018b7..71878dd 100644 --- a/arch/x86/lib/pci.c +++ b/arch/x86/lib/pci.c @@ -151,3 +151,38 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) return res; } + +#ifdef PCI_BIOS_DEBUG + +void print_bios_bios_stat(void) +{ + printf("16 bit functions:\n"); + printf("pci_bios_present: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_present)); + printf("pci_bios_find_device: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_find_device)); + printf("pci_bios_find_class: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_find_class)); + printf("pci_bios_generate_special_cycle: %d\n", + RELOC_16_LONG(0xf000, + num_pci_bios_generate_special_cycle)); + printf("pci_bios_read_cfg_byte: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_byte)); + printf("pci_bios_read_cfg_word: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_word)); + printf("pci_bios_read_cfg_dword: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_dword)); + printf("pci_bios_write_cfg_byte: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_byte)); + printf("pci_bios_write_cfg_word: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_word)); + printf("pci_bios_write_cfg_dword: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_dword)); + printf("pci_bios_get_irq_routing: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_get_irq_routing)); + printf("pci_bios_set_irq: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_set_irq)); + printf("pci_bios_unknown_function: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_unknown_function)); +} +#endif diff --git a/arch/x86/lib/video_bios.c b/arch/x86/lib/video_bios.c index f89f7d6..1e06759 100644 --- a/arch/x86/lib/video_bios.c +++ b/arch/x86/lib/video_bios.c @@ -39,45 +39,6 @@ #define PRINTF(fmt, args...) #endif -#ifdef CONFIG_PCI - -#ifdef PCI_BIOS_DEBUG -void print_bios_bios_stat(void) -{ - printf("16 bit functions:\n"); - printf("pci_bios_present: %d\n", - RELOC_16_LONG(0xf000, num_pci_bios_present)); - printf("pci_bios_find_device: %d\n", - RELOC_16_LONG(0xf000, num_pci_bios_find_device)); - printf("pci_bios_find_class: %d\n", - RELOC_16_LONG(0xf000, num_pci_bios_find_class)); - printf("pci_bios_generate_special_cycle: %d\n", - RELOC_16_LONG(0xf000, - num_pci_bios_generate_special_cycle)); - printf("pci_bios_read_cfg_byte: %d\n", - RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_byte)); - printf("pci_bios_read_cfg_word: %d\n", - RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_word)); - printf("pci_bios_read_cfg_dword: %d\n", - RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_dword)); - printf("pci_bios_write_cfg_byte: %d\n", - RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_byte)); - printf("pci_bios_write_cfg_word: %d\n", - RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_word)); - printf("pci_bios_write_cfg_dword: %d\n", - RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_dword)); - printf("pci_bios_get_irq_routing: %d\n", - RELOC_16_LONG(0xf000, num_pci_bios_get_irq_routing)); - printf("pci_bios_set_irq: %d\n", - RELOC_16_LONG(0xf000, num_pci_bios_set_irq)); - printf("pci_bios_unknown_function: %d\n", - RELOC_16_LONG(0xf000, num_pci_bios_unknown_function)); - -} -#endif - -#ifdef CONFIG_VIDEO - #define PCI_CLASS_VIDEO 3 #define PCI_CLASS_VIDEO_STD 0 #define PCI_CLASS_VIDEO_PROG_IF_VGA 0 @@ -233,5 +194,3 @@ int video_bios_init(void) return 1; } -#endif -#endif diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 688b238..6c48594 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -31,7 +31,8 @@ DECLARE_GLOBAL_DATA_PTR; static void print_num(const char *, ulong); -#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K) || defined(CONFIG_SANDBOX)) \ +#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K) || \ + defined(CONFIG_SANDBOX) || defined(CONFIG_X86)) \ || defined(CONFIG_CMD_NET) #define HAVE_PRINT_ETH static void print_eth(int idx); diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 70c74f6..d5c9cad 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -105,6 +105,7 @@ #define CONFIG_CMD_SETGETDCR #define CONFIG_CMD_SOURCE #define CONFIG_CMD_XIMG +#define CONFIG_CMD_ZBOOT #define CONFIG_BOOTDELAY 15 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" @@ -153,6 +154,10 @@ #undef CONFIG_SYS_GENERIC_TIMER #define CONFIG_SYS_PCAT_INTERRUPTS #define CONFIG_SYS_NUM_IRQS 16 +#define CONFIG_SYS_PC_BIOS +#define CONFIG_SYS_PCI_BIOS +#define CONFIG_SYS_X86_REALMODE +#define CONFIG_SYS_X86_ISR_TIMER /*----------------------------------------------------------------------- * Memory organization: -- cgit v0.10.2 From 303418cc97c0922cdbbc328e6d9111bd9a84d1c7 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:21 +0000 Subject: x86: Ensure IDT and GDT remain 16-byte aligned post relocation Some CPUs have strict alignment requirements for these tables Signed-off-by: Graeme Russ diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index e007511..e0958eb 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -174,7 +174,7 @@ struct desc_ptr { unsigned short segment; } __packed; -struct idt_entry idt[256]; +struct idt_entry idt[256] __attribute__((aligned(16))); struct desc_ptr idt_ptr; diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c index b445179..244a021 100644 --- a/arch/x86/lib/board.c +++ b/arch/x86/lib/board.c @@ -161,19 +161,26 @@ gd_t *gd; static int calculate_relocation_address(void) { - void *text_start = &__text_start; - void *bss_end = &__bss_end; - void *dest_addr; + ulong text_start = (ulong)&__text_start; + ulong bss_end = (ulong)&__bss_end; + ulong dest_addr; ulong rel_offset; /* Calculate destination RAM Address and relocation offset */ - dest_addr = (void *)gd->ram_size; + dest_addr = gd->ram_size; dest_addr -= CONFIG_SYS_STACK_SIZE; dest_addr -= (bss_end - text_start); + + /* + * Round destination address down to 16-byte boundary to keep + * IDT and GDT 16-byte aligned + */ + dest_addr &= ~15; + rel_offset = dest_addr - text_start; gd->start_addr_sp = gd->ram_size; - gd->relocaddr = (ulong)dest_addr; + gd->relocaddr = dest_addr; gd->reloc_off = rel_offset; return 0; -- cgit v0.10.2 From 1cfcf0370132315d6eee375afdf7207ff60a07e0 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:22 +0000 Subject: x86: Misc PCI touchups Signed-off-by: Graeme Russ diff --git a/arch/x86/cpu/sc520/sc520_pci.c b/arch/x86/cpu/sc520/sc520_pci.c index a13798f..52d07c1 100644 --- a/arch/x86/cpu/sc520/sc520_pci.c +++ b/arch/x86/cpu/sc520/sc520_pci.c @@ -130,9 +130,7 @@ void pci_sc520_init(struct pci_controller *hose) hose->last_busno = 0xff; hose->region_count = pci_set_regions(hose); - pci_setup_type1(hose, - SC520_REG_ADDR, - SC520_REG_DATA); + pci_setup_type1(hose); pci_register_hose(hose); diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index c09078e..37cc7e3 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -29,7 +29,7 @@ #define DEFINE_PCI_DEVICE_TABLE(_table) \ const struct pci_device_id _table[] -void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); +void pci_setup_type1(struct pci_controller *hose); int pci_enable_legacy_video_ports(struct pci_controller* hose); int pci_shadow_rom(pci_dev_t dev, unsigned char *dest); void pci_remove_rom_window(struct pci_controller* hose, u32 addr); diff --git a/arch/x86/lib/pci_type1.c b/arch/x86/lib/pci_type1.c index 6fc4df4..a25fa05 100644 --- a/arch/x86/lib/pci_type1.c +++ b/arch/x86/lib/pci_type1.c @@ -50,7 +50,11 @@ TYPE1_PCI_OP(write, byte, u8, outb, 3) TYPE1_PCI_OP(write, word, u16, outw, 2) TYPE1_PCI_OP(write, dword, u32, outl, 0) -void pci_setup_type1(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) +/* bus mapping constants (used for PCI core initialization) */ +#define PCI_REG_ADDR 0x00000cf8 +#define PCI_REG_DATA 0x00000cfc + +void pci_setup_type1(struct pci_controller *hose) { pci_set_ops(hose, type1_read_config_byte, @@ -60,6 +64,6 @@ void pci_setup_type1(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) type1_write_config_word, type1_write_config_dword); - hose->cfg_addr = (unsigned int *)cfg_addr; - hose->cfg_data = (unsigned char *)cfg_data; + hose->cfg_addr = (unsigned int *)PCI_REG_ADDR; + hose->cfg_data = (unsigned char *)PCI_REG_DATA; } -- cgit v0.10.2 From 2f0e0cd246c2279883062fcfe90cd705f05bcb31 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:23 +0000 Subject: x86: Misc cleanups Signed-off-by: Graeme Russ diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index d099fc9..f87633b 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -48,7 +48,7 @@ _x86boot_start: cli cld - /* Turn of cache (this might require a 486-class CPU) */ + /* Turn off cache (this might require a 486-class CPU) */ movl %cr0, %eax orl $(X86_CR0_NW | X86_CR0_CD), %eax movl %eax, %cr0 @@ -122,7 +122,8 @@ relocate_code: /* Jump to in-RAM copy of board_init_r() */ call *%ebp -die: hlt +die: + hlt jmp die hlt -- cgit v0.10.2 From 03228b26d5d999b05ea6e5946ad0375715b9043c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 12 Nov 2011 16:31:18 +0000 Subject: x86: Fix how the location of the realmode and bios blobs are calculated There are two blobs embedded into the u-boot image which are linked to run at an address which is different from where they actually end up in the ROM, one called "realmode" and one called "bios". There are realmode_setup and bios_setup functions which prepare those blobs by copying them into the location they're supposed to run from, among other things. During u-boot relocation from ROM to RAM, the text and a few data segments are copied over. The realmode and bios sections are not copied, and so the only place they can be read from is their original location in the ROM. Looking specifically at the bios blob, there are symbols defined in the linker script called __bios_start and __bios_size which are defined to be the start and size of the blob in the ROM. In the bios_setup function, there seem to be two mistakes happening. First, the offset from ROM to RAM is being added to __bios_start which implies that this code expects to use the copy moved to RAM. No such copy is made, so that's wrong. More subtly, when u-boot relocates itself, it goes through all of the relocations stored in .rel.dyn and fixes them up. This has the effect of transforming the __bios_start reference in bios_setup so that it refers to the version in RAM (if one existed) instead of the one in ROM. To correct for that, the offset actually needs to be subtracted out again to translate the address back into the ROM. The net effect is that for both blobs, a + needs to be changed to a -. Signed-off-by: Gabe Black diff --git a/arch/x86/lib/bios_setup.c b/arch/x86/lib/bios_setup.c index 053280b..0dfe4a1 100644 --- a/arch/x86/lib/bios_setup.c +++ b/arch/x86/lib/bios_setup.c @@ -78,7 +78,11 @@ static void setvector(int vector, u16 segment, void *handler) int bios_setup(void) { - ulong bios_start = (ulong)&__bios_start + gd->reloc_off; + /* + * The BIOS section is not relocated and still in the ROM. The + * __bios_start symbol was adjusted, though, so adjust it back. + */ + ulong bios_start = (ulong)&__bios_start - gd->reloc_off; ulong bios_size = (ulong)&__bios_size; static int done; diff --git a/arch/x86/lib/realmode.c b/arch/x86/lib/realmode.c index 5a525ee..bf0d0aa 100644 --- a/arch/x86/lib/realmode.c +++ b/arch/x86/lib/realmode.c @@ -30,7 +30,11 @@ int realmode_setup(void) { - ulong realmode_start = (ulong)&__realmode_start + gd->reloc_off; + /* + * The realmode section is not relocated and still in the ROM. The + * __realmode_start symbol was adjusted, though, so adjust it back. + */ + ulong realmode_start = (ulong)&__realmode_start - gd->reloc_off; ulong realmode_size = (ulong)&__realmode_size; /* copy the realmode switch code */ -- cgit v0.10.2 From 769db03a4a4ea1dc7e43c089c2227a0c8b4ffcbc Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 12 Nov 2011 16:34:48 +0000 Subject: x86: Don't relocate symbols which point to things that aren't relocated This change adds an upper bound for symbols which are fixed up after u-boot is relocated into RAM. This way portions that are left at their original location can be referred to without having to manually fix up any pointers. Signed-off-by: Gabe Black diff --git a/arch/x86/lib/bios_setup.c b/arch/x86/lib/bios_setup.c index 0dfe4a1..265f7d6 100644 --- a/arch/x86/lib/bios_setup.c +++ b/arch/x86/lib/bios_setup.c @@ -78,11 +78,8 @@ static void setvector(int vector, u16 segment, void *handler) int bios_setup(void) { - /* - * The BIOS section is not relocated and still in the ROM. The - * __bios_start symbol was adjusted, though, so adjust it back. - */ - ulong bios_start = (ulong)&__bios_start - gd->reloc_off; + /* The BIOS section is not relocated and still in the ROM. */ + ulong bios_start = (ulong)&__bios_start; ulong bios_size = (ulong)&__bios_size; static int done; diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c index 244a021..18e0ede 100644 --- a/arch/x86/lib/board.c +++ b/arch/x86/lib/board.c @@ -231,8 +231,11 @@ static int do_elf_reloc_fixups(void) offset_ptr_ram = offset_ptr_rom + gd->reloc_off; /* Check that the target points into .text */ - if (*offset_ptr_ram >= CONFIG_SYS_TEXT_BASE) + if (*offset_ptr_ram >= CONFIG_SYS_TEXT_BASE && + *offset_ptr_ram < + (CONFIG_SYS_TEXT_BASE + size)) { *offset_ptr_ram += gd->reloc_off; + } } } while (re_src++ < re_end); diff --git a/arch/x86/lib/realmode.c b/arch/x86/lib/realmode.c index bf0d0aa..75511b2 100644 --- a/arch/x86/lib/realmode.c +++ b/arch/x86/lib/realmode.c @@ -30,11 +30,8 @@ int realmode_setup(void) { - /* - * The realmode section is not relocated and still in the ROM. The - * __realmode_start symbol was adjusted, though, so adjust it back. - */ - ulong realmode_start = (ulong)&__realmode_start - gd->reloc_off; + /* The realmode section is not relocated and still in the ROM. */ + ulong realmode_start = (ulong)&__realmode_start; ulong realmode_size = (ulong)&__realmode_size; /* copy the realmode switch code */ -- cgit v0.10.2 From 60a9b6bfddbe1e3ae280fe5422ccd283bc31a591 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 16 Nov 2011 23:32:50 +0000 Subject: x86: Fix a few recently added bugs Signed-off-by: Gabe Black Signed-off-by: Graeme Russ diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 48d2f7a..61d0b69 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -37,6 +37,7 @@ #include #include #include +#include /* * Constructor for a conventional segment GDT (or LDT) entry diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c index 18e0ede..d742fec 100644 --- a/arch/x86/lib/board.c +++ b/arch/x86/lib/board.c @@ -220,6 +220,9 @@ static int do_elf_reloc_fixups(void) Elf32_Addr *offset_ptr_rom; Elf32_Addr *offset_ptr_ram; + /* The size of the region of u-boot that runs out of RAM. */ + uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start; + do { /* Get the location from the relocation entry */ offset_ptr_rom = (Elf32_Addr *)re_src->r_offset; @@ -228,7 +231,8 @@ static int do_elf_reloc_fixups(void) if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE) { /* Switch to the in-RAM version */ - offset_ptr_ram = offset_ptr_rom + gd->reloc_off; + offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom + + gd->reloc_off); /* Check that the target points into .text */ if (*offset_ptr_ram >= CONFIG_SYS_TEXT_BASE && -- cgit v0.10.2 From dbaef6ef33912a863f9fb550857028fb96e42c59 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 14 Nov 2011 14:47:18 +0000 Subject: x86: Import the glibc memset implementation The new implementation is about twice as fast as the old. This is from glibc-2.14, sysdeps/i386/memset.c. Signed-off-by: Gabe Black diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h index 3643a79..3aa6c11 100644 --- a/arch/x86/include/asm/string.h +++ b/arch/x86/include/asm/string.h @@ -23,7 +23,7 @@ extern void * memmove(void *, const void *, __kernel_size_t); #undef __HAVE_ARCH_MEMCHR extern void * memchr(const void *, int, __kernel_size_t); -#undef __HAVE_ARCH_MEMSET +#define __HAVE_ARCH_MEMSET extern void * memset(void *, int, __kernel_size_t); #undef __HAVE_ARCH_MEMZERO diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index eb5fa10..90f3283 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -38,6 +38,7 @@ COBJS-$(CONFIG_SYS_GENERIC_TIMER) += pcat_timer.o COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_PCI) += pci_type1.o COBJS-$(CONFIG_SYS_X86_REALMODE) += realmode.o +COBJS-y += string.o COBJS-$(CONFIG_SYS_X86_ISR_TIMER) += timer.o COBJS-$(CONFIG_VIDEO) += video_bios.o COBJS-$(CONFIG_VIDEO) += video.o diff --git a/arch/x86/lib/string.c b/arch/x86/lib/string.c new file mode 100644 index 0000000..f2ea7e4 --- /dev/null +++ b/arch/x86/lib/string.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc. + * This file is part of the GNU C Library. + * Copyright (c) 2011 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* From glibc-2.14, sysdeps/i386/memset.c */ + +#include +#include +#include + +typedef uint32_t op_t; + +void *memset(void *dstpp, int c, size_t len) +{ + int d0; + unsigned long int dstp = (unsigned long int) dstpp; + + /* This explicit register allocation improves code very much indeed. */ + register op_t x asm("ax"); + + x = (unsigned char) c; + + /* Clear the direction flag, so filling will move forward. */ + asm volatile("cld"); + + /* This threshold value is optimal. */ + if (len >= 12) { + /* Fill X with four copies of the char we want to fill with. */ + x |= (x << 8); + x |= (x << 16); + + /* Adjust LEN for the bytes handled in the first loop. */ + len -= (-dstp) % sizeof(op_t); + + /* + * There are at least some bytes to set. No need to test for + * LEN == 0 in this alignment loop. + */ + + /* Fill bytes until DSTP is aligned on a longword boundary. */ + asm volatile( + "rep\n" + "stosb" /* %0, %2, %3 */ : + "=D" (dstp), "=c" (d0) : + "0" (dstp), "1" ((-dstp) % sizeof(op_t)), "a" (x) : + "memory"); + + /* Fill longwords. */ + asm volatile( + "rep\n" + "stosl" /* %0, %2, %3 */ : + "=D" (dstp), "=c" (d0) : + "0" (dstp), "1" (len / sizeof(op_t)), "a" (x) : + "memory"); + len %= sizeof(op_t); + } + + /* Write the last few bytes. */ + asm volatile( + "rep\n" + "stosb" /* %0, %2, %3 */ : + "=D" (dstp), "=c" (d0) : + "0" (dstp), "1" (len), "a" (x) : + "memory"); + + return dstpp; +} -- cgit v0.10.2 From 36b2409a3d469b5133d105fa12089429a1900bde Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 16 Nov 2011 23:01:37 +0000 Subject: x86: Wrap small helper functions from libgcc to avoid an ABI mismatch When gcc compiles some 64 bit operations on a 32 bit machine, it generates calls to small functions instead of instructions which do the job directly. Those functions are defined in libgcc and transparently provide whatever functionality was necessary. Unfortunately, u-boot can be built with a non-standard ABI when libgcc isn't. More specifically, u-boot uses -mregparm. When the u-boot and libgcc are linked together, very confusing bugs can crop up, for instance seemingly normal integer division or modulus getting the wrong answer or even raising a spurious divide by zero exception. This change borrows (steals) a technique and some code from coreboot which solves this problem by creating wrappers which translate the calling convention when calling the functions in libgcc. Unfortunately that means that these instructions which had already been turned into functions have even more overhead, but more importantly it makes them work properly. To find all of the functions that needed wrapping, u-boot was compiled without linking in libgcc. All the symbols the linker complained were undefined were presumed to be the symbols that are needed from libgcc. These were a subset of the symbols covered by the coreboot code, so it was used unmodified. To prevent symbols which are provided by libgcc but not currently wrapped (or even known about) from being silently linked against by code generated by libgcc, a new copy of libgcc is created where all the symbols are prefixed with __normal_. Without being purposefully wrapped, these symbols will cause linker errors instead of silently introducing very subtle, confusing bugs. Another approach would be to whitelist symbols from libgcc and strip out all the others. The problem with this approach is that it requires the white listed symbols to be specified three times, once for objcopy, once so the linker inserts the wrapped, and once to generate the wrapper itself, while this implementation needs it to be listed only twice. There isn't much tangible difference in what each approach produces, so this one was preferred. Signed-off-by: Gabe Black diff --git a/arch/x86/config.mk b/arch/x86/config.mk index fe9083f..23cacff 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -41,3 +41,10 @@ PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions LDFLAGS_FINAL += --gc-sections -pie +LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3 +LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3 + +NORMAL_LIBGCC = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name) +PREFIXED_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/$(shell basename $(NORMAL_LIBGCC)) + +export USE_PRIVATE_LIBGCC=$(shell dirname $(PREFIXED_LIBGCC)) diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 90f3283..d584aa4 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -32,6 +32,7 @@ SOBJS-$(CONFIG_SYS_X86_REALMODE) += realmode_switch.o COBJS-$(CONFIG_SYS_PC_BIOS) += bios_setup.o COBJS-y += board.o COBJS-y += bootm.o +COBJS-y += gcc.o COBJS-y += interrupts.o COBJS-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o COBJS-$(CONFIG_SYS_GENERIC_TIMER) += pcat_timer.o @@ -50,6 +51,11 @@ OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) $(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) +$(PREFIXED_LIBGCC): $(NORMAL_LIBGCC) + $(OBJCOPY) $< $@ --prefix-symbols=__normal_ + +$(LIB): $(PREFIXED_LIBGCC) + ######################################################################### # defines $(obj).depend target diff --git a/arch/x86/lib/gcc.c b/arch/x86/lib/gcc.c new file mode 100644 index 0000000..4043431 --- /dev/null +++ b/arch/x86/lib/gcc.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or later of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifdef __GNUC__ + +/* + * GCC's libgcc handling is quite broken. While the libgcc functions + * are always regparm(0) the code that calls them uses whatever the + * compiler call specifies. Therefore we need a wrapper around those + * functions. See gcc bug PR41055 for more information. + */ +#define WRAP_LIBGCC_CALL(type, name) \ + type __normal_##name(type a, type b) __attribute__((regparm(0))); \ + type __wrap_##name(type a, type b); \ + type __wrap_##name(type a, type b) { return __normal_##name(a, b); } + +WRAP_LIBGCC_CALL(long long, __divdi3) +WRAP_LIBGCC_CALL(unsigned long long, __udivdi3) +WRAP_LIBGCC_CALL(long long, __moddi3) +WRAP_LIBGCC_CALL(unsigned long long, __umoddi3) + +#endif -- cgit v0.10.2 From dd4a5b2246e34c59343c5bdb7bdced71e46d4ad5 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 14 Nov 2011 19:24:14 +0000 Subject: x86: Make the i8042 driver checkpatch clean Signed-off-by: Gabe Black diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index 58094c9..83b1bf4 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -28,11 +28,11 @@ #include #ifdef CONFIG_USE_CPCIDVI -extern u8 gt_cpcidvi_in8(u32 offset); +extern u8 gt_cpcidvi_in8(u32 offset); extern void gt_cpcidvi_out8(u32 offset, u8 data); #define in8(a) gt_cpcidvi_in8(a) -#define out8(a, b) gt_cpcidvi_out8(a,b) +#define out8(a, b) gt_cpcidvi_out8(a, b) #endif #include @@ -40,9 +40,9 @@ extern void gt_cpcidvi_out8(u32 offset, u8 data); /* defines */ #ifdef CONFIG_CONSOLE_CURSOR -extern void console_cursor (int state); +extern void console_cursor(int state); static int blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT; -static int cursor_state = 0; +static int cursor_state; #endif /* locals */ @@ -50,307 +50,303 @@ static int cursor_state = 0; static int kbd_input = -1; /* no input yet */ static int kbd_mapping = KBD_US; /* default US keyboard */ static int kbd_flags = NORMAL; /* after reset */ -static int kbd_state = 0; /* unshift code */ - -static void kbd_conv_char (unsigned char scan_code); -static void kbd_led_set (void); -static void kbd_normal (unsigned char scan_code); -static void kbd_shift (unsigned char scan_code); -static void kbd_ctrl (unsigned char scan_code); -static void kbd_num (unsigned char scan_code); -static void kbd_caps (unsigned char scan_code); -static void kbd_scroll (unsigned char scan_code); -static void kbd_alt (unsigned char scan_code); -static int kbd_input_empty (void); -static int kbd_reset (void); - -static unsigned char kbd_fct_map [144] = - { /* kbd_fct_map table for scan code */ - 0, AS, AS, AS, AS, AS, AS, AS, /* scan 0- 7 */ - AS, AS, AS, AS, AS, AS, AS, AS, /* scan 8- F */ - AS, AS, AS, AS, AS, AS, AS, AS, /* scan 10-17 */ - AS, AS, AS, AS, AS, CN, AS, AS, /* scan 18-1F */ - AS, AS, AS, AS, AS, AS, AS, AS, /* scan 20-27 */ - AS, AS, SH, AS, AS, AS, AS, AS, /* scan 28-2F */ - AS, AS, AS, AS, AS, AS, SH, AS, /* scan 30-37 */ - AS, AS, CP, 0, 0, 0, 0, 0, /* scan 38-3F */ - 0, 0, 0, 0, 0, NM, ST, ES, /* scan 40-47 */ - ES, ES, ES, ES, ES, ES, ES, ES, /* scan 48-4F */ - ES, ES, ES, ES, 0, 0, AS, 0, /* scan 50-57 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ - AS, 0, 0, AS, 0, 0, AS, 0, /* scan 70-77 */ - 0, AS, 0, 0, 0, AS, 0, 0, /* scan 78-7F */ - AS, CN, AS, AS, AK, ST, EX, EX, /* enhanced */ - AS, EX, EX, AS, EX, AS, EX, EX /* enhanced */ - }; - -static unsigned char kbd_key_map [2][5][144] = - { - { /* US keyboard */ - { /* unshift code */ - 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ - '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */ - 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */ - 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */ - 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */ - '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */ - 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */ - ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ - 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ - '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ - '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ - 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ - }, - { /* shift code */ - 0, 0x1b, '!', '@', '#', '$', '%', '^', /* scan 0- 7 */ - '&', '*', '(', ')', '_', '+', 0x08, '\t', /* scan 8- F */ - 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', /* scan 10-17 */ - 'O', 'P', '{', '}', '\r', CN, 'A', 'S', /* scan 18-1F */ - 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', /* scan 20-27 */ - '"', '~', SH, '|', 'Z', 'X', 'C', 'V', /* scan 28-2F */ - 'B', 'N', 'M', '<', '>', '?', SH, '*', /* scan 30-37 */ - ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ - 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ - '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ - '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ - 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ - }, - { /* control code */ - 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */ - 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */ - 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */ - 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */ - 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */ - 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */ - 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */ - 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */ - 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ - }, - { /* non numeric code */ - 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ - '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */ - 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */ - 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */ - 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */ - '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */ - 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */ - ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ - 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */ - 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */ - 'r', 's', 'p', 'n', 0, 0, 0, 0, /* scan 50-57 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ - 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ - }, - { /* right alt mode - not used in US keyboard */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 8 - F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50 -57 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ - } - }, - { /* german keyboard */ - { /* unshift code */ - 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ - '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */ - 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */ - 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */ - 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */ - 0x84, '^', SH, '#', 'y', 'x', 'c', 'v', /* scan 28-2F */ - 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */ - ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ - 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ - '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ - '2', '3', '0', ',', 0, 0, '<', 0, /* scan 50-57 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ - 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ - }, - { /* shift code */ - 0, 0x1b, '!', '"', 0x15, '$', '%', '&', /* scan 0- 7 */ - '/', '(', ')', '=', '?', '`', 0x08, '\t', /* scan 8- F */ - 'Q', 'W', 'E', 'R', 'T', 'Z', 'U', 'I', /* scan 10-17 */ - 'O', 'P', 0x9a, '*', '\r', CN, 'A', 'S', /* scan 18-1F */ - 'D', 'F', 'G', 'H', 'J', 'K', 'L', 0x99, /* scan 20-27 */ - 0x8e, 0xf8, SH, '\'', 'Y', 'X', 'C', 'V', /* scan 28-2F */ - 'B', 'N', 'M', ';', ':', '_', SH, '*', /* scan 30-37 */ - ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ - 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ - '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ - '2', '3', '0', ',', 0, 0, '>', 0, /* scan 50-57 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ - 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ - }, - { /* control code */ - 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */ - 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */ - 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */ - 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */ - 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */ - 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */ - 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */ - 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */ - 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ - }, - { /* non numeric code */ - 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ - '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */ - 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */ - 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */ - 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */ - 0x84, '^', SH, 0, 'y', 'x', 'c', 'v', /* scan 28-2F */ - 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */ - ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ - 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */ - 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */ - 'r', 's', 'p', 'n', 0, 0, '<', 0, /* scan 50-57 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ - 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ - }, - { /* Right alt mode - is used in German keyboard */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */ - '{', '[', ']', '}', '\\', 0xff, 0xff, 0xff, /* scan 8 - F */ - '@', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */ - 0xff, 0xff, 0xff, '~', 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */ - 0xff, 0xff, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '|', 0xff, /* scan 50 -57 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ - } - } - }; - -static unsigned char ext_key_map [] = - { - 0x1c, /* keypad enter */ - 0x1d, /* right control */ - 0x35, /* keypad slash */ - 0x37, /* print screen */ - 0x38, /* right alt */ - 0x46, /* break */ - 0x47, /* editpad home */ - 0x48, /* editpad up */ - 0x49, /* editpad pgup */ - 0x4b, /* editpad left */ - 0x4d, /* editpad right */ - 0x4f, /* editpad end */ - 0x50, /* editpad dn */ - 0x51, /* editpad pgdn */ - 0x52, /* editpad ins */ - 0x53, /* editpad del */ - 0x00 /* map end */ - }; +static int kbd_state; /* unshift code */ + +static void kbd_conv_char(unsigned char scan_code); +static void kbd_led_set(void); +static void kbd_normal(unsigned char scan_code); +static void kbd_shift(unsigned char scan_code); +static void kbd_ctrl(unsigned char scan_code); +static void kbd_num(unsigned char scan_code); +static void kbd_caps(unsigned char scan_code); +static void kbd_scroll(unsigned char scan_code); +static void kbd_alt(unsigned char scan_code); +static int kbd_input_empty(void); +static int kbd_reset(void); + +static unsigned char kbd_fct_map[144] = { + /* kbd_fct_map table for scan code */ + 0, AS, AS, AS, AS, AS, AS, AS, /* scan 0- 7 */ + AS, AS, AS, AS, AS, AS, AS, AS, /* scan 8- F */ + AS, AS, AS, AS, AS, AS, AS, AS, /* scan 10-17 */ + AS, AS, AS, AS, AS, CN, AS, AS, /* scan 18-1F */ + AS, AS, AS, AS, AS, AS, AS, AS, /* scan 20-27 */ + AS, AS, SH, AS, AS, AS, AS, AS, /* scan 28-2F */ + AS, AS, AS, AS, AS, AS, SH, AS, /* scan 30-37 */ + AS, AS, CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, ES, /* scan 40-47 */ + ES, ES, ES, ES, ES, ES, ES, ES, /* scan 48-4F */ + ES, ES, ES, ES, 0, 0, AS, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + AS, 0, 0, AS, 0, 0, AS, 0, /* scan 70-77 */ + 0, AS, 0, 0, 0, AS, 0, 0, /* scan 78-7F */ + AS, CN, AS, AS, AK, ST, EX, EX, /* enhanced */ + AS, EX, EX, AS, EX, AS, EX, EX /* enhanced */ + }; + +static unsigned char kbd_key_map[2][5][144] = { + { /* US keyboard */ + { /* unshift code */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */ + 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */ + '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* shift code */ + 0, 0x1b, '!', '@', '#', '$', '%', '^', /* scan 0- 7 */ + '&', '*', '(', ')', '_', '+', 0x08, '\t', /* scan 8- F */ + 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', /* scan 10-17 */ + 'O', 'P', '{', '}', '\r', CN, 'A', 'S', /* scan 18-1F */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', /* scan 20-27 */ + '"', '~', SH, '|', 'Z', 'X', 'C', 'V', /* scan 28-2F */ + 'B', 'N', 'M', '<', '>', '?', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* control code */ + 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */ + 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */ + 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */ + 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */ + 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */ + 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */ + 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */ + 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + }, + { /* non numeric code */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */ + 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */ + '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */ + 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */ + 'r', 's', 'p', 'n', 0, 0, 0, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* right alt mode - not used in US keyboard */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 8 - F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50 -57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + } + }, + { /* german keyboard */ + { /* unshift code */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */ + 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */ + 0x84, '^', SH, '#', 'y', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', ',', 0, 0, '<', 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* shift code */ + 0, 0x1b, '!', '"', 0x15, '$', '%', '&', /* scan 0- 7 */ + '/', '(', ')', '=', '?', '`', 0x08, '\t', /* scan 8- F */ + 'Q', 'W', 'E', 'R', 'T', 'Z', 'U', 'I', /* scan 10-17 */ + 'O', 'P', 0x9a, '*', '\r', CN, 'A', 'S', /* scan 18-1F */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', 0x99, /* scan 20-27 */ + 0x8e, 0xf8, SH, '\'', 'Y', 'X', 'C', 'V', /* scan 28-2F */ + 'B', 'N', 'M', ';', ':', '_', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', ',', 0, 0, '>', 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* control code */ + 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */ + 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */ + 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */ + 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */ + 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */ + 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */ + 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */ + 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + }, + { /* non numeric code */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */ + 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */ + 0x84, '^', SH, 0, 'y', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */ + 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */ + 'r', 's', 'p', 'n', 0, 0, '<', 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* Right alt mode - is used in German keyboard */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */ + '{', '[', ']', '}', '\\', 0xff, 0xff, 0xff, /* scan 8 - F */ + '@', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */ + 0xff, 0xff, 0xff, '~', 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */ + 0xff, 0xff, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '|', 0xff, /* scan 50 -57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + } + } + }; + +static unsigned char ext_key_map[] = { + 0x1c, /* keypad enter */ + 0x1d, /* right control */ + 0x35, /* keypad slash */ + 0x37, /* print screen */ + 0x38, /* right alt */ + 0x46, /* break */ + 0x47, /* editpad home */ + 0x48, /* editpad up */ + 0x49, /* editpad pgup */ + 0x4b, /* editpad left */ + 0x4d, /* editpad right */ + 0x4f, /* editpad end */ + 0x50, /* editpad dn */ + 0x51, /* editpad pgdn */ + 0x52, /* editpad ins */ + 0x53, /* editpad del */ + 0x00 /* map end */ + }; /******************************************************************************* * * i8042_kbd_init - reset keyboard and init state flags */ -int i8042_kbd_init (void) +int i8042_kbd_init(void) { - int keymap, try; - char *penv; + int keymap, try; + char *penv; #ifdef CONFIG_USE_CPCIDVI - if ((penv = getenv ("console")) != NULL) { - if (strncmp (penv, "serial", 7) == 0) { - return -1; - } - } + penv = getenv("console"); + if (penv != NULL) { + if (strncmp(penv, "serial", 7) == 0) + return -1; + } #endif - /* Init keyboard device (default US layout) */ - keymap = KBD_US; - if ((penv = getenv ("keymap")) != NULL) - { - if (strncmp (penv, "de", 3) == 0) - keymap = KBD_GER; - } - - for (try = 0; try < KBD_RESET_TRIES; try++) - { - if (kbd_reset() == 0) - { - kbd_mapping = keymap; - kbd_flags = NORMAL; - kbd_state = 0; - kbd_led_set(); - return 0; - } - } - return -1; + /* Init keyboard device (default US layout) */ + keymap = KBD_US; + penv = getenv("keymap"); + if (penv != NULL) { + if (strncmp(penv, "de", 3) == 0) + keymap = KBD_GER; + } + + for (try = 0; try < KBD_RESET_TRIES; try++) { + if (kbd_reset() == 0) { + kbd_mapping = keymap; + kbd_flags = NORMAL; + kbd_state = 0; + kbd_led_set(); + return 0; + } + } + return -1; } @@ -359,34 +355,32 @@ int i8042_kbd_init (void) * i8042_tstc - test if keyboard input is available * option: cursor blinking if called in a loop */ -int i8042_tstc (void) +int i8042_tstc(void) { - unsigned char scan_code = 0; + unsigned char scan_code = 0; #ifdef CONFIG_CONSOLE_CURSOR - if (--blinkCount == 0) - { - cursor_state ^= 1; - console_cursor (cursor_state); - blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT; - udelay (10); - } + if (--blinkCount == 0) { + cursor_state ^= 1; + console_cursor(cursor_state); + blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT; + udelay(10); + } #endif - if ((in8 (I8042_STATUS_REG) & 0x01) == 0) + if ((in8(I8042_STATUS_REG) & 0x01) == 0) { + return 0; + } else { + scan_code = in8(I8042_DATA_REG); + if (scan_code == 0xfa) + return 0; + + kbd_conv_char(scan_code); + + if (kbd_input != -1) + return 1; + } return 0; - else - { - scan_code = in8 (I8042_DATA_REG); - if (scan_code == 0xfa) - return 0; - - kbd_conv_char(scan_code); - - if (kbd_input != -1) - return 1; - } - return 0; } @@ -395,276 +389,256 @@ int i8042_tstc (void) * i8042_getc - wait till keyboard input is available * option: turn on/off cursor while waiting */ -int i8042_getc (void) +int i8042_getc(void) { - int ret_chr; - unsigned char scan_code; + int ret_chr; + unsigned char scan_code; - while (kbd_input == -1) - { - while ((in8 (I8042_STATUS_REG) & 0x01) == 0) - { + while (kbd_input == -1) { + while ((in8(I8042_STATUS_REG) & 0x01) == 0) { #ifdef CONFIG_CONSOLE_CURSOR - if (--blinkCount==0) - { - cursor_state ^= 1; - console_cursor (cursor_state); - blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT; - } - udelay (10); + if (--blinkCount == 0) { + cursor_state ^= 1; + console_cursor(cursor_state); + blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT; + } + udelay(10); #endif + } + scan_code = in8(I8042_DATA_REG); + if (scan_code != 0xfa) + kbd_conv_char (scan_code); } - - scan_code = in8 (I8042_DATA_REG); - - if (scan_code != 0xfa) - kbd_conv_char (scan_code); - } - ret_chr = kbd_input; - kbd_input = -1; - return ret_chr; + ret_chr = kbd_input; + kbd_input = -1; + return ret_chr; } /******************************************************************************/ -static void kbd_conv_char (unsigned char scan_code) +static void kbd_conv_char(unsigned char scan_code) { - if (scan_code == 0xe0) - { - kbd_flags |= EXT; - return; - } - - /* if high bit of scan_code, set break flag */ - if (scan_code & 0x80) - kbd_flags |= BRK; - else - kbd_flags &= ~BRK; - - if ((scan_code == 0xe1) || (kbd_flags & E1)) - { - if (scan_code == 0xe1) - { - kbd_flags ^= BRK; /* reset the break flag */ - kbd_flags ^= E1; /* bitwise EXOR with E1 flag */ + if (scan_code == 0xe0) { + kbd_flags |= EXT; + return; } - return; - } - scan_code &= 0x7f; + /* if high bit of scan_code, set break flag */ + if (scan_code & 0x80) + kbd_flags |= BRK; + else + kbd_flags &= ~BRK; + + if ((scan_code == 0xe1) || (kbd_flags & E1)) { + if (scan_code == 0xe1) { + kbd_flags ^= BRK; /* reset the break flag */ + kbd_flags ^= E1; /* bitwise EXOR with E1 flag */ + } + return; + } - if (kbd_flags & EXT) - { - int i; + scan_code &= 0x7f; + + if (kbd_flags & EXT) { + int i; + + kbd_flags ^= EXT; + for (i = 0; ext_key_map[i]; i++) { + if (ext_key_map[i] == scan_code) { + scan_code = 0x80 + i; + break; + } + } + /* not found ? */ + if (!ext_key_map[i]) + return; + } - kbd_flags ^= EXT; - for (i=0; ext_key_map[i]; i++) - { - if (ext_key_map[i] == scan_code) - { - scan_code = 0x80 + i; + switch (kbd_fct_map[scan_code]) { + case AS: + kbd_normal(scan_code); + break; + case SH: + kbd_shift(scan_code); + break; + case CN: + kbd_ctrl(scan_code); + break; + case NM: + kbd_num(scan_code); + break; + case CP: + kbd_caps(scan_code); + break; + case ST: + kbd_scroll(scan_code); + break; + case AK: + kbd_alt(scan_code); break; - } } - /* not found ? */ - if (!ext_key_map[i]) - return; - } - - switch (kbd_fct_map [scan_code]) - { - case AS: kbd_normal (scan_code); - break; - case SH: kbd_shift (scan_code); - break; - case CN: kbd_ctrl (scan_code); - break; - case NM: kbd_num (scan_code); - break; - case CP: kbd_caps (scan_code); - break; - case ST: kbd_scroll (scan_code); - break; - case AK: kbd_alt (scan_code); - break; - } - return; + return; } /******************************************************************************/ -static void kbd_normal (unsigned char scan_code) +static void kbd_normal(unsigned char scan_code) { - unsigned char chr; - - if ((kbd_flags & BRK) == NORMAL) - { - chr = kbd_key_map [kbd_mapping][kbd_state][scan_code]; - if ((chr == 0xff) || (chr == 0x00)) - { - return; + unsigned char chr; + + if ((kbd_flags & BRK) == NORMAL) { + chr = kbd_key_map[kbd_mapping][kbd_state][scan_code]; + if ((chr == 0xff) || (chr == 0x00)) + return; + + /* if caps lock convert upper to lower */ + if (((kbd_flags & CAPS) == CAPS) && + (chr >= 'a' && chr <= 'z')) { + chr -= 'a' - 'A'; + } + kbd_input = chr; } - - /* if caps lock convert upper to lower */ - if (((kbd_flags & CAPS) == CAPS) && (chr >= 'a' && chr <= 'z')) - { - chr -= 'a' - 'A'; - } - kbd_input = chr; - } } /******************************************************************************/ -static void kbd_shift (unsigned char scan_code) +static void kbd_shift(unsigned char scan_code) { - if ((kbd_flags & BRK) == BRK) - { - kbd_state = AS; - kbd_flags &= (~SHIFT); - } - else - { - kbd_state = SH; - kbd_flags |= SHIFT; - } + if ((kbd_flags & BRK) == BRK) { + kbd_state = AS; + kbd_flags &= (~SHIFT); + } else { + kbd_state = SH; + kbd_flags |= SHIFT; + } } /******************************************************************************/ -static void kbd_ctrl (unsigned char scan_code) +static void kbd_ctrl(unsigned char scan_code) { - if ((kbd_flags & BRK) == BRK) - { - kbd_state = AS; - kbd_flags &= (~CTRL); - } - else - { - kbd_state = CN; - kbd_flags |= CTRL; - } + if ((kbd_flags & BRK) == BRK) { + kbd_state = AS; + kbd_flags &= (~CTRL); + } else { + kbd_state = CN; + kbd_flags |= CTRL; + } } /******************************************************************************/ -static void kbd_caps (unsigned char scan_code) +static void kbd_caps(unsigned char scan_code) { - if ((kbd_flags & BRK) == NORMAL) - { - kbd_flags ^= CAPS; - kbd_led_set (); /* update keyboard LED */ - } + if ((kbd_flags & BRK) == NORMAL) { + kbd_flags ^= CAPS; + kbd_led_set(); /* update keyboard LED */ + } } /******************************************************************************/ -static void kbd_num (unsigned char scan_code) +static void kbd_num(unsigned char scan_code) { - if ((kbd_flags & BRK) == NORMAL) - { - kbd_flags ^= NUM; - kbd_state = (kbd_flags & NUM) ? AS : NM; - kbd_led_set (); /* update keyboard LED */ - } + if ((kbd_flags & BRK) == NORMAL) { + kbd_flags ^= NUM; + kbd_state = (kbd_flags & NUM) ? AS : NM; + kbd_led_set(); /* update keyboard LED */ + } } /******************************************************************************/ -static void kbd_scroll (unsigned char scan_code) +static void kbd_scroll(unsigned char scan_code) { - if ((kbd_flags & BRK) == NORMAL) - { - kbd_flags ^= STP; - kbd_led_set (); /* update keyboard LED */ - if (kbd_flags & STP) - kbd_input = 0x13; - else - kbd_input = 0x11; - } + if ((kbd_flags & BRK) == NORMAL) { + kbd_flags ^= STP; + kbd_led_set(); /* update keyboard LED */ + if (kbd_flags & STP) + kbd_input = 0x13; + else + kbd_input = 0x11; + } } /******************************************************************************/ -static void kbd_alt (unsigned char scan_code) +static void kbd_alt(unsigned char scan_code) { - if ((kbd_flags & BRK) == BRK) - { - kbd_state = AS; - kbd_flags &= (~ALT); - } - else - { - kbd_state = AK; - kbd_flags &= ALT; - } + if ((kbd_flags & BRK) == BRK) { + kbd_state = AS; + kbd_flags &= (~ALT); + } else { + kbd_state = AK; + kbd_flags &= ALT; + } } /******************************************************************************/ -static void kbd_led_set (void) +static void kbd_led_set(void) { - kbd_input_empty(); - out8 (I8042_DATA_REG, 0xed); /* SET LED command */ - kbd_input_empty(); - out8 (I8042_DATA_REG, (kbd_flags & 0x7)); /* LED bits only */ + kbd_input_empty(); + out8(I8042_DATA_REG, 0xed); /* SET LED command */ + kbd_input_empty(); + out8(I8042_DATA_REG, (kbd_flags & 0x7)); /* LED bits only */ } /******************************************************************************/ -static int kbd_input_empty (void) +static int kbd_input_empty(void) { - int kbdTimeout = KBD_TIMEOUT; + int kbdTimeout = KBD_TIMEOUT; - /* wait for input buf empty */ - while ((in8 (I8042_STATUS_REG) & 0x02) && kbdTimeout--) - udelay(1000); + /* wait for input buf empty */ + while ((in8(I8042_STATUS_REG) & 0x02) && kbdTimeout--) + udelay(1000); - return kbdTimeout; + return kbdTimeout; } /******************************************************************************/ -static int kbd_reset (void) +static int kbd_reset(void) { - if (kbd_input_empty() == 0) - return -1; + if (kbd_input_empty() == 0) + return -1; - out8 (I8042_DATA_REG, 0xff); + out8(I8042_DATA_REG, 0xff); - udelay(250000); + udelay(250000); - if (kbd_input_empty() == 0) - return -1; + if (kbd_input_empty() == 0) + return -1; #ifdef CONFIG_USE_CPCIDVI - out8 (I8042_COMMAND_REG, 0x60); + out8(I8042_COMMAND_REG, 0x60); #else - out8 (I8042_DATA_REG, 0x60); + out8(I8042_DATA_REG, 0x60); #endif - if (kbd_input_empty() == 0) - return -1; + if (kbd_input_empty() == 0) + return -1; - out8 (I8042_DATA_REG, 0x45); + out8(I8042_DATA_REG, 0x45); - if (kbd_input_empty() == 0) - return -1; + if (kbd_input_empty() == 0) + return -1; - out8 (I8042_COMMAND_REG, 0xae); + out8(I8042_COMMAND_REG, 0xae); - if (kbd_input_empty() == 0) - return -1; + if (kbd_input_empty() == 0) + return -1; - return 0; + return 0; } -- cgit v0.10.2 From 22e0f5a9ecab85f36a0fe69892d950c1ac212c91 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 14 Nov 2011 20:18:12 +0000 Subject: x86: Fix some bugs in the i8402 driver when no controller is present If no controller is present, the i8402 driver should return immediately and not attempt to operate on the missing hardware. In kbd_input_empty, the status register is checked every millisecond to see whether the input buffer is empty, up to a timeout which is tracked by decrimenting a counter each time the check is performed. The decrement is performed with a postfix -- operator, and the value of the counter is checked in place. That means that when the counter reaches zero and the loop terminates, it will actually be decrimented one more time and become -1. That value is returned as the return value of the function. That would give the right answer if it wasn't for that extra decrement because a timeout would indicate that the buffer never became empty. This change fixes both of those bugs. Signed-off-by: Gabe Black diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index 83b1bf4..c3bc536 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -313,6 +313,13 @@ static unsigned char ext_key_map[] = { 0x00 /* map end */ }; +/******************************************************************************/ + +static int kbd_controller_present(void) +{ + return in8(I8042_STATUS_REG) != 0xff; +} + /******************************************************************************* * * i8042_kbd_init - reset keyboard and init state flags @@ -322,6 +329,9 @@ int i8042_kbd_init(void) int keymap, try; char *penv; + if (!kbd_controller_present()) + return -1; + #ifdef CONFIG_USE_CPCIDVI penv = getenv("console"); if (penv != NULL) { @@ -603,7 +613,7 @@ static int kbd_input_empty(void) while ((in8(I8042_STATUS_REG) & 0x02) && kbdTimeout--) udelay(1000); - return kbdTimeout; + return kbdTimeout != -1; } /******************************************************************************/ -- cgit v0.10.2 From 43f082bb7fc1c24b32a4abc693869c7d14d42829 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 22 Nov 2011 06:51:15 -0600 Subject: powerpc/85xx: Add workaround for erratum CPU-A003999 Erratum A-003999: Running Floating Point instructions requires special initialization. Impact: Floating point arithmetic operations may result in an incorrect value. Workaround: Perform a read modify write to set bit 7 to a 1 in SPR 977 before executing any floating point arithmetic operation. This bit can be set when setting MSR[FP], and can be cleared when clearing MSR[FP]. Alternatively, the bit can be set once at boot time, and never cleared. There will be no performance degradation due to setting this bit. Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 253bf08..523f297 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -53,6 +53,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) puts("Work-around for Erratum CPU22 enabled\n"); #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) + puts("Work-around for Erratum CPU-A003999 enabled\n"); +#endif #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 6678ed4..c81e19c 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -68,6 +68,12 @@ __secondary_start_page: mtspr SPRN_HID1,r3 #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 + mfspr r3,977 + oris r3,r3,0x0100 + mtspr 977,r3 +#endif + /* Enable branch prediction */ lis r3,BUCSR_ENABLE@h ori r3,r3,BUCSR_ENABLE@l diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 7bd5cc0..4d37d6e 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -253,6 +253,12 @@ l2_disabled: mtspr HID1,r0 #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 + mfspr r3,977 + oris r3,r3,0x0100 + mtspr 977,r3 +#endif + /* Enable Branch Prediction */ #if defined(CONFIG_BTB) lis r0,BUCSR_ENABLE@h diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 981d639..f1da82e 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -313,6 +313,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #elif defined(CONFIG_PPC_P2041) #define CONFIG_MAX_CPUS 4 @@ -331,6 +332,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -349,6 +351,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #elif defined(CONFIG_PPC_P3060) #define CONFIG_MAX_CPUS 8 @@ -364,6 +367,7 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 @@ -374,6 +378,7 @@ #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -402,6 +407,7 @@ #define CONFIG_SYS_P4080_ERRATUM_SERDES9 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) -- cgit v0.10.2 From 33c875366e1d3e433881a86704816cdad847532f Mon Sep 17 00:00:00 2001 From: Jia Hongtao Date: Tue, 15 Nov 2011 15:04:11 +0800 Subject: powerpc/85xx: fixup flexcan device tree clock-frequency Make the fixup matchable with dts and kernel. Update the compatible from "fsl,flexcan-v1.0" to "fsl,p1010-flexcan" and Change the "clock-freq" property to "clock-frequency". We also change flexcan frequency from CCB-clock to CCB-clock/2 according to P1010 spec. We now keep the old interfaces to make previous kernel work. They should be removed in the future. Signed-off-by: Jia Hongtao Signed-off-by: Li Yang Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 9d31568..a53a31d 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -660,8 +660,19 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", "timer-frequency", gd->bus_clk/2, 1); + /* + * clock-freq should change to clock-frequency and + * flexcan-v1.0 should change to p1010-flexcan respectively + * in the future. + */ do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", - "clock_freq", gd->bus_clk, 1); + "clock_freq", gd->bus_clk/2, 1); + + do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", + "clock-frequency", gd->bus_clk/2, 1); + + do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan", + "clock-frequency", gd->bus_clk/2, 1); fdt_fixup_usb(blob); } -- cgit v0.10.2 From 4108508a96972e1200867666890d19fb63f76025 Mon Sep 17 00:00:00 2001 From: York Sun Date: Sun, 20 Nov 2011 10:01:35 -0800 Subject: powerpc/85xx: Add workaround for erratum A-003474 Erratum A-003474: Internal DDR calibration circuit is not supported Impact: Experience shows no significant benefit to device operation with auto-calibration enabled versus it disabled. To ensure consistent timing results, Freescale recommends this feature be disabled in future customer products. There should be no impact to parts that are already operating in the field. Workaround: Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following: 1. Write a value of 0x0000_0015 to the register at offset CCSRBAR + DDR OFFSET + 0xf30 2. Write a value of 0x2400_0000 to the register at offset CCSRBAR + DDR OFFSET + 0xf54 Signed-off-by: York Sun Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 523f297..2ed5a98 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -56,6 +56,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) puts("Work-around for Erratum CPU-A003999 enabled\n"); #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474) + puts("Work-around for Erratum DDR-A003473 enabled\n"); +#endif #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index c8c84a1..18e9cc5 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -115,6 +115,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, for (i = 0; i < 32; i++) out_be32(&ddr->debug[i], regs->debug[i]); +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 + out_be32(&ddr->debug[12], 0x00000015); + out_be32(&ddr->debug[21], 0x24000000); +#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */ + /* Set, but do not enable the memory */ temp_sdram_cfg = regs->ddr_sdram_cfg; temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index f1da82e..2e4be34 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -314,6 +314,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P2041) #define CONFIG_MAX_CPUS 4 @@ -333,6 +334,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -352,6 +354,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P3060) #define CONFIG_MAX_CPUS 8 @@ -379,6 +382,7 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -408,6 +412,7 @@ #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) @@ -427,6 +432,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 @@ -445,6 +451,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #else #error Processor type not defined for this platform -- cgit v0.10.2 From 3e0529f742e893653848494ffb9f7cd0d91304bf Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 21 Nov 2011 17:10:22 -0600 Subject: powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA controller, so it should be defined in config_mpc85xx.h instead of the various board header files. So now CONFIG_FSL_SATA_V2 is always defined on the P1013, P1022, P2041, P3041, P5010, and P5020. It was already defined for the P1010 and P1014. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 2e4be34..8654625 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -150,6 +150,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -237,6 +238,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -321,6 +323,7 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -341,6 +344,7 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -420,6 +424,7 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -439,6 +444,7 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 1158fec..70d751d 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -345,7 +345,6 @@ /* SATA */ #define CONFIG_LIBATA #define CONFIG_FSL_SATA -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 6d45bb1..f9fe3cf 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -446,10 +446,9 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_PCI */ /* SATA */ -#define CONFIG_FSL_SATA_V2 -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA #define CONFIG_FSL_SATA +#ifdef CONFIG_FSL_SATA +#define CONFIG_LIBATA #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index 57d5de5..98e7a42 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -32,7 +32,6 @@ #define CONFIG_MMC #define CONFIG_NAND_FSL_ELBC -#define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE3 #define CONFIG_PCIE4 #define CONFIG_SYS_DPAA_RMAN diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index a9cee23..4afc4f1 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -32,7 +32,6 @@ #define CONFIG_MMC #define CONFIG_NAND_FSL_ELBC -#define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE3 #define CONFIG_PCIE4 #define CONFIG_SYS_FSL_RAID_ENGINE -- cgit v0.10.2 From fbc20aab119b70119a2c1db7dfbecb4a6ee0f6a5 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 21 Nov 2011 17:10:23 -0600 Subject: powerpc/85xx: always implement the work-around for Erratum SATA_A001 On the P1022/P1013, the work-around for erratum SATA_A001 was implemented only if U-Boot initializes SATA, but SATA is not initialized by default. So move the work-around to the CPU initialization function, so that it's always executed on the SOCs that need it. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b9a8193..27aa038 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -37,12 +37,15 @@ #include #include #include +#include #include "mp.h" #ifdef CONFIG_SYS_QE_FW_IN_NAND #include #include #endif +#include "../../../../drivers/block/fsl_sata.h" + DECLARE_GLOBAL_DATA_PTR; extern void srio_init(void); @@ -301,6 +304,7 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); */ int cpu_init_r(void) { + __maybe_unused u32 svr = get_svr(); #ifdef CONFIG_SYS_LBC_LCRR volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; #endif @@ -316,10 +320,9 @@ int cpu_init_r(void) #if defined(CONFIG_L2_CACHE) volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; volatile uint cache_ctl; - uint svr, ver; + uint ver; u32 l2siz_field; - svr = get_svr(); ver = SVR_SOC_VER(svr); asm("msync;isync"); @@ -401,8 +404,8 @@ int cpu_init_r(void) puts("enabled\n"); } #elif defined(CONFIG_BACKSIDE_L2_CACHE) - if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || - (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) { + if ((SVR_SOC_VER(svr) == SVR_P2040) || + (SVR_SOC_VER(svr) == SVR_P2040_E)) { puts("N/A\n"); goto skip_l2; } @@ -488,6 +491,32 @@ skip_l2: fman_enet_init(); #endif +#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) + /* + * For P1022/1013 Rev1.0 silicon, after power on SATA host + * controller is configured in legacy mode instead of the + * expected enterprise mode. Software needs to clear bit[28] + * of HControl register to change to enterprise mode from + * legacy mode. We assume that the controller is offline. + */ + if (IS_SVR_REV(svr, 1, 0) && + ((SVR_SOC_VER(svr) == SVR_P1022) || + (SVR_SOC_VER(svr) == SVR_P1022_E) || + (SVR_SOC_VER(svr) == SVR_P1013) || + (SVR_SOC_VER(svr) == SVR_P1013_E))) { + fsl_sata_reg_t *reg; + + /* first SATA controller */ + reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; + clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); + + /* second SATA controller */ + reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; + clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); + } +#endif + + return 0; } diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index 6b35173..3026ade 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -197,27 +197,6 @@ int init_sata(int dev) /* Wait the controller offline */ ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000); -#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) - /* - * For P1022/1013 Rev1.0 silicon, after power on SATA host - * controller is configured in legacy mode instead of the - * expected enterprise mode. software needs to clear bit[28] - * of HControl register to change to enterprise mode from - * legacy mode. - */ - { - u32 svr = get_svr(); - if (IS_SVR_REV(svr, 1, 0) && - ((SVR_SOC_VER(svr) == SVR_P1022) || - (SVR_SOC_VER(svr) == SVR_P1022_E) || - (SVR_SOC_VER(svr) == SVR_P1013) || - (SVR_SOC_VER(svr) == SVR_P1013_E))) { - out_le32(®->hstatus, 0x20000000); - out_le32(®->hcontrol, 0x00000100); - } - } -#endif - /* Set the command header base address to CHBA register to tell DMA */ out_le32(®->chba, (u32)cmd_hdr & ~0x3); diff --git a/drivers/block/fsl_sata.h b/drivers/block/fsl_sata.h index 576efaf..cecff68 100644 --- a/drivers/block/fsl_sata.h +++ b/drivers/block/fsl_sata.h @@ -103,6 +103,7 @@ typedef struct fsl_sata_reg { */ #define HCONTROL_ONOFF 0x80000000 /* Online or offline request */ #define HCONTROL_FORCE_OFFLINE 0x40000000 /* Force offline request */ +#define HCONTROL_ENTERPRISE_EN 0x10000000 /* Enterprise mode enabled */ #define HCONTROL_HDR_SNOOP 0x00000400 /* Command header snoop */ #define HCONTROL_PMP_ATTACHED 0x00000200 /* Port multiplier attached */ -- cgit v0.10.2 From f2717b47eac74fe262d89c6d8f6bb5a047a77229 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 22 Nov 2011 09:21:25 -0600 Subject: powerpc/85xx: clean up and document the QE/FMAN microcode macros Several macros are used to identify and locate the microcode binary image that U-boot needs to upload to the QE or Fman. Both the QE and the Fman use the QE Firmware binary format to package their respective microcode data, which is why the same macros are used for both. A given SOC will only have a QE or an Fman, so this is safe. Unfortunately, the current macro definition and usage has inconsistencies. For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address of NAND. There's no way to know by looking at a variable how it's supposed to be used. In the future, the code which uploads QE firmware and Fman firmware will be merged. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala diff --git a/README b/README index 07f1d11..fda0190 100644 --- a/README +++ b/README @@ -3274,6 +3274,44 @@ Low Level (hardware related) configuration options: be used if available. These functions may be faster under some conditions but may increase the binary size. +Freescale QE/FMAN Firmware Support: +----------------------------------- + +The Freescale QUICCEngine (QE) and Frame Manager (FMAN) both support the +loading of "firmware", which is encoded in the QE firmware binary format. +This firmware often needs to be loaded during U-Boot booting, so macros +are used to identify the storage device (NOR flash, SPI, etc) and the address +within that device. + +- CONFIG_SYS_QE_FMAN_FW_ADDR + The address in the storage device where the firmware is located. The + meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro + is also specified. + +- CONFIG_SYS_QE_FMAN_FW_LENGTH + The maximum possible size of the firmware. The firmware binary format + has a field that specifies the actual size of the firmware, but it + might not be possible to read any part of the firmware unless some + local storage is allocated to hold the entire firmware first. + +- CONFIG_SYS_QE_FMAN_FW_IN_NOR + Specifies that QE/FMAN firmware is located in NOR flash, mapped as + normal addressable memory via the LBC. CONFIG_SYS_FMAN_FW_ADDR is the + virtual address in NOR flash. + +- CONFIG_SYS_QE_FMAN_FW_IN_NAND + Specifies that QE/FMAN firmware is located in NAND flash. + CONFIG_SYS_FMAN_FW_ADDR is the offset within NAND flash. + +- CONFIG_SYS_QE_FMAN_FW_IN_MMC + Specifies that QE/FMAN firmware is located on the primary SD/MMC + device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device. + +- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH + Specifies that QE/FMAN firmware is located on the primary SPI + device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device. + + Building the Software: ====================== diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 27aa038..2e4a06c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -39,7 +39,7 @@ #include #include #include "mp.h" -#ifdef CONFIG_SYS_QE_FW_IN_NAND +#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include #include #endif @@ -552,17 +552,17 @@ void cpu_secondary_init_r(void) { #ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ -#ifdef CONFIG_SYS_QE_FW_IN_NAND +#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND int ret; - size_t fw_length = CONFIG_SYS_QE_FW_LENGTH; + size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; /* load QE firmware from NAND flash to DDR first */ - ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND, - &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); + ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, + &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); if (ret && ret == -EUCLEAN) { printf ("NAND read for QE firmware at offset %x failed %d\n", - CONFIG_SYS_QE_FW_IN_NAND, ret); + CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); } #endif qe_init(qe_base); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index a53a31d..62c7ea1 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -466,7 +466,7 @@ void fdt_fixup_fman_firmware(void *blob) return; } - if (length > CONFIG_SYS_FMAN_FW_LENGTH) { + if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) { printf("Fman firmware at %p is too large (size=%u)\n", fmanfw, length); return; diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 846c372..0b8c33f 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -25,11 +25,11 @@ #include "fm.h" #include "../../qe/qe.h" /* For struct qe_firmware */ -#ifdef CONFIG_SYS_QE_FW_IN_NAND +#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH) #include -#elif defined(CONFIG_SYS_QE_FW_IN_MMC) +#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC) #include #endif @@ -363,21 +363,21 @@ int fm_init_common(int index, struct ccsr_fman *reg) { int rc; char env_addr[32]; -#if defined(CONFIG_SYS_FMAN_FW_ADDR) - void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR; -#elif defined(CONFIG_SYS_QE_FW_IN_NAND) - size_t fw_length = CONFIG_SYS_FMAN_FW_LENGTH; - void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH); +#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR) + void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; +#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND) + size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; + void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); - rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND, + rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_ADDR, &fw_length, (u_char *)addr); if (rc == -EUCLEAN) { printf("NAND read of FMAN firmware at offset 0x%x failed %d\n", - CONFIG_SYS_QE_FW_IN_NAND, rc); + CONFIG_SYS_QE_FMAN_FW_ADDR, rc); } #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH) struct spi_flash *ucode_flash; - void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH); + void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); int ret = 0; ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, @@ -385,17 +385,17 @@ int fm_init_common(int index, struct ccsr_fman *reg) if (!ucode_flash) printf("SF: probe for ucode failed\n"); else { - ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FW_IN_SPIFLASH, - CONFIG_SYS_FMAN_FW_LENGTH, addr); + ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FMAN_FW_ADDR, + CONFIG_SYS_QE_FMAN_FW_LENGTH, addr); if (ret) printf("SF: read for ucode failed\n"); spi_flash_free(ucode_flash); } -#elif defined(CONFIG_SYS_QE_FW_IN_MMC) +#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC) int dev = CONFIG_SYS_MMC_ENV_DEV; - void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH); - u32 cnt = CONFIG_SYS_FMAN_FW_LENGTH / 512; - u32 blk = CONFIG_SYS_QE_FW_IN_MMC / 512; + void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; + u32 blk = CONFIG_SYS_QE_FMAN_FW_ADDR / 512; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); if (!mmc) diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index c4ec2f4..9f71151 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -170,11 +170,11 @@ void qe_init(uint qe_base) /* Init the QE IMMR base */ qe_immr = (qe_map_t *)qe_base; -#ifdef CONFIG_SYS_QE_FW_ADDR +#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NOR /* * Upload microcode to IRAM for those SOCs which do not have ROM in QE. */ - qe_upload_firmware((const struct qe_firmware *) CONFIG_SYS_QE_FW_ADDR); + qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR); /* enable the microcode in IRAM */ out_be32(&qe_immr->iram.iready,QE_IRAM_READY); diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index ab27b98..7a5d86d 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -510,7 +510,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ /* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FW_ADDR 0xfff00000 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000 /* * BOOTP options diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index 013a6ac..e057b1f 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -526,12 +526,14 @@ extern unsigned long get_clock_freq(void); #ifndef CONFIG_NAND /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 #else -#define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000 +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000 #endif -#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index f9fe3cf..a48055e 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -414,21 +414,25 @@ unsigned long get_board_sys_clk(unsigned long dummy); * env is stored at 0x100000, sector size is 0x10000, ucode is stored after * env, so we got 0x110000. */ -#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000 +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is * about 545KB (1089 blocks), Env is stored after the image, and the env size is * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. */ -#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) #elif defined(CONFIG_NAND) -#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) #else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 #endif -#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index bc0aeeb..0622b9f 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -474,21 +474,25 @@ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after * env, so we got 0x110000. */ -#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000 +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is * about 545KB (1089 blocks), Env is stored after the image, and the env size is * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. */ -#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) #elif defined(CONFIG_NAND) -#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) #else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 #endif -#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 5a69902..8e8fa16 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -677,8 +677,9 @@ #ifdef CONFIG_QE /* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FW_ADDR 0xefec0000 -#define CONFIG_SYS_QE_FW_LENGTH 0x10000 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #endif /* CONFIG_QE */ #ifdef CONFIG_P1025RDB -- cgit v0.10.2 From ae6b03fefc1a8b27d834ef12e0a586f4237fdb1f Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Tue, 22 Nov 2011 16:51:13 +0800 Subject: powerpc/p3060qds: Add board related support for P3060QDS platform The P3060QDS is a Freescale reference board for the six-core P3060 SOC. P3060QDS Board Overview: Memory subsystem: - 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus) - 128M Bytes NOR flash single-chip memory - 16M Bytes SPI flash - 8K Bytes AT24C64 I2C EEPROM for RCW Ethernet: - Eight Ethernet controllers (4x1G + 4x1G/2.5G) - Three VSC8641 PHYs on board (2xRGMII + 1xMII) - Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3 PCIe: Two PCI Express 2.0 controllers/ports USB: Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board I2C: Four I2C controllers UART: Supports two dUARTs up to 115200 bps for console RapidIO: Two RapidIO, sRIO1 and sRIO2 Signed-off-by: Shengzhou Liu Signed-off-by: York Sun Signed-off-by: Kumar Gala diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 353d3c6..9077aaf 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_FSL_VIA) += cds_via.o COBJS-$(CONFIG_FMAN_ENET) += fman.o COBJS-$(CONFIG_FSL_PIXIS) += pixis.o COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o +COBJS-$(CONFIG_FSL_QIXIS) += qixis.o COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o @@ -50,12 +51,14 @@ COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o COBJS-$(CONFIG_P1022DS) += ics307_clk.o COBJS-$(CONFIG_P2020DS) += ics307_clk.o COBJS-$(CONFIG_P3041DS) += ics307_clk.o +COBJS-$(CONFIG_P3060QDS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o COBJS-$(CONFIG_P5020DS) += ics307_clk.o # deal with common files for P-series corenet based devices SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o +SUBLIB-$(CONFIG_P3060QDS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c index 6acbc36..95a3cd7 100644 --- a/board/freescale/common/ics307_clk.c +++ b/board/freescale/common/ics307_clk.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -25,10 +25,15 @@ #include "ics307_clk.h" -#ifdef CONFIG_FSL_NGPIXIS +#if defined(CONFIG_FSL_NGPIXIS) #include "ngpixis.h" +#define fpga_reg pixis +#elif defined(CONFIG_FSL_QIXIS) +#include "qixis.h" +#define fpga_reg ((struct qixis *)QIXIS_BASE) #else #include "pixis.h" +#define fpga_reg pixis #endif /* define for SYS CLK or CLK1Frequency */ @@ -143,15 +148,15 @@ static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) unsigned long get_board_sys_clk(void) { return ics307_clk_freq( - in_8(&pixis->sclk[0]), - in_8(&pixis->sclk[1]), - in_8(&pixis->sclk[2])); + in_8(&fpga_reg->sclk[0]), + in_8(&fpga_reg->sclk[1]), + in_8(&fpga_reg->sclk[2])); } unsigned long get_board_ddr_clk(void) { return ics307_clk_freq( - in_8(&pixis->dclk[0]), - in_8(&pixis->dclk[1]), - in_8(&pixis->dclk[2])); + in_8(&fpga_reg->dclk[0]), + in_8(&fpga_reg->dclk[1]), + in_8(&fpga_reg->dclk[2])); } diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c new file mode 100644 index 0000000..6cd7e51 --- /dev/null +++ b/board/freescale/common/qixis.c @@ -0,0 +1,151 @@ +/* + * Copyright 2011 Freescale Semiconductor + * Author: Shengzhou Liu + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the QIXIS of some Freescale reference boards. + * + */ + +#include +#include +#include +#include "qixis.h" + +u8 qixis_read(unsigned int reg) +{ + void *p = (void *)QIXIS_BASE; + + return in_8(p + reg); +} + +void qixis_write(unsigned int reg, u8 value) +{ + void *p = (void *)QIXIS_BASE; + + out_8(p + reg, value); +} + +void qixis_reset(void) +{ + QIXIS_WRITE(rst_ctl, 0x83); +} + +void qixis_bank_reset(void) +{ + QIXIS_WRITE(rcfg_ctl, 0x20); + QIXIS_WRITE(rcfg_ctl, 0x21); +} + +/* Set the boot bank to the power-on default bank0 */ +void clear_altbank(void) +{ + u8 reg; + + reg = QIXIS_READ(brdcfg[0]); + reg = reg & ~QIXIS_LBMAP_MASK; + QIXIS_WRITE(brdcfg[0], reg); +} + +/* Set the boot bank to the alternate bank */ +void set_altbank(void) +{ + u8 reg; + + reg = QIXIS_READ(brdcfg[0]); + reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK; + QIXIS_WRITE(brdcfg[0], reg); +} + +#ifdef DEBUG +static void qixis_dump_regs(void) +{ + int i; + + printf("id = %02x\n", QIXIS_READ(id)); + printf("arch = %02x\n", QIXIS_READ(arch)); + printf("scver = %02x\n", QIXIS_READ(scver)); + printf("model = %02x\n", QIXIS_READ(model)); + printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl)); + printf("aux = %02x\n", QIXIS_READ(aux)); + for (i = 0; i < 16; i++) + printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i])); + for (i = 0; i < 16; i++) + printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i])); + printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]), + QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2])); + printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]), + QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2])); + printf("aux = %02x\n", QIXIS_READ(aux)); + printf("watch = %02x\n", QIXIS_READ(watch)); + printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys)); + printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl)); + printf("present = %02x\n", QIXIS_READ(present)); + printf("clk_spd = %02x\n", QIXIS_READ(clk_spd)); + printf("stat_dut = %02x\n", QIXIS_READ(stat_dut)); + printf("stat_sys = %02x\n", QIXIS_READ(stat_sys)); + printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm)); + printf("ctl_sys2 = %02x\n", QIXIS_READ(ctl_sys2)); +} +#endif + +int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + + if (argc <= 1) { + clear_altbank(); + qixis_reset(); + } else if (strcmp(argv[1], "altbank") == 0) { + set_altbank(); + qixis_bank_reset(); + } else if (strcmp(argv[1], "watchdog") == 0) { + static char *period[9] = {"2s", "4s", "8s", "16s", "32s", + "1min", "2min", "4min", "8min"}; + u8 rcfg = QIXIS_READ(rcfg_ctl); + + if (argv[2] == NULL) { + printf("qixis watchdog \n"); + return 0; + } + for (i = 0; i < ARRAY_SIZE(period); i++) { + if (strcmp(argv[2], period[i]) == 0) { + /* disable watchdog */ + QIXIS_WRITE(rcfg_ctl, rcfg & ~0x08); + QIXIS_WRITE(watch, ((i<<2) - 1)); + QIXIS_WRITE(rcfg_ctl, rcfg); + return 0; + } + } + } + +#ifdef DEBUG + else if (strcmp(argv[1], "dump") == 0) { + qixis_dump_regs(); + return 0; + } +#endif + + else { + printf("Invalid option: %s\n", argv[1]); + return 1; + } + + return 0; +} + +U_BOOT_CMD( + qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd, + "Reset the board using the FPGA sequencer", + "- hard reset to default bank\n" + "qixis_reset altbank - reset to alternate bank\n" + "qixis watchdog - set the watchdog period\n" + " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" +#ifdef DEBUG + "qixis_reset dump - display the QIXIS registers\n" +#endif + ); diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h new file mode 100644 index 0000000..7a0268a --- /dev/null +++ b/board/freescale/common/qixis.h @@ -0,0 +1,101 @@ +/* + * Copyright 2011 Freescale Semiconductor + * Author: Shengzhou Liu + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the QIXIS of some Freescale reference boards. + */ + +#ifndef __QIXIS_H_ +#define __QIXIS_H_ + +struct qixis { + u8 id; /* ID value uniquely identifying each QDS board type */ + u8 arch; /* Board version information */ + u8 scver; /* QIXIS Version Register */ + u8 model; /* Information of software programming model version */ + u8 tagdata; + u8 ctl_sys; + u8 aux; /* Auxiliary Register,0x06 */ + u8 clk_spd; + u8 stat_dut; + u8 stat_sys; + u8 stat_alrm; + u8 present; + u8 ctl_sys2; + u8 rcw_ctl; + u8 ctl_led; + u8 i2cblk; + u8 rcfg_ctl; /* Reconfig Control Register,0x10 */ + u8 rcfg_st; + u8 dcm_ad; + u8 dcm_da; + u8 dcmd; + u8 dmsg; + u8 gdc; + u8 gdd; /* DCM Debug Data Register,0x17 */ + u8 dmack; + u8 res1[6]; + u8 watch; /* Watchdog Register,0x1F */ + u8 pwr_ctl[2]; /* Power Control Register,0x20 */ + u8 res2[2]; + u8 pwr_stat[4]; /* Power Status Register,0x24 */ + u8 res3[8]; + u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */ + u8 res4[2]; + u8 sclk[3]; /* Clock Configuration Registers,0x34 */ + u8 res5; + u8 dclk[3]; + u8 res6; + u8 clk_dspd[3]; + u8 res7; + u8 rst_ctl; /* Reset Control Register,0x40 */ + u8 rst_stat; /* Reset Status Register */ + u8 rst_rsn; /* Reset Reason Register */ + u8 rst_frc[2]; /* Reset Force Registers,0x43 */ + u8 res8[11]; + u8 brdcfg[16]; /* Board Configuration Register,0x50 */ + u8 dutcfg[16]; + u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */ + u8 rcw_data; + u8 res9[5]; + u8 post_ctl; + u8 post_stat; + u8 post_dat[2]; + u8 pi_d[4]; + u8 gpio_io[4]; + u8 gpio_dir[4]; + u8 res10[20]; + u8 rjtag_ctl; + u8 rjtag_dat; + u8 res11[2]; + u8 trig_src[4]; + u8 trig_dst[4]; + u8 trig_stat; + u8 res12[3]; + u8 trig_ctr[4]; + u8 res13[48]; + u8 aux2[4]; /* Auxiliary Registers,0xE0 */ + u8 res14[10]; + u8 aux_ad; + u8 aux_da; + u8 res15[16]; +}; + +#define QIXIS_BASE 0xffdf0000 +#define QIXIS_LBMAP_SWITCH 7 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_ALTBANK 0x04 + +u8 qixis_read(unsigned int reg); +void qixis_write(unsigned int reg, u8 value); + +#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg)) +#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) + +#endif diff --git a/board/freescale/p3060qds/Makefile b/board/freescale/p3060qds/Makefile new file mode 100644 index 0000000..ae136f4 --- /dev/null +++ b/board/freescale/p3060qds/Makefile @@ -0,0 +1,54 @@ +# +# Copyright 2011 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += eth.o +COBJS-y += fixed_ddr.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p3060qds/ddr.c b/board/freescale/p3060qds/ddr.c new file mode 100644 index 0000000..9affbf0 --- /dev/null +++ b/board/freescale/p3060qds/ddr.c @@ -0,0 +1,248 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "p3060qds.h" + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ + +phys_size_t fixed_sdram(void) +{ + int i; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + unsigned int lawbar1_target_id; + ulong ddr_freq, ddr_freq_mhz; + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; + + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && + (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, + fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + + /* + * setup laws for DDR. If not interleaving, presuming half memory on + * DDR1 and the other half on DDR2 + */ + if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) { + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, + LAW_TRGT_IF_DDR_INTRLV) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + } else { + lawbar1_target_id = LAW_TRGT_IF_DDR_1; + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, + lawbar1_target_id) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + } + return ddr_size; +} + +struct board_specific_params { + u32 n_ranks; + u32 datarate_mhz_high; + u32 clk_adjust; + u32 wrlvl_start; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +}; + +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_params udimm[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | |delay | + */ + {4, 850, 4, 6, 0xff, 2, 0}, + {4, 950, 5, 7, 0xff, 2, 0}, + {4, 1050, 5, 8, 0xff, 2, 0}, + {4, 1250, 5, 10, 0xff, 2, 0}, + {4, 1350, 5, 11, 0xff, 2, 0}, + {4, 1666, 5, 12, 0xff, 2, 0}, + {2, 850, 5, 6, 0xff, 2, 0}, + {2, 950, 5, 7, 0xff, 2, 0}, + {2, 1250, 4, 6, 0xff, 2, 0}, + {2, 1350, 5, 7, 0xff, 2, 0}, + {2, 1666, 5, 8, 0xff, 2, 0}, + {1, 850, 4, 5, 0xff, 2, 0}, + {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1666, 4, 8, 0xff, 2, 0}, + {} +}; + +static const struct board_specific_params rdimm[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | |delay | + */ + {4, 850, 4, 6, 0xff, 2, 0}, + {4, 950, 5, 7, 0xff, 2, 0}, + {4, 1050, 5, 8, 0xff, 2, 0}, + {4, 1250, 5, 10, 0xff, 2, 0}, + {4, 1350, 5, 11, 0xff, 2, 0}, + {4, 1666, 5, 12, 0xff, 2, 0}, + {2, 850, 4, 6, 0xff, 2, 0}, + {2, 1050, 4, 7, 0xff, 2, 0}, + {2, 1666, 4, 8, 0xff, 2, 0}, + {1, 850, 4, 5, 0xff, 2, 0}, + {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1666, 4, 8, 0xff, 2, 0}, + {} +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_params *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + if (popts->registered_dimm_en) + pbsp = rdimm; + else + pbsp = udimm; + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->twoT_en = pbsp->force_2T; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s!\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->twoT_en = pbsp_highest->force_2T; + } else { + panic("DIMM is not supported by this board"); + } + + +found: + + /* + * The datasheet of HMT125U7BFR8C-H9 blocks CL=7 as reservered. + * However SPD still claims CL=7 is supported. Extensive tests + * confirmed this board cannot work stably with CL=7 with this + * particular DIMM. + */ + if (ddr_freq >= 800 && ddr_freq < 1066 && \ + !strncmp(pdimm[0].mpart, "HMT125U7BFR8C-H9", 16)) { + popts->cas_latency_override = 1; + popts->cas_latency_override_value = 8; + debug("Override CL to 8\n"); + } + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 60 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing...."); + + if (fsl_use_spd()) { + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + } else { + puts("using fixed parameters\n"); + dram_size = fixed_sdram(); + } + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + debug(" DDR: "); + return dram_size; +} diff --git a/board/freescale/p3060qds/eth.c b/board/freescale/p3060qds/eth.c new file mode 100644 index 0000000..3f812db --- /dev/null +++ b/board/freescale/p3060qds/eth.c @@ -0,0 +1,482 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "../common/fman.h" + +#include "p3060qds_qixis.h" + +#define EMI_NONE 0xffffffff +#define EMI1_RGMII1 0 +#define EMI1_SLOT1 1 +#define EMI1_SLOT2 2 +#define EMI1_SLOT3 3 +#define EMI1_RGMII2 4 + +static int mdio_mux[NUM_FM_PORTS]; + +static char *mdio_names[5] = { + "P3060QDS_MDIO0", + "P3060QDS_MDIO1", + "P3060QDS_MDIO2", + "P3060QDS_MDIO3", + "P3060QDS_MDIO4", +}; + +/* + * Mapping of all 18 SERDES lanes to board slots. + * A value of '0' here means that the mapping must be determined + * dynamically, Lane 8/9/16/17 map to Slot1 or Aurora debug + */ +static u8 lane_to_slot[] = { + 4, 4, 4, 4, 3, 3, 3, 3, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0 +}; + +static char *p3060qds_mdio_name_for_muxval(u32 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u32 muxval) +{ + struct mii_dev *bus; + char *name = p3060qds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct p3060qds_mdio { + u32 muxval; + struct mii_dev *realbus; +}; + +static void p3060qds_mux_mdio(u32 muxval) +{ + u8 brdcfg4; + + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << 4); + QIXIS_WRITE(brdcfg[4], brdcfg4); +} + +static int p3060qds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct p3060qds_mdio *priv = bus->priv; + + p3060qds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int p3060qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct p3060qds_mdio *priv = bus->priv; + + p3060qds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int p3060qds_mdio_reset(struct mii_dev *bus) +{ + struct p3060qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int p3060qds_mdio_init(char *realbusname, u32 muxval) +{ + struct p3060qds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate P3060QDS MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate P3060QDS private data\n"); + free(bus); + return -1; + } + + bus->read = p3060qds_mdio_read; + bus->write = p3060qds_mdio_write; + bus->reset = p3060qds_mdio_reset; + sprintf(bus->name, p3060qds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, + enum fm_port port, int offset) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int srds_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + if (mdio_mux[port] == EMI1_RGMII1) + fdt_set_phy_handle(blob, prop, pa, "phy_rgmii1"); + + if (mdio_mux[port] == EMI1_RGMII2) + fdt_set_phy_handle(blob, prop, pa, "phy_rgmii2"); + + if ((mdio_mux[port] == EMI1_SLOT1) && ((srds_prtcl == 0x3) + || (srds_prtcl == 0x6))) { + switch (port) { + case FM2_DTSEC4: + fdt_set_phy_handle(blob, prop, pa, "phy2_slot1"); + break; + case FM1_DTSEC4: + fdt_set_phy_handle(blob, prop, pa, "phy3_slot1"); + break; + default: + break; + } + } + + if (mdio_mux[port] == EMI1_SLOT3) { + switch (port) { + case FM2_DTSEC3: + fdt_set_phy_handle(blob, prop, pa, "phy0_slot3"); + break; + case FM1_DTSEC3: + fdt_set_phy_handle(blob, prop, pa, "phy1_slot3"); + break; + default: + break; + } + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i, lane, idx; + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + + switch (mdio_mux[i]) { + case EMI1_SLOT1: + if (lane >= 14) { + fdt_status_okay_by_alias(fdt, + "emi1_slot1"); + fdt_status_disabled_by_alias(fdt, + "emi1_slot1_bk1"); + } else { + fdt_status_disabled_by_alias(fdt, + "emi1_slot1"); + fdt_status_okay_by_alias(fdt, + "emi1_slot1_bk1"); + } + break; + case EMI1_SLOT2: + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + break; + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC1) + fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); + + if (i == FM1_DTSEC2) + fdt_status_okay_by_alias(fdt, "emi1_rgmii2"); + break; + default: + break; + } + } +#if (CONFIG_SYS_NUM_FMAN == 2) + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + idx = i - FM2_DTSEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); + if (lane >= 0) { + switch (mdio_mux[i]) { + case EMI1_SLOT1: + if (lane >= 14) + fdt_status_okay_by_alias(fdt, + "emi1_slot1"); + else + fdt_status_okay_by_alias(fdt, + "emi1_slot1_bk1"); + break; + case EMI1_SLOT2: + fdt_status_okay_by_alias(fdt, + "emi1_slot2"); + break; + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, + "emi1_slot3"); + break; + } + } + break; + default: + break; + } + } +#endif +} + +static void initialize_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int sdprtl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + switch (sdprtl) { + case 0x03: + case 0x06: + lane_to_slot[8] = 1; + lane_to_slot[9] = lane_to_slot[8]; + lane_to_slot[16] = 5; + lane_to_slot[17] = lane_to_slot[16]; + break; + case 0x16: + case 0x19: + case 0x1C: + lane_to_slot[8] = 5; + lane_to_slot[9] = lane_to_slot[8]; + lane_to_slot[16] = 1; + lane_to_slot[17] = lane_to_slot[16]; + break; + default: + puts("Invalid SerDes protocol for P3060QDS\n"); + break; + } +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; + int i; + struct fsl_pq_mdio_info dtsec_mdio_info; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int srds_cfg = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + initialize_lane_to_slot(); + + /* + * Set TBIPA on FM1@DTSEC1. This is needed for configurations + * where FM1@DTSEC1 isn't used directly, since it provides + * MDIO for other ports. + */ + out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + /* Register the 5 muxing front-ends to the MDIO buses */ + if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII) + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + + if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII) + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + + if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII) + fm_info_set_phy_address(FM1_DTSEC1, 1); /* RGMII1 */ + else if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII) + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT2_PHY_ADDR); + + if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII) + fm_info_set_phy_address(FM1_DTSEC2, 2); /* RGMII2 */ + else if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_SGMII) + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + + fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT3_PHY_ADDR); + + switch (srds_cfg) { + case 0x03: + case 0x06: + fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0x16: + case 0x19: + case 0x1C: + fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); + break; + default: + puts("Invalid SerDes protocol for P3060QDS\n"); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1, lane, slot; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + if (QIXIS_READ(present) & (1 << (slot - 1))) + fm_disable_port(i); + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + }; + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC1) { + mdio_mux[i] = EMI1_RGMII1; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + } else if (i == FM1_DTSEC2) { + mdio_mux[i] = EMI1_RGMII2; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + } + break; + default: + break; + } + } + +#if (CONFIG_SYS_NUM_FMAN == 2) + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + int idx = i - FM2_DTSEC1, lane, slot; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + if (QIXIS_READ(present) & (1 << (slot - 1))) + fm_disable_port(i); + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + }; + break; + default: + break; + } + } +#endif /* CONFIG_SYS_NUM_FMAN */ + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/p3060qds/fixed_ddr.c b/board/freescale/p3060qds/fixed_ddr.c new file mode 100644 index 0000000..125988d --- /dev/null +++ b/board/freescale/p3060qds/fixed_ddr.c @@ -0,0 +1,214 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 +#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 +#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45 +#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912 +#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40 +#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000 +#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100 +#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104 +#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944 +#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF +#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830 +#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000 +#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100 +#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104 +#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844 +#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce +#define CONFIG_SYS_DDR_MODE_1_900 0x00441620 +#define CONFIG_SYS_DDR_MODE_2_900 0x00080000 +#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100 +#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc +#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 +#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 + +#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 +#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202 +#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 +#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5 0x02401400 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 +#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000 +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {750, 850, &ddr_cfg_regs_800}, + {850, 950, &ddr_cfg_regs_900}, + {950, 1050, &ddr_cfg_regs_1000}, + {1050, 1250, &ddr_cfg_regs_1200}, + {0, 0, NULL} +}; diff --git a/board/freescale/p3060qds/p3060qds.c b/board/freescale/p3060qds/p3060qds.c new file mode 100644 index 0000000..c6c74f2 --- /dev/null +++ b/board/freescale/p3060qds/p3060qds.c @@ -0,0 +1,341 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "p3060qds.h" +#include "p3060qds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + u8 sw; + struct cpu_type *cpu = gd->cpu; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + unsigned int i; + + printf("Board: %s", cpu->name); + puts("QDS, "); + + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("Promjet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else + printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); + +#ifdef CONFIG_PHYS_64BIT + puts("36-bit Addressing\n"); +#endif + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); + + puts("SERDES Reference Clocks: "); + sw = QIXIS_READ(brdcfg[2]); + for (i = 0; i < 3; i++) { + static const char * const freq[] = {"100", "125", "Reserved", + "156.25"}; + unsigned int clock = (sw >> (2 * i)) & 3; + + printf("Bank%u=%sMhz ", i+1, freq[clock]); + } + puts("\n"); + + return 0; +} + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* only single DDR controller on QDS board, disable DDR1_MCK4/5 */ + setbits_be32(&gur->ddrclkdr, 0x00030000); + + return 0; +} + +void board_config_serdes_mux(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int cfg = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + switch (cfg) { + case 0x03: + case 0x06: + /* set Lane I,J as SGMII */ + QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_B | BRDCFG6_SD3MX_A | + BRDCFG6_SD2MX_B | BRDCFG6_SD1MX_A); + break; + case 0x16: + case 0x19: + case 0x1c: + /* set Lane I,J as Aurora Debug */ + QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_A | BRDCFG6_SD3MX_B | + BRDCFG6_SD2MX_A | BRDCFG6_SD1MX_B); + break; + default: + puts("Invalid SerDes protocol for P3060QDS\n"); + break; + } +} + +void board_config_usb_mux(void) +{ + u8 brdcfg4, brdcfg5, brdcfg7; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr11 = in_be32(&gur->rcwsr[11]); + u32 ec1 = rcwsr11 & FSL_CORENET_RCWSR11_EC1; + u32 ec2 = rcwsr11 & FSL_CORENET_RCWSR11_EC2; + + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EC_MODE_MASK; + if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) && + (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) { + brdcfg4 |= BRDCFG4_EC2_USB_EC1_USB; + + } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) && + ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) || + (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) { + brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_USB; + + } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) && + (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) { + brdcfg4 |= BRDCFG4_EC2_USB_EC1_RGMII; + + } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) && + ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) || + (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) { + brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_RGMII; + } else { + brdcfg4 |= BRDCFG4_EC2_MII_EC1_MII; + } + QIXIS_WRITE(brdcfg[4], brdcfg4); + + brdcfg5 = QIXIS_READ(brdcfg[5]); + brdcfg5 &= ~(BRDCFG5_USB1ID_MASK | BRDCFG5_USB2ID_MASK); + brdcfg5 |= (BRDCFG5_USB1ID_CTRL | BRDCFG5_USB2ID_CTRL); + QIXIS_WRITE(brdcfg[5], brdcfg5); + + brdcfg7 = BRDCFG7_JTAGMX_COP_JTAG | BRDCFG7_IQ1MX_IRQ_EVT | + BRDCFG7_G1MX_USB1 | BRDCFG7_D1MX_TSEC3USB | BRDCFG7_I3MX_USB1; + QIXIS_WRITE(brdcfg[7], brdcfg7); +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + board_config_serdes_mux(); + board_config_usb_mux(); + + return 0; +} + +static const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + default: + return "150"; + } +} + +#define NUM_SRDS_BANKS 3 + +int misc_init_r(void) +{ + serdes_corenet_t *srds_regs; + u32 actual[NUM_SRDS_BANKS]; + unsigned int i; + u8 sw; + + sw = QIXIS_READ(brdcfg[2]); + for (i = 0; i < 3; i++) { + unsigned int clock = (sw >> (2 * i)) & 3; + switch (clock) { + case 0: + actual[i] = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 1: + actual[i] = SRDS_PLLCR0_RFCK_SEL_125; + break; + case 3: + actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; + break; + default: + printf("Warning: SDREFCLK%u switch setting of '10' is " + "unsupported\n", i + 1); + break; + } + } + + srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + for (i = 0; i < NUM_SRDS_BANKS; i++) { + u32 pllcr0 = in_be32(&srds_regs->bank[i].pllcr0); + u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + if (expected != actual[i]) { + printf("Warning: SERDES bank %u expects reference clock" + " %sMHz, but actual is %sMHz\n", i + 1, + serdes_clock_to_string(expected), + serdes_clock_to_string(actual[i])); + } + } + + return 0; +} + +/* + * This is map of CVDD values. 33 means CVDD is 3.3v, 25 means CVDD is 2.5v, + * 18 means CVDD is 1.8v. + */ +static u8 IO_VSEL[] = { + 33, 33, 33, 25, 25, 25, 18, 18, 18, + 33, 33, 33, 25, 25, 25, 18, 18, 18, + 33, 33, 33, 25, 25, 25, 18, 18, 18, + 33, 33, 33, 33, 33 +}; + +#define IO_VSEL_MASK 0x1f + +/* + * different CVDD selects diffenert spi flashs, read dutcfg[3] to get CVDD, + * then set status of spi flash nodes to 'disabled' according to CVDD. + * CVDD '33' will select spi flash0 and flash1, CVDD '25' will select spi + * flash2, CVDD '18' will select spi flash3. + */ +void fdt_fixup_board_spi(void *blob) +{ + u8 sw5 = QIXIS_READ(dutcfg[3]); + + switch (IO_VSEL[sw5 & IO_VSEL_MASK]) { + /* 3.3v */ + case 33: + do_fixup_by_compat(blob, "atmel,at45db081d", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "spansion,sst25wf040", "status", + "disabled", strlen("disabled") + 1, 1); + break; + /* 2.5v */ + case 25: + do_fixup_by_compat(blob, "spansion,s25sl12801", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "spansion,en25q32", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "spansion,sst25wf040", "status", + "disabled", strlen("disabled") + 1, 1); + break; + /* 1.8v */ + case 18: + do_fixup_by_compat(blob, "spansion,s25sl12801", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "spansion,en25q32", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "atmel,at45db081d", "status", + "disabled", strlen("disabled") + 1, 1); + break; + } +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + fdt_fixup_board_spi(blob); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif +} diff --git a/board/freescale/p3060qds/p3060qds.h b/board/freescale/p3060qds/p3060qds.h new file mode 100644 index 0000000..3da6815 --- /dev/null +++ b/board/freescale/p3060qds/p3060qds.h @@ -0,0 +1,30 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __P3060QDS_H__ +#define __P3060QDS_H__ + +#include +#include + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); +extern fixed_ddr_parm_t fixed_ddr_parm_0[]; + +#endif diff --git a/board/freescale/p3060qds/p3060qds_qixis.h b/board/freescale/p3060qds/p3060qds_qixis.h new file mode 100644 index 0000000..4d5d6a2 --- /dev/null +++ b/board/freescale/p3060qds/p3060qds_qixis.h @@ -0,0 +1,74 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __P3060QDS_QIXIS_H__ +#define __P3060QDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for P3060QDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EC_MODE_MASK 0x0F +#define BRDCFG4_EC2_MII_EC1_MII 0x00 +#define BRDCFG4_EC2_MII_EC1_USB 0x03 +#define BRDCFG4_EC2_USB_EC1_MII 0x0C +#define BRDCFG4_EC2_USB_EC1_USB 0x0F +#define BRDCFG4_EC2_USB_EC1_RGMII 0x0E +#define BRDCFG4_EC2_RGMII_EC1_USB 0x0B +#define BRDCFG4_EC2_RGMII_EC1_RGMII 0x0A +#define BRDCFG4_EMISEL_MASK 0xF0 + +#define BRDCFG5_ECLKS_MASK 0x80 +#define BRDCFG5_USB1ID_MASK 0x40 +#define BRDCFG5_USB2ID_MASK 0x20 +#define BRDCFG5_GC2MX_MASK 0x0C +#define BRDCFG5_T15MX_MASK 0x03 +#define BRDCFG5_ECLKS_IEEE1588_CM 0x80 +#define BRDCFG5_USB1ID_CTRL 0x40 +#define BRDCFG5_USB2ID_CTRL 0x20 + +#define BRDCFG6_SD1MX_A 0x01 +#define BRDCFG6_SD1MX_B 0x00 +#define BRDCFG6_SD2MX_A 0x02 +#define BRDCFG6_SD2MX_B 0x00 +#define BRDCFG6_SD3MX_A 0x04 +#define BRDCFG6_SD3MX_B 0x00 +#define BRDCFG6_SD4MX_A 0x08 +#define BRDCFG6_SD4MX_B 0x00 + +#define BRDCFG7_JTAGMX_MASK 0xC0 +#define BRDCFG7_IQ1MX_MASK 0x20 +#define BRDCFG7_G1MX_MASK 0x10 +#define BRDCFG7_D1MX_MASK 0x0C +#define BRDCFG7_I3MX_MASK 0x03 +#define BRDCFG7_JTAGMX_AURORA 0x00 +#define BRDCFG7_JTAGMX_FPGA 0x80 +#define BRDCFG7_JTAGMX_COP_JTAG 0xC0 +#define BRDCFG7_IQ1MX_IRQ_EVT 0x00 +#define BRDCFG7_IQ1MX_USB2 0x20 +#define BRDCFG7_G1MX_USB1 0x00 +#define BRDCFG7_G1MX_TSEC3 0x10 +#define BRDCFG7_D1MX_DMA 0x00 +#define BRDCFG7_D1MX_TSEC3USB 0x04 +#define BRDCFG7_D1MX_HDLC2 0x08 +#define BRDCFG7_I3MX_UART2_I2C34 0x00 +#define BRDCFG7_I3MX_GPIO_EVT 0x01 +#define BRDCFG7_I3MX_USB1 0x02 +#define BRDCFG7_I3MX_TSEC3 0x03 + +#endif diff --git a/boards.cfg b/boards.cfg index c83d861..8608b0e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -726,6 +726,9 @@ P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +P3060QDS powerpc mpc85xx p3060qds freescale +P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 +P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT P4080DS powerpc mpc85xx corenet_ds freescale P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT diff --git a/doc/README.p3060qds b/doc/README.p3060qds new file mode 100644 index 0000000..2ed49ca --- /dev/null +++ b/doc/README.p3060qds @@ -0,0 +1,111 @@ +Overview +========= +The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC. + +The P3060 Processor combines six e500mc Power Architecture processor +cores(1.2GHz) with high-performance datapath acceleration +architecture(DPAA), CoreNet fabric infrastructure, as well as network +and peripheral bus interfaces required for networking, telecom/datacom, +wireless infrastructure, and military/aerospace applications. + + +P3060QDS Board Specifications: +============================== +Memory subsystem: + * 2G Bytes UDIMM DDR3(64bit bus) with ECC on + * 128M Bytes NOR flash single-chip memory + * 16M Bytes SPI flash + * 8K Bytes AT24C64 I2C EEPROM for RCW + +Ethernet(Default SERDES 0x19): + * FM1-dTSEC1: connected to RGMII PHY1 (Vitesse VSC8641 on board,Bottom of dual RJ45) + * FM1-dTSEC2: connected to RGMII PHY2 (Vitesse VSC8641 on board,Top of dual RJ45) + * FM1-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port1 in slot1) + * FM1-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port3 in slot1) + * FM2-dTSEC1: connected to SGMII PHY (Vitesse VSC8234 port0 in slot2) + * FM2-dTSEC2: connected to SGMII PHY (Vitesse VSC8234 port2 in slot2) + * FM2-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port0 in slot1) + * FM2-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port2 in slot1) + +PCIe: + * PCIe1: Lanes A, B, C and D of Bank1 are connected to one x4 PCIe SLOT4 + * PCIe2: Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT3 + +RapidIO: + * sRIO1: Lanes E, F, G and H of Bank1 are connected to sRIO1 (SLOT3) + * sRIO2: Lanes A, B, C and D of Bank1 are connected to sRIO2 (SLOT4) + +USB: + * USB1: connected via an external ULPI PHY SMC3315 to a TYPE-A interface + * USB2: connected via an external ULPI PHY SMC3315 to a TYPE-AB interface + +I2C: + * I2C1_CH0: EEPROM AT24C64(0x50) RCW, AT24C02(0x51) DDR SPD, + AT24C02(0x53) DDR SPD, AT24C02(0x57) SystemID, RTC DS3232(0x68) + * I2C1_CH1: 1588 RiserCard(0x55), HSLB Testport, TempMon + ADT7461(0x4C), SerDesMux DS64MB201(0x51/59/5C/5D) + * I2C1_CH2: VDD/GVDD/GIDD ZL6100 (0x21/0x22/0x23/0x24/0x40) + * I2C1_CH3: OCM CFG AT24C02(0x55), OCM IPL AT24C64(0x56) + * I2C1_CH4: PCIe SLOT1 + * I2C1_CH5: PCIe SLOT2 + * I2C1_CH6: PCIe SLOT3 + * I2C1_CH7: PCIe SLOT4 + * I2C2: NULL + * I2C3: NULL + +UART: + * Supports two UARTs up to 115200 bps for console + + +Boot from NOR flash +=================== +1. Build image + export ARCH=powerpc + export CROSS_COMPILE=/your_path/gcc-4.5.xx-eglibc-2.11.xx/powerpc-linux-gnu/bin/powerpc-linux-gnu- + make P3060QDS_config + make + +2. Program image + => tftp 1000000 u-boot.bin + => protect off all + => erase eff80000 efffffff + => cp.b 1000000 eff80000 80000 + +3. Program RCW + => tftp 1000000 rcw.bin + => protect off all + => erase e8000000 e801ffff + => cp.b 1000000 e8000000 50 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => protect off all + => erase ef000000 ef0fffff + => cp.b 1000000 ef000000 2000 + +5. Change DIP-switch + RCW Location: SW1[1-5] = 01101 (eLBC 16bit NOR flash) + Note: 1 stands for 'on', 0 stands for 'off' + + +Using the Device Tree Source File +================================= +To create the DTB (Device Tree Binary) image file, use a command +similar to this: + dtc -O dtb -b 0 -p 1024 p3060qds.dts > p3060qds.dtb + +Or use the following command: + {linux-2.6}/make p3060qds.dtb ARCH=powerpc + +then the dtb file will be generated under the following directory: + {linux-2.6}/arch/powerpc/boot/p3060qds.dtb + + +Booting Linux +============= +Place a linux uImage in the TFTP disk area. + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp 3000000 p3060rdb.dtb + bootm 1000000 2000000 3000000 + diff --git a/include/configs/P3060QDS.h b/include/configs/P3060QDS.h new file mode 100644 index 0000000..8006547 --- /dev/null +++ b/include/configs/P3060QDS.h @@ -0,0 +1,48 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P3060 QDS board configuration file + */ +#define CONFIG_P3060QDS +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P3060 +#define CONFIG_FSL_QIXIS + +#define CONFIG_NAND_FSL_ELBC + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SPI_FLASH_EON +#define CONFIG_SPI_FLASH_SST + +#include "corenet_ds.h" + +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F + +/* There is a PCA9547 8-channel I2C-bus multiplexer on P3060QDS board */ +#define CONFIG_I2C_MUX +#define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 0622b9f..7925b95 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -168,7 +168,11 @@ #define CONFIG_DDR_SPD #define CONFIG_FSL_DDR3 +#ifdef CONFIG_P3060QDS +#define CONFIG_SYS_SPD_BUS_NUM 0 +#else #define CONFIG_SYS_SPD_BUS_NUM 1 +#endif #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ @@ -641,7 +645,7 @@ #define CONFIG_BAUDRATE 115200 -#if defined(CONFIG_P4080DS) +#if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS) #define __USB_PHY_TYPE ulpi #else #define __USB_PHY_TYPE utmi -- cgit v0.10.2 From 2f3a71f235f442beb9419cee94ef6888b24f8259 Mon Sep 17 00:00:00 2001 From: "Ira W. Snyder" Date: Mon, 21 Nov 2011 13:20:33 -0800 Subject: mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification Newer JEDEC DDR3 SPD Specifications define several additional values for the DDR3 module_type field which were undefined when this code was written. Update the code to handle the newer module types. Signed-off-by: Ira W. Snyder Cc: York Sun Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index ffb503a..d0a5466 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -135,6 +135,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) { case DDR3_SPD_MODULETYPE_RDIMM: case DDR3_SPD_MODULETYPE_MINI_RDIMM: + case DDR3_SPD_MODULETYPE_72B_SO_RDIMM: /* Registered/buffered DIMMs */ pdimm->registered_dimm = 1; for (i = 0; i < 16; i += 2) { @@ -148,6 +149,12 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, case DDR3_SPD_MODULETYPE_SO_DIMM: case DDR3_SPD_MODULETYPE_MICRO_DIMM: case DDR3_SPD_MODULETYPE_MINI_UDIMM: + case DDR3_SPD_MODULETYPE_MINI_CDIMM: + case DDR3_SPD_MODULETYPE_72B_SO_UDIMM: + case DDR3_SPD_MODULETYPE_72B_SO_CDIMM: + case DDR3_SPD_MODULETYPE_LRDIMM: + case DDR3_SPD_MODULETYPE_16B_SO_DIMM: + case DDR3_SPD_MODULETYPE_32B_SO_DIMM: /* Unbuffered DIMMs */ if (spd->mod_section.unbuffered.addr_mapping & 0x1) pdimm->mirrored_dimm = 1; diff --git a/include/ddr_spd.h b/include/ddr_spd.h index 40a0463..a9230b9 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -325,5 +325,12 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); #define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04) #define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05) #define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06) +#define DDR3_SPD_MODULETYPE_MINI_CDIMM (0x07) +#define DDR3_SPD_MODULETYPE_72B_SO_UDIMM (0x08) +#define DDR3_SPD_MODULETYPE_72B_SO_RDIMM (0x09) +#define DDR3_SPD_MODULETYPE_72B_SO_CDIMM (0x0A) +#define DDR3_SPD_MODULETYPE_LRDIMM (0x0B) +#define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C) +#define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D) #endif /* _DDR_SPD_H_ */ -- cgit v0.10.2 From cc15df57b1ce2fb7b9aac7567b25e7b3bef28458 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Wed, 16 Nov 2011 13:28:34 -0600 Subject: powerpc/85xx: verify the localbus device tree address before booting the OS The localbus controller node in the device tree is typically a root node, even though the controller is part of CCSR. If we were to put the lbc node under the SOC node, then the 'ranges' property in the lbc node would translate through the 'ranges' property of the parent SOC node, and we don't want that. Since the lbc is a separate node, it's possible for the 'reg' property to be wrong. This happened with the original version of p1022ds.dts, which used a 32-bit value in the 'reg' address, instead of a 36-bit address. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 62c7ea1..977770e 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -688,6 +688,12 @@ void ft_cpu_setup(void *blob, bd_t *bd) #define CCSR_VIRT_TO_PHYS(x) \ (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) +static void msg(const char *name, uint64_t uaddr, uint64_t daddr) +{ + printf("Warning: U-Boot configured %s at address %llx,\n" + "but the device tree has it at %llx\n", name, uaddr, daddr); +} + /* * Verify the device tree * @@ -703,33 +709,32 @@ void ft_cpu_setup(void *blob, bd_t *bd) */ int ft_verify_fdt(void *fdt) { - uint64_t ccsr = 0; + uint64_t addr = 0; int aliases; int off; /* First check the CCSR base address */ off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4); if (off > 0) - ccsr = fdt_get_base_address(fdt, off); + addr = fdt_get_base_address(fdt, off); - if (!ccsr) { + if (!addr) { printf("Warning: could not determine base CCSR address in " "device tree\n"); /* No point in checking anything else */ return 0; } - if (ccsr != CONFIG_SYS_CCSRBAR_PHYS) { - printf("Warning: U-Boot configured CCSR at address %llx,\n" - "but the device tree has it at %llx\n", - (uint64_t) CONFIG_SYS_CCSRBAR_PHYS, ccsr); + if (addr != CONFIG_SYS_CCSRBAR_PHYS) { + msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr); /* No point in checking anything else */ return 0; } /* - * Get the 'aliases' node. If there isn't one, then there's nothing - * left to do. + * Check some nodes via aliases. We assume that U-Boot and the device + * tree enumerate the devices equally. E.g. the first serial port in + * U-Boot is the same as "serial0" in the device tree. */ aliases = fdt_path_offset(fdt, "/aliases"); if (aliases > 0) { @@ -746,5 +751,30 @@ int ft_verify_fdt(void *fdt) #endif } + /* + * The localbus node is typically a root node, even though the lbc + * controller is part of CCSR. If we were to put the lbc node under + * the SOC node, then the 'ranges' property in the lbc node would + * translate through the 'ranges' property of the parent SOC node, and + * we don't want that. Since it's a separate node, it's possible for + * the 'reg' property to be wrong, so check it here. For now, we + * only check for "fsl,elbc" nodes. + */ +#ifdef CONFIG_SYS_LBC_ADDR + off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc"); + if (off > 0) { + const u32 *reg = fdt_getprop(fdt, off, "reg", NULL); + if (reg) { + uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR); + + addr = fdt_translate_address(fdt, off, reg); + if (uaddr != addr) { + msg("the localbus", uaddr, addr); + return 0; + } + } + } +#endif + return 1; } -- cgit v0.10.2 From c18de0d7ae230393bed520cd8656660e1f29c252 Mon Sep 17 00:00:00 2001 From: "Ira W. Snyder" Date: Mon, 21 Nov 2011 13:20:32 -0800 Subject: mpc85xx: support board-specific reset function This is useful for boards which cannot be reset in the usual way for the 85xx CPU. An example is a board which can only be reset by a hardware watchdog. Signed-off-by: Ira W. Snyder Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 49c0551..c1815e8 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -42,6 +42,16 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * Default board reset function + */ +static void +__board_reset(void) +{ + /* Do nothing */ +} +void board_reset(void) __attribute__((weak, alias("__board_reset"))); + int checkcpu (void) { sys_info_t sysinfo; @@ -215,7 +225,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) mtspr(DBCR0,val); #else volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ + + /* Attempt board-specific reset */ + board_reset(); + + /* Next try asserting HRESET_REQ */ + out_be32(&gur->rstcr, 0x2); udelay(100); #endif -- cgit v0.10.2 From 411e150375de1ab15029bc82fa9af8a4bfb51383 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 23 Nov 2011 10:02:41 -0600 Subject: arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warning Fix: interactive.c: In function 'fsl_ddr_interactive': interactive.c:1357:15: warning: variable 'len' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c index d7d66ef..5b72437 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c @@ -1354,7 +1354,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo) { unsigned long long ddrsize; const char *prompt = "FSL DDR>"; - unsigned int len; char buffer[CONFIG_SYS_CBSIZE]; char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ int argc; @@ -1389,7 +1388,7 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo) * No need to worry for buffer overflow here in * this function; readline() maxes out at CFG_CBSIZE */ - len = readline_into_buffer(prompt, buffer); + readline_into_buffer(prompt, buffer); argc = parse_line(buffer, argv); if (argc == 0) continue; -- cgit v0.10.2 From 9839709ea3df89f6021034508f48b97cab33ebb8 Mon Sep 17 00:00:00 2001 From: "Ira W. Snyder" Date: Wed, 23 Nov 2011 08:25:58 -0800 Subject: mpc85xx: support for Freescale COM Express P2020 This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder Signed-off-by: Kumar Gala diff --git a/MAINTAINERS b/MAINTAINERS index c68842e..0456658 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -450,6 +450,10 @@ Jon Smirl pcm030 MPC5200 +Ira W. Snyder + + P2020COME P2020 + Timur Tabi MPC8349E-mITX MPC8349 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 99fe97d..9b08cb8 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2420,6 +2420,7 @@ struct ccsr_rman { #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 +#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000 #ifdef CONFIG_TSECV2 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 #else diff --git a/board/freescale/p2020come/Makefile b/board/freescale/p2020come/Makefile new file mode 100644 index 0000000..ba87904 --- /dev/null +++ b/board/freescale/p2020come/Makefile @@ -0,0 +1,46 @@ +# +# Copyright 2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c new file mode 100644 index 0000000..85f84c6 --- /dev/null +++ b/board/freescale/p2020come/ddr.c @@ -0,0 +1,45 @@ +/* + * Copyright 2009, 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + + if (!pdimm->n_ranks) + return; + + /* + * Set DDR_SDRAM_CLK_CNTL = 0x02800000 + * + * Clock is launched 5/8 applied cycle after address/command + */ + popts->clk_adjust = 5; +} diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c new file mode 100644 index 0000000..20ba36f --- /dev/null +++ b/board/freescale/p2020come/law.c @@ -0,0 +1,39 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Create a dummy LAW entry for the DDR SDRAM which will be replaced when + * the DDR SPD setup code runs. + * + * This table would be empty, except that it is used before the BSS section is + * initialized, and therefore must have at least one entry to push it into + * the DATA section. + */ +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_SDRAM_BASE, LAW_SIZE_4K, LAW_TRGT_IF_DDR), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c new file mode 100644 index 0000000..8cf7bee --- /dev/null +++ b/board/freescale/p2020come/p2020come.c @@ -0,0 +1,287 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_PCI) +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_PCI) +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void ft_pci_board_setup(void *blob) +{ + FT_FSL_PCI_SETUP; +} +#endif + +#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \ + SGMII_PHY_RST_SET | PCIE_RST_SET | \ + RGMII_PHY_RST_SET) + +#define SYSCLK_MASK 0x00200000 +#define BOARDREV_MASK 0x10100000 +#define BOARDREV_B 0x10100000 +#define BOARDREV_C 0x00100000 +#define BOARDREV_D 0x00000000 + +#define SYSCLK_66 66666666 +#define SYSCLK_50 50000000 +#define SYSCLK_100 100000000 + +unsigned long get_board_sys_clk(ulong dummy) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; + + ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; + switch (ddr_ratio) { + case 0x0C: + return SYSCLK_66; + case 0x0A: + case 0x08: + return SYSCLK_100; + default: + puts("ERROR: unknown DDR ratio\n"); + return SYSCLK_100; + } +} + +unsigned long get_board_ddr_clk(ulong dummy) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; + + ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; + switch (ddr_ratio) { + case 0x0C: + case 0x0A: + return SYSCLK_66; + case 0x08: + return SYSCLK_100; + default: + puts("ERROR: unknown DDR ratio\n"); + return SYSCLK_100; + } +} + +#ifdef CONFIG_MMC +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->pmuxcr, + (MPC85xx_PMUXCR_SDHC_CD | + MPC85xx_PMUXCR_SDHC_WP)); + + /* All the device are enable except for SRIO12 */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO); + return 0; +} +#endif + +#define GPIO_DIR 0x0f3a0000 +#define GPIO_ODR 0x00000000 +#define GPIO_DAT 0x001a0000 + +int checkboard(void) +{ + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00); + + /* + * GPIO + * 0 - 3: CarryBoard Input; + * 4 - 7: CarryBoard Output; + * 8 : Mux as SDHC_CD (card detection) + * 9 : Mux as SDHC_WP + * 10 : Clear Watchdog timer + * 11 : LED Input + * 12 : Output to 1 + * 13 : Open Drain + * 14 : LED Output + * 15 : Switch Input + * + * Set GPIOs 11, 12, 14 to 1. + */ + out_be32(&pgpio->gpodr, GPIO_ODR); + mpc85xx_gpio_set(0xffffffff, GPIO_DIR, GPIO_DAT); + + puts("Board: Freescale COM Express P2020\n"); + return 0; +} + +#define M41ST85W_I2C_BUS 1 +#define M41ST85W_I2C_ADDR 0x68 +#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args) + +static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name) +{ + u8 data; + + if (i2c_read(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) { + M41ST85W_ERROR("unable to read %s bit\n", name); + return; + } + + if (data & mask) { + data &= ~mask; + if (i2c_write(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) { + M41ST85W_ERROR("unable to clear %s bit\n", name); + return; + } + } +} + +#define M41ST85W_REG_SEC2 0x01 +#define M41ST85W_REG_SEC2_ST 0x80 + +#define M41ST85W_REG_ALHOUR 0x0c +#define M41ST85W_REG_ALHOUR_HT 0x40 + +/* + * The P2020COME board has a STMicro M41ST85W RTC/watchdog + * at i2c bus 1 address 0x68. + */ +static void start_rtc(void) +{ + unsigned int bus = i2c_get_bus_num(); + + if (i2c_set_bus_num(M41ST85W_I2C_BUS)) { + M41ST85W_ERROR("unable to set i2c bus\n"); + goto out; + } + + /* ensure ST (stop) and HT (halt update) bits are cleared */ + m41st85w_clear_bit(M41ST85W_REG_SEC2, M41ST85W_REG_SEC2_ST, "ST"); + m41st85w_clear_bit(M41ST85W_REG_ALHOUR, M41ST85W_REG_ALHOUR_HT, "HT"); + +out: + /* reset the i2c bus */ + i2c_set_bus_num(bus); +} + +int board_early_init_r(void) +{ + start_rtc(); + return 0; +} + +#define M41ST85W_REG_WATCHDOG 0x09 +#define M41ST85W_REG_WATCHDOG_WDS 0x80 +#define M41ST85W_REG_WATCHDOG_BMB0 0x04 + +void board_reset(void) +{ + u8 data = M41ST85W_REG_WATCHDOG_WDS | M41ST85W_REG_WATCHDOG_BMB0; + + /* set the hardware watchdog timeout to 1/16 second, then hang */ + i2c_set_bus_num(M41ST85W_I2C_BUS); + i2c_write(M41ST85W_I2C_ADDR, M41ST85W_REG_WATCHDOG, 1, &data, 1); + + while (1) + /* hang */; +} + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + if (is_serdes_configured(SGMII_TSEC3)) { + puts("eTSEC3 is in sgmii mode."); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + +#if defined(CONFIG_PCI) + ft_pci_board_setup(blob); +#endif + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_dr_usb(blob, bd); +} +#endif diff --git a/board/freescale/p2020come/tlb.c b/board/freescale/p2020come/tlb.c new file mode 100644 index 0000000..d787ac3 --- /dev/null +++ b/board/freescale/p2020come/tlb.c @@ -0,0 +1,99 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#if defined(CONFIG_PCI) + /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI1 0xD000,0000 - 0xDFFF,FFFF, size = 256M */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * *I*G* - PCI I/O + * + * PCI3 => 0xFFC10000 + * PCI2 => 0xFFC2,0000 + * PCI1 => 0xFFC3,0000 + */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256K, 1), +#endif /* #if defined(CONFIG_PCI) */ + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - DDR3 2G Part 1: 0 - 0x3fff,ffff , size = 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* DDR3 2G Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 8608b0e..84cf6b2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -717,6 +717,8 @@ P2020RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freesca P2020RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,NAND P2020RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD P2020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH +P2020COME_SDCARD powerpc mpc85xx p2020come freescale - P2020COME:SDCARD +P2020COME_SPIFLASH powerpc mpc85xx p2020come freescale - P2020COME:SPIFLASH P2041RDB powerpc mpc85xx p2041rdb freescale P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P2041RDB_SECURE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SECURE_BOOT diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h new file mode 100644 index 0000000..db88b68 --- /dev/null +++ b/include/configs/P2020COME.h @@ -0,0 +1,576 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* The P2020COME board is only booted via the Freescale On-Chip ROM */ +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC + +#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc + +#ifdef CONFIG_SDCARD +#define CONFIG_RAMBOOT_SDCARD 1 +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH 1 +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/ +#define CONFIG_P2020 1 +#define CONFIG_P2020COME 1 +#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ +#define CONFIG_MP + +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#if defined(CONFIG_PCI) +#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ +#define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */ + +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#endif /* #if defined(CONFIG_PCI) */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_PCI) +#define CONFIG_E1000 1 /* E1000 pci Ethernet card */ +#endif + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_ddr_clk(unsigned long dummy); +extern unsigned long get_board_sys_clk(unsigned long dummy); +#endif + +/* + * For P2020COME DDRCLK and SYSCLK are from the same oscillator + * For DA phase the SYSCLK is 66MHz + * For EA phase the SYSCLK is 100MHz + */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) + +#define CONFIG_HWCONFIG + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch prediction */ + +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x1fffffff +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + + + + + + + + /* + * Config the L2 Cache as L2 SRAM + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull +#else +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#endif +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR \ + + CONFIG_SYS_L2_SIZE) + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#define CONFIG_FSL_DDR3 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD + +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +#define CONFIG_SYS_SDRAM_SIZE 2048ULL /* DDR size on P2020COME */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d +#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 +#define CONFIG_SYS_DDR_SBE 0x00ff0000 + +#define CONFIG_SYS_SPD_BUS_NUM 1 +#define SPD_EEPROM_ADDRESS 0x53 + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR3 2G Cacheable + * 0x8000_0000 0x9fff_ffff PCI Express 3 Mem 1G non-cacheable + * 0xa000_0000 0xbfff_ffff PCI Express 2 Mem 1G non-cacheable + * 0xc000_0000 0xdfff_ffff PCI Express 1 Mem 1G non-cacheable + * 0xffc1_0000 0xffc1_ffff PCI Express 3 IO 64K non-cacheable + * 0xffc2_0000 0xffc2_ffff PCI Express 2 IO 64K non-cacheable + * 0xffc3_0000 0xffc3_ffff PCI Express 1 IO 64K non-cacheable + * + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ + +/* There is no NOR Flash on P2020COME */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_HWCONFIG + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* the assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * I2C2 EEPROM + */ +#define CONFIG_ID_EEPROM +#ifdef CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#endif +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR2 0x18 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#if defined(CONFIG_PCI) + +/* controller 3, Slot 3, tgtid 3, Base address 8000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc10000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP +#undef CONFIG_RTL8139 + +#ifdef CONFIG_RTL8139 +/* This macro is used by RTL8139 but not defined in PPC architecture */ +#define KSEG1ADDR(x) (x) +#define _IO_BASE 0x00000000 +#endif + + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 2 +#define TSEC3_PHY_ADDR 1 + +#undef CONFIG_VSC7385_ENET + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#if defined(CONFIG_RAMBOOT_SDCARD) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_RAMBOOT_SPIFLASH) + #define CONFIG_ENV_IS_IN_SPI_FLASH + #define CONFIG_ENV_SPI_BUS 0 + #define CONFIG_ENV_SPI_CS 0 + #define CONFIG_ENV_SPI_MAX_HZ 10000000 + #define CONFIG_ENV_SPI_MODE 0 + #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ + #define CONFIG_ENV_SECT_SIZE 0x10000 + #define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_MMC 1 + +#ifdef CONFIG_MMC +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#endif /* CONFIG_MMC */ + +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#define CONFIG_HAS_FSL_DR_USB +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Misc Extra Settings */ +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 +#define CONFIG_CMD_DHCP 1 + +#define CONFIG_CMD_DATE 1 +#define CONFIG_RTC_M41T62 1 +#define CONFIG_SYS_RTC_BUS_NUM 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#endif + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ecc=on\0" \ + "bootcmd=run sdboot\0" \ + "sdboot=setenv bootargs root=/dev/mmcblk0p2 rw " \ + "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ + "$othbootargs; mmcinfo; " \ + "ext2load mmc 0:2 $loadaddr /boot/$bootfile; " \ + "ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; " \ + "bootm $loadaddr - $fdtaddr\0" \ + "sdfatboot=setenv bootargs root=/dev/ram rw " \ + "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ + "$othbootargs; mmcinfo; " \ + "fatload mmc 0:1 $loadaddr $bootfile; " \ + "fatload mmc 0:1 $fdtaddr $fdtfile; " \ + "fatload mmc 0:1 $ramdiskaddr $ramdiskfile; " \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + "usbboot=setenv bootargs root=/dev/sda1 rw " \ + "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ + "$othbootargs; " \ + "usb start; " \ + "ext2load usb 0:1 $loadaddr /boot/$bootfile; " \ + "ext2load usb 0:1 $fdtaddr /boot/$fdtfile; " \ + "bootm $loadaddr - $fdtaddr\0" \ + "usbfatboot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start; " \ + "fatload usb 0:2 $loadaddr $bootfile; " \ + "fatload usb 0:2 $fdtaddr $fdtfile; " \ + "fatload usb 0:2 $ramdiskaddr $ramdiskfile; " \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + "usbext2boot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start; " \ + "ext2load usb 0:4 $loadaddr $bootfile; " \ + "ext2load usb 0:4 $fdtaddr $fdtfile; " \ + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile; " \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + "upgradespi=sf probe 0; " \ + "setenv startaddr 0; " \ + "setenv erasesize a0000; " \ + "tftp 1000000 $tftppath/$uboot_spi; " \ + "sf erase $startaddr $erasesize; " \ + "sf write 1000000 $startaddr $filesize; " \ + "sf erase 100000 120000\0" \ + "clearspienv=sf probe 0;sf erase 100000 20000\0" \ + "othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0" \ + "netdev=eth0\0" \ + "rootdelaysecond=15\0" \ + "uboot_nor=u-boot-nor.bin\0" \ + "uboot_spi=u-boot-p2020.spi\0" \ + "uboot_sd=u-boot-p2020.bin\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs-dev.ext2.img\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=uImage-2.6.32-p2020.dtb\0" \ + "tftppath=p2020\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "usb start;" \ + "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ + "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $tftppath/$bootfile;" \ + "tftp $fdtaddr $tftppath/$fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $tftppath/$ramdiskfile;" \ + "tftp $loadaddr $tftppath/$bootfile;" \ + "tftp $fdtaddr $tftppath/$fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From 2fe6b7f70f423b66e23ad6fb0848b71252b2b2cd Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Thu, 13 Oct 2011 15:12:22 +0200 Subject: ppc4xx: use CONFIG_PCI_BOOTDELAY instead of private implementation This patch switches PMC440 board code to the CONFIG_PCI_BOOTDELAY option instead of using a private implemention. This relies on Anatolji's patch that moves the pcidelay handling behind pci_target_init. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 5236f44..0d56064 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -617,21 +617,6 @@ void pci_master_init(struct pci_controller *hose) static void wait_for_pci_ready(void) { - int i; - char *s = getenv("pcidelay"); - /* - * We have our own handling of the pcidelay variable. - * Using CONFIG_PCI_BOOTDELAY enables pausing for host - * and adapter devices. For adapter devices we do not - * want this. - */ - if (s) { - int ms = simple_strtoul(s, NULL, 10); - printf("PCI: Waiting for %d ms\n", ms); - for (i=0; i Date: Thu, 13 Oct 2011 15:12:23 +0200 Subject: ppc4xx: remove invalid access to PCI_BRDGOPT2 register This patch removes an invalid call to pci_write_config_dword to PCI_BRDGOPT2 register. This function must not be used from pci_target_init and is also at the wrong place. The correct call is done later in pci_target_init via pci_hose_write_config_dword. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 0d56064..3713e37 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -574,8 +574,6 @@ void pci_target_init(struct pci_controller *hose) /* No error reporting */ pci_hose_write_config_word(hose, 0, PCI_ERREN, 0); - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - if (!is_monarch()) { /* Program the board's subsystem id/classcode */ pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, -- cgit v0.10.2 From a6569c63b368efeff262e11586319b8c8515ca00 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Thu, 24 Nov 2011 16:36:06 +0100 Subject: ppc4xx: fix PMC440 painit command This patch fixes the PMC440 BSP command painit. The implementation was broken since the step to the new environment handling. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index 0202876..f1ffb7b 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -342,7 +342,8 @@ U_BOOT_CMD( #if defined(CONFIG_PRAM) #include -extern env_t *env_ptr; +#include +#include int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -351,6 +352,10 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) u32 param; ulong *lptr; + env_t *envp; + char *res; + int len; + v = getenv("pram"); if (v) pram = simple_strtoul(v, NULL, 10); @@ -384,7 +389,15 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* env is first (4k aligned) */ nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1)); - memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE); + envp = (env_t *)nextbase; + res = (char *)envp->data; + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + return 1; + } + envp->crc = crc32(0, envp->data, ENV_SIZE); + *(--lptr) = CONFIG_ENV_SIZE; /* size */ *(--lptr) = base - nextbase; /* offset | type=0 */ -- cgit v0.10.2 From 255ef4d9091fe896ff152629a8cb290ee92c9fde Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Thu, 20 Oct 2011 11:12:55 +0200 Subject: ppc4xx: Add Io64 board support Board support for the Guntermann & Drunck Io64. Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese diff --git a/MAINTAINERS b/MAINTAINERS index c68842e..7c21981 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -150,6 +150,7 @@ Dirk Eibach gdppc440etx PPC440EP/GR intip PPC460EX io PPC405EP + io64 PPC405EX iocon PPC405EP neo PPC405EP diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c new file mode 100644 index 0000000..0d25214 --- /dev/null +++ b/board/gdsys/405ex/405ex.c @@ -0,0 +1,250 @@ +#include +#include +#include +#include +#include + +#include + +#include "405ex.h" + +#define REFLECTION_TESTPATTERN 0xdede +#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) + +DECLARE_GLOBAL_DATA_PTR; + +int get_fpga_state(unsigned dev) +{ + return gd->fpga_state[dev]; +} + +void print_fpga_state(unsigned dev) +{ + if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED) + puts(" Waiting for FPGA-DONE timed out.\n"); + if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) + puts(" FPGA reflection test failed.\n"); +} + +int board_early_init_f(void) +{ + u32 val; + + /*--------------------------------------------------------------------+ + | Interrupt controller setup + +--------------------------------------------------------------------+ + +---------------------------------------------------------------------+ + |Interrupt| Source | Pol. | Sensi.| Crit. | + +---------+-----------------------------------+-------+-------+-------+ + | IRQ 00 | UART0 | High | Level | Non | + | IRQ 01 | UART1 | High | Level | Non | + | IRQ 02 | IIC0 | High | Level | Non | + | IRQ 03 | TBD | High | Level | Non | + | IRQ 04 | TBD | High | Level | Non | + | IRQ 05 | EBM | High | Level | Non | + | IRQ 06 | BGI | High | Level | Non | + | IRQ 07 | IIC1 | Rising| Edge | Non | + | IRQ 08 | SPI | High | Lvl/ed| Non | + | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | + | IRQ 10 | MAL TX EOB | High | Level | Non | + | IRQ 11 | MAL RX EOB | High | Level | Non | + | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | + | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | + | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | + | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | + | IRQ 16 | PCIE0 AL | high | Level | Non | + | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | + | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | + | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | + | IRQ 20 | PCIE0 TCR | High | Level | Non | + | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | + | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | + | IRQ 23 | Security EIP-94 | High | Level | Non | + | IRQ 24 | EMAC0 interrupt | High | Level | Non | + | IRQ 25 | EMAC1 interrupt | High | Level | Non | + | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | + | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | + | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | + | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | + | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | + | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | + |---------------------------------------------------------------------- + | IRQ 32 | MAL Serr | High | Level | Non | + | IRQ 33 | MAL Txde | High | Level | Non | + | IRQ 34 | MAL Rxde | High | Level | Non | + | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | + | IRQ 36 | PCIE0 DCR Error | High | Level | Non | + | IRQ 37 | EBC | High |Lvl Edg| Non | + | IRQ 38 | NDFC | High | Level | Non | + | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | + | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | + | IRQ 41 | PCIE1 AL | high | Level | Non | + | IRQ 42 | PCIE1 VPD access | rising| edge | Non | + | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | + | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | + | IRQ 45 | PCIE1 TCR | High | Level | Non | + | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | + | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | + | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | + | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | + | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | + | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | + | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | + | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | + | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | + | IRQ 55 | Serial ROM | High | Level | Non | + | IRQ 56 | GPT Decrement Pulse | High | Level | Non | + | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | + | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | + | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | + | IRQ 60 | EMAC0 Wake-up | High | Level | Non | + | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | + | IRQ 62 | EMAC1 Wake-up | High | Level | Non | + |---------------------------------------------------------------------- + | IRQ 64 | PE0 AL | High | Level | Non | + | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | + | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | + | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | + | IRQ 68 | PE0 TCR | High | Level | Non | + | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | + | IRQ 70 | PE0 DCR Error | High | Level | Non | + | IRQ 71 | Reserved | N/A | N/A | Non | + | IRQ 72 | PE1 AL | High | Level | Non | + | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | + | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | + | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | + | IRQ 76 | PE1 TCR | High | Level | Non | + | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | + | IRQ 78 | PE1 DCR Error | High | Level | Non | + | IRQ 79 | Reserved | N/A | N/A | Non | + | IRQ 80 | PE2 AL | High | Level | Non | + | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | + | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | + | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | + | IRQ 84 | PE2 TCR | High | Level | Non | + | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | + | IRQ 86 | PE2 DCR Error | High | Level | Non | + | IRQ 87 | Reserved | N/A | N/A | Non | + | IRQ 88 | External IRQ(5) | Progr | Progr | Non | + | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | + | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | + | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | + | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | + | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | + | IRQ 94 | Reserved | N/A | N/A | Non | + | IRQ 95 | Reserved | N/A | N/A | Non | + |--------------------------------------------------------------------- + +---------+-----------------------------------+-------+-------+------*/ + /*--------------------------------------------------------------------+ + | Initialise UIC registers. Clear all interrupts. Disable all + | interrupts. + | Set critical interrupt values. Set interrupt polarities. Set + | interrupt trigger levels. Make bit 0 High priority. Clear all + | interrupts again. + +-------------------------------------------------------------------*/ + + mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ + mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ + mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ + + mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ + mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ + mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */ + mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */ + + mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */ + /* Except cascade UIC0 and UIC1 */ + mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ + mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ + mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */ + mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */ + + /* + * Note: Some cores are still in reset when the chip starts, so + * take them out of reset + */ + mtsdr(SDR0_SRST, 0); + + /* + * Configure PFC (Pin Function Control) registers + */ + val = SDR0_PFC1_GPT_FREQ; + mtsdr(SDR0_PFC1, val); + + return 0; +} + +int board_early_init_r(void) +{ + unsigned k; + unsigned ctr; + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->fpga_state[k] = 0; + + /* + * reset FPGA + */ + gd405ex_init(); + + gd405ex_set_fpga_reset(1); + + gd405ex_setup_hw(); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + ctr = 0; + while (!gd405ex_get_fpga_done(k)) { + udelay(100000); + if (ctr++ > 5) { + gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED; + break; + } + } + } + + udelay(10); + + gd405ex_set_fpga_reset(0); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k); +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI + u16 *reflection_target = &fpga->reflection_low; +#else + u16 *reflection_target = &fpga->reflection_high; +#endif + /* + * wait for fpga out of reset + */ + ctr = 0; + while (1) { + out_le16(&fpga->reflection_low, + REFLECTION_TESTPATTERN); + + if (in_le16(reflection_target) == + REFLECTION_TESTPATTERN_INV) + break; + + udelay(100000); + if (ctr++ > 5) { + gd->fpga_state[k] |= + FPGA_STATE_REFLECTION_FAILED; + break; + } + } + } + + return 0; +} diff --git a/board/gdsys/405ex/405ex.h b/board/gdsys/405ex/405ex.h new file mode 100644 index 0000000..b15623f --- /dev/null +++ b/board/gdsys/405ex/405ex.h @@ -0,0 +1,10 @@ +#ifndef __405EX_H_ +#define __405EX_H_ + +/* functions to be provided by board implementation */ +void gd405ex_init(void); +void gd405ex_set_fpga_reset(unsigned state); +void gd405ex_setup_hw(void); +int gd405ex_get_fpga_done(unsigned fpga); + +#endif /* __405EX_H_ */ diff --git a/board/gdsys/405ex/Makefile b/board/gdsys/405ex/Makefile new file mode 100644 index 0000000..4549705 --- /dev/null +++ b/board/gdsys/405ex/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-$(CONFIG_IO64) += io64.o + +COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o + +COBJS := $(BOARD).o $(COBJS-y) + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/gdsys/405ex/chip_config.c b/board/gdsys/405ex/chip_config.c new file mode 100644 index 0000000..12cb3bf --- /dev/null +++ b/board/gdsys/405ex/chip_config.c @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include + +/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */ + +struct ppc4xx_config ppc4xx_config_val[] = { + { + "333-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83", + { + 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66", + { + 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "400-200-66-nor", "NOR CPU: 400 PLB: 200 OPB: 66 EBC: 66", + { + 0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100", + { + 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", + { + 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", + { + 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00, + 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 + } + }, + { + "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", + { + 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", + { + 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00, + 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 + } + }, + { + "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111", + { + 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, +}; + +int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c new file mode 100644 index 0000000..a997571 --- /dev/null +++ b/board/gdsys/405ex/io64.c @@ -0,0 +1,384 @@ +/* + * (C) Copyright 2010 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * based on kilauea.c + * by Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "405ex.h" +#include + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define PHYREG_CONTROL 0 +#define PHYREG_PAGE_ADDRESS 22 +#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16 +#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26 +#define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17 +#define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21 + +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) +#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) + +enum { + UNITTYPE_CCD_SWITCH = 1, +}; + +enum { + HWVER_100 = 0, + HWVER_110 = 1, +}; + +static inline void blank_string(int size) +{ + int i; + + for (i = 0; i < size; i++) + putc('\b'); + for (i = 0; i < size; i++) + putc(' '); + for (i = 0; i < size; i++) + putc('\b'); +} + +/* + * Board early initialization function + */ +int misc_init_r(void) +{ + /* startup fans */ + dtt_init(); + +#ifdef CONFIG_ENV_IS_IN_FLASH + /* Monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + -CONFIG_SYS_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); +#endif + + return 0; +} + +static void print_fpga_info(unsigned dev) +{ + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev); + u16 versions = in_le16(&fpga->versions); + u16 fpga_version = in_le16(&fpga->fpga_version); + u16 fpga_features = in_le16(&fpga->fpga_features); + int fpga_state = get_fpga_state(dev); + + unsigned unit_type; + unsigned hardware_version; + unsigned feature_channels; + unsigned feature_expansion; + + printf("FPGA%d: ", dev); + if (fpga_state & FPGA_STATE_PLATFORM) + printf("(legacy) "); + + if (fpga_state & FPGA_STATE_DONE_FAILED) { + printf(" done timed out\n"); + return; + } + + if (fpga_state & FPGA_STATE_REFLECTION_FAILED) { + printf(" refelectione test failed\n"); + return; + } + + unit_type = (versions & 0xf000) >> 12; + hardware_version = versions & 0x000f; + feature_channels = fpga_features & 0x007f; + feature_expansion = fpga_features & (1<<15); + + switch (unit_type) { + case UNITTYPE_CCD_SWITCH: + printf("CCD-Switch"); + break; + + default: + printf("UnitType %d(not supported)", unit_type); + break; + } + + switch (hardware_version) { + case HWVER_100: + printf(" HW-Ver 1.00\n"); + break; + + case HWVER_110: + printf(" HW-Ver 1.10\n"); + break; + + default: + printf(" HW-Ver %d(not supported)\n", + hardware_version); + break; + } + + printf(" FPGA V %d.%02d, features:", + fpga_version / 100, fpga_version % 100); + + printf(" %d channel(s)", feature_channels); + + printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: CATCenter Io64\n"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + + return 0; +} + +int configure_gbit_phy(char *bus, unsigned char addr) +{ + unsigned short value; + + /* select page 0 */ + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000)) + goto err_out; + /* switch to powerdown */ + if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, + &value)) + goto err_out; + if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, + value | 0x0004)) + goto err_out; + /* select page 2 */ + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002)) + goto err_out; + /* disable SGMII autonegotiation */ + if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48)) + goto err_out; + /* select page 0 */ + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000)) + goto err_out; + /* switch from powerdown to normal operation */ + if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, + &value)) + goto err_out; + if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, + value & ~0x0004)) + goto err_out; + /* reset phy so settings take effect */ + if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140)) + goto err_out; + + return 0; + +err_out: + printf("Error writing to the PHY addr=%02x\n", addr); + return -1; +} + +int verify_gbit_phy(char *bus, unsigned char addr) +{ + unsigned short value; + + /* select page 2 */ + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002)) + goto err_out; + /* verify SGMII link status */ + if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value)) + goto err_out; + if (!(value & (1 << 10))) + return -2; + + return 0; + +err_out: + printf("Error writing to the PHY addr=%02x\n", addr); + return -1; +} + +int last_stage_init(void) +{ + unsigned int k; + unsigned int fpga; + ihs_fpga_t *fpga0 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); + ihs_fpga_t *fpga1 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(1); + int failed = 0; + char str_phys[] = "Setup PHYs -"; + char str_serdes[] = "Start SERDES blocks"; + char str_channels[] = "Start FPGA channels"; + char str_locks[] = "Verify SERDES locks"; + char str_status[] = "Verify PHY status -"; + char slash[] = "\\|/-\\|/-"; + + print_fpga_info(0); + print_fpga_info(1); + + /* setup Gbit PHYs */ + puts("TRANS: "); + puts(str_phys); + miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, + bb_miiphy_read, bb_miiphy_write); + + for (k = 0; k < 32; ++k) { + configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k); + putc('\b'); + putc(slash[k % 8]); + } + + miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME, + bb_miiphy_read, bb_miiphy_write); + + for (k = 0; k < 32; ++k) { + configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k); + putc('\b'); + putc(slash[k % 8]); + } + blank_string(strlen(str_phys)); + + /* take fpga serdes blocks out of reset */ + puts(str_serdes); + udelay(500000); + out_le16(&fpga0->quad_serdes_reset, 0); + out_le16(&fpga1->quad_serdes_reset, 0); + blank_string(strlen(str_serdes)); + + /* take channels out of reset */ + puts(str_channels); + udelay(500000); + for (fpga = 0; fpga < 2; ++fpga) { + u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int; + for (k = 0; k < 32; ++k) + out_le16(ch0_config_int + 4 * k, 0); + } + blank_string(strlen(str_channels)); + + /* verify channels serdes lock */ + puts(str_locks); + udelay(500000); + for (fpga = 0; fpga < 2; ++fpga) { + u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int; + for (k = 0; k < 32; ++k) { + u16 status = in_le16(ch0_status_int + 4*k); + if (!(status & (1 << 4))) { + failed = 1; + printf("fpga %d channel %d: no serdes lock\n", + fpga, k); + } + /* reset events */ + out_le16(ch0_status_int + 4*k, status); + } + } + blank_string(strlen(str_locks)); + + /* verify phy status */ + puts(str_status); + for (k = 0; k < 32; ++k) { + if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) { + printf("verify baseboard phy %d failed\n", k); + failed = 1; + } + putc('\b'); + putc(slash[k % 8]); + } + for (k = 0; k < 32; ++k) { + if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) { + printf("verify extensionboard phy %d failed\n", k); + failed = 1; + } + putc('\b'); + putc(slash[k % 8]); + } + blank_string(strlen(str_status)); + + printf("Starting 64 channels %s\n", failed ? "failed" : "ok"); + + return 0; +} + +void gd405ex_init(void) +{ + unsigned int k; + + if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */ + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->fpga_state[k] |= FPGA_STATE_PLATFORM; + } else { + pca9698_direction_output(0x22, 39, 1); + } +} + +void gd405ex_set_fpga_reset(unsigned state) +{ + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; + + if (legacy) { + if (state) { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + } else { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + } + } else { + pca9698_set_value(0x22, 39, state ? 0 : 1); + } +} + +void gd405ex_setup_hw(void) +{ + gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0); + gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1); +} + +int gd405ex_get_fpga_done(unsigned fpga) +{ + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; + + if (legacy) + return in_le16((void *)LATCH3_BASE) + & CONFIG_SYS_FPGA_DONE(fpga); + else + return pca9698_get_value(0x22, fpga ? 9 : 8); +} diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 2868cc8..05dd65d 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -30,6 +30,7 @@ endif LIB = $(obj)lib$(VENDOR).o COBJS-$(CONFIG_IO) += miiphybb.o +COBJS-$(CONFIG_IO64) += miiphybb.o COBJS-$(CONFIG_IOCON) += osd.o COBJS-$(CONFIG_DLVISION_10G) += osd.o diff --git a/board/gdsys/common/miiphybb.c b/board/gdsys/common/miiphybb.c index e56e966..46f1a1e 100644 --- a/board/gdsys/common/miiphybb.c +++ b/board/gdsys/common/miiphybb.c @@ -26,6 +26,11 @@ #include +struct io_bb_pinset { + int mdio; + int mdc; +}; + static int io_bb_mii_init(struct bb_miiphy_bus *bus) { return 0; @@ -33,47 +38,57 @@ static int io_bb_mii_init(struct bb_miiphy_bus *bus) static int io_bb_mdio_active(struct bb_miiphy_bus *bus) { + struct io_bb_pinset *pins = bus->priv; + out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) | CONFIG_SYS_MDIO_PIN); + in_be32((void *)GPIO0_TCR) | pins->mdio); return 0; } static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus) { + struct io_bb_pinset *pins = bus->priv; + out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) & ~CONFIG_SYS_MDIO_PIN); + in_be32((void *)GPIO0_TCR) & ~pins->mdio); return 0; } static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v) { + struct io_bb_pinset *pins = bus->priv; + if (v) out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDIO_PIN); + in_be32((void *)GPIO0_OR) | pins->mdio); else out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDIO_PIN); + in_be32((void *)GPIO0_OR) & ~pins->mdio); return 0; } static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) { - *v = ((in_be32((void *)GPIO0_IR) & CONFIG_SYS_MDIO_PIN) != 0); + struct io_bb_pinset *pins = bus->priv; + + *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0); return 0; } static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v) { + struct io_bb_pinset *pins = bus->priv; + if (v) out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDC_PIN); + in_be32((void *)GPIO0_OR) | pins->mdc); else out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDC_PIN); + in_be32((void *)GPIO0_OR) & ~pins->mdc); return 0; } @@ -85,6 +100,19 @@ static int io_bb_delay(struct bb_miiphy_bus *bus) return 0; } +struct io_bb_pinset io_bb_pinsets[] = { + { + .mdio = CONFIG_SYS_MDIO_PIN, + .mdc = CONFIG_SYS_MDC_PIN, + }, +#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME + { + .mdio = CONFIG_SYS_MDIO1_PIN, + .mdc = CONFIG_SYS_MDC1_PIN, + }, +#endif +}; + struct bb_miiphy_bus bb_miiphy_buses[] = { { .name = CONFIG_SYS_GBIT_MII_BUSNAME, @@ -95,7 +123,21 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { .get_mdio = io_bb_get_mdio, .set_mdc = io_bb_set_mdc, .delay = io_bb_delay, - } + .priv = &io_bb_pinsets[0], + }, +#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME + { + .name = CONFIG_SYS_GBIT_MII1_BUSNAME, + .init = io_bb_mii_init, + .mdio_active = io_bb_mdio_active, + .mdio_tristate = io_bb_mdio_tristate, + .set_mdio = io_bb_set_mdio, + .get_mdio = io_bb_get_mdio, + .set_mdc = io_bb_set_mdc, + .delay = io_bb_delay, + .priv = &io_bb_pinsets[1], + }, +#endif }; int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / diff --git a/boards.cfg b/boards.cfg index c83d861..d13c47a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -954,6 +954,7 @@ dlvision-10g powerpc ppc4xx 405ep gdsys gdppc440etx powerpc ppc4xx - gdsys intip powerpc ppc4xx intip gdsys - intip:INTIB io powerpc ppc4xx 405ep gdsys +io64 powerpc ppc4xx 405ex gdsys iocon powerpc ppc4xx 405ep gdsys neo powerpc ppc4xx - gdsys icon powerpc ppc4xx - mosaixtech diff --git a/include/configs/io64.h b/include/configs/io64.h new file mode 100644 index 0000000..51b2dd1 --- /dev/null +++ b/include/configs/io64.h @@ -0,0 +1,566 @@ +/* + * (C) Copyright 2011 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * based on kilauea.h + * by Stefan Roese, DENX Software Engineering, sr@denx.de. + * and Grant Erickson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * io64.h - configuration for Guntermann & Drunck Io64 (405EX) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_IO64 1 /* Board is Io64 */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EX 1 /* Specifc 405EX support*/ +#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 +#endif + +/* + * CHIP_21 errata + */ +#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY + +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME io64 +#define CONFIG_IDENT_STRING " io64 0.01" +#include "amcc-common.h" + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R +#define CONFIG_LAST_STAGE_INIT + +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CONFIG_SYS_FLASH_BASE 0xFC000000 +#define CONFIG_SYS_NVRAM_BASE 0xF0000000 +#define CONFIG_SYS_FPGA0_BASE 0xF0100000 +#define CONFIG_SYS_FPGA1_BASE 0xF0108000 +#define CONFIG_SYS_LATCH_BASE 0xF0200000 + +/*----------------------------------------------------------------------- + * Initial RAM & Stack Pointer Configuration Options + * + * There are traditionally three options for the primordial + * (i.e. initial) stack usage on the 405-series: + * + * 1) On-chip Memory (OCM) (i.e. SRAM) + * 2) Data cache + * 3) SDRAM + * + * For the 405EX(r), there is no OCM, so we are left with (2) or (3) + * the latter of which is less than desireable since it requires + * setting up the SDRAM and ECC in assembly code. + * + * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip + * select on the External Bus Controller (EBC) and then select a + * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid, + * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and + * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid, + * physical SDRAM to use (3). + *-----------------------------------------------------------------------*/ + +#define CONFIG_SYS_INIT_DCACHE_CS 4 + +#if defined(CONFIG_SYS_INIT_DCACHE_CS) +#define CONFIG_SYS_INIT_RAM_ADDR \ + (CONFIG_SYS_SDRAM_BASE + (1 << 30)) /* 1 GiB */ +#else +#define CONFIG_SYS_INIT_RAM_ADDR \ + (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */ +#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ + +#define CONFIG_SYS_INIT_RAM_SIZE \ + (4 << 10) /* 4 KiB */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * If the data cache is being used for the primordial stack and global + * data area, the POST word must be placed somewhere else. The General + * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves + * its compare and mask register contents across reset, so it is used + * for the POST word. + */ + +#if defined(CONFIG_SYS_INIT_DCACHE_CS) +# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +# define CONFIG_SYS_POST_WORD_ADDR \ + (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) +#else +# define CONFIG_SYS_INIT_EXTRA_SIZE 16 +# define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE) +# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR +#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_BASE_BAUD 691200 + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* Gbit PHYs */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +#define CONFIG_BITBANGMII_MULTI + +#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 12) /* MDIO is GPIO12 */ +#define CONFIG_SYS_MDC_PIN (0x80000000 >> 13) /* MDC is GPIO13 */ + +#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy0" + +#define CONFIG_SYS_MDIO1_PIN (0x80000000 >> 2) /* MDIO is GPIO2 */ +#define CONFIG_SYS_MDC1_PIN (0x80000000 >> 3) /* MDC is GPIO3 */ + +#define CONFIG_SYS_GBIT_MII1_BUSNAME "io_miiphy1" + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SYS_MBYTES_SDRAM (128) /* 128MB */ + +/* + * CONFIG_PPC4xx_DDR_AUTOCALIBRATION + * + * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx + * SDRAM Controller DDR autocalibration values and takes a lot longer + * to run than Method_B. + * (See the Method_A and Method_B algorithm discription in the file: + * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c) + * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A + * + * DDR Autocalibration Method_B is the default. + */ +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION +#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION +#undef CONFIG_PPC4xx_DDR_METHOD_A + +#define CONFIG_SYS_SDRAM0_MB0CF_BASE ((0 << 20) + CONFIG_SYS_SDRAM_BASE) + +/* DDR1/2 SDRAM Device Control Register Data Values */ +#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \ + SDRAM_RXBAS_SDSZ_128MB | \ + SDRAM_RXBAS_SDAM_MODE2 | \ + SDRAM_RXBAS_SDBE_ENABLE) +#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE +#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE +#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE +#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \ + SDRAM_MCOPT1_4_BANKS | \ + SDRAM_MCOPT1_DDR2_TYPE | \ + SDRAM_MCOPT1_QDEP | \ + SDRAM_MCOPT1_DCOO_DISABLED) +#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \ + SDRAM_MODT_EB0R_ENABLE) +#define CONFIG_SYS_SDRAM0_MODT1 0x00000000 +#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \ + SDRAM_CODT_CKLZ_36OHM | \ + SDRAM_CODT_DQS_1_8_V_DDR2 | \ + SDRAM_CODT_IO_NMODE) +#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560) +#define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(80) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP)) +#define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(3) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) +#define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL)) +#define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \ + SDRAM_INITPLR_IMA_ENCODE(0)) +#define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_75OHM)) +#define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ + JEDEC_MA_MR_CL_DDR2_5_0_CLK | \ + JEDEC_MA_MR_BLEN_4 | \ + JEDEC_MA_MR_DLL_RESET)) +#define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(3) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ + SDRAM_INITPLR_IBA_ENCODE(0x0) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) +#define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ + JEDEC_MA_MR_CL_DDR2_5_0_CLK | \ + JEDEC_MA_MR_BLEN_4)) +#define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \ + JEDEC_MA_EMR_RDQS_DISABLE | \ + JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_DISABLED | \ + JEDEC_MA_EMR_ODS_NORMAL)) +#define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \ + JEDEC_MA_EMR_RDQS_DISABLE | \ + JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_DISABLED | \ + JEDEC_MA_EMR_ODS_NORMAL)) +#define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE) +#define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE) +#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \ + SDRAM_RQDC_RQFD_ENCODE(56)) +#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521) +#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2) +#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \ + SDRAM_DLCR_DLCS_CONT_DONE | \ + SDRAM_DLCR_DLCV_ENCODE(165)) +#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV) +#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000 +#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \ + SDRAM_SDTR1_RTW_2_CLK | \ + SDRAM_SDTR1_WTWO_1_CLK | \ + SDRAM_SDTR1_RTRO_1_CLK) +#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \ + SDRAM_SDTR2_WTR_2_CLK | \ + SDRAM_SDTR2_XSNR_32_CLK | \ + SDRAM_SDTR2_WPC_4_CLK | \ + SDRAM_SDTR2_RPC_2_CLK | \ + SDRAM_SDTR2_RP_3_CLK | \ + SDRAM_SDTR2_RRD_2_CLK) +#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \ + SDRAM_SDTR3_RC_ENCODE(12) | \ + SDRAM_SDTR3_XCS | \ + SDRAM_SDTR3_RFC_ENCODE(21)) +#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \ + SDRAM_MMODE_DCL_DDR2_5_0_CLK | \ + SDRAM_MMODE_BLEN_4) +#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \ + SDRAM_MEMODE_RTT_75OHM) + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ + +#define CONFIG_PCA9698 1 /* NXP PCA9698 */ + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 + +/* Temp sensor/hwmon/dtt */ +#define CONFIG_DTT_LM63 1 /* National LM63 */ +#define CONFIG_DTT_SENSORS { 0x18, 0x4c, 0x4e } /* Sensor addresses */ +#define CONFIG_DTT_PWM_LOOKUPTABLE \ + { { 40, 10 }, { 43, 13 }, { 46, 16 }, \ + { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } } +#define CONFIG_DTT_TACH_LIMIT 0xa10 + +/*----------------------------------------------------------------------- + * Ethernet + *----------------------------------------------------------------------*/ +#define CONFIG_M88E1111_PHY 1 +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII +#define CONFIG_PHY_ADDR 0x12 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 1 + +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 0x13 + +/* Debug messages for the DDR autocalibration */ +#define CONFIG_AUTOCALIB "silent\0" + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "logversion=2\0" \ + "kernel_addr=fc000000\0" \ + "fdt_addr=fc1e0000\0" \ + "ramdisk_addr=fc200000\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:RP\0" \ + "" + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_CHIP_CONFIG +#define CONFIG_CMD_DTT + +#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY + +/* POST support */ +#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ + CONFIG_SYS_POST_CPU | \ + CONFIG_SYS_POST_ETHER | \ + CONFIG_SYS_POST_I2C | \ + CONFIG_SYS_POST_MEMORY_ON | \ + CONFIG_SYS_POST_UART) + +/* Define here the base-addresses of the UARTs to test in POST */ +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ + CONFIG_SYS_NS16550_COM2 } + +#define CONFIG_LOGBUFFER +#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ + +/* Memory Bank 0 (NOR-flash) */ +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(11) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(1) | \ + EBC_BXAP_WBF_ENCODE(2) | \ + EBC_BXAP_TH_ENCODE(2) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ + EBC_BXCR_BS_64MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* Memory Bank 1 (NVRAM/Uart) */ +#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_ENABLED | \ + EBC_BXAP_FWT_ENCODE(8) | \ + EBC_BXAP_BWT_ENCODE(4) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(1) | \ + EBC_BXAP_WBN_ENCODE(1) | \ + EBC_BXAP_WBF_ENCODE(1) | \ + EBC_BXAP_TH_ENCODE(2) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_8BIT) + +/* Memory Bank 2 (FPGA) */ +#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(5) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(2) | \ + EBC_BXAP_WBN_ENCODE(1) | \ + EBC_BXAP_WBF_ENCODE(1) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* Memory Bank 3 (Latches) */ +#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \ + EBC_BXAP_FWT_ENCODE(8) | \ + EBC_BXAP_BWT_ENCODE(4) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(1) | \ + EBC_BXAP_WBN_ENCODE(1) | \ + EBC_BXAP_WBF_ENCODE(1) | \ + EBC_BXAP_TH_ENCODE(2) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* EBC peripherals */ + +#define CONFIG_SYS_FPGA_BASE(k) \ + (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE) + +#define CONFIG_SYS_FPGA_DONE(k) \ + (k ? 0x0040 : 0x0080) + +#define CONFIG_SYS_FPGA_COUNT 2 + +#define CONFIG_SYS_LATCH0_RESET 0xffff +#define CONFIG_SYS_LATCH0_BOOT 0xffff +#define CONFIG_SYS_LATCH1_RESET 0xffbf +#define CONFIG_SYS_LATCH1_BOOT 0xffff + +/*----------------------------------------------------------------------- + * GPIO Setup + *----------------------------------------------------------------------*/ +#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO0 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO3 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO6 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO8 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO9 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO10 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO11 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO12 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO13 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO14 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO15 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO16 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO17 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO18 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO19 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO20 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO21 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO22 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO23 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO24 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_0 }, /* GPIO25 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO26 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO27 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO28 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO29 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO30 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO31 */ \ +} \ +} + +#define CONFIG_SYS_GPIO_STARTUP_FINISHED 15 +#define CONFIG_SYS_GPIO_STARTUP_FINISHED_N 14 + +#endif /* __CONFIG_H */ diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index c0b1b5c..e7a072b 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -24,9 +24,12 @@ #ifndef __GDSYS_FPGA_H #define __GDSYS_FPGA_H +int init_func_fpga(void); + enum { FPGA_STATE_DONE_FAILED = 1 << 0, FPGA_STATE_REFLECTION_FAILED = 1 << 1, + FPGA_STATE_PLATFORM = 1 << 2, }; int get_fpga_state(unsigned dev); @@ -68,6 +71,22 @@ typedef struct ihs_fpga { } ihs_fpga_t; #endif +#ifdef CONFIG_IO64 +typedef struct ihs_fpga { + u16 reflection_low; /* 0x0000 */ + u16 versions; /* 0x0002 */ + u16 fpga_features; /* 0x0004 */ + u16 fpga_version; /* 0x0006 */ + u16 reserved_0[5]; /* 0x0008 */ + u16 quad_serdes_reset; /* 0x0012 */ + u16 reserved_1[502]; /* 0x0014 */ + u16 ch0_status_int; /* 0x0400 */ + u16 ch0_config_int; /* 0x0402 */ + u16 reserved_2[7677]; /* 0x0404 */ + u16 reflection_high; /* 0x3ffe */ +} ihs_fpga_t; +#endif + #ifdef CONFIG_IOCON typedef struct ihs_fpga { u16 reflection_low; /* 0x0000 */ -- cgit v0.10.2 From b9b50e89d317c58becd0e2d7fac2e21e3a81dd0a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 10 Nov 2011 13:17:53 -0700 Subject: image: Implement IH_TYPE_KERNEL_NOLOAD The legacy uImage format includes an absolute load and entry-point address. When bootm operates on a kernel uImage in memory that isn't loaded at the address in the image's load address, U-Boot will copy the image to its address in the header. Some kernel images can actually be loaded and used at any arbitrary address. An example is an ARM Linux kernel zImage file. To represent this capability, IH_TYPE_KERNEL_NOLOAD is implemented, which operates just like IH_TYPE_KERNEL, except that the load address header is ignored, and U-Boot does not copy the image to its load address, but rather uses it in-place. This is useful when sharing a single (uImage-wrapped) zImage across multiple boards with different memory layouts; in this case, a specific load address need not be picked when creating the uImage, but instead is selected by the board-specific U-Boot environment used to load and boot that image. v2: Rename from IH_TYPE_KERNEL_ANYLOAD to IH_TYPE_KERNEL_NOLOAD. Signed-off-by: Stephen Warren Signed-off-by: Stefan Roese diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index b073f09..8cafe3e 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -272,7 +272,13 @@ static int bootm_start(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] return 1; } + if (images.os.type == IH_TYPE_KERNEL_NOLOAD) { + images.os.load = images.os.image_start; + images.ep += images.os.load; + } + if (((images.os.type == IH_TYPE_KERNEL) || + (images.os.type == IH_TYPE_KERNEL_NOLOAD) || (images.os.type == IH_TYPE_MULTI)) && (images.os.os == IH_OS_LINUX)) { /* find ramdisk */ @@ -796,7 +802,8 @@ static int fit_check_kernel(const void *fit, int os_noffset, int verify) } show_boot_progress(106); - if (!fit_image_check_type(fit, os_noffset, IH_TYPE_KERNEL)) { + if (!fit_image_check_type(fit, os_noffset, IH_TYPE_KERNEL) && + !fit_image_check_type(fit, os_noffset, IH_TYPE_KERNEL_NOLOAD)) { puts("Not a kernel image\n"); show_boot_progress(-106); return 0; @@ -874,6 +881,7 @@ static void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc, /* get os_data and os_len */ switch (image_get_type(hdr)) { case IH_TYPE_KERNEL: + case IH_TYPE_KERNEL_NOLOAD: *os_data = image_get_data(hdr); *os_len = image_get_data_size(hdr); break; diff --git a/common/image.c b/common/image.c index 555d9d9..aacae5a 100644 --- a/common/image.c +++ b/common/image.c @@ -136,6 +136,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_FIRMWARE, "firmware", "Firmware", }, { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, { IH_TYPE_KERNEL, "kernel", "Kernel Image", }, + { IH_TYPE_KERNEL_NOLOAD, "kernel_noload", "Kernel Image (no loading done)", }, { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",}, { IH_TYPE_INVALID, NULL, "Invalid Image", }, diff --git a/include/image.h b/include/image.h index 6a41c2e..466c980 100644 --- a/include/image.h +++ b/include/image.h @@ -162,6 +162,7 @@ #define IH_TYPE_UBLIMAGE 11 /* Davinci UBL Image */ #define IH_TYPE_OMAPIMAGE 12 /* TI OMAP Config Header Image */ #define IH_TYPE_AISIMAGE 13 /* TI Davinci AIS Image */ +#define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */ /* * Compression Types diff --git a/tools/default_image.c b/tools/default_image.c index 6ea3b46..e9d0729 100644 --- a/tools/default_image.c +++ b/tools/default_image.c @@ -35,7 +35,8 @@ static image_header_t header; static int image_check_image_types(uint8_t type) { - if ((type > IH_TYPE_INVALID) && (type < IH_TYPE_FLATDT)) + if (((type > IH_TYPE_INVALID) && (type < IH_TYPE_FLATDT)) || + (type == IH_TYPE_KERNEL_NOLOAD)) return EXIT_SUCCESS; else return EXIT_FAILURE; -- cgit v0.10.2 From d510859bed4165ebf2635c74c40a037cd2819fce Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 10 Nov 2011 13:17:54 -0700 Subject: image: Don't detect XIP images as overlapping. bootm_load_os() detects when it writes the decompressed image over the top of the compressed image. If this happens, the original image is corrupted. When the original image is a multi-component legacy image, or a (potentially multi-component) FIT image, this implies that other components may be corrupted. In turn, this means that booting is unlikely to be successful. However, in the case of no image compresssion coupled with an image with load address equal to where the image is already located (e.g. an XIP kernel, or IH_TYPE_KERNEL_ANYLOAD), there has been no copy and hence no corruption, no matter whether it's a single-component legacy image, a multi-component legacy image, or a FIT image. In this case, disable the overlap detection, and allow boot to continue. Without this change, when booting a single-component legacy image that contains an IH_TYPE_KERNEL_ANYLOAD, bootm_load_os() would have returned BOOTM_ERR_OVERLAP, but the caller ignores this, and boot continues and succeeds. Now, the false error is no longer even returned. Without this change, when booting a FIT image that contains an IH_TYPE_KERNEL_ANYLOAD, bootm_load_os() would have returned BOOTM_ERR_OVERLAP, which would then cause the caller to reset the board. Now, the false error is no longer returned, and boot succeeds. Signed-off-by: Stephen Warren Signed-off-by: Stefan Roese diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 8cafe3e..d5745b1 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -320,6 +320,7 @@ static int bootm_load_os(image_info_t os, ulong *load_end, int boot_progress) ulong image_start = os.image_start; ulong image_len = os.image_len; __maybe_unused uint unc_len = CONFIG_SYS_BOOTM_LEN; + int no_overlap = 0; #if defined(CONFIG_LZMA) || defined(CONFIG_LZO) int ret; #endif /* defined(CONFIG_LZMA) || defined(CONFIG_LZO) */ @@ -330,6 +331,7 @@ static int bootm_load_os(image_info_t os, ulong *load_end, int boot_progress) case IH_COMP_NONE: if (load == blob_start || load == image_start) { printf(" XIP %s ... ", type_name); + no_overlap = 1; } else { printf(" Loading %s ... ", type_name); memmove_wd((void *)load, (void *)image_start, @@ -424,7 +426,7 @@ static int bootm_load_os(image_info_t os, ulong *load_end, int boot_progress) if (boot_progress) show_boot_progress(7); - if ((load < blob_end) && (*load_end > blob_start)) { + if (!no_overlap && (load < blob_end) && (*load_end > blob_start)) { debug("images.os.start = 0x%lX, images.os.end = 0x%lx\n", blob_start, blob_end); debug("images.os.load = 0x%lx, load_end = 0x%lx\n", load, -- cgit v0.10.2 From bba8f3929e1ae3c09274b8dcdf0ad7b099494f71 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:44 +0000 Subject: alpr board: Fix GCC 4.6 build warnings Fix: fpga.c: In function 'fpga_pre_fn': fpga.c:88:16: warning: variable 'reg' set but not used [-Wunused-but-set-variable] nand.c: In function 'alpr_nand_dev_ready': nand.c:125:18: warning: variable 'val' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Cc: Stefan Roese Acked-by: Stefan Roese diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c index e7686ad..1cce798 100644 --- a/board/prodrive/alpr/fpga.c +++ b/board/prodrive/alpr/fpga.c @@ -85,9 +85,6 @@ static unsigned long regval; /* PROGRAM_SEL_DPR = LOW */ int fpga_pre_fn(int cookie) { - unsigned long reg; - - reg = in32(GPIO0_IR); /* Enable the FPGA Chain */ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN); SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN); diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c index b18c96b..d35cfed 100644 --- a/board/prodrive/alpr/nand.c +++ b/board/prodrive/alpr/nand.c @@ -122,12 +122,10 @@ static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len static int alpr_nand_dev_ready(struct mtd_info *mtd) { - volatile u_char val; - /* * Blocking read to wait for NAND to be ready */ - val = readb(&(alpr_ndfc->addr_wait)); + (void)readb(&(alpr_ndfc->addr_wait)); /* * Return always true -- cgit v0.10.2 From 2752a525b8f6f1b591b0a053f284bc51848eb174 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:45 +0000 Subject: board/amirix/ap1000/flash.c: Fix GCC 4.6 build warning Fix: flash.c: In function 'flash_write_cfiword': flash.c:778:11: warning: variable 'ctladdr' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Acked-by: Marek Vasut diff --git a/board/amirix/ap1000/flash.c b/board/amirix/ap1000/flash.c index 1e742e5..bf8877e 100644 --- a/board/amirix/ap1000/flash.c +++ b/board/amirix/ap1000/flash.c @@ -774,12 +774,9 @@ static ulong flash_get_size (ulong base, int banknum) static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword) { - - cfiptr_t ctladdr; cfiptr_t cptr; int flag; - ctladdr.cp = flash_make_addr (info, 0, 0); cptr.cp = (uchar *) dest; /* Check if Flash is (sufficiently) erased */ -- cgit v0.10.2 From 24ec52dec298ffb5298cd57ddd3567fe00347988 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:46 +0000 Subject: drivers/block/sata_dwc.c: Fix GCC 4.6 build warning Fix: sata_dwc.c: In function 'scan_sata': sata_dwc.c:535:38: warning: variable 'udma_mask' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Cc: Kazuaki Ichinohe diff --git a/drivers/block/sata_dwc.c b/drivers/block/sata_dwc.c index 69ec5fd..75101b5 100644 --- a/drivers/block/sata_dwc.c +++ b/drivers/block/sata_dwc.c @@ -532,7 +532,7 @@ int scan_sata(int dev) u8 status; const u16 *id; struct ata_device *ata_dev = &ata_device; - unsigned long pio_mask, mwdma_mask, udma_mask; + unsigned long pio_mask, mwdma_mask; char revbuf[7]; u16 iobuf[ATA_SECTOR_WORDS]; @@ -622,10 +622,6 @@ int scan_sata(int dev) mwdma_mask |= (1 << 4); } - udma_mask = 0; - if (id[ATA_ID_FIELD_VALID] & (1 << 2)) - udma_mask = id[ATA_ID_UDMA_MODES] & 0xff; - if (ata_dev->class == ATA_DEV_ATA) { if (ata_id_is_cfa(id)) { if (id[162] & 1) -- cgit v0.10.2 From fc4df325dc90d194428cb188e24abf6aae48dc50 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:47 +0000 Subject: board/cray/L1/flash.c: Fix GCC 4.6 build warning Fix: flash.c: In function 'flash_erase': flash.c:276:24: warning: variable 'l_sect' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Acked-by: Marek Vasut diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c index a3d893e..77a2100 100644 --- a/board/cray/L1/flash.c +++ b/board/cray/L1/flash.c @@ -273,7 +273,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) { volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) { @@ -303,16 +303,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - printf("Erasing sector %p\n", addr2); + addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); + printf("Erasing sector %p\n", addr2); addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; @@ -320,15 +318,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7(info, sect); } } -- cgit v0.10.2 From 4fcfbec0d74d20dc230a4a4e0e36a9f3bf17ce46 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:48 +0000 Subject: DB64360: Fix GCC 4.6 build warnings Fix: db64360.c: In function 'debug_led': db64360.c:413:6: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_real_open': mv_eth.c:424:6: warning: variable 'port_status' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_stop': mv_eth.c:642:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_xmit': mv_eth.c:718:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_receive': mv_eth.c:803:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_get_stats': mv_eth.c:902:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_update_stat': mv_eth.c:930:24: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] mv_eth.c:929:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_print_stat': mv_eth.c:1011:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'eth_clear_mib_counters': mv_eth.c:2068:15: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'check_dimm': sdram_init.c:289:50: warning: variable 'trrd_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:37: warning: variable 'tras_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:24: warning: variable 'trcd_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:8: warning: variable 'trp_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:279:34: warning: variable 'devicesForErrCheck' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'setup_sdram': sdram_init.c:1256:13: warning: variable 'check' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'initdram': sdram_init.c:1735:25: warning: variable 'check' set but not used [-Wunused-but-set-variable] sdram_init.c:1733:14: warning: variable 's1' set but not used [-Wunused-but-set-variable] sdram_init.c:1733:6: warning: variable 's0' set but not used [-Wunused-but-set-variable] Note: no attempt was make to clean up the mess coding style and other issues in sdram_init.c Signed-off-by: Wolfgang Denk diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c index 35b695e..5183466 100644 --- a/board/Marvell/db64360/db64360.c +++ b/board/Marvell/db64360/db64360.c @@ -34,6 +34,7 @@ #include "../include/mv_gen_reg.h" #include #include +#include #include "eth.h" #include "mpsc.h" @@ -410,7 +411,7 @@ int checkboard (void) void debug_led (int led, int mode) { volatile int *addr = 0; - int dummy; + __maybe_unused int dummy; if (mode == 1) { switch (led) { diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c index 30304b0..6340585 100644 --- a/board/Marvell/db64360/mv_eth.c +++ b/board/Marvell/db64360/mv_eth.c @@ -421,7 +421,7 @@ static int mv64360_eth_real_open (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; unsigned int port_num; - u32 port_status, phy_reg_data; + u32 phy_reg_data; ethernet_private = (ETH_PORT_INFO *) dev->priv; /* ronen - when we update the MAC env params we only update dev->enetaddr @@ -519,7 +519,7 @@ static int mv64360_eth_real_open (struct eth_device *dev) */ MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); + MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); /* Check Link status on phy */ eth_port_read_smi_reg (port_num, 1, &phy_reg_data); @@ -637,15 +637,6 @@ static int mv64360_eth_free_rx_rings (struct eth_device *dev) int mv64360_eth_stop (struct eth_device *dev) { - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - /* Disable all gigE address decoder */ MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f); DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); @@ -715,7 +706,6 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, { ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; ETH_FUNC_RET_STATUS status; struct net_device_stats *stats; @@ -724,7 +714,6 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; @@ -800,15 +789,12 @@ int mv64360_eth_receive (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; struct net_device_stats *stats; - ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == @@ -899,12 +885,10 @@ static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; - unsigned int port_num; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; mv64360_eth_update_stat (dev); @@ -926,13 +910,10 @@ static void mv64360_eth_update_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; - volatile unsigned int dummy; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; /* These are false updates */ @@ -955,12 +936,12 @@ static void mv64360_eth_update_stat (struct eth_device *dev) * But the unsigned long in PowerPC and MIPS are 32bit. So the next read * is just a dummy read for proper work of the GigE port */ - dummy = eth_read_mib_counter (ethernet_private->port_num, + eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); stats->tx_bytes += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_LOW); - dummy = eth_read_mib_counter (ethernet_private->port_num, + eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_HIGH); stats->rx_errors += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, @@ -1008,12 +989,10 @@ static void mv64360_eth_print_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; /* These are false updates */ @@ -2065,13 +2044,11 @@ static void eth_port_init_mac_tables (ETH_PORT eth_port_num) static void eth_clear_mib_counters (ETH_PORT eth_port_num) { int i; - unsigned int dummy; /* Perform dummy reads from MIB counters */ for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; i += 4) - dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE - (eth_port_num) + i)); + MV_REG_READ((MV64360_ETH_MIB_COUNTERS_BASE(eth_port_num) + i)); return; } diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c index d52d3f0..e62ed0c 100644 --- a/board/Marvell/db64360/sdram_init.c +++ b/board/Marvell/db64360/sdram_init.c @@ -44,15 +44,8 @@ DECLARE_GLOBAL_DATA_PTR; -#undef DEBUG #define MAP_PCI -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - int set_dfcdlInit (void); /* setup delay line of Mv64360 */ int mvDmaIsChannelActive (int); int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); @@ -276,7 +269,7 @@ return 0; #else uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; int ret; - unsigned int i, j, density = 1, devicesForErrCheck = 0; + unsigned int i, j, density = 1; #ifdef DEBUG unsigned int k; @@ -286,17 +279,17 @@ return 0; uchar supp_cal, cal_val; ulong memclk, tmemclk; ulong tmp; - uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; + uchar trp_clocks = 0, tras_clocks; uchar data[128]; memclk = gd->bus_clk; tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - DP (puts ("before i2c read\n")); + debug("before i2c read\n"); ret = i2c_read (addr, 0, 1, data, 128); - DP (puts ("after i2c read\n")); + debug("after i2c read\n"); /* zero all the values */ memset (dimmInfo, 0, sizeof (*dimmInfo)); @@ -307,7 +300,7 @@ return 0; } if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); + debug("No DIMM in slot %d [err = %x]\n", slot, ret); return 0; } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ @@ -385,48 +378,46 @@ return 0; switch (i) { case 2: /* Memory type (DDR / SDRAM) */ dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; -#ifdef DEBUG if (dimmInfo->memoryType == 0) - DP (printf + debug ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot)); + dimmInfo->slot); if (dimmInfo->memoryType == 1) - DP (printf + debug ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot)); -#endif + dimmInfo->slot); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 3: /* Number Of Row Addresses */ dimmInfo->numOfRowAddresses = data[i]; - DP (printf + debug ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses)); + dimmInfo->numOfRowAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 4: /* Number Of Column Addresses */ dimmInfo->numOfColAddresses = data[i]; - DP (printf + debug ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses)); + dimmInfo->numOfColAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 5: /* Number Of Module Banks */ dimmInfo->numOfModuleBanks = data[i]; - DP (printf + debug ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks)); + dimmInfo->numOfModuleBanks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 6: /* Data Width */ dimmInfo->dataWidth = data[i]; - DP (printf + debug ("Module Data Width: %d\n", - dimmInfo->dataWidth)); + dimmInfo->dataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -434,33 +425,33 @@ return 0; switch (data[i]) { case 0x0: dimmInfo->voltageInterface = TTL_5V_TOLERANT; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug + ("Module is TTL_5V_TOLERANT\n"); break; case 0x1: dimmInfo->voltageInterface = LVTTL; - DP (printf - ("Module is LVTTL\n")); + debug + ("Module is LVTTL\n"); break; case 0x2: dimmInfo->voltageInterface = HSTL_1_5V; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug + ("Module is TTL_5V_TOLERANT\n"); break; case 0x3: dimmInfo->voltageInterface = SSTL_3_3V; - DP (printf - ("Module is HSTL_1_5V\n")); + debug + ("Module is HSTL_1_5V\n"); break; case 0x4: dimmInfo->voltageInterface = SSTL_2_5V; - DP (printf - ("Module is SSTL_2_5V\n")); + debug + ("Module is SSTL_2_5V\n"); break; default: dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - DP (printf - ("Module is VOLTAGE_UNKNOWN\n")); + debug + ("Module is VOLTAGE_UNKNOWN\n"); break; } break; @@ -479,9 +470,9 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = rightOfPoint; - DP (printf + debug ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -494,49 +485,49 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOut_LoP = leftOfPoint; dimmInfo->clockToDataOut_RoP = rightOfPoint; - DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */ + debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ /*#ifdef CONFIG_ECC */ case 11: /* Error Check Type */ dimmInfo->errorCheckType = data[i]; - DP (printf + debug ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType)); + dimmInfo->errorCheckType); break; /* #endif */ /*------------------------------------------------------------------------------------------------------------------------------*/ case 12: /* Refresh Interval */ dimmInfo->RefreshInterval = data[i]; - DP (printf + debug ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval)); + dimmInfo->RefreshInterval); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 13: /* Sdram Width */ dimmInfo->sdramWidth = data[i]; - DP (printf + debug ("Sdram Width: %d\n", - dimmInfo->sdramWidth)); + dimmInfo->sdramWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 14: /* Error Check Data Width */ dimmInfo->errorCheckDataWidth = data[i]; - DP (printf + debug ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth)); + dimmInfo->errorCheckDataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 15: /* Minimum Clock Delay */ dimmInfo->minClkDelay = data[i]; - DP (printf + debug ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay)); + dimmInfo->minClkDelay); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -552,26 +543,26 @@ return 0; dimmInfo->burstLengthSupported = data[i]; #ifdef DEBUG - DP (printf - ("Burst Length Supported: ")); + debug + ("Burst Length Supported: "); if (dimmInfo->burstLengthSupported & 0x01) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->burstLengthSupported & 0x02) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->burstLengthSupported & 0x04) - DP (printf ("4, ")); + debug("4, "); if (dimmInfo->burstLengthSupported & 0x08) - DP (printf ("8, ")); - DP (printf (" Bit \n")); + debug("8, "); + debug(" Bit \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 17: /* Number Of Banks On Each Device */ dimmInfo->numOfBanksOnEachDevice = data[i]; - DP (printf + debug ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice)); + dimmInfo->numOfBanksOnEachDevice); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -591,34 +582,34 @@ return 0; ********************************************************/ dimmInfo->suportedCasLatencies = data[i]; #ifdef DEBUG - DP (printf - ("Suported Cas Latencies: (CL) ")); + debug + ("Suported Cas Latencies: (CL) "); if (dimmInfo->memoryType == 0) { /* SDRAM */ for (k = 0; k <= 7; k++) { if (dimmInfo-> suportedCasLatencies & (1 << k)) - DP (printf + debug ("%d, ", - k + 1)); + k + 1); } } else { /* DDR-RAM */ if (dimmInfo->suportedCasLatencies & 1) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->suportedCasLatencies & 2) - DP (printf ("1.5, ")); + debug("1.5, "); if (dimmInfo->suportedCasLatencies & 4) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->suportedCasLatencies & 8) - DP (printf ("2.5, ")); + debug("2.5, "); if (dimmInfo->suportedCasLatencies & 16) - DP (printf ("3, ")); + debug("3, "); if (dimmInfo->suportedCasLatencies & 32) - DP (printf ("3.5, ")); + debug("3.5, "); } - DP (printf ("\n")); + debug("\n"); #endif /* Calculating MAX CAS latency */ for (j = 7; j > 0; j--) { @@ -630,8 +621,8 @@ return 0; /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ switch (j) { case 7: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug + ("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -639,8 +630,8 @@ return 0; hang (); break; case 6: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug + ("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -648,36 +639,36 @@ return 0; hang (); break; case 5: - DP (printf - ("Max. Cas Latencies (DDR): 3.5 clk's\n")); + debug + ("Max. Cas Latencies (DDR): 3.5 clk's\n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3_5; break; case 4: - DP (printf - ("Max. Cas Latencies (DDR): 3 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 3 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3; break; case 3: - DP (printf - ("Max. Cas Latencies (DDR): 2.5 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 2.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2_5; break; case 2: - DP (printf - ("Max. Cas Latencies (DDR): 2 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 2 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2; break; case 1: - DP (printf - ("Max. Cas Latencies (DDR): 1.5 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 1.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_1_5; @@ -707,8 +698,8 @@ return 0; dimmInfo-> maxClSupported_DDR >> 1; - DP (printf - ("*** Change actual Cas Latencies cause of minimumCycleTime n")); + debug + ("*** Change actual Cas Latencies cause of minimumCycleTime n"); } /* ronen - checkif the Dimm frequency compared to the Sysclock. */ if ((dimmInfo-> @@ -744,32 +735,32 @@ return 0; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf + debug ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; case SDRAM: /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - DP (printf + debug ("Max. Cas Latencies (SD): %d\n", dimmInfo-> - maxClSupported_SD)); + maxClSupported_SD); dimmInfo-> maxCASlatencySupported_LoP = j; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf + debug ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; } break; @@ -779,7 +770,7 @@ return 0; /*------------------------------------------------------------------------------------------------------------------------------*/ case 21: /* Buffered Address And Control Inputs */ - DP (printf ("\nModul Attributes (SPD Byte 21): \n")); + debug("\nModul Attributes (SPD Byte 21): \n"); dimmInfo->bufferedAddrAndControlInputs = data[i] & BIT0; dimmInfo->registeredAddrAndControlInputs = @@ -794,60 +785,60 @@ return 0; (data[i] & BIT6) >> 6; #ifdef DEBUG if (dimmInfo->bufferedAddrAndControlInputs == 1) - DP (printf - (" - Buffered Address/Control Input: Yes \n")); + debug + (" - Buffered Address/Control Input: Yes \n"); else - DP (printf - (" - Buffered Address/Control Input: No \n")); + debug + (" - Buffered Address/Control Input: No \n"); if (dimmInfo->registeredAddrAndControlInputs == 1) - DP (printf - (" - Registered Address/Control Input: Yes \n")); + debug + (" - Registered Address/Control Input: Yes \n"); else - DP (printf - (" - Registered Address/Control Input: No \n")); + debug + (" - Registered Address/Control Input: No \n"); if (dimmInfo->onCardPLL == 1) - DP (printf - (" - On-Card PLL (clock): Yes \n")); + debug + (" - On-Card PLL (clock): Yes \n"); else - DP (printf - (" - On-Card PLL (clock): No \n")); + debug + (" - On-Card PLL (clock): No \n"); if (dimmInfo->bufferedDQMBinputs == 1) - DP (printf - (" - Bufferd DQMB Inputs: Yes \n")); + debug + (" - Bufferd DQMB Inputs: Yes \n"); else - DP (printf - (" - Bufferd DQMB Inputs: No \n")); + debug + (" - Bufferd DQMB Inputs: No \n"); if (dimmInfo->registeredDQMBinputs == 1) - DP (printf - (" - Registered DQMB Inputs: Yes \n")); + debug + (" - Registered DQMB Inputs: Yes \n"); else - DP (printf - (" - Registered DQMB Inputs: No \n")); + debug + (" - Registered DQMB Inputs: No \n"); if (dimmInfo->differentialClockInput == 1) - DP (printf - (" - Differential Clock Input: Yes \n")); + debug + (" - Differential Clock Input: Yes \n"); else - DP (printf - (" - Differential Clock Input: No \n")); + debug + (" - Differential Clock Input: No \n"); if (dimmInfo->redundantRowAddressing == 1) - DP (printf - (" - redundant Row Addressing: Yes \n")); + debug + (" - redundant Row Addressing: Yes \n"); else - DP (printf - (" - redundant Row Addressing: No \n")); + debug + (" - redundant Row Addressing: No \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 22: /* Suported AutoPreCharge */ - DP (printf ("\nModul Attributes (SPD Byte 22): \n")); + debug("\nModul Attributes (SPD Byte 22): \n"); dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; dimmInfo->suportedAutoPreCharge = (data[i] & BIT1) >> 1; @@ -861,46 +852,46 @@ return 0; (data[i] & BIT5) >> 5; #ifdef DEBUG if (dimmInfo->suportedEarlyRasPreCharge == 1) - DP (printf - (" - Early Ras Precharge: Yes \n")); + debug + (" - Early Ras Precharge: Yes \n"); else - DP (printf - (" - Early Ras Precharge: No \n")); + debug + (" - Early Ras Precharge: No \n"); if (dimmInfo->suportedAutoPreCharge == 1) - DP (printf - (" - AutoPreCharge: Yes \n")); + debug + (" - AutoPreCharge: Yes \n"); else - DP (printf - (" - AutoPreCharge: No \n")); + debug + (" - AutoPreCharge: No \n"); if (dimmInfo->suportedPreChargeAll == 1) - DP (printf - (" - Precharge All: Yes \n")); + debug + (" - Precharge All: Yes \n"); else - DP (printf - (" - Precharge All: No \n")); + debug + (" - Precharge All: No \n"); if (dimmInfo->suportedWrite1ReadBurst == 1) - DP (printf - (" - Write 1/ReadBurst: Yes \n")); + debug + (" - Write 1/ReadBurst: Yes \n"); else - DP (printf - (" - Write 1/ReadBurst: No \n")); + debug + (" - Write 1/ReadBurst: No \n"); if (dimmInfo->suported5PercentLowVCC == 1) - DP (printf - (" - lower VCC tolerance: 5 Percent \n")); + debug + (" - lower VCC tolerance: 5 Percent \n"); else - DP (printf - (" - lower VCC tolerance: 10 Percent \n")); + debug + (" - lower VCC tolerance: 10 Percent \n"); if (dimmInfo->suported5PercentUpperVCC == 1) - DP (printf - (" - upper VCC tolerance: 5 Percent \n")); + debug + (" - upper VCC tolerance: 5 Percent \n"); else - DP (printf - (" - upper VCC tolerance: 10 Percent \n")); + debug + (" - upper VCC tolerance: 10 Percent \n"); #endif break; @@ -919,7 +910,7 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = rightOfPoint; - DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -932,9 +923,9 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - DP (printf + debug ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -951,7 +942,7 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = rightOfPoint; - DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -964,9 +955,9 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - DP (printf + debug ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -983,12 +974,12 @@ return 0; trp_clocks = (dimmInfo->minRowPrechargeTime + (tmemclk - 1)) / tmemclk; - DP (printf + debug ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100)); - DP (printf + tmemclk, tmemclk / 100, tmemclk % 100); + debug ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1002,12 +993,9 @@ return 0; rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trrd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1021,12 +1009,9 @@ return 0; rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trcd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1035,41 +1020,41 @@ return 0; tras_clocks = (NSto10PS (data[i]) + (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks)); + dimmInfo->minRasPulseWidth, tras_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 31: /* Module Bank Density */ dimmInfo->moduleBankDensity = data[i]; - DP (printf + debug ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity)); + dimmInfo->moduleBankDensity); #ifdef DEBUG - DP (printf - ("*** Offered Densities (more than 1 = Multisize-Module): ")); + debug + ("*** Offered Densities (more than 1 = Multisize-Module): "); { if (dimmInfo->moduleBankDensity & 1) - DP (printf ("4MB, ")); + debug("4MB, "); if (dimmInfo->moduleBankDensity & 2) - DP (printf ("8MB, ")); + debug("8MB, "); if (dimmInfo->moduleBankDensity & 4) - DP (printf ("16MB, ")); + debug("16MB, "); if (dimmInfo->moduleBankDensity & 8) - DP (printf ("32MB, ")); + debug("32MB, "); if (dimmInfo->moduleBankDensity & 16) - DP (printf ("64MB, ")); + debug("64MB, "); if (dimmInfo->moduleBankDensity & 32) - DP (printf ("128MB, ")); + debug("128MB, "); if ((dimmInfo->moduleBankDensity & 64) || (dimmInfo->moduleBankDensity & 128)) { - DP (printf ("ERROR, ")); + debug("ERROR, "); hang (); } } - DP (printf ("\n")); + debug("\n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1095,9 +1080,9 @@ return 0; } dimmInfo->addrAndCommandSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1122,9 +1107,9 @@ return 0; } dimmInfo->addrAndCommandHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1149,9 +1134,9 @@ return 0; } dimmInfo->dataInputSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1176,9 +1161,9 @@ return 0; } dimmInfo->dataInputHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ } @@ -1194,8 +1179,6 @@ return 0; dimmInfo->numberOfDevices = (dimmInfo->dataWidth / dimmInfo->sdramWidth) * dimmInfo->numOfModuleBanks; - devicesForErrCheck = - (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; if ((dimmInfo->errorCheckType == 0x1) || (dimmInfo->errorCheckType == 0x2) || (dimmInfo->errorCheckType == 0x3)) { @@ -1217,7 +1200,7 @@ return 0; tmp *= dimmInfo->sdramWidth; tmp = tmp >> 24; /* div by 0x4000000 (64M) */ dimmInfo->drb_size = (uchar) tmp; - DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); + debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); /* try a CAS latency of 3 first... */ @@ -1236,11 +1219,11 @@ return 0; cal_val = 2; } - DP (printf ("cal_val = %d\n", cal_val)); + debug("cal_val = %d\n", cal_val); /* bummer, did't work... */ if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); + debug("Couldn't find a good CAS latency\n"); hang (); return 0; } @@ -1272,13 +1255,13 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* delay line */ set_dfcdlInit (); /* may be its not needed */ - DP (printf ("Delay line set done\n")); + debug("Delay line set done\n"); /* set SDRAM mode NOP */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x5); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); } /* SDRAM configuration */ @@ -1329,12 +1312,12 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); break; } - DP (printf ("calculated refresh interval %0x\n", sdram_config_reg)); + debug("calculated refresh interval %0x\n", sdram_config_reg); /* make sure the refresh value is only 14 bits */ if (sdram_config_reg > 0x1fff) sdram_config_reg = 0x1fff; - DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg)); + debug("adjusted refresh interval %0x\n", sdram_config_reg); /* we want physical bank interleaving and */ /* virtual bank interleaving enabled so do nothing */ @@ -1344,30 +1327,30 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs == 1) { /* it's registered DRAM, so set the reg. DRAM bit */ sdram_config_reg = sdram_config_reg | BIT17; - DP (printf ("Enabling registered DRAM bit\n")); + debug("Enabling registered DRAM bit\n"); } /* turn on DRAM ECC? */ #ifdef CONFIG_MV64360_ECC if (info->errorCheckType == 0x2) { /* DRAM has ECC, so turn it on */ sdram_config_reg = sdram_config_reg | BIT18; - DP (printf ("Enabling ECC\n")); + debug("Enabling ECC\n"); } #endif /* set the data DQS pin configuration */ switch (info->sdramWidth) { case 0x4: /* memory is x4 */ sdram_config_reg = sdram_config_reg | BIT20 | BIT21; - DP (printf ("Data DQS pins set for 16 pins\n")); + debug("Data DQS pins set for 16 pins\n"); break; case 0x8: /* memory is x8 or x16 */ case 0x10: sdram_config_reg = sdram_config_reg | BIT21; - DP (printf ("Data DQS pins set for 8 pins\n")); + debug("Data DQS pins set for 8 pins\n"); break; case 0x20: /* memory is x32 */ /* both bits are cleared for x32 so nothing to do */ - DP (printf ("Data DQS pins set for 2 pins\n")); + debug("Data DQS pins set for 2 pins\n"); break; default: /* memory width unsupported */ printf ("DRAM chip width is unknown!\n"); @@ -1390,23 +1373,23 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* write the value into the SDRAM configuration register */ GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); - DP (printf + debug ("OOOOOOOOO sdram_conf 0x1400: %08x\n", - GTREGREAD (SDRAM_CONFIG))); + GTREGREAD (SDRAM_CONFIG)); /* SDRAM open pages control keep open as much as I can */ GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - DP (printf + debug ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); + GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ if (tmp == 0) - DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); + debug("Core Signals are sync (by HW-Setting)!!!\n"); else - DP (printf - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); + debug + ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); /* SDRAM set CAS Latency according to SPD information */ switch (info->memoryType) { @@ -1419,7 +1402,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* Calculate the settings for SDRAM mode and Dunit control low registers */ /* Values set according to technical bulletin TB-92 rev. c */ case DDR: - DP (printf ("### SET-CL for DDR-RAM\n")); + debug("### SET-CL for DDR-RAM\n"); switch (info->maxClSupported_DDR) { case DDR_CL_3: tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ @@ -1428,18 +1411,18 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x05110051; else tmp_dunit_control_low = 0x24110051; - DP (printf + debug ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */ if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ tmp_dunit_control_low = 0x2C1107F2; else tmp_dunit_control_low = 0x3C1107d2; - DP (printf + debug ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_2_5: @@ -1449,9 +1432,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x25110051; else tmp_dunit_control_low = 0x24110051; - DP (printf + debug ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */ if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ @@ -1460,9 +1443,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); } else tmp_dunit_control_low = 0x1B1107d2; - DP (printf + debug ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_2: @@ -1472,9 +1455,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x04110051; else tmp_dunit_control_low = 0x03110051; - DP (printf + debug ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */ if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ @@ -1483,9 +1466,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); } else tmp_dunit_control_low = 0x3B1107d2; - DP (printf + debug ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_1_5: @@ -1495,9 +1478,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x24110051; else tmp_dunit_control_low = 0x23110051; - DP (printf + debug ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */ if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ @@ -1506,9 +1489,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); } else tmp_dunit_control_low = 0x1A1107d2; - DP (printf + debug ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; @@ -1528,8 +1511,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ @@ -1538,8 +1521,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); } /*------------------------------------------------------------------------------ */ @@ -1549,29 +1532,29 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* program this with the default value */ tmp = 0x02; /* power-up default address select decoding value */ - DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); + debug("drb_size (n*64Mbit): %d\n", info->drb_size); /* figure out the DRAM chip size */ sdram_chip_size = (1 << (info->numOfRowAddresses + info->numOfColAddresses)); sdram_chip_size *= info->sdramWidth; sdram_chip_size *= 4; - DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size)); + debug("computed sdram chip size is %#lx\n", sdram_chip_size); /* divide sdram chip size by 64 Mbits */ sdram_chip_size = sdram_chip_size / 0x4000000; switch (sdram_chip_size) { case 1: /* 64 Mbit */ case 2: /* 128 Mbit */ - DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); + debug("RAM-Device_size 64Mbit or 128Mbit)\n"); tmp |= (0x00 << 4); break; case 4: /* 256 Mbit */ case 8: /* 512 Mbit */ - DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); + debug("RAM-Device_size 256Mbit or 512Mbit)\n"); tmp |= (0x01 << 4); break; case 16: /* 1 Gbit */ case 32: /* 2 Gbit */ - DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); + debug("RAM-Device_size 1Gbit or 2Gbit)\n"); tmp |= (0x02 << 4); break; default: @@ -1582,15 +1565,15 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* SDRAM address control */ GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - DP (printf + debug ("setting up sdram address control (0x1410) with: %08lx \n", - tmp)); + tmp); /* ------------------------------------------------------------------------------ */ /* same settings for registerd & non-registerd DDR SDRAM */ - DP (printf + debug ("setting up sdram_timing_control_low (0x1408) with: %08x \n", - 0x11511220)); + 0x11511220); GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220); @@ -1602,42 +1585,38 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs || info->registeredDQMBinputs) { tmp |= (1 << 17); - DP (printf + debug ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", info->registeredAddrAndControlInputs, - info->registeredDQMBinputs)); + info->registeredDQMBinputs); } /* Use buffer 1 to return read data to the CPU * Page 426 MV64360 */ tmp |= (1 << 26); - DP (printf + debug ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); - DP (printf + GTREGREAD (SDRAM_CONFIG)); + debug ("After Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); + GTREGREAD (SDRAM_CONFIG)); /* SDRAM timing To_do: */ /* ------------------------------------------------------------------------------ */ - DP (printf + debug ("setting up sdram_timing_control_high (0x140c) with: %08x \n", - 0x9)); + 0x9); GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9); - DP (printf + debug ("setting up sdram address pads control (0x14c0) with: %08x \n", - 0x7d5014a)); + 0x7d5014a); GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); - DP (printf - indent: Standard input:1450: Warning:old style assignment ambiguity in "=*". Assuming "= *" - -indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". Assuming "= *" - + debug ("setting up sdram data pads control (0x14c4) with: %08x \n", - 0x7d5014a)); + 0x7d5014a); GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); /* ------------------------------------------------------------------------------ */ @@ -1647,8 +1626,8 @@ indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". As /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ { i = info->slot; - DP (printf - ("\n*** Running a MRS cycle for bank %d ***\n", i)); + debug + ("\n*** Running a MRS cycle for bank %d ***\n", i); /* map the bank */ memory_map_bank (i, 0, GB / 4); @@ -1656,17 +1635,17 @@ indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". As /* set SDRAM mode */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); check = GTREGREAD (SDRAM_OPERATION); - DP (printf + debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + check); /* switch back to normal operation mode */ GT_REG_WRITE (SDRAM_OPERATION, 0); check = GTREGREAD (SDRAM_OPERATION); - DP (printf + debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + check); /* unmap the bank */ memory_map_bank (i, 0, 0); @@ -1712,9 +1691,9 @@ long int dram_size (long int *base, long int maxsize) *b = save2; if (val != cnt) { - DP (printf + debug ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr)); + (unsigned int) val, (unsigned int) addr); /* fix boundary condition.. STARTVAL means zero */ if (cnt == STARTVAL / sizeof (long)) cnt = 0; @@ -1730,9 +1709,8 @@ long int dram_size (long int *base, long int maxsize) * controlling logic happens */ phys_size_t initdram (int board_type) { - int s0 = 0, s1 = 0; int checkbank[4] = {[0 ... 3] = 0 }; - ulong realsize, total, check; + ulong realsize, total; AUX_MEM_DIMM_INFO dimmInfo1; AUX_MEM_DIMM_INFO dimmInfo2; int nhr, bank_no; @@ -1747,10 +1725,10 @@ phys_size_t initdram (int board_type) printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); } else { /* DIMM0 */ - s0 = check_dimm (0, &dimmInfo1); + check_dimm (0, &dimmInfo1); /* DIMM1 */ - s1 = check_dimm (1, &dimmInfo2); + check_dimm (1, &dimmInfo2); memory_map_bank (0, 0, 0); memory_map_bank (1, 0, 0); @@ -1784,7 +1762,6 @@ phys_size_t initdram (int board_type) /* next, size the SDRAM banks */ realsize = total = 0; - check = GB / 4; if (dimmInfo1.numOfModuleBanks > 0) { checkbank[0] = 1; } -- cgit v0.10.2 From 774b35768571d5b061fc8287dc532c9ea96c443b Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:49 +0000 Subject: DB64460: Fix GCC 4.6 build warnings Fix: db64460.c: In function 'debug_led': db64460.c:413:6: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64460_eth_real_open': mv_eth.c:423:6: warning: variable 'port_status' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64460_eth_stop': mv_eth.c:641:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64460_eth_xmit': mv_eth.c:717:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64460_eth_receive': mv_eth.c:802:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64460_eth_get_stats': mv_eth.c:901:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64460_eth_update_stat': mv_eth.c:929:24: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] mv_eth.c:928:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64460_eth_print_stat': mv_eth.c:1010:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'eth_clear_mib_counters': mv_eth.c:2067:15: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'check_dimm': sdram_init.c:289:50: warning: variable 'trrd_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:37: warning: variable 'tras_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:24: warning: variable 'trcd_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:8: warning: variable 'trp_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:279:34: warning: variable 'devicesForErrCheck' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'setup_sdram': sdram_init.c:1255:13: warning: variable 'check' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'initdram': sdram_init.c:1744:25: warning: variable 'check' set but not used [-Wunused-but-set-variable] sdram_init.c:1742:14: warning: variable 's1' set but not used [-Wunused-but-set-variable] sdram_init.c:1742:6: warning: variable 's0' set but not used [-Wunused-but-set-variable] Note: no attempt was make to clean up the mess coding style and other issues in sdram_init.c Signed-off-by: Wolfgang Denk diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c index 14e6355..a7836ed 100644 --- a/board/Marvell/db64460/db64460.c +++ b/board/Marvell/db64460/db64460.c @@ -34,6 +34,7 @@ #include "../include/mv_gen_reg.h" #include #include +#include #include "eth.h" #include "mpsc.h" @@ -410,7 +411,7 @@ int checkboard (void) void debug_led (int led, int mode) { volatile int *addr = 0; - int dummy; + __maybe_unused int dummy; if (mode == 1) { switch (led) { diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c index cd9d5a4..4aefbaf 100644 --- a/board/Marvell/db64460/mv_eth.c +++ b/board/Marvell/db64460/mv_eth.c @@ -420,7 +420,7 @@ static int mv64460_eth_real_open (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; unsigned int port_num; - u32 port_status, phy_reg_data; + u32 phy_reg_data; ethernet_private = (ETH_PORT_INFO *) dev->priv; /* ronen - when we update the MAC env params we only update dev->enetaddr @@ -518,7 +518,7 @@ static int mv64460_eth_real_open (struct eth_device *dev) */ MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); + MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); /* Check Link status on phy */ eth_port_read_smi_reg (port_num, 1, &phy_reg_data); @@ -636,15 +636,6 @@ static int mv64460_eth_free_rx_rings (struct eth_device *dev) int mv64460_eth_stop (struct eth_device *dev) { - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - /* Disable all gigE address decoder */ MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f); DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); @@ -714,7 +705,6 @@ int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, { ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; ETH_FUNC_RET_STATUS status; struct net_device_stats *stats; @@ -723,7 +713,6 @@ int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; @@ -799,15 +788,12 @@ int mv64460_eth_receive (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; struct net_device_stats *stats; - ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == @@ -898,12 +884,10 @@ static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; - unsigned int port_num; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; mv64460_eth_update_stat (dev); @@ -925,13 +909,10 @@ static void mv64460_eth_update_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; - volatile unsigned int dummy; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; /* These are false updates */ @@ -954,12 +935,12 @@ static void mv64460_eth_update_stat (struct eth_device *dev) * But the unsigned long in PowerPC and MIPS are 32bit. So the next read * is just a dummy read for proper work of the GigE port */ - dummy = eth_read_mib_counter (ethernet_private->port_num, + eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); stats->tx_bytes += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_LOW); - dummy = eth_read_mib_counter (ethernet_private->port_num, + eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_HIGH); stats->rx_errors += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, @@ -1007,12 +988,10 @@ static void mv64460_eth_print_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; /* These are false updates */ @@ -2064,13 +2043,11 @@ static void eth_port_init_mac_tables (ETH_PORT eth_port_num) static void eth_clear_mib_counters (ETH_PORT eth_port_num) { int i; - unsigned int dummy; /* Perform dummy reads from MIB counters */ for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; i += 4) - dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE - (eth_port_num) + i)); + MV_REG_READ((MV64460_ETH_MIB_COUNTERS_BASE(eth_port_num) + i)); return; } diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c index e328d8f..6297447 100644 --- a/board/Marvell/db64460/sdram_init.c +++ b/board/Marvell/db64460/sdram_init.c @@ -44,15 +44,8 @@ DECLARE_GLOBAL_DATA_PTR; -#undef DEBUG #define MAP_PCI -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - int set_dfcdlInit (void); /* setup delay line of Mv64460 */ int mvDmaIsChannelActive (int); int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); @@ -69,14 +62,12 @@ memory_map_bank (unsigned int bankNo, #endif -#ifdef DEBUG if (bankLength > 0) { - printf ("mapping bank %d at %08x - %08x\n", + debug("mapping bank %d at %08x - %08x\n", bankNo, bankBase, bankBase + bankLength - 1); } else { - printf ("unmapping bank %d\n", bankNo); + debug("unmapping bank %d\n", bankNo); } -#endif memoryMapBank (bankNo, bankBase, bankLength); @@ -276,7 +267,7 @@ return 0; #else uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; int ret; - unsigned int i, j, density = 1, devicesForErrCheck = 0; + unsigned int i, j, density = 1; #ifdef DEBUG unsigned int k; @@ -286,17 +277,17 @@ return 0; uchar supp_cal, cal_val; ulong memclk, tmemclk; ulong tmp; - uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; + uchar trp_clocks = 0, tras_clocks; uchar data[128]; memclk = gd->bus_clk; tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - DP (puts ("before i2c read\n")); + debug("before i2c read\n"); ret = i2c_read (addr, 0, 1, data, 128); - DP (puts ("after i2c read\n")); + debug("after i2c read\n"); /* zero all the values */ memset (dimmInfo, 0, sizeof (*dimmInfo)); @@ -307,7 +298,7 @@ return 0; } if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); + debug("No DIMM in slot %d [err = %x]\n", slot, ret); return 0; } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ @@ -387,46 +378,46 @@ return 0; dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; #ifdef DEBUG if (dimmInfo->memoryType == 0) - DP (printf + debug ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot)); + dimmInfo->slot); if (dimmInfo->memoryType == 1) - DP (printf + debug ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot)); + dimmInfo->slot); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 3: /* Number Of Row Addresses */ dimmInfo->numOfRowAddresses = data[i]; - DP (printf + debug ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses)); + dimmInfo->numOfRowAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 4: /* Number Of Column Addresses */ dimmInfo->numOfColAddresses = data[i]; - DP (printf + debug ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses)); + dimmInfo->numOfColAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 5: /* Number Of Module Banks */ dimmInfo->numOfModuleBanks = data[i]; - DP (printf + debug ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks)); + dimmInfo->numOfModuleBanks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 6: /* Data Width */ dimmInfo->dataWidth = data[i]; - DP (printf + debug ("Module Data Width: %d\n", - dimmInfo->dataWidth)); + dimmInfo->dataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -434,33 +425,33 @@ return 0; switch (data[i]) { case 0x0: dimmInfo->voltageInterface = TTL_5V_TOLERANT; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug + ("Module is TTL_5V_TOLERANT\n"); break; case 0x1: dimmInfo->voltageInterface = LVTTL; - DP (printf - ("Module is LVTTL\n")); + debug + ("Module is LVTTL\n"); break; case 0x2: dimmInfo->voltageInterface = HSTL_1_5V; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug + ("Module is TTL_5V_TOLERANT\n"); break; case 0x3: dimmInfo->voltageInterface = SSTL_3_3V; - DP (printf - ("Module is HSTL_1_5V\n")); + debug + ("Module is HSTL_1_5V\n"); break; case 0x4: dimmInfo->voltageInterface = SSTL_2_5V; - DP (printf - ("Module is SSTL_2_5V\n")); + debug + ("Module is SSTL_2_5V\n"); break; default: dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - DP (printf - ("Module is VOLTAGE_UNKNOWN\n")); + debug + ("Module is VOLTAGE_UNKNOWN\n"); break; } break; @@ -479,9 +470,9 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = rightOfPoint; - DP (printf + debug ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -494,49 +485,49 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOut_LoP = leftOfPoint; dimmInfo->clockToDataOut_RoP = rightOfPoint; - DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */ + debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ /*#ifdef CONFIG_ECC */ case 11: /* Error Check Type */ dimmInfo->errorCheckType = data[i]; - DP (printf + debug ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType)); + dimmInfo->errorCheckType); break; /* #endif */ /*------------------------------------------------------------------------------------------------------------------------------*/ case 12: /* Refresh Interval */ dimmInfo->RefreshInterval = data[i]; - DP (printf + debug ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval)); + dimmInfo->RefreshInterval); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 13: /* Sdram Width */ dimmInfo->sdramWidth = data[i]; - DP (printf + debug ("Sdram Width: %d\n", - dimmInfo->sdramWidth)); + dimmInfo->sdramWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 14: /* Error Check Data Width */ dimmInfo->errorCheckDataWidth = data[i]; - DP (printf + debug ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth)); + dimmInfo->errorCheckDataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 15: /* Minimum Clock Delay */ dimmInfo->minClkDelay = data[i]; - DP (printf + debug ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay)); + dimmInfo->minClkDelay); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -552,26 +543,26 @@ return 0; dimmInfo->burstLengthSupported = data[i]; #ifdef DEBUG - DP (printf - ("Burst Length Supported: ")); + debug + ("Burst Length Supported: "); if (dimmInfo->burstLengthSupported & 0x01) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->burstLengthSupported & 0x02) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->burstLengthSupported & 0x04) - DP (printf ("4, ")); + debug("4, "); if (dimmInfo->burstLengthSupported & 0x08) - DP (printf ("8, ")); - DP (printf (" Bit \n")); + debug("8, "); + debug(" Bit \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 17: /* Number Of Banks On Each Device */ dimmInfo->numOfBanksOnEachDevice = data[i]; - DP (printf + debug ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice)); + dimmInfo->numOfBanksOnEachDevice); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -591,34 +582,34 @@ return 0; ********************************************************/ dimmInfo->suportedCasLatencies = data[i]; #ifdef DEBUG - DP (printf - ("Suported Cas Latencies: (CL) ")); + debug + ("Suported Cas Latencies: (CL) "); if (dimmInfo->memoryType == 0) { /* SDRAM */ for (k = 0; k <= 7; k++) { if (dimmInfo-> suportedCasLatencies & (1 << k)) - DP (printf + debug ("%d, ", - k + 1)); + k + 1); } } else { /* DDR-RAM */ if (dimmInfo->suportedCasLatencies & 1) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->suportedCasLatencies & 2) - DP (printf ("1.5, ")); + debug("1.5, "); if (dimmInfo->suportedCasLatencies & 4) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->suportedCasLatencies & 8) - DP (printf ("2.5, ")); + debug("2.5, "); if (dimmInfo->suportedCasLatencies & 16) - DP (printf ("3, ")); + debug("3, "); if (dimmInfo->suportedCasLatencies & 32) - DP (printf ("3.5, ")); + debug("3.5, "); } - DP (printf ("\n")); + debug("\n"); #endif /* Calculating MAX CAS latency */ for (j = 7; j > 0; j--) { @@ -630,8 +621,8 @@ return 0; /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ switch (j) { case 7: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug + ("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -639,8 +630,8 @@ return 0; hang (); break; case 6: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug + ("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -648,36 +639,36 @@ return 0; hang (); break; case 5: - DP (printf - ("Max. Cas Latencies (DDR): 3.5 clk's\n")); + debug + ("Max. Cas Latencies (DDR): 3.5 clk's\n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3_5; break; case 4: - DP (printf - ("Max. Cas Latencies (DDR): 3 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 3 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3; break; case 3: - DP (printf - ("Max. Cas Latencies (DDR): 2.5 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 2.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2_5; break; case 2: - DP (printf - ("Max. Cas Latencies (DDR): 2 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 2 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2; break; case 1: - DP (printf - ("Max. Cas Latencies (DDR): 1.5 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 1.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_1_5; @@ -707,8 +698,8 @@ return 0; dimmInfo-> maxClSupported_DDR >> 1; - DP (printf - ("*** Change actual Cas Latencies cause of minimumCycleTime n")); + debug + ("*** Change actual Cas Latencies cause of minimumCycleTime n"); } /* ronen - checkif the Dimm frequency compared to the Sysclock. */ if ((dimmInfo-> @@ -744,32 +735,32 @@ return 0; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf + debug ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; case SDRAM: /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - DP (printf + debug ("Max. Cas Latencies (SD): %d\n", dimmInfo-> - maxClSupported_SD)); + maxClSupported_SD); dimmInfo-> maxCASlatencySupported_LoP = j; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf + debug ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; } break; @@ -779,7 +770,7 @@ return 0; /*------------------------------------------------------------------------------------------------------------------------------*/ case 21: /* Buffered Address And Control Inputs */ - DP (printf ("\nModul Attributes (SPD Byte 21): \n")); + debug("\nModul Attributes (SPD Byte 21): \n"); dimmInfo->bufferedAddrAndControlInputs = data[i] & BIT0; dimmInfo->registeredAddrAndControlInputs = @@ -794,60 +785,60 @@ return 0; (data[i] & BIT6) >> 6; #ifdef DEBUG if (dimmInfo->bufferedAddrAndControlInputs == 1) - DP (printf - (" - Buffered Address/Control Input: Yes \n")); + debug + (" - Buffered Address/Control Input: Yes \n"); else - DP (printf - (" - Buffered Address/Control Input: No \n")); + debug + (" - Buffered Address/Control Input: No \n"); if (dimmInfo->registeredAddrAndControlInputs == 1) - DP (printf - (" - Registered Address/Control Input: Yes \n")); + debug + (" - Registered Address/Control Input: Yes \n"); else - DP (printf - (" - Registered Address/Control Input: No \n")); + debug + (" - Registered Address/Control Input: No \n"); if (dimmInfo->onCardPLL == 1) - DP (printf - (" - On-Card PLL (clock): Yes \n")); + debug + (" - On-Card PLL (clock): Yes \n"); else - DP (printf - (" - On-Card PLL (clock): No \n")); + debug + (" - On-Card PLL (clock): No \n"); if (dimmInfo->bufferedDQMBinputs == 1) - DP (printf - (" - Bufferd DQMB Inputs: Yes \n")); + debug + (" - Bufferd DQMB Inputs: Yes \n"); else - DP (printf - (" - Bufferd DQMB Inputs: No \n")); + debug + (" - Bufferd DQMB Inputs: No \n"); if (dimmInfo->registeredDQMBinputs == 1) - DP (printf - (" - Registered DQMB Inputs: Yes \n")); + debug + (" - Registered DQMB Inputs: Yes \n"); else - DP (printf - (" - Registered DQMB Inputs: No \n")); + debug + (" - Registered DQMB Inputs: No \n"); if (dimmInfo->differentialClockInput == 1) - DP (printf - (" - Differential Clock Input: Yes \n")); + debug + (" - Differential Clock Input: Yes \n"); else - DP (printf - (" - Differential Clock Input: No \n")); + debug + (" - Differential Clock Input: No \n"); if (dimmInfo->redundantRowAddressing == 1) - DP (printf - (" - redundant Row Addressing: Yes \n")); + debug + (" - redundant Row Addressing: Yes \n"); else - DP (printf - (" - redundant Row Addressing: No \n")); + debug + (" - redundant Row Addressing: No \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 22: /* Suported AutoPreCharge */ - DP (printf ("\nModul Attributes (SPD Byte 22): \n")); + debug("\nModul Attributes (SPD Byte 22): \n"); dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; dimmInfo->suportedAutoPreCharge = (data[i] & BIT1) >> 1; @@ -861,46 +852,46 @@ return 0; (data[i] & BIT5) >> 5; #ifdef DEBUG if (dimmInfo->suportedEarlyRasPreCharge == 1) - DP (printf - (" - Early Ras Precharge: Yes \n")); + debug + (" - Early Ras Precharge: Yes \n"); else - DP (printf - (" - Early Ras Precharge: No \n")); + debug + (" - Early Ras Precharge: No \n"); if (dimmInfo->suportedAutoPreCharge == 1) - DP (printf - (" - AutoPreCharge: Yes \n")); + debug + (" - AutoPreCharge: Yes \n"); else - DP (printf - (" - AutoPreCharge: No \n")); + debug + (" - AutoPreCharge: No \n"); if (dimmInfo->suportedPreChargeAll == 1) - DP (printf - (" - Precharge All: Yes \n")); + debug + (" - Precharge All: Yes \n"); else - DP (printf - (" - Precharge All: No \n")); + debug + (" - Precharge All: No \n"); if (dimmInfo->suportedWrite1ReadBurst == 1) - DP (printf - (" - Write 1/ReadBurst: Yes \n")); + debug + (" - Write 1/ReadBurst: Yes \n"); else - DP (printf - (" - Write 1/ReadBurst: No \n")); + debug + (" - Write 1/ReadBurst: No \n"); if (dimmInfo->suported5PercentLowVCC == 1) - DP (printf - (" - lower VCC tolerance: 5 Percent \n")); + debug + (" - lower VCC tolerance: 5 Percent \n"); else - DP (printf - (" - lower VCC tolerance: 10 Percent \n")); + debug + (" - lower VCC tolerance: 10 Percent \n"); if (dimmInfo->suported5PercentUpperVCC == 1) - DP (printf - (" - upper VCC tolerance: 5 Percent \n")); + debug + (" - upper VCC tolerance: 5 Percent \n"); else - DP (printf - (" - upper VCC tolerance: 10 Percent \n")); + debug + (" - upper VCC tolerance: 10 Percent \n"); #endif break; @@ -919,7 +910,7 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = rightOfPoint; - DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -932,9 +923,9 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - DP (printf + debug ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -951,7 +942,7 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = rightOfPoint; - DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -964,9 +955,9 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - DP (printf + debug ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -983,12 +974,12 @@ return 0; trp_clocks = (dimmInfo->minRowPrechargeTime + (tmemclk - 1)) / tmemclk; - DP (printf + debug ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100)); - DP (printf + tmemclk, tmemclk / 100, tmemclk % 100); + debug ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1002,12 +993,9 @@ return 0; rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trrd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1021,12 +1009,9 @@ return 0; rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trcd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1035,41 +1020,41 @@ return 0; tras_clocks = (NSto10PS (data[i]) + (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks)); + dimmInfo->minRasPulseWidth, tras_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 31: /* Module Bank Density */ dimmInfo->moduleBankDensity = data[i]; - DP (printf + debug ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity)); + dimmInfo->moduleBankDensity); #ifdef DEBUG - DP (printf - ("*** Offered Densities (more than 1 = Multisize-Module): ")); + debug + ("*** Offered Densities (more than 1 = Multisize-Module): "); { if (dimmInfo->moduleBankDensity & 1) - DP (printf ("4MB, ")); + debug("4MB, "); if (dimmInfo->moduleBankDensity & 2) - DP (printf ("8MB, ")); + debug("8MB, "); if (dimmInfo->moduleBankDensity & 4) - DP (printf ("16MB, ")); + debug("16MB, "); if (dimmInfo->moduleBankDensity & 8) - DP (printf ("32MB, ")); + debug("32MB, "); if (dimmInfo->moduleBankDensity & 16) - DP (printf ("64MB, ")); + debug("64MB, "); if (dimmInfo->moduleBankDensity & 32) - DP (printf ("128MB, ")); + debug("128MB, "); if ((dimmInfo->moduleBankDensity & 64) || (dimmInfo->moduleBankDensity & 128)) { - DP (printf ("ERROR, ")); + debug("ERROR, "); hang (); } } - DP (printf ("\n")); + debug("\n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1095,9 +1080,9 @@ return 0; } dimmInfo->addrAndCommandSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1122,9 +1107,9 @@ return 0; } dimmInfo->addrAndCommandHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1149,9 +1134,9 @@ return 0; } dimmInfo->dataInputSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1176,9 +1161,9 @@ return 0; } dimmInfo->dataInputHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ } @@ -1194,8 +1179,6 @@ return 0; dimmInfo->numberOfDevices = (dimmInfo->dataWidth / dimmInfo->sdramWidth) * dimmInfo->numOfModuleBanks; - devicesForErrCheck = - (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; if ((dimmInfo->errorCheckType == 0x1) || (dimmInfo->errorCheckType == 0x2) || (dimmInfo->errorCheckType == 0x3)) { @@ -1217,7 +1200,7 @@ return 0; tmp *= dimmInfo->sdramWidth; tmp = tmp >> 24; /* div by 0x4000000 (64M) */ dimmInfo->drb_size = (uchar) tmp; - DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); + debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); /* try a CAS latency of 3 first... */ @@ -1236,11 +1219,11 @@ return 0; cal_val = 2; } - DP (printf ("cal_val = %d\n", cal_val)); + debug("cal_val = %d\n", cal_val); /* bummer, did't work... */ if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); + debug("Couldn't find a good CAS latency\n"); hang (); return 0; } @@ -1271,13 +1254,13 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* delay line */ set_dfcdlInit (); /* may be its not needed */ - DP (printf ("Delay line set done\n")); + debug("Delay line set done\n"); /* set SDRAM mode NOP */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x5); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); } /* SDRAM configuration */ @@ -1328,12 +1311,12 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); break; } - DP (printf ("calculated refresh interval %0x\n", sdram_config_reg)); + debug("calculated refresh interval %0x\n", sdram_config_reg); /* make sure the refresh value is only 14 bits */ if (sdram_config_reg > 0x1fff) sdram_config_reg = 0x1fff; - DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg)); + debug("adjusted refresh interval %0x\n", sdram_config_reg); /* we want physical bank interleaving and */ /* virtual bank interleaving enabled so do nothing */ @@ -1343,30 +1326,30 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs == 1) { /* it's registered DRAM, so set the reg. DRAM bit */ sdram_config_reg = sdram_config_reg | BIT17; - DP (printf ("Enabling registered DRAM bit\n")); + debug("Enabling registered DRAM bit\n"); } /* turn on DRAM ECC? */ #ifdef CONFIG_MV64460_ECC if (info->errorCheckType == 0x2) { /* DRAM has ECC, so turn it on */ sdram_config_reg = sdram_config_reg | BIT18; - DP (printf ("Enabling ECC\n")); + debug("Enabling ECC\n"); } #endif /* set the data DQS pin configuration */ switch (info->sdramWidth) { case 0x4: /* memory is x4 */ sdram_config_reg = sdram_config_reg | BIT20 | BIT21; - DP (printf ("Data DQS pins set for 16 pins\n")); + debug("Data DQS pins set for 16 pins\n"); break; case 0x8: /* memory is x8 or x16 */ case 0x10: sdram_config_reg = sdram_config_reg | BIT21; - DP (printf ("Data DQS pins set for 8 pins\n")); + debug("Data DQS pins set for 8 pins\n"); break; case 0x20: /* memory is x32 */ /* both bits are cleared for x32 so nothing to do */ - DP (printf ("Data DQS pins set for 2 pins\n")); + debug("Data DQS pins set for 2 pins\n"); break; default: /* memory width unsupported */ printf ("DRAM chip width is unknown!\n"); @@ -1392,21 +1375,21 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* write the value into the SDRAM configuration register */ GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); - DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG))); + debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)); /* SDRAM open pages control keep open as much as I can */ GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - DP (printf + debug ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); + GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ if (tmp == 0) - DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); + debug("Core Signals are sync (by HW-Setting)!!!\n"); else - DP (printf - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); + debug + ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); /* SDRAM set CAS Latency according to SPD information */ switch (info->memoryType) { @@ -1419,7 +1402,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* Calculate the settings for SDRAM mode and Dunit control low registers */ /* Values set according to technical bulletin TB-92 rev. c */ case DDR: - DP (printf ("### SET-CL for DDR-RAM\n")); + debug("### SET-CL for DDR-RAM\n"); /* ronen db64460 - change the tmp_dunit_control_low setting!!! */ switch (info->maxClSupported_DDR) { case DDR_CL_3: @@ -1429,9 +1412,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x05110051; else tmp_dunit_control_low = 0x24110051; - DP (printf + debug ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); } else { /* clk sync. bypassed */ @@ -1439,9 +1422,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0xC5000540; else tmp_dunit_control_low = 0xC4000540; - DP (printf + debug ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_2_5: @@ -1451,9 +1434,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x25110051; else tmp_dunit_control_low = 0x24110051; - DP (printf + debug ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); } else { /* clk sync. bypassed */ @@ -1464,9 +1447,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* hang();1 */ } else tmp_dunit_control_low = 0xC4000540; - DP (printf + debug ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_2: @@ -1476,9 +1459,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x04110051; else tmp_dunit_control_low = 0x03110051; - DP (printf + debug ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); } else { /* clk sync. bypassed */ @@ -1489,9 +1472,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0xC4000540; } else tmp_dunit_control_low = 0xC3000540;; - DP (printf + debug ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_1_5: @@ -1501,9 +1484,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x24110051; else tmp_dunit_control_low = 0x23110051; - DP (printf + debug ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); } else { /* clk sync. bypassed */ @@ -1514,9 +1497,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0xC4000540; } else tmp_dunit_control_low = 0xC3000540; - DP (printf + debug ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; @@ -1536,8 +1519,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ @@ -1546,8 +1529,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); } /*------------------------------------------------------------------------------ */ @@ -1557,29 +1540,29 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* program this with the default value */ tmp = 0x02; /* power-up default address select decoding value */ - DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); + debug("drb_size (n*64Mbit): %d\n", info->drb_size); /* figure out the DRAM chip size */ sdram_chip_size = (1 << (info->numOfRowAddresses + info->numOfColAddresses)); sdram_chip_size *= info->sdramWidth; sdram_chip_size *= 4; - DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size)); + debug("computed sdram chip size is %#lx\n", sdram_chip_size); /* divide sdram chip size by 64 Mbits */ sdram_chip_size = sdram_chip_size / 0x4000000; switch (sdram_chip_size) { case 1: /* 64 Mbit */ case 2: /* 128 Mbit */ - DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); + debug("RAM-Device_size 64Mbit or 128Mbit)\n"); tmp |= (0x00 << 4); break; case 4: /* 256 Mbit */ case 8: /* 512 Mbit */ - DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); + debug("RAM-Device_size 256Mbit or 512Mbit)\n"); tmp |= (0x01 << 4); break; case 16: /* 1 Gbit */ case 32: /* 2 Gbit */ - DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); + debug("RAM-Device_size 1Gbit or 2Gbit)\n"); tmp |= (0x02 << 4); break; default: @@ -1590,15 +1573,15 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* SDRAM address control */ GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - DP (printf + debug ("setting up sdram address control (0x1410) with: %08lx \n", - tmp)); + tmp); /* ------------------------------------------------------------------------------ */ /* same settings for registerd & non-registerd DDR SDRAM */ - DP (printf + debug ("setting up sdram_timing_control_low (0x1408) with: %08x \n", - 0x01501220)); + 0x01501220); /*ronen db64460 */ GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220); @@ -1611,10 +1594,10 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs || info->registeredDQMBinputs) { tmp |= (1 << 17); - DP (printf + debug ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", info->registeredAddrAndControlInputs, - info->registeredDQMBinputs)); + info->registeredDQMBinputs); } /* Use buffer 1 to return read data to the CPU @@ -1624,29 +1607,29 @@ indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". As 4460 */ tmp |= (1 << 26); - DP (printf + debug ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); - DP (printf + GTREGREAD (SDRAM_CONFIG)); + debug ("After Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); + GTREGREAD (SDRAM_CONFIG)); /* SDRAM timing To_do: */ /* ------------------------------------------------------------------------------ */ /* ronen db64460 */ - DP (printf + debug ("setting up sdram_timing_control_high (0x140c) with: %08x \n", - 0xc)); + 0xc); GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc); - DP (printf + debug ("setting up sdram address pads control (0x14c0) with: %08x \n", - 0x7d5014a)); + 0x7d5014a); GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); - DP (printf + debug ("setting up sdram data pads control (0x14c4) with: %08x \n", - 0x7d5014a)); + 0x7d5014a); GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); /* ------------------------------------------------------------------------------ */ @@ -1656,8 +1639,8 @@ indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". As /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ { i = info->slot; - DP (printf - ("\n*** Running a MRS cycle for bank %d ***\n", i)); + debug + ("\n*** Running a MRS cycle for bank %d ***\n", i); /* map the bank */ memory_map_bank (i, 0, GB / 4); @@ -1665,17 +1648,17 @@ indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". As /* set SDRAM mode */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); check = GTREGREAD (SDRAM_OPERATION); - DP (printf + debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + check); /* switch back to normal operation mode */ GT_REG_WRITE (SDRAM_OPERATION, 0); check = GTREGREAD (SDRAM_OPERATION); - DP (printf + debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + check); /* unmap the bank */ memory_map_bank (i, 0, 0); @@ -1721,9 +1704,9 @@ long int dram_size (long int *base, long int maxsize) *b = save2; if (val != cnt) { - DP (printf + debug ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr)); + (unsigned int) val, (unsigned int) addr); /* fix boundary condition.. STARTVAL means zero */ if (cnt == STARTVAL / sizeof (long)) cnt = 0; @@ -1739,9 +1722,8 @@ long int dram_size (long int *base, long int maxsize) * controlling logic happens */ phys_size_t initdram (int board_type) { - int s0 = 0, s1 = 0; int checkbank[4] = {[0 ... 3] = 0 }; - ulong realsize, total, check; + ulong realsize, total; AUX_MEM_DIMM_INFO dimmInfo1; AUX_MEM_DIMM_INFO dimmInfo2; int nhr, bank_no; @@ -1756,10 +1738,10 @@ phys_size_t initdram (int board_type) printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); } else { /* DIMM0 */ - s0 = check_dimm (0, &dimmInfo1); + check_dimm (0, &dimmInfo1); /* DIMM1 */ - s1 = check_dimm (1, &dimmInfo2); + check_dimm (1, &dimmInfo2); memory_map_bank (0, 0, 0); memory_map_bank (1, 0, 0); @@ -1793,7 +1775,6 @@ phys_size_t initdram (int board_type) /* next, size the SDRAM banks */ realsize = total = 0; - check = GB / 4; if (dimmInfo1.numOfModuleBanks > 0) { checkbank[0] = 1; } -- cgit v0.10.2 From effa4e30b06e7c4c7d4535bcab8e40652262b13c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:50 +0000 Subject: board/sandburst/common/flash.c: Fix GCC 4.6 build warning Fix: ../common/flash.c: In function 'flash_erase': ../common/flash.c:307:24: warning: variable 'l_sect' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Cc: Travis Sawyer Acked-by: Marek Vasut diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c index c65cb96..818a7c3 100644 --- a/board/sandburst/common/flash.c +++ b/board/sandburst/common/flash.c @@ -304,7 +304,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) { volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; int i; if ((s_first < 0) || (s_first > s_last)) { @@ -335,8 +335,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -363,7 +361,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ } - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must -- cgit v0.10.2 From b0b20d4795260df7bed6882866e6dd3ac12267dd Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:51 +0000 Subject: drivers/usb/host/sl811-hcd.c: Fix GCC 4.6 build warning Fix: sl811-hcd.c: In function 'sl811_rh_submit_urb': sl811-hcd.c:556:8: warning: variable 'wIndex' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Cc: Remy Bohmer diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c index c713d42..bb27dd5 100644 --- a/drivers/usb/host/sl811-hcd.c +++ b/drivers/usb/host/sl811-hcd.c @@ -550,11 +550,12 @@ static int sl811_rh_submit_urb(struct usb_device *usb_dev, unsigned long pipe, __u8 *bufp = data_buf; int len = 0; int status = 0; - __u16 bmRType_bReq; - __u16 wValue; - __u16 wIndex; - __u16 wLength; + __u16 wValue = le16_to_cpu (cmd->value); + __u16 wLength = le16_to_cpu (cmd->length); +#ifdef SL811_DEBUG + __u16 wIndex = le16_to_cpu (cmd->index); +#endif if (usb_pipeint(pipe)) { PDEBUG(0, "interrupt transfer unimplemented!\n"); @@ -562,9 +563,6 @@ static int sl811_rh_submit_urb(struct usb_device *usb_dev, unsigned long pipe, } bmRType_bReq = cmd->requesttype | (cmd->request << 8); - wValue = le16_to_cpu (cmd->value); - wIndex = le16_to_cpu (cmd->index); - wLength = le16_to_cpu (cmd->length); PDEBUG(5, "submit rh urb, req = %d(%x) val = %#x index = %#x len=%d\n", bmRType_bReq, bmRType_bReq, wValue, wIndex, wLength); -- cgit v0.10.2 From e607a15ddb5024a71b0f9e669fe819c1d8839d53 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:52 +0000 Subject: post/board/lwmon5/gdc.c: Fix GCC 4.6 build warning Fix: gdc.c: In function 'gdc_test_reg_one': gdc.c:66:6: warning: variable 'ret' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Cc: Stefan Roese Acked-by: Stefan Roese diff --git a/post/board/lwmon5/gdc.c b/post/board/lwmon5/gdc.c index 719194b..6bbd2c2 100644 --- a/post/board/lwmon5/gdc.c +++ b/post/board/lwmon5/gdc.c @@ -63,13 +63,12 @@ const static unsigned long otherpattern = 0x01234567; /* test write/read og a given LIME Register */ static int gdc_test_reg_one(uint value) { - int ret; uint read_value; /* write test pattern */ out_be32((void *)GDC_SCRATCH_REG, value); /* read other location (protect against data lines capacity) */ - ret = in_be32((void *)GDC_RAM_START); + in_be32((void *)GDC_RAM_START); /* verify test pattern */ read_value = in_be32((void *)GDC_SCRATCH_REG); if (read_value != value) { -- cgit v0.10.2 From ae5f6b3b2fa26eb82b58bd162535e5a80ebed543 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:53 +0000 Subject: board/mpl/common/flash.c: Fix GCC 4.6 build warning Fix: ../common/flash.c: In function 'flash_init': ../common/flash.c:160:16: warning: variable 'size_b1' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Cc: Denis Peter Acked-by: Marek Vasut diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index 81d7271..d5b63c0 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -157,7 +157,7 @@ unsigned long flash_init (void) int i; #if !defined(CONFIG_PATI) - unsigned long size_b1,flashcr,size_reg; + unsigned long flashcr,size_reg; int mode; extern char version_string; char *p = &version_string; @@ -197,7 +197,6 @@ unsigned long flash_init (void) #if !defined(CONFIG_PATI) /* protect reset vector */ flash_info[0].protect[flash_info[0].sector_count-1] = 1; - size_b1 = 0 ; flash_info[0].size = size_b0; /* set up flash cs according to the size */ size_reg=(flash_info[0].size >>20); -- cgit v0.10.2 From e38cc2c7713c3a6f25b75317bb4ddcf290d33dfd Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:54 +0000 Subject: board/freescale/mpc8610hpcd/mpc8610hpcd.c: Fix GCC 4.6 build warning Fix: mpc8610hpcd.c: In function 'pci_init_board': mpc8610hpcd.c:238:15: warning: variable 'pordevsr' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Cc: Kumar Gala Acked-by: Kumar Gala diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 5b3b560..2bcd5e6 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -235,12 +235,11 @@ void pci_init_board(void) volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; struct fsl_pci_info pci_info; - u32 devdisr, pordevsr; + u32 devdisr; int first_free_busno; int pci_agent; devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); first_free_busno = fsl_pcie_init_board(0); -- cgit v0.10.2 From ad37ef1a85114467cb8749e0ee785c1f9966109b Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:55 +0000 Subject: arch/powerpc/cpu/mpc86xx/cpu.c: Fix GCC 4.6 build warning Fix: cpu.c: In function 'checkcpu': cpu.c:51:7: warning: variable 'ver' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Cc: Kumar Gala Acked-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c index ffcc8e6..d2c8c78 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu.c +++ b/arch/powerpc/cpu/mpc86xx/cpu.c @@ -48,7 +48,6 @@ checkcpu(void) { sys_info_t sysinfo; uint pvr, svr; - uint ver; uint major, minor; char buf1[32], buf2[32]; volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; @@ -57,7 +56,6 @@ checkcpu(void) uint msscr0 = mfspr(MSSCR0); svr = get_svr(); - ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr); @@ -77,7 +75,6 @@ checkcpu(void) puts("Core: "); pvr = get_pvr(); - ver = PVR_E600_VER(pvr); major = PVR_E600_MAJ(pvr); minor = PVR_E600_MIN(pvr); -- cgit v0.10.2 From 24b0da3aebb63d945cbdad79a587dc6f90b7bec5 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:56 +0000 Subject: board/sbc405/strataflash.c: Fix GCC 4.6 build warning Fix: strataflash.c: In function 'flash_write_cfiword': strataflash.c:673:11: warning: variable 'ctladdr' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Acked-by: Marek Vasut diff --git a/board/sbc405/strataflash.c b/board/sbc405/strataflash.c index e5863d6..b0d3c6c 100644 --- a/board/sbc405/strataflash.c +++ b/board/sbc405/strataflash.c @@ -670,14 +670,11 @@ static ulong flash_get_size (ulong base, int banknum) static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) { - cfiptr_t ctladdr; cfiptr_t cptr; int flag; - ctladdr.cp = flash_make_addr(info, 0, 0); cptr.cp = (uchar *)dest; - /* Check if Flash is (sufficiently) erased */ switch(info->portwidth) { case FLASH_CFI_8BIT: -- cgit v0.10.2 From f008b17f8c2995996b5d100b71f8851d6f74a136 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:57 +0000 Subject: board/emk/top860/top860.c: Fix GCC 4.6 build warning Fix: top860.c: In function 'initdram': top860.c:90:11: warning: variable 'j' set but not used [-Wunused-but-set-variable] Note: No attempts were made to convert this file completely to using I/O accessors. This is left as an exercise for the board maintainer. Signed-off-by: Wolfgang Denk Cc: Reinhard Meyer diff --git a/board/emk/top860/top860.c b/board/emk/top860/top860.c index 76f7a0c..4df7f0e 100644 --- a/board/emk/top860/top860.c +++ b/board/emk/top860/top860.c @@ -34,6 +34,7 @@ #include #include #include +#include /***************************************************************************** * UPM table for 60ns EDO RAM at 25 MHz bus/external clock @@ -87,7 +88,7 @@ phys_size_t initdram (int board_type) */ if ((ulong) initdram & 0xff000000) { volatile uint *addr1, *addr2; - uint i, j; + uint i; upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl, sizeof (edo_60ns_25MHz_tbl) / sizeof (uint)); @@ -100,8 +101,8 @@ phys_size_t initdram (int board_type) */ addr1 = (volatile uint *) 0; addr2 = (volatile uint *) 0x00400000; - for (i = 0, j = 0; i < 8; i++) - j = addr1[0]; + for (i = 0; i < 8; i++) + in_be32(addr1); /* * Now check whether we got 4MB or 16MB populated -- cgit v0.10.2