From 6768146aeff0bd67a68ec6e0438667d505971449 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Wed, 25 Nov 2015 09:09:20 -0200 Subject: cgtqmx6eval: Fix defconfig name After the conversion to SPL the defconfig was renamed, so adjust it. Signed-off-by: Otavio Salvador diff --git a/board/congatec/cgtqmx6eval/MAINTAINERS b/board/congatec/cgtqmx6eval/MAINTAINERS index c41ebf5..48c0889 100644 --- a/board/congatec/cgtqmx6eval/MAINTAINERS +++ b/board/congatec/cgtqmx6eval/MAINTAINERS @@ -3,4 +3,4 @@ M: Otavio Salvador S: Maintained F: board/congatec/cgtqmx6eval/ F: include/configs/cgtqmx6eval.h -F: configs/cgtqmx6qeval_defconfig +F: configs/cgtqmx6eval_defconfig -- cgit v0.10.2 From 29bc24ec4f9f159b3fdaf9c85cce89504a54782a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Nov 2015 16:18:02 -0200 Subject: mx6sxsabresd: Fix Ethernet PHY reset sequence MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is registered") Ethernet is no longer functional. This commit does not have an issue in itself, but it revelead a problem with the Ethernet initialization. Fix this by calling enable_fec_anatop_clock() earlier and also by adding a 10ms reset delay as recommended in the AR8031 datasheet. Suggested-by: Jörg Krause Signed-off-by: Fabio Estevam Reviewed-by: Stefano Babic diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 3ee4662..56dc020 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -150,11 +150,15 @@ static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int reg; + int reg, ret; /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + return ret; + imx_iomux_v3_setup_multiple_pads(phy_control_pads, ARRAY_SIZE(phy_control_pads)); @@ -163,14 +167,14 @@ static int setup_fec(void) /* Reset AR8031 PHY */ gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); - udelay(500); + mdelay(10); gpio_set_value(IMX_GPIO_NR(2, 7), 1); reg = readl(&anatop->pll_enet); reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; writel(reg, &anatop->pll_enet); - return enable_fec_anatop_clock(0, ENET_125MHZ); + return 0; } int board_eth_init(bd_t *bis) -- cgit v0.10.2 From 9f74ebe1e4138dde40bc6dcbc858276ec7f0c7b2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 29 Oct 2015 15:59:25 +0800 Subject: imx: mx7: enable CONFIG_FSL_CLK This commit "677f970bc62a661690b3431543d5a5d5e682ba70" introduce a new macro "CONFIG_FSL_CLK" that get_clocks() should not be limited by ESDHC. But that patch missed to enable it for i.MX7. THis patch enables CONFIG_FSL_CLK to let get_clocks work. Signed-off-by: Peng Fan Cc: Adrian Alonso Cc: Stefano Babic Cc: Fabio Estevam diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 870e12e..d507fb4 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -36,6 +36,8 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_FSL_CLK + #define CONFIG_LOADADDR 0x80800000 #define CONFIG_SYS_TEXT_BASE 0x87800000 -- cgit v0.10.2 From 0ff47e590bb50978f3cb397e6b04f82702bfe954 Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Sun, 29 Nov 2015 18:30:34 +0100 Subject: imx: mx6: add missing return value cc: Peng Fan Signed-off-by: Jeroen Hofstee Reviewed-by: Peng Fan Reviewed-by: Stefano Babic diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index d325191..64514b1 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -727,6 +727,8 @@ int enable_lcdif_clock(u32 base_addr) reg = readl(&imx_ccm->CCGR2); reg |= MXC_CCM_CCGR2_LCD_MASK; writel(reg, &imx_ccm->CCGR2); + + return 0; } #endif -- cgit v0.10.2 From 0c890879fe2a5731df7aee3dd38e455008fa9977 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 30 Nov 2015 16:04:51 +0800 Subject: imx: mx6: fix reg base address when runtime usage Should use parenthese to wrap the macro definition, otherwise we will encounter error like the following: " if (base_addr != LCDIF1_BASE_ADDR) { puts("Wrong LCD interface!\n"); return -EINVAL; } " Without this patch, we will always encounter "Wrong LCD interface". Signed-off-by: Peng Fan Cc: Stefano Babic Reviewed-by: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 2f068e5..f24525e 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -335,10 +335,10 @@ #include /* only for i.MX6SX/UL */ -#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \ - MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR) -#define LCDIF1_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL)) ? \ - MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR +#define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \ + MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) +#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \ + MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR) extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); -- cgit v0.10.2 From 1c2d4a50e9b2b81c8cbbfb6fd03e061ace37ebec Mon Sep 17 00:00:00 2001 From: Vagrant Cascadian Date: Wed, 25 Nov 2015 00:37:10 +0100 Subject: arm: novena: Switch novena to config_distro_bootcmd Switch Novena to distro bootcmd, so it can be used with debian easily. Signed-off-by: Vagrant Cascadian Signed-off-by: Marek Vasut Cc: Sean Cross Cc: Stefano Babic Tested-by: Vagrant Cascadian diff --git a/include/configs/novena.h b/include/configs/novena.h index 4b4f2d7..5f0a230 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -16,6 +16,7 @@ #define CONFIG_FIT #define CONFIG_KEYBOARD +#include #include "mx6_common.h" /* U-Boot Commands */ @@ -58,7 +59,7 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttymxc1,115200 " -#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run net_nfs" #define CONFIG_HOSTNAME novena /* Physical Memory Map */ @@ -190,6 +191,7 @@ #endif /* Extra U-Boot environment. */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -199,6 +201,11 @@ "rootdev=/dev/mmcblk0p2\0" \ "netdev=eth0\0" \ "kernel_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ + "pxefile_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ + "scriptaddr="__stringify(CONFIG_LOADADDR)"\0" \ + "ramdisk_addr_r=0x28000000\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdtfile=imx6q-novena.dtb\0" \ "addcons=" \ "setenv bootargs ${bootargs} " \ "console=${consdev},${baudrate}\0" \ @@ -242,5 +249,19 @@ "fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\ "fi ; " \ "fi\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(SATA, sata, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#else +#define CONFIG_EXTRA_ENV_SETTINGS +#endif /* CONFIG_SPL_BUILD */ #endif /* __CONFIG_H */ -- cgit v0.10.2 From 839479dda6b449d911d1d56c599f2a9538bb2215 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Oct 2015 18:06:00 +0800 Subject: imx: ddr: drop duplicated debug info Drop duplicated debug info for tcl. Signed-off-by: Peng Fan Cc: Stefano Babic diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 6b039e4..567ddc4 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -796,7 +796,6 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, debug("Rtt_wr=%d\n", sysinfo->rtt_wr); debug("Rtt_nom=%d\n", sysinfo->rtt_nom); debug("SRT=%d\n", ddr3_cfg->SRT); - debug("tcl=%d\n", tcl); debug("twr=%d\n", twr); /* -- cgit v0.10.2 From f0b5f23f32adfb790293c4f1722042026fa98416 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Fri, 4 Dec 2015 12:32:48 -0700 Subject: ARM: imx: fsl_esdhc: fix usage of low 4 bits of sysctl register The low four bits of the SYSCTL register are reserved on the USDHC controller on i.MX6 and i.MX7 processors, but are used for clocking operations on earlier models. Guard against their usage by hiding the bit mask macros on those processors. These bits are used to prevent glitches when changing clocks on i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7. >From the i.MX6DQ RM: To prevent possible glitch on the card clock, clear the FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS or DVS in System Control Register) or setting RSTA bit. Signed-off-by: Eric Nelson Reviewed-by: Fabio Estevam Reviewed-by: Stefano Babic Reviewed-by: Hector Palacios diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c5054d6..1ccc576 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -502,15 +502,22 @@ static void set_sysctl(struct mmc *mmc, uint clock) clk = (pre_div << 8) | (div << 4); +#ifdef CONFIG_FSL_USDHC + esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); +#else esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); +#endif esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); udelay(10000); - clk = SYSCTL_PEREN | SYSCTL_CKEN; +#ifdef CONFIG_FSL_USDHC + esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA); +#else + esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); +#endif - esdhc_setbits32(®s->sysctl, clk); } #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK @@ -585,7 +592,9 @@ static int esdhc_init(struct mmc *mmc) esdhc_write32(®s->scr, 0x00000040); #endif +#ifndef CONFIG_FSL_USDHC esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); +#endif /* Set the initial clock speed */ mmc_set_clock(mmc, 400000); @@ -657,8 +666,10 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) /* First reset the eSDHC controller */ esdhc_reset(regs); +#ifndef CONFIG_FSL_USDHC esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); +#endif writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); memset(&cfg->cfg, 0, sizeof(cfg->cfg)); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index aa1b4cf..073048f 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -25,10 +25,12 @@ #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 #define SYSCTL_CLOCK_MASK 0x0000fff0 +#if !defined(CONFIG_FSL_USDHC) #define SYSCTL_CKEN 0x00000008 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 +#endif #define SYSCTL_RSTA 0x01000000 #define SYSCTL_RSTC 0x02000000 #define SYSCTL_RSTD 0x04000000 -- cgit v0.10.2 From 434afa809e91bbf67e003df8daf0e2f39c48ce59 Mon Sep 17 00:00:00 2001 From: Maximilian Schwerin Date: Wed, 25 Nov 2015 14:08:00 +0100 Subject: serial_mxc: Fix setup of UARTx_UFCR register This patch writes the default values for TXTL and RXTL to UARTx_UFCR. Without this patch some older kernel versions crash as UARTx_UFCR was not always correctly initialized. Signed-off-by: Maximilian Schwerin diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index d6cf1d8..51485c0 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -75,6 +75,7 @@ #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */ #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ #define USR1_RTSS (1<<14) /* RTS pin status */ @@ -135,6 +136,10 @@ DECLARE_GLOBAL_DATA_PTR; +#define TXTL 2 /* reset default */ +#define RXTL 1 /* reset default */ +#define RFDIV 4 /* divide input clock by 2 */ + static void mxc_serial_setbrg(void) { u32 clk = imx_get_uartclk(); @@ -142,7 +147,9 @@ static void mxc_serial_setbrg(void) if (!gd->baudrate) gd->baudrate = CONFIG_BAUDRATE; - __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF) + | (TXTL << UFCR_TXTL_SHF) + | (RXTL << UFCR_RXTL_SHF); __REG(UART_PHYS + UBIR) = 0xf; __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); -- cgit v0.10.2 From 843a3e5893a713a3df752d30d31861d5b03ad75c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?M=C3=A5ns=20Rullg=C3=A5rd?= Date: Tue, 8 Dec 2015 15:38:45 +0000 Subject: net: fec_mxc: configure MDIO hold time If the host clock frequency is higher than 100 MHz, the MDIO hold time needs to be increased from its current setting of one cycle in order to meet the specified minium of 10 ns. Writing an appropriate value to the HOLDTIME field of the MII_SPEED register achieves this. Comment copied from Linux kernel. Signed-off-by: Mans Rullgard Reviewed-by: Eric Nelson diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 79f6737..798cc16 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -131,13 +131,25 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. + * + * The i.MX28 and i.MX6 types have another field in the MSCR (aka + * MII_SPEED) register that defines the MDIO output hold time. Earlier + * versions are RAZ there, so just ignore the difference and write the + * register always. + * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. + * HOLDTIME + 1 is the number of clk cycles the fec is holding the + * output. + * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). + * Given that ceil(clkrate / 5000000) <= 64, the calculation for + * holdtime cannot result in a value greater than 3. */ - register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000); + u32 pclk = imx_get_fecclk(); + u32 speed = DIV_ROUND_UP(pclk, 5000000); + u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1; #ifdef FEC_QUIRK_ENET_MAC speed--; #endif - speed <<= 1; - writel(speed, ð->mii_speed); + writel(speed << 1 | hold << 8, ð->mii_speed); debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); } -- cgit v0.10.2 From 845a57b4de972aefb21bf7f13b23d472bccb6afb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?M=C3=A5ns=20Rullg=C3=A5rd?= Date: Tue, 8 Dec 2015 15:38:46 +0000 Subject: net: fec_mxc: unregister mdio bus on probe error If fecmxc_initialize_multi() fails, it frees but does not unregister the mdio bus, causing subsequent uses of the "mii" command to crash. Fix this by adding mdio_unregister() calls where needed. Signed-off-by: Mans Rullgard Reviewed-by: Eric Nelson diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 798cc16..3340dd2 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1109,6 +1109,7 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) #ifdef CONFIG_PHYLIB phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII); if (!phydev) { + mdio_unregister(bus); free(bus); return -ENOMEM; } @@ -1120,6 +1121,7 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) #ifdef CONFIG_PHYLIB free(phydev); #endif + mdio_unregister(bus); free(bus); } return ret; -- cgit v0.10.2 From a1ed155298eeb29000d9b1033be094c0f7c45212 Mon Sep 17 00:00:00 2001 From: Michael Schanz Date: Thu, 10 Dec 2015 09:58:35 +0100 Subject: cgtqmx6eval: fix pad configuration for SPI bus Use the macro SETUP_IOMUX_PAD(...) rather than imx_iomux_v3_setup_multiple_pads(...) in order to setup the pin configuration for ECSPI1. ARRAY_SIZE(pads) provides the wrong size for imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)) in case of MX6QDL. In the particular case, the content of GPR12 is overwritten and the IPG/AHB/ATB/ATP clocks are deactivated. Therefore, the connection to the system via JTAG is not possible anymore. Furthermore, kernel version 3.0.35 hangs during bootprocess in the function etm_init(). Signed-off-by: Michael Schanz Acked-by: Otavio Salvador diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 5fd526d..225de7c 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -404,7 +404,7 @@ static void setup_iomux_uart(void) #ifdef CONFIG_MXC_SPI static void setup_spi(void) { - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + SETUP_IOMUX_PADS(ecspi1_pads); gpio_direction_output(IMX_GPIO_NR(3, 19), 0); } #endif -- cgit v0.10.2 From fe21eaf92de4d78413e69c95ba23a869e17454f7 Mon Sep 17 00:00:00 2001 From: Michael Heimpold Date: Sun, 13 Dec 2015 12:08:37 +0100 Subject: ARM: mxs: allow boards to select DC-DC switching clock source For some board designs, it might be useful to switch the DC-DC clock source to something else rather the default 24 MHz, e.g. for EMI reasons. For this, override the mxs_power_setup_dcdc_clocksource function in your board support files. Example: void mxs_power_setup_dcdc_clocksource(void) { mxs_power_switch_dcdc_clocksource(POWER_MISC_FREQSEL_20MHZ); } Signed-off-by: Michael Heimpold Cc: Marek Vasut Cc: Otavio Salvador Cc: Fabio Estevam Acked-by: Marek Vasut diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 1972de8..1ec8e2b 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -248,6 +248,39 @@ static void mxs_power_setup_5v_detect(void) } /** + * mxs_power_switch_dcdc_clocksource() - Switch PLL clock for DC-DC converters + * @freqsel: One of the POWER_MISC_FREQSEL_xxx defines to select the clock + * + * This function configures and then enables an alternative PLL clock source + * for the DC-DC converters. + */ +void mxs_power_switch_dcdc_clocksource(uint32_t freqsel) +{ + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; + + /* Select clocksource for DC-DC converters */ + clrsetbits_le32(&power_regs->hw_power_misc, + POWER_MISC_FREQSEL_MASK, + freqsel); + setbits_le32(&power_regs->hw_power_misc, + POWER_MISC_SEL_PLLCLK); +} + +/** + * mxs_power_setup_dcdc_clocksource() - Setup PLL clock source for DC-DC converters + * + * Normally, there is no need to switch DC-DC clocksource. This is the reason, + * why this function is a stub and does nothing. However, boards can implement + * this function when required and call mxs_power_switch_dcdc_clocksource() to + * switch to an alternative clock source. + */ +__weak void mxs_power_setup_dcdc_clocksource(void) +{ + debug("SPL: Using default DC-DC clocksource\n"); +} + +/** * mxs_src_power_init() - Preconfigure the power block * * This function configures reasonable values for the DC-DC control loop @@ -872,6 +905,7 @@ static void mxs_power_configure_power_source(void) debug("SPL: Configuring power source\n"); + mxs_power_setup_dcdc_clocksource(); mxs_src_power_init(); if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 20ff101..f2b075e 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -25,6 +25,8 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)); void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, const iomux_cfg_t *iomux_setup, const unsigned int iomux_size); + +void mxs_power_switch_dcdc_clocksource(uint32_t freqsel); #endif struct mxs_pair { -- cgit v0.10.2 From 40f4839ce12adfc0223d6e3035cf9c3a4754a0ec Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 11 Dec 2015 17:30:42 +0100 Subject: imx_common: check for Serial Downloader in spl_boot_device Check for bmode before reading the boot device to check if a serial downloader is started, and returns UART if the serial downloader is set, letting SPL to wait for an image if CONFIG_SPL_YMODEM_SUPPORT is set. This allows to load again a SPL based board with imx_usb_loader together with a tool such as kermit. Signed-off-by: Stefano Babic CC: Tim Harvey CC: Fabio Estevam CC: Eric Nelson Reviewed-by: Eric Nelson Tested-by: Eric Nelson diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c index ac6e40e..caa45cf 100644 --- a/arch/arm/imx-common/spl.c +++ b/arch/arm/imx-common/spl.c @@ -20,7 +20,15 @@ u32 spl_boot_device(void) struct src *psrc = (struct src *)SRC_BASE_ADDR; unsigned int gpr10_boot = readl(&psrc->gpr10) & (1 << 28); unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1); + unsigned int bmode = readl(&psrc->sbmr2); + /* + * Check for BMODE if serial downloader is enabled + * BOOT_MODE - see IMX6DQRM Table 8-1 + */ + if ((((bmode >> 24) & 0x03) == 0x01) || /* Serial Downloader */ + (gpr10_boot && (reg == 1))) + return BOOT_DEVICE_UART; /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */ switch ((reg & 0x000000FF) >> 4) { /* EIM: See 8.5.1, Table 8-9 */ diff --git a/doc/README.imx6 b/doc/README.imx6 index 437af2f..e26ab71 100644 --- a/doc/README.imx6 +++ b/doc/README.imx6 @@ -84,3 +84,54 @@ Address: Reading bank 4: Word 0x00000002: 9f027772 00000004 + +2. Using imx_usb_loader for first install with SPL +-------------------------------------------------- + +imx_usb_loader is a very nice tool by BoundaryDevice that +allow to install U-Boot without a JTAG debugger, using +the USB boot mode as described in the manual. It is +a replacement for Freescale's MFGTOOLS. + +The sources can be found here: + + https://github.com/boundarydevices/imx_usb_loader.git + +Booting in USB mode, the i.MX6 announces itself to the Linux Host as: + +Bus 001 Device 111: ID 15a2:0061 Freescale Semiconductor, Inc. + +imx_usb_loader is able to download a single file (u-boot.imx) +to the board. For boards without SPL support, it is enough to +issue the command: + + sudo ../imx_usb_loader/imx_usb -v u-boot.imx + +Getting U-Boot when SPL support is active, it requires +two downloads. imx_usb_loader downloads the SPL into +OCRAM and starts it. SPL will check for a valid u-boot.img, and +because it is not found, it will wait for it using the y-modem +protocol via the console. + +A first install is then possible by combining imx_usb_loader with +another tool such as kermit. + +sudo ../imx_usb_loader/imx_usb -v SPL +kermit kermit_uboot + +and kermit_uboot contains something like this (set line should be adjusted): + +set line /dev/ttyUSB1 +set speed 115200 +SET CARRIER-WATCH OFF +set flow-control none +set handshake none +set prefixing all +set file type bin +set protocol ymodem +send u-boot.img +c + +The last "c" command tells kermit (from ckermit package in most distros) +to switch from command line mode to communication mode, and when the +script is finished, the U-Boot prompt is shown in the same shell. -- cgit v0.10.2 From aee3fddb677d86a131d9ac7bac2251f9a6ab2975 Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Fri, 18 Dec 2015 17:38:01 +0800 Subject: i2c: mxc: add a condition in case the parameter is NULL This could avoid executing the code that only applies to i.MX platforms. The bus_i2c_init() is called before relocation and will assgin value to a static variable. If U-Boot is then still running in a flash device, it's theoretically not allowed to write data to flash without an erasing operation. For i.MX platforms, the U-Boot is always running in DDR. Actually it causes asynchronous error when the ARM64 system error report is enabled and the flash write protect is set. Signed-off-by: Gong Qianyu Reviewed-by: Heiko Schocher diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index fa4c82f..b2d15c9 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -581,8 +581,16 @@ void bus_i2c_init(int index, int speed, int unused, return; } - mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn; - mxc_i2c_buses[index].idle_bus_data = idle_bus_data; + /* + * Warning: Be careful to allow the assignment to a static + * variable here. This function could be called while U-Boot is + * still running in flash memory. So such assignment is equal + * to write data to flash without erasing. + */ + if (idle_bus_fn) + mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn; + if (idle_bus_data) + mxc_i2c_buses[index].idle_bus_data = idle_bus_data; ret = enable_i2c_clk(1, index); if (ret < 0) { -- cgit v0.10.2 From ccf4326bac0371774265be0a8b13c150b445e703 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 15 Dec 2015 16:27:18 +0800 Subject: imx: mx6qsabreauto: support lvds display Move setup_display from board_early_init_f to board_init. Add more clock settings. Add blacklight iomux setting. Add display_info_t info for the lvds screen. Signed-off-by: Peng Fan Cc: Fabio Estevam Cc: Stefano Babic diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 7c0e90a..c2e9c57 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -412,14 +412,44 @@ u32 get_board_rev(void) } #if defined(CONFIG_VIDEO_IPUV3) +static void disable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + clrbits_le32(&iomux->gpr[2], + IOMUXC_GPR2_LVDS_CH0_MODE_MASK | + IOMUXC_GPR2_LVDS_CH1_MODE_MASK); +} + static void do_enable_hdmi(struct display_info_t const *dev) { + disable_lvds(dev); imx_enable_hdmi_phy(); } struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = NULL, + .enable = NULL, + .mode = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, .pixfmt = IPU_PIX_FMT_RGB24, .detect = detect_hdmi, .enable = do_enable_hdmi, @@ -440,18 +470,69 @@ struct display_info_t const displays[] = {{ } } }; size_t display_count = ARRAY_SIZE(displays); +iomux_v3_cfg_t const backlight_pads[] = { + MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_backlight(void) +{ + gpio_direction_output(IMX_GPIO_NR(2, 9), 1); + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); +} + static void setup_display(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; int reg; + setup_iomux_backlight(); enable_ipu_clock(); imx_setup_hdmi(); + /* Turn on LDB_DI0 and LDB_DI1 clocks */ + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | + MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | + (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + reg = readl(&mxc_ccm->chsccdr); reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 | + IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | + IOMUXC_GPR3_HDMI_MUX_CTL_MASK); + reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) | + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); } #endif /* CONFIG_VIDEO_IPUV3 */ @@ -467,9 +548,6 @@ int overwrite_console(void) int board_early_init_f(void) { setup_iomux_uart(); -#ifdef CONFIG_VIDEO_IPUV3 - setup_display(); -#endif #ifdef CONFIG_NAND_MXS setup_gpmi_nand(); @@ -494,6 +572,9 @@ int board_init(void) gpio_direction_output(IMX_GPIO_NR(1, 15), 1); imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp)); +#ifdef CONFIG_VIDEO_IPUV3 + setup_display(); +#endif setup_iomux_eimnor(); return 0; } -- cgit v0.10.2