From 7922a2d479b6cdce853b853b80d94675b955a66a Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Fri, 13 Jun 2014 17:00:56 +0900 Subject: Revert "exynos: Enable PSHOLD in SPL" This reverts commit eb0dd9986c3883820ff888c3738b013c0a7d918c. diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c index dcc270f..83e1dcf 100644 --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c @@ -49,8 +49,6 @@ int do_lowlevel_init(void) arch_cpu_init(); - set_ps_hold_ctrl(); - reset_status = get_reset_status(); switch (reset_status) { -- cgit v0.10.2 From cfde7588d8ad22560e2328574a4f415642170b92 Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Mon, 26 May 2014 19:17:03 +0530 Subject: Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_init Passing fewer arguments is better and mem_iv_size is never used. Let's keep only one argument and make it cleaner. Signed-off-by: Hatim Ali Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c b/arch/arm/cpu/armv7/exynos/dmc_common.c index cca925e..9b6ee69 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_common.c +++ b/arch/arm/cpu/armv7/exynos/dmc_common.c @@ -162,7 +162,7 @@ void mem_ctrl_init(int reset) /* If there are any other memory variant, add their init call below */ if (param->mem_type == DDR_MODE_DDR3) { - ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset); + ret = ddr3_mem_ctrl_init(mem, reset); if (ret) { /* will hang if failed to init memory control */ while (1) diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 487e6f4..4481ab4 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -28,8 +28,7 @@ static void reset_phy_ctrl(void) writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); } -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int reset) +int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) { unsigned int val; struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; @@ -221,8 +220,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, #endif #ifdef CONFIG_EXYNOS5420 -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int reset) +int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) { struct exynos5420_clock *clk = (struct exynos5420_clock *)samsung_get_base_clock(); @@ -244,7 +242,6 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc(); tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc() + DMC_OFFSET); - /* Enable PAUSE for DREX */ setbits_le32(&clk->pause, ENABLE_BIT); diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 53b0ace..314d6f4 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -890,16 +890,11 @@ enum { /* * Memory variant specific initialization code for DDR3 * - * @param mem Memory timings for this memory type. - * @param mem_iv_size Memory interleaving size is a configurable parameter - * which the DMC uses to decide how to split a memory - * chunk into smaller chunks to support concurrent - * accesses; may vary across boards. + * @param mem Memory timings for this memory type. * @param reset Reset DDR PHY during initialization. * @return 0 if ok, SETUP_ERR_... if there is a problem */ -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int reset); +int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset); /* Memory variant specific initialization code for LPDDR3 */ void lpddr3_mem_ctrl_init(void); -- cgit v0.10.2 From aacdd79095b0a7c258a76e4fdfc133af16b07dc0 Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Mon, 26 May 2014 19:18:06 +0530 Subject: Exynos5420: Remove code for enabling read leveling This patch intends to remove all code which enables hardware read leveling. All characterization environments may not cope up with h/w read leveling enabled, so we must disable this. Also, disabling h/w read leveling improves the MIF LVcc value (LVcc value is the value at which DDR will fail to work properly). Improving LVcc means we have enough voltage margin for MIF. When h/w leveling is enabled, we have almost zero volatge margin. Signed-off-by: Alim Akhtar Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 4481ab4..1d6048c 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -519,77 +519,6 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) &drex1->directcmd); } - if (mem->read_leveling_enable) { - /* Set Read DQ Calibration */ - val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4; - for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &drex0->directcmd); - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &drex1->directcmd); - } - - val = readl(&phy0_ctrl->phy_con1); - val |= READ_LEVELLING_DDR3; - writel(val, &phy0_ctrl->phy_con1); - val = readl(&phy1_ctrl->phy_con1); - val |= READ_LEVELLING_DDR3; - writel(val, &phy1_ctrl->phy_con1); - - val = readl(&phy0_ctrl->phy_con2); - val |= (RDLVL_EN | RDLVL_INCR_ADJ); - writel(val, &phy0_ctrl->phy_con2); - val = readl(&phy1_ctrl->phy_con2); - val |= (RDLVL_EN | RDLVL_INCR_ADJ); - writel(val, &phy1_ctrl->phy_con2); - - setbits_le32(&drex0->rdlvl_config, - CTRL_RDLVL_DATA_ENABLE); - i = TIMEOUT; - while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) - != RDLVL_COMPLETE_CHO) && (i > 0)) { - /* - * TODO(waihong): Comment on how long this take - * to timeout - */ - sdelay(100); - i--; - } - if (!i) - return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; - - clrbits_le32(&drex0->rdlvl_config, - CTRL_RDLVL_DATA_ENABLE); - setbits_le32(&drex1->rdlvl_config, - CTRL_RDLVL_DATA_ENABLE); - i = TIMEOUT; - while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) - != RDLVL_COMPLETE_CHO) && (i > 0)) { - /* - * TODO(waihong): Comment on how long this take - * to timeout - */ - sdelay(100); - i--; - } - if (!i) - return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; - - clrbits_le32(&drex1->rdlvl_config, - CTRL_RDLVL_DATA_ENABLE); - - val = (0x3 << DIRECT_CMD_BANK_SHIFT); - for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &drex0->directcmd); - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &drex1->directcmd); - } - - update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3); - update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3); - } - /* Common Settings for Leveling */ val = PHY_CON12_RESET_VAL; writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12); -- cgit v0.10.2 From c9334fcda90652e2f8c49f4517b728ebc6f5f623 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Mon, 26 May 2014 19:19:05 +0530 Subject: DMC: exynos5420: Gate CLKM to when reading PHY_CON13 when CLKM is running. If we stop CLKM when sampling it the glitches all go away, so we'll do that as per Samsung suggestion. We also check the "is it locked" bits of PHY_CON13 and loop until they show the the value sampled actually represents a locked value. It doesn't appear that the glitching and "is it locked" are related, but it seems wise to wait until the PHY tells us the value is good before we use it. In practice we will not loop more than a couple times (and usually won't loop at all). Signed-off-by: Doug Anderson Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 1d6048c..13003b8 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -230,6 +230,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) struct exynos5420_dmc *drex0, *drex1; struct exynos5420_tzasc *tzasc0, *tzasc1; uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1; + uint32_t lock0_info, lock1_info; int chip; int i; @@ -391,7 +392,41 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) */ dmc_config_mrs(mem, &drex0->directcmd); dmc_config_mrs(mem, &drex1->directcmd); - } else { + } + + /* + * Get PHY_CON13 from both phys. Gate CLKM around reading since + * PHY_CON13 is glitchy when CLKM is running. We're paranoid and + * wait until we get a "fine lock", though a coarse lock is probably + * OK (we only use the coarse numbers below). We try to gate the + * clock for as short a time as possible in case SDRAM is somehow + * sensitive. sdelay(10) in the loop is arbitrary to make sure + * there is some time for PHY_CON13 to get updated. In practice + * no delay appears to be needed. + */ + val = readl(&clk->gate_bus_cdrex); + while (true) { + writel(val & ~0x1, &clk->gate_bus_cdrex); + lock0_info = readl(&phy0_ctrl->phy_con13); + writel(val, &clk->gate_bus_cdrex); + + if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED) + break; + + sdelay(10); + } + while (true) { + writel(val & ~0x2, &clk->gate_bus_cdrex); + lock1_info = readl(&phy1_ctrl->phy_con13); + writel(val, &clk->gate_bus_cdrex); + + if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED) + break; + + sdelay(10); + } + + if (!reset) { /* * During Suspend-Resume & S/W-Reset, as soon as PMU releases * pad retention, CKE goes high. This causes memory contents @@ -442,15 +477,13 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); writel(val, &phy1_ctrl->phy_con1); - n_lock_r = readl(&phy0_ctrl->phy_con13); - n_lock_w_phy0 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2; + n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2; n_lock_r = readl(&phy0_ctrl->phy_con12); n_lock_r &= ~CTRL_DLL_ON; n_lock_r |= n_lock_w_phy0; writel(n_lock_r, &phy0_ctrl->phy_con12); - n_lock_r = readl(&phy1_ctrl->phy_con13); - n_lock_w_phy1 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2; + n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2; n_lock_r = readl(&phy1_ctrl->phy_con12); n_lock_r &= ~CTRL_DLL_ON; n_lock_r |= n_lock_w_phy1; diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 314d6f4..d415c91 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -284,6 +284,7 @@ #define CTRL_DLL_ON (1 << 5) #define CTRL_FORCE_MASK (0x7F << 8) #define CTRL_LOCK_COARSE_MASK (0x7F << 10) +#define CTRL_FINE_LOCKED 0x7 #define CTRL_OFFSETD_RESET_VAL 0x8 #define CTRL_OFFSETD_VAL 0x7F -- cgit v0.10.2 From ed32522fe048f9edcb3269c8d5af79c6e8c6daea Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Mon, 26 May 2014 19:20:08 +0530 Subject: Exynos5420: DMC: Add software read leveling Sometimes Read DQ and DQS are not in phase. Since, this phase shift differs from board to board, we need to calibrate it at DRAM init phase, that's read DQ calibration. This patch adds SW Read DQ calibration routine to compensate this skew. Signed-off-by: Alim Akhtar Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 13003b8..b86dd2d 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -6,6 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include @@ -16,7 +17,11 @@ #include "exynos5_setup.h" #include "clock_init.h" -#define TIMEOUT 10000 +#define TIMEOUT_US 10000 +#define NUM_BYTE_LANES 4 +#define DEFAULT_DQS 8 +#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ + || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0) #ifdef CONFIG_EXYNOS5250 static void reset_phy_ctrl(void) @@ -176,7 +181,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) writel(val, &phy1_ctrl->phy_con1); writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config); - i = TIMEOUT; + i = TIMEOUT_US; while ((readl(&dmc->phystatus) & (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) != (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) { @@ -220,6 +225,219 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) #endif #ifdef CONFIG_EXYNOS5420 +/** + * RAM address to use in the test. + * + * We'll use 4 words at this address and 4 at this address + 0x80 (Ares + * interleaves channels every 128 bytes). This will allow us to evaluate all of + * the chips in a 1 chip per channel (2GB) system and half the chips in a 2 + * chip per channel (4GB) system. We can't test the 2nd chip since we need to + * do tests before the 2nd chip is enabled. Looking at the 2nd chip isn't + * critical because the 1st and 2nd chip have very similar timings (they'd + * better have similar timings, since there's only a single adjustment that is + * shared by both chips). + */ +const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE; + +/* Test pattern with which RAM will be tested */ +static const unsigned int test_pattern[] = { + 0x5a5a5a5a, + 0xa5a5a5a5, + 0xf0f0f0f0, + 0x0f0f0f0f, +}; + +/** + * This function is a test vector for sw read leveling, + * it compares the read data with the written data. + * + * @param ch DMC channel number + * @param byte_lane which DQS byte offset, + * possible values are 0,1,2,3 + * @return TRUE if memory was good, FALSE if not. + */ +static bool dmc_valid_window_test_vector(int ch, int byte_lane) +{ + unsigned int read_data; + unsigned int mask; + int i; + + mask = 0xFF << (8 * byte_lane); + + for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { + read_data = readl(test_addr + i * 4 + ch * 0x80); + if ((read_data & mask) != (test_pattern[i] & mask)) + return false; + } + + return true; +} + +/** + * This function returns current read offset value. + * + * @param phy_ctrl pointer to the current phy controller + */ +static unsigned int dmc_get_read_offset_value(struct exynos5420_phy_control + *phy_ctrl) +{ + return readl(&phy_ctrl->phy_con4); +} + +/** + * This function performs resync, so that slave DLL is updated. + * + * @param phy_ctrl pointer to the current phy controller + */ +static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl) +{ + setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); + clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); +} + +/** + * This function sets read offset value register with 'offset'. + * + * ...we also call call ddr_phy_set_do_resync(). + * + * @param phy_ctrl pointer to the current phy controller + * @param offset offset to read DQS + */ +static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl, + unsigned int offset) +{ + writel(offset, &phy_ctrl->phy_con4); + ddr_phy_set_do_resync(phy_ctrl); +} + +/** + * Convert a 2s complement byte to a byte with a sign bit. + * + * NOTE: you shouldn't use normal math on the number returned by this function. + * As an example, -10 = 0xf6. After this function -10 = 0x8a. If you wanted + * to do math and get the average of 10 and -10 (should be 0): + * 0x8a + 0xa = 0x94 (-108) + * 0x94 / 2 = 0xca (-54) + * ...and 0xca = sign bit plus 0x4a, or -74 + * + * Also note that you lose the ability to represent -128 since there are two + * representations of 0. + * + * @param b The byte to convert in two's complement. + * @return The 7-bit value + sign bit. + */ + +unsigned char make_signed_byte(signed char b) +{ + if (b < 0) + return 0x80 | -b; + else + return b; +} + +/** + * Test various shifts starting at 'start' and going to 'end'. + * + * For each byte lane, we'll walk through shift starting at 'start' and going + * to 'end' (inclusive). When we are finally able to read the test pattern + * we'll store the value in the results array. + * + * @param phy_ctrl pointer to the current phy controller + * @param ch channel number + * @param start the start shift. -127 to 127 + * @param end the end shift. -127 to 127 + * @param results we'll store results for each byte lane. + */ + +void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch, + int start, int end, int results[NUM_BYTE_LANES]) +{ + int incr = (start < end) ? 1 : -1; + int byte_lane; + + for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) { + int shift; + + dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4); + results[byte_lane] = DEFAULT_DQS; + + for (shift = start; shift != (end + incr); shift += incr) { + unsigned int byte_offsetr; + unsigned int offsetr; + + byte_offsetr = make_signed_byte(shift); + + offsetr = dmc_get_read_offset_value(phy_ctrl); + offsetr &= ~(0xFF << (8 * byte_lane)); + offsetr |= (byte_offsetr << (8 * byte_lane)); + dmc_set_read_offset_value(phy_ctrl, offsetr); + + if (dmc_valid_window_test_vector(ch, byte_lane)) { + results[byte_lane] = shift; + break; + } + } + } +} + +/** + * This function performs SW read leveling to compensate DQ-DQS skew at + * receiver it first finds the optimal read offset value on each DQS + * then applies the value to PHY. + * + * Read offset value has its min margin and max margin. If read offset + * value exceeds its min or max margin, read data will have corruption. + * To avoid this we are doing sw read leveling. + * + * SW read leveling is: + * 1> Finding offset value's left_limit and right_limit + * 2> and calculate its center value + * 3> finally programs that center value to PHY + * 4> then PHY gets its optimal offset value. + * + * @param phy_ctrl pointer to the current phy controller + * @param ch channel number + * @param coarse_lock_val The coarse lock value read from PHY_CON13. + * (0 - 0x7f) + */ +static void software_find_read_offset(struct exynos5420_phy_control *phy_ctrl, + int ch, unsigned int coarse_lock_val) +{ + unsigned int offsetr_cent; + int byte_lane; + int left_limit; + int right_limit; + int left[NUM_BYTE_LANES]; + int right[NUM_BYTE_LANES]; + int i; + + /* Fill the memory with test patterns */ + for (i = 0; i < ARRAY_SIZE(test_pattern); i++) + writel(test_pattern[i], test_addr + i * 4 + ch * 0x80); + + /* Figure out the limits we'll test with; keep -127 < limit < 127 */ + left_limit = DEFAULT_DQS - coarse_lock_val; + right_limit = DEFAULT_DQS + coarse_lock_val; + if (right_limit > 127) + right_limit = 127; + + /* Fill in the location where reads were OK from left and right */ + test_shifts(phy_ctrl, ch, left_limit, right_limit, left); + test_shifts(phy_ctrl, ch, right_limit, left_limit, right); + + /* Make a final value by taking the center between the left and right */ + offsetr_cent = 0; + for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) { + int temp_center; + unsigned int vmwc; + + temp_center = (left[byte_lane] + right[byte_lane]) / 2; + vmwc = make_signed_byte(temp_center); + offsetr_cent |= vmwc << (8 * byte_lane); + } + dmc_set_read_offset_value(phy_ctrl, offsetr_cent); +} + int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) { struct exynos5420_clock *clk = @@ -229,6 +447,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl; struct exynos5420_dmc *drex0, *drex1; struct exynos5420_tzasc *tzasc0, *tzasc1; + struct exynos5_power *pmu; uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1; uint32_t lock0_info, lock1_info; int chip; @@ -243,6 +462,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc(); tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc() + DMC_OFFSET); + pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE; + /* Enable PAUSE for DREX */ setbits_le32(&clk->pause, ENABLE_BIT); @@ -512,7 +733,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) writel(val, &phy1_ctrl->phy_con1); writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config); - i = TIMEOUT; + i = TIMEOUT_US; while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) != RDLVL_COMPLETE_CHO) && (i > 0)) { /* @@ -527,7 +748,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config); writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config); - i = TIMEOUT; + i = TIMEOUT_US; while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) != RDLVL_COMPLETE_CHO) && (i > 0)) { /* @@ -561,6 +782,27 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN); } + /* + * Do software read leveling + * + * Do this before we turn on auto refresh since the auto refresh can + * be in conflict with the resync operation that's part of setting + * read leveling. + */ + if (!reset) { + /* restore calibrated value after resume */ + dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1)); + dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2)); + } else { + software_find_read_offset(phy0_ctrl, 0, + CTRL_LOCK_COARSE(lock0_info)); + software_find_read_offset(phy1_ctrl, 1, + CTRL_LOCK_COARSE(lock1_info)); + /* save calibrated value to restore after resume */ + writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1); + writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2); + } + /* Send PALL command */ dmc_config_prech(mem, &drex0->directcmd); dmc_config_prech(mem, &drex1->directcmd); diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index d415c91..d91e585 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -282,8 +282,11 @@ #define PHY_CON12_VAL 0x10107F50 #define CTRL_START (1 << 6) #define CTRL_DLL_ON (1 << 5) +#define CTRL_LOCK_COARSE_OFFSET 10 +#define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET) +#define CTRL_LOCK_COARSE(x) (((x) & CTRL_LOCK_COARSE_MASK) >> \ + CTRL_LOCK_COARSE_OFFSET) #define CTRL_FORCE_MASK (0x7F << 8) -#define CTRL_LOCK_COARSE_MASK (0x7F << 10) #define CTRL_FINE_LOCKED 0x7 #define CTRL_OFFSETD_RESET_VAL 0x8 diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index d78536d..ec3f9b6 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -467,6 +467,9 @@ enum mem_manuf { /* PHY_CON1 register fields */ #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 +/* PHY_CON4 rgister fields */ +#define PHY_CON10_CTRL_OFFSETR3 (1 << 24) + /* PHY_CON12 register fields */ #define PHY_CON12_CTRL_START_POINT_SHIFT 24 #define PHY_CON12_CTRL_INC_SHIFT 16 diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index a4b41ad..4f2447b 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -906,8 +906,8 @@ struct exynos5420_power { unsigned int sysip_dat3; unsigned char res11[0xe0]; unsigned int pmu_spare0; - unsigned int pmu_spare1; - unsigned int pmu_spare2; + unsigned int pmu_spare1; /* Store PHY0_CON4 for read leveling */ + unsigned int pmu_spare2; /* Store PHY1_CON4 for read leveling */ unsigned int pmu_spare3; unsigned char res12[0x4]; unsigned int cg_status0; -- cgit v0.10.2 From 0fabb6aff1ab2496f6a84e068a30583eecad7a73 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Majewski?= Date: Mon, 9 Jun 2014 14:02:16 +0200 Subject: FIX: config: goni: Change goni configuration to use Tizen's THOR downlodader Modify GONI's configuration to utilize THOR downloader. Signed-off-by: Lukasz Majewski Signed-off-by: Minkyu Kang diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index fce1716..c92e94c 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -79,10 +79,18 @@ #define CONFIG_USBDOWNLOAD_GADGET #define CONFIG_DFU_FUNCTION #define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* TIZEN THOR downloader support */ +#define CONFIG_CMD_THOR_DOWNLOAD +#define CONFIG_THOR_FUNCTION /* USB Samsung's IDs */ #define CONFIG_G_DNL_VENDOR_NUM 0x04E8 #define CONFIG_G_DNL_PRODUCT_NUM 0x6601 +#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM +#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D #define CONFIG_G_DNL_MANUFACTURER "Samsung" /* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ -- cgit v0.10.2 From 34ecd69445e362064618e64f43a3066e679dda7a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Majewski?= Date: Mon, 9 Jun 2014 11:36:07 +0200 Subject: FIX: config: goni: Change goni configuration to store envs at eMMC Up till now goni's configuration has been stored at OneNAND. Since u-boot itself is now stored at eMMC it is more handy to store envs there as well. Signed-off-by: Lukasz Majewski Signed-off-by: Minkyu Kang diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index c92e94c..6e795bf 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -228,9 +228,12 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ /* FLASH and environment organization */ -#define CONFIG_ENV_IS_IN_ONENAND 1 -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB, 0x40000 */ -#define CONFIG_ENV_ADDR (1 << 20) /* 1 MB, 0x100000 */ +#define CONFIG_MMC_DEFAULT_DEV 0 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ +#define CONFIG_ENV_OVERWRITE #define CONFIG_USE_ONENAND_BOARD_INIT #define CONFIG_SAMSUNG_ONENAND 1 -- cgit v0.10.2 From f8caed3131603453052e834ffe19040fae744614 Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Tue, 10 Jun 2014 14:54:18 +0530 Subject: Arndale: Enable preboot support We need to run 'usb start' as preboot command so that ethernet comes up during u-boot prompt. Signed-off-by: Tushar Behera Signed-off-by: Minkyu Kang diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 30ecd45..370db82 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -229,6 +229,8 @@ #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-arndale +#define CONFIG_PREBOOT + /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_SMC911X -- cgit v0.10.2 From 4a1883651f7e54ad5589ee98c17133fb07247c6f Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 10 Jun 2014 16:55:08 +0200 Subject: trats/trats2: exynos_power_init: return 0 if no battery detected. Generic board support is now enabled for Exynos 4, and if any init function returns an error then the init process is stopped. This makes a boot issue on the Trats and Trats2 devices. If the device is supplied by USB cable or an external power supply then it can't boot because function exynos_power_init returns an error. Now this function returns 0 if battery is not connected. Signed-off-by: Przemyslaw Marczak Cc: Lukasz Majewski Cc: Piotr Wilczek Cc: Minkyu Kang Signed-off-by: Minkyu Kang diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index fec72d4..3dd340b 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -332,7 +332,7 @@ int exynos_power_init(void) if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { puts("No battery detected\n"); - return -1; + return 0; } p_fg->fg->fg_battery_check(p_fg, p_bat); diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index e4987ce..fa26e61 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -214,7 +214,7 @@ int exynos_power_init(void) if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { puts("No battery detected\n"); - return -1; + return 0; } p_fg->fg->fg_battery_check(p_fg, p_bat); -- cgit v0.10.2 From e76d2a81bc350aebf4ae56753fb75983c7a4efdd Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Wed, 18 Jun 2014 17:52:41 +0530 Subject: Exynos: SPI: Fix reading data from SPI flash SPI recieve and transfer code in exynos_spi driver has a logical bug. We read data in a variable which can hold an integer. Then we assign this integer 32 bit value to another variable which has data type uchar. Latter represents a unit of our recieve buffer. Everytime when we write a value to our recieve buffer we step ahead by 4 units when actually we wrote to one unit. This results in the loss of 3 bytes out of every 4 bytes recieved. This patch intends to fix this bug. Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index 4d5def2..c92276f 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -302,7 +302,10 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, } } else { if (rxp || stopping) { - *rxp = temp; + if (step == 4) + *(uint32_t *)rxp = temp; + else + *rxp = temp; rxp += step; } in_bytes -= step; -- cgit v0.10.2 From eacf46d340db182a4068772ec43e2586e9eaf80b Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Wed, 18 Jun 2014 17:53:57 +0530 Subject: Exynos5420: Let macros be used for exynos5420 Macros defined in exynos5_setup.h specific to SMDK5420 are required for Peach-Pit too. Hence, replacing CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these macros for all the boards based on Exynos5420. Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index d91e585..3242093 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -435,10 +435,10 @@ /* * Definitions that differ with SoC's. - * Below is the part defining macros for smdk5250. - * Else part introduces macros for smdk5420. + * Below is the part defining macros for Exynos5250. + * Else part introduces macros for Exynos5420. */ -#ifndef CONFIG_SMDK5420 +#ifndef CONFIG_EXYNOS5420 /* APLL_CON1 */ #define APLL_CON1_VAL (0x00203800) -- cgit v0.10.2 From 8e4ab1d58265884bbc9da6c6720d7a635f00fb2b Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Wed, 18 Jun 2014 17:53:58 +0530 Subject: Exynos5420: Introduce support for the Peach-Pit board While the Exynos5420 chip is used in both Smdk5420 and in the Peach-Pit line of devices, there could be other boards using the same chip, so a common configuration file is being added (exynos5420.h) as well as two common device tree files (exynos54xx.dtsi & exynos5420.dtsi). The peach board as declared in boards.cfg is a copy of smdk5420 declaration. The configuration files are similar, but define different default device trees, console serial ports and prompts. The device tree files for smdk5420 and peach-pit inherit from the same common file. Signed-off-by: Vadim Bendebury Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5554615..933a464 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -6,7 +6,8 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-snow.dtb \ exynos5250-smdk5250.dtb \ - exynos5420-smdk5420.dtb + exynos5420-smdk5420.dtb \ + exynos5420-peach-pit.dtb dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts new file mode 100644 index 0000000..8d148af --- /dev/null +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -0,0 +1,127 @@ +/* + * SAMSUNG/GOOGLE Peach-Pit board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos54xx.dtsi" + +/ { + model = "Samsung/Google Peach Pit board based on Exynos5420"; + + compatible = "google,pit-rev#", "google,pit", + "google,peach", "samsung,exynos5420", "samsung,exynos5"; + + config { + google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */ + hwid = "PIT TEST A-A 7848"; + lazy-init = <1>; + }; + + aliases { + serial0 = "/serial@12C30000"; + console = "/serial@12C30000"; + pmic = "/i2c@12ca0000"; + }; + + dmc { + mem-manuf = "samsung"; + mem-type = "ddr3"; + clock-frequency = <800000000>; + arm-frequency = <1700000000>; + }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + /* MAX77802 is on i2c bus 4 */ + i2c@12ca0000 { + clock-frequency = <400000>; + power-regulator@9 { + compatible = "maxim,max77802-pmic"; + reg = <0x9>; + }; + }; + + i2c@12cd0000 { /* i2c7 */ + clock-frequency = <100000>; + soundcodec@20 { + reg = <0x20>; + compatible = "maxim,max98090-codec"; + }; + }; + + sound@3830000 { + samsung,codec-type = "max98090"; + }; + + i2c@12e10000 { /* i2c9 */ + clock-frequency = <400000>; + tpm@20 { + compatible = "infineon,slb9645-tpm"; + reg = <0x20>; + }; + }; + + spi@12d30000 { /* spi1 */ + spi-max-frequency = <50000000>; + firmware_storage_spi: flash@0 { + reg = <0>; + + /* + * A region for the kernel to store a panic event + * which the firmware will add to the log. + */ + elog-panic-event-offset = <0x01e00000 0x100000>; + + elog-shrink-size = <0x400>; + elog-full-threshold = <0xc00>; + }; + }; + + spi@12d40000 { /* spi2 */ + spi-max-frequency = <4000000>; + spi-deactivate-delay = <200>; + cros-ec@0 { + reg = <0>; + compatible = "google,cros-ec"; + spi-half-duplex; + spi-max-timeout-ms = <1100>; + spi-frame-header = <0xec>; + ec-interrupt = <&gpio 93 1>; /* GPX1_5 */ + + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; + }; + }; + }; + + xhci@12000000 { + samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */ + }; + + xhci@12400000 { + samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */ + }; +}; diff --git a/arch/arm/dts/exynos5420-smdk5420.dts b/arch/arm/dts/exynos5420-smdk5420.dts index d739763..1bc6256 100644 --- a/arch/arm/dts/exynos5420-smdk5420.dts +++ b/arch/arm/dts/exynos5420-smdk5420.dts @@ -8,7 +8,7 @@ */ /dts-v1/; -/include/ "exynos5420.dtsi" +/include/ "exynos54xx.dtsi" / { model = "SAMSUNG SMDK5420 board based on EXYNOS5420"; @@ -19,27 +19,6 @@ }; aliases { - i2c0 = "/i2c@12c60000"; - i2c1 = "/i2c@12c70000"; - i2c2 = "/i2c@12c80000"; - i2c3 = "/i2c@12c90000"; - i2c4 = "/i2c@12ca0000"; - i2c5 = "/i2c@12cb0000"; - i2c6 = "/i2c@12cc0000"; - i2c7 = "/i2c@12cd0000"; - i2c8 = "/i2c@12e00000"; - i2c9 = "/i2c@12e10000"; - i2c10 = "/i2c@12e20000"; - spi0 = "/spi@12d20000"; - spi1 = "/spi@12d30000"; - spi2 = "/spi@12d40000"; - spi3 = "/spi@131a0000"; - spi4 = "/spi@131b0000"; - mmc0 = "/mmc@12200000"; - mmc1 = "/mmc@12210000"; - mmc2 = "/mmc@12220000"; - xhci0 = "/xhci@12000000"; - xhci1 = "/xhci@12400000"; serial0 = "/serial@12C30000"; console = "/serial@12C30000"; }; diff --git a/arch/arm/dts/exynos5420.dtsi b/arch/arm/dts/exynos5420.dtsi deleted file mode 100644 index 02ead61..0000000 --- a/arch/arm/dts/exynos5420.dtsi +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2013 SAMSUNG Electronics - * SAMSUNG EXYNOS5420 SoC device tree source - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/include/ "exynos5.dtsi" - -/ { - config { - machine-arch-id = <4151>; - }; - - i2c@12ca0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5-hsi2c"; - reg = <0x12CA0000 0x100>; - interrupts = <0 60 0>; - }; - - i2c@12cb0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5-hsi2c"; - reg = <0x12CB0000 0x100>; - interrupts = <0 61 0>; - }; - - i2c@12cc0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5-hsi2c"; - reg = <0x12CC0000 0x100>; - interrupts = <0 62 0>; - }; - - i2c@12cd0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5-hsi2c"; - reg = <0x12CD0000 0x100>; - interrupts = <0 63 0>; - }; - - i2c@12e00000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5-hsi2c"; - reg = <0x12E00000 0x100>; - interrupts = <0 87 0>; - }; - - i2c@12e10000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5-hsi2c"; - reg = <0x12E10000 0x100>; - interrupts = <0 88 0>; - }; - - i2c@12e20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5-hsi2c"; - reg = <0x12E20000 0x100>; - interrupts = <0 203 0>; - }; -}; diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi new file mode 100644 index 0000000..b9f8e0b --- /dev/null +++ b/arch/arm/dts/exynos54xx.dtsi @@ -0,0 +1,151 @@ +/* + * (C) Copyright 2013 SAMSUNG Electronics + * SAMSUNG EXYNOS5420 SoC device tree source + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "exynos5.dtsi" + +/ { + config { + machine-arch-id = <4151>; + }; + + aliases { + i2c0 = "/i2c@12c60000"; + i2c1 = "/i2c@12c70000"; + i2c2 = "/i2c@12c80000"; + i2c3 = "/i2c@12c90000"; + i2c4 = "/i2c@12ca0000"; + i2c5 = "/i2c@12cb0000"; + i2c6 = "/i2c@12cc0000"; + i2c7 = "/i2c@12cd0000"; + i2c8 = "/i2c@12e00000"; + i2c9 = "/i2c@12e10000"; + i2c10 = "/i2c@12e20000"; + spi0 = "/spi@12d20000"; + spi1 = "/spi@12d30000"; + spi2 = "/spi@12d40000"; + spi3 = "/spi@131a0000"; + spi4 = "/spi@131b0000"; + mmc0 = "/mmc@12200000"; + mmc1 = "/mmc@12210000"; + mmc2 = "/mmc@12220000"; + xhci0 = "/xhci@12000000"; + xhci1 = "/xhci@12400000"; + }; + + i2c@12ca0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CA0000 0x100>; + interrupts = <0 60 0>; + }; + + i2c@12cb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CB0000 0x100>; + interrupts = <0 61 0>; + }; + + i2c@12cc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CC0000 0x100>; + interrupts = <0 62 0>; + }; + + i2c@12cd0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CD0000 0x100>; + interrupts = <0 63 0>; + }; + + i2c@12e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E00000 0x100>; + interrupts = <0 87 0>; + }; + + i2c@12e10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E10000 0x100>; + interrupts = <0 88 0>; + }; + + i2c@12e20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E20000 0x100>; + interrupts = <0 203 0>; + }; + + mmc@12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + samsung,removable = <0>; + samsung,pre-init; + }; + + mmc@12210000 { + status = "disabled"; + }; + + mmc@12220000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + samsung,removable = <1>; + }; + + mmc@12230000 { + status = "disabled"; + }; + + fimd@14400000 { + /* sysmmu is not used in U-Boot */ + samsung,disable-sysmmu; + }; + + dp@145b0000 { + samsung,lt-status = <0>; + + samsung,master-mode = <0>; + samsung,bist-mode = <0>; + samsung,bist-pattern = <0>; + samsung,h-sync-polarity = <0>; + samsung,v-sync-polarity = <0>; + samsung,interlaced = <0>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + }; + + dmc { + mem-type = "ddr3"; + }; + + xhci1: xhci@12400000 { + compatible = "samsung,exynos5250-xhci"; + reg = <0x12400000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + phy { + compatible = "samsung,exynos5250-usb3-phy"; + reg = <0x12500000 0x100>; + }; + }; +}; diff --git a/boards.cfg b/boards.cfg index 5a85fad..1527ebe 100644 --- a/boards.cfg +++ b/boards.cfg @@ -293,6 +293,7 @@ Active arm armv7 exynos samsung origen Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde +Active arm armv7 exynos samsung smdk5420 peach-pit - Akshay Saraswat Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap Active arm armv7 exynos samsung trats trats - Lukasz Majewski Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h new file mode 100644 index 0000000..3a28bbc --- /dev/null +++ b/include/configs/exynos5420.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5420 SoC + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS5420_H +#define __CONFIG_EXYNOS5420_H + +#define CONFIG_EXYNOS5420 /* which is in a Exynos5 Family */ + +#define MACH_TYPE_SMDK5420 8002 +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 + +#define CONFIG_VAR_SIZE_SPL + +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_TEXT_BASE 0x23E00000 +#ifdef CONFIG_VAR_SIZE_SPL +#define CONFIG_SPL_TEXT_BASE 0x02024410 +#else +#define CONFIG_SPL_TEXT_BASE 0x02024400 +#endif +#define CONFIG_IRAM_TOP 0x02074000 + +#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420" + +#define CONFIG_MAX_I2C_NUM 11 + +/* Enable FIT support and comparison */ +#define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH + +#define CONFIG_BOARD_REV_GPIO_COUNT 2 + +#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" + +/* + * Put the initial stack pointer 1KB below this to allow room for the + * SPL marker. This value is arbitrary, but gd_t is placed starting here. + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) + +#endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h new file mode 100644 index 0000000..76b8d7a --- /dev/null +++ b/include/configs/peach-pit.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG/GOOGLE PEACH-PIT board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PEACH_PIT_H +#define __CONFIG_PEACH_PIT_H + +#include + +#include + +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos5420-peach-pit + +/* select serial console configuration */ +#define CONFIG_SERIAL3 /* use SERIAL 3 */ + +#define CONFIG_SYS_PROMPT "Peach # " +#define CONFIG_IDENT_STRING " for Peach" + +#endif /* __CONFIG_PEACH_PIT_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 58f706a..606739b 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -1,58 +1,27 @@ /* * Copyright (C) 2013 Samsung Electronics * - * Configuration settings for the SAMSUNG EXYNOS5420 board. + * Configuration settings for the SAMSUNG SMDK5420 board. * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_5420_H -#define __CONFIG_5420_H +#ifndef __CONFIG_SMDK5420_H +#define __CONFIG_SMDK5420_H #include -#define CONFIG_EXYNOS5420 /* which is in a Exynos5 Family */ +#include + #define CONFIG_SMDK5420 /* which is in a SMDK5420 */ #undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5420-smdk5420 -#define CONFIG_VAR_SIZE_SPL - -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_TEXT_BASE 0x23E00000 - -#define CONFIG_BOARD_REV_GPIO_COUNT 2 - -/* MACH_TYPE_SMDK5420 macro will be removed once added to mach-types */ -#define MACH_TYPE_SMDK5420 8002 /* Temporary number */ -#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 - /* select serial console configuration */ -#define CONFIG_SERIAL3 /* use SERIAL 3 */ - -#ifdef CONFIG_VAR_SIZE_SPL -#define CONFIG_SPL_TEXT_BASE 0x02024410 -#else -#define CONFIG_SPL_TEXT_BASE 0x02024400 -#endif - -#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" - -#define CONFIG_SYS_PROMPT "SMDK5420 # " -#define CONFIG_IDENT_STRING " for SMDK5420" - -#define CONFIG_IRAM_TOP 0x02074000 -/* - * Put the initial stack pointer 1KB below this to allow room for the - * SPL marker. This value is arbitrary, but gd_t is placed starting here. - */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) - -#define CONFIG_MAX_I2C_NUM 11 +#define CONFIG_SERIAL3 /* use SERIAL 3 */ -/* Enable FIT support and comparison */ -#define CONFIG_FIT -#define CONFIG_FIT_BEST_MATCH +#define CONFIG_SYS_PROMPT "SMDK5420 # " +#define CONFIG_IDENT_STRING " for SMDK5420" -#endif /* __CONFIG_5420_H */ +#endif /* __CONFIG_SMDK5420_H */ -- cgit v0.10.2 From fa25315741aa9197bcc2ed7e09f5fd61b09003be Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Wed, 18 Jun 2014 17:53:59 +0530 Subject: Exynos5: Config: Place environment at the end of SPI flash Currently environment resides at the location where BL2 ends. This may hold good in case there is an empty space at this position. But what if this place already has a binary or is expected to have one. To avoid such scenarios it is better to save environment at the end of the flash. Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index b830495..d9f5625 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -207,7 +207,10 @@ #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) -#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) + +/* Store environment at the end of a 4 MB SPI flash */ +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) /* U-boot copy size from boot Media to DRAM.*/ #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) -- cgit v0.10.2 From d2fe10fd42ba419749900340f7eb0d9e751c4702 Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Wed, 18 Jun 2014 17:54:00 +0530 Subject: Exynos5: Config: Increase SPL footprint for Exynos5420 Max footprint for SPL in both Exynos 5250 and 5420 is limited to 14 KB. For Exynos5250 we need to keep it 14 KB because BL1 supports only fixed size SPL downloading. But in case of Exynos5420 we need not restrict it to 14 KB. And also, the SPL size for Exynos5420 is expected to increase with the upcoming patches and the patches under review right now. Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index d9f5625..1129f59 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -144,8 +144,6 @@ /* specific .lds file */ #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 9d1d56a..4cfbf25 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -20,6 +20,8 @@ #define MACH_TYPE_SMDK5250 3774 #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) + /* USB */ #define CONFIG_CMD_USB #define CONFIG_USB_XHCI diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h index 3a28bbc..2ffe5ee 100644 --- a/include/configs/exynos5420.h +++ b/include/configs/exynos5420.h @@ -25,6 +25,8 @@ #endif #define CONFIG_IRAM_TOP 0x02074000 +#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) + #define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420" #define CONFIG_MAX_I2C_NUM 11 -- cgit v0.10.2 From 582693b273b43ec0ca6694d61456ba0a0b9739a9 Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Wed, 18 Jun 2014 17:54:01 +0530 Subject: Exynos5: Config: Enable USB boot mode for all Exynos5 SoCs Right now USB booting is enabled for Exynos5250 only. Moving all the configs for USB boot mode from exynos5250-dt.h to exynos5-dt.h in order to enableUSB booting for all Exynos5 SoCs. Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index 1129f59..3c51650 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -292,4 +292,10 @@ #define CONFIG_CMD_GPIO +/* USB boot mode */ +#define CONFIG_USB_BOOTING +#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 +#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 +#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 + #endif /* __CONFIG_H */ diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 4cfbf25..3982010 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -29,12 +29,6 @@ #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE -/* USB boot mode */ -#define CONFIG_USB_BOOTING -#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 -#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 -#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 - #define CONFIG_SPL_TEXT_BASE 0x02023400 #define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" -- cgit v0.10.2 From 0cf7e18904f245d0ba7a5ed85ed48bea386258d4 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Wed, 18 Jun 2014 17:54:02 +0530 Subject: Exynos: Split 5250 and 5420 memory bank configuration Since snow has a different memory configuration than peach, split the configuration between the 5250 and 5420. Exynos 5420 supports runtime memory configuration detection, and can make the determination between 4 and 7 banks at runtime. Include the bank size with the number of banks for context to make the number of banks meaningful. Signed-off-by: Michael Pratt Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index 3c51650..e36a031 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -161,8 +161,6 @@ #define CONFIG_RD_LVL -#define CONFIG_NR_DRAM_BANKS 8 -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 3982010..74e72a5 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -65,4 +65,9 @@ #define LCD_YRES 1600 #define LCD_BPP LCD_COLOR16 #endif + +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 8 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + #endif /* __CONFIG_5250_H */ diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h index 2ffe5ee..d2a9556 100644 --- a/include/configs/exynos5420.h +++ b/include/configs/exynos5420.h @@ -45,4 +45,8 @@ */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + #endif /* __CONFIG_EXYNOS5420_H */ -- cgit v0.10.2 From 00d4796c555b95e986b4a01a9322d49f64c1349f Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Wed, 18 Jun 2014 22:13:52 +0200 Subject: PMIC: MAX77686: fix invalid bus check Since p->bus is unsigned checking for negative values is optimized away. Since bus is already used as an argument use tmp. While at it, don't declare variables in the middle of a function. cc: Rajeshwari Shinde Signed-off-by: Jeroen Hofstee Signed-off-by: Minkyu Kang diff --git a/drivers/power/pmic/pmic_max77686.c b/drivers/power/pmic/pmic_max77686.c index d4c430e..df1fd91 100644 --- a/drivers/power/pmic/pmic_max77686.c +++ b/drivers/power/pmic/pmic_max77686.c @@ -210,6 +210,10 @@ int pmic_init(unsigned char bus) { static const char name[] = "MAX77686_PMIC"; struct pmic *p = pmic_alloc(); +#ifdef CONFIG_OF_CONTROL + const void *blob = gd->fdt_blob; + int node, parent, tmp; +#endif if (!p) { printf("%s: POWER allocation error!\n", __func__); @@ -217,9 +221,6 @@ int pmic_init(unsigned char bus) } #ifdef CONFIG_OF_CONTROL - const void *blob = gd->fdt_blob; - int node, parent; - node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_MAX77686_PMIC); if (node < 0) { debug("PMIC: No node for PMIC Chip in device tree\n"); @@ -233,11 +234,13 @@ int pmic_init(unsigned char bus) return -1; } - p->bus = i2c_get_bus_num_fdt(parent); - if (p->bus < 0) { + /* tmp since p->bus is unsigned */ + tmp = i2c_get_bus_num_fdt(parent); + if (tmp < 0) { debug("%s: Cannot find I2C bus\n", __func__); return -1; } + p->bus = tmp; p->hw.i2c.addr = fdtdec_get_int(blob, node, "reg", 9); #else p->bus = bus; -- cgit v0.10.2 From 5287d595449512385e25f5afcb68a130bf08bae6 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Fri, 27 Jun 2014 12:32:06 +0200 Subject: Samsung: Goni: change maintainer to Robert Baldyga Robert Baldyga will now take care of this board. Signed-off-by: Przemyslaw Marczak Cc: Robert Baldyga Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang diff --git a/boards.cfg b/boards.cfg index 1527ebe..673e599 100644 --- a/boards.cfg +++ b/boards.cfg @@ -379,7 +379,7 @@ Active arm armv7 rmobile renesas koelsch Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu -Active arm armv7 s5pc1xx samsung goni s5p_goni - Przemyslaw Marczak +Active arm armv7 s5pc1xx samsung goni s5p_goni - Robert Baldyga Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII - -- cgit v0.10.2