From 8a1a7595cfbcb12d01a5c1f486ebfd50af90c34c Mon Sep 17 00:00:00 2001 From: George McCollister Date: Tue, 7 Jun 2016 13:40:18 -0500 Subject: x86: acpi: Fix madt lapic generation An accumulated length was incorrectly added to current each pass through the loop. On system with more than 2 cores this caused a corrupt MADT to be generated. Signed-off-by: George McCollister Reviewed-by: Simon Glass Reviewed-by: Bin Meng diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index ffb4678..bb71286 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -183,20 +183,20 @@ static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic, int acpi_create_madt_lapics(u32 current) { struct udevice *dev; - int length = 0; + int total_length = 0; for (uclass_find_first_device(UCLASS_CPU, &dev); dev; uclass_find_next_device(&dev)) { struct cpu_platdata *plat = dev_get_parent_platdata(dev); - - length += acpi_create_madt_lapic( - (struct acpi_madt_lapic *)current, - plat->cpu_id, plat->cpu_id); + int length = acpi_create_madt_lapic( + (struct acpi_madt_lapic *)current, + plat->cpu_id, plat->cpu_id); current += length; + total_length += length; } - return length; + return total_length; } int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, -- cgit v0.10.2 From 8142340ee3847c6422294fad0f1adc01c9d27e2b Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 8 Jun 2016 05:07:32 -0700 Subject: x86: ich6_gpio: Output return value of syscon_get_by_driver_data() The call to syscon_get_by_driver_data() does not save its return value. Print it out to aid debugging. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index b7e379a..2d66d04 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -114,9 +114,11 @@ static int ich6_gpio_probe(struct udevice *dev) struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct ich6_bank_priv *bank = dev_get_priv(dev); struct udevice *pinctrl; + int ret; /* Set up pin control if available */ - syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl); + ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl); + debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret); uc_priv->gpio_count = GPIO_PER_BANK; uc_priv->bank_name = plat->bank_name; -- cgit v0.10.2 From e264e3cc5be81548c6f102b6b597a474e5bd4f20 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 8 Jun 2016 05:07:33 -0700 Subject: x86: baytrail: Add 'reg' property in the pinctrl node Without a 'reg' property, pinctrl driver probe routine fails in its pre_probe() with a return value of -EINVAL. Add 'reg' property for all BayTrail boards. Note for BayleyBay, the pinctrl node is newly added. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 4a50d86..536049b 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -65,6 +65,11 @@ }; }; + pch_pinctrl { + compatible = "intel,x86-pinctrl"; + reg = <0 0>; + }; + pci { compatible = "pci-x86"; #address-cells = <3>; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 1a4ecaa..7e69ba4 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -30,6 +30,7 @@ pch_pinctrl { compatible = "intel,x86-pinctrl"; + reg = <0 0>; }; chosen { diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 936455b..fda170c 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -29,6 +29,7 @@ pch_pinctrl { compatible = "intel,x86-pinctrl"; + reg = <0 0>; /* GPIO E0 */ soc_gpio_s5_0@0 { -- cgit v0.10.2 From 58d1fedb1f7d1a65918dcdc82c53f83b4c813368 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 8 Jun 2016 05:07:34 -0700 Subject: x86: baytrail: Change fsp, emmc-boot-mode to "auto" At present all BayTrail boards configure fsp,emmc-boot-mode to 2, which means "eMMC 4.1" per FSP documentation. However, eMMC 4.1 only shows up on some early stepping silicon of BayTrail SoC. Newer stepping SoC integrates an eMMC 4.5 controller. Intel FSP provides a config option fsp,emmc-boot-mode which tells FSP which eMMC controller it initializes. Instead of hardcoded to 2, now we change it to 1 which means "auto". With this change, MinnowMax board (with a D0 stepping BayTrail SoC) can see the eMMC 4.5 controller at PCI address 00.17.00 via U-Boot 'pci' command. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 536049b..1c2f671 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -218,7 +218,7 @@ fsp,mrc-init-mmio-size = <0x800>; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <2>; + fsp,emmc-boot-mode = <1>; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 7e69ba4..1e14c8b 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -218,7 +218,7 @@ fsp,mrc-init-mmio-size = <0x800>; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <2>; + fsp,emmc-boot-mode = <1>; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index fda170c..ba96e36 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -247,7 +247,7 @@ fsp,mrc-init-mmio-size = <0x800>; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <2>; + fsp,emmc-boot-mode = <1>; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1; -- cgit v0.10.2 From f7a01e4848a97935985f58e5cd1b133dad298323 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 8 Jun 2016 05:07:35 -0700 Subject: x86: baytrail: Configure card detect pin of the SD controller As of today, the latest version FSP (gold4) for BayTrail misses the PAD configuration of the SD controller's Card Detect signal. The default PAD value for the CD pin sets the pin to work in GPIO mode, which causes card detect status cannot be reflected by the Present State register in the SD controller (bit 16 & bit 18 are always zero). Add a configuration for this pin in the pinctrl node. Note I've checked the PAD configuration for all the pins in all the 3 controllers (eMMC/SDIO/SD). Only this SDMMC3_CD_B pin does not get initialized to correct mode by FSP. With fsp,emmc-boot-mode set to 2 (eMMC 4.1), eMMC pins are initialized to func 1, but if we set fsp,emmc-boot-mode to 1 (auto), those pins are initialized to func 3 which is correct according to datasheet. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 1c2f671..c8907ce 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -68,6 +68,21 @@ pch_pinctrl { compatible = "intel,x86-pinctrl"; reg = <0 0>; + + /* + * As of today, the latest version FSP (gold4) for BayTrail + * misses the PAD configuration of the SD controller's Card + * Detect signal. The default PAD value for the CD pin sets + * the pin to work in GPIO mode, which causes card detect + * status cannot be reflected by the Present State register + * in the SD controller (bit 16 & bit 18 are always zero). + * + * Configure this pin to function 1 (SD controller). + */ + sdmmc3_cd@0 { + pad-offset = <0x3a0>; + mode-func = <1>; + }; }; pci { diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 1e14c8b..fba089d 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -31,6 +31,21 @@ pch_pinctrl { compatible = "intel,x86-pinctrl"; reg = <0 0>; + + /* + * As of today, the latest version FSP (gold4) for BayTrail + * misses the PAD configuration of the SD controller's Card + * Detect signal. The default PAD value for the CD pin sets + * the pin to work in GPIO mode, which causes card detect + * status cannot be reflected by the Present State register + * in the SD controller (bit 16 & bit 18 are always zero). + * + * Configure this pin to function 1 (SD controller). + */ + sdmmc3_cd@0 { + pad-offset = <0x3a0>; + mode-func = <1>; + }; }; chosen { diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index ba96e36..1a8a8cc 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -73,6 +73,21 @@ output-value = <1>; direction = ; }; + + /* + * As of today, the latest version FSP (gold4) for BayTrail + * misses the PAD configuration of the SD controller's Card + * Detect signal. The default PAD value for the CD pin sets + * the pin to work in GPIO mode, which causes card detect + * status cannot be reflected by the Present State register + * in the SD controller (bit 16 & bit 18 are always zero). + * + * Configure this pin to function 1 (SD controller). + */ + sdmmc3_cd@0 { + pad-offset = <0x3a0>; + mode-func = <1>; + }; }; chosen { -- cgit v0.10.2 From 2600ba6de07d80407308c632c7bfa3a538b36549 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 8 Jun 2016 05:07:36 -0700 Subject: x86: Update x86-pinctrl driver device-tree-bindings doc This updates the device-tree-bindings doc for x86-pinctrl driver: - clarify "gpio-offset" is required only when "mode-gpio" is set - correct property name "pull-strength" - use tab instead of space at several places Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt index 22d3bec..8c3a84c 100644 --- a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt +++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt @@ -9,7 +9,7 @@ The PINCTRL master node requires the following properties: Pin nodes must be children of the pinctrl master node and can contain the following properties: - pad-offset - (required) offset in the IOBASE for the pin to configure -- gpio-offset - (required) 2 cells +- gpio-offset - (required only when 'mode-gpio' is set) 2 cells - offset in the GPIOBASE for the pin to configure - the bit shift in this register (4 = bit 4) - mode-gpio - (optional) standalone property to force the pin into GPIO mode @@ -18,16 +18,16 @@ contain the following properties: in case of 'mode-gpio' property set: - output-value - (optional) this set the default output value of the GPIO - direction - (optional) this set the direction of the gpio -- pull-str - (optional) this set the pull strength of the pin +- pull-strength - (optional) this set the pull strength of the pin - pull-assign - (optional) this set the pull assignement (up/down) of the pin -- invert - (optional) this input pin is inverted +- invert - (optional) this input pin is inverted Example: pin_usb_host_en0@0 { - gpio-offset = <0x80 8>; - pad-offset = <0x260>; - mode-gpio; - output-value = <1>; - direction = ; + gpio-offset = <0x80 8>; + pad-offset = <0x260>; + mode-gpio; + output-value = <1>; + direction = ; }; -- cgit v0.10.2 From 2f29c83eec16b806947c6a224c3a3f70bc31edc9 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 8 Jun 2016 05:07:37 -0700 Subject: x86: Enable regmap and syscon for coreboot and qemu-x86 These are generic and should be turned on on coreboot and qemu-x86. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig index 2fa11fd..b18d80d 100644 --- a/configs/coreboot-x86_defconfig +++ b/configs/coreboot-x86_defconfig @@ -24,6 +24,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 45bb3ec..a03cff8 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -28,6 +28,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CPU=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_GIGADEVICE=y -- cgit v0.10.2 From d8906c1f3fd9e437066a9de7ff2de306696a7598 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 8 Jun 2016 05:07:38 -0700 Subject: x86: Probe pinctrl driver in cpu_init_r() At present pinctrl driver gets probed in ich6_gpio driver's probe routine, which has two issues: - Pin's PADs only gets configured when GPIO driver is probed, which is not done by default. This leaves the board in a partially functional state as we must initialize PADs correctly to get perepherals fully working. - The probe routine of pinctrl driver is called multiple times, as normally there are multiple GPIO controllers. It should really be called just once. Move the call to syscon_get_by_driver_data() from ich6_gpio driver to cpu_init_r(). Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass Reviewed-by: George McCollister Tested-by: George McCollister diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index e522ff3..269043d 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -751,6 +752,10 @@ int cpu_init_r(void) uclass_first_device(UCLASS_PCH, &dev); uclass_first_device(UCLASS_LPC, &dev); + /* Set up pin control if available */ + ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); + debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret); + return 0; } diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index 2d66d04..fd6181f 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include @@ -113,12 +112,6 @@ static int ich6_gpio_probe(struct udevice *dev) struct ich6_bank_platdata *plat = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct ich6_bank_priv *bank = dev_get_priv(dev); - struct udevice *pinctrl; - int ret; - - /* Set up pin control if available */ - ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl); - debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret); uc_priv->gpio_count = GPIO_PER_BANK; uc_priv->bank_name = plat->bank_name; -- cgit v0.10.2 From 9769e05bcf79939bad23a719982dd1f85a110f3c Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 8 Jun 2016 05:07:39 -0700 Subject: x86: broadwell: gpio: Remove the codes to set up pin control Now that we have set up pin control in cpu_init_r(), remove the duplicated codes in the broadwell gpio driver. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass diff --git a/drivers/gpio/intel_broadwell_gpio.c b/drivers/gpio/intel_broadwell_gpio.c index 81ce446..8b50900 100644 --- a/drivers/gpio/intel_broadwell_gpio.c +++ b/drivers/gpio/intel_broadwell_gpio.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -119,12 +118,6 @@ static int broadwell_gpio_probe(struct udevice *dev) struct broadwell_bank_platdata *plat = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct broadwell_bank_priv *priv = dev_get_priv(dev); - struct udevice *pinctrl; - int ret; - - /* Set up pin control if available */ - ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl); - debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret); uc_priv->gpio_count = GPIO_PER_BANK; uc_priv->bank_name = plat->bank_name; -- cgit v0.10.2