From 01a97a11db75c1a006da7b40d8ba4a325f05960c Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 12 May 2016 12:07:39 -0600
Subject: ARM: tegra: use DT bindings for GPIO naming

There are currently many places that define the list of all Tegra GPIOs;
the DT binding header and custom Tegra-specific header file gpio.h. Fix
the redundancy by replacing everything with the DT binding header file.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h
index daf5698..db60864 100644
--- a/arch/arm/include/asm/arch-tegra/gpio.h
+++ b/arch/arm/include/asm/arch-tegra/gpio.h
@@ -6,6 +6,8 @@
 #ifndef _TEGRA_GPIO_H_
 #define _TEGRA_GPIO_H_
 
+#include <dt-bindings/gpio/tegra-gpio.h>
+
 #define TEGRA_GPIOS_PER_PORT	8
 #define TEGRA_PORTS_PER_BANK	4
 #define MAX_NUM_GPIOS           (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h
index 1a6dcb8..ba748a5 100644
--- a/arch/arm/include/asm/arch-tegra124/gpio.h
+++ b/arch/arm/include/asm/arch-tegra124/gpio.h
@@ -41,263 +41,4 @@ struct gpio_ctlr {
 	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
 };
 
-enum gpio_pin {
-	GPIO_PA0 = 0,	/* pin 0 */
-	GPIO_PA1,
-	GPIO_PA2,
-	GPIO_PA3,
-	GPIO_PA4,
-	GPIO_PA5,
-	GPIO_PA6,
-	GPIO_PA7,
-	GPIO_PB0,	/* pin 8 */
-	GPIO_PB1,
-	GPIO_PB2,
-	GPIO_PB3,
-	GPIO_PB4,
-	GPIO_PB5,
-	GPIO_PB6,
-	GPIO_PB7,
-	GPIO_PC0,	/* pin 16 */
-	GPIO_PC1,
-	GPIO_PC2,
-	GPIO_PC3,
-	GPIO_PC4,
-	GPIO_PC5,
-	GPIO_PC6,
-	GPIO_PC7,
-	GPIO_PD0,	/* pin 24 */
-	GPIO_PD1,
-	GPIO_PD2,
-	GPIO_PD3,
-	GPIO_PD4,
-	GPIO_PD5,
-	GPIO_PD6,
-	GPIO_PD7,
-	GPIO_PE0,	/* pin 32 */
-	GPIO_PE1,
-	GPIO_PE2,
-	GPIO_PE3,
-	GPIO_PE4,
-	GPIO_PE5,
-	GPIO_PE6,
-	GPIO_PE7,
-	GPIO_PF0,	/* pin 40 */
-	GPIO_PF1,
-	GPIO_PF2,
-	GPIO_PF3,
-	GPIO_PF4,
-	GPIO_PF5,
-	GPIO_PF6,
-	GPIO_PF7,
-	GPIO_PG0,	/* pin 48 */
-	GPIO_PG1,
-	GPIO_PG2,
-	GPIO_PG3,
-	GPIO_PG4,
-	GPIO_PG5,
-	GPIO_PG6,
-	GPIO_PG7,
-	GPIO_PH0,	/* pin 56 */
-	GPIO_PH1,
-	GPIO_PH2,
-	GPIO_PH3,
-	GPIO_PH4,
-	GPIO_PH5,
-	GPIO_PH6,
-	GPIO_PH7,
-	GPIO_PI0,	/* pin 64 */
-	GPIO_PI1,
-	GPIO_PI2,
-	GPIO_PI3,
-	GPIO_PI4,
-	GPIO_PI5,
-	GPIO_PI6,
-	GPIO_PI7,
-	GPIO_PJ0,	/* pin 72 */
-	GPIO_PJ1,
-	GPIO_PJ2,
-	GPIO_PJ3,
-	GPIO_PJ4,
-	GPIO_PJ5,
-	GPIO_PJ6,
-	GPIO_PJ7,
-	GPIO_PK0,	/* pin 80 */
-	GPIO_PK1,
-	GPIO_PK2,
-	GPIO_PK3,
-	GPIO_PK4,
-	GPIO_PK5,
-	GPIO_PK6,
-	GPIO_PK7,
-	GPIO_PL0,	/* pin 88 */
-	GPIO_PL1,
-	GPIO_PL2,
-	GPIO_PL3,
-	GPIO_PL4,
-	GPIO_PL5,
-	GPIO_PL6,
-	GPIO_PL7,
-	GPIO_PM0,	/* pin 96 */
-	GPIO_PM1,
-	GPIO_PM2,
-	GPIO_PM3,
-	GPIO_PM4,
-	GPIO_PM5,
-	GPIO_PM6,
-	GPIO_PM7,
-	GPIO_PN0,	/* pin 104 */
-	GPIO_PN1,
-	GPIO_PN2,
-	GPIO_PN3,
-	GPIO_PN4,
-	GPIO_PN5,
-	GPIO_PN6,
-	GPIO_PN7,
-	GPIO_PO0,	/* pin 112 */
-	GPIO_PO1,
-	GPIO_PO2,
-	GPIO_PO3,
-	GPIO_PO4,
-	GPIO_PO5,
-	GPIO_PO6,
-	GPIO_PO7,
-	GPIO_PP0,	/* pin 120 */
-	GPIO_PP1,
-	GPIO_PP2,
-	GPIO_PP3,
-	GPIO_PP4,
-	GPIO_PP5,
-	GPIO_PP6,
-	GPIO_PP7,
-	GPIO_PQ0,	/* pin 128 */
-	GPIO_PQ1,
-	GPIO_PQ2,
-	GPIO_PQ3,
-	GPIO_PQ4,
-	GPIO_PQ5,
-	GPIO_PQ6,
-	GPIO_PQ7,
-	GPIO_PR0,	/* pin 136 */
-	GPIO_PR1,
-	GPIO_PR2,
-	GPIO_PR3,
-	GPIO_PR4,
-	GPIO_PR5,
-	GPIO_PR6,
-	GPIO_PR7,
-	GPIO_PS0,	/* pin 144 */
-	GPIO_PS1,
-	GPIO_PS2,
-	GPIO_PS3,
-	GPIO_PS4,
-	GPIO_PS5,
-	GPIO_PS6,
-	GPIO_PS7,
-	GPIO_PT0,	/* pin 152 */
-	GPIO_PT1,
-	GPIO_PT2,
-	GPIO_PT3,
-	GPIO_PT4,
-	GPIO_PT5,
-	GPIO_PT6,
-	GPIO_PT7,
-	GPIO_PU0,	/* pin 160 */
-	GPIO_PU1,
-	GPIO_PU2,
-	GPIO_PU3,
-	GPIO_PU4,
-	GPIO_PU5,
-	GPIO_PU6,
-	GPIO_PU7,
-	GPIO_PV0,	/* pin 168 */
-	GPIO_PV1,
-	GPIO_PV2,
-	GPIO_PV3,
-	GPIO_PV4,
-	GPIO_PV5,
-	GPIO_PV6,
-	GPIO_PV7,
-	GPIO_PW0,	/* pin 176 */
-	GPIO_PW1,
-	GPIO_PW2,
-	GPIO_PW3,
-	GPIO_PW4,
-	GPIO_PW5,
-	GPIO_PW6,
-	GPIO_PW7,
-	GPIO_PX0,	/* pin 184 */
-	GPIO_PX1,
-	GPIO_PX2,
-	GPIO_PX3,
-	GPIO_PX4,
-	GPIO_PX5,
-	GPIO_PX6,
-	GPIO_PX7,
-	GPIO_PY0,	/* pin 192 */
-	GPIO_PY1,
-	GPIO_PY2,
-	GPIO_PY3,
-	GPIO_PY4,
-	GPIO_PY5,
-	GPIO_PY6,
-	GPIO_PY7,
-	GPIO_PZ0,	/* pin 200 */
-	GPIO_PZ1,
-	GPIO_PZ2,
-	GPIO_PZ3,
-	GPIO_PZ4,
-	GPIO_PZ5,
-	GPIO_PZ6,
-	GPIO_PZ7,
-	GPIO_PAA0,	/* pin 208 */
-	GPIO_PAA1,
-	GPIO_PAA2,
-	GPIO_PAA3,
-	GPIO_PAA4,
-	GPIO_PAA5,
-	GPIO_PAA6,
-	GPIO_PAA7,
-	GPIO_PBB0,	/* pin 216 */
-	GPIO_PBB1,
-	GPIO_PBB2,
-	GPIO_PBB3,
-	GPIO_PBB4,
-	GPIO_PBB5,
-	GPIO_PBB6,
-	GPIO_PBB7,
-	GPIO_PCC0,	/* pin 224 */
-	GPIO_PCC1,
-	GPIO_PCC2,
-	GPIO_PCC3,
-	GPIO_PCC4,
-	GPIO_PCC5,
-	GPIO_PCC6,
-	GPIO_PCC7,
-	GPIO_PDD0,	/* pin 232 */
-	GPIO_PDD1,
-	GPIO_PDD2,
-	GPIO_PDD3,
-	GPIO_PDD4,
-	GPIO_PDD5,
-	GPIO_PDD6,
-	GPIO_PDD7,
-	GPIO_PEE0,	/* pin 240 */
-	GPIO_PEE1,
-	GPIO_PEE2,
-	GPIO_PEE3,
-	GPIO_PEE4,
-	GPIO_PEE5,
-	GPIO_PEE6,
-	GPIO_PEE7,
-	GPIO_PFF0,	/* pin 248 */
-	GPIO_PFF1,
-	GPIO_PFF2,
-	GPIO_PFF3,
-	GPIO_PFF4,
-	GPIO_PFF5,
-	GPIO_PFF6,
-	GPIO_PFF7,	/* pin 255 */
-};
-
 #endif	/* _TEGRA124_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/gpio.h b/arch/arm/include/asm/arch-tegra20/gpio.h
index b40b1ff..af301e7 100644
--- a/arch/arm/include/asm/arch-tegra20/gpio.h
+++ b/arch/arm/include/asm/arch-tegra20/gpio.h
@@ -33,231 +33,4 @@ struct gpio_ctlr {
 	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
 };
 
-enum gpio_pin {
-	GPIO_PA0 = 0,	/* pin 0 */
-	GPIO_PA1,
-	GPIO_PA2,
-	GPIO_PA3,
-	GPIO_PA4,
-	GPIO_PA5,
-	GPIO_PA6,
-	GPIO_PA7,
-	GPIO_PB0,	/* pin 8 */
-	GPIO_PB1,
-	GPIO_PB2,
-	GPIO_PB3,
-	GPIO_PB4,
-	GPIO_PB5,
-	GPIO_PB6,
-	GPIO_PB7,
-	GPIO_PC0,	/* pin 16 */
-	GPIO_PC1,
-	GPIO_PC2,
-	GPIO_PC3,
-	GPIO_PC4,
-	GPIO_PC5,
-	GPIO_PC6,
-	GPIO_PC7,
-	GPIO_PD0,	/* pin 24 */
-	GPIO_PD1,
-	GPIO_PD2,
-	GPIO_PD3,
-	GPIO_PD4,
-	GPIO_PD5,
-	GPIO_PD6,
-	GPIO_PD7,
-	GPIO_PE0,	/* pin 32 */
-	GPIO_PE1,
-	GPIO_PE2,
-	GPIO_PE3,
-	GPIO_PE4,
-	GPIO_PE5,
-	GPIO_PE6,
-	GPIO_PE7,
-	GPIO_PF0,	/* pin 40 */
-	GPIO_PF1,
-	GPIO_PF2,
-	GPIO_PF3,
-	GPIO_PF4,
-	GPIO_PF5,
-	GPIO_PF6,
-	GPIO_PF7,
-	GPIO_PG0,	/* pin 48 */
-	GPIO_PG1,
-	GPIO_PG2,
-	GPIO_PG3,
-	GPIO_PG4,
-	GPIO_PG5,
-	GPIO_PG6,
-	GPIO_PG7,
-	GPIO_PH0,	/* pin 56 */
-	GPIO_PH1,
-	GPIO_PH2,
-	GPIO_PH3,
-	GPIO_PH4,
-	GPIO_PH5,
-	GPIO_PH6,
-	GPIO_PH7,
-	GPIO_PI0,	/* pin 64 */
-	GPIO_PI1,
-	GPIO_PI2,
-	GPIO_PI3,
-	GPIO_PI4,
-	GPIO_PI5,
-	GPIO_PI6,
-	GPIO_PI7,
-	GPIO_PJ0,	/* pin 72 */
-	GPIO_PJ1,
-	GPIO_PJ2,
-	GPIO_PJ3,
-	GPIO_PJ4,
-	GPIO_PJ5,
-	GPIO_PJ6,
-	GPIO_PJ7,
-	GPIO_PK0,	/* pin 80 */
-	GPIO_PK1,
-	GPIO_PK2,
-	GPIO_PK3,
-	GPIO_PK4,
-	GPIO_PK5,
-	GPIO_PK6,
-	GPIO_PK7,
-	GPIO_PL0,	/* pin 88 */
-	GPIO_PL1,
-	GPIO_PL2,
-	GPIO_PL3,
-	GPIO_PL4,
-	GPIO_PL5,
-	GPIO_PL6,
-	GPIO_PL7,
-	GPIO_PM0,	/* pin 96 */
-	GPIO_PM1,
-	GPIO_PM2,
-	GPIO_PM3,
-	GPIO_PM4,
-	GPIO_PM5,
-	GPIO_PM6,
-	GPIO_PM7,
-	GPIO_PN0,	/* pin 104 */
-	GPIO_PN1,
-	GPIO_PN2,
-	GPIO_PN3,
-	GPIO_PN4,
-	GPIO_PN5,
-	GPIO_PN6,
-	GPIO_PN7,
-	GPIO_PO0,	/* pin 112 */
-	GPIO_PO1,
-	GPIO_PO2,
-	GPIO_PO3,
-	GPIO_PO4,
-	GPIO_PO5,
-	GPIO_PO6,
-	GPIO_PO7,
-	GPIO_PP0,	/* pin 120 */
-	GPIO_PP1,
-	GPIO_PP2,
-	GPIO_PP3,
-	GPIO_PP4,
-	GPIO_PP5,
-	GPIO_PP6,
-	GPIO_PP7,
-	GPIO_PQ0,	/* pin 128 */
-	GPIO_PQ1,
-	GPIO_PQ2,
-	GPIO_PQ3,
-	GPIO_PQ4,
-	GPIO_PQ5,
-	GPIO_PQ6,
-	GPIO_PQ7,
-	GPIO_PR0,	/* pin 136 */
-	GPIO_PR1,
-	GPIO_PR2,
-	GPIO_PR3,
-	GPIO_PR4,
-	GPIO_PR5,
-	GPIO_PR6,
-	GPIO_PR7,
-	GPIO_PS0,	/* pin 144 */
-	GPIO_PS1,
-	GPIO_PS2,
-	GPIO_PS3,
-	GPIO_PS4,
-	GPIO_PS5,
-	GPIO_PS6,
-	GPIO_PS7,
-	GPIO_PT0,	/* pin 152 */
-	GPIO_PT1,
-	GPIO_PT2,
-	GPIO_PT3,
-	GPIO_PT4,
-	GPIO_PT5,
-	GPIO_PT6,
-	GPIO_PT7,
-	GPIO_PU0,	/* pin 160 */
-	GPIO_PU1,
-	GPIO_PU2,
-	GPIO_PU3,
-	GPIO_PU4,
-	GPIO_PU5,
-	GPIO_PU6,
-	GPIO_PU7,
-	GPIO_PV0,	/* pin 168 */
-	GPIO_PV1,
-	GPIO_PV2,
-	GPIO_PV3,
-	GPIO_PV4,
-	GPIO_PV5,
-	GPIO_PV6,
-	GPIO_PV7,
-	GPIO_PW0,	/* pin 176 */
-	GPIO_PW1,
-	GPIO_PW2,
-	GPIO_PW3,
-	GPIO_PW4,
-	GPIO_PW5,
-	GPIO_PW6,
-	GPIO_PW7,
-	GPIO_PX0,	/* pin 184 */
-	GPIO_PX1,
-	GPIO_PX2,
-	GPIO_PX3,
-	GPIO_PX4,
-	GPIO_PX5,
-	GPIO_PX6,
-	GPIO_PX7,
-	GPIO_PY0,	/* pin 192 */
-	GPIO_PY1,
-	GPIO_PY2,
-	GPIO_PY3,
-	GPIO_PY4,
-	GPIO_PY5,
-	GPIO_PY6,
-	GPIO_PY7,
-	GPIO_PZ0,	/* pin 200 */
-	GPIO_PZ1,
-	GPIO_PZ2,
-	GPIO_PZ3,
-	GPIO_PZ4,
-	GPIO_PZ5,
-	GPIO_PZ6,
-	GPIO_PZ7,
-	GPIO_PAA0,	/* pin 208 */
-	GPIO_PAA1,
-	GPIO_PAA2,
-	GPIO_PAA3,
-	GPIO_PAA4,
-	GPIO_PAA5,
-	GPIO_PAA6,
-	GPIO_PAA7,
-	GPIO_PBB0,	/* pin 216 */
-	GPIO_PBB1,
-	GPIO_PBB2,
-	GPIO_PBB3,
-	GPIO_PBB4,
-	GPIO_PBB5,
-	GPIO_PBB6,
-	GPIO_PBB7,	/* pin 223 */
-};
-
 #endif	/* TEGRA20_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h b/arch/arm/include/asm/arch-tegra210/gpio.h
index 71af423..389d5b6 100644
--- a/arch/arm/include/asm/arch-tegra210/gpio.h
+++ b/arch/arm/include/asm/arch-tegra210/gpio.h
@@ -41,263 +41,4 @@ struct gpio_ctlr {
 	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
 };
 
-enum gpio_pin {
-	GPIO_PA0 = 0,	/* pin 0 */
-	GPIO_PA1,
-	GPIO_PA2,
-	GPIO_PA3,
-	GPIO_PA4,
-	GPIO_PA5,
-	GPIO_PA6,
-	GPIO_PA7,
-	GPIO_PB0,	/* pin 8 */
-	GPIO_PB1,
-	GPIO_PB2,
-	GPIO_PB3,
-	GPIO_PB4,
-	GPIO_PB5,
-	GPIO_PB6,
-	GPIO_PB7,
-	GPIO_PC0,	/* pin 16 */
-	GPIO_PC1,
-	GPIO_PC2,
-	GPIO_PC3,
-	GPIO_PC4,
-	GPIO_PC5,
-	GPIO_PC6,
-	GPIO_PC7,
-	GPIO_PD0,	/* pin 24 */
-	GPIO_PD1,
-	GPIO_PD2,
-	GPIO_PD3,
-	GPIO_PD4,
-	GPIO_PD5,
-	GPIO_PD6,
-	GPIO_PD7,
-	GPIO_PE0,	/* pin 32 */
-	GPIO_PE1,
-	GPIO_PE2,
-	GPIO_PE3,
-	GPIO_PE4,
-	GPIO_PE5,
-	GPIO_PE6,
-	GPIO_PE7,
-	GPIO_PF0,	/* pin 40 */
-	GPIO_PF1,
-	GPIO_PF2,
-	GPIO_PF3,
-	GPIO_PF4,
-	GPIO_PF5,
-	GPIO_PF6,
-	GPIO_PF7,
-	GPIO_PG0,	/* pin 48 */
-	GPIO_PG1,
-	GPIO_PG2,
-	GPIO_PG3,
-	GPIO_PG4,
-	GPIO_PG5,
-	GPIO_PG6,
-	GPIO_PG7,
-	GPIO_PH0,	/* pin 56 */
-	GPIO_PH1,
-	GPIO_PH2,
-	GPIO_PH3,
-	GPIO_PH4,
-	GPIO_PH5,
-	GPIO_PH6,
-	GPIO_PH7,
-	GPIO_PI0,	/* pin 64 */
-	GPIO_PI1,
-	GPIO_PI2,
-	GPIO_PI3,
-	GPIO_PI4,
-	GPIO_PI5,
-	GPIO_PI6,
-	GPIO_PI7,
-	GPIO_PJ0,	/* pin 72 */
-	GPIO_PJ1,
-	GPIO_PJ2,
-	GPIO_PJ3,
-	GPIO_PJ4,
-	GPIO_PJ5,
-	GPIO_PJ6,
-	GPIO_PJ7,
-	GPIO_PK0,	/* pin 80 */
-	GPIO_PK1,
-	GPIO_PK2,
-	GPIO_PK3,
-	GPIO_PK4,
-	GPIO_PK5,
-	GPIO_PK6,
-	GPIO_PK7,
-	GPIO_PL0,	/* pin 88 */
-	GPIO_PL1,
-	GPIO_PL2,
-	GPIO_PL3,
-	GPIO_PL4,
-	GPIO_PL5,
-	GPIO_PL6,
-	GPIO_PL7,
-	GPIO_PM0,	/* pin 96 */
-	GPIO_PM1,
-	GPIO_PM2,
-	GPIO_PM3,
-	GPIO_PM4,
-	GPIO_PM5,
-	GPIO_PM6,
-	GPIO_PM7,
-	GPIO_PN0,	/* pin 104 */
-	GPIO_PN1,
-	GPIO_PN2,
-	GPIO_PN3,
-	GPIO_PN4,
-	GPIO_PN5,
-	GPIO_PN6,
-	GPIO_PN7,
-	GPIO_PO0,	/* pin 112 */
-	GPIO_PO1,
-	GPIO_PO2,
-	GPIO_PO3,
-	GPIO_PO4,
-	GPIO_PO5,
-	GPIO_PO6,
-	GPIO_PO7,
-	GPIO_PP0,	/* pin 120 */
-	GPIO_PP1,
-	GPIO_PP2,
-	GPIO_PP3,
-	GPIO_PP4,
-	GPIO_PP5,
-	GPIO_PP6,
-	GPIO_PP7,
-	GPIO_PQ0,	/* pin 128 */
-	GPIO_PQ1,
-	GPIO_PQ2,
-	GPIO_PQ3,
-	GPIO_PQ4,
-	GPIO_PQ5,
-	GPIO_PQ6,
-	GPIO_PQ7,
-	GPIO_PR0,	/* pin 136 */
-	GPIO_PR1,
-	GPIO_PR2,
-	GPIO_PR3,
-	GPIO_PR4,
-	GPIO_PR5,
-	GPIO_PR6,
-	GPIO_PR7,
-	GPIO_PS0,	/* pin 144 */
-	GPIO_PS1,
-	GPIO_PS2,
-	GPIO_PS3,
-	GPIO_PS4,
-	GPIO_PS5,
-	GPIO_PS6,
-	GPIO_PS7,
-	GPIO_PT0,	/* pin 152 */
-	GPIO_PT1,
-	GPIO_PT2,
-	GPIO_PT3,
-	GPIO_PT4,
-	GPIO_PT5,
-	GPIO_PT6,
-	GPIO_PT7,
-	GPIO_PU0,	/* pin 160 */
-	GPIO_PU1,
-	GPIO_PU2,
-	GPIO_PU3,
-	GPIO_PU4,
-	GPIO_PU5,
-	GPIO_PU6,
-	GPIO_PU7,
-	GPIO_PV0,	/* pin 168 */
-	GPIO_PV1,
-	GPIO_PV2,
-	GPIO_PV3,
-	GPIO_PV4,
-	GPIO_PV5,
-	GPIO_PV6,
-	GPIO_PV7,
-	GPIO_PW0,	/* pin 176 */
-	GPIO_PW1,
-	GPIO_PW2,
-	GPIO_PW3,
-	GPIO_PW4,
-	GPIO_PW5,
-	GPIO_PW6,
-	GPIO_PW7,
-	GPIO_PX0,	/* pin 184 */
-	GPIO_PX1,
-	GPIO_PX2,
-	GPIO_PX3,
-	GPIO_PX4,
-	GPIO_PX5,
-	GPIO_PX6,
-	GPIO_PX7,
-	GPIO_PY0,	/* pin 192 */
-	GPIO_PY1,
-	GPIO_PY2,
-	GPIO_PY3,
-	GPIO_PY4,
-	GPIO_PY5,
-	GPIO_PY6,
-	GPIO_PY7,
-	GPIO_PZ0,	/* pin 200 */
-	GPIO_PZ1,
-	GPIO_PZ2,
-	GPIO_PZ3,
-	GPIO_PZ4,
-	GPIO_PZ5,
-	GPIO_PZ6,
-	GPIO_PZ7,
-	GPIO_PAA0,	/* pin 208 */
-	GPIO_PAA1,
-	GPIO_PAA2,
-	GPIO_PAA3,
-	GPIO_PAA4,
-	GPIO_PAA5,
-	GPIO_PAA6,
-	GPIO_PAA7,
-	GPIO_PBB0,	/* pin 216 */
-	GPIO_PBB1,
-	GPIO_PBB2,
-	GPIO_PBB3,
-	GPIO_PBB4,
-	GPIO_PBB5,
-	GPIO_PBB6,
-	GPIO_PBB7,
-	GPIO_PCC0,	/* pin 224 */
-	GPIO_PCC1,
-	GPIO_PCC2,
-	GPIO_PCC3,
-	GPIO_PCC4,
-	GPIO_PCC5,
-	GPIO_PCC6,
-	GPIO_PCC7,
-	GPIO_PDD0,	/* pin 232 */
-	GPIO_PDD1,
-	GPIO_PDD2,
-	GPIO_PDD3,
-	GPIO_PDD4,
-	GPIO_PDD5,
-	GPIO_PDD6,
-	GPIO_PDD7,
-	GPIO_PEE0,	/* pin 240 */
-	GPIO_PEE1,
-	GPIO_PEE2,
-	GPIO_PEE3,
-	GPIO_PEE4,
-	GPIO_PEE5,
-	GPIO_PEE6,
-	GPIO_PEE7,
-	GPIO_PFF0,	/* pin 248 */
-	GPIO_PFF1,
-	GPIO_PFF2,
-	GPIO_PFF3,
-	GPIO_PFF4,
-	GPIO_PFF5,
-	GPIO_PFF6,
-	GPIO_PFF7,	/* pin 255 */
-};
-
 #endif	/* _TEGRA210_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h
index d2c6c78..e384327 100644
--- a/arch/arm/include/asm/arch-tegra30/gpio.h
+++ b/arch/arm/include/asm/arch-tegra30/gpio.h
@@ -40,255 +40,4 @@ struct gpio_ctlr {
 	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
 };
 
-enum gpio_pin {
-	GPIO_PA0 = 0,	/* pin 0 */
-	GPIO_PA1,
-	GPIO_PA2,
-	GPIO_PA3,
-	GPIO_PA4,
-	GPIO_PA5,
-	GPIO_PA6,
-	GPIO_PA7,
-	GPIO_PB0,	/* pin 8 */
-	GPIO_PB1,
-	GPIO_PB2,
-	GPIO_PB3,
-	GPIO_PB4,
-	GPIO_PB5,
-	GPIO_PB6,
-	GPIO_PB7,
-	GPIO_PC0,	/* pin 16 */
-	GPIO_PC1,
-	GPIO_PC2,
-	GPIO_PC3,
-	GPIO_PC4,
-	GPIO_PC5,
-	GPIO_PC6,
-	GPIO_PC7,
-	GPIO_PD0,	/* pin 24 */
-	GPIO_PD1,
-	GPIO_PD2,
-	GPIO_PD3,
-	GPIO_PD4,
-	GPIO_PD5,
-	GPIO_PD6,
-	GPIO_PD7,
-	GPIO_PE0,	/* pin 32 */
-	GPIO_PE1,
-	GPIO_PE2,
-	GPIO_PE3,
-	GPIO_PE4,
-	GPIO_PE5,
-	GPIO_PE6,
-	GPIO_PE7,
-	GPIO_PF0,	/* pin 40 */
-	GPIO_PF1,
-	GPIO_PF2,
-	GPIO_PF3,
-	GPIO_PF4,
-	GPIO_PF5,
-	GPIO_PF6,
-	GPIO_PF7,
-	GPIO_PG0,	/* pin 48 */
-	GPIO_PG1,
-	GPIO_PG2,
-	GPIO_PG3,
-	GPIO_PG4,
-	GPIO_PG5,
-	GPIO_PG6,
-	GPIO_PG7,
-	GPIO_PH0,	/* pin 56 */
-	GPIO_PH1,
-	GPIO_PH2,
-	GPIO_PH3,
-	GPIO_PH4,
-	GPIO_PH5,
-	GPIO_PH6,
-	GPIO_PH7,
-	GPIO_PI0,	/* pin 64 */
-	GPIO_PI1,
-	GPIO_PI2,
-	GPIO_PI3,
-	GPIO_PI4,
-	GPIO_PI5,
-	GPIO_PI6,
-	GPIO_PI7,
-	GPIO_PJ0,	/* pin 72 */
-	GPIO_PJ1,
-	GPIO_PJ2,
-	GPIO_PJ3,
-	GPIO_PJ4,
-	GPIO_PJ5,
-	GPIO_PJ6,
-	GPIO_PJ7,
-	GPIO_PK0,	/* pin 80 */
-	GPIO_PK1,
-	GPIO_PK2,
-	GPIO_PK3,
-	GPIO_PK4,
-	GPIO_PK5,
-	GPIO_PK6,
-	GPIO_PK7,
-	GPIO_PL0,	/* pin 88 */
-	GPIO_PL1,
-	GPIO_PL2,
-	GPIO_PL3,
-	GPIO_PL4,
-	GPIO_PL5,
-	GPIO_PL6,
-	GPIO_PL7,
-	GPIO_PM0,	/* pin 96 */
-	GPIO_PM1,
-	GPIO_PM2,
-	GPIO_PM3,
-	GPIO_PM4,
-	GPIO_PM5,
-	GPIO_PM6,
-	GPIO_PM7,
-	GPIO_PN0,	/* pin 104 */
-	GPIO_PN1,
-	GPIO_PN2,
-	GPIO_PN3,
-	GPIO_PN4,
-	GPIO_PN5,
-	GPIO_PN6,
-	GPIO_PN7,
-	GPIO_PO0,	/* pin 112 */
-	GPIO_PO1,
-	GPIO_PO2,
-	GPIO_PO3,
-	GPIO_PO4,
-	GPIO_PO5,
-	GPIO_PO6,
-	GPIO_PO7,
-	GPIO_PP0,	/* pin 120 */
-	GPIO_PP1,
-	GPIO_PP2,
-	GPIO_PP3,
-	GPIO_PP4,
-	GPIO_PP5,
-	GPIO_PP6,
-	GPIO_PP7,
-	GPIO_PQ0,	/* pin 128 */
-	GPIO_PQ1,
-	GPIO_PQ2,
-	GPIO_PQ3,
-	GPIO_PQ4,
-	GPIO_PQ5,
-	GPIO_PQ6,
-	GPIO_PQ7,
-	GPIO_PR0,	/* pin 136 */
-	GPIO_PR1,
-	GPIO_PR2,
-	GPIO_PR3,
-	GPIO_PR4,
-	GPIO_PR5,
-	GPIO_PR6,
-	GPIO_PR7,
-	GPIO_PS0,	/* pin 144 */
-	GPIO_PS1,
-	GPIO_PS2,
-	GPIO_PS3,
-	GPIO_PS4,
-	GPIO_PS5,
-	GPIO_PS6,
-	GPIO_PS7,
-	GPIO_PT0,	/* pin 152 */
-	GPIO_PT1,
-	GPIO_PT2,
-	GPIO_PT3,
-	GPIO_PT4,
-	GPIO_PT5,
-	GPIO_PT6,
-	GPIO_PT7,
-	GPIO_PU0,	/* pin 160 */
-	GPIO_PU1,
-	GPIO_PU2,
-	GPIO_PU3,
-	GPIO_PU4,
-	GPIO_PU5,
-	GPIO_PU6,
-	GPIO_PU7,
-	GPIO_PV0,	/* pin 168 */
-	GPIO_PV1,
-	GPIO_PV2,
-	GPIO_PV3,
-	GPIO_PV4,
-	GPIO_PV5,
-	GPIO_PV6,
-	GPIO_PV7,
-	GPIO_PW0,	/* pin 176 */
-	GPIO_PW1,
-	GPIO_PW2,
-	GPIO_PW3,
-	GPIO_PW4,
-	GPIO_PW5,
-	GPIO_PW6,
-	GPIO_PW7,
-	GPIO_PX0,	/* pin 184 */
-	GPIO_PX1,
-	GPIO_PX2,
-	GPIO_PX3,
-	GPIO_PX4,
-	GPIO_PX5,
-	GPIO_PX6,
-	GPIO_PX7,
-	GPIO_PY0,	/* pin 192 */
-	GPIO_PY1,
-	GPIO_PY2,
-	GPIO_PY3,
-	GPIO_PY4,
-	GPIO_PY5,
-	GPIO_PY6,
-	GPIO_PY7,
-	GPIO_PZ0,	/* pin 200 */
-	GPIO_PZ1,
-	GPIO_PZ2,
-	GPIO_PZ3,
-	GPIO_PZ4,
-	GPIO_PZ5,
-	GPIO_PZ6,
-	GPIO_PZ7,
-	GPIO_PAA0,	/* pin 208 */
-	GPIO_PAA1,
-	GPIO_PAA2,
-	GPIO_PAA3,
-	GPIO_PAA4,
-	GPIO_PAA5,
-	GPIO_PAA6,
-	GPIO_PAA7,
-	GPIO_PBB0,	/* pin 216 */
-	GPIO_PBB1,
-	GPIO_PBB2,
-	GPIO_PBB3,
-	GPIO_PBB4,
-	GPIO_PBB5,
-	GPIO_PBB6,
-	GPIO_PBB7,
-	GPIO_PCC0,	/* pin 224 */
-	GPIO_PCC1,
-	GPIO_PCC2,
-	GPIO_PCC3,
-	GPIO_PCC4,
-	GPIO_PCC5,
-	GPIO_PCC6,
-	GPIO_PCC7,
-	GPIO_PDD0,	/* pin 232 */
-	GPIO_PDD1,
-	GPIO_PDD2,
-	GPIO_PDD3,
-	GPIO_PDD4,
-	GPIO_PDD5,
-	GPIO_PDD6,
-	GPIO_PDD7,
-	GPIO_PEE0,	/* pin 240 */
-	GPIO_PEE1,
-	GPIO_PEE2,
-	GPIO_PEE3,
-	GPIO_PEE4,
-	GPIO_PEE5,
-	GPIO_PEE6,
-	GPIO_PEE7,	/* pin 247 */
-};
-
 #endif	/* _TEGRA30_GPIO_H_ */
diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c
index 1704627..106be9b 100644
--- a/board/avionic-design/common/tamonten-ng.c
+++ b/board/avionic-design/common/tamonten-ng.c
@@ -42,12 +42,12 @@ void pinmux_init(void)
 void gpio_early_init(void)
 {
 	/* Turn on the alive signal */
-	gpio_request(GPIO_PV2, "ALIVE");
-	gpio_direction_output(GPIO_PV2, 1);
+	gpio_request(TEGRA_GPIO(V, 2), "ALIVE");
+	gpio_direction_output(TEGRA_GPIO(V, 2), 1);
 
 	/* Remove the reset on the external periph */
-	gpio_request(GPIO_PI4, "nRST_PERIPH");
-	gpio_direction_output(GPIO_PI4, 1);
+	gpio_request(TEGRA_GPIO(I, 4), "nRST_PERIPH");
+	gpio_direction_output(TEGRA_GPIO(I, 4), 1);
 }
 
 void pmu_write(uchar reg, uchar data)
@@ -73,8 +73,8 @@ void board_sdmmc_voltage_init(void)
 	pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300));
 
 	/* Switch the power on */
-	gpio_request(GPIO_PJ2, "EN_3V3_EMMC");
-	gpio_direction_output(GPIO_PJ2, 1);
+	gpio_request(TEGRA_GPIO(J, 2), "EN_3V3_EMMC");
+	gpio_direction_output(TEGRA_GPIO(J, 2), 1);
 }
 
 /*
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c
index 9c86779..4fb36a2 100644
--- a/board/avionic-design/common/tamonten.c
+++ b/board/avionic-design/common/tamonten.c
@@ -23,8 +23,8 @@
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 void gpio_early_init(void)
 {
-	gpio_request(GPIO_PI4, NULL);
-	gpio_direction_output(GPIO_PI4, 1);
+	gpio_request(TEGRA_GPIO(I, 4), NULL);
+	gpio_direction_output(TEGRA_GPIO(I, 4), 1);
 }
 #endif
 
diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c
index ba15e2e..f04f843 100644
--- a/board/nvidia/cardhu/cardhu.c
+++ b/board/nvidia/cardhu/cardhu.c
@@ -110,11 +110,11 @@ int tegra_pcie_board_init(void)
 	}
 
 	/* GPIO: PEX = 3.3V */
-	err = gpio_request(GPIO_PL7, "PEX");
+	err = gpio_request(TEGRA_GPIO(L, 7), "PEX");
 	if (err < 0)
 		return err;
 
-	gpio_direction_output(GPIO_PL7, 1);
+	gpio_direction_output(TEGRA_GPIO(L, 7), 1);
 
 	/* TPS659110: LDO2_REG = 1.05V, ACTIVE */
 	data[0] = 0x15;
diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
index 7eb1e6c..7955ca5 100644
--- a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
+++ b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
@@ -15,71 +15,71 @@
 #ifndef _PINMUX_CONFIG_E2220_1170_H_
 #define _PINMUX_CONFIG_E2220_1170_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config e2220_1170_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A5,   IN),
-	GPIO_INIT(A6,   IN),
-	GPIO_INIT(B4,   IN),
-	GPIO_INIT(E6,   IN),
-	GPIO_INIT(G2,   OUT0),
-	GPIO_INIT(G3,   OUT0),
-	GPIO_INIT(H0,   OUT0),
-	GPIO_INIT(H1,   OUT0),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H3,   OUT0),
-	GPIO_INIT(H4,   OUT0),
-	GPIO_INIT(H5,   IN),
-	GPIO_INIT(H6,   OUT0),
-	GPIO_INIT(H7,   OUT0),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I2,   OUT0),
-	GPIO_INIT(I3,   OUT0),
-	GPIO_INIT(K0,   IN),
-	GPIO_INIT(K1,   OUT0),
-	GPIO_INIT(K2,   OUT0),
-	GPIO_INIT(K3,   OUT0),
-	GPIO_INIT(K4,   IN),
-	GPIO_INIT(K5,   OUT0),
-	GPIO_INIT(K6,   IN),
-	GPIO_INIT(K7,   OUT0),
-	GPIO_INIT(L0,   OUT0),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S5,   OUT0),
-	GPIO_INIT(S6,   OUT0),
-	GPIO_INIT(S7,   OUT0),
-	GPIO_INIT(T0,   OUT0),
-	GPIO_INIT(T1,   OUT0),
-	GPIO_INIT(V1,   OUT0),
-	GPIO_INIT(V2,   OUT0),
-	GPIO_INIT(V3,   IN),
-	GPIO_INIT(V5,   OUT0),
-	GPIO_INIT(V6,   OUT0),
-	GPIO_INIT(X0,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X2,   IN),
-	GPIO_INIT(X3,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X5,   IN),
-	GPIO_INIT(X6,   IN),
-	GPIO_INIT(X7,   IN),
-	GPIO_INIT(Y0,   IN),
-	GPIO_INIT(Y1,   IN),
-	GPIO_INIT(Z0,   IN),
-	GPIO_INIT(Z4,   OUT0),
-	GPIO_INIT(BB2,  OUT0),
-	GPIO_INIT(BB3,  OUT0),
-	GPIO_INIT(BB4,  IN),
-	GPIO_INIT(CC1,  IN),
-	GPIO_INIT(CC5,  OUT0),
-	GPIO_INIT(CC6,  IN),
-	GPIO_INIT(CC7,  OUT0),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    5,   IN),
+	GPIO_INIT(A,    6,   IN),
+	GPIO_INIT(B,    4,   IN),
+	GPIO_INIT(E,    6,   IN),
+	GPIO_INIT(G,    2,   OUT0),
+	GPIO_INIT(G,    3,   OUT0),
+	GPIO_INIT(H,    0,   OUT0),
+	GPIO_INIT(H,    1,   OUT0),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    3,   OUT0),
+	GPIO_INIT(H,    4,   OUT0),
+	GPIO_INIT(H,    5,   IN),
+	GPIO_INIT(H,    6,   OUT0),
+	GPIO_INIT(H,    7,   OUT0),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    2,   OUT0),
+	GPIO_INIT(I,    3,   OUT0),
+	GPIO_INIT(K,    0,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   OUT0),
+	GPIO_INIT(K,    3,   OUT0),
+	GPIO_INIT(K,    4,   IN),
+	GPIO_INIT(K,    5,   OUT0),
+	GPIO_INIT(K,    6,   IN),
+	GPIO_INIT(K,    7,   OUT0),
+	GPIO_INIT(L,    0,   OUT0),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    5,   OUT0),
+	GPIO_INIT(S,    6,   OUT0),
+	GPIO_INIT(S,    7,   OUT0),
+	GPIO_INIT(T,    0,   OUT0),
+	GPIO_INIT(T,    1,   OUT0),
+	GPIO_INIT(V,    1,   OUT0),
+	GPIO_INIT(V,    2,   OUT0),
+	GPIO_INIT(V,    3,   IN),
+	GPIO_INIT(V,    5,   OUT0),
+	GPIO_INIT(V,    6,   OUT0),
+	GPIO_INIT(X,    0,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    2,   IN),
+	GPIO_INIT(X,    3,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    5,   IN),
+	GPIO_INIT(X,    6,   IN),
+	GPIO_INIT(X,    7,   IN),
+	GPIO_INIT(Y,    0,   IN),
+	GPIO_INIT(Y,    1,   IN),
+	GPIO_INIT(Z,    0,   IN),
+	GPIO_INIT(Z,    4,   OUT0),
+	GPIO_INIT(BB,   2,   OUT0),
+	GPIO_INIT(BB,   3,   OUT0),
+	GPIO_INIT(BB,   4,   IN),
+	GPIO_INIT(CC,   1,   IN),
+	GPIO_INIT(CC,   5,   OUT0),
+	GPIO_INIT(CC,   6,   IN),
+	GPIO_INIT(CC,   7,   OUT0),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
index 00e0cdc..01237db 100644
--- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
+++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
@@ -15,63 +15,63 @@
 #ifndef _PINMUX_CONFIG_JETSON_TK1_H_
 #define _PINMUX_CONFIG_JETSON_TK1_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(G1,   IN),
-	GPIO_INIT(G2,   IN),
-	GPIO_INIT(G3,   IN),
-	GPIO_INIT(G4,   IN),
-	GPIO_INIT(H2,   OUT0),
-	GPIO_INIT(H4,   IN),
-	GPIO_INIT(H7,   IN),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I6,   IN),
-	GPIO_INIT(J0,   IN),
-	GPIO_INIT(K1,   OUT0),
-	GPIO_INIT(K2,   IN),
-	GPIO_INIT(K4,   OUT0),
-	GPIO_INIT(K6,   OUT0),
-	GPIO_INIT(N7,   IN),
-	GPIO_INIT(O1,   IN),
-	GPIO_INIT(O4,   IN),
-	GPIO_INIT(P2,   OUT0),
-	GPIO_INIT(Q0,   IN),
-	GPIO_INIT(Q3,   IN),
-	GPIO_INIT(Q5,   IN),
-	GPIO_INIT(R0,   OUT0),
-	GPIO_INIT(R2,   OUT0),
-	GPIO_INIT(R4,   IN),
-	GPIO_INIT(R7,   IN),
-	GPIO_INIT(S7,   IN),
-	GPIO_INIT(T0,   OUT0),
-	GPIO_INIT(T1,   IN),
-	GPIO_INIT(U0,   IN),
-	GPIO_INIT(U1,   IN),
-	GPIO_INIT(U2,   IN),
-	GPIO_INIT(U3,   IN),
-	GPIO_INIT(U4,   IN),
-	GPIO_INIT(U5,   IN),
-	GPIO_INIT(U6,   IN),
-	GPIO_INIT(V0,   IN),
-	GPIO_INIT(V1,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X7,   OUT0),
-	GPIO_INIT(BB3,  OUT0),
-	GPIO_INIT(BB5,  OUT0),
-	GPIO_INIT(BB6,  OUT0),
-	GPIO_INIT(BB7,  OUT0),
-	GPIO_INIT(CC1,  IN),
-	GPIO_INIT(CC2,  IN),
-	GPIO_INIT(EE2,  OUT1),
+	/*        port, pin, init_val */
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    1,   IN),
+	GPIO_INIT(G,    2,   IN),
+	GPIO_INIT(G,    3,   IN),
+	GPIO_INIT(G,    4,   IN),
+	GPIO_INIT(H,    2,   OUT0),
+	GPIO_INIT(H,    4,   IN),
+	GPIO_INIT(H,    7,   IN),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    4,   OUT0),
+	GPIO_INIT(K,    6,   OUT0),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(O,    1,   IN),
+	GPIO_INIT(O,    4,   IN),
+	GPIO_INIT(P,    2,   OUT0),
+	GPIO_INIT(Q,    0,   IN),
+	GPIO_INIT(Q,    3,   IN),
+	GPIO_INIT(Q,    5,   IN),
+	GPIO_INIT(R,    0,   OUT0),
+	GPIO_INIT(R,    2,   OUT0),
+	GPIO_INIT(R,    4,   IN),
+	GPIO_INIT(R,    7,   IN),
+	GPIO_INIT(S,    7,   IN),
+	GPIO_INIT(T,    0,   OUT0),
+	GPIO_INIT(T,    1,   IN),
+	GPIO_INIT(U,    0,   IN),
+	GPIO_INIT(U,    1,   IN),
+	GPIO_INIT(U,    2,   IN),
+	GPIO_INIT(U,    3,   IN),
+	GPIO_INIT(U,    4,   IN),
+	GPIO_INIT(U,    5,   IN),
+	GPIO_INIT(U,    6,   IN),
+	GPIO_INIT(V,    0,   IN),
+	GPIO_INIT(V,    1,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    7,   OUT0),
+	GPIO_INIT(BB,   3,   OUT0),
+	GPIO_INIT(BB,   5,   OUT0),
+	GPIO_INIT(BB,   6,   OUT0),
+	GPIO_INIT(BB,   7,   OUT0),
+	GPIO_INIT(CC,   1,   IN),
+	GPIO_INIT(CC,   2,   IN),
+	GPIO_INIT(EE,   2,   OUT1),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c
index ba96401..8f68ae9 100644
--- a/board/nvidia/nyan-big/nyan-big.c
+++ b/board/nvidia/nyan-big/nyan-big.c
@@ -36,8 +36,9 @@ void pinmux_init(void)
 
 int tegra_board_id(void)
 {
-	static const int vector[] = {GPIO_PQ3, GPIO_PT1, GPIO_PX1,
-					GPIO_PX4, -1};
+	static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1),
+					TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4),
+					-1};
 
 	gpio_claim_vector(vector, "board_id%d");
 	return gpio_get_values_as_int(vector);
diff --git a/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/board/nvidia/nyan-big/pinmux-config-nyan-big.h
index dca0171..fd7f1d1 100644
--- a/board/nvidia/nyan-big/pinmux-config-nyan-big.h
+++ b/board/nvidia/nyan-big/pinmux-config-nyan-big.h
@@ -15,59 +15,59 @@
 #ifndef _PINMUX_CONFIG_NYAN_BIG_H_
 #define _PINMUX_CONFIG_NYAN_BIG_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config nyan_big_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A0,   IN),
-	GPIO_INIT(C7,   IN),
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(G1,   IN),
-	GPIO_INIT(G2,   IN),
-	GPIO_INIT(G3,   IN),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H4,   IN),
-	GPIO_INIT(H6,   IN),
-	GPIO_INIT(H7,   OUT1),
-	GPIO_INIT(I0,   IN),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I5,   OUT1),
-	GPIO_INIT(I6,   IN),
-	GPIO_INIT(I7,   IN),
-	GPIO_INIT(J0,   IN),
-	GPIO_INIT(J7,   IN),
-	GPIO_INIT(K1,   OUT0),
-	GPIO_INIT(K2,   IN),
-	GPIO_INIT(K4,   OUT0),
-	GPIO_INIT(K6,   OUT0),
-	GPIO_INIT(K7,   IN),
-	GPIO_INIT(N7,   IN),
-	GPIO_INIT(P2,   OUT0),
-	GPIO_INIT(Q0,   IN),
-	GPIO_INIT(Q2,   IN),
-	GPIO_INIT(Q3,   IN),
-	GPIO_INIT(Q6,   IN),
-	GPIO_INIT(Q7,   IN),
-	GPIO_INIT(R0,   OUT0),
-	GPIO_INIT(R1,   IN),
-	GPIO_INIT(R4,   IN),
-	GPIO_INIT(R7,   IN),
-	GPIO_INIT(S3,   OUT0),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S7,   IN),
-	GPIO_INIT(T1,   IN),
-	GPIO_INIT(U4,   IN),
-	GPIO_INIT(U5,   IN),
-	GPIO_INIT(U6,   IN),
-	GPIO_INIT(V0,   IN),
-	GPIO_INIT(W3,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X7,   OUT0),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    0,   IN),
+	GPIO_INIT(C,    7,   IN),
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    1,   IN),
+	GPIO_INIT(G,    2,   IN),
+	GPIO_INIT(G,    3,   IN),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    4,   IN),
+	GPIO_INIT(H,    6,   IN),
+	GPIO_INIT(H,    7,   OUT1),
+	GPIO_INIT(I,    0,   IN),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    5,   OUT1),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(I,    7,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(J,    7,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    4,   OUT0),
+	GPIO_INIT(K,    6,   OUT0),
+	GPIO_INIT(K,    7,   IN),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(P,    2,   OUT0),
+	GPIO_INIT(Q,    0,   IN),
+	GPIO_INIT(Q,    2,   IN),
+	GPIO_INIT(Q,    3,   IN),
+	GPIO_INIT(Q,    6,   IN),
+	GPIO_INIT(Q,    7,   IN),
+	GPIO_INIT(R,    0,   OUT0),
+	GPIO_INIT(R,    1,   IN),
+	GPIO_INIT(R,    4,   IN),
+	GPIO_INIT(R,    7,   IN),
+	GPIO_INIT(S,    3,   OUT0),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    7,   IN),
+	GPIO_INIT(T,    1,   IN),
+	GPIO_INIT(U,    4,   IN),
+	GPIO_INIT(U,    5,   IN),
+	GPIO_INIT(U,    6,   IN),
+	GPIO_INIT(V,    0,   IN),
+	GPIO_INIT(W,    3,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    7,   OUT0),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
diff --git a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h
index 35706b4..24acbcc 100644
--- a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h
+++ b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h
@@ -15,62 +15,62 @@
 #ifndef _PINMUX_CONFIG_P2371_0000_H_
 #define _PINMUX_CONFIG_P2371_0000_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config p2371_0000_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A5,   IN),
-	GPIO_INIT(E4,   OUT0),
-	GPIO_INIT(E6,   IN),
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(G3,   OUT0),
-	GPIO_INIT(H0,   OUT0),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H3,   OUT0),
-	GPIO_INIT(H4,   OUT0),
-	GPIO_INIT(H5,   IN),
-	GPIO_INIT(H6,   OUT0),
-	GPIO_INIT(H7,   OUT0),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I2,   OUT0),
-	GPIO_INIT(I3,   OUT0),
-	GPIO_INIT(K4,   IN),
-	GPIO_INIT(K5,   OUT0),
-	GPIO_INIT(K6,   IN),
-	GPIO_INIT(K7,   OUT0),
-	GPIO_INIT(L0,   OUT0),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S5,   OUT0),
-	GPIO_INIT(S6,   OUT0),
-	GPIO_INIT(S7,   OUT0),
-	GPIO_INIT(T0,   OUT0),
-	GPIO_INIT(T1,   OUT0),
-	GPIO_INIT(V1,   OUT0),
-	GPIO_INIT(V2,   OUT0),
-	GPIO_INIT(V5,   OUT0),
-	GPIO_INIT(V6,   OUT0),
-	GPIO_INIT(V7,   OUT1),
-	GPIO_INIT(X0,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X2,   IN),
-	GPIO_INIT(X3,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X5,   IN),
-	GPIO_INIT(X6,   IN),
-	GPIO_INIT(X7,   IN),
-	GPIO_INIT(Y1,   IN),
-	GPIO_INIT(Z0,   IN),
-	GPIO_INIT(Z4,   OUT0),
-	GPIO_INIT(BB2,  OUT0),
-	GPIO_INIT(BB3,  OUT0),
-	GPIO_INIT(CC1,  IN),
-	GPIO_INIT(CC6,  IN),
-	GPIO_INIT(CC7,  OUT0),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    5,   IN),
+	GPIO_INIT(E,    4,   OUT0),
+	GPIO_INIT(E,    6,   IN),
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    3,   OUT0),
+	GPIO_INIT(H,    0,   OUT0),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    3,   OUT0),
+	GPIO_INIT(H,    4,   OUT0),
+	GPIO_INIT(H,    5,   IN),
+	GPIO_INIT(H,    6,   OUT0),
+	GPIO_INIT(H,    7,   OUT0),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    2,   OUT0),
+	GPIO_INIT(I,    3,   OUT0),
+	GPIO_INIT(K,    4,   IN),
+	GPIO_INIT(K,    5,   OUT0),
+	GPIO_INIT(K,    6,   IN),
+	GPIO_INIT(K,    7,   OUT0),
+	GPIO_INIT(L,    0,   OUT0),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    5,   OUT0),
+	GPIO_INIT(S,    6,   OUT0),
+	GPIO_INIT(S,    7,   OUT0),
+	GPIO_INIT(T,    0,   OUT0),
+	GPIO_INIT(T,    1,   OUT0),
+	GPIO_INIT(V,    1,   OUT0),
+	GPIO_INIT(V,    2,   OUT0),
+	GPIO_INIT(V,    5,   OUT0),
+	GPIO_INIT(V,    6,   OUT0),
+	GPIO_INIT(V,    7,   OUT1),
+	GPIO_INIT(X,    0,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    2,   IN),
+	GPIO_INIT(X,    3,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    5,   IN),
+	GPIO_INIT(X,    6,   IN),
+	GPIO_INIT(X,    7,   IN),
+	GPIO_INIT(Y,    1,   IN),
+	GPIO_INIT(Z,    0,   IN),
+	GPIO_INIT(Z,    4,   OUT0),
+	GPIO_INIT(BB,   2,   OUT0),
+	GPIO_INIT(BB,   3,   OUT0),
+	GPIO_INIT(CC,   1,   IN),
+	GPIO_INIT(CC,   6,   IN),
+	GPIO_INIT(CC,   7,   OUT0),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
diff --git a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
index d5be6ec..601728e 100644
--- a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
+++ b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
@@ -15,73 +15,73 @@
 #ifndef _PINMUX_CONFIG_P2371_2180_H_
 #define _PINMUX_CONFIG_P2371_2180_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config p2371_2180_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A5,   IN),
-	GPIO_INIT(B0,   IN),
-	GPIO_INIT(B1,   IN),
-	GPIO_INIT(B2,   IN),
-	GPIO_INIT(B3,   IN),
-	GPIO_INIT(C0,   IN),
-	GPIO_INIT(C1,   IN),
-	GPIO_INIT(C2,   IN),
-	GPIO_INIT(C3,   IN),
-	GPIO_INIT(C4,   IN),
-	GPIO_INIT(E4,   IN),
-	GPIO_INIT(E5,   IN),
-	GPIO_INIT(E6,   IN),
-	GPIO_INIT(H0,   OUT0),
-	GPIO_INIT(H1,   OUT0),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H3,   OUT0),
-	GPIO_INIT(H4,   OUT0),
-	GPIO_INIT(H5,   IN),
-	GPIO_INIT(H6,   IN),
-	GPIO_INIT(H7,   IN),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I2,   OUT0),
-	GPIO_INIT(K4,   IN),
-	GPIO_INIT(K5,   OUT0),
-	GPIO_INIT(K6,   IN),
-	GPIO_INIT(K7,   IN),
-	GPIO_INIT(L1,   IN),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S5,   OUT0),
-	GPIO_INIT(S6,   OUT0),
-	GPIO_INIT(S7,   OUT0),
-	GPIO_INIT(T0,   OUT0),
-	GPIO_INIT(T1,   OUT0),
-	GPIO_INIT(U2,   IN),
-	GPIO_INIT(U3,   IN),
-	GPIO_INIT(V1,   OUT0),
-	GPIO_INIT(V2,   OUT0),
-	GPIO_INIT(V3,   IN),
-	GPIO_INIT(V5,   OUT0),
-	GPIO_INIT(V6,   OUT0),
-	GPIO_INIT(X0,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X2,   IN),
-	GPIO_INIT(X3,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X5,   IN),
-	GPIO_INIT(X6,   IN),
-	GPIO_INIT(X7,   IN),
-	GPIO_INIT(Y0,   IN),
-	GPIO_INIT(Y1,   IN),
-	GPIO_INIT(Z0,   IN),
-	GPIO_INIT(Z2,   IN),
-	GPIO_INIT(Z3,   OUT0),
-	GPIO_INIT(BB0,  IN),
-	GPIO_INIT(BB2,  OUT0),
-	GPIO_INIT(BB3,  IN),
-	GPIO_INIT(CC1,  IN),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    5,   IN),
+	GPIO_INIT(B,    0,   IN),
+	GPIO_INIT(B,    1,   IN),
+	GPIO_INIT(B,    2,   IN),
+	GPIO_INIT(B,    3,   IN),
+	GPIO_INIT(C,    0,   IN),
+	GPIO_INIT(C,    1,   IN),
+	GPIO_INIT(C,    2,   IN),
+	GPIO_INIT(C,    3,   IN),
+	GPIO_INIT(C,    4,   IN),
+	GPIO_INIT(E,    4,   IN),
+	GPIO_INIT(E,    5,   IN),
+	GPIO_INIT(E,    6,   IN),
+	GPIO_INIT(H,    0,   OUT0),
+	GPIO_INIT(H,    1,   OUT0),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    3,   OUT0),
+	GPIO_INIT(H,    4,   OUT0),
+	GPIO_INIT(H,    5,   IN),
+	GPIO_INIT(H,    6,   IN),
+	GPIO_INIT(H,    7,   IN),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    2,   OUT0),
+	GPIO_INIT(K,    4,   IN),
+	GPIO_INIT(K,    5,   OUT0),
+	GPIO_INIT(K,    6,   IN),
+	GPIO_INIT(K,    7,   IN),
+	GPIO_INIT(L,    1,   IN),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    5,   OUT0),
+	GPIO_INIT(S,    6,   OUT0),
+	GPIO_INIT(S,    7,   OUT0),
+	GPIO_INIT(T,    0,   OUT0),
+	GPIO_INIT(T,    1,   OUT0),
+	GPIO_INIT(U,    2,   IN),
+	GPIO_INIT(U,    3,   IN),
+	GPIO_INIT(V,    1,   OUT0),
+	GPIO_INIT(V,    2,   OUT0),
+	GPIO_INIT(V,    3,   IN),
+	GPIO_INIT(V,    5,   OUT0),
+	GPIO_INIT(V,    6,   OUT0),
+	GPIO_INIT(X,    0,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    2,   IN),
+	GPIO_INIT(X,    3,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    5,   IN),
+	GPIO_INIT(X,    6,   IN),
+	GPIO_INIT(X,    7,   IN),
+	GPIO_INIT(Y,    0,   IN),
+	GPIO_INIT(Y,    1,   IN),
+	GPIO_INIT(Z,    0,   IN),
+	GPIO_INIT(Z,    2,   IN),
+	GPIO_INIT(Z,    3,   OUT0),
+	GPIO_INIT(BB,   0,   IN),
+	GPIO_INIT(BB,   2,   OUT0),
+	GPIO_INIT(BB,   3,   IN),
+	GPIO_INIT(CC,   1,   IN),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c
index d80a7d0..7ce656f 100644
--- a/board/nvidia/p2571/p2571.c
+++ b/board/nvidia/p2571/p2571.c
@@ -58,6 +58,6 @@ void pinmux_init(void)
 void start_cpu_fan(void)
 {
 	/* GPIO_PE4 is PS_VDD_FAN_ENABLE */
-	gpio_request(GPIO_PE4, "FAN_VDD");
-	gpio_direction_output(GPIO_PE4, 1);
+	gpio_request(TEGRA_GPIO(E, 4), "FAN_VDD");
+	gpio_direction_output(TEGRA_GPIO(E, 4), 1);
 }
diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h
index d323301..dd4228f 100644
--- a/board/nvidia/p2571/pinmux-config-p2571.h
+++ b/board/nvidia/p2571/pinmux-config-p2571.h
@@ -15,37 +15,37 @@
 #ifndef _PINMUX_CONFIG_P2571_H_
 #define _PINMUX_CONFIG_P2571_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config p2571_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A0,   IN),
-	GPIO_INIT(A5,   IN),
-	GPIO_INIT(D4,   IN),
-	GPIO_INIT(E4,   OUT0),
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(H0,   OUT0),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H3,   OUT0),
-	GPIO_INIT(H4,   OUT0),
-	GPIO_INIT(H5,   IN),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(V1,   OUT0),
-	GPIO_INIT(V6,   OUT1),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X6,   IN),
-	GPIO_INIT(X7,   IN),
-	GPIO_INIT(Y1,   IN),
-	GPIO_INIT(Z0,   IN),
-	GPIO_INIT(Z4,   OUT0),
-	GPIO_INIT(BB2,  OUT0),
-	GPIO_INIT(CC1,  IN),
-	GPIO_INIT(CC3,  IN),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    0,   IN),
+	GPIO_INIT(A,    5,   IN),
+	GPIO_INIT(D,    4,   IN),
+	GPIO_INIT(E,    4,   OUT0),
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(H,    0,   OUT0),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    3,   OUT0),
+	GPIO_INIT(H,    4,   OUT0),
+	GPIO_INIT(H,    5,   IN),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(V,    1,   OUT0),
+	GPIO_INIT(V,    6,   OUT1),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    6,   IN),
+	GPIO_INIT(X,    7,   IN),
+	GPIO_INIT(Y,    1,   IN),
+	GPIO_INIT(Z,    0,   IN),
+	GPIO_INIT(Z,    4,   OUT0),
+	GPIO_INIT(BB,   2,   OUT0),
+	GPIO_INIT(CC,   1,   IN),
+	GPIO_INIT(CC,   3,   IN),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 2d07001..fc9c1c9 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -20,8 +20,8 @@
 void gpio_early_init_uart(void)
 {
 	/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
-	gpio_request(GPIO_PI3, "uart_en");
-	gpio_direction_output(GPIO_PI3, 0);
+	gpio_request(TEGRA_GPIO(I, 3), "uart_en");
+	gpio_direction_output(TEGRA_GPIO(I, 3), 0);
 }
 #endif
 
diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h
index fb444b3..59d53ef 100644
--- a/board/nvidia/venice2/pinmux-config-venice2.h
+++ b/board/nvidia/venice2/pinmux-config-venice2.h
@@ -15,70 +15,70 @@
 #ifndef _PINMUX_CONFIG_VENICE2_H_
 #define _PINMUX_CONFIG_VENICE2_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config venice2_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A0,   IN),
-	GPIO_INIT(C7,   IN),
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(G1,   IN),
-	GPIO_INIT(G2,   IN),
-	GPIO_INIT(G3,   IN),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H4,   IN),
-	GPIO_INIT(H5,   OUT0),
-	GPIO_INIT(H6,   IN),
-	GPIO_INIT(H7,   OUT1),
-	GPIO_INIT(I0,   IN),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I2,   OUT0),
-	GPIO_INIT(I4,   OUT0),
-	GPIO_INIT(I5,   OUT1),
-	GPIO_INIT(I6,   IN),
-	GPIO_INIT(J0,   IN),
-	GPIO_INIT(J7,   IN),
-	GPIO_INIT(K0,   IN),
-	GPIO_INIT(K1,   OUT0),
-	GPIO_INIT(K2,   IN),
-	GPIO_INIT(K3,   IN),
-	GPIO_INIT(K4,   OUT0),
-	GPIO_INIT(K6,   OUT0),
-	GPIO_INIT(K7,   IN),
-	GPIO_INIT(N7,   IN),
-	GPIO_INIT(O2,   IN),
-	GPIO_INIT(O5,   IN),
-	GPIO_INIT(O6,   OUT0),
-	GPIO_INIT(O7,   IN),
-	GPIO_INIT(P2,   OUT0),
-	GPIO_INIT(Q0,   IN),
-	GPIO_INIT(Q2,   IN),
-	GPIO_INIT(Q3,   IN),
-	GPIO_INIT(Q6,   IN),
-	GPIO_INIT(Q7,   IN),
-	GPIO_INIT(R0,   OUT0),
-	GPIO_INIT(R1,   IN),
-	GPIO_INIT(R4,   IN),
-	GPIO_INIT(S0,   IN),
-	GPIO_INIT(S3,   OUT0),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S7,   IN),
-	GPIO_INIT(T1,   IN),
-	GPIO_INIT(U4,   IN),
-	GPIO_INIT(U5,   IN),
-	GPIO_INIT(U6,   IN),
-	GPIO_INIT(V0,   IN),
-	GPIO_INIT(V1,   IN),
-	GPIO_INIT(W3,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X3,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X7,   OUT0),
-	GPIO_INIT(CC5,  OUT0),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    0,   IN),
+	GPIO_INIT(C,    7,   IN),
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    1,   IN),
+	GPIO_INIT(G,    2,   IN),
+	GPIO_INIT(G,    3,   IN),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    4,   IN),
+	GPIO_INIT(H,    5,   OUT0),
+	GPIO_INIT(H,    6,   IN),
+	GPIO_INIT(H,    7,   OUT1),
+	GPIO_INIT(I,    0,   IN),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    2,   OUT0),
+	GPIO_INIT(I,    4,   OUT0),
+	GPIO_INIT(I,    5,   OUT1),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(J,    7,   IN),
+	GPIO_INIT(K,    0,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    3,   IN),
+	GPIO_INIT(K,    4,   OUT0),
+	GPIO_INIT(K,    6,   OUT0),
+	GPIO_INIT(K,    7,   IN),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(O,    2,   IN),
+	GPIO_INIT(O,    5,   IN),
+	GPIO_INIT(O,    6,   OUT0),
+	GPIO_INIT(O,    7,   IN),
+	GPIO_INIT(P,    2,   OUT0),
+	GPIO_INIT(Q,    0,   IN),
+	GPIO_INIT(Q,    2,   IN),
+	GPIO_INIT(Q,    3,   IN),
+	GPIO_INIT(Q,    6,   IN),
+	GPIO_INIT(Q,    7,   IN),
+	GPIO_INIT(R,    0,   OUT0),
+	GPIO_INIT(R,    1,   IN),
+	GPIO_INIT(R,    4,   IN),
+	GPIO_INIT(S,    0,   IN),
+	GPIO_INIT(S,    3,   OUT0),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    7,   IN),
+	GPIO_INIT(T,    1,   IN),
+	GPIO_INIT(U,    4,   IN),
+	GPIO_INIT(U,    5,   IN),
+	GPIO_INIT(U,    6,   IN),
+	GPIO_INIT(V,    0,   IN),
+	GPIO_INIT(V,    1,   IN),
+	GPIO_INIT(W,    3,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    3,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    7,   OUT0),
+	GPIO_INIT(CC,   5,   OUT0),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c
index 879f25a..68fbf49 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -103,11 +103,11 @@ void pin_mux_usb(void)
 	pinmux_tristate_disable(PMUX_PINGRP_DTE);
 
 	/* Reset ASIX using LAN_RESET */
-	gpio_request(GPIO_PV4, "LAN_RESET");
-	gpio_direction_output(GPIO_PV4, 0);
+	gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET");
+	gpio_direction_output(TEGRA_GPIO(V, 4), 0);
 	pinmux_tristate_disable(PMUX_PINGRP_GPV);
 	udelay(5);
-	gpio_set_value(GPIO_PV4, 1);
+	gpio_set_value(TEGRA_GPIO(V, 4), 1);
 
 	/* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
 	pinmux_tristate_disable(PMUX_PINGRP_SPIG);
diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c
index 44b5beb..e32362a 100644
--- a/board/toradex/colibri_t30/colibri_t30.c
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -47,8 +47,8 @@ void pinmux_init(void)
 void pin_mux_usb(void)
 {
 	/* Reset ASIX using LAN_RESET */
-	gpio_request(GPIO_PDD0, "LAN_RESET");
-	gpio_direction_output(GPIO_PDD0, 0);
+	gpio_request(TEGRA_GPIO(DD, 0), "LAN_RESET");
+	gpio_direction_output(TEGRA_GPIO(DD, 0), 0);
 	udelay(5);
-	gpio_set_value(GPIO_PDD0, 1);
+	gpio_set_value(TEGRA_GPIO(DD, 0), 1);
 }
-- 
cgit v0.10.2


From e6bf0ca0e2ef8d87d754f788be1b9b5d58c01860 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 12 May 2016 12:07:40 -0600
Subject: ARM: tegra: fix naming in GPIO DT binding header

According to the Tegra TRM, GPIOs are aggregated into /ports/ of 8 GPIOs,
not into /banks/. Fix <dt-bindings/gpio/tegra-gpio.h> to correctly reflect
this naming convention. While this seems like silly churn, it will become
slightly more important once we introduce the GPIO binding for upcoming
Tegra chips. This mirrors an identical commit in the Linux kernel.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h
index 197dc28..a1c09e8 100644
--- a/include/dt-bindings/gpio/tegra-gpio.h
+++ b/include/dt-bindings/gpio/tegra-gpio.h
@@ -12,40 +12,40 @@
 
 #include <dt-bindings/gpio/gpio.h>
 
-#define TEGRA_GPIO_BANK_ID_A 0
-#define TEGRA_GPIO_BANK_ID_B 1
-#define TEGRA_GPIO_BANK_ID_C 2
-#define TEGRA_GPIO_BANK_ID_D 3
-#define TEGRA_GPIO_BANK_ID_E 4
-#define TEGRA_GPIO_BANK_ID_F 5
-#define TEGRA_GPIO_BANK_ID_G 6
-#define TEGRA_GPIO_BANK_ID_H 7
-#define TEGRA_GPIO_BANK_ID_I 8
-#define TEGRA_GPIO_BANK_ID_J 9
-#define TEGRA_GPIO_BANK_ID_K 10
-#define TEGRA_GPIO_BANK_ID_L 11
-#define TEGRA_GPIO_BANK_ID_M 12
-#define TEGRA_GPIO_BANK_ID_N 13
-#define TEGRA_GPIO_BANK_ID_O 14
-#define TEGRA_GPIO_BANK_ID_P 15
-#define TEGRA_GPIO_BANK_ID_Q 16
-#define TEGRA_GPIO_BANK_ID_R 17
-#define TEGRA_GPIO_BANK_ID_S 18
-#define TEGRA_GPIO_BANK_ID_T 19
-#define TEGRA_GPIO_BANK_ID_U 20
-#define TEGRA_GPIO_BANK_ID_V 21
-#define TEGRA_GPIO_BANK_ID_W 22
-#define TEGRA_GPIO_BANK_ID_X 23
-#define TEGRA_GPIO_BANK_ID_Y 24
-#define TEGRA_GPIO_BANK_ID_Z 25
-#define TEGRA_GPIO_BANK_ID_AA 26
-#define TEGRA_GPIO_BANK_ID_BB 27
-#define TEGRA_GPIO_BANK_ID_CC 28
-#define TEGRA_GPIO_BANK_ID_DD 29
-#define TEGRA_GPIO_BANK_ID_EE 30
-#define TEGRA_GPIO_BANK_ID_FF 31
+#define TEGRA_GPIO_PORT_A 0
+#define TEGRA_GPIO_PORT_B 1
+#define TEGRA_GPIO_PORT_C 2
+#define TEGRA_GPIO_PORT_D 3
+#define TEGRA_GPIO_PORT_E 4
+#define TEGRA_GPIO_PORT_F 5
+#define TEGRA_GPIO_PORT_G 6
+#define TEGRA_GPIO_PORT_H 7
+#define TEGRA_GPIO_PORT_I 8
+#define TEGRA_GPIO_PORT_J 9
+#define TEGRA_GPIO_PORT_K 10
+#define TEGRA_GPIO_PORT_L 11
+#define TEGRA_GPIO_PORT_M 12
+#define TEGRA_GPIO_PORT_N 13
+#define TEGRA_GPIO_PORT_O 14
+#define TEGRA_GPIO_PORT_P 15
+#define TEGRA_GPIO_PORT_Q 16
+#define TEGRA_GPIO_PORT_R 17
+#define TEGRA_GPIO_PORT_S 18
+#define TEGRA_GPIO_PORT_T 19
+#define TEGRA_GPIO_PORT_U 20
+#define TEGRA_GPIO_PORT_V 21
+#define TEGRA_GPIO_PORT_W 22
+#define TEGRA_GPIO_PORT_X 23
+#define TEGRA_GPIO_PORT_Y 24
+#define TEGRA_GPIO_PORT_Z 25
+#define TEGRA_GPIO_PORT_AA 26
+#define TEGRA_GPIO_PORT_BB 27
+#define TEGRA_GPIO_PORT_CC 28
+#define TEGRA_GPIO_PORT_DD 29
+#define TEGRA_GPIO_PORT_EE 30
+#define TEGRA_GPIO_PORT_FF 31
 
-#define TEGRA_GPIO(bank, offset) \
-	((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
+#define TEGRA_GPIO(port, offset) \
+	((TEGRA_GPIO_PORT_##port * 8) + offset)
 
 #endif
-- 
cgit v0.10.2


From 601800be22a37cc518e023adc8e32ad15f00a2c6 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 12 May 2016 12:07:41 -0600
Subject: ARM: tegra: convert CONFIG_TEGRA_GPIO to Kconfig

Future chips will contain different GPIO HW. This change will enable
future SoC support to select the appropriate GPIO driver for their HW,
in a future-looking fashion, using Kconfig.

TEGRA_GPIO is not simply selected by TEGRA_COMMON (even though all
current Tegra chips used this GPIO HW) to simplify the later addition
of support for Tegra SoCs that use different GPIO HW.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index ba6983f..616a1c3 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -22,6 +22,7 @@ config TEGRA_ARMV7_COMMON
 	select SPL
 	select SUPPORT_SPL
 	select TEGRA_COMMON
+	select TEGRA_GPIO
 
 config TEGRA_ARMV8_COMMON
 	bool "Tegra 64-bit common options"
@@ -50,6 +51,7 @@ config TEGRA124
 
 config TEGRA210
 	bool "Tegra210 family"
+	select TEGRA_GPIO
 	select TEGRA_ARMV8_COMMON
 
 endchoice
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 93a7e8c..f730744 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -109,6 +109,13 @@ config SANDBOX_GPIO_COUNT
 	  of 'anonymous' GPIOs that do not belong to any device or bank.
 	  Select a suitable value depending on your needs.
 
+config TEGRA_GPIO
+	bool "Tegra20..210 GPIO driver"
+	depends on DM_GPIO
+	help
+	  Support for the GPIO controller contained in NVIDIA Tegra20 through
+	  Tegra210.
+
 config GPIO_UNIPHIER
 	bool "UniPhier GPIO"
 	depends on ARCH_UNIPHIER
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 92d4dd8..7b0940a 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -111,7 +111,6 @@
 						CONFIG_SYS_INIT_RAM_SIZE - \
 						GENERATED_GBL_DATA_SIZE)
 
-#define CONFIG_TEGRA_GPIO
 #define CONFIG_CMD_ENTERRCM
 
 /* Defines for SPL */
-- 
cgit v0.10.2


From 074a1fdd27953aacb59346c83baaf443335ea04e Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 25 May 2016 14:38:51 -0600
Subject: gpio: add Tegra186 GPIO driver

Tegra186's GPIO controller register layout is significantly different from
previous chips, so add a new driver for it. In fact, there are two
different GPIO controllers in Tegra186 that share a similar register
layout, but very different port mapping. This driver covers both.

The DT binding is already present in the Linux kernel (in linux-next via
the Tegra tree so far).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org> # v1
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt b/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt
new file mode 100644
index 0000000..c82a2e2
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt
@@ -0,0 +1,161 @@
+NVIDIA Tegra186 GPIO controllers
+
+Tegra186 contains two GPIO controllers; a main controller and an "AON"
+controller. This binding document applies to both controllers. The register
+layouts for the controllers share many similarities, but also some significant
+differences. Hence, this document describes closely related but different
+bindings and compatible values.
+
+The Tegra186 GPIO controller allows software to set the IO direction of, and
+read/write the value of, numerous GPIO signals. Routing of GPIO signals to
+package balls is under the control of a separate pin controller HW block. Two
+major sets of registers exist:
+
+a) Security registers, which allow configuration of allowed access to the GPIO
+register set. These registers exist in a single contiguous block of physical
+address space. The size of this block, and the security features available,
+varies between the different GPIO controllers.
+
+Access to this set of registers is not necessary in all circumstances. Code
+that wishes to configure access to the GPIO registers needs access to these
+registers to do so. Code which simply wishes to read or write GPIO data does not
+need access to these registers.
+
+b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
+controllers, these registers are exposed via multiple "physical aliases" in
+address space, each of which access the same underlying state. See the hardware
+documentation for rationale. Any particular GPIO client is expected to access
+just one of these physical aliases.
+
+Tegra HW documentation describes a unified naming convention for all GPIOs
+implemented by the SoC. Each GPIO is assigned to a port, and a port may control
+a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
+name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
+or GPIO_PCC3.
+
+The number of ports implemented by each GPIO controller varies. The number of
+implemented GPIOs within each port varies. GPIO registers within a controller
+are grouped and laid out according to the port they affect.
+
+The mapping from port name to the GPIO controller that implements that port, and
+the mapping from port name to register offset within a controller, are both
+extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
+describes the port-level mapping. In that file, the naming convention for ports
+matches the HW documentation. The values chosen for the names are alphabetically
+sorted within a particular controller. Drivers need to map between the DT GPIO
+IDs and HW register offsets using a lookup table.
+
+Each GPIO controller can generate a number of interrupt signals. Each signal
+represents the aggregate status for all GPIOs within a set of ports. Thus, the
+number of interrupt signals generated by a controller varies as a rough function
+of the number of ports it implements. Note that the HW documentation refers to
+both the overall controller HW module and the sets-of-ports as "controllers".
+
+Each GPIO controller in fact generates multiple interrupts signals for each set
+of ports. Each GPIO may be configured to feed into a specific one of the
+interrupt signals generated by a set-of-ports. The intent is for each generated
+signal to be routed to a different CPU, thus allowing different CPUs to each
+handle subsets of the interrupts within a port. The status of each of these
+per-port-set signals is reported via a separate register. Thus, a driver needs
+to know which status register to observe. This binding currently defines no
+configuration mechanism for this. By default, drivers should use register
+GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
+define a property to configure this.
+
+Required properties:
+- compatible
+    Array of strings.
+    One of:
+    - "nvidia,tegra186-gpio".
+    - "nvidia,tegra186-gpio-aon".
+- reg-names
+    Array of strings.
+    Contains a list of names for the register spaces described by the reg
+    property. May contain the following entries, in any order:
+    - "gpio": Mandatory. GPIO control registers. This may cover either:
+        a) The single physical alias that this OS should use.
+        b) All physical aliases that exist in the controller. This is
+           appropriate when the OS is responsible for managing assignment of
+           the physical aliases.
+    - "security": Optional. Security configuration registers.
+    Users of this binding MUST look up entries in the reg property by name,
+    using this reg-names property to do so.
+- reg
+    Array of (physical base address, length) tuples.
+    Must contain one entry per entry in the reg-names property, in a matching
+    order.
+- interrupts
+    Array of interrupt specifiers.
+    The interrupt outputs from the HW block, one per set of ports, in the
+    order the HW manual describes them. The number of entries required varies
+    depending on compatible value:
+    - "nvidia,tegra186-gpio": 6 entries.
+    - "nvidia,tegra186-gpio-aon": 1 entry.
+- gpio-controller
+    Boolean.
+    Marks the device node as a GPIO controller/provider.
+- #gpio-cells
+    Single-cell integer.
+    Must be <2>.
+    Indicates how many cells are used in a consumer's GPIO specifier.
+    In the specifier:
+    - The first cell is the pin number.
+        See <dt-bindings/gpio/tegra186-gpio.h>.
+    - The second cell contains flags:
+        - Bit 0 specifies polarity
+            - 0: Active-high (normal).
+            - 1: Active-low (inverted).
+- interrupt-controller
+    Boolean.
+    Marks the device node as an interrupt controller/provider.
+- #interrupt-cells
+    Single-cell integer.
+    Must be <2>.
+    Indicates how many cells are used in a consumer's interrupt specifier.
+    In the specifier:
+    - The first cell is the GPIO number.
+        See <dt-bindings/gpio/tegra186-gpio.h>.
+    - The second cell is contains flags:
+        - Bits [3:0] indicate trigger type and level:
+            - 1: Low-to-high edge triggered.
+            - 2: High-to-low edge triggered.
+            - 4: Active high level-sensitive.
+            - 8: Active low level-sensitive.
+            Valid combinations are 1, 2, 3, 4, 8.
+
+Example:
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+gpio@2200000 {
+	compatible = "nvidia,tegra186-gpio";
+	reg-names = "security", "gpio";
+	reg =
+		<0x0 0x2200000 0x0 0x10000>,
+		<0x0 0x2210000 0x0 0x10000>;
+	interrupts =
+		<0 47 IRQ_TYPE_LEVEL_HIGH>,
+		<0 50 IRQ_TYPE_LEVEL_HIGH>,
+		<0 53 IRQ_TYPE_LEVEL_HIGH>,
+		<0 56 IRQ_TYPE_LEVEL_HIGH>,
+		<0 59 IRQ_TYPE_LEVEL_HIGH>,
+		<0 180 IRQ_TYPE_LEVEL_HIGH>;
+	gpio-controller;
+	#gpio-cells = <2>;
+	interrupt-controller;
+	#interrupt-cells = <2>;
+};
+
+gpio@c2f0000 {
+	compatible = "nvidia,tegra186-gpio-aon";
+	reg-names = "security", "gpio";
+	reg =
+		<0x0 0xc2f0000 0x0 0x1000>,
+		<0x0 0xc2f1000 0x0 0x1000>;
+	interrupts =
+		<0 60 IRQ_TYPE_LEVEL_HIGH>;
+	gpio-controller;
+	#gpio-cells = <2>;
+	interrupt-controller;
+	#interrupt-cells = <2>;
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index f730744..32219ed 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -116,6 +116,14 @@ config TEGRA_GPIO
 	  Support for the GPIO controller contained in NVIDIA Tegra20 through
 	  Tegra210.
 
+config TEGRA186_GPIO
+	bool "Tegra186 GPIO driver"
+	depends on DM_GPIO
+	help
+	  Support for the GPIO controller contained in NVIDIA Tegra186. This
+	  covers both the "main" and "AON" controller instances, even though
+	  they have slightly different register layout.
+
 config GPIO_UNIPHIER
 	bool "UniPhier GPIO"
 	depends on ARCH_UNIPHIER
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ddec1ef..3c43101 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_S5P)		+= s5p_gpio.o
 obj-$(CONFIG_SANDBOX_GPIO)	+= sandbox.o
 obj-$(CONFIG_SPEAR_GPIO)	+= spear_gpio.o
 obj-$(CONFIG_TEGRA_GPIO)	+= tegra_gpio.o
+obj-$(CONFIG_TEGRA186_GPIO)	+= tegra186_gpio.o
 obj-$(CONFIG_DA8XX_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_DM644X_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_ALTERA_PIO)	+= altera_pio.o
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index fefe3ca..64abcba 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -8,7 +8,6 @@
  */
 
 #include <common.h>
-#include <clk.h>
 #include <dm.h>
 #include <syscon.h>
 #include <asm/errno.h>
diff --git a/drivers/gpio/tegra186_gpio.c b/drivers/gpio/tegra186_gpio.c
new file mode 100644
index 0000000..1c68151
--- /dev/null
+++ b/drivers/gpio/tegra186_gpio.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION.
+ * (based on tegra_gpio.c)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <asm/gpio.h>
+#include <dm/device-internal.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "tegra186_gpio_priv.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct tegra186_gpio_port_data {
+	const char *name;
+	uint32_t offset;
+};
+
+struct tegra186_gpio_ctlr_data {
+	const struct tegra186_gpio_port_data *ports;
+	uint32_t port_count;
+};
+
+struct tegra186_gpio_platdata {
+	const char *name;
+	uint32_t *regs;
+};
+
+static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg,
+				   uint32_t gpio)
+{
+	struct tegra186_gpio_platdata *plat = dev->platdata;
+	uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4;
+
+	return &(plat->regs[index]);
+}
+
+static int tegra186_gpio_set_out(struct udevice *dev, unsigned offset,
+				 bool output)
+{
+	uint32_t *reg;
+	uint32_t rval;
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_CONTROL, offset);
+	rval = readl(reg);
+	if (output)
+		rval &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
+	else
+		rval |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
+	writel(rval, reg);
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+	rval = readl(reg);
+	if (output)
+		rval |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
+	else
+		rval &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
+	rval |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
+	writel(rval, reg);
+
+	return 0;
+}
+
+static int tegra186_gpio_set_val(struct udevice *dev, unsigned offset, bool val)
+{
+	uint32_t *reg;
+	uint32_t rval;
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE, offset);
+	rval = readl(reg);
+	if (val)
+		rval |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
+	else
+		rval &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
+	writel(rval, reg);
+
+	return 0;
+}
+
+static int tegra186_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+	return tegra186_gpio_set_out(dev, offset, false);
+}
+
+static int tegra186_gpio_direction_output(struct udevice *dev, unsigned offset,
+				       int value)
+{
+	int ret;
+
+	ret = tegra186_gpio_set_val(dev, offset, value != 0);
+	if (ret)
+		return ret;
+	return tegra186_gpio_set_out(dev, offset, true);
+}
+
+static int tegra186_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+	uint32_t *reg;
+	uint32_t rval;
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+	rval = readl(reg);
+
+	if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
+		reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE,
+					offset);
+	else
+		reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_INPUT, offset);
+
+	rval = readl(reg);
+	return !!rval;
+}
+
+static int tegra186_gpio_set_value(struct udevice *dev, unsigned offset,
+				   int value)
+{
+	return tegra186_gpio_set_val(dev, offset, value != 0);
+}
+
+static int tegra186_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	uint32_t *reg;
+	uint32_t rval;
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+	rval = readl(reg);
+	if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
+		return GPIOF_OUTPUT;
+	else
+		return GPIOF_INPUT;
+}
+
+static int tegra186_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+			    struct fdtdec_phandle_args *args)
+{
+	int gpio, port, ret;
+
+	gpio = args->args[0];
+	port = gpio / TEGRA186_GPIO_PER_GPIO_COUNT;
+	ret = device_get_child(dev, port, &desc->dev);
+	if (ret)
+		return ret;
+	desc->offset = gpio % TEGRA186_GPIO_PER_GPIO_COUNT;
+	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops tegra186_gpio_ops = {
+	.direction_input	= tegra186_gpio_direction_input,
+	.direction_output	= tegra186_gpio_direction_output,
+	.get_value		= tegra186_gpio_get_value,
+	.set_value		= tegra186_gpio_set_value,
+	.get_function		= tegra186_gpio_get_function,
+	.xlate			= tegra186_gpio_xlate,
+};
+
+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child device
+ * for each port within the controller.
+ */
+static int tegra186_gpio_bind(struct udevice *parent)
+{
+	struct tegra186_gpio_platdata *parent_plat = parent->platdata;
+	struct tegra186_gpio_ctlr_data *ctlr_data =
+		(struct tegra186_gpio_ctlr_data *)dev_get_driver_data(parent);
+	uint32_t *regs;
+	int port, ret;
+
+	/* If this is a child device, there is nothing to do here */
+	if (parent_plat)
+		return 0;
+
+	regs = (uint32_t *)dev_get_addr_name(parent, "gpio");
+	if (regs == (uint32_t *)FDT_ADDR_T_NONE)
+		return -ENODEV;
+
+	for (port = 0; port < ctlr_data->port_count; port++) {
+		struct tegra186_gpio_platdata *plat;
+		struct udevice *dev;
+
+		plat = calloc(1, sizeof(*plat));
+		if (!plat)
+			return -ENOMEM;
+		plat->name = ctlr_data->ports[port].name;
+		plat->regs = &(regs[ctlr_data->ports[port].offset / 4]);
+
+		ret = device_bind(parent, parent->driver, plat->name, plat,
+				  -1, &dev);
+		if (ret)
+			return ret;
+		dev->of_offset = parent->of_offset;
+	}
+
+	return 0;
+}
+
+static int tegra186_gpio_probe(struct udevice *dev)
+{
+	struct tegra186_gpio_platdata *plat = dev->platdata;
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	/* Only child devices have ports */
+	if (!plat)
+		return 0;
+
+	uc_priv->gpio_count = TEGRA186_GPIO_PER_GPIO_COUNT;
+	uc_priv->bank_name = plat->name;
+
+	return 0;
+}
+
+static const struct tegra186_gpio_port_data tegra186_gpio_main_ports[] = {
+	{"A",  0x2000},
+	{"B",  0x3000},
+	{"C",  0x3200},
+	{"D",  0x3400},
+	{"E",  0x2200},
+	{"F",  0x2400},
+	{"G",  0x4200},
+	{"H",  0x1000},
+	{"I",  0x0800},
+	{"J",  0x5000},
+	{"K",  0x5200},
+	{"L",  0x1200},
+	{"M",  0x5600},
+	{"N",  0x0000},
+	{"O",  0x0200},
+	{"P",  0x4000},
+	{"Q",  0x0400},
+	{"R",  0x0a00},
+	{"T",  0x0600},
+	{"X",  0x1400},
+	{"Y",  0x1600},
+	{"BB", 0x2600},
+	{"CC", 0x5400},
+};
+
+static const struct tegra186_gpio_ctlr_data tegra186_gpio_main_data = {
+	.ports = tegra186_gpio_main_ports,
+	.port_count = ARRAY_SIZE(tegra186_gpio_main_ports),
+};
+
+static const struct tegra186_gpio_port_data tegra186_gpio_aon_ports[] = {
+	{"S",  0x0200},
+	{"U",  0x0400},
+	{"V",  0x0800},
+	{"W",  0x0a00},
+	{"Z",  0x0e00},
+	{"AA", 0x0c00},
+	{"EE", 0x0600},
+	{"FF", 0x0000},
+};
+
+static const struct tegra186_gpio_ctlr_data tegra186_gpio_aon_data = {
+	.ports = tegra186_gpio_aon_ports,
+	.port_count = ARRAY_SIZE(tegra186_gpio_aon_ports),
+};
+
+static const struct udevice_id tegra186_gpio_ids[] = {
+	{
+		.compatible = "nvidia,tegra186-gpio",
+		.data = (ulong)&tegra186_gpio_main_data,
+	},
+	{
+		.compatible = "nvidia,tegra186-gpio-aon",
+		.data = (ulong)&tegra186_gpio_aon_data,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(tegra186_gpio) = {
+	.name = "tegra186_gpio",
+	.id = UCLASS_GPIO,
+	.of_match = tegra186_gpio_ids,
+	.bind = tegra186_gpio_bind,
+	.probe = tegra186_gpio_probe,
+	.ops = &tegra186_gpio_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/gpio/tegra186_gpio_priv.h b/drivers/gpio/tegra186_gpio_priv.h
new file mode 100644
index 0000000..9e85a434
--- /dev/null
+++ b/drivers/gpio/tegra186_gpio_priv.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_GPIO_PRIV_H_
+#define _TEGRA186_GPIO_PRIV_H_
+
+/*
+ * For each GPIO, there are a set of registers than affect it, all packed
+ * back-to-back.
+ */
+#define TEGRA186_GPIO_ENABLE_CONFIG				0x00
+#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE			BIT(0)
+#define TEGRA186_GPIO_ENABLE_CONFIG_OUT				BIT(1)
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SHIFT		2
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK		3
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE		0
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL		1
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE	2
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE	3
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL_HIGH_RISING	BIT(4)
+#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE_ENABLE		BIT(5)
+#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT_ENABLE		BIT(6)
+#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMPING_ENABLE		BIT(7)
+
+#define TEGRA186_GPIO_DEBOUNCE_THRESHOLD			0x04
+
+#define TEGRA186_GPIO_INPUT					0x08
+
+#define TEGRA186_GPIO_OUTPUT_CONTROL				0x0c
+#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED			BIT(0)
+
+#define TEGRA186_GPIO_OUTPUT_VALUE				0x10
+#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH				1
+
+#define TEGRA186_GPIO_INTERRUPT_CLEAR				0x14
+
+/*
+ * 8 GPIOs are packed into a port. Their registers appear back-to-back in the
+ * port's address space.
+ */
+#define TEGRA186_GPIO_PER_GPIO_STRIDE				0x20
+#define TEGRA186_GPIO_PER_GPIO_COUNT				8
+
+/*
+ * Per-port registers are packed immediately following all of a port's
+ * per-GPIO registers.
+ */
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G			0x100
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G_STRIDE			4
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G_COUNT			8
+
+/*
+ * The registers for multiple ports are packed together back-to-back to form
+ * the overall controller.
+ */
+#define TEGRA186_GPIO_PER_PORT_STRIDE				0x200
+
+#endif
diff --git a/include/dt-bindings/gpio/tegra186-gpio.h b/include/dt-bindings/gpio/tegra186-gpio.h
new file mode 100644
index 0000000..7e6fb95
--- /dev/null
+++ b/include/dt-bindings/gpio/tegra186-gpio.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This header provides constants for binding nvidia,tegra186-gpio*.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA_MAIN_GPIO_PORT_A 0
+#define TEGRA_MAIN_GPIO_PORT_B 1
+#define TEGRA_MAIN_GPIO_PORT_C 2
+#define TEGRA_MAIN_GPIO_PORT_D 3
+#define TEGRA_MAIN_GPIO_PORT_E 4
+#define TEGRA_MAIN_GPIO_PORT_F 5
+#define TEGRA_MAIN_GPIO_PORT_G 6
+#define TEGRA_MAIN_GPIO_PORT_H 7
+#define TEGRA_MAIN_GPIO_PORT_I 8
+#define TEGRA_MAIN_GPIO_PORT_J 9
+#define TEGRA_MAIN_GPIO_PORT_K 10
+#define TEGRA_MAIN_GPIO_PORT_L 11
+#define TEGRA_MAIN_GPIO_PORT_M 12
+#define TEGRA_MAIN_GPIO_PORT_N 13
+#define TEGRA_MAIN_GPIO_PORT_O 14
+#define TEGRA_MAIN_GPIO_PORT_P 15
+#define TEGRA_MAIN_GPIO_PORT_Q 16
+#define TEGRA_MAIN_GPIO_PORT_R 17
+#define TEGRA_MAIN_GPIO_PORT_T 18
+#define TEGRA_MAIN_GPIO_PORT_X 19
+#define TEGRA_MAIN_GPIO_PORT_Y 20
+#define TEGRA_MAIN_GPIO_PORT_BB 21
+#define TEGRA_MAIN_GPIO_PORT_CC 22
+
+#define TEGRA_MAIN_GPIO(port, offset) \
+	((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
+
+/* GPIOs implemented by AON GPIO controller */
+#define TEGRA_AON_GPIO_PORT_S 0
+#define TEGRA_AON_GPIO_PORT_U 1
+#define TEGRA_AON_GPIO_PORT_V 2
+#define TEGRA_AON_GPIO_PORT_W 3
+#define TEGRA_AON_GPIO_PORT_Z 4
+#define TEGRA_AON_GPIO_PORT_AA 5
+#define TEGRA_AON_GPIO_PORT_EE 6
+#define TEGRA_AON_GPIO_PORT_FF 7
+
+#define TEGRA_AON_GPIO(port, offset) \
+	((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
+
+#endif
-- 
cgit v0.10.2


From 39f633320c569a5d975d2d051ff2683db27bd021 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 12 May 2016 12:11:23 -0600
Subject: mmc: tegra: add basic Tegra186 support

Tegra186's MMC controller needs to be explicitly identified. Add another
compatible value for it.

Tegra186 will use an entirely different clock/reset control mechanism to
existing chips, and will use standard clock/reset APIs rather than the
existing Tegra-specific custom APIs. The driver support for that isn't
ready yet, so simply disable all clock/reset usage if compiling for
Tegra186. This must happen at compile time rather than run-time since the
custom APIs won't even be compiled in on Tegra186. In the long term, the
plan would be to convert the existing custom APIs to standard APIs and get
rid of the ifdefs completely.

The system's main eMMC will work without any clock/reset support, since
the firmware will have already initialized the controller in order to
load U-Boot. Hence the driver is useful even in this apparently crippled
state.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index a20bdaa..75e56c4 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -134,7 +134,9 @@ struct mmc_host {
 	int id;			/* device id/number, 0-3 */
 	int enabled;		/* 1 to enable, 0 to disable */
 	int width;		/* Bus Width, 1, 4 or 8 */
+#ifndef CONFIG_TEGRA186
 	enum periph_id mmc_id;	/* Peripheral ID: PERIPH_ID_... */
+#endif
 	struct gpio_desc cd_gpio;	/* Change Detect GPIO */
 	struct gpio_desc pwr_gpio;	/* Power GPIO */
 	struct gpio_desc wp_gpio;	/* Write Protect GPIO */
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 573819a..c9d9432 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -11,8 +11,10 @@
 #include <common.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
+#ifndef CONFIG_TEGRA186
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/clk_rst.h>
+#endif
 #include <asm/arch-tegra/mmc.h>
 #include <asm/arch-tegra/tegra_mmc.h>
 #include <mmc.h>
@@ -357,8 +359,12 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
 	 */
 	if (clock == 0)
 		goto out;
+#ifndef CONFIG_TEGRA186
 	clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
 				    &div);
+#else
+	div = (20000000 + clock - 1) / clock;
+#endif
 	debug("div = %d\n", div);
 
 	writew(0, &host->reg->clkcon);
@@ -543,7 +549,9 @@ static int do_mmc_init(int dev_index, bool removable)
 	      gpio_get_number(&host->cd_gpio));
 
 	host->clock = 0;
+#ifndef CONFIG_TEGRA186
 	clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
+#endif
 
 	if (dm_gpio_is_valid(&host->pwr_gpio))
 		dm_gpio_set_value(&host->pwr_gpio, 1);
@@ -568,7 +576,11 @@ static int do_mmc_init(int dev_index, bool removable)
 	 *  (actually 52MHz)
 	 */
 	host->cfg.f_min = 375000;
+#ifndef CONFIG_TEGRA186
 	host->cfg.f_max = 48000000;
+#else
+	host->cfg.f_max = 375000;
+#endif
 
 	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
@@ -600,11 +612,13 @@ static int mmc_get_config(const void *blob, int node, struct mmc_host *host,
 		return -FDT_ERR_NOTFOUND;
 	}
 
+#ifndef CONFIG_TEGRA186
 	host->mmc_id = clock_decode_periph_id(blob, node);
 	if (host->mmc_id == PERIPH_ID_NONE) {
 		debug("%s: could not decode periph id\n", __func__);
 		return -FDT_ERR_NOTFOUND;
 	}
+#endif
 
 	/*
 	 * NOTE: mmc->bus_width is determined by mmc.c dynamically.
@@ -624,7 +638,13 @@ static int mmc_get_config(const void *blob, int node, struct mmc_host *host,
 	*removablep = !fdtdec_get_bool(blob, node, "non-removable");
 
 	debug("%s: found controller at %p, width = %d, periph_id = %d\n",
-		__func__, host->reg, host->width, host->mmc_id);
+		__func__, host->reg, host->width,
+#ifndef CONFIG_TEGRA186
+		host->mmc_id
+#else
+		-1
+#endif
+	);
 	return 0;
 }
 
@@ -668,6 +688,16 @@ void tegra_mmc_init(void)
 	const void *blob = gd->fdt_blob;
 	debug("%s entry\n", __func__);
 
+	/* See if any Tegra186 MMC controllers are present */
+	count = fdtdec_find_aliases_for_id(blob, "sdhci",
+		COMPAT_NVIDIA_TEGRA186_SDMMC, node_list,
+		CONFIG_SYS_MMC_MAX_DEVICE);
+	debug("%s: count of Tegra186 sdhci nodes is %d\n", __func__, count);
+	if (process_nodes(blob, node_list, count)) {
+		printf("%s: Error processing T186 mmc node(s)!\n", __func__);
+		return;
+	}
+
 	/* See if any Tegra210 MMC controllers are present */
 	count = fdtdec_find_aliases_for_id(blob, "sdhci",
 		COMPAT_NVIDIA_TEGRA210_SDMMC, node_list,
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 37d482a..54e3d81 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -123,6 +123,7 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA124_SOR,	/* Tegra 124 Serial Output Resource */
 	COMPAT_NVIDIA_TEGRA124_PMC,	/* Tegra 124 power mgmt controller */
 	COMPAT_NVIDIA_TEGRA20_DC,	/* Tegra 2 Display controller */
+	COMPAT_NVIDIA_TEGRA186_SDMMC,	/* Tegra186 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA210_SDMMC,	/* Tegra210 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA124_SDMMC,	/* Tegra124 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA30_SDMMC,	/* Tegra30 SDMMC controller */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 70acc29..ab002e9 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -30,6 +30,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"),
 	COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
 	COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+	COMPAT(NVIDIA_TEGRA186_SDMMC, "nvidia,tegra186-sdhci"),
 	COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
 	COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
 	COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
-- 
cgit v0.10.2


From c7ba99c8c18a606b95a89366bc4fd94a8295772f Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 12 May 2016 13:32:55 -0600
Subject: ARM: tegra: add core Tegra186 support

This adds the bare minimum code to support Tegra186, with UART and eMMC
working.

The empty gpio.h is required because <asm/gpio.h> includes it. A future
cleanup round may be able to solve this for all Tegra generations at once.

mach-tegra/Makefile is adjusted not to compile anything for Tegra186, but
instead to defer everything to mach-tegra/tegra186/Makefile. This allows
the SoC code to pick-and-choose which of the C files in the "common"
mach-tegra/ directory to compile in based on the SoC's needs. Most of the
code is not valid for Tegra186, and this approach removes the need for
mach-tegra/Makefile to contain many SoC-specific ifdefs. This approach
may be applied to all other Tegra SoCs in a future cleanup round.

board186.c is introduced to replace board.c and board2.c. These files
currently contain a slew of SoC- and board-specific code that is not
valid for Tegra186. This approach avoids adding yet more ifdefs to those
files. A future cleanup round may refactor most of board*.c into board-/
SoC-specific functions files thus allowing the top-level functions like
board_init_early_f to be shared again.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi
new file mode 100644
index 0000000..18b6a26
--- /dev/null
+++ b/arch/arm/dts/tegra186.dtsi
@@ -0,0 +1,56 @@
+#include "skeleton.dtsi"
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "nvidia,tegra186";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	gpio@2200000 {
+		compatible = "nvidia,tegra186-gpio";
+		reg-names = "security", "gpio";
+		reg =
+			<0x0 0x2200000 0x0 0x10000>,
+			<0x0 0x2210000 0x0 0x10000>;
+		interrupts =
+			<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	uarta: serial@3100000 {
+		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+		reg = <0x0 0x03100000 0x0 0x10000>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	sdhci@3460000 {
+		compatible = "nvidia,tegra186-sdhci";
+		reg = <0x0 0x03460000 0x0 0x200>;
+		interrupts = <GIC_SPI 31 0x04>;
+		status = "disabled";
+	};
+
+	gpio@c2f0000 {
+		compatible = "nvidia,tegra186-gpio-aon";
+		reg-names = "security", "gpio";
+		reg =
+			<0x0 0xc2f0000 0x0 0x1000>,
+			<0x0 0xc2f1000 0x0 0x1000>;
+		interrupts =
+			<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
diff --git a/arch/arm/include/asm/arch-tegra186/gpio.h b/arch/arm/include/asm/arch-tegra186/gpio.h
new file mode 100644
index 0000000..aaecfc7
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra186/gpio.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_GPIO_H_
+#define _TEGRA186_GPIO_H_
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra186/tegra.h b/arch/arm/include/asm/arch-tegra186/tegra.h
new file mode 100644
index 0000000..8031f23
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra186/tegra.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_TEGRA_H_
+#define _TEGRA186_TEGRA_H_
+
+#define GICD_BASE		0x03881000	/* Generic Int Cntrlr Distrib */
+#define GICC_BASE		0x03882000	/* Generic Int Cntrlr CPU I/F */
+#define NV_PA_SDRAM_BASE	0x80000000
+
+#include <asm/arch-tegra/tegra.h>
+
+#endif
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 616a1c3..b18a12e 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -54,6 +54,11 @@ config TEGRA210
 	select TEGRA_GPIO
 	select TEGRA_ARMV8_COMMON
 
+config TEGRA186
+	bool "Tegra186 family"
+	select TEGRA186_GPIO
+	select TEGRA_ARMV8_COMMON
+
 endchoice
 
 config TEGRA_DISCONNECT_UDC_ON_BOOT
@@ -77,5 +82,6 @@ source "arch/arm/mach-tegra/tegra30/Kconfig"
 source "arch/arm/mach-tegra/tegra114/Kconfig"
 source "arch/arm/mach-tegra/tegra124/Kconfig"
 source "arch/arm/mach-tegra/tegra210/Kconfig"
+source "arch/arm/mach-tegra/tegra186/Kconfig"
 
 endif
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index b2dbc69..12ee1cd 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -7,6 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+ifndef CONFIG_TEGRA186
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
 obj-y += cpu.o
@@ -30,9 +31,11 @@ obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
 endif
+endif
 
 obj-$(CONFIG_TEGRA20) += tegra20/
 obj-$(CONFIG_TEGRA30) += tegra30/
 obj-$(CONFIG_TEGRA114) += tegra114/
 obj-$(CONFIG_TEGRA124) += tegra124/
+obj-$(CONFIG_TEGRA186) += tegra186/
 obj-$(CONFIG_TEGRA210) += tegra210/
diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c
new file mode 100644
index 0000000..f4b6152
--- /dev/null
+++ b/arch/arm/mach-tegra/board186.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/mmc.h>
+#include <asm/arch-tegra/tegra_mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = (1.5 * 1024 * 1024 * 1024);
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+void pad_init_mmc(struct mmc_host *host)
+{
+}
+
+int board_mmc_init(bd_t *bd)
+{
+	tegra_mmc_init();
+
+	return 0;
+}
+
+int ft_system_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig
new file mode 100644
index 0000000..124d8e5
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/Kconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if TEGRA186
+
+choice
+	prompt "Tegra186 board select"
+
+endchoice
+
+config SYS_SOC
+	default "tegra186"
+
+endif
diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile
new file mode 100644
index 0000000..ce4610d
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/Makefile
@@ -0,0 +1,8 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += ../arm64-mmu.o
+obj-y += ../board186.o
+obj-y += ../lowlevel_init.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += ../sys_info.o
diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h
new file mode 100644
index 0000000..aa7b9d0
--- /dev/null
+++ b/include/configs/tegra186-common.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_COMMON_H_
+#define _TEGRA186_COMMON_H_
+
+#include "tegra-common.h"
+
+/* Cortex-A57 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_STACKBASE	0x82800000	/* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+#define CONFIG_SYS_TEXT_BASE	0x80080000
+
+/* Generic Interrupt Controller */
+#define CONFIG_GICV2
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define CONFIG_LOADADDR 0x80080000
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
+#define CONFIG_SPL_STACK		0x800ffffc
+
+#endif
-- 
cgit v0.10.2


From 10a03382f0f8e774e58df7143e1a8ea52903ae1f Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 12 May 2016 13:32:56 -0600
Subject: ARM: tegra: add p2771-0000 board support

P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The
combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B
port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO expansion
headers.

Currently, due to U-Boot's level of support for Tegra186, the only
features supported by U-Boot are the console UART and the on-board eMMC.
Additional features will be added over time.

U-Boot has so far been tested by replacing the kernel image on the device
with a U-Boot binary. It is anticipated that U-Boot will eventually
replace the CCPLEX bootloader binary, as on previous chips. This hasn't
yet been tested.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 92c7545..818d24e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -47,6 +47,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra124-jetson-tk1.dtb \
 	tegra124-nyan-big.dtb \
 	tegra124-venice2.dtb \
+	tegra186-p2771-0000.dtb \
 	tegra210-e2220-1170.dtb \
 	tegra210-p2371-0000.dtb \
 	tegra210-p2371-2180.dtb \
diff --git a/arch/arm/dts/tegra186-p2771-0000.dts b/arch/arm/dts/tegra186-p2771-0000.dts
new file mode 100644
index 0000000..5f29ee4
--- /dev/null
+++ b/arch/arm/dts/tegra186-p2771-0000.dts
@@ -0,0 +1,25 @@
+/dts-v1/;
+
+#include "tegra186.dtsi"
+
+/ {
+	model = "NVIDIA P2771-0000";
+	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
+
+	chosen {
+		stdout-path = &uarta;
+	};
+
+	aliases {
+		sdhci0 = "/sdhci@3460000";
+	};
+
+	memory {
+		reg = <0x0 0x80000000 0x0 0x60000000>;
+	};
+
+	sdhci@3460000 {
+		status = "okay";
+		bus-width = <8>;
+	};
+};
diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig
index 124d8e5..97cf23f 100644
--- a/arch/arm/mach-tegra/tegra186/Kconfig
+++ b/arch/arm/mach-tegra/tegra186/Kconfig
@@ -7,9 +7,19 @@ if TEGRA186
 choice
 	prompt "Tegra186 board select"
 
+config TARGET_P2771_0000
+	bool "NVIDIA Tegra186 P2771-0000 board"
+	help
+	  P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The
+	  combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB
+	  micro-B port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO
+	  expansion headers.
+
 endchoice
 
 config SYS_SOC
 	default "tegra186"
 
+source "board/nvidia/p2771-0000/Kconfig"
+
 endif
diff --git a/board/nvidia/p2771-0000/Kconfig b/board/nvidia/p2771-0000/Kconfig
new file mode 100644
index 0000000..1b1116f
--- /dev/null
+++ b/board/nvidia/p2771-0000/Kconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if TARGET_P2771_0000
+
+config SYS_BOARD
+	default "p2771-0000"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "p2771-0000"
+
+endif
diff --git a/board/nvidia/p2771-0000/MAINTAINERS b/board/nvidia/p2771-0000/MAINTAINERS
new file mode 100644
index 0000000..4fc4ebd
--- /dev/null
+++ b/board/nvidia/p2771-0000/MAINTAINERS
@@ -0,0 +1,6 @@
+P2771-0000 BOARD
+M:	Stephen Warren <swarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/p2771-0000/
+F:	include/configs/p2771-0000.h
+F:	configs/p2771-0000_defconfig
diff --git a/board/nvidia/p2771-0000/Makefile b/board/nvidia/p2771-0000/Makefile
new file mode 100644
index 0000000..b28a47d
--- /dev/null
+++ b/board/nvidia/p2771-0000/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y	+= p2771-0000.o
diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c
new file mode 100644
index 0000000..4ba8ebc
--- /dev/null
+++ b/board/nvidia/p2771-0000/p2771-0000.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
diff --git a/configs/p2771-0000_defconfig b/configs/p2771-0000_defconfig
new file mode 100644
index 0000000..9f2c418
--- /dev/null
+++ b/configs/p2771-0000_defconfig
@@ -0,0 +1,31 @@
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA186=y
+CONFIG_TARGET_P2771_0000=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Tegra186 (P2771-0000) # "
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h
new file mode 100644
index 0000000..257283f
--- /dev/null
+++ b/include/configs/p2771-0000.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _P2771_0000_H
+#define _P2771_0000_H
+
+#include <linux/sizes.h>
+
+#include "tegra186-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA P2771-0000"
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+#include "tegra-common-post.h"
+
+/* Crystal is 38.4MHz. clk_m runs at half that rate */
+#define COUNTER_FREQUENCY	19200000
+
+#endif
-- 
cgit v0.10.2