From 183f5fd3caec9266432a7cbd50f59cec8bbddc6a Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut@gmail.com>
Date: Tue, 5 Sep 2017 15:11:14 +0200
Subject: ARM: rmobile: Fix SD divider settings on Gen3

On RCar M3 and on RCar H3 newer than and not including ES1.0, the SD clock
must be divided by 4 rather than 2 because a hardware workaround present
only in the H3 ES1.0 has been removed from these chips. U-Boot currently
only supports M3 and H3 ES 2.0 and newer, so configure the SD pre-divider
to 4 to prevent SD instability.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index 2695de5..e260117 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -74,10 +74,10 @@ int board_early_init_f(void)
 	/* SDHI0, 3 */
 	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
 
-	writel(0, SD0CKCR);
-	writel(0, SD1CKCR);
-	writel(0, SD2CKCR);
-	writel(0, SD3CKCR);
+	writel(1, SD0CKCR);
+	writel(1, SD1CKCR);
+	writel(1, SD2CKCR);
+	writel(1, SD3CKCR);
 
 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
 	/* DVFS for reset */
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index 2b6cc61..dc23228 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -72,10 +72,10 @@ int board_early_init_f(void)
 	/* SDHI0 */
 	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
 
-	writel(0, SD0CKCR);
-	writel(0, SD1CKCR);
-	writel(0, SD2CKCR);
-	writel(0, SD3CKCR);
+	writel(1, SD0CKCR);
+	writel(1, SD1CKCR);
+	writel(1, SD2CKCR);
+	writel(1, SD3CKCR);
 
 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
 	/* DVFS for reset */
-- 
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