From c4ea142424fc5cb43a2db750cb772e84304e5fb8 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 6 Jul 2010 17:05:06 +0200 Subject: Use common function to set GPIOs for MX3 and MX5 The patch adds support for setting gpios to the MX51 processor and change name to the corresponding functions for MX31. In this way, it is possible to get rid of nasty #ifdef switches related to the processor type. Signed-off-by: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h b/arch/arm/include/asm/arch-mx31/mx31-regs.h index d72585c..f05e743 100644 --- a/arch/arm/include/asm/arch-mx31/mx31-regs.h +++ b/arch/arm/include/asm/arch-mx31/mx31-regs.h @@ -57,6 +57,14 @@ struct clock_control_regs { u32 pdr2; }; +/* GPIO Registers */ +struct gpio_regs { + u32 gpio_dr; + u32 gpio_dir; + u32 gpio_psr; +}; + + /* Bit definitions for RCSR register in CCM */ #define CCM_RCSR_NF16B (1 << 31) #define CCM_RCSR_NFMS (1 << 30) @@ -153,9 +161,9 @@ struct clock_control_regs { /* * GPIO */ -#define GPIO1_BASE 0x53FCC000 -#define GPIO2_BASE 0x53FD0000 -#define GPIO3_BASE 0x53FA4000 +#define GPIO1_BASE_ADDR 0x53FCC000 +#define GPIO2_BASE_ADDR 0x53FD0000 +#define GPIO3_BASE_ADDR 0x53FA4000 #define GPIO_DR 0x00000000 /* data register */ #define GPIO_GDIR 0x00000004 /* direction register */ #define GPIO_PSR 0x00000008 /* pad status register */ diff --git a/arch/arm/include/asm/arch-mx31/mx31.h b/arch/arm/include/asm/arch-mx31/mx31.h index f702d26..5a5aa11 100644 --- a/arch/arm/include/asm/arch-mx31/mx31.h +++ b/arch/arm/include/asm/arch-mx31/mx31.h @@ -28,31 +28,6 @@ extern u32 mx31_get_ipg_clk(void); #define imx_get_uartclk mx31_get_ipg_clk extern void mx31_gpio_mux(unsigned long mode); -enum mx31_gpio_direction { - MX31_GPIO_DIRECTION_IN, - MX31_GPIO_DIRECTION_OUT, -}; - -#ifdef CONFIG_MX31_GPIO -extern int mx31_gpio_direction(unsigned int gpio, - enum mx31_gpio_direction direction); -extern void mx31_gpio_set(unsigned int gpio, unsigned int value); -extern int mx31_gpio_get(unsigned int gpio); -#else -static inline int mx31_gpio_direction(unsigned int gpio, - enum mx31_gpio_direction direction) -{ - return 1; -} -static inline int mx31_gpio_get(unsigned int gpio) -{ - return 1; -} -static inline void mx31_gpio_set(unsigned int gpio, unsigned int value) -{ -} -#endif - void mx31_uart1_hw_init(void); void mx31_spi2_hw_init(void); diff --git a/arch/arm/include/asm/arch-mx51/imx-regs.h b/arch/arm/include/asm/arch-mx51/imx-regs.h index 3887d3c..0e3bc2a 100644 --- a/arch/arm/include/asm/arch-mx51/imx-regs.h +++ b/arch/arm/include/asm/arch-mx51/imx-regs.h @@ -256,6 +256,12 @@ struct weim { u32 cswcr2; }; +/* GPIO Registers */ +struct gpio_regs { + u32 gpio_dr; + u32 gpio_dir; + u32 gpio_psr; +}; #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MXC_MX51_H__ */ diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index e509383..9abc29c 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "qong_fpga.h" DECLARE_GLOBAL_DATA_PTR; @@ -41,9 +42,9 @@ int dram_init (void) static void qong_fpga_reset(void) { - mx31_gpio_set(QONG_FPGA_RST_PIN, 0); + mxc_gpio_set(QONG_FPGA_RST_PIN, 0); udelay(30); - mx31_gpio_set(QONG_FPGA_RST_PIN, 1); + mxc_gpio_set(QONG_FPGA_RST_PIN, 1); udelay(300); } @@ -66,11 +67,11 @@ int board_early_init_f (void) /* FPGA reset Pin */ /* rstn = 0 */ - mx31_gpio_set(QONG_FPGA_RST_PIN, 0); - mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT); + mxc_gpio_set(QONG_FPGA_RST_PIN, 0); + mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT); /* set interrupt pin as input */ - mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN); + mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN); #endif @@ -206,27 +207,27 @@ static void board_nand_setup(void) qong_fpga_reset(); /* Enable NAND flash */ - mx31_gpio_set(15, 1); - mx31_gpio_set(14, 1); - mx31_gpio_direction(15, MX31_GPIO_DIRECTION_OUT); - mx31_gpio_direction(16, MX31_GPIO_DIRECTION_IN); - mx31_gpio_direction(14, MX31_GPIO_DIRECTION_IN); - mx31_gpio_set(15, 0); + mxc_gpio_set(15, 1); + mxc_gpio_set(14, 1); + mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN); + mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN); + mxc_gpio_set(15, 0); } int qong_nand_rdy(void *chip) { udelay(1); - return mx31_gpio_get(16); + return mxc_gpio_get(16); } void qong_nand_select_chip(struct mtd_info *mtd, int chip) { if (chip >= 0) - mx31_gpio_set(15, 0); + mxc_gpio_set(15, 0); else - mx31_gpio_set(15, 1); + mxc_gpio_set(15, 1); } diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 07d395d..a0f4552 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,7 +27,7 @@ LIB := $(obj)libgpio.a COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o -COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o +COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o COBJS-$(CONFIG_S5P) += s5p_gpio.o diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c deleted file mode 100644 index b07f038..0000000 --- a/drivers/gpio/mx31_gpio.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (C) 2009 - * Guennadi Liakhovetski, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include - -/* GPIO port description */ -static unsigned long gpio_ports[] = { - [0] = GPIO1_BASE, - [1] = GPIO2_BASE, - [2] = GPIO3_BASE, -}; - -int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction) -{ - unsigned int port = gpio >> 5; - u32 l; - - if (port >= ARRAY_SIZE(gpio_ports)) - return 1; - - gpio &= 0x1f; - - l = __REG(gpio_ports[port] + GPIO_GDIR); - switch (direction) { - case MX31_GPIO_DIRECTION_OUT: - l |= 1 << gpio; - break; - case MX31_GPIO_DIRECTION_IN: - l &= ~(1 << gpio); - } - __REG(gpio_ports[port] + GPIO_GDIR) = l; - - return 0; -} - -void mx31_gpio_set(unsigned int gpio, unsigned int value) -{ - unsigned int port = gpio >> 5; - u32 l; - - if (port >= ARRAY_SIZE(gpio_ports)) - return; - - gpio &= 0x1f; - - l = __REG(gpio_ports[port] + GPIO_DR); - if (value) - l |= 1 << gpio; - else - l &= ~(1 << gpio); - __REG(gpio_ports[port] + GPIO_DR) = l; -} - -int mx31_gpio_get(unsigned int gpio) -{ - unsigned int port = gpio >> 5; - u32 l; - - if (port >= ARRAY_SIZE(gpio_ports)) - return -1; - - gpio &= 0x1f; - - l = (__REG(gpio_ports[port] + GPIO_DR) >> gpio) & 0x01; - - return l; -} diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c new file mode 100644 index 0000000..663141f --- /dev/null +++ b/drivers/gpio/mxc_gpio.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2009 + * Guennadi Liakhovetski, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#ifdef CONFIG_MX31 +#include +#endif +#ifdef CONFIG_MX51 +#include +#endif +#include +#include + +/* GPIO port description */ +static unsigned long gpio_ports[] = { + [0] = GPIO1_BASE_ADDR, + [1] = GPIO2_BASE_ADDR, + [2] = GPIO3_BASE_ADDR, +#ifdef CONFIG_MX51 + [3] = GPIO4_BASE_ADDR, +#endif +}; + +int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction) +{ + unsigned int port = gpio >> 5; + struct gpio_regs *regs; + u32 l; + + if (port >= ARRAY_SIZE(gpio_ports)) + return 1; + + gpio &= 0x1f; + + regs = (struct gpio_regs *)gpio_ports[port]; + + l = readl(®s->gpio_dir); + + switch (direction) { + case MXC_GPIO_DIRECTION_OUT: + l |= 1 << gpio; + break; + case MXC_GPIO_DIRECTION_IN: + l &= ~(1 << gpio); + } + writel(l, ®s->gpio_dir); + + return 0; +} + +void mxc_gpio_set(unsigned int gpio, unsigned int value) +{ + unsigned int port = gpio >> 5; + struct gpio_regs *regs; + u32 l; + + if (port >= ARRAY_SIZE(gpio_ports)) + return; + + gpio &= 0x1f; + + regs = (struct gpio_regs *)gpio_ports[port]; + + l = readl(®s->gpio_dr); + if (value) + l |= 1 << gpio; + else + l &= ~(1 << gpio); + writel(l, ®s->gpio_dr); +} + +int mxc_gpio_get(unsigned int gpio) +{ + unsigned int port = gpio >> 5; + struct gpio_regs *regs; + u32 l; + + if (port >= ARRAY_SIZE(gpio_ports)) + return -1; + + gpio &= 0x1f; + + regs = (struct gpio_regs *)gpio_ports[port]; + + l = (readl(®s->gpio_dr) >> gpio) & 0x01; + + return l; +} diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index e15a63c..802cd2e 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -23,6 +23,7 @@ #include #include #include +#include #ifdef CONFIG_MX27 /* i.MX27 has a completely wrong register layout and register definitions in the @@ -68,9 +69,6 @@ static unsigned long spi_bases[] = { 0x53f84000, }; -#define OUT MX31_GPIO_DIRECTION_OUT -#define mxc_gpio_direction mx31_gpio_direction -#define mxc_gpio_set mx31_gpio_set #elif defined(CONFIG_MX51) #include #include @@ -111,13 +109,12 @@ static unsigned long spi_bases[] = { CSPI2_BASE_ADDR, CSPI3_BASE_ADDR, }; -#define mxc_gpio_direction(gpio, dir) (0) -#define mxc_gpio_set(gpio, value) {} -#define OUT 1 #else #error "Unsupported architecture" #endif +#define OUT MXC_GPIO_DIRECTION_OUT + struct mxc_spi_slave { struct spi_slave slave; unsigned long base; @@ -126,6 +123,7 @@ struct mxc_spi_slave { u32 cfg_reg; #endif int gpio; + int ss_pol; }; static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) @@ -147,7 +145,7 @@ void spi_cs_activate(struct spi_slave *slave) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); if (mxcs->gpio > 0) - mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL); + mxc_gpio_set(mxcs->gpio, mxcs->ss_pol); } void spi_cs_deactivate(struct spi_slave *slave) @@ -155,7 +153,7 @@ void spi_cs_deactivate(struct spi_slave *slave) struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); if (mxcs->gpio > 0) mxc_gpio_set(mxcs->gpio, - !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL)); + !(mxcs->ss_pol)); } #ifdef CONFIG_MX51 @@ -394,6 +392,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, mxcs->slave.bus = bus; mxcs->slave.cs = cs; mxcs->base = spi_bases[bus]; + mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; #ifdef CONFIG_MX51 /* Can be used for i.MX31 too ? */ diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 1dbafa0..62944a9 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -183,7 +183,7 @@ #ifdef CONFIG_IMX31_PHYCORE_EET #define BOARD_LATE_INIT -#define CONFIG_MX31_GPIO 1 +#define CONFIG_MXC_GPIO #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 diff --git a/include/configs/qong.h b/include/configs/qong.h index 7a68b7b..7cd9558 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -52,7 +52,7 @@ #define CONFIG_MXC_UART 1 #define CONFIG_SYS_MX31_UART1 1 -#define CONFIG_MX31_GPIO +#define CONFIG_MXC_GPIO #define CONFIG_MXC_SPI #define CONFIG_DEFAULT_SPI_BUS 1 diff --git a/include/mxc_gpio.h b/include/mxc_gpio.h new file mode 100644 index 0000000..002ba61 --- /dev/null +++ b/include/mxc_gpio.h @@ -0,0 +1,52 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MXC_GPIO_H +#define __MXC_GPIO_H + +enum mxc_gpio_direction { + MXC_GPIO_DIRECTION_IN, + MXC_GPIO_DIRECTION_OUT, +}; + +#ifdef CONFIG_MXC_GPIO +extern int mxc_gpio_direction(unsigned int gpio, + enum mxc_gpio_direction direction); +extern void mxc_gpio_set(unsigned int gpio, unsigned int value); +extern int mxc_gpio_get(unsigned int gpio); +#else +static inline int mxc_gpio_direction(unsigned int gpio, + enum mxc_gpio_direction direction) +{ + return 1; +} +static inline int mxc_gpio_get(unsigned int gpio) +{ + return 1; +} +static inline void mxc_gpio_set(unsigned int gpio, unsigned int value) +{ +} +#endif + +#endif -- cgit v0.10.2 From 87d98d3b8ef855c9ce1c09ddb1b7ea884a1d4ec6 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 26 Jul 2010 10:05:05 +0200 Subject: ARM: Use syslib functions for all CORTEXA8 The OMAP3 cpu directory contains a syslib file with some utilities that can be shared by all targets using arm cortexa8 processors, not only OMAP. Signed-off-by: Stefano Babic diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index ae20299..7743fef 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -27,6 +27,7 @@ LIB = $(obj)lib$(CPU).a START := start.o COBJS := cpu.o +COBJS += syslib.o SRCS := $(START:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) @@ -44,4 +45,4 @@ include $(SRCTREE)/rules.mk sinclude $(obj).depend -######################################################################### \ No newline at end of file +######################################################################### diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index caee726..aedea7b 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -28,7 +28,6 @@ LIB = $(obj)libomap-common.a SOBJS := reset.o COBJS := timer.o -COBJS += syslib.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/arm/cpu/armv7/omap-common/syslib.c b/arch/arm/cpu/armv7/omap-common/syslib.c deleted file mode 100644 index f9ed9a3..0000000 --- a/arch/arm/cpu/armv7/omap-common/syslib.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * - * Richard Woodruff - * Syed Mohammed Khasim - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/************************************************************ - * sdelay() - simple spin loop. Will be constant time as - * its generally used in bypass conditions only. This - * is necessary until timers are accessible. - * - * not inline to increase chances its in cache when called - *************************************************************/ -void sdelay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = readl((u32)addr) & ~(msk << start_bit); - tmp |= value << start_bit; - writel(tmp, (u32)addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, - u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = readl((u32)read_addr) & read_bit_mask; - if (val == match_value) - return 1; - if (i == bound) - return 0; - } while (1); -} diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/cpu/armv7/syslib.c new file mode 100644 index 0000000..f9ed9a3 --- /dev/null +++ b/arch/arm/cpu/armv7/syslib.c @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * + * Richard Woodruff + * Syed Mohammed Khasim + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/************************************************************ + * sdelay() - simple spin loop. Will be constant time as + * its generally used in bypass conditions only. This + * is necessary until timers are accessible. + * + * not inline to increase chances its in cache when called + *************************************************************/ +void sdelay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = readl((u32)addr) & ~(msk << start_bit); + tmp |= value << start_bit; + writel(tmp, (u32)addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, + u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = readl((u32)read_addr) & read_bit_mask; + if (val == match_value) + return 1; + if (i == bound) + return 0; + } while (1); +} diff --git a/arch/arm/include/asm/arch-mx51/sys_proto.h b/arch/arm/include/asm/arch-mx51/sys_proto.h index bf500a8..f687503 100644 --- a/arch/arm/include/asm/arch-mx51/sys_proto.h +++ b/arch/arm/include/asm/arch-mx51/sys_proto.h @@ -26,5 +26,6 @@ u32 get_cpu_rev(void); #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +void sdelay(unsigned long); #endif -- cgit v0.10.2 From 35af33da00d7059c82fb042bc5a373ff4fd88ada Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 26 Jul 2010 17:28:44 +0200 Subject: MX51: Added pins definition to set up pads Add pins definitions to set up RAM pads. Pins have only a pad, there is no entry in the multiplexer. Signed-off-by: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx51/mx51_pins.h b/arch/arm/include/asm/arch-mx51/mx51_pins.h index ca26f41..b44ff25 100644 --- a/arch/arm/include/asm/arch-mx51/mx51_pins.h +++ b/arch/arm/include/asm/arch-mx51/mx51_pins.h @@ -368,6 +368,50 @@ enum iomux_pins { MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810), MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814), MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818), + + /* The following are PADS used for drive strength */ + + MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820), + MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838), + MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890), + MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C), + MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C), + MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884), + MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C), + MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864), + MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C), + MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874), + MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878), + MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880), + MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C), + MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C), + MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4), + MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC), + MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8), + MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C), + MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0), + MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0), + MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4), + MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC), + MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C), + MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848), + MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868), + MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4), + MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8), + MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac), + MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0), + MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4), + MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8), + MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC), + MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0), + MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4), + MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8), + MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC), + MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0), + MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4), + MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8), + MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC), + MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0), }; #endif /* __ASSEMBLY__ */ -- cgit v0.10.2 From 9583dfab1df155bf81e67859a3c2907ac0418260 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 20 Aug 2010 10:42:31 +0200 Subject: MX51: add structure to access System Reset Controller Signed-off-by: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx51/imx-regs.h b/arch/arm/include/asm/arch-mx51/imx-regs.h index 0e3bc2a..072ad0f 100644 --- a/arch/arm/include/asm/arch-mx51/imx-regs.h +++ b/arch/arm/include/asm/arch-mx51/imx-regs.h @@ -262,6 +262,16 @@ struct gpio_regs { u32 gpio_dir; u32 gpio_psr; }; + +/* System Reset Controller (SRC) */ +struct src { + u32 scr; + u32 sbmr; + u32 srsr; + u32 reserved1[2]; + u32 sisr; + u32 simr; +}; #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MXC_MX51_H__ */ -- cgit v0.10.2 From 4ec3d2a7456eec28fd5bd33680f5e677ac5b0370 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 18 Aug 2010 10:22:42 +0200 Subject: MXC: Add watchdog support to serial driver Calls WATCHDOG_RESET() inside serial driver for boards enabling watchdog. Signed-off-by: Stefano Babic diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 4b93e7b..f96b21f 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -18,6 +18,7 @@ */ #include +#include #ifdef CONFIG_MX31 #include #else @@ -189,7 +190,8 @@ void serial_setbrg (void) int serial_getc (void) { - while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); + while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + WATCHDOG_RESET(); return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ } @@ -198,7 +200,8 @@ void serial_putc (const char c) __REG(UART_PHYS + UTXD) = c; /* wait for transmitter to be ready */ - while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)); + while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) + WATCHDOG_RESET(); /* If \n, also do \r */ if (c == '\n') -- cgit v0.10.2 From 4d0e49d33639394d25a60a4e2d73e99634348af7 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 20 Aug 2010 12:47:31 +0200 Subject: MX51: Drop unused header file for mx51evk As stated in 272017853339f5b9685f9488bdaf5405812d12a4, the mx51evk has not CPLD and all references must be removed. This patch drop a .h file that still remains in board directory. Signed-off-by: Stefano Babic diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 75d642b..84386e6 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -33,12 +33,10 @@ #include #include #include -#include "mx51evk.h" DECLARE_GLOBAL_DATA_PTR; static u32 system_rev; -struct io_board_ctrl *mx51_io_board; #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[2] = { diff --git a/board/freescale/mx51evk/mx51evk.h b/board/freescale/mx51evk/mx51evk.h deleted file mode 100644 index 2854e71..0000000 --- a/board/freescale/mx51evk/mx51evk.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __BOARD_FREESCALE_MX51_EVK_H__ -#define __BOARD_FREESCALE_MX51_EVK_H__ - -#ifndef __ASSEMBLY__ -struct io_board_ctrl { - u16 led_ctrl; /* 0x00 */ - u16 resv1[0x03]; - u16 sb_stat; /* 0x08 */ - u16 resv2[0x03]; - u16 int_stat; /* 0x10 */ - u16 resv3[0x07]; - u16 int_rest; /* 0x20 */ - u16 resv4[0x0B]; - u16 int_mask; /* 0x38 */ - u16 resv5[0x03]; - u16 id1; /* 0x40 */ - u16 resv6[0x03]; - u16 id2; /* 0x48 */ - u16 resv7[0x03]; - u16 version; /* 0x50 */ - u16 resv8[0x03]; - u16 id3; /* 0x58 */ - u16 resv9[0x03]; - u16 sw_reset; /* 0x60 */ -}; -#endif - -#endif -- cgit v0.10.2 From 9f481e95baaca2a5a739f930c16b1cc485b0c1f3 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 23 Aug 2010 20:41:19 +0200 Subject: MXC: Correct SPI_CPOL setting in SPI driver The handling of the SPI_CPOL bit inside the SPI driver was wrong. As reported by the manual, the meaning of the SSPOL inside the configuration register is the same as reported by SPI specification (0 if low in idle, 1 is high on idle). The driver inverts this logic. Because this patch sets the logic as specified, it is required to clear the CPOL bit in the configuration file to adapt to the correct logic. Signed-off-by: Stefano Babic Signed-off-by: David Jander diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 802cd2e..c6c8f60 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -215,7 +215,7 @@ static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, if (mode & SPI_CS_HIGH) ss_pol = 1; - if (!(mode & SPI_CPOL)) + if (mode & SPI_CPOL) sclkpol = 1; if (mode & SPI_CPHA) @@ -412,7 +412,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (mode & SPI_CPHA) ctrl_reg |= MXC_CSPICTRL_PHA; - if (!(mode & SPI_CPOL)) + if (mode & SPI_CPOL) ctrl_reg |= MXC_CSPICTRL_POL; if (mode & SPI_CS_HIGH) ctrl_reg |= MXC_CSPICTRL_SSPOL; diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 4904856..88c62d1 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -66,13 +66,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index dedecd7..57955df 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -63,13 +63,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 0414cc3..4b4fb1a 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -67,13 +67,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 2 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 86a4731..8864f3a 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -73,7 +73,7 @@ #define CONFIG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 2500000 -#define CONFIG_FSL_PMIC_MODE (SPI_CPOL | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) /* * MMC Configs diff --git a/include/configs/qong.h b/include/configs/qong.h index 7cd9558..cbb53dd 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -56,14 +56,14 @@ #define CONFIG_MXC_SPI #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 100000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) /* FPGA */ #define CONFIG_QONG_FPGA 1 -- cgit v0.10.2 From 2f721d17339ee22bbc14fb0bb1dad20b82871923 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 20 Aug 2010 12:05:03 +0200 Subject: MXC: Fix byte-ordering in SPI driver for i.MX31/i.MX51 The actual SPI driver for i.MX31 and i.MX51 controller use a wrong byte ordering, because it is supposed to work only with Freescale's devices, as the Power Controllers (PMIC). The driver is not suitable for general purposes, because the buffers passed to spi_xfer must be 32-bit aligned, as it is used mainly to send integer to PMIC devices. The patch drops any kind of limitation and makes the driver useful with devices controlled sending commands composed by single bytes (or by a odd number of bytes), such as spi flash, sensor, etc. Because the byte ordering is changed, any current driver using this controller must be adapted, too. Signed-off-by: Stefano Babic diff --git a/drivers/misc/fsl_pmic.c b/drivers/misc/fsl_pmic.c index dca0a1d..5ee1de1 100644 --- a/drivers/misc/fsl_pmic.c +++ b/drivers/misc/fsl_pmic.c @@ -46,6 +46,7 @@ void pmic_spi_free(struct spi_slave *slave) u32 pmic_reg(u32 reg, u32 val, u32 write) { u32 pmic_tx, pmic_rx; + u32 tmp; if (!slave) { slave = pmic_spi_probe(); @@ -65,7 +66,9 @@ u32 pmic_reg(u32 reg, u32 val, u32 write) pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF); - if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx, + tmp = cpu_to_be32(pmic_tx); + + if (spi_xfer(slave, 4 << 3, &tmp, &pmic_rx, SPI_XFER_BEGIN | SPI_XFER_END)) { spi_release_bus(slave); return -1; @@ -73,7 +76,8 @@ u32 pmic_reg(u32 reg, u32 val, u32 write) if (write) { pmic_tx &= ~(1 << 31); - if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx, + tmp = cpu_to_be32(pmic_tx); + if (spi_xfer(slave, 4 << 3, &tmp, &pmic_rx, SPI_XFER_BEGIN | SPI_XFER_END)) { spi_release_bus(slave); return -1; @@ -81,7 +85,7 @@ u32 pmic_reg(u32 reg, u32 val, u32 write) } spi_release_bus(slave); - return pmic_rx; + return cpu_to_be32(pmic_rx); } void pmic_reg_write(u32 reg, u32 value) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index c6c8f60..d558137 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -62,6 +62,7 @@ #define MXC_CSPICTRL_MAXBITS 0x1f #define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 static unsigned long spi_bases[] = { 0x43fa4000, @@ -95,6 +96,7 @@ static unsigned long spi_bases[] = { #define MXC_CSPICTRL_RXOVF (1 << 6) #define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 32 /* Bit position inside CTRL register to be associated with SS */ #define MXC_CSPICTRL_CHAN 18 @@ -252,13 +254,15 @@ static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, } #endif -static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, - unsigned long flags) +int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, + const u8 *dout, u8 *din, unsigned long flags) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); + int nbytes = (bitlen + 7) / 8; + u32 data, cnt, i; - if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); + debug("%s: bitlen %d dout 0x%x din 0x%x\n", + __func__, bitlen, (u32)dout, (u32)din); mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | @@ -273,8 +277,46 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, reg_write(mxcs->base + MXC_CSPISTAT, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); - debug("Sending SPI 0x%x\n", data); - reg_write(mxcs->base + MXC_CSPITXDATA, data); + /* + * The SPI controller works only with words, + * check if less than a word is sent. + * Access to the FIFO is only 32 bit + */ + if (bitlen % 32) { + data = 0; + cnt = (bitlen % 32) / 8; + if (dout) { + for (i = 0; i < cnt; i++) { + data = (data << 8) | (*dout++ & 0xFF); + } + } + debug("Sending SPI 0x%x\n", data); + + reg_write(mxcs->base + MXC_CSPITXDATA, data); + nbytes -= cnt; + } + + data = 0; + + while (nbytes > 0) { + data = 0; + if (dout) { + /* Buffer is not 32-bit aligned */ + if ((unsigned long)dout & 0x03) { + data = 0; + for (i = 0; i < 4; i++, data <<= 8) { + data = (data << 8) | (*dout++ & 0xFF); + } + } else { + data = *(u32 *)dout; + data = cpu_to_be32(data); + } + dout += 4; + } + debug("Sending SPI 0x%x\n", data); + reg_write(mxcs->base + MXC_CSPITXDATA, data); + nbytes -= 4; + } /* FIFO is written, now starts the transfer setting the XCH bit */ reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | @@ -288,49 +330,78 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, reg_write(mxcs->base + MXC_CSPISTAT, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); - data = reg_read(mxcs->base + MXC_CSPIRXDATA); - debug("SPI Rx: 0x%x\n", data); + nbytes = (bitlen + 7) / 8; - if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); + cnt = nbytes % 32; - return data; + if (bitlen % 32) { + data = reg_read(mxcs->base + MXC_CSPIRXDATA); + cnt = (bitlen % 32) / 8; + debug("SPI Rx unaligned: 0x%x\n", data); + if (din) { + for (i = 0; i < cnt; i++, data >>= 8) { + *din++ = data & 0xFF; + } + } + nbytes -= cnt; + } + + while (nbytes > 0) { + u32 tmp; + tmp = reg_read(mxcs->base + MXC_CSPIRXDATA); + data = cpu_to_be32(tmp); + debug("SPI Rx: 0x%x 0x%x\n", tmp, data); + cnt = min(nbytes, sizeof(data)); + if (din) { + memcpy(din, &data, cnt); + din += cnt; + } + nbytes -= cnt; + } + + return 0; } + int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { - int n_blks = (bitlen + 31) / 32; - u32 *out_l, *in_l; - int i; + int n_bytes = (bitlen + 7) / 8; + int n_bits; + int ret; + u32 blk_size; + u8 *p_outbuf = (u8 *)dout; + u8 *p_inbuf = (u8 *)din; - if ((int)dout & 3 || (int)din & 3) { - printf("Error: unaligned buffers in: %p, out: %p\n", din, dout); - return 1; - } + if (!slave) + return -1; - /* This driver is currently partly broken, alert the user */ - if (bitlen > 16 && (bitlen % 32)) { - printf("Error: SPI transfer with bitlen=%d is broken.\n", - bitlen); - return 1; + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (n_bytes > 0) { + + if (n_bytes < MAX_SPI_BYTES) + blk_size = n_bytes; + else + blk_size = MAX_SPI_BYTES; + + n_bits = blk_size * 8; + + ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0); + + if (ret) + return ret; + if (dout) + p_outbuf += blk_size; + if (din) + p_inbuf += blk_size; + n_bytes -= blk_size; } - for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout; - i < n_blks; - i++, in_l++, out_l++, bitlen -= 32) { - u32 data = spi_xchg_single(slave, *out_l, bitlen, flags); - - /* Check if we're only transfering 8 or 16 bits */ - if (!i) { - if (bitlen < 9) - *(u8 *)din = data; - else if (bitlen < 17) - *(u16 *)din = data; - else - *in_l = data; - } + if (flags & SPI_XFER_END) { + spi_cs_deactivate(slave); } return 0; @@ -378,8 +449,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; mxcs = malloc(sizeof(struct mxc_spi_slave)); - if (!mxcs) + if (!mxcs) { + puts("mxc_spi: SPI Slave not allocated !\n"); return NULL; + } ret = decode_cs(mxcs, cs); if (ret < 0) { -- cgit v0.10.2 From f3554dfdd9a1efa9412f8a641c69bf4631240d33 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 30 Sep 2010 13:11:57 +0200 Subject: MX51: Register definitions cannot be included in board config file Due to wrong dependencies, it is not possible to include imx_regs.h inside the board configuration file. Signed-off-by: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx51/imx-regs.h b/arch/arm/include/asm/arch-mx51/imx-regs.h index 072ad0f..3ddda40 100644 --- a/arch/arm/include/asm/arch-mx51/imx-regs.h +++ b/arch/arm/include/asm/arch-mx51/imx-regs.h @@ -23,9 +23,6 @@ #ifndef __ASM_ARCH_MXC_MX51_H__ #define __ASM_ARCH_MXC_MX51_H__ -#define __REG(x) (*((volatile u32 *)(x))) -#define __REG16(x) (*((volatile u16 *)(x))) -#define __REG8(x) (*((volatile u8 *)(x))) /* * IRAM */ @@ -207,7 +204,12 @@ #define BOARD_REV_1_0 0x0 #define BOARD_REV_2_0 0x1 -#ifndef __ASSEMBLY__ +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) struct clkctl { u32 ccr; -- cgit v0.10.2 From 4b8d77bb93168e4cbaa2d0f040732de540ad5ea2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Tue, 7 Sep 2010 19:10:33 +0200 Subject: at91_emac.c: fix 'Warning: eth device name has a space!' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch also removes conditional nameing of at91_emac driver whether it's connection to PHY is RMII or MII. Signed-off-by: Andreas Bießmann diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c index d82459b..009a275 100644 --- a/drivers/net/at91_emac.c +++ b/drivers/net/at91_emac.c @@ -500,11 +500,7 @@ int at91emac_register(bd_t *bis, unsigned long iobase) memset(emacfix, 0, sizeof(emac_device)); memset(dev, 0, sizeof(*dev)); -#ifndef CONFIG_RMII - sprintf(dev->name, "AT91 EMAC"); -#else - sprintf(dev->name, "AT91 EMAC RMII"); -#endif + sprintf(dev->name, "emac"); dev->iobase = iobase; dev->priv = emacfix; dev->init = at91emac_init; -- cgit v0.10.2 From 38bda019e484c459e0d7a2ffb7be124bca14f586 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Tue, 7 Sep 2010 19:10:34 +0200 Subject: at91_emac.c: poll for IDLE when writing PHY MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch replaces the unnecessary waiting in at91emac_read() and at91emac_write() by checking the IDLE flag. Signed-off-by: Andreas Bießmann diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c index 009a275..ca2b16b 100644 --- a/drivers/net/at91_emac.c +++ b/drivers/net/at91_emac.c @@ -127,13 +127,19 @@ void at91emac_DisableMDIO(at91_emac_t *at91mac) int at91emac_read(at91_emac_t *at91mac, unsigned char addr, unsigned char reg, unsigned short *value) { + unsigned long netstat; at91emac_EnableMDIO(at91mac); writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R | AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | AT91_EMAC_MAN_PHYA(addr), &at91mac->man); - udelay(10000); + + do { + netstat = readl(&at91mac->sr); + DEBUG_AT91PHY("poll SR %08lx\n", netstat); + } while (!(netstat & AT91_EMAC_SR_IDLE)); + *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK; at91emac_DisableMDIO(at91mac); @@ -146,6 +152,7 @@ int at91emac_read(at91_emac_t *at91mac, unsigned char addr, int at91emac_write(at91_emac_t *at91mac, unsigned char addr, unsigned char reg, unsigned short value) { + unsigned long netstat; DEBUG_AT91PHY("AT91PHY write %x REG(%d)=%x\n", at91mac, reg, &value) at91emac_EnableMDIO(at91mac); @@ -154,9 +161,14 @@ int at91emac_write(at91_emac_t *at91mac, unsigned char addr, AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK), &at91mac->man); - udelay(10000); + + do { + netstat = readl(&at91mac->sr); + DEBUG_AT91PHY("poll SR %08lx\n", netstat); + } while (!(netstat & AT91_EMAC_SR_IDLE)); at91emac_DisableMDIO(at91mac); + return 0; } -- cgit v0.10.2 From 6341c5cf87cc966774dd3be429af9aa1a61cfa68 Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Tue, 14 Sep 2010 16:38:57 +0200 Subject: AT91: convert cpu.c to struct SoC access Signed-off-by: Reinhard Meyer diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/cpu/arm926ejs/at91/cpu.c index 141a7d1..087fe95 100644 --- a/arch/arm/cpu/arm926ejs/at91/cpu.c +++ b/arch/arm/cpu/arm926ejs/at91/cpu.c @@ -1,4 +1,6 @@ /* + * (C) Copyright 2010 + * Reinhard Meyer, reinhard.meyer@emk-elektronik.de * (C) Copyright 2009 * Jean-Christophe PLAGNIOL-VILLARD * @@ -22,12 +24,10 @@ */ #include -#ifdef CONFIG_AT91_LEGACY -#warning Your board is using legacy SoC access. Please update! -#endif #include #include +#include #include #include @@ -35,13 +35,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 0 #endif -/* - * The at91sam9260 has 4 GPBR (0-3), we'll use the last one, nr 3, - * to keep track of the bootcount. - */ -#define AT91_GPBR_BOOTCOUNT_REGISTER 3 -#define AT91_BOOTCOUNT_ADDRESS (AT91_GPBR + 4*AT91_GPBR_BOOTCOUNT_REGISTER) - int arch_cpu_init(void) { return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); @@ -66,27 +59,26 @@ int print_cpuinfo(void) #ifdef CONFIG_BOOTCOUNT_LIMIT /* - * Just as the mpc5xxx, we combine the BOOTCOUNT_MAGIC and boocount - * in one 32-bit register. This is done, as the AT91SAM9260 only has - * 4 GPBR. + * We combine the BOOTCOUNT_MAGIC and bootcount in one 32-bit register. + * This is done so we need to use only one of the four GPBR registers. */ void bootcount_store (ulong a) { - volatile ulong *save_addr = - (volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS); + at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; - *save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff); + writel((BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff), + &gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]); } ulong bootcount_load (void) { - volatile ulong *save_addr = - (volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS); + at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; - if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) + ulong val = readl(&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]); + if ((val & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) return 0; else - return (*save_addr & 0x0000ffff); + return val & 0x0000ffff; } #endif /* CONFIG_BOOTCOUNT_LIMIT */ -- cgit v0.10.2 From b944ad22b45cf46242451286e1c711f8e39b9003 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Tue, 7 Sep 2010 19:10:32 +0200 Subject: at91_emac.h: fix typo in register definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann Acked-by: Jens Scharsig diff --git a/arch/arm/include/asm/arch-at91/at91_emac.h b/arch/arm/include/asm/arch-at91/at91_emac.h index 45ae333..0e2ff78 100644 --- a/arch/arm/include/asm/arch-at91/at91_emac.h +++ b/arch/arm/include/asm/arch-at91/at91_emac.h @@ -61,7 +61,7 @@ typedef struct at91_emac { u32 reserved2[3]; u32 hsh; u32 hsl; - u32 sh1l; + u32 sa1l; u32 sa1h; u32 sa2l; u32 sa2h; -- cgit v0.10.2 From 125637c57265de980bd0d8e7d35f4b9c3d5264e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Fri, 3 Sep 2010 10:28:05 +0200 Subject: atmel_usart: change register access to C structure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch introduces C structure definition for register footprint of atmel's usart. Signed-off-by: Andreas Bießmann diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index cad3412..bfa1f3a 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -1,6 +1,9 @@ /* * Copyright (C) 2004-2006 Atmel Corporation * + * Modified to support C structur SoC access by + * Andreas Bießmann + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -16,10 +19,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include -#ifndef CONFIG_AT91_LEGACY -#define CONFIG_AT91_LEGACY -#warning Please update to use C structur SoC access ! -#endif #include #include @@ -46,6 +45,7 @@ DECLARE_GLOBAL_DATA_PTR; void serial_setbrg(void) { + atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE; unsigned long divisor; unsigned long usart_hz; @@ -56,32 +56,37 @@ void serial_setbrg(void) */ usart_hz = get_usart_clk_rate(USART_ID); divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate; - usart3_writel(BRGR, USART3_BF(CD, divisor)); + writel(USART3_BF(CD, divisor), &usart->brgr); } int serial_init(void) { - usart3_writel(CR, USART3_BIT(RSTRX) | USART3_BIT(RSTTX)); + atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE; + + writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr); serial_setbrg(); - usart3_writel(CR, USART3_BIT(RXEN) | USART3_BIT(TXEN)); - usart3_writel(MR, (USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) + writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr); + writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) | USART3_BF(USCLKS, USART3_USCLKS_MCK) | USART3_BF(CHRL, USART3_CHRL_8) | USART3_BF(PAR, USART3_PAR_NONE) - | USART3_BF(NBSTOP, USART3_NBSTOP_1))); + | USART3_BF(NBSTOP, USART3_NBSTOP_1)), + &usart->mr); return 0; } void serial_putc(char c) { + atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE; + if (c == '\n') serial_putc('\r'); - while (!(usart3_readl(CSR) & USART3_BIT(TXRDY))) ; - usart3_writel(THR, c); + while (!(readl(&usart->csr) & USART3_BIT(TXRDY))); + writel(c, &usart->thr); } void serial_puts(const char *s) @@ -92,12 +97,15 @@ void serial_puts(const char *s) int serial_getc(void) { - while (!(usart3_readl(CSR) & USART3_BIT(RXRDY))) + atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE; + + while (!(readl(&usart->csr) & USART3_BIT(RXRDY))) WATCHDOG_RESET(); - return usart3_readl(RHR); + return readl(&usart->rhr); } int serial_tstc(void) { - return (usart3_readl(CSR) & USART3_BIT(RXRDY)) != 0; + atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE; + return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0; } diff --git a/drivers/serial/atmel_usart.h b/drivers/serial/atmel_usart.h index af3773a..7cfc2d5 100644 --- a/drivers/serial/atmel_usart.h +++ b/drivers/serial/atmel_usart.h @@ -3,6 +3,9 @@ * * Copyright (C) 2005-2006 Atmel Corporation * + * Modified to support C structure SoC access by + * Andreas Bießmann + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -20,32 +23,27 @@ #ifndef __DRIVERS_ATMEL_USART_H__ #define __DRIVERS_ATMEL_USART_H__ -/* USART3 register offsets */ -#define USART3_CR 0x0000 -#define USART3_MR 0x0004 -#define USART3_IER 0x0008 -#define USART3_IDR 0x000c -#define USART3_IMR 0x0010 -#define USART3_CSR 0x0014 -#define USART3_RHR 0x0018 -#define USART3_THR 0x001c -#define USART3_BRGR 0x0020 -#define USART3_RTOR 0x0024 -#define USART3_TTGR 0x0028 -#define USART3_FIDI 0x0040 -#define USART3_NER 0x0044 -#define USART3_XXR 0x0048 -#define USART3_IFR 0x004c -#define USART3_RPR 0x0100 -#define USART3_RCR 0x0104 -#define USART3_TPR 0x0108 -#define USART3_TCR 0x010c -#define USART3_RNPR 0x0110 -#define USART3_RNCR 0x0114 -#define USART3_TNPR 0x0118 -#define USART3_TNCR 0x011c -#define USART3_PTCR 0x0120 -#define USART3_PTSR 0x0124 +/* USART3 register footprint */ +typedef struct atmel_usart3 { + u32 cr; + u32 mr; + u32 ier; + u32 idr; + u32 imr; + u32 csr; + u32 rhr; + u32 thr; + u32 brgr; + u32 rtor; + u32 ttgr; + u32 reserved0[5]; + u32 fidi; + u32 ner; + u32 reserved1; + u32 ifr; + u32 man; + u32 reserved2[54]; // version and PDC not needed +} atmel_usart3_t; /* Bitfields in CR */ #define USART3_RSTRX_OFFSET 2 @@ -305,10 +303,4 @@ << USART3_##name##_OFFSET)) \ | USART3_BF(name,value)) -/* Register access macros */ -#define usart3_readl(reg) \ - readl((void *)USART_BASE + USART3_##reg) -#define usart3_writel(reg,value) \ - writel((value), (void *)USART_BASE + USART3_##reg) - #endif /* __DRIVERS_ATMEL_USART_H__ */ -- cgit v0.10.2 From c8f6d84d10d324e0b0462e09629f210b046e1018 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 13 Sep 2010 08:26:39 +0200 Subject: at91: Add arch_preboot_os which disables PIT in a faster way When disabled the PIT runs until it reaches the CPIV value. The Linux PIT driver stops the PIT and waits until it stopped. This can take over 100ms. Simply stopping in u-boot isn't sufficient as the PIT will still be running when Linux is waiting until it stopped. So, we stop it in u-boot by setting the compare value to a value slightly greater than the current running counter to make the PIT stopped in short time. Signed-off-by: Alexander Stein diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/cpu/arm926ejs/at91/cpu.c index 087fe95..5e30f1d 100644 --- a/arch/arm/cpu/arm926ejs/at91/cpu.c +++ b/arch/arm/cpu/arm926ejs/at91/cpu.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include @@ -40,6 +41,21 @@ int arch_cpu_init(void) return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); } +void arch_preboot_os(void) +{ + ulong cpiv; + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + + cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir)); + + /* + * Disable PITC + * Add 0x1000 to current counter to stop it faster + * without waiting for wrapping back to 0 + */ + writel(cpiv + 0x1000, &pit->mr); +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { -- cgit v0.10.2 From f8f8acd7249d224ed5f9704a5738c469b137bc8e Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 6 Jul 2010 19:32:09 +0200 Subject: MX51: Support for TTECH vision2 board The patch adds support for TTECH vision2 board. The board has 512MB RAM, SDHC slot and 4MB SPI device from StMicron. Signed-off-by: Stefano Babic diff --git a/MAINTAINERS b/MAINTAINERS index 2cf29dd..b348559 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -547,6 +547,7 @@ Stefano Babic polaris xscale trizepsiv xscale mx51evk i.MX51 + vision2 i.MX51 Dirk Behme diff --git a/board/ttcontrol/vision2/Makefile b/board/ttcontrol/vision2/Makefile new file mode 100644 index 0000000..309e3a3 --- /dev/null +++ b/board/ttcontrol/vision2/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := vision2.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ttcontrol/vision2/config.mk b/board/ttcontrol/vision2/config.mk new file mode 100644 index 0000000..59f3367 --- /dev/null +++ b/board/ttcontrol/vision2/config.mk @@ -0,0 +1,25 @@ +# +# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds +TEXT_BASE = 0x97800000 +IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage_hynix.cfg diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg new file mode 100644 index 0000000..ed531db --- /dev/null +++ b/board/ttcontrol/vision2/imximage_hynix.cfg @@ -0,0 +1,209 @@ +# +# (C) Copyright 2009 +# Stefano Babic DENX Software Engineering sbabic@denx.de. +# +# (C) Copyright 2010 +# Klaus Steinhammer TTECH Control Gmbh kst@tttech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# Boot Device : one of +# spi, nand, onenand, sd + +BOOT_FROM spi + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register + +####################### +### Disable WDOG ### +####################### +DATA 2 0x73f98000 0x30 + +####################### +### SET DDR Clk ### +####################### + +# CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) +DATA 4 0x73FD4018 0x000024C0 + +# DOUBLE SPI CLK (13MHz->26 MHz Clock) +DATA 4 0x73FD4038 0x2010241 + +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa8600 0x00000107 +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa8604 0x00000107 +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa8608 0x00000187 +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa860c 0x00000187 +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa8614 0x00000107 +#IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) +DATA 4 0x73fa86a8 0x00000187 + +####################### +### Settings IOMUXC ### +####################### + +# DDR IOMUX configuration +# Control, Data, Address pads are in their default state: HIGH DS, FAST SR. +# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS +DATA 4 0x73fa84b8 0x000000e7 +# PVTC MAX (at GPC, PGR reg) +#DATA 4 0x73FD8004 0x1fc00000 + +#DQM0 DS high slew rate slow +DATA 4 0x73fa84d4 0x000000e4 +#DQM1 DS high slew rate slow +DATA 4 0x73fa84d8 0x000000e4 +#DQM2 DS high slew rate slow +DATA 4 0x73fa84dc 0x000000e4 +#DQM3 DS high slew rate slow +DATA 4 0x73fa84e0 0x000000e4 + +#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow +DATA 4 0x73fa84bc 0x000000c4 +#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow +DATA 4 0x73fa84c0 0x000000c4 +#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow +DATA 4 0x73fa84c4 0x000000c4 +#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow +DATA 4 0x73fa84c8 0x000000c4 + +#DRAM_DATA B0 +DATA 4 0x73fa88a4 0x00000004 +#DRAM_DATA B1 +DATA 4 0x73fa88ac 0x00000004 +#DRAM_DATA B2 +DATA 4 0x73fa88b8 0x00000004 +#DRAM_DATA B3 +DATA 4 0x73fa882c 0x00000004 + +#DRAM_DATA B0 slew rate +DATA 4 0x73fa8878 0x00000000 +#DRAM_DATA B1 slew rate +DATA 4 0x73fa8880 0x00000000 +#DRAM_DATA B2 slew rate +DATA 4 0x73fa888c 0x00000000 +#DRAM_DATA B3 slew rate +DATA 4 0x73fa889c 0x00000000 + +####################### +### Configure SDRAM ### +####################### + +# Configure CS0 +####################### + +# ESDCTL0: Enable controller +DATA 4 0x83fd9000 0x83220000 + +# Init DRAM on CS0 +# ESDSCR: Precharge command +DATA 4 0x83fd9014 0x04008008 +# ESDSCR: Refresh command +DATA 4 0x83fd9014 0x00008010 +# ESDSCR: Refresh command +DATA 4 0x83fd9014 0x00008010 +# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) +DATA 4 0x83fd9014 0x00338018 +# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) +DATA 4 0x83fd9014 0x0020801a +# ESDSCR +DATA 4 0x83fd9014 0x00008000 + +# ESDSCR: EMR with full Drive strength +#DATA 4 0x83fd9014 0x0000801a + +# ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 +DATA 4 0x83fd9000 0xC3220000 + +# ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks +# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks +#DATA 4 0x83fd9004 0xC33574AA + +#micron mDDR +# ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks +# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks +#DATA 4 0x83FD9004 0x101564a8 + +#hynix mDDR +# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks +# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks +DATA 4 0x83FD9004 0x704564a8 + +# ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 +DATA 4 0x83fd9010 0x000a1700 + +# Configure CS1 +####################### + +# ESDCTL1: Enable controller +DATA 4 0x83fd9008 0x83220000 + +# Init DRAM on CS1 +# ESDSCR: Precharge command +DATA 4 0x83fd9014 0x0400800c +# ESDSCR: Refresh command +DATA 4 0x83fd9014 0x00008014 +# ESDSCR: Refresh command +DATA 4 0x83fd9014 0x00008014 +# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) +DATA 4 0x83fd9014 0x0033801c +# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) +DATA 4 0x83fd9014 0x0020801e +# ESDSCR +DATA 4 0x83fd9014 0x00008004 + +# ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 +DATA 4 0x83fd9008 0xC3220000 + +# ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks +# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks +#DATA 4 0x83fd900c 0xC33574AA + +#micron mDDR +# ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks +# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks +#DATA 4 0x83FD900C 0x101564a8 + +#hynix mDDR +# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks +# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks +DATA 4 0x83FD900C 0x704564a8 + +# ESDSCR (mDRAM configuration finished) +DATA 4 0x83FD9014 0x00000004 + +# ESDSCR - clear "configuration request" bit +DATA 4 0x83fd9014 0x00000000 diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c new file mode 100644 index 0000000..c991ee2 --- /dev/null +++ b/board/ttcontrol/vision2/vision2.c @@ -0,0 +1,711 @@ +/* + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; + +#ifdef CONFIG_HW_WATCHDOG +#include + +void hw_watchdog_reset(void) +{ + int val; + + /* toggle watchdog trigger pin */ + val = mxc_gpio_get(66); + val = val ? 0 : 1; + mxc_gpio_set(66, val); +} +#endif + +static void init_drive_strength(void) +{ + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS, + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS, + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM); + + /* Setting pad options */ + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); +} + +u32 get_board_rev(void) +{ + system_rev = get_cpu_rev(); + + return system_rev; +} + +int dram_init(void) +{ +#ifdef CONFIG_SYS_ARM_WITHOUT_RELOC + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); +#if (CONFIG_NR_DRAM_BANKS > 1) + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); +#endif +#else + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); +#endif + + return 0; +} + +static void setup_weim(void) +{ + struct weim *pweim = (struct weim *)WEIM_BASE_ADDR; + + pweim->csgcr1 = 0x004100b9; + pweim->csgcr2 = 0x00000001; + pweim->csrcr1 = 0x0a018000; + pweim->csrcr2 = 0; + pweim->cswcr1 = 0x0704a240; +} + +static void setup_uart(void) +{ + unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST; + /* console RX on Pin EIM_D25 */ + mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad); + /* console TX on Pin EIM_D26 */ + mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad); +} + +#ifdef CONFIG_MXC_SPI +void spi_io_init(void) +{ + /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ + mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* + * SS1 will be used as GPIO because of uninterrupted + * long SPI transmissions (GPIO4_25) + */ + mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7); + mxc_iomux_set_pad(MX51_PIN_DI1_PIN11, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); +} + +static void reset_peripherals(int reset) +{ + if (reset) { + + /* reset_n is on NANDF_D15 */ + mxc_gpio_set(89, 0); + mxc_gpio_direction(89, MXC_GPIO_DIRECTION_OUT); + +#ifdef CONFIG_VISION2_HW_1_0 + /* + * set FEC Configuration lines + * set levels of FEC config lines + */ + mxc_gpio_set(75, 0); + mxc_gpio_set(74, 1); + mxc_gpio_set(95, 1); + mxc_gpio_direction(75, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(74, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(95, MXC_GPIO_DIRECTION_OUT); + + /* set direction of FEC config lines */ + mxc_gpio_set(59, 0); + mxc_gpio_set(60, 0); + mxc_gpio_set(61, 0); + mxc_gpio_set(55, 1); + mxc_gpio_direction(59, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(60, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(61, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(55, MXC_GPIO_DIRECTION_OUT); + + /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */ + mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1); + /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */ + mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1); + /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */ + mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1); + /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */ + mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1); + /* FEC_COL - sel GPIO (3-10) for configuration -> 1 */ + mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3); + /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */ + mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3); + /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */ + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3); +#endif + + /* + * activate reset_n pin + * Select mux mode: ALT3 mux port: NAND D15 + */ + mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_NANDF_D15, + PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX); + } else { + /* set FEC Control lines */ + mxc_gpio_direction(89, MXC_GPIO_DIRECTION_IN); + udelay(500); + +#ifdef CONFIG_VISION2_HW_1_0 + /* FEC RDATA[3] */ + mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); + + /* FEC RDATA[2] */ + mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); + + /* FEC RDATA[1] */ + mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); + + /* FEC RDATA[0] */ + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); + + /* FEC RX_CLK */ + mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); + + /* FEC RX_ER */ + mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); + + /* FEC COL */ + mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); +#endif + } +} + +static void power_init_mx51(void) +{ + unsigned int val; + + /* Write needed to Power Gate 2 register */ + val = pmic_reg_read(REG_POWER_MISC); + + /* enable VCAM with 2.775V to enable read from PMIC */ + val = VCAMCONFIG | VCAMEN; + pmic_reg_write(REG_MODE_1, val); + + /* + * Set switchers in Auto in NORMAL mode & STANDBY mode + * Setup the switcher mode for SW1 & SW2 + */ + val = pmic_reg_read(REG_SW_4); + val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | + (SWMODE_MASK << SWMODE2_SHIFT))); + val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); + pmic_reg_write(REG_SW_4, val); + + /* Setup the switcher mode for SW3 & SW4 */ + val = pmic_reg_read(REG_SW_5); + val &= ~((SWMODE_MASK << SWMODE4_SHIFT) | + (SWMODE_MASK << SWMODE3_SHIFT)); + val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE3_SHIFT); + pmic_reg_write(REG_SW_5, val); + + + /* Set VGEN3 to 1.8V, VCAM to 3.0V */ + val = pmic_reg_read(REG_SETTING_0); + val &= ~(VCAM_MASK | VGEN3_MASK); + val |= VCAM_3_0; + pmic_reg_write(REG_SETTING_0, val); + + /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */ + val = pmic_reg_read(REG_SETTING_1); + val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); + val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8; + pmic_reg_write(REG_SETTING_1, val); + + /* Configure VGEN3 and VCAM regulators to use external PNP */ + val = VGEN3CONFIG | VCAMCONFIG; + pmic_reg_write(REG_MODE_1, val); + udelay(200); + + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ + val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | + VVIDEOEN | VAUDIOEN | VSDEN; + pmic_reg_write(REG_MODE_1, val); + + val = pmic_reg_read(REG_POWER_CTL2); + val |= WDIRESET; + pmic_reg_write(REG_POWER_CTL2, val); + + udelay(2500); + +} +#endif + +static void setup_gpios(void) +{ + unsigned int i; + + /* CAM_SUP_DISn, GPIO1_7 */ + mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82); + + /* DAB Display EN, GPIO3_1 */ + mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82); + + /* WDOG_TRIGGER, GPIO3_2 */ + mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82); + + /* Now we need to trigger the watchdog */ + WATCHDOG_RESET(); + + /* Display2 TxEN, GPIO3_3 */ + mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82); + + /* DAB Light EN, GPIO3_4 */ + mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82); + + /* AUDIO_MUTE, GPIO3_5 */ + mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82); + + /* SPARE_OUT, GPIO3_6 */ + mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82); + + /* BEEPER_EN, GPIO3_26 */ + mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82); + + /* POWER_OFF, GPIO3_27 */ + mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82); + + /* FRAM_WE, GPIO3_30 */ + mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82); + + /* EXPANSION_EN, GPIO4_26 */ + mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82); + + /* + * Set GPIO1_4 to high and output; it is used to reset + * the system on reboot + */ + mxc_gpio_set(4, 1); + mxc_gpio_direction(4, MXC_GPIO_DIRECTION_OUT); + + mxc_gpio_set(7, 0); + mxc_gpio_direction(7, MXC_GPIO_DIRECTION_OUT); + for (i = 65; i < 71; i++) { + mxc_gpio_set(i, 0); + mxc_gpio_direction(i, MXC_GPIO_DIRECTION_OUT); + } + + mxc_gpio_set(94, 0); + mxc_gpio_direction(94, MXC_GPIO_DIRECTION_OUT); + + /* Set POWER_OFF high */ + mxc_gpio_set(91, 1); + mxc_gpio_direction(91, MXC_GPIO_DIRECTION_OUT); + + mxc_gpio_set(90, 0); + mxc_gpio_direction(90, MXC_GPIO_DIRECTION_OUT); + + mxc_gpio_set(122, 0); + mxc_gpio_direction(122, MXC_GPIO_DIRECTION_OUT); + + mxc_gpio_set(121, 1); + mxc_gpio_direction(121, MXC_GPIO_DIRECTION_OUT); + + WATCHDOG_RESET(); +} + +static void setup_fec(void) +{ + /*FEC_MDIO*/ + mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD); + + /*FEC_MDC*/ + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004); + + /* FEC RDATA[3] */ + mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); + + /* FEC RDATA[2] */ + mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); + + /* FEC RDATA[1] */ + mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); + + /* FEC RDATA[0] */ + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); + + /* FEC TDATA[3] */ + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004); + + /* FEC TDATA[2] */ + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004); + + /* FEC TDATA[1] */ + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004); + + /* FEC TDATA[0] */ + mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004); + + /* FEC TX_EN */ + mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004); + + /* FEC TX_ER */ + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004); + + /* FEC TX_CLK */ + mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180); + + /* FEC TX_COL */ + mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); + + /* FEC RX_CLK */ + mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); + + /* FEC RX_CRS */ + mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180); + + /* FEC RX_ER */ + mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); + + /* FEC RX_DV */ + mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180); +} + +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {MMC_SDHC1_BASE_ADDR, 1}, +}; + +int get_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) + *cd = mxc_gpio_get(0); + else + *cd = 0; + + return 0; +} + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_init(bd_t *bis) +{ + mxc_request_iomux(MX51_PIN_SD1_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD1_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_GPIO1_0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_0, + PAD_CTL_HYS_ENABLE); + mxc_request_iomux(MX51_PIN_GPIO1_1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_1, + PAD_CTL_HYS_ENABLE); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} +#endif + +int board_early_init_f(void) +{ + + + init_drive_strength(); + + /* Setup debug led */ + mxc_gpio_set(6, 0); + mxc_gpio_direction(6, MXC_GPIO_DIRECTION_OUT); + mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* wait a little while to give the pll time to settle */ + sdelay(100000); + + setup_weim(); + setup_uart(); + setup_fec(); + setup_gpios(); + + spi_io_init(); + + return 0; +} + +int board_init(void) +{ +#ifdef CONFIG_SYS_ARM_WITHOUT_RELOC + board_early_init_f(); +#endif + gd->bd->bi_arch_number = MACH_TYPE_TTC_VISION2; /* board id for linux */ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int board_late_init(void) +{ + power_init_mx51(); + + reset_peripherals(1); + udelay(2000); + reset_peripherals(0); + udelay(2000); + + /* Early revisions require a second reset */ +#ifdef CONFIG_VISION2_HW_1_0 + reset_peripherals(1); + udelay(2000); + reset_peripherals(0); + udelay(2000); +#endif + + return 0; +} + +int checkboard(void) +{ + u32 system_rev = get_cpu_rev(); + u32 cause; + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + + puts("Board: TTControl Vision II CPU V"); + + switch (system_rev & 0xff) { + case CHIP_REV_3_0: + puts("3.0 ["); + break; + case CHIP_REV_2_5: + puts("2.5 ["); + break; + case CHIP_REV_2_0: + puts("2.0 ["); + break; + case CHIP_REV_1_1: + puts("1.1 ["); + break; + case CHIP_REV_1_0: + default: + puts("1.0 ["); + break; + } + + cause = src_regs->srsr; + switch (cause) { + case 0x0001: + puts("POR"); + break; + case 0x0009: + puts("RST"); + break; + case 0x0010: + case 0x0011: + puts("WDOG"); + break; + default: + printf("unknown 0x%x", cause); + } + puts("]\n"); + + return 0; +} + diff --git a/boards.cfg b/boards.cfg index 02eb153..88c4060 100644 --- a/boards.cfg +++ b/boards.cfg @@ -47,6 +47,7 @@ jadecpu arm arm926ejs jadecpu syteco mb86r0x suen3 arm arm926ejs km_arm keymile kirkwood rd6281a arm arm926ejs - Marvell kirkwood mx51evk arm armv7 mx51evk freescale mx51 +vision2 arm armv7 vision2 ttcontrol mx51 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/vision2.h b/include/configs/vision2.h new file mode 100644 index 0000000..44a6f8b --- /dev/null +++ b/include/configs/vision2.h @@ -0,0 +1,214 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX51-3Stack Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_MX51 /* in a mx51 */ +#define CONFIG_L2_OFF + +#define CONFIG_MX51_HCLK_FREQ 24000000 +#define CONFIG_MX51_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define BOARD_LATE_INIT + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (2048 * 1024) + +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX51_UART3 +#define CONFIG_MXC_GPIO +#define CONFIG_MXC_SPI +#define CONFIG_HW_WATCHDOG + + /* + * SPI Configs + * */ +#define CONFIG_FSL_SF +#define CONFIG_CMD_SF + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + +/* + * Use gpio 4 pin 25 as chip select for SPI flash + * This corresponds to gpio 121 + */ +#define CONFIG_SPI_FLASH_CS (1 | (121 << 8)) +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 25000000 + +#define CONFIG_ENV_SPI_CS (1 | (121 << 8)) +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) +#define CONFIG_ENV_SIZE (4 * 1024) + +#define CONFIG_FSL_ENV_IN_SF +#define CONFIG_ENV_IS_IN_SPI_FLASH + +/* PMIC Controller */ +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 0 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 2500000 +#define CONFIG_FSL_PMIC_MODE SPI_MODE_0 +#define CONFIG_RTC_MC13783 + +/* + * MMC Configs + */ +#define CONFIG_FSL_ESDHC +#ifdef CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000) +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + +#define CONFIG_MMC + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_CMD_DATE + +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 3 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_SPI +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=0x90800000\0" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "Vision II U-boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x90000000 +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "Vision II U-boot > " + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024) +#define CONFIG_SYS_SDRAM_BASE 0x90000000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x1FFE8000 + +#ifndef CONFIG_SYS_ARM_WITHOUT_RELOC +#define CONFIG_SYS_INIT_RAM_END (64 * 1024) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET) +#undef CONFIG_SKIP_RELOCATE_UBOOT +#else +#define CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + 0x2000) +#endif + +#define CONFIG_BOARD_EARLY_INIT_F + +/* 166 MHz DDR RAM */ +#define CONFIG_SYS_DDR_CLKSEL 0 +#define CONFIG_SYS_CLKTL_CBCDR 0x19239100 + +#define CONFIG_SYS_NO_FLASH + +#endif /* __CONFIG_H */ diff --git a/include/mc13892.h b/include/mc13892.h index b291757..791e3ec 100644 --- a/include/mc13892.h +++ b/include/mc13892.h @@ -157,4 +157,7 @@ #define VSDSTBY (1 << 19) #define VSDMODE (1 << 20) +/* Reg Power Control 2*/ +#define WDIRESET (1 << 12) + #endif -- cgit v0.10.2 From da90d4ce386d0481c2e772624dfc32e511829238 Mon Sep 17 00:00:00 2001 From: Albert Aribaud Date: Tue, 5 Oct 2010 16:06:39 +0200 Subject: arm: bugfix: replace ble with blo in start.S files Generalized misuse of ble within relocation and bss initialization loops caused one iteration too many. Instead of ble ('branch if lower or equal'), use blo ('branch if lower'). While we're at it, fix all 'addreee' typos. Signed-off-by: Albert Aribaud diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 8b63192..494768e 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -235,8 +235,8 @@ stack_setup: copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #ifndef CONFIG_PRELOADER /* fix got entries */ @@ -355,8 +355,8 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ /* Set up the stack */ diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index e5e7913..6277ae0 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -284,8 +284,8 @@ stack_setup: copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #ifndef CONFIG_PRELOADER /* fix got entries */ @@ -500,8 +500,8 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ #ifdef CONFIG_ENABLE_MMU @@ -559,7 +559,7 @@ clbss_l: str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 - ble clbss_l + blo clbss_l #ifndef CONFIG_NAND_SPL ldr pc, _start_armboot diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 0f5f6c4..6a8d57b 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -201,8 +201,8 @@ stack_setup: copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #ifndef CONFIG_PRELOADER /* fix got entries */ @@ -318,8 +318,8 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ @@ -342,7 +342,7 @@ clear_bss: clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 - ble clbss_l + blo clbss_l ldr pc, _start_armboot diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index a079bb2..09ee815 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -246,8 +246,8 @@ stack_setup: copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #ifndef CONFIG_PRELOADER /* fix got entries */ @@ -406,8 +406,8 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ /* Set up the stack */ @@ -429,7 +429,7 @@ clear_bss: clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 - ble clbss_l + blo clbss_l ldr pc, _start_armboot diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index c0a856d..f173400 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -238,8 +238,8 @@ stack_setup: copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #ifndef CONFIG_PRELOADER /* fix got entries */ @@ -377,8 +377,8 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ /* Set up the stack */ @@ -400,7 +400,7 @@ clear_bss: clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 - ble clbss_l + blo clbss_l ldr pc, _start_armboot diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 16ee972..a960689 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -236,8 +236,8 @@ stack_setup: copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #ifndef CONFIG_PRELOADER /* fix got entries */ @@ -341,8 +341,8 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ /* Set up the stack */ @@ -368,7 +368,7 @@ clear_bss: clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 - ble clbss_l + blo clbss_l bl coloured_LED_init bl red_LED_on diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 18ed0b2..4f062e5 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -207,8 +207,8 @@ stack_setup: copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #ifndef CONFIG_PRELOADER /* fix got entries */ @@ -309,8 +309,8 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop /* Set up the stack */ stack_setup: diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index b39fdc6..79ef517 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -205,8 +205,8 @@ stack_setup: copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #ifndef CONFIG_PRELOADER /* fix got entries */ @@ -305,8 +305,8 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop /* Set up the stack */ stack_setup: @@ -327,7 +327,7 @@ clear_bss: clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 - ble clbss_l + blo clbss_l ldr pc, _start_armboot diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index f411c0f..c392c5d 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -209,8 +209,8 @@ stack_setup: copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #ifndef CONFIG_PRELOADER /* fix got entries */ @@ -324,8 +324,8 @@ relocate: @ relocate U-Boot to RAM copy_loop: @ copy 32 bytes at a time ldmia r0!, {r3 - r10} @ copy from source address [r0] stmia r1!, {r3 - r10} @ copy to target address [r1] - cmp r0, r2 @ until source end addreee [r2] - ble copy_loop + cmp r0, r2 @ until source end address [r2] + blo copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ /* Set up the stack */ diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index b2c8255..940d45d 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -330,8 +330,8 @@ stack_setup: copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #ifndef CONFIG_PRELOADER /* fix got entries */ @@ -547,8 +547,8 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ /* Set up the stack */ @@ -570,7 +570,7 @@ clear_bss: clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 - ble clbss_l + blo clbss_l ldr pc, _start_armboot diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S index 002116a..b8cf1b8 100644 --- a/arch/arm/cpu/lh7a40x/start.S +++ b/arch/arm/cpu/lh7a40x/start.S @@ -219,8 +219,8 @@ stack_setup: copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #ifndef CONFIG_PRELOADER /* fix got entries */ @@ -341,9 +341,8 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - blt copy_loop /* a 'ble' here actually copies */ - /* four bytes of bss */ + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ /* Set up the stack */ @@ -367,7 +366,7 @@ clear_bss: clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 - ble clbss_l + blo clbss_l ldr pc, _start_armboot diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 064ddbc..cfb9411 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -204,8 +204,8 @@ stack_setup: copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #ifndef CONFIG_PRELOADER /* fix got entries */ @@ -310,7 +310,7 @@ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ - ble copy_loop + blo copy_loop #endif /* !CONFIG_SKIP_RELOCATE_UBOOT */ /* Set up the stack */ @@ -337,7 +337,7 @@ clear_bss: clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 - ble clbss_l + blo clbss_l #endif ldr pc, _start_armboot diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index e1ab5cc..c5a67dc 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -191,8 +191,8 @@ stack_setup: copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #ifndef CONFIG_PRELOADER /* fix got entries */ @@ -225,7 +225,7 @@ vector_copy_loop: ldmia r0!, {r3-r10} stmia r1!, {r3-r10} cmp r0, r2 - ble vector_copy_loop + blo vector_copy_loop #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ clear_bss: @@ -310,8 +310,8 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop /* now copy to sram the interrupt vector @@ -324,7 +324,7 @@ vector_copy_loop: ldmia r0!, {r3-r10} stmia r1!, {r3-r10} cmp r0, r2 - ble vector_copy_loop + blo vector_copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ /* Set up the stack */ diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 4730e5a..d1262ad 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -195,8 +195,8 @@ stack_setup: copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #ifndef CONFIG_PRELOADER /* fix got entries */ @@ -293,8 +293,8 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ /* Set up the stack */ @@ -316,7 +316,7 @@ clear_bss: clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 - ble clbss_l + blo clbss_l ldr pc, _start_armboot -- cgit v0.10.2 From d778a2fbb360530395dfbc0dbe1f80b7bf959028 Mon Sep 17 00:00:00 2001 From: Albert Aribaud Date: Thu, 23 Sep 2010 21:49:23 +0200 Subject: orion5x: fix relocation-incompatible code Signed-off-by: Albert Aribaud diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index 260f88b..c36d7bf 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -77,6 +77,17 @@ unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) * * If remap function not used, remap_lo must be set as base * + * NOTES: + * + * 1) in order to avoid windows with inconsistent control and base values + * (which could prevent access to BOOTCS and hence execution from FLASH) + * always disable window before writing the base value then reenable it + * by writing the control value. + * + * 2) in order to avoid losing access to BOOTCS when disabling window 7, + * first configure window 6 for BOOTCS, then configure window 7 for BOOTCS, + * then configure windows 6 for its own target. + * * Reference Documentation: * Mbus-L to Mbus Bridge Registers Configuration. * (Sec 25.1 and 25.3 of Datasheet) @@ -86,57 +97,64 @@ int orion5x_config_adr_windows(void) struct orion5x_win_registers *winregs = (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE; - /* Window 0: PCIE MEM address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM, - ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM, - ORION5X_WIN_ENABLE), &winregs[0].ctrl); +/* Disable window 0, configure it for its intended target, enable it. */ + writel(0, &winregs[0].ctrl); writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base); writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo); writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi); - - /* Window 1: PCIE IO address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO, - ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO, - ORION5X_WIN_ENABLE), &winregs[1].ctrl); + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM, + ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM, + ORION5X_WIN_ENABLE), &winregs[0].ctrl); +/* Disable window 1, configure it for its intended target, enable it. */ + writel(0, &winregs[1].ctrl); writel(ORION5X_ADR_PCIE_IO, &winregs[1].base); writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo); writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi); - - /* Window 2: PCI MEM address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO, + ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO, + ORION5X_WIN_ENABLE), &winregs[1].ctrl); +/* Disable window 2, configure it for its intended target, enable it. */ + writel(0, &winregs[2].ctrl); + writel(ORION5X_ADR_PCI_MEM, &winregs[2].base); writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM, ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM, ORION5X_WIN_ENABLE), &winregs[2].ctrl); - writel(ORION5X_ADR_PCI_MEM, &winregs[2].base); - - /* Window 3: PCI IO address space */ +/* Disable window 3, configure it for its intended target, enable it. */ + writel(0, &winregs[3].ctrl); + writel(ORION5X_ADR_PCI_IO, &winregs[3].base); writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO, ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO, ORION5X_WIN_ENABLE), &winregs[3].ctrl); - writel(ORION5X_ADR_PCI_IO, &winregs[3].base); - - /* Window 4: DEV_CS0 address space */ +/* Disable window 4, configure it for its intended target, enable it. */ + writel(0, &winregs[4].ctrl); + writel(ORION5X_ADR_DEV_CS0, &winregs[4].base); writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0, ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0, ORION5X_WIN_ENABLE), &winregs[4].ctrl); - writel(ORION5X_ADR_DEV_CS0, &winregs[4].base); - - /* Window 5: DEV_CS1 address space */ +/* Disable window 5, configure it for its intended target, enable it. */ + writel(0, &winregs[5].ctrl); + writel(ORION5X_ADR_DEV_CS1, &winregs[5].base); writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1, ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1, ORION5X_WIN_ENABLE), &winregs[5].ctrl); - writel(ORION5X_ADR_DEV_CS1, &winregs[5].base); - - /* Window 6: DEV_CS2 address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2, - ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2, +/* Disable window 6, configure it for FLASH, enable it. */ + writel(0, &winregs[6].ctrl); + writel(ORION5X_ADR_BOOTROM, &winregs[6].base); + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM, ORION5X_WIN_ENABLE), &winregs[6].ctrl); - writel(ORION5X_ADR_DEV_CS2, &winregs[6].base); - - /* Window 7: BOOT Memory address space */ +/* Disable window 7, configure it for FLASH, enable it. */ + writel(0, &winregs[7].ctrl); + writel(ORION5X_ADR_BOOTROM, &winregs[7].base); writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM, ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM, ORION5X_WIN_ENABLE), &winregs[7].ctrl); - writel(ORION5X_ADR_BOOTROM, &winregs[7].base); +/* Disable window 6, configure it for its intended target, enable it. */ + writel(0, &winregs[6].ctrl); + writel(ORION5X_ADR_DEV_CS2, &winregs[6].base); + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2, + ORION5X_WIN_ENABLE), &winregs[6].ctrl); return 0; } @@ -265,6 +283,8 @@ int arch_misc_init(void) writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50); writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04); + /* initialize timer */ + timer_init_r(); return 0; } #endif /* CONFIG_ARCH_MISC_INIT */ diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c index 115448f..089ef47 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/timer.c +++ b/arch/arm/cpu/arm926ejs/orion5x/timer.c @@ -173,9 +173,11 @@ int timer_init(void) cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); writel(cntmrctrl, CNTMR_CTRL_REG); + return 0; +} +void timer_init_r(void) +{ /* init the timestamp and lastdec value */ reset_timer_masked(); - - return 0; } diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h index 6ce02a9..c84efaf 100644 --- a/arch/arm/include/asm/arch-orion5x/cpu.h +++ b/arch/arm/include/asm/arch-orion5x/cpu.h @@ -255,5 +255,6 @@ void reset_cpu(unsigned long ignored); u32 orion5x_device_id(void); u32 orion5x_device_rev(void); unsigned int orion5x_winctrl_calcsize(unsigned int sizeval); +void timer_init_r(void); #endif /* __ASSEMBLY__ */ #endif /* _ORION5X_CPU_H */ -- cgit v0.10.2 From 7054cfda6501d67b6796fb1b140655fe2b91aed5 Mon Sep 17 00:00:00 2001 From: Albert Aribaud <[albert.aribaud@free.fr]> Date: Thu, 16 Sep 2010 20:30:30 +0530 Subject: mvsata_ide: adjust port init sequence mvsata_ide_initialize_port(): adjust init sequence (SStatus should be checked only after all writes to SControl) and return success/failure to ide_preinit(). Also, as some tests showed init durations in the hundreds of us, raise the time-out to 01 ms to be on the safe side. Signed-off-by: Albert Aribaud diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index 077b278..3d6993a 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -91,29 +91,48 @@ struct mvsata_port_registers { #define MVSATA_SSTATUS_DET_DEVCOMM 0x00000003 /* + * Status codes to return to client callers. Currently, callers ignore + * exact value and only care for zero or nonzero, so no need to make this + * public, it is only #define'd for clarity. + * If/when standard negative codes are implemented in U-boot, then these + * #defines should be moved to, or replaced by ones from, the common list + * of status codes. + */ + +#define MVSATA_STATUS_OK 0 +#define MVSATA_STATUS_TIMEOUT -1 + +/* * Initialize one MVSATAHC port: set SControl's IPM to "always active" * and DET to "reset", then wait for SStatus's DET to become "device and * comm ok" (or time out after 50 us if no device), then set SControl's * DET back to "no action". */ -static void mvsata_ide_initialize_port(struct mvsata_port_registers *port) +static int mvsata_ide_initialize_port(struct mvsata_port_registers *port) { u32 control; u32 status; - u32 tout = 50; /* wait at most 50 us for SATA reset to complete */ + u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */ + /* Set control IPM to 3 (no low power) and DET to 1 (initialize) */ control = readl(&port->scontrol); control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT; writel(control, &port->scontrol); - while (--tout) { + /* Toggle control DET back to 0 (normal operation) */ + control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE; + writel(control, &port->scontrol); + /* wait for status DET to become 3 (device and communication OK) */ + while (--timeleft) { status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK; if (status == MVSATA_SSTATUS_DET_DEVCOMM) break; udelay(1); } - control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE; - writel(control, &port->scontrol); + /* return success or time-out error depending on time left */ + if (!timeleft) + return MVSATA_STATUS_TIMEOUT; + return MVSATA_STATUS_OK; } /* @@ -123,18 +142,23 @@ static void mvsata_ide_initialize_port(struct mvsata_port_registers *port) int ide_preinit(void) { + int status; /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE0_OFFSET) - mvsata_ide_initialize_port( + status = mvsata_ide_initialize_port( (struct mvsata_port_registers *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET)); + if (status) + return status; #endif /* Enable ATA port 1 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE1_OFFSET) - mvsata_ide_initialize_port( + status = mvsata_ide_initialize_port( (struct mvsata_port_registers *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET)); + if (status) + return status; #endif - /* return 0 as we always succeed */ - return 0; + /* return success if all ports initializations succeeded */ + return MVSATA_STATUS_OK; } -- cgit v0.10.2 From 35883cca8a7f3e2ef0bcbe14d52ef9e9b2b1ab81 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar <[prafulla@marvell.com]> Date: Mon, 20 Sep 2010 17:19:42 +0530 Subject: Kirkwood: print_cpuinfo fixed for valid devid revid Earlier Device Identification register was used to detect the type for SoC, considering 88F6282 support to be added, It is not possible to detect the same using current algorithm. With this patch, device ID is being read using PCIE devid register, also valid chip revision ID will also be read and displayed Signed-off-by: Prafulla Wadaskar diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index 82c978b..b4a4c04 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -54,10 +54,11 @@ unsigned char get_random_hex(void) u8 outbuf[BUFLEN]; /* - * in case of 88F6281/88F6192 A0, + * in case of 88F6281/88F6282/88F6192 A0, * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470 - * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are reserved regs and - * Does not have names at this moment (no errata available) + * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are + * reserved regs and does not have names at this moment + * (no errata available) */ writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478); for (i = 0; i < BUFLEN; i++) { @@ -271,20 +272,31 @@ static void kw_sysrst_check(void) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - char *name = "Unknown"; + char *rev; + u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff; + u8 revid = readl(KW_REG_PCIE_REVID) & 0xff; - switch (readl(KW_REG_DEVICE_ID) & 0x03) { - case 1: - name = "88F6192_A0"; + if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) { + printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid); + return -1; + } + + switch (revid) { + case 0: + rev = "Z0"; break; case 2: - name = "88F6281_A0"; + rev = "A0"; + break; + case 3: + rev = "A1"; break; default: - printf("SoC: Unsupported Kirkwood\n"); - return -1; + rev = "??"; + break; } - printf("SoC: Kirkwood %s\n", name); + + printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h index b3022a3..d28c51a 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/include/asm/arch-kirkwood/cpu.h @@ -35,6 +35,8 @@ #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \ ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c) +#define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00) +#define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08) #define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34) #define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50) #define SYSRST_CNT_1SEC_VAL (25*1000000) -- cgit v0.10.2 From 3b467ec4442b0d26e1f037a51cc2cbf75f37e932 Mon Sep 17 00:00:00 2001 From: Albert Aribaud <[albert.aribaud@free.fr]> Date: Thu, 7 Oct 2010 20:19:53 +0530 Subject: orion5x: optimize window size computation Signed-off-by: Chris Moore Signed-off-by: Albert Aribaud diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index c36d7bf..1894b52 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -48,24 +48,34 @@ void reset_cpu(unsigned long ignored) } /* - * Window Size + * Compute Window Size field value from size expressed in bytes * Used with the Base register to set the address window size and location. * Must be programmed from LSB to MSB as sequence of ones followed by * sequence of zeros. The number of ones specifies the size of the window in - * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte). - * NOTE: A value of 0x0 specifies 64-KByte size. + * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB). + * NOTES: + * 1) A sizeval equal to 0x0 specifies 4 GiB. + * 2) A return value of 0x0 specifies 64 KiB. */ unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) { - int i; - unsigned int j = 0; - u32 val = sizeval >> 1; + /* + * Calculate the number of 64 KiB blocks needed minus one (rounding up). + * For sizeval > 0 this is equivalent to: + * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1 + */ + sizeval = (sizeval - 1) >> 16; - for (i = 0; val >= 0x10000; i++) { - j |= (1 << i); - val = val >> 1; - } - return 0x0000ffff & j; + /* + * Propagate 'one' bits to the right by 'oring' them. + * We need only treat bits 15-0. + */ + sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */ + sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */ + sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */ + sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/ + + return sizeval; } /* -- cgit v0.10.2 From 6edf0f121f7c681ef32bf02c2c71feb8fd8e304d Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Thu, 30 Sep 2010 19:33:19 +0530 Subject: Kirkwood: dram_init is moved to dram.c For all Kirkwood boards so far dram_init function is duplicated dram_init function is moved to dram.c and relevant code from all board specific files removed If any board needs specific dram init handling than standard one, then, a macro CONFIG_SYS_BOARD_DRAM_INIT should be defined in board config header file and the dram_init function can be put in board specific source file For ex. keymile boards Signed-off-by: Prafulla Wadaskar diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c index 8f2a18a..7439c87 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c @@ -23,8 +23,11 @@ */ #include +#include #include +DECLARE_GLOBAL_DATA_PTR; + #define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08)) #define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08)) /* @@ -56,3 +59,38 @@ u32 kw_sdram_bs(enum memory_bank bank) result += 0x01000000; return result; } + +#ifndef CONFIG_SYS_BOARD_DRAM_INIT +int dram_init(void) +{ + int i; + + gd->ram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = kw_sdram_bar(i); + gd->bd->bi_dram[i].size = kw_sdram_bs(i); + /* + * It is assumed that all memory banks are consecutive + * and without gaps. + * If the gap is found, ram_size will be reported for + * consecutive memory only + */ + if (gd->bd->bi_dram[i].start != gd->ram_size) + break; + + gd->ram_size += gd->bd->bi_dram[i].size; + + } + return 0; +} + +/* + * If this function is not defined here, + * board.c alters dram bank zero configuration defined above. + */ +void dram_init_banksize(void) +{ + dram_init(); +} +#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ + diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index c028a53..4df4e9b 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -108,17 +108,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_RESET_PHY_R void mv_phy_88e1121_init(char *name) { diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index c959bf8..93d1400 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -110,17 +110,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_MV88E61XX_SWITCH void reset_phy(void) { diff --git a/board/Marvell/openrd_base/openrd_base.c b/board/Marvell/openrd_base/openrd_base.c index c00a08a..d006b2d 100644 --- a/board/Marvell/openrd_base/openrd_base.c +++ b/board/Marvell/openrd_base/openrd_base.c @@ -113,17 +113,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_RESET_PHY_R /* Configure and enable MV88E1116 PHY */ void reset_phy(void) diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index 8713a3c..0d76146 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -109,17 +109,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - void mv_phy_88e1116_init(char *name) { u16 reg; diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 547126a..173a7b8 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -108,17 +108,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_RESET_PHY_R /* Configure and enable MV88E1116 PHY */ void reset_phy(void) diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index 6c14ca0..62d21f6 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -85,6 +85,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_SYS_BOARD_DRAM_INIT /* Used board specific dram_init */ /* * How to get access to the slot ID. Put this here to make it easy -- cgit v0.10.2 From 44f1ec6c5e9c4ed833abe7ce4c266e4e6266493c Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Thu, 30 Sep 2010 22:53:43 +0530 Subject: kirkwood: added common config file mv-common.h It is observed that, in most of the board configs the code is being duplicated, also for any common change all board files needs update This issue was under discussion from long on mailing list and we converge on introducing common config file. With this patch- 1. Total Kirkwood specific configuration code is reduced by 210 lines 2. All common configuration can be shared by multiple boards 3. Easy to manage common updates like ARM relocation changes mv-common.h file is added to include/configs/ It contains all common configuration supported for all Kirkwood boards The respective board configs are updated for its usage Build tested for guruplug, mv88f6281gtw_ge, openrd_base, rd6281a and sheevaplug Binary execution tested for sheevaplug Todo: 1. Other custom Kirkwood boards to be synced 2. The support to be extended for Orion5X based boards Signed-off-by: Prafulla Wadaskar diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index eb3fa57..2c2682c 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -33,59 +33,13 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_MARVELL 1 -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_GURUPLUG /* Machine type */ - -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - -/* - * CLKs configurations - */ -#define CONFIG_SYS_HZ 1000 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200,230400, 460800, 921600 } -/* auto boot */ -#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ /* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - -#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ -/* * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ @@ -96,18 +50,13 @@ #define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_USB +#define CONFIG_CMD_IDE /* - * NAND configuration + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ -#define NAND_ALLOW_ERASE_ALL 1 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ -#endif +#include "mv-common.h" /* * Environment variables configurations @@ -143,55 +92,19 @@ "x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - -/* - * Other required configurations - */ -#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ -#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ -#define CONFIG_NR_DRAM_BANKS 4 -#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff /*(_512M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - -/* * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* specify more that one ports available */ -#define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_CMD_MII -#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ #define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ #define CONFIG_PHY_BASE_ADR 0 -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv88e1121 PHY */ #endif /* CONFIG_CMD_NET */ /* - * USB/EHCI + * SATA Driver configuration */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_SUPPORT_VFAT -#endif /* CONFIG_CMD_USB */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ #define CONFIG_SYS_ALT_MEMTEST diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h new file mode 100644 index 0000000..e78d29f --- /dev/null +++ b/include/configs/mv-common.h @@ -0,0 +1,225 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * This file contains Marvell Board Specific common defincations. + * This file should be included in board config header file. + * + * It supports common definations for Kirkwood platform + * TBD: support for Orion5X platforms + */ + +#ifndef _MV_COMMON_H +#define _MV_COMMON_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ + +#if defined(CONFIG_KIRKWOOD) +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ +#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ + +#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE +#define MV_UART0_BASE KW_UART0_BASE +#define MV_SATA_BASE KW_SATA_BASE +#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET +#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET + +#else +#error "Unsupported SoC" +#endif + +/* + * CLKs configurations + */ +#define CONFIG_SYS_HZ 1000 + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 MV_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200,230400, 460800, 921600 } +/* auto boot */ +#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ + +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_KIRKWOOD +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ +#define NAND_ALLOW_ERASE_ALL 1 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +/* + * SPI Flash configuration + */ +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH 1 +#define CONFIG_HARD_SPI 1 +#define CONFIG_KIRKWOOD_SPI 1 +#define CONFIG_SPI_FLASH_MACRONIX 1 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */ +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required minimal configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ +#endif /* CONFIG_CMD_NET */ + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_KIRKWOOD +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +/* + * IDE Support on SATA ports + */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_CMD_EXT2 +#define CONFIG_MVSATA_IDE +#define CONFIG_IDE_PREINIT +#define CONFIG_MVSATA_IDE_USE_PORT1 +/* Needs byte-swapping for ATA data register */ +#define CONFIG_IDE_SWAP_IO +/* Data, registers and alternate blocks are at the same offset */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) +#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) +#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) +/* Each 8-bit ATA register is aligned to a 4-bytes address */ +#define CONFIG_SYS_ATA_STRIDE 4 +/* Controller supports 48-bits LBA addressing */ +#define CONFIG_LBA48 +/* CONFIG_CMD_IDE requires some #defines for ATA registers */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 2 +/* ATA registers base is at SATA controller base */ +#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE +#endif /* CONFIG_CMD_IDE */ + +/* + * I2C related stuff + */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_I2C_MVTWSI +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +#endif /* _MV_COMMON_H */ diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h index 9ef03a6..d323829 100644 --- a/include/configs/mv88f6281gtw_ge.h +++ b/include/configs/mv88f6281gtw_ge.h @@ -33,66 +33,19 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_MARVELL 1 -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */ - -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ /* - * CLKs configurations - */ -#define CONFIG_SYS_HZ 1000 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200,230400, 460800, 921600 } -/* auto boot */ -#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - -#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ -/* * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include -#define CONFIG_CMD_AUTOSCRIPT #define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING #define CONFIG_CMD_ENV #define CONFIG_CMD_FAT #define CONFIG_CMD_PING @@ -100,17 +53,18 @@ #define CONFIG_CMD_USB /* - * Flash configuration + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros */ -#ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH 1 -#define CONFIG_HARD_SPI 1 -#define CONFIG_KIRKWOOD_SPI 1 -#define CONFIG_SPI_FLASH_MACRONIX 1 -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */ -#endif +#include "mv-common.h" + +/* Unwanted stuffs from mv-common.h */ +#undef CONFIG_CMD_EXT2 +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_FAT +#undef CONFIG_CMD_UBI +#undef CONFIG_CMD_UBIFS +#undef CONFIG_RBTREE /* * Environment variables configurations @@ -142,59 +96,11 @@ "x_bootargs_root=root=/dev/mtdblock3 ro rootfstype=squashfs\0" /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - -/* - * Other required minimal configurations - */ -#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ -#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ -#define CONFIG_NR_DRAM_BANKS 4 -#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - -/* * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* specify more that one ports available */ -#define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#endif /* CONFIG_CMD_NET */ - -/* - * Marvell 88Exxxx Switch configurations - */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init phy/swtich */ #define CONFIG_MV88E61XX_SWITCH /* Enable mv88e61xx switch driver */ - -/* - * USB/EHCI - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_SUPPORT_VFAT -#endif /* CONFIG_CMD_USB */ +#endif /* CONFIG_CMD_NET */ #endif /* _CONFIG_MV88F6281GTW_GE_H */ diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h index 846dfcd..cfdd09c 100644 --- a/include/configs/openrd_base.h +++ b/include/configs/openrd_base.h @@ -38,59 +38,12 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_MARVELL 1 -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_OPENRD_BASE /* Machine type */ - -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ - -/* - * CLKs configurations - */ -#define CONFIG_SYS_HZ 1000 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200,230400, 460800, 921600 } -/* auto boot */ -#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ -#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ /* * Commands configuration */ @@ -106,15 +59,10 @@ #define CONFIG_CMD_IDE /* - * NAND configuration + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ -#define NAND_ALLOW_ERASE_ALL 1 -#endif +#include "mv-common.h" /* * Environment variables configurations @@ -154,97 +102,19 @@ "mtdparts="MTDPARTS_DEFAULT"\0" /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */ -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - -/* - * Other required minimal configurations - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_AUTO_COMPLETE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ -#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ -#define CONFIG_NR_DRAM_BANKS 4 -#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - -/* * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* specify more that one ports available */ -#define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0x8 -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ #endif /* CONFIG_CMD_NET */ /* - * USB/EHCI - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_SUPPORT_VFAT -#endif /* CONFIG_CMD_USB */ - -/* - * IDe Support on SATA port0 - */ -#ifdef CONFIG_CMD_IDE -#define __io -#define CONFIG_CMD_EXT2 -#define CONFIG_MVSATA_IDE -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT1 -/* Needs byte-swapping for ATA data register */ -#define CONFIG_IDE_SWAP_IO -/* Data, registers and alternate blocks are at the same offset */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) -#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) -#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) -/* Each 8-bit ATA register is aligned to a 4-bytes address */ -#define CONFIG_SYS_ATA_STRIDE 4 -/* Controller supports 48-bits LBA addressing */ -#define CONFIG_LBA48 -/* CONFIG_CMD_IDE requires some #defines for ATA registers */ -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_IDE_MAXDEVICE 2 -/* ATA registers base is at SATA controller base */ -#define CONFIG_SYS_ATA_BASE_ADDR KW_SATA_BASE -/* ATA bus 0 is Kirkwood port 0 on openrd */ -#define CONFIG_SYS_ATA_IDE0_OFFSET KW_SATA_PORT0_OFFSET -/* ATA bus 1 is Kirkwood port 1 on openrd */ -#define CONFIG_SYS_ATA_IDE1_OFFSET KW_SATA_PORT1_OFFSET -#endif /* CONFIG_CMD_IDE */ - -/* - * File system + * SATA Driver configuration */ -#define CONFIG_CMD_FAT -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#define CONFIG_RBTREE -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_MTD_PARTITIONS -#define CONFIG_CMD_MTDPARTS -#define CONFIG_LZO +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ #endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h index 5857301..60f9579 100644 --- a/include/configs/rd6281a.h +++ b/include/configs/rd6281a.h @@ -33,59 +33,13 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_MARVELL 1 -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_RD6281A /* Machine type */ - -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - -/* - * CLKs configurations - */ -#define CONFIG_SYS_HZ 1000 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200,230400, 460800, 921600 } -/* auto boot */ -#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ /* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - -#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ -/* * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ @@ -97,17 +51,13 @@ #define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_USB +#define CONFIG_CMD_IDE /* - * NAND configuration + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ -#define NAND_ALLOW_ERASE_ALL 1 -#endif +#include "mv-common.h" /* * Environment variables configurations @@ -143,56 +93,23 @@ "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - -/* - * Other required minimal configurations - */ -#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ -#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ -#define CONFIG_NR_DRAM_BANKS 4 -#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - -/* * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* specify more that one ports available */ -#define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ #define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ #define CONFIG_MV88E61XX_MULTICHIP_ADRMODE #define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */ #define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */ #define CONFIG_PHY_BASE_ADR 0x0A -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init switch and PHY */ #define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */ #endif /* CONFIG_CMD_NET */ /* - * USB/EHCI + * SATA Driver configuration */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_SUPPORT_VFAT -#endif /* CONFIG_CMD_USB */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ #endif /* _CONFIG_RD6281A_H */ diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index c5de86e..83dd8ff 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -33,82 +33,28 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_MARVELL 1 -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_SHEEVAPLUG /* Machine type */ - -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - -/* - * CLKs configurations - */ -#define CONFIG_SYS_HZ 1000 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200,230400, 460800, 921600 } -/* auto boot */ -#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - -#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ /* * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include -#define CONFIG_CMD_AUTOSCRIPT #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV #define CONFIG_CMD_MII #define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_USB - /* - * NAND configuration + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ -#define NAND_ALLOW_ERASE_ALL 1 -#endif +#include "mv-common.h" /* * Environment variables configurations @@ -144,58 +90,14 @@ "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1 MiB for malloc() */ -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - -/* - * Other required minimal configurations - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_AUTO_COMPLETE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ -#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ -#define CONFIG_NR_DRAM_BANKS 4 -#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - -/* * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* specify more that one ports available */ -#define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ #endif /* CONFIG_CMD_NET */ /* - * USB/EHCI - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_SUPPORT_VFAT -#endif /* CONFIG_CMD_USB */ - -/* * File system */ #define CONFIG_CMD_EXT2 -- cgit v0.10.2 From d30b5706d8502df4c00dfa9ebd054a19fed6d496 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Thu, 30 Sep 2010 22:57:02 +0530 Subject: Kirkwood: Changes specific to ARM relocation support All Kirkwood based boards are supported for this new implementation ref: docs/README.arm-relocation Signed-off-by: Prafulla Wadaskar diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index e78d29f..bdcebd3 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -55,6 +55,11 @@ #error "Unsupported SoC" #endif +/* additions for new ARM relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +/* Kirkwood has 2k of Security SRAM, use it for SP */ +#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 + /* * CLKs configurations */ -- cgit v0.10.2 From d3497138ff352841da3573c7aa9df993c4afd136 Mon Sep 17 00:00:00 2001 From: Albert Aribaud <[albert.aribaud@free.fr]> Date: Thu, 16 Sep 2010 20:30:30 +0530 Subject: mvsata_ide: adjust port init sequence mvsata_ide_initialize_port(): adjust init sequence (SStatus should be checked only after all writes to SControl) and return success/failure to ide_preinit(). Also, as some tests showed init durations in the hundreds of us, raise the time-out to 01 ms to be on the safe side. Signed-off-by: Albert Aribaud diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index 077b278..3d6993a 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -91,29 +91,48 @@ struct mvsata_port_registers { #define MVSATA_SSTATUS_DET_DEVCOMM 0x00000003 /* + * Status codes to return to client callers. Currently, callers ignore + * exact value and only care for zero or nonzero, so no need to make this + * public, it is only #define'd for clarity. + * If/when standard negative codes are implemented in U-boot, then these + * #defines should be moved to, or replaced by ones from, the common list + * of status codes. + */ + +#define MVSATA_STATUS_OK 0 +#define MVSATA_STATUS_TIMEOUT -1 + +/* * Initialize one MVSATAHC port: set SControl's IPM to "always active" * and DET to "reset", then wait for SStatus's DET to become "device and * comm ok" (or time out after 50 us if no device), then set SControl's * DET back to "no action". */ -static void mvsata_ide_initialize_port(struct mvsata_port_registers *port) +static int mvsata_ide_initialize_port(struct mvsata_port_registers *port) { u32 control; u32 status; - u32 tout = 50; /* wait at most 50 us for SATA reset to complete */ + u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */ + /* Set control IPM to 3 (no low power) and DET to 1 (initialize) */ control = readl(&port->scontrol); control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT; writel(control, &port->scontrol); - while (--tout) { + /* Toggle control DET back to 0 (normal operation) */ + control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE; + writel(control, &port->scontrol); + /* wait for status DET to become 3 (device and communication OK) */ + while (--timeleft) { status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK; if (status == MVSATA_SSTATUS_DET_DEVCOMM) break; udelay(1); } - control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE; - writel(control, &port->scontrol); + /* return success or time-out error depending on time left */ + if (!timeleft) + return MVSATA_STATUS_TIMEOUT; + return MVSATA_STATUS_OK; } /* @@ -123,18 +142,23 @@ static void mvsata_ide_initialize_port(struct mvsata_port_registers *port) int ide_preinit(void) { + int status; /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE0_OFFSET) - mvsata_ide_initialize_port( + status = mvsata_ide_initialize_port( (struct mvsata_port_registers *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET)); + if (status) + return status; #endif /* Enable ATA port 1 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE1_OFFSET) - mvsata_ide_initialize_port( + status = mvsata_ide_initialize_port( (struct mvsata_port_registers *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET)); + if (status) + return status; #endif - /* return 0 as we always succeed */ - return 0; + /* return success if all ports initializations succeeded */ + return MVSATA_STATUS_OK; } -- cgit v0.10.2 From c0cd02073da1ec0737d45b2e60aac53201209b30 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar <[prafulla@marvell.com]> Date: Mon, 20 Sep 2010 17:19:42 +0530 Subject: Kirkwood: print_cpuinfo fixed for valid devid revid Earlier Device Identification register was used to detect the type for SoC, considering 88F6282 support to be added, It is not possible to detect the same using current algorithm. With this patch, device ID is being read using PCIE devid register, also valid chip revision ID will also be read and displayed Signed-off-by: Prafulla Wadaskar diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index 82c978b..b4a4c04 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -54,10 +54,11 @@ unsigned char get_random_hex(void) u8 outbuf[BUFLEN]; /* - * in case of 88F6281/88F6192 A0, + * in case of 88F6281/88F6282/88F6192 A0, * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470 - * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are reserved regs and - * Does not have names at this moment (no errata available) + * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are + * reserved regs and does not have names at this moment + * (no errata available) */ writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478); for (i = 0; i < BUFLEN; i++) { @@ -271,20 +272,31 @@ static void kw_sysrst_check(void) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - char *name = "Unknown"; + char *rev; + u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff; + u8 revid = readl(KW_REG_PCIE_REVID) & 0xff; - switch (readl(KW_REG_DEVICE_ID) & 0x03) { - case 1: - name = "88F6192_A0"; + if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) { + printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid); + return -1; + } + + switch (revid) { + case 0: + rev = "Z0"; break; case 2: - name = "88F6281_A0"; + rev = "A0"; + break; + case 3: + rev = "A1"; break; default: - printf("SoC: Unsupported Kirkwood\n"); - return -1; + rev = "??"; + break; } - printf("SoC: Kirkwood %s\n", name); + + printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h index b3022a3..d28c51a 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/include/asm/arch-kirkwood/cpu.h @@ -35,6 +35,8 @@ #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \ ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c) +#define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00) +#define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08) #define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34) #define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50) #define SYSRST_CNT_1SEC_VAL (25*1000000) -- cgit v0.10.2 From 500f2ff52a812d6ffd50b81978375116815f7f5b Mon Sep 17 00:00:00 2001 From: Albert Aribaud <[albert.aribaud@free.fr]> Date: Thu, 7 Oct 2010 20:19:53 +0530 Subject: orion5x: optimize window size computation Signed-off-by: Chris Moore Signed-off-by: Albert Aribaud diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index c36d7bf..1894b52 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -48,24 +48,34 @@ void reset_cpu(unsigned long ignored) } /* - * Window Size + * Compute Window Size field value from size expressed in bytes * Used with the Base register to set the address window size and location. * Must be programmed from LSB to MSB as sequence of ones followed by * sequence of zeros. The number of ones specifies the size of the window in - * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte). - * NOTE: A value of 0x0 specifies 64-KByte size. + * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB). + * NOTES: + * 1) A sizeval equal to 0x0 specifies 4 GiB. + * 2) A return value of 0x0 specifies 64 KiB. */ unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) { - int i; - unsigned int j = 0; - u32 val = sizeval >> 1; + /* + * Calculate the number of 64 KiB blocks needed minus one (rounding up). + * For sizeval > 0 this is equivalent to: + * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1 + */ + sizeval = (sizeval - 1) >> 16; - for (i = 0; val >= 0x10000; i++) { - j |= (1 << i); - val = val >> 1; - } - return 0x0000ffff & j; + /* + * Propagate 'one' bits to the right by 'oring' them. + * We need only treat bits 15-0. + */ + sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */ + sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */ + sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */ + sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/ + + return sizeval; } /* -- cgit v0.10.2 From beeb2589761d218076b2b5ed5699a08216ca8cf9 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Thu, 30 Sep 2010 19:33:19 +0530 Subject: Kirkwood: dram_init is moved to dram.c For all Kirkwood boards so far dram_init function is duplicated dram_init function is moved to dram.c and relevant code from all board specific files removed If any board needs specific dram init handling than standard one, then, a macro CONFIG_SYS_BOARD_DRAM_INIT should be defined in board config header file and the dram_init function can be put in board specific source file For ex. keymile boards Signed-off-by: Prafulla Wadaskar diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c index 8f2a18a..7439c87 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c @@ -23,8 +23,11 @@ */ #include +#include #include +DECLARE_GLOBAL_DATA_PTR; + #define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08)) #define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08)) /* @@ -56,3 +59,38 @@ u32 kw_sdram_bs(enum memory_bank bank) result += 0x01000000; return result; } + +#ifndef CONFIG_SYS_BOARD_DRAM_INIT +int dram_init(void) +{ + int i; + + gd->ram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = kw_sdram_bar(i); + gd->bd->bi_dram[i].size = kw_sdram_bs(i); + /* + * It is assumed that all memory banks are consecutive + * and without gaps. + * If the gap is found, ram_size will be reported for + * consecutive memory only + */ + if (gd->bd->bi_dram[i].start != gd->ram_size) + break; + + gd->ram_size += gd->bd->bi_dram[i].size; + + } + return 0; +} + +/* + * If this function is not defined here, + * board.c alters dram bank zero configuration defined above. + */ +void dram_init_banksize(void) +{ + dram_init(); +} +#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ + diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index c028a53..4df4e9b 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -108,17 +108,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_RESET_PHY_R void mv_phy_88e1121_init(char *name) { diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index c959bf8..93d1400 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -110,17 +110,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_MV88E61XX_SWITCH void reset_phy(void) { diff --git a/board/Marvell/openrd_base/openrd_base.c b/board/Marvell/openrd_base/openrd_base.c index c00a08a..d006b2d 100644 --- a/board/Marvell/openrd_base/openrd_base.c +++ b/board/Marvell/openrd_base/openrd_base.c @@ -113,17 +113,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_RESET_PHY_R /* Configure and enable MV88E1116 PHY */ void reset_phy(void) diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index 8713a3c..0d76146 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -109,17 +109,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - void mv_phy_88e1116_init(char *name) { u16 reg; diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 547126a..173a7b8 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -108,17 +108,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_RESET_PHY_R /* Configure and enable MV88E1116 PHY */ void reset_phy(void) diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index 6c14ca0..62d21f6 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -85,6 +85,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_SYS_BOARD_DRAM_INIT /* Used board specific dram_init */ /* * How to get access to the slot ID. Put this here to make it easy -- cgit v0.10.2 From 54e999a30af2ce4fab27b01a90676de3f1db1f49 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Thu, 30 Sep 2010 22:53:43 +0530 Subject: kirkwood: added common config file mv-common.h It is observed that, in most of the board configs the code is being duplicated, also for any common change all board files needs update This issue was under discussion from long on mailing list and we converge on introducing common config file. With this patch- 1. Total Kirkwood specific configuration code is reduced by 210 lines 2. All common configuration can be shared by multiple boards 3. Easy to manage common updates like ARM relocation changes mv-common.h file is added to include/configs/ It contains all common configuration supported for all Kirkwood boards The respective board configs are updated for its usage Build tested for guruplug, mv88f6281gtw_ge, openrd_base, rd6281a and sheevaplug Binary execution tested for sheevaplug Todo: 1. Other custom Kirkwood boards to be synced 2. The support to be extended for Orion5X based boards Signed-off-by: Prafulla Wadaskar diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index eb3fa57..2c2682c 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -33,59 +33,13 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_MARVELL 1 -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_GURUPLUG /* Machine type */ - -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - -/* - * CLKs configurations - */ -#define CONFIG_SYS_HZ 1000 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200,230400, 460800, 921600 } -/* auto boot */ -#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ /* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - -#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ -/* * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ @@ -96,18 +50,13 @@ #define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_USB +#define CONFIG_CMD_IDE /* - * NAND configuration + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ -#define NAND_ALLOW_ERASE_ALL 1 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ -#endif +#include "mv-common.h" /* * Environment variables configurations @@ -143,55 +92,19 @@ "x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - -/* - * Other required configurations - */ -#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ -#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ -#define CONFIG_NR_DRAM_BANKS 4 -#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff /*(_512M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - -/* * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* specify more that one ports available */ -#define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_CMD_MII -#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ #define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ #define CONFIG_PHY_BASE_ADR 0 -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv88e1121 PHY */ #endif /* CONFIG_CMD_NET */ /* - * USB/EHCI + * SATA Driver configuration */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_SUPPORT_VFAT -#endif /* CONFIG_CMD_USB */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ #define CONFIG_SYS_ALT_MEMTEST diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h new file mode 100644 index 0000000..e78d29f --- /dev/null +++ b/include/configs/mv-common.h @@ -0,0 +1,225 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * This file contains Marvell Board Specific common defincations. + * This file should be included in board config header file. + * + * It supports common definations for Kirkwood platform + * TBD: support for Orion5X platforms + */ + +#ifndef _MV_COMMON_H +#define _MV_COMMON_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ + +#if defined(CONFIG_KIRKWOOD) +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ +#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ + +#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE +#define MV_UART0_BASE KW_UART0_BASE +#define MV_SATA_BASE KW_SATA_BASE +#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET +#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET + +#else +#error "Unsupported SoC" +#endif + +/* + * CLKs configurations + */ +#define CONFIG_SYS_HZ 1000 + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 MV_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200,230400, 460800, 921600 } +/* auto boot */ +#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ + +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_KIRKWOOD +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ +#define NAND_ALLOW_ERASE_ALL 1 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +/* + * SPI Flash configuration + */ +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH 1 +#define CONFIG_HARD_SPI 1 +#define CONFIG_KIRKWOOD_SPI 1 +#define CONFIG_SPI_FLASH_MACRONIX 1 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */ +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required minimal configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ +#endif /* CONFIG_CMD_NET */ + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_KIRKWOOD +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +/* + * IDE Support on SATA ports + */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_CMD_EXT2 +#define CONFIG_MVSATA_IDE +#define CONFIG_IDE_PREINIT +#define CONFIG_MVSATA_IDE_USE_PORT1 +/* Needs byte-swapping for ATA data register */ +#define CONFIG_IDE_SWAP_IO +/* Data, registers and alternate blocks are at the same offset */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) +#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) +#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) +/* Each 8-bit ATA register is aligned to a 4-bytes address */ +#define CONFIG_SYS_ATA_STRIDE 4 +/* Controller supports 48-bits LBA addressing */ +#define CONFIG_LBA48 +/* CONFIG_CMD_IDE requires some #defines for ATA registers */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 2 +/* ATA registers base is at SATA controller base */ +#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE +#endif /* CONFIG_CMD_IDE */ + +/* + * I2C related stuff + */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_I2C_MVTWSI +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +#endif /* _MV_COMMON_H */ diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h index 9ef03a6..d323829 100644 --- a/include/configs/mv88f6281gtw_ge.h +++ b/include/configs/mv88f6281gtw_ge.h @@ -33,66 +33,19 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_MARVELL 1 -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */ - -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ /* - * CLKs configurations - */ -#define CONFIG_SYS_HZ 1000 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200,230400, 460800, 921600 } -/* auto boot */ -#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - -#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ -/* * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include -#define CONFIG_CMD_AUTOSCRIPT #define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING #define CONFIG_CMD_ENV #define CONFIG_CMD_FAT #define CONFIG_CMD_PING @@ -100,17 +53,18 @@ #define CONFIG_CMD_USB /* - * Flash configuration + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros */ -#ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH 1 -#define CONFIG_HARD_SPI 1 -#define CONFIG_KIRKWOOD_SPI 1 -#define CONFIG_SPI_FLASH_MACRONIX 1 -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */ -#endif +#include "mv-common.h" + +/* Unwanted stuffs from mv-common.h */ +#undef CONFIG_CMD_EXT2 +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_FAT +#undef CONFIG_CMD_UBI +#undef CONFIG_CMD_UBIFS +#undef CONFIG_RBTREE /* * Environment variables configurations @@ -142,59 +96,11 @@ "x_bootargs_root=root=/dev/mtdblock3 ro rootfstype=squashfs\0" /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - -/* - * Other required minimal configurations - */ -#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ -#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ -#define CONFIG_NR_DRAM_BANKS 4 -#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - -/* * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* specify more that one ports available */ -#define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#endif /* CONFIG_CMD_NET */ - -/* - * Marvell 88Exxxx Switch configurations - */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init phy/swtich */ #define CONFIG_MV88E61XX_SWITCH /* Enable mv88e61xx switch driver */ - -/* - * USB/EHCI - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_SUPPORT_VFAT -#endif /* CONFIG_CMD_USB */ +#endif /* CONFIG_CMD_NET */ #endif /* _CONFIG_MV88F6281GTW_GE_H */ diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h index 846dfcd..cfdd09c 100644 --- a/include/configs/openrd_base.h +++ b/include/configs/openrd_base.h @@ -38,59 +38,12 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_MARVELL 1 -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_OPENRD_BASE /* Machine type */ - -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ - -/* - * CLKs configurations - */ -#define CONFIG_SYS_HZ 1000 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200,230400, 460800, 921600 } -/* auto boot */ -#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ -#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ /* * Commands configuration */ @@ -106,15 +59,10 @@ #define CONFIG_CMD_IDE /* - * NAND configuration + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ -#define NAND_ALLOW_ERASE_ALL 1 -#endif +#include "mv-common.h" /* * Environment variables configurations @@ -154,97 +102,19 @@ "mtdparts="MTDPARTS_DEFAULT"\0" /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */ -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - -/* - * Other required minimal configurations - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_AUTO_COMPLETE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ -#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ -#define CONFIG_NR_DRAM_BANKS 4 -#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - -/* * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* specify more that one ports available */ -#define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0x8 -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ #endif /* CONFIG_CMD_NET */ /* - * USB/EHCI - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_SUPPORT_VFAT -#endif /* CONFIG_CMD_USB */ - -/* - * IDe Support on SATA port0 - */ -#ifdef CONFIG_CMD_IDE -#define __io -#define CONFIG_CMD_EXT2 -#define CONFIG_MVSATA_IDE -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT1 -/* Needs byte-swapping for ATA data register */ -#define CONFIG_IDE_SWAP_IO -/* Data, registers and alternate blocks are at the same offset */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) -#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) -#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) -/* Each 8-bit ATA register is aligned to a 4-bytes address */ -#define CONFIG_SYS_ATA_STRIDE 4 -/* Controller supports 48-bits LBA addressing */ -#define CONFIG_LBA48 -/* CONFIG_CMD_IDE requires some #defines for ATA registers */ -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_IDE_MAXDEVICE 2 -/* ATA registers base is at SATA controller base */ -#define CONFIG_SYS_ATA_BASE_ADDR KW_SATA_BASE -/* ATA bus 0 is Kirkwood port 0 on openrd */ -#define CONFIG_SYS_ATA_IDE0_OFFSET KW_SATA_PORT0_OFFSET -/* ATA bus 1 is Kirkwood port 1 on openrd */ -#define CONFIG_SYS_ATA_IDE1_OFFSET KW_SATA_PORT1_OFFSET -#endif /* CONFIG_CMD_IDE */ - -/* - * File system + * SATA Driver configuration */ -#define CONFIG_CMD_FAT -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#define CONFIG_RBTREE -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_MTD_PARTITIONS -#define CONFIG_CMD_MTDPARTS -#define CONFIG_LZO +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ #endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h index 5857301..60f9579 100644 --- a/include/configs/rd6281a.h +++ b/include/configs/rd6281a.h @@ -33,59 +33,13 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_MARVELL 1 -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_RD6281A /* Machine type */ - -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - -/* - * CLKs configurations - */ -#define CONFIG_SYS_HZ 1000 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200,230400, 460800, 921600 } -/* auto boot */ -#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ /* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - -#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ -/* * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ @@ -97,17 +51,13 @@ #define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_USB +#define CONFIG_CMD_IDE /* - * NAND configuration + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ -#define NAND_ALLOW_ERASE_ALL 1 -#endif +#include "mv-common.h" /* * Environment variables configurations @@ -143,56 +93,23 @@ "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - -/* - * Other required minimal configurations - */ -#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ -#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ -#define CONFIG_NR_DRAM_BANKS 4 -#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - -/* * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* specify more that one ports available */ -#define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ #define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ #define CONFIG_MV88E61XX_MULTICHIP_ADRMODE #define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */ #define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */ #define CONFIG_PHY_BASE_ADR 0x0A -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init switch and PHY */ #define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */ #endif /* CONFIG_CMD_NET */ /* - * USB/EHCI + * SATA Driver configuration */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_SUPPORT_VFAT -#endif /* CONFIG_CMD_USB */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ #endif /* _CONFIG_RD6281A_H */ diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index c5de86e..83dd8ff 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -33,82 +33,28 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_MARVELL 1 -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_SHEEVAPLUG /* Machine type */ - -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - -/* - * CLKs configurations - */ -#define CONFIG_SYS_HZ 1000 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200,230400, 460800, 921600 } -/* auto boot */ -#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - -#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ /* * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include -#define CONFIG_CMD_AUTOSCRIPT #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV #define CONFIG_CMD_MII #define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_USB - /* - * NAND configuration + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ -#define NAND_ALLOW_ERASE_ALL 1 -#endif +#include "mv-common.h" /* * Environment variables configurations @@ -144,58 +90,14 @@ "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1 MiB for malloc() */ -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - -/* - * Other required minimal configurations - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_AUTO_COMPLETE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ -#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ -#define CONFIG_NR_DRAM_BANKS 4 -#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - -/* * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* specify more that one ports available */ -#define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ #endif /* CONFIG_CMD_NET */ /* - * USB/EHCI - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_SUPPORT_VFAT -#endif /* CONFIG_CMD_USB */ - -/* * File system */ #define CONFIG_CMD_EXT2 -- cgit v0.10.2 From 0b20ed76c07e8607436d649db768502dcd94dc9b Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Thu, 30 Sep 2010 22:57:02 +0530 Subject: Kirkwood: Changes specific to ARM relocation support All Kirkwood based boards are supported for this new implementation ref: docs/README.arm-relocation Signed-off-by: Prafulla Wadaskar diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index e78d29f..bdcebd3 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -55,6 +55,11 @@ #error "Unsupported SoC" #endif +/* additions for new ARM relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +/* Kirkwood has 2k of Security SRAM, use it for SP */ +#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 + /* * CLKs configurations */ -- cgit v0.10.2 From a784c01adcefe3efd4e651c5230e6117a7be35f8 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 22 Sep 2010 14:06:33 +0200 Subject: ARM: relocation: fix typo in comment Signed-off-by: Heiko Schocher diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 812e5f2..905a292 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -235,7 +235,7 @@ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ -/* additions for new relocation code, must added to all boards */ +/* additions for new relocation code, must be added to all boards */ #undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 8673e6f..faa0f50 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -180,7 +180,7 @@ int get_scl (void); #undef CONFIG_JFFS2_CMDLINE #endif -/* additions for new relocation code, must added to all boards */ +/* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_INIT_SP_ADDR (0x00000000 + 0x1000 - /* Fix this */ \ CONFIG_SYS_GBL_DATA_SIZE) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 2463be4..21078cf 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -340,7 +340,7 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif -/* additions for new relocation code, must added to all boards */ +/* additions for new relocation code, must be added to all boards */ #undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE) diff --git a/include/configs/qong.h b/include/configs/qong.h index cbb53dd..62ba7e0 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -282,7 +282,7 @@ extern int qong_nand_rdy(void *chip); "mtdparts=physmap-flash.0:384k(U-Boot),128k(env1)," \ "128k(env2),2432k(kernel),13m(ramdisk),-(user)" -/* additions for new relocation code, must added to all boards */ +/* additions for new relocation code, must be added to all boards */ #undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR diff --git a/include/configs/tx25.h b/include/configs/tx25.h index c798570..7faa453 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -176,7 +176,7 @@ "update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0" \ "upd=run load update\0" \ -/* additions for new relocation code, must added to all boards */ +/* additions for new relocation code, must be added to all boards */ #undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ -- cgit v0.10.2 From 11080ab66dc2c7f36e03f2cf7a8d86d94a58869f Mon Sep 17 00:00:00 2001 From: Ben Gardiner Date: Wed, 22 Sep 2010 17:32:49 -0400 Subject: ARM: relocation: don't undef CONFIG_SYS_ARM_WITHOUT_RELOC There were some #undef's of CONFIG_SYS_ARM_WITHOUT_RELOC added to a few board configs as part of the arm relocation series; but these are not needed now as we do not #undef what is not #defined in the first place. Signed-off-by: Ben Gardiner CC: Heiko Schocher diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index d02b196..e0a3bae 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -138,7 +138,6 @@ #endif /* additions for new relocation code, must added to all boards */ -#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ CONFIG_SYS_GBL_DATA_SIZE) diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 905a292..88e8d3d 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -236,7 +236,6 @@ "mtdparts=" MTDPARTS_DEFAULT "\0" \ /* additions for new relocation code, must be added to all boards */ -#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ CONFIG_SYS_GBL_DATA_SIZE) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 21078cf..1bd0f37 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -341,7 +341,6 @@ extern unsigned int boot_flash_type; #endif /* additions for new relocation code, must be added to all boards */ -#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE) diff --git a/include/configs/qong.h b/include/configs/qong.h index 62ba7e0..7f284ef 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -283,7 +283,6 @@ extern int qong_nand_rdy(void *chip); "128k(env2),2432k(kernel),13m(ramdisk),-(user)" /* additions for new relocation code, must be added to all boards */ -#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_END IRAM_SIZE diff --git a/include/configs/tx25.h b/include/configs/tx25.h index 7faa453..bcc8140 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -177,7 +177,6 @@ "upd=run load update\0" \ /* additions for new relocation code, must be added to all boards */ -#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ CONFIG_SYS_GBL_DATA_SIZE) -- cgit v0.10.2 From a4a87d8a933f648381d0cb9a913058cc2afa3cd4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Fri, 24 Sep 2010 23:31:43 +0200 Subject: arch/arm/include/asm/sizes.h: cleanups MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Merge several sizes.h in asm/arch subdirectories into a single asm/sizes.h file. Fixup usage of asm/arch/sizes.h in some files to use the merged file. Signed-off-by: Andreas Bießmann diff --git a/arch/arm/include/asm/arch-arm925t/sizes.h b/arch/arm/include/asm/arch-arm925t/sizes.h deleted file mode 100644 index 7319bd9..0000000 --- a/arch/arm/include/asm/arch-arm925t/sizes.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ diff --git a/arch/arm/include/asm/arch-arm926ejs/sizes.h b/arch/arm/include/asm/arch-arm926ejs/sizes.h deleted file mode 100644 index ef0b99b..0000000 --- a/arch/arm/include/asm/arch-arm926ejs/sizes.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307 - * USA - */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ diff --git a/arch/arm/include/asm/arch-omap/sizes.h b/arch/arm/include/asm/arch-omap/sizes.h deleted file mode 100644 index f8d92ca..0000000 --- a/arch/arm/include/asm/arch-omap/sizes.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif - -/* END */ diff --git a/arch/arm/include/asm/arch-omap24xx/omap2420.h b/arch/arm/include/asm/arch-omap24xx/omap2420.h index 0c11bec..6032419 100644 --- a/arch/arm/include/asm/arch-omap24xx/omap2420.h +++ b/arch/arm/include/asm/arch-omap24xx/omap2420.h @@ -25,7 +25,7 @@ #ifndef _OMAP2420_SYS_H_ #define _OMAP2420_SYS_H_ -#include +#include /* * 2420 specific Section diff --git a/arch/arm/include/asm/arch-omap24xx/sizes.h b/arch/arm/include/asm/arch-omap24xx/sizes.h deleted file mode 100644 index aaba18f..0000000 --- a/arch/arm/include/asm/arch-omap24xx/sizes.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_31M 0x01F00000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h index f8d92ca..b0b4f6a 100644 --- a/arch/arm/include/asm/sizes.h +++ b/arch/arm/include/asm/sizes.h @@ -13,9 +13,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ /* Size defintions * Copyright (C) ARM Limited 1998. All rights reserved. */ @@ -28,6 +25,7 @@ #define SZ_4K 0x00001000 #define SZ_8K 0x00002000 #define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 #define SZ_64K 0x00010000 #define SZ_128K 0x00020000 #define SZ_256K 0x00040000 @@ -38,6 +36,7 @@ #define SZ_4M 0x00400000 #define SZ_8M 0x00800000 #define SZ_16M 0x01000000 +#define SZ_31M 0x01F00000 #define SZ_32M 0x02000000 #define SZ_64M 0x04000000 #define SZ_128M 0x08000000 diff --git a/include/configs/h2_p2_dbg_board.h b/include/configs/h2_p2_dbg_board.h index e0d823f..a4dea7d 100644 --- a/include/configs/h2_p2_dbg_board.h +++ b/include/configs/h2_p2_dbg_board.h @@ -31,7 +31,7 @@ #ifndef __INCLUDED_H2_P2_DBH_BOARD_H #define __INCLUDED_H2_P2_DBH_BOARD_H -#include +#include /* * The Debug board is designed to function with the P2 Sample, H2 diff --git a/include/configs/omap1510.h b/include/configs/omap1510.h index 931560c..e6d9c7a 100644 --- a/include/configs/omap1510.h +++ b/include/configs/omap1510.h @@ -28,7 +28,7 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include +#include /* There are 2 sets of general I/O --> diff --git a/include/configs/omap730.h b/include/configs/omap730.h index 04d5144..c7682a1 100644 --- a/include/configs/omap730.h +++ b/include/configs/omap730.h @@ -31,7 +31,7 @@ #ifndef __INCLUDED_OMAP730_H #define __INCLUDED_OMAP730_H -#include +#include /*************************************************************************** * OMAP730 Configuration Registers -- cgit v0.10.2 From b80e41ac54690e50dbcb0e9f19ebb1f3c8076983 Mon Sep 17 00:00:00 2001 From: Matt Waddel Date: Thu, 7 Oct 2010 15:48:45 -0600 Subject: ARMV7: Versatile Express Coretile CortexA9x4 support Adds support for the ARM quad-core Cortex-A9 processor This system includes a motherboard(Versatile Express), daughterboard (Coretile), and SOC(Cortex-A9 quad core). The serial port, ethernet, and flash systems work with these additions. The naming convention is: SOC -> CortexA9 quad core = ca9x4 daughterboard -> Coretile = ct motherboard -> Versatile Express = vxp This gives ca9x4_ct_vxp.c as the board support file. Signed-off-by: Matt Waddel diff --git a/MAINTAINERS b/MAINTAINERS index 785fccf..a394ac9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -800,6 +800,10 @@ Hugo Villeneuve SFFSDR ARM926EJS +Matt Waddel + + ca9x4_ct_vxp ARM ARMV7 (Quad Core) + Prafulla Wadaskar mv88f6281gtw_ge ARM926EJS (Kirkwood SoC) diff --git a/MAKEALL b/MAKEALL index 1b506d6..abceccd 100755 --- a/MAKEALL +++ b/MAKEALL @@ -489,6 +489,7 @@ LIST_ARM11=" \ ######################################################################### LIST_ARMV7=" \ am3517_evm \ + ca9x4_ct_vxp \ devkit8000 \ mx51evk \ omap3_beagle \ diff --git a/arch/arm/include/asm/arch-armv7/sysctrl.h b/arch/arm/include/asm/arch-armv7/sysctrl.h new file mode 100644 index 0000000..4e45167 --- /dev/null +++ b/arch/arm/include/asm/arch-armv7/sysctrl.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2010 Linaro + * Matt Waddel, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _SYSCTRL_H_ +#define _SYSCTRL_H_ + +/* System controller (SP810) register definitions */ +#define SP810_TIMER0_ENSEL (1 << 15) +#define SP810_TIMER1_ENSEL (1 << 17) +#define SP810_TIMER2_ENSEL (1 << 19) +#define SP810_TIMER3_ENSEL (1 << 21) + +struct sysctrl { + u32 scctrl; /* 0x000 */ + u32 scsysstat; + u32 scimctrl; + u32 scimstat; + u32 scxtalctrl; + u32 scpllctrl; + u32 scpllfctrl; + u32 scperctrl0; + u32 scperctrl1; + u32 scperen; + u32 scperdis; + u32 scperclken; + u32 scperstat; + u32 res1[0x006]; + u32 scflashctrl; /* 0x04c */ + u32 res2[0x3a4]; + u32 scsysid0; /* 0xee0 */ + u32 scsysid1; + u32 scsysid2; + u32 scsysid3; + u32 scitcr; + u32 scitir0; + u32 scitir1; + u32 scitor; + u32 sccntctrl; + u32 sccntdata; + u32 sccntstep; + u32 res3[0x32]; + u32 scperiphid0; /* 0xfe0 */ + u32 scperiphid1; + u32 scperiphid2; + u32 scperiphid3; + u32 scpcellid0; + u32 scpcellid1; + u32 scpcellid2; + u32 scpcellid3; +}; +#endif /* _SYSCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-armv7/systimer.h b/arch/arm/include/asm/arch-armv7/systimer.h new file mode 100644 index 0000000..e745e37 --- /dev/null +++ b/arch/arm/include/asm/arch-armv7/systimer.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2010 Linaro + * Matt Waddel, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _SYSTIMER_H_ +#define _SYSTIMER_H_ + +/* AMBA timer register base address */ +#define SYSTIMER_BASE 0x10011000 + +#define SYSHZ_CLOCK 1000000 /* Timers -> 1Mhz */ +#define SYSTIMER_RELOAD 0xFFFFFFFF +#define SYSTIMER_EN (1 << 7) +#define SYSTIMER_32BIT (1 << 1) + +struct systimer { + u32 timer0load; /* 0x00 */ + u32 timer0value; + u32 timer0control; + u32 timer0intclr; + u32 timer0ris; + u32 timer0mis; + u32 timer0bgload; + u32 timer1load; /* 0x20 */ + u32 timer1value; + u32 timer1control; + u32 timer1intclr; + u32 timer1ris; + u32 timer1mis; + u32 timer1bgload; +}; +#endif /* _SYSTIMER_H_ */ diff --git a/arch/arm/include/asm/arch-armv7/wdt.h b/arch/arm/include/asm/arch-armv7/wdt.h new file mode 100644 index 0000000..ee74c38 --- /dev/null +++ b/arch/arm/include/asm/arch-armv7/wdt.h @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2010 + * Matt Waddel, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _WDT_H_ +#define _WDT_H_ + +/* Watchdog timer (SP805) register base address */ +#define WDT_BASE 0x100E5000 + +#define WDT_EN 0x2 +#define WDT_RESET_LOAD 0x0 + +struct wdt { + u32 wdogload; /* 0x000 */ + u32 wdogvalue; + u32 wdogcontrol; + u32 wdogintclr; + u32 wdogris; + u32 wdogmis; + u32 res1[0x2F9]; + u32 wdoglock; /* 0xC00 */ + u32 res2[0xBE]; + u32 wdogitcr; /* 0xF00 */ + u32 wdogitop; + u32 res3[0x35]; + u32 wdogperiphid0; /* 0xFE0 */ + u32 wdogperiphid1; + u32 wdogperiphid2; + u32 wdogperiphid3; + u32 wdogpcellid0; + u32 wdogpcellid1; + u32 wdogpcellid2; + u32 wdogpcellid3; +}; + +#endif /* _WDT_H_ */ diff --git a/board/armltd/vexpress/Makefile b/board/armltd/vexpress/Makefile new file mode 100644 index 0000000..ee5c0d8 --- /dev/null +++ b/board/armltd/vexpress/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := ca9x4_ct_vxp.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c b/board/armltd/vexpress/ca9x4_ct_vxp.c new file mode 100644 index 0000000..48dfc8c --- /dev/null +++ b/board/armltd/vexpress/ca9x4_ct_vxp.c @@ -0,0 +1,220 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +static ulong timestamp; +static ulong lastdec; + +static struct wdt *wdt_base = (struct wdt *)WDT_BASE; +static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE; +static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE; + +static void flash__init(void); +static void vexpress_timer_init(void); +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress(int progress) +{ + printf("Boot reached stage %d\n", progress); +} +#endif + +static inline void delay(ulong loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0" (loops)); +} + +int board_init(void) +{ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS; + gd->flags = 0; + + icache_enable(); + flash__init(); + vexpress_timer_init(); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} + +static void flash__init(void) +{ + /* Setup the sytem control register to allow writing to flash */ + writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN, + &sysctrl_base->scflashctrl); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size(PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); +} + +int timer_init(void) +{ + return 0; +} + +/* + * Start timer: + * Setup a 32 bit timer, running at 1KHz + * Versatile Express Motherboard provides 1 MHz timer + */ +static void vexpress_timer_init(void) +{ + /* + * Set clock frequency in system controller: + * VEXPRESS_REFCLK is 32KHz + * VEXPRESS_TIMCLK is 1MHz + */ + writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL | + SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL | + readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl); + + /* + * Set Timer0 to be: + * Enabled, free running, no interrupt, 32-bit, wrapping + */ + writel(SYSTIMER_RELOAD, &systimer_base->timer0load); + writel(SYSTIMER_RELOAD, &systimer_base->timer0value); + writel(SYSTIMER_EN | SYSTIMER_32BIT | \ + readl(&systimer_base->timer0control), \ + &systimer_base->timer0control); + + reset_timer_masked(); +} + +/* Use the ARM Watchdog System to cause reset */ +void reset_cpu(ulong addr) +{ + writeb(WDT_EN, &wdt_base->wdogcontrol); + writel(WDT_RESET_LOAD, &wdt_base->wdogload); + while (1) + ; +} + +/* + * Delay x useconds AND perserve advance timstamp value + * assumes timer is ticking at 1 msec + */ +void udelay(ulong usec) +{ + ulong tmo, tmp; + + tmo = usec / 1000; + tmp = get_timer(0); /* get current timestamp */ + + /* + * If setting this forward will roll time stamp then + * reset "advancing" timestamp to 0 and set lastdec value + * otherwise set the advancing stamp to the wake up time + */ + if ((tmo + tmp + 1) < tmp) + reset_timer_masked(); + else + tmo += tmp; + + while (get_timer_masked() < tmo) + ; /* loop till wakeup event */ +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void reset_timer_masked(void) +{ + lastdec = readl(&systimer_base->timer0value) / 1000; + timestamp = 0; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer_masked(void) +{ + ulong now = readl(&systimer_base->timer0value) / 1000; + + if (lastdec >= now) { /* normal mode (non roll) */ + timestamp += lastdec - now; + } else { /* count down timer overflowed */ + /* + * nts = ts + ld - now + * ts = old stamp, ld = time before passing through - 1 + * now = amount of time after passing though - 1 + * nts = new "advancing time stamp" + */ + timestamp += lastdec + SYSTIMER_RELOAD - now; + } + lastdec = now; + + return timestamp; +} + +void lowlevel_init(void) +{ +} + +ulong get_board_rev(void){ + return readl((u32 *)SYS_ID); +} diff --git a/board/armltd/vexpress/config.mk b/board/armltd/vexpress/config.mk new file mode 100644 index 0000000..2d797d7 --- /dev/null +++ b/board/armltd/vexpress/config.mk @@ -0,0 +1,23 @@ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Linux-Kernel is expected to be at 0x60008000 +# +TEXT_BASE = 0x60800000 +LDSCRIPT := $(SRCTREE)/board/armltd/vexpress/u-boot.lds diff --git a/board/armltd/vexpress/u-boot.lds b/board/armltd/vexpress/u-boot.lds new file mode 100644 index 0000000..5ac62f2 --- /dev/null +++ b/board/armltd/vexpress/u-boot.lds @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + arch/arm/cpu/armv7/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata))) } + + . = ALIGN(4); + .data : { *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + + __got_start = .; + . = ALIGN(4); + .got : { *(.got) } + __got_end = .; + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/boards.cfg b/boards.cfg index 62ffa42..38fa570 100644 --- a/boards.cfg +++ b/boards.cfg @@ -252,6 +252,7 @@ imx27lite arm arm926ejs imx27lite logicpd mx27 magnesium arm arm926ejs imx27lite logicpd mx27 omap5912osk arm arm926ejs - ti omap edminiv2 arm arm926ejs - LaCie orion5x +ca9x4_ct_vxp arm armv7 vexpress armltd omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 omap3_zoom1 arm armv7 zoom1 logicpd omap3 diff --git a/include/configs/ca9x4_ct_vxp.h b/include/configs/ca9x4_ct_vxp.h new file mode 100644 index 0000000..5547d55 --- /dev/null +++ b/include/configs/ca9x4_ct_vxp.h @@ -0,0 +1,196 @@ +/* + * (C) Copyright 2010 Linaro + * Matt Waddel, + * + * Configuration for Versatile Express. Parts were derived from other ARM + * configurations. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Board info register */ +#define SYS_ID 0x10000000 +#define CONFIG_REVISION_TAG 1 + +/* High Level Configuration Options */ +#define CONFIG_ARMV7 1 + +#define CONFIG_SYS_MEMTEST_START 0x60000000 +#define CONFIG_SYS_MEMTEST_END 0x20000000 +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_L2_OFF 1 +#define CONFIG_INITRD_TAG 1 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define SCTL_BASE 0x10001000 +#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) + +/* SMSC9115 Ethernet from SMSC9118 family */ +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_32_BIT 1 +#define CONFIG_SMC911X_BASE 0x4E000000 + +/* PL011 Serial Configuration */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} +#define CONFIG_CONS_INDEX 0 + +#define CONFIG_BAUDRATE 38400 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_SERIAL0 0x10009000 +#define CONFIG_SYS_SERIAL1 0x1000A000 + +/* Command line configuration */ +#define CONFIG_CMD_BDI +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV +#define CONFIG_NET_MULTI +#define CONFIG_CMD_RUN + +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_MMC 1 +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Miscellaneous configurable options */ +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_LOAD_ADDR 0x60008000 /* load address */ +#define LINUX_BOOT_PARAM_ADDR 0x60000200 +#define CONFIG_BOOTDELAY 2 + +/* Stack sizes are set up in start.S using the settings below */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ +#endif + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 0x60000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ +#define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */ + +/* additions for new relocation code */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_END 0x1000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET + +/* Basic environment settings */ +#define CONFIG_BOOTCOMMAND "run bootflash;" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80008000\0" \ + "initrd=0x61000000\0" \ + "kerneladdr=0x44100000\0" \ + "initrdaddr=0x44800000\0" \ + "maxinitrd=0x1800000\0" \ + "console=ttyAMA0,38400n8\0" \ + "dram=1024M\0" \ + "root=/dev/sda1 rw\0" \ + "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \ + "24M@0x2000000(initrd)\0" \ + "flashargs=setenv bootargs root=${root} console=${console} " \ + "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \ + "devtmpfs.mount=0 vmalloc=256M\0" \ + "bootflash=run flashargs; " \ + "cp ${initrdaddr} ${initrd} ${maxinitrd}; " \ + "bootm ${kerneladdr} ${initrd}\0" + +/* FLASH and environment organization */ +#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_SIZE 0x04000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_BASE0 0x40000000 +#define CONFIG_SYS_FLASH_BASE1 0x44000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0 + +/* Timeout values in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ + +/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ +#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ +#define FLASH_MAX_SECTOR_SIZE 0x00040000 /* 256 KB sectors */ + +/* Room required on the stack for the environment data */ +#define CONFIG_ENV_SIZE FLASH_MAX_SECTOR_SIZE + +/* + * Amount of flash used for environment: + * We don't know which end has the small erase blocks so we use the penultimate + * sector location for the environment + */ +#define CONFIG_ENV_SECT_SIZE FLASH_MAX_SECTOR_SIZE +#define CONFIG_ENV_OVERWRITE 1 + +/* Store environment at top of flash */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - \ + (2 * CONFIG_ENV_SECT_SIZE)) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE1 + \ + CONFIG_ENV_OFFSET) +#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \ + CONFIG_SYS_FLASH_BASE1 } + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "VExpress# " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ +#define CONFIG_CMD_SOURCE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_MAXARGS 16 /* max command args */ + +#endif -- cgit v0.10.2 From 249d5219c4cf0a6ec423deb6e0eb8a77b3a405fa Mon Sep 17 00:00:00 2001 From: Matt Waddel Date: Thu, 7 Oct 2010 15:48:46 -0600 Subject: ARMV7: Fixed baudrate setting in pl01x driver The pl01x serial driver was lacking the code to switch baudrates from the command line. Fixed by simply saving the new baudrate and calling serial_init() again. Also fixed CamelCase variables, I/O accessors and comment style. Signed-off-by: Matt Waddel diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index c645cef..c0ae947 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -29,25 +29,23 @@ #include #include - +#include #include "serial_pl01x.h" -#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) -#define IO_READ(addr) (*(volatile unsigned int *)(addr)) - /* * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1 * Versatile PB has four UARTs. */ #define CONSOLE_PORT CONFIG_CONS_INDEX -#define baudRate CONFIG_BAUDRATE static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; #define NUM_PORTS (sizeof(port)/sizeof(port[0])) static void pl01x_putc (int portnum, char c); static int pl01x_getc (int portnum); static int pl01x_tstc (int portnum); +unsigned int baudrate = CONFIG_BAUDRATE; +DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_PL010_SERIAL @@ -55,16 +53,11 @@ int serial_init (void) { unsigned int divisor; - /* - ** First, disable everything. - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0); + /* First, disable everything */ + writel(0x0, port[CONSOLE_PORT] + UART_PL010_CR); - /* - ** Set baud rate - ** - */ - switch (baudRate) { + /* Set baud rate */ + switch (baudrate) { case 9600: divisor = UART_PL010_BAUD_9600; break; @@ -89,20 +82,15 @@ int serial_init (void) divisor = UART_PL010_BAUD_38400; } - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM, - ((divisor & 0xf00) >> 8)); - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff)); + writel(((divisor & 0xf00) >> 8), port[CONSOLE_PORT] + UART_PL010_LCRM); + writel((divisor & 0xff), port[CONSOLE_PORT] + UART_PL010_LCRL); - /* - ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH, - (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN)); + /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ + writel((UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN), + port[CONSOLE_PORT] + UART_PL010_LCRH); - /* - ** Finally, enable the UART - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN)); + /* Finally, enable the UART */ + writel((UART_PL010_CR_UARTEN), port[CONSOLE_PORT] + UART_PL010_CR); return 0; } @@ -118,38 +106,31 @@ int serial_init (void) unsigned int remainder; unsigned int fraction; - /* - ** First, disable everything. - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0); + /* First, disable everything */ + writel(0x0, port[CONSOLE_PORT] + UART_PL011_CR); /* - ** Set baud rate - ** - ** IBRD = UART_CLK / (16 * BAUD_RATE) - ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) + * Set baud rate + * + * IBRD = UART_CLK / (16 * BAUD_RATE) + * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) */ - temp = 16 * baudRate; + temp = 16 * baudrate; divider = CONFIG_PL011_CLOCK / temp; remainder = CONFIG_PL011_CLOCK % temp; - temp = (8 * remainder) / baudRate; + temp = (8 * remainder) / baudrate; fraction = (temp >> 1) + (temp & 1); - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider); - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction); + writel(divider, port[CONSOLE_PORT] + UART_PL011_IBRD); + writel(fraction, port[CONSOLE_PORT] + UART_PL011_FBRD); - /* - ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH, - (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN)); + /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ + writel((UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN), + port[CONSOLE_PORT] + UART_PL011_LCRH); - /* - ** Finally, enable the UART - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, - (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | - UART_PL011_CR_RXE)); + /* Finally, enable the UART */ + writel((UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE), + port[CONSOLE_PORT] + UART_PL011_CR); return 0; } @@ -183,16 +164,18 @@ int serial_tstc (void) void serial_setbrg (void) { + baudrate = gd->baudrate; + serial_init(); } static void pl01x_putc (int portnum, char c) { /* Wait until there is space in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF) + while (readl(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF) WATCHDOG_RESET(); /* Send the character */ - IO_WRITE (port[portnum] + UART_PL01x_DR, c); + writel(c, port[portnum] + UART_PL01x_DR); } static int pl01x_getc (int portnum) @@ -200,15 +183,15 @@ static int pl01x_getc (int portnum) unsigned int data; /* Wait until there is data in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE) + while (readl(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE) WATCHDOG_RESET(); - data = IO_READ (port[portnum] + UART_PL01x_DR); + data = readl(port[portnum] + UART_PL01x_DR); /* Check for an error flag */ if (data & 0xFFFFFF00) { /* Clear the error */ - IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); + writel(0xFFFFFFFF, port[portnum] + UART_PL01x_ECR); return -1; } @@ -218,6 +201,6 @@ static int pl01x_getc (int portnum) static int pl01x_tstc (int portnum) { WATCHDOG_RESET(); - return !(IO_READ (port[portnum] + UART_PL01x_FR) & + return !(readl(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); } -- cgit v0.10.2 From 89bca0ab697fc75160dd0d685d7cb2ed26609a6d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Fri, 24 Sep 2010 21:20:40 +0200 Subject: board/armltd/integrator/split_by_variant.sh: fix 'echo -n' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch fixes an error when running MAKEALL for ARM9. On OS X /bin/sh uses builtin echo which does not utilise '-n' switch. GNU manual for builtins recomend to use here-document style to solve this portability issue. This patch removes the usage of 'echo -n' and replace by here-document style or a oneline echo command. Signed-off-by: Andreas Bießmann CC: Peter Pearse diff --git a/board/armltd/integrator/split_by_variant.sh b/board/armltd/integrator/split_by_variant.sh index 702b436..d869dd2 100755 --- a/board/armltd/integrator/split_by_variant.sh +++ b/board/armltd/integrator/split_by_variant.sh @@ -10,12 +10,12 @@ then # --------------------------------------------------------- # Set the platform defines # --------------------------------------------------------- -echo -n "/* Integrator configuration implied " > ${config_file} -echo " by Makefile target */" >> ${config_file} -echo -n "#define CONFIG_INTEGRATOR" >> ${config_file} -echo " /* Integrator board */" >> ${config_file} -echo -n "#define CONFIG_ARCH_INTEGRATOR" >> ${config_file} -echo " 1 /* Integrator/AP */" >> ${config_file} +cat > ${config_file} << _EOF +/* Integrator configuration implied by Makefile target */ +#define CONFIG_INTEGRATOR /* Integrator board */ +#define CONFIG_ARCH_INTEGRATOR 1 /* Integrator/AP */ +_EOF + # --------------------------------------------------------- # Set the core module defines according to Core Module # --------------------------------------------------------- @@ -50,37 +50,37 @@ else ap720t_config) cpu="arm720t" - echo -n "#define CONFIG_CM720T" >> ${config_file} - echo " 1 /* CPU core is ARM720T */ " >> ${config_file} + echo "#define CONFIG_CM720T 1 /* CPU core is ARM720T */" \ + >> ${config_file} variant="Core module CM720T" ;; ap922_XA10_config) cpu="arm_intcm" variant="unported core module CM922T_XA10" - echo -n "#define CONFIG_CM922T_XA10" >> ${config_file} - echo " 1 /* CPU core is ARM922T_XA10 */" >> ${config_file} + echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \ + >> ${config_file} ;; ap920t_config) cpu="arm920t" variant="Core module CM920T" - echo -n "#define CONFIG_CM920T" >> ${config_file} - echo " 1 /* CPU core is ARM920T */" >> ${config_file} + echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \ + >> ${config_file} ;; ap926ejs_config) cpu="arm926ejs" variant="Core module CM926EJ-S" - echo -n "#define CONFIG_CM926EJ_S" >> ${config_file} - echo " 1 /* CPU core is ARM926EJ-S */ " >> ${config_file} + echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \ + >> ${config_file} ;; ap946es_config) cpu="arm946es" variant="Core module CM946E-S" - echo -n "#define CONFIG_CM946E_S" >> ${config_file} - echo " 1 /* CPU core is ARM946E-S */ " >> ${config_file} + echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \ + >> ${config_file} ;; *) @@ -94,33 +94,26 @@ fi case "$cpu" in arm_intcm) - echo "/* Core module undefined/not ported */" >> ${config_file} - echo "#define CONFIG_ARM_INTCM 1" >> ${config_file} - echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> ${config_file} - echo -n " /* CM may not have " >> ${config_file} - echo "multiple SSRAM mapping */" >> ${config_file} - echo -n "#undef CONFIG_CM_SPD_DETECT " >> ${config_file} - echo -n " /* CM may not support SPD " >> ${config_file} - echo "query */" >> ${config_file} - echo -n "#undef CONFIG_CM_REMAP " >> ${config_file} - echo -n " /* CM may not support " >> ${config_file} - echo "remapping */" >> ${config_file} - echo -n "#undef CONFIG_CM_INIT " >> ${config_file} - echo -n " /* CM may not have " >> ${config_file} - echo "initialization reg */" >> ${config_file} - echo -n "#undef CONFIG_CM_TCRAM " >> ${config_file} - echo " /* CM may not have TCRAM */" >> ${config_file} - echo -n " /* May not be processor " >> ${config_file} - echo "without cache support */" >> ${config_file} - echo "#define CONFIG_SYS_NO_ICACHE 1" >> ${config_file} - echo "#define CONFIG_SYS_NO_DCACHE 1" >> ${config_file} + cat >> ${config_file} << _EOF +/* Core module undefined/not ported */ +#define CONFIG_ARM_INTCM 1 +#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */ +#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */ +#undef CONFIG_CM_REMAP /* CM may not support remapping */ +#undef CONFIG_CM_INIT /* CM may not have initialization reg */ +#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */ +/* May not be processor without cache support */ +#define CONFIG_SYS_NO_ICACHE 1 +#define CONFIG_SYS_NO_DCACHE 1 +_EOF ;; arm720t) - echo -n " /* May not be processor " >> ${config_file} - echo "without cache support */" >> ${config_file} - echo "#define CONFIG_SYS_NO_ICACHE 1" >> ${config_file} - echo "#define CONFIG_SYS_NO_DCACHE 1" >> ${config_file} + cat >> ${config_file} << _EOF +/* May not be processor without cache support */ +#define CONFIG_SYS_NO_ICACHE 1 +#define CONFIG_SYS_NO_DCACHE 1 +_EOF ;; esac @@ -129,12 +122,11 @@ else # --------------------------------------------------------- # Set the platform defines # --------------------------------------------------------- -echo -n "/* Integrator configuration implied " > ${config_file} -echo " by Makefile target */" >> ${config_file} -echo -n "#define CONFIG_INTEGRATOR" >> ${config_file} -echo " /* Integrator board */" >> ${config_file} -echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> ${config_file} -echo " 1 /* Integrator/CP */" >> ${config_file} +cat >> ${config_file} << _EOF +/* Integrator configuration implied by Makefile target */ +#define CONFIG_INTEGRATOR /* Integrator board */ +#define CONFIG_ARCH_CINTEGRATOR 1 /* Integrator/CP */ +_EOF cpu="arm_intcm" variant="unknown core module" @@ -163,37 +155,37 @@ else cp922_XA10_config) cpu="arm_intcm" variant="unported core module CM922T_XA10" - echo -n "#define CONFIG_CM922T_XA10" >> ${config_file} - echo " 1 /* CPU core is ARM922T_XA10 */" >> ${config_file} + echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \ + >> ${config_file} ;; cp920t_config) cpu="arm920t" variant="Core module CM920T" - echo -n "#define CONFIG_CM920T" >> ${config_file} - echo " 1 /* CPU core is ARM920T */" >> ${config_file} + echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \ + >> ${config_file} ;; cp926ejs_config) cpu="arm926ejs" variant="Core module CM926EJ-S" - echo -n "#define CONFIG_CM926EJ_S" >> ${config_file} - echo " 1 /* CPU core is ARM926EJ-S */ " >> ${config_file} + echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \ + >> ${config_file} ;; cp946es_config) cpu="arm946es" variant="Core module CM946E-S" - echo -n "#define CONFIG_CM946E_S" >> ${config_file} - echo " 1 /* CPU core is ARM946E-S */ " >> ${config_file} + echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \ + >> ${config_file} ;; cp1136_config) cpu="arm1136" variant="Core module CM1136EJF-S" - echo -n "#define CONFIG_CM1136EJF_S" >> ${config_file} - echo " 1 /* CPU core is ARM1136JF-S */ " >> ${config_file} + echo "#define CONFIG_CM1136EJF_S 1 /* CPU core is ARM1136JF-S */" \ + >> ${config_file} ;; *) @@ -208,22 +200,15 @@ fi if [ "$cpu" = "arm_intcm" ] then - echo "/* Core module undefined/not ported */" >> ${config_file} - echo "#define CONFIG_ARM_INTCM 1" >> ${config_file} - echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> ${config_file} - echo -n " /* CM may not have " >> ${config_file} - echo "multiple SSRAM mapping */" >> ${config_file} - echo -n "#undef CONFIG_CM_SPD_DETECT " >> ${config_file} - echo -n " /* CM may not support SPD " >> ${config_file} - echo "query */" >> ${config_file} - echo -n "#undef CONFIG_CM_REMAP " >> ${config_file} - echo -n " /* CM may not support " >> ${config_file} - echo "remapping */" >> ${config_file} - echo -n "#undef CONFIG_CM_INIT " >> ${config_file} - echo -n " /* CM may not have " >> ${config_file} - echo "initialization reg */" >> ${config_file} - echo -n "#undef CONFIG_CM_TCRAM " >> ${config_file} - echo " /* CM may not have TCRAM */" >> ${config_file} + cat >> ${config_file} << _EOF +/* Core module undefined/not ported */ +#define CONFIG_ARM_INTCM 1 +#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */ +#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */ +#undef CONFIG_CM_REMAP /* CM may not support remapping */ +#undef CONFIG_CM_INIT /* CM may not have initialization reg */ +#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */ +_EOF fi fi # ap -- cgit v0.10.2